repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
luebbers/reconos
|
tests/benchmarks/semaphore/hw/src/hwt_semaphore_post.vhd
| 1 | 9,425 |
--
-- hwt_semaphore_post.vhd: measure time for semaphore_post() operation
--
-- This HW thread measures the time it takes to execute a semaphore_post()
-- operation from hardware.
-- To avoid side effects caused by activity of the delegate after returnung
-- from a sem_post() call, this thread waits a defined number of clock
-- cycles between consecutive calls to reconos_sem_post(). This number can
-- be configured using the init_data value. A typical value is 100000, which
-- is equivalent to a millisecond.
--
-- This HW thread uses the dcr_timebase core to do consistent and synchronized
-- measurements of elapsed bus clock cycles.
--
-- Author Enno Luebbers <[email protected]>
-- Date 09.02.2008
--
-- For detailed documentation of the functions, see the associated header
-- file or the documentation (if such a header exists).
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group
--
-- (C) Copyright University of Paderborn 2007. Permission to copy,
-- use, modify, sell and distribute this software is granted provided
-- this copyright notice appears in all copies. This software is
-- provided "as is" without express or implied warranty, and with no
-- claim as to its suitability for any purpose.
--
---------------------------------------------------------------------------
-- Major Changes:
--
-- 09.02.2008 Enno Luebbers File created
-- 11.02.2008 Enno Luebbers Modified to use timebase core
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.all;
entity hwt_semaphore_post is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector( 0 to C_BURST_AWIDTH-1 );
o_RAMData : out std_logic_vector( 0 to C_BURST_DWIDTH-1 );
i_RAMData : in std_logic_vector( 0 to C_BURST_DWIDTH-1 );
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- time base
i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end entity;
architecture Behavioral of hwt_semaphore_post is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
constant C_SEMAPHORE : std_logic_vector(31 downto 0) := X"00000000";
constant C_MBOX_RESULT : std_logic_vector(31 downto 0) := X"00000001";
type t_state is ( STATE_INIT, -- get initial data (delay in clocks)
STATE_WAIT_BEFORE, -- wait before measuring
STATE_POST_SEM, -- post semaphore
STATE_MEASURE, -- measure elapsed time
STATE_WAIT_AFTER, -- wait after measuring
STATE_PUT_RESULT_START, -- post elapsed time to software mbox
STATE_PUT_RESULT_STOP,
STATE_EXIT); -- exit
signal state : t_state;
signal counter : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal reset_counter : std_logic := '1';
begin
state_proc: process( clk, reset )
variable delay : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable result_start : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable result_stop : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable retval : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable done : boolean := false;
variable success : boolean := false;
begin
if reset = '1' then
reconos_reset( o_osif, i_osif );
state <= STATE_INIT;
reset_counter <= '1';
result_start := (others => '0');
result_stop := (others => '0');
retval := (others => '0');
elsif rising_edge( clk ) then
reconos_begin( o_osif, i_osif );
if reconos_ready( i_osif ) then
case state is
when STATE_INIT =>
reconos_get_init_data(done, o_osif, i_osif, delay);
if done then
reset_counter <= '1';
state <= STATE_WAIT_BEFORE;
end if;
when STATE_WAIT_BEFORE =>
reset_counter <= '0';
if counter >= delay then
reset_counter <= '1';
result_start := i_timeBase;
state <= STATE_POST_SEM;
end if;
when STATE_POST_SEM =>
reconos_sem_post(o_osif,i_osif,C_SEMAPHORE);
state <= STATE_MEASURE;
when STATE_MEASURE =>
result_stop := i_timeBase;
state <= STATE_WAIT_AFTER;
when STATE_WAIT_AFTER =>
reset_counter <= '0';
if counter >= delay then
reset_counter <= '1';
state <= STATE_PUT_RESULT_START;
end if;
when STATE_PUT_RESULT_START =>
reconos_mbox_put(done,
success,
o_osif,
i_osif,
C_MBOX_RESULT,
result_start);
if done then
if success then
state <= STATE_PUT_RESULT_STOP;
else
retval := X"0000_0001"; -- first mbox_put failed
state <= STATE_EXIT;
end if;
end if;
when STATE_PUT_RESULT_STOP =>
reconos_mbox_put(done,
success,
o_osif,
i_osif,
C_MBOX_RESULT,
result_stop);
if done then
if success then
retval := X"0000_0000"; -- all is well
state <= STATE_EXIT;
else
retval := X"0000_0002"; -- second mbox_put failed
state <= STATE_EXIT;
end if;
end if;
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, retval);
end case;
end if;
end if;
end process;
--
-- counter process to wait cycles
--
counter_proc : process(clk, reset)
begin
if reset = '1' then
counter <= (others => '0');
elsif rising_edge(clk) then
if reset_counter = '1' then
counter <= (others => '0');
else
counter <= counter + 1;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
e098b6733abdb45c0964f7c5565feba1
| 0.392149 | 5.674293 | false | false | false | false |
twlostow/dsi-shield
|
hdl/top/rev1/rev1_top.vhd
| 1 | 31,116 |
--
-- DSI Shield
-- Copyright (C) 2013-2014 twl <[email protected]>
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 3 of the License, or (at your option) any later version.
--
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- rev1_top.vhd - top level for rev 1.1. PCB FPGA
--
--
library ieee;
use ieee.std_logic_1164.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
library unisim;
use unisim.vcomponents.all;
-- Table 1: PLL Settings for the supported displays.
-- Display Type Refresh Mul Sys_Div Phy_Div PHY_Freq Clock period
-- Droid DNA 48 Hz 26 7 1 650 MHz 1538 ps
-- Optimus P880 60 Hz 30 8 2 375 MHz 2666 ps
-- Iphone 4 60 Hz 31 8 2 387.5 MHz 2580 ps
entity rev1_top is
generic (
g_lm32_firmware : string := "boot.ram";
g_with_hdmi : boolean := true;
-- DDR clock-to-data delay
g_data_delay : integer := 0;
-- DDR data-to-DQs delay
g_dqs_delay : integer := 75 - 45;
-- PLL configuration:
-- Fsys = 25 MHz * g_pll_mul / g_pll_sys_div
-- Fphy = 25 MHz * g_pll_mul / g_pll_phy_div
-- PLL multiplier
g_pll_mul : integer := 31;
-- System clock PLL divider
g_pll_sys_div : integer := 8;
-- DSI PHY clock PLL divider
g_pll_phy_div : integer := 2;
-- DSI PHY clock period, in picoseconds
g_clock_period_ps : integer := 1538
);
port (
clk_25m_i : in std_logic;
rst_n_a_i : in std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-------------------------------------------------------------------------------
-- HDMI
-------------------------------------------------------------------------------
hdmi_rx_p_i : in std_logic_vector(3 downto 0);
hdmi_rx_n_i : in std_logic_vector(3 downto 0);
hdmi_scl_b : inout std_logic;
hdmi_sda_b : inout std_logic;
hdmi_hpd_o : out std_logic;
hdmi_p5v_notif_i : in std_logic;
-------------------------------------------------------------------------------
-- SDRAM
-------------------------------------------------------------------------------
sdram_clk_p : out std_logic;
sdram_clk_n : out std_logic;
sdram_cke : out std_logic;
sdram_cs_n : out std_logic;
sdram_we_n : out std_logic;
sdram_cas_n : out std_logic;
sdram_ras_n : out std_logic;
sdram_adr : out std_logic_vector(12 downto 0);
sdram_ba : out std_logic_vector(1 downto 0);
sdram_dm : out std_logic_vector(1 downto 0);
sdram_dq : inout std_logic_vector(15 downto 0);
sdram_dqs : inout std_logic_vector(1 downto 0);
-------------------------------------------------------------------------------
-- DSI ports
-------------------------------------------------------------------------------
dsi_clk_p_o : out std_logic;
dsi_clk_n_o : out std_logic;
dsi_clk_lp_p_o : out std_logic;
dsi_clk_lp_n_o : out std_logic;
dsi_hs_p_o : out std_logic_vector(3 downto 0);
dsi_hs_n_o : out std_logic_vector(3 downto 0);
dsi_lp_p_o : out std_logic_vector(3 downto 0);
dsi_lp_n_o : out std_logic_vector(3 downto 0);
dsi_resetb_o : out std_logic;
dsi_gpio0_o : out std_logic;
dsi_gpio1_o : out std_logic;
lcd_pwren_o : out std_logic
);
end rev1_top;
architecture rtl of rev1_top is
component dsi_core is
generic(
g_pixels_per_clock : integer := 2;
g_lanes : integer := 4;
g_fifo_size : integer := 4096;
g_invert_lanes : integer := 0;
g_invert_clock : integer := 0;
g_clock_period_ps : integer := 2000
);
port(
clk_sys_i : in std_logic;
clk_dsi_i : in std_logic;
clk_phy_i : in std_logic;
rst_n_i : in std_logic;
pll_locked_i : in std_logic;
pix_almost_full_o : out std_logic;
pix_i : in std_logic_vector (24 * g_pixels_per_clock-1 downto 0) := (others => '0');
pix_wr_i : in std_logic;
pix_vsync_i : in std_logic;
pix_next_frame_o : out std_logic;
dsi_clk_p_o : out std_logic;
dsi_clk_n_o : out std_logic;
dsi_clk_lp_p_o : out std_logic;
dsi_clk_lp_n_o : out std_logic;
dsi_clk_lp_oe_o : out std_logic;
dsi_hs_p_o : out std_logic_vector(g_lanes-1 downto 0);
dsi_hs_n_o : out std_logic_vector(g_lanes-1 downto 0);
dsi_lp_p_o : out std_logic_vector(g_lanes-1 downto 0);
dsi_lp_n_o : out std_logic_vector(g_lanes-1 downto 0);
dsi_lp_oe_o : out std_logic_vector(g_lanes-1 downto 0);
dsi_reset_n_o : out std_logic;
dsi_gpio_o : out std_logic_vector(2 downto 0);
wb_adr_i : in std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_stall_o : out std_logic;
wb_ack_o : out std_logic
);
end component;
component fml_wb_bridge
generic (
sdram_depth : integer := 26);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
fml_adr : out std_logic_vector(sdram_depth-1 downto 0);
fml_stb : out std_logic;
fml_we : out std_logic;
fml_ack : in std_logic;
fml_sel : out std_logic_vector(3 downto 0);
fml_di : in std_logic_vector(31 downto 0);
fml_do : out std_logic_vector(31 downto 0);
wb_adr_i : in std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_stall_o : out std_logic;
wb_ack_o : out std_logic
);
end component;
component fmlarb
generic(
fml_depth : integer := 26;
fml_width : integer := 32);
port (
sys_clk : in std_logic;
sys_rst : in std_logic;
-- Interface 0 has higher priority than the others
m0_adr : in std_logic_vector(fml_depth-1 downto 0) := (others => '0');
m0_stb : in std_logic := '0';
m0_we : in std_logic := '0';
m0_ack : out std_logic;
m0_sel : in std_logic_vector(fml_width/8-1 downto 0) := (others => '0');
m0_di : in std_logic_vector(fml_width-1 downto 0) := (others => '0');
m0_do : out std_logic_vector(fml_width-1 downto 0);
m1_adr : in std_logic_vector(fml_depth-1 downto 0) := (others => '0');
m1_stb : in std_logic := '0';
m1_we : in std_logic := '0';
m1_ack : out std_logic;
m1_sel : in std_logic_vector(fml_width/8-1 downto 0) := (others => '0');
m1_di : in std_logic_vector(fml_width-1 downto 0) := (others => '0');
m1_do : out std_logic_vector(fml_width-1 downto 0);
m2_adr : in std_logic_vector(fml_depth-1 downto 0) := (others => '0');
m2_stb : in std_logic := '0';
m2_we : in std_logic := '0';
m2_ack : out std_logic;
m2_sel : in std_logic_vector(fml_width/8-1 downto 0) := (others => '0');
m2_di : in std_logic_vector(fml_width-1 downto 0) := (others => '0');
m2_do : out std_logic_vector(fml_width-1 downto 0);
m3_adr : in std_logic_vector(fml_depth-1 downto 0) := (others => '0');
m3_stb : in std_logic := '0';
m3_we : in std_logic := '0';
m3_ack : out std_logic;
m3_sel : in std_logic_vector(fml_width/8-1 downto 0) := (others => '0');
m3_di : in std_logic_vector(fml_width-1 downto 0) := (others => '0');
m3_do : out std_logic_vector(fml_width-1 downto 0);
m4_adr : in std_logic_vector(fml_depth-1 downto 0) := (others => '0');
m4_stb : in std_logic := '0';
m4_we : in std_logic := '0';
m4_ack : out std_logic;
m4_sel : in std_logic_vector(fml_width/8-1 downto 0) := (others => '0');
m4_di : in std_logic_vector(fml_width-1 downto 0) := (others => '0');
m4_do : out std_logic_vector(fml_width-1 downto 0);
m5_adr : in std_logic_vector(fml_depth-1 downto 0) := (others => '0');
m5_stb : in std_logic := '0';
m5_we : in std_logic := '0';
m5_ack : out std_logic;
m5_sel : in std_logic_vector(fml_width/8-1 downto 0) := (others => '0');
m5_di : in std_logic_vector(fml_width-1 downto 0) := (others => '0');
m5_do : out std_logic_vector(fml_width-1 downto 0);
s_adr : out std_logic_vector(fml_depth-1 downto 0);
s_stb : out std_logic;
s_we : out std_logic;
s_eack : in std_logic;
s_sel : out std_logic_vector(fml_width/8-1 downto 0);
s_di : in std_logic_vector(fml_width-1 downto 0);
s_do : out std_logic_vector(fml_width-1 downto 0)
);
end component;
component hpdmc
generic (
csr_addr : integer := 0;
sdram_depth : integer := 25;
sdram_columndepth : integer := 9;
data_delay : integer := 20;
dqs_delay : integer := 20
);
port (
sys_clk : in std_logic;
sys_clk_n : in std_logic;
sys_rst : in std_logic;
csr_a : in std_logic_vector(13 downto 0);
csr_we : in std_logic;
csr_di : in std_logic_vector(31 downto 0);
csr_do : out std_logic_vector(31 downto 0);
fml_adr : in std_logic_vector(sdram_depth-1 downto 0);
fml_stb : in std_logic;
fml_we : in std_logic;
fml_eack : out std_logic;
fml_ack : out std_logic;
fml_sel : in std_logic_vector(3 downto 0);
fml_di : in std_logic_vector(31 downto 0);
fml_do : out std_logic_vector(31 downto 0);
sdram_clk_p : out std_logic;
sdram_clk_n : out std_logic;
sdram_cke : out std_logic;
sdram_cs_n : out std_logic;
sdram_we_n : out std_logic;
sdram_cas_n : out std_logic;
sdram_ras_n : out std_logic;
sdram_adr : out std_logic_vector(12 downto 0);
sdram_ba : out std_logic_vector(1 downto 0);
sdram_dm : out std_logic_vector(1 downto 0);
sdram_dq : inout std_logic_vector(15 downto 0);
sdram_dqs : inout std_logic_vector(1 downto 0)
);
end component;
component dsi_pll_spartan6
generic (
g_mul : integer;
g_sys_div : integer;
g_phy_div : integer);
port (
clk_in_i : in std_logic;
clk_sys_o : out std_logic;
clk_sys_n_o : out std_logic;
clk_dsi_o : out std_logic;
clk_phy_o : out std_logic;
locked_o : out std_logic);
end component;
component reset_gen
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
end component;
component fml_framebuffer
generic (
g_fml_depth : integer := 25;
g_pll_phy_div : integer;
g_pll_sys_div : integer;
g_pll_mul : integer
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
pix_almost_full_i : in std_logic;
pix_wr_o : out std_logic;
pix_o : out std_logic_vector(47 downto 0);
pix_vsync_o : out std_logic;
pix_next_frame_i : in std_logic;
fml_adr : out std_logic_vector(g_fml_depth-1 downto 0);
fml_stb : out std_logic;
fml_we : out std_logic;
fml_ack : in std_logic;
fml_sel : out std_logic_vector(3 downto 0);
fml_di : in std_logic_vector(31 downto 0);
wb_adr_i : in std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_stall_o : out std_logic;
wb_ack_o : out std_logic;
mixer_ctl_i : in std_logic_vector(7 downto 0);
mixer_ctl_o : out std_logic_vector(7 downto 0);
edid_addr_o : out std_logic_vector(7 downto 0);
edid_data_o : out std_logic_vector(7 downto 0);
edid_wr_o : out std_logic
);
end component;
component hdmi_rx_wrapper
port (
rst_a_i : in std_logic;
tmds_clk_p_i : in std_logic;
tmds_clk_n_i : in std_logic;
red_p_i : in std_logic;
red_n_i : in std_logic;
green_p_i : in std_logic;
green_n_i : in std_logic;
blue_p_i : in std_logic;
blue_n_i : in std_logic;
clk_pixel_o : out std_logic;
hsync_o : out std_logic;
vsync_o : out std_logic;
de_o : out std_logic;
pixel_o : out std_logic_vector(47 downto 0);
pixel_valid_o : out std_logic;
link_up_o : out std_logic
);
end component;
component edid_eeprom is
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
scl_b : inout std_logic;
sda_b : inout std_logic;
hdmi_p5v_notif_i : in std_logic;
hdmi_hpd_en_o : out std_logic;
addr_i : in std_logic_vector(7 downto 0);
data_i : in std_logic_vector(7 downto 0);
wr_i : in std_logic);
end component;
component video_mixer is
port(
clk_sys_i : in std_logic;
clk_dvi_i : in std_logic;
rst_n_i : in std_logic;
fb_almost_full_o : out std_logic;
fb_wr_i : in std_logic;
fb_pixel_i : in std_logic_vector(47 downto 0);
fb_vsync_i : in std_logic;
fb_next_frame_o : out std_logic;
dvi_de_i : in std_logic;
dvi_hsync_i : in std_logic;
dvi_vsync_i : in std_logic;
dvi_pixel_i : in std_logic_vector(47 downto 0);
dvi_valid_i : in std_logic;
dvi_link_up_i : in std_logic;
dsif_almost_full_i : in std_logic;
dsif_wr_o : out std_logic;
dsif_pix_o : out std_logic_vector(47 downto 0);
dsif_vsync_o : out std_logic;
dsif_next_frame_i : in std_logic;
mixer_ctl_i : in std_logic_vector(7 downto 0);
mixer_ctl_o : out std_logic_vector(7 downto 0)
);
end component;
constant c_cnx_slave_ports : integer := 1;
constant c_cnx_master_ports : integer := 6;
constant c_master_cpu_i : integer := 0;
constant c_slave_dpram : integer := 0;
constant c_slave_uart : integer := 1;
constant c_slave_dsi : integer := 2;
constant c_slave_ddram_csr : integer := 3;
constant c_slave_fb_csr : integer := 4;
constant c_slave_ddram_mem : integer := 5;
signal cnx_slave_in : t_wishbone_slave_in_array(c_cnx_slave_ports-1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(c_cnx_slave_ports-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_cnx_master_ports-1 downto 0);
signal cnx_master_out : t_wishbone_master_out_array(c_cnx_master_ports-1 downto 0);
constant c_cfg_base_addr : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
(0 => x"00000000", -- 64KB of fpga memory
1 => x"00010000", -- The second port to the same memory
2 => x"00020000",
3 => x"00030000",
4 => x"00040000",
5 => x"40000000"); -- Peripherals
constant c_cfg_base_mask : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
(0 => x"ffff0000",
1 => x"ffff0000",
2 => x"ffff0000",
3 => x"ffff0000",
4 => x"ffff0000",
5 => x"c0000000");
signal cpu_iwb_out : t_wishbone_master_out;
signal cpu_iwb_in : t_wishbone_master_in;
signal rst_n_sys, rst_sys, rst_n_dsi, clk_phy, clk_sys, clk_dsi, clk_sys_n, pll_locked, pll_locked_n, dsi_wr : std_logic;
signal dsi_lp_p_int, dsi_lp_n_int, dsi_lp_oe : std_logic_vector(3 downto 0);
signal dsi_clk_lp_p, dsi_clk_lp_n, dsi_clk_lp_oe : std_logic;
attribute keep : string;
attribute keep of clk_phy : signal is "true";
attribute keep of clk_sys : signal is "true";
attribute keep of clk_sys_n : signal is "true";
attribute keep of clk_dsi : signal is "true";
signal csr_we : std_logic;
signal dsi_wr_sync : std_logic_vector(7 downto 0);
signal pll_clk_in, pll_clk_fb, pll_clk_dsi: std_logic;
signal pll_clk_sys, pll_clk_sys_n : std_logic;
signal dsif_almost_full : std_logic;
signal dsif_wr : std_logic;
signal dsif_pix : std_logic_vector(47 downto 0);
signal dsif_vsync : std_logic;
signal dsif_next_frame : std_logic;
signal fb_almost_full : std_logic;
signal fb_wr : std_logic;
signal fb_pix : std_logic_vector(47 downto 0);
signal fb_vsync : std_logic;
signal fb_next_frame : std_logic;
type t_fml_link is record
adr : std_logic_vector(24 downto 0);
stb, we, ack, eack : std_logic;
d_m2s : std_logic_vector(31 downto 0);
d_s2m : std_logic_vector(31 downto 0);
sel : std_logic_vector(3 downto 0);
end record;
signal ddrc, fwb, frameb : t_fml_link;
signal hdmi_link_up, hdmi_pclk, hdmi_vsync, hdmi_hsync, hdmi_de, hdmi_valid : std_logic;
signal hdmi_pixel : std_logic_vector(47 downto 0);
signal mix_ctl_tomix, mix_ctl_tofb : std_logic_vector(7 downto 0);
signal edid_addr, edid_data : std_logic_vector(7 downto 0);
signal edid_wr : std_logic;
signal dsi_gpio : std_logic_vector(2 downto 0);
signal uart_txd_int : std_logic;
begin -- rtl
uart_txd_o <= uart_txd_int;
rst_sys <= not rst_n_sys;
U_Sync_DSI_Reset : gc_sync_ffs
port map (
clk_i => clk_dsi,
rst_n_i => '1',
data_i => rst_n_sys,
synced_o => rst_n_dsi);
U_IbufG_CLKIn: IBUFG
port map (
I => clk_25m_i,
O => pll_clk_in
);
U_PLL : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => g_pll_mul,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => g_pll_phy_div,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => g_pll_phy_div * 8,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => g_pll_sys_div,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DIVIDE => g_pll_sys_div,
CLKOUT3_PHASE => 180.000,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 40.000,
REF_JITTER => 0.010)
port map (
CLKIN => pll_clk_in,
CLKFBOUT => pll_clk_fb,
CLKOUT0 => clk_phy,
CLKOUT1 => pll_clk_dsi,
CLKOUT2 => pll_clk_sys,
CLKOUT3 => pll_clk_sys_n,
LOCKED => pll_locked,
RST => '0',
CLKFBIN => pll_clk_fb);
pll_locked_n <= not pll_locked;
U_BufG_CLK_DSI: BUFG
port map (
I => pll_clk_dsi,
O => clk_dsi);
U_BufG_CLK_SYS: BUFG
port map (
I => pll_clk_sys,
O => clk_sys);
U_BufG_CLK_SYS_N: BUFG
port map (
I => pll_clk_sys_n,
O => clk_sys_n);
U_Reset_Gen : reset_gen
port map (
clk_sys_i => clk_sys,
rst_pcie_n_a_i => pll_locked_n,
rst_button_n_a_i => rst_n_a_i,
rst_n_o => rst_n_sys);
U_CPU : xwb_lm32
generic map (
g_profile => "medium_icache")
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
irq_i => x"00000000",
dwb_o => cnx_slave_in(0),
dwb_i => cnx_slave_out(0),
iwb_o => cpu_iwb_out,
iwb_i => cpu_iwb_in);
U_Intercon : xwb_crossbar
generic map (
g_num_masters => c_cnx_slave_ports,
g_num_slaves => c_cnx_master_ports,
g_registered => true,
g_address => c_cfg_base_addr,
g_mask => c_cfg_base_mask)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
U_DPRAM : xwb_dpram
generic map (
g_size => 4096, -- 16kB
g_init_file => g_lm32_firmware,
g_must_have_init_file => true,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => BYTE)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
slave1_i => cnx_master_out(c_slave_dpram),
slave1_o => cnx_master_in(c_slave_dpram),
slave2_i => cpu_iwb_out,
slave2_o => cpu_iwb_in);
U_UART : xwb_simple_uart
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
slave_i => cnx_master_out(c_slave_uart),
slave_o => cnx_master_in(c_slave_uart),
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_int);
csr_we <= cnx_master_out(c_slave_ddram_csr).cyc and cnx_master_out(c_slave_ddram_csr).stb and
cnx_master_out(c_slave_ddram_csr).we;
U_DDR_Controller : hpdmc
generic map (
data_delay => g_data_delay,
dqs_delay => g_dqs_delay)
port map (
sys_clk => clk_sys,
sys_clk_n => clk_sys_n,
sys_rst => rst_sys,
csr_a => cnx_master_out(c_slave_ddram_csr).adr(15 downto 2),
csr_we => csr_we,
csr_di => cnx_master_out(c_slave_ddram_csr).dat,
csr_do => cnx_master_in(c_slave_ddram_csr).dat,
fml_adr => ddrc.adr(24 downto 0),
fml_stb => ddrc.stb,
fml_we => ddrc.we,
fml_eack => ddrc.eack,
fml_sel => ddrc.sel,
fml_di => ddrc.d_m2s,
fml_do => ddrc.d_s2m,
sdram_clk_p => sdram_clk_p,
sdram_clk_n => sdram_clk_n,
sdram_cke => sdram_cke,
sdram_cs_n => sdram_cs_n,
sdram_we_n => sdram_we_n,
sdram_cas_n => sdram_cas_n,
sdram_ras_n => sdram_ras_n,
sdram_adr => sdram_adr,
sdram_ba => sdram_ba,
sdram_dm => sdram_dm,
sdram_dq => sdram_dq,
sdram_dqs => sdram_dqs);
U_FML_Arb : fmlarb
generic map (
fml_depth => 25)
port map (
sys_clk => clk_sys,
sys_rst => rst_sys,
m0_adr => frameb.adr,
m0_stb => frameb.stb,
m0_we => frameb.we,
m0_ack => frameb.ack,
m0_sel => frameb.sel,
m0_do => frameb.d_s2m,
m1_adr => fwb.adr,
m1_stb => fwb.stb,
m1_we => fwb.we,
m1_ack => fwb.ack,
m1_sel => fwb.sel,
m1_di => fwb.d_m2s,
m1_do => fwb.d_s2m,
s_adr => ddrc.adr,
s_stb => ddrc.stb,
s_we => ddrc.we,
s_eack => ddrc.eack,
s_sel => ddrc.sel,
s_di => ddrc.d_s2m,
s_do => ddrc.d_m2s);
U_FML_WB_Bridge : fml_wb_bridge
generic map (
sdram_depth => 25)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
fml_adr => fwb.adr,
fml_stb => fwb.stb,
fml_we => fwb.we,
fml_ack => fwb.ack,
fml_sel => fwb.sel,
fml_di => fwb.d_s2m,
fml_do => fwb.d_m2s,
wb_adr_i => cnx_master_out(c_slave_ddram_mem).adr,
wb_cyc_i => cnx_master_out(c_slave_ddram_mem).cyc,
wb_we_i => cnx_master_out(c_slave_ddram_mem).we,
wb_sel_i => cnx_master_out(c_slave_ddram_mem).sel,
wb_stb_i => cnx_master_out(c_slave_ddram_mem).stb,
wb_dat_i => cnx_master_out(c_slave_ddram_mem).dat,
wb_dat_o => cnx_master_in(c_slave_ddram_mem).dat,
wb_stall_o => cnx_master_in(c_slave_ddram_mem).stall,
wb_ack_o => cnx_master_in(c_slave_ddram_mem).ack
);
U_DSI_Core : dsi_core
generic map
(g_clock_period_ps => g_clock_period_ps)
port map (
clk_dsi_i => clk_dsi,
clk_sys_i => clk_sys,
clk_phy_i => clk_phy,
rst_n_i => rst_n_dsi,
pll_locked_i => pll_locked,
pix_i => dsif_pix,
pix_almost_full_o => dsif_almost_full,
pix_vsync_i => dsif_vsync,
pix_next_frame_o => dsif_next_frame,
pix_wr_i => dsif_wr,
dsi_clk_p_o => dsi_clk_p_o,
dsi_clk_n_o => dsi_clk_n_o,
dsi_clk_lp_n_o => dsi_clk_lp_n,
dsi_clk_lp_p_o => dsi_clk_lp_p,
dsi_clk_lp_oe_o => dsi_clk_lp_oe,
dsi_hs_p_o => dsi_hs_p_o,
dsi_hs_n_o => dsi_hs_n_o,
dsi_lp_p_o => dsi_lp_p_int,
dsi_lp_n_o => dsi_lp_n_int,
dsi_lp_oe_o => dsi_lp_oe,
dsi_reset_n_o => dsi_resetb_o,
dsi_gpio_o => dsi_gpio,
wb_adr_i => cnx_master_out(c_slave_dsi).adr,
wb_cyc_i => cnx_master_out(c_slave_dsi).cyc,
wb_we_i => cnx_master_out(c_slave_dsi).we,
wb_sel_i => cnx_master_out(c_slave_dsi).sel,
wb_stb_i => cnx_master_out(c_slave_dsi).stb,
wb_dat_i => cnx_master_out(c_slave_dsi).dat,
wb_dat_o => cnx_master_in(c_slave_dsi).dat,
wb_stall_o => cnx_master_in(c_slave_dsi).stall,
wb_ack_o => cnx_master_in(c_slave_dsi).ack
);
lcd_pwren_o <= '1';
U_Framebuffer : fml_framebuffer
generic map (
g_fml_depth => 25,
g_pll_phy_div => g_pll_phy_div,
g_pll_sys_div => g_pll_sys_div,
g_pll_mul => g_pll_mul
)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
pix_almost_full_i => fb_almost_full,
pix_wr_o => fb_wr,
pix_o => fb_pix,
pix_vsync_o => fb_vsync,
pix_next_frame_i => fb_next_frame,
fml_adr => frameb.adr,
fml_stb => frameb.stb,
fml_we => frameb.we,
fml_ack => frameb.ack,
fml_sel => frameb.sel,
fml_di => frameb.d_s2m,
wb_adr_i => cnx_master_out(c_slave_fb_csr).adr,
wb_cyc_i => cnx_master_out(c_slave_fb_csr).cyc,
wb_we_i => cnx_master_out(c_slave_fb_csr).we,
wb_sel_i => cnx_master_out(c_slave_fb_csr).sel,
wb_stb_i => cnx_master_out(c_slave_fb_csr).stb,
wb_dat_i => cnx_master_out(c_slave_fb_csr).dat,
wb_dat_o => cnx_master_in(c_slave_fb_csr).dat,
wb_stall_o => cnx_master_in(c_slave_fb_csr).stall,
wb_ack_o => cnx_master_in(c_slave_fb_csr).ack,
mixer_ctl_o => mix_ctl_tomix,
mixer_ctl_i => mix_ctl_tofb,
edid_addr_o => edid_addr,
edid_data_o => edid_data,
edid_wr_o => edid_wr
);
gen_with_hdmi_sampler : if (g_with_hdmi = true) generate
U_HDMI_RX : hdmi_rx_wrapper
port map
(
rst_a_i => rst_sys,
tmds_clk_p_i => hdmi_rx_p_i(3),
tmds_clk_n_i => hdmi_rx_n_i(3),
blue_p_i => hdmi_rx_p_i(0),
blue_n_i => hdmi_rx_n_i(0),
green_p_i => hdmi_rx_p_i(1),
green_n_i => hdmi_rx_n_i(1),
red_p_i => hdmi_rx_p_i(2),
red_n_i => hdmi_rx_n_i(2),
clk_pixel_o => hdmi_pclk,
hsync_o => hdmi_hsync,
vsync_o => hdmi_vsync,
de_o => hdmi_de,
link_up_o => hdmi_link_up,
pixel_o => hdmi_pixel,
pixel_valid_o => hdmi_valid
);
U_EDID_EEPROM : edid_eeprom
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
scl_b => hdmi_scl_b,
sda_b => hdmi_sda_b,
hdmi_p5v_notif_i => hdmi_p5v_notif_i,
hdmi_hpd_en_o => hdmi_hpd_o,
addr_i => edid_addr,
data_i => edid_data,
wr_i => edid_wr);
end generate gen_with_hdmi_sampler;
U_Video_Mixer : video_mixer
port map (
clk_sys_i => clk_sys,
clk_dvi_i => hdmi_pclk,
rst_n_i => rst_n_sys,
fb_almost_full_o => fb_almost_full,
fb_wr_i => fb_wr,
fb_pixel_i => fb_pix,
fb_vsync_i => fb_vsync,
fb_next_frame_o => fb_next_frame,
dvi_de_i => hdmi_de,
dvi_hsync_i => hdmi_hsync,
dvi_vsync_i => hdmi_vsync,
dvi_pixel_i => hdmi_pixel,
dvi_valid_i => hdmi_valid,
dvi_link_up_i => hdmi_link_up,
dsif_almost_full_i => dsif_almost_full,
dsif_wr_o => dsif_wr,
dsif_pix_o => dsif_pix,
dsif_vsync_o => dsif_vsync,
dsif_next_frame_i => dsif_next_frame,
mixer_ctl_i => mix_ctl_tomix,
mixer_ctl_o => mix_ctl_tofb
);
gen_lp_tristates : for i in 0 to 3 generate
dsi_lp_p_o(i) <= '1' when (dsi_lp_p_int(i) = '1' and dsi_lp_oe(i) = '1') else 'Z';
dsi_lp_n_o(i) <= '1' when (dsi_lp_n_int(i) = '1' and dsi_lp_oe(i) = '1') else 'Z';
end generate gen_lp_tristates;
dsi_clk_lp_p_o <= '1' when (dsi_clk_lp_p = '1' and dsi_clk_lp_oe = '1') else 'Z';
dsi_clk_lp_n_o <= '1' when (dsi_clk_lp_n = '1' and dsi_clk_lp_oe = '1') else 'Z';
process(clk_sys)
begin
if rising_edge(clk_sys) then
cnx_master_in(c_slave_ddram_csr).ack <= cnx_master_out(c_slave_ddram_csr).stb and cnx_master_out(c_slave_ddram_csr).cyc;
end if;
end process;
cnx_master_in(c_slave_dsi).err <= '0';
cnx_master_in(c_slave_ddram_csr).stall <= '0';
cnx_master_in(c_slave_ddram_csr).err <= '0';
cnx_master_in(c_slave_ddram_mem).err <= '0';
dsi_gpio1_o <= dsi_gpio(0);
dsi_gpio0_o <= 'Z';
end rtl;
|
lgpl-3.0
|
0751905a40a29147d34988e3daf46f8f
| 0.519218 | 2.948825 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/TempDisplay.vhd
| 1 | 9,689 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Albert Fazakas, Elod Gyorgy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 14:50:40 03/17/2014
-- Design Name:
-- Module Name: TempDisplay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TempDisplay is
generic(
X_TMP_COL_WIDTH : natural := 50; -- = SZ_TH_WIDTH - width of a TEMP column
Y_TMP_COL_HEIGHT : natural := 472; -- = SZ_TH_HEIGHT - height of a TEMP column
X_TMP_H_LOC : natural := 1050; -- X Location of the TEMP Column
Y_TMP_V_LOC : natural := 80; -- Y Location of the TEMP Column
INPUT_DATA_WIDTH : natural := 12; -- Data width is 13 for the ADT7420 Temperature Sensor and
-- 12 for the XADC temperature data and the Accelerometer Temperature Sensor
TMP_TYPE : string := "XADC" -- Either "XADC" or "TEMP_ACC"
);
Port ( CLK_I : in STD_LOGIC;
TEMP_IN : in STD_LOGIC_VECTOR (INPUT_DATA_WIDTH - 1 downto 0);
H_COUNT_I : in STD_LOGIC_VECTOR (11 downto 0);
V_COUNT_I : in STD_LOGIC_VECTOR (11 downto 0);
-- Temperature Red, Green and Blue signals
TEMP_R_OUT : out STD_LOGIC_VECTOR (3 downto 0);
TEMP_G_OUT : out STD_LOGIC_VECTOR (3 downto 0);
TEMP_B_OUT : out STD_LOGIC_VECTOR (3 downto 0)
);
end TempDisplay;
architecture Behavioral of TempDisplay is
-- Used as starting point for the Temperature level size
-- The Temperature level size is according to the value of the temperature displayed
constant TEMP_OFFSET : std_logic_vector (11 downto 0) := "001000100110"; --550
constant TEMP_BOTTOM : natural := Y_TMP_V_LOC + Y_TMP_COL_HEIGHT + 1;
-- Maximum temperature
constant TEMP_MAX : std_logic_vector (23 downto 0) := X"000500"; -- 80C * 16
-- Convert Celsius to pixels such as 0C = 0 pixels, 80C = 480pixels
constant CELSIUS_TO_PIXELS : std_logic_vector(2 downto 0) := "110"; --6 = 480/(80-0)
-- Scale incoming XADC temperature data, according to the XADC datasheet
constant XADC_TMP_SCALE : std_logic_vector(17 downto 0) := "111110111" & "111110011"; --503.975 (18bit)
-- Convert Kelvin to Celsius
constant XADC_TMP_OFFSET : std_logic_vector(30 downto 0) := conv_std_logic_vector(integer(round(273.15)*4096.0), 31);
-- Converted and scaled temperature value
signal temp_value : std_logic_vector(9 downto 0);
-- Synchronize incoming temperature to the clock
signal temp_sync0, temp_sync : std_logic_vector(TEMP_IN'range);
-- signal storing the scaled XADC temperature data
signal temp_xad_scaled : std_logic_vector(temp_sync'length+XADC_TMP_SCALE'length-1 downto 0); --12bit*18bit=30bit
-- signal storing the offseted XADC temperature data
signal temp_xad_offset : std_logic_vector(XADC_TMP_OFFSET'range); --31bit
-- signal storing XADC temperature data converted to Celsius
signal temp_xad_celsius : std_logic_vector(temp_xad_offset'length-8-1 downto 0); --23bit
-- Signal storing the FPGA temperature limited to between 0C and 80C * 16
signal temp_xad_capped : std_logic_vector(temp_xad_celsius'high-1 downto 0); --no sign bit
-- The temperature scaled to pixels
signal temp_xad_px_scaled : std_logic_vector(temp_xad_capped'high+CELSIUS_TO_PIXELS'high+1 downto temp_xad_capped'low);
-- Signal storing the Temp Sensor or Accelerometer temperature limited to between 0C and 80C * 16
signal temp_capped : std_logic_vector(temp_sync'high-1 downto temp_sync'low);
-- Signal storing the Temp Sensor or Accelerometer temperature scaled to pixels: 0 = 0C, 480 = 80C * 16
signal temp_scaled : std_logic_vector(temp_capped'high+CELSIUS_TO_PIXELS'high+1 downto temp_capped'low);
-- Temp Column green and red color components
signal temp_color_red : std_logic_vector(3 downto 0);
signal temp_color_green : std_logic_vector(3 downto 0);
-- Temp Column red, green and blue signals
signal temp_red : std_logic_vector (3 downto 0);
signal temp_green : std_logic_vector (3 downto 0);
signal temp_blue : std_logic_vector (3 downto 0);
begin
-- The XADC temperature data will have to scaled with 503.975,
-- then transformed from Kelvin to Celsius
-- Then limit and scale it to pixels: 0 = 0C, 480 = 80C * 16, and multiply by 0.0625 (i.e. divide by 16)
XADC:
if TMP_TYPE = "XADC" generate
begin
process(CLK_I)
begin
if CLK_I'EVENT and CLK_I = '1' then
temp_sync0 <= TEMP_IN; --synchronize with pxl_clk domain
temp_sync <= temp_sync0;
--30b 12b 18b
temp_xad_scaled <= temp_sync * XADC_TMP_SCALE; -- ADC * 503.975 (fixed-point; decimal point at 9b)
temp_xad_offset <= '0' & temp_xad_scaled(29 downto 9) - XADC_TMP_OFFSET; -- ADC * 503.975 - 273.15 * 4096
temp_xad_celsius <= temp_xad_offset(temp_xad_offset'high downto 8); -- (ADC * 503.975 - 273.15) / 256; 1LSB=0.625C
if (temp_xad_celsius(temp_xad_celsius'high) = '1') then --if negative, cap to 0
temp_xad_capped <= (others => '0');
elsif (temp_xad_celsius(temp_xad_celsius'high-1 downto 0) > TEMP_MAX) then --if too big, cap to maximum scale /0.0625
temp_xad_capped <= TEMP_MAX(temp_xad_capped'range);
else
temp_xad_capped <= temp_xad_celsius(temp_xad_celsius'high-1 downto 0); --get rid of the sign bit
end if;
temp_xad_px_scaled <= temp_xad_capped * CELSIUS_TO_PIXELS; --scale to pixels
end if;
end process;
temp_value <= temp_xad_px_scaled(13 downto 4); -- * 0.0625 (1/2^4)
end generate;
-- The ADT7420 temperature sensor data and the ADXL362 accelerometer temperature data
-- will have to be limited and scaled to pixels: 0 = 0C, 480 = 80C * 16,
-- then multiply by 0.0625 (i.e. divide by 16)
-- Note that the accelerometer temperature data in fact is 0.065C /LSB. Multiplying it by 0.0625
-- at 80C the error will be about 3..4C
TEMP_ACC:
if TMP_TYPE = "TEMP_ACC" generate
process(CLK_I)
begin
if CLK_I'EVENT and CLK_I = '1' then
temp_sync0 <= TEMP_IN; --synchronize with pxl_clk domain
temp_sync <= temp_sync0;
if (temp_sync(temp_sync'high) = '1') then --if negative, cap to 0
temp_capped <= (others => '0');
elsif (temp_sync(temp_sync'high-1 downto 0) > TEMP_MAX) then -- if too big, cap to maximum scale /0.0625
temp_capped <= TEMP_MAX(temp_capped'range);
else
temp_capped <= temp_sync(temp_sync'high-1 downto 0); --get rid of the sign bit
end if;
temp_scaled <= temp_capped * CELSIUS_TO_PIXELS; --scale to pixels
end if;
end process;
temp_value <= temp_scaled(13 downto 4); -- * 0.0625 (1/2^4)
end generate;
-- Temperature Color Decode - As temperature is higher, the color turns from green to red
temp_color_red <= x"0" when temp_value < 16 else
x"1" when temp_value < 32 else
x"2" when temp_value < 48 else
x"3" when temp_value < 64 else
x"4" when temp_value < 80 else
x"5" when temp_value < 96 else
x"6" when temp_value < 112 else
x"7" when temp_value < 128 else
x"8" when temp_value < 144 else
x"9" when temp_value < 160 else
x"A" when temp_value < 176 else
x"B" when temp_value < 192 else
x"C" when temp_value < 208 else
x"D" when temp_value < 224 else
x"E" when temp_value < 240 else
x"F";
temp_color_green <= x"F" when temp_value < 256 else
x"E" when temp_value < 272 else
x"D" when temp_value < 288 else
x"C" when temp_value < 304 else
x"B" when temp_value < 320 else
x"A" when temp_value < 336 else
x"9" when temp_value < 352 else
x"8" when temp_value < 368 else
x"7" when temp_value < 384 else
x"6" when temp_value < 400 else
x"5" when temp_value < 416 else
x"4" when temp_value < 432 else
x"3" when temp_value < 448 else
x"2" when temp_value < 464 else
x"1" when temp_value < 480 else
x"0";
-- Red, Green and Blue Signals for the Temperature Column
temp_red <= temp_color_red when (H_COUNT_I > X_TMP_H_LOC and H_COUNT_I < X_TMP_H_LOC + X_TMP_COL_WIDTH)
and (V_COUNT_I > (TEMP_OFFSET - temp_value) and V_COUNT_I < TEMP_BOTTOM)
else x"F";
temp_green <= temp_color_green when (H_COUNT_I > X_TMP_H_LOC and H_COUNT_I < X_TMP_H_LOC + X_TMP_COL_WIDTH)
and (V_COUNT_I > (TEMP_OFFSET - temp_value) and V_COUNT_I < TEMP_BOTTOM)
else x"F";
-- The Temperature Colum color will be either a green-red combination (from green to orange, then red), or white
temp_blue <= x"0" when (H_COUNT_I > X_TMP_H_LOC and H_COUNT_I < X_TMP_H_LOC + X_TMP_COL_WIDTH)
and (V_COUNT_I > (TEMP_OFFSET - temp_value) and V_COUNT_I < TEMP_BOTTOM)
else x"F";
-- Assign Outputs
TEMP_R_OUT <= temp_red;
TEMP_G_OUT <= temp_green;
TEMP_B_OUT <= temp_blue;
end Behavioral;
|
gpl-3.0
|
09d90f29467ab89648aa731d5f4a5989
| 0.632573 | 3.288866 | false | false | false | false |
bzero/freezing-spice
|
src/dpram.vhd
| 2 | 2,668 |
-- Based on the Quartus II VHDL Template for True Dual-Port RAM with single clock
-- Read-during-write on port A or B returns newly written data
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_textio.all;
use std.textio.all;
entity dpram is
generic(g_data_width : natural := 16;
g_addr_width : natural := 10;
g_init : boolean := false;
g_init_file : string := "");
port(clk : in std_logic;
addr_a : in std_logic_vector(g_addr_width-1 downto 0);
addr_b : in std_logic_vector(g_addr_width-1 downto 0);
data_a : in std_logic_vector((g_data_width-1) downto 0);
data_b : in std_logic_vector((g_data_width-1) downto 0);
we_a : in std_logic := '1';
we_b : in std_logic := '1';
q_a : out std_logic_vector((g_data_width -1) downto 0);
q_b : out std_logic_vector((g_data_width -1) downto 0));
end dpram;
architecture rtl of dpram is
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((g_data_width-1) downto 0);
type ram_t is array(0 to 2**g_addr_width-1) of word_t;
-- function to initialize the RAM from a file
--impure function init_ram(fn : in string) return ram_t is
-- file f : text;
-- variable l : line;
-- variable ram : ram_t;
--begin
-- if g_init = true then
-- file_open(f, fn, READ_MODE);
-- for i in ram_t'range loop
-- readline(f, l);
-- read(l, ram(i));
-- end loop;
-- file_close(f);
-- else
-- ram := (others => (others => '0'));
-- end if;
-- return ram;
--end function;
-- Declare the RAM
shared variable ram : ram_t := (others => (others => '0')); --init_ram(g_init_file);
begin
-- Port A
process (clk)
variable addr : natural range 0 to 2**g_addr_width-1;
begin
if (rising_edge(clk)) then
addr := to_integer(unsigned(addr_a));
if (we_a = '1') then
ram(addr) := data_a;
end if;
q_a <= ram(addr);
end if;
end process;
-- Port B
process (clk)
variable addr : natural range 0 to 2**g_addr_width-1;
begin
if (rising_edge(clk)) then
addr := to_integer(unsigned(addr_b));
if (we_b = '1') then
ram(addr) := data_b;
end if;
q_b <= ram(addr);
end if;
end process;
end rtl;
|
bsd-3-clause
|
6ca7bebcd72c878fcdc3526b605390a0
| 0.505247 | 3.377215 | false | false | false | false |
bzero/freezing-spice
|
src/id.vhd
| 2 | 10,456 |
library ieee;
use ieee.std_logic_1164.all;
use work.common.all;
use work.id_pkg.all;
entity instruction_decoder is
port (d : in id_in;
q : out id_out); -- decoded data
end entity instruction_decoder;
architecture behavioral of instruction_decoder is
-------------------------------------------------
-- Types
-------------------------------------------------
type imm_type_t is (IMM_NONE, IMM_I, IMM_S, IMM_B, IMM_U, IMM_J);
-------------------------------------------------
-- Signals
-------------------------------------------------
signal decoded : id_out := c_decoded_reset;
begin -- architecture behavioral
-------------------------------------------------
-- Assign module outputs
-------------------------------------------------
q <= decoded;
-------------------------------------------------
-- Decode the RISCV instruction
-------------------------------------------------
decode_proc : process (d) is
variable opcode : std_logic_vector(6 downto 0);
variable funct3 : std_logic_vector(2 downto 0);
variable imm_type : imm_type_t := IMM_NONE;
variable insn : word;
variable rd : std_logic_vector(4 downto 0);
begin -- process decode_proc
insn := d.instruction;
rd := insn(11 downto 7);
-- defaults & important fields
opcode := insn(6 downto 0);
funct3 := insn(14 downto 12);
decoded.rs1 <= insn(19 downto 15);
decoded.rs2 <= insn(24 downto 20);
decoded.rd <= rd;
decoded.opcode <= opcode;
decoded.rs1_rd <= '0';
decoded.rs2_rd <= '0';
decoded.alu_func <= ALU_NONE;
decoded.op2_src <= '0';
decoded.insn_type <= OP_ILLEGAL;
decoded.load_type <= LOAD_NONE;
decoded.store_type <= STORE_NONE;
decoded.imm <= (others => '0');
decoded.use_imm <= '0';
decoded.branch_type <= BRANCH_NONE;
decoded.rf_we <= '0';
case (opcode) is
-- Load Upper Immediate
when c_op_lui =>
decoded.insn_type <= OP_LUI;
imm_type := IMM_U;
if (rd /= "00000") then
decoded.rf_we <= '1';
end if;
-- Add Upper Immediate to PC
when c_op_auipc =>
decoded.insn_type <= OP_AUIPC;
imm_type := IMM_U;
decoded.alu_func <= ALU_ADD;
if (rd /= "00000") then
decoded.rf_we <= '1';
end if;
-- Jump And Link
when c_op_jal =>
decoded.insn_type <= OP_JAL;
decoded.alu_func <= ALU_ADD;
imm_type := IMM_J;
if (rd /= "00000") then
decoded.rf_we <= '1';
end if;
-- Jump And Link Register
when c_op_jalr =>
decoded.insn_type <= OP_JALR;
decoded.alu_func <= ALU_ADD;
imm_type := IMM_I;
decoded.rs1_rd <= '1';
if (rd /= "00000") then
decoded.rf_we <= '1';
end if;
-- Branch to target address, if condition is met
when c_op_branch =>
decoded.insn_type <= OP_BRANCH;
decoded.alu_func <= ALU_ADD;
imm_type := IMM_B;
decoded.rs1_rd <= '1';
decoded.rs2_rd <= '1';
case (funct3) is
when "000" => decoded.branch_type <= BEQ;
when "001" => decoded.branch_type <= BNE;
when "100" => decoded.branch_type <= BLT;
when "101" => decoded.branch_type <= BGE;
when "110" => decoded.branch_type <= BLTU;
when "111" => decoded.branch_type <= BGEU;
when others => null;
end case;
-- load data from memory
when c_op_load =>
decoded.insn_type <= OP_LOAD;
imm_type := IMM_I;
decoded.rs1_rd <= '1';
decoded.alu_func <= ALU_ADD;
if (rd /= "00000") then
decoded.rf_we <= '1';
end if;
case (funct3) is
when "000" => decoded.load_type <= LB;
when "001" => decoded.load_type <= LH;
when "010" => decoded.load_type <= LW;
when "100" => decoded.load_type <= LBU;
when "101" => decoded.load_type <= LHU;
when others => null;
end case;
-- store data to memory
when c_op_store =>
decoded.insn_type <= OP_STORE;
imm_type := IMM_S;
decoded.alu_func <= ALU_ADD;
decoded.rs1_rd <= '1';
decoded.rs2_rd <= '1';
case (funct3) is
when "000" => decoded.store_type <= SB;
when "001" => decoded.store_type <= SH;
when "010" => decoded.store_type <= SW;
when others => null;
end case;
-- perform computation with immediate value and a register
when c_op_imm =>
decoded.insn_type <= OP_ALU;
decoded.op2_src <= '1';
imm_type := IMM_I;
decoded.rs1_rd <= '1';
decoded.use_imm <= '1';
if (rd /= "00000") then
decoded.rf_we <= '1';
end if;
case (funct3) is
when "000" => decoded.alu_func <= ALU_ADD;
when "001" => decoded.alu_func <= ALU_SLL;
when "010" => decoded.alu_func <= ALU_SLT;
when "011" => decoded.alu_func <= ALU_SLTU;
when "100" => decoded.alu_func <= ALU_XOR;
when "110" => decoded.alu_func <= ALU_OR;
when "111" => decoded.alu_func <= ALU_AND;
when "101" =>
if (insn(30) = '1') then
decoded.alu_func <= ALU_SRA;
else
decoded.alu_func <= ALU_SRL;
end if;
when others => null;
end case;
-- perform computation with two register values
when c_op_reg =>
decoded.insn_type <= OP_ALU;
decoded.rs1_rd <= '1';
decoded.rs2_rd <= '1';
if (rd /= "00000") then
decoded.rf_we <= '1';
end if;
case (funct3) is
when "000" =>
if (insn(30) = '1') then
decoded.alu_func <= ALU_SUB;
else
decoded.alu_func <= ALU_ADD;
end if;
when "001" => decoded.alu_func <= ALU_SLL;
when "010" => decoded.alu_func <= ALU_SLT;
when "011" => decoded.alu_func <= ALU_SLTU;
when "100" => decoded.alu_func <= ALU_XOR;
when "101" =>
if (insn(30) = '1') then
decoded.alu_func <= ALU_SRA;
else
decoded.alu_func <= ALU_SRL;
end if;
when "110" => decoded.alu_func <= ALU_OR;
when "111" => decoded.alu_func <= ALU_AND;
when others => null;
end case;
-- @TODO other insnructions
--when c_op_misc_mem =>
-- insn_type <= OP_FENCE;
--when c_op_system =>
-- insn_type <= OP_SYSTEM;
when others =>
decoded.insn_type <= OP_ILLEGAL;
end case;
-- decode and sign-extend the immediate value
case imm_type is
when IMM_I =>
for i in 31 downto 12 loop
decoded.imm(i) <= insn(31);
end loop;
decoded.imm(11 downto 5) <= insn(31 downto 25);
decoded.imm(4 downto 1) <= insn(24 downto 21);
decoded.imm(0) <= insn(20);
when IMM_S =>
for i in 31 downto 11 loop
decoded.imm(i) <= insn(31);
end loop; -- i
decoded.imm(10 downto 5) <= insn(30 downto 25);
decoded.imm(4 downto 1) <= insn(11 downto 8);
decoded.imm(0) <= insn(7);
when IMM_B =>
for i in 31 downto 13 loop
decoded.imm(i) <= insn(31);
end loop; -- i
decoded.imm(12) <= insn(31);
decoded.imm(11) <= insn(7);
decoded.imm(10 downto 5) <= insn(30 downto 25);
decoded.imm(4 downto 1) <= insn(11 downto 8);
decoded.imm(0) <= '0';
when IMM_U =>
decoded.imm(31) <= insn(31);
decoded.imm(30 downto 20) <= insn(30 downto 20);
decoded.imm(19 downto 12) <= insn(19 downto 12);
decoded.imm(11 downto 0) <= (others => '0');
when IMM_J =>
for i in 31 downto 20 loop
decoded.imm(i) <= insn(31);
end loop; -- i
decoded.imm(19 downto 12) <= insn(19 downto 12);
decoded.imm(11) <= insn(20);
decoded.imm(10 downto 5) <= insn(30 downto 25);
decoded.imm(4 downto 1) <= insn(24 downto 21);
decoded.imm(0) <= '0';
when others => decoded.imm <= (others => '0');
end case;
end process decode_proc;
end architecture behavioral;
|
bsd-3-clause
|
c0edb4a31c9c18e76d9fb05243405e60
| 0.389824 | 4.443689 | false | false | false | false |
bzero/freezing-spice
|
tests/pipeline_tb.vhd
| 2 | 7,171 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.common.all;
use work.decode_pkg.all;
use work.encode_pkg.all;
entity pipeline_tb is
end entity pipeline_tb;
architecture testbench of pipeline_tb is
signal clk : std_logic := '0';
signal rst_n : std_logic := '1';
-- inputs
signal insn_in : word := (others => '0');
signal insn_addr : word := (others => '0');
signal insn_valid : std_logic := '0';
signal data_in : word := (others => '0');
signal data_in_valid : std_logic := '0';
-- outputs
signal data_write_en : std_logic;
signal data_read_en : std_logic;
signal data_addr : word;
signal data_out : word;
-- simulation specific
signal done : boolean := false;
constant clk_period : time := 10 ns; -- 100 MHz
-- the program memory
type ram_t is array(0 to 100) of word;
constant rom : ram_t := (0 => encode_i_type(I_ADDI, "000000000100", 0, 1), -- ADDI x0, x1, 4
4 => encode_i_type(I_ADDI, "000000001000", 0, 2), -- ADDI x0, x2, 8
8 => encode_r_type(R_ADD, 1, 2, 3), -- ADD x1, x2, x3
12 => encode_u_type(U_LUI, "10000000000000000001", 4), -- LUI 0x80001, x4
16 => encode_uj_type(UJ_JAL, "00000000000000010010", 6), -- JAL 18, x6
20 => encode_i_type(I_ADDI, "000000000001", 0, 1), -- ADDI x0, x1, 1 -- this should not get executed
24 => encode_i_type(I_ADDI, "000000000001", 0, 1), -- ADDI x0, x1, 1 -- this should not get executed
28 => encode_i_type(I_ADDI, "000000000001", 0, 1), -- ADDI x0, x1, 1 -- this should not get executed
32 => encode_i_type(I_ADDI, "000000000001", 0, 1), -- ADDI x0, x1, 1 -- this should not get executed
36 => encode_i_type(I_ADDI, "000000000001", 0, 1), -- ADDI x0, x1, 1 -- this should not get executed
40 => NOP,
44 => NOP,
48 => NOP,
52 => encode_r_type(R_ADD, 3, 4, 5), -- ADD x3, x4, x5
56 => encode_u_type(U_AUIPC, "10000000000000000001", 8), -- AUIPC 0x80001, x8
-- should store the value in x8 into address 8 (offset 4 + value in x1 (4))
60 => encode_s_type(S_SW, "000000000100", 1, 8), -- SW x1, x8, 4
64 => encode_i_type(I_LH, "000000001000", 0, 9), -- LH x0, x9, 8
68 => encode_r_type(R_ADD, 8, 9, 10), -- ADD x8, x9, x10
72 => encode_sb_type(SB_BNE, "111111111110", 9, 8), -- BNE x9, x8, -4
-- 72 => encode_uj_type(UJ_JAL, "00000000000000000000", 7), -- JAL x7, 0
76 => encode_i_type(I_ADDI, "000000000001", 0, 1), -- ADDI x0, x1, 1 -- this should not get executed
80 => encode_i_type(I_ADDI, "000000000011", 0, 1), -- ADDI x0, x1, 3 -- this should not get executed
84 => encode_i_type(I_ADDI, "000000000111", 0, 1), -- ADDI x0, x1, 3 -- this should not get executed
88 => encode_i_type(I_ADDI, "000000001111", 0, 1), -- ADDI x0, x1, 3 -- this should not get executed
92 => encode_i_type(I_ADDI, "000000011111", 0, 1), -- ADDI x0, x1, 3 -- this should not get executed
others => NOP);
-- data memory
signal ram : ram_t := (0 => "10000000000000001000000010000001",
others => (others => '0'));
signal aux_addr : std_logic_vector(6 downto 0) := (others => '0');
signal aux_in : word;
signal aux_write : std_logic := '0';
begin
instruction_memory : entity work.dpram(rtl)
generic map (g_data_width => 32,
g_addr_width => 7,
g_init => false,
g_init_file => "")
port map (clk => clk,
addr_a => insn_addr(6 downto 0),
data_a => (others => '0'),
we_a => '0',
q_a => insn_in,
addr_b => aux_addr,
data_b => aux_in,
we_b => aux_write,
q_b => open);
-- create a clock
clk <= '0' when done else (not clk) after clk_period / 2;
-- purpose: data memory
ram_proc : process (clk, rst_n) is
variable addr : integer;
begin
if rst_n = '0' then
data_in_valid <= '0';
elsif rising_edge(clk) then
data_in_valid <= '0';
addr := to_integer(unsigned(data_addr));
if data_write_en = '1' then
ram(addr) <= data_out;
elsif data_read_en = '1' then
data_in <= ram(addr);
data_in_valid <= '1';
end if;
end if;
end process ram_proc;
-- instantiate the unit under test
uut : entity work.pipeline(Behavioral)
generic map (
g_initial_pc => (others => '0'),
g_for_sim => true)
port map (
clk => clk,
rst_n => rst_n,
insn_in => insn_in,
insn_addr => insn_addr,
insn_valid => insn_valid,
data_in => data_in,
data_out => data_out,
data_addr => data_addr,
data_write_en => data_write_en,
data_read_en => data_read_en,
data_in_valid => data_in_valid);
-- purpose: Provide stimulus to test the pipeline
-- type : combinational
stimulus_proc : process is
variable i : natural := 0;
begin -- process stimulus_proc
-- reset sequence
println ("Beginning simulation");
-- fill up the instruction memory
rst_n <= '0';
aux_write <= '1';
while i <= ram'high loop
aux_addr <= std_logic_vector(to_unsigned(i,7));
aux_in <= rom(i);
i := i + 4;
wait for clk_period;
end loop;
aux_write <= '0';
wait for clk_period * 2;
rst_n <= '1';
wait for clk_period;
insn_valid <= '1';
-- begin stimulus
wait for clk_period * 45;
-- finished with simulation
----------------------------------------------------------------
println("Simulation complete");
----------------------------------------------------------------
done <= true;
wait;
end process stimulus_proc;
end architecture testbench;
|
bsd-3-clause
|
d1bbb78032da3027c83b4563e3b35784
| 0.441919 | 3.878313 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/AccelArithmetics.vhd
| 1 | 9,819 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Albert Fazakas
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 14:45:49 03/05/2014
-- Design Name:
-- Module Name: AccelArithmetics - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This module transforms the incoming acceleration data from the ADXL_Control module into a format
-- that is displayed on the VGA screen:
-- - The incoming ACCEL_X_IN, ACCEL_Y_IN and ACCEL_Z_IN data is on 2g scale (-2g to +2g) represented on
-- 12 bits two's complement
-- - The ACCEL_Y_IN data is inverted, according to the accelerometer layout position on the Nexys4 board
--
-- - Both ACCEL_X_IN and ACCEL_Y_IN are scaled and limited to ACC_X_Y_MIN - ACC_X_Y_MAX (by default 0-511),
-- meaning: -1g: ACC_X_Y_MIN, 0g: (ACC_X_Y_MAX - ACC_X_Y_MIN)/2, 1g: ACC_X_Y_MAX. In this case will be
-- -1g: 0, 0g: 255 and 1g: 511, corresponding to the accelerometer data display on the VGA screen of 512 * 512
-- pixels.
--
-- - The acceleration magnitude is calculated according to the formula SQRT (ACC_X^2 + ACC_Y^2 + ACC_Z^2). For square
-- root calculation, a Logicore Square Root component is used. Due to the scaling purposes on the screen, the result
-- of the square root calculation is also divided by four.
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use ieee.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_signed.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AccelArithmetics is
generic
(
SYSCLK_FREQUENCY_HZ : integer := 100000000;
ACC_X_Y_MAX : STD_LOGIC_VECTOR (9 downto 0) := "01" & X"FF"; -- 511 pixels, corresponding to +1g
ACC_X_Y_MIN : STD_LOGIC_VECTOR (9 downto 0) := (others => '0') -- corresponding to -1g
);
port
(
SYSCLK : in STD_LOGIC; -- System Clock
RESET : in STD_LOGIC;
-- Accelerometer data input signals
ACCEL_X_IN : in STD_LOGIC_VECTOR (11 downto 0);
ACCEL_Y_IN : in STD_LOGIC_VECTOR (11 downto 0);
ACCEL_Z_IN : in STD_LOGIC_VECTOR (11 downto 0);
Data_Ready : in STD_LOGIC;
-- Accelerometer data output signals to be sent to the VGA display
ACCEL_X_OUT : out STD_LOGIC_VECTOR (8 downto 0);
ACCEL_Y_OUT : out STD_LOGIC_VECTOR (8 downto 0);
ACCEL_MAG_OUT : out STD_LOGIC_VECTOR (11 downto 0)
);
end AccelArithmetics;
architecture Behavioral of AccelArithmetics is
-- convert ACCEL_X and ACCEL_Y data to unsigned and divide by 4
-- (scaled to 0-1023, with -2g=0, 0g=511, 2g=1023)
-- Then limit to -1g = 0, 0g = 255, 1g = 511
-- Use a Square Root Logicore component to calculate the magnitude
COMPONENT Square_Root
PORT (
aclk : IN STD_LOGIC;
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
ATTRIBUTE SYN_BLACK_BOX : BOOLEAN;
ATTRIBUTE SYN_BLACK_BOX OF Square_Root : COMPONENT IS TRUE;
ATTRIBUTE BLACK_BOX_PAD_PIN : STRING;
ATTRIBUTE BLACK_BOX_PAD_PIN OF Square_Root : COMPONENT IS "aclk,s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[15:0]";
constant SUM_FACTOR : std_logic_vector (12 downto 0) := '0' & X"7FF"; --2047
constant LOWER_ACC_BOUNDARY : std_logic_vector (9 downto 0) := "00" & X"FF"; -- 255
constant UPPER_ACC_BOUNDARY : std_logic_vector (9 downto 0) := "10" & X"FF"; -- 767
-- Invert Y axis data in order to display it on the screen correctly
signal ACCEL_Y_IN_INV : STD_LOGIC_VECTOR (11 downto 0);
signal ACCEL_X_SUM : std_logic_vector (12 downto 0) := (others => '0'); -- one more bit to keep the sign extension
signal ACCEL_Y_SUM : std_logic_vector (12 downto 0) := (others => '0');
signal ACCEL_X_SUM_SHIFTED : std_logic_vector (9 downto 0) := (others => '0'); -- Divide the sum by four
signal ACCEL_Y_SUM_SHIFTED : std_logic_vector (9 downto 0) := (others => '0');
signal ACCEL_X_CLIP : std_logic_vector (9 downto 0) := (others => '0');
signal ACCEL_Y_CLIP : std_logic_vector (9 downto 0) := (others => '0');
-- Calculate magnitude
-- Pipe Data_Ready
signal Data_Ready_0, Data_Ready_1 : std_logic := '0';
signal ACCEL_X_SQUARE : std_logic_vector (23 downto 0) := (others => '0');
signal ACCEL_Y_SQUARE : std_logic_vector (23 downto 0) := (others => '0');
signal ACCEL_Z_SQUARE : std_logic_vector (23 downto 0) := (others => '0');
signal ACCEL_MAG_SQUARE : std_logic_vector (25 downto 0) := (others => '0');
signal ACCEL_MAG_SQRT: std_logic_vector (13 downto 0) := (others => '0');
signal m_axis_dout_tdata: std_logic_vector (15 downto 0);
begin
-- Invert Accel_Y data to display on the screen the box movement
-- on the Y axis according to the board movement
ACCEL_Y_IN_INV <= (NOT ACCEL_Y_IN) + X"001";
-- Add 2047 to the incoming acceleration data
-- Therefore ACCEL_X_SUM and ACCEL_Y_SUM will be scaled to
-- -2g = 0, -1g = 1023, 0g = 2047, 1g = 3071, 2g = 4095
Accel_Sum: process (SYSCLK, RESET, ACCEL_X_IN, ACCEL_Y_IN, Data_Ready)
begin
if SYSCLK'EVENT and SYSCLK = '1' then
if RESET = '1' then
ACCEL_X_SUM <= (others => '0');
ACCEL_Y_SUM <= (others => '0');
elsif Data_Ready = '1' then
if ACCEL_X_IN(11) = '1' then -- if negative, keep the sign extension
ACCEL_X_SUM <= ('1' & ACCEL_X_IN) + SUM_FACTOR;
else
ACCEL_X_SUM <= ('0' & ACCEL_X_IN) + SUM_FACTOR;
end if;
if ACCEL_Y_IN_INV(11) = '1' then -- if negative, keep the sign extension
ACCEL_Y_SUM <= ('1' & ACCEL_Y_IN_INV) + SUM_FACTOR;
else
ACCEL_Y_SUM <= ('0' & ACCEL_Y_IN_INV) + SUM_FACTOR;
end if;
end if;
end if;
end process Accel_Sum;
-- Divide by four ACCEL_X_SUM and ACCEL_Y_SUM, therefore will be scaled to
-- -2g = 0, -1g = 255, 0g = 511, 1g = 767, 2g = 1023
ACCEL_X_SUM_SHIFTED <= ACCEL_X_SUM(11 downto 2);
ACCEL_Y_SUM_SHIFTED <= ACCEL_Y_SUM(11 downto 2);
-- Subtract 255 and limit to -1g = 0, 0g = 255, 1g = 511
Accel_Clip: process (SYSCLK, RESET, ACCEL_X_SUM, ACCEL_Y_SUM)
begin
if SYSCLK'EVENT and SYSCLK = '1' then
if RESET = '1' then
ACCEL_X_CLIP <= (others => '0');
ACCEL_Y_CLIP <= (others => '0');
else -- If the sum is negative or < 255 (-1g)
if (ACCEL_X_SUM(12) = '1') or (unsigned(ACCEL_X_SUM_SHIFTED) < unsigned(LOWER_ACC_BOUNDARY)) then
ACCEL_X_CLIP <= ACC_X_Y_MIN ; -- Limit to 0
elsif (unsigned(ACCEL_X_SUM_SHIFTED) >= unsigned(UPPER_ACC_BOUNDARY)) then
ACCEL_X_CLIP <= ACC_X_Y_MAX; -- Limit to 511
else
ACCEL_X_CLIP <= ACCEL_X_SUM_SHIFTED - LOWER_ACC_BOUNDARY; -- subtract 255
end if;
-- If the sum is negative or < 255 (-1g)
if (ACCEL_Y_SUM(12) = '1') or (unsigned(ACCEL_Y_SUM_SHIFTED) < unsigned(LOWER_ACC_BOUNDARY)) then
ACCEL_Y_CLIP <= ACC_X_Y_MIN; -- Limit to 0
elsif (unsigned(ACCEL_Y_SUM_SHIFTED) >= unsigned(UPPER_ACC_BOUNDARY)) then
ACCEL_Y_CLIP <= ACC_X_Y_MAX; -- Limit to 511
else
ACCEL_Y_CLIP <= ACCEL_Y_SUM_SHIFTED - LOWER_ACC_BOUNDARY; -- subtract 255
end if;
end if;
end if;
end process Accel_Clip;
-- ACCEL_X_CLIP and ACCEL_Y_CLIP values (0-511) can be represented on 9 bits
ACCEL_X_OUT <= ACCEL_X_CLIP(8 downto 0);
ACCEL_Y_OUT <= ACCEL_Y_CLIP(8 downto 0);
-- Pipe Data_Ready
Pipe_Data_Ready : process (SYSCLK, RESET, Data_Ready, Data_Ready_0)
begin
if SYSCLK'EVENT and SYSCLK = '1' then
if RESET = '1' then
Data_Ready_0 <= '0';
Data_Ready_1 <= '0';
else
Data_Ready_0 <= Data_Ready;
Data_Ready_1 <= Data_Ready_0;
end if;
end if;
end process Pipe_Data_Ready;
-- Calculate squares of the incoming acceleration values
Calculate_Square: process (SYSCLK, Data_Ready, ACCEL_X_IN, ACCEL_Y_IN, ACCEL_Z_IN)
begin
if SYSCLK'EVENT and SYSCLK = '1' then
if Data_Ready = '1' then
ACCEL_X_SQUARE <= ACCEL_X_IN * ACCEL_X_IN;
ACCEL_Y_SQUARE <= ACCEL_Y_IN * ACCEL_Y_IN;
ACCEL_Z_SQUARE <= ACCEL_Z_IN * ACCEL_Z_IN;
end if;
end if;
end process Calculate_Square;
-- Calculate the sum of the squares to determine the magnitude of the acceleration
Calculate_Square_Sum: process (SYSCLK, Data_Ready_0, ACCEL_X_SQUARE, ACCEL_Y_SQUARE, ACCEL_Z_SQUARE)
begin
if SYSCLK'EVENT and SYSCLK = '1' then
if Data_Ready_0 = '1' then
ACCEL_MAG_SQUARE <= ("00" & ACCEL_X_SQUARE) + ("00" & ACCEL_Y_SQUARE) + ("00" & ACCEL_Z_SQUARE);
end if;
end if;
end process Calculate_Square_Sum;
-- Calculate the square root to determine magnitude
Magnitude_Calculation : Square_Root
PORT MAP (
aclk => SYSCLK,
s_axis_cartesian_tvalid => Data_Ready_1,
s_axis_cartesian_tdata => ("000000" & ACCEL_MAG_SQUARE),
m_axis_dout_tvalid => open,
m_axis_dout_tdata => m_axis_dout_tdata
);
ACCEL_MAG_SQRT <= m_axis_dout_tdata (13 downto 0);
-- Also divide the square root by 4
ACCEL_MAG_OUT <= ACCEL_MAG_SQRT(13 downto 2);
end Behavioral;
|
gpl-3.0
|
3f5d06e7d6b1c7a664a48856f9c0da6c
| 0.615847 | 3.27737 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.ip_user_files/ipstatic/axi_uartlite_v2_0_10/hdl/src/vhdl/uartlite_core.vhd
| 1 | 21,394 |
-------------------------------------------------------------------------------
-- uartlite_core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2012] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_core.vhd
-- Version: v2.0
-- Description: UART Lite core for implementing UART logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_uartlite_v2_0_10;
-- baudrate refered from axi_uartlite_v2_0_10
use axi_uartlite_v2_0_10.baudrate;
-- uartlite_rx refered from axi_uartlite_v2_0_10
use axi_uartlite_v2_0_10.uartlite_rx;
-- uartlite_tx refered from axi_uartlite_v2_0_10
use axi_uartlite_v2_0_10.uartlite_tx;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- Slave attachment interface
-- bus2ip_data -- bus2ip data signal
-- bus2ip_rdce -- bus2ip read CE
-- bus2ip_wrce -- bus2ip write CE
-- ip2bus_rdack -- ip2bus read acknowledgement
-- ip2bus_wrack -- ip2bus write acknowledgement
-- ip2bus_error -- ip2bus error
-- SIn_DBus -- ip2bus data
-- UART Lite interface
-- RX -- Receive Data
-- TX -- Transmit Data
-- Interrupt -- UART Interrupt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_core is
generic
(
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ: integer := 100_000_000;
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
-- IPIF signals
bus2ip_data : in std_logic_vector(0 to 7);
bus2ip_rdce : in std_logic_vector(0 to 3);
bus2ip_wrce : in std_logic_vector(0 to 3);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
SIn_DBus : out std_logic_vector(0 to 7);
-- UART signals
RX : in std_logic;
TX : out std_logic;
Interrupt : out std_logic
);
end entity uartlite_core;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
---------------------------------------------------------------------------
-- function declarations
---------------------------------------------------------------------------
function CALC_RATIO ( C_S_AXI_ACLK_FREQ_HZ : integer;
C_BAUDRATE : integer ) return Integer is
constant C_BAUDRATE_16_BY_2: integer := (16 * C_BAUDRATE) / 2;
constant REMAINDER : integer :=
C_S_AXI_ACLK_FREQ_HZ rem (16 * C_BAUDRATE);
constant RATIO : integer :=
C_S_AXI_ACLK_FREQ_HZ / (16 * C_BAUDRATE);
begin
if (C_BAUDRATE_16_BY_2 < REMAINDER) then
return (RATIO + 1);
else
return RATIO;
end if;
end function CALC_RATIO;
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant RATIO : integer := CALC_RATIO( C_S_AXI_ACLK_FREQ_HZ, C_BAUDRATE);
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
-- Read Only
signal status_reg : std_logic_vector(0 to 7) := (others => '0');
-- bit 7 rx_Data_Present
-- bit 6 rx_Buffer_Full
-- bit 5 tx_Buffer_Empty
-- bit 4 tx_Buffer_Full
-- bit 3 enable_interrupts
-- bit 2 Overrun Error
-- bit 1 Frame Error
-- bit 0 Parity Error (If C_USE_PARITY is true, otherwise '0')
-- Write Only
-- Below mentioned bits belong to Control Register and are declared as
-- signals below
-- bit 0-2 Dont'Care
-- bit 3 enable_interrupts
-- bit 4-5 Dont'Care
-- bit 6 Reset_RX_FIFO
-- bit 7 Reset_TX_FIFO
signal en_16x_Baud : std_logic;
signal enable_interrupts : std_logic;
signal reset_RX_FIFO : std_logic;
signal rx_Data : std_logic_vector(0 to C_DATA_BITS-1);
signal rx_Data_Present : std_logic;
signal rx_Buffer_Full : std_logic;
signal rx_Frame_Error : std_logic;
signal rx_Overrun_Error : std_logic;
signal rx_Parity_Error : std_logic;
signal clr_Status : std_logic;
signal reset_TX_FIFO : std_logic;
signal tx_Buffer_Full : std_logic;
signal tx_Buffer_Empty : std_logic;
signal tx_Buffer_Empty_Pre : std_logic;
signal rx_Data_Present_Pre : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
-- Generating the acknowledgement and error signals
---------------------------------------------------------------------------
ip2bus_rdack <= bus2ip_rdce(0) or bus2ip_rdce(2) or bus2ip_rdce(1)
or bus2ip_rdce(3);
ip2bus_wrack <= bus2ip_wrce(1) or bus2ip_wrce(3) or bus2ip_wrce(0)
or bus2ip_wrce(2);
ip2bus_error <= ((bus2ip_rdce(0) and not rx_Data_Present) or
(bus2ip_wrce(1) and tx_Buffer_Full) );
-------------------------------------------------------------------------
-- BAUD_RATE_I : Instansiating the baudrate module
-------------------------------------------------------------------------
BAUD_RATE_I : entity axi_uartlite_v2_0_10.baudrate
generic map
(
C_RATIO => RATIO
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud
);
-------------------------------------------------------------------------
-- Status register handling
-------------------------------------------------------------------------
status_reg(7) <= rx_Data_Present;
status_reg(6) <= rx_Buffer_Full;
status_reg(5) <= tx_Buffer_Empty;
status_reg(4) <= tx_Buffer_Full;
status_reg(3) <= enable_interrupts;
-------------------------------------------------------------------------
-- CLEAR_STATUS_REG : Process to clear status register
-------------------------------------------------------------------------
CLEAR_STATUS_REG : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then
if Reset = '1' then
clr_Status <= '0';
else
clr_Status <= bus2ip_rdce(2);
end if;
end if;
end process CLEAR_STATUS_REG;
-------------------------------------------------------------------------
-- Process to register rx_Overrun_Error
-------------------------------------------------------------------------
RX_OVERRUN_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Reset = '1') or (clr_Status = '1')) then
status_reg(2) <= '0';
elsif (rx_Overrun_Error = '1') then
status_reg(2) <= '1';
end if;
end if;
end process RX_OVERRUN_ERROR_DFF;
-------------------------------------------------------------------------
-- Process to register rx_Frame_Error
-------------------------------------------------------------------------
RX_FRAME_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(1) <= '0';
else
if (clr_Status = '1') then
status_reg(1) <= '0';
elsif (rx_Frame_Error = '1') then
status_reg(1) <= '1';
end if;
end if;
end if;
end process RX_FRAME_ERROR_DFF;
-------------------------------------------------------------------------
-- If C_USE_PARITY = 1, register rx_Parity_Error
-------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
RX_PARITY_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(0) <= '0';
else
if (clr_Status = '1') then
status_reg(0) <= '0';
elsif (rx_Parity_Error = '1') then
status_reg(0) <= '1';
end if;
end if;
end if;
end process RX_PARITY_ERROR_DFF;
end generate USING_PARITY;
-------------------------------------------------------------------------
-- NO_PARITY : If C_USE_PARITY = 0, rx_Parity_Error bit is not present
-------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
status_reg(0) <= '0';
end generate NO_PARITY;
-------------------------------------------------------------------------
-- CTRL_REG_DFF : Control Register Handling
-------------------------------------------------------------------------
CTRL_REG_DFF : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
reset_TX_FIFO <= '1';
reset_RX_FIFO <= '1';
enable_interrupts <= '0';
elsif (bus2ip_wrce(3) = '1') then
reset_RX_FIFO <= bus2ip_data(6);
reset_TX_FIFO <= bus2ip_data(7);
enable_interrupts <= bus2ip_data(3);
else
reset_TX_FIFO <= '0';
reset_RX_FIFO <= '0';
end if;
end if;
end process CTRL_REG_DFF;
-------------------------------------------------------------------------
-- Tx Fifo Interrupt handling
-------------------------------------------------------------------------
TX_BUFFER_EMPTY_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Buffer_Empty_Pre <= '0';
else
if (bus2ip_wrce(1) = '1') then
tx_Buffer_Empty_Pre <= '0';
else
tx_Buffer_Empty_Pre <= tx_Buffer_Empty;
end if;
end if;
end if;
end process TX_BUFFER_EMPTY_DFF_I;
-------------------------------------------------------------------------
-- Rx Fifo Interrupt handling
-------------------------------------------------------------------------
RX_BUFFER_DATA_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
rx_Data_Present_Pre <= '0';
else
if (bus2ip_rdce(0) = '1') then
rx_Data_Present_Pre <= '0';
else
rx_Data_Present_Pre <= rx_Data_Present;
end if;
end if;
end if;
end process RX_BUFFER_DATA_DFF_I;
-------------------------------------------------------------------------
-- Interrupt register handling
-------------------------------------------------------------------------
INTERRUPT_DFF: process (Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then -- synchronous reset (active high)
Interrupt <= '0';
else
Interrupt <= enable_interrupts and
((rx_Data_Present and not rx_Data_Present_Pre) or
(tx_Buffer_Empty and not tx_Buffer_Empty_Pre));
end if;
end if;
end process INTERRUPT_DFF;
-------------------------------------------------------------------------
-- READ_MUX : Read bus interface handling
-------------------------------------------------------------------------
READ_MUX : process (status_reg, bus2ip_rdce(2), bus2ip_rdce(0), rx_Data) is
begin -- process Read_Mux
if (bus2ip_rdce(2) = '1') then
SIn_DBus <= status_reg;
elsif (bus2ip_rdce(0) = '1') then
SIn_DBus((8-C_DATA_BITS) to 7) <= rx_Data;
SIn_DBus(0 to (7-C_DATA_BITS)) <= (others => '0');
else
SIn_DBus <= (others => '0');
end if;
end process READ_MUX;
-------------------------------------------------------------------------
-- UARTLITE_RX_I : Instansiating the receive module
-------------------------------------------------------------------------
UARTLITE_RX_I : entity axi_uartlite_v2_0_10.uartlite_rx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
RX => RX,
Read_RX_FIFO => bus2ip_rdce(0),
Reset_RX_FIFO => reset_RX_FIFO,
RX_Data => rx_Data,
RX_Data_Present => rx_Data_Present,
RX_Buffer_Full => rx_Buffer_Full,
RX_Frame_Error => rx_Frame_Error,
RX_Overrun_Error => rx_Overrun_Error,
RX_Parity_Error => rx_Parity_Error
);
-------------------------------------------------------------------------
-- UARTLITE_TX_I : Instansiating the transmit module
-------------------------------------------------------------------------
UARTLITE_TX_I : entity axi_uartlite_v2_0_10.uartlite_tx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
TX => TX,
Write_TX_FIFO => bus2ip_wrce(1),
Reset_TX_FIFO => reset_TX_FIFO,
TX_Data => bus2ip_data(8-C_DATA_BITS to 7),
TX_Buffer_Full => tx_Buffer_Full,
TX_Buffer_Empty => tx_Buffer_Empty
);
end architecture RTL;
|
mit
|
96d217f17ce74c24afdbbe4a097d3a07
| 0.402683 | 4.835895 | false | false | false | false |
luebbers/reconos
|
tests/automated/memcopy/hw/hwthreads/memcopy/hwt_memcopy.vhd
| 1 | 5,276 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
entity hwt_memcopy is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector( 0 to C_BURST_AWIDTH-1 );
o_RAMData : out std_logic_vector( 0 to C_BURST_DWIDTH-1 );
i_RAMData : in std_logic_vector( 0 to C_BURST_DWIDTH-1 );
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end entity;
architecture Behavioral of hwt_memcopy is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
--constant C_MBOX : std_logic_vector(31 downto 0) := X"00000000"; -- debug
type t_state is ( STATE_INIT,
--STATE_SEND_INIT_DATA, -- debug
STATE_READ_SRC,
STATE_READ_DST,
STATE_READ_SIZE,
--STATE_SEND_SRC, -- debug
--STATE_SEND_DST, -- debug
--STATE_SEND_SIZE, -- debug
STATE_READ_BURST,
STATE_WRITE_BURST,
STATE_READ_WORD,
STATE_WRITE_WORD,
STATE_DONE,
--STATE_SEND_DONE, -- debug
STATE_FINAL);
signal state : t_state;
begin
state_proc: process( clk, reset )
variable args : std_logic_vector(31 downto 0);
variable src : std_logic_vector(31 downto 0);
variable dst : std_logic_vector(31 downto 0);
variable size : std_logic_vector(31 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable done : boolean;
variable success : boolean;
begin
if reset = '1' then
reconos_reset( o_osif, i_osif );
state <= STATE_INIT;
args := (others => '0');
src := (others => '0');
dst := (others => '0');
size := (others => '0');
tmp := (others => '0');
done := false;
success := false;
elsif rising_edge( clk ) then
reconos_begin( o_osif, i_osif );
if reconos_ready( i_osif ) then
case state is
when STATE_INIT =>
reconos_get_init_data(done, o_osif, i_osif, args);
if done then state <= STATE_READ_SRC; end if;
-- if done then state <= STATE_SEND_INIT_DATA; end if; -- debug
--------------------------------------------
-- when STATE_SEND_INIT_DATA =>
-- reconos_mbox_put(done,success,o_osif,i_osif,C_MBOX, args);
-- if done then state <= STATE_READ_SRC; end if;
--------------------------------------------
when STATE_READ_SRC =>
reconos_read(done, o_osif, i_osif, args, src);
if done then state <= STATE_READ_DST; end if;
when STATE_READ_DST =>
reconos_read(done, o_osif, i_osif, args + 4, dst);
if done then state <= STATE_READ_SIZE; end if;
when STATE_READ_SIZE =>
reconos_read(done, o_osif, i_osif, args + 8, size);
if done then state <= STATE_READ_BURST; end if;
-- if done then state <= STATE_SEND_SRC; end if;
----------------------------------------
-- when STATE_SEND_SRC =>
-- reconos_mbox_put(done,success,o_osif,i_osif,C_MBOX, src);
-- if done then state <= STATE_SEND_DST; end if;
-- when STATE_SEND_DST =>
-- reconos_mbox_put(done,success,o_osif,i_osif,C_MBOX, dst);
-- if done then state <= STATE_SEND_SIZE; end if;
-- when STATE_SEND_SIZE =>
-- reconos_mbox_put(done,success,o_osif,i_osif,C_MBOX, size);
-- if done then state <= STATE_READ_BURST; end if;
----------------------------------------
when STATE_READ_BURST =>
if (size >= 128) and (src(2 downto 0) = B"000") then
reconos_read_burst (done, o_osif, i_osif, X"00000000", src);
if done then
state <= STATE_WRITE_BURST;
src := src + 128;
end if;
else
state <= STATE_READ_WORD;
end if;
when STATE_WRITE_BURST =>
reconos_write_burst (done, o_osif, i_osif, X"00000000", dst);
if done then
state <= STATE_READ_BURST;
-- state <= STATE_SEND_SRC; -- debug
dst := dst + 128;
size := size - 128;
end if;
when STATE_READ_WORD =>
if size > 0 then
reconos_read(done, o_osif, i_osif, src, tmp);
if done then
state <= STATE_WRITE_WORD;
src := src + 4;
end if;
else
state <= STATE_DONE;
end if;
when STATE_WRITE_WORD =>
reconos_write(done, o_osif, i_osif, dst, tmp);
if done then
state <= STATE_READ_BURST;
-- state <= STATE_SEND_SRC; -- debug
dst := dst + 4;
size := size - 4;
end if;
when STATE_DONE =>
reconos_write(done, o_osif, i_osif, args + 8, X"00000000");
state <= STATE_FINAL;
-- state <= STATE_SEND_DONE; -- debug
--------------------------------------------
-- when STATE_SEND_DONE =>
-- reconos_mbox_put(done,success,o_osif,i_osif,C_MBOX, X"0112358D");
-- if done then state <= STATE_FINAL; end if;
--------------------------------------------
when STATE_FINAL =>
state <= STATE_FINAL;
end case;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
8a61021b6a6f9df489ffd5381853e30e
| 0.546626 | 3.155502 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/DRAM/DRAM_macro.vhd
| 1 | 42,836 |
---------------------------------------------------------------------------
--
-- Module : DRAM_macro.vhd
--
-- Version : 1.2
--
-- Last Update : 2005-06-29
--
-- Project : Parameterizable LocalLink FIFO
--
-- Description : Distributed RAM Macro
--
-- Designer : Wen Ying Wei, Davy Huang
--
-- Company : Xilinx, Inc.
--
-- Disclaimer : XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2005 Xilinx, Inc.
-- All rights reserved.
--
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_bit.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.fifo_u.all;
use work.DRAM_fifo_pkg.all;
entity DRAM_macro is
generic (
DRAM_DEPTH : integer := 16; -- FIFO depth, default is 16,
-- allowable values are 16, 32,
-- 64, 128.
WR_DWIDTH : integer := 32; --FIFO write data width.
--Allowed: 8, 16, 32, 64
RD_DWIDTH : integer := 32; --FIFO read data width.
--Allowed: 8, 16, 32, 64
WR_REM_WIDTH : integer := 2; --log2(WR_DWIDTH/8)
RD_REM_WIDTH : integer := 2; --log2(RD_DWIDTH/8)
RD_ADDR_MINOR_WIDTH : integer := 1;
RD_ADDR_WIDTH : integer := 9;
WR_ADDR_MINOR_WIDTH : integer := 1;
WR_ADDR_WIDTH : integer := 9;
CTRL_WIDTH: integer := 3;
glbtm : time := 1 ns );
port (
-- Reset
fifo_gsr: in std_logic;
-- clocks
wr_clk: in std_logic;
rd_clk: in std_logic;
rd_allow: in std_logic;
rd_allow_minor: in std_logic;
rd_addr: in std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
rd_addr_minor: in std_logic_vector(RD_ADDR_MINOR_WIDTH-1 downto 0);
rd_data: out std_logic_vector(RD_DWIDTH -1 downto 0);
rd_rem: out std_logic_vector(RD_REM_WIDTH-1 downto 0);
rd_sof_n: out std_logic;
rd_eof_n: out std_logic;
wr_allow: in std_logic;
wr_allow_minor: in std_logic;
wr_allow_minor_p: in std_logic;
wr_addr: in std_logic_vector(WR_ADDR_WIDTH-1 downto 0);
wr_addr_minor: in std_logic_vector(WR_ADDR_MINOR_WIDTH-1 downto 0);
wr_data: in std_logic_vector(WR_DWIDTH-1 downto 0);
wr_rem: in std_logic_vector(WR_REM_WIDTH-1 downto 0);
wr_sof_n: in std_logic;
wr_eof_n: in std_logic;
wr_sof_n_p: in std_logic;
wr_eof_n_p: in std_logic;
ctrl_wr_buf: out std_logic_vector(CTRL_WIDTH-1 downto 0)
);
end DRAM_macro;
architecture DRAM_macro_hdl of DRAM_macro is
-- Constants Related to FIFO Width parameters for Data
constant MEM_IDX : integer := SQUARE2(DRAM_DEPTH);
constant MAX_WIDTH: integer := GET_MAX_WIDTH(RD_DWIDTH, WR_DWIDTH);
constant WRDW_div_RDDW: integer := GET_WRDW_div_RDDW(RD_DWIDTH, WR_DWIDTH);
--Constants Related to FIFO Width parameters for Control
constant REM_SEL_HIGH_VALUE : integer := GET_HIGH_VALUE(RD_REM_WIDTH,WR_REM_WIDTH);
type rd_data_vec_type is array(0 to 2**RD_ADDR_MINOR_WIDTH-1) of std_logic_vector(RD_DWIDTH-1 downto 0);
type rd_rem_vec_type is array(0 to 2**RD_ADDR_MINOR_WIDTH-1) of std_logic_vector(RD_REM_WIDTH-1 downto 0);
constant RD_MINOR_HIGH : integer := POWER2(RD_ADDR_MINOR_WIDTH);
constant REM_SEL_HIGH1 : integer := POWER2(REM_SEL_HIGH_VALUE);
constant WR_MINOR_HIGH : integer := POWER2(WR_ADDR_MINOR_WIDTH);
constant LEN_IFACE_SIZE: integer := 16; -- Length count is a std_logic_vec
-- of 16 bits by default.
-- User may change size.
constant LEN_COUNT_SIZE: integer := 14;
-- length control constants
constant LEN_BYTE_RATIO: integer := WR_DWIDTH/8;
signal rd_en: std_logic;
signal wr_en: std_logic;
-- Control RAM signals --
signal rd_rem_p: rd_rem_vec_type;
signal rd_sof_n_p: std_logic_vector(RD_MINOR_HIGH-1 downto 0);
signal rd_eof_n_p: std_logic_vector(RD_MINOR_HIGH-1 downto 0);
signal ctrl_rd_buf: std_logic_vector(CTRL_WIDTH-1 downto 0);
signal ctrl_wr_buf_i: std_logic_vector(CTRL_WIDTH-1 downto 0);
signal ctrl_rd_temp: std_logic_vector(CTRL_WIDTH-1 downto 0);
signal ctrl_rd_buf_p: std_logic_vector((RD_REM_WIDTH+2)*(WRDW_div_RDDW)-1 downto 0);
-------------------------
-- Temp signals --
signal rd_temp: std_logic_vector(MAX_WIDTH-1 downto 0);
signal rd_buf: std_logic_vector(MAX_WIDTH-1 downto 0);
signal rd_data_p: rd_data_vec_type;
signal wr_buf: std_logic_vector(MAX_WIDTH-1 downto 0);
signal min_addr1: integer := 0;
signal min_addr2: integer := 0;
signal rem_sel1 : integer := 0;
signal rem_sel2: integer := 0;
signal gnd: std_logic;
signal pwr: std_logic;
begin
----------------------------------------------------------------------------------
-- SOF, EOF, REM mapping
----------------------------------------------------------------------------------
rd_switch_gen1: if (WR_DWIDTH > RD_DWIDTH) generate
min_addr1 <= slv2int(rd_addr_minor);
-- Data mapping --
rd_gen: for i in 0 to RD_MINOR_HIGH-1 generate
rd_data_p(i) <= rd_buf(i * RD_DWIDTH + RD_DWIDTH - 1 downto i * RD_DWIDTH);
rd_rem_p(i) <= ctrl_rd_buf_p(i*(2+RD_REM_WIDTH) + RD_REM_WIDTH-1 downto i*(2+RD_REM_WIDTH));
rd_sof_n_p(i) <= ctrl_rd_buf_p(i*(2+RD_REM_WIDTH) + RD_REM_WIDTH);
rd_eof_n_p(i) <= ctrl_rd_buf_p(i*(2+RD_REM_WIDTH) + RD_REM_WIDTH+1);
end generate rd_gen;
ctrl_gen1a: if RD_DWIDTH /= 8 generate -- if read data width is 8 then there is no rem signal
-- SOF mapping
ctrl_rd_buf_p(RD_REM_WIDTH) <= '0' when ctrl_rd_buf(WR_REM_WIDTH) = '0' else '1';
sof_gen_for: for k in 1 to REM_SEL_HIGH1-1 generate
ctrl_rd_buf_p(k*(2+RD_REM_WIDTH)+RD_REM_WIDTH) <= '1';
end generate sof_gen_for;
rem_sel1 <= slv2int(ctrl_rd_buf(WR_REM_WIDTH-1 downto RD_REM_WIDTH));
ctrl_gen1b: if RD_DWIDTH = 16 generate
-- REM mapping
rem_gen_for1: for i in 0 to REM_SEL_HIGH1-1 generate
ctrl_rd_buf_p(i*(2+RD_REM_WIDTH)) <= ctrl_rd_buf(0) when rem_sel1 = i else '0'; --rem
end generate rem_gen_for1;
-- EOF mapping
eof_gen_for1: for j in 0 to REM_SEL_HIGH1-1 generate
ctrl_rd_buf_p(j*(2+RD_REM_WIDTH)+2) <= ctrl_rd_buf(WR_REM_WIDTH +1) when rem_sel1 = j else '1';
end generate eof_gen_for1;
end generate ctrl_gen1b;
rem_gen1c: if RD_DWIDTH > 16 generate
-- REM mapping
rem_gen_for2: for i in 0 to REM_SEL_HIGH1-1 generate
ctrl_rd_buf_p(i*(2+RD_REM_WIDTH)+RD_REM_WIDTH-1 downto i*(2+RD_REM_WIDTH)) <= ctrl_rd_buf(RD_REM_WIDTH-1 downto 0) when
rem_sel1 = i else (others => 'X') ;
end generate rem_gen_for2;
-- EOF mapping
eof_gen_for2: for j in 0 to REM_SEL_HIGH1-1 generate
ctrl_rd_buf_p(j*(2+RD_REM_WIDTH)+RD_REM_WIDTH+1) <= ctrl_rd_buf(WR_REM_WIDTH+1) when rem_sel1 = j else '1';
end generate eof_gen_for2;
end generate rem_gen1c;
end generate ctrl_gen1a;
ctrl_gen1b: if RD_DWIDTH = 8 generate
-- SOF mapping
ctrl_rd_buf_p(RD_REM_WIDTH) <= '0' when ctrl_rd_buf(WR_REM_WIDTH) = '0' else '1';
sof_gen_for: for k in 1 to WR_DWIDTH/RD_DWIDTH-1 generate
ctrl_rd_buf_p(k*(2+RD_REM_WIDTH)+RD_REM_WIDTH) <= '1';
end generate sof_gen_for;
rem_sel2 <= slv2int(ctrl_rd_buf(WR_REM_WIDTH-1 downto 0));
eof_gen_for2: for k in 0 to WR_DWIDTH/RD_DWIDTH-1 generate
ctrl_rd_buf_p(k*(2+RD_REM_WIDTH)+2) <= ctrl_rd_buf(WR_REM_WIDTH+1) when rem_sel2 = k else '1';
end generate eof_gen_for2;
end generate ctrl_gen1b;
rd_rem_gen0: if RD_DWIDTH = 8 generate
rd_process1: process (rd_clk, fifo_gsr)
begin
rd_rem <= (others => '0');
if (fifo_gsr = '1') then
rd_data <= (others => '0');
rd_sof_n <= '1';
rd_eof_n <= '1';
elsif rd_clk'EVENT and rd_clk = '1' then
if rd_allow_minor = '1' then
rd_data <= rd_data_p(min_addr1) after glbtm;
rd_sof_n <= rd_sof_n_p(min_addr1) after glbtm;
rd_eof_n <= rd_eof_n_p(min_addr1) after glbtm;
end if;
end if;
end process rd_process1;
end generate;
rd_rem_gen1: if RD_DWIDTH /= 8 generate
rd_process1: process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
rd_data <= (others => '0');
rd_rem <= (others => '0');
rd_sof_n <= '1';
rd_eof_n <= '1';
elsif rd_clk'EVENT and rd_clk = '1' then
if rd_allow_minor = '1' then
rd_data <= rd_data_p(min_addr1) after glbtm;
rd_rem <= rd_rem_p(min_addr1) after glbtm;
rd_sof_n <= rd_sof_n_p(min_addr1) after glbtm;
rd_eof_n <= rd_eof_n_p(min_addr1) after glbtm;
end if;
end if;
end process rd_process1;
end generate;
end generate rd_switch_gen1;
rd_switch_gen2: if (WR_DWIDTH <= RD_DWIDTH) generate
rd_rem_gen0: if RD_DWIDTH = 8 generate
rd_process2: process (rd_clk, fifo_gsr)
begin
rd_rem <= (others => '0');
if (fifo_gsr = '1') then
rd_data <= (others => '0');
rd_sof_n <= '1';
rd_eof_n <= '1';
elsif rd_clk'EVENT and rd_clk = '1' then
if rd_allow = '1' then
rd_data <= rd_buf after glbtm;
rd_sof_n <= ctrl_rd_buf(RD_REM_WIDTH) after glbtm;
rd_eof_n <= ctrl_rd_buf(RD_REM_WIDTH+1) after glbtm;
end if;
end if;
end process rd_process2;
end generate;
rd_rem_gen1: if RD_DWIDTH /= 8 generate
rd_process2: process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
rd_data <= (others => '0');
rd_rem <= (others => '0');
rd_sof_n <= '1';
rd_eof_n <= '1';
elsif rd_clk'EVENT and rd_clk = '1' then
if rd_allow = '1' then
rd_data <= rd_buf after glbtm;
rd_rem <= ctrl_rd_buf(RD_REM_WIDTH-1 downto 0) after glbtm;
rd_sof_n <= ctrl_rd_buf(RD_REM_WIDTH) after glbtm;
rd_eof_n <= ctrl_rd_buf(RD_REM_WIDTH+1) after glbtm;
end if;
end if;
end process rd_process2;
end generate;
end generate rd_switch_gen2;
-------------------------------------------------------------------------------
-- The write format is as follows: for WR_DWIDTH <= RD_DWIDTH
-- wr_data_1 + wr_data_2 + ... + wr_data_n --> wr_buf --> DRAM
-- wr_buf:
--
-- MSB LSB
-- ___________ ___________ __________
-- | wr_data_n |--- | wr_data_2 |wr_data_1 |
-- ----------- ----------- ----------
--
-- wr_sof_n + wr_eof_n + wr_rem --> ctrl_wr_buf_i --> DRAM
-- ctrl_wr_buf_i:
--
-- MSB LSB
-- _______ _______ _____
-- | eof_n | sof_n | rem |
-- ------- ------- -----
-------------------------------------------------------------------------------
wr_switch_gen1: if WR_DWIDTH < RD_DWIDTH generate
min_addr2 <= slv2int(wr_addr_minor);
data_proc: process (wr_clk, fifo_gsr)
begin
if fifo_gsr = '1' then
wr_buf <= (others => '0');
ctrl_wr_buf_i <= (others => '0');
elsif wr_clk'EVENT and wr_clk = '1' then
if wr_allow_minor = '1' then
wr_buf(min_addr2 * WR_DWIDTH + WR_DWIDTH -1 downto min_addr2 * WR_DWIDTH) <= wr_data after glbtm;
-- SOF
if min_addr2 = 0 then
ctrl_wr_buf_i(RD_REM_WIDTH) <= wr_sof_n after glbtm;
end if;
-- EOF
ctrl_wr_buf_i(RD_REM_WIDTH+1) <= wr_eof_n after glbtm;
-- REM
if wr_eof_n = '0' then
if WR_DWIDTH = 8 then
ctrl_wr_buf_i(RD_REM_WIDTH-1 downto 0) <= wr_addr_minor after glbtm;
else
ctrl_wr_buf_i(RD_REM_WIDTH-1 downto 0) <= wr_addr_minor & wr_rem after glbtm;
end if;
end if;
end if;
end if;
end process data_proc;
end generate wr_switch_gen1;
wr_switch_gen2:if (WR_DWIDTH >= RD_DWIDTH) generate
wr_buf <= wr_data;
ctrl_wr_buf_i(WR_REM_WIDTH-1 downto 0) <= wr_rem;
ctrl_wr_buf_i(WR_REM_WIDTH) <= wr_sof_n;
ctrl_wr_buf_i(WR_REM_WIDTH + 1) <= wr_eof_n;
end generate wr_switch_gen2;
ctrl_wr_buf <= ctrl_wr_buf_i;
-------------------------------------------------------------------------------
----------------------Distributed SelectRAM port mapping-----------------------
-- It uses up to 512 deep RAM, in which 64 and lower are horizontally --
-- cascaded primitives and 128 and up are macro of 64 deep RAM. --
-------------------------------------------------------------------------------
DRAMgen1: if DRAM_DEPTH = 16 generate
begin
gen11: if WR_DWIDTH > RD_DWIDTH generate
-- Data RAM --
DRAM11gen: for i in 0 to WR_DWIDTH-1 generate
D_RAM1: RAM16X1D port map (
D => wr_buf(i),
WE => wr_allow,
WCLK => wr_clk,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPO => rd_buf(i),
SPO => rd_temp(i));
end generate DRAM11gen;
-- LL Control RAM --
DRAM11agen: for i in 0 to CTRL_WIDTH-1 generate
D_RAM1: RAM16X1D port map (
D => ctrl_wr_buf_i(i),
WE => wr_allow,
WCLK => wr_clk,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPO => ctrl_rd_buf(i),
SPO => ctrl_rd_temp(i));
end generate DRAM11agen;
end generate gen11;
gen12: if WR_DWIDTH < RD_DWIDTH generate
-- Data RAM --
DRAM12gen: for i in 0 to RD_DWIDTH-1 generate
D_RAM1: RAM16X1D port map (
D => wr_buf(i),
WE => wr_allow,
WCLK => wr_clk,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPO => rd_buf(i),
SPO => rd_temp(i));
end generate DRAM12gen;
-- Control RAM --
DRAM12agen: for i in 0 to CTRL_WIDTH-1 generate
D_RAM1: RAM16X1D port map (
D => ctrl_wr_buf_i(i),
WE => wr_allow,
WCLK => wr_clk,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPO => ctrl_rd_buf(i),
SPO => ctrl_rd_temp(i));
end generate DRAM12agen;
end generate gen12;
gen13: if WR_DWIDTH = RD_DWIDTH generate
-- Data RAM --
DRAM13gen: for i in 0 to WR_DWIDTH-1 generate
D_RAM1: RAM16X1D port map (
D => wr_buf(i),
WE => wr_allow,
WCLK => wr_clk,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPO => rd_buf(i),
SPO => rd_temp(i));
end generate DRAM13gen;
-- Control RAM --
DRAM13agen: for i in 0 to CTRL_WIDTH-1 generate
D_RAM1: RAM16X1D port map (
D => ctrl_wr_buf_i(i),
WE => wr_allow,
WCLK => wr_clk,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPO => ctrl_rd_buf(i),
SPO => ctrl_rd_temp(i));
end generate DRAM13agen;
end generate gen13;
end generate DRAMgen1;
DRAMgen2: if DRAM_DEPTH = 32 generate
begin
gen21: if WR_DWIDTH > RD_DWIDTH generate
-- Data RAM --
DRAM21gen: for i in 0 to WR_DWIDTH-1 generate
D_RAM1: RAM32X1D port map (
D => wr_buf(i),
WE => wr_allow,
WCLK => wr_clk,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
A4 => wr_addr(4),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPRA4 => rd_addr(4),
DPO => rd_buf(i),
SPO => rd_temp(i));
end generate DRAM21gen;
-- Control RAM --
DRAM21agen: for i in 0 to CTRL_WIDTH-1 generate
D_RAM1: RAM32X1D port map (
D => ctrl_wr_buf_i(i),
WE => wr_allow,
WCLK => wr_clk,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
A4 => wr_addr(4),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPRA4 => rd_addr(4),
DPO => ctrl_rd_buf(i),
SPO => ctrl_rd_temp(i));
end generate DRAM21agen;
end generate gen21;
gen22: if WR_DWIDTH < RD_DWIDTH generate
-- Data RAM --
DRAM22gen: for i in 0 to RD_DWIDTH-1 generate
D_RAM1: RAM32X1D port map (
D => wr_buf(i),
WE => wr_allow,
WCLK => wr_clk,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
A4 => wr_addr(4),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPRA4 => rd_addr(4),
DPO => rd_buf(i),
SPO => rd_temp(i));
end generate DRAM22gen;
-- Controal FIFO --
DRAM22agen: for i in 0 to CTRL_WIDTH-1 generate
D_RAM1: RAM32X1D port map (
D => ctrl_wr_buf_i(i),
WE => wr_allow,
WCLK => wr_clk,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
A4 => wr_addr(4),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPRA4 => rd_addr(4),
DPO => ctrl_rd_buf(i),
SPO => ctrl_rd_temp(i));
end generate DRAM22agen;
end generate gen22;
gen23: if WR_DWIDTH = RD_DWIDTH generate
-- Data RAM --
DRAM23gen: for i in 0 to WR_DWIDTH-1 generate
D_RAM1: RAM32X1D port map (
D => wr_buf(i),
WE => wr_allow,
WCLK => wr_clk,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
A4 => wr_addr(4),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPRA4 => rd_addr(4),
DPO => rd_buf(i),
SPO => rd_temp(i));
end generate DRAM23gen;
-- Control RAM --
DRAM23agen: for i in 0 to CTRL_WIDTH-1 generate
D_RAM1: RAM32X1D port map (
D => ctrl_wr_buf_i(i),
WE => wr_allow,
WCLK => wr_clk,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
A4 => wr_addr(4),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPRA4 => rd_addr(4),
DPO => ctrl_rd_buf(i),
SPO => ctrl_rd_temp(i));
end generate DRAM23agen;
end generate gen23;
end generate DRAMgen2;
DRAMgen3: if DRAM_DEPTH = 64 generate
begin
gen31: if WR_DWIDTH > RD_DWIDTH generate
-- Data RAM --
DRAM31gen: for i in 0 to WR_DWIDTH-1 generate
D_RAM1: RAM64X1D port map (
D => wr_buf(i),
WE => wr_allow,
WCLK => wr_clk,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
A4 => wr_addr(4),
A5 => wr_addr(5),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPRA4 => rd_addr(4),
DPRA5 => rd_addr(5),
DPO => rd_buf(i),
SPO => rd_temp(i));
end generate DRAM31gen;
-- Control RAM --
DRAM31agen: for i in 0 to CTRL_WIDTH-1 generate
D_RAM1: RAM64X1D port map (
D => ctrl_wr_buf_i(i),
WE => wr_allow,
WCLK => wr_clk,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
A4 => wr_addr(4),
A5 => wr_addr(5),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPRA4 => rd_addr(4),
DPRA5 => rd_addr(5),
DPO => ctrl_rd_buf(i),
SPO => ctrl_rd_temp(i));
end generate DRAM31agen;
end generate gen31;
gen32: if WR_DWIDTH < RD_DWIDTH generate
-- Data RAM --
DRAM32gen: for i in 0 to RD_DWIDTH-1 generate
D_RAM1: RAM64X1D port map (
D => wr_buf(i),
WE => wr_allow,
WCLK => wr_clk,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
A4 => wr_addr(4),
A5 => wr_addr(5),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPRA4 => rd_addr(4),
DPRA5 => rd_addr(5),
DPO => rd_buf(i),
SPO => rd_temp(i));
end generate DRAM32gen;
-- Control RAM --
DRAM32agen: for i in 0 to CTRL_WIDTH-1 generate
D_RAM1: RAM64X1D port map (
D => ctrl_wr_buf_i(i),
WE => wr_allow,
WCLK => wr_clk,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
A4 => wr_addr(4),
A5 => wr_addr(5),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPRA4 => rd_addr(4),
DPRA5 => rd_addr(5),
DPO => ctrl_rd_buf(i),
SPO => ctrl_rd_temp(i));
end generate DRAM32agen;
end generate gen32;
gen33: if WR_DWIDTH = RD_DWIDTH generate
-- Data RAM --
DRAM33gen: for i in 0 to WR_DWIDTH-1 generate
D_RAM1: RAM64X1D port map (
D => wr_buf(i),
WE => wr_allow,
WCLK => wr_clk,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
A4 => wr_addr(4),
A5 => wr_addr(5),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPRA4 => rd_addr(4),
DPRA5 => rd_addr(5),
DPO => rd_buf(i),
SPO => rd_temp(i));
end generate DRAM33gen;
-- Control RAM --
DRAM33agen: for i in 0 to CTRL_WIDTH-1 generate
D_RAM1: RAM64X1D port map (
D => ctrl_wr_buf_i(i),
WE => wr_allow,
WCLK => wr_clk,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
A4 => wr_addr(4),
A5 => wr_addr(5),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPRA4 => rd_addr(4),
DPRA5 => rd_addr(5),
DPO => ctrl_rd_buf(i),
SPO => ctrl_rd_temp(i));
end generate DRAM33agen;
end generate gen33;
end generate DRAMgen3;
DRAMgen4: if DRAM_DEPTH = 128 generate
begin
gen41: if WR_DWIDTH > RD_DWIDTH generate
-- Data RAM --
DRAM41gen: for i in 0 to WR_DWIDTH-1 generate
D_RAM1: RAM_64nX1
generic map(2, 7)
port map (
DI => wr_buf(i),
WEn => wr_allow,
WCLK => wr_clk,
Ad => wr_addr(6 downto 0),
DRA => rd_addr(6 downto 0),
DO => rd_buf(i),
SO => rd_temp(i));
end generate DRAM41gen;
-- Control RAM --
DRAM41agen: for i in 0 to CTRL_WIDTH-1 generate
D_RAM1: RAM_64nX1
generic map(2, 7)
port map (
DI => ctrl_wr_buf_i(i),
WEn => wr_allow,
WCLK => wr_clk,
Ad => wr_addr(6 downto 0),
DRA => rd_addr(6 downto 0),
DO => ctrl_rd_buf(i),
SO => ctrl_rd_temp(i));
end generate DRAM41agen;
end generate gen41;
gen42: if WR_DWIDTH < RD_DWIDTH generate
-- Data RAM --
DRAM42gen: for i in 0 to RD_DWIDTH-1 generate
D_RAM1: RAM_64nX1
generic map(2, 7)
port map (
DI => wr_buf(i),
WEn => wr_allow,
WCLK => wr_clk,
Ad => wr_addr(6 downto 0),
DRA => rd_addr(6 downto 0),
DO => rd_buf(i),
SO => rd_temp(i));
end generate DRAM42gen;
-- Control RAM --
DRAM42agen: for i in 0 to CTRL_WIDTH-1 generate
D_RAM1: RAM_64nX1
generic map(2, 7)
port map (
DI => ctrl_wr_buf_i(i),
WEn => wr_allow,
WCLK => wr_clk,
Ad => wr_addr(6 downto 0),
DRA => rd_addr(6 downto 0),
DO => ctrl_rd_buf(i),
SO => ctrl_rd_temp(i));
end generate DRAM42agen;
end generate gen42;
gen43: if WR_DWIDTH = RD_DWIDTH generate
-- Data RAM --
DRAM43gen: for i in 0 to WR_DWIDTH-1 generate
D_RAM1: RAM_64nX1
generic map(2, 7)
port map (
DI => wr_buf(i),
WEn => wr_allow,
WCLK => wr_clk,
Ad => wr_addr(6 downto 0),
DRA => rd_addr(6 downto 0),
DO => rd_buf(i),
SO => rd_temp(i));
end generate DRAM43gen;
-- Control RAM --
DRAM43agen: for i in 0 to CTRL_WIDTH-1 generate
D_RAM1: RAM_64nX1
generic map(2, 7)
port map (
DI => ctrl_wr_buf_i(i),
WEn => wr_allow,
WCLK => wr_clk,
Ad => wr_addr(6 downto 0),
DRA => rd_addr(6 downto 0),
DO => ctrl_rd_buf(i),
SO => ctrl_rd_temp(i));
end generate DRAM43agen;
end generate gen43;
end generate DRAMgen4;
DRAMgen5: if DRAM_DEPTH = 256 generate
begin
gen51: if WR_DWIDTH > RD_DWIDTH generate
-- Data RAM --
DRAM51gen: for i in 0 to WR_DWIDTH-1 generate
D_RAM1: RAM_64nX1
generic map(4, 8)
port map (
DI => wr_buf(i),
WEn => wr_allow,
WCLK => wr_clk,
Ad => wr_addr(7 downto 0),
DRA => rd_addr(7 downto 0),
DO => rd_buf(i),
SO => rd_temp(i));
end generate DRAM51gen;
-- Control RAM --
DRAM51agen: for i in 0 to CTRL_WIDTH-1 generate
D_RAM1: RAM_64nX1
generic map(4, 8)
port map (
DI => ctrl_wr_buf_i(i),
WEn => wr_allow,
WCLK => wr_clk,
Ad => wr_addr(7 downto 0),
DRA => rd_addr(7 downto 0),
DO => ctrl_rd_buf(i),
SO => ctrl_rd_temp(i));
end generate DRAM51agen;
end generate gen51;
gen52: if WR_DWIDTH < RD_DWIDTH generate
-- Data RAM --
DRAM52gen: for i in 0 to RD_DWIDTH-1 generate
D_RAM1: RAM_64nX1
generic map(4, 8)
port map (
DI => wr_buf(i),
WEn => wr_allow,
WCLK => wr_clk,
Ad => wr_addr(7 downto 0),
DRA => rd_addr(7 downto 0),
DO => rd_buf(i),
SO => rd_temp(i));
end generate DRAM52gen;
-- Control RAM --
DRAM52agen: for i in 0 to CTRL_WIDTH-1 generate
D_RAM1: RAM_64nX1
generic map(4, 8)
port map (
DI => ctrl_wr_buf_i(i),
WEn => wr_allow,
WCLK => wr_clk,
Ad => wr_addr(7 downto 0),
DRA => rd_addr(7 downto 0),
DO => ctrl_rd_buf(i),
SO => ctrl_rd_temp(i));
end generate DRAM52agen;
end generate gen52;
gen53: if WR_DWIDTH = RD_DWIDTH generate
-- Data RAM --
DRAM53gen: for i in 0 to WR_DWIDTH-1 generate
D_RAM1: RAM_64nX1
generic map(4, 8)
port map (
DI => wr_buf(i),
WEn => wr_allow,
WCLK => wr_clk,
Ad => wr_addr(7 downto 0),
DRA => rd_addr(7 downto 0),
DO => rd_buf(i),
SO => rd_temp(i));
end generate DRAM53gen;
-- Control RAM --
DRAM53agen: for i in 0 to CTRL_WIDTH-1 generate
D_RAM1: RAM_64nX1
generic map(4, 8)
port map (
DI => ctrl_wr_buf_i(i),
WEn => wr_allow,
WCLK => wr_clk,
Ad => wr_addr(7 downto 0),
DRA => rd_addr(7 downto 0),
DO => ctrl_rd_buf(i),
SO => ctrl_rd_temp(i));
end generate DRAM53agen;
end generate gen53;
end generate DRAMgen5;
DRAMgen6: if DRAM_DEPTH = 512 generate
begin
gen61: if WR_DWIDTH > RD_DWIDTH generate
-- Data RAM --
DRAM61gen: for i in 0 to WR_DWIDTH-1 generate
D_RAM1: RAM_64nX1
generic map(8, 9)
port map (
DI => wr_buf(i),
WEn => wr_allow,
WCLK => wr_clk,
Ad => wr_addr(8 downto 0),
DRA => rd_addr(8 downto 0),
DO => rd_buf(i),
SO => rd_temp(i));
end generate DRAM61gen;
-- Control RAM --
DRAM61agen: for i in 0 to CTRL_WIDTH-1 generate
D_RAM1: RAM_64nX1
generic map(8, 9)
port map (
DI => ctrl_wr_buf_i(i),
WEn => wr_allow,
WCLK => wr_clk,
Ad => wr_addr(8 downto 0),
DRA => rd_addr(8 downto 0),
DO => ctrl_rd_buf(i),
SO => ctrl_rd_temp(i));
end generate DRAM61agen;
end generate gen61;
gen62: if WR_DWIDTH < RD_DWIDTH generate
-- Data RAM --
DRAM62gen: for i in 0 to RD_DWIDTH-1 generate
D_RAM1: RAM_64nX1
generic map(8, 9)
port map (
DI => wr_buf(i),
WEn => wr_allow,
WCLK => wr_clk,
Ad => wr_addr(8 downto 0),
DRA => rd_addr(8 downto 0),
DO => rd_buf(i),
SO => rd_temp(i));
end generate DRAM62gen;
-- Control RAM --
DRAM62agen: for i in 0 to CTRL_WIDTH-1 generate
D_RAM1: RAM_64nX1
generic map(8, 9)
port map (
DI => ctrl_wr_buf_i(i),
WEn => wr_allow,
WCLK => wr_clk,
Ad => wr_addr(8 downto 0),
DRA => rd_addr(8 downto 0),
DO => ctrl_rd_buf(i),
SO => ctrl_rd_temp(i));
end generate DRAM62agen;
end generate gen62;
gen63: if WR_DWIDTH = RD_DWIDTH generate
-- Data RAM --
DRAM63gen: for i in 0 to WR_DWIDTH-1 generate
D_RAM1: RAM_64nX1
generic map(8, 9)
port map (
DI => wr_buf(i),
WEn => wr_allow,
WCLK => wr_clk,
Ad => wr_addr(8 downto 0),
DRA => rd_addr(8 downto 0),
DO => rd_buf(i),
SO => rd_temp(i));
end generate DRAM63gen;
-- Control RAM --
DRAM63agen: for i in 0 to CTRL_WIDTH-1 generate
D_RAM1: RAM_64nX1
generic map(8, 9)
port map (
DI => ctrl_wr_buf_i(i),
WEn => wr_allow,
WCLK => wr_clk,
Ad => wr_addr(8 downto 0),
DRA => rd_addr(8 downto 0),
DO => ctrl_rd_buf(i),
SO => ctrl_rd_temp(i));
end generate DRAM63agen;
end generate gen63;
end generate DRAMgen6;
end DRAM_macro_hdl;
|
gpl-3.0
|
25af2e3ea0901c1127f974f4340d8018
| 0.379471 | 3.829087 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/first/first.vhd
| 1 | 11,930 |
--!
--! \file first.vhd
--!
--! \author Ariane Keller
--! \date 29.07.2009
-- Demo file for the multibus. This file will be executed in slot 1.
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity first is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32;
C_NR_SLOTS : integer := 3
);
port (
-- user defined signals: use the signal names defined in the system.ucf file!
-- user defined signals only work if they are before the reconos signals!
-- Signals for the Multibus
ready_0 : out std_logic;
req_0 : out std_logic_vector(0 to 3 -1);
grant_0 : in std_logic_vector(0 to 3 - 1);
data_0 : out std_logic_vector(0 to 3 * 32 - 1);
sof_0 : out std_logic_vector(0 to C_NR_SLOTS - 1);
eof_0 : out std_logic_vector(0 to C_NR_SLOTS - 1);
src_rdy_0 : out std_logic_vector(0 to C_NR_SLOTS - 1);
dst_rdy_0 : in std_logic_vector(0 to C_NR_SLOTS - 1);
busdata_0 : in std_logic_vector(0 to 32 - 1);
bussof_0 : in std_logic;
buseof_0 : in std_logic;
bus_dst_rdy_0 : out std_logic;
bus_src_rdy_0 : in std_logic;
--- end user defined ports
-- normal reconOS signals
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- second ram
o_RAMAddr_x : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData_x : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData_x : in std_logic_vector(0 to C_BURST_DWIDTH-1); -- 32 bit
o_RAMWE_x : out std_logic;
o_RAMClk_x : out std_logic
);
end first;
architecture Behavioral of first is
-------------
-- constants
------------
constant C_MBOX_HANDLE_SW_HW : std_logic_vector(0 to 31) := X"00000000";
constant C_MBOX_HANDLE_HW_SW : std_logic_vector(0 to 31) := X"00000001";
-----------------
-- state machines
-----------------
type os_state is ( STATE_INIT,
STATE_SEND_ANSWER,
STATE_GET_COMMAND,
STATE_DECODE);
signal os_sync_state : os_state := STATE_INIT;
type s_state is ( S_STATE_INIT,
S_STATE_WAIT,
S_STATE_LOCK,
S_STATE_SEND_FIRST,
S_STATE_INTERM);
signal send_to_0_state : s_state;
signal send_to_0_state_next : s_state;
signal send_to_1_state : s_state;
signal send_to_1_state_next : s_state;
signal send_to_2_state : s_state;
signal send_to_2_state_next : s_state;
type r_state is ( R_STATE_INIT,
R_STATE_COUNT);
signal receive_state : r_state;
signal receive_state_next : r_state;
---------------------
-- Signal declaration
---------------------
-- bus signals (for communication between hw threats
signal to_0_data : std_logic_vector(0 to 32 - 1);
signal to_1_data : std_logic_vector(0 to 32 - 1);
signal to_2_data : std_logic_vector(0 to 32 - 1);
signal to_0_sof : std_logic;
signal to_1_sof : std_logic;
signal to_2_sof : std_logic;
signal to_1_eof : std_logic;
signal to_2_eof : std_logic;
signal to_0_eof : std_logic;
signal received_counter : natural;
signal received_counter_next: natural;
signal start_to_0 : std_logic;
signal s_0_counter : natural;
signal s_0_counter_next : natural;
signal start_to_1 : std_logic;
signal s_1_counter : natural;
signal s_1_counter_next : natural;
signal start_to_2 : std_logic;
signal s_2_counter : natural;
signal s_2_counter_next : natural;
--end signal declaration
begin
--default assignements
-- we don't need the memories
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWE <= '0';
o_RAMClk <= '0';
o_RAMAddr_x <= (others => '0');
o_RAMData_x <= (others => '0');
o_RAMWE_x <= '0';
o_RAMClk_x <= '0';
data_0 <= to_0_data & to_1_data & to_2_data;
ready_0 <= '0'; -- unused?
-----------------
-- State machines
-----------------
receiving : process(busdata_0, bussof_0, buseof_0, bus_src_rdy_0,
receive_state, received_counter)
begin
bus_dst_rdy_0 <= '1';
receive_state_next <= receive_state;
received_counter_next <= received_counter;
case receive_state is
when R_STATE_INIT =>
received_counter_next <= 0;
receive_state_next <= R_STATE_COUNT;
when R_STATE_COUNT =>
if bussof_0 = '1' then
received_counter_next <= received_counter + 1;
end if;
end case;
end process;
send_to_0 : process(start_to_0, send_to_0_state, s_0_counter, grant_0)
begin
src_rdy_0(0) <= '0';
to_0_data <= (others => '0');
sof_0(0) <= '0';
eof_0(0) <= '0';
req_0(0) <= '0';
send_to_0_state_next <= send_to_0_state;
s_0_counter_next <= s_0_counter;
case send_to_0_state is
when S_STATE_INIT =>
send_to_0_state_next <= S_STATE_WAIT;
s_0_counter_next <= 0;
when S_STATE_WAIT =>
if start_to_0 = '1' then
send_to_0_state_next <= S_STATE_LOCK;
end if;
when S_STATE_LOCK =>
req_0(0) <= '1';--req has to be high as long as we send packets.
if grant_0(0) = '0' then
send_to_0_state_next <= S_STATE_LOCK;
else
send_to_0_state_next <= S_STATE_SEND_FIRST;
end if;
when S_STATE_SEND_FIRST =>
src_rdy_0(0) <= '1';
sof_0(0) <= '1';
to_0_data <= (others => '1');
s_0_counter_next <= s_0_counter + 1;
send_to_0_state_next <= S_STATE_INTERM;
req_0(0) <= '1';
when S_STATE_INTERM =>
req_0(0) <= '1';
src_rdy_0(0) <= '1';
to_0_data <= (others => '0');
if s_0_counter = 15 then
s_0_counter_next <= 0;
send_to_0_state_next <= S_STATE_WAIT;
eof_0(0) <= '1';
else
s_0_counter_next <= s_0_counter + 1;
end if;
when others =>
send_to_0_state_next <= S_STATE_INIT;
end case;
end process;
send_to_1 : process(start_to_1, send_to_1_state, s_1_counter, grant_0)
begin
src_rdy_0(1) <= '0';
to_1_data <= (others => '0');
sof_0(1) <= '0';
eof_0(1) <= '0';
req_0(1) <= '0';
send_to_1_state_next <= send_to_1_state;
s_1_counter_next <= s_1_counter;
case send_to_1_state is
when S_STATE_INIT =>
send_to_1_state_next <= S_STATE_WAIT;
s_1_counter_next <= 0;
when S_STATE_WAIT =>
if start_to_1 = '1' then
send_to_1_state_next <= S_STATE_LOCK;
end if;
when S_STATE_LOCK =>
req_0(1) <= '1';
if grant_0(1) = '0' then
send_to_1_state_next <= S_STATE_LOCK;
else
send_to_1_state_next <= S_STATE_SEND_FIRST;
end if;
when S_STATE_SEND_FIRST =>
src_rdy_0(1) <= '1';
sof_0(1) <= '1';
to_1_data <= (others => '1');
s_1_counter_next <= s_1_counter + 1;
send_to_1_state_next <= S_STATE_INTERM;
req_0(1) <= '1';
when S_STATE_INTERM =>
req_0(1) <= '1';
src_rdy_0(1) <= '1';
to_1_data <= (others => '0');
if s_1_counter = 15 then
s_1_counter_next <= 0;
send_to_1_state_next <= S_STATE_WAIT;
eof_0(1) <= '1';
else
s_1_counter_next <= s_1_counter + 1;
end if;
when others =>
send_to_1_state_next <= S_STATE_INIT;
end case;
end process;
send_to_2 : process(start_to_2, send_to_2_state, s_2_counter, grant_0)
begin
src_rdy_0(2) <= '0';
to_2_data <= (others => '0');
sof_0(2) <= '0';
eof_0(2) <= '0';
req_0(2) <= '0';
send_to_2_state_next <= send_to_2_state;
s_2_counter_next <= s_2_counter;
case send_to_2_state is
when S_STATE_INIT =>
send_to_2_state_next <= S_STATE_WAIT;
s_2_counter_next <= 0;
when S_STATE_WAIT =>
if start_to_2 = '1' then
send_to_2_state_next <= S_STATE_LOCK;
end if;
when S_STATE_LOCK =>
req_0(2) <= '1';
if grant_0(2) = '0' then
send_to_2_state_next <= S_STATE_LOCK;
else
send_to_2_state_next <= S_STATE_SEND_FIRST;
end if;
when S_STATE_SEND_FIRST =>
src_rdy_0(2) <= '1';
sof_0(2) <= '1';
to_2_data <= (others => '1');
s_2_counter_next <= s_2_counter + 1;
send_to_2_state_next <= S_STATE_INTERM;
req_0(2) <= '1';
when S_STATE_INTERM =>
req_0(2) <= '1';
src_rdy_0(2) <= '1';
to_2_data <= (others => '0');
if s_2_counter = 15 then
s_2_counter_next <= 0;
send_to_2_state_next <= S_STATE_WAIT;
eof_0(2) <= '1';
else
s_2_counter_next <= s_2_counter + 1;
end if;
when others =>
send_to_2_state_next <= S_STATE_INIT;
end case;
end process;
-- memzing process
-- updates all the registers
proces_mem : process(clk, reset)
begin
if reset = '1' then
send_to_0_state <= S_STATE_INIT;
s_0_counter <= 0;
send_to_1_state <= S_STATE_INIT;
s_1_counter <= 0;
send_to_2_state <= S_STATE_INIT;
s_2_counter <= 0;
receive_state <= R_STATE_INIT;
received_counter <= 0;
elsif rising_edge(clk) then
send_to_0_state <= send_to_0_state_next;
s_0_counter <= s_0_counter_next;
send_to_1_state <= send_to_1_state_next;
s_1_counter <= s_1_counter_next;
send_to_2_state <= send_to_2_state_next;
s_2_counter <= s_2_counter_next;
receive_state <= receive_state_next;
received_counter <= received_counter_next;
end if;
end process;
-- OS synchronization state machine
-- this has to have this special format!
state_proc : process(clk, reset)
variable success : boolean;
variable done : boolean;
variable sw_command : std_logic_vector(0 to C_OSIF_DATA_WIDTH - 1);
begin
if reset = '1' then
reconos_reset_with_signature(o_osif, i_osif, X"ABCDEF01");
os_sync_state <= STATE_INIT;
start_to_0 <= '0';
start_to_1 <= '0';
start_to_2 <= '0';
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case os_sync_state is
when STATE_INIT =>
os_sync_state <= STATE_GET_COMMAND;
start_to_0 <= '0';
start_to_1 <= '0';
start_to_2 <= '0';
when STATE_SEND_ANSWER =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MBOX_HANDLE_HW_SW,
std_logic_vector(to_unsigned(received_counter,C_OSIF_DATA_WIDTH)));
if done then
os_sync_state <= STATE_GET_COMMAND;
end if;
when STATE_GET_COMMAND =>
reconos_mbox_get(done, success, o_osif, i_osif, C_MBOX_HANDLE_SW_HW, sw_command);
if done and success then
os_sync_state <= STATE_DECODE;
end if;
when STATE_DECODE =>
--default: command not known
os_sync_state <= STATE_GET_COMMAND;
-- element 0 indicates whether this thread should send to slot 0,
-- element 1 indicates whether this thread should send to slot 1,
-- element 6 indicates whether the receive counter from the bus interface
-- should be reported
if sw_command(6) = '1' then
os_sync_state <= STATE_SEND_ANSWER;
else
if sw_command(0) = '1' then
start_to_0 <= '1';
else
start_to_0 <= '0';
end if;
if sw_command(1) = '1' then
start_to_1 <= '1';
else
start_to_1 <= '0';
end if;
if sw_command(2) = '1' then
start_to_2 <= '1';
else
start_to_2 <= '0';
end if;
end if;
when others =>
os_sync_state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
039ed4fceea8cb425a710969e73c7713
| 0.56798 | 2.6582 | false | false | false | false |
luebbers/reconos
|
core/pcores/osif_tlb_v2_01_a/hdl/vhdl/tlb.vhd
| 1 | 5,397 |
------------------------------------------------------------------------------
-- TLB implementation with asynchronous read and synchronous write.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library osif_tlb_v2_01_a;
use osif_tlb_v2_01_a.all;
entity tlb is
generic
(
C_TAG_WIDTH : integer := 20;
C_DATA_WIDTH : integer := 21
);
port
(
clk : in std_logic;
rst : in std_logic;
i_tag : in std_logic_vector(C_TAG_WIDTH - 1 downto 0);
i_data : in std_logic_vector(C_DATA_WIDTH - 1 downto 0);
o_data : out std_logic_vector(C_DATA_WIDTH - 1 downto 0);
i_we : in std_logic;
o_busy : out std_logic;
-- o_wdone : out std_logic;
o_match : out std_logic;
i_invalidate : in std_logic
);
end entity;
architecture imp of tlb is
component cam27x32
port (
clk : in std_logic;
din : in std_logic_vector(26 downto 0);
we : in std_logic;
wr_addr : in std_logic_vector(4 downto 0);
busy : out std_logic;
match : out std_logic;
match_addr : out std_logic_vector(31 downto 0);
single_match : out std_logic
);
end component;
component cam27x32b
port (
clk : in std_logic;
din : in std_logic_vector(26 downto 0);
we : in std_logic;
wr_addr : in std_logic_vector(4 downto 0);
busy : out std_logic;
match : out std_logic;
match_addr : out std_logic_vector(31 downto 0);
single_match : out std_logic
);
end component;
-- content addressable RAM with depth 32 and 27 bit width (~ 3 BRAMS)
component cam27x32m
port (
clk : in std_logic;
din : in std_logic_vector(26 downto 0);
we : in std_logic;
wr_addr : in std_logic_vector(4 downto 0);
busy : out std_logic;
match : out std_logic;
match_addr : out std_logic_vector(31 downto 0)
);
end component;
constant C_CAM_WIDTH : natural := 27;
constant C_CAM_DEPTH : natural := 32;
-- data entries
type rpn_array_t is array(C_CAM_DEPTH - 1 downto 0) of std_logic_vector(C_DATA_WIDTH - 1 downto 0);
signal din : std_logic_vector(C_CAM_WIDTH - 1 downto 0);
signal pad : std_logic_vector(C_CAM_WIDTH - 1 - C_TAG_WIDTH downto 0);
signal waddr : std_logic_vector(4 downto 0);
signal match : std_logic;
signal match_addr : std_logic_vector(4 downto 0);
signal multi_match_addr : std_logic_vector(C_CAM_DEPTH - 1 downto 0);
signal busy : std_logic;
signal data_rpn : rpn_array_t;
signal data_valid : std_logic_vector(C_CAM_DEPTH - 1 downto 0);
signal we : std_logic;
begin
pad <= (others => '0');
din <= i_tag & pad;
o_busy <= busy;
--output_or : process(match_addr, data_rpn, data_valid, match)
--variable tmp : std_logic_vector(C_DATA_WIDTH - 1 downto 0);
--begin
--if rising_edge(clk) then
o_data <= data_rpn(CONV_INTEGER(match_addr));
o_match <= data_valid(CONV_INTEGER(match_addr)) and match;
--end if;
--end process;
write_sync : process(clk, rst, i_invalidate)
variable step : integer range 0 to 1;
begin
if rst = '1' or i_invalidate = '1' then
data_valid <= (others => '0');
step := 0;
elsif rising_edge(clk) then
we <= '0';
case step is
when 0 =>
-- o_wdone <= '0';
if i_we = '1' then -- i_we must stay high for 1 cycle
if busy = '0' then -- ignore write requests while busy
data_rpn(CONV_INTEGER(waddr)) <= i_data;
data_valid(CONV_INTEGER(waddr)) <= '1';
we <= '1';
end if;
step := 1;
end if;
when 1 =>
waddr <= waddr + 1;
-- o_wdone <= '1';
step := 0;
end case;
end if;
end process;
i_match_encoder : entity osif_tlb_v2_01_a.match_encoder
port map (
i_multi_match => multi_match_addr,
i_mask => data_valid,
o_match_addr => match_addr,
o_match => match
);
i_cam27x32 : cam27x32m
port map (
clk => clk,
din => din,
we => we,
wr_addr => waddr,
busy => busy,
--match => match,
match_addr => multi_match_addr
);
end architecture;
|
gpl-3.0
|
9302b88aaa66c1bfca2978df6b63ef54
| 0.451177 | 3.933673 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/TempSensorCtl.vhd
| 1 | 13,335 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Elod Gyorgy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 15:26:37 02/17/2014
-- Design Name:
-- Module Name: TempSensorCtl - Behavioral
-- Project Name: Nexys4 User Demo
-- Target Devices:
-- Tool versions:
-- Description:
-- This module represents the controller for the Nexys4 onboard ADT7420
-- temperature sensor. The module uses a Two-Wire Interface controller to
-- configure the ADT7420 and read the temperature continuously.
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.all;
use IEEE.std_logic_arith.all;
-- Use the package defined in the TWICtl.vhd file
use work.TWIUtils.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TempSensorCtl is
Generic (CLOCKFREQ : natural := 100); -- input CLK frequency in MHz
Port (
TMP_SCL : inout STD_LOGIC;
TMP_SDA : inout STD_LOGIC;
-- TMP_INT : in STD_LOGIC; -- Interrupt line from the ADT7420, not used in this project
-- TMP_CT : in STD_LOGIC; -- Critical Temperature interrupt line from ADT7420, not used in this project
TEMP_O : out STD_LOGIC_VECTOR(12 downto 0); --12-bit two's complement temperature with sign bit
RDY_O : out STD_LOGIC; --'1' when there is a valid temperature reading on TEMP_O
ERR_O : out STD_LOGIC; --'1' if communication error
CLK_I : in STD_LOGIC;
SRST_I : in STD_LOGIC
);
end TempSensorCtl;
architecture Behavioral of TempSensorCtl is
-- TWI Controller component declaration
component TWICtl
generic
(
CLOCKFREQ : natural := 50; -- input CLK frequency in MHz
ATTEMPT_SLAVE_UNBLOCK : boolean := false --setting this true will attempt
--to drive a few clock pulses for a slave to allow to finish a previous
--interrupted read transfer, otherwise the bus might remain locked up
);
port (
MSG_I : in STD_LOGIC; --new message
STB_I : in STD_LOGIC; --strobe
A_I : in STD_LOGIC_VECTOR (7 downto 0); --address input bus
D_I : in STD_LOGIC_VECTOR (7 downto 0); --data input bus
D_O : out STD_LOGIC_VECTOR (7 downto 0); --data output bus
DONE_O : out STD_LOGIC; --done status signal
ERR_O : out STD_LOGIC; --error status
ERRTYPE_O : out error_type; --error type
CLK : in std_logic;
SRST : in std_logic;
----------------------------------------------------------------------------------
-- TWI bus signals
----------------------------------------------------------------------------------
SDA : inout std_logic; --TWI SDA
SCL : inout std_logic --TWI SCL
);
end component;
----------------------------------------------------------------------------------
-- Definitions for the I2C initialization vector
----------------------------------------------------------------------------------
constant IRD : std_logic := '1'; -- init read
constant IWR : std_logic := '0'; -- init write
constant ADT7420_ADDR : std_logic_vector(7 downto 1) := "1001011"; -- TWI Slave Address
constant ADT7420_RID : std_logic_vector(7 downto 0) := x"0B"; -- ID Register Address for the ADT7420
constant ADT7420_RRESET : std_logic_vector(7 downto 0) := x"2F"; -- Software Reset Register
constant ADT7420_RTEMP : std_logic_vector(7 downto 0) := x"00"; -- Temperature Read MSB Address
constant ADT7420_ID : std_logic_vector(7 downto 0) := x"CB"; -- ADT7420 Manufacturer ID
constant DELAY : NATURAL := 1; --ms
constant DELAY_CYCLES : NATURAL := natural(ceil(real(DELAY*1000*CLOCKFREQ)));
constant RETRY_COUNT : NATURAL := 10;
-- State MAchine states definition
type state_type is (
stIdle, -- Idle State
stInitReg, -- Send register address from the init vector
stInitData, -- Send data byte from the init vector
stRetry, -- Retry state reached when there is a bus error, will retry RETRY_COUNT times
stReadTempR, -- Send temperature register address
stReadTempD1, -- Read temperature MSB
stReadTempD2, -- Read temperature LSB
stError -- Error state when reached when there is a bus error after a successful init; stays here until reset
);
signal state, nstate : state_type;
constant NO_OF_INIT_VECTORS : natural := 3; -- number of init vectors in TempSensInitMap
constant DATA_WIDTH : integer := 1 + 8 + 8; -- RD/WR bit + 1 byte register address + 1 byte data
constant ADDR_WIDTH : natural := natural(ceil(log(real(NO_OF_INIT_VECTORS), 2.0)));
type TempSensInitMap_type is array (0 to NO_OF_INIT_VECTORS-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal TempSensInitMap: TempSensInitMap_type := (
IRD & x"0B" & x"CB", -- Read ID R[0x0B]=0xCB
IWR & x"2F" & x"00", -- Reset R[0x2F]=don't care
IRD & x"0B" & x"CB" -- Read ID R[0x0B]=0xCB
);
signal initWord: std_logic_vector (DATA_WIDTH-1 downto 0);
signal initA : natural range 0 to NO_OF_INIT_VECTORS := 0; --init vector index
signal initEn : std_logic;
--Two-Wire Controller signals
signal twiMsg, twiStb, twiDone, twiErr : std_logic;
signal twiDi, twiDo, twiAddr : std_logic_vector(7 downto 0);
--Wait counter used between retry attempts
signal waitCnt : natural range 0 to DELAY_CYCLES := DELAY_CYCLES;
signal waitCntEn : std_logic;
--Retry counter to count down attempts to get rid of a bus error
signal retryCnt : natural range 0 to RETRY_COUNT := RETRY_COUNT;
signal retryCntEn : std_logic;
-- Temporary register to store received data
signal tempReg : std_logic_vector(15 downto 0) := (others => '0');
-- Flag indicating that a new temperature data is available
signal fReady : boolean := false;
begin
----------------------------------------------------------------------------------
-- Outputs
----------------------------------------------------------------------------------
TEMP_O <= tempReg(15 downto 3);
RDY_O <= '1' when fReady else
'0';
ERR_O <= '1' when state = stError else
'0';
----------------------------------------------------------------------------------
-- I2C Master Controller
----------------------------------------------------------------------------------
Inst_TWICtl : TWICtl
generic map (
ATTEMPT_SLAVE_UNBLOCK => true,
CLOCKFREQ => 100
)
port map (
MSG_I => twiMsg,
STB_I => twiStb,
A_I => twiAddr,
D_I => twiDi,
D_O => twiDo,
DONE_O => twiDone,
ERR_O => twiErr,
ERRTYPE_O => open,
CLK => CLK_I,
SRST => SRST_I,
SDA => TMP_SDA,
SCL => TMP_SCL
);
----------------------------------------------------------------------------------
-- Initialiation Map RAM
----------------------------------------------------------------------------------
initWord <= TempSensInitMap(initA);
InitA_CNT: process (CLK_I)
begin
if Rising_Edge(CLK_I) then
if (state = stIdle or initA = NO_OF_INIT_VECTORS) then
initA <= 0;
elsif (initEn = '1') then
initA <= initA + 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- Delay and Retry Counters
----------------------------------------------------------------------------------
Wait_CNT: process (CLK_I)
begin
if Rising_Edge(CLK_I) then
if (waitCntEn = '0') then
waitCnt <= DELAY_CYCLES;
else
waitCnt <= waitCnt - 1;
end if;
end if;
end process;
Retry_CNT: process (CLK_I)
begin
if Rising_Edge(CLK_I) then
if (state = stIdle) then
retryCnt <= RETRY_COUNT;
elsif (retryCntEn = '1') then
retryCnt <= retryCnt - 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- Temperature Registers
----------------------------------------------------------------------------------
TemperatureReg: process (CLK_I)
variable temp : std_logic_vector(7 downto 0);
begin
if Rising_Edge(CLK_I) then
--MSB
if (state = stReadTempD1 and twiDone = '1' and twiErr = '0') then
temp := twiDo;
end if;
--LSB
if (state = stReadTempD2 and twiDone = '1' and twiErr = '0') then
tempReg <= temp & twiDo;
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- Ready Flag
----------------------------------------------------------------------------------
ReadyFlag: process (CLK_I)
begin
if Rising_Edge(CLK_I) then
if (state = stIdle or state = stError) then
fReady <= false;
elsif (state = stReadTempD2 and twiDone = '1' and twiErr = '0') then
fReady <= true;
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- Initialization FSM & Continuous temperature read
----------------------------------------------------------------------------------
SYNC_PROC: process (CLK_I)
begin
if (CLK_I'event and CLK_I = '1') then
if (SRST_I = '1') then
state <= stIdle;
else
state <= nstate;
end if;
end if;
end process;
OUTPUT_DECODE: process (state, initWord, twiDone, twiErr, twiDo, retryCnt, waitCnt, initA)
begin
twiStb <= '0'; --byte send/receive strobe
twiMsg <= '0'; --new transfer request (repeated start)
waitCntEn <= '0'; --wait countdown enable
twiDi <= "--------"; --byte to send
twiAddr <= ADT7420_ADDR & '0'; --I2C device address with R/W bit
initEn <= '0'; --increase init map address
retryCntEn <= '0'; --retry countdown enable
case (state) is
when stIdle =>
when stInitReg => --this state sends the register address from the current init vector
twiStb <= '1';
twiMsg <= '1';
twiAddr(0) <= IWR; --Register address is a write
twiDi <= initWord(15 downto 8);
when stInitData => --this state sends the data byte from the current init vector
twiStb <= '1';
twiAddr(0) <= initWord(initWord'high); --could be read or write
twiDi <= initWord(7 downto 0);
if (twiDone = '1' and
(twiErr = '0' or (initWord(16) = IWR and initWord(15 downto 8) = ADT7420_RRESET)) and
(initWord(initWord'high) = IWR or twiDo = initWord(7 downto 0))) then
initEn <= '1';
end if;
when stRetry=> --in case of an I2C error during initialization this state will be reached
if (retryCnt /= 0) then
waitCntEn <= '1';
if (waitCnt = 0) then
retryCntEn <= '1';
end if;
end if;
when stReadTempR => --this state sends the temperature register address
twiStb <= '1';
twiMsg <= '1';
twiDi <= ADT7420_RTEMP;
twiAddr(0) <= IWR; --Register address is a write
when stReadTempD1 => --this state reads the temperature MSB
twiStb <= '1';
twiAddr(0) <= IRD;
when stReadTempD2 => --this state reads the temperature LSB
twiStb <= '1';
twiAddr(0) <= IRD;
when stError => --in case of an I2C error during temperature poll
null; --stay here
end case;
end process;
NEXT_STATE_DECODE: process (state, twiDone, twiErr, initWord, twiDo, retryCnt, waitCnt)
begin
--declare default state for nstate to avoid latches
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
nstate <= stInitReg;
when stInitReg =>
if (twiDone = '1') then
if (twiErr = '1') then
nstate <= stRetry;
else
nstate <= stInitData;
end if;
end if;
when stInitData =>
if (twiDone = '1') then
if (twiErr = '1') then
nstate <= stRetry;
else
if (initWord(initWord'high) = IRD and twiDo /= initWord(7 downto 0)) then
nstate <= stRetry;
elsif (initA = NO_OF_INIT_VECTORS-1) then
nstate <= stReadTempR;
else
nstate <= stInitReg;
end if;
end if;
end if;
when stRetry =>
if (retryCnt = 0) then
nstate <= stError;
elsif (waitCnt = 0) then
nstate <= stInitReg; --new retry attempt
end if;
when stReadTempR =>
if (twiDone = '1') then
if (twiErr = '1') then
nstate <= stError;
else
nstate <= stReadTempD1;
end if;
end if;
when stReadTempD1 =>
if (twiDone = '1') then
if (twiErr = '1') then
nstate <= stError;
else
nstate <= stReadTempD2;
end if;
end if;
when stReadTempD2 =>
if (twiDone = '1') then
if (twiErr = '1') then
nstate <= stError;
else
nstate <= stReadTempR;
end if;
end if;
when stError =>
null; --stay
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
gpl-3.0
|
ebb739c4f8e93192a305edb0cb1065dd
| 0.540832 | 3.847374 | false | false | false | false |
bzero/freezing-spice
|
tests/decoder_tb.vhd
| 2 | 15,333 |
library ieee;
use ieee.std_logic_1164.all;
use work.decode_pkg.all;
use work.common.all;
use work.encode_pkg.all;
entity decoder_tb is
end entity decoder_tb;
architecture testbench of decoder_tb is
-- inputs
signal insn : word;
-- outputs
signal decoded : decoded_t;
procedure verify_r_type (insn_type : in insn_type_t;
r_insn : in r_insn_t;
rs1, rs2, d : in std_logic_vector(4 downto 0)) is
begin
print_insn(insn_type);
assert decoded.insn_type = insn_type report "Invalid instruction type" severity error;
case (r_insn) is
when R_ADD => assert decoded.alu_func = ALU_ADD report "Invalid ALU function" severity error;
when R_SLT => assert decoded.alu_func = ALU_SLT report "Invalid ALU function" severity error;
when R_SLTU => assert decoded.alu_func = ALU_SLTU report "Invalid ALU function" severity error;
when R_AND => assert decoded.alu_func = ALU_AND report "Invalid ALU function" severity error;
when R_OR => assert decoded.alu_func = ALU_OR report "Invalid ALU function" severity error;
when R_XOR => assert decoded.alu_func = ALU_XOR report "Invalid ALU function" severity error;
when R_SLL => assert decoded.alu_func = ALU_SLL report "Invalid ALU function" severity error;
when R_SRL => assert decoded.alu_func = ALU_SRL report "Invalid ALU function" severity error;
when R_SUB => assert decoded.alu_func = ALU_SUB report "Invalid ALU function" severity error;
when R_SRA => assert decoded.alu_func = ALU_SRA report "Invalid ALU function" severity error;
end case;
end procedure verify_r_type;
-- purpose: verify U-type instruction
procedure verify_u_type (
insn_type : in insn_type_t;
imm : in word;
rd : in std_logic_vector(4 downto 0)) is
begin
print_insn(insn_type);
assert decoded.insn_type = insn_type report "Invalid instruction type" severity error;
assert decoded.imm = imm report "Invalid Immediate Value" severity error;
assert decoded.rd = rd report "Invalid Rd" severity error;
end procedure verify_u_type;
-- purpose: verify UJ-type instruction
procedure verify_uj_type (
insn_type : in insn_type_t;
imm : in word;
rd : in std_logic_vector(4 downto 0)) is
begin -- procedure verify_uj_type
print_insn(insn_type);
assert decoded.insn_type = insn_type report "Invalid instruction type" severity error;
assert decoded.imm = imm report "Invalid immediate" severity error;
assert decoded.rd = rd report "Invalid Rd" severity error;
end procedure verify_uj_type;
-- purpose: verify a decoded I-type instruction
procedure verify_i_type (insn_type : in insn_type_t;
i_type : in i_insn_t;
imm : in word;
rs1, rd : in std_logic_vector(4 downto 0)) is
begin -- procedure verify_i_type
print_insn(insn_type);
assert decoded.insn_type = insn_type report "Invalid instruction type" severity error;
assert decoded.imm = imm report "Invalid immediate" severity error;
assert decoded.rs1 = rs1 report "Invalid Rs1" severity error;
assert decoded.rd = rd report "Invalid Rd" severity error;
case (insn_type) is
when OP_LOAD =>
case i_type is
when I_LB => assert decoded.load_type = LB report "Invalid load type" severity error;
when I_LH => assert decoded.load_type = LH report "Invalid load type" severity error;
when I_LW => assert decoded.load_type = LW report "Invalid load type" severity error;
when I_LBU => assert decoded.load_type = LBU report "Invalid load type" severity error;
when I_LHU => assert decoded.load_type = LHU report "Invalid load type" severity error;
when others => assert false report "Unexpected load type" severity error;
end case;
when OP_ALU =>
case i_type is
when I_ADDI => assert decoded.alu_func = ALU_ADD report "Invalid ALU function" severity error;
when I_SLTI => assert decoded.alu_func = ALU_SLT report "Invalid ALU function" severity error;
when I_SLTIU => assert decoded.alu_func = ALU_SLTU report "Invalid ALU function" severity error;
when I_XORI => assert decoded.alu_func = ALU_XOR report "Invalid ALU function" severity error;
when I_ORI => assert decoded.alu_func = ALU_OR report "Invalid ALU function" severity error;
when I_ANDI => assert decoded.alu_func = ALU_AND report "Invalid ALU function" severity error;
when others => assert false report "Unexpected ALU function" severity error;
end case;
when OP_JALR => null;
when others =>
assert false report "Unexpected instruction type" severity error;
end case;
end procedure verify_i_type;
procedure verify_s_type (insn_type : in insn_type_t;
s_type : in s_insn_t;
imm : in word;
rs1, rs2 : in std_logic_vector(4 downto 0)) is
begin
print_insn(insn_type);
assert decoded.insn_type = insn_type report "Invalid instruction type" severity error;
assert decoded.imm = imm report "" severity error;
assert decoded.rs1 = rs1 report "Invalid Rs1" severity error;
assert decoded.rs2 = rs2 report "Invalid Rs2" severity error;
case s_type is
when S_SB => assert decoded.store_type = SB report "Invalid store type" severity error;
when S_SH => assert decoded.store_type = SH report "Invalid store type" severity error;
when S_SW => assert decoded.store_type = SW report "Invalid store type" severity error;
when others => assert false report "Unexpected store type" severity error;
end case;
end procedure verify_s_type;
-- purpose: verify a decoded SB-type instruction
procedure verify_sb_type (
insn_type : in insn_type_t;
imm : in word;
branch_type : in branch_type_t;
rs1, rs2 : in std_logic_vector(4 downto 0)) is
begin -- procedure verify_sb_type
print_insn(insn_type);
assert decoded.insn_type = insn_type report "Invalid instruction type" severity error;
assert decoded.imm = imm report "Invalid immediate" severity error;
assert decoded.branch_type = branch_type report "Invalid branch type" severity error;
assert decoded.rs1 = rs1 report "Invalid Rs1" severity error;
assert decoded.rs2 = rs2 report "Invalid Rs2" severity error;
end procedure verify_sb_type;
-- purpose: verify a decoded I-type shift instruction
procedure verify_i_shift (
i_insn : in i_insn_t;
shamt : in std_logic_vector(4 downto 0);
rs1, rd : in std_logic_vector(4 downto 0)) is
begin -- procedure verify_i_shift
println("Instruction type: ALU SHIFT");
assert decoded.insn_type = OP_ALU report "Expected OP_ALU" severity error;
case i_insn is
when I_SLLI =>
assert decoded.alu_func = ALU_SLL report "Invalid ALU type" severity error;
when I_SRLI =>
assert decoded.alu_func = ALU_SRL report "Invalid ALU type" severity error;
when I_SRAI =>
assert decoded.alu_func = ALU_SRA report "Invalid ALU type" severity error;
when others =>
assert false report "Invalid Shift type" severity error;
end case;
end procedure verify_i_shift;
begin -- architecture test
uut : entity work.decoder(behavioral)
port map (insn => insn,
decoded => decoded);
-- purpose: provide stimulus and verification of the RISCV decoder
-- type : combinational
-- inputs :
-- outputs: asserts
stimulus_proc : process is
begin -- process stimulus_proc
-- LUI
insn <= encode_u_type(U_LUI, "01010101010101010101", 31);
wait for 1 ns;
verify_u_type(OP_LUI, "01010101010101010101000000000000", "11111");
-- AUIPC
insn <= encode_u_type(U_AUIPC, "10101010101010101010", 21);
wait for 1 ns;
verify_u_type(OP_AUIPC, "10101010101010101010000000000000", "10101");
-- JAL
insn <= encode_uj_type(UJ_JAL, "11010101001010101010", 10);
wait for 1 ns;
verify_uj_type(OP_JAL, "11111111111110101010010101010100", "01010");
-- JALR
insn <= encode_i_type(I_JALR, "110011001100", 6, 5);
wait for 1 ns;
verify_i_type(OP_JALR, I_JALR, "11111111111111111111110011001100", "00110", "00101");
-- BEQ
insn <= encode_sb_type(SB_BEQ, "101101101101", 20, 1);
wait for 1 ns;
verify_sb_type(OP_BRANCH, "11111111111111111111011011011010", BEQ, "10100", "00001");
-- BNE
insn <= encode_sb_type(SB_BNE, "000010000101", 16, 18);
wait for 1 ns;
verify_sb_type(OP_BRANCH, "00000000000000000000000100001010", BNE, "10000", "10010");
-- BLT
insn <= encode_sb_type(SB_BLT, "001011001110", 15, 14);
wait for 1 ns;
verify_sb_type(OP_BRANCH, "00000000000000000000010110011100", BLT, "01111", "01110");
-- BGE
insn <= encode_sb_type(SB_BGE, "001010101001", 13, 12);
wait for 1 ns;
verify_sb_type(OP_BRANCH, "00000000000000000000010101010010", BGE, "01101", "01100");
-- BLTU
insn <= encode_sb_type(SB_BLTU, "001010101001", 13, 12);
wait for 1 ns;
verify_sb_type(OP_BRANCH, "00000000000000000000010101010010", BLTU, "01101", "01100");
-- BGEU
insn <= encode_sb_type(SB_BGEU, "101111000110", 11, 10);
wait for 1 ns;
verify_sb_type(OP_BRANCH, "11111111111111111111011110001100", BGEU, "01011", "01010");
-- LB
insn <= encode_i_type(I_LB, "000111000111", 9, 8);
wait for 1 ns;
verify_i_type(OP_LOAD, I_LB, "00000000000000000000000111000111", "01001", "01000");
-- LH
insn <= encode_i_type(I_LH, "011011011011", 7, 6);
wait for 1 ns;
verify_i_type(OP_LOAD, I_LH, "00000000000000000000011011011011", "00111", "00110");
-- LW
insn <= encode_i_type(I_LW, "011011011010", 5, 4);
wait for 1 ns;
verify_i_type(OP_LOAD, I_LW, "00000000000000000000011011011010", "00101", "00100");
-- LBU
insn <= encode_i_type(I_LBU, "110110110110", 3, 2);
wait for 1 ns;
verify_i_type(OP_LOAD, I_LBU, "11111111111111111111110110110110", "00011", "00010");
-- LHU
insn <= encode_i_type(I_LHU, "111111111111", 1, 0);
wait for 1 ns;
verify_i_type(OP_LOAD, I_LHU, "11111111111111111111111111111111", "00001", "00000");
-- SB
insn <= encode_s_type(S_SB, "011111111110", 21, 22);
wait for 1 ns;
verify_s_type(OP_STORE, S_SB, "00000000000000000000011111111110", "10101", "10110");
-- SH
insn <= encode_s_type(S_SH, "011111111110", 21, 22);
wait for 1 ns;
verify_s_type(OP_STORE, S_SH, "00000000000000000000011111111110", "10101", "10110");
-- SW
insn <= encode_s_type(S_SW, "001111111110", 23, 24);
wait for 1 ns;
verify_s_type(OP_STORE, S_SW, "00000000000000000000001111111110", "10111", "11000");
-- ADDI
insn <= encode_i_type(I_ADDI, "111111111111", 25, 26);
wait for 1 ns;
verify_i_type(OP_ALU, I_ADDI, "11111111111111111111111111111111", "11001", "11010");
-- SLTI
insn <= encode_i_type(I_SLTI, "111111111110", 27, 28);
wait for 1 ns;
verify_i_type(OP_ALU, I_SLTI, "11111111111111111111111111111110", "11011", "11100");
-- SLTIU
insn <= encode_i_type(I_SLTIU, "111111111100", 29, 30);
wait for 1 ns;
verify_i_type(OP_ALU, I_SLTIU, "11111111111111111111111111111100", "11101", "11110");
-- XORI
insn <= encode_i_type(I_XORI, "111111111110", 31, 30);
wait for 1 ns;
verify_i_type(OP_ALU, I_XORI, "11111111111111111111111111111110", "11111", "11110");
-- ORI
insn <= encode_i_type(I_ORI, "111111111110", 1, 2);
wait for 1 ns;
verify_i_type(OP_ALU, I_ORI, "11111111111111111111111111111110", "00001", "00010");
-- ANDI
insn <= encode_i_type(I_ANDI, "111111111110", 3, 4);
wait for 1 ns;
verify_i_type(OP_ALU, I_ANDI, "11111111111111111111111111111110", "00011", "00100");
-- SLLI
insn <= encode_i_shift(I_SLLI, "11100", 5, 6);
wait for 1 ns;
verify_i_shift(I_SLLI, "11100", "00101", "00110");
-- SRLI
insn <= encode_i_shift(I_SRLI, "11101", 7, 8);
wait for 1 ns;
verify_i_shift(I_SRLI, "11101", "00101", "00110");
-- SRAI
insn <= encode_i_shift(I_SRAI, "11110", 9, 10);
wait for 1 ns;
verify_i_shift(I_SRAI, "11110", "00101", "00110");
-- ADD
insn <= encode_r_type(R_ADD, 2, 4, 8);
wait for 1 ns;
verify_r_type(OP_ALU, R_ADD, "00010", "00100", "01000");
-- SUB
insn <= encode_r_type(R_SUB, 16, 31, 1);
wait for 1 ns;
verify_r_type(OP_ALU, R_SUB, "10000", "11111", "00001");
-- SLL
insn <= encode_r_type(R_SLL, 0, 0, 0);
wait for 1 ns;
verify_r_type(OP_ALU, R_SLL, "00000", "00000", "00000");
-- SLT
insn <= encode_r_type(R_SLT, 16, 8, 4);
wait for 1 ns;
verify_r_type(OP_ALU, R_SLT, "10000", "01000", "00100");
-- SLTU
insn <= encode_r_type(R_SLTU, 24, 12, 6);
wait for 1 ns;
verify_r_type(OP_ALU, R_SLTU, "11000", "01100", "00110");
-- XOR
insn <= encode_r_type(R_XOR, 0, 0, 0);
wait for 1 ns;
verify_r_type(OP_ALU, R_XOR, "00000", "00000", "00000");
-- SRL
insn <= encode_r_type(R_SRL, 0, 0, 0);
wait for 1 ns;
verify_r_type(OP_ALU, R_SRL, "00000", "00000", "00000");
-- SRA
insn <= encode_r_type(R_SRA, 0, 0, 0);
wait for 1 ns;
verify_r_type(OP_ALU, R_SRA, "00000", "00000", "00000");
-- OR
insn <= encode_r_type(R_OR, 0, 0, 0);
wait for 1 ns;
verify_r_type(OP_ALU, R_OR, "00000", "00000", "00000");
-- AND
insn <= encode_r_type(R_AND, 0, 0, 0);
wait for 1 ns;
verify_r_type(OP_ALU, R_AND, "00000", "00000", "00000");
-- @todo others
----------------------------------------------------------------
println("Verification complete");
----------------------------------------------------------------
wait;
end process stimulus_proc;
end architecture testbench;
|
bsd-3-clause
|
8020d5a865d322a3e4dcca49ed0bef2d
| 0.574708 | 3.88079 | false | false | false | false |
zebarnabe/music-keyboard-vhdl
|
src/main/voiceSynth.vhd
| 1 | 1,736 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:34:41 10/24/2015
-- Design Name:
-- Module Name: voiceSynth - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity voiceSynth is
Port ( clk : in STD_LOGIC;
enable : in STD_LOGIC;
period : in unsigned (15 downto 0);
sig : out STD_LOGIC_VECTOR (7 downto 0));
end voiceSynth;
architecture Behavioral of voiceSynth is
constant clkDiv: integer := 4;
-- Nexys 2 runs at 50,000,000 Mhz..
-- Sample clock at 3125000Hz.
signal counter: std_logic_vector(16 + clkDiv downto 0);
begin
clkCounter: process(clk, period, enable)
begin
if rising_edge(clk) then
if (counter(counter'left downto clkDiv) < '0'&std_logic_vector(period)) and (enable = '1') then
counter <= std_logic_vector(unsigned(counter) + 1);
else
counter <= (others => '0');
end if;
end if;
end process;
synth: process(counter, period)
begin
if counter(16 + clkDiv downto clkDiv) > ('0' & std_logic_vector(period/2)) then
sig <= (others => '1');
else
sig <= (others => '0');
end if;
end process;
end Behavioral;
|
gpl-2.0
|
14e14b2eb5fdc5484838194d587912af
| 0.605415 | 3.67019 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v1_00_a/hdl/vhdl/TESTBENCH_ac97_core.vhd
| 4 | 14,277 |
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_core.vhd,v 1.1 2005/02/17 20:29:34 crh Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_ac97_core.vhd
--
-- Description: Simple testbench for ac97_core
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:34 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBENCH_ac97_core is
end TESTBENCH_ac97_core;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.TESTBENCH_ac97_package.all;
architecture behavioral of TESTBENCH_ac97_core is
component ac97_core is
generic (
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
-- AC97 register interface
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Strobe : in std_logic; -- initiates a "read" command
AC97_Reg_Write_Strobe : in std_logic; -- initiates a "write" command
AC97_Reg_Busy : out std_logic;
AC97_Reg_Error : out std_logic;
AC97_Reg_Read_Data_Valid : out std_logic;
-- Playback signal interface
PCM_Playback_Left: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Right: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Playback_Left_Accept: out std_logic;
PCM_Playback_Right_Accept: out std_logic;
-- Record signal interface
PCM_Record_Left: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Right: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
--
CODEC_RDY : out std_logic
);
end component;
component ac97_model is
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end component;
signal reset : std_logic;
signal ac97_reset : std_logic;
signal clk : std_logic;
signal sync : std_logic;
signal sdata_out : std_logic;
signal sdata_in : std_logic;
signal reg_addr : std_logic_vector(0 to 6);
signal reg_write_data : std_logic_vector(0 to 15);
signal reg_read_data : std_logic_vector(0 to 15);
signal reg_read_data_valid : std_logic;
signal reg_read_strobe, reg_write_strobe : std_logic := '0';
signal reg_error : std_logic := '0';
signal reg_busy, reg_data_valid : std_logic;
signal play_left_accept, play_right_accept : std_logic;
signal PCM_Playback_Left: std_logic_vector(0 to 15) := (others =>'0');
signal PCM_Playback_Right: std_logic_vector(0 to 15) := (others => '0');
signal PCM_Playback_Left_Valid: std_logic;
signal PCM_Playback_Right_Valid: std_logic;
signal PCM_Record_Left: std_logic_vector(0 to 15);
signal PCM_Record_Right: std_logic_vector(0 to 15);
signal PCM_Record_Left_Valid: std_logic;
signal PCM_Record_Right_Valid: std_logic;
signal New_Frame : std_logic;
signal CODEC_RDY : std_logic;
signal test_no : integer;
begin -- behavioral
ac97_reset <= not reset;
model : ac97_model
port map (
AC97Reset_n => ac97_reset,
Bit_Clk => clk,
Sync => sync,
SData_Out => sdata_out,
SData_In => sdata_in
);
uut: ac97_core
port map (
Reset => reset,
-- signals attaching directly to AC97 codec
AC97_Bit_Clk => clk,
AC97_Sync => sync,
AC97_SData_Out => sdata_out,
AC97_SData_In => sdata_in,
AC97_Reg_Addr => reg_addr,
AC97_Reg_Write_Data => reg_write_data,
AC97_Reg_Read_Data => reg_read_data,
AC97_Reg_Read_Strobe => reg_read_strobe, --
AC97_Reg_Write_Strobe => reg_write_strobe, --
AC97_Reg_Busy => reg_busy, --
AC97_Reg_Error => reg_error, -- d
AC97_Reg_Read_Data_Valid => reg_data_valid, -- d
PCM_Playback_Left => PCM_Playback_Left,
PCM_Playback_Right => PCM_Playback_Right,
PCM_Playback_Left_Valid => PCM_Playback_Left_Valid,
PCM_Playback_Right_Valid => PCM_Playback_Right_Valid,
PCM_Playback_Left_Accept => play_left_accept, -- d
PCM_Playback_Right_Accept => play_right_accept, -- d
PCM_Record_Left => PCM_Record_Left,
PCM_Record_Right => PCM_Record_Right,
PCM_Record_Left_Valid => PCM_Record_Left_Valid,
PCM_Record_Right_Valid => PCM_Record_Right_Valid,
CODEC_RDY => CODEC_RDY
);
-- simulate a 20 ns reset pulse
opb_rst_gen: process
begin
reset <= '1';
wait for 20 ns;
reset <= '0';
wait;
end process opb_rst_gen;
-- Test process
register_if_process: process
begin
--PCM_Playback_Right_Valid <= '0';
--PCM_Playback_Left_Valid <= '0';
reg_read_strobe <= '0';
reg_write_strobe <= '0';
reg_addr <= (others => '0');
--PCM_Playback_Left <= (others => '0');
--PCM_Playback_Right <= (others => '0');
-- wait for codec ready
test_no <= 0;
wait until CODEC_RDY='1';
for i in 300 downto 0 loop
wait until clk'event and clk='1';
end loop;
-- Perform a register write (to reset register)
test_no <= 1;
reg_addr <= "0000010";
reg_write_data <= X"A5A5";
wait until clk'event and clk='1';
reg_write_strobe <= '1';
wait until clk'event and clk='1';
reg_write_strobe <= '0';
reg_addr <= "0000000";
reg_write_data <= X"0000";
wait until clk'event and clk='1';
wait until reg_busy = '0';
-- Perform a register read
test_no <= 2;
for i in 300 downto 0 loop
wait until clk'event and clk='1';
end loop;
reg_addr <= "0000010";
wait until clk'event and clk='1';
reg_read_strobe <= '1';
wait until clk'event and clk='1';
reg_read_strobe <= '0';
reg_addr <= "0000000";
wait until clk'event and clk='1';
wait until reg_busy = '0';
test_no <= 3;
-- -- set default values
-- reg_addr <= (others => '0');
-- reg_write_data <= (others => '0');
-- reg_read <= '0';
-- reg_write <= '0';
-- PCM_Playback_Left <= (others => '0');
-- PCM_Playback_Right <= (others => '0');
-- PCM_Playback_Left_Valid <= '0';
-- PCM_Playback_Right_Valid <= '0';
-- -- 1. Wait until CODEC ready before doing anything
-- wait until CODEC_RDY='1' and clk'event and clk='1';
-- -- skip some time slots before performing a bus cycle
-- for i in 300 downto 0 loop
-- wait until clk'event and clk='1';
-- end loop;
-- -- Start at first sync pulse
-- wait until Sync'event and Sync='1';
-- --wait until clk'event and clk='1';
-- wait until clk'event and clk='1';
-- test_no <= 1;
-- -- send some playback data
-- PCM_Playback_Left <= X"8001";
-- PCM_Playback_Right <= X"0180";
-- PCM_Playback_Left_Valid <= '1';
-- PCM_Playback_Right_Valid <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- test_no <= 2;
-- PCM_Playback_Left <= X"4002";
-- PCM_Playback_Right <= X"0240";
-- wait until New_Frame'event and New_Frame='0';
-- test_no <= 3;
-- -- send a read command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_read <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- reg_read <= '0';
-- wait;
-- -- send a write command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_write_data <= X"5A5A";
-- reg_write <= '1';
-- wait until New_Frame'event and New_Frame='0';
wait;
end process;
-- Test process
PCM_Playback_Left_Valid <= '1';
PCM_Playback_Right_Valid <= '1';
play_data_process: process
type register_type is array(0 to 31) of std_logic_vector(15 downto 0);
variable play_data : register_type := (
X"0001", X"0002", X"0004", X"0008", X"0010", X"0020", X"0040", X"0080",
X"0100", X"0200", X"0400", X"0800", X"1000", X"2000", X"4000", X"8000",
X"0001", X"0002", X"0004", X"0008", X"0010", X"0020", X"0040", X"0080",
X"0100", X"0200", X"0400", X"0800", X"1000", X"2000", X"4000", X"8000"
);
variable count : integer := 0;
begin
wait until codec_rdy = '1';
for count in 0 to 31 loop
PCM_Playback_Left <= play_data(count);
PCM_Playback_Right <= play_data(count);
wait until play_left_accept = '1' and
play_right_accept = '1' and clk'event and clk='1';
wait until clk'event and clk='1';
wait until clk'event and clk='1';
end loop;
end process;
-- -- Recording Data
-- sdata_in_proc: process
-- variable slot0 : std_logic_vector(15 downto 0) := "1001100000000000";
-- -- Control address
-- variable slot1 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- Control data
-- variable slot2 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- PCM left (0x69696)
-- variable slot3 : std_logic_vector(19 downto 0) := "01101001011010010110";
-- -- PCM right (0x96969)
-- variable slot4 : std_logic_vector(19 downto 0) := "10010110100101101001";
-- begin
-- sdata_in <= '0';
-- -- 1. Wait until CODEC ready before doing anything
-- wait until CODEC_RDY='1' and clk'event and clk='1';
-- -- skip some time slots before performing a bus cycle
-- for i in 300 downto 0 loop
-- wait until clk'event and clk='1';
-- end loop;
-- -- Start at first sync pulse
-- wait until Sync'event and Sync='1';
-- --wait until clk'event and clk='1';
-- wait until clk'event and clk='1';
-- -- (1) record data
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (2) record data
-- slot3 := X"8001_0";
-- slot4 := X"1234_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (3) record data
-- slot3 := X"4002_0";
-- slot4 := X"2345_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (4) record data & some control data
-- slot3 := X"2004_0";
-- slot4 := X"3456_0";
-- slot0 := "1011100000000000";
-- slot2 := X"FEDC_B";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (5) record data
-- slot3 := X"1008_0";
-- slot4 := X"3456_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- wait;
-- end process;
-- -- Recording Data
-- control_proc: process
-- begin
-- reg_addr <= (others => '0');
-- reg_write_data <= (others => '0');
-- reg_read <= '0';
-- reg_write <= '0';
-- PCM_Playback_Left <= (others => '0');
-- PCM_Playback_Right <= (others => '0');
-- PCM_Playback_Left_Valid <= '0';
-- PCM_Playback_Right_Valid <= '0';
-- -- skip 2 frames
-- for i in 1 downto 0 loop
-- wait until New_Frame'event and New_Frame='0';
-- end loop;
-- -- send some playback data
-- PCM_Playback_Left <= X"8001";
-- PCM_Playback_Right <= X"0180";
-- PCM_Playback_Left_Valid <= '1';
-- PCM_Playback_Right_Valid <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- PCM_Playback_Left <= X"4002";
-- PCM_Playback_Right <= X"0240";
-- wait until New_Frame'event and New_Frame='0';
-- -- send a write command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_write_data <= X"5A5A";
-- reg_write <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- reg_write <= '0';
-- PCM_Playback_Left <= X"1008";
-- PCM_Playback_Right <= X"0810";
-- wait;
-- end process;
end behavioral;
|
gpl-3.0
|
a3f553f40d642c304a9da8af701509c9
| 0.521608 | 3.288116 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/wb_slave_adapter.vhd
| 1 | 6,071 |
-- universal "adapter"
-- pipelined <> classic
-- word-aligned/byte-aligned address
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity wb_slave_adapter is
generic (
g_master_use_struct : boolean;
g_master_mode : t_wishbone_interface_mode;
g_master_granularity : t_wishbone_address_granularity;
g_slave_use_struct : boolean;
g_slave_mode : t_wishbone_interface_mode;
g_slave_granularity : t_wishbone_address_granularity
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- slave port (i.e. wb_slave_adapter is slave)
sl_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
sl_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
sl_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
sl_cyc_i : in std_logic;
sl_stb_i : in std_logic;
sl_we_i : in std_logic;
sl_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
sl_err_o : out std_logic;
sl_rty_o : out std_logic;
sl_ack_o : out std_logic;
sl_stall_o : out std_logic;
sl_int_o : out std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- master port (i.e. wb_slave_adapter is master)
ma_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
ma_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
ma_sel_o : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
ma_cyc_o : out std_logic;
ma_stb_o : out std_logic;
ma_we_o : out std_logic;
ma_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
ma_err_i : in std_logic;
ma_rty_i : in std_logic;
ma_ack_i : in std_logic;
ma_stall_i : in std_logic;
ma_int_i : in std_logic;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out
);
end wb_slave_adapter;
architecture rtl of wb_slave_adapter is
function f_num_byte_address_bits
return integer is
begin
case c_wishbone_data_width is
when 8 => return 0;
when 16 => return 1;
when 32 => return 2;
when 64 => return 3;
when others =>
report "wb_slave_adapter: invalid c_wishbone_data_width (we support 8, 16, 32 and 64)" severity failure;
end case;
return 0;
end f_num_byte_address_bits;
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
type t_fsm_state is (IDLE, WAIT4ACK);
signal fsm_state : t_fsm_state := IDLE;
signal master_in : t_wishbone_master_in;
signal master_out : t_wishbone_master_out;
signal slave_in : t_wishbone_slave_in;
signal slave_out : t_wishbone_slave_out;
signal stored_we : std_logic;
begin -- rtl
gen_slave_use_struct : if (g_slave_use_struct) generate
slave_in <= slave_i;
end generate gen_slave_use_struct;
gen_slave_use_slv : if (not g_slave_use_struct) generate
slave_in.cyc <= sl_cyc_i;
slave_in.stb <= sl_stb_i;
slave_in.we <= sl_we_i;
slave_in.dat <= sl_dat_i;
slave_in.sel <= sl_sel_i;
slave_in.adr <= sl_adr_i;
end generate gen_slave_use_slv;
slave_o <= slave_out;
sl_ack_o <= slave_out.ack;
sl_rty_o <= slave_out.rty;
sl_err_o <= slave_out.err;
sl_stall_o <= slave_out.stall;
sl_dat_o <= slave_out.dat;
sl_int_o <= slave_out.int;
gen_master_use_struct : if (g_master_use_struct) generate
master_in <= master_i;
end generate gen_master_use_struct;
gen_master_use_slv : if (not g_master_use_struct) generate
master_in <= (
ack => ma_ack_i,
rty => ma_rty_i,
err => ma_err_i,
dat => ma_dat_i,
stall => ma_stall_i,
int => ma_int_i);
end generate gen_master_use_slv;
master_o <= master_out;
ma_adr_o <= master_out.adr;
ma_dat_o <= master_out.dat;
ma_sel_o <= master_out.sel;
ma_cyc_o <= master_out.cyc;
ma_stb_o <= master_out.stb;
ma_we_o <= master_out.we;
p_gen_address : process(slave_in, master_out)
begin
if(g_master_granularity = g_slave_granularity) then
master_out.adr <= slave_in.adr;
elsif(g_master_granularity = BYTE) then -- byte->word
master_out.adr <= slave_in.adr(c_wishbone_address_width-f_num_byte_address_bits-1 downto 0)
& f_zeros(f_num_byte_address_bits);
else
master_out.adr <= f_zeros(f_num_byte_address_bits)
& slave_in.adr(c_wishbone_address_width-1 downto f_num_byte_address_bits);
end if;
end process;
P2C : if (g_slave_mode = PIPELINED and g_master_mode = CLASSIC) generate
master_out.stb <= slave_in.stb;
slave_out.stall <= not master_in.ack;
end generate;
C2P : if (g_slave_mode = CLASSIC and g_master_mode = PIPELINED) generate
master_out.stb <= slave_in.stb when fsm_state=IDLE else '0';
slave_out.stall <= '0'; -- classic will ignore this anyway
state_machine : process(clk_sys_i) is
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
fsm_state <= IDLE;
else
case fsm_state is
when IDLE =>
if slave_in.stb ='1' and master_in.stall='0' and master_in.ack='0' then
fsm_state <= WAIT4ACK;
end if;
when WAIT4ACK =>
if master_in.ack='1' then
fsm_state <= IDLE;
end if;
end case;
end if;
end if;
end process;
end generate;
X2X : if (g_slave_mode = g_master_mode) generate
master_out.stb <= slave_in.stb;
slave_out.stall <= master_in.stall;
end generate;
master_out.dat <= slave_in.dat;
master_out.cyc <= slave_in.cyc;
master_out.sel <= slave_in.sel;
master_out.we <= slave_in.we;
slave_out.ack <= master_in.ack;
slave_out.err <= master_in.err;
slave_out.rty <= master_in.rty;
slave_out.dat <= master_in.dat;
slave_out.int <= master_in.int;
end rtl;
|
lgpl-3.0
|
baf9f081a5e03f7cafe8532e8a886608
| 0.608961 | 2.938529 | false | false | false | false |
luebbers/reconos
|
tests/benchmarks/mutex/hw/pcores/hw_task_v1_01_b/hdl/vhdl/hw_task.vhd
| 1 | 3,190 |
------------
-- pcore top level wrapper
-- generated at 2008-02-12 16:14:05.727709 by 'mkhwtask.py hwt_mutex_unlock 1 ../src/hwt_mutex_unlock.vhd'
------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hw_task is
generic (
C_BUS_BURST_AWIDTH : integer := 13; -- Note: This addresses bytes
C_BUS_BURST_DWIDTH : integer := 64;
C_TASK_BURST_AWIDTH : integer := 11; -- this addresses 32Bit words
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif_flat : in std_logic_vector;
o_osif_flat : out std_logic_vector;
-- burst mem interface
i_burstAddr : in std_logic_vector(0 to C_BUS_BURST_AWIDTH-1);
i_burstData : in std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
o_burstData : out std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
i_burstWE : in std_logic;
-- time base
i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end hw_task;
architecture structural of hw_task is
component burst_ram
port (
addra: IN std_logic_VECTOR(10 downto 0);
addrb: IN std_logic_VECTOR(9 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(31 downto 0);
dinb: IN std_logic_VECTOR(63 downto 0);
douta: OUT std_logic_VECTOR(31 downto 0);
doutb: OUT std_logic_VECTOR(63 downto 0);
wea: IN std_logic;
web: IN std_logic
);
end component;
signal o_osif_flat_i : std_logic_vector(0 to 41);
signal i_osif_flat_i : std_logic_vector(0 to 44);
signal o_osif : osif_task2os_t;
signal i_osif : osif_os2task_t;
signal task2burst_Addr : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
signal task2burst_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal burst2task_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal task2burst_WE : std_logic;
signal task2burst_Clk : std_logic;
attribute keep_hierarchy : string;
attribute keep_hierarchy of structural: architecture is "true";
begin
-- connect top level signals
o_osif_flat <= o_osif_flat_i;
i_osif_flat_i <= i_osif_flat;
-- (un)flatten osif records
o_osif_flat_i <= to_std_logic_vector(o_osif);
i_osif <= to_osif_os2task_t(i_osif_flat_i);
-- instantiate user task
hwt_mutex_i : entity hwt_mutex
port map (
clk => clk,
reset => reset,
i_osif => i_osif,
o_osif => o_osif,
o_RAMAddr => task2burst_Addr,
o_RAMData => task2burst_Data,
i_RAMData => burst2task_Data,
o_RAMWE => task2burst_WE,
o_RAMClk => task2burst_Clk,
i_timeBase => i_timeBase
);
burst_ram_i : burst_ram
port map (
addra => task2burst_Addr,
addrb => i_burstAddr(0 to C_BUS_BURST_AWIDTH-1 -3), -- RAM is addressing 64Bit values
clka => task2burst_Clk,
clkb => clk,
dina => task2burst_Data,
dinb => i_burstData,
douta => burst2task_Data,
doutb => o_burstData,
wea => task2burst_WE,
web => i_burstWE
);
end structural;
|
gpl-3.0
|
187be85b25f919e10a5999f40c5d8faa
| 0.66395 | 2.810573 | false | false | false | false |
williammacdowell/gcm
|
src/fpga/mix_columns_ea.vhd
| 1 | 5,887 |
-------------------------------------------------------------------------------
-- Title : Mix Columns
-- Project : AES-GCM
-------------------------------------------------------------------------------
-- File : mix_columns_ea.vhd
-- Author : Bill MacDowell <bill@bill-macdowell-laptop>
-- Company :
-- Created : 2017-03-20
-- Last update: 2017-04-02
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This block implements the MixColumns transformation per the AES
-- Spec in FIPS 197. This transformation treats the 128-bit input block like a
-- 4x4 byte matrix. Each column is operated on individually with the following
-- matrix multiplication:
--
-- Input column: Output column:
-- | S0,c | | 02 03 01 01 | |S'0,c|
-- | S1,c | x | 01 02 03 01 | = |S'1,c|
-- | S2,c | | 01 01 02 03 | |S'2,c|
-- | S3,c | | 03 01 01 02 | |S'3,c|
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-03-20 1.0 bill Created
-------------------------------------------------------------------------------
library ieee;
library work;
use ieee.std_logic_1164.all;
use work.gcm_pkg.all;
entity mix_columns is
port(
clk : in std_logic;
rst : in std_logic;
block_in : in std_logic_vector(127 downto 0);
block_out : out std_logic_vector(127 downto 0));
end entity mix_columns;
architecture rtl of mix_columns is
-- These are for converting the 128-bit vectors to 4x4 byte matricies
signal matrix_in : t_matrix;
signal matrix_out : t_matrix;
-- These are for multiplying the matrix by 2 and 3
type t_shft_matrix is array (15 downto 0) of std_logic_vector(8 downto 0);
signal shift2 : t_shft_matrix;
signal shift3 : t_shft_matrix;
signal matrix_in_x_2 : t_matrix;
signal matrix_in_x_3 : t_matrix;
begin
-- Convert between 128-bit vector and 4x4 byte matrix here. No added logic,
-- just some type conversions to make VHDL happy
v2m : process (block_in) is
begin
matrix_in <= vector_to_matrix(block_in);
end process v2m;
m2v : process (matrix_out) is
begin
block_out <= matrix_to_vector(matrix_out);
end process m2v;
-- This process handles the multiplication by 2 and 3 of each of the elements
-- of the matrix. It also takes care of the mix-columns transformation
mix_columns_proc : process (clk) is
begin
if clk'event and clk = '1' then
-- loop through all the bytes in the matrix
for byte_idx in 15 downto 0 loop
-- 1 shift left covers the multiply by 2. The XOR with matrix_in
-- coveres the multiply by 3 because all we are doing is multiplying by
-- 2 then adding 1. Addition in the finite field is done with XOR
shift2(byte_idx) <= matrix_in(byte_idx) & '0';
shift3(byte_idx) <= (matrix_in(byte_idx) & '0') xor ('0' & matrix_in(byte_idx));
-- Now we need to do conditional XORs by reducing the results above
-- modulo m(x). This only needs to apply to results with MSb = '1'
if shift2(byte_idx)(shift2(byte_idx)'high) = '1' then
matrix_in_x_2(byte_idx) <= shift2(byte_idx)(7 downto 0) xor c_irreducible_polynomial;
else
matrix_in_x_2(byte_idx) <= shift2(byte_idx)(7 downto 0);
end if;
if shift3(byte_idx)(shift3(byte_idx)'high) = '1' then
matrix_in_x_3(byte_idx) <= shift3(byte_idx)(7 downto 0) xor c_irreducible_polynomial;
else
matrix_in_x_3(byte_idx) <= shift3(byte_idx)(7 downto 0);
end if;
end loop;
-- Here just doing matrix multiplication
--row one
matrix_out(0) <= matrix_in_x_2(0) xor matrix_in_x_3(1) xor matrix_in(2) xor matrix_in(3);
matrix_out(4) <= matrix_in_x_2(4) xor matrix_in_x_3(5) xor matrix_in(6) xor matrix_in(7);
matrix_out(8) <= matrix_in_x_2(8) xor matrix_in_x_3(9) xor matrix_in(10) xor matrix_in(11);
matrix_out(12) <= matrix_in_x_2(12) xor matrix_in_x_3(13) xor matrix_in(14) xor matrix_in(15);
--row two
matrix_out(1) <= matrix_in(0) xor matrix_in_x_2(1) xor matrix_in_x_3(2) xor matrix_in(3);
matrix_out(5) <= matrix_in(4) xor matrix_in_x_2(5) xor matrix_in_x_3(6) xor matrix_in(7);
matrix_out(9) <= matrix_in(8) xor matrix_in_x_2(9) xor matrix_in_x_3(10) xor matrix_in(11);
matrix_out(13) <= matrix_in(12) xor matrix_in_x_2(13) xor matrix_in_x_3(14) xor matrix_in(15);
--row three
matrix_out(2) <= matrix_in(0) xor matrix_in(1) xor matrix_in_x_2(2) xor matrix_in_x_3(3);
matrix_out(6) <= matrix_in(4) xor matrix_in(5) xor matrix_in_x_2(6) xor matrix_in_x_3(7);
matrix_out(10) <= matrix_in(8) xor matrix_in(9) xor matrix_in_x_2(10) xor matrix_in_x_3(11);
matrix_out(14) <= matrix_in(12) xor matrix_in(13) xor matrix_in_x_2(14) xor matrix_in_x_3(15);
--row four
matrix_out(3) <= matrix_in_x_3(0) xor matrix_in(1) xor matrix_in(2) xor matrix_in_x_2(3);
matrix_out(7) <= matrix_in_x_3(4) xor matrix_in(5) xor matrix_in(6) xor matrix_in_x_2(7);
matrix_out(11) <= matrix_in_x_3(8) xor matrix_in(9) xor matrix_in(10) xor matrix_in_x_2(11);
matrix_out(15) <= matrix_in_x_3(12) xor matrix_in(13) xor matrix_in(14) xor matrix_in_x_2(15);
if rst = '1' then
matrix_out <= (others => (others => '0'));
shift2 <= (others => (others => '0'));
shift3 <= (others => (others => '0'));
matrix_in_x_2 <= (others => (others => '0'));
matrix_in_x_3 <= (others => (others => '0'));
end if;
end if;
end process;
end rtl;
|
gpl-3.0
|
62360a914834d11ad623c7d41da352cd
| 0.558859 | 3.148128 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/inferred_async_fifo.vhd
| 2 | 9,492 |
-------------------------------------------------------------------------------
-- Title : Parametrizable asynchronous FIFO (Generic version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_async_fifo.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2014-07-31
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Dual-clock asynchronous FIFO.
-- - configurable data width and size
-- - configurable full/empty/almost full/almost empty/word count signals
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.gencores_pkg.all;
entity inferred_async_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_rd_empty : boolean := true; -- with empty flag
g_with_rd_full : boolean := false; -- with full flag
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false; -- with words counter
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer -- threshold for almost full flag
);
port (
rst_n_i : in std_logic := '1';
-- write port
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic; -- TODO: assign
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- read port
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic; -- TODO: assign
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
end inferred_async_fifo;
architecture syn of inferred_async_fifo is
function f_bin2gray(bin : std_logic_vector) return std_logic_vector is
begin
return bin(bin'left) & (bin(bin'left-1 downto 0) xor bin(bin'left downto 1));
end f_bin2gray;
function f_gray2bin(gray : std_logic_vector) return std_logic_vector is
variable bin : std_logic_vector(gray'left downto 0);
begin
-- gray to binary
for i in 0 to gray'left loop
bin(i) := '0';
for j in i to gray'left loop
bin(i) := bin(i) xor gray(j);
end loop; -- j
end loop; -- i
return bin;
end f_gray2bin;
constant c_counter_bits : integer := f_log2_size(g_size) + 1;
subtype t_counter is std_logic_vector(c_counter_bits-1 downto 0);
type t_counter_block is record
bin, bin_next, gray, gray_next : t_counter;
bin_x, gray_x, gray_xm : t_counter;
end record;
type t_mem_type is array (0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
signal mem : t_mem_type;
signal rcb, wcb : t_counter_block;
signal full_int, empty_int : std_logic;
signal almost_full_int, almost_empty_int : std_logic;
signal going_full : std_logic;
signal wr_count, rd_count : t_counter;
signal rd_int, we_int : std_logic;
signal wr_empty_xm, wr_empty_x : std_logic;
signal rd_full_xm, rd_full_x : std_logic;
signal almost_full_x, almost_full_xm : std_logic;
signal almost_empty_x, almost_empty_xm : std_logic;
begin -- syn
rd_int <= rd_i and not empty_int;
we_int <= we_i and not full_int;
p_mem_write : process(clk_wr_i)
begin
if rising_edge(clk_wr_i) then
if(we_int = '1') then
mem(to_integer(unsigned(wcb.bin(wcb.bin'left-1 downto 0)))) <= d_i;
end if;
end if;
end process;
p_mem_read : process(clk_rd_i)
begin
if rising_edge(clk_rd_i) then
if(rd_int = '1') then
q_o <= mem(to_integer(unsigned(rcb.bin(rcb.bin'left-1 downto 0))));
end if;
end if;
end process;
wcb.bin_next <= std_logic_vector(unsigned(wcb.bin) + 1);
wcb.gray_next <= f_bin2gray(wcb.bin_next);
p_write_ptr : process(clk_wr_i, rst_n_i)
begin
if rst_n_i = '0' then
wcb.bin <= (others => '0');
wcb.gray <= (others => '0');
elsif rising_edge(clk_wr_i) then
if(we_int = '1') then
wcb.bin <= wcb.bin_next;
wcb.gray <= wcb.gray_next;
end if;
end if;
end process;
rcb.bin_next <= std_logic_vector(unsigned(rcb.bin) + 1);
rcb.gray_next <= f_bin2gray(rcb.bin_next);
p_read_ptr : process(clk_rd_i, rst_n_i)
begin
if rst_n_i = '0' then
rcb.bin <= (others => '0');
rcb.gray <= (others => '0');
elsif rising_edge(clk_rd_i) then
if(rd_int = '1') then
rcb.bin <= rcb.bin_next;
rcb.gray <= rcb.gray_next;
end if;
end if;
end process;
U_Sync1: gc_sync_register
generic map (
g_width => c_counter_bits)
port map (
clk_i => clk_wr_i,
rst_n_a_i => rst_n_i,
d_i => rcb.gray,
q_o => rcb.gray_x);
U_Sync2: gc_sync_register
generic map (
g_width => c_counter_bits)
port map (
clk_i => clk_rd_i,
rst_n_a_i => rst_n_i,
d_i => wcb.gray,
q_o => wcb.gray_x);
wcb.bin_x <= f_gray2bin(wcb.gray_x);
rcb.bin_x <= f_gray2bin(rcb.gray_x);
p_gen_empty : process(clk_rd_i, rst_n_i)
begin
if rst_n_i = '0' then
empty_int <= '1';
elsif rising_edge (clk_rd_i) then
if(rcb.gray = wcb.gray_x or (rd_int = '1' and (wcb.gray_x = rcb.gray_next))) then
empty_int <= '1';
else
empty_int <= '0';
end if;
end if;
end process;
U_Sync_Empty: gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_wr_i,
rst_n_i => rst_n_i,
data_i => empty_int,
synced_o => wr_empty_x);
U_Sync_Full: gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_rd_i,
rst_n_i => rst_n_i,
data_i => full_int,
synced_o => rd_full_x);
rd_empty_o <= empty_int;
wr_empty_o <= wr_empty_x;
p_gen_going_full : process(we_int, wcb, rcb)
begin
if ((wcb.bin (wcb.bin'left-1 downto 0) = rcb.bin_x(rcb.bin_x'left-1 downto 0))
and (wcb.bin(wcb.bin'left) /= rcb.bin_x(wcb.bin_x'left))) then
going_full <= '1';
elsif (we_int = '1'
and (wcb.bin_next(wcb.bin'left-1 downto 0) = rcb.bin_x(rcb.bin_x'left-1 downto 0))
and (wcb.bin_next(wcb.bin'left) /= rcb.bin_x(rcb.bin_x'left))) then
going_full <= '1';
else
going_full <= '0';
end if;
end process;
p_register_full : process(clk_wr_i, rst_n_i)
begin
if rst_n_i = '0' then
full_int <= '0';
elsif rising_edge (clk_wr_i) then
full_int <= going_full;
end if;
end process;
wr_full_o <= full_int;
rd_full_o <= rd_full_x;
p_reg_almost_full : process(clk_wr_i, rst_n_i)
begin
if rst_n_i = '0' then
almost_full_int <= '0';
elsif rising_edge(clk_wr_i) then
wr_count <= std_logic_vector(unsigned(wcb.bin) - unsigned(rcb.bin_x));
if (unsigned(wr_count) >= g_almost_full_threshold) then
almost_full_int <= '1';
else
almost_full_int <= '0';
end if;
end if;
end process;
U_Sync_AlmostFull: gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_rd_i,
rst_n_i => rst_n_i,
data_i => almost_full_int,
synced_o => almost_full_x);
wr_almost_full_o <= almost_full_int;
rd_almost_full_o <= almost_full_x;
p_reg_almost_empty : process(clk_rd_i, rst_n_i)
begin
if rst_n_i = '0' then
almost_empty_int <= '1';
elsif rising_edge(clk_rd_i) then
rd_count <= std_logic_vector(unsigned(wcb.bin_x) - unsigned(rcb.bin));
if (unsigned(rd_count) <= g_almost_empty_threshold) then
almost_empty_int <= '1';
else
almost_empty_int <= '0';
end if;
end if;
end process;
U_Sync_AlmostEmpty: gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_wr_i,
rst_n_i => rst_n_i,
data_i => almost_empty_int,
synced_o => almost_empty_x);
rd_almost_empty_o <= almost_empty_int;
wr_almost_empty_o <= almost_empty_x;
wr_count_o <= std_logic_vector(wr_count(f_log2_size(g_size)-1 downto 0));
rd_count_o <= std_logic_vector(rd_count(f_log2_size(g_size)-1 downto 0));
end syn;
|
lgpl-3.0
|
7b4a591591a39260427be04663272c66
| 0.544775 | 3.028717 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/AudioDemo.vhd
| 1 | 20,037 |
----------------------------------------------------------------------------
-- Author: Mihaita Nagy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 15:45:01 02/10/2014
-- Design Name:
-- Module Name: AudioDemo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- Description:
-- This module represents the Audio Demo for the Nexys4 DDR onboard ADMP421 Omnidirectional Microphone
-- The module consists of several components:
-- - Deserializer, module name PdmDes, that generates the pdm_clk signal for the microphone,
-- receives the microphone data and deserializes it in 16-bit samples. No PDM decoding is done
--
-- - RAM controller, module name RamCntrl, that emulates a RAM Memory Controller and writes the samples to,
-- or reads from a RAM Memory.
--
-- - RAM to DDR interface and DDR controller, module name Ram2Ddr, that creates a RAM-style interface
-- for the Nexys4 onboard Micron MT47H64M16HR-25 1Gb (64M X 16) DDR2 memory. The DDR interface was generated
-- using Memory Interface Generator (MIG) v 1.9. The Ram2Ddr component is controlled by the RamCntrl controller
-- described above and can be also used separately as a memory solution for ISE designs
--
-- - Serializer, module name PdmSer, that receives the samples read from the memory, deserializes and
-- sends the PDM modulated data to the Sallen-Key Butterworth Low Pass 4th Order Filter, from where
-- audio can be listened on the Mono Audio Out connector (J8)
--
-- - Led-Bar, module name LedBar, that generates the progressbar on LD15..LD0 which moves to left
-- when recording ands to right when playing back
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity AudioDemo is
port (
-- Common
clk_i : in std_logic;
clk_200_i : in std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
rst_i : in std_logic;
-- Peripherals
btn_u : in std_logic;
leds_o : out std_logic_vector(15 downto 0);
-- Microphone PDM signals
pdm_m_clk_o : out std_logic; -- Output M_CLK signal to the microphone
pdm_m_data_i : in std_logic; -- Input PDM data from the microphone
pdm_lrsel_o : out std_logic; -- Set to '0', therefore data is read on the positive edge
-- Audio output signals
pwm_audio_o : inout std_logic; -- Output Audio data to the lowpass filters
pwm_sdaudio_o : out std_logic; -- Output Audio enable
-- DDR2 interface
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
pdm_clk_rising_o : out std_logic -- Signaling the rising edge of M_CLK, used by the MicDisplay
-- component in the VGA controller
);
end AudioDemo;
architecture Behavioral of AudioDemo is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
component Dbncr is
generic(
NR_OF_CLKS : integer := 4095);
port(
clk_i : in std_logic;
sig_i : in std_logic;
pls_o : out std_logic);
end component;
-- deserializer
component PdmDes is
generic(
C_NR_OF_BITS : integer := 16;
C_SYS_CLK_FREQ_MHZ : integer := 100;
C_PDM_FREQ_HZ : integer := 2000000
);
port(
clk_i : in std_logic;
en_i : in std_logic; -- Enable deserializing (during record)
done_o : out std_logic; -- Signaling that 16 bits are deserialized
data_o : out std_logic_vector(C_NR_OF_BITS - 1 downto 0); -- output deserialized data
-- PDM
pdm_m_clk_o : out std_logic; -- Output M_CLK signal to the microphone
pdm_m_data_i : in std_logic; -- Input PDM data from the microphone
pdm_lrsel_o : out std_logic; -- Set to '0', therefore data is read on the positive edge
pdm_clk_rising_o : out std_logic -- Signaling the rising edge of M_CLK, used by the MicDisplay
-- component in the VGA controller
);
end component;
-- RAM Controller
component RamCntrl is
generic (
-- read/write cycle (ns)
C_RW_CYCLE_NS : integer := 100
);
port (
-- Control interface
clk_i : in std_logic; -- 100 MHz system clock
rst_i : in std_logic; -- active high system reset
rnw_i : in std_logic; -- read/write
be_i : in std_logic_vector(3 downto 0); -- byte enable
addr_i : in std_logic_vector(31 downto 0); -- address input
data_i : in std_logic_vector(31 downto 0); -- data input
cs_i : in std_logic; -- active high chip select
data_o : out std_logic_vector(31 downto 0); -- data output
rd_ack_o : out std_logic; -- read acknowledge flag
wr_ack_o : out std_logic; -- write acknowledge flag
-- RAM Memory signals
Mem_A : out std_logic_vector(26 downto 0); -- Address
Mem_DQ_O : out std_logic_vector(15 downto 0); -- Data Out
Mem_DQ_I : in std_logic_vector(15 downto 0); -- Data In
Mem_DQ_T : out std_logic_vector(15 downto 0); -- Data Tristate Enable, used for a bidirectional data bus only
Mem_CEN : out std_logic; -- Chip Enable
Mem_OEN : out std_logic; -- Output Enable
Mem_WEN : out std_logic; -- Write Enable
Mem_UB : out std_logic; -- Upper Byte
Mem_LB : out std_logic -- Lower Byte
);
end component;
-- RAM to DDR interface and DDR Controller
component Ram2Ddr is
port (
-- Common
clk_200MHz_i : in std_logic; -- 200 MHz system clock
rst_i : in std_logic; -- active high system reset
device_temp_i : in std_logic_vector(11 downto 0);
-- RAM interface
ram_a : in std_logic_vector(26 downto 0);
ram_dq_i : in std_logic_vector(15 downto 0);
ram_dq_o : out std_logic_vector(15 downto 0);
ram_cen : in std_logic;
ram_oen : in std_logic;
ram_wen : in std_logic;
ram_ub : in std_logic;
ram_lb : in std_logic;
-- DDR2 interface
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0));
end component;
-- pdm serializer
component PdmSer is
generic(
C_NR_OF_BITS : integer := 16;
C_SYS_CLK_FREQ_MHZ : integer := 100;
C_PDM_FREQ_HZ : integer := 2000000
);
port(
clk_i : in std_logic;
en_i : in std_logic; -- Enable serializing (during playback)
done_o : out std_logic; -- Signaling that data_i is sent
data_i : in std_logic_vector(C_NR_OF_BITS - 1 downto 0); -- input data
-- PWM
pwm_audio_o : inout std_logic -- Output audio data
);
end component;
-- led-bar
component LedBar is
generic(
C_SYS_CLK_FREQ_MHZ : integer := 100;
C_SECONDS_TO_RECORD : integer := 3);
port(
clk_i : in std_logic; -- system clock
en_i : in std_logic; -- active-high enable
rnl_i : in std_logic; -- Right/Left shift select
leds_o : out std_logic_vector(15 downto 0)); -- output LED bus
end component;
------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------
constant SECONDS_TO_RECORD : integer := 5;
constant PDM_FREQ_HZ : integer := 2000000;
constant SYS_CLK_FREQ_MHZ : integer := 100;
constant NR_OF_BITS : integer := 16;
constant NR_SAMPLES_TO_REC : integer := (((SECONDS_TO_RECORD*PDM_FREQ_HZ)/NR_OF_BITS) - 1);
constant RW_CYCLE_NS : integer := 1200;
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
type state_type is (stIdle, stRecord, stInter, stPlayback);
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal state, next_state : state_type;
-- common
signal btnu_int : std_logic;
signal rnw_int : std_logic;
signal addr_int : std_logic_vector(31 downto 0);
signal done_int : std_logic;
signal pwm_audio_o_int : std_logic;
-- record
signal en_des : std_logic;
signal done_des : std_logic;
signal done_async_des : std_logic;
signal data_des : std_logic_vector(15 downto 0) := (others => '0');
signal data_dess : std_logic_vector(31 downto 0) := (others => '0');
signal addr_rec : std_logic_vector(31 downto 0) := (others => '0');
signal cntRecSamples : integer := 0;
signal done_des_dly : std_logic;
-- playback
signal en_ser : std_logic;
signal done_ser : std_logic;
signal rd_ack_int : std_logic;
signal data_ser : std_logic_vector(31 downto 0);
signal data_serr : std_logic_vector(15 downto 0);
signal done_async_ser : std_logic;
signal addr_play : std_logic_vector(31 downto 0) := (others => '0');
signal cntPlaySamples : integer := 0;
signal done_ser_dly : std_logic;
-- led-bar
signal en_leds : std_logic;
signal rnl_int : std_logic;
-- memory interconnection signals
signal mem_a : std_logic_vector(26 downto 0);
signal mem_a_int : std_logic_vector(26 downto 0);
signal mem_dq_i : std_logic_vector(15 downto 0);
signal mem_dq_o : std_logic_vector(15 downto 0);
signal mem_cen : std_logic;
signal mem_oen : std_logic;
signal mem_wen : std_logic;
signal mem_ub : std_logic;
signal mem_lb : std_logic;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
Btnu: Dbncr
generic map(
NR_OF_CLKS => 4095)
port map(
clk_i => clk_i,
sig_i => btn_u,
pls_o => btnu_int);
------------------------------------------------------------------------
-- Deserializer
------------------------------------------------------------------------
Deserializer: PdmDes
generic map(
C_NR_OF_BITS => NR_OF_BITS,
C_SYS_CLK_FREQ_MHZ => SYS_CLK_FREQ_MHZ,
C_PDM_FREQ_HZ => PDM_FREQ_HZ)
port map(
clk_i => clk_i,
en_i => en_des,
done_o => done_async_des,
data_o => data_des,
pdm_m_clk_o => pdm_m_clk_o,
pdm_m_data_i => pdm_m_data_i,
pdm_lrsel_o => pdm_lrsel_o,
pdm_clk_rising_o => pdm_clk_rising_o
);
------------------------------------------------------------------------
-- Memory
------------------------------------------------------------------------
RAM: RamCntrl
generic map (
C_RW_CYCLE_NS => RW_CYCLE_NS)
port map (
clk_i => clk_i,
rst_i => rst_i,
rnw_i => rnw_int,
be_i => "0011", -- 16-bit access
addr_i => addr_int,
data_i => data_dess,
cs_i => done_int,
data_o => data_ser,
rd_ack_o => rd_ack_int,
wr_ack_o => open,
-- RAM Memory signals
Mem_A => mem_a,
Mem_DQ_O => mem_dq_i,
Mem_DQ_I => mem_dq_o,
Mem_DQ_T => open,
Mem_CEN => mem_cen,
Mem_OEN => mem_oen,
Mem_WEN => mem_wen,
Mem_UB => mem_ub,
Mem_LB => mem_lb
);
DDR: Ram2Ddr
port map (
clk_200MHz_i => clk_200_i,
rst_i => rst_i,
device_temp_i => device_temp_i,
-- RAM interface
ram_a => mem_a,
ram_dq_i => mem_dq_i,
ram_dq_o => mem_dq_o,
ram_cen => mem_cen,
ram_oen => mem_oen,
ram_wen => mem_wen,
ram_ub => mem_ub,
ram_lb => mem_lb,
-- DDR2 interface
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n
);
done_int <= done_des when state = stRecord else
done_ser when state = stPlayback else '0';
------------------------------------------------------------------------
-- Serializer
------------------------------------------------------------------------
process(clk_i)
begin
if rising_edge(clk_i) then
if rd_ack_int = '1' then
data_serr <= data_ser(15 downto 0);
end if;
-- done deserializer
done_des <= done_async_des;
-- deserialized data
data_dess <= x"0000" & data_des;
-- done serializer
done_ser <= done_async_ser;
end if;
end process;
Serializer: PdmSer
generic map(
C_NR_OF_BITS => NR_OF_BITS,
C_SYS_CLK_FREQ_MHZ => SYS_CLK_FREQ_MHZ,
C_PDM_FREQ_HZ => PDM_FREQ_HZ)
port map(
clk_i => clk_i,
en_i => en_ser,
done_o => done_async_ser,
data_i => data_serr,
pwm_audio_o => pwm_audio_o
);
-- count the recorded samples
process(clk_i)
begin
if rising_edge(clk_i) then
if state = stRecord then
if done_des = '1' then
cntRecSamples <= cntRecSamples + 1;
end if;
if done_des_dly = '1' then
addr_rec <= addr_rec + "10";
end if;
else
cntRecSamples <= 0;
addr_rec <= (others => '0');
end if;
done_des_dly <= done_des;
end if;
end process;
-- count the played samples
process(clk_i)
begin
if rising_edge(clk_i) then
if state = stPlayback then
if done_ser = '1' then
cntPlaySamples <= cntPlaySamples + 1;
end if;
if done_ser_dly = '1' then
addr_play <= addr_play + "10";
end if;
else
cntPlaySamples <= 0;
addr_play <= (others => '0');
end if;
done_ser_dly <= done_ser;
end if;
end process;
------------------------------------------------------------------------
-- FSM
------------------------------------------------------------------------
SYNC_PROC: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
state <= stIdle;
else
state <= next_state;
end if;
end if;
end process;
--Decode Outputs from the State Machine
OUTPUT_DECODE: process(clk_i)
begin
if rising_edge(clk_i) then
case (state) is
when stIdle =>
rnw_int <= '0';
en_ser <= '0';
en_des <= '0';
addr_int <= (others => '0');
en_leds <= '0';
rnl_int <= '0';
pwm_sdaudio_o <= '1';
when stRecord =>
rnw_int <= '0';
en_ser <= '0';
en_des <= '1';
addr_int <= addr_rec;
en_leds <= '1';
rnl_int <= '1';
pwm_sdaudio_o <= '1';
when stInter =>
rnw_int <= '0';
en_ser <= '0';
en_des <= '0';
addr_int <= (others => '0');
en_leds <= '0';
rnl_int <= '0';
pwm_sdaudio_o <= '1';
when stPlayback =>
rnw_int <= '1';
en_ser <= '1';
en_des <= '0';
addr_int <= addr_play;
en_leds <= '1';
rnl_int <= '0';
pwm_sdaudio_o <= '1';
when others =>
rnw_int <= '0';
en_ser <= '0';
en_des <= '0';
addr_int <= (others => '0');
en_leds <= '0';
rnl_int <= '0';
pwm_sdaudio_o <= '1';
end case;
end if;
end process;
NEXT_STATE_DECODE: process(state, btnu_int, cntRecSamples, cntPlaySamples)
begin
next_state <= state;
case (state) is
when stIdle =>
if btnu_int = '1' then
next_state <= stRecord;
end if;
when stRecord =>
if cntRecSamples = NR_SAMPLES_TO_REC then
next_state <= stInter;
end if;
when stInter =>
next_state <= stPlayback;
when stPlayback =>
if btnu_int = '1' then
next_state <= stIdle;
elsif cntPlaySamples = NR_SAMPLES_TO_REC then
next_state <= stIdle;
end if;
when others =>
next_state <= stIdle;
end case;
end process;
------------------------------------------------------------------------
-- LED-bar display
------------------------------------------------------------------------
Leds: LedBar
generic map(
C_SYS_CLK_FREQ_MHZ => SYS_CLK_FREQ_MHZ,
C_SECONDS_TO_RECORD => SECONDS_TO_RECORD)
port map(
clk_i => clk_i,
en_i => en_leds,
rnl_i => rnl_int,
leds_o => leds_o);
end Behavioral;
|
gpl-3.0
|
87e6438db5c70dc6fddc5fc0eef9edf1
| 0.469981 | 3.802809 | false | false | false | false |
luebbers/reconos
|
demos/particle_filter_framework/hw/src/framework/resampling_old.vhd
| 1 | 15,689 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use IEEE.STD_LOGIC_ARITH.all;
--use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v1_03_a;
use reconos_v1_03_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity resampling is
generic (
C_TASK_BURST_AWIDTH : integer := 11;
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end resampling;
architecture Behavioral of resampling is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- resources:
-- semaphores
constant C_SEM_WAIT : std_logic_vector(0 to 31) := X"00000000";
constant C_SEM_POST : std_logic_vector(0 to 31) := X"00000001";
-- message box
constant C_MB_START : std_logic_vector(0 to 31) := X"00000002";
constant GRANULARITY :integer := 16384;
-- states
type t_state is (STATE_INIT, STATE_GET_MB, STATE_READ_N_1, STATE_READ_N_2,
STATE_READ_PARTICLE_SIZE_1, STATE_READ_PARTICLE_SIZE_2,
STATE_SEM_WAIT, STATE_LOAD_PARTICLE, STATE_LOAD_W, STATE_CALCULATE_BEST_PARTICLE,
STATE_RESAMPLING, STATE_LOAD_WEIGHT, STATE_CALCULATE_CLONE_FACTOR_1,
STATE_CALCULATE_CLONE_FACTOR_2, STATE_CALCULATE_CLONE_FACTOR_3, STATE_CALCULATE_CLONE_FACTOR_4,
STATE_CLONE_PARTICLE, STATE_CLONE_PARTICLE_READ, STATE_CLONE_PARTICLE_WRITE,
STATE_CORRECTION_READ, STATE_CORRECTION, STATE_CORRECTION_WRITE, STATE_SEM_POST);
-- current state
signal state : t_state := STATE_SEM_WAIT;
-- input, output
signal in_value : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal out_value : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- particle array
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal current_particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- old particle array
signal old_particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal current_old_particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- message box
signal mb_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of particles (set by message box, default = 100)
signal N : integer := 100;
-- size of a particle
signal particle_size : integer := 128;
-- particle counter
signal counter : integer;
-- particle counter for clone factor
signal counter_clone_factor : integer;
-- particle counter for cloned particles at all
signal counter_cloned_particles : integer;
-- current particle weight
signal current_particle_weight : integer;
-- sum of particle weights
signal sum_of_particle_weights : integer;
-- current clone factor
signal current_clone_factor : integer;
-- best particle
signal best_particle_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal highest_particle_weight : integer;
--signal init_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
-- burst ram interface is not used
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWE <= '0';
o_RAMClk <= clk;
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
-- success signal for Reconos method, which gets a message box
variable success : boolean;
-- signals for particle weight, N, particle_size and old_particle_array_address
variable particle_weight_sig : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable N_sig : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_sig : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable old_particle_array_address_sig : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
--variable factor : integer;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_INIT;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_INIT =>
--! init state, receive particle array address
reconos_get_init_data_s (done, o_osif, i_osif, particle_array_address);
if done then
state <= STATE_GET_MB;
--state <= STATE_SEM_WAIT;
end if;
when STATE_GET_MB =>
--! receive message box
--reconos_mbox_get_s(done, success, o_osif, i_osif, C_MB_START, mb_address);
reconos_mbox_get_s(done, success, o_osif, i_osif, C_MB_START, old_particle_array_address);
if done then
--old_particle_array_address <= mb_address;
state <= STATE_READ_N_1;
end if;
when STATE_READ_N_1 =>
--! read variable N (= # of particles)
reconos_mbox_get_s (done, success, o_osif, i_osif, C_MB_START, mb_address);
if done then
state <= STATE_READ_N_2;
end if;
when STATE_READ_N_2 =>
--! read variable N (= # of particles)
reconos_read (done, o_osif, i_osif, mb_address, N_sig);
if done then
N <= TO_INTEGER(SIGNED(N_sig));
state <= STATE_READ_PARTICLE_SIZE_1;
end if;
when STATE_READ_PARTICLE_SIZE_1 =>
--! read particle size
reconos_mbox_get_s (done, success, o_osif, i_osif, C_MB_START, mb_address);
if done then
state <= STATE_READ_PARTICLE_SIZE_2;
end if;
when STATE_READ_PARTICLE_SIZE_2 =>
--! read particle size
reconos_read (done, o_osif, i_osif, mb_address, particle_size_sig);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_sig));
state <= STATE_SEM_WAIT;
end if;
when STATE_SEM_WAIT =>
--! wait for semaphore
reconos_sem_wait (o_osif, i_osif, C_SEM_WAIT);
state <= STATE_LOAD_PARTICLE;
--state <= STATE_SEM_POST;
when STATE_LOAD_PARTICLE =>
--! set current array addresses to the first elements in the arrays
-- and init sum of weights
current_old_particle_array_address <= old_particle_array_address;
current_particle_array_address <= particle_array_address;
--sum_of_particle_weights <= 0;
counter <= 0;
highest_particle_weight <= 0;
best_particle_address <= old_particle_array_address;
state <= STATE_LOAD_W;
--state <= STATE_RESAMPLING;
when STATE_LOAD_W =>
--! load weight of current particle
reconos_read(done, o_osif, i_osif, current_old_particle_array_address, particle_weight_sig);
if done then
state <= STATE_CALCULATE_BEST_PARTICLE;
current_particle_weight <= TO_INTEGER(SIGNED(particle_weight_sig));
counter <= counter + 1;
end if;
when STATE_CALCULATE_BEST_PARTICLE =>
--! calculate the sum of all particle weights
--sum_of_particle_weights <= sum_of_particle_weights + current_particle_weight;
if (current_particle_weight > highest_particle_weight) then
-- remember best position
highest_particle_weight <= current_particle_weight;
best_particle_address <= current_old_particle_array_address;
end if;
if (counter < N) then
current_old_particle_array_address <= current_old_particle_array_address + particle_size;
state <= STATE_LOAD_W;
else
state <= STATE_RESAMPLING;
--state <= STATE_SEM_POST;
end if;
--
-- THE RESAMPLING PART IN DETAIL
--
-- 0) STATE_RESAMPLING:
--
-- init addresses and counter
-- i = 0; // old_particles
-- k = 0; // particles
--
--
-- 1) STATE_LOAD_WEIGHT:
--
-- load weight of i-th old particle
-- i++
--
--
-- 2) STATE_CALCULATE_CLONE_FACTOR
--
-- calculate clone factor = round (w * N / sum_weights)
-- j = 0; // clone factor counter
--
--
-- 3) STATE_CLONE_PARTICLE
--
-- if (i > N) then
--
-- if (k < N) then
-- go to step 6 // not enough particles cloned, but no more old particles
-- else
-- go to end // enough particles cloned
-- end if
--
-- elsif (N <= k) then
--
-- go to end // enough particles cloned
--
-- elsif (clone_factor <= j)
--
-- go to step 1 // no more cloning needed for this particle, get next
--
-- elsif (j < clone_factor)
--
-- if (j == 0)
--
-- go to step 4 // first load particle to local RAM
--
-- else
--
-- go to step 5 // particle allready loaded to local RAM
--
-- end if
--
-- end if
--
--
-- 4) STATE_CLONE_PARTICLE_READ
--
-- read old particle [i] to local RAM
--
--
-- 5) STATE_CLONE_PARTICLE_WRITE
--
-- write local RAM to particle [k]
-- k++
-- j++
-- go to step 3
--
--
-- 6) STATE_CORRECTION_READ
--
-- read best particle to local RAM
--
--
-- 7) STATE_CORRECTION
--
-- if (k <= N) then
-- go to step 8
-- else
-- go to end
-- end if
--
--
-- 8) STATE_CORRECTION_WRITE
--
-- write best particle to particles[k];
-- k++;
-- go to step 7
when STATE_RESAMPLING =>
--! init counter and array addresses
current_old_particle_array_address <= old_particle_array_address;
current_particle_array_address <= particle_array_address;
counter <= 0;
counter_cloned_particles <= 0;
state <= STATE_LOAD_WEIGHT;
when STATE_LOAD_WEIGHT =>
--! load weight of current particle
reconos_read(done, o_osif, i_osif, current_old_particle_array_address, particle_weight_sig);
if done then
state <= STATE_CALCULATE_CLONE_FACTOR_1;
current_particle_weight <= TO_INTEGER(SIGNED(particle_weight_sig));
counter <= counter + 1;
end if;
when STATE_CALCULATE_CLONE_FACTOR_1 =>
--! calculate the factor the current particle has to be cloned
current_clone_factor <= 2 * N * current_particle_weight;
state <= STATE_CALCULATE_CLONE_FACTOR_2;
when STATE_CALCULATE_CLONE_FACTOR_2 =>
--! calculate the factor the current particle has to be cloned
current_clone_factor <= current_clone_factor / GRANULARITY;
state <= STATE_CALCULATE_CLONE_FACTOR_3;
when STATE_CALCULATE_CLONE_FACTOR_3 =>
--! calculate the factor the current particle has to be cloned
current_clone_factor <= current_clone_factor + 1;
state <= STATE_CALCULATE_CLONE_FACTOR_4;
when STATE_CALCULATE_CLONE_FACTOR_4 =>
--! calculate the factor the current particle has to be cloned
current_clone_factor <= current_clone_factor / 2;
counter_clone_factor <= 0;
state <= STATE_CLONE_PARTICLE;
when STATE_CLONE_PARTICLE =>
--! clone partice as often as needed
if (counter > N) then
if (counter_cloned_particles < N) then
-- there are not enough clones, so correct it
state <= STATE_CORRECTION_READ;
--state <= STATE_SEM_POST;
else
-- everything finished, because there are enough clones
state <= STATE_SEM_POST;
end if;
elsif (N <= counter_cloned_particles) then
-- everything finished, because there are enough clones
state <= STATE_SEM_POST;
elsif (current_clone_factor <= counter_clone_factor) then
-- get next particle
state <= STATE_LOAD_WEIGHT;
current_old_particle_array_address <= current_old_particle_array_address + particle_size;
elsif (counter_clone_factor < current_clone_factor) then
if (counter_clone_factor = 0) then
-- first load the particle to local RAM
state <= STATE_CLONE_PARTICLE_READ;
else
-- later, the particles can be just written
state <= STATE_CLONE_PARTICLE_WRITE;
end if;
end if;
when STATE_CLONE_PARTICLE_READ =>
--! load old particles [counter] to local RAM
reconos_read_burst(done, o_osif, i_osif, local_ram_address, current_old_particle_array_address);
if done then
state <= STATE_CLONE_PARTICLE_WRITE;
end if;
when STATE_CLONE_PARTICLE_WRITE =>
--! write particles [counter_cloned_particles] from RAM
reconos_write_burst(done, o_osif, i_osif, local_ram_address, current_particle_array_address);
if done then
state <= STATE_CLONE_PARTICLE;
counter_clone_factor <= counter_clone_factor + 1;
counter_cloned_particles <= counter_cloned_particles + 1;
current_particle_array_address <= current_particle_array_address + particle_size;
end if;
when STATE_CORRECTION_READ =>
--! load best particle
--reconos_read_burst(done, o_osif, i_osif, local_ram_address, old_particle_array_address);
reconos_read_burst(done, o_osif, i_osif, local_ram_address, best_particle_address);
if done then
state <= STATE_CORRECTION;
end if;
when STATE_CORRECTION =>
--! if less than N particles are cloned, clone another particle (the best one)
if (counter_cloned_particles <= N) then
-- write correction
state <= STATE_CORRECTION_WRITE;
else
-- correction finished, N particles are cloned
state <= STATE_SEM_POST;
end if;
when STATE_CORRECTION_WRITE =>
--! CLONE PARTICLE
-- particles_array[counter_cloned_particles] <= old_particle_array[best]
--PUT IT AWAY
--reconos_write_burst(done, o_osif, i_osif, local_ram_address, current_particle_array_address);
if done then
state <= STATE_CORRECTION;
counter_cloned_particles <= counter_cloned_particles + 1;
current_particle_array_address <= current_particle_array_address + particle_size;
end if;
when STATE_SEM_POST =>
reconos_sem_post (o_osif, i_osif, C_SEM_POST);
state <= STATE_SEM_WAIT;
when others =>
state <= STATE_SEM_WAIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
cda4e7946e92554c8cbb0bb27bd6a761
| 0.584932 | 3.791445 | false | false | false | false |
luebbers/reconos
|
demos/mbox_demo/hw/src/threadA.vhd
| 1 | 7,308 |
--
-- threadA.vhd
-- demo thread
-- After waiting on C_SEM_START, it reads a block of 8 kBytes from memory
-- (using its init_data as address) then sends that data one by one to mail
-- box C_MBOX_TRANSFER. Both transactions are timed, and sent to C_MBOX_READTIME,
-- C_MBOX_PUTTIME respectively.
--
-- NOTE: These measurements may not be entirely accurate due to the bus load
-- incurred by the OS commands.
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 15.10.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity threadA is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
i_timeBase : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)
);
end threadA;
architecture Behavioral of threadA is
-- timer address (FIXME: hardcoded!)
constant TIMER_ADDR : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"50004000";
-- ReconOS resources used by this thread
constant C_SEM_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_TRANSFER : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_READTIME : std_logic_vector(0 to 31) := X"00000002";
constant C_MB_PUTTIME : std_logic_vector(0 to 31) := X"00000003";
-- OS synchronization state machine states (TODO: measurements!)
type t_state is (
STATE_INIT,
STATE_WAIT,
STATE_READTIME_START,
STATE_READ,
STATE_READTIME_STOP,
STATE_TRANSFER,
STATE_PUTTIME_STOP,
STATE_POST_READTIME_1,
STATE_POST_READTIME_2,
STATE_POST_PUTTIME_1,
STATE_POST_PUTTIME_2
);
signal state : t_state := STATE_INIT;
-- address of data to sort in main memory
signal address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- RAM address
signal RAMAddr : std_logic_vector(0 to C_BURST_AWIDTH-1);
begin
-- hook up RAM signals
o_RAMClk <= clk;
o_RAMAddr <= RAMAddr(0 to C_BURST_AWIDTH-2) & not RAMAddr(C_BURST_AWIDTH-1); -- invert LSB of address to get the word ordering right
o_RAMWE <= '0';
o_RAMData <= (others => '0');
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable burst_counter : natural range 0 to 8192/128 - 1; -- transfer 128 bytes at once
variable trans_counter : natural range 0 to 8192/4 - 1; -- transfer 4 bytes at once
-- timing values
variable readtime_1 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0001";
variable readtime_2 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0001";
variable puttime_1 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0002";
variable puttime_2 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0002";
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
address <= (others => '0');
state <= STATE_INIT;
burst_counter := 0;
trans_counter := 0;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
-- read init data
when STATE_INIT =>
reconos_get_init_data_s(done, o_osif, i_osif, address);
if done then
state <= STATE_WAIT;
end if;
-- wait for start semaphore
when STATE_WAIT =>
reconos_sem_wait(o_osif, i_osif, C_SEM_START);
burst_counter := 0;
state <= STATE_READTIME_START;
-- get start time of burst transfer
when STATE_READTIME_START =>
readtime_1 := i_timeBase;
-- reconos_read(done, o_osif, i_osif, TIMER_ADDR, readtime_1);
-- if done then
state <= STATE_READ;
-- end if;
-- read data from main memory into local burst RAM.
when STATE_READ =>
reconos_read_burst (done, o_osif, i_osif, std_logic_vector(TO_UNSIGNED(burst_counter*128, C_OSIF_DATA_WIDTH)), address+(burst_counter*128));
if done then
if burst_counter = 8192/128 - 1 then
trans_counter := 0;
RAMAddr <= (others => '0');
state <= STATE_READTIME_STOP;
else
burst_counter := burst_counter + 1;
end if;
end if;
-- get stop time of burst transfer
when STATE_READTIME_STOP =>
readtime_2 := i_timeBase;
-- reconos_read(done, o_osif, i_osif, TIMER_ADDR, readtime_2);
-- if done then
puttime_1 := readtime_2; -- nach der Messung ist vor der Messung :)
state <= STATE_TRANSFER;
-- end if;
-- transfer data across mailbox
-- this state also hides the RAM access timing, since this is a multi-cycle
-- command, and the "data" parameter is only transferred in the second cycle.
when STATE_TRANSFER =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_TRANSFER, i_RAMData);
if done and success then
if trans_counter = 8192/4 - 1 then
state <= STATE_PUTTIME_STOP;
else
RAMAddr <= RAMAddr + 1;
trans_counter := trans_counter + 1;
end if;
end if;
-- get stop time of FIFO transfer
when STATE_PUTTIME_STOP =>
puttime_2 := i_timeBase;
-- reconos_read(done, o_osif, i_osif, TIMER_ADDR, puttime_2);
-- if done then
state <= STATE_POST_READTIME_1;
-- end if;
-- write read time to mailbox
when STATE_POST_READTIME_1 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_READTIME, readtime_1);
if done and success then
state <= STATE_POST_READTIME_2;
end if;
when STATE_POST_READTIME_2 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_READTIME, readtime_2);
if done and success then
state <= STATE_POST_PUTTIME_1;
end if;
-- write transfer time to mailbox
when STATE_POST_PUTTIME_1 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_PUTTIME, puttime_1);
if done and success then
state <= STATE_POST_PUTTIME_2;
end if;
when STATE_POST_PUTTIME_2 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_PUTTIME, puttime_2);
if done and success then
state <= STATE_WAIT;
end if;
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
25937ac09e808ffc66ae7df98ce2db6f
| 0.613437 | 3.460227 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/ac97_model.vhd
| 7 | 14,137 |
-------------------------------------------------------------------------------
-- ac97_model.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_model.vhd
--
-- Description:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.TextIO.all;
entity ac97_model is
generic (
BIT_CLK_STARTUP_TIME : time := 1 us
);
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end entity ac97_model;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.testbench_ac97_package.all;
architecture model of ac97_model is
signal reset_delay : std_logic := '1';
signal initial_reset : std_logic := '0';
signal bit_clk_i, bit_clk_freq : std_logic;
signal sync_d, end_of_frame, end_of_slot : std_logic;
signal frame_count : integer := 1;
signal valid_frame,codec_rdy : std_logic := '0';
signal shift_reg_in, shift_reg_out : std_logic_vector(19 downto 0) := (others => '0');
signal left_in_data, right_in_data : std_logic_vector(15 downto 0);
signal register_control_valid, register_data_valid : std_logic;
signal register_write, register_read : std_logic := '0';
signal register_address : std_logic_vector(6 downto 0) := (others => '0');
signal slot0_in : std_logic_vector(15 downto 0) := (others => '0');
signal slot1_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot2_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot3_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot4_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot0_out : std_logic_vector(15 downto 0) := (others => '0');
signal slot1_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot2_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot3_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot4_out : std_logic_vector(19 downto 0) := (others => '0');
signal slot_counter : integer;
signal bit_counter : integer;
--
type register_type is array(0 to 63) of std_logic_vector(15 downto 0);
signal ac97_registers : register_type := (
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000"
);
type audio_type is array(0 to 15) of std_logic_vector(15 downto 0);
signal record_values : audio_type := (
X"1234", X"2345", X"3456", X"4567", X"5678", X"6789", X"789a", X"89ab",
X"1234", X"2345", X"3456", X"4567", X"5678", X"6789", X"789a", X"89ab"
);
signal record_value : unsigned(19 downto 0) := X"00010";
signal record_sample_counter : integer := 0;
signal temp_record_sample_count : integer := 0;
signal temp_play_sample_count : integer := 0;
signal valid_record_data : std_logic := '0';
signal request_play_data : std_logic := '0';
constant sample_skip : integer := 3; -- skip every 3rd sample
begin
-----------------------------------------------------------------------------
-- Clock
-----------------------------------------------------------------------------
-- simulate a 12.8? MHz ac97 clk
ac97_clk_freq_PROCESS: process
begin
Bit_Clk_freq <= '0';
wait for 40.69 ns;
Bit_Clk_freq <= '1';
wait for 40.69 ns;
end process ac97_clk_freq_PROCESS;
process (ac97reset_n)
begin
if ac97reset_n = '0' and ac97reset_n'event then
initial_reset <= '1';
end if;
end process;
-- Delay state machine to simulate a delay on the bit clock
reset_delay <= transport AC97Reset_n after BIT_CLK_STARTUP_TIME;
-- Gated bit clock signal
Bit_Clk_i <= Bit_Clk_freq when reset_delay = '1' and ac97reset_n = '1'
and initial_reset = '1'
else '0';
bit_clk <= bit_clk_i;
-----------------------------------------------------------------------------
-- Receiving shift register
-----------------------------------------------------------------------------
process (bit_clk_i)
begin
if (bit_clk_i = '0' and bit_clk_i'event) then
shift_reg_out <= shift_reg_out(18 downto 0) & sdata_out;
end if;
end process;
process (bit_clk_i)
begin
if (bit_clk_i = '0' and bit_clk_i'event) then
if (bit_counter = 0) then
if (slot_counter = 1) then
slot0_out <= shift_reg_out(15 downto 0);
elsif (slot_counter = 2) then
slot1_out <= shift_reg_out;
elsif (slot_counter = 3) then
slot2_out <= shift_reg_out;
elsif (slot_counter = 4) then
slot3_out <= shift_reg_out;
elsif (slot_counter = 5) then
slot4_out <= shift_reg_out;
end if;
end if;
end if;
end process;
register_control_valid <= slot0_out(14) and slot0_out(15);
register_data_valid <= slot0_out(13) and slot0_out(15);
register_address <= slot1_out(18 downto 12);
register_write <= register_control_valid and (not slot1_out(19));
register_read <= register_control_valid and slot1_out(19);
-----------------------------------------------------------------------------
-- Register return data interface
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if register_read = '1' then
slot2_in <= X"A55A0"; -- send sample data
slot0_in(13) <= '1';
write(my_line, string'("CODEC: Reading from address "));
write(my_line, bit_vector'( To_bitvector( register_address) ));
writeline(output, my_line);
else
slot2_in <= (others => '0');
slot0_in(13) <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Register write
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if register_write = '1' then
write(my_line, string'("CODEC: Writing value "));
write(my_line, bit_vector'( To_bitvector( slot2_out(19 downto 4))));
write(my_line, string'(" to address "));
write(my_line, bit_vector'( To_bitvector( register_address) ));
writeline(output, my_line);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Slot in
-----------------------------------------------------------------------------
slot0_in(15) <= codec_rdy;
slot0_in(14) <= register_control_valid; -- mimic register command
-- slot_in(13) set by register return state machine
slot0_in(12) <= valid_record_data; -- valid PCM
slot0_in(11) <= valid_record_data; -- valid PCM
slot0_in(10 downto 0) <= (others => '0');
slot1_in <= '0' & register_address &
(not request_play_data) & (not request_play_data) & "0000000000";
-----------------------------------------------------------------------------
-- Play Data
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if ac97reset_n = '0' then
request_play_data <= '0';
temp_play_sample_count <= 0;
elsif bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 6 then
temp_play_sample_count <= temp_play_sample_count + 1;
if temp_play_sample_count = sample_skip then
temp_play_sample_count <= 0;
request_play_data <= '0';
else
request_play_data <= '1';
end if;
end if;
end process;
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if request_play_data = '1' then
write(my_line, string'("CODEC: Playback Left="));
write(my_line, bit_vector'( To_bitvector( slot3_out ) ));
write(my_line, string'(" Playback Right="));
write(my_line, bit_vector'( To_bitvector( slot4_out ) ));
writeline(output, my_line);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Record Data
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if ac97reset_n = '0' then
slot3_in <= (others => '0');
slot4_in <= (others => '0');
valid_record_data <= '0';
elsif bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
temp_record_sample_count <= temp_record_sample_count + 1;
if temp_record_sample_count = sample_skip then
temp_record_sample_count <= 0;
slot3_in <= X"00000";
slot4_in <= X"00000";
valid_record_data <= '0';
else
slot3_in <= CONV_STD_LOGIC_VECTOR(record_value,20);
slot4_in <= CONV_STD_LOGIC_VECTOR(record_value,20);
record_value <= record_value + 16;
valid_record_data <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Sending shift register
-----------------------------------------------------------------------------
process (bit_clk_i)
begin
if ac97reset_n = '0' then
shift_reg_in <= (others => '0');
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if end_of_slot = '1' then
case slot_counter is
when 12 => -- slot 0
shift_reg_in <= slot0_in & "0000";
when 0 => -- slot 1
shift_reg_in <= slot1_in;
when 1 =>
shift_reg_in <= slot2_in;
when 2 =>
shift_reg_in <= slot3_in;
when 3 =>
shift_reg_in <= slot4_in;
when others =>
shift_reg_in <= (others => '0');
end case;
else
shift_reg_in <= shift_reg_in(18 downto 0) & '0';
end if;
end if;
end process;
SData_In <= shift_reg_in(19);
-----------------------------------------------------------------------------
-- Codec Ready
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (AC97Reset_n = '0') then
codec_rdy <= '0';
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if codec_rdy = '0' and end_of_frame = '1' and valid_frame = '1' then
codec_rdy <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Valid frame checker
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (AC97Reset_n = '0') then
valid_frame <= '0';
frame_count <= 0;
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if end_of_frame = '1' then
if (frame_count = 255) then
valid_frame <= '1';
else
valid_frame <= '0';
end if;
frame_count <= 0;
else
frame_count <= frame_count + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- End of frame set by sync
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (bit_clk_i = '1' and bit_clk_i'event) then
sync_d <= sync;
end if;
end process;
end_of_frame <= sync and (not sync_d);
-----------------------------------------------------------------------------
-- slot_counter & bit_counter state machine
-----------------------------------------------------------------------------
end_of_slot <= '1' when ((slot_counter = 0 and bit_counter = 15) or
bit_counter = 19)
else '0';
process (bit_clk_i)
begin
if (AC97Reset_n = '0') then
bit_counter <= 0;
slot_counter <= 0;
elsif (bit_clk_i = '1' and bit_clk_i'event) then
-- wait for sync to initialize sequence
if (end_of_frame = '1') then
slot_counter <= 0;
bit_counter <= 0;
else
if end_of_slot = '1' then
bit_counter <= 0;
if slot_counter = 12 then
slot_counter <= 0;
else
slot_counter <= slot_counter + 1;
end if;
else
bit_counter <= bit_counter +1;
end if;
end if;
end if;
end process;
end architecture model;
|
gpl-3.0
|
752875d0eab6c9f4855193a6f1b62bf8
| 0.457735 | 3.796187 | false | false | false | false |
williammacdowell/gcm
|
src/fpga/s_box_ea.vhd
| 1 | 15,062 |
-------------------------------------------------------------------------------
-- Title : Substitution Box
-- Project : AES-GCM
-------------------------------------------------------------------------------
-- File : s_box_ea.vhd
-- Author : Bill MacDowell <bill@bill-macdowell-laptop>
-- Company :
-- Created : 2017-03-15
-- Last update: 2017-03-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: LUT implementation of the S-Box portion of the AES cipher as
-- described in the FIPS 197 AES Spec
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-03-15 1.0 bill Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity s_box is
port (
clk : in std_logic;
rst : in std_logic;
byte_in : in std_logic_vector(7 downto 0);
byte_out : out std_logic_vector(7 downto 0));
end entity s_box;
architecture rtl of s_box is
begin -- architecture rtl
-- This process just implements the S-Box lookup table defined in FIPS 197
s_box_proc: process (clk) is
begin -- process s_box_proc
if clk'event and clk = '1' then -- rising clock edge
case byte_in is
-- Row 0
when x"00" =>
byte_out <= x"63";
when x"01" =>
byte_out <= x"7c";
when x"02" =>
byte_out <= x"77";
when x"03" =>
byte_out <= x"7b";
when x"04" =>
byte_out <= x"f2";
when x"05" =>
byte_out <= x"6b";
when x"06" =>
byte_out <= x"6f";
when x"07" =>
byte_out <= x"c5";
when x"08" =>
byte_out <= x"30";
when x"09" =>
byte_out <= x"01";
when x"0a" =>
byte_out <= x"67";
when x"0b" =>
byte_out <= x"2b";
when x"0c" =>
byte_out <= x"fe";
when x"0d" =>
byte_out <= x"d7";
when x"0e" =>
byte_out <= x"ab";
when x"0f" =>
byte_out <= x"76";
-- Row 1
when x"10" =>
byte_out <= x"ca";
when x"11" =>
byte_out <= x"82";
when x"12" =>
byte_out <= x"c9";
when x"13" =>
byte_out <= x"7d";
when x"14" =>
byte_out <= x"fa";
when x"15" =>
byte_out <= x"59";
when x"16" =>
byte_out <= x"47";
when x"17" =>
byte_out <= x"f0";
when x"18" =>
byte_out <= x"ad";
when x"19" =>
byte_out <= x"d4";
when x"1a" =>
byte_out <= x"a2";
when x"1b" =>
byte_out <= x"af";
when x"1c" =>
byte_out <= x"9c";
when x"1d" =>
byte_out <= x"a4";
when x"1e" =>
byte_out <= x"72";
when x"1f" =>
byte_out <= x"c0";
-- Row 2
when x"20" =>
byte_out <= x"b7";
when x"21" =>
byte_out <= x"fd";
when x"22" =>
byte_out <= x"93";
when x"23" =>
byte_out <= x"26";
when x"24" =>
byte_out <= x"36";
when x"25" =>
byte_out <= x"3f";
when x"26" =>
byte_out <= x"f7";
when x"27" =>
byte_out <= x"cc";
when x"28" =>
byte_out <= x"34";
when x"29" =>
byte_out <= x"a5";
when x"2a" =>
byte_out <= x"e5";
when x"2b" =>
byte_out <= x"f1";
when x"2c" =>
byte_out <= x"71";
when x"2d" =>
byte_out <= x"d8";
when x"2e" =>
byte_out <= x"31";
when x"2f" =>
byte_out <= x"15";
-- Row 3
when x"30" =>
byte_out <= x"04";
when x"31" =>
byte_out <= x"c7";
when x"32" =>
byte_out <= x"23";
when x"33" =>
byte_out <= x"c3";
when x"34" =>
byte_out <= x"18";
when x"35" =>
byte_out <= x"96";
when x"36" =>
byte_out <= x"05";
when x"37" =>
byte_out <= x"9a";
when x"38" =>
byte_out <= x"07";
when x"39" =>
byte_out <= x"12";
when x"3a" =>
byte_out <= x"80";
when x"3b" =>
byte_out <= x"e2";
when x"3c" =>
byte_out <= x"eb";
when x"3d" =>
byte_out <= x"27";
when x"3e" =>
byte_out <= x"b2";
when x"3f" =>
byte_out <= x"75";
-- Row 4
when x"40" =>
byte_out <= x"09";
when x"41" =>
byte_out <= x"83";
when x"42" =>
byte_out <= x"2c";
when x"43" =>
byte_out <= x"1a";
when x"44" =>
byte_out <= x"1b";
when x"45" =>
byte_out <= x"6e";
when x"46" =>
byte_out <= x"5a";
when x"47" =>
byte_out <= x"a0";
when x"48" =>
byte_out <= x"52";
when x"49" =>
byte_out <= x"3b";
when x"4a" =>
byte_out <= x"d6";
when x"4b" =>
byte_out <= x"b3";
when x"4c" =>
byte_out <= x"29";
when x"4d" =>
byte_out <= x"e3";
when x"4e" =>
byte_out <= x"2f";
when x"4f" =>
byte_out <= x"84";
-- Row 5
when x"50" =>
byte_out <= x"53";
when x"51" =>
byte_out <= x"d1";
when x"52" =>
byte_out <= x"00";
when x"53" =>
byte_out <= x"ed";
when x"54" =>
byte_out <= x"20";
when x"55" =>
byte_out <= x"fc";
when x"56" =>
byte_out <= x"b1";
when x"57" =>
byte_out <= x"5b";
when x"58" =>
byte_out <= x"6a";
when x"59" =>
byte_out <= x"cb";
when x"5a" =>
byte_out <= x"be";
when x"5b" =>
byte_out <= x"39";
when x"5c" =>
byte_out <= x"4a";
when x"5d" =>
byte_out <= x"4c";
when x"5e" =>
byte_out <= x"58";
when x"5f" =>
byte_out <= x"cf";
-- Row 6
when x"60" =>
byte_out <= x"d0";
when x"61" =>
byte_out <= x"ef";
when x"62" =>
byte_out <= x"aa";
when x"63" =>
byte_out <= x"fb";
when x"64" =>
byte_out <= x"43";
when x"65" =>
byte_out <= x"4d";
when x"66" =>
byte_out <= x"33";
when x"67" =>
byte_out <= x"85";
when x"68" =>
byte_out <= x"45";
when x"69" =>
byte_out <= x"f9";
when x"6a" =>
byte_out <= x"02";
when x"6b" =>
byte_out <= x"7f";
when x"6c" =>
byte_out <= x"50";
when x"6d" =>
byte_out <= x"3c";
when x"6e" =>
byte_out <= x"9f";
when x"6f" =>
byte_out <= x"a8";
-- Row 7
when x"70" =>
byte_out <= x"51";
when x"71" =>
byte_out <= x"a3";
when x"72" =>
byte_out <= x"40";
when x"73" =>
byte_out <= x"8f";
when x"74" =>
byte_out <= x"92";
when x"75" =>
byte_out <= x"9d";
when x"76" =>
byte_out <= x"38";
when x"77" =>
byte_out <= x"f5";
when x"78" =>
byte_out <= x"bc";
when x"79" =>
byte_out <= x"b6";
when x"7a" =>
byte_out <= x"da";
when x"7b" =>
byte_out <= x"21";
when x"7c" =>
byte_out <= x"10";
when x"7d" =>
byte_out <= x"ff";
when x"7e" =>
byte_out <= x"f3";
when x"7f" =>
byte_out <= x"d2";
-- Row 8
when x"80" =>
byte_out <= x"cd";
when x"81" =>
byte_out <= x"0c";
when x"82" =>
byte_out <= x"13";
when x"83" =>
byte_out <= x"ec";
when x"84" =>
byte_out <= x"5f";
when x"85" =>
byte_out <= x"97";
when x"86" =>
byte_out <= x"44";
when x"87" =>
byte_out <= x"17";
when x"88" =>
byte_out <= x"c4";
when x"89" =>
byte_out <= x"a7";
when x"8a" =>
byte_out <= x"7e";
when x"8b" =>
byte_out <= x"3d";
when x"8c" =>
byte_out <= x"64";
when x"8d" =>
byte_out <= x"5d";
when x"8e" =>
byte_out <= x"19";
when x"8f" =>
byte_out <= x"73";
-- Row 9
when x"90" =>
byte_out <= x"60";
when x"91" =>
byte_out <= x"81";
when x"92" =>
byte_out <= x"4f";
when x"93" =>
byte_out <= x"dc";
when x"94" =>
byte_out <= x"22";
when x"95" =>
byte_out <= x"2a";
when x"96" =>
byte_out <= x"90";
when x"97" =>
byte_out <= x"88";
when x"98" =>
byte_out <= x"46";
when x"99" =>
byte_out <= x"ee";
when x"9a" =>
byte_out <= x"b8";
when x"9b" =>
byte_out <= x"14";
when x"9c" =>
byte_out <= x"de";
when x"9d" =>
byte_out <= x"5e";
when x"9e" =>
byte_out <= x"0b";
when x"9f" =>
byte_out <= x"db";
-- Row 10
when x"a0" =>
byte_out <= x"e0";
when x"a1" =>
byte_out <= x"32";
when x"a2" =>
byte_out <= x"3a";
when x"a3" =>
byte_out <= x"0a";
when x"a4" =>
byte_out <= x"49";
when x"a5" =>
byte_out <= x"06";
when x"a6" =>
byte_out <= x"24";
when x"a7" =>
byte_out <= x"5c";
when x"a8" =>
byte_out <= x"c2";
when x"a9" =>
byte_out <= x"d3";
when x"aa" =>
byte_out <= x"ac";
when x"ab" =>
byte_out <= x"62";
when x"ac" =>
byte_out <= x"91";
when x"ad" =>
byte_out <= x"95";
when x"ae" =>
byte_out <= x"e4";
when x"af" =>
byte_out <= x"79";
-- Row 11
when x"b0" =>
byte_out <= x"e7";
when x"b1" =>
byte_out <= x"c8";
when x"b2" =>
byte_out <= x"37";
when x"b3" =>
byte_out <= x"6d";
when x"b4" =>
byte_out <= x"8d";
when x"b5" =>
byte_out <= x"d5";
when x"b6" =>
byte_out <= x"4e";
when x"b7" =>
byte_out <= x"a9";
when x"b8" =>
byte_out <= x"6c";
when x"b9" =>
byte_out <= x"56";
when x"ba" =>
byte_out <= x"f4";
when x"bb" =>
byte_out <= x"ea";
when x"bc" =>
byte_out <= x"65";
when x"bd" =>
byte_out <= x"7a";
when x"be" =>
byte_out <= x"ae";
when x"bf" =>
byte_out <= x"08";
-- Row 12
when x"c0" =>
byte_out <= x"ba";
when x"c1" =>
byte_out <= x"78";
when x"c2" =>
byte_out <= x"25";
when x"c3" =>
byte_out <= x"2e";
when x"c4" =>
byte_out <= x"1c";
when x"c5" =>
byte_out <= x"a6";
when x"c6" =>
byte_out <= x"b4";
when x"c7" =>
byte_out <= x"c6";
when x"c8" =>
byte_out <= x"e8";
when x"c9" =>
byte_out <= x"dd";
when x"ca" =>
byte_out <= x"74";
when x"cb" =>
byte_out <= x"1f";
when x"cc" =>
byte_out <= x"4b";
when x"cd" =>
byte_out <= x"bd";
when x"ce" =>
byte_out <= x"8b";
when x"cf" =>
byte_out <= x"8a";
-- Row 13
when x"d0" =>
byte_out <= x"70";
when x"d1" =>
byte_out <= x"3e";
when x"d2" =>
byte_out <= x"b5";
when x"d3" =>
byte_out <= x"66";
when x"d4" =>
byte_out <= x"48";
when x"d5" =>
byte_out <= x"03";
when x"d6" =>
byte_out <= x"f6";
when x"d7" =>
byte_out <= x"0e";
when x"d8" =>
byte_out <= x"61";
when x"d9" =>
byte_out <= x"35";
when x"da" =>
byte_out <= x"57";
when x"db" =>
byte_out <= x"b9";
when x"dc" =>
byte_out <= x"86";
when x"dd" =>
byte_out <= x"c1";
when x"de" =>
byte_out <= x"1d";
when x"df" =>
byte_out <= x"9e";
-- Row 14
when x"e0" =>
byte_out <= x"e1";
when x"e1" =>
byte_out <= x"f8";
when x"e2" =>
byte_out <= x"98";
when x"e3" =>
byte_out <= x"11";
when x"e4" =>
byte_out <= x"69";
when x"e5" =>
byte_out <= x"d9";
when x"e6" =>
byte_out <= x"8e";
when x"e7" =>
byte_out <= x"94";
when x"e8" =>
byte_out <= x"9b";
when x"e9" =>
byte_out <= x"1e";
when x"ea" =>
byte_out <= x"87";
when x"eb" =>
byte_out <= x"e9";
when x"ec" =>
byte_out <= x"ce";
when x"ed" =>
byte_out <= x"55";
when x"ee" =>
byte_out <= x"28";
when x"ef" =>
byte_out <= x"df";
-- Row 15
when x"f0" =>
byte_out <= x"8c";
when x"f1" =>
byte_out <= x"a1";
when x"f2" =>
byte_out <= x"89";
when x"f3" =>
byte_out <= x"0d";
when x"f4" =>
byte_out <= x"bf";
when x"f5" =>
byte_out <= x"e6";
when x"f6" =>
byte_out <= x"42";
when x"f7" =>
byte_out <= x"68";
when x"f8" =>
byte_out <= x"41";
when x"f9" =>
byte_out <= x"99";
when x"fa" =>
byte_out <= x"2d";
when x"fb" =>
byte_out <= x"0f";
when x"fc" =>
byte_out <= x"b0";
when x"fd" =>
byte_out <= x"54";
when x"fe" =>
byte_out <= x"bb";
when x"ff" =>
byte_out <= x"16";
when others => null;
end case;
if rst = '1' then
byte_out <= (others => '0');
end if;
end if;
end process s_box_proc;
end rtl;
|
gpl-3.0
|
88e44926d10cbaf71aca87794e64e799
| 0.343845 | 3.140534 | false | false | false | false |
five-elephants/hw-neural-sampling
|
top.vhdl
| 1 | 2,678 |
library ieee;
use ieee.std_logic_1164.all;
use work.sampling.all;
use work.net_config.all;
entity top is
port (
ext_clk, async_resetb : in std_ulogic
);
end top;
architecture rtl of top is
------------------------------------------------------------
-- component declarations
------------------------------------------------------------
component clockgen is
port (
ext_clk, async_resetb : in std_ulogic;
clk, sync_reset : out std_ulogic
);
end component;
component sampling_shell is
generic (
num_samplers : integer := 4;
tau : positive := 20;
num_observers : natural := 16
);
port (
clk, reset : in std_ulogic;
observed_joints : in state_array2_t(1 to num_observers, 1 to num_samplers);
joint_counters : out joint_counter_array_t(1 to num_observers);
systime : out systime_t
);
end component;
component jtag_access is
generic (
num_samplers : integer;
num_observers : natural
);
port (
clk, reset : in std_ulogic;
joint_counters : in joint_counter_array_t(1 to num_observers);
systime : in systime_t
);
end component;
------------------------------------------------------------
-- local signals
------------------------------------------------------------
signal clk, reset : std_ulogic;
--signal observed_joints : state_array2_t(1 to num_observers, 1 to num_samplers);
signal joint_counters : joint_counter_array_t(1 to num_observers);
signal systime : systime_t;
begin
------------------------------------------------------------
-- support logic
------------------------------------------------------------
clkgen: clockgen
port map (
ext_clk => ext_clk,
clk => clk,
async_resetb => async_resetb,
sync_reset => reset
);
------------------------------------------------------------
-- sampling related stuff
------------------------------------------------------------
sampling: sampling_shell
generic map (
num_samplers => num_samplers,
tau => tau,
num_observers => num_observers
)
port map (
clk => clk,
reset => reset,
observed_joints => observed_joints,
joint_counters => joint_counters,
systime => systime
);
------------------------------------------------------------
-- JTAG interface
------------------------------------------------------------
jtag_inst: jtag_access
generic map (
num_samplers => num_samplers,
num_observers => num_observers
)
port map (
clk => clk,
reset => reset,
joint_counters => joint_counters,
systime => systime
);
end rtl;
|
apache-2.0
|
11432696f76b01680acdeb0ab7a137d0
| 0.473488 | 4.723104 | false | false | false | false |
luebbers/reconos
|
support/templates/bfmsim_plb_osif_v2_01_a/simulation/behavioral/bfm_memory_wrapper.vhd
| 1 | 5,863 |
-------------------------------------------------------------------------------
-- bfm_memory_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_slave_bfm_v1_00_a;
use plb_slave_bfm_v1_00_a.All;
entity bfm_memory_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_ordered : in std_logic;
PLB_lockErr : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_pendReq : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MErr : out std_logic_vector(0 to 1)
);
end bfm_memory_wrapper;
architecture STRUCTURE of bfm_memory_wrapper is
component plb_slave_bfm is
generic (
PLB_SLAVE_SIZE : std_logic_vector(0 to 1);
PLB_SLAVE_NUM : std_logic_vector(0 to 3);
PLB_SLAVE_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE_ADDR_HI_1 : std_logic_vector(0 to 31);
C_PLB_DWIDTH : integer;
C_PLB_NUM_MASTERS : integer;
C_PLB_MID_WIDTH : integer
);
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_PLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_PLB_DWIDTH/8)-1));
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_ordered : in std_logic;
PLB_lockErr : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_pendReq : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_PLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_PLB_NUM_MASTERS-1));
Sl_MErr : out std_logic_vector(0 to (C_PLB_NUM_MASTERS-1))
);
end component;
begin
bfm_memory : plb_slave_bfm
generic map (
PLB_SLAVE_SIZE => "01",
PLB_SLAVE_NUM => "0000",
PLB_SLAVE_ADDR_LO_0 => X"10000000",
PLB_SLAVE_ADDR_HI_0 => X"1000ffff",
PLB_SLAVE_ADDR_LO_1 => X"20000000",
PLB_SLAVE_ADDR_HI_1 => X"2000ffff",
C_PLB_DWIDTH => 64,
C_PLB_NUM_MASTERS => 2,
C_PLB_MID_WIDTH => 1
)
port map (
PLB_CLK => PLB_CLK,
PLB_RESET => PLB_RESET,
SYNCH_OUT => SYNCH_OUT,
SYNCH_IN => SYNCH_IN,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_msize => PLB_msize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_ordered => PLB_ordered,
PLB_lockErr => PLB_lockErr,
PLB_ABus => PLB_ABus,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_pendReq => PLB_pendReq,
PLB_pendPri => PLB_pendPri,
PLB_reqPri => PLB_reqPri,
Sl_addrAck => Sl_addrAck,
Sl_ssize => Sl_ssize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MErr => Sl_MErr
);
end architecture STRUCTURE;
|
gpl-3.0
|
82865565c80a93315fa2fb95ad466a19
| 0.580249 | 3.169189 | false | false | false | false |
zebarnabe/music-keyboard-vhdl
|
src/main/segDispDriver.vhd
| 1 | 1,946 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:01:12 07/01/2015
-- Design Name:
-- Module Name: segDispDriver - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity segDispDriver is
Port ( clk : in STD_LOGIC;
dig1 : in STD_LOGIC_VECTOR (7 downto 0);
dig2 : in STD_LOGIC_VECTOR (7 downto 0);
dig3 : in STD_LOGIC_VECTOR (7 downto 0);
dig4 : in STD_LOGIC_VECTOR (7 downto 0);
cat : out STD_LOGIC_VECTOR (7 downto 0);
an : out STD_LOGIC_VECTOR (3 downto 0));
end segDispDriver;
architecture Behavioral of segDispDriver is
signal anodes : STD_LOGIC_VECTOR (3 downto 0) := "0111";
signal cntDiv : std_logic_vector(15 downto 0) := (others => '0');
begin
process(clk, dig1, dig2, dig3, dig4)
begin
if (rising_edge(clk)) then
cntDiv <= cntDiv + 1;
if (cntDiv = "1111111111111111") then
anodes <= anodes(2 downto 0) & anodes(3);
else
anodes <= anodes;
end if;
case anodes is
when "0111" => cat <= not dig1;
when "1011" => cat <= not dig2;
when "1101" => cat <= not dig3;
when "1110" => cat <= not dig4;
when others => cat <= (others => '0');
end case;
end if;
end process;
an <= anodes;
end Behavioral;
|
gpl-2.0
|
d4f6cffc63e56a9bc0f0f2b4caece1f0
| 0.569887 | 3.637383 | false | false | false | false |
makestuff/vhdl
|
analyzer/producer.vhdl
| 1 | 3,476 |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity producer is
port(
clk_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
write_out : out std_logic;
full_in : in std_logic;
trigger_in : in std_logic;
count_in : in unsigned(31 downto 0);
alarm_out : out std_logic;
ch_in : in std_logic
--ch_in : in std_logic_vector(1 downto 0)
);
end producer;
architecture behavioural of producer is
type StateType is (
STATE_IDLE,
STATE_GET0,
STATE_GET1,
STATE_GET2,
STATE_GET3
);
signal state, state_next : StateType := STATE_IDLE;
signal count, count_next : unsigned(31 downto 0); -- Write count
signal alarm, alarm_next : std_logic := '0';
signal chanBits, chanBits_next : std_logic_vector(5 downto 0) := "000000";
signal ch_sync1 : std_logic;
signal ch_sync2 : std_logic;
signal ch_sync3 : std_logic;
--signal ch_sync1 : std_logic_vector(1 downto 0) := "00";
--signal ch_sync2 : std_logic_vector(1 downto 0) := "00";
--signal ch_sync3 : std_logic_vector(1 downto 0) := "00";
--signal ch, ch_next : std_logic_vector(1 downto 0) := "00";
begin
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
state <= state_next;
count <= count_next;
alarm <= alarm_next;
chanBits <= chanBits_next;
ch_sync1 <= ch_in;
ch_sync2 <= ch_sync1;
ch_sync3 <= ch_sync2;
--ch <= ch_next;
end if;
end process;
--ch_next <=
-- ch_sync2 when ch_sync1 = ch_sync2 and ch_sync2 = ch_sync3 else
-- ch;
alarm_next <=
'1' when full_in = '1'
else alarm;
alarm_out <= alarm;
process(state, count, chanBits, ch_sync2, ch_sync3, count_in, trigger_in)
begin
state_next <= state;
count_next <= count;
write_out <= '0';
chanBits_next <= chanBits;
data_out <= (others => '0');
case state is
when STATE_GET0 =>
chanBits_next(1 downto 0) <= ch_sync2 & ch_sync3;
state_next <= STATE_GET1;
when STATE_GET1 =>
chanBits_next(3 downto 2) <= ch_sync2 & ch_sync3;
state_next <= STATE_GET2;
when STATE_GET2 =>
chanBits_next(5 downto 4) <= ch_sync2 & ch_sync3;
state_next <= STATE_GET3;
when STATE_GET3 =>
--data_out <= std_logic_vector(count(7 downto 0));
data_out <= ch_sync2 & ch_sync3 & chanBits;
write_out <= '1';
count_next <= count - 1;
if ( count = 1 ) then
state_next <= STATE_IDLE;
else
state_next <= STATE_GET0;
end if;
-- STATE_IDLE and others
when others =>
if ( trigger_in = '1' ) then
state_next <= STATE_GET0;
count_next <= count_in;
end if;
end case;
end process;
end behavioural;
|
gpl-3.0
|
b8dfab0afcf719ebc465e7d3bc564397
| 0.620253 | 2.960818 | false | false | false | false |
makestuff/vhdl
|
analyzer/sevenseg.vhdl
| 1 | 2,577 |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sevenseg is
port(
clk_in : in std_logic;
data_in : in std_logic_vector(15 downto 0);
segs_out : out std_logic_vector(6 downto 0);
anodes_out : out std_logic_vector(3 downto 0)
);
end sevenseg;
architecture behavioural of sevenseg is
-- Refresh rate 50M/2^18 ~ 190Hz
-- Refresh rate 8M/2^16 ~ 122Hz
constant COUNTER_WIDTH : natural := 18;
signal count : unsigned(COUNTER_WIDTH-1 downto 0) := (others => '0');
signal count_next : unsigned(COUNTER_WIDTH-1 downto 0);
signal anode_select : std_logic_vector(1 downto 0);
signal nibble : std_logic_vector(3 downto 0);
begin
count_next <= count + 1;
anode_select <= std_logic_vector(count(COUNTER_WIDTH-1 downto COUNTER_WIDTH-2));
-- Update counter, drive anodes_out and select bits to display for each 7-seg
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
count <= count_next;
case anode_select is
when "00" =>
anodes_out <= "0111";
nibble <= data_in(15 downto 12);
when "01" =>
anodes_out <= "1011";
nibble <= data_in(11 downto 8);
when "10" =>
anodes_out <= "1101";
nibble <= data_in(7 downto 4);
when others =>
anodes_out <= "1110";
nibble <= data_in(3 downto 0);
end case;
end if;
end process;
-- Decode selected nibble
with nibble select
segs_out <=
"1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0010000" when "1001",
"0001000" when "1010",
"0000011" when "1011",
"1000110" when "1100",
"0100001" when "1101",
"0000110" when "1110",
"0001110" when others;
end behavioural;
|
gpl-3.0
|
98d4fc8fae89d052fd7e9c1eb1989ccc
| 0.658518 | 3.257901 | false | false | false | false |
dries007/Basys3
|
VGA/VGA.srcs/sources_1/new/test_top.vhd
| 1 | 2,035 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test_top is
Port (
led : out STD_LOGIC_VECTOR (2 downto 0);
clk : in STD_LOGIC;
vgaRed : out STD_LOGIC_VECTOR(3 downto 0);
vgaBlue : out STD_LOGIC_VECTOR(3 downto 0);
vgaGreen : out STD_LOGIC_VECTOR(3 downto 0);
Hsync : out STD_LOGIC;
Vsync : out STD_LOGIC
);
end test_top;
architecture Behavioral of test_top is
constant REFRESH_RATE : natural := 60;
constant WIDTH : natural := 640;
constant FRONT_PORCH_H : natural := 16;
constant SYNC_PULSE_H : natural := 96;
constant BACK_PORCH_H : natural := 48;
constant WHOLE_LINE : natural := WIDTH + FRONT_PORCH_H + SYNC_PULSE_H + BACK_PORCH_H;
constant HEIGHT : natural := 480;
constant FRONT_PORCH_V : natural := 10;
constant SYNC_PULSE_V : natural := 2;
constant BACK_PORCH_V : natural := 33;
constant WHOLE_FRAME : natural := HEIGHT + FRONT_PORCH_V + SYNC_PULSE_V + BACK_PORCH_V;
signal clk_pxl : STD_LOGIC := '0';
signal h_count : integer range 0 to WHOLE_LINE;
signal v_count : integer range 0 to WHOLE_FRAME;
begin
CD_PXL_CLK: entity work.ClockDivider
generic map (
CLK_IN_HZ => 100000000,
CLK_OUT_HZ => 25175000
)
port map (
clk_in => clk,
clk_out => clk_pxl
);
process (clk_pxl)
begin
if (rising_edge(clk_pxl)) then
if (h_count = WHOLE_LINE) then
h_count <= 0;
led(1) <= '1'; -- debug
else
h_count <= h_count + 1;
led(1) <= '0'; -- debug
end if;
end if;
end process;
process (clk_pxl)
begin
if (rising_edge(clk_pxl)) then
if ((v_count = WHOLE_FRAME) and (h_count = WHOLE_LINE)) then
v_count <= 0;
led(2) <= '1'; -- debug
elsif (h_count = WHOLE_LINE) then
v_count <= v_count + 1;
led(2) <= '0'; -- debug
end if;
end if;
end process;
led(0) <= clk_pxl;
end Behavioral;
|
mit
|
5a4602f40e19e3dc4fdbdc2233de3491
| 0.557248 | 3.449153 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.srcs/sources_1/ip/FrameBuffer/synth/FrameBuffer.vhd
| 1 | 15,058 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY FrameBuffer IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END FrameBuffer;
ARCHITECTURE FrameBuffer_arch OF FrameBuffer IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF FrameBuffer_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF FrameBuffer_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF FrameBuffer_arch : ARCHITECTURE IS "FrameBuffer,blk_mem_gen_v8_3_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF FrameBuffer_arch: ARCHITECTURE IS "FrameBuffer,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=FrameBuffer.mif,C_INIT_FILE=FrameBuffer.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=10240,C_READ_DEPTH_A=10240,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=10240,C_READ_DEPTH_B=10240,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.61856 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "FrameBuffer.mif",
C_INIT_FILE => "FrameBuffer.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 10240,
C_READ_DEPTH_A => 10240,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 10240,
C_READ_DEPTH_B => 10240,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "2",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.61856 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END FrameBuffer_arch;
|
mit
|
29f6ab817f865803ef0f56cbdd1c3306
| 0.631956 | 3.061814 | false | false | false | false |
luebbers/reconos
|
support/threads/fifo_conv/hwt_fifo_conv.vhd
| 1 | 7,169 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v1_03_a;
use reconos_v1_03_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hwt_fifo_conv is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector( 0 to C_BURST_AWIDTH-1 );
o_RAMData : out std_logic_vector( 0 to C_BURST_DWIDTH-1 );
i_RAMData : in std_logic_vector( 0 to C_BURST_DWIDTH-1 );
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end entity;
architecture Behavioral of hwt_fifo_conv is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
constant C_PIX_AWIDTH : natural := 9;
constant C_LINE_AWIDTH : natural := 9;
constant C_PIX_PER_LINE : natural := 320;
-- os ressources
constant C_FIFO_GET_HANDLE : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)
:= X"00000000";
constant C_FIFO_PUT_HANDLE : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)
:= X"00000001";
type t_state is (
STATE_INIT,
STATE_READ_KERNEL,
STATE_PREPARE_PUT_LINE,
STATE_LOAD_A,
STATE_LOAD_B,
STATE_LOAD_C,
STATE_DISPATCH,
STATE_PUT_LINE,
STATE_GET_LINE,
STATE_READY,
STATE_PUT_LAPLACE,
STATE_GET,
STATE_PUT_LAPLACE_WAIT,
STATE_PUT_LAPLACE_WAIT2,
STATE_FINAL);
signal state : t_state;
signal next_line : std_logic;
signal line_sel : std_logic_vector(1 downto 0);
signal pix_sel : std_logic_vector(C_PIX_AWIDTH - 1 downto 0);
signal local_addr : std_logic_vector(C_BURST_AWIDTH - 1 downto 0);
signal last_line : std_logic;
signal ready : std_logic;
signal init_data : std_logic_vector(31 downto 0);
signal r24 : std_logic_vector(23 downto 0);
signal g24 : std_logic_vector(23 downto 0);
signal b24 : std_logic_vector(23 downto 0);
signal r8 : std_logic_vector(7 downto 0);
signal g8 : std_logic_vector(7 downto 0);
signal b8 : std_logic_vector(7 downto 0);
signal pix_out : std_logic_vector(31 downto 0);
signal conv_ien : std_logic;
signal kernel : std_logic_vector(80 downto 0);
begin
lag : entity WORK.line_addr_generator
port map (
rst => reset,
next_line => next_line,
line_sel => line_sel,
frame_offset => open,
pix_sel => pix_sel,
bram_addr => local_addr,
last_line => last_line,
ready => ready
);
conv_r : entity WORK.conv_filter3x3
port map(
clk => clk,
rst => reset,
shift_in => r24,
shift_out => r8,
ien => conv_ien,
kernel => kernel
);
conv_g : entity WORK.conv_filter3x3
port map(
clk => clk,
rst => reset,
shift_in => g24,
shift_out => g8,
ien => conv_ien,
kernel => kernel
);
conv_b : entity WORK.conv_filter3x3
port map(
clk => clk,
rst => reset,
shift_in => b24,
shift_out => b8,
ien => conv_ien,
kernel => kernel
);
pix_out <= X"00" & b8 & g8 & r8;
o_RAMAddr <= local_addr(C_BURST_AWIDTH-1 downto 1) & not local_addr(0);
o_RAMClk <= clk;
state_proc: process( clk, reset )
variable done : boolean;
variable success : boolean;
variable burst_counter : integer;
variable pix_a : std_logic_vector(31 downto 0);
variable pix_b : std_logic_vector(31 downto 0);
variable pix_c : std_logic_vector(31 downto 0);
variable invert : std_logic_vector(31 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable kernel_counter : integer range 0 to 15;
begin
if reset = '1' then
reconos_reset( o_osif, i_osif );
state <= STATE_INIT;
next_line <= '0';
line_sel <= (others => '0');
pix_sel <= (others => '0');
conv_ien <= '0';
init_data <= (others => '0');
kernel_counter := 0;
elsif rising_edge( clk ) then
reconos_begin( o_osif, i_osif );
if reconos_ready( i_osif ) then
case state is
when STATE_INIT =>
reconos_get_init_data_s (done, o_osif, i_osif, init_data);
next_line <= '1';
if done then state <= STATE_READ_KERNEL; end if;
when STATE_READ_KERNEL =>
reconos_read(done, o_osif, i_osif,
init_data + 4*kernel_counter, tmp);
if done then
kernel(9*kernel_counter + 8 downto 9*kernel_counter) <= tmp(8 downto 0);
kernel_counter := kernel_counter + 1;
if kernel_counter = 9 then
kernel_counter := 0;
state <= STATE_GET_LINE;
end if;
end if;
when STATE_GET_LINE =>
o_RAMWE <= '0';
if pix_sel = C_PIX_PER_LINE - 1 then
pix_sel <= (others => '0');
next_line <= '0';
state <= STATE_READY;
else
pix_sel <= pix_sel + 1;
state <= STATE_GET;
end if;
when STATE_GET =>
o_RAMwe <= '1';
reconos_mbox_get_s(done,success,o_osif,i_osif,C_FIFO_GET_HANDLE,o_RAMData);
if done then
state <= STATE_GET_LINE;
end if;
when STATE_READY =>
if last_line = '1' then
state <= STATE_FINAL;
elsif ready = '0' then
next_line <= '1';
state <= STATE_GET_LINE;
else
next_line <= '1';
state <= STATE_PREPARE_PUT_LINE;
end if;
when STATE_PREPARE_PUT_LINE =>
state <= STATE_PUT_LINE;
when STATE_PUT_LINE =>
o_RAMwe <= '0';
line_sel <= B"00"; -- keep addr -> 0 (default)
if pix_sel = C_PIX_PER_LINE - 1 then
pix_sel <= (others => '0');
state <= STATE_GET_LINE;
else
line_sel <= B"01"; -- addr -> 1
pix_sel <= pix_sel + 1;
state <= STATE_LOAD_A;
end if;
when STATE_LOAD_A =>
line_sel <= B"10"; -- addr -> 2
pix_a := i_RAMData; -- load -> 0
state <= STATE_LOAD_B;
when STATE_LOAD_B =>
pix_b := i_RAMData; -- addr -> 0
line_sel <= B"00"; -- load -> 1
state <= STATE_LOAD_C;
when STATE_LOAD_C =>
pix_c := i_RAMData; -- load -> 2
state <= STATE_DISPATCH;
when STATE_DISPATCH =>
r24 <= pix_a(7 downto 0) & pix_b(7 downto 0) & pix_c(7 downto 0);
g24 <= pix_a(15 downto 8) & pix_b(15 downto 8) & pix_c(15 downto 8);
b24 <= pix_a(23 downto 16) & pix_b(23 downto 16) & pix_c(23 downto 16);
conv_ien <= '1';
state <= STATE_PUT_LAPLACE_WAIT;
when STATE_PUT_LAPLACE_WAIT =>
conv_ien <= '0';
state <= STATE_PUT_LAPLACE_WAIT2;
when STATE_PUT_LAPLACE_WAIT2 =>
state <= STATE_PUT_LAPLACE;
when STATE_PUT_LAPLACE =>
reconos_mbox_put(done,success,o_osif,i_osif,C_FIFO_PUT_HANDLE,
pix_out);
if done then
state <= STATE_PUT_LINE;
end if;
when STATE_FINAL =>
state <= STATE_FINAL;
end case;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
ba12587a2aebc496d88400476dfdfd96
| 0.579021 | 2.964847 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_fa4_test1.vhd
| 4 | 1,861 |
library ieee;
use ieee.numeric_bit.all;
-- Declare a 1-bit full-adder.
entity fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit
);
end entity fa1;
architecture fa1_rtl of fa1 is
begin
s_o <= a_i xor b_i xor c_i;
c_o <= (a_i and b_i) or (c_i and (a_i xor b_i));
end architecture fa1_rtl;
-- Declare and implement a 4-bit full-adder that uses the
-- 1-bit full-adder described above.
entity fa4 is
port (va_i, vb_i: in bit_vector (3 downto 0);
c_i: in bit;
vs_o: out bit_vector (3 downto 0);
c_o: out bit
);
end entity fa4;
architecture fa4_rtl of fa4 is
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit);
end component fa1;
-- internal carry signals propagation
signal c_int4, c_int3, c_int2, c_int1, c_int0: bit;
begin
-- carry in
c_int0 <= c_i;
-- slice 0
s0: fa1 port map (c_i => c_int0,
a_i => va_i(0),
b_i => vb_i(0),
s_o => vs_o(0),
c_o => c_int1
);
-- slice 1
s1: fa1 port map (c_i => c_int1,
a_i => va_i(1),
b_i => vb_i(1),
s_o => vs_o(1),
c_o => c_int2
);
-- slice 2
s2: fa1 port map (c_i => c_int2,
a_i => va_i(2),
b_i => vb_i(2),
s_o => vs_o(2),
c_o => c_int3
);
-- slice 3
s3: fa1 port map (c_i => c_int3,
a_i => va_i(3),
b_i => vb_i(3),
s_o => vs_o(3),
c_o => c_int4
);
-- carry out
c_o <= c_int4;
end architecture fa4_rtl;
|
gpl-2.0
|
a35a7efaaf8572874e8d14697eb721c3
| 0.40892 | 2.991961 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/gc_shiftreg.vhd
| 2 | 1,469 |
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.genram_pkg.all;
entity gc_shiftreg is
generic (
g_size : integer);
port (
clk_i : in std_logic;
en_i : in std_logic;
d_i : in std_logic;
q_o : out std_logic;
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0));
end gc_shiftreg;
architecture wrapper of gc_shiftreg is
component SRLC32E
port (
Q : out std_ulogic;
A : in std_logic_vector (4 downto 0);
CE : in std_ulogic;
CLK : in std_ulogic;
D : in std_ulogic);
end component;
signal a : std_logic_vector(4 downto 0);
signal sr : std_logic_vector(g_size-1 downto 0);
begin -- wrapper
assert (g_size <= 32) report "gc_shiftreg[xilinx]: forced SRL32 implementation can be done only for 32-bit or smaller shift registers" severity warning;
a <= std_logic_vector(resize(unsigned(a_i), 5));
gen_srl32 : if(g_size <= 32) generate
U_SRLC32 : SRLC32E
port map (
Q => q_o,
A => a,
CE => en_i,
CLK => clk_i,
D => d_i);
end generate gen_srl32;
gen_inferred : if(g_size > 32) generate
p_srl : process(clk_i)
begin
if rising_edge(clk_i) then
if en_i = '1' then
sr <= sr(sr'left - 1 downto 0) & d_i;
end if;
end if;
end process;
q_o <= sr(TO_INTEGER(unsigned(a_i)));
end generate gen_inferred;
end wrapper;
|
lgpl-3.0
|
bef1215bbb52797080f7f64c99767b8f
| 0.575221 | 2.997959 | false | false | false | false |
luebbers/reconos
|
support/templates/bfmsim_xps_osif_v2_01_a/simulation/behavioral/bfm_system.vhd
| 1 | 31,801 |
-------------------------------------------------------------------------------
-- bfm_system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bfm_system is
port (
sys_reset : in std_logic;
sys_clk : in std_logic
);
end bfm_system;
architecture STRUCTURE of bfm_system is
component bfm_processor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_MAddrAck : in std_logic;
PLB_MSsize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_buslock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 15);
M_msize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 127);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic
);
end component;
component bfm_memory_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MIRQ : out std_logic_vector(0 to 1)
);
end component;
component bfm_monitor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 3);
M_buslock : in std_logic_vector(0 to 1);
M_RNW : in std_logic_vector(0 to 1);
M_BE : in std_logic_vector(0 to 31);
M_msize : in std_logic_vector(0 to 3);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_TAttribute : in std_logic_vector(0 to 31);
M_lockErr : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_UABus : in std_logic_vector(0 to 63);
M_ABus : in std_logic_vector(0 to 63);
M_wrDBus : in std_logic_vector(0 to 255);
M_wrBurst : in std_logic_vector(0 to 1);
M_rdBurst : in std_logic_vector(0 to 1);
PLB_MAddrAck : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic_vector(0 to 1);
PLB_MTimeout : in std_logic_vector(0 to 1);
PLB_MBusy : in std_logic_vector(0 to 1);
PLB_MRdErr : in std_logic_vector(0 to 1);
PLB_MWrErr : in std_logic_vector(0 to 1);
PLB_MIRQ : in std_logic_vector(0 to 1);
PLB_MWrDAck : in std_logic_vector(0 to 1);
PLB_MRdDBus : in std_logic_vector(0 to 255);
PLB_MRdWdAddr : in std_logic_vector(0 to 7);
PLB_MRdDAck : in std_logic_vector(0 to 1);
PLB_MRdBTerm : in std_logic_vector(0 to 1);
PLB_MWrBTerm : in std_logic_vector(0 to 1);
PLB_Mssize : in std_logic_vector(0 to 3);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to 0);
PLB_wrPrim : in std_logic_vector(0 to 0);
PLB_MasterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to 0);
Sl_wait : in std_logic_vector(0 to 0);
Sl_rearbitrate : in std_logic_vector(0 to 0);
Sl_wrDAck : in std_logic_vector(0 to 0);
Sl_wrComp : in std_logic_vector(0 to 0);
Sl_wrBTerm : in std_logic_vector(0 to 0);
Sl_rdDBus : in std_logic_vector(0 to 127);
Sl_rdWdAddr : in std_logic_vector(0 to 3);
Sl_rdDAck : in std_logic_vector(0 to 0);
Sl_rdComp : in std_logic_vector(0 to 0);
Sl_rdBTerm : in std_logic_vector(0 to 0);
Sl_MBusy : in std_logic_vector(0 to 1);
Sl_MRdErr : in std_logic_vector(0 to 1);
Sl_MWrErr : in std_logic_vector(0 to 1);
Sl_MIRQ : in std_logic_vector(0 to 1);
Sl_ssize : in std_logic_vector(0 to 1);
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to 127);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to 1);
PLB_SMRdErr : in std_logic_vector(0 to 1);
PLB_SMWrErr : in std_logic_vector(0 to 1);
PLB_SMIRQ : in std_logic_vector(0 to 1);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end component;
component synch_bus_wrapper is
port (
FROM_SYNCH_OUT : in std_logic_vector(0 to 127);
TO_SYNCH_IN : out std_logic_vector(0 to 31)
);
end component;
component plb_bus_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 0);
MPLB_Rst : out std_logic_vector(0 to 1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 63);
M_UABus : in std_logic_vector(0 to 63);
M_BE : in std_logic_vector(0 to 31);
M_RNW : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_busLock : in std_logic_vector(0 to 1);
M_TAttribute : in std_logic_vector(0 to 31);
M_lockErr : in std_logic_vector(0 to 1);
M_MSize : in std_logic_vector(0 to 3);
M_priority : in std_logic_vector(0 to 3);
M_rdBurst : in std_logic_vector(0 to 1);
M_request : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_wrBurst : in std_logic_vector(0 to 1);
M_wrDBus : in std_logic_vector(0 to 255);
Sl_addrAck : in std_logic_vector(0 to 0);
Sl_MRdErr : in std_logic_vector(0 to 1);
Sl_MWrErr : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 0);
Sl_rdComp : in std_logic_vector(0 to 0);
Sl_rdDAck : in std_logic_vector(0 to 0);
Sl_rdDBus : in std_logic_vector(0 to 127);
Sl_rdWdAddr : in std_logic_vector(0 to 3);
Sl_rearbitrate : in std_logic_vector(0 to 0);
Sl_SSize : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 0);
Sl_wrBTerm : in std_logic_vector(0 to 0);
Sl_wrComp : in std_logic_vector(0 to 0);
Sl_wrDAck : in std_logic_vector(0 to 0);
Sl_MIRQ : in std_logic_vector(0 to 1);
PLB_MIRQ : out std_logic_vector(0 to 1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 15);
PLB_MAddrAck : out std_logic_vector(0 to 1);
PLB_MTimeout : out std_logic_vector(0 to 1);
PLB_MBusy : out std_logic_vector(0 to 1);
PLB_MRdErr : out std_logic_vector(0 to 1);
PLB_MWrErr : out std_logic_vector(0 to 1);
PLB_MRdBTerm : out std_logic_vector(0 to 1);
PLB_MRdDAck : out std_logic_vector(0 to 1);
PLB_MRdDBus : out std_logic_vector(0 to 255);
PLB_MRdWdAddr : out std_logic_vector(0 to 7);
PLB_MRearbitrate : out std_logic_vector(0 to 1);
PLB_MWrBTerm : out std_logic_vector(0 to 1);
PLB_MWrDAck : out std_logic_vector(0 to 1);
PLB_MSSize : out std_logic_vector(0 to 3);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 0);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 127);
PLB_wrPrim : out std_logic_vector(0 to 0);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 1);
PLB_SMWrErr : out std_logic_vector(0 to 1);
PLB_SMBusy : out std_logic_vector(0 to 1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 127);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
PLB2OPB_rearb : in std_logic_vector(0 to 0);
Bus_Error_Det : out std_logic
);
end component;
component my_core_wrapper is
port (
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 15);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 127);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end component;
-- Internal signals
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd2 : std_logic_vector(0 to 1);
signal net_gnd10 : std_logic_vector(0 to 9);
signal net_gnd32 : std_logic_vector(0 to 31);
signal pgassign1 : std_logic_vector(0 to 127);
signal plb_bus_MPLB_Rst : std_logic_vector(0 to 1);
signal plb_bus_M_ABus : std_logic_vector(0 to 63);
signal plb_bus_M_BE : std_logic_vector(0 to 31);
signal plb_bus_M_MSize : std_logic_vector(0 to 3);
signal plb_bus_M_RNW : std_logic_vector(0 to 1);
signal plb_bus_M_TAttribute : std_logic_vector(0 to 31);
signal plb_bus_M_UABus : std_logic_vector(0 to 63);
signal plb_bus_M_abort : std_logic_vector(0 to 1);
signal plb_bus_M_busLock : std_logic_vector(0 to 1);
signal plb_bus_M_lockErr : std_logic_vector(0 to 1);
signal plb_bus_M_priority : std_logic_vector(0 to 3);
signal plb_bus_M_rdBurst : std_logic_vector(0 to 1);
signal plb_bus_M_request : std_logic_vector(0 to 1);
signal plb_bus_M_size : std_logic_vector(0 to 7);
signal plb_bus_M_type : std_logic_vector(0 to 5);
signal plb_bus_M_wrBurst : std_logic_vector(0 to 1);
signal plb_bus_M_wrDBus : std_logic_vector(0 to 255);
signal plb_bus_PLB_ABus : std_logic_vector(0 to 31);
signal plb_bus_PLB_BE : std_logic_vector(0 to 15);
signal plb_bus_PLB_MAddrAck : std_logic_vector(0 to 1);
signal plb_bus_PLB_MBusy : std_logic_vector(0 to 1);
signal plb_bus_PLB_MIRQ : std_logic_vector(0 to 1);
signal plb_bus_PLB_MRdBTerm : std_logic_vector(0 to 1);
signal plb_bus_PLB_MRdDAck : std_logic_vector(0 to 1);
signal plb_bus_PLB_MRdDBus : std_logic_vector(0 to 255);
signal plb_bus_PLB_MRdErr : std_logic_vector(0 to 1);
signal plb_bus_PLB_MRdWdAddr : std_logic_vector(0 to 7);
signal plb_bus_PLB_MRearbitrate : std_logic_vector(0 to 1);
signal plb_bus_PLB_MSSize : std_logic_vector(0 to 3);
signal plb_bus_PLB_MSize : std_logic_vector(0 to 1);
signal plb_bus_PLB_MTimeout : std_logic_vector(0 to 1);
signal plb_bus_PLB_MWrBTerm : std_logic_vector(0 to 1);
signal plb_bus_PLB_MWrDAck : std_logic_vector(0 to 1);
signal plb_bus_PLB_MWrErr : std_logic_vector(0 to 1);
signal plb_bus_PLB_PAValid : std_logic;
signal plb_bus_PLB_RNW : std_logic;
signal plb_bus_PLB_Rst : std_logic;
signal plb_bus_PLB_SAValid : std_logic;
signal plb_bus_PLB_SMBusy : std_logic_vector(0 to 1);
signal plb_bus_PLB_SMRdErr : std_logic_vector(0 to 1);
signal plb_bus_PLB_SMWrErr : std_logic_vector(0 to 1);
signal plb_bus_PLB_SaddrAck : std_logic;
signal plb_bus_PLB_SrdBTerm : std_logic;
signal plb_bus_PLB_SrdComp : std_logic;
signal plb_bus_PLB_SrdDAck : std_logic;
signal plb_bus_PLB_SrdDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_SrdWdAddr : std_logic_vector(0 to 3);
signal plb_bus_PLB_Srearbitrate : std_logic;
signal plb_bus_PLB_Sssize : std_logic_vector(0 to 1);
signal plb_bus_PLB_Swait : std_logic;
signal plb_bus_PLB_SwrBTerm : std_logic;
signal plb_bus_PLB_SwrComp : std_logic;
signal plb_bus_PLB_SwrDAck : std_logic;
signal plb_bus_PLB_TAttribute : std_logic_vector(0 to 15);
signal plb_bus_PLB_UABus : std_logic_vector(0 to 31);
signal plb_bus_PLB_abort : std_logic;
signal plb_bus_PLB_busLock : std_logic;
signal plb_bus_PLB_lockErr : std_logic;
signal plb_bus_PLB_masterID : std_logic_vector(0 to 0);
signal plb_bus_PLB_rdBurst : std_logic;
signal plb_bus_PLB_rdPrim : std_logic_vector(0 to 0);
signal plb_bus_PLB_rdpendPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_rdpendReq : std_logic;
signal plb_bus_PLB_reqPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_size : std_logic_vector(0 to 3);
signal plb_bus_PLB_type : std_logic_vector(0 to 2);
signal plb_bus_PLB_wrBurst : std_logic;
signal plb_bus_PLB_wrDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_wrPrim : std_logic_vector(0 to 0);
signal plb_bus_PLB_wrpendPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_wrpendReq : std_logic;
signal plb_bus_Sl_MBusy : std_logic_vector(0 to 1);
signal plb_bus_Sl_MIRQ : std_logic_vector(0 to 1);
signal plb_bus_Sl_MRdErr : std_logic_vector(0 to 1);
signal plb_bus_Sl_MWrErr : std_logic_vector(0 to 1);
signal plb_bus_Sl_SSize : std_logic_vector(0 to 1);
signal plb_bus_Sl_addrAck : std_logic_vector(0 to 0);
signal plb_bus_Sl_rdBTerm : std_logic_vector(0 to 0);
signal plb_bus_Sl_rdComp : std_logic_vector(0 to 0);
signal plb_bus_Sl_rdDAck : std_logic_vector(0 to 0);
signal plb_bus_Sl_rdDBus : std_logic_vector(0 to 127);
signal plb_bus_Sl_rdWdAddr : std_logic_vector(0 to 3);
signal plb_bus_Sl_rearbitrate : std_logic_vector(0 to 0);
signal plb_bus_Sl_wait : std_logic_vector(0 to 0);
signal plb_bus_Sl_wrBTerm : std_logic_vector(0 to 0);
signal plb_bus_Sl_wrComp : std_logic_vector(0 to 0);
signal plb_bus_Sl_wrDAck : std_logic_vector(0 to 0);
signal synch : std_logic_vector(0 to 31);
signal synch0 : std_logic_vector(0 to 31);
signal synch1 : std_logic_vector(0 to 31);
signal synch2 : std_logic_vector(0 to 31);
signal synch3 : std_logic_vector(0 to 31);
begin
-- Internal assignments
pgassign1(0 to 31) <= synch0(0 to 31);
pgassign1(32 to 63) <= synch1(0 to 31);
pgassign1(64 to 95) <= synch2(0 to 31);
pgassign1(96 to 127) <= synch3(0 to 31);
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd10(0 to 9) <= B"0000000000";
net_gnd2(0 to 1) <= B"00";
net_gnd32(0 to 31) <= B"00000000000000000000000000000000";
bfm_processor : bfm_processor_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch0,
SYNCH_IN => synch,
PLB_MAddrAck => plb_bus_PLB_MAddrAck(0),
PLB_MSsize => plb_bus_PLB_MSSize(0 to 1),
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate(0),
PLB_MTimeout => plb_bus_PLB_MTimeout(0),
PLB_MBusy => plb_bus_PLB_MBusy(0),
PLB_MRdErr => plb_bus_PLB_MRdErr(0),
PLB_MWrErr => plb_bus_PLB_MWrErr(0),
PLB_MIRQ => plb_bus_PLB_MIRQ(0),
PLB_MWrDAck => plb_bus_PLB_MWrDAck(0),
PLB_MRdDBus => plb_bus_PLB_MRdDBus(0 to 127),
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr(0 to 3),
PLB_MRdDAck => plb_bus_PLB_MRdDAck(0),
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm(0),
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm(0),
M_request => plb_bus_M_request(0),
M_priority => plb_bus_M_priority(0 to 1),
M_buslock => plb_bus_M_busLock(0),
M_RNW => plb_bus_M_RNW(0),
M_BE => plb_bus_M_BE(0 to 15),
M_msize => plb_bus_M_MSize(0 to 1),
M_size => plb_bus_M_size(0 to 3),
M_type => plb_bus_M_type(0 to 2),
M_TAttribute => plb_bus_M_TAttribute(0 to 15),
M_lockErr => plb_bus_M_lockErr(0),
M_abort => plb_bus_M_abort(0),
M_UABus => plb_bus_M_UABus(0 to 31),
M_ABus => plb_bus_M_ABus(0 to 31),
M_wrDBus => plb_bus_M_wrDBus(0 to 127),
M_wrBurst => plb_bus_M_wrBurst(0),
M_rdBurst => plb_bus_M_rdBurst(0)
);
bfm_memory : bfm_memory_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch1,
SYNCH_IN => synch,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim(0),
PLB_wrPrim => plb_bus_PLB_wrPrim(0),
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_msize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_TAttribute => plb_bus_PLB_TAttribute,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_UABus => plb_bus_PLB_UABus,
PLB_ABus => plb_bus_PLB_ABus,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdpendReq => plb_bus_PLB_rdpendReq,
PLB_wrpendReq => plb_bus_PLB_wrpendReq,
PLB_rdpendPri => plb_bus_PLB_rdpendPri,
PLB_wrpendPri => plb_bus_PLB_wrpendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
Sl_addrAck => plb_bus_Sl_addrAck(0),
Sl_ssize => plb_bus_Sl_SSize,
Sl_wait => plb_bus_Sl_wait(0),
Sl_rearbitrate => plb_bus_Sl_rearbitrate(0),
Sl_wrDAck => plb_bus_Sl_wrDAck(0),
Sl_wrComp => plb_bus_Sl_wrComp(0),
Sl_wrBTerm => plb_bus_Sl_wrBTerm(0),
Sl_rdDBus => plb_bus_Sl_rdDBus,
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr,
Sl_rdDAck => plb_bus_Sl_rdDAck(0),
Sl_rdComp => plb_bus_Sl_rdComp(0),
Sl_rdBTerm => plb_bus_Sl_rdBTerm(0),
Sl_MBusy => plb_bus_Sl_MBusy,
Sl_MRdErr => plb_bus_Sl_MRdErr,
Sl_MWrErr => plb_bus_Sl_MWrErr,
Sl_MIRQ => plb_bus_Sl_MIRQ
);
bfm_monitor : bfm_monitor_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch2,
SYNCH_IN => synch,
M_request => plb_bus_M_request,
M_priority => plb_bus_M_priority,
M_buslock => plb_bus_M_busLock,
M_RNW => plb_bus_M_RNW,
M_BE => plb_bus_M_BE,
M_msize => plb_bus_M_MSize,
M_size => plb_bus_M_size,
M_type => plb_bus_M_type,
M_TAttribute => plb_bus_M_TAttribute,
M_lockErr => plb_bus_M_lockErr,
M_abort => plb_bus_M_abort,
M_UABus => plb_bus_M_UABus,
M_ABus => plb_bus_M_ABus,
M_wrDBus => plb_bus_M_wrDBus,
M_wrBurst => plb_bus_M_wrBurst,
M_rdBurst => plb_bus_M_rdBurst,
PLB_MAddrAck => plb_bus_PLB_MAddrAck,
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate,
PLB_MTimeout => plb_bus_PLB_MTimeout,
PLB_MBusy => plb_bus_PLB_MBusy,
PLB_MRdErr => plb_bus_PLB_MRdErr,
PLB_MWrErr => plb_bus_PLB_MWrErr,
PLB_MIRQ => plb_bus_PLB_MIRQ,
PLB_MWrDAck => plb_bus_PLB_MWrDAck,
PLB_MRdDBus => plb_bus_PLB_MRdDBus,
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr,
PLB_MRdDAck => plb_bus_PLB_MRdDAck,
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm,
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm,
PLB_Mssize => plb_bus_PLB_MSSize,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim(0 to 0),
PLB_wrPrim => plb_bus_PLB_wrPrim(0 to 0),
PLB_MasterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_msize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_TAttribute => plb_bus_PLB_TAttribute,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_UABus => plb_bus_PLB_UABus,
PLB_ABus => plb_bus_PLB_ABus,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdpendReq => plb_bus_PLB_rdpendReq,
PLB_wrpendReq => plb_bus_PLB_wrpendReq,
PLB_rdpendPri => plb_bus_PLB_rdpendPri,
PLB_wrpendPri => plb_bus_PLB_wrpendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
Sl_addrAck => plb_bus_Sl_addrAck(0 to 0),
Sl_wait => plb_bus_Sl_wait(0 to 0),
Sl_rearbitrate => plb_bus_Sl_rearbitrate(0 to 0),
Sl_wrDAck => plb_bus_Sl_wrDAck(0 to 0),
Sl_wrComp => plb_bus_Sl_wrComp(0 to 0),
Sl_wrBTerm => plb_bus_Sl_wrBTerm(0 to 0),
Sl_rdDBus => plb_bus_Sl_rdDBus,
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr,
Sl_rdDAck => plb_bus_Sl_rdDAck(0 to 0),
Sl_rdComp => plb_bus_Sl_rdComp(0 to 0),
Sl_rdBTerm => plb_bus_Sl_rdBTerm(0 to 0),
Sl_MBusy => plb_bus_Sl_MBusy,
Sl_MRdErr => plb_bus_Sl_MRdErr,
Sl_MWrErr => plb_bus_Sl_MWrErr,
Sl_MIRQ => plb_bus_Sl_MIRQ,
Sl_ssize => plb_bus_Sl_SSize,
PLB_SaddrAck => plb_bus_PLB_SaddrAck,
PLB_Swait => plb_bus_PLB_Swait,
PLB_Srearbitrate => plb_bus_PLB_Srearbitrate,
PLB_SwrDAck => plb_bus_PLB_SwrDAck,
PLB_SwrComp => plb_bus_PLB_SwrComp,
PLB_SwrBTerm => plb_bus_PLB_SwrBTerm,
PLB_SrdDBus => plb_bus_PLB_SrdDBus,
PLB_SrdWdAddr => plb_bus_PLB_SrdWdAddr,
PLB_SrdDAck => plb_bus_PLB_SrdDAck,
PLB_SrdComp => plb_bus_PLB_SrdComp,
PLB_SrdBTerm => plb_bus_PLB_SrdBTerm,
PLB_SMBusy => plb_bus_PLB_SMBusy,
PLB_SMRdErr => plb_bus_PLB_SMRdErr,
PLB_SMWrErr => plb_bus_PLB_SMWrErr,
PLB_SMIRQ => net_gnd2,
PLB_Sssize => plb_bus_PLB_Sssize
);
synch_bus : synch_bus_wrapper
port map (
FROM_SYNCH_OUT => pgassign1,
TO_SYNCH_IN => synch
);
plb_bus : plb_bus_wrapper
port map (
PLB_Clk => sys_clk,
SYS_Rst => sys_reset,
PLB_Rst => plb_bus_PLB_Rst,
SPLB_Rst => open,
MPLB_Rst => plb_bus_MPLB_Rst,
PLB_dcrAck => open,
PLB_dcrDBus => open,
DCR_ABus => net_gnd10,
DCR_DBus => net_gnd32,
DCR_Read => net_gnd0,
DCR_Write => net_gnd0,
M_ABus => plb_bus_M_ABus,
M_UABus => plb_bus_M_UABus,
M_BE => plb_bus_M_BE,
M_RNW => plb_bus_M_RNW,
M_abort => plb_bus_M_abort,
M_busLock => plb_bus_M_busLock,
M_TAttribute => plb_bus_M_TAttribute,
M_lockErr => plb_bus_M_lockErr,
M_MSize => plb_bus_M_MSize,
M_priority => plb_bus_M_priority,
M_rdBurst => plb_bus_M_rdBurst,
M_request => plb_bus_M_request,
M_size => plb_bus_M_size,
M_type => plb_bus_M_type,
M_wrBurst => plb_bus_M_wrBurst,
M_wrDBus => plb_bus_M_wrDBus,
Sl_addrAck => plb_bus_Sl_addrAck(0 to 0),
Sl_MRdErr => plb_bus_Sl_MRdErr,
Sl_MWrErr => plb_bus_Sl_MWrErr,
Sl_MBusy => plb_bus_Sl_MBusy,
Sl_rdBTerm => plb_bus_Sl_rdBTerm(0 to 0),
Sl_rdComp => plb_bus_Sl_rdComp(0 to 0),
Sl_rdDAck => plb_bus_Sl_rdDAck(0 to 0),
Sl_rdDBus => plb_bus_Sl_rdDBus,
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr,
Sl_rearbitrate => plb_bus_Sl_rearbitrate(0 to 0),
Sl_SSize => plb_bus_Sl_SSize,
Sl_wait => plb_bus_Sl_wait(0 to 0),
Sl_wrBTerm => plb_bus_Sl_wrBTerm(0 to 0),
Sl_wrComp => plb_bus_Sl_wrComp(0 to 0),
Sl_wrDAck => plb_bus_Sl_wrDAck(0 to 0),
Sl_MIRQ => plb_bus_Sl_MIRQ,
PLB_MIRQ => plb_bus_PLB_MIRQ,
PLB_ABus => plb_bus_PLB_ABus,
PLB_UABus => plb_bus_PLB_UABus,
PLB_BE => plb_bus_PLB_BE,
PLB_MAddrAck => plb_bus_PLB_MAddrAck,
PLB_MTimeout => plb_bus_PLB_MTimeout,
PLB_MBusy => plb_bus_PLB_MBusy,
PLB_MRdErr => plb_bus_PLB_MRdErr,
PLB_MWrErr => plb_bus_PLB_MWrErr,
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm,
PLB_MRdDAck => plb_bus_PLB_MRdDAck,
PLB_MRdDBus => plb_bus_PLB_MRdDBus,
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr,
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate,
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm,
PLB_MWrDAck => plb_bus_PLB_MWrDAck,
PLB_MSSize => plb_bus_PLB_MSSize,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_RNW => plb_bus_PLB_RNW,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_TAttribute => plb_bus_PLB_TAttribute,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_MSize => plb_bus_PLB_MSize,
PLB_rdPendPri => plb_bus_PLB_rdpendPri,
PLB_wrPendPri => plb_bus_PLB_wrpendPri,
PLB_rdPendReq => plb_bus_PLB_rdpendReq,
PLB_wrPendReq => plb_bus_PLB_wrpendReq,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdPrim => plb_bus_PLB_rdPrim(0 to 0),
PLB_reqPri => plb_bus_PLB_reqPri,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrPrim => plb_bus_PLB_wrPrim(0 to 0),
PLB_SaddrAck => plb_bus_PLB_SaddrAck,
PLB_SMRdErr => plb_bus_PLB_SMRdErr,
PLB_SMWrErr => plb_bus_PLB_SMWrErr,
PLB_SMBusy => plb_bus_PLB_SMBusy,
PLB_SrdBTerm => plb_bus_PLB_SrdBTerm,
PLB_SrdComp => plb_bus_PLB_SrdComp,
PLB_SrdDAck => plb_bus_PLB_SrdDAck,
PLB_SrdDBus => plb_bus_PLB_SrdDBus,
PLB_SrdWdAddr => plb_bus_PLB_SrdWdAddr,
PLB_Srearbitrate => plb_bus_PLB_Srearbitrate,
PLB_Sssize => plb_bus_PLB_Sssize,
PLB_Swait => plb_bus_PLB_Swait,
PLB_SwrBTerm => plb_bus_PLB_SwrBTerm,
PLB_SwrComp => plb_bus_PLB_SwrComp,
PLB_SwrDAck => plb_bus_PLB_SwrDAck,
PLB2OPB_rearb => net_gnd1(0 to 0),
Bus_Error_Det => open
);
my_core : my_core_wrapper
port map (
MPLB_Clk => sys_clk,
MPLB_Rst => plb_bus_MPLB_Rst(1),
M_request => plb_bus_M_request(1),
M_priority => plb_bus_M_priority(2 to 3),
M_busLock => plb_bus_M_busLock(1),
M_RNW => plb_bus_M_RNW(1),
M_BE => plb_bus_M_BE(16 to 31),
M_MSize => plb_bus_M_MSize(2 to 3),
M_size => plb_bus_M_size(4 to 7),
M_type => plb_bus_M_type(3 to 5),
M_TAttribute => plb_bus_M_TAttribute(16 to 31),
M_lockErr => plb_bus_M_lockErr(1),
M_abort => plb_bus_M_abort(1),
M_UABus => plb_bus_M_UABus(32 to 63),
M_ABus => plb_bus_M_ABus(32 to 63),
M_wrDBus => plb_bus_M_wrDBus(128 to 255),
M_wrBurst => plb_bus_M_wrBurst(1),
M_rdBurst => plb_bus_M_rdBurst(1),
PLB_MAddrAck => plb_bus_PLB_MAddrAck(1),
PLB_MSSize => plb_bus_PLB_MSSize(2 to 3),
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate(1),
PLB_MTimeout => plb_bus_PLB_MTimeout(1),
PLB_MBusy => plb_bus_PLB_MBusy(1),
PLB_MRdErr => plb_bus_PLB_MRdErr(1),
PLB_MWrErr => plb_bus_PLB_MWrErr(1),
PLB_MIRQ => plb_bus_PLB_MIRQ(1),
PLB_MRdDBus => plb_bus_PLB_MRdDBus(128 to 255),
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr(4 to 7),
PLB_MRdDAck => plb_bus_PLB_MRdDAck(1),
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm(1),
PLB_MWrDAck => plb_bus_PLB_MWrDAck(1),
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm(1),
SYNCH_IN => synch,
SYNCH_OUT => synch3
);
end architecture STRUCTURE;
|
gpl-3.0
|
3561ec616ee6c8f1daba52ef7914b386
| 0.607434 | 3.027513 | false | false | false | false |
luebbers/reconos
|
support/pcores/dcrfifo_v1_00_a/hdl/vhdl/dcrfifo.vhd
| 1 | 9,115 |
--!
--! \file dcrfifo.vhd
--!
--! Implementation of a FIFO with DCR bus attachment.
--!
--! control register : BASE_ADDR
--! when read:
--! bit 31 = underrun indicator (initial: 0)
--! bit 30 = overflow indicator (initial: 0)
--! bit 28 = write only indicator (initial: 1)
--! bits 0 to 27 = number of words in FIFO (initial: 0)
--!
--! Writing 0xAFFEBEAF to the control register clears the write only bit.
--! Reading from the FIFO then becomes possible. Writing 0xAFFEDEAD to
--! the control register resets the FIFO. This is at the moment the only
--! way to clear the underrun and overflow bits. Writing any other value
--! to the control register sets the write only bit. This is a precaution
--! to protect the FIFO from crazy operating systems.
--!
--! fifo resgister : BASE_ADDR + 1
--! Reading from the fifo register returns the first word in the FIFO.
--! If the FIFO is empty the result is undefined and the underrun bit is
--! set.
--! When the write only bit is cleared, reading from the fifo register
--! also advances to the next word in the fifo. IF the write only bit is
--! set, reads from the fifo register do not alter the contents of the
--! FIFO.
--! Writing a word to the fifo register puts that word into the FIFO
--! unless no more space is left. In that case the value written is
--! discarded and the overflow bit is set.
--!
--!
--! \author Andreas Agne <[email protected]>
--! \date 18.02.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major changes
-- 18.02.2009 Andreas Agne Initial implementation
---
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dcrfifo is
generic (
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_NUM_REGS : integer := 2;
C_FIFO_AWIDTH : integer := 15
);
port ( -- the DCR bus interface
clk : in std_logic;
reset : in std_logic; -- high active synchronous
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(C_DCR_DWIDTH-1 downto 0);
i_dcrABus : in std_logic_vector(C_DCR_AWIDTH-1 downto 0);
i_dcrDBus : in std_logic_vector(C_DCR_DWIDTH-1 downto 0);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic
);
end dcrfifo;
architecture Behavioral of dcrfifo is
-- address of status register (read only)
constant ADDR_COUNT : std_logic_vector := C_DCR_BASEADDR;
-- address of fifo register (read/write)
constant ADDR_FIFO : std_logic_vector := C_DCR_BASEADDR + 1;
-- fifo count width
constant FIFO_DEPTH : integer := 2**C_FIFO_AWIDTH;
-- fifo memory type
type t_ram is array (FIFO_DEPTH-1 downto 0) of std_logic_vector(C_DCR_DWIDTH-1 downto 0);
-- fifo memory
signal fifo_mem : t_ram;
-- fifo output
signal fifo_out : std_logic_vector(C_DCR_DWIDTH-1 downto 0);
-- fifo input
signal fifo_in : std_logic_vector(C_DCR_DWIDTH-1 downto 0);
-- fifo output address register
signal fifo_outaddr : std_logic_vector(C_FIFO_AWIDTH-1 downto 0);
-- fifo input address register
signal fifo_inaddr : std_logic_vector(C_FIFO_AWIDTH-1 downto 0);
-- fifo count register
signal fifo_count : std_logic_vector(C_FIFO_AWIDTH-1 downto 0);
-- fifo write_enable signal
signal fifo_we : std_logic;
-- advance to next output word
signal fifo_next : std_logic;
-- fifo full indicator
signal fifo_full : std_logic;
-- fifo empty indicator
signal fifo_empty : std_logic;
-- fifo overflow
signal fifo_overflow : std_logic;
-- fifo underrun
signal fifo_underrun : std_logic;
-- fifo contol
signal fifo_ctrl : std_logic;
-- fifo write only
signal fifo_wronly_set : std_logic;
signal fifo_wronly : std_logic;
-- fifo reset
signal fifo_reset : std_logic;
-- registers indicating type of request
signal readStateReg : std_logic;
signal writeStateReg : std_logic;
signal readFifoReg : std_logic;
signal writeFifoReg : std_logic;
-- asynchronous signals indicating type of request (input to the registers above)
signal readState : std_logic;
signal writeState : std_logic;
signal readFifo : std_logic;
signal writeFifo : std_logic;
begin
-- asynchronously determine the type of request
readState <= '1' when i_dcrRead = '1' and i_dcrABus = ADDR_COUNT else '0';
writeState <= '1' when i_dcrWrite = '1' and i_dcrABus = ADDR_COUNT else '0';
readFifo <= '1' when i_dcrRead = '1' and i_dcrABus = ADDR_FIFO else '0';
writeFifo <= '1' when i_dcrWrite = '1' and i_dcrABus = ADDR_FIFO else '0';
-- DCR ack
o_dcrAck <= readStateReg or readFifoReg or writeFifoReg or writeStateReg;
-- fifo advance to next word
fifo_next <= readFifoReg and (not readFifo);
-- fifo write enable
fifo_we <= (not writeFifoReg) and writeFifo;
-- control register access
fifo_ctrl <= (not writeStateReg) and writeState;
-- connect fifo input to DCR
fifo_in <= i_dcrDBus;
-- fifo full and empty signals
fifo_empty <= '1' when CONV_INTEGER(fifo_count) = 0 else '0';
fifo_full <= '1' when CONV_INTEGER(fifo_count) = FIFO_DEPTH - 1 else '0';
-- fifo control signals
fifo_wronly_set <= '0' when i_dcrDBus = X"AFFEBEEF" else '1';
fifo_reset <= '1' when i_dcrDBus = X"AFFEDEAD" else '0';
-- bypass mux as in UG018 page 105 (data output for read requests)
bypass_mux : process (readFifo, readState, i_dcrDBus, fifo_count, fifo_out,
fifo_underrun, fifo_overflow, fifo_wronly)
begin
o_dcrDBus <= i_dcrDBus;
if readFifo = '1' then o_dcrDBus <= fifo_out;
elsif readState = '1' then
o_dcrDBus(C_FIFO_AWIDTH-1 downto 0) <= fifo_count;
o_dcrDBus(C_DCR_DWIDTH-1) <= fifo_underrun;
o_dcrDBus(C_DCR_DWIDTH-2) <= fifo_overflow;
o_dcrDBus(C_DCR_DWIDTH-7) <= fifo_wronly;
end if;
end process;
-- process registers that indicate the type of request
syn_req : process (clk, reset, readFifo, readState, writeFifo)
begin
if reset = '1' then
readStateReg <= '0';
readFifoReg <= '0';
writeFifoReg <= '0';
writeStateReg <= '0';
elsif rising_edge(clk) then
readStateReg <= '0';
readFifoReg <= '0';
writeFifoReg <= '0';
writeStateReg <= '0';
if readFifo = '1' then readFifoReg <= '1'; end if;
if readState = '1' then readStateReg <= '1'; end if;
if writeFifo = '1' then writeFifoReg <= '1'; end if;
if writeState = '1' then writeStateReg <= '1'; end if;
end if;
end process;
-- FIFO implementation: this inferres a two port block ram and some additional
-- control logic and registers
fifo : process (clk, reset, fifo_we, fifo_next, fifo_full, fifo_empty, fifo_reset,
fifo_ctrl, fifo_wronly, fifo_wronly_set)
begin
if reset = '1' then
fifo_inaddr <= (others => '0');
fifo_outaddr <= (others => '0');
fifo_count <= (others => '0');
fifo_overflow <= '0';
fifo_underrun <= '0';
fifo_wronly <= '1';
elsif rising_edge(clk) then
fifo_out <= fifo_mem(CONV_INTEGER(fifo_outaddr));
if fifo_ctrl = '1' then
if fifo_reset = '1' then
fifo_inaddr <= (others => '0');
fifo_outaddr <= (others => '0');
fifo_count <= (others => '0');
fifo_overflow <= '0';
fifo_underrun <= '0';
fifo_wronly <= '1';
end if;
fifo_wronly <= fifo_wronly_set;
elsif fifo_we = '1' then
if fifo_full = '1' then
fifo_overflow <= '1';
else
fifo_mem(CONV_INTEGER(fifo_inaddr)) <= fifo_in;
fifo_inaddr <= fifo_inaddr + 1;
fifo_count <= fifo_count + 1;
end if;
elsif fifo_next = '1' and fifo_wronly = '0' then
if fifo_empty = '1' then
fifo_underrun <= '1';
else
fifo_outaddr <= fifo_outaddr + 1;
fifo_count <= fifo_count - 1;
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
ee1ceee21abf98fab9a150c817466181
| 0.640702 | 3.326642 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v1_00_a/hdl/vhdl/command_fifo.vhd
| 4 | 28,631 |
-------------------------------------------------------------------------------
-- $Id: command_fifo.vhd,v 1.1 2005/02/17 20:29:35 crh Exp $
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename:
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:35 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.all;
use UNISIM.vcomponents.all;
entity command_fifo is
port (
Clk : in std_logic;
Reset : in std_logic;
NextCommand : in std_logic;
CommandNum : out std_logic_vector(8 downto 0);
Data : out std_logic_vector(15 downto 0);
Address : out std_logic_vector(6 downto 0);
ValidCommand: out std_logic
);
end entity command_fifo;
-- Commands for AC97:
-- WriteAC97Reg(0x0,0x0); // reset registers
-- WriteAC97Reg(0x2,0x808); // master volume (0db gain)
-- WriteAC97Reg(0xa,0x8000); // mute PC beep
-- WriteAC97Reg(0x4,0x808); // headphone vol (aux out)
-- WriteAC97Reg(0x18,0x808); // pcmoutvol (amp out line)
-- WriteAC97Reg(0x1a,0x404); // record source (line in for left and right)
-- WriteAC97Reg(0x1c,0x008); // record gain (8 steps of 1.5 dB = +12.0 dB)
-- WriteAC97Reg(0x20,0x1); // bypass 3d sound
-- 80000000
-- 80020808
-- 800a8000
-- 80040808
-- 80180808
-- 801a0404
-- 801c0008
-- 80200001
-- 80200001801c0008801a04048018080880040808800a80008002080880000000
architecture IMP of command_fifo is
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0a : string;
attribute INIT_0b : string;
attribute INIT_0c : string;
attribute INIT_0d : string;
attribute INIT_0e : string;
attribute INIT_0f : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1a : string;
attribute INIT_1b : string;
attribute INIT_1c : string;
attribute INIT_1d : string;
attribute INIT_1e : string;
attribute INIT_1f : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2a : string;
attribute INIT_2b : string;
attribute INIT_2c : string;
attribute INIT_2d : string;
attribute INIT_2e : string;
attribute INIT_2f : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3a : string;
attribute INIT_3b : string;
attribute INIT_3c : string;
attribute INIT_3d : string;
attribute INIT_3e : string;
attribute INIT_3f : string;
attribute INIT_00 of u1 : label is
"80200001801c0008801a04048018080880040808800a80008002080880000000";
attribute INIT_01 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_02 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_03 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_04 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_05 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_06 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_07 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_08 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_09 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0a of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0b of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0c of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0d of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0e of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0f of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_10 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_11 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1a of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1b of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1c of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1d of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1e of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1f of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2a of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2b of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2c of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2d of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2e of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2f of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_32 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_33 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_34 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_35 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_36 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_37 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_38 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3a of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3b of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3c of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3d of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3e of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3f of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
component RAMB16_S36
generic (
INIT : bit_vector := X"000000000";
SRVAL : bit_vector := X"000000000";
write_mode : string := "WRITE_FIRST";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
signal xram_di : std_logic_vector(31 downto 0); -- BlockRAM data in (zero)
signal command_addr : unsigned(8 downto 0); -- BlockRAM data in (zero)
signal xram_addr : std_logic_vector(8 downto 0); -- BlockRAM data in (zero)
signal xram_dip : std_logic_vector(3 downto 0); -- BlockRAM data in (zero)
signal xram_dop : std_logic_vector(3 downto 0); -- BlockRAM data out
signal xram_en : std_logic; -- BlockRAM enable (always on)
signal xram_we : std_logic; -- BlockRAM write enable (zero)
signal xram_reset : std_logic; -- BlockRAM reset (zero)
signal xram_do : std_logic_vector(31 downto 0);
begin
-- address (need to define)
block_ram_address_PROCESS : process (Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then
command_addr <= (others => '0');
elsif NextCommand = '1' then
command_addr <= command_addr + 1;
end if;
end if;
end process;
-- Define input signals to BlockRam
xram_di <= (others => '0'); -- no data in
xram_dip <= (others => '0'); -- 2-bit data (not used)
xram_en <= '1'; -- always enabled
xram_we <= '0'; -- do not need to write
xram_reset <= '0';
Data <= xram_do(15 downto 0);
Address <= xram_do(22 downto 16);
ValidCommand <= xram_do(31);
-- Instance the BlockRam
u1: RAMB16_S36
--translate_off
-- Note that the these generic map values are used for simulation
-- only. To insure that the simulation matches the actual ram values,
-- make sure that the attributes used above are the same as the
-- generics used below.
generic map (
INIT_00 =>
X"80200001801c0008801a04048018080880040808800a80008002080880000000",
INIT_01 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0a =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0b =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0e =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1a =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1b =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1c =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1d =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1e =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1f =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2a =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2b =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2c =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2d =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2e =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2f =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3a =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3b =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3c =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3d =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3e =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3f =>
X"0000000000000000000000000000000000000000000000000000000000000000"
)
--translate_on
port map(
di => xram_di,
dip => xram_dip,
addr => xram_addr,
do => xram_do,
dop => xram_dop,
clk => clk,
SSR => xram_reset,
EN => xram_en,
WE => xram_we
);
xram_addr <= CONV_STD_LOGIC_VECTOR(command_addr, command_addr'length);
CommandNum <= xram_addr;
end architecture IMP;
|
gpl-3.0
|
d2a32ef35b47eaab0e80df7b0a04b199
| 0.709406 | 5.919165 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v1_00_a/hdl/vhdl/TESTBENCH_ac97_fifo.vhd
| 4 | 12,653 |
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_fifo.vhd,v 1.1 2005/02/17 20:29:34 crh Exp $
-------------------------------------------------------------------------------
-- TESTBENCH_ac97_fifo.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_ac97_fifo.vhd
--
-- Description: Simple testbench for ac97_fifo
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:34 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBENCH_ac97_fifo is
end TESTBENCH_ac97_fifo;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.testbench_ac97_package.all;
architecture behavioral of TESTBENCH_ac97_fifo is
component ac97_fifo is
generic (
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLAYBACK : integer := 1;
C_RECORD : integer := 0;
C_INTR_LEVEL : integer := 1;
C_USE_BRAM : integer := 1
);
port (
-- IP Interface
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to 31);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic;
Bus2IP_WrCE : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
-- CODEC signals
Bit_Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic;
AC97Reset_n : out std_logic
);
end component;
component ac97_model is
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end component;
-- IP Interface
signal Bus2IP_Addr : std_logic_vector(0 to 31);
signal Bus2IP_Clk : std_logic;
signal Bus2IP_CS : std_logic;
signal Bus2IP_Data : std_logic_vector(0 to 31);
signal Bus2IP_BE : std_logic_vector(0 to 3);
signal Bus2IP_RdCE : std_logic;
signal Bus2IP_Reset : std_logic;
signal Bus2IP_WrCE : std_logic;
signal IP2Bus_Data : std_logic_vector(0 to 31);
signal Interrupt : std_logic;
signal Bit_Clk : std_logic;
signal Sync : std_logic;
signal SData_Out : std_logic;
signal SData_In : std_logic;
signal AC97Reset_n : std_logic;
signal test_no : integer;
signal IP_READ : std_logic_vector(0 to 31);
signal sample : integer := 0;
begin -- behavioral
uut_1 : ac97_model
port map (
AC97Reset_n => ac97reset_n,
Bit_Clk => Bit_Clk,
Sync => Sync,
SData_Out => SData_Out,
SData_In => SData_In
);
uut : ac97_fifo
generic map (
C_INTR_LEVEL => 1,
C_PLAYBACK => 1,
C_RECORD => 1
)
port map (
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => Bus2IP_Reset,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_Data => Bus2IP_Data,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
IP2Bus_Data => IP2Bus_Data,
Interrupt => Interrupt,
-- CODEC signals
Bit_Clk => Bit_Clk,
Sync => Sync,
SData_Out => SData_Out,
SData_In => SData_In,
AC97Reset_n => AC97Reset_n
);
clkgen_2: process
begin
Bus2IP_Clk<= '0';
wait for 5 ns;
Bus2IP_Clk<= '1';
wait for 5 ns;
end process;
-- simulate a reset
opb_rst_gen: process
begin
Bus2IP_Reset <= '1';
wait for 20 ns;
Bus2IP_Reset <= '0';
wait;
end process opb_rst_gen;
-- IP bus
IP_proc: process
begin
test_no <= 0;
Bus2IP_RdCE <= '0';
Bus2IP_WrCE <= '0';
Bus2IP_CS <= '0';
Bus2IP_ADDR <= (others => '0');
Bus2IP_DATA <= (others => '0');
IP_READ <= (others => '0');
-- skip some time slots before performing a bus cycle
for i in 100 downto 0 loop
wait until Bus2IP_Clk'event and BUS2IP_Clk='1';
end loop;
-- Test 7. Reset CODEC
test_no <= 7;
write_ip(Bus2IP_Clk, FIFO_CTRL_OFFSET, X"00000010", Bus2IP_CS,
Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, FIFO_CTRL_OFFSET, X"00000000", Bus2IP_CS,
Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
-- Test 1. Wait until codec ready is found (ready status)
test_no <= 1;
while IP_READ(26) /= '1' loop
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
for i in 50 downto 0 loop
wait until Bus2IP_Clk'event and BUS2IP_Clk='1';
end loop;
end loop;
-- Test #2: Clear FIFO status & read status again
test_no <= 2;
write_ip(Bus2IP_Clk, FIFO_CTRL_OFFSET, FIFO_CLEAR_MASK, Bus2IP_CS,
Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
-- Test #6: Write data into playback fifo
for i in 64 downto 0 loop
wait until Bus2IP_Clk'event and BUS2IP_Clk='1';
end loop;
test_no <= 6;
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"AAAA_5555", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"5555_AAAA", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"AAAA_5555", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"5555_AAAA", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"AAAA_5555", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"5555_AAAA", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"AAAA_5555", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"5555_AAAA", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
-- Test #3: Read AC 97 register
wait until sync'event and sync='1';
test_no <= 3;
-- Write to AC97_CTRL_ADDR (perform a AC97 "read")
-- Address = "41" (lower 7 bits)
-- Read = 1 "0b1xxx xxxx"
write_ip(Bus2IP_Clk, REG_ADDR_OFFSET, X"0000_00C1", Bus2IP_CS, Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
-- read from the status register until transfer is complete
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
while ip_read(27) /= '0' loop
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
end loop;
-- Now read the value of the data register returned
read_ip(Bus2IP_Clk, IP2Bus_Data, REG_DATA_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
-- Test #4: Write AC 97 register
for i in 128 downto 0 loop
wait until Bus2IP_Clk'event and BUS2IP_Clk='1';
end loop;
test_no <= 4;
write_ip(Bus2IP_Clk, REG_DATA_WRITE_OFFSET, X"0000_8001",
Bus2IP_CS, Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
-- Write to AC97_CTRL_ADDR (perform a AC97 "write")
-- Address = "41" (lower 7 bits)
-- Read = 0 "0b1xxx xxxx"
write_ip(Bus2IP_Clk, REG_ADDR_OFFSET, X"0000_0041", Bus2IP_CS, Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
while ip_read(27) /= '0' loop
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
end loop;
-- Test #5: Read Playback data
for i in 64 downto 0 loop
wait until Bus2IP_Clk'event and BUS2IP_Clk='1';
end loop;
test_no <= 5;
read_ip(Bus2IP_Clk, IP2Bus_Data, IN_FIFO_OFFSET,Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
read_ip(Bus2IP_Clk, IP2Bus_Data, IN_FIFO_OFFSET,Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
read_ip(Bus2IP_Clk, IP2Bus_Data, IN_FIFO_OFFSET,Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
read_ip(Bus2IP_Clk, IP2Bus_Data, IN_FIFO_OFFSET,Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
-- Test #8 - Interrupt
test_no <= 8;
-- Clear FIFO & read status
write_ip(Bus2IP_Clk, FIFO_CTRL_OFFSET, FIFO_CLEAR_MASK, Bus2IP_CS,
Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
read_ip(Bus2IP_Clk, IP2Bus_Data, STATUS_OFFSET, Bus2IP_CS, Bus2IP_Addr,
Bus2IP_RdCE, ip_read);
-- Fill FIFO
for i in 512 downto 0 loop
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
end loop;
-- Enable interrupts
write_ip(Bus2IP_Clk, FIFO_CTRL_OFFSET, ENABLE_PLAY_INT_MASK, Bus2IP_CS,
Bus2IP_Addr,
Bus2IP_Data, Bus2IP_WrCE);
-- Wait until an interrupt occurs
wait until Interrupt'event and Interrupt = '1';
-- Wait for a few more samples
for i in 3 downto 0 loop
wait until sync'event and sync='1';
end loop;
-- Put some more data into the Fifo and make sure the interrupt goes away
for i in 8 downto 0 loop
write_ip(Bus2IP_Clk, OUT_FIFO_OFFSET, X"8001_8001", Bus2IP_CS,
Bus2IP_Addr, Bus2IP_Data, Bus2IP_WrCE);
end loop;
wait;
end process;
end behavioral;
|
gpl-3.0
|
ede649fc6b3f3e9479b0cdf3a4940e0c
| 0.528175 | 3.191173 | false | true | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/GPIO/src/hdl/debouncer.vhd
| 1 | 3,415 |
----------------------------------------------------------------------------
-- debouncer.vhd -- Signal Debouncer
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2011 Digilent, Inc.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- This component is used to debounce signals. It is designed to
-- independently debounce a variable number of signals, the number of which
-- are set using the PORT_WIDTH generic. Debouncing is done by only
-- registering a change in a button state if it remains constant for
-- the number of clocks determined by the DEBNC_CLOCKS generic.
--
-- Generic Descriptions:
--
-- PORT_WIDTH - The number of signals to debounce. determines the width
-- of the SIGNAL_I and SIGNAL_O std_logic_vectors
-- DEBNC_CLOCKS - The number of clocks (CLK_I) to wait before registering
-- a change.
--
-- Port Descriptions:
--
-- SIGNAL_I - The input signals. A vector of width equal to PORT_WIDTH
-- CLK_I - Input clock
-- SIGNAL_O - The debounced signals. A vector of width equal to PORT_WIDTH
--
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2011(SamB): Created using Xilinx Tools 13.2
-- 08/29/2013(SamB): Improved reuseability by using generics
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
USE IEEE.NUMERIC_STD.ALL;
use IEEE.math_real.all;
entity debouncer is
Generic ( DEBNC_CLOCKS : INTEGER range 2 to (INTEGER'high) := 2**16;
PORT_WIDTH : INTEGER range 1 to (INTEGER'high) := 5);
Port ( SIGNAL_I : in STD_LOGIC_VECTOR ((PORT_WIDTH - 1) downto 0);
CLK_I : in STD_LOGIC;
SIGNAL_O : out STD_LOGIC_VECTOR ((PORT_WIDTH - 1) downto 0));
end debouncer;
architecture Behavioral of debouncer is
constant CNTR_WIDTH : integer := natural(ceil(LOG2(real(DEBNC_CLOCKS))));
constant CNTR_MAX : std_logic_vector((CNTR_WIDTH - 1) downto 0) := std_logic_vector(to_unsigned((DEBNC_CLOCKS - 1), CNTR_WIDTH));
type VECTOR_ARRAY_TYPE is array (integer range <>) of std_logic_vector((CNTR_WIDTH - 1) downto 0);
signal sig_cntrs_ary : VECTOR_ARRAY_TYPE (0 to (PORT_WIDTH - 1)) := (others=>(others=>'0'));
signal sig_out_reg : std_logic_vector((PORT_WIDTH - 1) downto 0) := (others => '0');
begin
debounce_process : process (CLK_I)
begin
if (rising_edge(CLK_I)) then
for index in 0 to (PORT_WIDTH - 1) loop
if (sig_cntrs_ary(index) = CNTR_MAX) then
sig_out_reg(index) <= not(sig_out_reg(index));
end if;
end loop;
end if;
end process;
counter_process : process (CLK_I)
begin
if (rising_edge(CLK_I)) then
for index in 0 to (PORT_WIDTH - 1) loop
if ((sig_out_reg(index) = '1') xor (SIGNAL_I(index) = '1')) then
if (sig_cntrs_ary(index) = CNTR_MAX) then
sig_cntrs_ary(index) <= (others => '0');
else
sig_cntrs_ary(index) <= sig_cntrs_ary(index) + 1;
end if;
else
sig_cntrs_ary(index) <= (others => '0');
end if;
end loop;
end if;
end process;
SIGNAL_O <= sig_out_reg;
end Behavioral;
|
gpl-3.0
|
008610defb7125e77e781c3f01138095
| 0.549927 | 3.798665 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/Music_Looper_Demo/src/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig_sim.vhd
| 1 | 76,945 |
--*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 2.3
-- \ \ Application : MIG
-- / / Filename : mig_7series_0_mig.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Top-level module. This module can be instantiated in the
-- system and interconnect as shown in user design wrapper file (user top module).
-- In addition to the memory controller, the module instantiates:
-- 1. Clock generation/distribution, reset logic
-- 2. IDELAY control block
-- 3. Debug logic
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mig_7series_0_mig is
generic (
RST_ACT_LOW : integer := 1;
-- =1 for active low reset,
-- =0 for active high.
--***************************************************************************
-- The following parameters refer to width of various ports
--***************************************************************************
BANK_WIDTH : integer := 3;
-- # of memory Bank Address bits.
CK_WIDTH : integer := 1;
-- # of CK/CK# outputs to memory.
COL_WIDTH : integer := 10;
-- # of memory Column Address bits.
CS_WIDTH : integer := 1;
-- # of unique CS outputs to memory.
nCS_PER_RANK : integer := 1;
-- # of unique CS outputs per rank for phy
CKE_WIDTH : integer := 1;
-- # of CKE outputs to memory.
DATA_BUF_ADDR_WIDTH : integer := 5;
DQ_CNT_WIDTH : integer := 4;
-- = ceil(log2(DQ_WIDTH))
DQ_PER_DM : integer := 8;
DM_WIDTH : integer := 2;
-- # of DM (data mask)
DQ_WIDTH : integer := 16;
-- # of DQ (data)
DQS_WIDTH : integer := 2;
DQS_CNT_WIDTH : integer := 1;
-- = ceil(log2(DQS_WIDTH))
DRAM_WIDTH : integer := 8;
-- # of DQ per DQS
ECC : string := "OFF";
ECC_TEST : string := "OFF";
PAYLOAD_WIDTH : integer := 16;
MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
--Possible Parameters
--1.BANK_ROW_COLUMN : Address mapping is
-- in form of Bank Row Column.
--2.ROW_BANK_COLUMN : Address mapping is
-- in the form of Row Bank Column.
--3.TG_TEST : Scrambles Address bits
-- for distributed Addressing.
nBANK_MACHS : integer := 4;
RANKS : integer := 1;
-- # of Ranks.
ODT_WIDTH : integer := 1;
-- # of ODT outputs to memory.
ROW_WIDTH : integer := 13;
-- # of memory Row Address bits.
ADDR_WIDTH : integer := 27;
-- # = RANK_WIDTH + BANK_WIDTH
-- + ROW_WIDTH + COL_WIDTH;
-- Chip Select is always tied to low for
-- single rank devices
USE_CS_PORT : integer := 1;
-- # = 1, When Chip Select (CS#) output is enabled
-- = 0, When Chip Select (CS#) output is disabled
-- If CS_N disabled, user must connect
-- DRAM CS_N input(s) to ground
USE_DM_PORT : integer := 1;
-- # = 1, When Data Mask option is enabled
-- = 0, When Data Mask option is disbaled
-- When Data Mask option is disabled in
-- MIG Controller Options page, the logic
-- related to Data Mask should not get
-- synthesized
USE_ODT_PORT : integer := 1;
-- # = 1, When ODT output is enabled
-- = 0, When ODT output is disabled
PHY_CONTROL_MASTER_BANK : integer := 0;
-- The bank index where master PHY_CONTROL resides,
-- equal to the PLL residing bank
MEM_DENSITY : string := "1Gb";
-- Indicates the density of the Memory part
-- Added for the sake of Vivado simulations
MEM_SPEEDGRADE : string := "25E";
-- Indicates the Speed grade of Memory Part
-- Added for the sake of Vivado simulations
MEM_DEVICE_WIDTH : integer := 16;
-- Indicates the device width of the Memory Part
-- Added for the sake of Vivado simulations
--***************************************************************************
-- The following parameters are mode register settings
--***************************************************************************
AL : string := "0";
-- DDR3 SDRAM:
-- Additive Latency (Mode Register 1).
-- # = "0", "CL-1", "CL-2".
-- DDR2 SDRAM:
-- Additive Latency (Extended Mode Register).
nAL : integer := 0;
-- # Additive Latency in number of clock
-- cycles.
BURST_MODE : string := "8";
-- DDR3 SDRAM:
-- Burst Length (Mode Register 0).
-- # = "8", "4", "OTF".
-- DDR2 SDRAM:
-- Burst Length (Mode Register).
-- # = "8", "4".
BURST_TYPE : string := "SEQ";
-- DDR3 SDRAM: Burst Type (Mode Register 0).
-- DDR2 SDRAM: Burst Type (Mode Register).
-- # = "SEQ" - (Sequential),
-- = "INT" - (Interleaved).
CL : integer := 5;
-- in number of clock cycles
-- DDR3 SDRAM: CAS Latency (Mode Register 0).
-- DDR2 SDRAM: CAS Latency (Mode Register).
OUTPUT_DRV : string := "HIGH";
-- Output Drive Strength (Extended Mode Register).
-- # = "HIGH" - FULL,
-- = "LOW" - REDUCED.
RTT_NOM : string := "50";
-- RTT (Nominal) (Extended Mode Register).
-- = "150" - 150 Ohms,
-- = "75" - 75 Ohms,
-- = "50" - 50 Ohms.
ADDR_CMD_MODE : string := "1T" ;
-- # = "1T", "2T".
REG_CTRL : string := "OFF";
-- # = "ON" - RDIMMs,
-- = "OFF" - Components, SODIMMs, UDIMMs.
--***************************************************************************
-- The following parameters are multiplier and divisor factors for PLLE2.
-- Based on the selected design frequency these parameters vary.
--***************************************************************************
CLKIN_PERIOD : integer := 4999;
-- Input Clock Period
CLKFBOUT_MULT : integer := 6;
-- write PLL VCO multiplier
DIVCLK_DIVIDE : integer := 1;
-- write PLL VCO divisor
CLKOUT0_PHASE : real := 0.0;
-- Phase for PLL output clock (CLKOUT0)
CLKOUT0_DIVIDE : integer := 2;
-- VCO output divisor for PLL output clock (CLKOUT0)
CLKOUT1_DIVIDE : integer := 4;
-- VCO output divisor for PLL output clock (CLKOUT1)
CLKOUT2_DIVIDE : integer := 64;
-- VCO output divisor for PLL output clock (CLKOUT2)
CLKOUT3_DIVIDE : integer := 16;
-- VCO output divisor for PLL output clock (CLKOUT3)
MMCM_VCO : integer := 1200;
-- Max Freq (MHz) of MMCM VCO
MMCM_MULT_F : integer := 15;
-- write MMCM VCO multiplier
MMCM_DIVCLK_DIVIDE : integer := 1;
-- write MMCM VCO divisor
--***************************************************************************
-- Memory Timing Parameters. These parameters varies based on the selected
-- memory part.
--***************************************************************************
tCKE : integer := 7500;
-- memory tCKE paramter in pS
tFAW : integer := 45000;
-- memory tRAW paramter in pS.
tPRDI : integer := 1000000;
-- memory tPRDI paramter in pS.
tRAS : integer := 40000;
-- memory tRAS paramter in pS.
tRCD : integer := 15000;
-- memory tRCD paramter in pS.
tREFI : integer := 7800000;
-- memory tREFI paramter in pS.
tRFC : integer := 127500;
-- memory tRFC paramter in pS.
tRP : integer := 12500;
-- memory tRP paramter in pS.
tRRD : integer := 10000;
-- memory tRRD paramter in pS.
tRTP : integer := 7500;
-- memory tRTP paramter in pS.
tWTR : integer := 7500;
-- memory tWTR paramter in pS.
tZQI : integer := 128000000;
-- memory tZQI paramter in nS.
tZQCS : integer := 64;
-- memory tZQCS paramter in clock cycles.
--***************************************************************************
-- Simulation parameters
--***************************************************************************
SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
--***************************************************************************
-- The following parameters varies based on the pin out entered in MIG GUI.
-- Do not change any of these parameters directly by editing the RTL.
-- Any changes required should be done through GUI and the design regenerated.
--***************************************************************************
BYTE_LANES_B0 : std_logic_vector(3 downto 0) := "1111";
-- Byte lanes used in an IO column.
BYTE_LANES_B1 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B2 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B3 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B4 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
DATA_CTL_B0 : std_logic_vector(3 downto 0) := "0101";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B1 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B2 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B3 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B4 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
PHY_0_BITLANES : std_logic_vector(47 downto 0) := X"FFC3F7FFF3FE";
PHY_1_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
PHY_2_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
-- control/address/data pin mapping parameters
CK_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000003";
ADDR_MAP
: std_logic_vector(191 downto 0) := X"00000000001003301A01903203A034018036012011017015";
BANK_MAP : std_logic_vector(35 downto 0) := X"01301601B";
CAS_MAP : std_logic_vector(11 downto 0) := X"039";
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0) := X"00";
CKE_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000038";
ODT_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000035";
CS_MAP : std_logic_vector(119 downto 0) := X"000000000000000000000000000037";
PARITY_MAP : std_logic_vector(11 downto 0) := X"000";
RAS_MAP : std_logic_vector(11 downto 0) := X"014";
WE_MAP : std_logic_vector(11 downto 0) := X"03B";
DQS_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000200";
DATA0_MAP : std_logic_vector(95 downto 0) := X"008004009007005001006003";
DATA1_MAP : std_logic_vector(95 downto 0) := X"022028020024027025026021";
DATA2_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA3_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA4_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA5_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA6_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA7_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA8_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA9_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA10_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA11_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA12_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA13_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA14_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA15_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA16_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA17_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
MASK0_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000029002";
MASK1_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
SLOT_0_CONFIG : std_logic_vector(7 downto 0) := "00000001";
-- Mapping of Ranks.
SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00000000";
-- Mapping of Ranks.
--***************************************************************************
-- IODELAY and PHY related parameters
--***************************************************************************
IBUF_LPWR_MODE : string := "OFF";
-- to phy_top
DATA_IO_IDLE_PWRDWN : string := "ON";
-- # = "ON", "OFF"
BANK_TYPE : string := "HR_IO";
-- # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
DATA_IO_PRIM_TYPE : string := "HR_LP";
-- # = "HP_LP", "HR_LP", "DEFAULT"
CKE_ODT_AUX : string := "FALSE";
USER_REFRESH : string := "OFF";
WRLVL : string := "OFF";
-- # = "ON" - DDR3 SDRAM
-- = "OFF" - DDR2 SDRAM.
ORDERING : string := "STRICT";
-- # = "NORM", "STRICT", "RELAXED".
CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000";
-- Calibration row address will be used for
-- calibration read and write operations
CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000";
-- Calibration column address will be used for
-- calibration read and write operations
CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000";
-- Calibration bank address will be used for
-- calibration read and write operations
TCQ : integer := 100;
IODELAY_GRP0 : string := "MIG_7SERIES_0_IODELAY_MIG0";
-- It is associated to a set of IODELAYs with
-- an IDELAYCTRL that have same IODELAY CONTROLLER
-- clock frequency (200MHz).
IODELAY_GRP1 : string := "MIG_7SERIES_0_IODELAY_MIG1";
-- It is associated to a set of IODELAYs with
-- an IDELAYCTRL that have same IODELAY CONTROLLER
-- clock frequency (300MHz/400MHz).
SYSCLK_TYPE : string := "NO_BUFFER";
-- System clock type DIFFERENTIAL, SINGLE_ENDED,
-- NO_BUFFER
REFCLK_TYPE : string := "USE_SYSTEM_CLOCK";
-- Reference clock type DIFFERENTIAL, SINGLE_ENDED
-- NO_BUFFER, USE_SYSTEM_CLOCK
SYS_RST_PORT : string := "FALSE";
-- "TRUE" - if pin is selected for sys_rst
-- and IBUF will be instantiated.
-- "FALSE" - if pin is not selected for sys_rst
FPGA_SPEED_GRADE : integer := 1;
-- FPGA speed grade
REF_CLK_MMCM_IODELAY_CTRL : string := "FALSE";
CMD_PIPE_PLUS1 : string := "ON";
-- add pipeline stage between MC and PHY
DRAM_TYPE : string := "DDR2";
CAL_WIDTH : string := "HALF";
STARVE_LIMIT : integer := 2;
-- # = 2,3,4.
--***************************************************************************
-- Referece clock frequency parameters
--***************************************************************************
REFCLK_FREQ : real := 200.0;
-- IODELAYCTRL reference clock frequency
DIFF_TERM_REFCLK : string := "TRUE";
-- Differential Termination for idelay
-- reference clock input pins
--***************************************************************************
-- System clock frequency parameters
--***************************************************************************
tCK : integer := 3333;
-- memory tCK paramter.
-- # = Clock Period in pS.
nCK_PER_CLK : integer := 4;
-- # of memory CKs per fabric CLK
DIFF_TERM_SYSCLK : string := "TRUE";
-- Differential Termination for System
-- clock input pins
--***************************************************************************
-- Debug parameters
--***************************************************************************
DEBUG_PORT : string := "OFF";
-- # = "ON" Enable debug signals/controls.
-- = "OFF" Disable debug signals/controls.
--***************************************************************************
-- Temparature monitor parameter
--***************************************************************************
TEMP_MON_CONTROL : string := "EXTERNAL"
-- # = "INTERNAL", "EXTERNAL"
-- RST_ACT_LOW : integer := 1
-- =1 for active low reset,
-- =0 for active high.
);
port (
-- Inouts
ddr2_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr2_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr2_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr2_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr2_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr2_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr2_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
-- Inputs
-- Single-ended system clock
sys_clk_i : in std_logic;
-- user interface signals
app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH/8)-1 downto 0) ;
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
-- The 12 MSB bits of the temperature sensor transfer
-- function need to be connected to this port. This port
-- will be synchronized w.r.t. to fabric clock internally.
-- System reset - Default polarity of sys_rst pin is Active Low.
-- System reset polarity will change based on the option
-- selected in GUI.
sys_rst : in std_logic
);
end entity mig_7series_0_mig;
architecture arch_mig_7series_0_mig of mig_7series_0_mig is
-- clogb2 function - ceiling of log base 2
function clogb2 (size : integer) return integer is
variable base : integer := 1;
variable inp : integer := 0;
begin
inp := size - 1;
while (inp > 1) loop
inp := inp/2 ;
base := base + 1;
end loop;
return base;
end function;
constant DATA_WIDTH : integer := 16;
function ECCWIDTH return integer is
begin
if(ECC = "OFF") then
return 0;
else
if(DATA_WIDTH <= 4) then
return 4;
elsif(DATA_WIDTH <= 10) then
return 5;
elsif(DATA_WIDTH <= 26) then
return 6;
elsif(DATA_WIDTH <= 57) then
return 7;
elsif(DATA_WIDTH <= 120) then
return 8;
elsif(DATA_WIDTH <= 247) then
return 9;
else
return 10;
end if;
end if;
end function;
constant RANK_WIDTH : integer := clogb2(RANKS);
function XWIDTH return integer is
begin
if(CS_WIDTH = 1) then
return 0;
else
return RANK_WIDTH;
end if;
end function;
constant TAPSPERKCLK : integer := 56;
function TEMP_MON return string is
begin
if(SIMULATION = "TRUE") then
return "ON";
else
return "OFF";
end if;
end function;
constant BM_CNT_WIDTH : integer := clogb2(nBANK_MACHS);
constant ECC_WIDTH : integer := ECCWIDTH;
constant DATA_BUF_OFFSET_WIDTH : integer := 1;
constant MC_ERR_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH
+ COL_WIDTH + DATA_BUF_OFFSET_WIDTH;
constant APP_DATA_WIDTH : integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
constant APP_MASK_WIDTH : integer := APP_DATA_WIDTH / 8;
constant TEMP_MON_EN : string := TEMP_MON;
-- Enable or disable the temp monitor module
constant tTEMPSAMPLE : integer := 10000000; -- sample every 10 us
constant XADC_CLK_PERIOD : integer := 5000; -- Use 200 MHz IODELAYCTRL clock
component mig_7series_v2_3_iodelay_ctrl is
generic(
TCQ : integer;
IODELAY_GRP0 : string;
IODELAY_GRP1 : string;
REFCLK_TYPE : string;
SYSCLK_TYPE : string;
SYS_RST_PORT : string;
RST_ACT_LOW : integer;
DIFF_TERM_REFCLK : string;
FPGA_SPEED_GRADE : integer;
REF_CLK_MMCM_IODELAY_CTRL : string
);
port (
clk_ref_p : in std_logic;
clk_ref_n : in std_logic;
clk_ref_i : in std_logic;
sys_rst : in std_logic;
clk_ref : out std_logic_vector(1 downto 0);
sys_rst_o : out std_logic;
iodelay_ctrl_rdy : out std_logic_vector(1 downto 0)
);
end component mig_7series_v2_3_iodelay_ctrl;
component mig_7series_v2_3_clk_ibuf is
generic (
SYSCLK_TYPE : string;
DIFF_TERM_SYSCLK : string
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk_i : in std_logic;
mmcm_clk : out std_logic
);
end component mig_7series_v2_3_clk_ibuf;
component mig_7series_v2_3_infrastructure is
generic (
SIMULATION : string := "TRUE";
TCQ : integer;
CLKIN_PERIOD : integer;
nCK_PER_CLK : integer;
SYSCLK_TYPE : string;
UI_EXTRA_CLOCKS : string := "FALSE";
CLKFBOUT_MULT : integer;
DIVCLK_DIVIDE : integer;
CLKOUT0_PHASE : real;
CLKOUT0_DIVIDE : integer;
CLKOUT1_DIVIDE : integer;
CLKOUT2_DIVIDE : integer;
CLKOUT3_DIVIDE : integer;
MMCM_VCO : integer;
MMCM_MULT_F : integer;
MMCM_DIVCLK_DIVIDE : integer;
MMCM_CLKOUT0_EN : string := "FALSE";
MMCM_CLKOUT1_EN : string := "FALSE";
MMCM_CLKOUT2_EN : string := "FALSE";
MMCM_CLKOUT3_EN : string := "FALSE";
MMCM_CLKOUT4_EN : string := "FALSE";
MMCM_CLKOUT0_DIVIDE : integer := 1;
MMCM_CLKOUT1_DIVIDE : integer := 1;
MMCM_CLKOUT2_DIVIDE : integer := 1;
MMCM_CLKOUT3_DIVIDE : integer := 1;
MMCM_CLKOUT4_DIVIDE : integer := 1;
RST_ACT_LOW : integer;
tCK : integer;
MEM_TYPE : string
);
port (
mmcm_clk : in std_logic;
sys_rst : in std_logic;
iodelay_ctrl_rdy : in std_logic_vector(1 downto 0);
psen : in std_logic;
psincdec : in std_logic;
clk : out std_logic;
mem_refclk : out std_logic;
freq_refclk : out std_logic;
sync_pulse : out std_logic;
mmcm_ps_clk : out std_logic;
poc_sample_pd : out std_logic;
iddr_rst : out std_logic;
psdone : out std_logic;
auxout_clk : out std_logic;
ui_addn_clk_0 : out std_logic;
ui_addn_clk_1 : out std_logic;
ui_addn_clk_2 : out std_logic;
ui_addn_clk_3 : out std_logic;
ui_addn_clk_4 : out std_logic;
pll_locked : out std_logic;
mmcm_locked : out std_logic;
rstdiv0 : out std_logic;
rst_phaser_ref : out std_logic;
ref_dll_lock : in std_logic
);
end component mig_7series_v2_3_infrastructure;
component mig_7series_v2_3_tempmon is
generic (
TCQ : integer;
TEMP_MON_CONTROL : string;
XADC_CLK_PERIOD : integer;
tTEMPSAMPLE : integer
);
port (
clk : in std_logic;
xadc_clk : in std_logic;
rst : in std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
device_temp : out std_logic_vector(11 downto 0)
);
end component mig_7series_v2_3_tempmon;
component mig_7series_v2_3_memc_ui_top_std is
generic (
TCQ : integer;
DDR3_VDD_OP_VOLT : string := "135";
PAYLOAD_WIDTH : integer;
ADDR_CMD_MODE : string;
AL : string;
BANK_WIDTH : integer;
BM_CNT_WIDTH : integer;
BURST_MODE : string;
BURST_TYPE : string;
CA_MIRROR : string := "FALSE";
CK_WIDTH : integer;
CL : integer;
COL_WIDTH : integer;
CMD_PIPE_PLUS1 : string;
CS_WIDTH : integer;
CKE_WIDTH : integer;
CWL : integer := 5;
DATA_WIDTH : integer;
DATA_BUF_ADDR_WIDTH : integer;
DATA_BUF_OFFSET_WIDTH : integer := 1;
DDR2_DQSN_ENABLE : string := "YES";
DM_WIDTH : integer;
DQ_CNT_WIDTH : integer;
DQ_WIDTH : integer;
DQS_CNT_WIDTH : integer;
DQS_WIDTH : integer;
DRAM_TYPE : string;
DRAM_WIDTH : integer;
ECC : string;
ECC_WIDTH : integer;
ECC_TEST : string;
MC_ERR_ADDR_WIDTH : integer;
MASTER_PHY_CTL : integer;
nAL : integer;
nBANK_MACHS : integer;
nCK_PER_CLK : integer;
nCS_PER_RANK : integer;
ORDERING : string;
IBUF_LPWR_MODE : string;
BANK_TYPE : string;
DATA_IO_PRIM_TYPE : string;
DATA_IO_IDLE_PWRDWN : string;
IODELAY_GRP0 : string;
IODELAY_GRP1 : string;
FPGA_SPEED_GRADE : integer;
OUTPUT_DRV : string;
REG_CTRL : string;
RTT_NOM : string;
RTT_WR : string := "120";
STARVE_LIMIT : integer;
tCK : integer;
tCKE : integer;
tFAW : integer;
tPRDI : integer;
tRAS : integer;
tRCD : integer;
tREFI : integer;
tRFC : integer;
tRP : integer;
tRRD : integer;
tRTP : integer;
tWTR : integer;
tZQI : integer;
tZQCS : integer;
USER_REFRESH : string;
TEMP_MON_EN : string;
WRLVL : string;
DEBUG_PORT : string;
CAL_WIDTH : string;
RANK_WIDTH : integer;
RANKS : integer;
ODT_WIDTH : integer;
ROW_WIDTH : integer;
ADDR_WIDTH : integer;
APP_MASK_WIDTH : integer;
APP_DATA_WIDTH : integer;
BYTE_LANES_B0 : std_logic_vector(3 downto 0);
BYTE_LANES_B1 : std_logic_vector(3 downto 0);
BYTE_LANES_B2 : std_logic_vector(3 downto 0);
BYTE_LANES_B3 : std_logic_vector(3 downto 0);
BYTE_LANES_B4 : std_logic_vector(3 downto 0);
DATA_CTL_B0 : std_logic_vector(3 downto 0);
DATA_CTL_B1 : std_logic_vector(3 downto 0);
DATA_CTL_B2 : std_logic_vector(3 downto 0);
DATA_CTL_B3 : std_logic_vector(3 downto 0);
DATA_CTL_B4 : std_logic_vector(3 downto 0);
PHY_0_BITLANES : std_logic_vector(47 downto 0);
PHY_1_BITLANES : std_logic_vector(47 downto 0);
PHY_2_BITLANES : std_logic_vector(47 downto 0);
CK_BYTE_MAP : std_logic_vector(143 downto 0);
ADDR_MAP : std_logic_vector(191 downto 0);
BANK_MAP : std_logic_vector(35 downto 0);
CAS_MAP : std_logic_vector(11 downto 0);
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0);
CKE_MAP : std_logic_vector(95 downto 0);
ODT_MAP : std_logic_vector(95 downto 0);
CKE_ODT_AUX : string;
CS_MAP : std_logic_vector(119 downto 0);
PARITY_MAP : std_logic_vector(11 downto 0);
RAS_MAP : std_logic_vector(11 downto 0);
WE_MAP : std_logic_vector(11 downto 0);
DQS_BYTE_MAP : std_logic_vector(143 downto 0);
DATA0_MAP : std_logic_vector(95 downto 0);
DATA1_MAP : std_logic_vector(95 downto 0);
DATA2_MAP : std_logic_vector(95 downto 0);
DATA3_MAP : std_logic_vector(95 downto 0);
DATA4_MAP : std_logic_vector(95 downto 0);
DATA5_MAP : std_logic_vector(95 downto 0);
DATA6_MAP : std_logic_vector(95 downto 0);
DATA7_MAP : std_logic_vector(95 downto 0);
DATA8_MAP : std_logic_vector(95 downto 0);
DATA9_MAP : std_logic_vector(95 downto 0);
DATA10_MAP : std_logic_vector(95 downto 0);
DATA11_MAP : std_logic_vector(95 downto 0);
DATA12_MAP : std_logic_vector(95 downto 0);
DATA13_MAP : std_logic_vector(95 downto 0);
DATA14_MAP : std_logic_vector(95 downto 0);
DATA15_MAP : std_logic_vector(95 downto 0);
DATA16_MAP : std_logic_vector(95 downto 0);
DATA17_MAP : std_logic_vector(95 downto 0);
MASK0_MAP : std_logic_vector(107 downto 0);
MASK1_MAP : std_logic_vector(107 downto 0);
SLOT_0_CONFIG : std_logic_vector(7 downto 0);
SLOT_1_CONFIG : std_logic_vector(7 downto 0);
MEM_ADDR_ORDER : string;
CALIB_ROW_ADD : std_logic_vector(15 downto 0);
CALIB_COL_ADD : std_logic_vector(11 downto 0);
CALIB_BA_ADD : std_logic_vector(2 downto 0);
SIM_BYPASS_INIT_CAL : string;
REFCLK_FREQ : real;
USE_CS_PORT : integer;
USE_DM_PORT : integer;
USE_ODT_PORT : integer;
IDELAY_ADJ : string;
FINE_PER_BIT : string;
CENTER_COMP_MODE : string;
PI_VAL_ADJ : string;
TAPSPERKCLK : integer := 56
);
port (
clk : in std_logic;
clk_ref : in std_logic_vector(1 downto 0);
mem_refclk : in std_logic;
freq_refclk : in std_logic;
pll_lock : in std_logic;
sync_pulse : in std_logic;
rst : in std_logic;
rst_phaser_ref : in std_logic;
ref_dll_lock : out std_logic;
iddr_rst : in std_logic;
mmcm_ps_clk : in std_logic;
poc_sample_pd : in std_logic;
ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr_cas_n : out std_logic;
ddr_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_ck : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
ddr_ras_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_parity : out std_logic;
ddr_we_n : out std_logic;
bank_mach_next : out std_logic_vector(BM_CNT_WIDTH-1 downto 0);
app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_hi_pri : in std_logic;
app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8)-1 downto 0);
app_wdf_wren : in std_logic;
app_correct_en_i : in std_logic;
app_raw_not_ecc : in std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
app_ecc_multiple_err : out std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
psen : out std_logic;
psincdec : out std_logic;
psdone : in std_logic;
device_temp : in std_logic_vector(11 downto 0);
dbg_idel_down_all : in std_logic;
dbg_idel_down_cpt : in std_logic;
dbg_idel_up_all : in std_logic;
dbg_idel_up_cpt : in std_logic;
dbg_sel_all_idel_cpt : in std_logic;
dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
dbg_cpt_first_edge_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_cpt_second_edge_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0);
dbg_rddata : out std_logic_vector((2*nCK_PER_CLK*DQ_WIDTH)-1 downto 0);
dbg_rdlvl_done : out std_logic_vector(1 downto 0);
dbg_rdlvl_err : out std_logic_vector(1 downto 0);
dbg_rdlvl_start : out std_logic_vector(1 downto 0);
dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0);
dbg_wl_edge_detect_valid : out std_logic;
dbg_wrlvl_done : out std_logic;
dbg_wrlvl_err : out std_logic;
dbg_wrlvl_start : out std_logic;
dbg_final_po_fine_tap_cnt : out std_logic_vector((6*DQS_WIDTH)-1 downto 0);
dbg_final_po_coarse_tap_cnt : out std_logic_vector((3*DQS_WIDTH)-1 downto 0);
dbg_prbs_final_dqs_tap_cnt_r : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_prbs_first_edge_taps : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_prbs_second_edge_taps : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
init_calib_complete : out std_logic;
dbg_sel_pi_incdec : in std_logic;
dbg_sel_po_incdec : in std_logic;
dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0);
dbg_pi_f_inc : in std_logic;
dbg_pi_f_dec : in std_logic;
dbg_po_f_inc : in std_logic;
dbg_po_f_stg23_sel : in std_logic;
dbg_po_f_dec : in std_logic;
dbg_cpt_tap_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_dq_idelay_tap_cnt : out std_logic_vector((5*DQS_WIDTH*RANKS)-1 downto 0);
dbg_rddata_valid : out std_logic;
dbg_wrlvl_fine_tap_cnt : out std_logic_vector((6*DQS_WIDTH)-1 downto 0);
dbg_wrlvl_coarse_tap_cnt : out std_logic_vector((3*DQS_WIDTH)-1 downto 0);
dbg_rd_data_offset : out std_logic_vector((6*RANKS)-1 downto 0);
dbg_calib_top : out std_logic_vector(255 downto 0);
dbg_phy_wrlvl : out std_logic_vector(255 downto 0);
dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
dbg_phy_wrcal : out std_logic_vector(99 downto 0);
dbg_phy_init : out std_logic_vector(255 downto 0);
dbg_prbs_rdlvl : out std_logic_vector(255 downto 0);
dbg_dqs_found_cal : out std_logic_vector(255 downto 0);
dbg_pi_counter_read_val : out std_logic_vector(5 downto 0);
dbg_po_counter_read_val : out std_logic_vector(8 downto 0);
dbg_pi_phaselock_start : out std_logic;
dbg_pi_phaselocked_done : out std_logic;
dbg_pi_phaselock_err : out std_logic;
dbg_pi_dqsfound_start : out std_logic;
dbg_pi_dqsfound_done : out std_logic;
dbg_pi_dqsfound_err : out std_logic;
dbg_wrcal_start : out std_logic;
dbg_wrcal_done : out std_logic;
dbg_wrcal_err : out std_logic;
dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0);
dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0);
dbg_calib_rd_data_offset_1 : out std_logic_vector((6*RANKS)-1 downto 0);
dbg_calib_rd_data_offset_2 : out std_logic_vector((6*RANKS)-1 downto 0);
dbg_data_offset : out std_logic_vector(5 downto 0);
dbg_data_offset_1 : out std_logic_vector(5 downto 0);
dbg_data_offset_2 : out std_logic_vector(5 downto 0);
dbg_oclkdelay_calib_start : out std_logic;
dbg_oclkdelay_calib_done : out std_logic;
dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0);
dbg_oclkdelay_rd_data : out std_logic_vector((DRAM_WIDTH*16)-1 downto 0)
);
end component mig_7series_v2_3_memc_ui_top_std;
-- Signal declarations
signal bank_mach_next : std_logic_vector(BM_CNT_WIDTH-1 downto 0);
signal clk : std_logic;
signal clk_ref : std_logic_vector(1 downto 0);
signal iodelay_ctrl_rdy : std_logic_vector(1 downto 0);
signal clk_ref_in : std_logic;
signal sys_rst_o : std_logic;
signal freq_refclk : std_logic;
signal mem_refclk : std_logic;
signal pll_locked : std_logic;
signal sync_pulse : std_logic;
signal mmcm_ps_clk : std_logic;
signal poc_sample_pd : std_logic;
signal psen : std_logic;
signal psincdec : std_logic;
signal psdone : std_logic;
signal iddr_rst : std_logic;
signal ref_dll_lock : std_logic;
signal rst_phaser_ref : std_logic;
signal rst : std_logic;
signal app_ecc_multiple_err : std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
signal ddr2_reset_n : std_logic;
signal ddr2_parity : std_logic;
signal init_calib_complete_i : std_logic;
signal sys_clk_p : std_logic;
signal sys_clk_n : std_logic;
signal mmcm_clk : std_logic;
signal clk_ref_p : std_logic;
signal clk_ref_n : std_logic;
signal clk_ref_i : std_logic;
signal device_temp : std_logic_vector(11 downto 0);
-- Debug port signals
signal dbg_idel_down_all : std_logic;
signal dbg_idel_down_cpt : std_logic;
signal dbg_idel_up_all : std_logic;
signal dbg_idel_up_cpt : std_logic;
signal dbg_sel_all_idel_cpt : std_logic;
signal dbg_sel_idel_cpt : std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
signal dbg_po_f_stg23_sel : std_logic;
signal dbg_sel_pi_incdec : std_logic;
signal dbg_sel_po_incdec : std_logic;
signal dbg_byte_sel : std_logic_vector(DQS_CNT_WIDTH downto 0);
signal dbg_pi_f_inc : std_logic;
signal dbg_po_f_inc : std_logic;
signal dbg_pi_f_dec : std_logic;
signal dbg_po_f_dec : std_logic;
signal dbg_pi_counter_read_val : std_logic_vector(5 downto 0);
signal dbg_po_counter_read_val : std_logic_vector(8 downto 0);
signal dbg_prbs_final_dqs_tap_cnt_r : std_logic_vector(11 downto 0);
signal dbg_prbs_first_edge_taps : std_logic_vector(11 downto 0);
signal dbg_prbs_second_edge_taps : std_logic_vector(11 downto 0);
signal dbg_cpt_tap_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_dq_idelay_tap_cnt : std_logic_vector((5*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_calib_top : std_logic_vector(255 downto 0);
signal dbg_cpt_first_edge_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_cpt_second_edge_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_rd_data_offset : std_logic_vector((6*RANKS)-1 downto 0);
signal dbg_phy_rdlvl : std_logic_vector(255 downto 0);
signal dbg_phy_wrcal : std_logic_vector(99 downto 0);
signal dbg_final_po_fine_tap_cnt : std_logic_vector((6*DQS_WIDTH)-1 downto 0);
signal dbg_final_po_coarse_tap_cnt : std_logic_vector((3*DQS_WIDTH)-1 downto 0);
signal dbg_phy_wrlvl : std_logic_vector(255 downto 0);
signal dbg_phy_init : std_logic_vector(255 downto 0);
signal dbg_prbs_rdlvl : std_logic_vector(255 downto 0);
signal dbg_dqs_found_cal : std_logic_vector(255 downto 0);
signal dbg_pi_phaselock_start : std_logic;
signal dbg_pi_phaselocked_done : std_logic;
signal dbg_pi_phaselock_err : std_logic;
signal dbg_pi_dqsfound_start : std_logic;
signal dbg_pi_dqsfound_done : std_logic;
signal dbg_pi_dqsfound_err : std_logic;
signal dbg_wrcal_start : std_logic;
signal dbg_wrcal_done : std_logic;
signal dbg_wrcal_err : std_logic;
signal dbg_pi_dqs_found_lanes_phy4lanes : std_logic_vector(11 downto 0);
signal dbg_pi_phase_locked_phy4lanes : std_logic_vector(11 downto 0);
signal dbg_oclkdelay_calib_start : std_logic;
signal dbg_oclkdelay_calib_done : std_logic;
signal dbg_phy_oclkdelay_cal : std_logic_vector(255 downto 0);
signal dbg_oclkdelay_rd_data : std_logic_vector((DRAM_WIDTH*16)-1 downto 0);
signal dbg_rd_data_edge_detect : std_logic_vector(DQS_WIDTH-1 downto 0);
signal dbg_rddata : std_logic_vector((2*nCK_PER_CLK*DQ_WIDTH)-1 downto 0);
signal dbg_rddata_valid : std_logic;
signal dbg_rdlvl_done : std_logic_vector(1 downto 0);
signal dbg_rdlvl_err : std_logic_vector(1 downto 0);
signal dbg_rdlvl_start : std_logic_vector(1 downto 0);
signal dbg_wrlvl_fine_tap_cnt : std_logic_vector((6*DQS_WIDTH)-1 downto 0);
signal dbg_wrlvl_coarse_tap_cnt : std_logic_vector((3*DQS_WIDTH)-1 downto 0);
signal dbg_tap_cnt_during_wrlvl : std_logic_vector(5 downto 0);
signal dbg_wl_edge_detect_valid : std_logic;
signal dbg_wrlvl_done : std_logic;
signal dbg_wrlvl_err : std_logic;
signal dbg_wrlvl_start : std_logic;
signal dbg_rddata_r : std_logic_vector(63 downto 0);
signal dbg_rddata_valid_r : std_logic;
signal ocal_tap_cnt : std_logic_vector(53 downto 0);
signal dbg_dqs : std_logic_vector(4 downto 0);
signal dbg_bit : std_logic_vector(8 downto 0);
signal rd_data_edge_detect_r : std_logic_vector(8 downto 0);
signal wl_po_fine_cnt : std_logic_vector(53 downto 0);
signal wl_po_coarse_cnt : std_logic_vector(26 downto 0);
signal dbg_calib_rd_data_offset_1 : std_logic_vector((6*RANKS)-1 downto 0);
signal dbg_calib_rd_data_offset_2 : std_logic_vector((6*RANKS)-1 downto 0);
signal dbg_data_offset : std_logic_vector(5 downto 0);
signal dbg_data_offset_1 : std_logic_vector(5 downto 0);
signal dbg_data_offset_2 : std_logic_vector(5 downto 0);
signal all_zeros : std_logic_vector((2*nCK_PER_CLK)-1 downto 0) := (others => '0');
signal ddr2_ila_basic_int : std_logic_vector(119 downto 0);
signal ddr2_ila_wrpath_int : std_logic_vector(390 downto 0);
signal ddr2_ila_rdpath_int : std_logic_vector(1023 downto 0);
signal dbg_prbs_final_dqs_tap_cnt_r_int : std_logic_vector(11 downto 0);
signal dbg_prbs_first_edge_taps_int : std_logic_vector(11 downto 0);
signal dbg_prbs_second_edge_taps_int : std_logic_vector(11 downto 0);
begin
--***************************************************************************
ui_clk <= clk;
ui_clk_sync_rst <= rst;
sys_clk_p <= '0';
sys_clk_n <= '0';
clk_ref_i <= '0';
init_calib_complete <= init_calib_complete_i;
clk_ref_in_use_sys_clk : if (REFCLK_TYPE = "USE_SYSTEM_CLOCK") generate
clk_ref_in <= mmcm_clk;
end generate;
clk_ref_in_others : if (REFCLK_TYPE /= "USE_SYSTEM_CLOCK") generate
clk_ref_in <= clk_ref_i;
end generate;
u_iodelay_ctrl : mig_7series_v2_3_iodelay_ctrl
generic map
(
TCQ => TCQ,
IODELAY_GRP0 => IODELAY_GRP0,
IODELAY_GRP1 => IODELAY_GRP1,
REFCLK_TYPE => REFCLK_TYPE,
SYSCLK_TYPE => SYSCLK_TYPE,
SYS_RST_PORT => SYS_RST_PORT,
RST_ACT_LOW => RST_ACT_LOW,
DIFF_TERM_REFCLK => DIFF_TERM_REFCLK,
FPGA_SPEED_GRADE => FPGA_SPEED_GRADE,
REF_CLK_MMCM_IODELAY_CTRL => REF_CLK_MMCM_IODELAY_CTRL
)
port map
(
-- Outputs
iodelay_ctrl_rdy => iodelay_ctrl_rdy,
sys_rst_o => sys_rst_o,
clk_ref => clk_ref,
-- Inputs
clk_ref_p => clk_ref_p,
clk_ref_n => clk_ref_n,
clk_ref_i => clk_ref_in,
sys_rst => sys_rst
);
u_ddr2_clk_ibuf : mig_7series_v2_3_clk_ibuf
generic map
(
SYSCLK_TYPE => SYSCLK_TYPE,
DIFF_TERM_SYSCLK => DIFF_TERM_SYSCLK
)
port map
(
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_clk_i => sys_clk_i,
mmcm_clk => mmcm_clk
);
-- Temperature monitoring logic
temp_mon_enabled : if (TEMP_MON_EN = "ON") generate
u_tempmon : mig_7series_v2_3_tempmon
generic map
(
TCQ => TCQ,
TEMP_MON_CONTROL => TEMP_MON_CONTROL,
XADC_CLK_PERIOD => XADC_CLK_PERIOD,
tTEMPSAMPLE => tTEMPSAMPLE
)
port map
(
clk => clk,
xadc_clk => clk_ref(0),
rst => rst,
device_temp_i => device_temp_i,
device_temp => device_temp
);
end generate;
temp_mon_disabled : if (TEMP_MON_EN /= "ON") generate
device_temp <= (others => '0');
end generate;
u_ddr2_infrastructure : mig_7series_v2_3_infrastructure
generic map
(
TCQ => TCQ,
nCK_PER_CLK => nCK_PER_CLK,
CLKIN_PERIOD => CLKIN_PERIOD,
SYSCLK_TYPE => SYSCLK_TYPE,
CLKFBOUT_MULT => CLKFBOUT_MULT,
DIVCLK_DIVIDE => DIVCLK_DIVIDE,
CLKOUT0_PHASE => CLKOUT0_PHASE,
CLKOUT0_DIVIDE => CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => CLKOUT3_DIVIDE,
MMCM_VCO => MMCM_VCO,
MMCM_MULT_F => MMCM_MULT_F,
MMCM_DIVCLK_DIVIDE => MMCM_DIVCLK_DIVIDE,
RST_ACT_LOW => RST_ACT_LOW,
tCK => tCK,
MEM_TYPE => DRAM_TYPE
)
port map
(
-- Outputs
rstdiv0 => rst,
clk => clk,
mem_refclk => mem_refclk,
freq_refclk => freq_refclk,
sync_pulse => sync_pulse,
psen => psen,
psincdec => psincdec,
mmcm_ps_clk => mmcm_ps_clk,
poc_sample_pd => poc_sample_pd,
iddr_rst => iddr_rst,
psdone => psdone,
auxout_clk => open,
ui_addn_clk_0 => open,
ui_addn_clk_1 => open,
ui_addn_clk_2 => open,
ui_addn_clk_3 => open,
ui_addn_clk_4 => open,
pll_locked => pll_locked,
mmcm_locked => open,
rst_phaser_ref => rst_phaser_ref,
-- Inputs
mmcm_clk => mmcm_clk,
sys_rst => sys_rst_o,
iodelay_ctrl_rdy => iodelay_ctrl_rdy,
ref_dll_lock => ref_dll_lock
);
u_memc_ui_top_std : mig_7series_v2_3_memc_ui_top_std
generic map (
TCQ => TCQ,
ADDR_CMD_MODE => ADDR_CMD_MODE,
AL => AL,
PAYLOAD_WIDTH => PAYLOAD_WIDTH,
BANK_WIDTH => BANK_WIDTH,
BM_CNT_WIDTH => BM_CNT_WIDTH,
BURST_MODE => BURST_MODE,
BURST_TYPE => BURST_TYPE,
CK_WIDTH => CK_WIDTH,
COL_WIDTH => COL_WIDTH,
CMD_PIPE_PLUS1 => CMD_PIPE_PLUS1,
CS_WIDTH => CS_WIDTH,
nCS_PER_RANK => nCS_PER_RANK,
CKE_WIDTH => CKE_WIDTH,
DATA_WIDTH => DATA_WIDTH,
DATA_BUF_ADDR_WIDTH => DATA_BUF_ADDR_WIDTH,
DM_WIDTH => DM_WIDTH,
DQ_CNT_WIDTH => DQ_CNT_WIDTH,
DQ_WIDTH => DQ_WIDTH,
DQS_CNT_WIDTH => DQS_CNT_WIDTH,
DQS_WIDTH => DQS_WIDTH,
DRAM_TYPE => DRAM_TYPE,
DRAM_WIDTH => DRAM_WIDTH,
ECC => ECC,
ECC_WIDTH => ECC_WIDTH,
ECC_TEST => ECC_TEST,
MC_ERR_ADDR_WIDTH => MC_ERR_ADDR_WIDTH,
REFCLK_FREQ => REFCLK_FREQ,
nAL => nAL,
nBANK_MACHS => nBANK_MACHS,
CKE_ODT_AUX => CKE_ODT_AUX,
nCK_PER_CLK => nCK_PER_CLK,
ORDERING => ORDERING,
OUTPUT_DRV => OUTPUT_DRV,
IBUF_LPWR_MODE => IBUF_LPWR_MODE,
DATA_IO_IDLE_PWRDWN => DATA_IO_IDLE_PWRDWN,
BANK_TYPE => BANK_TYPE,
DATA_IO_PRIM_TYPE => DATA_IO_PRIM_TYPE,
IODELAY_GRP0 => IODELAY_GRP0,
IODELAY_GRP1 => IODELAY_GRP1,
FPGA_SPEED_GRADE => FPGA_SPEED_GRADE,
REG_CTRL => REG_CTRL,
RTT_NOM => RTT_NOM,
CL => CL,
tCK => tCK,
tCKE => tCKE,
tFAW => tFAW,
tPRDI => tPRDI,
tRAS => tRAS,
tRCD => tRCD,
tREFI => tREFI,
tRFC => tRFC,
tRP => tRP,
tRRD => tRRD,
tRTP => tRTP,
tWTR => tWTR,
tZQI => tZQI,
tZQCS => tZQCS,
USER_REFRESH => USER_REFRESH,
TEMP_MON_EN => TEMP_MON_EN,
WRLVL => WRLVL,
DEBUG_PORT => DEBUG_PORT,
CAL_WIDTH => CAL_WIDTH,
RANK_WIDTH => RANK_WIDTH,
RANKS => RANKS,
ODT_WIDTH => ODT_WIDTH,
ROW_WIDTH => ROW_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
APP_DATA_WIDTH => APP_DATA_WIDTH,
APP_MASK_WIDTH => APP_MASK_WIDTH,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
BYTE_LANES_B0 => BYTE_LANES_B0,
BYTE_LANES_B1 => BYTE_LANES_B1,
BYTE_LANES_B2 => BYTE_LANES_B2,
BYTE_LANES_B3 => BYTE_LANES_B3,
BYTE_LANES_B4 => BYTE_LANES_B4,
DATA_CTL_B0 => DATA_CTL_B0,
DATA_CTL_B1 => DATA_CTL_B1,
DATA_CTL_B2 => DATA_CTL_B2,
DATA_CTL_B3 => DATA_CTL_B3,
DATA_CTL_B4 => DATA_CTL_B4,
PHY_0_BITLANES => PHY_0_BITLANES,
PHY_1_BITLANES => PHY_1_BITLANES,
PHY_2_BITLANES => PHY_2_BITLANES,
CK_BYTE_MAP => CK_BYTE_MAP,
ADDR_MAP => ADDR_MAP,
BANK_MAP => BANK_MAP,
CAS_MAP => CAS_MAP,
CKE_ODT_BYTE_MAP => CKE_ODT_BYTE_MAP,
CKE_MAP => CKE_MAP,
ODT_MAP => ODT_MAP,
CS_MAP => CS_MAP,
PARITY_MAP => PARITY_MAP,
RAS_MAP => RAS_MAP,
WE_MAP => WE_MAP,
DQS_BYTE_MAP => DQS_BYTE_MAP,
DATA0_MAP => DATA0_MAP,
DATA1_MAP => DATA1_MAP,
DATA2_MAP => DATA2_MAP,
DATA3_MAP => DATA3_MAP,
DATA4_MAP => DATA4_MAP,
DATA5_MAP => DATA5_MAP,
DATA6_MAP => DATA6_MAP,
DATA7_MAP => DATA7_MAP,
DATA8_MAP => DATA8_MAP,
DATA9_MAP => DATA9_MAP,
DATA10_MAP => DATA10_MAP,
DATA11_MAP => DATA11_MAP,
DATA12_MAP => DATA12_MAP,
DATA13_MAP => DATA13_MAP,
DATA14_MAP => DATA14_MAP,
DATA15_MAP => DATA15_MAP,
DATA16_MAP => DATA16_MAP,
DATA17_MAP => DATA17_MAP,
MASK0_MAP => MASK0_MAP,
MASK1_MAP => MASK1_MAP,
CALIB_ROW_ADD => CALIB_ROW_ADD,
CALIB_COL_ADD => CALIB_COL_ADD,
CALIB_BA_ADD => CALIB_BA_ADD,
SLOT_0_CONFIG => SLOT_0_CONFIG,
SLOT_1_CONFIG => SLOT_1_CONFIG,
MEM_ADDR_ORDER => MEM_ADDR_ORDER,
STARVE_LIMIT => STARVE_LIMIT,
USE_CS_PORT => USE_CS_PORT,
USE_DM_PORT => USE_DM_PORT,
USE_ODT_PORT => USE_ODT_PORT,
IDELAY_ADJ => "OFF",
FINE_PER_BIT => "OFF",
CENTER_COMP_MODE => "OFF",
PI_VAL_ADJ => "OFF",
MASTER_PHY_CTL => PHY_CONTROL_MASTER_BANK,
TAPSPERKCLK => TAPSPERKCLK
)
port map (
clk => clk,
clk_ref => clk_ref,
mem_refclk => mem_refclk, --memory clock
freq_refclk => freq_refclk,
pll_lock => pll_locked,
sync_pulse => sync_pulse,
rst => rst,
rst_phaser_ref => rst_phaser_ref,
ref_dll_lock => ref_dll_lock,
iddr_rst => iddr_rst,
mmcm_ps_clk => mmcm_ps_clk,
poc_sample_pd => poc_sample_pd,
-- Memory interface ports
ddr_dq => ddr2_dq,
ddr_dqs_n => ddr2_dqs_n,
ddr_dqs => ddr2_dqs_p,
ddr_addr => ddr2_addr,
ddr_ba => ddr2_ba,
ddr_cas_n => ddr2_cas_n,
ddr_ck_n => ddr2_ck_n,
ddr_ck => ddr2_ck_p,
ddr_cke => ddr2_cke,
ddr_cs_n => ddr2_cs_n,
ddr_dm => ddr2_dm,
ddr_odt => ddr2_odt,
ddr_ras_n => ddr2_ras_n,
ddr_reset_n => ddr2_reset_n,
ddr_parity => ddr2_parity,
ddr_we_n => ddr2_we_n,
bank_mach_next => bank_mach_next,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_hi_pri => '0',
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_mask => app_wdf_mask,
app_wdf_wren => app_wdf_wren,
app_ecc_multiple_err => app_ecc_multiple_err,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => app_sr_req,
app_sr_active => app_sr_active,
app_ref_req => app_ref_req,
app_ref_ack => app_ref_ack,
app_zq_req => app_zq_req,
app_zq_ack => app_zq_ack,
app_raw_not_ecc => all_zeros,
app_correct_en_i => '1',
psen => psen,
psincdec => psincdec,
psdone => psdone,
device_temp => device_temp,
-- Debug logic ports
dbg_idel_up_all => dbg_idel_up_all,
dbg_idel_down_all => dbg_idel_down_all,
dbg_idel_up_cpt => dbg_idel_up_cpt,
dbg_idel_down_cpt => dbg_idel_down_cpt,
dbg_sel_idel_cpt => dbg_sel_idel_cpt,
dbg_sel_all_idel_cpt => dbg_sel_all_idel_cpt,
dbg_sel_pi_incdec => dbg_sel_pi_incdec,
dbg_sel_po_incdec => dbg_sel_po_incdec,
dbg_byte_sel => dbg_byte_sel,
dbg_pi_f_inc => dbg_pi_f_inc,
dbg_pi_f_dec => dbg_pi_f_dec,
dbg_po_f_inc => dbg_po_f_inc,
dbg_po_f_stg23_sel => dbg_po_f_stg23_sel,
dbg_po_f_dec => dbg_po_f_dec,
dbg_cpt_tap_cnt => dbg_cpt_tap_cnt,
dbg_dq_idelay_tap_cnt => dbg_dq_idelay_tap_cnt,
dbg_calib_top => dbg_calib_top,
dbg_cpt_first_edge_cnt => dbg_cpt_first_edge_cnt,
dbg_cpt_second_edge_cnt => dbg_cpt_second_edge_cnt,
dbg_rd_data_offset => dbg_rd_data_offset,
dbg_phy_rdlvl => dbg_phy_rdlvl,
dbg_phy_wrcal => dbg_phy_wrcal,
dbg_final_po_fine_tap_cnt => dbg_final_po_fine_tap_cnt,
dbg_final_po_coarse_tap_cnt => dbg_final_po_coarse_tap_cnt,
dbg_rd_data_edge_detect => dbg_rd_data_edge_detect,
dbg_rddata => dbg_rddata,
dbg_rddata_valid => dbg_rddata_valid,
dbg_rdlvl_done => dbg_rdlvl_done,
dbg_rdlvl_err => dbg_rdlvl_err,
dbg_rdlvl_start => dbg_rdlvl_start,
dbg_wrlvl_fine_tap_cnt => dbg_wrlvl_fine_tap_cnt,
dbg_wrlvl_coarse_tap_cnt => dbg_wrlvl_coarse_tap_cnt,
dbg_tap_cnt_during_wrlvl => dbg_tap_cnt_during_wrlvl,
dbg_wl_edge_detect_valid => dbg_wl_edge_detect_valid,
dbg_wrlvl_done => dbg_wrlvl_done,
dbg_wrlvl_err => dbg_wrlvl_err,
dbg_wrlvl_start => dbg_wrlvl_start,
dbg_phy_wrlvl => dbg_phy_wrlvl,
dbg_phy_init => dbg_phy_init,
dbg_prbs_rdlvl => dbg_prbs_rdlvl,
dbg_dqs_found_cal => dbg_dqs_found_cal,
dbg_pi_counter_read_val => dbg_pi_counter_read_val,
dbg_po_counter_read_val => dbg_po_counter_read_val,
dbg_pi_phaselock_start => dbg_pi_phaselock_start,
dbg_pi_phaselocked_done => dbg_pi_phaselocked_done,
dbg_pi_phaselock_err => dbg_pi_phaselock_err,
dbg_pi_phase_locked_phy4lanes => dbg_pi_phase_locked_phy4lanes,
dbg_pi_dqsfound_start => dbg_pi_dqsfound_start,
dbg_pi_dqsfound_done => dbg_pi_dqsfound_done,
dbg_pi_dqsfound_err => dbg_pi_dqsfound_err,
dbg_pi_dqs_found_lanes_phy4lanes => dbg_pi_dqs_found_lanes_phy4lanes,
dbg_calib_rd_data_offset_1 => dbg_calib_rd_data_offset_1,
dbg_calib_rd_data_offset_2 => dbg_calib_rd_data_offset_2,
dbg_data_offset => dbg_data_offset,
dbg_data_offset_1 => dbg_data_offset_1,
dbg_data_offset_2 => dbg_data_offset_2,
dbg_wrcal_start => dbg_wrcal_start,
dbg_wrcal_done => dbg_wrcal_done,
dbg_wrcal_err => dbg_wrcal_err,
dbg_phy_oclkdelay_cal => dbg_phy_oclkdelay_cal,
dbg_oclkdelay_rd_data => dbg_oclkdelay_rd_data,
dbg_oclkdelay_calib_start => dbg_oclkdelay_calib_start,
dbg_oclkdelay_calib_done => dbg_oclkdelay_calib_done,
dbg_prbs_final_dqs_tap_cnt_r => dbg_prbs_final_dqs_tap_cnt_r_int,
dbg_prbs_first_edge_taps => dbg_prbs_first_edge_taps_int,
dbg_prbs_second_edge_taps => dbg_prbs_second_edge_taps_int,
init_calib_complete => init_calib_complete_i
);
--*********************************************************************
-- Resetting all RTL debug inputs as the debug ports are not enabled
--*********************************************************************
dbg_idel_down_all <= '0';
dbg_idel_down_cpt <= '0';
dbg_idel_up_all <= '0';
dbg_idel_up_cpt <= '0';
dbg_sel_all_idel_cpt <= '0';
dbg_sel_idel_cpt <= (others => '0');
dbg_byte_sel <= (others => '0');
dbg_sel_pi_incdec <= '0';
dbg_pi_f_inc <= '0';
dbg_pi_f_dec <= '0';
dbg_po_f_inc <= '0';
dbg_po_f_dec <= '0';
dbg_po_f_stg23_sel <= '0';
dbg_sel_po_incdec <= '0';
end architecture arch_mig_7series_0_mig;
|
gpl-3.0
|
474ec756ed483f43bf298c6ad89b80fe
| 0.450023 | 4.200284 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/DRAM/RAM_64nX1.vhd
| 1 | 6,800 |
-------------------------------------------------------------------------------
-- --
-- Module : RAM_64nX1.vhd Last Update: --
-- --
-- Description : This parameterizable module cascade Distributed --
-- RAM primitive to build a larger macro with different data --
-- widths and depths for the LocalLink FIFO. --
-- -- --
-- Designer : Wen Ying Wei --
-- --
-- Company : Xilinx, Inc. --
-- --
-- Disclaimer : THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --
-- WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY --
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR --
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. --
-- THEY ARE ONLY INTENDED TO BE USED BY XILINX --
-- CUSTOMERS, AND WITHIN XILINX DEVICES. --
-- --
-- Copyright (c) 2003 Xilinx, Inc. --
-- All rights reserved --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.fifo_u.all;
entity RAM_64nX1 is
generic (
RAM_NUM : integer; -- 4, 8
ADDR_WIDTH : integer -- equal to ceiling[log2(RAM_NUM * 64)]
);
port (
DI : in std_logic;
WEn : in std_logic;
WCLK : in std_logic;
Ad : in std_logic_vector(ADDR_WIDTH-1 downto 0);
DRA : in std_logic_vector(ADDR_WIDTH-1 downto 0);
DO : out std_logic;
SO : out std_logic);
end RAM_64nX1;
architecture RAM_64nX1_hdl of RAM_64nX1 is
signal wr_en : std_logic_vector(RAM_NUM-1 downto 0);
signal dp : std_logic_vector(RAM_NUM-1 downto 0);
signal sp : std_logic_vector(RAM_NUM-1 downto 0);
signal wr_ram_sel : std_logic_vector(RAM_NUM-1 downto 0);
signal rd_ram_sel : std_logic_vector(RAM_NUM-1 downto 0);
component RAM64X1D
port (
D : in std_logic;
WE : in std_logic;
WCLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
A5 : in std_logic;
DPRA0 : in std_logic;
DPRA1 : in std_logic;
DPRA2 : in std_logic;
DPRA3 : in std_logic;
DPRA4 : in std_logic;
DPRA5 : in std_logic;
DPO : out std_logic;
SPO : out std_logic);
end component;
begin
-- binary to one-hot
wr_ram_sel_gen1 : if RAM_NUM = 1 generate
wr_ram_sel(0) <= '1';
end generate;
wr_ram_sel_gen2 : if RAM_NUM > 1 generate
wr_ram_sel <= conv_std_logic_vector(POWER2(conv_integer(Ad(ADDR_WIDTH-1 downto 6) )), RAM_NUM);
end generate;
wr_en_gen: for i in 0 to RAM_NUM-1 generate
wr_en(i) <= WEn and wr_ram_sel(i);
end generate;
-- binary to one-hot
rd_ram_sel_gen1 : if RAM_NUM = 1 generate
rd_ram_sel(0) <= '1';
end generate;
rd_ram_sel_gen2 : if RAM_NUM > 1 generate
rd_ram_sel <= conv_std_logic_vector(POWER2(conv_integer(DRA(ADDR_WIDTH-1 downto 6))), RAM_NUM);
end generate;
--data output mux
do_gen1: if RAM_NUM = 1 generate
DO <= dp(0);
end generate;
do_gen2: if RAM_NUM = 2 generate
DO <= dp(0) when rd_ram_sel = "01" else dp(1);
end generate;
do_gen4: if RAM_NUM = 4 generate --depth is 256
DO <= dp(0) when rd_ram_sel = "0001"
else dp(1) when rd_ram_sel = "0010"
else dp(2) when rd_ram_sel = "0100"
else dp(3);
end generate;
do_gen8: if RAM_NUM = 8 generate --depth is 512
DO <= dp(0) when rd_ram_sel = "00000001"
else dp(1) when rd_ram_sel = "00000010"
else dp(2) when rd_ram_sel = "00000100"
else dp(3) when rd_ram_sel = "00001000"
else dp(4) when rd_ram_sel = "00010000"
else dp(5) when rd_ram_sel = "00100000"
else dp(6) when rd_ram_sel = "01000000"
else dp(7);
end generate;
so_gen1: if RAM_NUM = 1 generate
SO <= sp(0);
end generate;
so_gen2: if RAM_NUM = 2 generate
SO <= sp(0) when rd_ram_sel = "01" else sp(1);
end generate;
so_gen4: if RAM_NUM = 4 generate
SO <= sp(0) when rd_ram_sel = "0001"
else sp(1) when rd_ram_sel = "0010"
else sp(2) when rd_ram_sel = "0100"
else sp(3);
end generate;
so_gen8: if RAM_NUM = 8 generate
SO <= sp(0) when rd_ram_sel = "00000001"
else sp(1) when rd_ram_sel = "00000010"
else sp(2) when rd_ram_sel = "00000100"
else sp(3) when rd_ram_sel = "00001000"
else sp(4) when rd_ram_sel = "00010000"
else sp(5) when rd_ram_sel = "00100000"
else sp(6) when rd_ram_sel = "01000000"
else sp(7);
end generate;
dram_gen: for i in 0 to RAM_NUM-1 generate
DRAM64x1: RAM64X1D port map (
D => DI,
WE => wr_en(i),
WCLK => WCLK,
A0 => Ad(0),
A1 => Ad(1),
A2 => Ad(2),
A3 => Ad(3),
A4 => Ad(4),
A5 => Ad(5),
DPRA0 => DRA(0),
DPRA1 => DRA(1),
DPRA2 => DRA(2),
DPRA3 => DRA(3),
DPRA4 => DRA(4),
DPRA5 => DRA(5),
DPO => dp(i),
SPO => sp(i));
end generate;
end RAM_64nX1_hdl;
|
gpl-3.0
|
0083dbe0bbf5a8352174abf7ef302ff1
| 0.419412 | 3.697662 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/v6_emac_v1_4_block.vhd
| 1 | 22,232 |
-------------------------------------------------------------------------------
-- Title : Block-level Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
-- Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
-- File : v6_emac_v1_4_block.vhd
-- Version : 1.4
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Description: This is the block-level wrapper for the Virtex-6 Embedded
-- Tri-Mode Ethernet MAC. It is intended that this example design
-- can be quickly adapted and downloaded onto an FPGA to provide
-- a hardware test environment.
--
-- The block-level wrapper:
--
-- * instantiates appropriate PHY interface modules (GMII, MII,
-- RGMII, SGMII or 1000BASE-X) as required per the user
-- configuration;
--
-- * instantiates some clocking and reset resources to operate
-- the EMAC and its example design.
--
-- Please refer to the Datasheet, Getting Started Guide, and
-- the Virtex-6 Embedded Tri-Mode Ethernet MAC User Gude for
-- further information.
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Entity declaration for the block-level wrapper
-------------------------------------------------------------------------------
entity v6_emac_v1_4_block is
port(
-- 125MHz clock output from transceiver
CLK125_OUT : out std_logic;
-- 125MHz clock input from BUFG
CLK125 : in std_logic;
-- Client receiver interface
EMACCLIENTRXD : out std_logic_vector(7 downto 0);
EMACCLIENTRXDVLD : out std_logic;
EMACCLIENTRXGOODFRAME : out std_logic;
EMACCLIENTRXBADFRAME : out std_logic;
EMACCLIENTRXFRAMEDROP : out std_logic;
EMACCLIENTRXSTATS : out std_logic_vector(6 downto 0);
EMACCLIENTRXSTATSVLD : out std_logic;
EMACCLIENTRXSTATSBYTEVLD : out std_logic;
-- Client transmitter interface
CLIENTEMACTXD : in std_logic_vector(7 downto 0);
CLIENTEMACTXDVLD : in std_logic;
EMACCLIENTTXACK : out std_logic;
CLIENTEMACTXFIRSTBYTE : in std_logic;
CLIENTEMACTXUNDERRUN : in std_logic;
EMACCLIENTTXCOLLISION : out std_logic;
EMACCLIENTTXRETRANSMIT : out std_logic;
CLIENTEMACTXIFGDELAY : in std_logic_vector(7 downto 0);
EMACCLIENTTXSTATS : out std_logic;
EMACCLIENTTXSTATSVLD : out std_logic;
EMACCLIENTTXSTATSBYTEVLD : out std_logic;
-- MAC control interface
CLIENTEMACPAUSEREQ : in std_logic;
CLIENTEMACPAUSEVAL : in std_logic_vector(15 downto 0);
-- EMAC-transceiver link status
EMACCLIENTSYNCACQSTATUS : out std_logic;
-- Auto-Negotiation interrupt
EMACANINTERRUPT : out std_logic;
-- SGMII interface
TXP : out std_logic;
TXN : out std_logic;
RXP : in std_logic;
RXN : in std_logic;
PHYAD : in std_logic_vector(4 downto 0);
RESETDONE : out std_logic;
-- SGMII transceiver clock buffer input
CLK_DS : in std_logic;
-- Asynchronous reset
RESET : in std_logic
);
end v6_emac_v1_4_block;
architecture TOP_LEVEL of v6_emac_v1_4_block is
-------------------------------------------------------------------------------
-- Component declarations for lower hierarchial level entities
-------------------------------------------------------------------------------
-- Component declaration for the primitive-level EMAC wrapper
component v6_emac_v1_4 is
port(
-- Client receiver interface
EMACCLIENTRXCLIENTCLKOUT : out std_logic;
CLIENTEMACRXCLIENTCLKIN : in std_logic;
EMACCLIENTRXD : out std_logic_vector(7 downto 0);
EMACCLIENTRXDVLD : out std_logic;
EMACCLIENTRXDVLDMSW : out std_logic;
EMACCLIENTRXGOODFRAME : out std_logic;
EMACCLIENTRXBADFRAME : out std_logic;
EMACCLIENTRXFRAMEDROP : out std_logic;
EMACCLIENTRXSTATS : out std_logic_vector(6 downto 0);
EMACCLIENTRXSTATSVLD : out std_logic;
EMACCLIENTRXSTATSBYTEVLD : out std_logic;
-- Client transmitter interface
EMACCLIENTTXCLIENTCLKOUT : out std_logic;
CLIENTEMACTXCLIENTCLKIN : in std_logic;
CLIENTEMACTXD : in std_logic_vector(7 downto 0);
CLIENTEMACTXDVLD : in std_logic;
CLIENTEMACTXDVLDMSW : in std_logic;
EMACCLIENTTXACK : out std_logic;
CLIENTEMACTXFIRSTBYTE : in std_logic;
CLIENTEMACTXUNDERRUN : in std_logic;
EMACCLIENTTXCOLLISION : out std_logic;
EMACCLIENTTXRETRANSMIT : out std_logic;
CLIENTEMACTXIFGDELAY : in std_logic_vector(7 downto 0);
EMACCLIENTTXSTATS : out std_logic;
EMACCLIENTTXSTATSVLD : out std_logic;
EMACCLIENTTXSTATSBYTEVLD : out std_logic;
-- MAC control interface
CLIENTEMACPAUSEREQ : in std_logic;
CLIENTEMACPAUSEVAL : in std_logic_vector(15 downto 0);
-- Clock signals
GTX_CLK : in std_logic;
PHYEMACTXGMIIMIICLKIN : in std_logic;
EMACPHYTXGMIIMIICLKOUT : out std_logic;
-- SGMII interface
RXDATA : in std_logic_vector(7 downto 0);
TXDATA : out std_logic_vector(7 downto 0);
MMCM_LOCKED : in std_logic;
AN_INTERRUPT : out std_logic;
SIGNAL_DETECT : in std_logic;
PHYAD : in std_logic_vector(4 downto 0);
ENCOMMAALIGN : out std_logic;
LOOPBACKMSB : out std_logic;
MGTRXRESET : out std_logic;
MGTTXRESET : out std_logic;
POWERDOWN : out std_logic;
SYNCACQSTATUS : out std_logic;
RXCLKCORCNT : in std_logic_vector(2 downto 0);
RXBUFSTATUS : in std_logic;
RXCHARISCOMMA : in std_logic;
RXCHARISK : in std_logic;
RXDISPERR : in std_logic;
RXNOTINTABLE : in std_logic;
RXREALIGN : in std_logic;
RXRUNDISP : in std_logic;
TXBUFERR : in std_logic;
TXCHARDISPMODE : out std_logic;
TXCHARDISPVAL : out std_logic;
TXCHARISK : out std_logic;
-- Asynchronous reset
RESET : in std_logic
);
end component;
-- Component declaration for the GTX wrapper
component v6_gtxwizard_top
port (
RESETDONE : out std_logic;
ENMCOMMAALIGN : in std_logic;
ENPCOMMAALIGN : in std_logic;
LOOPBACK : in std_logic;
POWERDOWN : in std_logic;
RXUSRCLK2 : in std_logic;
RXRESET : in std_logic;
TXCHARDISPMODE : in std_logic;
TXCHARDISPVAL : in std_logic;
TXCHARISK : in std_logic;
TXDATA : in std_logic_vector (7 downto 0);
TXUSRCLK2 : in std_logic;
TXRESET : in std_logic;
RXCHARISCOMMA : out std_logic;
RXCHARISK : out std_logic;
RXCLKCORCNT : out std_logic_vector (2 downto 0);
RXDATA : out std_logic_vector (7 downto 0);
RXDISPERR : out std_logic;
RXNOTINTABLE : out std_logic;
RXRUNDISP : out std_logic;
RXBUFERR : out std_logic;
TXBUFERR : out std_logic;
PLLLKDET : out std_logic;
TXOUTCLK : out std_logic;
RXELECIDLE : out std_logic;
TXN : out std_logic;
TXP : out std_logic;
RXN : in std_logic;
RXP : in std_logic;
CLK_DS : in std_logic;
PMARESET : in std_logic
);
end component;
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
-- Power and ground signals
signal gnd_i : std_logic;
signal vcc_i : std_logic;
-- Asynchronous reset signals
signal reset_ibuf_i : std_logic;
signal reset_i : std_logic;
signal reset_r : std_logic_vector(3 downto 0);
-- Client clocking signals
signal rx_client_clk_out_i : std_logic;
signal rx_client_clk_in_i : std_logic;
signal tx_client_clk_out_i : std_logic;
signal tx_client_clk_in_i : std_logic;
-- Physical interface signals
signal emac_locked_i : std_logic;
signal mgt_rx_data_i : std_logic_vector(7 downto 0);
signal mgt_tx_data_i : std_logic_vector(7 downto 0);
signal signal_detect_i : std_logic;
signal elecidle_i : std_logic;
signal resetdone_i : std_logic;
signal encommaalign_i : std_logic;
signal loopback_i : std_logic;
signal mgt_rx_reset_i : std_logic;
signal mgt_tx_reset_i : std_logic;
signal powerdown_i : std_logic;
signal rxclkcorcnt_i : std_logic_vector(2 downto 0);
signal rxchariscomma_i : std_logic;
signal rxcharisk_i : std_logic;
signal rxdisperr_i : std_logic;
signal rxnotintable_i : std_logic;
signal rxrundisp_i : std_logic;
signal txbuferr_i : std_logic;
signal txchardispmode_i : std_logic;
signal txchardispval_i : std_logic;
signal txcharisk_i : std_logic;
signal gtx_clk_ibufg_i : std_logic;
signal rxbufstatus_i : std_logic;
signal rxchariscomma_r : std_logic;
signal rxcharisk_r : std_logic;
signal rxclkcorcnt_r : std_logic_vector(2 downto 0);
signal mgt_rx_data_r : std_logic_vector(7 downto 0);
signal rxdisperr_r : std_logic;
signal rxnotintable_r : std_logic;
signal rxrundisp_r : std_logic;
signal txchardispmode_r : std_logic;
signal txchardispval_r : std_logic;
signal txcharisk_r : std_logic;
signal mgt_tx_data_r : std_logic_vector(7 downto 0);
-- Transceiver clocking signals
signal usrclk2 : std_logic;
signal txoutclk : std_logic;
signal plllock_i : std_logic;
-------------------------------------------------------------------------------
-- Attribute declarations
-------------------------------------------------------------------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of reset_r : signal is "TRUE";
-------------------------------------------------------------------------------
-- Main body of code
-------------------------------------------------------------------------------
begin
gnd_i <= '0';
vcc_i <= '1';
---------------------------------------------------------------------------
-- Main reset circuitry
---------------------------------------------------------------------------
reset_ibuf_i <= RESET;
-- Synchronize and extend the external reset signal
process(usrclk2, reset_ibuf_i)
begin
if (reset_ibuf_i = '1') then
reset_r <= "1111";
elsif usrclk2'event and usrclk2 = '1' then
if (plllock_i = '1') then
reset_r <= reset_r(2 downto 0) & reset_ibuf_i;
end if;
end if;
end process;
-- Apply the extended reset pulse to the EMAC
reset_i <= reset_r(3);
---------------------------------------------------------------------------
-- Instantiate GTX for SGMII or 1000BASE-X PCS/PMA physical interface
---------------------------------------------------------------------------
v6_gtxwizard_top_inst : v6_gtxwizard_top
PORT MAP (
RESETDONE => resetdone_i,
ENMCOMMAALIGN => encommaalign_i,
ENPCOMMAALIGN => encommaalign_i,
LOOPBACK => loopback_i,
POWERDOWN => powerdown_i,
RXUSRCLK2 => usrclk2,
RXRESET => mgt_rx_reset_i,
TXCHARDISPMODE => txchardispmode_r,
TXCHARDISPVAL => txchardispval_r,
TXCHARISK => txcharisk_r,
TXDATA => mgt_tx_data_r,
TXUSRCLK2 => usrclk2,
TXRESET => mgt_tx_reset_i,
RXCHARISCOMMA => rxchariscomma_i,
RXCHARISK => rxcharisk_i,
RXCLKCORCNT => rxclkcorcnt_i,
RXDATA => mgt_rx_data_i,
RXDISPERR => rxdisperr_i,
RXNOTINTABLE => rxnotintable_i,
RXRUNDISP => rxrundisp_i,
RXBUFERR => rxbufstatus_i,
TXBUFERR => txbuferr_i,
PLLLKDET => plllock_i,
TXOUTCLK => txoutclk,
RXELECIDLE => elecidle_i,
TXN => TXN,
TXP => TXP,
RXN => RXN,
RXP => RXP,
CLK_DS => CLK_DS,
PMARESET => reset_ibuf_i
);
RESETDONE <= resetdone_i;
--------------------------------------------------------------------------
-- Register the signals between EMAC and transceiver for timing purposes
--------------------------------------------------------------------------
regrx : process (usrclk2, reset_i)
begin
if reset_i = '1' then
rxchariscomma_r <= '0';
rxcharisk_r <= '0';
rxclkcorcnt_r <= (others => '0');
mgt_rx_data_r <= (others => '0');
rxdisperr_r <= '0';
rxnotintable_r <= '0';
rxrundisp_r <= '0';
txchardispmode_r <= '0';
txchardispval_r <= '0';
txcharisk_r <= '0';
mgt_tx_data_r <= (others => '0');
elsif usrclk2'event and usrclk2 = '1' then
rxchariscomma_r <= rxchariscomma_i;
rxcharisk_r <= rxcharisk_i;
rxclkcorcnt_r <= rxclkcorcnt_i;
mgt_rx_data_r <= mgt_rx_data_i;
rxdisperr_r <= rxdisperr_i;
rxnotintable_r <= rxnotintable_i;
rxrundisp_r <= rxrundisp_i;
txchardispmode_r <= txchardispmode_i after 1 ns;
txchardispval_r <= txchardispval_i after 1 ns;
txcharisk_r <= txcharisk_i after 1 ns;
mgt_tx_data_r <= mgt_tx_data_i after 1 ns;
end if;
end process regrx;
-- Detect when there has been a disconnect
signal_detect_i <= not(elecidle_i);
--------------------------------------------------------------------
-- GTX clock management
--------------------------------------------------------------------
-- 125MHz clock is used for GT user clocks and used
-- to clock all Ethernet core logic
usrclk2 <= CLK125;
-- GTX reference clock
gtx_clk_ibufg_i <= usrclk2;
-- PLL locks
emac_locked_i <= plllock_i;
-- SGMII client-side transmit clock
tx_client_clk_in_i <= usrclk2;
-- SGMII client-side receive clock
rx_client_clk_in_i <= usrclk2;
-- 125MHz clock output from transceiver
CLK125_OUT <= txoutclk;
--------------------------------------------------------------------------
-- Instantiate the primitive-level EMAC wrapper (v6_emac_v1_4.vhd)
--------------------------------------------------------------------------
v6_emac_v1_4_inst : v6_emac_v1_4
port map (
-- Client receiver interface
EMACCLIENTRXCLIENTCLKOUT => rx_client_clk_out_i,
CLIENTEMACRXCLIENTCLKIN => rx_client_clk_in_i,
EMACCLIENTRXD => EMACCLIENTRXD,
EMACCLIENTRXDVLD => EMACCLIENTRXDVLD,
EMACCLIENTRXDVLDMSW => open,
EMACCLIENTRXGOODFRAME => EMACCLIENTRXGOODFRAME,
EMACCLIENTRXBADFRAME => EMACCLIENTRXBADFRAME,
EMACCLIENTRXFRAMEDROP => EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS => EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD => EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD => EMACCLIENTRXSTATSBYTEVLD,
-- Client transmitter interface
EMACCLIENTTXCLIENTCLKOUT => tx_client_clk_out_i,
CLIENTEMACTXCLIENTCLKIN => tx_client_clk_in_i,
CLIENTEMACTXD => CLIENTEMACTXD,
CLIENTEMACTXDVLD => CLIENTEMACTXDVLD,
CLIENTEMACTXDVLDMSW => gnd_i,
EMACCLIENTTXACK => EMACCLIENTTXACK,
CLIENTEMACTXFIRSTBYTE => CLIENTEMACTXFIRSTBYTE,
CLIENTEMACTXUNDERRUN => CLIENTEMACTXUNDERRUN,
EMACCLIENTTXCOLLISION => EMACCLIENTTXCOLLISION,
EMACCLIENTTXRETRANSMIT => EMACCLIENTTXRETRANSMIT,
CLIENTEMACTXIFGDELAY => CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS => EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD => EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD => EMACCLIENTTXSTATSBYTEVLD,
-- MAC control interface
CLIENTEMACPAUSEREQ => CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL => CLIENTEMACPAUSEVAL,
-- Clock signals
GTX_CLK => usrclk2,
EMACPHYTXGMIIMIICLKOUT => open,
PHYEMACTXGMIIMIICLKIN => gnd_i,
-- SGMII interface
RXDATA => mgt_rx_data_r,
TXDATA => mgt_tx_data_i,
MMCM_LOCKED => emac_locked_i,
AN_INTERRUPT => EMACANINTERRUPT,
SIGNAL_DETECT => signal_detect_i,
PHYAD => PHYAD,
ENCOMMAALIGN => encommaalign_i,
LOOPBACKMSB => loopback_i,
MGTRXRESET => mgt_rx_reset_i,
MGTTXRESET => mgt_tx_reset_i,
POWERDOWN => powerdown_i,
SYNCACQSTATUS => EMACCLIENTSYNCACQSTATUS,
RXCLKCORCNT => rxclkcorcnt_r,
RXBUFSTATUS => rxbufstatus_i,
RXCHARISCOMMA => rxchariscomma_r,
RXCHARISK => rxcharisk_r,
RXDISPERR => rxdisperr_r,
RXNOTINTABLE => rxnotintable_r,
RXREALIGN => '0',
RXRUNDISP => rxrundisp_r,
TXBUFERR => txbuferr_i,
TXCHARDISPMODE => txchardispmode_i,
TXCHARDISPVAL => txchardispval_i,
TXCHARISK => txcharisk_i,
-- Asynchronous reset
RESET => reset_i
);
end TOP_LEVEL;
|
gpl-3.0
|
f89ea85996f63d22de6ffbca2e2eda8a
| 0.509401 | 5.0027 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v1_00_a/hdl/vhdl/TESTBENCH_ac97_if.vhd
| 4 | 3,256 |
-------------------------------------------------------------------------------
-- TESTBENCH_standalone.vhd
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_standalone.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:34 $
--
-- History:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBENCH_standalone is
end TESTBENCH_standalone;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.testbench_ac97_package.all;
architecture behavioral of TESTBENCH_standalone is
component ac97_if is
port (
ClkIn : in std_logic;
Reset : in std_logic;
PCM_Playback_Left: in std_logic_vector(15 downto 0);
PCM_Playback_Right: in std_logic_vector(15 downto 0);
PCM_Playback_Accept: out std_logic;
PCM_Record_Left: out std_logic_vector(15 downto 0);
PCM_Record_Right: out std_logic_vector(15 downto 0);
PCM_Record_Valid: out std_logic;
Debug : out std_logic_Vector(3 downto 0);
AC97Reset_n : out std_logic; -- AC97Clk
AC97Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic
);
end component;
component ac97_model is
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end component;
signal bit_clk, sync, sdata_out, sdata_in : std_logic;
signal ac97_reset_n, fast_clk, reset : std_logic;
signal pcm_play_left, pcm_play_right : std_logic_vector(15 downto 0);
signal pcm_record_left, pcm_record_right : std_logic_vector(15 downto 0) := (others => '0');
begin -- behavioral
clk_PROCESS : process is
begin
fast_clk <= '0';
wait for 5 ns;
fast_clk <= '1';
wait for 5 ns;
end process;
reset_PROCESS : process is
begin
reset <= '1';
wait for 5 us;
reset <= '0';
wait;
end process;
uut : ac97_if
port map (
ClkIn => fast_clk,
Reset => reset,
PCM_Playback_Left => pcm_play_left,
PCM_Playback_Right => pcm_play_right,
PCM_Playback_Accept => open,
PCM_Record_Left => pcm_record_left,
PCM_Record_Right => pcm_record_right,
PCM_Record_Valid => open,
Debug => open,
AC97Reset_n => ac97_reset_n,
AC97Clk => Bit_Clk,
Sync => Sync,
SData_Out => SData_Out,
SData_In => SData_In
);
uut_1 : ac97_model
port map (
-- CODEC signals
AC97Reset_n => ac97_reset_n,
Bit_Clk => Bit_Clk,
Sync => Sync,
SData_Out => SData_Out,
SData_In => SData_In
);
end behavioral;
|
gpl-3.0
|
7bdbf52c6ad2ffbcca3eb4eb61c30679
| 0.491093 | 3.712657 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.ip_user_files/ipstatic/axi_uartlite_v2_0_10/hdl/src/vhdl/dynshreg_i_f.vhd
| 1 | 12,369 |
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_i_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
-- This version allows the client to specify the initial value
-- of the contents of the shift register, as applied
-- during configuration.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
--
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--------------------------------------------------------------------------------
-- Explanations of generics and ports regarding aspects that may not be obvious.
--
-- C_DWIDTH
--------
-- Theoretically, C_DWIDTH may be set to zero and this could be a more
-- natural or preferrable way of excluding a dynamic shift register
-- in a client than using a VHDL Generate statement. However, this usage is not
-- tested, and the user should expect that some VHDL tools will be deficient
-- with respect to handling this properly.
--
-- C_INIT_VALUE
---------------
-- C_INIT_VALUE can be used to specify the initial values of the elements
-- in the dynamic shift register, i.e. the values to be present after config-
-- uration. C_INIT_VALUE need not be the same size as the dynamic shift
-- register, i.e. C_DWIDTH*C_DEPTH. When smaller, C_INIT_VALUE
-- is replicated as many times as needed (possibly fractionally the last time)
-- to form a full initial value that is the size of the shift register.
-- So, if C_INIT_VALUE is left at its default value--an array of size one
-- whose value is '0'--the shift register will initialize with all bits at
-- all addresses set to '0'. This will also be the case if C_INIT_VALUE is a
-- null (size zero) array.
-- When determined according to the rules outlined above, the full
-- initial value is a std_logic_vector value from (0 to C_DWIDTH*C_DEPTH-1). It
-- is allocated to the addresses of the dynamic shift register in this
-- manner: The first C_DWIDTH values (i.e. 0 to C_CWIDTH-1) assigned to
-- the corresponding indices at address 0, the second C_DWIDTH values
-- assigned to address 1, and so forth.
-- Please note that the shift register is not resettable after configuration.
--
-- Addr
----
-- Addr addresses the elements of the dynamic shift register. Addr=0 causes
-- the most recently shifted-in element to appear at Dout, Addr=1
-- the second most recently shifted in element, etc. If C_DEPTH is not
-- a power of two, then not all of the values of Addr correspond to an
-- element in the shift register. When such an address is applied, the value
-- of Dout is undefined until a valid address is established.
--------------------------------------------------------------------------------
entity dynshreg_i_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_INIT_VALUE : bit_vector := "0";
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_i_f;
architecture behavioral of dynshreg_i_f is
constant USE_INFERRED : boolean := true;
type bv2sl_type is array(bit) of std_logic;
constant bv2sl : bv2sl_type := ('0' => '0', '1' => '1');
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
--
------------------------------------------------------------------------------
-- Function used to establish the full initial value. (See the comments for
-- C_INIT_VALUE, above.)
------------------------------------------------------------------------------
function full_initial_value(w : natural; d : positive; v : bit_vector
) return bit_vector is
variable r : bit_vector(0 to w*d-1);
variable i, j : natural;
-- i - the index where filling of r continues
-- j - the amount to fill on the cur. iteration of the while loop
begin
if w = 0 then null; -- Handle the case where the shift reg width is zero
elsif v'length = 0 then r := (others => '0');
else
i := 0;
while i /= r'length loop
j := min(v'length, r'length-i);
r(i to i+j-1) := v(0 to j-1);
i := i+j;
end loop;
end if;
return r;
end full_initial_value;
constant FULL_INIT_VAL : bit_vector(0 to C_DWIDTH*C_DEPTH -1)
:= full_initial_value(C_DWIDTH, C_DEPTH, C_INIT_VALUE);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
begin
INFERRED_GEN : if USE_INFERRED = true generate
--
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
--
function fill_data(w: natural; d: positive; v: bit_vector
) return dataType is
variable r : dataType;
begin
for i in 0 to d-1 loop
for j in 0 to w-1 loop
r(i)(j) := bv2sl(v(i*w+j));
end loop;
end loop;
return r;
end fill_data;
signal data: dataType := fill_data(C_DWIDTH, C_DEPTH, FULL_INIT_VAL);
--
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
|
mit
|
a14637b88ee1703b5e6ae1403c5e2223
| 0.510551 | 4.697683 | false | false | false | false |
luebbers/reconos
|
tests/simulation/plb/mbox_hwsw/test_mbox.vhd
| 1 | 2,322 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test_mbox is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end test_mbox;
architecture Behavioral of test_mbox is
constant C_MB_IN : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_OUT : std_logic_vector(0 to 31) := X"00000001";
type t_state is (STATE_GET, STATE_PUT);
signal state : t_state := STATE_GET;
signal data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal data_inv : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWE <= '0';
o_RAMClk <= clk;
data_inv <= not data;
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_GET;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_GET =>
reconos_mbox_tryget_s(done, success, o_osif, i_osif, C_MB_IN, data);
if done and success then
state <= STATE_PUT;
end if;
when STATE_PUT =>
reconos_mbox_tryput(done, success, o_osif, i_osif, C_MB_OUT, data_inv);
if done and success then
state <= STATE_GET;
end if;
when others =>
state <= STATE_GET;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
5302e691d73b1391496959f69349377c
| 0.595607 | 3.238494 | false | false | false | false |
luebbers/reconos
|
demos/particle_filter_framework/hw/dynamic_src/user_processes/uf_extract_observation.vhd
| 1 | 39,476 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.MATH_REAL.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : E X T R A C T O B S E R V A T I O N
--
--
-- The user function calcualtes a observation for a particle
-- A pointer to the input data is given. The user process can
-- ask for data at a specific address.
--
-- Thus, all needed data can be loaded into the entity. Thus,
-- the observation can be calculated via input data. When no more
-- data is needed, the observation is stored into the local ram.
--
-- If the observation is stored in the ram, the finished signal has
-- to be set to '1'.
--
------------------------------------------------------------------------------------
entity uf_extract_observation is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- parameters loaded
parameter_loaded : in std_logic;
parameter_loaded_ack : out std_logic;
-- new particle loaded
new_particle : in std_logic;
new_particle_ack : out std_logic;
-- input data address
input_data_address : in std_logic_vector(0 to 31);
input_data_needed : out std_logic;
-- get word data
word_data_en : in std_logic;
word_address : out std_logic_vector(0 to 31);
word_data : in std_logic_vector(0 to 31);
word_data_ack : out std_logic;
-- if the observation is calculated, this signal has to be set to '1'
finished : out std_logic
);
end uf_extract_observation;
architecture Behavioral of uf_extract_observation is
component pipelined_divider
port (
clk: in std_logic;
ce: in std_logic;
aclr: in std_logic;
sclr: in std_logic;
dividend: in std_logic_VECTOR(31 downto 0);
divisor: in std_logic_VECTOR(31 downto 0);
quot: out std_logic_VECTOR(31 downto 0);
remd: out std_logic_VECTOR(31 downto 0);
rfd: out std_logic);
end component;
type hsv_function is array ( 0 to 255) of integer;
-- GRANULARITY
constant GRAN_EXP : integer := 14;
constant GRANULARITY : integer := 2**GRAN_EXP;
constant hd_values : hsv_function := (
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9);
constant sdvd_values : hsv_function := (
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
9, 9, 9, 9, 9, 9);
-- states
type t_state is (STATE_INIT, STATE_READ_PARAMETER, STATE_INIT_HISTOGRAM,
STATE_READ_PARTICLE, STATE_ANALYZE_PARTICLE, STATE_CALCULATE_HISTOGRAM,
STATE_GET_PIXEL,STATE_UPDATE_HISTOGRAM, STATE_CHECK_FINISHED,
STATE_NORMALIZE_HISTOGRAM, STATE_COPY_HISTOGRAM,
STATE_FINISH);
signal state : t_state;
-----------------------------------------------------
-- signals needed for divider component
-----------------------------------------------------
-- clock enable
signal ce : std_logic;
-- synchronous clear
signal sclr : std_logic := '0';
-- asynchronous clear
signal aclr : std_logic := '0';
-- dividend
signal dividend : std_logic_vector(31 downto 0) := (others => '0');
-- divisor
signal divisor : std_logic_vector(31 downto 0) := "00000000000000000000000000000001";
-- quotient
signal quotient : std_logic_vector(31 downto 0) := (others => '0');
-- remainder
signal remainder : std_logic_vector(31 downto 0) := (others => '0');
-- ready for data
signal rfd : std_logic;
-- local ram address for interface
signal local_ram_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal local_ram_start_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- HSV signals
signal H : std_logic_vector(0 to 7) := (others => '0');
signal S : std_logic_vector(0 to 7) := (others => '0');
signal V : std_logic_vector(0 to 7) := (others => '0');
signal H_store : std_logic_vector(0 to 7) := (others => '0');
signal S_store : std_logic_vector(0 to 7) := (others => '0');
signal V_store : std_logic_vector(0 to 7) := (others => '0');
constant S_THRESH : integer := 25;
constant V_THRESH : integer := 50;
signal hd : natural range 0 to 9 := 0;
signal sd : natural range 0 to 9 := 0;
signal vd : natural range 0 to 9 := 0;
signal value : natural := 0;
-- copy histogram
signal copy_histo_en : std_logic := '0'; -- handshake signal
signal copy_histo_done : std_logic := '0'; -- handshake signal
signal copy_histo_addr : std_logic_vector(C_BURST_AWIDTH-1 downto 0); -- burst ram addr
signal copy_histo_bucket : std_logic_vector(6 downto 0); -- histogram addr
signal copy_histo_data : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- update histogram
signal update_histo_en : std_logic := '0'; -- handshake signal
signal update_histo_done : std_logic := '0'; -- handshake signal
signal update_histo_addr : std_logic_vector(C_BURST_AWIDTH-1 downto 0); -- burst ram addr
signal update_histo_bucket : std_logic_vector(6 downto 0); -- histogram addr
-- clear histogram
signal clear_histo_en : std_logic := '0'; -- handshake signal
signal clear_histo_done : std_logic := '0'; -- handshake signal
signal clear_histo_bucket : std_logic_vector(6 downto 0) := (others => '0'); -- histogram addr
-- normalize histogram
signal normalize_histo_en : std_logic := '0'; -- handshake signal
signal normalize_histo_done : std_logic := '0'; -- handshake signal
signal normalize_histo : std_logic := '0'; -- set histo_ram value
signal normalize_histo_value : std_logic_vector(31 downto 0) := (others=>'0'); -- new normalized histo value
signal normalize_histo_bucket : std_logic_vector(6 downto 0) := (others => '0'); -- histogram addr
-- read particle data
signal read_particle_en : std_logic := '0'; -- handshake signal
signal read_particle_done : std_logic := '0'; -- handshake signal
signal read_particle_addr : std_logic_vector(C_BURST_AWIDTH-1 downto 0) := (others=>'0');
-- analyze particle
signal analyze_particle_en : std_logic := '0'; -- handshake signal
signal analyze_particle_done : std_logic := '0'; -- handshake signal
-- read parameter
signal read_parameter_en : std_logic := '0'; -- handshake signal
signal read_parameter_done : std_logic := '0'; -- handshake signal
signal read_parameter_addr : std_logic_vector(C_BURST_AWIDTH-1 downto 0) := (others=>'0');
-- calculate histogram
signal calc_histo_en : std_logic := '0'; -- handshake signal
signal calc_histo_done : std_logic := '0'; -- handshake signal
-- get_pixel
signal get_pixel_en : std_logic := '0'; -- handshake signal
signal get_pixel_done : std_logic := '0'; -- handshake signal
-- histogram
type t_ram is array (109 downto 0) of std_logic_vector(31 downto 0);
signal histo_ram : t_ram; -- histogram memory
signal histo_bucket : std_logic_vector(6 downto 0); -- current histogram bucket
signal histo_inc : std_logic := '0'; -- enables incrementing
signal histo_clear : std_logic := '0'; -- enables setting to zero
signal histo_value : std_logic_vector(31 downto 0); -- value of current bucket
-- particle data
signal x : integer := 0;
signal y : integer := 0;
signal scale : integer := 0;
signal width : integer := 0;
signal height : integer := 0;
-- input data
-- left upper corner
signal x1 : integer := 0;
signal y1 : integer := 0;
-- right bottom corner
signal x2 : integer := 0;
signal y2 : integer := 2;
-- current pixel
signal px : integer := 0;
signal py : integer := 0;
-- current pixel
signal size_x : integer := 480;
signal size_y : integer := 360;
-- temporary signals
signal temp_x : integer := 0;
signal temp_y : integer := 0;
signal temp : integer := 0;
-- input data offset
signal input_data_offset : integer := 0;
-- sum of histogram
signal sum : integer := 0;
-- signal for counter
signal i : integer := 0;
signal j : integer := 0;
begin
divider : pipelined_divider
port map ( clk => clk, ce => ce, aclr => aclr, sclr => sclr, dividend => dividend,
divisor => divisor, quot => quotient, remd => remainder, rfd => rfd);
-- burst ram interface
o_RAMClk <= clk;
ce <= enable;
-- histogram memory is basically a single port ram with
-- asynchronous read. the current bucket is incremented each
-- clock cycle when histo_inc is high, or set to zero when
-- histo_clear is high.
-- @author: Andreas Agne
histo_value <= histo_ram(CONV_INTEGER(histo_bucket));
histo_ram_proc : process(clk)
begin
if rising_edge(clk) then
-- TRY: CLOCKED VERSION
--histo_value <= histo_ram(CONV_INTEGER(histo_bucket));
if histo_inc = '1' then
histo_ram(TO_INTEGER(UNSIGNED(histo_bucket))) <= histo_ram(CONV_INTEGER(histo_bucket)) + 1;
elsif histo_clear = '1' then
histo_ram(TO_INTEGER(UNSIGNED(histo_bucket))) <= (others=>'0');
elsif normalize_histo = '1' then
histo_ram(TO_INTEGER(UNSIGNED(histo_bucket))) <= normalize_histo_value;
end if;
end if;
end process;
-- signals and processes related to updating the histogram from
-- burst-ram data
update_histo_proc : process(clk, reset, update_histo_en)
variable step : natural range 0 to 3;
begin
if reset = '1' or update_histo_en = '0' then
step := 0;
histo_inc <= '0';
update_histo_addr <= (others => '0');
update_histo_done <= '0';
update_histo_bucket <= (others => '0');
elsif rising_edge(clk) then
case step is
when 0 => -- calculate hd
hd <= hd_values(TO_INTEGER(UNSIGNED(H_store)));
sd <= sdvd_values(TO_INTEGER(UNSIGNED(S_store)));
vd <= sdvd_values(TO_INTEGER(UNSIGNED(V_store)));
step := step + 1;
when 1 => -- calculate histogram position
if( S_THRESH <= S and V_THRESH <= V) then
value <= 10 * sd + hd;
else
value <= 100 + vd;
end if;
step := step + 1;
when 2 => -- increment histogram value
histo_inc <= '1';
update_histo_bucket <= STD_LOGIC_VECTOR(TO_UNSIGNED(value, 7));
step := step + 1;
when 3 => -- turn off histogram incrementing, set handshake signal
histo_inc <= '0';
update_histo_done <= '1';
-- when 0 => -- calculate hd
-- hd <= hd_values(TO_INTEGER(UNSIGNED(H)));
-- step := step + 1;
--
-- when 1 => -- calculate sd
-- sd <= sdvd_values(TO_INTEGER(UNSIGNED(S)));
-- step := step + 1;
--
-- when 2 => -- calculate vd
-- vd <= sdvd_values(TO_INTEGER(UNSIGNED(V)));
-- step := step + 1;
--
-- when 3 => -- calculate histogram position (1 of 2)
-- if( S_THRESH <= S and V_THRESH <= V) then
-- value <= 10 * sd;
-- else
-- value <= 100 + vd;
-- end if;
-- step := step + 1;
--
-- when 4 => -- calculate histogram position (2 of 2)
-- if( S_THRESH <= S and V_THRESH <= V) then
-- value <= value + hd;
-- end if;
-- step := step + 1;
--
-- when 5 => -- increment histogram value
-- histo_inc <= '1';
-- update_histo_bucket <= STD_LOGIC_VECTOR(TO_UNSIGNED(value, 7));
-- step := step + 1;
--
-- when 6 => -- turn off histogram incrementing, set handshake signal
-- histo_inc <= '0';
-- update_histo_done <= '1';
end case;
end if;
end process;
-- signals and processes related to copying the histogram to
-- burst-ram
-- @author: Andreas Agne
copy_histogram : process(clk, reset, copy_histo_en)
variable step : natural range 0 to 7;
begin
if reset = '1' or copy_histo_en = '0' then
copy_histo_addr <= (others => '0');
copy_histo_bucket <= (others => '0');
copy_histo_done <= '0';
o_RAMWE <= '0';
copy_histo_data <= (others => '0');
step := 0;
elsif rising_edge(clk) then
case step is
when 0 => -- set histogram and burst ram addresses to 0
copy_histo_addr <= (others => '0');
copy_histo_bucket <= (others => '0');
step := step + 1;
when 1 => -- copy first word
copy_histo_addr <= (others => '0');
copy_histo_bucket <= copy_histo_bucket + 1;
o_RAMWE <= '1';
copy_histo_data <= histo_value;
step := step + 1;
when 2 => -- copy remaining histogram buckets to burst ram
copy_histo_addr <= copy_histo_addr + 1;
copy_histo_bucket <= copy_histo_bucket + 1;
o_RAMWE <= '1';
copy_histo_data <= histo_value;
if (108 <= copy_histo_bucket) then
step := step + 1;
end if;
when 3 => -- wait (1 of 2)
o_RAMWE <= '1';
copy_histo_addr <= copy_histo_addr + 1;
copy_histo_data <= histo_value;
step := step + 1;
when 4 => -- wait (2 of 2)
o_RAMWE <= '1';
step := step + 1;
when 5 => -- write n
o_RAMWE <= '1';
copy_histo_addr <= copy_histo_addr + 1;
copy_histo_data <= STD_LOGIC_VECTOR(TO_SIGNED(110, 32));
step := step + 1;
when 6 => -- write dummy
o_RAMWE <= '1';
copy_histo_addr <= copy_histo_addr + 1;
copy_histo_data <= STD_LOGIC_VECTOR(TO_SIGNED(0, 32));
step := step + 1;
when 7 => -- all buckets copied -> set handshake signal
copy_histo_done <= '1';
copy_histo_bucket <= (others => '0');
o_RAMWE <= '0';
end case;
end if;
end process;
-- signals and processes related to calculating the histogram
calc_histo_proc : process(clk, reset, calc_histo_en)
variable step : natural range 0 to 5;
begin
if reset = '1' or calc_histo_en = '0' then
step := 0;
H_store(0 to 7) <= (others => '0');
S_store(0 to 7) <= (others => '0');
V_store(0 to 7) <= (others => '0');
update_histo_en <= '0';
get_pixel_en <= '0';
calc_histo_done <= '0';
elsif rising_edge(clk) then
case step is
when 0 => -- get 1st pixel
px <= x1;
py <= y1;
get_pixel_en <= '1';
update_histo_en <= '0';
step := step + 1;
when 1 => -- first pixel stored
if (get_pixel_done = '1') then
H_store(0 to 7) <= H(0 to 7);
S_store(0 to 7) <= S(0 to 7);
V_store(0 to 7) <= V(0 to 7);
get_pixel_en <= '0';
update_histo_en <= '0';
px <= px + 1;
step := step + 1;
end if;
when 2 => -- start parallel execution or last update
if (px > x2 and y2 <= py) then
-- finished: last update
step := step + 2;
update_histo_en <= '1';
get_pixel_en <= '0';
elsif (px > x2 and py < y2) then
-- next row
px <= x1;
py <= py + 1;
-- read next pixel and update histogram for last one
get_pixel_en <= '1';
update_histo_en <= '1';
step := step + 1;
else
-- default: read next pixel and update histogram for last one
get_pixel_en <= '1';
update_histo_en <= '1';
step := step + 1;
end if;
when 3 => -- parallel execution finished
if (update_histo_done = '1' and get_pixel_done = '1' ) then
get_pixel_en <= '0';
update_histo_en <= '0';
H_store(0 to 7) <= H(0 to 7);
S_store(0 to 7) <= S(0 to 7);
V_store(0 to 7) <= V(0 to 7);
px <= px + 1;
step := step - 1;
end if;
when 4 => -- last histogram update
if (update_histo_done = '1') then
update_histo_en <= '0';
get_pixel_en <= '0';
step := step + 1;
end if;
when 5 => -- set handshake signal
update_histo_en <= '0';
get_pixel_en <= '0';
calc_histo_done <= '1';
end case;
end if;
end process;
-- signals and processes related to clearing the histogram
-- @author: Andreas Agne
clear_histogram_proc : process(clk, reset, clear_histo_en)
variable step : natural range 0 to 3;
begin
if reset = '1' or clear_histo_en = '0' then
step := 0;
histo_clear <= '0';
clear_histo_bucket <= (others => '0');
clear_histo_done <= '0';
elsif rising_edge(clk) then
case step is
when 0 => -- enable bucket zeroing
clear_histo_bucket <= (others => '0');
histo_clear <= '1';
step := step + 1;
when 1 => -- visit every bucket
clear_histo_bucket <= clear_histo_bucket + 1;
if 108 <= clear_histo_bucket then
step := step + 1;
end if;
when 2 =>
step := step + 1;
when 3 => -- set handshake signal
histo_clear <= '0';
clear_histo_bucket <= (others => '0');
clear_histo_done <= '1';
end case;
end if;
end process;
-- reads parameter
read_parameter_proc: process (clk, reset, read_parameter_en)
variable step : natural range 0 to 4;
begin
if reset = '1' or read_parameter_en = '0' then
step := 0;
read_parameter_done <= '0';
parameter_loaded_ack <= '0';
elsif rising_edge(clk) then
case step is
when 0 =>
--! read parameter values
read_parameter_addr <= local_ram_start_address_if;
parameter_loaded_ack <= '0';
step := step + 1;
when 1 =>
--! wait one cycle
read_parameter_addr <= local_ram_start_address_if + 1;
step := step + 1;
when 2 =>
--! read size_x
size_x <= TO_INTEGER(SIGNED(i_RAMData));
step := step + 1;
when 3 =>
--! read size_y
size_y <= TO_INTEGER(SIGNED(i_RAMData));
parameter_loaded_ack <= '1';
step := step + 1;
when 4 =>
if (parameter_loaded = '0') then
read_parameter_done <= '1';
parameter_loaded_ack <= '0';
end if;
end case;
end if;
end process;
-- signals and processes related to normalizing the histograme
normalize_histogram_proc : process(clk, reset, normalize_histo_en, ce)
variable step : natural range 0 to 7;
begin
if reset = '1' or normalize_histo_en = '0' then
step := 0;
normalize_histo_bucket <= (others => '0');
normalize_histo_done <= '0';
divisor <= "00000000000000000000000000000001";
elsif ce = '0' then
elsif rising_edge(clk) then
case step is
when 0 =>
-- init sum calculation
i <= 0;
sum <= 0;
step := step + 1;
when 1 =>
-- calculate sum
sum <= sum + CONV_INTEGER(histo_ram(i));
if (i < 109) then
i <= i + 1;
else
step := step + 1;
end if;
-- init
when 2 =>
normalize_histo_bucket <= (others => '0');
normalize_histo <= '0';
i <= 0;
step := step + 1;
-- modify histo_values (histo_value * GRANULARITY) and sum up histogram
-- first histo_value
when 3 =>
normalize_histo <= '1';
-- modify value: value * GRANULARITY
normalize_histo_value <= histo_ram(i)(17 downto 0) & "00000000000000";
i <= 1;
step := step + 1;
-- other histo_values
when 4 =>
normalize_histo <= '1';
-- modify value: value * GRANULARITY
normalize_histo_value <= histo_ram(i)(17 downto 0) & "00000000000000";
if (i < 109) then
i <= i + 1;
end if;
if (normalize_histo_bucket < 109) then
normalize_histo_bucket <= normalize_histo_bucket + 1;
else
step := step + 1;
end if;
when 5 =>
-- start division
normalize_histo <= '0';
normalize_histo_bucket <= (others => '0');
divisor <= STD_LOGIC_VECTOR(TO_SIGNED(sum, 32));
i <= 0;
step := step + 1;
when 6 =>
-- put all 110 histogram values into pipelined divider.
-- pipelined divider has a latency of 36 clock cycles
-- 36 = 32 (width of dividend) + 4 (see: coregen datasheed)
-- one clock cycle per division
if (i<110) then
-- put histogram values to pipeline
dividend <= histo_ram(i);
i <= i + 1;
end if;
if (i > 36) then
-- collect division results
normalize_histo <= '1';
normalize_histo_value <= quotient;
if (normalize_histo_bucket < 109 and i > 37) then
normalize_histo_bucket <= normalize_histo_bucket + 1;
elsif (109 <= normalize_histo_bucket) then
step := step + 1;
end if;
end if;
when 7 =>
-- set handshake signal;
normalize_histo <= '0';
normalize_histo_bucket <= (others => '0');
normalize_histo_done <= '1';
end case;
end if;
end process;
-- reads particle data needed for histogram calculation
read_particle_proc: process (clk, reset, read_particle_en, ce)
variable step : natural range 0 to 8;
begin
if reset = '1' or read_particle_en = '0' then
step := 0;
read_particle_done <= '0';
--local_ram_address_if <= local_ram_start_address_if;
elsif ce = '0' then
elsif rising_edge(clk) and ce = '1' then
case step is
when 0 =>
--! increment local ram address to get x value
local_ram_address_if <= local_ram_start_address_if + 1;
step := step + 1;
when 1 =>
--! read particle values
read_particle_addr <= local_ram_address_if;
local_ram_address_if <= local_ram_address_if + 1;
step := step + 1;
when 2 =>
--! wait one cycle
local_ram_address_if <= local_ram_address_if + 1;
read_particle_addr <= local_ram_address_if;
step := step + 1;
when 3 =>
--! read x
x <= TO_INTEGER(SIGNED(i_RAMData));
local_ram_address_if <= local_ram_address_if + 6;
read_particle_addr <= local_ram_address_if;
step := step + 1;
when 4 =>
--! read y
y <= TO_INTEGER(SIGNED(i_RAMData));
local_ram_address_if <= local_ram_address_if + 1;
read_particle_addr <= local_ram_address_if;
step := step + 1;
when 5 =>
--! read scale
scale <= TO_INTEGER(SIGNED(i_RAMData));
read_particle_addr <= local_ram_address_if;
step := step + 1;
when 6 =>
--! read width
width <= TO_INTEGER(SIGNED(i_RAMData));
step := step + 1;
when 7 =>
--! read height
height <= TO_INTEGER(SIGNED(i_RAMData));
step := step + 1;
when 8 =>
read_particle_done <= '1';
end case;
end if;
end process;
-- analyzes particle data needed for histogram calculation
analyze_particle_proc: process (clk, reset, analyze_particle_en, ce)
variable step : natural range 0 to 17;
begin
if reset = '1' or analyze_particle_en = '0' then
step := 0;
analyze_particle_done <= '0';
elsif ce = '0' then
elsif rising_edge(clk) and ce = '1' then
case step is
when 0 =>
--! calculate upper left corner (x1, y1) and lower bottom corner (x2, y2) of frame piece
temp_x <= width - 1;
temp_y <= height - 1;
step := step + 1;
when 1 =>
--! calculate (x1, y1) and (x2, y2)
temp_x <= temp_x / 2;
step := step + 1;
when 2 =>
--! calculate (x1, y1) and (x2, y2)
temp_y <= temp_y / 2;
step := step + 1;
when 3 =>
--! calculate (x1, y1) and (x2, y2)
temp_x <= temp_x * scale;
step := step + 1;
when 4 =>
--! wait
step := step + 1;
when 5 =>
--! wait
step := step + 1;
when 6 =>
--! calculate (x1, y1) and (x2, y2)
temp_y <= temp_y * scale;
step := step + 1;
when 7 =>
--! wait
step := step + 1;
when 8 =>
--! wait
step := step + 1;
when 9 =>
--! calculate (x1, y1) and (x2, y2)
x1 <= x - temp_x;
step := step + 1;
when 10 =>
--! calculate (x1, y1) and (x2, y2)
x2 <= x + temp_x;
step := step + 1;
when 11 =>
--! calculate (x1, y1) and (x2, y2)
y1 <= y - temp_y;
step := step + 1;
when 12 =>
--! calculate (x1, y1) and (x2, y2)
y2 <= y + temp_y;
step := step + 1;
when 13 =>
--! calculate (x1, y1) and (x2, y2)
x1 <= x1 / GRANULARITY;
step := step + 1;
when 14 =>
--! calculate (x1, y1) and (x2, y2)
y1 <= y1 / GRANULARITY;
if (x1 < 0) then
x1 <= 0;
end if;
step := step + 1;
when 15 =>
--! calculate (x1, y1) and (x2, y2)
x2 <= x2 / GRANULARITY;
if (y1 < 0) then
y1 <= 0;
end if;
step := step + 1;
when 16 =>
--! calculate (x1, y1) and (x2, y2)
if (x2 > size_x - 1) then
x2 <= size_x - 1;
end if;
y2 <= y2 / GRANULARITY;
step := step + 1;
when 17 =>
--! finished
if (y2 > size_y - 1) then
y2 <= size_y - 1;
end if;
analyze_particle_done <= '1';
end case;
end if;
end process;
-- get next pixel needed for histogram calculation
get_pixel_proc: process (clk, reset, get_pixel_en, ce)
variable step : natural range 0 to 5;
begin
if reset = '1' or get_pixel_en = '0' then
step := 0;
get_pixel_done <= '0';
--word_address <= (others=>'0');
word_data_ack <= '0';
elsif ce = '0' then
elsif rising_edge(clk) then
case step is
when 0 =>
--! calculate offset for input data (1 of 3)
input_data_offset <= 1024 * py;
--input_data_offset <= 512 * py;
step := step + 1;
when 1 =>
--! calculate offset for input data (2 of 3)
input_data_offset <= input_data_offset + px;
step := step + 1;
when 2 =>
--! calculate offset for input data (3 of 3)
input_data_offset <= input_data_offset * 4;
step := step + 1;
when 3 =>
--! read pixel data using entitiy ports
input_data_needed <= '1';
word_address <= input_data_address + input_data_offset;
step := step + 1;
when 4 =>
--! receive pixel data
if word_data_en = '1' then
input_data_needed <= '0';
word_data_ack <= '1';
step := step + 1;
end if;
when 5 =>
--! split pixel data to H,S,V signals
H(0 to 7) <= word_data( 24 to 31);
S(0 to 7) <= word_data( 16 to 23);
V(0 to 7) <= word_data( 8 to 15);
get_pixel_done <= '1';
end case;
end if;
end process;
-- histogram ram mux
-- @author: Andreas Agne
-- updated
mux_proc: process(update_histo_en, copy_histo_en, clear_histo_en, normalize_histo_en,
read_particle_en, read_particle_addr, normalize_histo_bucket,
update_histo_addr, update_histo_bucket,
copy_histo_addr, copy_histo_bucket, clear_histo_bucket,
read_parameter_en, read_parameter_addr,
copy_histo_data)
variable addr : std_logic_vector(C_BURST_AWIDTH - 1 downto 0);
variable data : std_logic_vector(0 to C_BURST_DWIDTH-1);
variable bucket : std_logic_vector(6 downto 0);
begin
if update_histo_en = '1' then
addr := update_histo_addr;
bucket := update_histo_bucket;
data := (others => '0');
elsif copy_histo_en = '1' then
addr := copy_histo_addr;
bucket := copy_histo_bucket;
data := copy_histo_data;
elsif clear_histo_en = '1' then
addr := (others => '0');
bucket := clear_histo_bucket;
data := (others => '0');
elsif normalize_histo_en = '1' then
addr := (others => '0');
bucket := normalize_histo_bucket;
data := (others => '0');
elsif read_particle_en = '1' then
addr := read_particle_addr;
bucket := (others => '0');
data := (others => '0');
elsif read_parameter_en = '1' then
addr := read_parameter_addr;
bucket := (others => '0');
data := (others => '0');
else
addr := (others => '0');
bucket := (others => '0');
data := (others => '0');
end if;
o_RAMData <= data;
o_RAMAddr <= addr(C_BURST_AWIDTH - 1 downto 0);
histo_bucket <= bucket;
end process;
----------------------------------------------------------------------------------
--
-- 1) initialize histogram, finished = '0' (if new_particle = '1')
--
-- 2) read particle data
--
-- 3) extract needed information
--
-- 4) calculate input address, read pixel data (using entity ports)
--
-- 5) update histogram
--
-- 6) more pixel to load
-- go to step 4
-- else
-- go to step 7
--
-- 7) normalize histogram
--
-- 8) write histogram into local ram
--
-- 9) finshed = '1', wait for new_particle = '1'
--
----------------------------------------------------------------------------------
state_proc : process(clk, reset)
begin
if (reset = '1') then
state <= STATE_INIT;
new_particle_ack <= '0';
read_parameter_en <= '0';
finished <= '0';
elsif rising_edge(clk) then
if init = '1' then
state <= STATE_INIT;
finished <= '0';
clear_histo_en <= '0';
elsif enable = '1' then
case state is
when STATE_INIT =>
--! init data
finished <= '0';
calc_histo_en <= '0';
copy_histo_en <= '0';
read_particle_en <= '0';
analyze_particle_en <= '0';
if (new_particle = '1') then
new_particle_ack <= '1';
clear_histo_en <= '1';
state <= STATE_INIT_HISTOGRAM;
elsif (parameter_loaded = '1') then
read_parameter_en <= '1';
state <= STATE_READ_PARAMETER;
end if;
when STATE_READ_PARAMETER =>
--! init histogram
if (read_parameter_done = '1') then
read_parameter_en <= '0';
state <= STATE_INIT;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 1: INIT HISTOGRAM
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_INIT_HISTOGRAM =>
--! init histogram
if (clear_histo_done = '1') then
new_particle_ack <= '0';
clear_histo_en <= '0';
state <= STATE_READ_PARTICLE;
read_particle_en <= '1';
end if;
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
----
---- STEP 2: READ PARTICLE
----
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
when STATE_READ_PARTICLE =>
--! read particle values
if (read_particle_done = '1') then
analyze_particle_en <= '1';
read_particle_en <= '0';
state <= STATE_ANALYZE_PARTICLE;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 3: ANALYZE PARTICLE
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_ANALYZE_PARTICLE =>
--! calculate upper left corner (x1, y1) and lower bottom corner (x2, y2) of frame piece
if (analyze_particle_done = '1') then
analyze_particle_en <= '0';
--get_pixel_en <= '1';
--px <= x1;
--py <= y1;
--state <= STATE_GET_PIXEL;
calc_histo_en <= '1';
state <= STATE_CALCULATE_HISTOGRAM;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 4: GET PIXEL
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_CALCULATE_HISTOGRAM =>
-- get next pixel for histogram calculation
if (calc_histo_done = '1') then
calc_histo_en <= '0';
normalize_histo_en <= '1';
state <= STATE_NORMALIZE_HISTOGRAM;
end if;
-- when STATE_GET_PIXEL =>
-- -- get next pixel for histogram calculation
-- if (get_pixel_done = '1') then
-- get_pixel_en <= '0';
-- update_histo_en <= '1';
-- state <= STATE_UPDATE_HISTOGRAM;
-- end if;
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
----
---- STEP 5: HISTOGRAM UPDATE
----
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
--
-- when STATE_UPDATE_HISTOGRAM =>
-- --! update histogram
-- if update_histo_done = '1' then
-- update_histo_en <= '0';
-- px <= px + 1;
-- state <= STATE_CHECK_FINISHED;
-- end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 6: MORE PIXEL?
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
-- when STATE_CHECK_FINISHED =>
-- --! checks if more pixel have to be loaded
-- if (px > x2 and y2 <= py) then
-- -- finished
-- normalize_histo_en <= '1';
-- state <= STATE_NORMALIZE_HISTOGRAM;
-- -- CHANGE CHANGE CHANGE
-- --copy_histo_en <= '1';
-- --state <= STATE_COPY_HISTOGRAM;
-- -- END OF CHANGE CHANGE CHANGE
-- elsif (px > x2 and py < y2) then
-- -- next row
-- px <= x1;
-- py <= py + 1;
-- state <= STATE_GET_PIXEL;
-- get_pixel_en <= '1';
-- else
-- -- default: next pixel
-- state <= STATE_GET_PIXEL;
-- get_pixel_en <= '1';
-- end if;
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
----
---- STEP 7: NORMALIZE HISTOGRAM
----
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
when STATE_NORMALIZE_HISTOGRAM =>
--! normalize histogram
if (normalize_histo_done = '1') then
normalize_histo_en <= '0';
copy_histo_en <= '1';
state <= STATE_COPY_HISTOGRAM;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 8: WRITE HISTOGRAM TO LOCAL RAM
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_COPY_HISTOGRAM =>
--! normalize histogram
if (copy_histo_done = '1') then
copy_histo_en <= '0';
state <= STATE_FINISH;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 9: HISTOGRAM CALCULATION FINISHED; WAIT FOR NEW_PARTICLE
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_FINISH =>
--! write finished signal
finished <= '1';
if (new_particle = '1') then
state <= STATE_INIT;
end if;
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
afb6ee29cc389ba244754cf29019fe25
| 0.474693 | 3.536959 | false | false | false | false |
bzero/freezing-spice
|
tests/compare_tb.vhd
| 2 | 5,077 |
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.common.all;
use work.decode_pkg.all;
entity compare_tb is
end entity compare_tb;
architecture test of compare_tb is
signal branch_type : branch_type_t;
signal op1 : word;
signal op2 : word;
signal compare_result : std_logic;
begin -- architecture test
uut : entity work.compare_unit(behavioral)
port map (
branch_type => branch_type,
op1 => op1,
op2 => op2,
compare_result => compare_result);
process
begin
----------------------------------------------------------------
-- BEQ
----------------------------------------------------------------
println("BEQ");
branch_type <= BEQ;
op1 <= "00010001000100010001000100010001";
op2 <= "00010001000100010001000100010001";
wait for 1 ns;
assert compare_result = '1' report "Invalid BEQ" severity error;
op2 <= "00010001000100010001000100010000";
wait for 1 ns;
assert compare_result = '0' report "Invalid BEQ" severity error;
----------------------------------------------------------------
-- BNE
----------------------------------------------------------------
println("BNE");
branch_type <= BNE;
wait for 1 ns;
assert compare_result = '1' report "Invalid BNE" severity error;
op2 <= "00010001000100010001000100010001";
wait for 1 ns;
assert compare_result = '0' report "Invalid BNE" severity error;
----------------------------------------------------------------
-- BLT
----------------------------------------------------------------
println("BLT");
branch_type <= BLT;
op1 <= "00000000000000000000000000000001";
op2 <= "00000000000000000000000000000000";
wait for 1 ns;
assert compare_result = '0' report "Invalid BLT" severity error;
op1 <= "00000000000000000000000000000010";
wait for 1 ns;
assert compare_result = '0' report "Invalid BLT" severity error;
op2 <= "01111111111111111111111111111111";
wait for 1 ns;
assert compare_result = '1' report "Invalid BLT" severity error;
----------------------------------------------------------------
-- BGE
----------------------------------------------------------------
println("BGE");
branch_type <= BGE;
wait for 1 ns;
assert compare_result = '0' report "Invalid BGE" severity error;
op1 <= "00000000000000000000000000000010";
op2 <= "00000000000000000000000000000010";
wait for 1 ns;
assert compare_result = '1' report "Invalid BGE" severity error;
op1 <= "11111111111111111111111111111111";
wait for 1 ns;
assert compare_result = '0' report "Invalid BGE" severity error;
op2 <= "11111111111111111111111111111110";
wait for 1 ns;
assert compare_result = '1' report "Invalid BGE" severity error;
----------------------------------------------------------------
-- BLTU
----------------------------------------------------------------
println("BLTU");
branch_type <= BLTU;
wait for 1 ns;
assert compare_result = '0' report "Invalid BLTU" severity error;
op1 <= "11111111111111111111111111111100";
wait for 1 ns;
assert compare_result = '1' report "Invalid BLTU" severity error;
op2 <= "11111111111111111111111111111100";
wait for 1 ns;
assert compare_result = '0' report "Invalid BLTU" severity error;
----------------------------------------------------------------
-- BGEU
----------------------------------------------------------------
println("BGEU");
branch_type <= BGEU;
wait for 1 ns;
assert compare_result = '1' report "Invalid BGEU" severity error;
op1 <= "00000000000000000000000000000000";
op2 <= "00000000000000000000000000000000";
wait for 1 ns;
assert compare_result = '1' report "Invalid BGEU" severity error;
op1 <= "00000000000000000000000000000001";
wait for 1 ns;
assert compare_result = '1' report "Invalid BGEU" severity error;
op1 <= "11111111111111111111111111111111";
op2 <= "11111111111111111111111111111110";
wait for 1 ns;
assert compare_result = '1' report "Invalid BGEU" severity error;
----------------------------------------------------------------
println("Simulation complete");
----------------------------------------------------------------
wait;
end process;
end architecture test;
|
bsd-3-clause
|
f13d028426c9223c7e5de37921d38294
| 0.455584 | 5.924154 | false | false | false | false |
luebbers/reconos
|
tests/benchmarks/semaphore/hw/src/hwt_semaphore_wait.vhd
| 1 | 9,388 |
--
-- hwt_semaphore_wait.vhd: measure time for semaphore_wait() operation
--
-- This HW thread measures the time it takes to execute a semaphore_wait()
-- operation from hardware.
-- To avoid side effects caused by activity of the delegate after returnung
-- from a sem_wait() call, this thread waits a defined number of clock
-- cycles before and after calling reconos_sem_wait() before exiting the thread
-- This number can be configured using the init_data value. A typical value is
-- 100000, which is equivalent to a millisecond.
--
-- This HW thread uses the dcr_timebase core to do consistent and synchronized
-- measurements of elapsed bus clock cycles.
--
-- Author Enno Luebbers <[email protected]>
-- Date 11.02.2008
--
-- For detailed documentation of the functions, see the associated header
-- file or the documentation (if such a header exists).
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group
--
-- (C) Copyright University of Paderborn 2007. Permission to copy,
-- use, modify, sell and distribute this software is granted provided
-- this copyright notice appears in all copies. This software is
-- provided "as is" without express or implied warranty, and with no
-- claim as to its suitability for any purpose.
--
---------------------------------------------------------------------------
-- Major Changes:
--
-- 11.02.2008 Enno Luebbers File created
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.all;
entity hwt_semaphore_wait is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector( 0 to C_BURST_AWIDTH-1 );
o_RAMData : out std_logic_vector( 0 to C_BURST_DWIDTH-1 );
i_RAMData : in std_logic_vector( 0 to C_BURST_DWIDTH-1 );
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- time base
i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end entity;
architecture Behavioral of hwt_semaphore_wait is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
constant C_SEMAPHORE : std_logic_vector(31 downto 0) := X"00000000";
constant C_MBOX_RESULT : std_logic_vector(31 downto 0) := X"00000001";
type t_state is ( STATE_INIT, -- get initial data (delay in clocks)
STATE_WAIT_BEFORE, -- wait before measuring
STATE_WAIT_SEM, -- wait for semaphore
STATE_MEASURE, -- measure elapsed time
STATE_WAIT_AFTER, -- wait after measuring
STATE_PUT_RESULT_START, -- post elapsed time to software mbox
STATE_PUT_RESULT_STOP,
STATE_EXIT); -- exit
signal state : t_state;
signal counter : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal reset_counter : std_logic := '1';
begin
state_proc: process( clk, reset )
variable delay : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable result_start : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable result_stop : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable retval : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable done : boolean := false;
variable success : boolean := false;
begin
if reset = '1' then
reconos_reset( o_osif, i_osif );
state <= STATE_INIT;
reset_counter <= '1';
result_start := (others => '0');
result_stop := (others => '0');
retval := (others => '0');
elsif rising_edge( clk ) then
reconos_begin( o_osif, i_osif );
if reconos_ready( i_osif ) then
case state is
when STATE_INIT =>
reconos_get_init_data(done, o_osif, i_osif, delay);
if done then
reset_counter <= '1';
state <= STATE_WAIT_BEFORE;
end if;
when STATE_WAIT_BEFORE =>
reset_counter <= '0';
if counter >= delay then
reset_counter <= '1';
result_start := i_timeBase;
state <= STATE_WAIT_SEM;
end if;
when STATE_WAIT_SEM =>
reconos_sem_wait(o_osif,i_osif,C_SEMAPHORE);
state <= STATE_MEASURE;
when STATE_MEASURE =>
result_stop := i_timeBase;
state <= STATE_WAIT_AFTER;
when STATE_WAIT_AFTER =>
reset_counter <= '0';
if counter >= delay then
reset_counter <= '1';
state <= STATE_PUT_RESULT_START;
end if;
when STATE_PUT_RESULT_START =>
reconos_mbox_put(done,
success,
o_osif,
i_osif,
C_MBOX_RESULT,
result_start);
if done then
if success then
state <= STATE_PUT_RESULT_STOP;
else
retval := X"0000_0001"; -- first mbox_put failed
state <= STATE_EXIT;
end if;
end if;
when STATE_PUT_RESULT_STOP =>
reconos_mbox_put(done,
success,
o_osif,
i_osif,
C_MBOX_RESULT,
result_stop);
if done then
if success then
retval := X"0000_0000"; -- all is well
state <= STATE_EXIT;
else
retval := X"0000_0002"; -- second mbox_put failed
state <= STATE_EXIT;
end if;
end if;
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, retval);
end case;
end if;
end if;
end process;
--
-- counter process to wait cycles
--
counter_proc : process(clk, reset)
begin
if reset = '1' then
counter <= (others => '0');
elsif rising_edge(clk) then
if reset_counter = '1' then
counter <= (others => '0');
else
counter <= counter + 1;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
4d025890dafefd1661c65699de6cf646
| 0.391138 | 5.689697 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_fa4_test3.vhd
| 4 | 2,057 |
-- In this test, we declare a component in the "gates" package
-- and show that it can be referenced within the package namespace.
library ieee;
use ieee.numeric_bit.all;
package gates is
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit);
end component fa1;
end package gates;
-- Declare and implement a 4-bit full-adder that uses the
-- 1-bit full-adder described above.
entity fa4 is
port (va_i, vb_i: in bit_vector (3 downto 0);
c_i: in bit;
vs_o: out bit_vector (3 downto 0);
c_o: out bit
);
end entity fa4;
architecture fa4_rtl of fa4 is
use work.gates.fa1;
-- internal carry signals propagation
signal c_int: bit_vector (4 downto 0);
begin
-- carry in
c_int(0) <= c_i;
-- slice 0
s0: fa1 port map (c_i => c_int(0),
a_i => va_i(0),
b_i => vb_i(0),
s_o => vs_o(0),
c_o => c_int(1)
);
-- slice 1
s1: fa1 port map (c_i => c_int(1),
a_i => va_i(1),
b_i => vb_i(1),
s_o => vs_o(1),
c_o => c_int(2)
);
-- slice 2
s2: fa1 port map (c_i => c_int(2),
a_i => va_i(2),
b_i => vb_i(2),
s_o => vs_o(2),
c_o => c_int(3)
);
-- slice 3
s3: fa1 port map (c_i => c_int(3),
a_i => va_i(3),
b_i => vb_i(3),
s_o => vs_o(3),
c_o => c_int(4)
);
-- carry out
c_o <= c_int(4);
end architecture fa4_rtl;
-- Declare a 1-bit full-adder.
entity fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit
);
end entity fa1;
architecture fa1_rtl of fa1 is
begin
s_o <= a_i xor b_i xor c_i;
c_o <= (a_i and b_i) or (c_i and (a_i xor b_i));
end architecture fa1_rtl;
|
gpl-2.0
|
5572544f57672f7ecfec2e90c5808dba
| 0.436072 | 3.065574 | false | false | false | false |
luebbers/reconos
|
core/pcores/tlb_arbiter_v2_01_a/hdl/vhdl/tlb_arbiter.vhd
| 1 | 7,083 |
------------------------------------------------------------------------------
-- TLB arbiter implementation
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library tlb_arbiter_v2_01_a;
use tlb_arbiter_v2_01_a.all;
entity tlb_arbiter is
generic
(
C_TLBARB_NUM_PORTS : integer := 2;
C_TAG_WIDTH : integer := 20;
C_DATA_WIDTH : integer := 21
);
port
(
sys_clk : in std_logic;
sys_reset : in std_logic;
-- TLB client A
i_tag_a : in std_logic_vector(C_TAG_WIDTH - 1 downto 0);
i_data_a : in std_logic_vector(C_DATA_WIDTH - 1 downto 0);
o_data_a : out std_logic_vector(C_DATA_WIDTH - 1 downto 0);
i_request_a : in std_logic;
i_we_a : in std_logic;
o_match_a : out std_logic;
o_busy_a : out std_logic;
-- TLB client B
i_tag_b : in std_logic_vector(C_TAG_WIDTH - 1 downto 0);
i_data_b : in std_logic_vector(C_DATA_WIDTH - 1 downto 0);
o_data_b : out std_logic_vector(C_DATA_WIDTH - 1 downto 0);
i_request_b : in std_logic;
i_we_b : in std_logic;
o_match_b : out std_logic;
o_busy_b : out std_logic;
-- TLB client C
i_tag_c : in std_logic_vector(C_TAG_WIDTH - 1 downto 0);
i_data_c : in std_logic_vector(C_DATA_WIDTH - 1 downto 0);
o_data_c : out std_logic_vector(C_DATA_WIDTH - 1 downto 0);
i_request_c : in std_logic;
i_we_c : in std_logic;
o_match_c : out std_logic;
o_busy_c : out std_logic;
-- TLB client D
i_tag_d : in std_logic_vector(C_TAG_WIDTH - 1 downto 0);
i_data_d : in std_logic_vector(C_DATA_WIDTH - 1 downto 0);
o_data_d : out std_logic_vector(C_DATA_WIDTH - 1 downto 0);
i_request_d : in std_logic;
i_we_d : in std_logic;
o_match_d : out std_logic;
o_busy_d : out std_logic;
-- TLB
o_tlb_tag : out std_logic_vector(C_TAG_WIDTH - 1 downto 0);
i_tlb_data : in std_logic_vector(C_DATA_WIDTH - 1 downto 0);
o_tlb_data : out std_logic_vector(C_DATA_WIDTH - 1 downto 0);
i_tlb_match : in std_logic;
o_tlb_we : out std_logic;
i_tlb_busy : in std_logic
);
end entity;
architecture imp of tlb_arbiter is
signal active : std_logic;
signal counter : std_logic_vector(1 downto 0);
signal busy_a : std_logic;
signal busy_b : std_logic;
signal busy_c : std_logic;
signal busy_d : std_logic;
begin
o_data_a <= i_tlb_data;
o_data_b <= i_tlb_data;
o_data_c <= i_tlb_data;
o_data_d <= i_tlb_data;
o_match_a <= i_tlb_match;
o_match_b <= i_tlb_match;
o_match_c <= i_tlb_match;
o_match_d <= i_tlb_match;
-- active <= busy_a = '0' or busy_b = '0';
active <= not (busy_a and busy_b and busy_c and busy_d);
handle_request : process(sys_clk,sys_reset)
variable req_a : std_logic;
variable req_b : std_logic;
variable req_c : std_logic;
variable req_d : std_logic;
begin
if sys_reset = '1' then
busy_a <= '1';
busy_b <= '1';
busy_c <= '1';
busy_d <= '1';
counter <= (others => '0');
elsif rising_edge(sys_clk) then
req_a := i_request_a;
if C_TLBARB_NUM_PORTS > 1 then req_b := i_request_b; else req_b := '0'; end if;
if C_TLBARB_NUM_PORTS > 2 then req_c := i_request_c; else req_c := '0'; end if;
if C_TLBARB_NUM_PORTS > 3 then req_d := i_request_d; else req_d := '0'; end if;
if active = '1' then -- wait for end of request
if busy_a = '0' and req_a = '0' then busy_a <= '1'; end if;
if busy_b = '0' and req_b = '0' then busy_b <= '1'; end if;
if busy_c = '0' and req_c = '0' then busy_c <= '1'; end if;
if busy_d = '0' and req_d = '0' then busy_d <= '1'; end if;
else -- check incoming requests
if (req_a = '1' or req_b = '1') and (req_c = '1' or req_d = '1') then
if counter(1) = '0' then req_c := '0'; req_d := '0'; end if;
if counter(1) = '1' then req_a := '0'; req_b := '0'; end if;
end if;
if (req_a = '1' or req_c = '1') and (req_b = '1' or req_d = '1') then
if counter(0) = '0' then req_b := '0'; req_d := '0'; end if;
if counter(1) = '0' then req_a := '0'; req_c := '0'; end if;
end if;
busy_a <= not req_a;
busy_b <= not req_b;
busy_c <= not req_c;
busy_d <= not req_d;
counter <= counter + 1;
--if i_request_a = '1' and i_request_b = '1' then
-- if counter = '0' then busy_a <= '0'; end if;
-- if counter = '1' then busy_b <= '0'; end if;
-- counter <= not counter; -- increment counter
--elsif i_request_a = '1' and i_request_b = '0' then
-- busy_a <= '0';
--elsif i_request_a = '0' and i_request_b = '1' then
-- busy_b <= '0';
--end if;
end if;
end if;
end process;
tlb_mux : process(busy_a, busy_b, i_tag_a, i_tag_b, i_data_a, i_data_b, i_we_a, i_we_b, i_tlb_busy)
begin
o_busy_a <= '1';
o_busy_b <= '1';
o_busy_c <= '1';
o_busy_d <= '1';
if busy_a = '0' then
o_tlb_tag <= i_tag_a;
o_tlb_data <= i_data_a;
o_tlb_we <= i_we_a;
o_busy_a <= i_tlb_busy;
elsif busy_b = '0' then
o_tlb_tag <= i_tag_b;
o_tlb_data <= i_data_b;
o_tlb_we <= i_we_b;
o_busy_b <= i_tlb_busy;
elsif busy_c = '0' then
o_tlb_tag <= i_tag_c;
o_tlb_data <= i_data_c;
o_tlb_we <= i_we_c;
o_busy_c <= i_tlb_busy;
elsif busy_d = '0' then
o_tlb_tag <= i_tag_d;
o_tlb_data <= i_data_d;
o_tlb_we <= i_we_d;
o_busy_d <= i_tlb_busy;
else
o_tlb_tag <= (others => '0');
o_tlb_data <= (others => '0');
o_tlb_we <= '0';
end if;
end process;
end architecture;
|
gpl-3.0
|
738db6e15891c96d5d1efc340dee4f32
| 0.430044 | 3.121639 | false | false | false | false |
luebbers/reconos
|
support/pcores/message_manager_v1_00_a/hdl/vhdl/fast_queue.vhd
| 1 | 8,364 |
-- *************************************************************************
-- File: queue.vhd
-- Purpose: Implements a queue (FIFO) usiing inferred BRAM.
-- Author: Jason Agron
-- *************************************************************************
-- *************************************************************************
-- Library declarations
-- *************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.all;
library Unisim;
use Unisim.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity fast_queue is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
clk : in std_logic;
rst : in std_logic;
add_busy : out std_logic;
remove_busy : out std_logic;
add : in std_logic;
remove : in std_logic;
entryToAdd : in std_logic_vector(0 to DATA_BITS-1);
head : out std_logic_vector(0 to DATA_BITS-1);
headValid : out std_logic;
full : out std_logic;
empty : out std_logic
);
end entity fast_queue;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of fast_queue is
-- Declare the component for the inferred BRAM
component infer_bram_dual_port is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1);
CLKB : in std_logic;
ENB : in std_logic;
ADDRB : in std_logic_vector(0 to ADDRESS_BITS - 1);
DOB : out std_logic_vector(0 to DATA_BITS - 1)
);
end component infer_bram_dual_port;
-- Internal signals to hook up to output ports
signal empty_int, full_int, headValid_int : std_logic;
-- Signals to hook up to the inferred BRAM
signal ena, enb, wea : std_logic;
signal addra, addrb : std_logic_vector(0 to ADDRESS_BITS-1);
signal dia, doa, dob : std_logic_vector(0 to DATA_BITS-1);
-- ENQ FSM registers
signal tailPtr, tailPtr_next, nextFreePtr, nextFreePtr_next : std_logic_vector(0 to ADDRESS_BITS-1);
-- DEQ FSM registers
signal headPtr, headPtr_next : std_logic_vector(0 to ADDRESS_BITS-1);
signal deq_busy, deq_busy_next : std_logic;
signal enq_busy, enq_busy_next : std_logic;
-- Enqueue state enumeration
type enq_state_type is
(
reset,
idle,
finishAdd
);
signal currentEnqState, nextEnqState : enq_state_type := idle;
-- Dequeue state enumeration
type deq_state_type is
(
reset,
idle,
finishRemove
);
signal currentDeqState, nextDeqState : deq_state_type := idle;
-- *********************************************************
-- *********************************************************
-- *********************************************************
begin
-- Connect up status signals to output ports
empty <= empty_int;
full <= full_int;
headValid <= headValid_int;
add_busy <= enq_busy;
remove_busy <= deq_busy;
-- Instantiation of the BRAM block to hold the queue data structure
queue_BRAM : infer_bram_dual_port
generic map (
ADDRESS_BITS => ADDRESS_BITS,
DATA_BITS => DATA_BITS
)
port map (
CLKA => clk,
ENA => ena,
WEA => wea,
ADDRA => addra,
DIA => dia,
DOA => doa,
CLKB => clk,
ENB => enb,
ADDRB => addrb,
DOB => dob
);
-- Connect head output to data output B of RAM
head <= dob;
-- Status Process
-- Calculate FULL/EMPTY status
STATUS : process
--(clk, rst, tailPtr, headPtr, nextFreePtr, deq_busy) is
(clk, rst, tailPtr, headPtr, nextFreePtr, deq_busy_next) is
begin
if (clk'event and clk = '1') then
if (rst = '1') then
full_int <= '0';
empty_int <= '1';
else
-- Check "full" condition
if (nextFreePtr = headPtr) then
full_int <= '1';
else
full_int <= '0';
end if;
-- Check "empty" condition
-- * headValid = (not empty) and (not deq_busy)
if (tailPtr = headPtr) then
empty_int <= '1';
--headValid_int <= '0' and (not deq_busy);
headValid_int <= '0' and (not deq_busy_next);
else
empty_int <= '0';
headValid_int <= '1' and (not deq_busy_next);
--headValid_int <= '1' and (not deq_busy);
end if;
end if;
end if;
end process STATUS;
-- Syncrhonous ENQ FSM Process
-- Control state transitions of ENQ FSM
SYNCH_ENQ : process
(clk, rst, nextEnqState) is
begin
if (clk'event and clk = '1') then
if (rst = '1') then
-- Reset state
currentEnqState <= reset;
tailPtr <= (others => '0');
-- nextFreePtr <= (others => '0');
nextFreePtr <= conv_std_logic_vector(1,ADDRESS_BITS);
enq_busy <= '0';
else
-- Transition state
currentEnqState <= nextEnqState;
tailPtr <= tailPtr_next;
nextFreePtr <= nextFreePtr_next;
enq_busy <= enq_busy_next;
end if;
end if;
end process SYNCH_ENQ;
-- Combinational ENQ FSM Process
-- State machine logic for ENQ FSM
COMB_ENQ : process
(currentEnqState, add, entryToAdd, tailPtr, full_int) is
begin
-- Setup default values for FSM signals
nextEnqState <= currentEnqState;
tailPtr_next <= tailPtr;
nextFreePtr_next <= tailPtr + 1;
enq_busy_next <= '0';
addra <= tailPtr;
wea <= '0';
ena <= '0';
dia <= entryToAdd;
-- FSM case statement
case (currentEnqState) is
when reset =>
-- Reset state
tailPtr_next <= (others => '0');
--nextFreePtr <= (others => '0');
nextFreePtr_next <= conv_std_logic_vector(1,ADDRESS_BITS);
-- Move to idle state
nextEnqState <= idle;
when idle =>
-- If request to add and queue isn't full
if (add = '1' and full_int ='0') then
-- Write entry to BRAM
addra <= tailPtr;
wea <= '1';
ena <= '1';
dia <= entryToAdd;
-- Increment tailPtr
tailPtr_next <= tailPtr + 1;
enq_busy_next <= '1';
nextEnqState <= finishAdd;
-- Otherwise, stay in the idle state
else
enq_busy_next <= '0';
nextEnqState <= idle;
end if;
when finishAdd =>
-- Used for delay
enq_busy_next <= '0';
nextEnqState <= idle;
when others =>
nextEnqState <= reset;
end case;
end process COMB_ENQ;
-- Syncrhonous DEQ FSM Process
-- Control state transitions of DEQ FSM
SYNCH_DEQ : process
(clk, rst, nextDeqState) is
begin
if (clk'event and clk = '1') then
if (rst = '1') then
-- Reset state
currentDeqState <= reset;
headPtr <= (others => '0');
deq_busy <= '0';
else
-- Transition state
currentDeqState <= nextDeqState;
headPtr <= headPtr_next;
deq_busy <= deq_busy_next;
end if;
end if;
end process SYNCH_DEQ;
-- Combinational DEQ FSM Process
-- State machine logic for DEQ FSM
COMB_DEQ : process
(currentDeqState, remove, headPtr, headValid_int, empty_int) is
begin
-- Setup default values for FSM signals
nextDeqState <= currentDeqState;
headPtr_next <= headPtr;
deq_busy_next <= '0';
addrb <= headPtr;
enb <= '1';
-- FSM case statement
case (currentDeqState) is
when reset =>
-- Reset state
headPtr_next <= (others => '0');
deq_busy_next <= '0';
-- Move to idle state
nextDeqState <= idle;
when idle =>
-- If request to remove and queue isn't empty
if (remove = '1' and empty_int = '0') then
deq_busy_next <= '1';
headPtr_next <= headPtr + 1;
nextDeqState <= finishRemove;
-- Otherwise stay in idle state
else
deq_busy_next <= '0';
nextDeqState <= idle;
end if;
when finishRemove =>
-- Used for delay
deq_busy_next <= '0';
nextDeqState <= idle;
when others =>
nextDeqState <= reset;
end case;
end process COMB_DEQ;
end architecture implementation;
|
gpl-3.0
|
2fe137fe884c0dae30d09ef732d5dd58
| 0.556074 | 3.395859 | false | false | false | false |
iti-luebeck/RTeasy1
|
src/main/resources/vhdltmpl/cu_architecture_body.vhd
| 3 | 872 |
-- instantiate condition buffer register
condbuf_register: dff_reg
GENERIC MAP(width => %%I_WIDTH, triggering_edge => '%%EDGE')
PORT MAP(CLK => CLK, RESET => RESET, INPUT => I, OUTPUT => I_BUFFERED);
-- instantiate state register
state_register: dff_reg
GENERIC MAP(width => %%STATEWIDTH, triggering_edge => '%%EDGE')
PORT MAP(CLK => CLK, RESET => RESET, INPUT => NEXTSTATE, OUTPUT => STATE);
-- instantiate circuit for state transition function
statetrans: %%COMPONENT_NAME_cu_statetrans_net
PORT MAP(I => I_BUFFERED, STATE => STATE, NEXTSTATE => NEXTSTATE);
-- instantiate circuit for output function driving control signals
output: %%COMPONENT_NAME_cu_output_net
PORT MAP(I => I_BUFFERED, STATE => STATE, C => C_SIG);
-- only drive control signals when CLK='0' to avoid driving hazards to
-- operation unit
C <= C_SIG WHEN CLK='0' ELSE (OTHERS => '0');
|
bsd-3-clause
|
890648179471442f808d377d28ce26c7
| 0.697248 | 3.774892 | false | false | false | false |
luebbers/reconos
|
demos/sort_demo_inv_pr/hw/sort8kinv/bubble_sorter.vhd
| 1 | 6,023 |
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end bubble_sorter;
architecture Behavioral of bubble_sorter is
type state_t is (STATE_IDLE, STATE_LOAD_A, STATE_LOAD_B, STATE_LOAD_WAIT_A, STATE_LOAD_WAIT_B, STATE_COMPARE, STATE_WRITE, STATE_LOAD_NEXT, STATE_START_OVER);
signal state : state_t := STATE_IDLE;
signal ptr : natural range 0 to G_LEN-1; --std_logic_vector(0 to C_AWIDTH-1);
signal ptr_max : natural range 0 to G_LEN-1;
signal a : std_logic_vector(0 to G_DWIDTH-1);
signal b : std_logic_vector(0 to G_DWIDTH-1);
signal low : std_logic_vector(0 to G_DWIDTH-1);
signal high : std_logic_vector(0 to G_DWIDTH-1);
signal swap : boolean;
signal swapped : boolean;
begin
-- set RAM address
o_RAMAddr <= std_logic_vector(TO_UNSIGNED(ptr, G_AWIDTH));
-- concurrent signal assignments
swap <= true when a < b else false; -- should a and b be swapped?
low <= b when swap else a; -- lower value of a and b
high <= a when swap else b; -- higher value of a and b
-- sorting state machine
sort_proc : process(clk, reset)
variable ptr_max_new : natural range 0 to G_LEN-1; -- number of items left to sort
begin
if reset = '1' then
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
done <= '0';
swapped <= false;
a <= (others => '0');
b <= (others => '0');
elsif rising_edge(clk) then
o_RAMWE <= '0';
o_RAMData <= (others => '0');
case state is
when STATE_IDLE =>
done <= '0';
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
swapped <= false;
-- start sorting on 'start' signal
if start = '1' then
state <= STATE_LOAD_WAIT_A;
end if;
-- increase address (for B), wait for A to appear on RAM outputs
when STATE_LOAD_WAIT_A =>
ptr <= ptr + 1;
state <= STATE_LOAD_A;
-- wait for B to appear on RAM outputs
when STATE_LOAD_WAIT_B =>
state <= STATE_LOAD_B;
-- read A value from RAM
when STATE_LOAD_A =>
a <= i_RAMData;
state <= STATE_LOAD_B;
-- read B value from RAM
when STATE_LOAD_B =>
b <= i_RAMData;
state <= STATE_COMPARE;
-- compare A and B and act accordingly
when STATE_COMPARE =>
-- if A is higher than B
if swap then
-- write swapped values back
ptr <= ptr - 1; -- back to writing
o_RAMData <= low; -- write low value
o_RAMWE <= '1';
swapped <= true;
state <= STATE_WRITE;
else
if ptr < ptr_max then
-- generate addres for next value for b
a <= b;
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
else
-- if we swapped something then
if swapped then
-- start over
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
end if;
-- write high value
when STATE_WRITE =>
ptr_max_new := ptr; -- save location of last swapped value
ptr <= ptr + 1;
o_RAMData <= high;
o_RAMWE <= '1';
if ptr < ptr_max-1 then
state <= STATE_LOAD_NEXT;
else
-- if we swapped something then
if swapped then
-- start over
state <= STATE_START_OVER;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
-- load next B value
when STATE_LOAD_NEXT =>
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
-- start from beginning
when STATE_START_OVER =>
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
when others =>
state <= STATE_IDLE;
end case;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
2c15bbfe04c952a62941d61af2d2d074
| 0.497759 | 3.890827 | false | false | false | false |
luebbers/reconos
|
demos/particle_filter_framework/hw/src/user_processes/uf_resampling.vhd
| 1 | 13,315 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : R E S A M P L I N G
--
-- In many cases, this function does not have to be changed.
-- Only if you want/need to change/adjust the resampling algorithm
-- you can change it here.
--
-- Here the Residual Systematic Resampling Algorithm is used.
-- It is not easy to change to a complete other resampling algorithm,
-- because the framework is adjusted to use a algorithm, which
-- only uses one cycle of iterations and so without any correction cycle.
--
-- Some basic information about the resampling user function:
--
-- The particle weights are loaded into the local RAM by the Framework
-- The first 63 * 128 bytes (of 64 * 128 bytes) are filled with
-- all the particle weights needed. There will not be any space
-- between the particle weights.
--
-- The last 128 bytes are used for the resampling.
-- The user has to store two values for every particle.
-- 1. the index of the particle (as integer)
-- 2. the replication factor of the particle (as integer)
-- The ordering of this two values must not be changed,
-- because it is used later for the sampling step.
--
-- The two integer values (also known as index_type) are written
-- into the last 128 byte. Since two integer values need 8 bytes,
-- information about 16 particles can be written into the last 128 bytes
-- of the local ram before they have to be written by the Framework.
--
-- The outgoing signal write_burst has to be '1', if the the indexes
-- and replication factors should be written into the Main Memory.
-- This should only happen, if the information about 16
-- particles is resampled or the last particle has been resampled.
--
-- The incoming signal write_burst_done is equal to '1', if the
-- Framework has written the information to the Main Memory
--
-- If resampling is finished the outgoing signal finish has to be set to '1'.
-- A new run of the resampling will be started if the next particles are
-- loaded into local RAM. This is the case when the incoming signal
-- particles_loaded is equal to '1'.
--
------------------------------------------------------------------------------------
entity uf_resampling is
generic (
C_TASK_BURST_AWIDTH : integer := 11;
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- additional incoming signals
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- start signal for the resampling user process
particles_loaded : in std_logic;
-- number of particles in local RAM
number_of_particles : in integer;
-- number of particles in total
number_of_particles_in_total : in integer;
-- index of first particles (the particles are sorted increasingly)
start_particle_index : in integer;
-- resampling function init
U_init : in integer;
-- address of the last 128 byte burst in local RAM
write_address : in std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
-- information if a write burst has been handled by the Framework
write_burst_done : in std_logic;
-- additional outgoing signals
-- this signal has to be set to '1', if the Framework should write
-- the last burst from local RAM into Maim Memory
write_burst : out std_logic;
-- write burst done acknowledgement
write_burst_done_ack : out std_logic;
-- number of currently written particles
written_values : out integer;
-- if every particle is resampled, this signal has to be set to '1'
finished : out std_logic
);
end uf_resampling;
architecture Behavioral of uf_resampling is
-- GRANULARITY
constant GRANULARITY :integer := 16384;
-- local RAM read/write address
signal local_ram_read_address : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
signal local_ram_write_address : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- particle counter
signal counter : integer := 0;
-- particle counter for allready resampled particles at all
signal counter_resampled_particles : integer := 0;
-- write counter (used bytes)
signal write_counter :integer := 0;
-- current particle weight
signal current_particle_weight : integer := 0;
-- signals needed for residual systematic resampling
signal temp : integer := 0;
signal fact : integer := 0; -- replication factor
signal U : integer := 0;
-- states
type t_state1 is (STATE_INIT,
STATE_LOAD_PARTICLE_1, STATE_LOAD_PARTICLE_2, STATE_LOAD_WEIGHT,
STATE_CALCULATE_REPLICATION_FACTOR_1, STATE_CALCULATE_REPLICATION_FACTOR_2,
STATE_CALCULATE_REPLICATION_FACTOR_3, STATE_CALCULATE_REPLICATION_FACTOR_4,
STATE_CALCULATE_REPLICATION_FACTOR_5, STATE_CALCULATE_REPLICATION_FACTOR_6,
STATE_WRITE_PARTICLE_INDEX, STATE_WRITE_PARTICLE_REPLICATION,
STATE_WRITE_BURST_DECISION, STATE_WRITE_BURST, STATE_WRITE_BURST_DONE_ACK,
STATE_WRITE_BURST_DONE_ACK_2, STATE_FINISH);
-- current state
signal state1 : t_state1 := STATE_INIT;
begin
-- burst ram interface is not used
-- o_RAMAddr <= (others => '0');
-- o_RAMData <= (others => '0');
-- o_RAMWE <= '0';
o_RAMClk <= clk;
state_proc : process(clk, reset)
begin
if (reset = '1') then
state1 <= STATE_INIT;
elsif rising_edge(clk) then
if init = '1' then
state1 <= STATE_INIT;
o_RAMData <= (others=>'0');
o_RAMWE <= '0';
o_RAMAddr <= (others => '0');
U <= U_init;
elsif enable = '1' then
case state1 is
when STATE_INIT =>
--! init data
local_ram_read_address <= (others => '0');
local_ram_write_address <= write_address;
counter_resampled_particles <= 0;
counter <= start_particle_index;
current_particle_weight <= 0;
temp <= 0;
fact <= 0;
--U <= U_init;
write_counter <= 0;
written_values <= 0;
write_burst <= '0';
finished <= '0';
o_RAMWE <= '0';
if (particles_loaded = '1') then
state1 <= STATE_LOAD_PARTICLE_1;
end if;
-- 0) INIT
--
-- i = 0; // current particle
-- j = 0; // current replication factor
-- k = 0; // current number of cloned particles
-- finished = 0;
--
--
-- 1) LOAD_PARTICLE_1/2, LOAD_WEIGHT
--
-- load weight of i-th particle from local memory
-- i ++;
--
--
-- 2) CALCULATE_REPLICATION_FACTOR_1-8
--
-- calculate replication factor
--
--
-- 3) WRITE_PARTICLE_INDEX, WRITE_PARTICLE_REPLICATION
--
-- write particle index + replicationfactor to local ram
--
--
-- 4) WRITE_BURST
--
-- write_burst = 1;
-- if (write_burst_done)
--
-- write_burst = 0;
-- go to step 4
--
--
-- 5) FINISHED
--
-- finished = 1;
-- if (particles_loaded)
-- go to step 0;
when STATE_LOAD_PARTICLE_1 =>
--! load a particle
write_burst <= '0';
if (number_of_particles <= counter_resampled_particles) then
state1 <= STATE_WRITE_BURST_DECISION;
else
o_RAMAddr <= local_ram_read_address;
state1 <= STATE_LOAD_PARTICLE_2;
end if;
when STATE_LOAD_PARTICLE_2 =>
--!needed because reading from local RAM needs two clock steps
state1 <= STATE_LOAD_WEIGHT;
when STATE_LOAD_WEIGHT =>
--! load particle weight
current_particle_weight <= TO_INTEGER(SIGNED(i_RAMData));
state1 <= STATE_CALCULATE_REPLICATION_FACTOR_1;
when STATE_CALCULATE_REPLICATION_FACTOR_1 =>
--! calculate replication factor (step 2/6)
temp <= current_particle_weight * number_of_particles_in_total;
state1 <= STATE_CALCULATE_REPLICATION_FACTOR_2;
when STATE_CALCULATE_REPLICATION_FACTOR_2 =>
--! calculate replication factor (step 2/6)
temp <= temp - U;
state1 <= STATE_CALCULATE_REPLICATION_FACTOR_3;
when STATE_CALCULATE_REPLICATION_FACTOR_3 =>
--! calculate replication factor (step 3/6)
fact <= temp + GRANULARITY;
state1 <= STATE_CALCULATE_REPLICATION_FACTOR_4;
when STATE_CALCULATE_REPLICATION_FACTOR_4 =>
--! calculate replication factor (step 4/6)
fact <= fact / GRANULARITY;
state1 <= STATE_CALCULATE_REPLICATION_FACTOR_5;
when STATE_CALCULATE_REPLICATION_FACTOR_5 =>
--! calculate replication factor (step 5/6)
U <= fact * GRANULARITY;
state1 <= STATE_CALCULATE_REPLICATION_FACTOR_6;
when STATE_CALCULATE_REPLICATION_FACTOR_6 =>
--! calculate replication factor (step 6/6)
U <= U - temp;
state1 <= STATE_WRITE_PARTICLE_INDEX;
-- todo: change back
--state1 <= STATE_WRITE_BURST_DECISION;
when STATE_WRITE_PARTICLE_INDEX =>
--! read particle from local ram
-- copy particle_size / 32 from local RAM to local RAM
o_RAMWE <= '1';
o_RAMAddr <= local_ram_write_address;
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(counter, C_TASK_BURST_DWIDTH));
local_ram_write_address <= local_ram_write_address + 1;
state1 <= STATE_WRITE_PARTICLE_REPLICATION;
when STATE_WRITE_PARTICLE_REPLICATION =>
--! needed because reading takes 2 clock steps
o_RAMWE <= '1';
o_RAMAddr <= local_ram_write_address;
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(fact, C_TASK_BURST_DWIDTH));
local_ram_write_address <= local_ram_write_address + 1;
write_counter <= write_counter + 1;
state1 <= STATE_WRITE_BURST_DECISION;
when STATE_WRITE_BURST_DECISION =>
--! write burst to main memory
o_RAMWE <= '0';
if (16 <= write_counter) then
-- write burst
state1 <= STATE_WRITE_BURST;
-- todo change back
--state1 <= STATE_WRITE_BURST_DECISION;
write_counter <= 0;
local_ram_write_address <= write_address;
written_values <= 16;
elsif (number_of_particles <= counter_resampled_particles and write_counter > 0) then
-- write burst
state1 <= STATE_WRITE_BURST;
--todo: changed back
--state1 <= STATE_WRITE_BURST_DECISION;
write_counter <= 0;
--write_burst <= '1';
written_values <= write_counter;
elsif (number_of_particles <= counter_resampled_particles) then
state1 <= STATE_FINISH;
else
-- get next particle
counter <= counter + 1;
counter_resampled_particles <= counter_resampled_particles + 1;
local_ram_read_address <= local_ram_read_address + 1;
state1 <= STATE_LOAD_PARTICLE_1;
end if;
when STATE_WRITE_BURST =>
--! write burst to main memory
--write_burst <= '1';
--written_values <= write_counter;
--if (rising_edge (write_burst_done)) then
write_burst <= '1';
write_burst_done_ack <= '0';
--change back
--write_counter <= 0;
if (write_burst_done = '1') then
write_burst <= '0';
state1 <= STATE_WRITE_BURST_DONE_ACK;
end if;
when STATE_WRITE_BURST_DONE_ACK =>
--! write burst to main memory
write_burst_done_ack <= '1';
write_counter <= 0;
write_burst <= '0';
if (write_burst_done = '0') then
state1 <= STATE_WRITE_BURST_DONE_ACK_2;
end if;
-- if (number_of_particles <= counter_resampled_particles) then
--
-- state1 <= STATE_FINISH;
-- else
-- --todo: changed for hopefully good
-- --state1 <= STATE_LOAD_PARTICLE_1;
-- state1 <= STATE_WRITE_BURST_DECISION;
-- end if;
when STATE_WRITE_BURST_DONE_ACK_2 =>
--! write burst to main memory
write_burst_done_ack <= '0';
if (number_of_particles <= counter_resampled_particles) then
state1 <= STATE_FINISH;
else
--todo: changed for hopefully good
--state1 <= STATE_LOAD_PARTICLE_1;
state1 <= STATE_WRITE_BURST_DECISION;
end if;
when STATE_FINISH =>
--! write finished signal
write_burst <= '0';
finished <= '1';
if (particles_loaded = '1') then
state1 <= STATE_INIT;
end if;
when others =>
state1 <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
81c30b599a5047780ae5e43b79f3e620
| 0.593316 | 3.880793 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/ac97_command_rom.vhd
| 7 | 3,893 |
-------------------------------------------------------------------------------
-- Filename: ac97_fifo.vhd
--
-- Description: This module provides a simple FIFO interface for the AC97
-- module and provides an asyncrhonous interface for a
-- higher level module that is not synchronous with the AC97
-- clock (Bit_Clk).
--
-- This module will handle all of the initial commands
-- for the AC97 interface.
--
-- This module provides a bus independent interface so the
-- module can be used for more than one bus interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ac97_core
-- ac97_timing
-- srl_fifo
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $$
-- Date: $$
--
-- History:
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
-- Command format V R AAAAAAA DDDDDDDD DDDDDDDD
-- V = Valid command (1 = valid, 0 = invalid)
-- R = Read (1=read, 0=write)
-- A = Address (7 bits)
-- D = Data (16 bits)
-- '1' & X"000000"; Write 0x0 to 0x0 (reset registers)
-- '1' & X"020808"; Write 0x808 to 0x2 (master volume 0db gain)
-- '1' & X"040808"; Write 0x808 to 0x4 (headphone vol)
-- '1' & X"0a8000"; Write 0x8000 to 0xa (mute PC beep)
-- '0' & X"180808"; Write 0x808 to 0x18 pcmoutvol (amp out line)
-- '1' & X"1a0404"; Write 0x404 to 0x1a record source (line in for left and right)
-- '1' & X"1c0008"; Write (0x1c,0x008); // record gain (8 steps of 1.5 dB = +12.0 dB)
entity ac97_command_rom is
generic (
COMMAND_0: std_logic_vector(24 downto 0) := '1' & X"000000";
COMMAND_1: std_logic_vector(24 downto 0) := '1' & X"020808";
COMMAND_2: std_logic_vector(24 downto 0) := '1' & X"040808";
COMMAND_3: std_logic_vector(24 downto 0) := '1' & X"0a8000";
COMMAND_4: std_logic_vector(24 downto 0) := '1' & X"180808";
COMMAND_5: std_logic_vector(24 downto 0) := '1' & X"1a0404";
COMMAND_6: std_logic_vector(24 downto 0) := '1' & X"1c0a0a";
COMMAND_7: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_8: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_9: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_A: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_B: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_C: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_D: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_E: std_logic_vector(24 downto 0) := '0' & X"000000";
COMMAND_F: std_logic_vector(24 downto 0) := '0' & X"000000"
);
port (
ClkIn : in std_logic;
ROMAddr : in std_logic_vector(3 downto 0);
ROMData : out std_logic_vector(24 downto 0)
);
end entity ac97_command_rom;
architecture IMP of ac97_command_rom is
type command_ram_type is array(15 downto 0) of std_logic_vector(24 downto 0);
constant command_rom : command_ram_type := (
COMMAND_F, COMMAND_E, COMMAND_D, COMMAND_C,
COMMAND_B, COMMAND_A, COMMAND_9, COMMAND_8,
COMMAND_7, COMMAND_6, COMMAND_5, COMMAND_4,
COMMAND_3, COMMAND_2, COMMAND_1, COMMAND_0
);
begin
-- ROM_STYLE
process (ClkIn)
begin
if ClkIn'event and CLkIn='1' then
ROMData <= command_rom(CONV_INTEGER(ROMAddr));
end if;
end process;
end architecture IMP;
|
gpl-3.0
|
5e35b91514e8a9360736ffcea6f1552c
| 0.535577 | 3.252297 | false | false | false | false |
makestuff/vhdl
|
dpimref/topLevel.vhd
| 1 | 5,709 |
--
-- Copyright (C) 2011 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TopLevel is
port(
-- Main 50MHz clock
clk : in std_logic;
-- Reset button (BTN0)
reset : in std_logic;
-- Host interface signals
eppDataBus : inout std_logic_vector(7 downto 0);
eppAddrStrobe : in std_logic;
eppDataStrobe : in std_logic;
eppReadNotWrite : in std_logic;
eppAck : out std_logic
);
end TopLevel;
architecture Behavioural of TopLevel is
type State is (
STATE_IDLE,
STATE_ADDR_WRITE_EXEC,
STATE_ADDR_WRITE_ACK,
STATE_DATA_WRITE_EXEC,
STATE_DATA_WRITE_ACK,
STATE_DATA_READ_EXEC,
STATE_DATA_READ_ACK
);
-- State and next-state
signal iThisState, iNextState : State;
-- Synchronised versions of asynchronous inputs
signal iSyncAddrStrobe : std_logic;
signal iSyncDataStrobe : std_logic;
signal iSyncReadNotWrite : std_logic;
-- Data to be mux'd back to host
signal iDataOutput : std_logic_vector(7 downto 0);
-- Registers
signal iThisRegAddr, iNextRegAddr : std_logic_vector(1 downto 0);
signal iThisAck, iNextAck : std_logic;
signal iThisR0, iNextR0 : std_logic_vector(7 downto 0);
signal iThisR1, iNextR1 : std_logic_vector(7 downto 0);
signal iThisR2, iNextR2 : std_logic_vector(7 downto 0);
signal iThisR3, iNextR3 : std_logic_vector(7 downto 0);
begin
-- Drive the outputs
eppAck <= iThisAck;
-- EPP operation
eppDataBus <=
iDataOutput when ( eppReadNotWrite = '1' ) else
"ZZZZZZZZ";
with ( iThisRegAddr ) select
iDataOutput <=
iThisR0 when "00",
iThisR1 when "01",
iThisR2 when "10",
iThisR3 when others;
-- Infer registers
process(clk, reset)
begin
if ( reset = '1' ) then
iThisState <= STATE_IDLE;
iThisRegAddr <= (others => '0');
iThisR0 <= (others => '0');
iThisR1 <= (others => '0');
iThisR2 <= (others => '0');
iThisR3 <= (others => '0');
iThisAck <= '0';
iSyncAddrStrobe <= '1';
iSyncDataStrobe <= '1';
iSyncReadNotWrite <= '1';
elsif ( clk'event and clk = '1' ) then
iThisState <= iNextState;
iThisRegAddr <= iNextRegAddr;
iThisR0 <= iNextR0;
iThisR1 <= iNextR1;
iThisR2 <= iNextR2;
iThisR3 <= iNextR3;
iThisAck <= iNextAck;
iSyncAddrStrobe <= eppAddrStrobe;
iSyncDataStrobe <= eppDataStrobe;
iSyncReadNotWrite <= eppReadNotWrite;
end if;
end process;
-- Next state logic
process(
eppDataBus, iThisState, iThisRegAddr,
iSyncAddrStrobe, iSyncDataStrobe, iSyncReadNotWrite,
iThisR0, iThisR1, iThisR2, iThisR3)
begin
iNextAck <= '0';
iNextState <= STATE_IDLE;
iNextRegAddr <= iThisRegAddr;
iNextR0 <= iThisR0;
iNextR1 <= iThisR1;
iNextR2 <= iThisR2;
iNextR3 <= iThisR3;
case iThisState is
when STATE_IDLE =>
if ( iSyncAddrStrobe = '0' ) then
-- Address can only be written, not read
if ( iSyncReadNotWrite = '0' ) then
iNextState <= STATE_ADDR_WRITE_EXEC;
end if;
elsif ( iSyncDataStrobe = '0' ) then
-- Register read or write
if ( iSyncReadNotWrite = '0' ) then
iNextState <= STATE_DATA_WRITE_EXEC;
else
iNextState <= STATE_DATA_READ_EXEC;
end if;
end if;
-- Write address register
when STATE_ADDR_WRITE_EXEC =>
iNextRegAddr <= eppDataBus(1 downto 0);
iNextState <= STATE_ADDR_WRITE_ACK;
iNextAck <= '0';
when STATE_ADDR_WRITE_ACK =>
if ( iSyncAddrStrobe = '0' ) then
iNextState <= STATE_ADDR_WRITE_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Write data register
when STATE_DATA_WRITE_EXEC =>
case iThisRegAddr is
when "00" =>
iNextR0 <= eppDataBus;
when "01" =>
iNextR1 <= eppDataBus;
when "10" =>
iNextR2 <= eppDataBus;
when others =>
iNextR3 <= eppDataBus;
end case;
iNextState <= STATE_DATA_WRITE_ACK;
iNextAck <= '1';
when STATE_DATA_WRITE_ACK =>
if ( iSyncDataStrobe = '0' ) then
iNextState <= STATE_DATA_WRITE_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Read data register
when STATE_DATA_READ_EXEC =>
iNextAck <= '1';
iNextState <= STATE_DATA_READ_ACK;
when STATE_DATA_READ_ACK =>
if ( iSyncDataStrobe = '0' ) then
iNextState <= STATE_DATA_READ_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Some unknown state
when others =>
iNextState <= STATE_IDLE;
end case;
end process;
end Behavioural;
|
gpl-3.0
|
d5ec1c2e243058f92ff0a9834690fdc0
| 0.595551 | 3.581556 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/work7b/bigcount.vhd
| 4 | 641 |
library ieee;
library uselib;
use ieee.std_logic_1164.all;
use uselib.work7.all;
entity bigcount is
port (clk, reset: in std_logic;
count: out std_logic_vector (24 downto 0)
);
end entity bigcount;
architecture bigcount_rtl of bigcount is
signal d, t, q, myreset: std_logic;
begin
d <= t xor q;
myreset <= reset or t;
f1: fdc port map (clk => clk, reset => reset, d => d, q => q);
tb: timebase port map (CLOCK => clk, RESET => myreset, ENABLE => '1', TICK => t, COUNT_VALUE => open );
counting: timebase port map (CLOCK => clk, RESET => reset, ENABLE => q, TICK => open, COUNT_VALUE => count );
end bigcount_rtl;
|
gpl-2.0
|
5109df297c7958a368d1b74305db3fc2
| 0.645866 | 3.11165 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/generic_simple_dpram.vhd
| 2 | 3,302 |
-------------------------------------------------------------------------------
-- Title : Parametrizable dual-port synchronous RAM (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_simple_dpram.vhd
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2013-03-04
-- Last update: 2013-10-30
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
-- Todo:
-- - loading initial contents from file
-- - add support for read-first/write-first address conflict resulution (only
-- supported by Xilinx in VHDL templates)
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-03-04 1.0 wterpstra Initial version: wrapper to generic_dpram
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.genram_pkg.all;
use work.memory_loader_pkg.all;
entity generic_simple_dpram is
generic (
-- standard parameters
g_data_width : natural := 32;
g_size : natural := 16384;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_dual_clock : boolean := true;
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
-- Port A
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
-- Port B
clkb_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_simple_dpram;
architecture syn of generic_simple_dpram is
begin
-- Works well enough until a Xilinx guru can optimize it.
true_dp : generic_dpram
generic map(
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_dual_clock => g_dual_clock)
port map(
rst_n_i => rst_n_i,
clka_i => clka_i,
bwea_i => bwea_i,
wea_i => wea_i,
aa_i => aa_i,
da_i => da_i,
qa_o => open,
clkb_i => clkb_i,
bweb_i => f_zeros((g_data_width+7)/8),
web_i => '0',
ab_i => ab_i,
db_i => f_zeros(g_data_width),
qb_o => qb_o);
end syn;
|
lgpl-3.0
|
15dd37d049fd9734f08c035edbbfaf79
| 0.496366 | 3.689385 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/gencores_pkg.vhd
| 1 | 22,636 |
-------------------------------------------------------------------------------
-- Title : General cores VHDL package
-- Project : General Cores library
-------------------------------------------------------------------------------
-- File : gencores_pkg.vhd
-- Author : Tomasz Wlostowski
-- Theodor-Adrian Stana
-- Matthieu Cattin
-- Company : CERN
-- Created : 2009-09-01
-- Last update: 2014-07-31
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
-- Description:
-- Package incorporating simple VHDL modules, which are used
-- in the WR and other OHWR projects.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009-2012 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2009-09-01 0.9 twlostow Created
-- 2011-04-18 1.0 twlostow Added comments & header
-- 2013-11-20 1.1 tstana Added glitch filter and I2C slave
-- 2014-03-14 1.2 mcattin Added dynamic glitch filter
-- 2014-03-20 1.3 mcattin Added bicolor led controller
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
package gencores_pkg is
--============================================================================
-- Component instantiations
--============================================================================
------------------------------------------------------------------------------
-- Pulse extender
------------------------------------------------------------------------------
component gc_extend_pulse
generic (
g_width : natural);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_i : in std_logic;
extended_o : out std_logic);
end component;
------------------------------------------------------------------------------
-- CRC generator
------------------------------------------------------------------------------
component gc_crc_gen
generic (
g_polynomial : std_logic_vector := x"04C11DB7";
g_init_value : std_logic_vector := x"ffffffff";
g_residue : std_logic_vector := x"38fb2284";
g_data_width : integer range 2 to 256 := 16;
g_half_width : integer range 2 to 256 := 8;
g_sync_reset : integer range 0 to 1 := 1;
g_dual_width : integer range 0 to 1 := 0;
g_registered_match_output : boolean := true;
g_registered_crc_output : boolean := true);
port (
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
half_i : in std_logic;
restart_i : in std_logic := '0';
data_i : in std_logic_vector(g_data_width - 1 downto 0);
match_o : out std_logic;
crc_o : out std_logic_vector(g_polynomial'length - 1 downto 0));
end component;
------------------------------------------------------------------------------
-- Moving average
------------------------------------------------------------------------------
component gc_moving_average
generic (
g_data_width : natural;
g_avg_log2 : natural range 1 to 8);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
din_i : in std_logic_vector(g_data_width-1 downto 0);
din_stb_i : in std_logic;
dout_o : out std_logic_vector(g_data_width-1 downto 0);
dout_stb_o : out std_logic);
end component;
------------------------------------------------------------------------------
-- PI controller
------------------------------------------------------------------------------
component gc_dual_pi_controller
generic (
g_error_bits : integer;
g_dacval_bits : integer;
g_output_bias : integer;
g_integrator_fracbits : integer;
g_integrator_overbits : integer;
g_coef_bits : integer);
port (
clk_sys_i : in std_logic;
rst_n_sysclk_i : in std_logic;
phase_err_i : in std_logic_vector(g_error_bits-1 downto 0);
phase_err_stb_p_i : in std_logic;
freq_err_i : in std_logic_vector(g_error_bits-1 downto 0);
freq_err_stb_p_i : in std_logic;
mode_sel_i : in std_logic;
dac_val_o : out std_logic_vector(g_dacval_bits-1 downto 0);
dac_val_stb_p_o : out std_logic;
pll_pcr_enable_i : in std_logic;
pll_pcr_force_f_i : in std_logic;
pll_fbgr_f_kp_i : in std_logic_vector(g_coef_bits-1 downto 0);
pll_fbgr_f_ki_i : in std_logic_vector(g_coef_bits-1 downto 0);
pll_pbgr_p_kp_i : in std_logic_vector(g_coef_bits-1 downto 0);
pll_pbgr_p_ki_i : in std_logic_vector(g_coef_bits-1 downto 0));
end component;
------------------------------------------------------------------------------
-- Serial 16-bit DAC interface (SPI/QSPI/MICROWIRE compatible)
------------------------------------------------------------------------------
component gc_serial_dac
generic (
g_num_data_bits : integer;
g_num_extra_bits : integer;
g_num_cs_select : integer;
g_sclk_polarity : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
value_i : in std_logic_vector(g_num_data_bits-1 downto 0);
cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0);
load_i : in std_logic;
sclk_divsel_i : in std_logic_vector(2 downto 0);
dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0);
dac_sclk_o : out std_logic;
dac_sdata_o : out std_logic;
busy_o : out std_logic);
end component;
------------------------------------------------------------------------------
-- Synchronisation FF chain
------------------------------------------------------------------------------
component gc_sync_ffs
generic (
g_sync_edge : string := "positive");
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
data_i : in std_logic;
synced_o : out std_logic;
npulse_o : out std_logic;
ppulse_o : out std_logic);
end component;
------------------------------------------------------------------------------
-- Pulse synchroniser
------------------------------------------------------------------------------
component gc_pulse_synchronizer
port (
clk_in_i : in std_logic;
clk_out_i : in std_logic;
rst_n_i : in std_logic;
d_ready_o : out std_logic;
d_p_i : in std_logic;
q_p_o : out std_logic);
end component;
------------------------------------------------------------------------------
-- Pulse synchroniser (with reset from both clock domains)
------------------------------------------------------------------------------
component gc_pulse_synchronizer2 is
port (
clk_in_i : in std_logic;
rst_in_n_i : in std_logic;
clk_out_i : in std_logic;
rst_out_n_i : in std_logic;
d_ready_o : out std_logic;
d_p_i : in std_logic;
q_p_o : out std_logic);
end component;
------------------------------------------------------------------------------
-- Frequency meter
------------------------------------------------------------------------------
component gc_frequency_meter
generic (
g_with_internal_timebase : boolean;
g_clk_sys_freq : integer;
g_counter_bits : integer);
port (
clk_sys_i : in std_logic;
clk_in_i : in std_logic;
rst_n_i : in std_logic;
pps_p1_i : in std_logic;
freq_o : out std_logic_vector(g_counter_bits-1 downto 0);
freq_valid_o : out std_logic);
end component;
------------------------------------------------------------------------------
-- Time-division multiplexer with round robin arbitration
------------------------------------------------------------------------------
component gc_arbitrated_mux
generic (
g_num_inputs : integer;
g_width : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
d_i : in std_logic_vector(g_num_inputs * g_width-1 downto 0);
d_valid_i : in std_logic_vector(g_num_inputs-1 downto 0);
d_req_o : out std_logic_vector(g_num_inputs-1 downto 0);
q_o : out std_logic_vector(g_width-1 downto 0);
q_valid_o : out std_logic;
q_input_id_o : out std_logic_vector(f_log2_size(g_num_inputs)-1 downto 0));
end component;
------------------------------------------------------------------------------
-- Power-On reset generator
------------------------------------------------------------------------------
component gc_reset is
generic(
g_clocks : natural := 1;
g_logdelay : natural := 10;
g_syncdepth : natural := 3);
port(
free_clk_i : in std_logic;
locked_i : in std_logic := '1'; -- All the PLL locked signals ANDed together
clks_i : in std_logic_vector(g_clocks-1 downto 0);
rstn_o : out std_logic_vector(g_clocks-1 downto 0));
end component;
------------------------------------------------------------------------------
-- Round robin arbiter
------------------------------------------------------------------------------
component gc_rr_arbiter
generic (
g_size : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
req_i : in std_logic_vector(g_size-1 downto 0);
grant_o : out std_logic_vector(g_size-1 downto 0);
grant_comb_o : out std_logic_vector(g_size-1 downto 0));
end component;
------------------------------------------------------------------------------
-- Pack or unpack words
------------------------------------------------------------------------------
component gc_word_packer
generic (
g_input_width : integer;
g_output_width : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
d_i : in std_logic_vector(g_input_width-1 downto 0);
d_valid_i : in std_logic;
d_req_o : out std_logic;
flush_i : in std_logic := '0';
q_o : out std_logic_vector(g_output_width-1 downto 0);
q_valid_o : out std_logic;
q_req_i : in std_logic);
end component;
------------------------------------------------------------------------------
-- Adder
------------------------------------------------------------------------------
component gc_big_adder is
generic(
g_data_bits : natural := 64;
g_parts : natural := 4);
port(
clk_i : in std_logic;
stall_i : in std_logic := '0';
a_i : in std_logic_vector(g_data_bits-1 downto 0);
b_i : in std_logic_vector(g_data_bits-1 downto 0);
c_i : in std_logic := '0';
c1_o : out std_logic;
x2_o : out std_logic_vector(g_data_bits-1 downto 0);
c2_o : out std_logic);
end component;
------------------------------------------------------------------------------
-- I2C slave
------------------------------------------------------------------------------
constant c_i2cs_idle : std_logic_vector(1 downto 0) := "00";
constant c_i2cs_addr_good : std_logic_vector(1 downto 0) := "01";
constant c_i2cs_rd_done : std_logic_vector(1 downto 0) := "10";
constant c_i2cs_wr_done : std_logic_vector(1 downto 0) := "11";
component gc_i2c_slave is
generic
(
-- Length of glitch filter
-- 0 - SCL and SDA lines are passed only through synchronizer
-- 1 - one clk_i glitches filtered
-- 2 - two clk_i glitches filtered
g_gf_len : natural := 0
);
port
(
-- Clock, reset ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- Slave address
i2c_addr_i : in std_logic_vector(6 downto 0);
-- ACK input, should be set after done_p_o = '1'
-- (note that the bit is reversed wrt I2C ACK bit)
-- '1' - ACK
-- '0' - NACK
ack_i : in std_logic;
-- Byte to send, should be loaded while done_p_o = '1'
tx_byte_i : in std_logic_vector(7 downto 0);
-- Received byte, valid after done_p_o = '1'
rx_byte_o : out std_logic_vector(7 downto 0);
-- Pulse outputs signaling various I2C actions
-- Start and stop conditions
i2c_sta_p_o : out std_logic;
i2c_sto_p_o : out std_logic;
-- Received address corresponds addr_i
addr_good_p_o : out std_logic;
-- Read and write done
r_done_p_o : out std_logic;
w_done_p_o : out std_logic;
-- I2C bus operation, set after address detection
-- '0' - write
-- '1' - read
op_o : out std_logic
);
end component gc_i2c_slave;
------------------------------------------------------------------------------
-- Glitch filter
------------------------------------------------------------------------------
component gc_glitch_filt is
generic
(
-- Length of glitch filter:
-- g_len = 1 => data width should be > 1 clk_i cycle
-- g_len = 2 => data width should be > 2 clk_i cycle
-- etc.
g_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Data input
dat_i : in std_logic;
-- Data output
-- latency: g_len+1 clk_i cycles
dat_o : out std_logic
);
end component gc_glitch_filt;
------------------------------------------------------------------------------
-- Dynamic glitch filter
------------------------------------------------------------------------------
component gc_dyn_glitch_filt is
generic
(
-- Number of bit of the glitch filter length input
g_len_width : natural := 8
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter length
len_i : in std_logic_vector(g_len_width-1 downto 0);
-- Data input
dat_i : in std_logic;
-- Data output
-- latency: g_len+1 clk_i cycles
dat_o : out std_logic
);
end component gc_dyn_glitch_filt;
------------------------------------------------------------------------------
-- FSM Watchdog Timer
------------------------------------------------------------------------------
component gc_fsm_watchdog is
generic
(
-- Maximum value of watchdog timer in clk_i cycles
g_wdt_max : integer := 65535
);
port
(
-- Clock and active-low reset line
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Active-high watchdog timer reset line, synchronous to clk_i
wdt_rst_i : in std_logic;
-- Active-high reset output, synchronous to clk_i
fsm_rst_o : out std_logic
);
end component gc_fsm_watchdog;
------------------------------------------------------------------------------
-- Bicolor LED controller
------------------------------------------------------------------------------
constant c_led_red : std_logic_vector(1 downto 0) := "10";
constant c_led_green : std_logic_vector(1 downto 0) := "01";
constant c_led_red_green : std_logic_vector(1 downto 0) := "11";
constant c_led_off : std_logic_vector(1 downto 0) := "00";
component gc_bicolor_led_ctrl
generic(
g_nb_column : natural := 4;
g_nb_line : natural := 2;
g_clk_freq : natural := 125000000; -- in Hz
g_refresh_rate : natural := 250 -- in Hz
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
led_intensity_i : in std_logic_vector(6 downto 0);
led_state_i : in std_logic_vector((g_nb_line * g_nb_column * 2) - 1 downto 0);
column_o : out std_logic_vector(g_nb_column - 1 downto 0);
line_o : out std_logic_vector(g_nb_line - 1 downto 0);
line_oen_o : out std_logic_vector(g_nb_line - 1 downto 0)
);
end component;
component gc_sync_register is
generic (
g_width : integer);
port (
clk_i : in std_logic;
rst_n_a_i : in std_logic;
d_i : in std_logic_vector(g_width-1 downto 0);
q_o : out std_logic_vector(g_width-1 downto 0));
end component gc_sync_register;
--============================================================================
-- Procedures and functions
--============================================================================
procedure f_rr_arbitrate (
signal req : in std_logic_vector;
signal pre_grant : in std_logic_vector;
signal grant : out std_logic_vector);
function f_onehot_decode(x : std_logic_vector; size : integer) return std_logic_vector;
function f_big_ripple(a, b : std_logic_vector; c : std_logic) return std_logic_vector;
function f_gray_encode(x : std_logic_vector) return std_logic_vector;
function f_gray_decode(x : std_logic_vector; step : natural) return std_logic_vector;
function log2_ceil(N : natural) return positive;
end package;
package body gencores_pkg is
------------------------------------------------------------------------------
-- Simple round-robin arbiter:
-- req = requests (1 = pending request),
-- pre_grant = previous grant vector (1 cycle delay)
-- grant = new grant vector
------------------------------------------------------------------------------
procedure f_rr_arbitrate (
signal req : in std_logic_vector;
signal pre_grant : in std_logic_vector;
signal grant : out std_logic_vector)is
variable reqs : std_logic_vector(req'length - 1 downto 0);
variable gnts : std_logic_vector(req'length - 1 downto 0);
variable gnt : std_logic_vector(req'length - 1 downto 0);
variable gntM : std_logic_vector(req'length - 1 downto 0);
variable zeros : std_logic_vector(req'length - 1 downto 0);
begin
zeros := (others => '0');
-- bit twiddling magic :
gnt := req and std_logic_vector(unsigned(not req) + 1);
reqs := req and not (std_logic_vector(unsigned(pre_grant) - 1) or pre_grant);
gnts := reqs and std_logic_vector(unsigned(not reqs)+1);
if(reqs = zeros) then
gntM := gnt;
else
gntM := gnts;
end if;
if((req and pre_grant) = zeros) then
grant <= gntM;
else
grant <= pre_grant;
end if;
end f_rr_arbitrate;
function f_onehot_decode(x : std_logic_vector; size : integer) return std_logic_vector is
begin
for j in 0 to x'left loop
if x(j) /= '0' then
return std_logic_vector(to_unsigned(j, size));
end if;
end loop; -- i
return std_logic_vector(to_unsigned(0, size));
end f_onehot_decode;
------------------------------------------------------------------------------
-- Carry ripple
------------------------------------------------------------------------------
function f_big_ripple(a, b : std_logic_vector; c : std_logic) return std_logic_vector is
constant len : natural := a'length;
variable aw, bw, rw : std_logic_vector(len+1 downto 0);
variable x : std_logic_vector(len downto 0);
begin
aw := "0" & a & c;
bw := "0" & b & c;
rw := std_logic_vector(unsigned(aw) + unsigned(bw));
x := rw(len+1 downto 1);
return x;
end f_big_ripple;
------------------------------------------------------------------------------
-- Gray encoder
------------------------------------------------------------------------------
function f_gray_encode(x : std_logic_vector) return std_logic_vector is
variable o : std_logic_vector(x'length downto 0);
begin
o := (x & '0') xor ('0' & x);
return o(x'length downto 1);
end f_gray_encode;
------------------------------------------------------------------------------
-- Gray decoder
-- call with step=1
------------------------------------------------------------------------------
function f_gray_decode(x : std_logic_vector; step : natural) return std_logic_vector is
constant len : natural := x'length;
alias y : std_logic_vector(len-1 downto 0) is x;
variable z : std_logic_vector(len-1 downto 0) := (others => '0');
begin
if step >= len then
return y;
else
z(len-step-1 downto 0) := y(len-1 downto step);
return f_gray_decode(y xor z, step+step);
end if;
end f_gray_decode;
------------------------------------------------------------------------------
-- Returns log of 2 of a natural number
------------------------------------------------------------------------------
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
end gencores_pkg;
|
lgpl-3.0
|
cc2e416fd7822c48924b0ee288132820
| 0.450521 | 4.014187 | false | false | false | false |
luebbers/reconos
|
support/threads/shared/conv_filter3x3.vhd
| 1 | 5,797 |
--
-- \file conv_filter3x3.vhd
--
-- Implements a configurable 3x3 convolution kernel
--
-- \author Andreas Agne <[email protected]>
-- \date 21.11.2007
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity conv_filter3x3 is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ien : in STD_LOGIC;
shift_in : in STD_LOGIC_VECTOR (23 downto 0);
shift_out : out STD_LOGIC_VECTOR (7 downto 0);
kernel : in STD_LOGIC_VECTOR (80 downto 0) -- 9x9
);
end conv_filter3x3;
architecture Behavioral of conv_filter3x3 is
type t_state is ( STATE_ADD,
STATE_SHIFT_OUT);
signal state : t_state;
signal row_a : std_logic_vector(23 downto 0);
signal row_b : std_logic_vector(23 downto 0);
signal row_c : std_logic_vector(23 downto 0);
signal pixels : std_logic_vector(71 downto 0); -- 9 pixels x 8 bit
signal p0,p1,p2,p3,p4,p5,p6,p7,p8 : std_logic_vector(7 downto 0);
signal k0,k1,k2,k3,k4,k5,k6,k7,k8 : std_logic_vector(8 downto 0);
signal m0,m1,m2,m3,m4,m5,m6,m7,m8 : std_logic_vector(15 downto 0);
function my_sum(sign : std_logic_vector(8 downto 0);
m0 : std_logic_vector(15 downto 0);
m1 : std_logic_vector(15 downto 0);
m2 : std_logic_vector(15 downto 0);
m3 : std_logic_vector(15 downto 0);
m4 : std_logic_vector(15 downto 0);
m5 : std_logic_vector(15 downto 0);
m6 : std_logic_vector(15 downto 0);
m7 : std_logic_vector(15 downto 0);
m8 : std_logic_vector(15 downto 0)) return std_logic_vector is
variable s : std_logic_vector(19 downto 0);
variable s0 : std_logic_vector(19 downto 0);
variable s1 : std_logic_vector(19 downto 0);
variable s2 : std_logic_vector(19 downto 0);
variable s3 : std_logic_vector(19 downto 0);
variable s4 : std_logic_vector(19 downto 0);
variable s5 : std_logic_vector(19 downto 0);
variable result : std_logic_vector(7 downto 0);
begin
s0 := X"20000";
s1 := X"20000";
s2 := X"20000";
s3 := X"20000";
if sign(0) = '0' then s0 := s0 + m0(15 downto 4);
else s0 := s0 - m0(15 downto 4); end if;
if sign(1) = '0' then s0 := s0 + m1(15 downto 4);
else s0 := s0 - m1(15 downto 4); end if;
if sign(2) = '0' then s1 := s1 + m2(15 downto 4);
else s1 := s1 - m2(15 downto 4); end if;
if sign(3) = '0' then s1 := s1 + m3(15 downto 4);
else s1 := s1 - m3(15 downto 4); end if;
if sign(4) = '0' then s2 := s2 + m4(15 downto 4);
else s2 := s2 - m4(15 downto 4); end if;
if sign(5) = '0' then s2 := s2 + m5(15 downto 4);
else s2 := s2 - m5(15 downto 4); end if;
if sign(6) = '0' then s3 := s3 + m6(15 downto 4);
else s3 := s3 - m6(15 downto 4); end if;
if sign(7) = '0' then s3 := s3 + m7(15 downto 4);
else s3 := s3 - m7(15 downto 4); end if;
if sign(8) = '0' then s3 := s3 + m8(15 downto 4);
else s3 := s3 - m8(15 downto 4); end if;
s4 := s0 + s1;
s5 := s2 + s3;
s := s4 + s5;
if s > X"800FF" then
result := X"FF";
elsif s < X"80000" then
result := X"00";
else
result := s(7 downto 0);
end if;
return result;
end function;
begin
pixels <= row_a & row_b & row_c;
p0 <= pixels(1*8-1 downto 0*8);
p1 <= pixels(2*8-1 downto 1*8);
p2 <= pixels(3*8-1 downto 2*8);
p3 <= pixels(4*8-1 downto 3*8);
p4 <= pixels(5*8-1 downto 4*8);
p5 <= pixels(6*8-1 downto 5*8);
p6 <= pixels(7*8-1 downto 6*8);
p7 <= pixels(8*8-1 downto 7*8);
p8 <= pixels(9*8-1 downto 8*8);
k0 <= kernel(1*9-1 downto 0*9);
k1 <= kernel(2*9-1 downto 1*9);
k2 <= kernel(3*9-1 downto 2*9);
k3 <= kernel(4*9-1 downto 3*9);
k4 <= kernel(5*9-1 downto 4*9);
k5 <= kernel(6*9-1 downto 5*9);
k6 <= kernel(7*9-1 downto 6*9);
k7 <= kernel(8*9-1 downto 7*9);
k8 <= kernel(9*9-1 downto 8*9);
shift : process(clk, rst)
variable sum : std_logic_vector(15 downto 0);
begin
if rising_edge(clk) then
if ien = '1' then
row_a <= shift_in;
row_b <= row_a;
row_c <= row_b;
end if;
m0 <= p0*k0(7 downto 0);
m1 <= p1*k1(7 downto 0);
m2 <= p2*k2(7 downto 0);
m3 <= p3*k3(7 downto 0);
m4 <= p4*k4(7 downto 0);
m5 <= p5*k5(7 downto 0);
m6 <= p6*k6(7 downto 0);
m7 <= p7*k7(7 downto 0);
m8 <= p8*k8(7 downto 0);
shift_out <= my_sum(k0(8)&k1(8)&k2(8)&k3(8)&k4(8)&k5(8)&k6(8)&k7(8)&k8(8),
m0 ,m1 ,m2 ,m3 ,m4 ,m5 ,m6 ,m7 ,m8);
end if;
end process;
end Behavioral;
|
gpl-3.0
|
53d6373086269d077442e0b9592492d5
| 0.575988 | 2.683796 | false | false | false | false |
whitef0x0/EECE353-Lab5
|
drawline.vhd
| 1 | 4,263 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity drawline is
port(CLK : in std_logic;
RST : in std_logic;
DRAW : in std_logic
x_start : in std_logic_vector(7 downto 0);
y_start : in std_logic_vector(7 downto 0);
x_end : in std_logic_vector(7 downto 0);
y_end : in std_logic_vector(7 downto 0);
line_color : in std_logic_vector(2 downto 0);
VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0); -- The outs go to VGA controller
VGA_HS : out std_logic;
VGA_VS : out std_logic;
VGA_BLANK : out std_logic;
VGA_SYNC : out std_logic;
VGA_CLK : out std_logic);
end drawline;
architecture rtl of drawline is
-- Component from the Verilog file: vga_adapter.v
component vga_adapter
generic(RESOLUTION : string);
port (
resetn : in std_logic;
clock : in std_logic;
colour : in std_logic_vector(2 downto 0);
x : in std_logic_vector(7 downto 0);
y : in std_logic_vector(6 downto 0);
plot : in std_logic;
VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0);
VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK : out std_logic);
end component;
component fsm_line is
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
xdone, ydone, ldone : IN STD_LOGIC;
sw : IN STD_LOGIC_VECTOR(17 downto 0);
draw : IN STD_LOGIC;
resetx, resety, incr_y, incr_x, plot, initl, drawl : OUT STD_LOGIC;
colour : OUT STD_LOGIC_VECTOR(2 downto 0);
x : OUT STD_LOGIC_VECTOR(7 downto 0);
y : OUT STD_LOGIC_VECTOR(6 downto 0);
ledg : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end component;
component datapath_line is
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
resetx, resety, incr_y, incr_x, initl, drawl : IN STD_LOGIC;
x : OUT STD_LOGIC_VECTOR(7 downto 0);
y : OUT STD_LOGIC_VECTOR(6 downto 0);
x0in : IN STD_LOGIC_VECTOR(7 downto 0); -- x1
y0in : IN STD_LOGIC_VECTOR(6 downto 0); -- y1
x1in : IN STD_LOGIC_VECTOR(7 downto 0); -- x0
y1in : IN STD_LOGIC_VECTOR(6 downto 0); -- y0
xdone, ydone, ldone : OUT STD_LOGIC
);
end component;
signal s_x : std_logic_vector(7 downto 0) := "00000000";
signal s_y : std_logic_vector(6 downto 0) := "0000000";
signal colour : std_logic_vector(2 downto 0);
signal plot : std_logic;
signal resety, resetx, initl : std_logic;
signal xdone, ydone, ldone : std_logic;
signal incr_y, incr_x, drawl : std_logic;
signal x_int : std_logic_vector(7 downto 0);
signal y_int : std_logic_vector(6 downto 0);
begin
vga_u0 : vga_adapter
generic map(RESOLUTION => "160x120")
port map(resetn => RST,
clock => CLK,
colour => colour,
x => s_x,
y => s_y,
plot => plot,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_HS => VGA_HS,
VGA_VS => VGA_VS,
VGA_BLANK => VGA_BLANK,
VGA_SYNC => VGA_SYNC,
VGA_CLK => VGA_CLK
);
fsm_line0 : fsm_line PORT MAP(
clock => CLK,
resetb => RST,
xdone => xdone,
ydone => ydone,
ldone => ldone,
--sw => SW,
draw => DRAW,
resetx => resetx,
resety => resety,
incr_y => incr_y,
incr_x => incr_x,
plot => plot,
initl => initl,
drawl => drawl,
colour_in => line_color,
colour_out => colour,
x => x_int,
y => y_int,
);
datapath_line0 : datapath_line PORT MAP(
clock => CLK,
resetb => RST,
resetx => resetx,
resety => resety,
initl => initl,
drawl => drawl,
x => s_x,
y => s_y,
xin => x_int,
yin => y_int,
xdone => xdone,
ydone => ydone,
ldone => ldone,
incr_y => incr_y,
incr_x => incr_x
);
end rtl;
|
mit
|
4fc9865df22ba6149c630af259ea4a3d
| 0.50997 | 3.095861 | false | false | false | false |
luebbers/reconos
|
core/pcores/plb_osif_v2_01_a/hdl/vhdl/mem_plb34.vhd
| 1 | 13,813 |
--!
--! \file mem_plb34.vhd
--!
--! Memory bus interface for the 64-bit PLB v34.
--!
--! \author Enno Luebbers <[email protected]>
--! \date 08.12.2008
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 08.12.2008 Enno Luebbers File created.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
library plb_osif_v2_01_a;
use plb_osif_v2_01_a.all;
entity mem_plb34 is
generic
(
C_SLAVE_BASEADDR : std_logic_vector := X"FFFFFFFF";
-- Bus protocol parameters
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
C_NUM_CE : integer := 2;
C_BURST_AWIDTH : integer := 13; -- 1024 x 64 Bit = 8192 Bytes = 2^13 Bytes
C_BURST_BASEADDR : std_logic_vector := X"00004000"; -- system memory base address for burst ram access
C_BURSTLEN_WIDTH : integer := 5
);
port
(
clk : in std_logic;
reset : in std_logic;
-- data interface ---------------------------
-- burst mem interface
o_burstAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_burstData : out std_logic_vector(0 to C_PLB_DWIDTH-1);
i_burstData : in std_logic_vector(0 to C_PLB_DWIDTH-1);
o_burstWE : out std_logic;
o_burstBE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
-- single word data input/output
i_singleData : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- osif2bus
o_singleData : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- bus2osif
-- control interface ------------------------
-- addresses for master transfers
i_localAddr : in std_logic_vector(0 to C_AWIDTH-1);
i_targetAddr : in std_logic_vector(0 to C_AWIDTH-1);
-- single word transfer requests
i_singleRdReq : in std_logic;
i_singleWrReq : in std_logic;
-- burst transfer requests
i_burstRdReq : in std_logic;
i_burstWrReq : in std_logic;
i_burstLen : in std_logic_vector(0 to C_BURSTLEN_WIDTH-1); -- number of burst beats (n x 64 bits)
-- status outputs
o_busy : out std_logic;
o_rdDone : out std_logic;
o_wrDone : out std_logic;
-- PLBv34 bus interface -----------------------------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH - 1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_DataX : in std_logic_vector(C_DWIDTH to C_PLB_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_PLB_DWIDTH/8-1);
Bus2IP_Burst : in std_logic;
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_DataX : out std_logic_vector(C_DWIDTH to C_PLB_DWIDTH-1);
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstLastAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_MstBE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
IP2Bus_MstBurst : out std_logic;
IP2Bus_MstBusLock : out std_logic;
IP2Bus_MstNum : out std_logic_vector(0 to 4);
IP2Bus_MstRdReq : out std_logic;
IP2Bus_MstWrReq : out std_logic;
IP2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1)
);
end entity mem_plb34;
architecture arch of mem_plb34 is
---------
-- read/write acknowledge
---------
signal ram_IP2Bus_RdAck : std_logic;
signal ram_IP2Bus_WrAck : std_logic;
signal slv_IP2Bus_RdAck : std_logic;
signal slv_IP2Bus_WrAck : std_logic;
signal slv_rddata : std_logic_vector(0 to C_DWIDTH-1);
begin
-----------------------------------------------------------------------
-- bus_master_inst: bus master instantiation
--
-- The bus_master module is responsible for initiating a bus read or
-- write transaction through the IPIF master services. The actual
-- transaction will appear like a bus initiated slave request at the
-- IPIF slave attachment and is therefore handled by bus_slave_regs
-- or the bus2burst process.
-----------------------------------------------------------------------
bus_master_inst : entity plb_osif_v2_01_a.bus_master
generic map (
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
C_SLAVE_BASEADDR => C_SLAVE_BASEADDR,
C_BURST_BASEADDR => C_BURST_BASEADDR,
C_BURSTLEN_WIDTH => C_BURSTLEN_WIDTH
)
port map (
clk => clk,
reset => reset,
-- PLB bus master signals
Bus2IP_MstError => Bus2IP_MstError,
Bus2IP_MstLastAck => Bus2IP_MstLastAck,
Bus2IP_MstRdAck => Bus2IP_MstRdAck,
Bus2IP_MstWrAck => Bus2IP_MstWrAck,
Bus2IP_MstRetry => Bus2IP_MstRetry,
Bus2IP_MstTimeOut => Bus2IP_MstTimeOut,
IP2Bus_Addr => IP2Bus_Addr,
IP2Bus_MstBE => IP2Bus_MstBE,
IP2Bus_MstBurst => IP2Bus_MstBurst,
IP2Bus_MstBusLock => IP2Bus_MstBusLock,
IP2Bus_MstNum => IP2Bus_MstNum,
IP2Bus_MstRdReq => IP2Bus_MstRdReq,
IP2Bus_MstWrReq => IP2Bus_MstWrReq,
IP2IP_Addr => IP2IP_Addr,
-- user interface
i_target_addr => i_targetAddr,
i_my_addr => i_localAddr,
i_read_req => i_singleRdReq,
i_write_req => i_singleWrReq,
i_burst_read_req => i_burstRdReq,
i_burst_write_req => i_burstWrReq,
i_burst_length => i_burstLen,
o_busy => o_busy,
o_read_done => o_rdDone,
o_write_done => o_wrDone
);
-----------------------------------------------------------------------
-- bus_slave_regs_inst: PLB bus slave instatiation
--
-- Handles access to the shared memory register
-- Used for single word memory accesses
-- (e.g. reconos_read() and reconos_write())
-----------------------------------------------------------------------
bus_slave_regs_inst : entity plb_osif_v2_01_a.bus_slave_regs
generic map (
C_DWIDTH => C_DWIDTH,
C_NUM_REGS => C_NUM_CE-1
)
port map (
clk => Bus2IP_Clk,
reset => Bus2IP_Reset,
-- bus slave signals
Bus2IP_Data => Bus2IP_Data,
Bus2IP_BE => Bus2IP_BE(0 to (C_DWIDTH/8)-1),
Bus2IP_RdCE => Bus2IP_RdCE(0 to C_NUM_CE-2),
Bus2IP_WrCE => Bus2IP_WrCE(0 to C_NUM_CE-2),
IP2Bus_Data => slv_RdData,
IP2Bus_RdAck => slv_IP2Bus_RdAck,
IP2Bus_WrAck => slv_IP2Bus_WrAck,
-- user registers
slv_osif2bus_shm => i_singleData,
slv_bus2osif_shm => o_singleData
);
-- read/write acknowledge
IP2Bus_RdAck <= slv_IP2Bus_RdAck or ram_IP2Bus_RdAck;
IP2Bus_WrAck <= slv_IP2Bus_WrAck or ram_IP2Bus_WrAck;
-- no error handling / retry / timeout
IP2Bus_Error <= '0';
IP2Bus_Retry <= '0';
IP2Bus_ToutSup <= '0';
-- multiplex data, if PLB connected
IP2Bus_Data <= i_burstData(0 to C_DWIDTH-1) when ram_IP2Bus_RdAck = '1' else slv_RdData;
IP2Bus_DataX <= i_burstData(C_DWIDTH to C_PLB_DWIDTH-1);
o_burstData <= Bus2IP_Data & Bus2IP_DataX;
-- burstWE <= ram_IP2Bus_WrAck and Bus2IP_WrReq;
o_burstBE <= Bus2IP_BE;
-------------------------------------------------------------------
-- bus2burst: handles bus accesses to burst memory
--
-- supports both single and burst accesses
-------------------------------------------------------------------
bus2burst : process(Bus2IP_Clk, Bus2IP_Reset)
type ram_state_t is (IDLE, BURST_READ, BURST_WRITE, SINGLE_READ);
variable ram_state : ram_state_t;
variable start_addr : std_logic_vector(0 to C_BURST_AWIDTH-1);
variable counter : natural := 0;
begin
if Bus2IP_Reset = '1' then
ram_state := IDLE;
start_addr := (others => '0');
counter := 0;
ram_IP2Bus_RdAck <= '0';
ram_IP2Bus_WrAck <= '0';
o_burstAddr <= (others => '0');
o_burstWE <= '0';
elsif rising_edge(Bus2IP_Clk) then
case ram_state is
when IDLE =>
counter := 0;
o_burstWE <= '0';
ram_IP2Bus_RdAck <= '0';
ram_IP2Bus_WrAck <= '0';
-- if Bus2IP_RdReq = '1' then
if Bus2IP_RdCE(1) = '1' and Bus2IP_RdReq = '1' then
if Bus2IP_Burst = '1' then
start_addr := Bus2IP_Addr(C_PLB_AWIDTH-C_BURST_AWIDTH to C_PLB_AWIDTH-1); -- get burst start address
o_burstAddr <= start_addr + counter*8;
ram_state := BURST_READ;
else
o_burstAddr <= Bus2IP_Addr(C_PLB_AWIDTH-C_BURST_AWIDTH to C_PLB_AWIDTH-1);
ram_state := SINGLE_READ;
end if;
-- elsif Bus2IP_WrReq = '1' then
elsif Bus2IP_WrCE(1) = '1'and Bus2IP_WrReq = '1' then
if Bus2IP_Burst = '1' then
start_addr := Bus2IP_Addr(C_PLB_AWIDTH-C_BURST_AWIDTH to C_PLB_AWIDTH-1); -- get burst start address
o_burstAddr <= start_addr + counter*8;
ram_IP2Bus_WrAck <= '1';
o_burstWE <= '1';
ram_state := BURST_WRITE;
else
o_burstAddr <= Bus2IP_Addr(C_PLB_AWIDTH-C_BURST_AWIDTH to C_PLB_AWIDTH-1);
ram_IP2Bus_WrAck <= '1';
o_burstWE <= '1';
ram_state := IDLE;
end if;
end if;
when BURST_READ =>
ram_IP2Bus_RdAck <= '1';
counter := counter + 1;
if Bus2IP_Burst = '0' then -- Bus2IP_Burst is deasserted at the second to last data beat
ram_IP2Bus_RdAck <= '0';
ram_state := IDLE;
end if;
o_burstAddr <= start_addr + counter*8;
when BURST_WRITE =>
counter := counter + 1;
if Bus2IP_Burst = '0' then -- Bus2IP_Burst is deasserted at the second to last data beat
ram_IP2Bus_WrAck <= '0';
o_burstWE <= '0';
ram_state := IDLE;
end if;
o_burstAddr <= start_addr + counter*8;
when SINGLE_READ =>
ram_IP2Bus_RdAck <= '1';
ram_state := IDLE;
end case;
end if;
end process;
end arch;
|
gpl-3.0
|
7659264b24c0fbe17fabbc25f204f0e7
| 0.482516 | 3.915249 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/Dbncr.vhd
| 1 | 2,323 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Mihaita Nagy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 17:11:29 03/06/2013
-- Design Name:
-- Module Name: dbncr - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This module represents a debouncer and is used to synchronize with the system clock
-- and remove glitches from the incoming button signals
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Dbncr is
generic(
NR_OF_CLKS : integer := 4095 -- Number of System Clock periods while the incoming signal
); -- has to be stable until a one-shot output signal is generated
port(
clk_i : in std_logic;
sig_i : in std_logic;
pls_o : out std_logic
);
end Dbncr;
architecture Behavioral of Dbncr is
signal cnt : integer range 0 to NR_OF_CLKS-1;
signal sigTmp : std_logic;
signal stble, stbleTmp : std_logic;
begin
DEB: process(clk_i)
begin
if rising_edge(clk_i) then
if sig_i = sigTmp then -- Count the number of clock periods if the signal is stable
if cnt = NR_OF_CLKS-1 then
stble <= sig_i;
else
cnt <= cnt + 1;
end if;
else -- Reset counter and sample the new signal value
cnt <= 0;
sigTmp <= sig_i;
end if;
end if;
end process DEB;
PLS: process(clk_i)
begin
if rising_edge(clk_i) then
stbleTmp <= stble;
end if;
end process PLS;
-- generate the one-shot output signal
pls_o <= '1' when stbleTmp = '0' and stble = '1' else '0';
end Behavioral;
|
gpl-3.0
|
725e954877c8b8d49fb5fc134982bbca
| 0.537667 | 4.285978 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/Ps2Interface.vhd
| 3 | 32,097 |
------------------------------------------------------------------------
-- ps2interface.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- This file contains the implementation of a generic bidirectional
-- ps/2 interface.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web for understanding how
-- the ps/2 protocol works.
-- http://www.computer-engineering.org/ps2protocol/
-- This module implements a generic bidirectional ps/2 interface. It can
-- be used with any ps/2 compatible device. It offers its clients a
-- convenient way to exchange data with the device. The interface
-- transparently wraps the byte to be sent into a ps/2 frame, generates
-- parity for byte and sends the frame one bit at a time to the device.
-- Similarly, when receiving data from the ps2 device, the interface
-- receives the frame, checks for parity, and extract the usefull data
-- and forwards it to the client. If an error occurs during receiving
-- or sending a byte, the client is informed by settings the err output
-- line high. This way, the client can resend the data or can issue
-- a resend command to the device.
-- The physical ps/2 interface uses 4 lines
-- For the 6-pin connector pins are assigned as follows:
-- 1 - Data
-- 2 - Not Implemented
-- 3 - Ground
-- 4 - Vcc (+5V)
-- 5 - Clock
-- 6 - Not Implemented
-- The clock line carries the device generated clock which has a
-- frequency in range 10 - 16.7 kHz (30 to 50us). When line is idle
-- it is placed in high impedance. The clock is only generated when
-- device is sending or receiving data.
-- The Data and Clock lines are both open-collector with pullup
-- resistors to Vcc. An "open-collector" interface has two possible
-- states: low('0') or high impedance('Z').
-- When device wants to send a byte, it pulls the clock line low and the
-- host(i.e. this interfaces) recognizes that the device is sending data
-- When the host wants to send data, it maeks a request to send. This
-- is done by holding the clock line low for at least 100us, then with
-- the clock line low, the data line is brought low. Next the clock line
-- is released (placed in high impedance). The devices begins generating
-- clock signal on clock line.
-- When receiving data, bits are read from the data line (ps2_data) on
-- the falling edge of the clock (ps2_clk). When sending data, the
-- device reads the bits from the data line on the rising edge of the
-- clock.
-- A frame for sending a byte is comprised of 11 bits as shown bellow:
-- bits 10 9 8 7 6 5 4 3 2 1 0
-- -------------------------------------------------------------
-- | STOP| PAR | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | START |
-- -------------------------------------------------------------
-- STOP - stop bit, always '1'
-- PAR - parity bit, odd parity for the 8 data bits.
-- - select in such way that the number of bits of '1' in the data
-- - bits together with parity bit is odd.
-- D0-7 - data bits.
-- START - start bit, always '0'
--
-- Frame is sent bit by bit starting with the least significant bit
-- (starting bit) and is received the same way. This is done, when
-- receiving, by shifting the frame register to the left when a bit
-- is available and placing the bit on data line on the most significant
-- bit. This way the first bit sent will reach the least significant bit
-- of the frame when all the bits have been received. When sending data
-- the least significant bit of the frame is placed on the data line
-- and the frame is shifted to the right when another bit needs to be
-- sent. During the request to send, when releasing the clock line,
-- the device reads the data line and interprets the data on it as the
-- first bit of the frame. Data line is low at that time, at this is the
-- way the start bit('0') is sent. Because of this, when sending, only
-- 10 shifts of the frame will be made.
-- While the interface is sending or receiving data, the busy output
-- signal goes high. When interface is idle, busy is low.
-- After sending all the bits in the frame, the device must acknowledge
-- the data sent. This is done by the host releasing and data line
-- (clock line is already released) after the last bit is sent. The
-- devices brings the data line and the clock line low, in this order,
-- to acknowledge the data. If data line is high when clock line goes
-- low after last bit, the device did not acknowledge the data and
-- err output is set.
-- A FSM is used to manage the transitions the set all the command
-- signals. States that begin with "rx_" are used to receive data
-- from device and states begining with "tx_" are used to send data
-- to the device.
-- For the parity bit, a ROM holds the parity bit for all possible
-- data (256 possible values, since 8 bits of data). The ROM has
-- dimensions 256x1bit. For obtaining the parity bit of a value,
-- the bit at the data value address is read. Ex: to find the parity
-- bit of 174, the bit at address 174 is read.
-- For generating the necessary delay, counters are used. For example,
-- to generate the 100us delay a 14 bit counter is used that has the
-- upper limit for counting 10000. The interface is designed to run
-- at 100MHz. Thus, 10000x10ns = 100us.
-----------------------------------------------------------------------
-- If using the interface at different frequency than 100MHz, adjusting
-- the delay counters is necessary!!!
-----------------------------------------------------------------------
-- Clock line(ps2_clk) and data line(ps2_data) are passed through a
-- debouncer for the transitions of the clock and data to be clean.
-- Also, ps2_clk_s and ps2_data_s hold the debounced and synchronized
-- value of the clock and data line to the system clock(clk).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- ps2_clk - inout pin, clock line of the ps/2 interface
-- ps2_data - inout pin, data line of the ps/2 interface
-- clk - input pin, system clock signal
-- rst - input pin, system reset signal
-- tx_data - input pin, 8 bits, from client
-- - data to be sent to the device
-- write_data - input pin, from client
-- - should be active for one clock period when then
-- - client wants to send data to the device and
-- - data to be sent is valid on tx_data
-- rx_data - output pin, 8 bits, to client
-- - data received from device
-- read - output pin, to client
-- - active for one clock period when new data is
-- - available from device
-- busy - output pin, to client
-- - active while sending or receiving data.
-- err - output pin, to client
-- - active for one clock period when an error occurred
-- - during sending or receiving.
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
-- the ps2interface entity declaration
-- read above for behavioral description and port definitions.
entity Ps2Interface is
port(
ps2_clk : inout std_logic;
ps2_data : inout std_logic;
clk : in std_logic;
rst : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
write_data : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
read_data : out std_logic;
busy : out std_logic;
err : out std_logic
);
-- forces the extraction of distributed ram for
-- the parity rom memory.
-- please remove if block ram is preffered.
attribute rom_extract : string;
attribute rom_extract of Ps2Interface: entity is "yes";
attribute rom_style : string;
attribute rom_style of Ps2Interface: entity is "distributed";
end Ps2Interface;
architecture Behavioral of Ps2Interface is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- Values are valid for a 100MHz clk. Please adjust for other
-- frequencies if necessary!
-- upper limit for 100us delay counter.
-- 10000 * 10ns = 100us
constant DELAY_100US : std_logic_vector(13 downto 0):= "10011100010000";
-- 10000 clock periods
-- upper limit for 20us delay counter.
-- 2000 * 10ns = 20us
constant DELAY_20US : std_logic_vector(10 downto 0) := "11111010000";
-- 2000 clock periods
-- upper limit for 63clk delay counter.
constant DELAY_63CLK : std_logic_vector(6 downto 0) := "1111111";
-- 63 clock periods
-- delay from debouncing ps2_clk and ps2_data signals
constant DEBOUNCE_DELAY : std_logic_vector(3 downto 0) := "1111";
-- number of bits in a frame
constant NUMBITS: std_logic_vector(3 downto 0) := "1011"; -- 11
-- parity bit position in frame
constant PARITY_BIT: positive := 9;
-- (odd) parity bit ROM
-- Used instead of logic because this way speed is far greater
-- 256x1bit rom
-- If the odd parity bit for a 8 bits number, x, is needed
-- the bit at address x is the parity bit.
type ROM is array(0 to 255) of std_logic;
constant parityrom : ROM := (
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1'
);
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- 14 bits counter
-- max value DELAY_100US
-- used to wait 100us
signal delay_100us_count: std_logic_vector(13 downto 0) :=
(others => '0');
-- 11 bits counter
-- max value DELAY_20US
-- used to wait 20us
signal delay_20us_count: std_logic_vector(10 downto 0) :=
(others => '0');
-- 11 bits counter
-- max value DELAY_63CLK
-- used to wait 63 clock periods
signal delay_63clk_count: std_logic_vector(6 downto 0) :=
(others => '0');
-- done signal for the couters above
-- when a counter reaches max value,the corresponding done signal is set
signal delay_100us_done, delay_20us_done, delay_63clk_done: std_logic;
-- enable signal for 100us delay counter
signal delay_100us_counter_enable: std_logic := '0';
-- enable signal for 20us delay counter
signal delay_20us_counter_enable : std_logic := '0';
-- enable signal for 63clk delay counter
signal delay_63clk_counter_enable: std_logic := '0';
-- synchronzed input for ps2_clk and ps2_data
signal ps2_clk_s,ps2_data_s: std_logic := '1';
-- control the output of ps2_clk and ps2_data
-- if 1 then corresponding signal (ps2_clk or ps2_data) is
-- put in high impedance ('Z').
signal ps2_clk_h,ps2_data_h: std_logic := '1';
-- states of the FSM for controlling the communcation with the device
-- states that begin with "rx_" are used when receiving data
-- states that begin with "tx_" are used when transmiting data
type fsm_state is
(
idle,rx_clk_h,rx_clk_l,rx_down_edge,rx_error_parity,rx_data_ready,
tx_force_clk_l,tx_bring_data_down,tx_release_clk,
tx_first_wait_down_edge,tx_clk_l,tx_wait_up_edge,tx_clk_h,
tx_wait_up_edge_before_ack,tx_wait_ack,tx_received_ack,
tx_error_no_ack
);
-- the signal that holds the current state of the FSM
-- implicitly state is idle.
signal state: fsm_state := idle;
-- register that holds the frame received or the one to be sent.
-- Its contents are shifted in from the bus one bit at a time
-- from left to right when receiving data and are shifted on the
-- bus (ps2_data) one bit at a time to the right when sending data
signal frame: std_logic_vector(10 downto 0) := (others => '0');
-- how many bits have been sent or received.
signal bit_count: std_logic_vector(3 downto 0) := (others => '0');
-- when active the bit counter is reset.
signal reset_bit_count: std_logic := '0';
-- when active the contents of the frame is shifted to the right
-- and the most significant bit of frame is loaded with ps2_data.
signal shift_frame: std_logic := '0';
-- parity of the byte that was received from the device.
-- must match the parity bit received, else error occurred.
signal rx_parity: std_logic := '0';
-- parity bit that is sent with the frame, representing the
-- odd parity of the byte currently being sent
signal tx_parity: std_logic := '0';
-- when active, frame is loaded with the start bit, data on
-- tx_data, parity bit (tx_parity) and stop bit
-- this frame will be sent to the device.
signal load_tx_data: std_logic := '0';
-- when active bits 8 downto 1 from frame are loaded into
-- rx_data register. This is the byte received from the device.
signal load_rx_data: std_logic := '0';
-- intermediary signals used to debounce the inputs ps2_clk and ps2_data
signal ps2_clk_clean,ps2_data_clean: std_logic := '1';
-- debounce counter for the ps2_clk input and the ps2_data input.
signal clk_count,data_count: std_logic_vector(3 downto 0);
-- last value on ps2_clk and ps2_data.
signal clk_inter,data_inter: std_logic := '1';
begin
---------------------------------------------------------------------
-- FLAGS and PS2 CLOCK AND DATA LINES
---------------------------------------------------------------------
-- clean ps2_clk signal (debounce)
-- note that this introduces a delay in ps2_clk of
-- DEBOUNCE_DELAY clocks
process(clk)
begin
if(rising_edge(clk)) then
-- if the current bit on ps2_clk is different
-- from the last value, then reset counter
-- and retain value
if(ps2_clk /= clk_inter) then
clk_inter <= ps2_clk;
clk_count <= (others => '0');
-- if counter reached upper limit, then
-- the signal is clean
elsif(clk_count = DEBOUNCE_DELAY) then
ps2_clk_clean <= clk_inter;
-- ps2_clk did not change, but counter did not
-- reach limit. Increment counter
else
clk_count <= clk_count + 1;
end if;
end if;
end process;
-- clean ps2_data signal (debounce)
-- note that this introduces a delay in ps2_data of
-- DEBOUNCE_DELAY clocks
process(clk)
begin
if(rising_edge(clk)) then
-- if the current bit on ps2_data is different
-- from the last value, then reset counter
-- and retain value
if(ps2_data /= data_inter) then
data_inter <= ps2_data;
data_count <= (others => '0');
-- if counter reached upper limit, then
-- the signal is clean
elsif(data_count = DEBOUNCE_DELAY) then
ps2_data_clean <= data_inter;
-- ps2_data did not change, but counter did not
-- reach limit. Increment counter
else
data_count <= data_count + 1;
end if;
end if;
end process;
-- Synchronize ps2 entries
ps2_clk_s <= ps2_clk_clean when rising_edge(clk);
ps2_data_s <= ps2_data_clean when rising_edge(clk);
-- Assign parity from frame bits 8 downto 1, this is the parity
-- that should be received inside the frame on PARITY_BIT position
rx_parity <= parityrom(conv_integer(frame(8 downto 1)))
when rising_edge(clk);
-- The parity for the data to be sent
tx_parity <= parityrom(conv_integer(tx_data)) when rising_edge(clk);
-- Force ps2_clk to '0' if ps2_clk_h = '0', else release the line
-- ('Z' = +5Vcc because of pull-ups)
ps2_clk <= 'Z' when ps2_clk_h = '1' else '0';
-- Force ps2_data to '0' if ps2_data_h = '0', else release the line
-- ('Z' = +5Vcc because of pull-ups)
ps2_data <= 'Z' when ps2_data_h = '1' else '0';
-- Control busy flag. Interface is not busy while in idle state.
busy <= '0' when state = idle else '1';
-- reset the bit counter when in idle state.
reset_bit_count <= '1' when state = idle else '0';
-- Control shifting of the frame
-- When receiving from device, data is read
-- on the falling edge of ps2_clk
-- When sending to device, data is read by device
-- on the rising edge of ps2_clk
shift_frame <= '1' when state = rx_down_edge or
state = tx_clk_l else
'0';
---------------------------------------------------------------------
-- FINITE STATE MACHINE
---------------------------------------------------------------------
-- For the current state establish next state
-- and give necessary commands
manage_fsm: process(clk,rst,state,ps2_clk_s,ps2_data_s,write_data,tx_data,
bit_count,rx_parity,frame,delay_100us_done,
delay_20us_done,delay_63clk_done)
begin
-- if reset occurs, go to idle state.
if(rst = '1') then
state <= idle;
elsif(rising_edge(clk)) then
-- default values for these signals
-- ensures signals are reset to default value
-- when coditions for their activation are no
-- longer applied (transition to other state,
-- where signal should not be active)
-- Idle value for ps2_clk and ps2_data is 'Z'
ps2_clk_h <= '1';
ps2_data_h <= '1';
load_tx_data <= '0';
load_rx_data <= '0';
read_data <= '0';
err <= '0';
case state is
-- wait for the device to begin a transmission
-- by pulling the clock line low and go to state
-- rx_down_edge or, if write is high, the
-- client of this interface wants to send a byte
-- to the device and a transition is made to state
-- tx_force_clk_l
when idle =>
if(ps2_clk_s = '0') then
state <= rx_down_edge;
elsif(write_data = '1') then
state <= tx_force_clk_l;
else
state <= idle;
end if;
-- ps2_clk is high, check if all the bits have been read
-- if, last bit read, check parity, and if parity ok
-- load received data into rx_data.
-- else if more bits left, then wait for the ps2_clk to
-- go low
when rx_clk_h =>
if(bit_count = NUMBITS) then
if(not (rx_parity = frame(PARITY_BIT))) then
state <= rx_error_parity;
else
load_rx_data <= '1';
state <= rx_data_ready;
end if;
elsif(ps2_clk_s = '0') then
state <= rx_down_edge;
else
state <= rx_clk_h;
end if;
-- data must be read into frame in this state
-- the ps2_clk just transitioned from high to low
when rx_down_edge =>
state <= rx_clk_l;
-- ps2_clk line is low, wait for it to go high
when rx_clk_l =>
if(ps2_clk_s = '1') then
state <= rx_clk_h;
else
state <= rx_clk_l;
end if;
-- parity bit received is invalid
-- signal error and go back to idle.
when rx_error_parity =>
err <= '1';
state <= idle;
-- parity bit received was good
-- set read signal for the client to know
-- a new byte was received and is available on rx_data
when rx_data_ready =>
read_data <= '1';
state <= idle;
-- the client wishes to transmit a byte to the device
-- this is done by holding ps2_clk down for at least 100us
-- bringing down ps2_data, wait 20us and then releasing
-- the ps2_clk.
-- This constitutes a request to send command.
-- In this state, the ps2_clk line is held down and
-- the counter for waiting 100us is eanbled.
-- when the counter reached upper limit, transition
-- to tx_bring_data_down
when tx_force_clk_l =>
load_tx_data <= '1';
ps2_clk_h <= '0';
if(delay_100us_done = '1') then
state <= tx_bring_data_down;
else
state <= tx_force_clk_l;
end if;
-- with the ps2_clk line low bring ps2_data low
-- wait for 20us and then go to tx_release_clk
when tx_bring_data_down =>
-- keep clock line low
ps2_clk_h <= '0';
-- set data line low
-- when clock is released in the next state
-- the device will read bit 0 on data line
-- and this bit represents the start bit.
ps2_data_h <= '0'; -- start bit = '0'
if(delay_20us_done = '1') then
state <= tx_release_clk;
else
state <= tx_bring_data_down;
end if;
-- release the ps2_clk line
-- keep holding data line low
when tx_release_clk =>
ps2_clk_h <= '1';
-- must maintain data low,
-- otherwise will be released by default value
ps2_data_h <= '0';
state <= tx_first_wait_down_edge;
-- state is necessary because the clock signal
-- is not released instantaneously and, because of debounce,
-- delay is even greater.
-- Wait 63 clock periods for the clock line to release
-- then if clock is low then go to tx_clk_l
-- else wait until ps2_clk goes low.
when tx_first_wait_down_edge =>
ps2_data_h <= '0';
if(delay_63clk_done = '1') then
if(ps2_clk_s = '0') then
state <= tx_clk_l;
else
state <= tx_first_wait_down_edge;
end if;
else
state <= tx_first_wait_down_edge;
end if;
-- place the least significant bit from frame
-- on the data line
-- During this state the frame is shifted one
-- bit to the right
when tx_clk_l =>
ps2_data_h <= frame(0);
state <= tx_wait_up_edge;
-- wait for the clock to go high
-- this is the edge on which the device reads the data
-- on ps2_data.
-- keep holding ps2_data on frame(0) because else
-- will be released by default value.
-- Check if sent the last bit and if so, release data line
-- and go to state that wait for acknowledge
when tx_wait_up_edge =>
ps2_data_h <= frame(0);
-- NUMBITS - 1 because first (start bit = 0) bit was read
-- when the clock line was released in the request to
-- send command (see tx_bring_data_down state).
if(bit_count = NUMBITS-1) then
ps2_data_h <= '1';
state <= tx_wait_up_edge_before_ack;
-- if more bits to send, wait for the up edge
-- of ps2_clk
elsif(ps2_clk_s = '1') then
state <= tx_clk_h;
else
state <= tx_wait_up_edge;
end if;
-- ps2_clk is released, wait for down edge
-- and go to tx_clk_l when arrived
when tx_clk_h =>
ps2_data_h <= frame(0);
if(ps2_clk_s = '0') then
state <= tx_clk_l;
else
state <= tx_clk_h;
end if;
-- release ps2_data and wait for rising edge of ps2_clk
-- once this occurs, transition to tx_wait_ack
when tx_wait_up_edge_before_ack =>
ps2_data_h <= '1';
if(ps2_clk_s = '1') then
state <= tx_wait_ack;
else
state <= tx_wait_up_edge_before_ack;
end if;
-- wait for the falling edge of the clock line
-- if data line is low when this occurs, the
-- ack is received
-- else if data line is high, the device did not
-- acknowledge the transimission
when tx_wait_ack =>
if(ps2_clk_s = '0') then
if(ps2_data_s = '0') then
-- acknowledge received
state <= tx_received_ack;
else
-- acknowledge not received
state <= tx_error_no_ack;
end if;
else
state <= tx_wait_ack;
end if;
-- wait for ps2_clk to be released together with ps2_data
-- (bus to be idle) and go back to idle state
when tx_received_ack =>
if(ps2_clk_s = '1' and ps2_data_s = '1') then
state <= idle;
else
state <= tx_received_ack;
end if;
-- wait for ps2_clk to be released together with ps2_data
-- (bus to be idle) and go back to idle state
-- signal error for not receiving ack
when tx_error_no_ack =>
if(ps2_clk_s = '1' and ps2_data_s = '1') then
err <= '1';
state <= idle;
else
state <= tx_error_no_ack;
end if;
-- if invalid transition occurred, signal error and
-- go back to idle state
when others =>
err <= '1';
state <= idle;
end case;
end if;
end process manage_fsm;
---------------------------------------------------------------------
-- DELAY COUNTERS
---------------------------------------------------------------------
-- Enable the 100us counter only when state is tx_force_clk_l
delay_100us_counter_enable <= '1' when state = tx_force_clk_l else '0';
-- Counter for a 100us delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_100us_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_100us_counter_enable = '1') then
if(delay_100us_count = (DELAY_100US)) then
delay_100us_count <= delay_100us_count;
delay_100us_done <= '1';
else
delay_100us_count <= delay_100us_count + 1;
delay_100us_done <= '0';
end if;
else
delay_100us_count <= (others => '0');
delay_100us_done <= '0';
end if;
end if;
end process delay_100us_counter;
-- Enable the 20us counter only when state is tx_bring_data_down
delay_20us_counter_enable <= '1' when state = tx_bring_data_down else '0';
-- Counter for a 20us delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_20us_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_20us_counter_enable = '1') then
if(delay_20us_count = (DELAY_20US)) then
delay_20us_count <= delay_20us_count;
delay_20us_done <= '1';
else
delay_20us_count <= delay_20us_count + 1;
delay_20us_done <= '0';
end if;
else
delay_20us_count <= (others => '0');
delay_20us_done <= '0';
end if;
end if;
end process delay_20us_counter;
-- Enable the 63clk counter only when state is tx_first_wait_down_edge
delay_63clk_counter_enable <= '1' when state = tx_first_wait_down_edge else '0';
-- Counter for a 63 clock periods delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_63clk_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_63clk_counter_enable = '1') then
if(delay_63clk_count = (DELAY_63CLK)) then
delay_63clk_count <= delay_63clk_count;
delay_63clk_done <= '1';
else
delay_63clk_count <= delay_63clk_count + 1;
delay_63clk_done <= '0';
end if;
else
delay_63clk_count <= (others => '0');
delay_63clk_done <= '0';
end if;
end if;
end process delay_63clk_counter;
---------------------------------------------------------------------
-- BIT COUNTER AND FRAME SHIFTING LOGIC
---------------------------------------------------------------------
-- counts the number of bits shifted into the frame
-- or out of the frame.
bit_counter: process(clk)
begin
if(rising_edge(clk)) then
if(reset_bit_count = '1') then
bit_count <= (others => '0');
elsif(shift_frame = '1') then
bit_count <= bit_count + 1;
end if;
end if;
end process bit_counter;
-- shifts frame with one bit to right when shift_frame is acitve
-- and loads data into frame from tx_data then load_tx_data is high
load_tx_data_into_frame: process(clk)
begin
if(rising_edge(clk)) then
if(load_tx_data = '1') then
frame(8 downto 1) <= tx_data; -- byte to send
frame(0) <= '0'; -- start bit
frame(10) <= '1'; -- stop bit
frame(9) <= tx_parity; -- parity bit
elsif(shift_frame = '1') then
-- shift right 1 bit
frame(9 downto 0) <= frame(10 downto 1);
-- shift in from the ps2_data line
frame(10) <= ps2_data_s;
end if;
end if;
end process load_tx_data_into_frame;
-- Loads data from frame into rx_data output when data is ready
do_load_rx_data: process(clk)
begin
if(rising_edge(clk)) then
if(load_rx_data = '1') then
rx_data <= frame(8 downto 1);
end if;
end if;
end process do_load_rx_data;
end Behavioral;
|
gpl-3.0
|
e29d2390f539b7c3d1d2c5b28c535d34
| 0.53815 | 3.973385 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/dcr_v29_v9_00_a/hdl/vhdl/or_muxcy.vhd
| 7 | 10,361 |
-------------------------------------------------------------------------------
-- $Id: or_muxcy.vhd,v 1.1.4.1 2009/10/06 21:09:10 gburch Exp $
-------------------------------------------------------------------------------
-- or_muxcy
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_muxcy.vhd
--
-- Description: This file is used to OR together consecutive bits within
-- sections of a bus.
--
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 04/06/01 -- First version
--
-- ALS 05/18/01
-- ^^^^^^
-- Added use of carry chain muxes if number of bits is > 4
-- ~~~~~~
-- BLT 05/23/01
-- ^^^^^^
-- Removed pad_4 function, replaced with arithmetic expression
-- ~~~~~~
-- BLT 05/24/01
-- ^^^^^^
-- Removed Sig input, removed C_START_BIT and C_BUS_SIZE
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Unisim library contains Xilinx primitives
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BITS -- number of bits to OR in bus section
--
-- Definition of Ports:
-- input In_Bus -- bus containing bits to be ORd
-- output Or_out -- OR result
--
-------------------------------------------------------------------------------
entity or_muxcy is
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end or_muxcy;
architecture implementation of or_muxcy is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Pad the number of bits to OR to the next multiple of 4
constant NUM_BITS_PAD : integer := ((C_NUM_BITS-1)/4+1)*4;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-- define output of OR chain
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Carry Chain muxes are used to implement OR of 4 bits or more
component MUXCY
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
begin
-- If the number of bits to OR is 4 or less, a simple LUT can be used
LESSTHAN4_GEN: if C_NUM_BITS < 5 generate
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to C_NUM_BITS-1) := (others => '0');
begin
BIT_LOOP: for i in 0 to C_NUM_BITS-1 generate
FIRST: if i = 0 generate
or_tmp(i) <= In_bus(0);
end generate FIRST;
REST: if i /= 0 generate
or_tmp(i) <= or_tmp(i-1) or In_bus(i);
end generate REST;
end generate BIT_LOOP;
Or_out <= or_tmp(C_NUM_BITS-1);
end generate LESSTHAN4_GEN;
-- If the number of bits to OR is 4 or more, then use LUTs and
-- carry chain. Pad the number of bits to the nearest multiple of 4
MORETHAN4_GEN: if C_NUM_BITS >= 5 generate
-- define output of LUTs
signal lut_out : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
-- define padded input bus
signal in_bus_pad : std_logic_vector(0 to NUM_BITS_PAD-1) := (others => '0');
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
begin
-- pad input bus
in_bus_pad(0 to C_NUM_BITS-1) <= In_bus(0 to C_NUM_BITS-1);
OR_GENERATE: for i in 0 to NUM_BITS_PAD/4-1 generate
lut_out(i) <= not( in_bus_pad(i*4) or
in_bus_pad(i*4+1) or
in_bus_pad(i*4+2) or
in_bus_pad(i*4+3) );
FIRST: if i = 0 generate
FIRSTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => '0' , --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate FIRST;
REST: if i /= 0 generate
RESTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => or_tmp(i-1), --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate REST;
end generate OR_GENERATE;
Or_out <= or_tmp(NUM_BITS_PAD/4-1);
end generate MORETHAN4_GEN;
end implementation;
|
gpl-3.0
|
3019d23acc3ef1e7956fc4eae01e2336
| 0.406042 | 5.04922 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/MouseDisplay.vhd
| 1 | 11,892 |
------------------------------------------------------------------------
-- mouse_displayer.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains the implementation of a mouse cursor.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Mouse position is received from the mouse_controller, horizontal and
-- vertical counters are received from vga_module and if the counters
-- are inside the mouse cursor bounds, then the mouse is sent to the
-- screen.
-- The mouse display module can be also used as an overlay of the VGA
-- signal, also blanking the VGA screen, if the red_in, green_in, blue_in
-- and the blank_in signals are used.
-- In this application the signals mentioned and their corresponding code
-- lines are commented, therefore the mouse display module only generates
-- the RGB signals to display the cursor, and the VGA controller decides
-- whether or not to display the cursor.
-- The mouse cursor is 16x16 pixels and uses 2 colors: white and black.
-- For the color encoding 2 bits are used to be able to use transparency.
-- The cursor is stored in a 256X2 bit distributed ram memory. If the current
-- pixel of the mouse is "00" then output color is black, if "01" then is
-- white and if "10" or "11" then the pixel is transparent and the input
-- R, G and B signals are passed to the output.
-- In this way, the mouse cursor will not be a 16x16 square, instead will
-- have an arrow shape.
-- The memory address is composed from the difference of the vga counters
-- and mouse position: xdiff is the difference on 4 bits (because cursor
-- is 16 pixels width) between the horizontal vga counter and the xpos
-- of the mouse. ydiff is the difference on 4 bits (because cursor
-- has 16 pixels in height) between the vertical vga counter and the
-- ypos of the mouse. By concatenating ydiff and xidff (in this order)
-- the memory address of the current pixel is obtained.
-- A distributed memory implementation is forced by the attributes, to save
-- BRAM resources.
-- If the blank input from the vga_module is active, this means that current
-- pixel is not inside visible screen and color outputs are set to black
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- pixel_clk - input pin, representing the pixel clock, used
-- - by the vga_controller for the currently used
-- - resolution, generated by a dcm. 25MHz for 640x480,
-- - 40MHz for 800x600 and 108 MHz for 1280x1024.
-- - This clock is used to read pixels from memory
-- - and output data on color outputs.
-- xpos - input pin, 10 bits, from mouse_controller
-- - the x position of the mouse relative to the upper
-- - left corner
-- ypos - input pin, 10 bits, from mouse_controller
-- - the y position of the mouse relative to the upper
-- - left corner
-- hcount - input pin, 11 bits, from vga_module
-- - the horizontal counter from the vga_controller
-- - tells the horizontal position of the current pixel
-- - on the screen from left to right.
-- vcount - input pin, 11 bits, from vga_module
-- - the vertical counter from the vga_controller
-- - tells the vertical position of the currentl pixel
-- - on the screen from top to bottom.
-- red_out - output pin, 4 bits, to vga hardware module.
-- - red output channel
-- green_out - output pin, 4 bits, to vga hardware module.
-- - green output channel
-- blue_out - output pin, 4 bits, to vga hardware module.
-- - blue output channel
------------------- Signals used when the mouse display is in overlay mode
-- blank - input pin, from vga_module
-- - if active, current pixel is not in visible area,
-- - and color outputs should be set on 0.
-- red_in - input pin, 4 bits, from effects_layer
-- - red channel input of the image to be displayed
-- green_in - input pin, 4 bits, from effects_layer
-- - green channel input of the image to be displayed
-- blue_in - input pin, 4 bits, from effects_layer
-- - blue channel input of the image to be displayed
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
--library UNISIM;
--use UNISIM.VComponents.all;
-- the mouse_displayer entity declaration
-- read above for behavioral description and port definitions.
entity MouseDisplay is
port (
pixel_clk: in std_logic;
xpos : in std_logic_vector(11 downto 0);
ypos : in std_logic_vector(11 downto 0);
hcount : in std_logic_vector(11 downto 0);
vcount : in std_logic_vector(11 downto 0);
--blank : in std_logic; -- if VGA blank is used
--red_in : in std_logic_vector(3 downto 0); -- if VGA signal pass-through is used
--green_in : in std_logic_vector(3 downto 0);
--blue_in : in std_logic_vector(3 downto 0);
enable_mouse_display_out : out std_logic;
red_out : out std_logic_vector(3 downto 0);
green_out: out std_logic_vector(3 downto 0);
blue_out : out std_logic_vector(3 downto 0)
);
-- force synthesizer to extract distributed ram for the
-- displayrom signal, and not a block ram, to save BRAM resources.
attribute rom_extract : string;
attribute rom_extract of MouseDisplay: entity is "yes";
attribute rom_style : string;
attribute rom_style of MouseDisplay: entity is "distributed";
end MouseDisplay;
architecture Behavioral of MouseDisplay is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
type displayrom is array(0 to 255) of std_logic_vector(1 downto 0);
-- the memory that holds the cursor.
-- 00 - black
-- 01 - white
-- 1x - transparent
constant mouserom: displayrom := (
"00","00","11","11","11","11","11","11","11","11","11","11","11","11","11","11",
"00","01","00","11","11","11","11","11","11","11","11","11","11","11","11","11",
"00","01","01","00","11","11","11","11","11","11","11","11","11","11","11","11",
"00","01","01","01","00","11","11","11","11","11","11","11","11","11","11","11",
"00","01","01","01","01","00","11","11","11","11","11","11","11","11","11","11",
"00","01","01","01","01","01","00","11","11","11","11","11","11","11","11","11",
"00","01","01","01","01","01","01","00","11","11","11","11","11","11","11","11",
"00","01","01","01","01","01","01","01","00","11","11","11","11","11","11","11",
"00","01","01","01","01","01","00","00","00","00","11","11","11","11","11","11",
"00","01","01","01","01","01","00","11","11","11","11","11","11","11","11","11",
"00","01","00","00","01","01","00","11","11","11","11","11","11","11","11","11",
"00","00","11","11","00","01","01","00","11","11","11","11","11","11","11","11",
"00","11","11","11","00","01","01","00","11","11","11","11","11","11","11","11",
"11","11","11","11","11","00","01","01","00","11","11","11","11","11","11","11",
"11","11","11","11","11","00","01","01","00","11","11","11","11","11","11","11",
"11","11","11","11","11","11","00","00","11","11","11","11","11","11","11","11"
);
-- width and height of cursor.
constant OFFSET: std_logic_vector(4 downto 0) := "10000"; -- 16
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- pixel from the display memory, representing currently displayed
-- pixel of the cursor, if the cursor is being display at this point
signal mousepixel: std_logic_vector(1 downto 0) := (others => '0');
-- when high, enables displaying of the cursor, and reading the
-- cursor memory.
signal enable_mouse_display: std_logic := '0';
-- difference in range 0-15 between the vga counters and mouse position
signal xdiff: std_logic_vector(3 downto 0) := (others => '0');
signal ydiff: std_logic_vector(3 downto 0) := (others => '0');
signal red_int : std_logic_vector(3 downto 0);
signal green_int: std_logic_vector(3 downto 0);
signal blue_int : std_logic_vector(3 downto 0);
signal red_int1 : std_logic_vector(3 downto 0);
signal green_int1: std_logic_vector(3 downto 0);
signal blue_int1 : std_logic_vector(3 downto 0);
begin
-- compute xdiff
x_diff: process(hcount, xpos)
variable temp_diff: std_logic_vector(11 downto 0) := (others => '0');
begin
temp_diff := hcount - xpos;
xdiff <= temp_diff(3 downto 0);
end process x_diff;
-- compute ydiff
y_diff: process(vcount, xpos)
variable temp_diff: std_logic_vector(11 downto 0) := (others => '0');
begin
temp_diff := vcount - ypos;
ydiff <= temp_diff(3 downto 0);
end process y_diff;
-- read pixel from memory at address obtained by concatenation of
-- ydiff and xdiff
mousepixel <= mouserom(conv_integer(ydiff & xdiff))
when rising_edge(pixel_clk);
-- set enable_mouse_display high if vga counters inside cursor block
enable_mouse: process(pixel_clk, hcount, vcount, xpos, ypos)
begin
if(rising_edge(pixel_clk)) then
if(hcount >= xpos +X"001" and hcount < (xpos + OFFSET - X"001") and
vcount >= ypos and vcount < (ypos + OFFSET)) and
(mousepixel = "00" or mousepixel = "01")
then
enable_mouse_display <= '1';
else
enable_mouse_display <= '0';
end if;
end if;
end process enable_mouse;
enable_mouse_display_out <= enable_mouse_display;
-- if cursor display is enabled, then, according to pixel
-- value, set the output color channels.
process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
-- if in visible screen
-- if(blank = '0') then
-- in display is enabled
if(enable_mouse_display = '1') then
-- white pixel of cursor
if(mousepixel = "01") then
red_out <= (others => '1');
green_out <= (others => '1');
blue_out <= (others => '1');
-- black pixel of cursor
elsif(mousepixel = "00") then
red_out <= (others => '0');
green_out <= (others => '0');
blue_out <= (others => '0');
-- transparent pixel of cursor
-- let input pass to output
-- else
-- red_out <= red_in;
-- green_out <= green_in;
-- blue_out <= blue_in;
end if;
-- cursor display is not enabled
-- let input pass to output.
-- else
-- red_out <= red_in;
-- green_out <= green_in;
-- blue_out <= blue_in;
end if;
-- not in visible screen, black outputs.
-- else
-- red_out <= (others => '0');
-- green_out <= (others => '0');
-- blue_out <= (others => '0');
-- end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
555c075cc9a440aa15421717158378d8
| 0.548268 | 3.949518 | false | false | false | false |
luebbers/reconos
|
demos/pr_demo/src/add.vhd
| 1 | 3,524 |
--!
--! \file add.vhd
--!
--! Demo thread for partial reconfiguration
--!
--! \author Enno Luebbers <[email protected]>
--! \date 27.01.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 27.01.2009 Enno Luebbers File created.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity add is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32;
C_SUB_NADD : integer := 0 -- 0: ADD, 1: SUB
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end add;
architecture Behavioral of add is
-- OS synchronization state machine states
type t_state is (STATE_INIT, STATE_READ, STATE_WRITE, STATE_EXIT);
signal state : t_state := STATE_INIT;
-- address of data to process in main memory
signal address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal result : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
begin
-- tie RAM signals low (we don't use them)
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWe <= '0';
o_RAMClk <= '0';
-- calculate result in parallel
result <= data + 1 when C_SUB_NADD = 0 else data - 1;
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable next_state : t_state := STATE_INIT;
begin
if reset = '1' then
reconos_reset_with_signature(o_osif, i_osif, X"ABCDEF00");
state <= STATE_INIT;
next_state := STATE_INIT;
done := false;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
-- read target address from init data
when STATE_INIT =>
reconos_get_init_data_s(done, o_osif, i_osif, address);
next_state := STATE_READ;
-- read data from target address
when STATE_READ =>
reconos_read_s(done, o_osif, i_osif, address, data);
next_state := STATE_WRITE;
-- write result to target address
when STATE_WRITE =>
reconos_write(done, o_osif, i_osif, address, result);
next_state := STATE_EXIT;
-- terminate
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, C_RECONOS_SUCCESS);
when others =>
next_state := STATE_INIT;
end case;
if done then
state <= next_state;
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
296b94684bcb9659808dfe9a0aa23169
| 0.55874 | 3.621788 | false | false | false | false |
dries007/Basys3
|
VGA/VGA.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_v8_0_9/hdl/dist_mem_gen_v8_0_vhsyn_rfs.vhd
| 3 | 173,089 |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
FljaF+ZK5aTHOSoz3Vm0NikqVWMDJsa6B0n5auKkcpK2yfoh4NMkFSOGE7i5hT2G2OmDqFCWm9tc
YAtAWO+FxQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
VuHaklO7fcZbgvP/LjbDl/EkRXQ49xbJLUgv+LZx08h9iHpdX2Ad3aJUyi+Mm9SkBjkQeTn5r1+S
UG63i7k74LO8DLOaV3ZAhFR26xemCFTNJhRV4WTlZbaDLwwTwolHtox5pPvqWrwcNRDKm9g8NMnd
YlHXjrXG4dqROwhGPUI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WAq9qlahy6KlJsiHBBevZuw6t0Jp82EaHyCmJmjvHJivVcOW3KZdOOfURBNRkusEitAk1MkxNe6L
L6cmOfxHAEuRdaZIV66SXnaQlslUC+pq4qMr/jfAGJ3DJdTsESR1ZFBYPC2OjmQQSJYrsuq3Mzog
08Frm4578r9zPyPrm0LgntCsWpMTxRK41Sng54PqFpRAYq5QhuP+3dDRR24uHiQVUuazpUojsMHr
qoIx1CP9ZqTvjPRnXBxIpH5eLoDYj6bFmQgexpJ3bvvAW0WiugaGTZVovP2cvJMkLs3ZGRRaO+zq
FcUqeyIIJHBNVqylq/pvPhOFst8y5+ciHZ3t4w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Yq33ayD7wgTkUY+RWI1XonEAiab9AzVkA7dXTmOZfa7ISu17TZwSbltbMAhnr4GF4Jl3Y8HG3hjT
7bY0kOMVsdKjGf3kSU5+vTAIjgCdYljUCBTv4kT9dfjWV6Cjp5/SibdrzHrc5SJeVkq4q17t+yNg
WkIseRKbFrq4ezUzVC8=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
HXfm/AZ/ud2Y4S5qqMYsPiQ3g9n/rykDHG5PRuN+zMAnkGd8WacaI+RNCKTOz5kVKZEHmiuyVO7m
1f7BH8YYiPHdY7sTsETmBlHyDUg2KYlA9kBZNgl1/G4UfFybzqB1hPjNeDlYrx2hGl2Rn1ga2d+k
kR5dguhyx3SrvtKq8b7grLjcVoYJNAsdUWd25TxYjciRhkm6LOn5xR3KhhMzwf7Mn9IUOAtJSm5g
SDyWFCRkMly40iesFXFhz8mgoZwCWK/2uXxtKyxESDgdOF4wzmw5gPExNb8F3K3/nozp7O9hDVl4
I/hme3WpwnYqWOds8jCaZjXYkAkFo5lDr8v9uA==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
i6v3YdDbVzL18BogPhzR4t1Ahtm6V8UqO0yAPKBsHgo9MYOjFBrsCPG7wE0IZu3KCaepIeukpdPs
2i7EenNWDS0NuzR7XhYir4/YLj/TW3UNGyw8BWzcbuHgp7lJ1O6oUBgtEVjwFusGzg0l6YW0jxe2
KlNoNBiWZ6+APdl3zMTqLZUEiHw0RErAbJMWmHUC5gkwy4LoVN1MgV+1yNdbLiEVTBBAGkyJOWj6
NdxX1huqIDLcNSytSgE3qVLshELpJxqJbzOtoDeE2t+opV/i4GnmARwrKWC2T81imMwyqbKhcVYw
MbWPxDjPMyBa8uxgADiFBOwP42jGZ5pNWTt3Aw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 126000)
`protect data_block
m0oW47TYlYqGazlovl3TxO/O5Dgq2YSqzwrVkFzgEHAL/x8wVye0MZBErAoR5qxSW98Q5PzF9Asp
/vGdyCePeOnPKthaeQaJgHtBGzXMoyS8lfmglS1vieOodCAgvv48iY0WIJMLh2HNpF/xZFH4ZIBH
q9vAbKB+SSJeDt2pYbR8iLYTa3C4l6FsylCywQXsMtFD8AHdgiKE8/0bO+imWCpK3QzdHxP4U+wh
19FEqsxk7xQx4iCoDonm/K8B38nRFMjrcLQ20vrAi8IClpI5D1LCzCAFuhAmp5srwpSfbbupCGSY
XkEARW81iQPP8M51s0zZ5/QHAwEz6HDs/NhzOeIWxqB3PCTnXS/eH906n/yvNjJzooJ5Z6Lb6RUX
BHeP2XMruRB/5HSjiEU0RV3d32RbgIQMGUJjfeg7f1ZqqBhlrNFwlT6ub+W1F8UP6019lRwTlfVo
IB3OrND9imve21zO8/Eo0QMmVd3DuJz4Ic+bw408n74ImM+bC8fnf6kKX5rl9sMO+cIuTvTo8wka
wTqsex9g5JZwLIDfNmmNfum1BRLfnc1wVe0V5R2D4pVz0GhufazhrUQtQQnaU+4Rb2DKe0qxl6k5
6ICVsCceo6sP6HSrC5eZp2jMRCiW88nu5+akAxMbU/RMAh/HJMc+2Vb6oCdQBuvLL5kOA0ULwwt/
AH95dOCz/dMXkW9HWMgJKskjLgPtL/afJHkPDDzk20O2UixRidRqo5qcQuaiqbVyGF0MaxrkuWFA
zAOUxi3vp9hSHjvas0pHT9PEA1CDWqH8ZLueSBzbzBZKANtaZRzT9Z6G9Qvd6WiWdOvBK3IRmZZR
cu0Fe9Rs/hTIyeQaWV19Um6Rd706OPiAFKNEzpbLxfd/DKfs+EZ6qUTEghbR0ORojeWDJ8uOwi1J
LdK06y2T/phgbP0A2/N/k6+A+os3SkwQhRy27w3ihvtKjsEdyvxDKrx/f1Ay7glqCNNFbzmDlwSh
Aso1IS1IEOZju+hSMgizT8tf1kscCtJ+7j0lhFi+a/secZr5BIHHtIHvsux++V+AktGUkxGb1zNQ
z1438aZrCvELOd2S20tnL5vmxLkJnqAZjnJNBA41v71H44wHaESZ8wXGO5yJYCtpK/9S6IGuzYdp
tiPmezIcOuO5MWyiXY9DePBq3qgPGLNGPoK6k30Ol7QwR7qVCJ1O249vVraQejquyN1+10c09jKd
lKP1zhOTrAGeP0tEqoR44m0k/3steQZz87Zaw1+NavUOMuHm6tav2yGdIv1Sm9g1cB3OiItamzNt
yOzTm9f34fnghez1xnsRj/Hnx/oF1GgKGr2yXVHfyaDCQ6ortQWs8vZxngCxslJzxz3cxv4VzZ2V
AgRgVdzpfz3046iixpXur7rVKoOMQJZ+ZgrNyZkRUUcJi3/7zYhdvmxg2FLIwTHz5hXykAcLuy88
D+QUgRk8WnpXa0BeeLwtYc1U4HD/FqwOuPmL2H0MGZnqQunO+gBigTItKKaqEQNpA4JNGcPVPX4i
1bmx01kEhQIZsxHgxM6USvDpWNQ6bzfp3f4ZTGzCMxWgcdyKEsOxjTGm5TSd0QEGuE9tSf3sk2Wr
AefPwlw3qoxKUzq1XN1gZ139vmVg+c/HFQ3uv6WSWZGOHTgCSP0A0zPT4FxMRhY00GwC7lqaH/7x
/JVlp/0cfZ+DJnA4xZQ9iYeA2rJa1ZW1oRvagyenUBCUsnkKnefUpfCSrat4P+6PpFqUN0yhIgCN
E+ryTzuSYE1rz03ZAAJfAU5tCgTZAIObB41R8FX9RsP1+j6eoZDCx+OqI+tOBk2zGQd+lygAe/0U
8OJXfs2HSKVJF3Om2kwtGq6rdIw6Ckswb+Kh8+q2+Oz/DGucrAky1ZYBjUpiLxZV1e4lZZRniD6L
bjipJ2kvi0u6icH8CFd2eKPjSAk3FKyq3oyvezsZizJkPr4fWbe0RnkZoEoTG3DbW0Kr7E6um4QS
DQ9FLaGKcV9ofwt3dCYhjNifIVG2pXwX+8MAvbPpg502YbuLygzbqoSxEuTDEMqEnsTXUsMIL4ii
uRbgyK+0wDywu79nIFOEkCJJMP/SjahtcbY0MIShz/SsLyftQTQfQJtjZxqsbrTGg6m5snMnj5NQ
t72SlGmj4+IxWYQZEkWf2X0zsIRbFWkG84ieoB62Ohfi71PtPhQzRuHL101d3BrjZLf+MBdUTp6l
ehepesC+c2PpbF6UNRsSsZNvqpQx7d1/Q2zqvbynyJa/Jj98dX8/qRS1LLWfL9o5Grdjujd1xMOQ
yocDZkjh516vda7Q6/69PoyELAHKQyj0owLt/n0gSq/tsT8Yr0jH+WHKDC1pCM9t7+K1Plyokzgd
dmivQH6tUA/fDTTHcRwbBBN4b289hgE4dPbdp6A4eHa8a29IAg8OPzDdBpdVv60FigkfAgpl7XZ5
Y0I/9FDeNzMhRo+EU+hCDYdEVcZDNDjQGfxwns6WMiKik4VC3jYscvmA/qK+cI/lVupNHyJ9MSTI
jm+sM1g1vQGZl0Arn9qynMk6gLHB4rFnSOJ694FGOZz8rrCYiB0yWrCzq+1B1FgceniBes9HRgZT
6xw9KwORwiIc8lwraW5QVeIZqGtEeks7Be1Km8RKcOkOTyunq1hkpMFllvLS0Mps/3D5XZXaSlLa
E5iq1WW6lpWFST4Fri1pBwPVHWktruQaK3OZwcXepIaXx3Dy1yc0fB3N6TWzjIFkzDUmQ2Zq7kNT
N2xGkfQ8g8mGmg0OjSuSBg7HjauS0HFxHA7/T6Chq4YpVuksce0TzkrAtwBXqhKlZt5K1EBSGqmy
Lpa92eRNk7NtptRs1Lez6Sskx/qcL2KEzspp16Hlj+NcOq5o+4/+9Lky5YyAutUhsNVc+z6+3R92
XAANd7vpRygKhAU5OO2wVsjAQeHcD9KavY1L6OudB5iVLhO22VLUXC4UIHF4X1tuSzLYseo1UnlT
Il28nlMt6UZV+jtd1cBOsNUCYXp5o5pwhSHMd9hgsgXgffAAYnnN24ck6oaSX0hbgUqnNpqm1Dt/
UCBpXWyZ5DzOWVwsKGEh5Kq4ZTYz3rtnbxJiQa1sXxDSMDa627Alk4o56LbYn0x5S1qxFU3Q8W6k
mhk2dsHcAwlBwzq7lTIH+KPiSI7wdSRKfd66L3zAtYAovqDX29Aat7YnaLbw/j/mnbqOCMZWpJ45
NlIU7/xi8JG5e0NNm18ET9PWr8tTczvnWm6sbA0ocjakn4ttJPCe1HBSmJ+SyY4WTF3T02d6icb9
mL0aI24dPmkKutaop+4d+Ku6RpARzsWig/aAdzFeuavDOVrga2F0OgdoK5bQmIStgbJ9fcXMVSoi
iN49UviRhSoIIaLxsOoiRg5S4GH3olJ2XLoh17ctBr08xqGAVKyPkxIDbCjJebLY7N4q7/SB9ySR
SMXVM08Mjv46DLj9C/PL8VoSAnF2OKzVpRUoiHiigie/Bcm2So5WoDqYQ8i8D0ckj/DB6qhicvhT
UQtnoI7a6oAZs5fI5ggIVg5YhR0BkpevG7tZ2MmEYFxl7Mg+Ohnq0O+q1IPEMdjE002KVKydNfxq
xqpw57Dk0K+6MdANF2R8zytf2A2m3GtPlT1ZaX37u4zAbDuAJtqB7ReHFuNPW7MeNeA6jNSLJyS/
fS4HfvFiqvnQH+63kUlp6t61686vXXwkZrAb5i0xX3ob9+eGj8bdQGpg0xMAQoCMLRqfEkGRsiat
hKOlBAEz9qihQz+eGznjWLClgwhxWJC/uNMVXHetfeHbEADsySqXnQUSigOWRza6pbWuwv6k5gJe
rTGAb7OOFPjKw5IU87JA7K4q0u6pJ7JBn5OlMjHhtliieuo7cuU2UzQjpoOXH/s7cqn3Qm978FVu
1DyQQYNKE33/BzpbDontOsm0VFpKU3TBxiOyZu8BqFT10XsiVG+a9rbPujhABlZuQ9PeogeU02yw
ltTQ8o78YOx9uviVi9Vr8OvqR6cWzbIOYedUCgzt3HQTpiVcjrV3cR6+I48570SJyD+kp6BHHjqu
3x/6PNydrQzTFeqpKYgPvCUeFPv/Xw1t8rdRZbxkRIWHl50BgVfQWz7W69Jq/VPqW8Ya5uv4MER2
ARqTwNTEXzfkrexC6DDCelVsI8kwKVjY5FAHi58EtrrsPJU2VGpmYXoWNnT58ubA3kJllKcwJLbI
r7r1JOo2mAT1VsGfjrHAWyDMCMgVn1SJQc+d/9/ncHh9h6xfRb7rxhbhCRzUirInVDtpigFKuBIb
a7HFWr3X2QtK9f4cBS89GGqSqGcsoJFPjxf30AQHCRsnHf2+NtrtDusw02H5xHfW8fUkaAFgReeC
DqKCBFwTu91grrz7Sgy/tHsJVU+MHlVqL57wuep944in1O1iMiFnrcBVjU5n1hdCz+R3Q6C4EQRC
0sHFh/IowAzfoETKK+SrCLFGKTugNKxy5Oj21LoMCNOFQjiqe5+0akv90EPU9X4iIiHHGkf3Znrc
gY8V2QiqgfmQOj9L6HzmcMmPrI0eq6VVTBB8+CVWgdA/UwesPundjJ34WSrQ/xkf8/ec/da4FSVt
AQwoBx6k4tsYt7ZL4dwuVyHzygA5CT9u4OHmNC3OAPrgGp8wx3w9qwgE5uX+xS4fBQgBl3dObjhc
nHL9IFhDECxJMOZ9Lv0UbTWwM8yGVPRGs1gIGz9ZTFaEeO7XrCKaDO9zP/b1IuqqCch+PWt/0l+q
ebh2gg499o6/Z/dMm+vrNG0l5qSWKFUbQLdo6daXpnVFX2E5UtkPPYtYljfEQlegiuHsPRQw/Dvf
oUnHCi6aayhBkRJPsDnkHQlp7Zu8DCxmCBtp9D7sZ1McGPj1O6pwccA/H0CuTuQaQHLW0VZHqEjm
jh0GASSXDE91oUzygX9B1i0UIKbILn+dvXW+1lqR7saCEBsxf3oipDCmwJjnEc4c89ycIs9wQjMx
jR/gr7BfJ3TwnPkrxZj6aUbqiUdRUCK4m2pr1x6DJX5ZdUwoPpaT9XP2Yco9K77PYOw6VOBV1X4Q
h44VHPFSgIqOg4xNsWHlG9yvEahazfKBc4D1NvditoR67CXoYpGlslBuy3D60NeO3BmwPyUdgyBq
PIE6CunrUlzGwS6IYmmZAK+JCG/RSWtxEtLmrzlzLhqOGRg7RduDlD9wORTt8OaJYmw070Phawg7
x70+rlKLa1N77UiyaDglLBLpTusEcC30clGkh35Uc5Z+IC56MLzymA62tzykbkiIHbcxjiA7cfDp
7ZGvQwOJ3SfmvBbS5D+cDvsVCrwKCJv66zIntOTthMtYDQEB/Xg4wc6hVaTlliNyHuJ+gPXvKh4R
3reEgEUnTyzjM22Pbb0IEo8DXr6L+J5jmZvzEkYWYCmSDt41SDEyjyDWt9FYEp7a51x8btchm/BS
BAKeH9wp6HqoRzaWqYuDRI1sIJL8cYbn1cuTJTPwqkrp9sMdhq5PINfVB12O7phWPBgjFj2zTmVs
UgqH1N46mAy233TNdBhyp2xztx4dRdAwW067xwaEQgtO2J3cR6vKgJYqhDQkEfmFbkB9rmo/Se8e
hooDCCtQrGfou/ggBgtxDTwDV69uCP571Werw9eUfC25Zgbxlb2L/dmPYDhBmjkOHr4WeSN7AyPI
wCQfsCYEpxbV9MeULxFzai1Xf+908yWWls4P29zSy21gzmb5EuPOkxYF/USKjnhMzRyktfjVF4dN
4OGcFDaVkRVtx6zoqWhIZLuqCdVWaZAi2mrI/UT0YyK1V2PapuZ1SVbpxSHmJbQPmau1HjqzXlUd
MWvUKlVLeFNEET7XZN+ERfxsnGTlE2lYFW48ddvTLM486gQV7QO5fQFw2+YiwFK76PY/Auu6+58j
TphXIen8e71IQ3khRPn6ndem4SQFUA+xk7eM8Ci45FQkzuoCM+4D1PLJW998gYO5ZVZL5I2PrLxR
ShRvb4u0lUmgwLfeeAJp+I+PZr44k+S8/cHL2FsgyLP0zr4B1n9jiiDdjKwUJlcbwDe7OukzvcI9
aaT99iNcSc/6+WXYcGE2bOvTrpbYkNpnOVEFN8ipJOM7cdRi50y1zSr9Iv+KjLhGXn99JcNqqeO+
U+0xa/wbkXDhcNf6eA/oGlJbrpskFJ8W+8mruGVPloNF/DHvo9klGF4LXEzilA4wSLEgmL84Tgx5
0EUaGxX7lMJQr1NLfN9R9fLm4ogZyTS8Lcos+3/756uvQH1wzTUMQgZWua0UFfohvp20MGo6QNXv
LDipoHtl2m0XMA45IahnbIfL2fHNeE5E0sdaM0L0Ph/76lhqbJofoFe8TW+QQKs0JZ8XATQWnJFG
JLSUJ/W4pdL45oP55i3Vp9AB7duQHRtZ/0e3UEs0BDSK3PFqTGmMO+/fur8DrsO0ifI+FRQG+rfu
ZvL5T794pfTsl77bU+CIk8WFsIWax4jTeGoI5HTdwi0YrvOVPLjoSNTzZnqIFj2rMl1qNjOlFH3s
HYN9Zu/tXw/QvIfiibpydpW6mheI9XxTHCa7A++lVAv4G4lhLwIVEqVnWkGueBbKBQyj6v3gqx6H
gBR94dltEYbJqPI75c73Rb4Ult0Rgredaz4MjKinKJ/otoY4SdA39FqmgHtrd4od1GiBV4ElagiE
ZpvdglejyomZHK4qgDQehtASxMFmj/5sPoi0IbBJY/AQcu0Wa5YLF3Ib6ihzQaZOHiqQTQgvXfwR
Mu8Usw9P3D8zWqfwKshF8tFc6CqyAVkiJDGB/O0GpaWcdviAQCewSB6Kj8PQ0mCHYxzbpLDvlxNg
FMOlxCepyYn/c0Agw9Kn4H4XlJbkvU9ihtYrDHrj8UqqqIo9Z5sZVuqeBiD4Zramj1EQyRRdSgGg
2NzAEhpS0X+MNO/FQ0mmkD6BvoGku+WRNTiZtOKXgtyJMN/5+11eXfHeK6szSiUA4GLPX84Lx55i
DPfvNn1MgOcXzTIKo5PPHBBQSr7lhL8cHBuYx1WoKdjeqq6piQBHfq9kes0snk7dKh9dgtRZX3kT
fpW3L+ENo1mauLEkvqbYi/yDDGyunHaoE/hCEfi9HzWA+txt4Y0S0zDaH+y5aqyPFXXnag4Wv1if
FwOiFf9vtxI2QyZb5nZR/iHZA3QZBSmIGAVv/5SB9Cks8pNCfElUb2gaPeldgi8mQ0KAht18MPuA
nsjzt536huHqc7dpeXyQAeFsv4UTSDONr5WzWmS0N998N5+ILYtxp4e+M4nvMEVehpCck+HhFgo6
g8vQBRNoLH2pc1VCKY410dE/oCZtYXy1N2Lh9q8bXNcKQ7EhUXgPnrKQx1ketHrZiLCz1qnOfwZo
SLgm6dni9xSrgwVrTjq7ydeiKbXTnMgNpG0/EQy7a3KgUH72B305CnGpAP1qz2J2g3+ZW7ye1z+O
bm7PSXiEp2AtJPFv0YAVTseT1xts2fxN69MEy2+DJcAVdsNt8W/Qt1AEKaiRgYxPKb5YWQltwltD
ClWhLSqQNZb0R3h9nUjIJ0+1McrbdDP1dXM2npM3DFQVXXRweUJ5bU3c+nQThMLV6QLQoG63hwr2
10qEUj/0xsnoR5+EGokIcGPigSuib31DnflEEid8s2I5pd0PLyQQNK69vLKVr0f3q4/7qeiPNhVw
kQpUnuVhOav4LYcUwM1K2ydT5SgU/JBLbJZo/SRxtNamNXGwn0OzEZT6kXByu66y5GSd8ucuy8uk
PxhIlylXCdZCZQ4ZeNnnT6U+z/o5E8woipM/ALOAkI0H04Yry/T4m9XWISM4W9CwsPdj9cDlfE9k
Fy6tAPCEQjFAgiD1qMykpzmueYhk3dgMiGRvmUsZumaC7BIkx5MsrUrr7GaozK45TTmHN73UUfWn
5/H+bLcJY2xQ+FXunSdNevdQi9R4ovQCgXGO26lFZwfN0ozuaKNJgnQXMJ1YfOt2GedFO7VeFZXi
PUJCQFYhKhDtlfUN49xBdvkfNdE4sbJvrHgdQf5ynS/wIFo1gDV2vNMMLQxHuaa1y3koe2jxQtxi
nKvVWZaZN3Lziv/26SnexlTd5zyNcb895xA76msu6kO71rBZpeos9gIi5sLHiwwstGR6srWHRY3r
jwrE60Qro+86oKjsRzVsKGCw1/OkxHdOghJUEshmQeDmeDCz3LIcT7UEI6Vy9R/uCB4ET/4DlgoB
Iw0DJ9hVOe9wbvbokJ9QY/jWnCqUg2fxCM2NMgfhAZb1VHuE67CR+5wQM0JWrTWIFDYB+YFIdbEl
NVmpoJPfjc93q7H2ZQHyz/7teHyiGFajbh1e7NGCqpIh6RKeLg1fN4R0qze41+z9uVBSUR3rb5g/
wPzh0CBKnxvSWYg+UXBnASrvz2dA56DUxsyYi6flSD1lI568wKwH8xPqBCijIq7cEK4MQFETjchi
YjKmhV+TuBOPAnxkqoeYaxmSbeTrXEXTJD4QAqh0BziPRViFZlgHOtP+DvWjZlLIb8V/yCM3zOPu
GP4CyPDjwboeMHScZ3/LATupt/G1iIr2+sH5OZfK1nnSGM7KNLqyaHq31cAthZsyuIQMSBrGdK/7
TzMcJN+W6UvTLydIKpZaxfyhiDGpITqUj09Gj8Vt+vPB+4DrSxP09yicQRWMh1P64lZubaBWj1z3
o86MyaUEImpZnCe2TEUaijryZf171athZzpGrUXuGzpmmWO/2zwCo9r/KM8lCNlmrOLqYfe/uSSE
m51u1tjBn06nSfXUaM7wYp3Wmy4czXhVYu7f4/kjht6W973RVb/+bVSNmBfRNF0UnVBJvR0wkxpa
92d2BnE58vSBbmTluRj6nnQpb0jopzGyfOFe/fZe+zxeczSGew6ccbf3jV6bDQVfvx0PcYVdh926
vIVqlFLLBYOrLXhzIPpPytdC4TDAM96uNM9FmbHlT7Y41uk1vSQKvz4ivjULpeF0At8SwSrRsMMG
9dT4oEwKcsRkTe3oqUZOBwafSsXY+sxjxGUkhrc9eTAi+2E1OWJ3vO/x/WqNKXp2SjD3V3CJRdny
SZDoHpgm2kFr8C7kTc6BVe5m/2sA8FGVZBR/xX4sgNb3FoROdM56S0PRldnx5SWDjVVJAbpkaNia
URK1W98HF4keruPMnW3Fx4kfcV3EM2zGGK9oQk9QoCssijuhfHIe/cJ/nkL/s+wk7s+5TKxd3B3A
kx7+5xtDV9yKQvEDvTfeVsSpr4PAL6hJv4kguwtG/gpzgg73ClHkn6aKk6YiNkUqs3KE33nmEiS1
PKNR38ifl5yGBcUtlY+vsZhWj8GZm+QUMNjVtn32LXs1+rVJCetS/KuSxCzGhsHpzDKMQAIMcwDQ
Tu2a4maDhr/ybYRbTWKvHzCY6MpsI4YzG07iVgXC9THETXrGVWKXaHjmljD+wTBUY6bYda9BMQYl
5f5eDLc3fSI5Ve997WrD9jYE09J16qHlmacou3O9sjoKwnQQ/FDjd7eL900nSiMDsRbiUPgH35Lo
cv8PdGrAjo2GTd+hqO5R88eQjcF+gScJDVGx04DSV3A5hs2MRCUq07qcRzG2DWNJGVmaO8AYsj8t
ZTA24zKnpyVrFTgmraZ83I4rM5xkrhSV+tV6rlE4cAhanDdi/qnyhTTHEu+QbwAI7HPjOY4vBGCJ
UE8aIotaSy0SQqz6l8pL5WkE55Kn94V1XciVr6ULQYDiBA4NLNzbW1LaYRmmEn8r3OXctUh/VwM0
eVVpb4xoVJGSOA3GW33kDoROZjsxo425znA0LDsYQ8cHh5aIcReexxkAr9lEPWHIuD+M1r+F/jKG
IG7LVHNGDdLYEFeu4vnv2YsOLHHIa12X3fWEiIYFo8GKwOWE+bOrW20gn3aIwbeyfeYeTjlkTdKe
3biBcuKO+6XM0BNp7Xkjch3ZJoAVm+KZcPkowpRfnT5Fgmms4A73hACK4v+tlJhJcHb1j3LuT0yz
SBEM+VJGsZxiat3LbveE9gKzHIXKIrjj3t9/PAy4VtLsUedMe9zAL36GfVCKkcZ82Q94vfm1oIM+
VqVZWj0y7cYF5/znkbs8e/QgjGG0AwVXgaz3LnVB63FBNFxcY2wboKhAMoop+bXHQGJNI/uzCb/v
ySNuUYBfqihyjOxxfwNUEoP0r8pkRsqBJqswR1t+WoR4D7sJbhxommQbjfS17qf/u5xtex02ozpP
G9+aAUJ6SusIcDc0fORI9+nhMQcB7JmLAqbIzEb+cCN5NEjKpxEWlggWaVAW/Eop8HRMqi3lm359
qTrJ34tKrbxlFM6defdmui5X7S2+3hGVNpyJ3z/pSpKgKVqbnwSThyLTtn0z3q/nI15S6ulnVVJl
mJV+oHjpcuK/H86H8LB3uARx1U+MTEO4g78QYsGhHu49LN52O+n0vH0u5sYEYQDCLzOKSPnYWX46
/2i8t9PiqO6cZ2hkVi6tVjLqb6V4XqnUAANHyvmdNiU784zyWfnMuTLOAIXbQFRUpKbZ8SYAiakB
+qCFmycqFoMTdwlGjN4E0tKm9szSWjZ7fILzYfmc+fdHNqO4ZGP5pGaaBsdZ7lwgw5gy7sYhUjwC
RLhCSGk0LL4o/RyJSW6XhgepELQrEmgb9mox4HuM2vQsvoFXO5zoJnkV4FYjYE6r/WqbbeHVseIY
UpZZBKlYUJPcHtT78hGccCzPJfldCDQro7hisGLMGZMZd3HzsPYcAXG2Jvr13Xj9IxZ6fard2ieu
fpCLnCjwEGMP/dhKmZf8EstIWV+u6I2BB8VdyAo0+6Gn6G4a+ZXiXYrbzpqOPJrLfIhyP5E+sjGn
NdczxhDxoXngUd90SMZwmyj+tg0s3J2BWrhFY1/7BozWWLsOiXfLMFHFBrptKa1gSh0+Fy7koncj
99JTR/bz0ay6ZEjkvJxPAIlULHlJap9VDlC/9nyKvbL06ntmT17DKZvHuG4hYebgbfCp9WLupS0i
h+4ppWsiumDEyrLrU2Yck4JPckehqLjTktTTBwCAhDMQVplCuJ3L6tBphhypZasTglzG+EUmHL5c
qsOydPSKSP+0gyJ+qcw7tRczVHTosHPasvSdJlJwdZh5DaK+fnwrpUJgT6mw8rUYdAtooeeVnyla
g+Jf61f5Fp4z6xtSC5N9+lubzNOWsxbJ42PyF2Oh14Vy6AYFup+GzUNMKQiorS1cY/LQ/XviONHY
Zcauf3/dHovNIBnih7IpWp1COOzvn63rSCdHmB+D9Lfpr+yl95MOPyNVfZOzeEep+wWnN26PDywy
IPx7aGKkf5EG0e5pMe+DKHWL9UkXi5dsJtG6KzWhhT/YNzSLobKWfA6xFtFZgRM3GbS0qG0nXhrp
nT2z9VUKUsZd6wEZ0II/BFUA2Qt72OloFrFu5nDERQz4P3GVPaSeWC3kuFsHT4XaO37L+EWarhJI
FRKBVJhHGqSiQpB9DuQG3ZfRbpezXpN4lyh94jvg695mlJXUnFfk6qzg4641A49Pp6k2vxyvJ2k3
iO6sK0e/sjnwzawvz84zKGxCjT5mwpIy5yX+kgMuobR4hH9DvabwJkCIRHTa9vEedbRNqkqiflHh
dMixfaMk91pkmwTS/lz1OCWoRw4qT0l0tFxGRweuwpT1gXQcRxiz3TJUZ0ZLT0Xy4+r0gL3/I9xD
tRkRD2bvEAqDX1VHdRahsfgCEJTFyJtoyJqcOAgj8uNd7VKGjjAWTSBHt8BHsNhPh9sHOCjroVRV
rjRW9kYQu/p7+N6gmme8tTAuWE/N4nAmyugIg0c4CqAAg3fshhU4/Cdj2UbDMRlBfFccPCnA4chL
x8INuqTm3fYd4BqQor8uTAsve+S86B/TWvUwGI4IBty+mmCYgo3BXcvYfBOvKZu7+NKggr/Cz9Ca
+1TyE517RQuD1JDE+jlPK+rtOXI74uI4TKk700IH6iISxrHo0G8bT5UjSE39t0rmLYxE6zYD6CQk
YMeL5DaadUy9LRoa4oDOwuca46otA23kqoRy17lApnVQ5VOklPqcP6/78j2v6zuPRDjFOlEsxzB+
JL6PxqKkDJB9A3b9fgbORWajB5L1OisLaKHrbiRqbOD9hPtCA/BMguDU4edAxDC5lnaYp03RUCsN
zg2m3V/4H4aN5pNAT9vV3J7gFxe1ORycia+z/X8TehwcKCnxbvu6SSZyhyZnHPtB+BInJTYNAlW4
NemiqNKLKE2CLUD+/w7eOgSkNbKmGLFuzq9NpLnePhnW0v+R4voqpSdpZRpS1oNy3NM3HxUgn21r
ni4zgK+q+Wz5heL4kB5rYTf5ddUjMVSoZQGhAxb8+xP+RaIrY75VkI5thbKnQTt3mtWAlh8ysb5F
zvrHXfelv9z9G6iEsQdwvkLAYRmixmeSgI8gp/c1PAHjuKnRBSyfez1VYDW2I1bayhaIrpP+7fcv
98dKheCghNJuv+7058e3RWYFcyRS5d0e6WQm2kWJxunsMuircE+2uQvFGXP+X7XA4nt7V0B1aKda
uSBvHzIr+9i/UtLcnPR9s8DDT83btfGIK5qIHEk10u6B11hwWqpbEIvpvO2M7Wr2bA91z0JhXbpT
HHCbQTD9+2GW3Ty27MyOzNLX96Y3YZFRPFjYgyftMzysozt2sJqEd9xiXnrM8vKcvOo/vOtmptb8
oDMCq8fVtZbDGsxwu8nhlpd8VMUsEJ50iU1O0RoK9NnaIjDP4pX3Av6M69Ji4NPD/b0EYaNxqT1w
IWvmWm7mpTGLnfO9dihH1q3STXk7P4xR+9P5qU6/HJH3v+PbOV0X99iKTuuugLQ6ansuCCWnk4Dn
FTda4KOqNIiqUJvZ5hMUlKY42TsYCmnINCgn7yFlSQSfT1G8E0Pjx5aSvMXQe1+7g35jGILTAPAq
mYOnq5VAOEVZgoqwELHmU6/+0wquSEm5gm98J8wwga6Yl7Fgx1zlzMl1WwXp1OHA2Nl6Sa5qP7PD
ktM6twS09g12w07fMWGkhDj9+RqJp+F9GPiW4PGNmn+E/Y/eSoReCViezPq0JXHVliQfTTcZ5L33
W5KL7ePXS/PvAe3/eRXvMefYNooQGemIvTxjz5tJmwybtbD/FrRnjHlw2AiuBESeu5NYU6Y9nx3b
LljabuAWQnfoWcWjacCJ/7Wf9Mm5HI/h/ZR6/fFlWQ0Vjo79VBtPcmssPvqckU9hdNR7Ev7HDhjO
Hf4PJotY9HTlv9IZH+UO3/V0XzSHp9VzETyOB0qk732Du9SwkwFC0fvfZXkL+FlBHX5jpCmKdPrn
Tf+561s0qbLyrwZ75lDuQbiNd6eGrUQ7LEDhtmvQUIcrdKroe/u3MM7/OXVFU5k1nLb48/kbahMN
lORBsxSATRN4zJgD3byEMzzxIUdZcly7BkyaeYg6HvtG+E+lHB8HUkZB5RK99xp45j0CiiLwsc0F
uNDYHV+ibahOsrF5KhYE94utae1fvLdcAjpx8qfm/taAiRZv0J51HjFpS1z6thUMPrhtaJrRZDgg
D2DraM2+kEfDgZVqSE3VwcU5gTqy6j/JWhN/LkB6khkJVBgEnIXC8saPyYHhIqnYNqezOkNPp0uo
irQzew4/nWCDi993JhbYuX70Gn9v+hFvfJXUUIy8BKvN9sFUMFvrWhACyjPdVxZpebaAVTi9Y5Yy
m8LLThcwnM7YnAcer1KGF3nDak2SHyU5l2wwXCuZU0P3NSMstPFlGCDraQBbXVmeR1IL73YqT3J4
dlLPF8KVIizBxZWk03+HPDWU4ejTdjxhAklB5y+XUUPCk24p3o0gaG164ObxOWv3MQEfL9BOOCOk
XL6QdNYD3mbvMY4D9D6hKEcQ/VlQHnFD/41ZlmPNo6vyjPortKCrIEer2h0Zl9yc776sgLwfNnws
ApjXasPcisi0DdCXm2tqosVTdFMr7isDP/EcrEYxPG3NJpRV9/VYt9LY8GxX1ujgrlhcpU7slrNK
I4NlobsmNph9GVc71QAVP5LNe2HXL8XVrz+o8ZlfHAwmn0SoaBeMJXzpuK0CxaC9RQL6C2atSWRV
aBoZ4sD/5JsCdAwTWQNRPNNrQWmBSNkmMx91avJQW4GCOtC+LhkEHoodHVtnYwewreB6DYYVgcnH
1gM680tMN1FIvOjq8ULnc4+eQcs7Xftzi4i5kO27/NBlUvJfLh8fAKXNssYszUhj8gI/6v2hnDLT
ZSaeDNWN8AJykV/cW0IU4Z34AAcz4TzuJbfZqu6HAZTrN09kKekPmdmtcFNt6ApzODSpacVF56Pt
VPy61LyuWja15faybI7ecfZcdWc0V+T0mjKoayPN5wXuptOHnIuDG0jf4jkVIV7aoQ3rWSgsUTLO
5BEW2GEfoHwFVVQjX/WTvZvJtxhTCkMC22ugJK/6ddQpqzog2VT9COQW19mhA/+qOSuxi2Llksn/
AigIw8dpPMYXzdJvLGXjgAIuSE57DzStbwrlL/h8EoDHUywuXuzFWDZAuL5BYehZ+QzVeVNNrDQ3
Mluio6EQN8RytqSMhYnIIec14b/4Ao8Mo7zFrYY64sXKblaAinLD5tcEaGXcnBHzqzelJyWCia2Q
KFYxFKn3H3cOmhsOd/FguyDjVbv1EFxAqWm57Gwg553EgqMhPgNZ77Tuge9TlbuuOWSPoMEbpnxd
+ySlCZntYof2XnKSdqHuqbHPsjVvUhlSNBKDaN6arIsuUlWJfAPr+rt8WrtQWI0duNKCYalDfzbT
VD1mqZiDq5Yf4Nsi90Fh+a9xqpATbDLBAqGSMyTLOQ/7jZq3namHpklZ55B6WQqDpYGbpQxCGx7r
Yl3Jq5Bhh9slE/qwXpDI9GSFB3YXcMIInsJNQF7MHCD+lozuUZx9nkE3Kn+HdIESIWHyOWktPYOe
ETgWigkst4BUMiMuvw51LcDNIshFcTTpJIDWjyVYxgQPL9W/6i4/Yo0ZrzQZRSP5KspqqvWvvEM0
b5H6dImi11ODUaH5u9Ky2MLxoyGkgKzgy3gr4Yi1B8FYWylTAi2+Mh006FaxkpXjCaaHjSU9dvU7
YkiIEWkjbBBRH/hOqy4RnlptwqkHBRUTylsKkgrDvEFCe3NMQUMxVOqsK4fiUM2MSbBLnhxj5Bvy
kPZrD0j466p84TeldZX2DYNWC6EkxGK0FPlZ9kInUC7XQ/M5UjIPH3MUvnq+4gWdDJvq9F4KASWH
cl403p5g+DdclHnpiRzjoThTdS2mL5fULCTUCEOXoAaq62QEBPUXrIYVDdGVoWAnNPAgWk+6WVdu
sWqsqlw3FDDsGVuaseJBqFVz9U8ld8zfTggvTSlStWLdrYnHjHAMgZJrqq6c0SMl+1BjZy0q0CXz
Cy4mjlGC8j+iT27zqeMbyofCYIAZgldA/5xnTJ0F2mE4UZd1A4dLctS35KNNdiIgBssEmSiXcuVk
P90cJgvjPqbSucNKLZi7NNfeq9ZtclA8FRJRF7FrAAx8jBVUSypGYx7jLGGL01z8p2in1p14PASH
1fYs9A6jg7fbxuW6uApu1ncWn2pNJUWNiMVlFvg+n+SnV9R8UscCn6Q2MuHCWatlgMzIw0il47Ue
T9VkfGH5IH6wb9W2S/7NZbIHHF7pTGm4R9okZpGTwfRH75wfijHz06IWN3CNeMA9jG9sdxaBi+3V
vTNoxDssdPwC4PH+PxIP2GI80lP9R5S/TYrQ30rTw13KxvqGSqsZqYFm/auUa0Q6NlFk+EP71trw
m2npmv4SzMaQ7GAxznIY/1lRPVZLLNQQy0H2wVw1cWtC1vp/pnQdTHYfWGFhIhOEW0HVN3f3uPdC
rgAj6ToYzVM+OcXoAnbKUCKYw14K7fCo9B1gEbvgAlPk9Jq9Tgdrq8ZGe2Q5tl0ik9h8lJ037U2l
lGHwqPK22MiIgqZt6cPVCGBgKmQ1/i23dzrNw8UoFGnv+oUMfLb93Ig1jO7e/Z44Q9yi91sf1xSz
/zbdnJn2B+ccDibR4YWUqR51fFNU0KNz8YRLrf4L0hfEuDL2w2jUe+v+OoMshX/bk78FBpshVdKP
cIkK2/7NPV3Xp1/5nLMW5Sb8MV3QE5eo8A32GSDljj892BkR0zY0xpwNPlkxzlmxzX1i75VFQ2Pk
c8xgTpCpdp6TKzDxfNzUg0UBmfuoJP4HUSRFVnYstWteNctsaiXXTfeopRBBevnkou8QgkJDYuB9
qCuOcClwTZVlfnJjID20bQhBT+9frkfbyiQ39zc76q5zrNwrwHG5GBn8Sqdtf81W6o3nQjEWPk7s
As75nOb+vvH3DZTKhYKUGfQY3OevomksUVgwaBCDKRCEG++QI1AKk0vgew0u7Cn7ttQPI3R/9gb7
GgH65jR6maVWYhCRfAfTTW/Hf3LJZ2/6mLbAk135imezR433m2jEI8tUV4j2De11X9/t/ZgOo2NJ
v61NVA0bP3DciCuHQNGGqVrHnS1fCHFWHLslE0P8jqicAAb/8msMLZJYdH8IAJ3HpnvWUxe0gNTt
owqkkzUxonclgwqMwPSdxFAvDy8juFUaG/JRAMeqeLdfjCI/LFCnFiiDVVihuMPQa3y5/zAbTXVd
94riVOZDU9KrZvqJ7tupuAq3kq/+QS8CeSuQ8MnPcPeFArliIPhdbnVioyaruZNM6Ee7fCT9WkgX
0QJPcPKbhHaE525mcJm0o5FLjsCNYFp10BWHJW2YIV2ywwEX/jml+S6G25c2abyZtc+jlomYLg1P
22719yAdedr9/FHubBbonNhIaMd1LRIBt0jQ8fVM1xrgbd6AKE3z3+wS+7LMQ01GD87MfNtfWgio
uBdHrE/N3+X2gDiDNAGMePKmZRhLvbJQzdBYl/Kzxg7LuvgNXFCFcL27B9ryICzyfDfTn9nVDc13
JUi98xFT4OL9ncK+SeNs5nK1NkoVA1QlDvMpW9YgJLPxVlNi88puhSbiKLQLYHRAXh1x5vKls2DM
ff3WeaDBQ6tkKg5+zdbC+6C4KcntdQw1KZ1FXWfBadJGkoplOk3nrUbXsee9KGtHU6xZGKV7KWab
vMExNJ8PUmNHnv9i4Eep7OTQ7GBXuRddMY7zjgQnikcLwpEz/c5vpduWhEae+ww/6vMIBrkqtg0h
OGlnRT5tn7wZmLtO7Dev4YojrWvJ2iXZpXz4N/j5CKIyi/46n0zABJla2lBmtiXTkTE1/B6QYDY3
QgYDvnoK/TPLzZGbWvmGMQPinYUhqnQFAuZHe0ba2p+7mjtNeB7Yf9QaTXqFeak0X43ICyjKQLxi
nrSx74CS1bNRUMUHXh5Dl0+Hi6EL+JnkBs7hYsheauZJYQsrKya/gND216PRlUULg8azCiIvW99C
YFNEpduMmgPUSErCmCR7XYJcOFNq7uHjDG79yXus+lZ4EI3+ADCxJ0msWWZh7FHE2FJsOZD4Jyli
IbrjJ7ZQzsNq1uv3diYQ7tpE7l3WGA4okIdQAWpGvSOh21enHd5ahPiw0wQP330ibLzLEt51+XOg
/t1Uqxigs2EIlG2f+iNrceFWQBQUL28qPudZkSj1sGKy3u4YFaVsOqXt1Dp6X+Mt3HT/CbMbMOdC
bt4uLUJH0sHNM6F6ug1LELxKHySHAhXIm8M8IG1IXp8ZuMGcb89vkkaFOjWC0TXEAjIZ/UkG7Ts/
0n9MmSNoI7itLbgWUrfNx97riWyEzKlZogGwF28JUkuVn+QDRX4bI+/jBkdbEZzUa0CmQrq7tRnC
0d32RDRBI98zJTP2EbtPZXdvUHNif9mo5V1Q+QDrMWlalqkh/7wpzrcWRTTrhx1U1VGB7T8hEkr2
vBnz0np35PLE4IaNGTvKgziLg51/56kMGwUdEchBj7gN9DuKKmI5er61nWNfPHfJiI4MYTBo9t2c
0UOuVlBcA4VcRyoMpsYQf7q1Box+S61L82Ig6cC+XhSTrKDJhlUuty08SmxcQcuAhVnI9nXNPIVx
b/jb0oJwN+AwI5OkAsJIuBw9rCLJ9U4DKxJcc86bST+m5WUGrO9ao7sZ6hqK4XAKoSpph+9nvl0z
gAHVbaJ9Z2MjUXW53L4cCoq8l0IfqpWpE4g7omJQDM/5vtSXD8HKjlaJ6yceWPAafm2NIRxU8UJ8
+K9kdw3R1YdkKWKDYi6omIZAypaqMCJTgHKBrQCiwZDYYMKQ0XLHfnUC0iQLpfs2iSIBdnupUA/6
I0g36I324n4562RgQupVYPMXTT0/LD4p7eXO08gc4QSFFKeJdM3T7LV8MlbX8umT1pNsx3E4/o5/
w3v+hsFmIQzSkmyCixMPwSiEw2/6DylohqXlVBAOH/iVEvvVWO+TEJR9/9zrCY2MZPHXKmbZLITq
dHbGVuZtSG2Dsq1NLQZS8vb0fNQF2lyVW+pXJ0cussRaEtPbEbhksEwDoOgEIre3D0q7wcvxBFX3
/SDJ9ps/OKt8Dwmf7Rxq6z0LcNjLhCpOnix8PD53LRvl5cO+/800SvSNjVNnywnnv7oqQsb04Zhe
4ewvkty7rqu5hCsznCcp/LKfSSP31vaxGhOaNCPGzJkEFkkBc9ow8WTUqv6O0mPski4QWAhhBHoW
XdZFG3i81eFQAgxB1BXhbBsdSC0MxJCDaUT3AaKuVBrAAGesbJOynQ6YUfli9Z+9sGKsOVt0fqIj
MhnHXbs9aHCGhaYXsv73HdYSG2JYNb5wFFvrKzwYfvp44RiV/cVbHS2zMcYrscnWd1eohmuzd+oK
pwdASH9bbHFQkfSfVczfvDb3N5lzQVG2brTw37Btbm3TfmY56aMpx7aIE/njM1Zas6ZFYKYAdVMS
Hb3kCRyYBQhrMzuhmdrnWff1CwF3hSkRmBPaRxo2SHNtT1bH7VYnlrrZIUAhhZ4E/0KZycM/07ro
garBJwv+cbt58ju0XoqOndKTi9q4eLJgPRyoHlw1uVvBwJeVPkQDDxPq4mqOn3ZJRPzCR4fLefX0
YKz2WCb6NUheduZcLuc70ZIbla+TiJtV5MASFcoBuI++NETtkFOIjlkpXLzlIAhpDwbgXbsgI/4g
kOMg2gu3to0zFClNvhH49KmGRIm7a1jxS7Xfuw9K+xPdmA+4QPbYsggHbcReEHvrceEuP6VwDwwT
zzwB3RXtjS6CbhocBQcxE4s9mjIcyB7/5Tha9qJNFCuSl0q0e4BqMjSXYgecPzFNWIer2xJzEj2V
a8qK9esuiN/G9+x819Z7Ng0HLAFRMD5/vy/EGje5/RsjBjpW5F3hIhT1CXYvm8v7zbLMxudKUBws
pXH8G6PLNptcJFG02Mco3wwPBivY4BXDHqO3vt75YdtYgwfaJY6NP2dos99IHOO/mVgVCq4zZeyX
dePbP6Dat2LK9NXNGyjC7MX6RusldA38uC7jTjUO56lI+jurw2TfEqdWmhuywKim1TZL4HWcyO93
UQBKt+Tj5B3pHbWx6zESaJfMbmwSU7QlbWpCJADEzScZcTMHtxzSQ+zf3ujFlt3ETbYgPAtxphnO
65BIdUOdTbgV9zHFxRY1QKXJXKMlAjrGUYH6l/j+RRFATA6e+tzl3VQtMcyosCQ8LSM0Hnl1yNID
YXvlCXSVNIliGZsvi+zeqvgb9z1e2VNopmbADnHzUSLUPbJk1+fTP4XTujcJICPKEIvlZwgB4C2/
/0hY05zlmmtU1O8ZRQ0izfr1g2ssyhARlpwCJX1qjimd3jJunx5J4zKs51zL/YsCYfetWIo2NQKU
gZdNWBAE/Lxngr8mRQYo4SEyaaHwRLc7Z216lFZyVNDpa7wCpmMcT3IsQv5J0/w3Lrwe5ewTzSpV
I2TRspCBOIC9TO7LZ3dW9LPkk01jp2+ALjvK8KfEQh8TgWHyClcN46YA94+MMrNE7kITrOl3VHTr
hT7IO9BAFD7aad4LT2FJ3uOR1nU87QTXDgVOHNlbyoP4yT4bn6l5Mymhhj5Ah8ektdOYXU2umq2y
EO5Ly9TAgRzf9EcMYuZ7J+xJcduhXwr6fMvQqrJphb7QGDcj6pUcnAP8PXi623Ea/08rXZcYB2e0
sf5/d9MEA2ZtyJQtw9Vd709jfJD6f2AjHO3vagjCQmcXnk//jgAU30sGccXm5SJd3dcDJONnH/bK
0dMruE7rA6ygto5aBnFjgap9ZKUnlaWQwEfCcGMjooSXUv5G6JEy/jKJtFoaaT1i/bcZtEbUaNQO
0y2laNQFqLf3WjxLVd6S7zvffwcjgVNgeRVaGm4LsdMMt1mLU+W82RTNKdqf1eEW2ZHrPzmacRmY
C1JATnoufwowu3TIRk8jmFuaTbtkLgmbW7n2A2pfAR5e3kbyT2ZcZrQb++guVqApMg5h1A2D+Nmg
hKLBGdrG4YMUXPi+o/DM+8lIh/dHgDFHAEghLbaplCc6L5R44PshI/gGVn/8k2rBeuM72l+niAy4
wXRdVn8Uo6c16pVzmJNvKnTKS0lM8Cmww1RLnv79KLljY28BYZaiqh5IB2+PJtUrVy7HVJr7fniU
8G2H2aSAXg+cgpKHVKi2goCkM6tWirWWRJOSuJsggjc/0lGrpMifgbN2pKUuXJAVk1sN1BmvzzLp
APRaOND5pVZHigrMfF6st4NHhsYCDtS3CBuKXHf7RtEO+4ttPgTm+5AGp+wftz8y77CThtqrr/2+
lnOzrYMNsxVMLF/ZPU7fMeg2tJn1pnjvLaqCFA+bN3LyQF01T6DCpGwN7lM5BvwM8q4oa9eBuioP
o2H8ckdwnuzipGvknAbZufdUFa89vFwJnZ9QJsoPnEQNOeOCR+qWZR6qILlLGh8OYZAfetVruxVl
ZtI8neHqjT5KSIxM8HZYOl04X9vB5I08APugkJwQvMhYWtmgRxzYS2x1IucrMJcil0/lvDuBSazf
NcW0i2Qmhx7g/mNxkS+3ydE3SikWMsbBPMe6N9QyPs1DTb6kLgGTITznYjejiV64ovRvq20KYXoe
G82OWMNaE1j1l0RN1YuqaE3qc6Ptc+ptrCOt7EWI1ECewGHY/VvPvXcdlxnO83Wpze3lcoR95ZU1
Lnc6frQ5OyK2Z7CtIhhq2gwgfnNwVx2Ao8tqMnW7zYFGcT5VOZKIMSAWqhPUOLHyjmAlbTKfXh1A
r20/cbFS3Ya/XUDVoeqGjz9Wq0rYG2eROVCISUeuI3vNDscYUTtHU5uHg6bzbbz32h3y2cp8VIrc
IUeYNokF2wP5/muKzhYe5HhGM6rWEcSUVzX8bwcfwaykoR5hv3VLDz6wodUX3Kw0JKK2h3zTHvhG
3vpMyjn5uYy2vEcoLRXH3pEMhqRaGNjgmL6JtZDFQgpnBhC9UlRV6qrRU4UvTj8WiojIgI3v1sTB
Qwr/E50vqUAbaRdZ1zoV9vQiSgWTRrJ7BneuujRkZWH723R9A+EP2pAGgSMQQ++YpnFSxtkXCtau
rqT64v6MFk1ZjDGa+QpDcXmpGJsUkEAMZKe/kVrUdjtLi6FliEsigdy7to9DUvCBQaZrGJtH01bT
lUg/JEOCUsrsu7sSRf3QCLaVvxcaScH2a1uZkl1RQ+V22o4EI2D24h2DJSNW6Z14qh4OrNtEy5Vx
pH+i60R3xD63HGllovCrRXVWbxjZkoLCxjWYnakS2sHE0EKw8OFz2lfkNjpqeXToFuOtqciB/P2g
969uWWRzMqCVqXQ93tk9Z9rckTC6uThgHuWVe2mmg5RCt7OLX9SSADLWTSazVyNLPpISjjASBabW
xCZoPFQ1KRiA12MTKT44j8/m7ycQoyOKsVuxPJrDnd7cTIj1tJc8S3gg8Y+UNRglFkkzFVJlmV1D
DXvD8KKQSuPO2urHDp+9e8jDPh4K4SlcG+Iyl7sEZZcNgQPsKCyB2+QGALaicHN781/W4rSVcXKR
ORlr6zQDheAJsLTfrzhMSU0haToxlPpDoa50Qs4uUYQzOr7k6bndEzvH380LbQBzkTcsPudlm8Y+
l5Jp4P6noXtl95c9w9svcXQwYZZ+w10OZ6cqeOAcyCfRNFCJwNUyjXhxfSz5qJREfl7ZxpRx6FYU
F2HC5JbupcLFipTh4rQay7ovLJMaOSazpSt80KYKxZqI/VcTnLCtNeeSGBVjeWobQ8GJGui6OQUy
gMqAu3Kyk57+5Qj01LYIFTV1xAL9OCaWiPuFnpAy1KATpAkMmyAZv2I35cy0BhByz8QqhNtDkWEG
UyIXm1xqJRKsT+6ZU11dzMwkJNEtxIROizl2/sW84hVWl+qVcQmmRBZQGTouA0Xrbgdvkp8vJte+
wjp9TgyM8XG3hu5VDszaJK9gf58m4y3ygc/OxFbwuWJHmbPSTlkPhTocOUZAlstvN50InmCyhr1i
6vJNjOOqwE7AKak7/2C468FZKcxSU6Zod2MK1lH4smlD5oOMrxidgpkE6aINBXSagdCVVTmmpuCQ
9aRFTX6NPpunz0MeaBAUYrclr1Q0vYJKQCMCsUNJNSRXzzkZIWucTW5XsZRtt/YYD7gv6jkznwMu
bU9dR/N4uofS2b80AlLeUCZZk59Lo2LXy7RcSRB+IC4Z8b5Z4NHXYVPHnvCMsPoIKJJXSkivUWiJ
6n6XkyiSb3VQUYjGCS1DQhJ6knMs4Cj/3b9rkkvCLHgXFPbiQe/Gxi9r6dtbwiBfoTExFdLTZ5Uk
Fejix7GXHPzVwXKJPnNjsyIICgK5LTX7DTMHFOJQtopEz790UkMajHE0OEykaTvzLJr7/VGffeE1
CBgnWHrz5PLhlgqEAF+aD/jvP3UDIe31ECrfs9vJCoR0FIYCMk7r5bzFVrbMTlLXI3LCUU4KZDa+
oKLKbLPP043QEpRcRZ54aKKGWV9WofW1MPcaAy1Q05XmTN2KOOdpQbDJ2q1NidY02wGZF0dAcfV+
BHcIzBCQ7IMkhWYiuLYM7e4GE7Gny6B+Y30/l+GuFHKuTUQBlWDWYuy3UuQXZT8ua0VI4RL8UbOt
u9q7ptUCRWBrSzldQsBM3/0Woa4mN0phREpxrUwwyqQ+VvwJlU6Pe430PVxeZjSoGg7uTiOHgDCz
NNPm9ZjKp9lPGilwsoCJoCEft2p4HyNTEmmUiw3FXoh8CX5hgZC9Oj8EUp4Ejal3YsJzzk1geQZC
RlQ6Rsz8ZtYikg0hKaNVBL0nocFuKL06uQ5I94kFy+LTmFldlPcFtwiDMTCk+Wf7/LtIvSJGvBxo
lk0cmrpG4s1joqsazHXC5k+e+KM2TCHviPw6gI0dBdLj4D0BRDxE1czuxWiHUYfS06B4qD9+3r3s
W1aWHSb+F2gLhU1qj/nKkzY4UrT6kRWldbYfkzeOhOu5+uV1UqTMfagqSwl+imM9SlrXCH/O53gv
wmGsRQMDXGM5O2uWSYv0zqF6OTC5l6Xapg0m8q27VNev8sAiZP3Xtob7WeNaumBEOl9pK5/suAcW
HzDe+34mcDMP2+x/7yUu2XC82/Myvvhv0vtOVLYzadb2Ph+k+DQ5ZXRLIc8ccEY9iLjdDT93e++U
2RE+v+VxF5n9BCmmuwGvO4yEEVGPtytqkYU4FGrj0g2nFLWSfGGtXUdw5Y0Svi5Q7dnzCy6e8u3r
NSscOgTXMM/J3pj4YvIBRXkgTkle3krQFwD+6j8zHCPSh/VPN9Ad6jgXogUfT3v56i2d4PPbNmP0
zFgsZFExAn9t6BdlvVp8jRFbtymaRgk8KM1Mudv9EEOsgMgM9952oUm3lVioXibaNEjOYwj7pyfH
Ma0ufTWRkKueEAi6N/LRdEUnlOvpcCVuavjZoOhIcDn8eUceTVLfYNRlHVV0+T21Q52prBpYdJhB
TNs3TthlK/syTS3o727cT6eYn3KBxxRTucFRElV+55KyMzjpHHn+6X6Rac8xCvc6VfYqC8yR+qel
o4UGfJ8BHOf9FlcTHAmUqygH+Y33XedUIrfBW59F+UgH23i1MR/UtToSRAv6SpqaP4Mb9OHSd4e1
4oUF4nPcK+o2cBv5Dby2LKT/dKSCB5OofFK2Tn4eKzz6uZ68FC7pcreI42GahVCgJZBJPDyNT9jF
ATbLOd7STkY4ec8reWLNNTmJHZbZCdwBhlvFfGtMdtHLIB/q6AY67G4kJCLBTWkC3k3pk0ZaZnam
EWWuB9Ziqi8j0DxgO1UuKaKruHd7/mGTD1lvNiI5HLRswMFoMmTpp+OjmIa9KXakipzuFrSII/VP
OBYSEeSIHMfPlCdrgn4b8mYGBU2SXc7FfgLnQEUx61r9MQeqNICSYknBIKbNxz4syVPo8vQC/kLj
bRI900TiimzrOpXRdFVAaC1TccNYfognEzTxkknCvrWg06BCAd91z6rBukhEoBTPFHJ4J7Q/uPVt
4ox5IMf7aykHX+eEoyctiSeFtiWFOdk7uknl7863eAtDLZzlKUMAxB6NCcnQmEK6925Fd4W9JAhb
FiEITCnSujN6Wn+Sdw5Pbe6ASoFGIxHljBFSZT/5dX4SFJNUe7a18SckcnJOWyHR8SKJzImdimw7
23rWt9SPg4TE/uF06OmiwgCsf7c+rqqRdhUf96QD0g2EbTmdfPLD47zI036P9afRbgR+vDBqveC9
LMr2GP5r9hLHQACJIRYu1ChCdD6QW7Kh3081ZZFsQpDRMpwHhzyb09N1k0QLNPduYy9kWYi6Wajw
VyMZCNmWWbMO7FbUrVyJ+vl6zafD9iFrKQLUIMIst49tl+8v5LMA4Q60ccjTqw4DXD5/ApC8Ge+k
qlwmyDu6vNQzP7EfpxXlbx15AM6TTBN6Fyyso2zuUtrJ28F0NBqzzqvmTURn9HYuqcwLYnnQmcBt
NpbQCbur9Ooci/UIzyPtWhVQTSx0y3Tv15iRcCyboJPFqrRD8XHlYr4WWVzoyLBjlBenOm+sU7Zs
N1emBVeHMlxBYe7qALZHxbb/siqlBuAgb6FEpT320CE1UnVGUyz1N5+bFJvH2VBqHW/bf1SkXsgm
d4+Xnt6OGYMUijSIMEfjOUa+IiwRa3dfutpk3C1897Hm953Kqe+Yxb50olOi6iCeXq7TdpAWU56V
UM44z4AphLz2JlBZ+Q645fpgEoG1c1dQT9UnN/dsLmMAXUBcHNcg+hWtJ3Hf2h1ZV49VImnC4y03
4f7w4S9HXQ28pRbV7Vr4zEKi7U48XeGYc7IXDvOdUT8W/MYtknX7/AnUzs/h0tazFN1bGo9yfZFO
TjUBlJE1JdLWSjkqdxh6a2KG858sm96p7nTHP/xB0l4khvvQu0uUi/KOgBrxGAzn7Gvwb94jC5fe
uxNTdWUUzNRlNaajXbqSr5sE0YoaxA15USXA4uYBMNBhzlYnkUDHkh65L6lhs3G8MdkgLs6Yav3o
KA6IGlyvDvMCnFCLgWcYowauvVJWDpMi8rY8hiRhRk3V8iThVV+qxOh2mDrK4D73fpG96Q4B/u56
wMzboLSeJomTDwPf3/bKkAfbSguBNlNcgHE2bKHwaLd+CMzruGQknVLW3OdzZGR7lVGCo4ZNY/XD
KssFimoyf23jgIS2ENUSC0gKNqpKSJkGEQRUL7e29hOYInk3Zx1Ak4QiwrsQrnt4UhFlBWHcEIXt
JDwsTMdLArdlHzxeLrktDi6/1NO1UGGej6NoreZcUOO7eGTRVm3EJkVGidt9PGfuHpDYDiiVAPmy
Te8w1AlzaYJFxHtT75CVOxGiz9ZZ+Bf75YVt9qd0PAItJgnS3NQRdFuVf63EFir8pdb960zRRcg9
zKWR+QV8K629OPECHavNWHCyDdQAwc7F8KNr9k/75YXg11dKAtK9QKVcZnc6GQeOLd9x/xvQD4AU
2aHb4g9wR4LmpdFAnW+mF1PNy8xzGEuQcobTcCn7Aqyma2SZm0ZTXG6kPy0J5HkVWXtlyLuIdCj0
deueDj9CJaLeKkYMXrXFPffO5DVtQ7W2AfgOpQ6YDugI1blxnkeuW1pJGfbzlPCo+Zn7BMzGvH/Y
KbeVv6Bsn1HORMMgZz6e4n53RErC7m52IJE9rs+cUY7NaLK1lF8OaQpWQ6gEnEtp2nwliRgxigvz
iqLVOtlW+/YPXtg3d0XPWRKzx3qmtvtSYiS73stJiL9uS/P0ODKmn5zNHxlhtEbY/t1K6p/6GeGH
C5s0RzagZS4sRQpuhHMwfD1itaKUk7KYP1CtIcC0eb+/nD6OnZdyT+3xJLVyeLSfa7tYvb8PB00Q
VryBN/5mRpo9wOpSnFT4q4x0ysB4ZHYWbWJcb8sK5UM2T/ShgCf2eoTBIO7UHkjubM0ioQp6vDPL
1UWUm1mRaN7m/nVe3VY1MyqhgUyFykWEglJ0yMjDgtvPez+XPNaN1nquBDFrh2mp2AHPM66aLiON
fxajOWifCP/XwJoKxhj/nzpHj0CVCLtmtRh2nDqmNM0QiWzN0FpYY7qTurU6nb3+ELpm61pvy2O/
XRZH8meWRk45ItHNWdnyMbfDxdyjUK4OEjZ4JcUybFfgTcmu3I//mJJyKPU5lo+Wly+i02lW4lHc
ormeVQsvHTgbDcqw1pnr+5500MP28qGPguPUFs3bffQU5O5Tx3z8gRx2P9qwSNj2ufJuzkqi7B4B
oAjDDT+ovAiHA0BhysVf6mcdJZC5xEtiTfNu7ygdtSFcpkmmPgp3sfEkhUC62uVG52PNWUjGoU5a
ai1f6IaKJ4FTIjLHfKgMwWrxDxcUb7sldsa7i25RZETcbRFYd309gXa9P+6a4g3cBhq75WlJITd0
vn6FOK7+MYNFviq3Du7qdXTDg5dHUfdvPXCeMPRLqCKIrxBtaAZwGCRBuAZoWHtIPSKZbiZCJ0xJ
WyD7AVfohkVH7un/GTqmnukIjAB6UPqKjVSsFLYuH9m6yna9HFf+nRflJlTrNwfE+8W0q8UGCrEJ
aNiC4MdJsw/95Bm1f4WhPtWCwRe/yQFo1nVzrJJUK7XDNnmTT0i2oHusI5jH5wN2lgXM4AQWCLVM
Q0UdWi2mNAc4p/qyYWl7S5Dge9Ki2cM7Sh8HcOkRUPWhb432oeJadDBD+i5LMngeOdu9ORscaNoi
I/aCPSNxgw9hgs+4LhH2zVFWLAJmKGcOCQuwwH74EaYI65SCLhLwHXALPB1pfv2MO4AyWKoxaVot
p/yANvuz65X0+/ieUJ7pOMHOPrSSIYTy75DkHw+9EsP6eRXW3IK8WW15ljv5lqepWVnSIbEJrsSi
0bLGHvNCtcB/RMcO3ccQdxYhtwFlxGF1Rsyba+vSU7ngNqaIkIg8KgqebqSRxB1siJnoMcbsVR+c
86ycuC+17+EnDoqAZI9KX7FhT2sSuAlvdlaJWj8xk8Cet3ncE8j1o8kdL7uebSn/lxSAWXuVyTPL
OFfxo1VUZPYdRrNRdpQSzZXqiuUd73XMo5e+Tv8fY4t7fIKimLZzafwYRfhH/y2Yg4E+x9t8YoD+
VPEPwNtWZ4Uz2tBxw0eLD8G9CrSRcvgXVjrsPCsC2sV9EKZCdJCWsOjPKLhjRANHu+B0VgER5DjB
5hMsg0JCjVtxpPk8RbeUf6egeOZRLchPLKEp4mlg1M7vjxakLMEbh9fuf1/esWxajCh8GET5mTum
jkYKON0uDwhD1OIK06m8hiuu1Kg2QI1vFBvATtIxOt+r6NNlIfgCSGRsD/NBc5GVxgflfzrnj020
D+qHkxKqGo5qWJC96ZLxWyV59HPd8kXuXUPVRHad1jFHhMe0ObrrhLo4+Cl9bNXIdh3uR8YQ6KU6
S5jEBkd8E0cW2mrJx0ReileYxryMrLX6Pb1IXSqCRyaeL2XYI2NcESNBa30EL/FOcnswZy2tab3N
F8oQspInMhzAZC/g3nzUJoPeETQ75/xqLZWWVxryXjVaPcTOGPAFXBinZM+aHbczhjAQwH4idgqm
JDT1dQsN6foH5tBe/l/ZIcz6mznTCfYrm7zCcSGrbg4E6ulYFZErVBBNW7l/l9L7pxG+5i9icaFE
i8c6ik35JebI5+VEssi6WtlxwQO6VnwH3r5jBOGGMOlRn/emHV2UcKC+AsLIOXLU0L2Lc2YHfzpa
RWBO5UOh6ZIS6z91QgU2vdFTpnQKpNxUgI420XOwGzFnxxpIe1wgAbWvkUIX9oRSb/t91loXNh8Z
CgVrx6euiIAWJ8illS+1x/SCOw73dT5BFoUFG+6mx9bqctybaiRP9xwVARQTPHrv02XBNTZYE845
xODg5bJ28WsTZsaDGJrV2QaddHDcZKWJM76EL1mVwdmfTIRA8F923GnUAbmtjrZVLHfnShA75Ypj
ozZvCFmAVrkYcpL5uk/QUgnb3bK7J5mP0+7KcQrC0p6+t4D7bbRGVN2drEM88sXUI3bilzF81S/l
zurSf5/tpcvgVx1usw0eqSHnEny18rlZ8iPmL5JeTO3DGIzwcduqa4j7yUxDTNdmEJpk6M1+ltg6
PsJy0Pr/Gp4vd4MbgCUUZ+w3yzjJmx0Z2OALTvQKMHyg6P1DUGomK7IVy4WWQ8z2Pwa2G6WLC6tg
I9Vd/hdMEjIFJYhHVd6XbRxHbUO9HXQwbI0bvuG08T48h6Z3kUUNDnDcdgaIFtI+TQVwzBudmmSs
Fz3rrcijPdO8JmXEHTQMPL/Blyz1iekCKbrIbtfxIUcXLl+w+BYCqDU6IJRnHHiZN3uBzHCPgXoW
fFMNBn1l+duhSpQKNPaE5V/Io5M4lGduiJ72ZaATYLOeBUXWkdv9xdVhuC1pfk1zOX/EYkSUy6H3
DEDIR3zsGqhF7qWy5gdDgitE4sPj6FHj6dQfh70ROcdCUNCc7tzK0NJTR5gZqmspd3LmfiflzHr+
Pgu9BUejTP3jZuCq7+ccc4nOr1RlCdt7VfT8+IgsvYEr0WDkw4JsyHUPlncWLh3MKTrAumiNSw3z
M96jMWkAm5BJqBOGYNoI57QmiiYTcrjjLxvY50J2swLu7yz3xFzI+192f4dGv+Zdf4hAhsNAd/6i
UFanEHHJUvceYQluJLMCHEVNsKGlE/Q3onIunXqMxcGLoL/Hvqo25pd8dk9dcDEFZ7h6iT1gfjY2
lFHZduRDpm0fFR8clJ8mTynK2qy6LAaXInG7/dD255ibPGjpZyg71hcuVvWtmgPhwyg8W4latNl9
yEf+mgvHMmWHedRJEChhE2lpEt6yh0eLTrcPalhUAI5XKOR7P2LtlqIUQ3alSxJxpArc52z6/rb4
/IedzRibK7ZIsdFJf3lC1FjdEzeGyzeRW+oVw1PkeiBUuCmiiM5xjrlrPmNM7NkWsYtdnyVXQs58
b7EK8JSN+TIr7RxcRYxdQwrcLs+9X2/FQ2QvysrLX//tHYAWAwwyCtFtKV5qjOFQXyjJD0uxlfBx
UgdsEgXFuGAoCWG6eHdDqB4S98RegwNcTXpeo++U6b5r8efxiIwifGfUDRe6vLS1oaPCiJeXKSma
oVisxsGGRtu5L1QjzkwRdSsC0x+rKx6vTavae1JhD4rzHbFZ/msJ55M4g6uboVISwYudobwkxTE/
/bvUI6L4ooOR9m00OCSo6Z5WMYwCfhw449gZ+qptC5pWr2Nps6Oi2X9iD0fURhUrbE9K/dP/V099
jiOBCgivx4NRM07IDGvzQGRQhJjVaSHnVY5cYd/A4Twv5S+2kHe4z4smmAHivgU6dgHOz6JdmBg8
/c8qaHR4cdh8GhMqi6fNkXqRe7jjhgH6tLkW/HdHwxyxMTRMiqwhLaIiKopagDhIUuK76H+Ldi9n
ZoOGIi8BwoQPWys1zs8b19JjLv7T3ZcsmCjg64Q2shySZHOh/siUlHkvd2rU+IFz+EyFVL917HX5
ArIhb76UUBW8vOluEaZBo5EDPRe4iwIx/BCdQdjkMsUndOUvPTPr+NabLfO84dw2Lsg24LsmM1Fn
m2ctWb6JgOwh2v8iLvXdEwpjqL3em+5P/iJaPC/pDj2XjNhCOimr3+2OT4EeYiVtVgZwzjYe/GMp
vXcDt+dzu5ObYRDOmpac0NgEN6H1W45S8R9W9hSCreNV6Wex+2JcLcbPvkXRMrfAVti2IHBIr/w+
DB3/HevfZbCKa64lTeUeI4jERuWQLK3MmY8IYbltEEwt4WSqcYPkGr9HF4dQSBb8C/2kNW6hP0y8
6eV8c8wJwlkxHfIbjvDZWCyCv2FxvB3LPFEIOgWsu3zuIWw9Xyf9tZsoCVQPIr6wy2TPIJe+Ypdk
DIs0poXVfCtt+lkrASV+MrBpoTDp+6Svxdu1HYUvWHr/1GBXb5Wb6xyD83PQAXs3IazE1YGR5C60
Dj9eb7IJLFvSBiQxZMg0HL5VkthJ7QUIsoyRjnkY3YnxqNRYfqZ5Usey/LtRLS9oK2hX+rHyMfUK
Hf4ANTN8jK2fpN+9BnqHw1We7cTgBzLLyuH7fZ+bAdQaFAS9WOCbGMjTUJeCc5RdmEJFjrAbf+go
vJXR0qWRDZL5F7zTq3vOb4xcad37p9oFjvI6kUus6QnE5BP9sTIwQRSRCVFWjlyrFxGuqrPQfxvI
i6ws9j05TUajMQWFLkplP5WV6vLH95ibTjLQQcWLKtaz3TcuXMA02xaDtGXy+HLvIk6Ne1QtscUW
8yhn1iAPh7i0c90C24nb+4BqRRJqbBpqFhD+l8IjrJrp/B/Jho3jUMP/jp6t786SEw/UhtlGmEFL
WwpHO09DyRkOMqgImobdjWZSvbQb96gBl8rcpQ7/dHSeXDTbMEPPDiQVfIuapORO/pPh4OnVAlTd
VwDXOfKyVOWXRgvP1iSJfBHGxg9Dil8KCze+pi2jXvLUJaK8JsWEoHKtRnN70dMagSMV03OPGnXk
ekGjmMqOypmBun9Ft7oLVmS/M4JvgHPxFwfzExhsfEOQLXIUiygATRdeVwdzBvX3tK72etwnf24J
bqLuBw7v5oz0wddQ8OyP6vf1PYLOawDU+QMRE4wagvKZDiO0AmrT+edAKcKNucxYLoPNi6kl4BI7
fdhNqaVBtSv2STs4iAmrJdNMCcbH6AiJqbT00grSloxMfFsI5iKX70gPCkL/GgEoJvAiKorJ/wW3
B5ubTxs1APy6ZHQtP6H41VRujyJT5rexWG0Y2+SXxp6pQxbBoRA14fqM2o3snHmh65RNxojB5YLN
AlWTq6jqIFaW2gNwLnaYRfIHFMheysyr7I/YaqilQXauzflRcQj+HaSKZsWRglb1QGScKqPcrXb1
wXGN67XkDsxT+MwBgN0HN/zbYGDYCHiBL9V/EayMvJPcHGKqeal/jBmAjSHmxGOg3hRyZQ/vAKAH
+lJbDuLzB1jjkiF09lCa7PWN7AaZrx6tbPjRNIgGzrDzfiWn5Nvj3LP2btzHfthzGzXcw5xjWa5q
44bEyL7kqyWLlMRn8zq8MFdtURGaL9wq+6Zi+gRwr1mkxQGvgOXY3t21jWMUfEeSzZ14zojkR8V3
kzkOwKyomnHV3dy7wUn+5bjJX7+KnEsjk9W1TKltuZuFaMZKy5GqfT1olYBGRu/HUD/W9QLYptDD
/ssMGvdq1ksIoGrRkpOERI7pVSTnZYY7viEhM5yxfv2KliFniNcxdqkyKN4j1UJJtIHTB0T2Hl5X
cCDCjn1mjyd1IHygHMd2peGr6bV0SAKHfgYU70ebb+vSMVpfEpPzpXWfWDYm7PK8d4Kb+E7tIe9X
gowhAe4Yw35N43xMUeBIADH+AuSgyj3P0QGxQcWGZcINnYhEJjXQD2EdUQds4BzvXVzrF2P3UoMw
Jo+KLHStHVaLP0iRa+nah+8a4rBBgDApMIQCAZ4cZwQtsARlglRTAwh7zVS/676MK4ayBTalHdxW
nrf+5+pTQnTPLKiqhPBdzuS8j1bQszyossGA8nVPWL3AtExQRTXlNVccERgnVBHSXlKEhCScL7kw
z2d3RNelkvF0LxmhxoULBUFPs4yE4M56bhsMSSIww7MS3SDNLoudGFg8FGgnNjHski3YCJtv9N8o
PBIrsMYtha1mNryO7FxK6097SSzQbsIa+c4zuHXu5jJfBLqSar9LjxiMmxj+2dIE/HJx5UqJ5voy
LVDSOt7Ea5Qyyb7ttiqKLi/23FNku1M+vzPSYdnEQN5t293ngBRBPtVN5pxjyDswwWJqr9Ay+Avn
/SafQwaf0lGp+IcfUPXeTewNydpsDZPOTRktiXtEQM/mkjFKvZfRmqnV0iCPgbGqnJP/+FotWtbQ
W2N//mbpj/MgRS5465hAKQjg0ssmqYYBiKipM0kdKFa19yv4vq9VXFzaW0REbpfqWvmj6HIlpG6b
sU/jQ+PNhzYGA2DoUNgTkf+5T1vtBUs8GMBf+ImJN6eCJ13Mu6tLIaEdWBVBMJ96QLeUJUcGIazE
CEVqjMzCBgyf18nLOQp8kZOQr/ENgkBuDnaiiXOWbhbthWdfqdZKUYzfaLC6zHZrptgVENdDgQPE
WYBu3yKB8fYBEBfgqw21NFyiRGeCBIQyMZrkNhDfYVYp534n3K2rmyrcRwf7zj+PJIvLHfWryH1a
7mjbhcejKDOmuIK98m7Zs9JKbf69ZMjhrLxA5kicYyjeqVbCSkyncqB6RLYhqBg5tcRRt70E4cV+
FrofG43kvWduisfRt8NHJoxl0otogcLv+U7jgqAuLx0fKFTV2pISluM1wcUI/jPuSYrvJoJwtJ7L
HsGacSyk8biSAnRreWrYdQGEL/OOyotw8HnBwvmDzC0flL1UFZQA4iUFPACZWFAbNXTplJNG8xBk
g0yUFNrsi5ztr/7VKf5vKAiastDwALI2ghqLqvCB/1dodcDEaks20weIYC6sDl5mpXtzEbhKGrdT
Clzs8j8pu2V+Iq+ics7EEism/lbxTqS9wo/pPMTsvZwk8l3LRXlcmIqBKY9D1eEJaJboWaY5gULB
nSRNR4vxpKqWe1P/IFYyiuXuEnjmLFgtJrZEKkEQQmf+hXBH2MX59YgzvuIDxbn9QpQXvk//EmEr
1Vsi8RZZS+EqHN0ZSZBK5OVoeCdYpImcvYMJqb0MiiFeSX1t26SOPEIgUdmIa5z0gSTJcYETO8UF
bCcIcVXYD7ZLPc5t/I3BuUSw+qn3AxKYyohTpKzb7rjkLVzGkZP7777wbTzFGnnl4pfdBtHLfC/a
iygyQQwW+GoewEwihnjg/hlACn9RzOKIZpDhAW6RyXN9VfIoljOJwNhLjIVYpAH4asJFM8Ari9k7
sm3itgraUPhyUSCOiXUnNszg/lp8u8V3DHEE3hH+UE+eYBYWiq86Z/Rx2sA/BUrbeCTupxorl2GP
UMBiAjdgdl597QKjUurS1m02LqyzDVlU8hcU/tpyGcjO9H3lhB5+sLXzulpKgfpcuifmnUsbU9c3
g+pqmGMtqwAzmpDMTwTwiMsFJKHIiIp2lzw7TQJ8QPCdam7gho/6H6/5Y/TixoeJL3omEE/soeo3
a+Inv5oLLpPBzTDtJrL25IIX9gotvWnGHDtogL2e7ldf/p+vg4Q4rbaS9qC/uoJIOyvOPPLnmGs5
5NIhn+BmsQHErZYRuUz3C6PRBXCrRnhJODOfizs46Td4J3Ox3WS1yeB9E35ewGMpOvQnjt4h9jkE
SOU/5FWrzo27ZEeC/zhNaA0zlzGiHg6O0Tz7AeCVvFaAv7SrOJEHZXMSCDykewToqT7F1dfz+Pj7
VD0RLMWyaNgbiV9jIahlq5aZpLVoknZnnLDIPPkTx2za0ozt82Kh/zQJiX8ybZSiXiPF0GRTohvG
UC0/9osvflIVHp/sq1vPQfE4USfJM5z1gxKUoXnBxzGnoqaWQesZaIYWuVBDCDx/wuk6oyihjb9o
j5E/nYxI0R9aEXoO1UG1hi7ZbTe8kvl2EIRrxB0dVUyu7cK7Xzv4BvAnpct8DKWZKKpuYQf6VkX8
3no4bn/v+C3iPBfKRgfWyj63RExYnn3ZWJ3II0D53gMLIQsHtgt9+F9xtn38lg+79wqjFFi/7K3p
0Z/P3Ela628erDxtvnXYWTr3KQIi8mYVxyzXB62NICI5LVr46zZ2xxo068LKOyYNmeM09b4EUszv
AUi/i2RVEIfnRJ6ggx8MzyydmQaJzehu5K5V7G4t+wTSqmd/KTeBJaaenqCQrmxJUoGKha9vS7hm
NzIAoRoiu+VB0W6qeYdPBTPE9ugt9MfinQTXC1osdCWl7CU72s3UZvC+804GpuyJqujwO4uZrblh
UNzPB1cT2akgjvm6fPIfLFfTMBv1ZwOSiimLP+pcvTcPFy2GOqUTOOAV9VUdJRir0MFAMxkNOuSA
w1AxB/uQSi2lOGAodi0r2x0gUaF0UcXZVv08qed3P7Xkwcb0LkmVKZzIdf0cM3v56+hrAwXIgzSU
VUCf7AWVQTHOVU2suYW2CQ5FJt/gKS9FT4l/sldOzVNWINvGQLXQ1R7zmsuwYaaCie9L5JuO0yfn
4d7To6pFEnWc2WWJ9V+0D2l+Dd7Uj48yM08CclB/z1ZA+5pceVa/rhZDLNu2OkqIPVVWm3G4HQmt
FBYQUf2zzopsQWcquvYS1T4P9U+SJTUpvKT2CMAASYI7xwwgzqfDl1bmWZ5utUXWyoGhmRfVVqNe
GR+iUE6CsvJ/jSJkxWVkaPxhNbchAKTBUZYmnswfWsRkW/3lBLbMWjzmxoaxqekUmfE2CraTlMoZ
mtYJ8gsg7Z1rFg4UH0fzk1iMMdB0SnlkshHc05gGZUa7aEUcpu/gcg25Kx78ovt+bFuU4cGhWaRZ
TBVC/l6izE3jtMdv7gnmU/vqawVhZQpSsq8Ztsq/XRcyKoqnWwzdN6r8gYn7Ug5Vnh4nG4QgwkQb
FDxAIR96zCkFI3UUNd9WRnlfNk9gNxlNEyWS9Y+IT+UmMiwf9g9jcdBFPavcSzJ2BU23YscfYfiA
Fha5711DoJlNoDdT0QVAnrnn+oCQ+o1uUJ4DsxvrJ7Dr8Pp6gtp+ZW5UaXd2TEi3dVzC5se66jJB
gOHBbCnU77SSPDyYI2ZYESUgHueyzgbKGRXglXrGnZlXgscp9NrXtP0l2z8bl2y7IKY8VcPXA1Gx
m4LlVg2PMSESe8wQw7FXN2bNgRjxoDT75EaZsOIwJNADGsCTK+mYxZ9RqmzY55fdWFIeC6KmQO3u
PWofeMupmpwbH7O+vLSX0DLzQt+/MXCssBwhbfzpGv9NHIGO2IJLgT4rbQuaQhCicxzxOxG9+v4m
AIgBduCD/42iNm2CSxzluHmkr0T816xJelqlrB0Viqt/0eA3WF+uzbUtuaqT3LDrib1Bq5p2z7ss
dXb7TZiNUyv6AxPr3Flx1xHw0SuzRz1ysnjA7nbqqGB7JD4wskn+Dgf9vrV92F4QeygtPPBJhlPM
TO38Als5LKMCdD71MpHOjUrRNfw0AeP9cFzdqYSWl5u8SWI7t42qmdSkgNBYHNy0cvbzQ+uAOPSQ
3zq7sK3cjq521vhwquGNMVia6/yfPrAafgeIwcQiyN0Gvmd+RQnCGhgCT2neCfwoxzhVchaeK78l
me90aV9IYkuPsDBkTI0Rz25g20lj2i4qIJBynNqaigt2kVWTnvqLyzzay6SaFMhAtZBEwsKCKkXE
1M220DhQ5LFFkUWgpyu3F1T3/WVWYC5htlvHz5CPqtlIUt7aVk5+hVEb0t4CUnvo2pY/YEWiaclf
+RdwwVdsxjphTuzxGA7HT9QzQMt0kljyNDi47edqfci803j0/+jNKf36AIeVeoj7UEIvTUNRxOra
ByqvR2tqGat6iG2MaivJEaD1XOix4lagn1OEtqX2+b/W6qE3+TDutXGs+NW1chh58IgVNZ+gRo6p
lBXB7RhUeBOZkUygLGxK4jdv+pQA018dvG9D3++WSRvewbXw0nMwWTirHsV88IMi7fb+t3nCc9zQ
AoCUQN9pcGMuHnjoV4qa1GcpZXeLdJJYO5WwL5Brej118pq8B/L03vnJEk6DkvDJu+rMMAj8j5Hx
ka5Bp1PqHocGFPP75PgruEVh885g8vYO5Opxp5hqRL8uCVo/K/hZvjzFc+gTvmpis7sXBjGlthra
zAbCfu9hONTZYm1jEX5HJoGHtmwIu5aJalCKBoNHcUmXdiSfqkFr7YgdAfv1ndfnyEeiUvhA51lt
6bqkOZX8XatIrOpxfMVNnsdDmdY0MnmNCjt8jC9mEQmp6SiVo7Hdk8EkxQ+CIfCCmf3GuTomawgo
aboJPXkdnhlrWmhsUXFybYgChWyxpJLIr9LZfsRcPEh3EEnJ3i+jabNctynRQdFyWdteoEOQISbZ
iZzgyextp7/G89oeKaitn3+awHWpF/OCOd9IfLWfGnaoSVN2FEAqdHcskt9Em33XPKQv2PktCu0P
D+tATg0Vffewc3LUItDsyJsQkLac4No2h4ren8vm6lh/3AaKUUMthko8OtdceCCPqt9KU586oKmu
XinDQb3IXI8WXUtlYek/gyZqFsVknLsQSe7JUBjvpWg6cHHhnBrYAqlz8q375GNExMoRTy/DJ9j9
thtMtzxhC34t4mA07l8PDzHRvlUeG0TBwLwhvDRkp4RQf4RbE0oUHHLYBsp554abOimk6B39Eyb4
vSej46nS/C1WCrE4jFBehtKfiicCbC9Swka48Z1AqMG6JZUVbfGZv4D5Wz98FndX5Y/qMlgZstJY
+FiDUwq71F9IdhjpQa0+7s82F5W6rfy/kk4HSu8V39/GeC0qOtR2UYh0RWk3GQZ4RIr7Oi/UZk9u
T2SU5fWT8h44sIt1zgtWAHYy2MJ2HbJfACunIk0yt/uCukf08ZgxK7tHH6pZ+sw7H+zXP94TQa+f
KhSNYNPYJrZanUAUpPFimDDCgsw7yZNTZI5nRrOk7lMR1Lwu6BkQJyFywBN/ADKNtjXzHUbwtbqJ
gPVLHsrt9UwBxpnuMQEqq6cKRyjziRpNfZVDqjdqIWQdoeSxgyAuwOL5QiHpEHiARo99RTNCA8kU
xLLk/jmvxAqBhK/mAs+Fk28+Ur51sJ2BVlHa6ER5K7DKt6i33rtg9HYgpWg8kFTHkJqjY4MSwEe/
oG0ILDRi4sr8GQI8yK2qkI0zoJ3DWfa+eST+hJmQfJobDoil/XojQMjluS93kOenGVD7HxX7k5fY
ulj68eCeLBKdhFTQQ/g4jq742JWcWOTfgdaM22LxDNsoS5p4oZJMx4qg7OnA4RknNtNRHvYOkLOr
modwFc/aHocvfHDKrhgnYHgkvwiDKx/dUEAE2i2aez7ekVUJzZ9RtT+rvHizgcuguEh2P58z7eGd
bQvPmHgqeB48XDBJQrvmZC2E7fqmxUGTBwIqr/vjO7SJ1e5BwsuDXmFny6Y32t1c1G3xx8dCOKYQ
ljBweL2NgHUj69HHcRXUAOlZAIYwGGZyMlB+sm+PEIevxXyfYNgWuivbdbGHCFRkED3glNedyqHK
Decv/UgtpWKbU9hh4UkWl0ALAhD2oCspasTszWhM968yQ0wlO/3zV+nalqCIBhetbd1DDc2aZ7vn
483FtfIb4cEiJ8FRXifFvMlMZ1ZNk+WTKDlkLWhZvV5d5cq5Y1TdEoSIIstI8I1JSBL9fckCs2QF
5kvfmnkZQAwlRL8wMSP2RXZpQ0HJO6ajM+TkXtXzGiGLKNZ6l/n4ADRLXqzulX7FXToF9wwhXtrK
/iEwyc3Q/s6fXGuztFZiNF1nfobGE0DqYxfC2DuhEQmM42YPCkdlXF9FkahEiGczdADlMN7EUmS3
3LUpK4yO3zZ89PnvegLHwLn8qQqUgM4JgkeMS53jgrPj8z8nKN3xv9RMLWN0ufm8FfkIMXYUCdH6
8vJZMMwlliCT2ijzHxKgwVViv+1vovyoAh7JCoCYqNJl9fJW3mBBSaJlPSRqVK8399KVeqqPVBOA
Do24qBq8yHO5xHshyL8p7Q7JbmF9/+O9sVHENtg5CjFpbfrYuGV39EihEoFLPu1RMuCAWQVUhP57
33/GTKLvWg91XHFOzNPY5ca7y+747oJJjefyTjLtpmcB8Lf4gqSAuzVoFgFRplTHGDO097IpfI5A
wESV7/Z3UZ3NandMxkhMesRm3/UlDEms1zABzyAbb5ji8yrC+IxUzDiJOrLSLEP/bmPfDj9eVUEV
Mc1+0+3GcPNfji8LZhntwJPiB+9J6HQJjT4DXoEDORqEFLHvgqpbbMRTDqsR/C+JQ4HmWlMqPl1F
fou6ZpbzYfE/fXMH6GFeLc9wf40OTT154iasAAZu2lIOyOm5Z7OUu3KhOevxi9/CWOkU3xNPdtdq
djTMxSijOxfXqh7a12s8x5Iz0qcC43QuT25Z34JXkFaWilM72oMtiRPrckmXiGeUEVMNnH2Dlnos
FrLdfX6t/XKgvuw9BMKiZozC0d7oxS9E2/R2cd1Dxhn3Szea4CPjFyexNRBG/4GjdDG13MEuvaAv
aiALF+B2DpikhgqRCWkc93WrBnfXhxpDeZGtwPImEHezFof8uDM6Joq5vHFx6mbBLFpL9iumuL+F
J5y8qQbD5kJ/LjrSLwdloAnWkluIxHJ9U9u6Z8/c74txlW9lFdvf8JuyUTPVqV5YWkk4UG5O8vQO
AcRwb/EgAVE/6fCk+cNXecO0EY7XQ3a/gMKpReBFbExt+1kPyzuwgBUE4fmLRKrqQVTE7ny0l0uW
zBxrwhf4nJVaW38Rhte2Smi5ZxYqa06DBrS3rj29UdzAvS4BWo4Q+GVDGgU8y2Cx6Ajrvc1QsqQF
thd0PDZKbf1Udstcfa0H0i0ColXZtFQvLOd/06Dfug0MC/kKKOWA+3LEYg9NQbIp594jd1qSCY6u
21ZMgM9viKxUwtt6N4xhg8vwg1IFTCVBkrX6qiNa2iAM6rJUYwy5xcNJ24TfZO1NAQAL2z1efps+
DWBxY+sSlpqZPUQg4xb+82K3Lgl+u2aUywHUT/f9tgs6U37SajEfDMHtZpTK9JNuvxY5bc0pMrZa
p3M6rzHpbWFa0suD8cTAyNW+O1tBSixnnVgBbBnG5Ys1pccKsFxK9U5W9SfHc+qtV7PkOhbhV0Rv
yI11h7jy3z1jOdet0IOUWN+dQ8gzLdG5SPty+77UCJudHPzZPvRY1KRemxuYIjGCMoHa5V4n7hEB
gt9ZHuxhpFg9ngyRsi4CVr2ExuJMPrxbtugVTQKro3yq8KHC57L1vkxWLyFl/AulVLQYAZL3ev15
jbqYibjZrClBT9m3zXx7WogwTMom/8pSqANwqMZaCQaGvJYnIHVa1mD/nyjcXOi8QaMbjmU9osK0
trm2mB69N9uQphGLuOgNHZA0EzzpQwmHIM5qSB3qioDmGhrFx6mjUn0XJRbDMuijMi6OJ/sDv4FI
2c9c4njAJlzrT3fFVHB2ybCP3bCtGMwwVg3aX6hqZXqR4A3+7S7YJNyGmYVhXZVBAK0K0E+zwLSv
eARa+Ee93SSQEPZU2doKVGVl7wH4Otlk0wGNdoRRBHIywIxHJVG+O6NL0mTyRPER8iuQQ45Vuk84
InNFTKNg/188e0rS8CveAQgeHohxBM7lFBn6QTrCax7AFJ5kJ6dbJlEBmKkAHtnEskR3+vuqn/ft
dlqLy7d5B7TfJlzqapiZTRi7GPXLspWlJmsQ2+DLYqnNI/Plx2EQueGEq6w6h5UCTplxZq5Cu8du
6UFCZrvuAefsXBhY/v7YGuAsA7TUYF4V25Kj6iCrFvgoefYvdIP13pr2OygjrcarIY9cIpmMyhGZ
HfTJLQdRBmpIpmUS7lmewQUx52kV5rlJ7dKHeyn8T0CUgytro8SNSaev+NHZAC2qXHfCdLfdZ8+g
6xV6p1+epEEyRw0d72b5TI7/dhiCtcJczGClmq0fT2uDLBi7WbcjsQbwbk05+6A5NcZK2ky9G653
Ykz4p/oowfndD65wHx9NGBap0NdyvGKpkrx4/MtijHnOdkI8CmwT7iIc4PvPlSbVHZ804rHyT0SN
K7fbYZQS8gxOeHBel4mQoEq/Rs7BpCNzIdhQjCPBfnvgut8zp/9B8J1xckL1t3D469SV/5nSrLw8
JEPob7rHCsx/YsttL5XrblZ252XV3sXx5kTg2GvcspoGwzaBzFWcb7jeDujb2B5Ji3QJudBKpYdW
rsBmxox0LWlPdwnAyYrkKr46eRnNbSuhyc94LLIny9lobD+Mv3sG+8yuC1frtK4lE4AdnsT95XBR
gPgHN6aAELLmmvMAp5yIJb0ZMqlE9wUxbYP81azTcGB/3in3wLe+oLAkZIG/eMiKb2uOwpflfOgv
FreGoUMtESD/TJTlCh/0qAj9J+ZKb9TDIQjCeJjeK0WZ2YjsNDDgS/u8SuWK8fhJSUCML1fChuCK
LFeNpSdGoe0qb53V2oemymJYy1hrq8/JAWX1T2XgRw5iPv8FWb18w1YCV58Q0ppPBVcGXTeKViQY
wXdaH/gGEagXWTCGndnCQ4gpwjBJbqcorPfDup8oXaitUhyrbf5+UIzDxYvcX4PKT7Q0MU/+0Vr4
TOXcCjouQcTOMoqqMHyLFhTA/C/cq0PGgBbPoY1XJEqg1pQu/ZRSPspogHN7t1Cc0o3VPoyF4ncC
In1Xrq2wn+UbQ+pLlfr6vgT6mQQWcDxw9LCJQCZsO1kpaIw46qJcSAXskRDpVAOz3MzkjNlKiBZs
hrGLNql1kmG+YjpZuC2JJ48+Nj9LG+PPe4QEjfrkGASprXpKNFfcO5RtOK7s0/3P9tHPQ8cRHL0r
YWQKyiStOpiuPvw8j/WlqEkXe6L2bLnzQ2BATWVtXD7n+HWszVMYsLfacmQU7zU0DsTgGNZt0OPV
l+7KvnaWrTUrsvkrVOzm1yynG8u3XeF7s/WNNVWSbgHZu5UWSkN/peR1BXoHVDenYBmWN3kPmwqI
NZyfI8dBivkDuPrYQZxxvtiTd1AidJ3/vZ0OxFFgSXwjX9TotssB9409l/W3NgQ3LeBr5xyeUz88
LtuI7CfXJoihwm/QOfZuAnLI103NGf7ZY3SBp29/Xhv7owqJagnx1WKs9oYyKF4O+s7S/9EPVU91
hjzsISzNWDaTcDnDI0ZS7VzrJlvmVf3Ry5iWrQ6gsSFccMfjYLW2sbxBXAuFc+0UsKKGZFH21kPN
25xkhNQYeXd4G6+3absPGuZPKVmESqDn4pL4PmwVH0wuLUBj67sueMgMZet+2QPkj+fCUSPc2LlL
l5qJ+A2FI3YixkjgYQGr0s3Q9AUwfRkNrXH9NbzhgNPycbOuo2LUKsR0fNJD9Jjy2g5rIgJiTK9i
W14Zn1XzP++7wb6lSdClltFCSQejGAFp3wd2XMFYSoDoO6DzmH/mV9WdDEjSSg/Q8D4aHjB6M/Hc
FFAK9MjhyCBHCDC7fd63YK8+LsfZufIjSGJLzjTrAxADc1tBSGv6l3aP+ajpAE2lXDn+FnSfOfvQ
ppjHelf+Fyoh9aArFcZKwWfdwg2y0DwOW16pQ31cjnKdQBIuMjFftnZy+/pJolgVCqGI2xYJbfSg
aBAsEq+/tSF/yJu6QqpwjfzDS0KtRvDAvAJv7D9PAHN4YNi35D4U2KvTmWNbm4mH0tuijPQrzRYK
MM0t3yEnL9JFo89CR0jVAYUfjt6uIxUU5nXWTuRhjF+9mzzzJ21Xn1MqC98oYHrpF1hzzyyU6AB5
4tGoZuFs6BD3FkDnhfB4l6L/vIDjIxl6f4uveN9O+/1BrlP1eS25w5O8YlV3qSy3NV3VLJsRoTo9
zstV0eogj3mYio1QLqCaVBVHUNLgh4ZnoqdgYn6nTZT89Qs1f5wjJDtLIZWGhvd9rGwvCz99Ix8+
8n+ahal2gLL76aE4vKsTuMYH6QSSsLBCsqK0U35SKzMsq7a/yarBUG/tQm/frExr0bUUnlfRQpjA
TcENqgNjvT3WPFIpre/4LPqAcGRCUmtJ/HEYZjx2yuotGVNNN02ko/Z5LpXK2EjGMtCbLZ+Ceo7Y
yHRAp7w0ppQh9TqzzP7ur3amDKE4ufkd8bvaZBu63Iqffdo12hYV7dD3xtHgg34tKwZmOE98JWq6
MVTYuzHzh2fH3ec/kk94sokEAekZ4qfgi+5zQyGeDJxo4eCEK4F0kjdEfif6oizoAs5+nJlh3WbG
pVTnU1cyGaeKpSmCV6Ow4FLq+y0FY8jYhfD5WLAjLwkhkEJvg3F1J0EIQv03ep8bjdtexZdkTfYI
P4T01xL8n+lrrTXkXuxTVRxmdyUzsXrtI0pUnaWrX3IOvlzSugJvUEtysRhrpYsaGbzoQzLm2pbD
uEnVj7ta7v8IKvIDmjWjfKititZ1G6FJ0pLg8wEjIQCqMVLSvELqTCOYFnwjgY/Df9nlFdiPSRJj
zU2uUk/EZalDjd4Ho0N3DdueGlmFBuj7NgCCwgZY7i0b/vsGdi/iYauE03Z89m3IzCTvqSWzSzjS
HzLOxjI6OCKDL1++/35N4EgcEITzYA64gtnMdh1MRjWloxsEUWntvfLphEHIJL2wCOQMAciZo+2T
h61mVqpYSOqT6KJiPDDW8W2Y3g03hl7S+KqIruTwzTFx4cMKRrQdSr0vJFxjCQW3PfgtBKXa4FT7
QBpI3sVlxoGu/vggkkq6CKVf4/UVNIY7hhS3RidQUd/MeHwtIa9Z37LKyiH8hZmaFZOyNY2qOKk6
104/aWgz7JEQkV6Rim95imdcP4goXRvq+39yDXDYidxDyr67pnde2wTzIFRu4km96c6PY6AI/KZh
c4Av+zKxUOM8WA1eT4yGRs5UufWh2fglSHDOZOm6ciNf3MlXMoh43dJ6bA2uprUarjEKttwKpD89
382eKzhrX1L2kWnM8o3HxcIDfx0J0mWBUKZLscqHe4HTimQCqzgryBjEgnfWavYtjORc2kUNdli9
WhVYl+OcP90yvzJ3Y1V+97cQ5uHcnOGtbXzTnd4CI57oDCGyDzgxFa4Oq6pJe1Y70csxc8J4eNGt
A4jfc7tj5fSGUwt8I1QhzPvIsLUTtgQtJdD6kyydKLtiF73qqWSxtYpFwDtVgyJxFMJ46SvvN0Rx
JlsVK+z90BcY7x7Tiq8TJ/ExZj91zZm44wr1NpDrFI8aGkFO5y0ETRMPsmzDI87lCiVU8t12+KyH
qSKZr7kq6Pfdt1YFowbTPOV+3zOLb74QkC338MIos0SGN3G4T/i45lKqtrBNqTYO/qm4+ClAaBtG
1mmDb+hfpupSPJ1P+tTxHJYhTcUIUrYYBAUqU8anMvQlUI9Xy/SdM/h1Lh8qtP96Ai3/fl+ahCd2
EXvnBumHOThCemNFl7F6cP5ksYeCdSFy+RyF1hehcwkvguLRTb3negGJjbBOcmrKyoBb7CgGJmc8
bggi9t68TqitOu/nzq68FCyNXGJFE6qXWOkrQpAAGPI5dcF1aBYzlLJHt4hHb9lj+GdKkpgbDpfV
/cqRsAPAOgEgwfPWbZPfkMfOREhLOz3t1QDijSSHMmN9rNl+Fu2xQVxd73thBuq3gGJOb7KPCZC6
LPfMzhrxNeM+tTw7m0pKzPxBWgNePniCD0wUl+lmjKSbl1Q6dAEqPuZQN/3PK9x6pZlOPHGtS6ro
TkctCxDk44exC3NrsZJ1CQfT1PXtttewFuWzSzlxQMBzBWzfkN1io96HdAWAubD/V46wjQo+p7zj
cr9ZHnrSlUEgvDtbQHkN+clm3CzlB8lF2xd3g5z60SopeHCoIvrUSuK1MOurJYKZXAtaRfJHynQG
hVyndQtzjJ/n4iI2r0mO+xbJ5JnZKi7OrvUhonR0XqxlN2aXIyg751+T64tdu2CEMbPXJsNUjzzl
pfQvjFjUDv7UERBuDc1RqogZXCMLL7BefyogorwrQzJRLXoD+5CNo3VUFQwNhXABtdhzeghZU3Lu
y9KX5NzKbPk7w38Gyo1QGahig4MNQlVI4c0dBJJHAcujYdt/AL0mzEnbErSG3a/7KogFAj/HD8Pn
ZXVlWFm7btd/yNjkm83VStSD94jJnS4JQPV8fntw0vs1Ivq3RJ4OlOkflxs2amt6bpcYX/mqsLAz
2oL1TaejPR2Ok34IEc10D6PHT82sHEOnhl4KwOFDzTm1U7fecx7zKhZaVjwMBKs0vrZx+YTl6GDb
rRyeey2QcNZN+kuBiF/UodHmsczFLowc3DqFOiCzU/vRPzcZisCVCUVPwX9u5O1T7okG4/isD95M
5C57vpGLK9DXNFM042CTRtAUTRbySxVPRyw4p4QrRdg7nrtHhHtQg8qCZHsw9VLx6ndA2I9XIPnq
f7oi7eL3OwfiT56shGyooBIJzlbvRC3WTGGx82eWmDakeD4a4GPvTO1BczzX1ozrd2ARM/1Z22hZ
kSzqJVl+I6u0peshzunBshb+ibRx/PPN9we4oJiLjcxYtVkWBLEvMKklN5wh5DY70hL9zHWn/UAQ
ijF251DPmxmFxAGk2fBa8zC8zpPrnwbDzBshQ9yPj8Fxy9oHmQEy7bdaVWXrX81POyKEiS0rj8BJ
E/EdKnMY/58Fg9w2Dj4lsUww6gURgwKdJ9E4+Xkj4ckW3TkhdlDIhyYwppsYCjdNcMXUglX3Sv3e
COg+hjir7xEJ9ePuMibpCWXExzVlbY+XAFsa2T+oTJt2rlV5TWzjAPmQkAgAGxx4RHbeu1nYp0Ej
w9QJxe3ZRn+p41nL55kHz4bYq+UmQ8f3Q+9zX1ci7f5Mi+i18YEBFIH/aa07wsvoGOnqcAffalJi
A6ppYxQwh9k5k3LBqimIqK8RPkwNZwHCOlSUuKWv/9wmk3CBn09wdlumHQ5UBxCV+/wMTpCl+gZt
BlTl/eXNxoH8MbTBG11zcESxgKMKBEw15KMLzJ3agGhsB8HDhfxQ5jnTcDC2BV8I6Tslg8x9GgHY
fMmk42gaVmw9nfl4HjfVLON3mRRZrSx9i7CkEHpWwmsJJ+o+RNV3aPX923nVeAk/C5RKoDjZw2Qv
nIoogWEKt3R/uBXB5hxLTGDoyQjopLdXGRNj+scu2fuReRlY7s2Lyx8XWahTxvXLh8r1jj7pncRu
MBk1UHno02rERvLrfC0gYgj99dS0p4EUR+yS4m9C8Yg7oiss9Y5Seso45oNIEQH4X2YTeVSYxUnN
FIhwmjy7JXKWj7njZznciLyX6MQ6xrw0DGGnopoLvkPMiway0MG918oeiNkmgamDDh3NfSe20AcJ
ZYHymFh77jMUpviiDdNkevQqjGwyfgZMHJoPatzdgwkbSPw+TAC9LrNwuS/7MgbmMxnWCcYNw21S
Zfl/xsVf23vFX+e8NoCqWzypyj6Kevx/DD6V/+kxj/DtAcUOVgtUUihZRlLgYBSOypYL7JHjdSrg
QWG7UKdu7e4DzLe4FEP0y+SE3Sey4d9LhNvzyiUyCBjHAQZaTXRh9fCXMrmjFR0Y6vVNQmwXn8wV
bImai02XrNEuQZGu/cEW3UX7qpebJcHtIiQahh6hJ/PgCCEQqBDe1S+olRkghQD4lYL6vY6P+ce+
C5YOkdKy4uuaBup4pkfmM7RYGFo0ifOxIqfVpR+5YtwNbMQSWQ8YJZpbPxBXgmSITeRaYP5EAptF
+Kbs+KdmOBc2er/l+Xkd82KQNEIIlYH7vlitHbDTaKEygSCB752yYzAQkdHck8oA1feYodsG5IAX
MCJp5grdu0N7OPZp+ywFHYBZ2sSG05JMYPV14zglXilGABC8gkPDaidYnHlGVkm2A1WhnT+rmOVX
05e74Jfmc5s/s2n36XLNwK/pNCoFxJVeIVtNfUue1N7Om2WFvDtPotOpLA9/yysintv6EYuc6FJ/
v435s4rWuWvxr5oDWkgbgyCA4JPjXRgZM8hoG95Q09tpQs6NoAzoRaY9Rfl2ZeVQPE+WOfS6Tour
qhy/Fv2pdV+6PnGRxYJOA36aIOb3hUQD/AUis0IbcOqOhUVmxDt2g9SmvZ20qrAv+7WWGv+lXoVq
ZVVXuARJwngp/8exScqwtrLsIxIoDmPatM+emyn2ey6bJ4evg2wBq7qsX3WmYX5tfom1P8N91ZKB
3Rc9LmXgAb/OR5dA9juRhgaHiJgjYiGNR0/tNttQT6MiBufnk2P6SKws7h1P0L1PSbHmiTAVK9rF
xgoCEi+294gUgIyQaV+vCaHoun1g4Suly39kW3NISkDParAon6/K4xIZajnrr3OIFd5GoagIGmWe
pTKXYwTxS/BWzjEueh9ZsC1+IKHTOKjLlE+zFqPAPyLY3YUtZknIf63Yivkv9flaPXbCSr6XgLWs
//mGEsCAAwkr3ZNi3vL9ara+6TFMZ2iM1L1Ccaz9xdyWOpMC1yxPR9OwbplrA+EbDf8hFSOXgM8y
9baRvKnmAiagpaVRxnmAbIYiZJxjn5n4zKa7VqKTze4BrPH8wdRg2pYQaNOotUPq8IkPY4+TVyEw
fx8oO8YhaXgOV19uB20KRsW12+uVHL+WGi0diyBm+4PTBLUV4WXh0o8BHxKdvm5aBE2TWXJqM+0M
QtWmAPqPTQFxFZUzhSOmbVJW0PWzI9kcgfHl2kCsGEysYs+YtTiI2u9xWocbc0sSI0vwg1O4vrEC
S3ng1YvMW1gOMrwN0M10uOVDwTLsWcj3eGu7GBqaNDqcgFNTTRhRRCK0DEDT5nLF5zdv1rnPYlX8
uE53Lw2hKCrmEO//B1A3z2oeT3vlN4yhEYNagwwGE71kerGMnOockPawp0gYD795diuHB/0vVD81
OyGZZaxxVoKObuI/OQzcV3su1M+J2SEEedSjiWbls6g2teH2zMEraPAtOxpKbs6R2CVSFluKMLDQ
onyIO9SLUushySeJu0urMghfQX+SkZ+gq/obJPbQeBfcvTw3/YTj47Jb3wPqn5A+oPLL5GLYP5jj
WpNs+oBoDwce8jaJnCFDxr5u0X0doV96xruTY/NtUxfSgS5NIViou7if4A2i5RUgGlDozkCEZRmW
ck8dyOuA2gA30P4KmL2EzUNXVjNM3i9yvonpiKS+WBjAicqFkhQ/k/OmONaJ7fwdJAW+9LEiZ1ij
xTONYFiyq+w8dk6tpGMlY1KNKu5zzXhXeptBm8Tp3WtI1tQYLXUW7Zr9EsR2Yp0V87vJozX1xhlP
CnFRn5zxfMJTU7BzB7cN5sLtGK8Jz0pO9rwe4xxSA+XXj4u04yvIhYNub/c2dWQoIC36YsjIXRTn
tNJldevLAz9TYpGP0qYAnu1YaqFzDE+f1bStkCaHWtbqC7nHRjQTmmvPUEhnJ/0sZ8VDQUHLHWCG
34Loji5ype95i+CbSthVxQpQHhlkCq9y8eM1nPZKYRUpdOKdAZzr/XoYLJ8+J3XuEoGxRpqDbLU2
fq5Rvi4d31/7zjIPtxht4Biebx6ZfrumN4Vmea6QUHPyjBRjolbdC6o4XkZMmJNYUU743pvUJRLL
6hQn2A8UEvirw3Yvmh+2bGqdyen2Mt164uxUsOA7rDRXYIHLPB4Nwa4YZZU76SEVEVfGATaETep3
SXKXOCgWY04gXkZg+4uFy/+bH+GjoRTBQvJyeQiGaDoiIeJtKpi/4CciIrwrS57pICQeHU8/8dxj
L30YrMIHLs7m3I2iOITy48t4BrJgpuntiCNUWBYcDieKQWlTwHQ3EaNIFlqEBCjCuGPXAHVuGCTX
GwAx+6LKOb6+xRKIOBOyxWkKbKHOSI05VZ70RlN26cBWkqQLVQjx0uKoK2/t6cNEQQHEbVVs7dZe
eYykKbkilCrIe7rXqKuRVFWXF0FOKup+2BExvgN6tqfiWRLpKuLNFr8oWBAXeBToGw7VT2jyDgJE
cV7K+k1nhzegmW1rgnMNUwA/GEVpnibopjnplwGViixt5GVCs6YrT1yvrJ3VULGvRmXOyjElGnvY
XaqE1MZBg1d7FEN6EBL2Sb/8JkIeAQWibmFwqmS/pNeNoJIau2ylCrS6hOW2qAyWQQCHnxjb0WjI
p+bupTRfZ4eG/9Z6ughnlCbZiwvIQ+i7z283GqKlMzrsNI+wfNsrbAhX18cIedYtKmZLGh4d5PNW
NfwZV7B1NGaLSXpHxmLy6z2anXqUt5ElITlVtpcieKW8hts3T1YC0TftVkzySxGnRPukYUvFNyER
98BHLRAAykRChtJnAcy8wrE/qSbUZYIofYp9QvIfa2WjOjrPvSdBfpoJEmMuPQ3w+S8+t7HBH5fg
239WYH8WMhTpg2UDPd50GQAa9O48H9huuaMqNKAe13/nkM0LwksP8Isajd8br4ahBFl+yRBta4dU
LDd28G9akQDkTSgce98TmpvwoURk4nGN2G4PqL738YFjXvhkHHbxl54Gz+uU8IAZp1RfzMjlfOzR
u2ufRKvK4/CnPwS6bN94JFG70uMccUKYpTOYPZnMkPSLy9A1UZ5yAzgkSAu+YdteRE53atgWRvku
C6iVZ2QHLqE6pVJtbZuF9/uCq3EpZGmOVMSdmWS8iJ2DSaGPiI39WkNR/2neduWsaez/XAvqfoqZ
n2Q3ttTOntF2phR6LDZ+BBZc/pnAqddlp6H8fzaFhWwWReOAkewfP102gHcm39Z5ZGA/oahh3WiS
rvJK1NFKvURmuq7/tAne4qmN68kO57PqzXCarvhIOvh7UfIhB35XIJn2LKxTTZXPTvZW0SJL13C8
Yrjr5C5YsNSyASmoKZEZgu//q9SpH77b0j5oLoPzZVKuTotzMv1M5M3csNZafaOX0rtm0le2VX0Y
neEIR3fVLVrG38u8P3zyNCdy6rfiDTT12flep70FNtUeZ3bEcGncYddTKkz6HEfdubF3kskqXDml
QrLPsQ4UBh+1qODwo4Ng/UTfkuuOwzd6CKf+IEzVZGU6U7OYb4f7VyrpkaoGHIycuFoQwVZb4b/1
IL0Swzz9+UQswGVanls9upXIipp40w9c6miM2NzwY/wfIz7bhQjPJ5YCu8gCFNYWflyi2Ie30EVi
L0ZhMONjjEfb0DD5UZqkANHAXLfFt8z/Cc6h5OYSncYcckYwgWODQ3FrIXQ6Ac4BVT+xg1KyZrYl
W9Zkj/5YOZDc8kVPAEvSodhIcnh5h0FfWfz+ZM7FTPstUMBTwghouhg0KN+TZREsRe7MOaEHBhop
Rv2pdK3X1Qp5NAwqXPflgfwVpEtgj83q3MMtaXAHXWk8FR1hoCclLhzgMMPsUqclatlwihL3s9iq
+E4x3lqweSxDkFT+L9bG02ENh2IHmOh+Hal8DqZifHLbl9/6CkLrXWi1GRUhiw7gU7Or6D818tPl
fpG/s8kQFxQkV8SRMHyqJWFmKcCMGc9pOhKQ0aZ4ACxr8wwpn5c5Xp0cRUQho+lapQ8aco1HjuwP
lDqQRpFN3SwkIoWhhiM6yIiX7BmwA4hH4KRGl8Mnj6MsD/6jLL1CrsEXZ8E59/aRFvj4wO340exl
tr5/d4TEKWTXJyGrlY25DEhFiXt1DiRCD63knuhnfmYtOU1dGuXFmImpTudCcrQNwAgUr8UVx7+m
vZ9Nr76N7l51GyxmZVFEkipGJpzoh6i7R0HIvwTovmu734rSBjaYII5aEEW4UROTVOLbqzrzX72g
wwIJYdpFkqXgQFiJWOkZ432UgjfkNhIyMnJu6R6sOFtrF2zreEanSraVjsMV3jQeCqhSDOw6KC3z
aaTn5BB0ijRLekDst61FxMJPn+7DiYsE/mfsHyG1vjodixH4mcYHfvUOzHUYf83AERmNStiDaLN7
XF/+pR/jN3YeX9Qb0SWdeCWVpSwpOawXaPF/2JZxugiTR8S0DkrufPB/ttkHXp1aAcCC20bsmxYH
E6/x/FGDf/sPY1Esb07L70Vvy66X6eLTaMeMo/Re4gbOIgCIj/luoQwAGOihvP2x8d1S5Xi3Mw5W
mNPEROuTuoo4Y9GH14TusGtgXgMpJKFVRZ+0mBngM695Fz6umjxnmJj3Ph4I2/LanO6KqguOMKMp
3J4w5zLb/g1PkYL1syFOwE2sLwyFuubmX8xk4to5jGE4ouYfUUxAF9wtOUcCCifH9kjJYoZvOayL
EB7jUksIu35rz98G7t+9Owj6PvGf8w7pdt2ZBN2gyWa8dwLcvETcsaJNkCvCet/myZDLSx+XVAU5
6G+bX+oGdg/tMz3LhM4wx7HLv3Zf/tYi72zjmHpTEYDXyQzUnnABnLoqk/yENgRCYkbYlcyzdRct
+f1TPQSjk6T0biU+l0bOICIukOR7b1Rufk+WuXiRccm2o1gFIcjMFPhPnYfF9bjXkiSirObPwHYW
3MMk4KgCcStJOgsZMMuxURy6z0aG+ZbLAk191Wc/cZXRGjzTICL8jRdrHlDpEnodmqpU1OPnoO7D
AnBbvlJnh5GfmUXKk56wC08lYGoQQEVGSpVye/wazJzsv9sDVdsv8JQgIVuB4rBT8ITLHumYazcw
nLUDeTah8Le0PfR0Q1rm6X4xJM5oyHEk+xEvqIiH2ug89LQDi8g2Q6ExJkCNFmqvPgaedTeo3Mvj
N1lWxZMq62MCdWhDpO/RXiCU2wOs5iIO+BiR4kJps8XvoeDDuAjVGI18Cd7/AWW4/AxU5Lg6q+HK
MnrqXKUm0EOQOowpGGqElNNEfdqApmzZu5UQhwq9BLbOLzuE9oIsenVXDAR8zgdjNqtIxvS9XeJb
Aj2Sban1T03EtN28S48wzg5xlYvbV2DqKk/6NEMAt2Pok0ZS66FPaOxHRXpIAJo/Ko4W0JwtjM55
odQmkLpTd3LC2DHfzCOQ3LD2g8J17ERcJ51F8bJodDMn//s8pfUoQOKHfPSCof7RHB23zoQDsjRQ
jngYRx7o+pCI6XKsFvQcKmDdnGdYt095hNKISV3Aw0WN3eqzq5cTvYlHHDKLF6DXITNGaD36uOFW
TofVYFkztT7lQJ0FyhPoSCa1sZHRbKQqNYuQDRvD0LOykD/la9PVXOtM9JRhkXypGuaidlqdO/jb
dEPgpxBLvkB+M+9CGjKMzPOs2nGFBDqroS/OmOIcQ+qu7hHNaXOcD343jukI4MNUU6ClDP12SGDw
BHIlaI+5BPMYIWHtF/PMONRufBr9ibMKP5EGs7P+6054EzgwM6s0o7IwcI/mnUtgAis9Ge3/IVwp
vZcvTEsOHoBIviQvM/HBVzOVKRolG70SDIMJLlUk/3Ifv5J9o/Ah7/Bzh0DAkm2xXcM0ALGh480p
03MkvFHKsDsKDwaWM4drYNzvP61z+FPc+M4WGSgs9w5rPp5EB0jNRIkvCDsrra0QNMdaTSd8o6CK
nILo8w5Mkr42QKbUuJSpz5Ow88PrjMj+1kOHB65+xtqYTFcwZ7/xdbFh0U5324NA7GVnGup4Onf4
wU6ChFbUwy4kf6dLxsngfebFZyfn5QZA+fEEjdFElaJRtMnh13bXv16xE7R0H4shZoxnM7i5adXQ
4SGYVmc0LjvJbi1YaH3a5u6kmRhy42/YDUsoR1fRi+xYJd5/zbmKa8hDITK8+RmTtWZ9Dj3nEtZL
3obhChVttsLWuJv6Jaqh/fJq89I7kKGPuEkmQ5CCEZX43gcd7AxKK7lkK8jI6mtCgANE9x215Gxv
dtGKS3Z/fovB71xcpK9KQe7H5Z0H+2O7oIWV1XZ1N0ftZT3Zr2Ymt03+BVdCp4MDc+PHEK45samT
z3020x9MuZMFqZJdeLOnFEBmNwea1cAMxEz1d18QxUjlnTUjjo2nDc3MhK6nmzRu5hm4RDMgqVx5
3lcsmxsLfbrvwVjcQvviAJDuHO35YJtuqb2qFhElisGYEqEQlpK/pgb5R7eDm8RiG5wmDcWzZaPD
UNElGbso1KL5mYYEs5ew5bNnnuhEGw/n1mO/j4fNtq716s0MK9jWKGh9RI518VjwHGzAy8KiAItH
pptW6VrO3UnUUKVIV3VrASxjR/iEBBHLLtrUQJlqWRRyerOA1FScgi8ZouteGAJhM1oSUu4PvGuY
NF8tiAEITgZnO4yFgYAhbt3XK/1ZJv1CH1nJFiHNZNFq5DJOvX5mze8zAqA/UqdDvIA3rZxaurNf
a/mQr90+/JBo7cQyxcWauKfMXkH+Qk5iq7owIWsrtEKS3NbFgsOG+5ZY8csCDKjUeGkHc63XQVSF
ujmrxnedBt+rJbA85kB2/EaIfMzKJ+In7oI/rauHCmjYn95BhKDGyfvTpq4RkC0AuvOg6C5SMrdI
bLJwD0wFQRubKNH/ZMmlmW+NI0GkVr0j615nkX9GL47v8hF5Liv9aWvFpeP7ECBUoKTnnopAXrOe
hpQRTq9drr6J8yocQJ5FUOKBt2KNFz2+3KImyXZ5aUwUn0hW/etSythZhU15wbbP2ejBIzfVr4Cg
8lzDUbzA9sGzeqCMFBPEI45V1CHptz1L3gtsD4KEsF+eh+WRK+BY7KyDxBjiOKaVNIxuh3JVVDcA
hAHJYAP9jwF6TKRFo/pvnf1HflyPnsptjmRfBHhkZCeIBse3/fBDSuZRA/GdMb2QH0uqImTOFzaV
ZLU4hQ2pfWZBBJDL8J90Y5vtNTaoVDy8GmogsER3euGkmfMterO435nbl2PsoNk3Kfxd+srSRjh6
4YkPAoHH5x2wP13AxiOIahO6yQar7XbIvmCDIE39/AxaOnNgcG3y02UhWM/wLVKJuVVDIjpmYi9l
IyxGVaol3Ah4gu+qLopgGQ3vqK31wT5hmeN0tmDC/2E5HLDRmKNTZWZ8I8Vvcjy5aBk4O9m9ROFa
lCU395EqGhy4pDXuNY4m58TguNa8cuUC8Gw5P4lCarDdt7nAyDoFjFy+SqBV57E2o02wUszI8BmZ
ZpIIedB6WNwAtsU3OeCrLttvmnVPJDYmL4X0mz3T/kybgn9yvOwz9fTjkpA0NzlxO0ASTFbX+XHJ
GzMU2JtGTA0GxphYshsFRIdhcAoW7Xgm39skU4ufNGvH/J1M0M4wdfeMpNObnG87lTQ2deG0m1ca
fjjeWB2mVzeZb08W8/ENsZyXtSdldjD2xqnLQ/iAvsF6BwMXIPx/04F1S7qWIc78yt/yjaV9qjlF
pMLaMZlLjbwoxE/T0Z9B30tK+kWbwVGG5hGRKS+X+JU9jedWXK6wgqiGhZXac+skQ5ZZWLjnbVOr
1oUkvqg6J1nhw8/PfoM8r+mPKLnXuzpfHyx//wOn/Qs4uo65P7X8BncqpBIVdTwXVWCQMIBw8I4h
Gk1D7YBQEeRfeEpMt3KVRG5dIFVWzdslCEr3lpNz+q7q9wJ4u/cQrREMNc6vHb5ndLATNKd+/Xaf
XN8hHQFw33zk0jZawXpnaTm0bAyiZLvw5MBmDXz3h+BKAJFCvjZ99eq8O9cOYGCfA+nnBQlOrEjV
utoeVh1bKFrqKQoqe4HZ0QCkobLWU8oGIufxbeFTdohmRmPfoXD4SjT2j9W1QXg3Gs6FpytpElLg
aPSg5lr1XUx/zlGaeogpoMZb9Zod121f4IXe3PsvrbaKsNAQkYlLLYN9sA5ZppKrvwvplUY9Ls/r
FmMXAaD726JyMffKI21E7x8CtbtVMjWVHNi4gpj9PrV7ywmLfyETWs7A4luIYIRgys6/Zs8J5n4x
w3X+dTVw+caRefqkHLiMpam7uPPofbegV/cKGcSww4Bn3n06yE11H/YQQroAwLQ6LE/f4bAIopHK
WizJS0OxKnoxHorGhToJzhvz7j7mB92G1n1K6UocLN0EjVdqq3/Nup/ka/6gy/cqE1SW9B+wF+ad
TGje+o5MsSpX7HijDud37d69ZIcic5zI8pH6CgL/oB5dA+lJ4YYf1TwngBxDwV3tIYsyFI5LDzyg
jDe1OfuBpZYfyXXwXRj4Jj59QI7F9XUJhGePmeEUWr8acDnzteg7WksNsMVZldyMmp5LdlqrMUr5
RRTiKjA/y7mNyK2v/0t7/nLNEPvwCWNInIwua+6HuXNy2iBqYxSwpw2XRH00rFH7Jak3jQOq7X/F
46h17r1gpMD1ulzPbk5KqdPFYmlkOwEmhEGBDanV9wiH/vi7hvLy8GYHLUMVdvA63ON3SaJ5rezG
ZFNhonm5sor4dZrvDRYRa7rgcDvZhUJ/YP9N5BrRIWyu+0tUacnrZtHKq9nAUr65IVKY9Kj1fInz
+eq24BIxav/wg2gvIlKJ8WVMnAl5nlGc6Lfy/vDMqZ0Fhg+/TCxTfMZh3vH4ZW9Y21YCPMUsquym
CEe2+A321lI1n0Hxs5jrxnpmd/HCFv0xtXPvb5Z5Zq/1bvEWYF4C/cASB6P2EJf4YWFi14lGBZ44
/CrGDxVSPZBOH/f+YPrtIionssnJ6Rcugeh26dPl9hP3NtuWN5eQLfLwHir0rKQ65ufKv1siEqd2
OuN8xgLQvK2sHDjsoRNn/m6TDu3p/Z5kv1rOt56wmQzg/nDD13MnMGhYACnJTIlHnDhVuy4sno3P
GKIWIZFeAdTzJtrtz6vKDujwNay8bleXXaVyjqg/5+N3vp594ns4UgxMhtaY+41Nah3XB8ep34IV
IcMbUmWJNFjAMXRYYkodgeyLCNpmYGW2LpPVMFd0F3LR7TvrIJ9cheVB8aAvYr6HzJX8tGFGHTYo
zcd9u9bcyUzqoaYpXpGxeGTHkOZVazog3hitdVGLdW5s4pVlcvkdm5EyDvXBSHx2c7VXJ53A/0cA
wOxTH+vwOpph/hc2g2O3MPVWpqYFoEj1mZWmIcsEnyjEIEIMSXyDcgbnW6QobI9KRcTBuuAmZX/0
mRtZvAdgb/fB9ibIFeKQBP7/5fRqU/wk8wjtoUCrEHu8nAcmBSIEOoNnFjN4a1l1zGEj/FtVZajB
79Rd8QGbyNVVofEWVrTgwZDU0dMoOiZxUoTAg0RLvlXz5rX20oF+AxbY8O7nQy7qi7fko1gzQcCT
nN5IhNp6EZQZTFEA6+YhKPGfV1q4xhvUB03lGevaF25xjogarqZusSqg18njQh1gTXKqEEmAzbye
K37vyh9PtrKBQwWWnNhvAq8uVbHd/VS2tpr2Jv+WDWTphO4yv+SFz0IOyYsnx6TEgtuZharkAIZ6
O6uJGYe4VsxGMhE5Fx6ful7ygeH94hBczNsf921j/euMSGYEtynKaIpHPR/dkqOk1XxHh6mR4ZQd
AxD4aqp2JSYWLAC1o6TPh+9hQWbnJvd89hiH6/RrcjvDCIUN3vpZ5GPRgY+9aDdpE7gn0OTtbi6+
L3Ydho+j4qfdUFI/v3+jjjVbuTBzJc+w5CYSkXPjwBWxhDFI9wcp2OdjrQ3wPr+U5tDw5JaqhBql
eMCqMA3CwpXrU6ZZ2w96VE7oZRufreNGLvrmt3maZmIEytUZ2xtQ1OyIzuV0gkfoOUhZfeIJM1Kr
L7rNMC9o+lCOXB/hph4OhSlcOxlfsMof8spUhca1fqo06vhoQGqUMYOiAtIVWah1OW1eLcUvG885
nHurnShpCuRjMIpHneLzfj2a5Or6lMwE/ZaZ2dAcR6RR1nIMC7grPH1WnkB0VJ2EVPuuixIO1mpu
bf96UFw6B5IOt94LvC++GF67Juvgr1oYQgq+S8QgsVFnoWFu6ceF/5i6XbYLf4HGMmBd4xiMz07Y
LnauvUD+ce9TAwgOZY8MXInmw2F6K1gdEDNzBS0nEXuTJsUyuSdwVoqzgH1nMY7gw3ClDigyduSC
LIGR4AMgMdQRovzcvYzTHa3yvsu2mTPHtRfZ60Q795zMZSQCmt3HeCzjCY1eTtT5cUhFub7WCnER
vxP3/IbPLdvlRmurLU+0TbgclyDh7z0OUZRd294coTDmmE9wQ9RsvAWMjnAwb+kPyfyDGZm2/fna
PRqX3YCbJryUNJQZbpfpmzoC1yRVU8FXpmtRCGeHBm5cZ58WCXnLcQk8daw0uDi9ZK9rgR928xa+
dPVFeC9j+BRlAhyguJH0zfUXBhNMalXl6stjrnOmib1MoU93N3QJviylUSgDBpSRb//tSe+iL54+
5qBk6v1MeGUKZvNxFfNMuI7Lcnr3zqjI0bpmqESgdPW9F7iiZrUgWCWsyQTIW8nIIfbNPU61ft3F
d+ZT99pXG3qtrTEUTdpfeAraHEX5zcSWGU4cNdfK5h4U3EMXc52mYfUHXaqzpX9rjiYaVKctvITz
yC69xlw3YE4haTc+t0JjrlAmPQHiVVpYVboy1yQ69z87DpAOQvSrjgpKBeUCSL8QrTdEmzFvsG4O
9VdxOPVG7Z6xzp0ldPU/6QykcFQj9bftkPHDecx9EULzADF87FP8klGFKvBFT1BHksSxm9z5iAki
OqITrx2ieop1xOzC2aJ+NI2O3hgsCo6SXY0C9uofjfKyir9d7qSGK2JS8ub3PAfripPY10AlDLLw
e+LJZoOSqF7whAdn7xISppQlQYb0aRqQChqZ23wCGmnPg/i4ydJ21e8z6/htb5ubNszMOXfrvgXq
HJFAi+7DILVH5g8Q3MLHqvlIaHOHWeUbjy1bDiFsDd+jUZAaNRu8zdWPKfteU3+OqBBGaY8HPP3o
DJ51ldezXgnTMUkYHXcWxF9NzJc2QIgbRoYPATMFfBnNJKXXY9gX2WcAoOxbbrM3DDT04k1ZBbeA
jl4bpphWxq37JTKn2wi60QxLN1XGSJeOAeACb+giFPEVBP9gR1VcnRq62nOQKcs7vvdiEHdwl1XB
/OwiWnyQ201hw6wZqonULTetctQBS+SIZimbhMdLAgoswQ4wvVxsRgQHRlkj3fHzPE5cs83y4O0+
S+3IIjc0jY9acd3+YVQq8ApIlv2bsQQam11x9xVdY9+H/GlObYTBf9Epngee17cfsb4Rd0mtx8ml
Qo4Cc6AJLnw/hCsTyXQydgn9hNsgutQowyNMGXVWGOqWROruzOv04uryg5wZasnXkMN/eVBHxSue
DgJVsBrzgtxF1NeqGHDX2YQAm6iwaxaKkPcbBEgorpBDYyLnVIXKx9fUXOdSnsPVf6wyzkDklCT+
rC4dah6yhyan3StyPdjK/3T3edZI6cm9r8OM4lL7V3MOaspLH6lG1PucOUy+mEQK14JYT+XvBGbP
2bcaUyGyI7uakVd7j7+vEndus29LD/XKbiji1oz7/eDsG8/kC2fgf1BHMPpVVEpknuYQYALpLz9p
PJyII2a9ptu+kfx6MHvgrFJegOUu0AwCyjAOelMpIQq++kjlg2gIXB7LKyxR8T93Kk6Y/ekDyKWI
/4DYdUb1OLdI9cBdMDXGHLaSJsfHBUucrO5CKyB86as8n7eeWSecS/GT8IUgOpNEFGUg9CCeAYLy
1nwlZ2fZZjFLunJ9R/pm6w0PTC8DhejAH6MrzdAmC5boS/ZGlNWO7OPeKPYcG3z7noBFAk+obgu6
m6zoZmW7JMH4rVeYASXA5TYnA37dVXYVF8leun3YEP0MI+nJrsOVKYOrQARlghxmIjWJahGJj0Ku
Vwqxsb/RMeO01kQffMapeZMFsMpy5Ghg5auFS7gzB58hfg8A1Om63VnsLyx6L0eQQLn8ega/ers+
d7MLbHu3I9Jw2bgw3urlN8TBnXiA/MC4TME0/ok/bqv9hv1CAyspzZm/VO/hY/b/1poNH8HL2u+L
hGU566IiWymSEMXIdPXv8ksitJRQzWXcJP40+gz5nStys8iqy2NLNpGU2rjIzTepzrBtN/pYIhq4
VV6bpjuFe7j2AzaoOZ0cduKrJv3C7kQgJtx/3h8lyuK/TyDv4ArvQrMWKzdg6OyV8MfTCW0BLlOJ
K+/FJvEbjLFbaHm1+y04M/LXm1yWrYn3fj5h/Gz9L89NxtcFrEJeIu0xKj9HMOn9nKaxUeLwpysn
zs65ZJHkvV4ricKLcKGY0nrSmGMlpO7qXTkF1EVc8rdtd+POCEptG6lS2Idyb1/DAV9zaE2x6vqk
28cBwPF2wG4juifKJsPr9YNopg/Pq1WDYjE1k2VwLyPDCnf/0riHmvIT6icBMsvARP6gPhzk7RBI
lLU7/I2Se+i4bIga1k1uhON+ep3SSwFeAH/ub2KO3HufuM9zrFkvP8gFnsf0vXNw/bi6DlUNMFg/
vCwwOODlL7Z35vJ3DXX93POpPbGPQd0sGUZahBj/c+gL+ICFASxlpI3ADTWhlSPY/ZyoxW5lGfEW
i8MvQmuSplpZ+QfK5HnQ4xuJWnZQidMAuoNXjfocvnkwzuWAmtBQj4h4LYj6hrp5tQzSYJMgU2+x
AeQeh4EufPMM/wC7OEGC1fsHppsenC2EAKGlsAvWhGm7L9nkW6INo50cAshLxG0drWXYRHH0TU8Z
VxWdwdKCd/PEveeMbXGcrGOlnXTaloNz8PzfMS4gM07gNgDwaXLultQ6/58FespMpgvrdECzl+Yj
n2Qfzi1/cxPKoSm2FLkDfGnlF3L5B0XmlZl1tjAI0qmWaW8SZZoSz/GTZrDoZUPbA0YVwpgBcEmv
KXPcej81syl8XXyLt13cH5KB02ITCe4tI6NvW4X6GLWWdhlkSMe7aZ6LjgbZ5YbnhXT1t3B43+N2
Y7lZ7nReJSNnxwcwEQX2cNcxoZ3rsaPfb5LxvCzVz+xGw07hxKMgEM8kccuk1LlUyX1SYeMq0zEr
ZPA+KicEL7OV5ad76T9BgUVVj7D3ceOhH+bH4KZYY8u49OWXwU8nIRdf5w0Md2GH6Fb0ckM5jsyU
4m+nd0izqoopHwMWFXfZHo/hqymku8G3rVaJhwdyfbs/KuF7iSn0KwWcFkrn3urnz6WlqEaVxtMR
pE38wcKhV7D8UmULoppHWHz2K/7exQ3kzjhbi+xptlX/Fau0e7w3z5umh1noXiMY/xTgObgP/O7L
plkYFRrh/wcRp3fJTjg+cdEA7zHOppsVnbC+2/NM9T5OtgoQFrJnoPQ/JitbYYAxiXsEeXvExXfr
IQfIkZHlboyCO4QgulCoOsT9JLezEnqGczecYJNxZu2oVlrOWJJo6ArM2AEjkTeRSya4+ZVVaZ/b
A3mDPEbFDyjgIyhQ01mWH0n2LOfcUvDnJmk95h1oYw9+DCYmwKRkw31Dd9gx2Na5KSABlQFPZzvh
UCf4gFbP7JCbS6J7DP1KFRdigEyu9DaZ/iJtH1hxAmIs/C0Z1GV+SGN0P6XgxTtD/wUXrrADlbeP
OqHKi45ak+n7k1aJSI+0X1BPWh5tm2Wwc29dvLo/qDGJPfGnyUrYAbUHtjLONYIAT+rbItjtlPVG
gqdx9qAHj2DbVZpuMw3/e6rJXsWeEdmkmZkJApGyQuyO5LxlX4W3bBARY3UZ09wB+DEhwHY3JDGe
RhNqnlpKiFJHk1OZHew2WqpYd+VZJkM1Poq8rZk+3E8FKfw3HNELBHvSUmZPlfmpSXgGk/+9I/yn
s3kZP8mJzrTUMUmYj5+s+6c6pxXNdH0KXLLTevQvEbhdKYLmGL0xoewjGqYrzia4S3wfxe3fwSsy
+a+1gGXNqzRTUgPgehQ6XBzrzPFCRpaSb7xXp3LYjFepgIsT09HViajzu2mD4yvtBhkIityj1sXV
ivysa5UO/CxTumQJXZ825UZ7FBFOJh3DDisv3AtzvhEbZVr5H3T6n8OQTt/P4mbwE0vO5bcb7SDJ
cS4wzrAUlXpogENSo1/ttzw/jkdtXIwltxYgH5kw+1LI2s9myGpnjYAqYMKIbUQsIQI9VBzhLVtW
y1n9msQC9qHP5Flu4qZPmC+wwAMiyo2aXC/xXj5nAqCNPX0hCnANOGNwUDWrsuriCiY1qYeafoJG
MdM31vn9k9PamY6kOT6V2qwgekOrDHfOQjLTuwiqMqgwBa9UormpcmmSEjb42NspEmlS9ZzZCpeE
GPhlcE6GjC5gDWCb9m72haX8DKthRzmxAJf2Skp70aL0IK9wvUWV0IJvdmbowcNI10bKyxeUJL/3
vMPsB2i6Bk9NsrzD9aC3QxbLJV5E8/8oMKjVqbGfKLDtp1RczVYmBZ32U/858hbLtQQ3iDreqhfJ
WWbl4qmR6IQMdXGCOXoA22iPUjyrKi7ys0Fkbo3oNtzumh7+pdGxbozrv9896CQYr76WcwVt9+rx
BO/EVfUIvzgzhFj4/tQIh9gUyjHJIkDRUCVQQXduEtHd5sjNYW5mIl8akw+TIOJ1jREoTGg/l9hq
diIc96JaJLWv0n4sK1k5FpHWIE0u0XhNP3zpWBrdoGVasybesGUFyEv2Yw44u7uSTYtZtsw0MwV2
VgFtBPf2WPYIGFYBX8E77FbqMmPT4efesTn5DDBM9JU6enNqVtHUimXIhRyc3hiFJOMVxjPxwaRz
vUPePtVNW+NrHfM3ox6VPn1tpaWJ6gn0IJkmT+EzsjFLPlAXCVztqUhXhPI8g6UPbjnKlJH+OP/+
5mcWVMV6+LAC9MSYcFdwmsFqfvwl/ru3b32/TGp/+fFNGYICA4bfUc2sASTcejmhqa0FxAyCtlRd
RMCdEPQ6KQ7VKHSy9TfpUUMi0aYkyAHa28OloJaYjL4dJ9jikDvj2f9btfnxbtawL3cmmbjiaaoA
m0F2cgNnbaDPsHW1FK3icOZ0zzJktaWk/DUFSjN1OtZzbkpLlX3hJUF3R8qr6twlubsHcyA10ktl
5g2AY1Ut78Hx9oNshBtXXq6O6O2jHJZfKlTHmlydwrduvGVNaMUoN2SxUwswt8QmVAo8j2J5j/X1
n01bsP0dc9swGzEjdlJVPqlNFo30ImBtqnSRLOBbWa6tV6CBONT+dZ0wZppYqDtab3uG90TnAj0C
NqvWpSfys1S6wskH+QEi/o9XG6qJOoSfLXlJQY1hGntzBUzUN/Gg+9CFnJrPoM75LRbgM7xlEQPi
coPldOZ0JxwkKQcqJpcIfmeeYmj8fM2iDFnaZB17viCkIF9reKIM2JYC0X4TzsmixdgZSBw5t0+e
tm6ftRszerlNWs2ycfmxCB+h5zm7CWqwTUDYtg2GXdyBzlgbCw1pvR4HAIUAYYMjmZGJVM9Od4k9
bGrfThjH1PxfMViIyanE9RKRnqlDx/2LpNeC0nlca9OPHaKrQeVaQYWpinnaUdn+m1SpwgDpriJc
6uRFXF474xIjMDY4HOSccv+cnoZNXOgPKrOmV7j2XynON7f/XpOYGDANmlkpONqGnhAqM9AqB2P+
0tNn8ED9FacV2SQoRkyUJLg5GWERAjZYSKPRQs+TG/Uu1OJwdihoA3r4fGcAOQNwGhQ30Kvv6SdL
mIpeOp1Y0tPVwtMuYk7WnZqCSbPVwn52PkouGhx4+8cWcR0irFtS4ozXzo+eTyqgUoAeHfxOwg1C
Um+omv9GPZbiGOj2XZPGYNQe0npKKRC/fk+0e+Cr8xo4KTahh/yp/rZ8tdbybghK7ScTi8Mhui9i
ssdHK6Kan02qON+6ViHAOtzMPxj0RfNPwEkmD7C+5Puk4aZbIcQdd6U9oufIrnEwGSKKz/Ra7ssJ
Kccd6wlA7mb57uu5y4jM+IL2U5LY+bGuwtM1/ea/zvd2EckkKGy7+03RSRToewjcYUyiHANtgfx8
tDOa2RLURJUUKAgDurIQ6ipKTs2E/nNa9GTjd/o/geCqlWxdRrDOeJF3PsDZcl1jAvf1pNS4yYPE
2PmNt9WZSOqkKhoqfyphB0nxLXmBroQ0GiIm4dPjab9hy3BBSKTfWpyFwJ+wEWIesClNvLtAevYh
QUATPEYKnohjVO3nxN8TlGHJwhC+wcPv52SZYOJp0kF3ETG5hHqRexumasuwSq279wVx6TzimNzY
Sis4b4u++zdIEhBVL1hE/he97QZ0cR9TsWIliHldU57NL18rxEJj5UxaAt+STjv9+/yIo3TsIh6c
PDWv9ugroZhhvJFTj9+0Yn8HDq1t55+omcpxpneS6aItmj8e3ZvZ6kLqHqtY+y4HMAYd7GTK2GHh
IclxoJNaBZ/Y2mJvXlpx9w86s7wIBEvhWTshsUCqMlFcovNr7Y8RMPV25HM2jFf29TZtuCqcJ7yK
ptfr8PMw7Ybwx7caPWx0Z2KfWnYRPVM2bz96kw1zBU3tfNv+K+hytxP/7goLFfSyuxOsuT+zjplM
s9maCmE4RPg+3OZcWz2wuusGfF2Tm1ix8VszjSC6mA35Iueks9P8fqVNzV7B2Gl5qADNO5ih0bHP
1PsyNb5gjJBkGjRb5se5zEG5Ay2JOS9YKJtY/+X8c9MG56WpehjSK229bkKmL80ZzRqk7qu9YmdX
RtmqM/ZMv90oSsg6hViBedwvHhf75z4yJgzxw8YUwUprzlz3XG6g6a5NzgtYUVSUQSzaG8ZKfpal
aut7xp+BIxBSVBRHsUMpyl+dk1DX3vKkh/wZ1cOfALoezs3SFqm/yKP/CHIY2Hr2Vb6+zwOOpIDN
UK1SHlDkb16sAQwec1EASk4eAMeRfc2dOJyNjbgRPy9EaDNpgh+U6MxM26iYwe1ckEJDRviTZc7B
pLI/mBX6iOd2FwRkUFZLUeIH5YejDgjmLxnNvS5mgqPXHLmuwAZHwilPDfFqjwIcKjFtdKcYlIlF
jmcagSM9YuEVYqP0VAKcpyEK2mU8c0YlodLT5qviEqHp1F98ph+2PawS1B2xF7id2JtueoBmajug
pRE/DQD/iMiqUHUHXe5yXZapLdCOWwTJimFI4+v71z6F2z4hAZ+1z/oyVP6wOkVDw5irBSRdxr0q
JS7YIQF0+W6I8KJ3TK7TONZYZyntsd3+9mZcxQv2xEGf2ZIVB7u0Y5/ccUrysJtDDzVmBeqRiyO3
AfzbSY6TTax5/Z5TrmkbxC1RYDHwUUrUgAvCJlofMt4qb2BVqXFVrP9Z1vc5QgM1c+kRgmB6Nyg3
ftlAmdTJgxgcnULcxfnZkjCvGmxyD3hthyurQWAJwN6T39e0Y7TJw9MHI1JfWHrPyMVE4y1Mca7g
SHPNTo6NNxEa8PiRPtBJ1gFDV36Yo1O3doz9C5aM9VKP/ennCaMB0fbX00YIEmGR+lzo+FJ7IufY
Arz5r4kWXEhAXECMaiz8pL8l0ZO+5YOznXLDpo4E84kxF66xNxeyZckdIXQ1C20r6v8OkNXuVPLl
Zx224YrD414Ki75r4ac4M6KC+g2SoWCeJ5fjHC4573FcgILlZED4zw3au/YYEQ6AwuzKmdqt/6Td
zB3ir4i5ch2IJu+EApWhevVH0KZFuTZlxdUC/P/F5gsKWZeReZGnvgy3qQ4UFp+EAC+g1It3nDxW
L6cE24nD//NOv4kapvSWLD+cr1cXgp6ly5Jv/Xs1wFd5fYnWAFEASjMj85fkLFbw4GywUELLwvGS
1yt01+a4SQ5OGDUJaMPsPUP9ZKPqbFLtzpF3dchbM2+Mi8QYx6Cgx0aTvElLFaAfIHZmWhpnQ+Or
Gnsw3JTThSvDmnPCu8Sufhv9itGVMtFmPZip3tXivUxYOVA3F/5Wfd6DR8k0o2fHdZKsCVH0cjaL
T164yw/k0AtlTfYihRLqoCKrqDuu8q6LdQ/DgaPWKhm1eovH1/8x2wfZ6oGGDULGj1iIKlEMZWDT
ROrZ6pCDpNfXfg4crAWzP7uOj+K4vPe8QNN3F0YJz8VY1zY5DEOWngV7mPLyntJrGLE/hSc4v6w/
Sd6a73sz45EmYhoKtLupSl01V7BzpAljmL3RPTa58OOmAFxi4WEN9nXOnYdNw4oZ/bTnNa1CqhUm
jRDBTNH36bOL9y+30zTM2I6CyDyaw3QhNqf0ribuayyZdiu74yGSd87Nj1Ckp8pWQdS4e4VOOZri
Qc3snNkq18uxwCwKZPjziIzDPmYY99naZ1gyQOLaSa/hAoJFFUUaKxfi2XPgvtfqD/mQkI8ow3iE
cNvjmueXzie6+Qj3ZnJWJ2FaAOSbfVmtplPWttHQV2Q+3EgDDXMWk0OYIaMVGedIMPERd8KlV+NY
50XaSByw4lwzcTnq2+9yvNvRBJCuSk81R271DI8Fa/bondCyfXCe7tNam5htdfoi/nD4LLG+7p14
iXTxsT2XHsz4tLFMWYJVaABu1uLkRYDdUxYGvydqnEUQaAiTbrH1sQ0Qe7hPIZXujyeY8qGY0kct
KmUchYxiXPyy3iHvJc5pkls7EgtW5wtciiurRLGkCwvT/DasOQLpAFWK9LmQPeDxag5Qek3djiap
Y/+YNH8hiwsPU37xzZoX5CTPiNiRwntOg3K3OwyQ4vxNOKea1Ebstr2YdzcU2ZUqgLMV0ZtFLIcY
DmbKfive4sY5rBmECp8ZBuVmD4YqQOgZY+ik9EFjE47z5ZFCsFd6xo8VSzttajkIMXYSsnLMOACW
mBN4W00c3rKVp2ln+OEzNgvNFq1KakWnjMkEtzpZdqKyj7AIoeny9RlNhoa42Pxy9eOTf5lNU22B
qK9t0havJsWP4xKpjQu0nfglr3AUGRWY7e5PO1uwMDArB+N18a50tNd3QqM5cPWK5QjxXScFVjlv
qJwHZ31SRC983sySw8l3C2MJaOdPw88WE0p6CysMW3jFeu1i90YfWG+LtnHSfntOqLNblaoy3gEJ
wduXSqQ9X7k6ymUDsKOC+aArYZW2HjkJVT0B9N4jkbVmbabLseZc6hMoGR6dlRec4Oalfme+jrcw
SZ1tmEV0Ch6Ws72/nLyTAP8Y/UGtWuREk/Vn+T7pQi5n2k/A3KIHrqgbEnVPN1kBwDg7mIWIlhCs
nQ6WHlvDntSrD8rCBJGKagm/6Aj2iNnVzEQs4GGPJrrOrsdjHZnoQ0dMgG+F3/7jLbrkryhvpIDp
dqjJSv3nX84r4Y/NMsCuEWRISXjD8UnrC9zgzA3bmfhpvAWo6sBoU9cJIaGpWrEoqBb7Ol/MUF6a
RAS2o2NkwXNkeXjW4u79aBqIFRSBZbPC43vXg4RRk6+f/Nqqllerk5eC836F476uOzyKRaiDIGzB
otddKOmHcx8HhXflpIN8B7ly1NKKcO4OfUJCGJpDlk2a9bSeR/hQ5XK7i5x97f1H5ycZzNT7UlHS
LCAlrfff2M9Yogzt78RSLIc0EGGzMshu8LGSyfI9K8ThmAwUHtRiVVWMe1xTydAsCT9rBQO3QPhb
e5AvjP2k4suRxiMTiksXSfYN6atHES3JBf3702GvDHVD++YnTlNV9BHVI/LqfwC7nzYdI4lV9g5X
anYDB0oagmVwVcQdXoq8HZ1W40GEFVBWckMGp2Q5+R+9e9ZlCZOHtyt9HbZOXgAo3QUd9uAsxvJ5
6xVEHH/Yn2RO9MZaDUA7jvd4guzBDS1ipgOApsTv5dPhC+9nC6zcG18kv4M7XH0vKNzLHrU8pyP+
72OmsFSB9Mf/gmTG0IZT8UZr3x+kX21rkMgMueLEFamSQs9eeU7H1OiiZplzs3jx0VfofQmLQpoe
P5xHXdTfPA26yijSaNx9V8AqHWa+9iJABTXCejL7c+oBPUJUf5Lzm5Z9MsvpDQhWVjhjTI8XNld0
rw+YlU9fewp80AnsyUilPisYKdYzIW0Prwb/yPwWKBaI96G59eNsvtRYrXQ7QaNtTy0UCF4sLmVL
YMLrzzKy/RYjgT5T10vCMVedDOvPTG3uTExHOeOGF7SHq7ZPnggU7oM4R/ncOARcgQAJP55k5za9
uF4yc+1ybM+zaYtc9oQs5zYTvHoS67XGQLENPwdzD8sxHPtciHotiW07Xy7IhYWoE+vNgnZHNOL4
pjeHhzWK7lv6PVdUZ3qrvhQZLyClklYrfSqixElGYxSRDLzenhSoTBteQ7kHEL8EREgT2/O3Zi7W
my0FSN/lrQx0RelJ5RnGESiq1RKEGPAhgkTqS5NMExm3hDpb0S5mV8SZSpeyk9QHx8Kt+kU9nc3w
ANoU7r0wJGBfDESkhhP7Mn0fgUVDQek0I1mBaH6CzuYUFLTwwQnwl9DM0PnTJ2AZHxkh84mFn9R0
oGY7U9kY7Fca9jklBPzPEtq0n39bU08st1Vjk7UmE+R/NMQK42fiXYykXvITixsbcvj7UPEtsTjM
KcPDfFf2AqPhfOPZmI7wQ/1b011VsR2G37kdIgl6FA+JSgs46tn5CUMo8H2diXxGwJupMxBl3ioe
O5y6j5nBWjnbrJprA0/BXwRPcbk/CXxrkUFSZxqlTY5LC+T1/1KH1cLxdIzhoQ91oTbBXsQMssep
X8VPrF1Tr5xe8hlbf7vuSVL7HVX/LjEmJakM4mbnY+Fb445w0XbVZ3kL0dJGMqWUteNptpqMorVZ
sc/0aml8v8gdqjrGhlHkx1VSuUI0/MvRITzJLhyRsc5JOoA20KPoNO+xLiLTByLYCmWV6W50I8yk
yTGG2RxqDG1GS7ssaI39e8mjOFyXWNKt0IYVZpCGWBGW3q9Nj5T3A2te77OV/6YVDG/t2NpaG4az
YqfmLMvznVgWmkWBQ6q54pkdT/ve74+XYbxSSFpOI+LiMBiSDkZjOmmkLqRoEBn4Nx8vNCl9UrjN
GyLiahYK2PPkheS1EhYEBXURZoUzbXNCSRiS9Qo+eTBcacImLg2qvfqSZ8DWpM/6wLaG3k05Wm7w
vi6NyIp/RtDcb6qmoPVh+l7wYSR3jtO1No/UsYdPwQGAxsDF6ivLuM8kREpPqUIil5ZSjnKwq5R9
M92y/IrC0/TWdLRu7mJ2y21lsRQa46F0gfESw2LFq5FWrmfDFWDKwBzgimadJa2a+IUPwVh1bg0K
rY3R4m0gf0HZkRaeQyw6oqAE4Jvzlr7/k1ijZLTUm/MkR2v/+On7eSmd9oNhl4xqRMy14u4GovAb
mSgaRxoAzKjAEy10tLsYH7Db5AnePIdqwZO1EaDAFYfgSn7vKKjTIOlx3e9kDPLsowX20ZqNgcGc
iWCm/pGIRAtiX8iWdoxqrXPSpdxoLoMR3/8Tbc4JyVCZeRUOOQF8sAo+1HMlp3jhKG1KntuDKtWP
rNLcVtiwYm91jihIqD8szR6oVzDRms0CoK6wTH7Ee5bYAP6Axc1/AAjcNvYfIZo3vMMHP+3Af92M
0z+FylHTgTuJtsvqwAXPjrTt2nO27dXm+VLmkpM/OtWJa/mL2u9LoFomZ1/ylzqVfAmaC9t4dp9r
Unmp+G8JA/uge3eDWrB2ZiIHbEz365Uhhs8PfDtx8gWgoiMMjBnF1chrvTJSQ69BSvTIWT2ew5Wu
6pSxcrVeYvZj2JHDBBf4lhsyKsDjmsVWbt2/Mt/5w5I9FKHlEX6uCvr7hLw7AYa40cMYOTVwwWRB
Mh6ossDOWlkzmUoNZZpz6+AvboiY7EZUchMbwp0A2k7YfcWpqKMxMRtyXy5cifRaQfs0GpEce9Xt
phOmLeonDvDFBq8aGKPDmuGOx6cLrkv23VlsqwX8IPAZqNAOASUhTIJjHUZpAV0+VicmGta/v1Gr
loi6y8Lksgims6mtiEWOpijhHlGtrNyEySZZphdFNayzt5cVj3Vg8D0TqC7lrtcfDeS3BPAbCuLx
nZW5SUAaCtBAUvvapYkmVPXx07gRrlQIfiSpidPDbOPg7tQqD7lfr3HJmagO7qyHvOpBY8R9JsEU
tZGpj0fEkGXuQTBimbEhjSmapyAYeZODeuT0yhy+TM4UmdyBv9/bwOxfugtIstZY+UBCSaRMGTi/
xoHbFX4gTFC+3D7m85Bqff0suFXrSHXQtmr9iSiQ7XZfefEw6zHPOQmkMkQw57JHM3w3Pt+iaKSU
7SxgbuVb204XnT7WTmjn5hgYeiyDXluETk2iufaDB6hq0bpXLYG3wN3y4uAtytwn8ZXxBbdZHT1V
j618Clb4lU4GHQY3hagLnOEUT7fYDCPTxN4YGAq5U/xaBUlD86iAHgw5zZIrXKtskKdUXHGGd+hU
PSfsKNxakW6AFFin6ujweUDD3A4t6IVFPfGCIU39Fk7y4AYEz4nGbDQ46drNn+k9E3fAQ1FO8ui2
KaxKO6cjGnKOJ7HpSq/dudRAZslQdYnvGsKvPyOdtdLpuCLdysSdYQHvbGw8/Qn0qt6SHtJnRxPH
qQ8jkn6LeNbTFrIvq4aPbqUrNnCt2ZMg8BbU4k1CJd5f02V1YIbz5KhptNg0cXLI2T7mtffe08Kh
QWH9+p5VWjZRImPfa+wte0yaevE2DVkuRwy4z2Ovzt30ImrWVvQz9reyhwPX1+wpVSUwDXsIlE/4
Ae9FCH8h35LduJlEMB575+fE+x7L2wmTGSn2CDQzKjZiLF4a1O/JxQMUKFWGSJAzpm5As30Jn3V5
JJgtP7LZwea9Tp4FsryJGpYNVK7CHpzK2dB3/XWGA+P5O/wqmREEbLtM6H4scI2nCCFC/HnhWg/n
/jfldqhhqDBVLqdLQJLwaWSCpH2vZSu9yBWDoV/xwV4r80b22xVTfcr1k1sGR3904IH2FOYxr067
MgyBEPa8aA9l6qTMWe1F6HAspcAbjgjH2AfXs0XRMZ3gJMM/oI6JyyNFPjhj6AMy3NeLI4jh7xn7
pXgpreEf6SnLCzO/twgOa3EHdByr0WiOtdn5wlh4wnSd7Z7/GqY0Ht1+NXMyLYAhNq7i96velhEa
NXFnR/5Fy6m/mBPeL8Neqlu8xzfhJfFfKwqE19dvsOhmb9VHkKtA0arN8nDvN7UKRpTlTY/X3FAq
fmhMe60OEOWPp4ZapeM9uUXUOB+9dxg6gpYarJLIkVK5VUNRhkxyC9FwgtApzkvrx+XnsfRDkdyy
J8ljf+pfW3uA1+WnBzdZoih7Gnk4ko7ne61YWq4D+zqpPbZFYtU0ZpBAuwzkzsz36J/noLkuEmsI
z5S52y5bETrWGKC285v+r/yJmSggWh5krKVMQoOF+CYj6KLt1KUR0Ha+o9PfdZ/i8GEZr3/B3KFc
hbRXmggFW/RRCy+j/KfQwQoreprMVlCF0sGbqcYjmekflbRxZYFFSG4dUKEufftPlxQFLrJt+iol
HhVILRdowynlO7Wb/WJjZEpsP/cEyZjNwyBLHVA7ISqNllHfdAF53QJ22sxPG13rdxy+TVG9HTPL
PmdIHI/EOK/OF3bXxZ/PgW4cI4zXDpuHSATrtd4GrmVrDmYfGwiXnmH7FQOX0Wvj3kWxNmBZCXDz
oOemAHAxUSmxHlWN3AmSLGONNH2xAz1Ve/gPCatjuIFFRG72VrkTZ2LizS074Umab43urouc8VCP
kAucOdgxj4knRsAdt9sF95SlN+go0cwCFNFa8YOW0SylHDe4fQ3OZydDL+mBOjHQOnkwj+DEMjdz
7URkbFjN24LEL5g2CGpewMvlIz2Xf89bO7t6S4359QcNGK2mT3V12TqYnMTDAlHC4PZwSl5+qmG1
51OiNfRgCZGjXHdP78nskjL6H8RqnY0Ksu6fEZfetOg6yPoC1VsE8iMlxULL8CLfy90iNEWQVkG5
gfgIgvSyN9saJ2QAC5SxogD9iPTS268PXzJtlSODEJpf5VpnWvVjfowWZqFYoTLddwI7lFh4mgjp
emQerbqFFfQWTai8FAORSNeZFYja4o8/5SxVjdrTw1B3CT2QpparQDu7Y8ei/JbEkLCmVWqeby2N
subKLRUU8h3NmPkRUZ5DN+StYXxPwtuTQaYL6X4w8seOXyhfLE0vmJ3Guxl0GXsIzUEQgSaUv2VR
AKiUtL3vy6pbNKB1RokIfnvKpFqPrLLdK4+u45oCUMLoyNZ9BvIPe9v2HxruKbsRbvrnO/SwSLjZ
LGAPs3a3Mdl/4HTu62Fhf81e5V02l49EDtXpdcEUhWvvkSIcwsGpuAg2JdXxzPpezzAGMh4kXq7R
ftRvRkze0xnZqNoxyjsjZe8BmJn4pK4GbKI4kMxwAys0flA1/Mvi0HOMZJfrhsCHV+3aU5Al2ZaL
yKM1ChVtXJIY99LOgGdSBvOiLEcNYK/TEfLigX9Y7UaBrUyVAHCW5nN2CuxlfIsyPcKLenNJN6KX
xUrJ71LPDkgSFQGG1UWtom+JsmV0AxqiZ4ru3HPyHs4cSQFDXclPO394HGIoa4XO8rB7KrG1o3YG
AMy9DjVia7UtlMWbAKMSqcK0oR0zgcCIu+deEOtaxAwp8enSzCtpvgdA+WlRCPC23EQ5cR+KfJdO
AJXTJvjwKvR4R9AzkEUmjD4NFYk3ok4t62PSsB33rBN3od8ZqigbAKXfNRMdc0sO1dO0LujGhMZ2
XXU1XkVCBRkNMgM3zKmLuQGGZ8XKRURJXynjU4wJ8x48yK0+UQH5H+urCy4IR69pw1dXN+c7rS2s
C/Bs2zbkHieX/4Sy5l3wSAzOkL7GAvzLJVDQnUB+lscZgZDr++70hmiYGvvjpDup3O/iOj3zCdCm
anNK3N1SE37wiBHot6K7SmEUo7vGelNdnhbNBtyzUHBdMJ9gTFCt/OMLxlo0/NrAgQB4wUhpINgc
y9eG+uC1sw7KRhLDEvgSei2sjUGaqJCpUPXurXNRL8Q4zd0yz47BwZKso2lsNNkaJRc85ZiSL7YX
ebC1gOcJFmUQ/E56ohImnli1bAZ6QS9WVcpZEi/yJrOOBWmsoxQJDxZ1ZbmP1QaBQyedJi/0DSpD
wbt4arVEaVTmTt3WN8SzJbjBvfTp2ISUMaPtXIcbWh4bbVDHjzz4+lVf+hBIksQRvdNGa5mSP/pw
FsEY/AzfGWmTqaHw+py8om4Z5RketxIbZZkyC4v51vdVn0hrzz4iVgU1GY2Ao/DDmt0VsiOxEAGt
NZYl4GkNgMGfGBxqcZrDs4q9NpNwKVyhhuyViPhkW1x35815GxO46/2vAje3rGS3ibohX8bgqwKv
FbOcZbs2SvFt3Hn29LrmMkJmRpE9VWCR2btF6IZHWMk8dTg91Hm2lMT+uT7oGkNj2zjUYRXVehxZ
97/mXC2oVlFJ8zd6HWVBPhGbA15nMiR0ucIgU7ZimzO8Sz1WKasGy6py36vo3S606CttcjB5BZoC
sUkFGfEb4hP44LqDLNnHFo+tBrwu+NzV3JTgxqqyDRd6pq9HdM0wIGi/+yTD/+u8Em4sL27GLjBO
JeMcYCicB51ajmuTLH37OIV8eMcqT+gdK+4hpIazcX+ButLDCgkaMsj8x9Vk4ID4Ew96kekOSZA1
1I0PzNgohbO8tB43o7whatxMEHxnfRVX2ZMWJ8JOLaWjZWiQ+dqZemt96lcJ0ODSEDUXt3o+r7kE
N4OaEl1ZcArSOKgi/AZqrGCbI4T5FQyJ+Et0YkAUcz7W/SK+/r0faVuGzyCJdE/meYepG6IpkpwG
Kf5E1ZU1o9uJPOkdZgvXhHTtDuxzXLYzaKcy+KqmIoHKdosAM0qq0RQwlHbTE0MFwCrzxei9CGYq
6d0Z69lko4FdUtVok+x+4LfJ4Xkfjz33hLRSHP56MA/u5erZpEjCPaZUpbOL1wxqwol9jXySnmuX
jg8qUgk3uaTRBfz8Miv2nY6UZ+mUhZ98EugseAvPJfjMFspYBhRliq1db5VwAAztUs9+somnsk1l
VY1arNRsS8WD0OaXIq9FKXIwbdMOfcA+ntNxls8WiPCTHpTD0v5/0RTnVGNP02GB8QqJ3fTsqfl7
A2t5M1CNxnfcU6f1ATQyck0/ahtoSdBC7ikqvpckNzO7VmVOgL5k0MVb0XrWTCuhubIUBkSYWadG
dCT2AKe4KXr5uhaMd8P3IGTB4hep9oamgOBaitjWVRJmHkxUit5Mk5P56g/c64O3tH+P+0p+I3BD
cZC64Rwl2o0JwxDJyPND1P23+4jjhb7kwBNia5M0NaEyy2w3ctImTzWI/EhcsU++G5t+SoppSZJt
9noToFB+fULONxru76lAqJaOxEx0MGqjWCXOI25wezW8NhG9UT3D+ZffkisaczA52PYv6sLrgGq7
76ZmmSpYsroNe6+thapBX+BFM9W+Ha3HSJn54xFHE6KY6ra94Xl217EgkNsANOMWTwBATI5RhlPR
XbFQwFuSecv9eejqqyt3tvou+3poCtckm17d/B8bFI/US+kVQ35YVHUD5yjBfVjLmujWRiFsVLhi
0bYeZS1ClRjosyNymoYquDnwt7WKOGCmNzXuz2apynqxO1Ne7F5AduheXN8oYJeoUyFXvJ8XXbCU
0xLlEjBEMCpXKnxzCLLQ9ulad7U3uQXoeh8p1+efkaptEib9GahMACkX78oLkqi2mKXTCCGO0KpL
U4n3hct0Zp2lGD3jDjGflGAuAE+TbekpAbvYcyQXI+D+ECr+ZRgIBa4M8pc9XRFkNppJtapwbJTx
T8BNEiTaSnjpDFUswFuzdu6bai3HpQkKjqIeyP2EYHMW78PaW5W7qQkwalHybBvNVa5KoHTfTwtn
ATDIY3+/f0hWvtCINBad//fRn1t8tEK1twzviZwgRHmI1D+zEEka55PjYfGwyu3Tkeem7IqGhhjx
JfgREnWZjWAcoWiTcy3BNUWWe9429woXjePFGKtI/Zb5tztkniFJv0hggYz/+I/Z3G01XgSDBoth
jTZ5xqQdpH1kLtDATnV3kaDi9kvETxWamlU1UazjX5DpesNOeY+5DibiGrKHtTJnoXeGHQY+2LH9
0WeQi5MuICnKUin/kv9y3Qy1Hl5QehNcCJK/Y7kVTwNGbAfOv6r7mNtTSy2yTD49y3gvhnGsl883
v3kEBX/mrLObYx671zNkhlZ/6IdMPGORf1b9SDkMMruQgkObaMZi1adm71rGAd76InSBojQC70oS
wkqx0+jsz/Su/h7clqDri/zJYdeknUrvdXmceMYi9p+LX3zghSR0EaPZuuEw5WX7U+uBVfuI1S90
us+cuYD4RBDe43qnyatmDUihUGkLjlKOx7glFadK4PtHT6iGdm+cKE81b/d0CpUgUldPfKx2jOWM
ZgrQUeNDVGbSRJ/MZztJCDZvae2A4i98JIlhUPuooGibDPfAUl7/islyrsvfB5Cgsf/kLEakbsGE
xDVSfm3jPmzIofmP+S52AfKvUu7WjLnTMYNx660XvEUYCZEckFIdz9x8qMQZyMAdAzBzRGmTG7AQ
V3tc96aSzph1PfRhA4j+VKbM3LN1HPT3nV/JzHYRZU2IY1zSKu6KxrTpC3ji6R22hGObQPKdzeoR
2fw5grIungkLWEafiGunPRZzPXCKpIhnG9mPpbVyJZt3b5PYGGJ8ne1ShLYJwQIUvOQK0efKc/5K
k/GWDa8XJcIBnCnMSWEehVllKbQhAf7YApyFJDpDusMF8ceqzW7PaL4QkPD1CzKEOv5gCrGyK4kH
8PexYdxPeqDOpWaCVDHchqPA4ITzEcujte5ssSO9Kx9dvegvTS6TkspRO3XxMhaUQ3Pem9r7KDnP
OwVjzuM2H9Dk9JMyui1F/pqm3fbcc+deZvq9Qu6JlIKdaTG8u8dY2bC0dXF+QovVM3JrWbBRbjpQ
er2aLYPOyZFaRCdZhgpdtZkvCCS625zhWD2oiPkbh1pMWTCZHOSpsmO0wT7zR0hae7GfiBzYZ1lX
aBDhX3LZDz7eZQgcZhS7RImAGLNzpVOY3LaAvjNcjINFoIM2qj+qeAcxbV0cBjvB02P7OGdbKD7G
/bevAAOI2SYS3zWpmunAX3ByMpoYT+ViCZlfvTo7rwrpKifpeUOuuSyYXyYQr56ghmItQ1FqukTY
Pl4li7J17iXm7MEiLP9OjeCTI6spnm7ggBGT/g1CNV49lo2LtQjiTgoZEgV1+pKWa0Z3n5WUN7LY
5q8Zk5zq0wDPI3cSeNEnHKuZGqWxz/Oqkddm4cHWOgW2kuqEKEscgeor1a/yfE3GtYJx6DCk4Oa4
EoZPVZzPi21BD/l3aK7A2zP2VBwgfZXzo7+M5p/NG9DtAfhpjf3JsS3hu9+M1IuYvve8P/GoiMWL
A+4fu4NoMv+zsjDWiRBUidhAWfvVlp+/zMSfOHN2V82PBUOSJ9tXxCeOx8sB9DfX2y5IqzhLlgU8
jHjRz5j8mJMRSbbiJx8kD1VNu655RtKx+LD5zIKqF5OHtSaOXW/+YpVyHALSvaT74AGehkpw0DEd
qVZpxKOesk7sy/y1eu5tV67MJWT2QrDm8T+n1Z2VDxCTaSV36d0sA9XjOTZeM/Kgjj8HKKnntgfy
1S9VYgCHAFtp9w6cI9Gk4BCYAIEFwcgJ1MXfuJEsf7O6CGLDuU/M2Hag/KxbjNJp98rNbW51hN5M
oZims2/4uYhgQnpdXh1NeyWYCcC4S1fWx8McvubmHSKaTdHIVYCnOgUZKizkfjIsPlsDtxB5JnKy
fzUc+z95UITecMRtluds1IUESgdcoMi9TOtNPngEItIWSkJzdJ11aadghWSeBDVeTieq0u1L9Q3x
RPVqjd7p3luMB2wzyqBVhMYI4tGEV/isQCsHIAMFpb/oIlNKPY5vsGsVdsvVHed6wsiS+onXhzjY
TJNr3PX3f5b6w3WZSULq4I0WoHnF9JbidYBSeemSpRq5djV+93//gL+He3hZQFCuRwpkiBbDJAwO
UQ+eNxBMWCp8kiAoXLKCV+M/nQt5uiJnABGfQG+dqNNRf8Spr6iiYrky39Of3HkJ8R0PKzZ6qsQC
UlPc6gpn9P1jK52bzFJ6wxb1xzoyKmUvJykZfdupPpaBPZjHjEaLxzWGiVeWmal54ylW08YFfKsM
o5xgEicklC6a/Z7boGBofwvr2UvF6MhTcdrvjCaq5RrjSNPTgnIpDybhHrR7vmQuI/eY3bHiQhlm
mmJPKlXQzxxu+TMzTid6ezq7ZEc2WWxJawiZ7FWOCern2DaCXybjAJp1eQKdIC4SoZnnUm5YHwBR
iICp80WcGbCTGI6ZtXC6qX4yhnV//Mwk7MqB1DPpBKt2JjICqvFJybJ+t0/2YAzrZt7pAp2H84Hy
CvZVog9QknML5G8QG0UzTr25+FPBfgyxdaH6kWDLCbiIQZlZt2FBiZ5qV3EpRbAP+XQWLtO/3QUq
w83J6kLvTuM2B8stWImqS1q0AD+TRgyFE8iom92wruRYYtrX0qStcdFOYWVTfCOiHRKsCKUlqXcC
tvGtrDaRCel6kZRYCJpDnH+d7kkJRtiouExhRGdyMrLfI90eL9vCJ6j24HJE54mRyJKVGxUjsEj8
nN1Q7Sgc2UYddyfJjfHzp5hmZgy0UcYYI+948zwQ2q34tIGBZhKLSlC4CTk/PPyaQU894ws1LL81
QSoy1rCV2meneXs9tYMlsHq2X/TOXOg2fpw76gbCWEhhOp6DippVzCfc6kpIPkT/crxRKbj4DxT/
3Bi/NYHqDVCjJkRSzQkMRmxRMmxCZEbMjqT3soWXuVbVVBPdqGoZFLVN6fA/d8HVMKiG6nz0CLgY
9mGa02Ju1Tx8Z0ZEqq33LuVUaq09+lFrqCCXitegO1MeUCBkFTvL+a2LB2B7/wFZPY91C8zdmnuC
iE+WxqdIGr9/X/v+1G1fIWWtzTmq8fDd6Z33cV3BM3moTvq5VnGK+F1u4K/e23SR9cc5ddbx1Eyx
KxciXZS2nkkc13GDxiEOfO4b/BLukFUQEzIlUarTmj6fxtUZd/HIeiGoFIIxZwMbaOpuW4AehSU6
noFZ+aCamyhs1kjJT1lAHYiuePJA42mxA/oQ1bBJedhozpsXGmPxeuEzOaqjtm468jAIyb6iryhp
PfBO2pChzneq1aKeGPhFQpspveL4cgtGV3KQ0Ago2UdkKsSV7y5afbWZyF/MUHAYF78c1zk5i6N6
EX2yA3QcR5mxcPWfZZcLr/d5R+qp1SqxQevoebFdjJYA+XDwqQ7/qFp0NeIVAL4bePzfPiWDZtvh
AgAkK74AnFpKu3bKVyJfH3Vc4nzefHDQNW9d08PEyFau5SIVkhYgIoPT+cS9r5l9b1WvN8aE03BA
DD51UJMBxSvvGEWSJxcIG0/gySqnsJQpuSsO/Gak0TvVe2Lt4vUQxG/w8XHRM5zdA1E3VxX/zAvo
U0TiPzjeTtus7KI/VdhaVbuSetAFcaGmFPtl7azZJqzzP9rvEcdqWpRr+nwnzFBMm+0mAEHCDy9y
Jw19N2rQ+bfZtDPW+3FT8Kjj3UU7XscCU3b8xgmFb3Jl10kvWEAk4DeUQ7BwcTUyoXmsB4TBvH83
nbT4thi94Gmw8x+e3uzGU/AOkbpLzm2DU5ckhRjdyyeOqSTXtABpm3Zxu8Q0DFk1Nd/d0FIrw3SJ
HdAIuXOP7soXns3Bs9i5KHouH2g894agkPZOrP5NqmmoCfyuJjQnu99uLX/rIPfVZIIzz+lgxfjY
s6sybIYqmck9uCGUjYs5YiIjv5TkTSn13Xa+q1anNxPWUy9TUq3HTHgpabx6gFBovMgVPRAR+WF5
ywGUkC1aW6WresKGQTHhyNb7qukF28Hk5PDGPr2m0QP4Fbsel7CH5z1CditOKGRQjU3QaFeH1Dse
IjBvBFq/rq9VIaftLgY9/kd8SZ7v3EQBrblDd2ARq2SyGQbJ4kKCN2Dhsvg/abhZY9yidbzU4Qof
ZM2z/9iiw8Av4piySSMovyGCLo0TdtKBY+nZPbSIUYU66zG4dY5D088qxs6BUFHNSQyTxMYHndai
LHqSQ4yba6S550Q7hAalX7U4JCBPMZjUWXppQX755rwMyHIN1GBYg9DxJdIUJUA7pq665Y9vSlGX
HFvfRkw+hwCus99eDs6cgxBL6bHoAuS96lch6gRrXQcCnUAO2xW1FbLBddcXMtcvgAOTG6Pge0Hl
xzYRJsX2zc3u8g09zpnkK9Q+6xtRVnAvjAFiyt/r5PuzSk+C6yuuhLTY++AO7bjZ1sODT8UJcjM7
MjP+oFVnNF9p1NoX8//2WGufniOPJzuHOzhYGtpab1d9NZINwHjeFxCSqxkeeRhP1pdqLV7Q3i7v
mCKyN3JsllF91KRuJlS9IABXQpPb7eUaf+TYdKVrbms3OnKj7Ks1eO74spCIynLWBdKO1hlkNTM4
ksu7R3Q7zAFYeskJPNFy6Nh4ETo5sckOYTqLKdVy6DRGyrWKwmFcjbRHiCiXN7gDJ1MYYR6cqDDl
tZ5VXpQdHxKJl7ch5UQG9eBMCd77gSAfefmcwxe7qRnC8HqPkLQm8IltYkGQWK1n1BygOVWHyKnX
TsnWNSYWlSC9K1xgpJhdoLK0jDQhJMmrYkSWy/nTje8nXicrjIte3rOqVZVULzPGAQmbEJAv1AOO
Gp/bO8bS6RH4deJ1DcubfJFqOD1RqWAlnTiJ4u5il959lQ1IiNjMcmyG2d5pazU9Fft6FzZ9I6vY
hxxASknRloOlzHbxbn1RSd6ANvhfzr+VEuxUlq96PzsvCWttVbNeStH7YxqoAvGzFOeqRyysDRR0
Dmqe3+aGKquaY9fCQ9Old5g2BT7CB2nQxL3fBhDcZlf5pLSn+gM1cOcMfz7ezaPvh4aLSkgRHv2M
/c9HDNm3IHniAjulxFv7HnU+edCYFaxormrdYptLpdDmxssKbVfuJ6x0Sv/kK3+FecUnMj/FuGMo
69woVQkV4smY5XSib44M9TK+vDLLa7ziqgGlJ9JTeTQLWSEyZO8kKnxV1qD3jp9EDuN3u6XNmVdx
g3cG84pmaPf1qTwHMQ8R8fRD1+ezssB4DS+jp/uagboDNNEfJ3u8OF6kelx/iohSegBreuIvu/0d
QNknd0LOqw1TGiN7CdXxN3Z3AndHqJj4WJv9SQ9nPyzjYFw1regYgCEDMoHQHI3fJkMODfs1e9DA
JdFG14OocjEpPB+7jRq8KJDMx/nZR5WHSTtkDdakBtTYTjgCgUqVaUZ49NguHG3aVBD4tQ5JXNao
vaQ2MqMpYZZ6pUcRWf6cS9/L2W0AUlB3ZIDrfrHfquSjiPEFiR5806LoP8SO86qw+MzoNEX78Nk7
k5Ax36awtTxyGSHzmPTtFdayvDvjCPpMjAeZERUZHhGyYpENjsOf9DV3JDkkvFRM0AdqoyrdVO0S
hJZhuVq/3Wx+QLfrBdmz1k7MFUSRKPB2x6D1ZWLQ3XSsONJcJMTMuZ64opoHlFSZnWZv+yQLy/up
C7tgsbCGEVC9sInTyy6YIRuI4s+h1Kr/KJNKjr/lLX5NXqB0RQHbK1cOu5tQpOfXAuXH2Z7yix3U
l+/RmG0S6PCdhTRtsdA19Nzd46mIbFffn0FKsPH/whKxvFuOHlXiNqdBFYjC9o7pGR1o9iYdFHme
yv1hlwSBqtvSAA4Jjz2bPaLcLYN1u7c07qA/lwfqcxA06wn5hRmdjgB1K9sChCcPtcEg1bdggJeN
yb2vYt8p1afJjBUqGILzX2MMZYfWzeT0B0ShOEz2T1pDrYH/4HGNA4UhRDrzNa7QzctG3hmgG3tm
8b8awanFzZvQdTJsVMFS79BWMZOnOpQvvaTizzOZU75zPOlBFMmUuq1ilcS3Vv3KxRcn+qcXd5Cw
OUJrJDjAjIOqo75GwFHxdGEavqm7p/DWKXN+p3APrqu1Lk7IjEswt2y1ADZO7DRjS015TpDrnEPU
lJWDMsgUUrrlhirhge4CD0FIDAnmfqj6698/PvNU7WADGZmQqx8/zO3k1Duui3DnuCWzXh5Fu0Zk
boJYsJ2JWVIPHKDR1oz+97o5haACiagHvdPSE+6uvGew/KSb6pUeaUeGzOhGSO7p8R47oCn5tVmp
6PsUPRHfK2EeYoTocT1lak9mDJs2vp/JdmBrVQL84Ln0EaXRcQzUbEvSLISnwn+JsE2vuWmkOq0k
ygoPOaEowA/PjClKsQW8PtT8eZtuU4/YMtZJ/0m4L0ScdI+Io8+Jl+Xk1/8t1vI2R3l/2IKtZNxY
Most3hFen6DkmUFN1GqaAN1LUDhaXlJFFs2XhTgWyBYMRsHboN040+wQy4TyqQ47KZnqRmR+KSBj
RCVaLrNd79HSM7TBq5h0w8/xCSkFmVK4evAIKq0gU016JpVUaKiqsrqp9u/PtzPPq6XGq/RoSDpg
KpwOCt1M+Vi8n04AKWGfTWcBjVVZw4ddjKtqfkU9TSPZKMkkMFjV78HkE07zfhJKHSk4pSL7ajQ5
fecrRH0MQTJ1oLuW4MRCLTA8bFlGdoRRiPyjoTT4Ao1UmyEB24CEBp2M7B1UbuVZUe14PZwtlQPD
6DDMm5MM1NeVXMBD8g3I/+Ih/WhsdSUE0sWjQcD1VY2BOEH+h9f97OTxQYY3vRB64c+A4xzAATYG
HHMOrOV9pnLvDpiKUVLksm5HCw/Qd/AD86iMM+SWdn0ulfqWLWg8IPcz8uNx56m+a8pM2HOEm0FP
BfTwwF9VTSPGhUjjGALHTRz1BS6qiYy8AY8o9/PmTLrakzEQPhXUkLcx2nJih5fg1bffXbT0ZHYe
O+5zyab4vuq8OV4tMI95MhA3AW/njxbt9yFvYuVOJj1m6UWJaTwdA+qO1CGzGv0BovEDvaJWtDPu
A4uri9DFKF34+hlNu/gPslpWnRXs3oCrHWYKXIspAFU31KD5C/hhpcGgrPivWYoE/hfA0ffxJvyJ
uK8jlXUzIRCONIW15gpESfS0xYuNkk0qI+/bq0ZRzHVALTF6MUlyZpyfLLaSm7iGpFW96/GCK2gR
QObpAcP8grQauz/P/UsGhVyUXiRnuLFUGfL2rA9m1HQ+J1GWIm2GDZDeCChkk3UhqnCAenHR57fq
wbAyoq4N84DMEx2NreM8Z6qtSZZ7k9+E0QY54pwQWFAUEDV73DYa4jNe9tILWwg14l4Z68Krw49G
YsPbuTl32vIpwHT08XIy1or7iJsTAifIITXGAA6nhNPZRo989IUoxZqr/7OH5DzIJdhyPH7clgE8
mcQ3KTQCF6GhFafHM5kWWaKwOEumn2iIKwR/1Hcbkz9dOxU3e2orzc602fFf8m6zhQOFQuDdD9ZH
RUyTsUdAa0betb+EkQ1f4zq1TrDHI0VS+NIAHxbkpBPUVYmXBRcKJABY+g9szPKLS5BEku7uGc9S
u3WbsMcEyB/lo4IVG8nDVe2aTFoH9o7miHi/FaB8TMeSQnxymBmdNK5U+PqDbB7Z+xstpCgGG+fW
hovqWwT4OE/GRWmK31LUCCldFZVZvCHEmliJtHGUc0NtXUJCJhrA/Sf7Hjq2u8Q/AhuEMljvoWLK
8t4t0w4/Cr7vLvMiqu5ioX8TbkHxJuTB9/V8/witFzkC5NRoBbwvdlAf/gupEONHsHEOHVF9yPbZ
xgrCDHtO1izTpa+s5CfR4hPYdAqvXC719Oqy2rY4qQChKCfSmDI2L2zWVTOhegXx7l41IjUThivF
QP0sq7NFMKjm3rgnGGrFjmjiPi6Dl5vXwJOl8fvI+g17wjMPJbfN0CurzxxAC7kE5RmXBoomeUne
gWkBUyqFpEH75p4m3n4UsOmVG4V2a0Y0Cjc7gn4DDkA++137NhSAjeZKorZ7ejLsbNv5Rk84/SzQ
Y6vXmOL7NlcV0NOHMNxkqTjonMkKZ19Cl54sh0iGBcLsNI2LAriMI4xo+6YB10imi4Jc7G13+PLo
iD0Rld4YCKgZFWBzdPjPcVjEE5tTzUCxit7AH2GkeSHDoObaKxQTP6ySy/LKYRDhm1nnG/Lbc3Ed
65E4CVgD/0mWPHbXTzJWr/3I3f2+vho0/1UOkfAP0nrNoN69POv3D6ZFFXIBOS6SbSDKYygCctbz
36xHUY1vQGSeFnAA6C5q3v3ksf/7dOmgLNTWrkjeROGPM5lWL4JmfF5G838NdDgU+rZ4eZHPD2at
lawWuD3UA6ST0Fy7y2R/qmdY003Z0DVc65xK2PeFQ1VhMw3AbXXluMk4HqsdeZLRrgS3ik2tE9h4
LX8l6hpJoLzmaLir+Ewx7G+t1bbdrVmzYWhCIK5F6Zx+Lv9mgcBbrjmSzW+B197Cl9MXVqMujEBe
Xh3SZNDB5tkydcllQ7lnsM/UWoU7BmW/Jpgy7Z+/I+JZKK5IAfUQGN8J0lH6P02j2ATcCY2nqq7B
Yc6IxYoZTGQN+weyZj0khQmELNnzQOQi0Ssm1073NSeSEQIGkHYRp5kXfL6p8xGoPlKJUFVCTB7M
PFTdF5FeRZpNx+BVmv5ir8SIPCPfiI7u7/daMKpbSMHJUcw7LsSG7MIXo4HVsEWFpE00aWfgXM3N
rNAbpSCXINck7Y2j1K7jVaev087A9V79p/O/hbmtzZjpcHZ3YsefQub9hoUjbDiycWUJIUOD1b/h
lPhFd1obNzXilBi5mwoHR2nnzE2z5c9p6gesTsDHrukkP8FWXWN8k0z7pz9y6p1NdGWpOUyWqR0n
+p4Z6DMA4gW58NgKGa5HNnqenlJ1Wgn/ECTRERr/kKKwvQfxSVbl1djJaDPHzQwSSWqpkd2G/Bf/
vY3zS+mBel3dgWh7ys4uA/XwZ0ZS6yOjiRQu0FEYUwKO8lq/gF+8lZkvFev3zH0f+95J0OPKWZHO
+IKF6IiV6k87/77//QeteyB4KmD3xjxH6mKy+cO8AbPpClAOsrwtfSqlcNiPGmCZu5AO+jgPG2h3
FYaukgvve9dGaG9iHi579cpAU1Be+YJxwyX/+z1Det+KabJiPAZzbIhLvgN4M3Pt/+mDaIHYEqZN
pL8Btd6I96ZZSo/0LTr2Wq1dgmIzWiAYnHtTHheGAomVqkErqCad8nNB4tOULfC1LPIPP1Pdb97C
NU8fkLzVa/NMBsO5K0xYS5pU8k5WF90ALNP1qLeNycjg3DVTFNXh1aw5xbbTJhGjeDv3boWnxrJl
UOGOZddG8u4XhJfeHzxCk8Oodhe1uPeO4KitzApAEmp6pxedh6fjaTfpEqrL0Q8i1BEgK6uPsvkq
jEAcVkt293yZh/nDN6smlCCzCHKUXWxP0rAkPeLKVVXQD/8NZgojbOyu1NzseW+zo0tEbBW38+Dv
gmn0as1p6K6EJdATUkZPQ4kzbQRQyslSAbQdGP0J7VlpSHhz0wORUkKXmnxLbnY4IM893NvqWtbj
9wV67QebNq5j0zxZAYRC9q9VTbBPdM6c20wKugOaCqHWpVqqrldYX/j4Dk+gbjRUzTp3MqFzYfZ6
NgJ4jWLuVldfBVBe3QRgr5eTVVmoBND4BYbsa6ZXAeX3zDWqOQRtgzUQQzv/tJKUXvGXagc/X0w8
UVYm8dl0Gmt1R5IRgS9l8AsL3AGvMNkzsvXeTs5yhpn1DQGN2GUkfv1uXZLuxnp/d1jIVqYbwQCS
dNvQQww2bmmy4wJI+Kj+kIhj907RJ4/RoeBO/iIRJ4V+je+HAq50q8hWUdjKo+NlmmB/AeeA8rm0
ROVMgYeynCjiCQtUCE+bxW8mZqpLMrFGV5pfENueRwNyhteKOuCYgA8fO0Pc6rCoFocse3LoOKA3
ylKL/RWq/8PfxLa20ftPSJ3Sv1UhxlM6Zi6AL9hCH+fDzc70jOo+OgBORQ9VvmSVL+B6Bw/RFvup
leE4G3NCJXPqg85naDj6TP32KnFb3TBU8vvtI/LSU+A3M6FWwkAgvjkszAhZA4oMhfH6kQN5ewGE
nPzb0wxcABvm+puU+Ioce5CjP4kpNATsHUJnaYmRkwnxFraoxRDdn83Fbnp8s4J6gn26wEPO2NhY
Lk9smVYk5MpNw80sK0muLbNBOzQrVxRO2f/yI/ER8kfM9+EJ0Wa4O8tTQC0r2+iisygxonlNu0fK
5aMPcFaEC46w0c4V5k8EgDhHhvEnsmneAoMMsWSkl2Q9doQeipZY2gvyqmpfLFdnFswOPKhM7wq+
n3+G3jGJMsf9hEH/IfDdeTLZ1hZsxkd5w8LzB40oFSMXYhgM56KfSeXF5jk0qrhrPJ9E+Qgk16vs
B7NJE4DinejJe2Uzgb165QcKTIkzt+Q60Oqa6Qy7PBEpskmJBdLRvLdoJ/GfrOAVFaxruY1C6LxN
q5pw8E2mulUVwSifXaJxsUXoGaaSC/3nLiloDY00f9R6GTwOId9ARnmjRCACwrYqkCuG2XL2clSh
d/AV9L2lbsz/LO5JW22tU7whYpEuTVeU74Aa6RrCAVh/unLbu971GkwU36mpZdhdK8yTCAXGrdDQ
dptvAOTmHrDFRDR+mCtNUKxCDa7apfp1w9MPAln3Hslzd8hVeHm0AII36hknxGM8ukeQBr0xt9yp
FrcI0pxxDDOzSi/2h4GSUCTDXqaGcT0pcZuV5+RCGBChM8SaqagveheuMvCgnV6z0sg7WyGkhzYg
Yp6KKmYNFpmjCU0aSucf47fQ69WbaP5tdOb9bRelf2zeIP4+r+P3WwjUVSOnfOORdYm+GINfUFTJ
EtZY7Zj13RsyOxNudpUBc/527gzwM+3elXyT7ndhWviuAYFkDzeZaOu1pzPUE9lU4QSo664wz2BE
gsHeOHUBxT3gKbssU/tReBiyWLUZpjJF+KfNlUGpngDiAQ14IB/UkBFiZLG6ZBngRoDDjEWY5tbH
Y2Oo8pLIqSkY1lu516ZSq1vagwDMKduLMQrO4Zmhihy6wmN76CZBO/NEPT3+qDKnl/Y/p0dukHRB
gJHZIpmf1cIUMy18ySFOLmUwQr55C537JtDa1X9Mv7aA03fZs4p7T9Ia4U94Bl/UFsPy6CpLybQ+
eHr7ERnzRX9vrz3vpu1jjjf4hz8ce+rhgtDj3vWck5erZhVrT5GPVXqqzqj8WPdWqtFsAbvX8ly1
Agkxpj8OqjKcb7u41tggWmO0tDLINglrH2y6SpSlOtMVVysw8+mfC1tyE9IebT+7ffKIP2gSyPU+
0a9pG5bDjD7AkLhI3ZuN4un0Gf8evYhenPjBaJcR6asEERYw9gXG3WyXIy4G7XIyY/JY3nFAS8wH
E0M54ABuGdvYSuksC17jWU9Duz4dDMhGb9By4li8nn2MZoifkbQn/MeJhLfHrdgGcP9UYzOZLw6G
5H44MhP7+eP0QPfBJ/eS7jks+jTfJGq0942oSk1Uv1eA5gxZBqPBpGPZ3ang3QvKSeYVOH2TP59q
G0nsGUMeV8/Kwub9AwNcUuLtnt7rDyVPamUg/IjFDbOHQYcsRecgx71IK1ax6Lqs16yPmC+UXRgS
klhZAiqsqXwY6G33EpPYg6c85K+3w0wFbSK7KY4y+obe9VgCSc8lpnG++Jb286LP0KY3wJ5l/QsN
tUHe3J3JgvRdQaXi3cDDx9x6W1rasydGGhbS4S+JLWx432BMvauWrJiFk5dLfut7I6amjNkU2wFD
ep5QP868wcEeYKRfbDD8BfXIQypeVgeR7BX5+8goRm1DA3ew3ahTjf4iK7WMa4Zpq2cEJv+qi84g
xNI7IjpZU+N4/e//I5t15DlYtT+WEEozUuMNl8P8It0KZ+XsqrQbeT67ISrigSo2qiQEuwN2zjkj
w2usx4Ybr8VXwEpshF+cIo5B0k+wob+S0D+55aoAxKJptrwygpv42g2838czPOKVHY4JjIL03mHs
EzU2P8xUIx1u0u8MMUZrf127ZxKLogMuyoXqxevmzGrgR2w+gUKpktI7NT3cP/aFgk8g62TL1x6g
hspWSduoyofqjsRkXLrG+yAYJXOh278huvdXztkMKBR9fbRDOWbArkW5UnnZb8+tHltKocsms0Kh
H2+W13QMw8Vi5kcQ0BY0crUbq2BwWg8WF4uRgkt+5hsgJRpMLd/B4wIoRgKmKt+ati+nH6FbGSNw
6VyI/XMES4aXyvnUW/BjmtaGqjV9dyYyzM1QqvoL4mWem6GWd42Twcl1jnzFuDWyn5GBvVTFBUBi
7YCpw2kKO2CHqQ7BMnG7V3z68MPWye2FO3kUS51lv3tUTQ3sRVhonLZfGOUMuQc+3DZqBf57pqVM
oQ/Y4YyRZ54HzFo6T5OS27z3GYdu/Wbk/vIphnSvm8X8QglWVauQRRihnkTAhfAW+5tMe7Ngp/Pc
CkIfQpgtXutLg5NiaHGCsWPvrExgd1Yq7anJ8TDWiqP3fFWMF/ys1S93pHW1AaLwVqp6vURSZU8a
VsDvpAZ/dZq+nSXay1aGN4/2Jg9ezzeMuQn3yGJxGgKdTUcxYjrYp6YkK/VTO015m33Eh0czjVnW
9OrwoQpqtxJp/NrQ/ip+OJ+Szad6XNeMvqc5LBqjdDQXlSQ0xo7cHRFaSAMm02cM47edSlrR1gIJ
othV+70jhKbUm4TSdv+mTbmpuSI8/XUlshpQEzWcVTS/k8/mEAGCXJaUVmRj4QW7IaKcq+a5gu24
D5QnbZgDPdhpSj6BdBfm4+LY7MRuwZhuhXejcbIToECaoNG1LU4j/KyD957NhivnE4Uf4jzvySAa
rHRVqf+TEgWiLJ62NBqXfceZAupw1aG7cqHp0WFL9p63hqyXSmGFHN2duK2jicoPe/aMLfTHazNw
d8FO2KZ8+Fr0CLe6rmklqDHmETFF5KckHbNdpRSDBYcPPpGRHahW35Bo7p/mUEQtd3uzCPQpCa+m
bb4/q52V2JOubdnWuF12/Gk9ofuGTE4rR/bNKw2XJOTPWJvSMt+GR0Qn6UHLnp7eljwCigOZ2SPP
7t6tKt9Uy6xrUFYDDItKxjBtg4EZHkhYCWCZO8oDbX6ZPNbBiH4sC2LqG5DNkSeO9W3Q/KmH28o8
TVSsx/1W4KZ10RhTVN6DQCQUO7rFWflPqHy6rWFpOmM9RDbNCOmLuE8t7wMNUag0KrskAAFkaVol
O80WG30NhWh5WBl4eUZJmE4xflG4pBk4X7ACx7urVS55sljQmtlfwAibTKIBRknBPEkU4aGx6JMX
on9KVrs6EeH4S8ebD7NsfDRPLfEg76Lt9HIz3PpaVbkfXFxcIgq2JgqYtWYCdUVNm0E1s37s9Vxg
edGSXCeIVJFNl1vNrTBumdXpQWu2Ku2YY3/gMuAi5wzPEEPpGjDI4Ht7ya/xufSt3dsBUTcUyaim
tNhSe0MOuYw9gdcqHZun8j22YqCe1RIj1k4dI4AUJA2j1oKa1ddXN+mPKEbO8OyCq0Of+J74Wuaz
38Qf8QgGHsoZ94p37FsIk6kJVevL4O5XKQ/CqDA8ItIZgIyZM2CHAnE93S/0nmIFeBSGrd+ddvzX
SF4YTon689Z13jTt/v1ejSk2bnLa1VGuMDBMPKk/FZcUtMi+wJvuvASSHMXOZ/YMbzsblRTsYhqp
msAdU4OH8SuE4CArxgIM9+W29kQ/IK7Y/PhL0XtP1SNM0HmqUHevXseUlHSYf/hxQ/iqx5onPwpD
8sWD4K/Icq/I+/TComcKnYEnrFzAANiqBtymvP0v+rrWbsC8NTIYEdu0AIHGpqZ8BjFjaIOV8/sk
eKx3Dh/dBo7BVZMbmwj/e4K7s6XJAWwricscnfKpi9598A+YMIFJBpVrnYebNyLZqbHBEeBNhxCx
1AfmSmD7a3ZeEDofxAIffZkrIjNzrJjQXwYJoZc5fZtu42ZhVzX2FFhK/T02+LQgy99A9cEquZao
M9yBG9UyoC8z2u5VsbpQcKYM+GAbxjAR3eNO3MXz8yalsdkGbCdkWuK0ceOtYYkh1CQjwSh13p6n
WfHYsDWb/VlJjGoNfM+1+wDzn34LjLjuVciRi3/AAuLVae53WRxE6H3Exh6kKrOeteQIzOrc9SfC
2z3pMCrBzH3sYtteeq/nsLlnRFKOBSramB+PBxtO5MiMA8okgTrB3VkTxbdOeyorKZfWKdR7u6uA
LxDG2+uZkR7b/oNfzE26t1cmG94etkXcHHr9VFWSoMBqyDPAS0GpnWq1XRMy/DoKOSs+IuPp8Pao
vZAkv2y5BNnV2Uv+kegrxquDTxy4SIwUkDYy2dkRUPNpaUsFuAMT6Z0BvikX6i4WW5cpA28i4Mjl
L2nItghR5bl4zE1hCCdBYMZ7RmoY+XCFpN0ZbYsfnAUzIRAQw1R5rXRmy+xJ0iQdY8uWfO1+nsNC
BCmjW+q3tJd+fsrCxaiBcRO/7Y/cut9r8bEKvlPTlPaIMhF9VjonzYgeSQtLdGdxBTLlOS4YgRQG
WED4SRbymWASLVf24H/VExVeChqhKm2jRCqTZ5r0V+SWXwH1Yw3zXeQZ30pGaE2LydLNNjvQpkqG
s8g4/8/T0cPE/yleqTIdQ1eCrb2xu8FfGUPsUEFgVBt65FqUZHKADCtBWvuKSFHn36suad3j8zdg
3Ywos7q+tNBdwgJ/5xdymekcwmCqx7CUWR0VLdorztQKjKkqhnN9uRIcklQIQPt8jfzL5FyVXA/z
wcokpqBACaJY1uaTsejhnwAgpXBAun0LCSTdq5ydpnXzdY27UHs7c2b8pr5mj6zzz6ymp9o5gZ8B
NBhD/AqA/DrQZWVtNBi8VKhknubIkPXU0kqfe3RoamfSLlroRUFONvefbZvIqSQxCiHwY1RNSGdu
cKx+bKxIC7AzeO7M3mxKBfKI/o+Y0/q7Oud31zqhva5vBS1t9UhO97k4+4oQ/kU155apxWzUGgL2
zzEB+mDjeMGfvzl5uSXINKNnbWO5TSa+ZOGRXoxWXWu53fWTu2ldl7hqrK6p9pkf2qsaPYfxZhrY
p0H0PsmEqIP8VQeGveq4N/19uWM5kDrwna777ELREhS2onJeFceSXNfU+Cc98as51Rq9o75hgB+o
qioVVOGDlexVa2Btfd7+aYa0yrDURcZ0u8371af5r3wckXt6gyq1PPrZSLr/tI4Dws/M/z31NwW6
jR9xeJuAFwCUTORwe9S1KrJRBUDCKzqdlAB0lq04X4PEshJcCBhSNDgI+DJ49jHms1ANDGE5XS6i
nBsRiADSpVjB32GE9zI07Nr4Bls+f+A2tEMhA9BxewKZNN+9fYx3zkhzP48zmXvZmHZTHtFDdMSJ
QPWLUKUPaJbpdLO9c9FXjAC5Ir82vQiK4I0ceNYQT/B8IpPOCpnPvhJFr8RLIlCemDjBJCf2ngtf
Gx7zV2NGLJmMPy6IWMr9afhGjBOH4Kt77nUtooKbiSEmXhcdgFkXDK2rbj/Y+U8WFAgag+CH6MgP
nV6Qiq83gqJCilRZFdo2TVx885PX2TCRQReaIB8Awpmc6ChJbZvVfSQz9t8tsKmM93R5+9jJ+bl4
JTuP4jO3y1Bq53D3OenxgRPd84BvqUF+mPwXKC0/2kvmzQBdKGuiTD27lxOcT93zpb5+P7fVJBRv
R1k9kMr+H8/8Rn9XfIPecsiD/ZvVzH5Ypf86iBEq3iee86weB4qhqAuRTVJKiqn/r+UfKtjjClJ4
eMWTSAT14XSEaXqD98UbuVi2AYd2HG2q5j4up79tAuPlPJfqDQobPnERS5rQBKQRMWiYa3GYap7V
Ih4ChoqdrkKmHV8ZKpvvzDdSMichDCcMijfMaAHzModUC6Fb8vFxfjvQgvOhGg0p5lxBnMKZb3cp
SFejLfxysovRIaLvQIGHV/x/b0mXhMiTgbBIfiSfEJui7jETwdNnEjdDlO/DVrMymW+S3gPwOenf
mWkWjqD4vGdHQzhp2QxRLs9KvfZHvuKegxeZ4kDOKGh65oEh1IhxiWqs3mOBpsPbSOnGNt8QDTLL
idfuIvGG4pi4ZwefYxtqU9RvNYP/txDXEwzEzNj/3eehQp6m0J47SaZfNk/mJxVGwDxUYDaXhlqh
kkquGygRNscG1PovqJNrqxAByO2HxmUo4bGdoCOkhaaFfMd9nidArtc4yHBOWFBbynhCLhhq0ha0
wP2w9FJ5LFynwf4USajL5ZpCHi17uIO6Vx6BbO6GvhP7SFSgK6/TgBqXN07ZCxCXE9f+9ozLg/lz
RsLkMrUNc25v8weIp9FxbaUS0SrncOMtUobCGUkQFwm/4+iGWisRbvdRhIxWq08YGUJvqjWRPM1S
wIuK9fyDk6cvsL3u+aCdAXJiyxUNtrRzT33gbhjSGu+PXOXSYFUHiYTtYGzgUVIvz4zHtIAjsUeV
a/EWtGSyHYlMMFTQkHZqqLqHY1iToZDjcppOa8Ixb59W/nlNkj0BH5uyo6LSF4tb/4HFdcucjHOa
/O75Y6zxkLEFCp7VHq7lF6hmq8IeOybuw5rkZOuXb2zJyuP9wZIqNVR5Rr5kRjV4TRdfrIgs6F2H
YclXayFjDZp/qlmh/JP5j8plX3xIS36gnbmCo8kwvdm8RJ+UdhQEnmkWZBZT1Jk4x/C3bkoLRrSP
muiP/wahNObJcvm2p6Sw3yfpjguvATg6PNflIGQb92+5gi2Z/8NkDWSa4X2Y405A/zXJdsOqsm//
RltIhV3ohxRznybSfEQsGfVnFpYP+OkN2lqb3ZpVJCq55l6tBrd7Cl4+GMASF1istJ8PsNrCO+ZP
9ILiwfp7nn57a1tsNFDMdg0K+2RPd0/6M7cVkQ6mcLMAEm9piFSpM4ozJHawpoQi2ZnvT/H/a1L8
bhC6xDv7Ex0F2tYLL6HJzfGZS9f9bG/FCHLihNkxy+T9Is/bEs6CxB58q7Yvw38hlorEMOQYL9s6
ReWs6U1J3zrGOiW72pyCBXbIB0jnCzceakc+65R5/WO7pVmLoblR15/JZqNuE98RVxprypE/aVXI
9Dm24jAvavIyqQo3oI8t3BVx9UqoIcv7BwanTanwTm4PFivEZ2gErOOobeiKApwxWSQLbMp+TAHB
++Kk4LmcGU3q+TgtUffJ4B5RwDiwVjLYanIABfkLH4Ku7XAqGgthhfNCz2TQnENNIwxCzSrmLO2e
WVWyQhfJyP7gLAXbtzmQx782nbxA101b7HM1G2Z534vdhfLWGbfVek24wGZwZ9bknkGXeB4eqr14
IqpPCHWe6ZEp9EP5pil+zXwj4x9QsorOSOCBANd0h7i5W/nJpAQRBGT7sgcB9mHjPt0fqQUnIWQU
JFrGgR75BErCNZn/d6sT7e+j7a9pSYQvC+J9rk51ms0eORj3xHgXhh9xV8qwMC5Bie/opQArAWLC
e9DMVO/wgRCUqAenlmNXTOrUEA36sk170lCq2HM3Een38KS7VDOTVbBL4J2VUUJfqMt9Sght6lr+
0NR6a8eesbcv3zb6FmD0x27iO9S6PImaamel4xnO3ocTemRE3T5osxUt7rl+qKw/WMMbIj33UtZ8
pIYYcUcpQ0VAMt3po5bhJjv1cvJrm43hJAJEENHPlezW96ZSJGZb1d18xllu/MUQ12I0+dtPl6m0
DmFypwg9RuImv22CifmFEiDQKuUg3eI3f3IcfJ7Dk6f2qZ0LwU+bLy3vPA+nA21ORRsV0rhKNrvv
L2up3YwsHeM2mJ4hU4fIdMcnQBdj6U7qgUYDy6SBTKA5bWSzL8E/5fug+rCJ5ypW5o65qEffxklB
aHOTRZY1WUm+YiahUCi1PmcU9egp98r21fx1bvJdcBOf+t/uNZ6iEjdp9gcCCHg5nDPwtAehMHEk
sjjq88aijDZs/1eJaF84YMGRyLW/GRlo1mFTkuTHWjbI+UkD/XAdyy/XoygmGwYMhNX/9QXRqKvv
yM28CaaZ+m13A/5vBOm7qA7KAxI8Fx3sJIZVtW3lyLG5cyzQ7F91Hij+QfouuNkqIGMH8XGHG0ll
wMuz05EjQeUbmJVRI1/WHuzyw81hDiwIFAlXSUE34m0dywKclWlhocFc1wRCQxr2H8ZIr1/jTwCK
f5jRgiD96HIXOSQC0jO32YTeSOV5hg2xUh8M0DSlXFDfaDkPtjeHkj1uyHPivc5C6mtu7jqcZGj7
WGxUtI7edSgUNngeeLTj/jxrZjo9BFvgWaoPUeI0bvPTDj5q3L8H2VdeDDf/jpaX99GGii62vqBa
9p8F8QmaMHwBP9Qz2VpkpuEP18J5WfL57Fu4UbJ7mtcxudkzCLpytn9mi8NqP6zD+5uTsHe3dLPo
0HnK9PjD978CtL96dJmm1xhxeKwBfKY9NLU/7lRUrLCZWKLwkk7eMn1Do19Q5g3cuLInoPNQdpbM
F1rRhbrmU5QWDCbGK1zmCbUBtjvmj78MnHTtpQeoAIHMdrg+FAwgAAUa6RP8IExtvkcLz3HaD4gr
M1eL1DX9d4YQpyg5Db4lKfb9nJznT142+DsJrV/G6y+PuEp+ckLj/K9ffJAL5oNKbtQ0T1s2fiEl
cc8tTGFo0bOwsn7MPI844vE7mbRzFzV2UZGbVy3WTodl6Xx9te5Wx3CNqWYEOfIsFaqg+mT0Bf1T
5rw8MpIIB80eCPXjg1Jo8/NZ17p9kfAfUXspnNqg2ex7CS0vfKk1/5Iq7uuniZaOc75sCZ4GGn1W
c8FwyuvmRCFNe2XV+t/0W8xiRtkCH4OWCBvnbu4hftf9RVSomKssaO8+/uRXd6JbJ3P993QSKzy5
AtLbn/Tuvlun3lzTmBw9cCB+PvS0KPyhFiKw7XOaM7NCsD5pXecuDwyWQGHcJ6hqS90Vi2YZ1qu+
Zwlj1W3tU3kplKfWspK+zjm3v7vx71x72lH2F0l9lfimtmZ1hjWlcxrEtE7g8d6MNIYdU2ZZkDU0
xW1sds623gds/PRc9dIDSlRwgIVHBUEAXOf53oM966/b9opgG7Xra2P/j7aUcOa7YVsHqfB49V6E
ar1bb9e0Q5h/ERSdb0TZ90t1WXdXMGIE6rqCtgXK9sA9uj+uTB9bivzM/WEzSFUuDHGCTo5bx4s5
lapiBRVTRu3zGEF2Vg5jrdgqWY+Bmqwn5+RE24YqcNSTF0g1s7j5eLJrJppU5fU2xYps9GSLCxcC
zxn0sbR/TNbEHhHvYu6Uxpl/iCHiLY27po3LEFfEkrxyYH3r4m+KxURnI850l5wRyOeor62TMkKL
w/JOt8O6/quRiWBR7fRogYf7+wi+qYD8WxhEUTzY5wz2bUxKzDPfzLTb/otiE8Ll7oraYeaod5LF
lPr2Kz0WyXN6HEdQZoHKrLILfQRg5usLW4vas6GwIRtc0GDzouxig4BR8ePPOtx1VdwzYyzVe0ky
0BJquz2w8R7+HHjZDoLNgc6ahoQ3YW7ISWCALIJcX/dIb90ILtfrnmNKajbNYZftQt9IBSUt1aIh
6Rvce32eKG8ysLPizRFfljFk8EvAMfzef0JteAlH6WWt5lWsh24X9XPKj//WxLeCcLK3DgJahEp5
guX9UGk9zBBfJhVdJa1Xe1WCVv42hv/+vaP5fS+wcG4Z8vGi/9ruMOpBbRptGiw14P5CPOjyM9NU
LrnyU7UeR/NQ12Seq2h+d39ZFDSKmiRbW9X4CSsKpdVEHoP7DhsuDxTB/wJ9wkk16oTwmoSIUlm8
TVhScQB1B35uBGXDbOdi9lL7HgboDUUP/38XWu9LPPEITYeGeK6NwnCE5jG6O1s3T4DV7GB0WQvm
x08KTezYSrrXrB1Gum8uGWC9EEiEp6RlWF7n1TSgwCkqvrPx0PCDECU3n7eMNRuojU0plPKQJPoE
3887hRixiGjUOXqE06RRXSwZ8oAAeaaJEuugJrHMCEybg39yCThlOqjzJ96XSeLnhpIl7NWFjEw5
80gBj/5CbzN0Rju/HavAvM4WBRAlGsf2Ggqhdd3ftg1xB3yDrzhw6sfiU+6ApDmKCp/i9aj+ZlW4
06qOxt+4AcaukwZrewZHe+40B9qTcTwTNea87zuITkudo6Q9/VVNuqD4gZ0TQGln2slFxyKsQlBw
j47dSMn09MYaQ1uO6ibmB6ch2vWGOurP9jzVN2rjhnIiJIVVecC6hZ0FFfMLIHQhUMWSnBWnUlyZ
FT7Xra5Yfo1m62XQJ26mabITCGTHbboIZZm2AozrI8rtf3PYT6fZPV/q63Fs42U0RbzvLlVu+nwz
9ixcFBD9kqcfNKpy+9gabS/rEUJ6NNi4s5KXioBi17WijGugMOi+lGSXy+w0TwFTF/BacKksuNPw
f2qCKnQA4w3xkGyvUszZSWvEfv00FapUuOJToUgMAOlp+jd1CNMS4wKy0nSLDfmwODjJ5CsWiHbN
sdy+GxSA+rQqrDtv0M+oyKL691XKkyXF8A2AwPKpN91s2AeWpdL0Kl8kxR57IE+uQzgFAR5444ML
QnIgjC+AYQq0T3qu0Z+xtxaYafLwNBQo7BnaEZHCQXwX/KRIwoNmfFhz/v2T5bgKJGp+hJzhPGW+
/DIOeRFykv9LC0gA+OR2PRL5a+nYXitn2f476c8xgADfht/bYrkOola/XiVbHxe+3EYM0dXbep3r
EZRxO6qRUthevOJM+L/qsp4vCvF/1HeNFzM0A/qhSuYZ3z9OwM31u2PYEEVaTB+eo5xvnVhdNWkH
nYZUxROjwROfdsNdvHwrJ7vaJiiep4ppIfyIp63uhCSuBJAuTPISC/U8YAeBWNjXTZ25nSLdgQIz
RA3wM3Fo2yXQH2JGaZxYTP3ZLXCp5TAofWR+kKF0kBJdbehfBAHiaUNYJKeTJEICA1zXcA+jxdrF
EwqoDzpaJ3vNJItkkB1tg3zipIyovZnhY1oCJ5p5ku4Ijtdi8UoU+IwwFyLSawwQ+84l2gZGWfx7
V4W/v86oMwcQGoqozy1v/X5MlPna+YhIAMwiSXMSj29qeDpp9df/pJjJ9tt2Q97H1BsNrl2/RL3y
7U8v3NQp1zhP/sKl5jJJBuaiasilY2PeUmI4ld0uqetJfTQn7xP9GR+ViF/b5cQisg6MSgn7rawC
pRN0ok/MFUgUoCNilSHKsYCg61VlMk5VD/ljFB2iRegxmAWWBBcS4XAhFn3JusQbWG9GbiADDIzK
xzNS3m95tiGVY6C187E6tLr/jiL7qPqquyUU1ICJfNeHl4hmxAYxbXfVgU0XR/Wvi5qAaaY6WqMH
sCKPZDlRZDNFVftR54elCco98+JpfHHagENe3cukPiAt2j0qFU8zIY/pzt45zQYwZTrxENcEDgqH
0lWUTciXrMfLW+tBx+UTu5eZAgJPmzZ4hGUlqLM6g9LsXNe/WBeWK0ZDPIbAG4xVlwyZIJrcWVJn
irCIallFU4gPMzWd6zmTRlrKTRfO+tnXnV16Hr+aVSzI7SHaZWYG1P4K4KZsE9LEg8sD82k8S5Fz
4PYXh8oD6Dx2L3F6/7KDoThx3CqRGXdPdWFuAZPUVElFgyDMpSpGAKiQ2Y64OBtWF89akqU1i+38
Yp8hcKF73Y6kI9X+lP2ySfiI99F+JmMUMTg8IfimGj4ChvmKnQyscNE9imVsph/EFVLM9bvICgJT
GRwHVR7+7Ph06FsbbvZ0oIeg4m3dbsDMnM8Eb3hvhuHD9TVQajjDFIrlZY8SHe62JsVu3LBux8e3
xHdN0zZR/EJI3jv/4lUJmdEzY11AfBrHMMA6KvBgOBk1TntNVH6KS2RqgfjXsluJdP/thpgkt0a7
8mspI/IW1sKsGdiXPaWxuit0B5QlyB0+bEjW5RlyehZavD3ToyGoFNWJefbUk2UbDNLBsbMvG2+K
yFhmAa7PqLOqanOabahNj+6CvFhOPZgivb7j0r+ElBpO5FGVAmibMr/Ad51fkQoeBmFD8XxnKNt9
pdbJLgVVMu0c2h9Ho7zgKOb+yA7b0+tox0gqvm0jkKnzv66O4KjzSPBhg1bIUgTU7eV5VmfM6wgF
qbXS97L0M0bgd1raQjf/bmc/N/zZK89FJncNAhUFhqmHoFpe5XbrKhez35Rlf31pDa4BRc0X00Xs
yzFF0hVKNvMYB2kudtQ8ZO6U3VrUdg4gqcUxTbPvOAavW0mlRxJ/0kqUH3YUL9Qngt4CeUzz1GxX
pafDvUTZHT9qNCqMyWpbkxspSiWL2thY8xSRo1cgZNCWU6Nc5M1hlpaYJVDGA/r4PrLmBRzbjNK9
iQJTD1GmELOeFKp5GQsB3FKHZID7yLB26w0N5JQHr2eXEuHEV9p3qb9dL3Tinr9SjwNJ10rMh8vi
OHb9Wd6wqX610KyJHf/RqusDZ4qt9WZ6iORNjwdbwyPZF9q+T19frMA1/k+vwV5zDc3JmTJdocQb
AXhG7bONUVGJ7ZcwUgIgdSOwF/wjCPJC+FHaxP0woN6JZHMCDzQfm+sC563lh4LCeK20TrCr0on5
0Bw4pnRJP+fiStK9dqBGUGxaWtZRILdqg4tyHRA3eA8c6fOJ2MrWWF85RKlJYJTyZOE77JdDGynu
K6avRNfZqjKXNgF2Nx40fcPF2YTxz9NU6ONKldPdCsAYMM1VsC6c33I5Ew0Kv2JY1f6tHXoGUvu0
23oB6MG19/Bl58luYTnKQVyYGjnJ97X2W+KXKitCldjRjPCncHJSRywAyrAEpIWP8QmX+zFU049+
dlaTS7Y62eUl7Pc56xO7XUUQWb8Qz8y8FrApTbyvp0aS9ztmvbHPQf0EcHJYDDIaqFOv1wXDjGQZ
6Ipf5vZxCmEAwoaGDT3k3gl9vCTWocE/eFTrcXA+ZI6h/u+GlpzrwvqkuqjBkWQf5QtUk/zCiO93
AkYe9mN53lE3b0f35OjaT3Q3B/ECct/N9bomJ+VdNyWof4JQf00YwMJT5Z5q6H9/klyFNYOVcPaa
be+eTxYdMVKi3jkZH+gSntwvyLZiMlRDFVAjRjHJonNT4Z037ahkRwa8eIQFAK8A6GMQTrCMgyYI
T+4R0UTXSCV41J9LhrpRinBvNKSxLCI7Ss2OV1r6j2DwkkJJhxUfAHmJF4qGhqSq4SwwRgErukP9
edQeTZyLexIfPAvNFW5c6EubfCzxtKifMzLJ+8v1DQkBpdwWyNd9ZQ5aVKX2i3ZaLa0Bz/xBQL3u
i7r00e4Z0m3TtedYLDZ4OxZ/jFioiMdaTIpFpePRZB4WNx62XuKSjnOZ4Pt7j7DVR2auCDZVcGxU
1QXSQb7JrlXYtH6pN/7gsQCcDa3GdXkzvoi0kv7xUsJUq9cGAouj+hxqVI8YQclpHfNn2/678lf1
MYzt05Pf/P7JkoB+SjxaA6B8Ode0FXtM6wWprmR8hdeyhNUfm8d0nlDxdgZQB3t6x+F5BOWZfx2e
7sRjGFSBBKV6/0WKOKMnGksE+9v6LHG+m/padTbTFgaFddC3zjzQD77OqEo2XzAQCkwD0MrcyJQW
oQMYWrmG5V9SrGsg+kUvLJMFKZg4v97XuNA+icFEJHDNFXNnu38IKEdkia3/++r/vC+qK8NsdIpU
cYYCpLL8pk+k/LGEtoOn15lHKgN9x2UT+scGZLciaD33YeG97oX8ThdFhW1tFDj5hy1JOeE6Sbis
ZpOpbtenRQtxM+d6sfpO5e46NIfx1QJhPsNi0pya1pMBkTKAXKls+jH9PGS9FBa9/Ci+RLpxhOSY
gHXnQemuj/O1gUKb5rY6EtXr1SRgP9+PRIv9rB/APZFPZZnh7pEJhL21D0/SUnRiHGIJ5BN1yR4h
6jykKovG5NeoZj41JXlp2ZHujYgIW7gToQ9l+Mu9LI2LFoKufz50Flp/NYadIrsW5kCuLGBuECFc
iY8zlMxnmTCLpY0zt4q4wGZvPB8PYgeiJcmdhi/Xj1pb6u36//e/dsbsVvIx3OnrRuODqcuIMRps
wDWZIM89WJVHzSt+oETYJfLm1wGtmvwbiMVYYCRRBGssR7z8YHpbbCQWMAZHP35oRWyO1Ab7KGVb
i43Xg27yzZVWNl/wDFv7roeEWWKjo7U1+QnXDRwhn9lWh+5DtPNLAiUdwqCHv0W2aWYBJO+84Hgh
Dx8DoMSvwkIvDU5y23YecpoEVy+Kln2ud54qWwgRGX+EmmjB/y4k246ahqqViZi723EJM46wj1zD
3X9qZxfs+8Vvw1yQ59DmPa4+dXKDt3gVy10Qu2FoA/R8YaAFE74zQSkm4x03Wi0Cz91/W7fz6z/x
aTfL/XGfxwKWwbwE3ljcCRw3ZkC8B0zI3xXOx6JVSSfoJWGxBv20r6UDWWFChmaofybaVDVEKNeg
7J+xAHad3YKTEMXeyBFyQoC9WuI6vB6q6PFrj6RTLd8v9HoBvPpfQnFOBWAEQEMC++BH1Xugy2dT
6gdo2YSzS7bLe2qKipUMYFGBgKmOSEzE37DbHsdKQOUhoMR050Af9tiWfq64i9KOVcWrFgbPJ34l
OU38SoVBCX6rN3thlvr7Cxm9+YvXXuLA6B1uii45hBp7/88q2NT48eScuXmmw80jf6uqZU0MWZtB
MUYvhTYL8ILVrglFSAphVW6ZhsnsCBP22/y8VieabbHlj9jB5gZnPk3gZdVyvk+42ePTtfcrkAeU
nB77NvxyR00A/D7EfYfV0rzT6l65S54ZURDjRoqEQ0RyfoDpSF/Asvg2KJRF12OA9QgwuDPH7das
oJKBR7HrVT/3xsxJTXf3477p4l9rSX/Qq/A0AZy819lLJ90Wms3nlhLAYvHfAcTq2cCPAXMRb7Z+
vydD1v5Io054L+9zJvUjAUwfGWTzN0QB9jZM25k2qT+v0NAnaOcL00QAYv6pWqpWPFdPASl54iM3
xQoALDeUrL6JUzxLOsgLJBHYIiALum/yZUjGenGeUfDq0Vmk4rrKyHpQp7hdMl4UE6t3Cas72O+9
AjTfpQwKWCBHuVNI4oe2EfWwMSeQ449K/GhpzcpXpD8zxXOfvV98RXymF6tnv1Efre+uxdvP0kuB
hhZ2D84ytUS2pflvc8v9WX/X1psfzJn66PTaFiu0mCHiYGFVgPF0qeHhDK5F+cDNSh6u89iJIPOf
MVj1duQdqXR0DH2aI7y5aRE1CEKbxk28OWRMrk4KAfR4Ze7uxg3cple3eGfH8fWuu651YlOLMAAd
m80BHSEriyPPIuCXLDHRMqXTCCyBiUQe8YmDM2tILbJ/3cnwj23u5ZOciHl4NlhHg0hhI9TLqkdo
RqKaJQVUOgf06JKrsV4ZzF89/hUa4JgcxNXY3b3L+rY18rOCmnvc1P9DzcW2oHZy+FBldgpG3uz5
kHN3E2xUNjHqFCQb3VJ89ZPjk2TcvqBKrbkK++np4+QhRu2b5Uom2xSV5yGmwJIO6hDlDuiAxjVg
saounmWEdw/VU4mmveWEw14yk9acLwRHrR3t6ROEBPJPfj26yh0sPsKRGI/bkCk3/WkA8TXtMfiT
tft+RqwZ32bexbA5pNJr0Cf9nvfPMo1qmHWAjrx/6VRBdxBmTYbju4wxlzcp0tVsLdn9Ea5BmEnN
HH0cqerl0ioLD+mz30jC6J11A2Raa6VOV3bN9Be9v37vxWPOh/5ols1o06JYEQiFBKWiMdTaiO4b
UFOhUuAyZZe1whjJcJt74a4j/wf3laSB0hXvuFWbH7jYLytD8sUOsuraHWMq6/SC7I2G6Ktw/CgH
cDRncvK0v2LULqq4EU9bx96/bpuxtQl8H8LnUmpSQyH5nQQ1cR6TLJCgBL4+TBYX3N4nJVOLXct1
twsHHpuUExdNGF5nI4ENJnFls1iqAAgbXpAajrSuJuquAbu68W367BLqUuCofavj1MrYq2NTV/oq
PhTiKweevyYe/976VchYMCGcKz7nKq7eeAuQOcL8AkP5h0V4LFxvd7/5BRKxt8O58nQmS+DR+rNB
mg57dfyThnryUrSJztoCqbxwrUCIQTMe7yuU/DAMu+jivYyRpLQH+d6KMZJ93QlyMAIXDS/JzD/t
VORRwv4i0ioTQie6B000IIQkeTugNNhaBg1hdWMoFWxKzqGhHQiVAj8hrr8TyPKhF0kyKjxSIfb7
pkDXi17bw9BM1y60iRkURsRwfCIz429yR4eTt4jQOdkTpIx4jp1krhhLQ9C9BlUZ5iDJIRj0AlXY
LaMtr0fD72y0VM5RyTfblL1ix4Z8myygt2HJZBBz1UJqK3njy1KN4XU+GGwTsRvKKduqB1PGDXiZ
qgiqIHfz0vp9Yo4LwCrF3eMDakKN5DosYq0DN2PN7KxW5dgZyACvJmxNk76XuKnbnUC1g2eiNEI+
TGlAhbdPemqBFSl6o1r1lTuYpHHKsRXbHVz57OFlesNm+5Eu2ufkkf42fqq06fdxnf0hLcgMysWi
TG5AFSK5KuyCFQAy94qZhBWfMU+ACVvsy6zRRN8TzRSxNYxvDP14Pz5Rer3BFo3dNERRdpgzO4HK
ZuzyqhYekYcPVbtW345fwv7YKjrCqMmVHfDhIclzB3oW7Cpc+Lwq+XF6AHbOlURnGoM+7+MVdAye
F9dHHpfoDoVchA6N3FQkvcP1cjLwRS6hULXuW96m+2mAhY+AhUrhZzXkZMbauVskxb7BOrwW4jO6
yPcQHoVFoAQseb8+O81qDsxxjNynNUWAoeCKSWtPUVj/YkRpQQzu/0NbgHi5445jNnV6OfXR2y7O
FszjJw3NAfxe1lFK/cKFAPqfTJ3a6Jvv4ZJgAUkOwXR3fl5MBZ94fLIOKJxFsxgdtHfhdKLGKqK1
7FRkb+2nvQ0HC2MWM3OTFxzh8BTVM57URVewKPnLB78+FCZfggEsLS5rf18mm7P+IrVcTOKvgvLy
ERRpRr5xAQ9Cev2wjbUfkAXP5VqD7Jn9Is+PABHKeR5VNS4WAsgBIVR1WCODb5wrsvyH9N+aya17
wgjqNv3GoAtV6zeKejAf8vkZ/VsDgpYt+1lTUW102Da0oON/XH1JQuYu6ye/WBVeE3ksH/amGV5Y
e3DWLg8YYlsoMyJQUz30AySz3jg0Bl4WpguXtSIn9NnPR7kjgDOzAP3kEro9ajVGvVDr+qRHZUhw
NXRTDUcnAxlUesZ+BCnXd9vMbhen8Sv5T577x+Eo4IDHi59txl9xrYvYaMs86CBk+CG5P2S9iLwJ
X7wrrL8KkjWDhi2yaPX0dJs3tqPB4i7mJgO0jNey+wtUsvGqP8ztf3PBRxBopIYFliO+kgc7ku9N
/Cc65Wt+9D4LWqIyU5GNWn5lr5xftT6jrF/sShU6uA8JjCERWTJS1bq5FtcO2Xt2qCpEEcpJlt78
9wcQ6J5Wl9IoQb1S9X0MhbQ5Gh5hs0BE2Px2YcfuVHfCK4NEqInh2ehKrsbsJG/oL/atlGiJR12v
zje5cMO0nLi/1RRniK37EY7VO+wtA4hmJbc/A77gVkfuuIRfq2J0BjCF+ZlZ94gvOScvF6GNUaHG
QIjfXqvIiHgvTdoFy/CHoOMxqq7wnCUDKr7v8jgtweZvh2bT85f5CeY+9p0Drl9hSIYDOOMaYTmj
Djk9box8W62BmFnyRbGZxNeCoWlrqrnnklJICXysDiEbCmUYTKIV9XOlHxsuwTU6/OjeGru4Tu9C
vj/2gZK1tVQMYyfkqcoVq0rJMqi0nLVIw1MFo5Gx7B0DaOB3ZIR4GatUFvWG0MC37Z484YUSA4LP
SNjoHHOl2Gq8ah54iT+WoUN4wtrmzk9Q3nn2VyaaGHn+qtJhscFDf9l2KvMgT+y6nMjT+mWr1QaC
WVBEfPhvTKg6iR1b6se9qFLrMcOZ3YOpBmYbVIE5uR2OAnPQ223QbZauduITI2jyO+yqIYQC2BdK
EqUOevitMcUyA2uz9gBkB981x3pXMAFb1gC0CuoDLliM3VjkTXZOPx7zBBJeDeS1GbZbVCHXHcan
hKFtBv216EouzohdMpTlBR7UiuG7rEcQSoX+LRwb3Bj1gNpoJQ8ug4fqbC71jZRimIJtobbA4Qc/
6oJpLBFTo3FlPZVhpXFdG19a3xZ8XDFY+TeHEIXTxlmDGNiAmL//RwzHP80LP5We/jOG9JnWq/+h
ONRKUd3JzHZCwjFEcauQoFXJYRZIfjUpjY63HO8++mSiFnpZUAipT77kY3AUNMsqVssgo7Ul9v5D
/VC3v4hTCLl11VAq5zOt9Ddmu7aacJnpf4nOIV4bBkH5O/r+bO4IjzEzb4S2xEZCIDH6kGq9rhdv
50PQc5HXimj/5XD15hJXQYmBWlLc7HnCs/DeK3N9eJhXk5L9aofQwmPh9Hrxl14oIlI9QfRw25hA
duDl/6w2yTBgdLdcuHaXe7VXFIpncWK/GwR9UKMLutaIB1eCFZoexTl+d/JzhA2/0LwlwAFImgmc
dN0+uoakJrlfIERpMKyf8vP5kMXwL7ZRELxTcaCkJ3cbTV9xbqr2N4Ylwn8mgwlq7T38MkL35cHA
+GonN278oH/Nf6UICBIUuBlImzPMjH8yYKX+j2mWVmQGKqv7XsvSzxBlSlyP/61JcCxxCmyp78dz
LtmLye9dyT7sOU3kyjOvWvUXGWgiraJkX9ArUR+KGVbcqpKliyDBRS9kMOWqzjHoqXSdm5Vzt8D3
ONsuX15nVIucTOBm/Fmkf22U75GS2wNqzIw662UhIc39GSF/8aTkOBZPZFP8uCq7lxuyInNXrjmk
v6YS3ke/TE0G1U8H5IK8W+uCN0XUmLaQ9r3jmllfxfAU3rVDl4YKrioSHTyr50529wbL2wn5NqZv
fB8NP0cYyEtSMyZUTC3AMoPdEi4mY31qKh/5RpDpr9TKKtbkdutNBgrP9YS9z6oEDASPRlfBbFZ4
oquloaiVVLtZS2yQauFzG89Xpz3x/+7h2CnPbnyV3RVAgZzomXy6cpN4hR2k+aXR8WTTo1FW4tBb
h8nOOFi5WDRHr7AlJtXsTyBd75dCe9ZfXAVDpJT9eLXd8GX+LUgNpEoFdc01v7dfN6cDjq0VDDEB
oTz1anMA6ElABcuJC41aL8V4KyhbtpsWTjjdHIByIHsVmagrqoVue+cDbl17X9NuOyBIoSdX2Wkv
oW5faNBrPVyXz1BrpDSLLLYaFzpQ26TU6gwKcdJ+U/+QvAP01xQ8Q8qEFb8vS+5940BkuuW28y5b
fkZxyIv3lO6zY/ZYJ7iY3cgrIVQeJru/BGMZoPLyrsLwEVNd0GKKHw21UT4aei9TFVGMT0yMFrZ0
1qsrB9STQZPTigvImuHcXi5ezg2ENPhbEQ3d5BhSSHYeZmtAyNwtqYNbUUmNLcG0dGdSOIennYk1
6cxemCRUX1gVIV0WKFXgXW/w3dVPuPuugr4vD/FI2vpmu530DSD2TqwmEAJB9igk87PI36XPrnSs
ayrPFs6LEMikrExlg0nwdgnImSl3K0h5GGpugIzk4A34uvRjTlIcT6t8LY7ScWelVt9OKu5Z7NLC
GmkDRYxpptEgL/zfLafnd1yVjJlfoGjy0dpuytvMr87Ch5ejfYNR5WAT1spDgamsRG2h6ZnFyRLn
2vnmoSbU4/lzcd3t/9jsrjyCqV9+QvOU/Ia2ATi94tEHigF5WT7pDgsUUbk14N5yH3lBTQMgb1+0
vtRIpFaJgR0KeQtMLVDoP+rElJnnl95OepeCuwKS+fWo8KxS2aFrAP1xZHXCyOl4YsLV2U+18ijU
aZRzufZpimkhDCiep65L5im7z5OB6fl80/Bxbt8X46hYntdZ2nid5X9kII5qKvIL8jqdHKNl0PpC
VGowKCf4ls3uSAIzH0dLXvO0a7dUlewsdMbZ+99ayQKo/Vn4YblIq8xlAi6ZQjLSGef/ZlgH+V0O
x+MGX4NrZfkAdSvDdqynKJgRsXCfRaDVBRzHG6dxtU+rZjXUN0U/31K0NpX/iPDV/4/KcXukgX3o
xcgJ/as4CnPOk8fE1Gqx6ukazLplatDfbyhPt2cEvIX1D80wQ3RyTBhuab16rJDjTCtbXYxCq1NG
IYvbOZsAqHZrfppn5hX9j19J1W19vy3rbNNjp1u+ckLUv5O+cOXk/73d9qlo2TU2RbIVoHdlfXbE
/TGWUjHIylkiWsNhSVOm8rE4Cn7Jh8g3ifzs+2Bfgp3NOjbF8VJZMa5i93NMVUTKiyHmExjo52/J
0JU4g3ZlokN1HkIJ15ofn+0kKdmCmKezLNCu4R1xa6BaiOUATy+FE/2sMrrNCClBP0yr7+H3/C39
4aaw0KzMcTN0OFaLO0fGgS36DGaDQXNWTG3lsw78lH2JTVKSqU16wwU+tZoCjjx2r9JimUM6QDNI
AMTZ+QEskKnEFXEbQUrW8PPaR8eC0ukEfk0CbsnkhPrqXnLrB9MJdbGWuUdGQSMk2nMYD2zlVbtt
0GKt9ERqvIfjNjgX29Y4w94A9G9KFMZ5bkitDICYWwyvZqfpZdMrRO2iq8dlhQhMu2OjKj966SpB
ib/9NgkjAesLJXm7Q1XkA6YAkpXklg9noxkKYMl3N+I2+xYsvXpAu1zUM/qOqwECrVsfc0fRoBOH
TEh+WftkkAfwwjBIZp7RsLaz6+qJxGqamA/8T+TR/fSenzhC07DmZj0Xsh9Sf/VjebupgpYml/z2
BwkmLoZgfZ2irXp2JkK3VAmpMRGI3STeHeWiRynf4T3Uz84IvUhRskVuxEeTC7ps/6ENaxkwNfYR
MqLwAu63NIE/S20Jirj0YcHp5iNiMXfxqTZy/45TKi+RQmXSieE9umTCsiozNx4i0tVtVOa7r4OK
zBzGTRSXCwR6qusH2f+nJ/PAy6lNvanslS1N+USzGRWwPFTCEJQvpvO7yY1sguAW/WpBs4+beDc4
1IbrimkxM3b4qnOReUxAkraPNN2S7XkI1riiRvxrHQVLEErugpob860ynz+B6xL85mCmNjn0fNDn
V7YwYxGlQu+FqvVT4gJOnEuOQeI52Z7y3vbH71ba4Xv9HcXXQCz1oPF/zVE1ZGBJPPa5dZEpNHfG
621nSz9LU4BVgeZxDEhgGd96EeV5QmH82PiXwStAGOV7Bbv3a/pmMC5p5lwfqI1YnSmK/XZ9ej2G
tBByNKAQvAIiWZI790s9/G3Pdwtc+x8J3Ch5/cKtlG852pBzO8KRj7a72ZGnBiWsPmwztfuVPkNu
mfZ2339oBCxnED7PevxsUWjWZ0onjJ7xjZjJikn11ygqW0d3H3Db+t17I1FllMVjXAXbl7e72GZA
xsvHMvoIhFyQ/MFz9W4h996eY+LoazBfmXRIOoF672QKhtb6NmTqMOQ/uRg3O6Nn3SJlXheaEWir
ogYIvL3Lvl9pv/GyDzXXSbRK2luXSEdsTQajXdt+qvXI6jK065WulMTUVtFTEDpAE8O9Rm5hD+xN
ki/k6nBNw145fHO8nKig5a42Ju15A5TCcvqstw15BBk/CbwwGzIhhyoR2P+sFEC3AOhazfjToZSL
E/6TtVT5q4BY+P9M2wtOguoAUx7HgW33y+hQIef9OzdklO3LHTESin9j9RtilZ08bBHUfO6WLoQn
9OPsj3NUzuJrMrOsyrk5fAyMAwM3tEbLjhvOcYUJcUxeKR2Zie6BzWC+doG+I0IiQHkatyE68b8Z
XEx424upOX1U8xvWj4yjekpTiI+wgA2OUlfEMJVm5Hql1xzdP3j8TfV3cl0OdGniTOHZ4ezd7qSO
d+XON2T6ORgLOLjFbtLayKZ3FwdtmawtLBYV+R9bGDXE1cDk/hHOaH2rVmZMdVWNSbblEU6lMPhz
KK1PhVjIa1CEP+pOn8IFFnPNODlbASPYT38VK+0xXFgBm1o9CgeZtPSI+R2+drxUzhQ6afq9C72a
muPNOj/+QtgCImYHV91ozDmuUUwyZWBsUdtsCTAFAbJ3j+gO+kSeFN27uTQJ3J4myJTIbnndtjzv
kG94Ex4gbqoBiLU2jhFzj//1s+NFycuqIhjHQrVpoq6h3F3CK97/Vcs1FjyEgjZlhSeKzxNpZYQB
vNhI3NJSxUBnU+25B+YCS4O5+o/l3JirKopE7NNZOPi7WGXC7as7PVQ157OhvwuKaJuyUny2Yu+Y
3w0X4Ee/M26M/c04zgrnQ9/5dc6W2hmYJ7c2CAsGms2JAk6OrgLRSm8tdvrdPhZdT/a1GsfoHFA2
KLG3Ogd2vXQK96LVzFhDP3Q5pHZR0yd1z5yL6w4ILinDS6G6xM0Ddk4FVIxkZs4YVU3k3LIFB3Lf
iT6O8+7jBRozceLdHpD11JRPaBPgDYULMNhA6ACttkstGtOIBCYTWpmowxMzb6uI+1ypqduxOK41
Ymyzabx0nk/DjAAwg2q9BPkbkxTKW9ebWgOByVfkeFwoZbKxjRFIsPeIPI5lH73CUoyN7GW/+uRs
eTdbUtUXhukmy6Pp1F6n4pdrIeIoqz/kw2thrdMRFBEX2V1YPWL1StjPNs9gjEW2Idoz1Ik3KqlF
0H0DeOJM3K46GKSFhBIIkkq9B6/HCxueAf6RXm3tU5ZF5YIqO+OXq2ILUPUW99khPTklPMUL5r44
y7m8nQsmo1IDuQ3Ta0+OVtHN5/ZnL0ZdJMSZ4I96LNy78r05sXKgDLCGZ64n86LcxX4Q6HMFo5BS
pLE+JVzaLi8hm1xrSZpxLuO3UbFlm2oHSr7iOeuCxFVHDrjSq5T59LiC3N4CR3h770feSif5s+zA
aHNLNeKrRwQhFLXMzIXY9CuNIQKPquaKMpGzAJdcAFpK8XA+jmuVvFpJmSoTHeRQ56H3RY8Akcrl
SZmrraiEyn1h8XZfx+nk21BP01q2D547SDAfCyyu3i68L4xDsnr2LkXKZfohzwnVeg39Vy/kRAIV
gSpGJ5NMwgtEX/UPzWk8gh5Z0IwGislFIYYXHaabxnfEFvtq2+hEdAz2TwIXz1kWujkPwev7mnuJ
SlrkMHoFikGKbKJB4IZoX3kLiS5Whd9a5vZ89FsPTkcRYiKZbGUtAYL4sD0XiI/sEKMwgCsmW2qN
B0nXWwOw5gI0dr97DFDoWqgCV0nz7wv39jRV8zxnHw061igzx77fOA8K+b4KVjbL6zGjnTAxFvyD
5yom8jh4Klal/Jg60mu7C85VnheUxdqTvQCDAjUcRVD9fnKo7Tke2Qt2C8piQtREOEYoyB6PChzS
ike07WgySUFrW42T6QC5vOaULzVTQQV+/4nSEsH5jBmw8EuQAigrDJW3UAtXbem5SKJfxOjueHzW
ATcGhcn7NJfXEMA75G6wc0MrmL/8XEjAFABN+R5Ubw+WCxKaWgVnaUYj/KyHHwTwl401QjHpJUVq
b73d94F/m3zJksCZs62ANqjl2C27JmUP6ENOYHNoiw5LjsVp+IpxahA9cmbXSteNAa6YsaSMNvrH
vWdX3koY0K4lAi6UG87iUm3XUHH167wTPQlsYT3Vw8IW4tSjqvT6wRn+Q/kMMChwkSUbHCadr2lV
QOEjdFNlmCX2Jh+APZv32+aLiw8Tt+n1loTxzp49Busq5dzj8pjkY4J2tXG+OWKPe66SMPtQx007
DL4E8UC7DiiYrUPiA+IG8c/Dm1mYSmEhMuiHxjIFqPaUn6Gu7Jt8GNbQ3gTqxqXrssLjaSeW4aHB
1zCI4EK1EU5PD4EL93vNTJK/zg1Fx6Wy9JlMfGjBDquGDfZ5l1buIAANKFE5wkzLlkNveCuGwlDy
ILyAxmzv7Ly0LfBiSLmhfOJYEil9gjddx/7VZb1ReV4oxgHBsilgYbUykFKRhu+aDpzvzOWz8rrU
+f3Pxz31JC7RztkjIiJ+64uLYKHbSswMcbICn0NHahdgMchoWU+5B4E9qXoP0/g13jR4fSGkEkiB
JqyIrYpqyFmme79JFfLmz/Uc7wnTR8jM6tzebzLPi4M/+ez+bYXLHqNupmg5dPRlUARoMXGesG6n
HCDzPNf3tOJQERp0VEiN5AVnWcmxouXA0l4VEThqHCffBQoKUoescSAbwgf71l5xdu851zLopJwQ
Mr/0zGjhhl7RVuW8OmZN92tdubcZX9iTK/s+K/r4krb/kZFTCPah+yto9zWNi6ih1OvMji2PyiJg
OIAEJ8wZMfML3Olt2yuSjY2nXafTvqY5UCwXKKSOc8PKjeMYVMRdTsOGfXEXiVOYwylgQGPN1UMY
0+4p5hJK1LlhUXNNNIn2Vs0LnE4vKc2R2j4MGYKmb3nqB9+uH9h6noQ7lLv/sPTWAQiSHg9bPrFd
8La3Ukm1TxTHlu2sBBS3sR9nlL3hq3I2hlWGR5//944YR6rhEtuZ9NoEKDo1KfFbmlfaSHfOAvqh
DA4K13OPPYF/Uk6Gz5W4b9kk3+E0LpDF0BJiu1f+O1N21mpdMgQi0lUa3njzC+GPkE/Pkepn665V
ZNtVuXiVrD63qJcKf4+IcWErVwsRAupRMGrRqDY89nGpvtZYuh4yFoSzcCjxiF9I1Nqj/REaD1Xd
j3oRTZ50fEYzpUb7Ab3ymPqd4UAeY/28kXf5/eQNxQ0VLRyqBKbZ6p+bL7RjAGjACPtNV3im7Wqv
UrzZcgwe9Nbdu/E8Xl82uOChBhOKptiZxjeVEOdmlT8hMzfBqCkFpyb4D59TQ5svo8lg3fNKl5Ln
JedqfvRhhJ+8WkhhTU4TrGuEqKBsQuiJwR3TcqpAkhxiyJAzcOOH9PeF5rOhf8N7XDbUOoCb3NzU
m9sCCWu7DJXOvDbgGHLgd65jWydtDfBsf+jn7WRO+FkTiNCFLc0nDHwPHXY215NChBViKwDTt0TJ
y95CBERZmpmIGDYUQBuvP0GA7pXb8eWWhaaJZycKs/LduZW1yOThLVtoEp4/AareoQFfBta9i66B
NjfN9l4M6b+4MmwTc9qZRhcsqZOfWPEj6U2VEnIEpo8Q9tiYjGJVhJh5I1uVQHGF6FSlsWc1pS0B
oMVZzxKm3ADMizGZc9+qB5Z00mAIgta47mMz47Agstbqfvo1BC0oUByms9pRQOWMAx40JDNf/70l
Xvq4zGGPNFCxzn90pkWE6cIClpHDiRCZXS5/qY+l/dfYIoO4ZEgHzx2OAR5IMzxIlLGor8pYEMZl
oCb1KaWaHFicW6eNydjEJ5ODoKkg33irIQPbfMXEbwaypm6Yq7EdhA/M+3WxOE2m8lcBmf39eRli
7Wri12maJEZ2OGHmLKIHQ9YAzVKOxG6gV7wRLUqDx+xoIQH2SJfqNBjkW1s+a0OL8mta5OTwvdtV
puAjJp1gbubCGCD4BhReHjuukayg0kchqmhE9ttA0AhatX7iY6g+cv3CjgI1ncBIOo5K9qhTd7pe
XUDbJBHF3UujAvBuEypfvwa+G0nbHddtvGRMPkV0gecYG+yaeQyZYRH1zwwUcImwPCptuLIFSK0t
xTirw5tzH/Sabz8cnDH1Mjb5wVoG3SKt7rB5s1RFWNPF7bsvKG+lBVZxUyTLQOGbauyhsVm4rc5q
cWc0uJ/bJ2qZrzArnef2H63aRPmw98vbnRSiKn6CS3dSlcmH2DQZbchryUYUm6qq0bMA3xPrw6qH
bwUxyC+sseZ8cRYQbomRehimSmRfR6TUmaYLK+V/vNZQU/8HVy2QHhq764OaO4P7Liel/X1NnIHH
wIeZLK/BrskjJkvA3RGn1Kj7eCvlEqVQ5c2s/pqxIKjS0/0zvJQR/ArajVBS8OeHZhUz/qXurnlS
AjgRlExLs3XQl8jQbqRnrYw/8RjmtCUpILq0gNsbWxLRrhA/xeNPZOoFxYIGjj/SR77MM2ij36V+
oZblsS8Q97ps3Hst4CiE4HQPBGNoYtwQ9aKKESPilqW8PEo8Byjcq2OAsVmn8Y/Rt6bkPjry6EYE
ZV2/LhE2IkJfKMrIfe5COTw1fw1WWa1zZG7NQazpYSGciU3j7P53pxC9n+9N5qUwhLUBdOmDgBN9
ATZ4eQDR4PEBrIkZphsTqNP5JRsQoDUstNRfD74EU+euAxXnE2sbJfNpLMNEcThd8thFLoLy6F3n
TKimJ7y3xWeyzwVO+/AY1NGxpspkFm1qxAIs/4JL0j9xhkWYTylGJs5u0UBEx4qRSX1PH43xokRl
j/V+m8WYZq5H9sJS1tQ/dX4R+KmBxm9Nd7Cns72cuwT6bCSMT/mu6R1VfLAPcNFKdc5UGvW0JiM/
cuqRt36zbjAmb5MjLRrgOuVU35XLSkhYXkS1axwHALx/YaloKc6+RaPO7XekzQpTSPgWDtzSz7vZ
LtDLIc4LclHoa356D2JCvGObzufGL5O2m5jCge4nBhTHzCFWg4WfYGwV8ULkCcOhowxPk8i/A1+h
OJsAFzBbXs1L0ku3Ap8rw/Qwk2R3pIye8lIg+6kjbSTmtA1/AkSEY0gYl9+HsEVAXm+EM4BLeOqM
Iq6VCkVcSDHxCJK7oM0n7kzD8MBdjx6K2u9KqEvqJ7/VHl64Id738M1GknudqcUuWdA3YWMWp5Xb
N5iFGhB0U9ruedjZlcpG4+BON74sAbLmWbtLXHAg8terS0AvOoh/sq3iE+R+l3BRuGE5/P4JHBMi
bnDJm1GuQjg/mQKFKjblrxZmzYZu8I7mMVPPKzPkLGf6ObcGlyAm60Tt2bOgaCmeXSbaQVXXB1jF
/gNdJ/QJSlsWBTQfXRNZgts9Y9wTQ2k50X7c1Om1mUJcwfHtTGaWgrPhAQsXH3SCgNXPmSMtLgpc
2OkSvXVwH/c6pTqkxNN2BpNMVcJYptC2etGUE8nsXxu1vEDO7UOv/gkP+4E3MQRik6hXfuRDJ0ZS
BXvOkxFUBawEsHZjXWWdyzJQCVZYqfeQCHxYQbueDlsiqhdIYGV3PiZlKqGDWuKW+iS22SPruYuQ
5uMAhuoKpRmbvN2ToYMJGxePW9bk9YTUA8mK2/qjmifhb3uif/bmd7icAN/5FNvwr8MNcXVz7kul
YpWY3wj1wtqFDF6SV8r072NqSMKw4MWXfbft1f/LpubEgJhG0bGm0QRIlGbyip+FjlWqv3t39aok
pZV8taKhGLSwA+Xmh/rHq0mtmYDdC3hdEH27cNIm1cXI/GRJQLuV2vtBzYUCP3bLbaYvV8jLQxZk
9n8lg5ysmAf7AZtPfOqZ6Xb3RyykaWTe9F7N25E+w43utBsErTTiwsrToJqeTIJO/RLJHuNIVrRE
R7S7N5H/EjpPdnVahYwdDqlnwWh+bVgi++O9khwKjhn1Jz+7wj7DQ1HNXPzkl99+l2RBAHbdbkGe
IYGRN5QI2sCa58vSc4ZaHu/MhUXYYnIinTaKw085KMRbZdmWYKhLSM7IpcNy7r8AMEOty1BvYpqD
E+1fzX7PZijx2C9vgNlHHq5UYCpGZqf3YU+StDMT+++v8UPF+VgVnrolndKJbG5Tate8Cwl6U8RA
YioFQTLJenb+5ZqYZdzlge1c/LCtMFd29wlUfrH8ap/H+fv0N6DbM67WZvATDAIl+PNIvOsindwH
wyDQkLUnuo8+t6B8M5hJkbCEmwhK4Ww/jBmNiF3pYUKXGTVHVCGnAySCecDr1Hpblzt/r1XM7R81
1nPNtDCSZOduKmC5LGUOKkxPT6574DY8FjBlk/77KJAmjlXjp61HoAvgsSBsnSsltrJJGDCdgzFO
t10cMffioVSqFKZY67XgOE5E34Ze3TCLCuGqdszppWJA/TFrwkHKFjaUtw1bNhuAGbApAvusUxPm
VNweAQ7xRpi61i6cv7jjaUfFVk4zdtOAWKLh4KsiW/9vKEZ1O/M6m3ghOCVy3SVqhmW14VzD+5vR
+g4/inuYfgU8nKfOnEwg6DwVr/A1qjFAIv9E6KQWg+bXa4TOE3y1dpd3epa5P7zSDqGGqbTccsbn
apRiOxPb83X8hCorHPsVKjCaZPkcoXw10UKv4wWsdurKuHZ08aVlIq+AZ2hp50tyeQhTOhzf5eB+
N827047jgWs34WBmFfT6sxXz6mvXZQCBYUdS318nWtNoCvc8gX5cxOVp3u+e8UGjlMLSynA46jDx
aHGJN0N0Zhi5+Gd7jA92SMMzLRtUOEsZyR2dAABAh0Z/ggLgj1WAsm7R09WgTTvme5P2GDp+ldSC
NhDipxGOUyA82wYH4QUnc7tk4s02Hz4aIFmRCFKJWXUXHcY7B+IkWF99JJ7ggffU4ko0hxOs4SKj
HBdOEbRZ2FISi0KPf+eYJEGETm6Gx8bYk+D8ElCb8GRusspHSqernFYVsNU+GiCDOZxxponwm8lE
RINB7ER/3zVvG96sFyp1C42qrQs6bxSKiMFifXzhIpYJyY+UDqCM48tWtaGNGZWDbSg+s2aP0oll
NtGG0CpzAPPA6sS59+9hZUY5tmbXbmDW4e+pvAzabV0rtyoWPHS//hdPDPjcq0NYg7fB5LwoIsdS
d2B+UK+ykQwZrVTUjHDWXKb6Lg945cuYfqeHmJXQQMb2aG4+/lcW2IcG4+TpaqjJmZqrbPIafXgi
n/npdhJDbNMcZETWp9MGmNRZg2NU0fCDMgt6qoUWJSH5CetnXRf4UlmXPhNRgyKuTd7zxlanlpsr
yyK152KEYlOdAMCIsxFsp8pLfezP8E7qsgpHHrJsrtfZcYSbdNGk/VMbsZ+UEovJOiqrGqgW1cF0
GEIYdcUanS195Q9/F4LGfw7TPdBtQDmPkrS/P65DdjdoNL5y0IWbicoCpHSZJvwZtrQ2z84DB5Lu
+BAjdK1Fj4W8BRjmbVXd1t2oN2UlOtx/pEGeCDXHwK0zqvf4KYeIfQIy5PoEXGcLiO+dl4xeve1l
GtwPm480vCa+B/YOg82lumWnzHA6fSCIanq2jQBsJ697Tgm9oKwZC/va+BeE4yz5UqBPslQ2WTaV
e8LcT0zce6t26jjkn7iyzcsZuAXvymXo0dcxapl7W5Tbd6zJTQxQM0JpRRokHY0Yd1pga7Dkwnep
fda/29uNCN2PgugVi94iDJlwNVCy36bVySf+zcW01jg4EuF8BD6eYe1CQd/ntUR8y2knrhunLlrY
iEywjtB48xu+cUztHknP9ZOuSkxiMecNDUUXDSbvI0Z3wFRW+2D3wKFxfsuEqccPa6Se028HDcG/
8nt0hczSvHAJkTzvmXTOaxyr5c8s+q1nhiLrOWokCNUn2EzXRiyBximr+XrDvc90tTYrmYPu7TEc
0XbLGPvXNBBMOuKQFgdWoDPvzOzD4rM6CtAw6gg9bC0D6ZLiy2HtdqdI3GXoB3mR+Z+Fk0jS0tR2
Mclva+C14Bo7KgDPjxFANQ4UxheWX6HN0E72wZDaDamwjOsJZFnzk21MS1yv1UmmodWUP1uwtTFr
5FAEXaWnHyXgkKU4D23aLQIBFC0zFixzpaQSgO9MSerNGP8hLHpV8lh45Hy6XWjSRgQw0JWODVLN
tmXcG3DZ6dR7+JUOQNgpngbQBWTZeLCQ9JD64fXGA5QUIroqiPm7GxaS6i/vPlTveCjeaZIXbtrd
h1BSbsEtyip3wb8iCKqPo6gFh8A+4R+T8KIvUpabrpieDB4C4jEofjITiobhbt2+7723q4pYIPL1
RSv3nguxIYtj9zmoT+HFlOur18nG/Zoq2YeICzs8bKbHA0KStw5995qa3s5xYG7YhO5ITi149bFL
xHyEMumpZvUnIu3ZKS7VPO2WBIqcrNiPtdGK1rGkaVjFhX3ILJ30fmSHDXt8h3a8yoRjdrhc+Olp
EdO+fAPARLTXMhi0BKLS8VFtpOLB8AnUEGbm/FAUjelVtBA0I+ROtdLyuZXnPBgzI1yCSRCKuWQd
hdlkbYNIEFWfh0E5nBWF4B1hNVH1rgLRJ3rYAIWtn8QAY2vhQPurUgF0BrLKs1aK2JTpeVlkVR2k
9LeSonY/ePmm/GBMcC+08Wk3/PABWtll7Uf/4oDh/CR9ahODlhz4zS/Ij2VYzkVwXtoNh8xfHxhF
t2L3IJLSkqC8Ecid2DqJ9bw19vBMsYVUjimwjljj3rU6FBE4NejuLVdu8p9/lYpbTpqjUgVLJ9IS
PEzrfKqesoBWehnmBubU/EUDErEgruDC77Mqqu5aPQlJgDdSyNCZU2w5kJ36fuLvJaSGt+2lBsno
fbLUpF+RDgOEJcew+0Mxfgb8kN0k1c7oBBkS3tZ9ZAhYmynBiNXkpsMhFKQlzLRE5A1BZdqGQWTT
wDBPKtqyrF6pHU4zaCo7j/0XoXHIUAZyy9+yWSCHWxweUl4VXZYxE1qNk6FxhWdIsWJtUYhTKL4w
HW0vciRVsqhTBw3WEApQzkY0gKnIbmnhn6JSLH8aN7QK7CO6ooiV3ZCsJk1O9cH2C6wETURWdLkm
Q0BrqWv7VtUJsqDw7Chwuo5EAKFggwCeJKBKzSGsg0WX4q0CfMcmYMnAVXFl5d4AtvYNyhW2QB8G
XGLlsivxobGWK3RmiIGNkIACGh+bNKIbXyrCaNnI0d/KITo0FbiZoklp/gAA5r2e8bKDKd04y2Y4
iNnPOZ9E2q2hc90LNqeaBnO0mL71lwXQbH5x1Gnn64poxYDkxn1xIFiJYYwUD1WSK/fRTiBgjLsd
cm2W2ulDAhK+6eItbTx1enqEMayVg5ADPRSJ/8JC+bnNGbKQ09VLXfuwy4DYEtAmb7Ao3w9IhtWl
OFGZFhlFJRxbJSwDbUrxdhH0k+qYXIRksmEBfrB7IOF+7ZRPWwUp0CT+Yz8kKQR2/3qAQ3NJCXmt
keBMky5LtxI6KaZs8z8yDbPj/C0stVGeo5KQj4wtbRhkDJLM0IWAgh2n0mQ1HgQBE1A1iCIkgX0y
+Tuc7ZqgBYWpY/XPgN+LQXaefaMgmyYleD0DyKahbAMJA/PRFpPYwe2OcXOMvCKmgIWTFLZMnyKW
El1xYlE5BMludmDr6tefjSCYfEAu5ej7p25pD5rSqN03jNNljhjXCq8z1iacu0n/vbapPFoopUr4
Lj6wYMda8dX5hQBusc1N/0BTFM+UsIjBBELYfGFAhqi85m3U+re4/ID8S+McEgqkSxkIpXf6Oxn8
RnMFhyCwyEyssQiMpYJe5g/VFDg4EAWtAJLG2VrxkeOQg1CCKBvjG7zWUzXHBD3hfOJDCEEMO1Op
aHbmi0PrIkeZoLD1GKH7V31CC/z0Bmgsi3JzaDrlXlzyYosUrpBXQbxE/LvQDONi/eDHEf7R135k
1HO9zXmKACKk3cIYFKgNN8aISRZW+XSbvO5E/AyYaAXiGsyvNSXzxANqVCCZgEKM66BvnsSxvAW4
vBu3/phTm3Q1b/2Sg4cEGkhL+3SiAzKYEieYPWN4DyBvnt/QllMBiH3GnN0TXjKIR4Zz6WaY2cZk
qhNdZYp8wW8Q7vMIcbeDSEtHh+q9Rgj4NoVl/AefvBQF48jUDWL5EnMgUJM56ZELcpYfeOZAGm2x
eTxadl57CupGrRp6ufwptL+80acWwm3Ei2B4obbVq64R7YgEy+OBNl5huwB3jdeifIcXdGXABGQB
19cNGqLeoJFgMGnNKtV9KfV36OSIX6jjMpOP3DUnJ05btrRIeYILtu6vzBl2Tb01RLI9ABYDYTFf
giFZ/4jN+4DkajOtEW94XVHTWiBM6JrnY1o+7MSmT0jnjxbMwTMdKjCH55Pu2c/b0z1YDdvvqy49
tzAoDEa+hB9+Simiw3ehG+pSxRzh04xDQQor29UFAK86pycPl43FC+1QE6mgGmaMZJuj0eVO0B00
HFX0cK1Lv8DVpvvOCvE2ZS8lgd6WpkLK1sGfrzfOjN4sBgZ/JJSTCFiAlCdS/crT9dIDWrvkZiK+
TXRr/91iS7WHxq7YhtuskoZUb+uKw4qtQwsC2JO2mhsk24uwEp1Cvfy4VLTsoPAoyaVVHZlafKWs
Sm1tfnZywi3eUxkJAlLhyokOtFgHnB+mo79EUzrj4+7dZE6nTCVmsXecBhfiA9LjqZ5DYYCbHwzd
U+67OLbFIXxuwQkTkoFh3lS9WEm5tFATi5YonCn8c6K3Aer8EmSkJjkGQnl48fbvdsmrVaI/pHla
eULZCoSKABVWIZGknBVARluhO8+2rmGlEdsO6RRDLRtNCq3zaRTBDGpSdb51gaflnFoloJ7VQ32Q
ZHmuo5AuF+MqA1wt76XG+/QcPRTqMBp9lokG4xxxuMEELM8zz4VDzJxEk4AIaug/d0AbvDzeI0r+
OYTbrs6bS2CNucR4bldBU+oLjsQSIo2MP16jbrkmeNv3NCb6YzFVA4Tv0bMvNGNUXD+nFYloWM7z
LjY4IoKI+VA1BRObGxZ7glMvJul2YTnajlfdcHcUFhDmmNxDddya7OF87pDhOitRTOxZB8M+ATDN
fz7u3LdY9U2enyff6uzFOZzPJPCZMrEGAzZQBOHuIDTMWGEXqCmRhb8e/F70imOnbMTRMCUAQWyu
J+BvzXhHu+i00bxiklxaxglWfaohoKhCxN3aTy6whGYL+eSuT+hEja6JGNxoDMh6wmPj62lkaSK+
F+AiOkQBGho7QmoY/I8ymVVQ+8s0mk0Gegabo+6hcz01nJ/1krn+OGuARWqV4PyJNxG/+WnIG1SG
M+vP0l7wWS2/BZGt4lNb8gF9e8QOONuXwn4GJALmfV484sFDYfv3PgUmjj65t3GLKa583e9qhAGP
X7nqzxoLNr6xUnXztFVY5hu4cCiBOYNCzXOaHrr2jTLPV3ESgKWZnA2d+0sp0966YntAkAkA/tgt
Y/97jSBNMswPsu6GZ4w0Xd/PgOqX1UAbQ6gdE33W0bzVYRT2gdzTQD/cGPa2dBeCDuZexBP7GsUk
6OmOYUR9jH59M5Hz9PRpflb0gv3VItM4SYEs16HBuH5KlKhgMO7kKxT4sMwL5JVSWrmVPjgpLyu2
9SMToP5Bk9iuMQpo6W6DEfqBEvi3yQHfXe68Ii5sZRptpHLL+HXveXkOYFl4hBZtjsaQAU0oUMiD
DqheuDjhQD5HjDH8TXwLxg3vi5bZIZYv6Ef2UELn8DB2iV8eKt8N7eH7djR8cEyAYDmmWoNIB5aU
pr48EvAoMabH5ffRbE4qNbyrFv9AUK8L6KQ983APNAz40SaXR1TV205zrv0CZu6VDZbuvYdExA2/
94KLz0e2rvjMhF7MavggyMyeSg8jhXpq+aZy/9MCJKvWjhYMCzPdeLebcMpyHFz908HnnbSJ1Vye
QRHD7fawS4IcRtESSQ78B0bjYW7XRrQuAqDAmK4Pt3M4wKz9ivO9GzIKqPnlro9wJkfuXY/juQW6
F9EkLeOlCKcXiFXsVMjw/AjQJ1J7gaUUpp7QBO7XiiZJxKIQgoJaoLxPodcq1AMK/AstaBy5Eb64
u9R5nn9vWeRAZUMn+yYf+C7frF/2MpOfXcBxUkwgOMVhqSAgMKXyOiGDnOWGvV8dWNrU4Eqr4FC5
DS42E4MNILbQY6jud4RSrYrWC3x/4gnuyaRByYhkyjErKi2IjhsNY5aMQZsG/JDav5kz2i/EQM0q
2K8r7TxqEjguMCNM1fQthPDLPvhtwY14XspfYJIJZctXq4bkaYlz2Vt9uTn1UMbA6/EYMGKpUh+j
ZWRjWc7j5k11jEVyXiEupo23eKgxgbnLzrHWap5k4y1sJoiY1d/XZ5wxoAbzNHw3dzVDz1q3Rd/8
yI/vaREmONxKWa5/OOet63bAOrDeOWUProztjAKdxFrIxjt7XgSDEWTpXBtLZUmeyRu0Gi1mWQHO
NuvU9DBgl/ZWXvtWlpjZhRZlwoAuohwCI1ZgFPBeEFJK7OBdwelCZQfLnFblKtD0iC9mkotrd3jl
/qSO0JWBfPqWF8kGoOPpU0SrRY5DKRKr8h+iHSuu01fHzb6Cu2LE3ZEbZSWvqYIyjlx7N4Xw1zEU
W+TOAAG4vnBWIy2mb7Lrz3jlzj5WDL9MnkA+k3oV9ur7ucQdvt9rvZ1XtGX2m8k+3eqLn7EiO0Vc
+Y7snmfxJJGWT6k/6xlgH88EX/sy88YqHuisQOI4/nciiI+ZyDN9px+BHRRko6wjF7qIBAnO1aDZ
ILSLhozR8FghMkF0j3I66orvG1ILu5N5F9G2VaQD1ImFnAaJo97uyi9JdNCfg2PUqsFO/1vrsqGw
QM5UPreF4Lq7KRzKp4BJeaALuGpLGlEqJ+NvBLU+pueH70v6OnHcDfbt+IFQDj6+D/KvykbI1wnw
oNYLXOmv/uX/+GRcoZV+lL6hMg/sauZnjgh4Pk4H2BSZqLocwIknB6IUNsTjeqriNEdHRLxO9CMo
KBd1fjO5rcHBMnn6FAyILriBoBS9gHwfH1h2IIW0a+ZHcshpLMhEIaoarN6Wb2z9JsXOBbNQ7UWe
LYQmsvdTledHbzmifofdvAOpfQFI6G8fPqMR1tabnVXG5ajFrpVGpxAKwJeBVvE3fO0mL2VqQXv/
aR6v+qdAWpot9Z/p9Y84hJrHf2zytuYu4j2LH8wCzfj8nJxmdvOHODqnb73/kRYwCRqk3vsQhNpL
3DcNgRQY0fD/GZRg5j7CsjTiN9fB1PIcBczcDy2qIZA03G4NaNjXxPsfpnGYb94PGdFzdLlFvriJ
nakxJPYG+CBkDoh3yzvJorE9RJmBjBUkug4mGhu8EGw2uTvPr79Q14ORyg8HhZ2gFEMziKrTGV/f
5tONAKEaIfI3OHiIvwkkT0IQ+wBTAR9yk8jXHcUrllKbw7mWh0ATcoEDqIKPdEtZ/4Y5AYTj2qm1
OEJ4v5YHMbkZ8bvTAtYL9kYrZC1WSIi5A+Sw8jrxoKOMrnk8nd8S3IKIkoEtR6DSmh+0Q8Bl6HwU
abmD140Y4QvH9bW+OBUpdse26pZePHsVkmKfYR+HwiV8XHf4TAmK4eC9ZUH024BqZP5z+2JHvdVj
Ewt1hEC4FWj1WuK2SPxbI3v3CagCRQwLVMpI6T2Ll/hp/fzP9+RFbUBH44i3xQMFij6ibMpOmyP/
XBVQHCghsyN1tf6bL1b9rYBQeP/JOPw0otiDou497cyoLpFrr51Vbu8Ux0uZVZZkxh8eKCg3LB6B
g+T7Du8Qs5Suph2+hb8x6tob7s3ApcyzQPzcaqsbBQ5ZVJyDDN5vY10GPxdvYeu/xZAOGI1Tb4N+
ULPhzHcPwaYD1ZGta4Z+iaUFaUc/Pr6MZhRe3wCrzHLHjZQ5uj3rdS0nqQUs5VjslYNSyIyf17gz
6rgCtkTGvKsGtAIKw6SjdsD2VQFi0KHZFVyNqafuR3iNzOnFpQJIqA3qwIGp/bb+gF2Zk5xKbfLF
XhAkpINaj6q32oueVb7QPwJd0iWs/a4M4GjLup77r/U3BqHWr122uIIzGgkXw+eGNvFF+DcuMn3y
wd3iPKog+klSpDL0XSO/qx2+C42LaNSiY9lPO8yQOrcZ1jl1HcrYybECZoGNbuFTXV0f9HK82zk4
UD5ZPuOmCppqiIBloY/Q2bjjxg4TWlT6uSumVglPBzcgCNi1bKgoaOve5m/kgSgR5/vfmW0IrF7U
Dm5m1S8FJoUpNvOvYBDgj85C/ww37dOrChQt9RGjEomo7agY/5ywFzLXWiTngSM4K9xRqYWve973
YvgSO+PSV16x7S1MsbLy+O/L8P9ddtqCcLRb09KTanioTkBugjTzCswBa5YhWPe+uAAsYHrF4Tos
n0ACBNY+nlsDALw/M2fJkykCiN/NSq2c4/TnQmpK9upZsRg9UuNGkKG84+A2db623Um7neGc4Eua
1gA6xSgEEBACOP4BH/aRaa/BlbUk4wCeZJHyLSvUuw/MMFgthfShEeorgMrPbNK0nXfQp4fUE6pQ
SJTnIDYexq2Vrc5K54tElWlUEO5R8tBg9YEKdrigYE79ltflxyAdmlWsdjs4z7Gg+JKyCjuUe79t
u1Tomkc+lO6U8EOI5hAgNBBqyPMJMZlzTfjXbssCM4hCqRc0l4NV4UerQBzR6ObZ/ReFzFO4vSxN
cw4DHsHqewTchaDRFVsexltDx2E8XGSLLQXWL9tpvNnLjmgWIZNBwNVgSbmLrPzPXYFm9eH+1Dnp
l5nMRumorwo+5iTOri/tpTLbbvyoMk17qaliYYTA7hLlNovwEuorM7FOiEjZ13Re6kaMSX5NVCf0
wdt+BYwOX5roHznBLLxI/jr89Jmc/EpPyykb9PX8SjCou44+jTkuACnJZKh4xcihdPcuAUqmdsQn
lkDY5CTErRgidmYD2M9hxTfFrhOX3zJCHV6nX9CHzw7rXnAZdI3rFOP5Dq/kBJ517FX3HYh4nggJ
E39mxj+tJcI1IzC806/CI/z7lMPlKSkg2klunQH343gbJ35J8gd9OI9Yh904yYFBZtsuycnKJG8p
dkuAPCM51wxOgkaVM1YX0wOpYSFZrwAmTleyJOqqBqlWfTGpOQG08Ny7qGQPqiGATXVN5dG2hlIS
hJjzGHTxXWDtJ21AHfx1+R+UxCt9J6D6ka9sYq5gAKNmorjoSTyy80rBpl0CZf3fVOBqDcc6ikL7
mWWfawDqdELsgfn4/elZYdBgeCUGASi8MlhJW7Q+PVx+rXJZP7XKEk/BWyf3fma00mcqDCBsD21E
I5GiSzZvuxE0qJdwkCDhJjiPKhiHOkFlQlgaf2o2LKJS5/UkGx7RHm/ju+GtzE8bxfL+Vf0h/H1R
z5/acveky0lStGCpv1O7EbbRzpYV2oyKMHGtzfo01KrFbKkvafrT1busIWHdIaPZ112FoBC/EuaY
t+SW6YLId1p2mD8I7rNEMSDtZVbrq3ubcItoxi042oopvsh1f6HsfZkxIHTxWkDqZEQ3LdR0yvo3
uX30M755nsAGZoHJqfHDMuuOWB4GTjOBaR3YIOrPDTgJYF5NRHtnPIIGrgv14+sSIxzD/z6oh4J8
k86J/kk+UGAs8lu4p1YNYar4QdjUzLzrSlcOjMVlRcdJ7v62yYZGZxsrtyc33vmZdcGcMEsw1hJs
6SeFTJxpQOFz9RKz27w/wuXmSI750fOrar1lZCmHyHXRtdblrw8nwyIB57Ca/IwDhYgodmfvtsD9
e66YPwwGMjzuEYramIhEeTmtBXrxxwi3RD3uHybybu2fjj0CPvjGO8fUQDKSg9v2l6Hl8dma4CBV
AGuAhWYib8ReKMRcFE/tmPtK57GTwh+1K6LSfOFk7XeDXxW/idAqZwahVtnTXZH6TEh8DxmBpzuX
lCjxdZjOxMup3tZ/YyG15blqIAZw1qs4I9p8HeAUJjaCkMpGRXb7BiUBTER7DdGvY1Xvq8cZLxiH
zYCr/ScTzsaEYDGZFa276fdnQKUidsDMas47oMf2y1opg2e6wqYIfywy3OTztldTrfQbo9Il7SlQ
zVkZqurdgWrC2d3LKMx0V83/RN+QQ0WHLowwPYfTojXJd/BX4lsC/mYuDy3pF3XMJrWM1UcJ5wn+
W5Av2E4sj6qO0O77vtlcBLBddKNYZIgk5zNN5SDjwxCs7/h6Z8mpgI+GGwZ1E2pQZQMlgrYh8sDh
MO+mgKk8epHaoECRKhHuYoDtDvWiKAzV8r10JmHUdnEbUVln7SDMmREjJTxmWZf3p4knu5/Z+09s
V/yk2rATlO7sLUbOcn6yP9FR3zZdgEx+3zrSIYDI/eXS55DV03lcm//riibiQDrCiN7qKx2W/3kJ
p0QSayUjc4PqIWlsUmCCd/1e3TiraEH1N/4CQg827zjUXnT7FPgLMDzDNleWb0Jrkd7Kp4ubjDdQ
3E3F1odIPTXS55C3MBPgRiVAfrTPMJjLxW+r5Nqv43kLEdc8RGwNPRhjYmHH6OFdL6a8Os9QFKx9
0vFerRP93AStsa1mciMp1g2oE4LkVdJeV+MIEu/qY+BP5oSEoIVH9w0ceN2ghAvcRmhVm7KgvGJ5
/oNy+MjCdkY5vUF3qrYlVOOo5CYPJ4KvSV5un6odhZWiHuPvk+lchRD6PyQxOgYYughkilxJVacS
BHahARW+0MdVhazCLVKN0DUKxyOqLDT68DckPOCEfpRErdO7SSlJTR7W3gOiwtt54uTr72ZoONJF
hP+SF8yxBoDFAKllAp60FckHBNOq0FOlb1H+vGyQLRFfFP7QdVYqFF6F0buTOq5QRYhdq02AiN2w
nm0rzCUmrLASkgUaubry+v5+miqLM7OkUs24BC12zMYw2rDKjAzaH+cJBWdsrZtweGkrcITr8yRh
v/WRefhTsXGQqvvbHt+XastmpykTSFxlr1s4psFGpxy7bvW4dh9CQUsX2BezRN9oJQM6/icUj2fu
SbqFetkGN4nJofUkKygMepvrjStm9qZyLWfQKliS8vs3NJW+ZxeVL69rTmug9zkCt8OuosBwBa0O
bDCrNLanCuH5kLreKMSIxZ8v11TZpDb6PHLr5wMG/os8uqnsc6q+hiU4ZXFina1MioJHnfk+rMGi
jwCBK/S4SIZinKyIAmd99T3YHYkLzOaE3rxKjvt8UAcccPPXGivH8GvyX9pw/mt1m0v5LYMTW9XA
ZZ5lTS4FYdjJt2L8U4VNQ2h9mfIf3A3i7/+dRmlUCH+uSzOGvtqeHUf3Tig8FeOm2rDIFqcjTYwp
G226UzS+jcP5ykVd82mF/6J4dpTq9ZaFzuNQ4Pa6nmX0CUrBQP+VmGlhoBi7FwYAIPUbVzpzWZqd
kwx0gpJctSoM+aVOLK8zuF3SPEbDnmzgCR0Uh5h5frIn89LORUW5FP7IuwOnvdwrXpIPmbDVu509
5RrD4s/eoki46Lo6J+mjQ9Dlkg5N1pO8qhosyE1yoflwV0hcD8KI0XdiEMGJdReb+gQ6tmqT1srk
t5ep9as0kzWBQSojdkIKSsPbR7vDUKM01AXQd6BPDBA3b5xJAzQ2m/Z0etP4zCWf9MZerFa9xNb4
Um8plEPGaBxIE9nQQ4KP5dqjZ6SOLiUKDHMrm7UeA2IqqrcFLLG9rKz3C56rCOKxT6fiI5xrKFTJ
iF0IK/qStXaF7mQi11wxvs+3bRydsQsBwv3O1dFP737DxxV8szgzVRRApotdy4OnH/jBS+sj2UwV
RSZo/unBOX4uwP6klo0FRLgwsY+IZ0h/Y8WAkjnGWVEPlR80OUHTOZ8/CHJm7+0Zem4wxlTBWboP
AeK6um71u7rzAnc3sw/CEfq4Rcrodh9G8JDSC2b1tWk/vPyNpntmNckSDIB0bJ0cBIlEK1aXJV/X
PnYS6+gIIYPG7UGXnTajPWLpZNCZyafRxPy+QJvS++upOkJg0uTVKAAvMh47NJfsALGoxg5po/5x
A2F+jrFkgaMsqt4atUCY+EONpAqfiRl8PP/J9Q+uXKQJ8kIEa1ghF1Z3bQ9inIos9BTw1h3x3SVU
pIFilYw5QxXYpBPBOYsmQEPfijwdO3GHGyGUD4kJzklLFd/GL1jn+b3dLnFMgFLZSH18PGwOeYRL
7SpPR90cj6SknBk1lr6bE92tmVYYp3gox7UNWEDUm8hJjnNRRk836zI9YZ+1yxGI+AT6+hiax30t
MsLugAXqV3MjnLQT0yu+rdQiHmzgmWZW5wdsr2Rf0GYBp8Y5dGSHSFa2dLiPHHIMTAqjQPCKluRM
xxyk6FAu7eKK7QAzfhscq9ckhCwYvCbAbFLf0/ksnVmVTGYgV0Zq3CnjSJPRstIul/83lZ+gpPf0
7i0Rh9HlJVjYaSd2B8vt87R43z/CSNlFKG/gqwuyWaNm88WMU/uRVv96qUSOQ/BmBbB0a0oeSRkV
27ai6YlicqZVoBsh8Ez8NgOQhTJISlIPnYPqniFVMU9zD7+5aCIfe3V4z5wIpNpZVzCE5pm/J1A6
QFZMZl0zPqTeTmivC3SzysTwQzxamQxUlP4KaAQh73rY9PHqRbM60S+71WjaSUdirho9q40R/QBq
zM2Fm00g1vkBGDQ/Cv+oK140l3X/sTc6n4d3+2HKU1ieKRhha2s6em38sb3qQmwwIN91aV8vhSvG
fQ95dRWuYwThT+mI2Y7qEmdzVofI070QJst1VeqWI4D9JMJ8AXnur2ZFwPQ/24BNpgJ+V48A6KiA
eRMiE8W4ss38GuhizTJqusIg1qrgirwFK62Oq+18QsORfW0CZht9mqRzrgM5z/v1lQsDRU9X6aAy
WEV0GdBNsQFqEyRe16H+FQoXhwberVrCQxzCobibg2ojrLgXN9b8yTnzpHmC5POgKFbeS5+573Bz
L2CkNXTo2MJlpZgdNTzRS1293eNzuir9HQIyGg2MSB0umTdXkgdnHHH12N0r/5JA/OiK0kAHyM/f
UNvR9ZvmG++vkHlQHqyv/fHBRfOVgaLfmRzi7HgXoHaopv3qA/g5SFgWcZTbMhKT6uCKI7TxthbH
b1dmNk94qxW/r/M6nexIyNDVKsyptloxiTZr8JvttjMiAbXGqRrrzogMWB+vw9qks7jBCEKkfw3X
vg7xi29tO8Pz+oq3aOYrIc4bHNajfZ0/mBIQj9KO0u6aFzFdEuE85lFxFIWhQtlNzupwZxYwICP/
028cWojuMHLQr5RVEcbRWUTPxtvA/OEiB+4nhe5MaSZyf4zZQuZXWDYdRxMohB54J4L8J3CdfCEI
kH2dEVKxCc4G8hUx60tG6sg6lxrD5TPp9GmPwzF7kYlZ9l+gOAQXLa/MVaqD0/yRUKOSOeY02h4X
dxhDh+nZTNyvg6FDrDPaSSVeyfklj/xTKA1jzrBH21G3nhPJD21gbihxX7RURR3zwKq6zjWgnCIx
ZHTy33biyES8Be0Si2KcRoc20WxDao86gPrfmpWez42ooX6xp+0aDeAchlZP+6WcxZhOKc/WKmEk
GZj7G7D63yD7JyCX8RNtmr9sZKcqj8T1A3wbsIZmlnnYSj7pO/E14sJuzaki9Aek2zB/ZGTFyXsn
T3OmXJuJRWD7W4DOIzjCASq5DfAgJUWaanyjWDXjcAoJnvS3BQmp+tnwvoUwN335yamNiI8wX3Ft
osmw34tuusUGMTl362jVLX66FWz6P9AWEeyIvmjjA1hlnPV4iWW5Yu2XjbA0A8XGr+d9ZO6ysnNF
vc9hWhsMgmnGFJ1JOcRza63E3hXSSiipUq7FmgjuNzA035AbWNrh/BkEtE2c+w5MoEND/2dNsXlH
fXtUAXPgmS8lDRYn4Mrrwi+tEAEcjEctl4AY0ugHqa7ER9vXJKjWMgmT8NYqgfAc7bjxIEk/4Uba
z0aliaRjUkUCCdZhDLakFJ0Rd756H244wo7qMFxJayWBVljyeJWzcPN3ekwJG9K56E9fH+bYJJdB
90ImTjK1hYfO+YKUInykJKFVzP+7inWG5XmispyOhIVXy3Gv2FJUtOtYC3/hjMqnRjPuBZx6DlBy
CNYCS3gsDQt6CwjsGC9SxhoLEDh+osbhZoMHGYZpBSAt8pMVPixvJ8D9OKHa+MnF+rRJrrwzDBP8
BsQ5Wk92estjLG+xI3Usr19yrCj2UOGyOZ3pULkBMHhtaEjVJjtH9V6/1EICuYOyH288egcr11gp
m2nfBmq67W0VbJ/PE3yFnbgJppWZHun+x+vsCGo/tHes+iP8jAu7XKzVHHP7+nlbQPbpr2nV7ZnK
T1PfzTXhSYloEjz4wghwMFx4gV3C3wbNB7HoOcI9ldOrF88ps9HhHD1spz40jIhrOj4VA018dhaW
mCH9xjj+TQl/iGgMoOe9CPe0V+dX0FXIiLWNcq4uTpzydSa4XtxG+A905pakYqDNtDOGj8Khv1be
agpgBY+fTiZtO5OVYBpaCzPZgQDsMsI+A6pIoJExArGoVMZ9SuF52TXeVXfG9nEaccKVsnkxfw2R
JKEbNr/MZ+0p1z2T5YEQdnKie0KrqpYjsIqkOv0aAXYxYzfZYK6fxB6jHYC9rpYNnvgphfbqC39j
dH6v9GKg9v66BJ9XzChqH2p1UXC9fJf6zXVv+KKegXO7WWfmIFd1UqIQ0AnkS6mvsm+wQltP3hI9
rGfsa/nVdZ+rz/pyGCej10x1K1nXCSDxlUxd6OQz39jmW2kg4Loog6upjt/NuE9c6YYzJiA8Ul/W
OK78LY6RqErZ+XakQ/vsfVZ8e8rjzT7RxYuNpXeYMzMPIeZgO1+L3655JbbKLVvWAFpS0zwWUhDv
p/OEOwbVaJKM10bvN9J8/cbazoNdn3S+ejIrlPggW8cNz6FKMzyOyU0KrH7X+kkao488z4o3Kqv1
Gv5i1CC0yfzKX1rWPYCF0eocCzr9Xe0dI3KTEyjXTWtCTcQZA9SkmKnKoF+v8dw02i+xzHthJHd+
g41SlQbE57Yo4t1iks6mQRL2iCmacVUs+OBEopgRds+Hh4748N/eK9gKTx/cqRbA1hWSvWDqSE6M
A//vYF8xSQNI/isbmDdO28MkrxPiNxtxSJL+BjS28fiwhl1T5W5Pi9eOOCVSu/1Xc2vr9F/bsFyH
IyDsH7H8ZuD5Gl59aFITGzy/jg0JGnzdmFkC5AZTpx12t63ZZGpKVPIdiUZfej+7THRI5vr1Uq0B
N3Fro0DLU+VRvB42kXGzsRSJ5tQMCGFSDe4NOGbKDggPUdnJXSRjIE1E0iSmyLFWgCr9RQB83Vib
ZPdf4X4Qtz9Wfr0Q9Lqh/cqg+QrJi2XefbPaCRNy/eKBadfmfBNA/MSRYdoXsJsQtA9E0HdIiROs
a2QorbVMkzkdkgLWWSG83TNrDZVQD8tAqfbuzbNwnexyOFYq2AmQ8w0jfOfXcCmBol5dH5B9bsOz
kCDm5K1ZoUAJPuopeXr06tO2Uor2yEosbRInMLwrXrwWXEBA7CgMjXqqG2TKOCmiDcBhHkFJFCe0
wBRBGSM1gq7XqXiz4Z4izTac2VzlcNhZ/fedovWoezI6yqjacwk/zEcT7ceBEwSABZj9EB0uJpEF
L66cerZUMNKTzECGpyYaoTLn1nat45jDCBskyxyjWZJ4FR5b2gen/YQbmr71j3pDmN1BbN9uni3n
Dcfgx52V3jB/N2miDuvLDFzhHJiNMZd3LXZ25170hKkZX3wNahlbyp+eW9eXtkLVEW9/SEp5VcbE
+0WqZMlY0t8OlQaqR8Po5/a94GquBLarCdjvF2IADwhJOMKwqS4wtVTpyWxijiSKIl1xQDiWg0CW
04AhjLP8/hLDRZV60V9Pfxog9Ni6Hm5yq6ASoMDvmdPSi0MSI+QsgM4th811vCreXFPds4XIj0uW
timLUyepNcLvNbZALX4nd1TkxEa9+Yak76zqU3mh2fuBzrdHtrexG1x/uusZbHofI5vR1TCzN4vi
feWVeeu5/xg4BucCE2MJs83Dnf813Zuh+p36dXLm4STsKfByBAfbeN9f8iAPV3LFRbbwBYxyyfh4
mjjYfWCN2erD42hmHG+I4Ovx2n8bBYZeSDY0E0aHPmuGgzIK+C22ewhbfFSCLeZDHlDWyTd0aB4d
uxMeViCQd2MYBgWxfRcNt+JLseHJAIK7pPfqdg7q/r1DzLHKvrSMrhF4yi5SdG6CusYJBs1+CuSZ
zmI0Oidka/PzMgk+NZgtbDjrbjxN+3wAwGrdEFm8QXEyfOM4l9v5ErfHSB2y93BhdJecd9XcWuhQ
kK4hhTq+5EuF02CGQ6mq6dIqTZl9+WxwmUR++X6jJ1CYAIgSK8QHpG3Zk9PIhhIZHMdcmNPEvTLY
bdD3GDgCgHYdQnTaFIphWaJYWYtwPA45BiL8KHqpfLzASts2/ykLEJjQY6mcs4FATqnv62vS/GkO
7q6LDj/TT0SfxMuJWF9jeLXOE8RIAjd+wZQiCUjs/i1Q4dvTrkCRtcV1WQ+GBkV8+UY/0hEVNvub
CFM4wAh5meJQI1y9/ecKW6os7bsT+BSiUALHxlmjjxQABoP0uGG9mXDSpqPNEW/dTD38smLFJXoy
rSXu0cXN9Nv/WmfxwPEDAgD0AM3hRsN2CtWPCx4PeVvX32IS0XkTcbSao5XVwklDKb1oyNOm9jmU
/Kc8YByxzRf8gPmKlzbREQfeqT1IZEkGKPqUS/M2c8K02C0id8Cd0kNgMZh+MZ2S+8zzCkHhu6OE
UvK0WIagKyuLmaQGri5mkBsPsnzwVQeKwMQFtkM+XeQ8NWTd5+1cRD7oRym+E/IiK3cH8mC734G/
inmuBeTugKuo1tz+A0IsUh4gZPgqUj4K4AwMWBXHfeXwWsTgsu5ujiwLS+toHSjmowI8EMvMHfA2
E/GR07hoRNVFY68YNYnuVAgM3fj14XdRYPbo0wLgLvopAcTlmVo5jBW8be3GiVyAHSkDI8Mw8yKH
LX/dehH/5p9H6LZnLXJQpwFL17m5UfOWzuC/ieKOWKJKX7jzZ7MTCK/CHkIHrMPlw3kFw92aXGEv
awsyGm0IzMibH7TSzxpFm0F3Jb9Lb18ofIChm5IQqDFFe/TtNAeZEajHxARtYFRRCz3zte7tDdzp
IAhLrUTYchuZC1PHOwBLyLAQhLsZC4ZnPMBybKJVacVIP2C14dTaehuqnIumS5Hl72BHcLuAW1E3
B4TnWnzyj1h97zkb1Kal3Q68FdfAQqa+wUbN9lFYYBvNB0fDwIyjAu+p7gLPmCLc0h13Tmd9OSCc
qZKah+dexz9u/W+3c03wpSlP2WPNVnaJA2rSbsISZZM4b3oOTLVnmPtFjDStIk56zvmmoWyUqAyK
A1WZMMzgi2zdlkNZ8K82fkPM6PoGgRuKI4hk6xPfG8ES/z9iZ7dUMiEyoMssLiVHTxMLKKjm/oUi
Y3+c6IHifJ2jgZfPVbjo2o9v5ooTHOmg64yVp2l5PBnw/JixupivfAG6HiMPapGy0bh1QCOBtpzp
O7c1/grEoPFwUZ5Pl84P/iMd0D/jwiyynu0gAqA6175XuF5i00evvsLWVXSrNjRxl1NqwOjpKa0b
UKfVNtRrTSDXgmKHDbnEDAAtHQ4MV84X82SUxbN06rfBTXy404Yg96bcAWbuWPwNFXndqBOxyV7e
ez+tfzkQzz216p2n5n2BNKlIF4lllhN4hl5qUGFFWa1wqzs6XGsJwfiNxKxKBA+rAtc8xGbBt3N3
ReRTh3F39ojRNdtkT2LujdfmxOu+Tvy4Y2/aJBvi3ZvsXMfzgCkvZsggPFWs4JdSZgwi7PFZMuru
pSyvUZv7YR8HK56sUfFc8aop6OF4AG5AJjdt/BWbS4GIHRewo34ZpGrurEACaVJmLgZ8b4KdVsTB
zsI9ivXIrlkpmDzWtg8Qw14gbSEM4Hrjoks5XVBB57xKXIPLdLKoy8gSeO+mEPaYOrx5sSZxNuSS
lCalDHlrGbaqPCzwlcRJzZcT5cs7dP47tnJdYP65RZXF7wdUexYCFqMpLDjz5om6VrYMAMY+7P18
nra3QXQthM87Zui1S8nZmzBV/3EO5deH8OibvWiQBmuBl8lsAZC+74ySl5+hrWyZDWLJLPywGWr4
NFMbttLuuWcGST1qeayhr3gNrreZxcU6/CvMLZvb61vMNNBh6Uocipc9OITQVkcywyy4g1mO5w9h
SuisppFZ+7L/ixMB3W61EhlhUhBYiS6iMzGl/FlrqTEMpZ/V3oHQjvqiqTS7zX3F62BQxOm3+Keh
1YjPwbSE5ZCsXxVMhOQEnKt8HNhlZfNJQ3SM2AEmwUeRjgaIjaI7sUZzMrp/yrN/Wz7G8sBkZ6cS
Eqrx9dsAlikt+45nZLIJuOvfbnUGUZIMT6a2vF9AIaP6bS3Qj7lmfD2ez/nQRjJsV3T2Y6KvY8kH
Ysak05XvgRW0mDtEmqP9bsBZ9cpIC3Pd5PERc+RTBP5Iscowoa27h+fd0z6g2ll3kaWh64fMi3O5
xb7Eyb2GYIrmW/8gUBV4vMIWXJTCn8RU5SV6jt5K/PoBeMStgl9j4j5nrM3IYUK6Lwbq/J1ZPInv
jnZ/CeJH8t/EdEucbkZHiot/sip8IPN6SMKrfZowgcUKRT3hnAWdVCMmxhOhmkekZnIuMDouyoA5
LLeXdF54DPgrHBiyZspc1KqbTDEeQYijw2uhUkB3OtYOLD7V0aIxICi5On1hWYFBD0pQEfPkTdVe
YhUum7HQWzaIxhw+By962hF65aIcJ313ev494qm8HY8zXUSc4YoEcGwm+83q8G7qJoGEoI3MYH4A
t3q168oMyzdCR6y47TaF+DqmS816ABiTM6fL2tFfEDQGCe6/4HoZUNfMHFAWVMFW71uaH5l9Ge+p
bsNiofTNDK8O7IKvoYyz12GR81KNGpvrRLAjCGTS2fDV4BvcShwfwdWNe3lTwBz0L+3N6TUcMPVe
eSgNVGMH84GibSiDGPDZjT5bPO8zRK/hDK7lqD63hmkUSpTX0ZOl/E2rVZ50cd/SuqStr7bfXu4e
fGVn6Uyjabv/wcjU8EgsM944wPvQTsLw8XBHAuw8v2oUnYh3IlZw+cu+IK56b8RKZHBVAvEt0ONN
laMTXdZLmYwbLgvD1nFWXZbJOhtxOPiB4q5PkWjJdwshMThNufB3Xzf+W0cWA3aUMdArROa9fGEw
nb8ItF9mJ/la9JrwdtaQNrKrf5kMXJ+F+tDUDzqI/eukfXHw4+bc+cZf/cwC+N8u4eW1RcrtSZV5
OMburTPuqURRZkb5uOAJlpa504vUDvMrKGCvT4ZedqOuFfOvTAThqxD10cixDg2OPMzU+N/K2ZfO
mcC+juEQLXFFI5dz2gnGQ7054o3TiAXWKN7Npkni0s+k6Rakva2b+FRm7YQzooXGNEjiuDSAi9wQ
4BZcryY1lxyS3uBESzXDVQGuX93fGM/st8DljG1bO11Y5tqvTMhaWQu5svZHuSWJHXaH0G0ZuO4x
WRbmaFfD5KAUlp10lYevH0VLs45hN+7DeCgcV5jwyTjpyqjLgv2Gy17ujbw4WrVM8Kix+8eGSsll
zj+IJ81hLgbCf7W4T1/YQNkHStd6pHNsDx/iMf1xVGJAXfO4WVJtVb1S1eCBw7FLWVoHLbC15qFe
Np29CGEmdWrYJPjbSVBU4VIUfb5qBDPSQTxADrDNd4vA8O0BGSAfQVZ8OZa2qxU8mKC33mn2zu7u
bKnDiMXcbdAENMwgCPY0M8BdgiyP7skLlMkLE74SADY+iNSG8Eh09HC6rd9KEpSC0mb7wp2d+qHF
e0MF0tZhxubGO1ext2Mn8wJaGLPV7bmB3ei5+Hgw3KWM2W3RIU+7Qgzo3re2DTsSADLwUzLFMuF3
q2mQTDgAylXEBJ1/R39YW9iAQaNbjdJZvqe5eYm22Z+c5FF5p4ihExOcrA7buUF4hODc4ozdb/vy
FZxhEKJMzVfg0nlL8ralYveHIMJqP0X7nWbDYZBi1UH9p1unhpM4bgMpU5CdaLf7UjplkfUk2SR1
y27R7IvQNbwQHROKrCxFiB2AkDbMrnnltSSxgrJRSEnyCVn8UeF6sF71dpoGrWkDrZsFJg35qH3J
JmA5Zul7C66YPZhrHkDI6+Hqnv+akHNnbkRmXi+sPjXxgVYxc6pEYRw9uGe0D1p4LvmUvyPj98/O
XbbI5zfIHxafe/FLTtvLgGtgLQ9717cD8g9p8PZvNKoCp+0SUA4DZTatLeBEJrbAXfk8ivwNG/U7
NiRLldWIpkCrw7fueV5K3TtpL2KpCm73CMIC8q7M8z9CC4AwX6zRCObW13fl2XEY4p9o99h98e7g
ijQtIs3N/i/86x2UskgrMKgMoOzJQ9FDPgkyZB47PKNnlIcRnUANJ8JUE6rU3w9pBmmUSbFv+LDd
cnJG4dooFAJ/lz0u6b3Yv87LMixqbZ2J8M/1bIO6Ymg+sT/BQmduxDfQ2tb1YUn57par6EPL0czV
H/vMEkjjmCRP6JMFoJYs71kN110jGzpLT1bCEc+9oTIsCIt9VY/+n/5G6fy+Ebf7Eg5kRoS+jAZW
9Y+7smk9iktdihZYSarebMzclK8/JbN7B2jfRmOFqwxd4/IUwKX/GVU28WzoeqqKrK2elwEns0wj
86SwA6ZCwtuNvws4Iff0GksBxGK01AEggG8YJ8jofLu0S5OPkBc1gx/sSQk+dUt+dVIFNqsRiyx4
FVZUYrzi/V/M6Bz2mXgsc9ESI63Aym/CgyieC7//eFq3Oh4jGJa/CzJO7Yi47J4JMZqes/sQ2sbW
omJpcpDSLAdLHLYtQuqS8BOKdN8vWw6JHDUbN/xyCHTlsUm1bTN2z9iacsddgz+2oD9qg1H7z63l
3/XujixuXHvzlVfkuhc/Utsyaa8LXYZN2uJ22ty9xONUQS30dJy9laYlDciyOXxi76/e/9GlJr59
zJ91ch7K7HUc3V6d/o/CAasgiNW7J9/HbOBLMIWK+/3HnOg003agdSzCWXJnelIunMgzo62LDCNn
ba9KTghPIU61BFTiITOSrrQ+0oyTxOrztQdWTXF1lPdjPy85carTNjSdo1qzNasaBCntVDt3wlKg
+23PrkrgCzV6dWo71dlR5Yc9FYTpPscAAv2ozJr1OmN5ZVcujBkcUWPZR46nCGeGlJUdFbE4OTyX
/Xns/FxVM2rrkFQwAlUFoQ1VdMfA6qubiVahVnoYZIZX1BMaX+TPYyPTo7P234L6e7eBZS04h34C
S5PnXI1DSDloKlXJHVNkFT5bOubBwsx2m+svQt0D3phk/GjBpCXmUvYVfBFkcCRSjleVObuFHPc1
/K1UstRRCmqiT0qrRlh+Is7jqyZ3q/G1/1EUprpZTW0V9KiyXE7weiNj3XN38eZwbXVHmIfjprnH
B0RootM/FWySAjSlGbYWOFrnhWzHxcjm18Lr3ENDVjXmmUbmdqDfantqmW1aglPMPmGJ4L/sZiGF
6mvpt2DV6EKxIXfq4+LkKJN1aY9usCKhCu9kDIuPLC0AXA9OmXomxS3osIRM/IEpn3z2qIXEz+Ya
bQ0dR7KMQnnaeKThUBIAwJ325yDr1/HbXf8TbKm1ADSjl/DOg5j1dUzLCD+IeJ3PT7+U/g8QnUMU
qX0o0G8B9uIjLhlXuhGr3Lka0K9/TqPCc2JDZUUUfvbJI8HLBwc9bqfQnVviEbalECYhrwHSqu6b
NEjWtzFkl7VBjx7kjCJ4OUFI1E/6NxkJL36khjokjx0ttmdIsCaLSm4vLKmpk//+9yHfn8j/NYN1
2UMi/74EEFkjKNkQb3Ml857Zoc8Efzx9vEmscfGuA/WVHQUptjndsGg+jzuCp1NubMDOhKLyn+9s
tHhpXr3OZwYm9woEUgN8F3fGV4WAdXEL8TS0tw3DtGkQAEf1wikyjPGWbMPMooHt+VvmdFPviVcC
I+uHmislLhyCJ6/Qvm4y1au0I16604PquIV7OkWf6XC9u83xRRdAVwDUwQ90KXPFgo+MrcUW+Bq+
P1a60RJw1jPH3qA5eZ6UXxiNzbAbjrAJpNl3iiFWJv88iDgKaas5plfSPLbJZxSn4yJMrUqGGIg2
1MqepZ8rBFCyckkT3ge0GymV/EZa89QhEKkGZ3XWbYKOmH/0hI/qoWiagwECCFerKzqN1c9bKt+B
Hey2BqBQb3VxX/TWYKghKkQnp36JWNiM0yp6Rq5Q4atvnl/TzfpcJSPGCi+lZnfLdnqlzKESv2Ib
WVsXb3eVfxK7heREEvyBB2IRbIB4CyJcPAE7lAFy7Q1DNqYzLKSG1vfOqB1PkbiHGkePuWZ/gcBz
PHLyqldW17L+eRsdq87dI0xJee1B2wvabF9tE7nL5c3D+LND5GnHADavUerXOOq1vx95QPCJNtXf
Mk8gt0vLEZEoWb2G3qcAADDA3iUHTMyo2jpK7ixlrAiobCCL3g2ddQguTFA5GGbf/0xlPAPtEShE
e8AOAtEFFbc3TFkNu1R8HpRb1PEtjZn4fyy4tcBAcUpzQOjamE+qvu/Ds+4oKcLSSsb+pIcuTnnt
KTvx4ioznVZ/RYxzC+nrSgICj0Izw0ME/bE1VuQTzkzha2p/MbmHCluW3tzGym4RTCnNKNtVk64G
IcTuxGEBblos35+akgQyXshDLfmmQFl5r/z3QswvLztnOmqc8K3OngD2pBWHBiXvBivcKp3djnIN
mYBSpUieGzA128kcgZ1FPMn7hGkLzz+Jg4IEBjL4iH0j1bpm0meGVjRHq3LxTYaAb5NSZID9uwhl
t3dFvzwzP8KWHVxhjG46XR/ORTHCbE1aZG8LYDCXPA5ASxASS3EIiOM7Xx6CVb5XwaSqqxqywTp7
+r9ssm9wgTI0RBAkzApHC54V6ZnrJSTEwd5x/4it9U3vBSEcAXtQrVE6HlyPe9YZdkRIyKDbYT9W
P7vdvcgRc8nEiFbwMdl+vgrg/BPBU/VNP9nz0UKoOlAQ40O3yyqUiCRdhB5pfAWPrz23In4AmeQQ
J+mo4QtTBP594Mu6li2JRwRMOqsXdbjUxRQcZWfd6U934HOwAG0DS3EohU9Jc2N29kEsJndd2kx7
oCnxQsUYCRbOLN365bEhx9TfUc13GtiX/RvsqWw/YG7EaMxQMoeM8BAS1kNDoZrf27n0Nunlrmv3
usILIDDWHTIn99IFs8VvUOVlqX0yjIgGDVbe/UwvwAAWDyvenzFL5lT6CyuDGTGdmCQPi9HHGMIg
fejtcdvmjG2rk9RB484Jw0PPii1zJzz/DjOAiUFkBjxqIDSm9/CqTo9aVIC+6kBKLQybuBLtz1hm
YY1HzpUtrx2nvvEXsS2Wk833V9HHA+tS0xccuDjYnHu65uNFcy7hRm6lwgc9NtW3FUfCt6LELTsf
ILsKCacOI2Xur0qgfr2xf1YH0I9KfROCLUl7NPvyty69hwBts5beXJGvktpkxBgHUrhcUr3rNwHx
oFvrmNyI+23AaspX1WguKp1ynlelDtK24+HTFBCtBV/yOANKoS1l5MAcmrpxj5iEMDQGjl8ll4lO
TeG85nlFgK/AyIjBIUNeFDvwjn9GMIWW4/hoRRv/pmq2k1DaSf/qzVCA+LugxnuLYl+XcMeeT2bx
HaMfI+UGrQcCqtwQH5AQF4uqHPSZ8o6iEr5X7Z+tjY4HdeyhU8A7aZ0sGqh6Wl9/lM3HuGpZNNGe
y777dvGXu3Fv4CyXNbO1iLfbIsHbE89J8KctLmNLK1VMzVyE9H3aYqYeSz+cINK/GORVd3k3K+uT
+eKdtFZ6vus4UMXvfRIZamHKC00FUBhFvRhaNhzZBZ2FTe0CozjtZYfV7RsoOnOaz0HzATId+b6j
PpRo4w4G2R2alhA6J0ddsqY7hLDDLcubhmBp9Agss7/Eq70kSumNg/X4gHwGTD1kzbDtlktoB5tz
YsKcXPFuFrJOXNLlQKnjm78FRYcaxFHYyK+4/sDfAFLUW4C30hdHmKSQ4RVAnM72NZ6SMFkgW9u8
FBHT2tZ6iFq1DDbcufhtFXEv+YDHD9AilRDhU0Y4GRQzE+0r99QiLb4tSz+zIh0DZLFdgUkYlBk8
kOZJZZvmyq4K1Ds9yOH2rpJd1T7kG5p5Q26xjC3fUfEHR/Xxi2ZhQuEytLQeK7xJQTzHZkfjpFi2
tKgeIOCjujylIilfJzqFBcEnRi5xTbmye4AMwM4T7CK8nKtVfhX5XwMiHK/JFVhbCIpSTpEM1a7d
siydfYkbF/EpzTsjLAY/CN04RzNYn4TRjCm7iXv7VwxnJNG6YO6ONT4XxWCMJ34bTGoFrzgqumCd
RsMRQG7XLcnUcSfQtwvW5CDAiQscjx57Oc/sgjfQPF0Oq7NQDzVskKbtO8/Ia1anljyHNjKQAop7
CNM+KHJQd8qbrnvoHJY2nzhWdQP+bPH6OWXUA4UcJ8uWkXpPtJImdkxm6Nwj7vB8aICUqkUvxx5G
VNBkXB7Fap3dZIFPDY9paR0LO1nxrNJNy/0YI0hEVUv5/zD688ldaJRu9Hxkz+Ik8pUQ7HYjn7Hs
uyKwkhzt/qF3f9DnZdQbJAezlqs8HyAgiREsoDMTUNwg4cZ5/S+fJSPyDZojvP2X0o8J10dpJ99R
2sXzuzJqvyBFEGlKOQLBgWx/S1/p7r4jQPpH1NE6H3QDMRI3RMUX92TKPfr6mmm9ZsyHzkoVXEVv
I104gaR9+S6iAFzhjgRkYuuUklW/xwctEJILgyaSZ+Mb3cB5cT56SavX8jfHvsmcJod4hnmKDgeg
C+zB7WTU/l2ObUWvyQrsEd6yBsOpYg4VKjZUOJyUeMzJgBUbNztRyz0bHdqK/3AdYCn2AffwlHWV
B9jU4OgjoZhsaPKvj4vkiQWAiFz42iUJ/wOdzPQZGk5NKyiGEbBiZLgBu0yJkza/JIr101Z0afHp
gikcQqwjM9b0UX4wx2UlowpHECgagtEhQyorMkyIIGJHfkvGMXGLvhJIKxtfxN42HyqNqYCy8Vus
1aSkCjj+VmjSfSbuDX2Rescg4z9L8pjyqOA1whg8OCUj5ETaqaiWUUd3aj9sc2PkRz/x0m5F4Dbq
IuPk5u6QL+qdxP/NuOnMLSJaVBcaZNRG8Hh7swOAhFf9Se+byv3Ecb4ihbr0nlWJPHYA/WPCXguU
I9cyoGW9VJJTVGczXimxsRyDwWdByT2E6qdP/nvlyu8/vGAZ5NoY0A3Zm9wFPFzClNk/3slPYQ0Z
4f4wj6RicL185sP4irchFrFrJ15D9WXocXXmU5vfIG4xbHQql+PqcxBiNLb+H8aMv1G8vXA/xSCA
ZACSZ7Dn7BpotmudniBLZOAz+Zwj+kYknXoDpLKRm4nYQ5OPmajlM4gIy8a+qpDMTjz6MUbDcw+y
OpWOO5LmX0ch8YSCsE98Y0RR3N3aX858A5BiTsPS4hcm+Zm7jHoUrg6nhYed62e5TU/bkAwPzB/K
BDC5q7mlheHnPFPorQseRCBURpFsjzZAsV+Ss6Z26zkhwz8F/+TrbcvOpE2hK3Z1bxt/XASLPE9O
Z9dUET6jjLyHIgKhsFT6mzxuVUOeKuQCCyIGEFyjlQa1x3hRVELK737yeESeWLfoNfLU+ZxeGUT0
qPsNfy9tpFR6PLaQEK5BvqH1zIq27GO2kpHB67TMJb1clbefVmrXiuKu50hrFTxLEGqok1YH1s3l
ncPZy3nLL1ijnjM3S9iwEmJwbaGSIc6edEMMlnDqZURhEzW26Um9zHyd2QwejRU1bTRKt1KHrYkN
NWZkXxmSwIowTMknt+LaGmami+kbJrcVr5PkQuYHcBCKHc3led66XaQNtLtnyNxqorFIvck3uaen
d7V3nPXvjghB4JSasYJZ5eSBhI7VEZQlNsfvyWlBpxV10ddqR2E8k22adwCrAv5b8SbFYajDVTak
7RbLEK0Tr7LPn0hfr9q0edDBZ6dxpvqaL80h60iEp3OeXOogBmY88IbW0zomMlTOUzBtA/UFYWuI
giVRY7OPozQY48QmmowgZtn/2ArFBvYTd636CE3L4A/3bXlHl/g90lhInZRbdRAyDHyGxWMHHI3+
l9zA/X3VaRUyoG5ppv5pbw7n9A4Mv+NX4lqCKTvRnVZrVPI2sy+80teUqVrkr23QyGXzi/3dl/rE
OOHw39cl/2yCWjyubYjHX8fkKCIOCH1+0QgQXgxqwz6b//ecNOYKqbr9ehNsZo8K07pZUzZPONAT
nrnB43ncik80DBeEiKZIrexN1zXyAZbi/nsps8UQrdVdmgtcJS/wzZjxbuL0ok2Oo2jFiMuY40N7
A5GQ8MWjQx2fZHnSdgM8H66ugjB/NzWyO49oxs+WyEEoxrJAK+7qSl6ppGtjlT2nvXx9pnyjacMj
6aWbUfp65yYtED1YglSkRyunYZ8T26cx0Ar3Hg+GXn04KKiSwp8Jsv+BXaOMTJ2PneJI+DbFoLry
7zBRpFkZkcggEAV2+cWnC0Wb1D06mrR6CBVJTodeglxCFzHTpEcbfCugFw7tani344KouhPFXO4K
sLkDqwBua9VLVoEYBEXr8cgWjlmZSwwcwx6cOqNwU4ADb+qvdZpDp6dpuVuaVAywhbpfPdgemPsK
0N38ODCert4B4K33I+iWQ7OBMAkEcP8y3EleI6F0mLIbJRqcW/7els5mewVmGcS/zl6hEgzyUYAY
fM38ZwdRaoC+Avt1IC3qpfYtPLKJudn34rK78/63CwyZJLnA1WFDzA3WZZJTtNoftf6ZsNiu2VAb
6YJx4A53pq/b6uMmOtoCdiqGX5DAXFgNUB5JvhtRk4HY3m49G/5XWSPpBmf1Un6U2+x4AC/dpsgX
m/ZXX1Wc88nhTkb/fdxlFc0SExbiSbX35jee8twXTN7Nhs2RDH6jDxoAZAD0GRUiQ7OexUjP8ViC
5cDh2B85l29A4YPPxMMC3J0ygiCmVkyAYpNhezvf/jp3pNC+VbhqXxuqHaMtDzAo+CaY9K7TMTlo
Jr/JDm11wWHrtI16ItdeZEmhfFWOkkh4+AM5mu80A6n3s+c3Ea+m0H7HCyYYlkTqXj5AgXkSbeAj
4CszKhZWFVU6zv+8BKJkcVs8w80nj9sUCmSH+CVWwMkUTDWijDJV7lCEF+NdcEruP1Dr+ANBLftZ
dGoG2skR9BwxdGdvZ5InwxuFIgMSplbI7SSMxul1X4E0wiSkDr1K7WCY7Kjfb8WseJ8CWwOjIaBj
XsmGTVQdgMtQtWvNYhL29L6h7W5l6zJ22XmX9LKxl+l/eAjtuzguc94X7mSq3+tn2iZEKoXMxIZT
/5XAhyOwtOsJuL6Ys1q9xEqZqNbfVzeGK4TWGXiwrPKCVcslNpF5s+FIX0D0cZhJVtVnK1/CXCTG
UYCTTndEsK+mWGjpnm0O7mGflr2BDGOEzCBjJI1vVhPtbgUYU0aKuI7ae/qmGSgy2mexXRTtMWjl
9lmI0Zz9Qo9Ld2uWjdFN2CA0K1VcFXdukq/x84V0m6UDOULUOPbR1O+P8D70j3EU/2jVblkABtF9
yEHhcAuARwbHWvEKssT/rEzZUISNfWC04YnmVabZplNiwtj3ThadwsFhxKw6Ko51hqvLZonimnVj
T7lZdch9ynnzj3CjMoyf0H7aWyhpRReB1b0w+Mw0beYwYHktmqy3E58sEbqS56cDvHbbU9i2xdyT
8j5SQW5RNHoNsIU1ECxCfRWmjrcAQwOpTD5ynQTaPEgZI3wY49LzNxKVfKtfZ7SM1RRUugCnVYcE
LfxL8vokAX7KSOgtgEMw4FlJzM/MOmj1DXzHNBgCXq7Z7hyTlNEHVUzRssInq+oXX9TZw10iotYv
mdJ6CnPY3bcrAAj9dcX3BdjvUACPrFYcHeGGbeg/R2oyKL1NgeJs+0F2lRlu6rnXyyOH9pY3Z3V7
Rx4Xj0huK4QWhxsSnM8KIwm9Z37OUxBFNc15DWEqgkxvYQ9djlTRmkdoyHD3XFf7GdF1Yy8umc5i
Gy5BMJ3nrbbd9LeUFiEXcvqAqN6cCAvXgk8lNfuIEGNTFFVgvTWqROReITKRuDR+dxMP0AyLMwAr
27RieGPhmhEBGlvCgp4qn8EqTkrxWxM1bG5Hm3d/yOmJ10AyPhW1cQyJlczW1BLinAxQuk4BEG0A
tn2bCagJAubzYvRtPJc9icjMd251VHPx+2yWchAe9VHFXhvD8mU7JUxxaAlwrMMK6LHdXDP2aoL/
VH0K/mVcULPTbDFZs4EwzWBGEKauonFsxMnU8cd0yWA+Fl+ogBhIX4qMGDzOm7O2WuFtVXLaU6h3
5k9cGC+ujwhj5v6vBnIcIZBhe5fTo1EAfzt8sqZ2CsWH1Dc2/FCp/lUFFS+cHVQV3YZ59MhEJlFE
TQcEXGV32W2bU1U92mFc9C1qaPkqMxLrYV3qtq9yvAq+nd0Uo+yiGdoeGXarFjVTdXEcV7fo2gYg
YyUdblTenAQjobqHFW1VMHvL5XZDbRf0qIe410pWqF1TDYAXksgjUbiwiFHyT2xwOWeQ80mQGFTP
vPsDNdNUhhbItu3QYrTgwHySTFfpXMVPpquwA8xoFvT6AYu5QvA2Cp0vLzhv5BmQQDocdoVWNMP9
dxQS0CVrUvfX0AlFseGYwYL3bokyOoO0JTPetcTRKD/kjWQqluUH8E2pEokkh/ac/HZdq6so3Arj
YIPyiwJDMrTTZA+kAcraS4pt2Uu1uOWevknAhl4PGCHCpj8NWfJxtJl6IQLkN7O2AG7nOYZMc579
1iKkUnzULwyReOusC5wf3/e0k2YYhjlpfmEtXRjVbcxS2nRSzAQl87y37YBUZ2byx7frp3vkg72h
Q/8DdTz4ePmKZqXLn1gfMpAF7guk8G182fK/5sg5lwfeg5s6x5QqagZQ/9OMwi22/wtngmArSHLr
WNq90Lwv72tXhj709PRb7n+kilkdNaKp999XVux8Yho9SbabDxUbvPBuBWfDEpYHiULsihD1jqyJ
VNolmKFMZBqOXleXo2S+17NxZETQ4rjSdGG/ugrKXadcjvEddH0rjP/B4ZqkUDm9t1Z3y3Ob69iQ
4mfzVR5j9Wt+tqNe+gb20KlhDbUu5dFm+sYV5cby6uz2lPAouJ7EMp2I3/eNSQlsCIkmz6aVhgA+
VXDwf0Lr6d3ncv4cCUvm8iLNBMmQd4WkVk2cshou+EB6NUmR5TsZqEVd4+xrgM7SbABHKIicGZop
IqdHdfeBRHVrApCkRFMN9dAMDydVisOiyc9IuHVW9KxMFFkW/D+5a36Jl96fNA+sj3gwH6cErNTZ
pJSu/u2/fWwobSX3MIicOLFSxV9C67uVE0DTjchJagG6hzBK0ZPZBEVCBDr3DrsK15YXTi8F+gPs
AAi/Mx9rq/gRHWrydZpubjtYwxAcCB7VFpqornURykd6FbXJ8jQI7uuDeRF22AMA5VgV5G0RCkAy
7ep8ak5ao4WDEuq6dLO/6xKPItoNckBaxjZ/xFT82JijMyo4jGC6csTUxBHAbug2Wj/m1KzRUllj
GPZ2maEUHhY4sxNAc/Xl3ay+Qb6kBbSqLw+/59IdQ2pit3Kmo01EcaRdgKwrOmmZJhLoJQsNcs9i
STyjK1MLzpP0+GWhNTCKLd34/kJiPXWdpWTdbKgMkZhI7pEVi4kaFjDD8obogzdZAPZVaUMy+6wf
l6ls5yNyAJgJ+lZHNuGOmoH+/2W8TTaNsbJi0M0ECIeVl0IHt6F8MHdcCna0+ovjCh0FHtDRR8UH
dB4DZ1exv51HSA84OjUGf9BppG8oRJbv63RRu7LayfBMnT9Ib33dR1D76KGIO6OBIPc6+uX3VAq9
BE9Q7BYChIr8/6jj04S/7xXEt20MdqY+V1zFHeY+flPhIfgiEhbpUnxe6hzYH4tdCyMaPMK37Mm0
AxIAtd365Lv+LKSF4KxyrQsoqW68Uuhyw4IAvoQMD73h1OkfoCl81DxWkOOPUpStHEw2BXnqYCah
QyWaYaSQFHUSso7Gg7MDHQxJ7Ur3mFtso0VSzsdo0s37Z/m2LEtOuz1uqK/uC2DfpVGxeG63FYdI
CBbwB49YFj9RWIhYQLQ2aaCcBRSDoLGNuXVho/wQ6tLcexkSCLLl59A6k0/av+8IPxnrBNxVyhW6
dbtZeERtcyq3bD8oBpA/hZ7G61XA84ne1+RemNG0tBqk+2SGM8NnfvWp0rZFowgBDcf/4p5Kttec
6Ixx9sOx/oYvIbPYRCpdYlvMRYM4+oeYjGs6bQ9Ss2JQJjxjzb5hcCJ7LvsTxeCrjAWx7qBgHYoD
Tajbb5PyP/eXyDhUsP3uV7257Mfmbs96sbC+nf0Caj1VpZPcVRxzOh/M7cj9Z9lPAcxjFqLHHsN5
A6Z1J86Dd/qeo5nJ3CQlDHbL7MkMo2iNDtoZQaUBauPTa3y/Q98oRnxaLZ8VEwoLS7UBjc9/4f26
UzOQ1XSc+NPrzAysDFKMinxFV4tYAZpJ6ijW6nBFdhdWahljXlVLyFHhbIfv2nqSdemw9zEk2RV5
sY+wnTPx2xoVQBJnArawOS2Xt3UM5PQKG6o4l7D04nO2VLqq9s3LPYA9eIKFRsk1+haJ74I0Nw9s
ygUJWpaoQOmqj246CB6sz+1kNa4F5XOSaJBm2vwwKVaugs5kWI7BkBAlQiMOnaRYWYP1jgauD8iH
Uett8OQPZVfV35tAjGDEnUmZp+WjjjYcfbTxNmjv+HNTVgDE0g4mnRmmoG1b1JYLHcbBH/WULjjs
9cyxg5oYug32osx6SVExTIfeiCr2OrksRVNQSIlreKxdXqetrGrfvQ3NT2V4bCh0KrBsBAQDtdZd
p1F6+ZKyFhEmb9sKuFDobcK9RjfD/AL/ApgIQWSidWIorGWGJk9ulMNs9vn+3VBPEnEO44OM7fwT
hfNiMe/nI0ipTEBuTcy6o+HYBc+c6cydvih2mQRtbG6AuCpsbRPAgqbwM6wDOeTYDos4heBBR3Cu
q5UPvJ+Q1TE7+vGP0ZlFnhmQHrFlYdFrf+8vLgBnqevWYBuUWfcE9AM8p8YxXuYRK9Zqob1NHdck
4pdhU7ptClNIZZbWE1i2GK5nqm3LabJNanwiwpCCubO697zQbFn20uBpD9sfAkITNspKplYEY1to
uit6Rz+TgLiKFPT5Mm4eEZR90mwyu6PsA3+nSxTPPfi4F8sE+Si+lj/IOptIam8aLPsI9uEiV3lI
B0mE5l2Alx7H4KmypsUOH8M8e0j79kCA/stE0OajagEIS8wr5EN/op5OW3Z/zH4UxjHHS0Ub1P98
d4RVr8tRcBMZajdShr+ezuwd3iaN/mqw9/dFP+D917rIMguEBQb40DdEhd5gLPK5MmzCKIoc3N/6
XvAilgwHkE67EKcL33x/SsgM1rB5vmKFqbpsB0+seJL/2AQ5oB8PmnCYj6u+M9lKNKKkScUTkh+A
Iq0pVB/o2tidF9hMc9Rnz4A6f0V9jURDlL63KKrEcUknsPnarLCjEiMsZbn+j8X5kfMJz1baee14
v3TAzqOy3+4zCmHDR6gpUVghUzusOFVW7KDUlX8KlVY7SX0FtkEkgs+q2cP8xL4/AkBffFDiABja
V3EYOR5JU4hv+V4L72nfxvzhMDQwg2SrpeirHjIFoCsRB+7LhpDGMBi9v44IljE+LOlWkPbMccGo
iDBDZRf/Cmk03c2255DBk16ye72YXcWacsnHCETEemR27igS0yHtkD6sDTm7jBWvo9wrJ9Dt2K5H
S3w1L68BNqEuovp2rAFIllt/iPF/tnCd1ZqDA0YxdtumA5VSWpvODgBFXm8uC3LbS5+EF731fyOf
mfWMNdLut2vqRd9/hVrJQ6+Y4or9c7SAGn7L6oBgy6lpxkPagCZNWU8KTFqBHhec4nTrW9oTTb7Y
BjP4LQey47QF8zaJ6necn+WuKNj5yRix/7dkPcXrS0XrCkMuAD7At3J0lN1WfFxnNn5zSxSpe2NN
OcT5h7BlDKcAf1nHBNZ5nFjBuHlfk7tfxBvpSNc/Qes4ILd33IC1bxsSdKqd516r4tjahnM/WU6n
Xby/Ls5xuJmDE641bP/uegDjrMSvCpBjaIjP3FsbOS40vCEtlVMJaY4nK48rUn8XVYk7TmCQr4T1
y53XEk2gt3pqmWuhbrYAfUJ/96cyMIzGVi5SB72QMk317HusbZB71XHag5NYh/CsyLUwnKw8RpIZ
w3+x5pTmGSYWrNQQdd28oE9VyMMWOcBeLaZ7nVCl0oH1hCihcoipuELgaarWh1l9b57MeFJLkcH+
OyhKEnxo7gygRnGovQZeX5DJdwurfO0hV0LhGjimx88v1rPhAL5GAzsXbxjc9IYlHXLyP1xoSXR4
l40StLK+CV6kPxvruGSM/X7kG/BlWMPCW35vPa4zkxqHBqqCWMRE+tr09uGlPnkUwN1ZQ8EkhX+A
Xt0u2iBTFO1k3TumgQ8JggTcKTNoLdtz3pzH7paE1TmSbSexZ8KM0rG6mmnLat+WIXFkX6Z32yjj
0vZltU+IwyUoURFx6pfrmf8VZOr29dpggCvo5MSlHUBJ+IusAv+6zerMZj4ASFRY9owf3nxG4cVj
5BIYLZKvV8Gy4g5GlUr790CoHll+sZsvlSpvb0wzw2aOWWOkkeGhVc69TB8LEBBcaLp0zKBqpvfC
Avyziplzj9CUznb2NcXWTk/LtYxphNP3PQkB4+IICzmW7k+S5SkiTGcCosOE51nT6Xw81QhfEAZN
VXVNiKaVcvzHPYIz/zP5gd+fejVNZZyvlk1pWz+oBurM71Yfm5sB8GnIqkRBnpR3p/WCjD6s76rQ
x+c+f1I6WrtMR3MiWs6qIm/4ybPNl8VkVwPsdYzE9ulzBnwQzNgEb1agRkPctkdz1K6AIX8DCAdc
owBD0lwGWOyNwEMsr+OCdSYHy/ejrT8Rf6QqDCRK7FX1HY8y+ao81kQQkHm98z5n/uTJ1HnGpvG4
8sVxwm+H9NmtcTgOcKxREvHYVMfwfX9CbN3lNE/jabgxOpJbzCUH1MGYqm4V6TVxnvE3FTbNlmRl
BqpaLPsiOYJF0Vkk7vEARG55ip85B7jKoSq1IJd6Kcxp9OVEfAHK/Mu2SP6aZydUh2g7Vtbf6g9D
QFAWISk3krp4PSANlJ5AD6AzGEofKdhKTxTSbq+hAuw3qUCTcIQTYbvriiFh9i3U9byHhUUWd7Jn
uw9sFhoc1ogKvJoVjbtuXCWADB+Oo3Ku9/izqrMFy9/YYjCFl6x8i9f5k0RNhm9M/51d+jyjNb8p
1L/zyMTSr+i+gSjg2+LdgHXEzubGMc4vJeivuihic5FVrp11jaPf1CVrc1uNVUQXtOCMlL5F9vzt
a8CnA3bgNEVJnRxaMDdYD/qvwA6ZCF8QPKoEFIB9QWpa0yuFVfHMyzGHZFOOvXG/5fvParjSGi6Z
iUWLjLms56OWojOk/yydeEVoRjZPotISQDgIhD2u3ioTnQXqmp7ZvURr+GAFLWtBeX4fibtGKio2
qHgXm/bILLvcVHODV7oHEmi5/r8/5bmS+Jp+yiGQFRw3GP9ydrHvDYM7EdFvRWqmgv9z2hWIazcb
O9eXnabmArrx/1jvZDcZ7Y5XUF4sbrrENqkR8rrwxP2aiui+0xYNhicPM7GTl9IFTLwls22Kgnuq
oQe/l+MLKnS+pb9X7o5GltGJwbvO83dOU4UNNUI+ygDKb8JP10wO8c8TmDVp/YzjTx986O0TY34w
obGvwCgU83qHA4LVya1lyGGNcvK2ySu1cFd+BOBxsXLf0EestcYJiFAJJW9EWQdZL6BKw4Zeqcy8
9gdFhU4jnVnaD+lbu/TAlZxNm3om2nGrD12VhClkBqMq+04kBRIl23L7Xxs910mRQeU/Q6GpWNIY
1HJCFoV0sKddu9eIhVboC9BevnLyxTFni0z7BzIfh0eTYw1cLNxdeXjAtCTMXwzMwuvwkM2YlntY
UPJ3urhkpv/wTeP3KVo1F7Rw4dn9w2PRc7xfmonx6ZsUff1VoFq+UK84HaxMeohtEeiDCRzIEYzu
taCoSvdrf9N8CL3wchJf/7aNj88oaAOaRdGiAdf/jLg2zyr5/e3O6T5KNNgthAsXHqpDQqR+W+WW
Zxf5pExEAmOilF4rsgnD3W/EVm//tad2ekaz0R328j2Pw3ht/Lsq0HzoEQ/RQt+Cnq2EK0z+/u9S
8CiZ7HmnoI1vpa7JJWiOeIuMS9R67LKM1EVyZQId50TooGOrvLCsnnXT9e0g9SErkZI/5RSTEykz
YaNd7/TqiY2e611VvxEOl+EOmUjPdG2zSN9r6WjhxnlUXcROa54qnRBkgt88iKntq/SqxRn3m79p
shO8Ta7MvMJMOzkOaAadwJ29KzGYnwbZmwJZi/k806xgL88NUDfIXbIcRhILFrzAW7+bwQak2FEm
EM4MkLQwwRgfg0h5ZLDGQQK4HXrYMAd66xcbEFtS0qlJ+JyNCsEnDUYkpa2E5aRMoCgnurHwmpbq
wA/O9bBXG0NmlDsRVWzK1slkwZvT+NvjVzbA/+6V6duuNDsDQcMPTGbT7xXj++7x6uYRNXdb7mw6
RnBnFyZOdHa36pjOXcL/HC9Vf9q2EwVC/x9aR53kwhlw8WU3Fglvs6a+XdYVPgpqPTa8v8V0/Chx
+/wPmgKNPxXKgE5g0wtahhUonNIdCUGdhtsaP6adk74D6XOiTu43lFbf09nzNzGn5pduumndlQ/F
/19i9I5zgH5Z1j/+Gj1RRZbNojwHddRGG4dkQWvwEBH5LjbIaP9ut6Af9WvKHpugHgMoMVY5W8gy
3xqGZI4sBFSVqgxf52pmZBHehZ2e8edTN+r4Ff8umvaPWaj7rlQPmDG6skXWA2NcuZLvYzw0iyV8
eKYv83lwupIGGq0OhR91FOScAF38L80IXBwNDflap4ufAiDP6m/f+KlmoRSYItOOUDGkcnC7vY+B
/wSmOJcETjXkgNYPm9gQVnYcCS7dXGHC59LypLi29YYhhzfJ43QO5EBSHnZrmIGMpRFwA12WvkrR
fs/XleFrQQKHyoje9SPJmBg0nEv8i7x8Fpbjij2FBIruDd9rJ7QaFyXB4V4HrTOVDJqQjbnNRDgT
A6q3Rv+kA6n4fPJyLEwdeWMo8BqdGCE+oxxstCuPKWQSPjJufAqT4Yg4l7OM5yCiTJ2kRqNTFGyj
+LoxuLjNpXUH1P46DQUZzv6IDF4+VY2f9kuQ8wTe8pseojFPt5HZpLcoB98tbvYqWjG7X4scazni
lqVc5uylBxivLaKPSaeZiTO3MJ9zL85xuzlxqN4AO71Vn7oZEHZwNoEcG2ZF+AQFkzXaIkWIc94C
L8ZAeiQhLdfTpo0Zi21f1DptKpi3sBYZidh8WfHmqpSCbOts0tUsYzUkF5dYFs7tPM5Vp7qV5aXX
HEE0GUeq1a2yOK2izc98k0j8noTU8zb4WU5EiGWlazeBS4yCRbD9+cFRpm84pWkb5zbg2Ore/84z
Kp2cuGnaKntG8lYifaoG9J4S5O4LzxooRYeD2QeQI6XeN3/eLT/N9bX8rEebNNDV+tlBGXsnylzz
P/SawLuoFB+j150OMaMSfetws7zfeC488Q5pDG0uPbsuJa2jFphoaN7HSOcwO+70B1fphOLCeEo/
5Le/3egXYHsZgHbkNsG10nIKN5RJdjA+pKIv+JnR5Io9bYoClhu4GZF7b+isRTjcZf7g6H08GgHf
FT44U673DEsjJlz+ihumaFbpRTwi4ldv9QI6P7YPibRnHinZoyiKdzsUgBPKlsRlo4e3u7mFrhAn
A2J2LOX6RA4r6c/lRxoEaybIZLRkMtbIx6hyye73piQvwzM6bC6oRuNkB7Ex7+pRKdMm1R2ED+b1
JHmBFFLz/lk3dMgk0mFw6uIXvLd+80opUZQgQFy/nHa55m7Ri+bq3Pt/oVB3c3yVGesNw6RY+ckn
SzyX4BEQjGz0PdJVg/mu/K2QOQu+0VC5fgoaFgIb33QDbZELi6oHZjSOo+2vKwmxKb/l4thRRPL8
J3Ine2OgN8gJWfGiYQWoD5qbbTeP1c4MZg8PQtahwWny0XbsC4YpCadNYZmXivUAqV/IJKamQ5Hq
88V3lIRGsQ4i9gyTc2P5bQh5m1kxWTOq7S5TjWtSnZniaNjUnVSoArA/2Tciwq0SWDDa/KfRlR5k
JDmsnHBZVhiiFnKEWLpuqj08CrS019ra4TED3kZKOA0lRfSeHwKiKp4i0KZeYugR3WsA0rAc5CR2
yBNBAYIxyyepz0yrJAE4dP0bQxItJngabF5ZMzL0olLxrQEi4pjcsUNwYgO1/oAG/RxH43i4NCp1
sPON5nAifkiRcSWZ7pwJ8/UQXghZrg+hbJvuKaIpu2oMh9xXfitPFgXjmnpL96SmIt16jvjfEXs8
ZCO/azoBAwtnJ5kgb4VfE0H8bpKWGetVwjOByO/sN510E/GbQhEXeFqiQXKKeLnH6fzFmF50nDgo
vxwlPXwesBuFlWBxpqsPAGHrvNUl/yGtMAwZ92cVXJ4jXbozlGhuIJyFhj62oRQwEl2vXXuo1on/
6aWx5oE/DjDhTv9kYz9d4taSALJ1pyWpAmU21T2wk+qhy+MfEPMCdrIsTgbWnXSMfqT7QzgFkIKD
i3wKcLIKYWLUEIlU+gotC/wGdBD/4cscQfZpBzGoFGlUnSNKwkytdQ+jMtirCGsesh9pCbpfd5jk
GkZ5olPnW7sIL/PqgprtjZHbh2ki4z2VTE5xhGdti62eilLs/ME38YPQpc7WWUDhytKj3F/dtL36
S6lKm9uwkRMGs2xvgsK0iDyCZZhYcQnPrcvgqbegPKyGSVyRISOXP0rfclX61l/hWuDbcN4vxV9c
7Fgof6gw88ZU7ghH0P44r50bBnKjVhBAxWt49tZed0Lc2dXVUOmWvYhzcouNz8INxlIZg8O9YwV+
SeUTFhysWjB9a2dI6i2n6WnBwrT/oTHgCBG5i3PPrZS/BH9ejyAs191oOnHoXE1JU7S3h7k4K8UO
aaz/Ui4pCl2O16M2J9oTMfld+6t8o6pG4GbfHE6JGLpRh3c2zVTOIXVNtCGkNldLSNp7q7rkfmNr
/KhFXMM8ZRZu6JN8wxIbBSzGaJuulUQbNBjCB0+FqAQKZl3KQ5Zb+C4VV7Djopu041HU3iprPvHb
F/NVi2nTKSPDhq0mS0Cn7iaafLYqScXy2ujOnaayYGnRnBzF6y4c34cxSi6Wg6uUqSx1r+6RFUBl
i4ISl5vYv5TkM9dDLuHX28HDsdcbBOGUwZ6VGR2CC5/hM5U8P+B6Iki5bGgvt67XRhLSf5qTHICh
cLQKSwkljGWvzg9ryTiXS69YpODQAvEZ/r3Fy1neJTMla3wXJ+HXtNE7RQmbvyS0GM8g9MDAhNcu
2KMZh12bjSA5+JGPD+KzhChlna8AAylDi4rtWlbxnZc+17a5p8zl8OoaHXcXfg+dXsfE5+NXJGYf
mY0QrM/eUwEKrPewfAfgP+RXp3OQNCDR3msEMDFcc8WYmxNSEcKuK/+3iEnIuiUcRcqt6/W95T5f
p4S+Y6qftVludofwSjp7IrnwU0BRGGPWLq+VtZVxDfSIVEDqwJ8tgwwc0n0lMONQnxznJvhVkHUC
Y4gP1Di6NWx2Q3RFioF3jHLM8cb98ApY/j48NhvxYlCxC090wf/Yd8hBcobxCYr2HwdzmSo9KfhF
vtz3VejBsfaW4blqrv06wDb88Uo5xBYLAOCCT8W5vLJchh/1N9syY/5ueVos/mTTnsVLtygYB9J1
FwefoiPfm3uyaQFSooFjjTjK04x+1qMIVUIg+LKyl/+Rz5r6r+kv9hXIl5CQhsyhWSpm/RIcoT80
nbwD8DG7VGct1wU1FmywTHG+spNyVJrKyZ/m43IyraXe7+vrD0V1luATLwhfjNYvgu7dNgho9xmh
4ju8LjqBJfOKRDP7wDTrAUyI4LU4N/9sFCiZ56rVmKY0TDS7guDqDSizq61IvLin6VnMyagc1PJJ
EWC6+BkSc2hYJ8vxVJmyGFdvvBq3dzHmgcEDMA2iTEFYcEhOeHHwTZ670FZtwnzMkzZebj/rILjj
TV5jsfRZqoHdpRXmjqFfDME34qeiAktPeLHeL3x0sjSMlFHSS2l2OzNM+OtdSg2zyHrIDhRRJrGS
UlJ9Gqd9hbglgPQ5ncnhV4712XM9goGP/W4QDcqitmYYDoN48W3CXMe1dU+ByaqHm3vwF3UCk/pg
GE9cL8xZfjeJEtJL/LN7w/C63y9lGOvruMltNlsRDyUjApWwaHFyAkl2OHcUyb3dbVU5FpW0PpX5
VjoxJw+TE44Yq132RSJZKILfojodkOE0VjIqNN26stTgamzECkyfW0P8cSXViHplKlUCWITVY0Dq
a6HpNJcBOCag3cHbEfcFMbK+/0NtXyjiHz9NV5LuA6lVZla6iGHTlrHCThx28CusvggxNaJ3HpKm
XdehudID4XtBBJzIUnxE/LhwI3qXIw/8qVvFVcWBW5+9MZGeK/QMvMXOFSDYRg4XoHNYu6+3sD/P
2i3GtbD4dOqUCIeO7m6ghSJGfdBbkm5ORB/Yt/2jbII1HnDq4laSoplsoKQxZXMXH7n1N/Od9k2I
zQlzNk+VaccEzVhtHyK9UeDElRGz9emoWrgPRM9asrP6Y21FAfC+gGTVkbOp1BJlLt7eEqZpGtZs
ibPtX/x8JVy/46eSXRraSaYJbwXJvT26pFQghtTm3UQQCEFvTiX6G1KnO9LdXnkTsiL3j1pFOzKy
gThWiTej+xjJbiDSkRvNJAuTlxJbDmOeLAcXg4c6NR2luGos8LT76rRht5xwLnT9yNeDSIph3nuu
ZyreWBqojfgP5s3FwarZNRnUNni76y9QZvZix25iEnnpawmAP85RieMUvRK0K25pTW1KxtOJAtMJ
aHWSfAfTgKDeA0X8eiI6hLPwRz/AdjnVS2KyUxXYxjj1MXLWisGl3WXQU5GJ+o9UbF7qo9DJN9B8
xv+dq/dMP/mr1Ou5cQSaYFKMlOCOtREKIST8IH7iypoDX3IV5Fm4udNkD70Wk6cXeLL+wNsh1I9Y
vlrMLOTJvVy0c/h7sw72An8aBJhGuDuO3jAyT9OoaKJoQEaUi3HnnjUuq3beeZPcAgrQryiZeoqt
VGAA1DojEJUmHdu4At6X+uSB+AaM3KhpNYy2ZQwOMtgDcWL0hdALQrONjdmnqOP6JWpWDlLeDzAr
rrt8TOcjWdJ7jIkjp9KXSBW3mbOc8CmfSizry6d9nc79uyJ1FFnskbdbuT0ZBibRPExV7uId6e6Y
Ojnf85cvbSWO4zMSeyboI/VpauH6ptnX6nrarR8I9Y8n439xuuQk/+5tCCGKLsPG4pu2rl9l+gXU
f6BPEVUferWroQYmcNn2EUouxT8kn7old9MtSx6Di4mzj5s93aKznL3msVuke8byxQUtxTQTdBx7
k7wMYAv2a3P534btlZIG3/YQ/MIhz/0KPp0yGzM0CKHKs8/8eK9oVHafUmb8TNfQEa0FcCHO9zu+
49ZRVWmzhRgOJAhdpPw3iMODO5JRrEYOjv8qVywCiYv+G0fz181E3FfXrAfWyNCFkLu9YBxAuRUL
pTbDeX3top3cQVDKJJjaLC4VPxcROXzWJYk5J8Ck3m+FwDOWphaeFAGhTTLbqIDdH9AdX2rM8CG8
Q7CX+bpg8z18r36FhEutzMJ0xP4VjkGsgPeZtqDhTwY74hV/kiwLx998CL4MIHqQ4YIxJpzhgY8y
c2O+6aipqARCp7mhxeGWIHh12kiZ615hmSOE0z7BB2MV3SbhdJZlS9PghrRTJmAYptvQlpDxKeOM
SK6avNJKaDF8oHXa/WM+maVO760w0qqWIUJW8HSLmjuRgXCdTKmLPAD/1c8FepZjV/knjetqBmjc
oo7JawGnYChmw78+jm9OUmVWG3j6jDZ8OUxWYdhKpKgF42pI/OVB7HEAm+Dx8oRc418MD3qsE0H8
P0WjK4q4CWdO8/fCbNk/lnotupwvsDQcfIjdLWm9lFGvHCjE2kGsv8YsQ7XGU5UiMKmGa4SYHRGO
E+G9N2+iWyV610W+eXOV4jJgwRR67OhdpyS3NgkgOZfD3/kwLeoaBeDsB8qEKOHrSJKd1Up0NYO1
MpY7VNfS3hObXb47jtrnE1/kDU3n0E6NEaoonChie2DGcVcw7+4opKzzmZnleOQr6YsX5TmHkLwG
ccbZhBUyZZ8N8ffBY83V4rAJMXuT/iTmE+F1S5iZQFHjrldd93gALSHOzNbKe5riWPiBZN188bvn
oYEkomhN32vmUScA7mWY7TVF0mcS0ybSprn7XJ/cQoaWOcRuo4XXXXd9zEZlNMg8mdYNLE7fbHgO
oIkdMkmMK9+dWNzvx+YVkBnwsxxPm7giZDeSmCVy+ilwk74M1khcL+wvVsyzpagsLmqO7a/DLbic
rveqzkENIn/Pfl/H4CT7pSZlkhheZIXwcRFLffqDIdnwcSHQSleXiSVTh6MIEnKkL9GW6CklIBET
sIkw0WmAU+QH18TzzOFUzr+uUdl27o/WpGJhDqgvPOimXrRqeGvZCuRwT9wQ33q3qsGfTJAA2P2A
scjo0SIEw4yNFO/Lgp5WThVg2kVs9Q1kzb6gvvc+5lsShFUg+5llNruIYJF1FER7fWyHAS3t36sP
wUSj1v//lVq3MqphjwDsZAayuN1NL/HW2bw/OfFbhY0gJw8H0qzAzRBk9S9Tlw0STcK4oE8DD+gc
ws66QpMr7zp2fSkZKlyjLFqdDHZLYqfh0QYPHXqsxshEsnarGbskmq6rxu4IliO+IwOLe6TObGDM
EhnA1NBKQR3upeP5NAcqV7pavfwmZryR7+JA8WoMfsuSt/feNJVgF4Gc6+Uj0YDdBUntUebHaa3X
KG/hP8+nkXZKE77P3DqDV8mUTrqnmdGzdCAwWbMBeCJNEjVnRVTYhdKREBbpGFYRIzY52SFVgcyf
cx83+DmDPLvVjExd+ksuuNh936CqIM3/qXpg2aNET7fTg4wTSi7xl9vc8xIExZsJY6M9vxWcJRqS
CQCBwRlpIiB90I2UjDk0GwlpYxrB4/Z0hRFgiEfv2VNkNphyABK2QEiMkGUJOVxJaBWYqE4ST5pJ
CA15XWc4cKCO3G50L4RjvHqd+enGseWoVuwnIuz1+jsEox0JpOtEiaglqChtHcTTVOi9zIEzbG5i
s9yPC5ISE3NGggR+2+dIjE3WusNSVv/jQNBZZbH/5n8hdFrSBGu3zeezxzLfjvuKkMPRLrnUJchy
KG1kVc0pzqESSfdfHkHOMOdvJMPlxBIapqOh/iCHFx5+d2cM1wQ9DwOFTgRKojNpDEKGmPOM7c4e
auztrSQgH29pTeXJpMeeh+0ZIoF7bgegVEVqJ77Zq1kKx94AzOobd7bVEIFeN8W41KeOO/V7CUQ3
66TCDETRNYKqo40HCQvtylBJOH7Ef+PFLKejJYZ2W51xyQRBFs/vSWG1uZjl0Xo6q+S0nRjoQv37
Pf7JRQ7PQhKXpuIt/X3Qz+8KPqpZTOYGykYoTUKIPGoDQC5WYjz2U08JpRnk4uRa3EpWVyA5tI6E
mQ2hS76j/awD9iTKTf3ET5udQ+Gs9C8+GI7degLwITkP3s+oqzm3EO0spi32nBbeOJ4ZgBvEzsj7
/0MhsCIzVko3fOfK3nAHII0KMcxxJ5hqkUji+XDjQ8yeRiMopT54PD0gWeY/cGHjvJLvOt77dcLZ
M6q7uGv+8Wa+UhlELKm8QRpdSeC660c3Pv96URcd9Ncbt1/cdnPLgdA73eCg2LJQ2og4xx9oTWDm
DOm61pGedn1jiMrRhBtQV6T3qrz6/0AaXfnissjgm9iOFYRZyKB5CxrPXdq9XbLAQhuRDRBQiXUt
/4wCttQIHsLJSNimFQPM/DY5c3EH/nBrDjvK/M1WOdyxuhmWGyFxFkYASPvI3OadRal40hIAP/YT
Ycf+X7EfhR2dG3O6gBpY38UNBegbqRbo5u5ss3i0CjDbB98ycjJv1Kz1vcuKZYYrlFseM49m821J
XjRev0cqf1hOVbUGn1bY349hCYXfVUcH6XKevNSSQq1dvhTD2t8o0KQxeR+RNxFnrkIDoQnFfhOz
K4n7QzYTF65KlhyUY7NzH/nd/cSdWMfndfgsp4jJynw91KbCGj0CxUGU4/jE4vbz2GtSnDyqWHHn
gXO6pclh1CB10aS0IcDoTtw7DAryGsD+dMP6NTWAnEfdapxvFbwvQmRgHu4x+q/EnhqKSAL3qCCr
/oGvZbQvsAEfHN9ycd6nZJ7RJ6SH98Uxid7WmG3QKrtoGmcePMvL3OpkgXGovAURGu6yp1MlpJkg
06/0JY1cJnY4Ko1vX1x60/mi3Xj7r/WsfF0RgK/FRd0o6H+OeklWLFGx5iNncQnuCD3Tc2uDnEMA
Fcg/bSQmYO1hGPlLuvuDkQpre6ilQJCpp50Ne275rrhXZkR2TeL/tp1KyGl5mt5z4POiqazJik2S
8OnQ6aiHyQMO+ty8sB+JI1/mdrBrcJxyDdg1uYtSf4VV6i/B6CD/GivDHSHl8pSmu8IvdHQOVWym
LxXvkURFG+UGQ5QEapcYSzNVhOkweOtRK4DJ+DZpPyFmowHlfLWsG7PEOdGZnn+PubrmiMuykJQN
TI5IXcIhgJ75lI1Wq7VfHNCXnzvIkhOV087haowGztNEXiI9zLtOm/5iQNafnAAG5DD3BuKkzFqW
NzTJAslTJD1jd4uid+lyNSLLiGhj6m/bHXDgC9uuoxmgtrJVtDhU66Gvky9YUZmFpyhq/17/nFsf
/BfnoHrIvewN8AYXIjQWF7p2FnYmxvtrjz4DkPX8oQjQeBsdnIgE6SfXKpIQ25G9/30Y4F5nU2xM
jzGt7/6hf+MOKyp/cSQnTEGfjpS2CBLdKMAMpkS4kpNOoZs/aVQRgU5hea18Npnf2TPEDd+94WYu
2YvFhkfVohOb+vQ+ZsClSfg2Sw4DLooZ+P2uHoTDC1MmwlUtKVo8BR0fBSlAPL58Hjk3u2ovZbuO
tewMunj70UhIRnAzWR4zCAUgheUYIOop33RkONCLJEWC5QD/4Bna+Tb4L6IZ8TrBg+iX5HZptD/i
qpdTMuhCHXP9hcsJTZEwsdyiNp+m+fgBFI97rhHU523/Zh3iM14GBs3qY2UiTzVPX0il1Rp8qXrn
DQN6o76mhWjdtLpo/vaitMZkiit0xzbOqC7iOY47gplDDQTALkPDr1Cc3UxJqS/YAzrP6eRHXgZV
GmNKY4t2uWc9/5BzPFCf760eDkda/83T+GPbFCPh6Gfph9dggXukULTKWcTlN0DT5GwssWmVX41x
Yqj8Pon94pB8/oHr/+0psM9Zm5qdlOoJKgLOXzZn6I/LSBYjkTfUjX00JoNhVrfqjtdIdMsGu7tt
u8QDcZH6dWyVbeD+/1KnMaFflU+3thDq1nLhU+sD6Y2wwNSpWyWFZGa9S2ZNyw4lb23iryD5yFFz
6Q/iMByO2rvnskzfIoL3iIvsuynYyyfymQKWZwLbFEWMrFzRaCgOZdumL9Qh9fr6FdL1TRmFC6yH
dUNbo5bkkfIljF9nvo5pLGFM6FNpyiJUppkOtDM+yUN7sV4QHMGNtv3d3qyiCsquqtlKYBYUgsNh
7DGIIaHyfS0TQ9ER5y1eXX7IcG/TxiZE1TrdrGAlnQc5G2cE73QdAR3A8+k0d7PJYsbaKDNCdd5s
xLRgtUJKFPfhFX4oceOWH4Os7LoBScpZavZm2OfLTHWrG6cUWo8gC/m5cixVih62A1j+GXptjf1i
DwOjnqMeI4CK6p8cn9i0dohmBsLw9VEZTlAyjF83v0mMkJYkpekhvgzRKk5t77cal4qf3iG9AOes
TWNRuIKSHC+pA37sBrQYHqy2He3E8X4Q5OcK4owkwLyWtZTENtPAAwOOfrbXzfiQnoRwOw7QOVR5
JdK2GrveAXb0179qGJ8FWY6bJsshivv6qbxyWHrsqfNEJsMA3uux4A4x9yg+dLpIVHfly8+BOdoj
yYd8OYdzxGzn+QMs4782+1saglN7JI8T0IRwoPY+C8LMGii4PyXoiFr+MwrxG8d8C3XheMJXQdh0
nwdVAgJHoSPCeRuJtCQm459Sq4zhglBoUrVwrDoogAI9N/eneFrVJAzyoK+4HRZvW143wDB17H3f
3HOm2HZVTemdaFOWvuk9oQrsyuh1bmilBs/MP+cipcNyxoycXbJGyoBveaaKrp4K+bjw+P+zuPbR
u9zvjSLVv7XCxkg8e8n8U1/Zfy32b1xETgmrtIoTjOirbBEH9ZtSu6n7MrkhVT6QSwBYJNeviUo2
eD5VUWLJO75dQlwGU1yW5E0HTxuis6iqekboNZ52dQVbwAVFfdDwrMyszECKdV2RX4Z1nZNeYMZE
C/mbNxuk0WW801GxbktcFpsXowGUbdl04VM4hMWjVKOMOSnR5rLQCA8i6oP1pf0HI6sFXAIcX9zG
8xvcgYuNcgPYNxzgQFbJei7x0N7A7ZGaV2rnzi68i4ymdTU0J784WnuKTm9rVbBTdEhc45GOFdie
qqctyE85uWDf36zgGjAwfCqDY9HIjiLof8w64+yotW612mRYAsuwFDd5fT71rOZwbiysTMVVk/yG
0nMTmoDqvRh1lE8vrn5dusZguBTXRxih25m01ln16kpMwKZCfM8cwYJyQjLAfJLsjSCdSxk8/jtj
UAmZA6T1C7AZUh63VhdcUSuk1f6qqDtL1fxWAFY0pOMAGb9cMV8w5bbEdTQA45zxxoGLFflJI+ke
14XENigS3yrI2GcBzeLbhiS10zq5iIAHHkSV9jBtl6wy5uCQPz4/FzdRh9LPYOEoRA+TOIudv7N4
d8M9fJPbrvPO12ydqbLyf14R6q+et+4VOaV29gZXVutaneZ5JYcdhCJ3BpuwaT1gJyol7lp8Lnzn
N+E1aZyxriYLXXF8PIqBYPzHAdTYsCOzYmAk5KW4se+kb6cjs19IWATNGF4Pg7faFWfdHQoJv6y/
zsEovZvEceEJgysXXoCin8SMhkZ+e3x5y0WfZZWKAfjH5QAjfa16d4A6Cya9Rtsy2P9/hC5hYXmr
K6ehpDvhpcQsBtochPSI1pq2SmV6nxkO2iI38UI4u75Myi/ha3EhRorFTWIIY6uFoBqtJYBGshqz
WnstG6kK3F7X5yIZMWqXspuVNPVpnpMPOz7aTRojhNmInk+ezEatdN/JGK4VKnlxX7YvchSMGY8t
R6iKC9Weq8hTiJPdG7tBy3piT3awtXeDP37XrGnZA8Stb2bK2MJc0sejzSFMUBKrVCYiKWQSWED3
NhLAtT8L9++EPlEklXjzQG2K3kzDS09jQ1Gi8DwPX13KpEtNR1KWRrBSN8L+lY9Z+uiLMIprtYC0
hIXKXnDGzhY8MzvfpDsao5QcrQa7Tjh1s1ThKBA38FLaHEB+Egr6t4egfAzEYoXuBzjLITAI8f2N
LP7NT2Nmfaw9B6N/mBzCw7BI0FSAEXMo0qLm4ImPLXHi3ETEyaxQTF5OhDGQAPx9x19M7lwOZX0C
JkxP1fC8HvlcGrBN5NXR0+QGh6nu6PTGpHpUQbh9cLqTbMVzearcmxPp0QpJAMZlSHbRQsEKUWJM
pV51dn/CWkEQLhHvsZyJiF8hn74qCZmy0nO9t4KXP0k+LJzlopUMvgQF5qYTyLvQJBjOMosxJneL
jDHlEW0ra55Cvdlys0sNJhICMOPW/TwCwVfRUTelSBU3VV+Z5i6YTssg+NJ0qdHWVLZ5tC4gfx8N
tM+t/Y0qsCjD1MkI3N5YiBnv7CSgSpNg23+NHKut6VL+9s0n7kOFJH4OnoNH3LcDP6nKHyJsbl3I
Ef8kBKCjauNLq4OargrIpzgvOOQJ9N95Iyfa8yDZ91gBshzcnVM1rMOOAsiVRLjtNpNTZDoPiSaq
arGRyvlL9WhfOuIHK3hbRwxIY/YN5+YV4pOOKTsXQLArSbhAchAB5KhB1cOZAsyiOJbDJ6RRdEIg
Xhb962WRF16ZSQ+yBhw9BaAUFoRPO/I1+1r/LFmYskHNQlgBCExRSw4bMCjtaDdYRYTVzVNq0gso
zuw1tv0ppaOOykUsx7Dsd2WNF/89OcpcQHSnZLUcjNlkz0KiYfvd145o+G7tMpym/y9+N/AdXYsQ
7T+w041RFT3NcePuU1vyR1PZyCQZ8xPg+p1AgQM4TUA5YZGo08tYo4LzcRmIlMcVYQE6O46SoVs0
7gFRSupPwJnGf/s4ObxL5MXGXOgoVWXnDZI0wcRJsKbLKlWF9e4PxIyFjVtFHwrzyAkqSGM2TlsQ
KC6LvBkxy4pvOBBIewc3Tdm1sRGjSaomO6u3aczussZP6yMcSzXxcnOfBVKnQPgWyzONwCzSXMg8
kxdzUfVhi6CLhnwVFsC485qUi+SYGNRv++yANiRBvNK3DNrXYZ1fVu/OMhN5NdbMHZT9FP60KCnp
1gOR+UfriQFwXEOW31294BHHiw6tm2myDNx3BTLo9jks/ONCgA8DgCt+E7hUHI90WUpfjYpYk6aF
VCCbSnN4qcWJ0IdT8xVGfEuQlc5xgNE09w84GzH3d/i7sY+0tLv6QwZL1ll+3p7iLsd6kT7ZZgUk
QhhKzduAVFwv3NLT8DJmtWMNwzaY8IhPWPVwPQj7ukpXriP0nSAsAusqcaidwQz2vTHD5HIhlXPU
CVaUKzd+4rfPrsGNAJdu8QUVrTtyy8GZkQREFEnhJLGyoleAu06xd9RSFyPNPdh9beQl2jq8geIK
ZaNgmWHxCF14bJ6pDE0sd4fh5981PZkZo+8XFOraIu9UfH6zAibtqOo+ZnsZevQ4N9xXqF3Ir/w9
j+9jvhH4FJILptYVfyHeAjHMRjMvr83sKI5RkwcACO0sBqBMhu4/ir6EI+ddnduNMvXVyWUwrGYp
aCB9oxb2DVlWdM8Q9qVuB1PjBqomhNlMwybRxa8egyoG5D6l9Q8tjXT38lKYvFBO9J4T5SoyxJCD
9LeSXZrxnziJgjnmnZ3wsqgEXzQyj6CKd0dpv1oW7/g2B3QPmMbg5zsFyLcNihWN7ss9QcgvaO3i
GM0fvGJlEw9+BTK+w+UzWhNHKVtl8gDfqqqkoaACVYIkwLKUnDoZptbpDRZ1WMe5yUXEEJe8DSki
+VZovGLrcBdjECpqESl7RmSGg5S0n4982Whgr8UDurvtzLkd1WlrkrGkgy7b2OWR876cTpwr1ims
bFIf7rfwP5wts8Tp8egn9YaQ3s9whOdjG66n7RRxJ7tOK9W82ndDkDk+zyLmA81dM0SWRcmxv+2A
SQ96SFcuYKEGlJqfaAfeMW81lBciEGYSurE+hYrfvLIGvqJAoT/fBcqYBnmNokcfyDV/7hwSCFeT
WJpgzX5ozm+czZTlmpXh4spnTU4VEuogb6P8RO3c77tewPLugr5la6pQN8YnbGYSrX8SsWeUfGBm
OSnPkhBiEmCWGiJohxIUKAAqB1YgVwNpRYNaUk/hVOTvclRXk51ekBFrsEiMRkGO4MBLM6enWTbP
nZ/8f5T6dqZ4losfj3qlbnhz0FDJtVVvntUh3Sf+nn2Z1nRbpxdeXq5FY87s+sKKA82GrFD+eyvy
aX33bZ7Ru+ldZs8MshFg04GAk6yItjPdInbpK+/0khSZMowYn9HFVnsCkeYMOMiqm9Mn5XmXDF6B
GQRq7nPrIwTwZDVjw1PSACOtcDDi5xjayuI3R5wODK+Tp1CfIrQcne4+BBxGVCumb7LE8bd2c8jE
sOvxnQ/KcwCsdBLCyQqqut4GwvHZZqNTLAghUsVYyntZB3LQTJ/8XRLYO7Zz7+zxiqCBk5pQWi7b
9YcfpzEF42zghfxl4BaLxKT+kxeVEhH/MOgQa1I52/PjvvKk8ExfRiH3I8phx2LH6PFPwTms4yU8
exflSECHqN+hbmiuKpbA8Xof7t/HrdeVPWe1uEOYJDDX/JuR+2p3WUY0CTJ9DVQtfkBX+kr+kumV
pSObds05psrDZUVIAAngybpGGZ7plA8C5Iub/Y8m3EYG/H5stQQduXXkQGBT3QC6R022AJTMl5xN
EpICpnSOuLCMfYxK/nHtXTvhgptprMPxjlrfUbwrDpLDNxpVj9RnbjerxLjbabZ1svwlV9MqbcX9
0Cx7I0QHrAsArNw0yty1u5/YY3Nt/Equ7/B/7IirKJDowBfyGKBT8rrIBl+9h2kEPVXMjO5dTgOy
lpWVpp85Hsm8+GJyq6ZV8CDgiTlCoNGlH/lAUaXTHwdpF9y3Cg0+sqIFoJFdkdZRO8kYAcPZlAxM
RYds2DPaDJ5Bu3qvr7NWdDHxg9ekGebz4CnsOLWV4WCPEyDOh8322EgWMLj6tzJBPJDiKgT9T5OV
9oCjsO6y1J59gProTS+U+iIkHM4uBe1qfoE5bfWwAq9gHwe+QKRSTfcR7mWzoElMOSRNBF0OBCDs
Bl0M5JlSgjNJPlQ4dKksdAf8qYuHWN/3seSl9ButokqtqVN7Pu8xbg8dZwuxK0MegHjmOr+mj1xp
KF3EHHdW8/IcPcC45dbvfoykRmEDqb7qwY8TfOkgHDWMyOmea+nlzLkLTxyy4sm+lvQ/2zLmjbR1
AWhF6PMFfR9RvmmE2+voazSumEHJcOr428zWlhGV++qHKzGHwF1vDKhbmr3YYO/ABfTz7wmk9YB/
iv8OvlJU4+THlivfQ2Uy0VAT6Nj8X/HuNLsEGUadvun2d1aqRt8ripwR0zD6ifRIS2rki9MlJiWb
EC1v12JW0Jv7wc1mbgIMu0RIZqay2NCpzvYIe+it/f7oA+fu6NSzgTSgUce5ZjYz/6ONw3aBNf29
Ks6fEH0ZmJqIXp+71ms38PoHI/s/ymijl8dylaBRz0UWuPjlHpKg4AY1wVlcb/XaLpya2JsuiHuN
fO5cB0Zg3tblfPiTtd8Q5kONlSZqFDIIDProRlmkU8UbQCTLqAvVXBwlPFqDywU+djBg50vLRZZ3
PkYwytlas7Pt32HrDpLEwYIhLWDKK1AD6BxS66tfGQxZdHOWKWr8ZOXmS8O4EKy7VHmFhE5sLXOG
dyNUXTrA1yPCAsqsOw/oH+R8+T2RpA79vixwILvioM/RwR4goYT7IdCeSp3syM4Rlrit3xPYSvMP
lINA6ZEsjLRnSVF5ZcbpPXDk86k9zlQHYoJM32m5/ZtHNdtxXBcuTu/+ThiS1U70W5278/0Sikgk
C8lotj7FilWzN/MuTL6ad4/gota1GsqMXF3a85BGszxl1vshp7REdgjxKEdH7oHJvkR6c1X90t9w
VHAZAG40WlNKnmUP4dDrYzz/0o7OrcNZI8AKKynJxUSSX+XzhzaxJqP70KRaFWxLgUhF8wt8QVvd
sYJ+aOU+RQ+hpLArJvxHQD0FJpbH7ANdPFOnMNL9Em2V5UQ8ZgWOceor3WSbL2Gmy6MK4tCIh4uu
YGd1E9Yers03OiRUXxBj3Qgs9/2Cg/Y4OxF6KPg+BNLpldsJOO6EkL+hCIsBU5L9KiK+9sQ629iA
8oOjfGA9H10u3+1uFapb7tsQD1j7lQFs2IBPukKH4p6E+vpWyozEhpmUxQIZ0oz86sfwDRXIpKmt
/ON9YucSs5deTCarclsjZrYltjcQq4zJAqWZzc/b8mZ7JEoB1D9z4re4vqv1o7MDtUVJuuP4FFCv
varLbnAJkjWKNHqbn8ejdtHgylEdPS7S1P61OSo/H/j4UUzdS/kbYleM2U89C2PgBdz+r0Pm76ct
2rgcLwBvPqA/nXy7tUkTK5oeHrNv1kEg28ofuf432LinfUnUxjCYWUQfbA39AulUcOwBpqMTaQYv
MBMa1r5o6IqEeoDXDSvPsea3aw1Yx5vBYuME/PSLVIEZPju8yyMxBYOouNzbKP+hBDVDxrjqE4Q0
2WX+xlGICD+6UR6sJv2iXI6EErQAuRkzygkj85qgMmYsEMXz2YqliHeZUOha3ljAMmZhuyo2fiaW
ymR11HjxfNUmdzIjLg26c4B29qLwSDe0IgWWprVHISyXhntb64GK3NLDeSO71AauZLz+XXUXyY0l
R7H8s7h7lub8n6BXgmi/8qxpIGIT4qja+j95VgYaop5PWi7K9w4IgDAmlo+VClbIOHxp/QDP8GcO
xg2tu2H0EkqLKeiKi87ZXK3dBS4Gr5DLbS6VnC5DdYckNAgvBRLFnTdwyWxBLR4WjoISCt1RFKkd
oBDRt4MS78OPN6B3zf6Fuyq8iIXKqT6IzsZBGuGe+9iB5pt5TfoxhimWMYraZFwesGzJuZn6z909
3PKplzoQuA3FJAfq9ZBD1QfxxIEFDRmOUmfBtBWK1qqz8QmdZOIyAZelGOo0H/gCeSwKLJN1p4Gx
/7vB2Ldg5KNW7y8kM6EvdSUqRg9Y7FY1R3YVZdxoK3+WbTruHL3g4YJOxbF1eSMu18I0erKGrijj
8sWMByqM7ehcwdVRC1d8fp8bCCe1lOpKNFCnGkcjlsz5qmx3Q3ElxOJHwySYzou3GSwUWcYiqg2w
M8H6sxsoSbrv/2QnUto3jjibISg3z1AAjGJNKMeKHxensX3fms2upLltEC4+wVjCI3us/pDD24rc
+Fd3oBEQPwRzO4ddLDz0Svvhb7n84ZFpIEccQrZFVRKOW0c+fxJh5S3T1zkPgjn3cdGD1LfHMM1y
eAfAEfbOhZzt0rx1RST9UU1LKn2+4yOLHyow8zDy+Tbx4/ssBcxR06h4WS5/VSTnaN+iYO4L6WoK
ELh7iYIRKodT2BzZJ6NCykztO1M1GNJkjDnxNbfsutxufsEo+KjPye2m0NMf6BawrkbzjKutnuDv
nfp4RxrBwgU/ZmImOm5HY1qvmdeEdofhfkePqVUTI3s58YE+oc+P/dcOxp534xtUxNH/UkqIP22O
gYQYAIDAEPOjH5WvbtFIWSzrFmqQcwKLAMRLSNs3nGbdvoAFSBgOaPeXX1I43n3TS/NCAcDchpQE
L7xWCccsxL8NJPv9niElgkws+tfJX7Z4p8/Scpv0OQLpelgH8u56Mb7MHYQvr59lcElhjMsYmlU9
ZMfTFgwWu8e+pe2SOPh/AL8n3rbiAeC3pXsLWM/O2JdGFEusrB7lRZiKSeweAYRwJeVEblsVvUW0
GE06ZNaOEYBLmp3D3KIDqQY0Ni7j1jvoBiCSVPbS/cz33VnDl6lE+pBwAOFC6I9kW4QWQLCvAlzx
iYFX2h9FZFMYa09gr9tepuYlVBYR2gLMkX9opwvHB4M8vl691FhHiIG1u+8TJ212U4fVWwMO191m
ko9aBAw0O5/pf42eRYX8XwMFQLr5jr1lLCdOwB8TnOR1N5oOLH2gckYIQCSgHAos3mzx2Ub4Uqkl
fU4Rr2jhj1OMPEDruveRiUKYmxl680CVucycIhN88TvGtRXQceFUdbmUje5yrq6B/G4nm2+sUygF
/WeQ2yaZNa+76NFNjtVW2J9GadAaDDYHxNYg71hTApecdkBZ7PTEcOJvLWOyyJ9o9XrL5qH4UTbJ
wuAHhGxv+0l09HsUo1VQvMg7rxPLdEINASb4D2ipuxoPT0ubX/ytNAhmb5GxwOL8OYB0PxvFTHfT
CZ54dlPmz42KQPv9pC9QKgj79YEtH21CZalCu06da+xM6ifmPtxH2Yd3p9PWLj7g+ILsB4Gy7OtN
9qxnPSqRRrjtZU7/R5FbzLZluI2THh5xuTJOWOibfft8sYbveYIbLJ8goXN+YVEXurjCiBTnU/Tb
MrQn0cRIiXEjk1dDSj7DQizHnEF9oZNQHvqK9Y9TL6gCCTBkCfMLyJmAhONtC43pKUTR4pjCYRxX
C2QUkmFJvusdDN7e6sNnkvqMCrJUj1kZSFYcmubl/tIcQ7Kt3FVo5a+BXb0Lli5pZnd95KPK0SKd
X82hmNNNdUMYSd1ZehI62kHBEW/jp7ei1Ed6TPZF7QiWfvQgRFSGiFLjwZsKbOPc3QmfHRb8CUw0
+3bAnpTTKIpGHmgNVi9Cr2UpCG5xu5Pays+Db2Dp1QVm4GZKrKtZJwJBMad2Gxg5EYPxcC6Ni9fl
tpbbZhRnIg68L4gHMgNv0Q65GXoCsVFPGdA0TwN1GZohvSNB8Jk4ry/naIWJK5jzFGeZrvl2jKzJ
EOaBgxOpfakXbITtN+OO5w4LjGP/G/MTPtPL7nKhgSPiofUK0PMh9Z1IT+aMQke+yCWpSV7UpoUv
WSi1RxdWnUrDZZKELY3erBVMdspNAA7tVQDBz5pVcREITPnBX74gE4+epbeDN58pqVBu81OMu4cs
Crc3EEaKBEzXtZ9jREE9xJzFsA2dvhbTppP5j1lABAUv+5XUrEQKv4ZLs5f8KC05rU/w2F98Ch2X
53CnxBU1ykTzGYZiW4kthIkjUgUpt4yURnFg2BupuGB/MQVd4+qaDLA3BX61HGjy8c2dt22zhE+d
ylgqFXxjp8jt0FM0PBttNu7TE/9z0geHdwXpf7LDw2BVNavyNOdi1sYAl3SqBtExyUER6Kc7V+6D
dEXQaxIMRg1jmI/N0mXiU/CsPcAD77YQxDEj6Pa6TDkfMUrGTB8BUZ4lzuPXosdv7nFckIJI7nnC
2xq0G90OHIPypRQhtq2vJCN/VaeQNTTD/0mLVdn99Zk3/C+Jqc2Tljcx+kQjmdGik2OnzLuq2S48
18ZeXAJmP00+G7DhbsrOK+O7fTVkvUAoKz3XNvSc6F1G0jcVS5xx0p/6HruGRdfvfS84vya4mEgf
kNlCs7KK1WYl/yyRMagRkLUSpS8axEIdDnXR1eOhrF0NhGLZiomLydIEKvuC2823FNTtXllN0MZM
c1KgBis+7X91w6Cwt+R9MRbm0BNYlwEpM/sMvqAxYfIOt2CnVHLWRnyS/kqxgZKWVhgbGn0OfEDv
zgLSnXp7pEjBdMcpbvrmAltFqpOwI1tqmq9BMt+df/CzkQw3nIbzCJbP4kxm9MpTbHwZqJ83QkQ1
tmAZflRiWrxxQKSxJ6nLBP2t75XqimlyIZgcDL1RH5MMbeYngC3KZZvM8/HeSrT0q+lmSaCNzjhn
QDn+rX9Fh7al3bVNEAkPdxhyEWuOnDKhVJ6t5gFCI+QTgg9pehuYWEBMYt7CTXSFqem8qmbUUVSw
TP/qZ1YWOtTwQVST/iu7hIAvtg5U0SL7CEcKlCcqcYHkHkMgrmb2bWBqSTQoqFu6OFVJlS7c0Wp7
0l0xtYW4wqQmmuf84EoE3JU/xtwH2oppeUnrFXqzvtEdOr8M1/k0G43xB7aYX6XGOe7h2fAgE6Wt
wt3g31a9CiN6BVWDG2vBClIxd9uJnXqDs5hidicn+02klb7ow4mvVqU+ifVeYV/bH0eD1SQrGhMC
KXanDpDc/TXQNphdhM8aursdlQ4qXLmpz+mRgKKo+mvw9BKx1U8SQ9tBvgNVXmX73MFiTUT1Si/L
cM8ttbA08pD7jwa+UXP+0UGfJoizZhwQNyF/4F5tVwGjcgHrDw3XyBLoNtJM93ckpnsj++hI6afc
ADXW31cnj+3ZtASKrPr88ufc/h0/s8Ah/IZUu9B51D41qFLhmyB4IKYl1+jyhxzJBNRdXQljORYX
FU/FDgtk/iK/zs+29sPhUFGLRnT7VBRkvm6yTfN1Iu4AzNen9+wOYALT3CbylxiOtO8YfcYiOiRO
7gI6dGEa4jVe5w/4TnzEkLvyrs1dnHV+IGVojrySVX7ZkVeD06zTZ8VeZNzMqHot+0kEmJR2w9IK
WxFLFtMaSTPrBIZI0pMiyYAkGOrrg0ePbDHMnBlFCiJP+ePgMfL39rhWdytpKHkxjlYg+V9ZzgRc
GTJlIxSgPHgPKUAXfgCvEM1PXwEPC2IdK64jpIWiy3zsVbyncgAvMxueYsxniRQwVfitInySsLhQ
WQtmjtu4DeJ1E2vnhqG/D7yMcxi1r+v1Y5BlnZUSJe+S2dk60yCFqVVIRnMuVP9oEG0a73KovTUK
ElOEm6staia5KmDphOEzZQpEXt3itW4G7hF0BI8G10qm+wxVhKxswX5HkM2M0XbFO5FmkDIRQ7yz
KhzVgFZrnIpvxQ4uW5QGP7c832y+aCydpbqa16SdvyNW9ujIrsmAI9vSNR+EAaYzk6Enxo2oRbVH
RdViEET4qZ4lO3/Jc0pBWYP6abdjFUvUm98jsOJA3OfMq5RNk2E7u+YWG/SGRk93O3JEFR0hdRky
KPtE1OS3mwoSltMP/WQ6oCYqoueTVn9TuFbSYF5ZQTO2VzS6mmb6ikaQoRUxC30bwOX76Lcawcf0
ALTU0c9DtL41sqvX2scE6CtvNnJFRKbWMtuXpdWY+inpC8T2gve0V21iQxl0I3v9CVzglP05tftE
RSzvnN6FMH+C9SSMTXKe6vu9uYzICr72PKOAKi2+c9f3KF0EcpgjIK1PV+YtG7Z2rWEBsB9Pz01H
aOJqW3QJRVBC2IbEeuMWgjuUFEhp1UzJgL8Mz18g5OYHlFUXr7F9LmAkFP49Ot7vMpA5a1FRHgcD
pe4mgmsvDVu9Ypl8IYbAPdia7WnBrzb1JKw15gTDAEZCRfHwi+6dRD1qfg6TY3M6IPdq77Nig0fY
IrEMtTCd+SrFVS8o7xyluF5BYEWrSUkN290OApBYSLEo/2Y7DwdwDhVQEnpgd9Xlqr5hVPDziXUl
q7Gfjw637FBVDPM2ZHg2QgMSo+7khLpXzzZWsBxBvKj++GUnkXK2d/KY8FtN3uZ7SiKj0GD0PhZ6
0GVlavFkN5NE70mNid//r4sUFLvagpEwtA4FKBEksmWfRR0pHcFGAERe4SIEcLClT2DR4xbQzFyJ
SnjXwRD/EooArIeVG77k07sIGAjPu23qr9mwvAil0XpjmPlimOLzqOYJNIwreqaoAkMgTTeqWLvm
VXCGVush8QYzF3dhJZgYH7TbsC+GDyH6RwFW0rEryOdy3NnbHY/GVUd5cWrMh4dS6UuVJ9obqW2E
EbH74p9N1K6SkwOWziCl4PIvuLzMV52QCN2g0zjKmGzGIfmLNxr20AFcXo17Rv1CFuED7/ncwHQj
427PJz7ZUpwHuDAgltywL+7pBT3ut8vX8gxBpWJASfVCnYaItEKMct3MpbZu5/MmnySg7ua3ZKPZ
RSrTn3FZVIYC59/MF28jV+zGeqdUdsXZMf3yRWjDl53zJb4XhZu3N83VQkjBGefpCpRU7YNtKTSV
qB35bnletyG4RM4gIQcwv/7WE+utU825R2nrA49mpdRpMm8l3mw2Z026zxioCk30+bFzHluGjoxw
h/xcgviV83PQkWnwJy6BaIqjpf00ULc1Jwh7VuqjVPqaioiTro/V47ZHUVHUht7mnpTmu1agdpkh
gqPVoy1QBjSIW4919BXgXFQt7E27ejP0ZqEsaqbZi5AAxiJ3C2v9+JFcPy9a2naUC1RuF0yvdZmU
9FP41lDd9hx9O+ZbDHqDWcVdh3xmqCk5OsdBxNat6l/C8Y01AFZInxj0i2p7xXDon2E6geK0P6W9
fFuHpszR11gxFQ10qlOLQ2TNnl/yERpcyf5V9doiVt+bebpoqGrycli7SFpXR30NLOC0BgWGKIXO
oO0gWj60UmjZXq6s1XxA59UzwnCgM45tC9qYr/unhKEWpDARDWJayMqLv4/5PD+SH99StWEaZI3U
5W3CU9qCwrPUUH5OGf/+soJIPiO9XEf0LEBrhpf4vvuHvzuzhtR6cXX02stNJoEilffeku3qwE2n
8fQy1YUZShmztv9VpxANRNB6VV9wQ2tQCfvcd3b8NUYhzMrZ80gpfXAJbHq7G2HkhRPS4+wuGhXg
t5w5si8KmIz3uUbJwhztdcs2HhP6ceqAdVecf5H7L0SRa7iZNKlAwn9YlGPTZQqrMlPIFYkDMZgO
Hr/reLXIgENCSXioBtELPT7A28LlNI/HDfkaL03h+2mXB73ulu/OPSlSQ0Ymusr76GJH1irjyGyS
AzzChateZXns6wmNu+GoleKMUjvqI09397+4coKmjW2ykH1GNFXfd3HAcjB8dm2tRagSZcJPc3rC
9fHWSaSh1/7bQ23DJ/rat9baUMnT27j9LoH4zQ29iNeAx6tj7X488diJDcmkvyuY4rK39AuVNb1t
xFpmLthcuRAica+DtZH86RDNa52Pu9NdgckqyjT2OV07VpPILfmlkZvS3lG3eOBWlVbx2cIzNlWU
Q/oDYs++RQ0eP4Hy0t/3XoRoPoq8P5GpMlUbHfMm2iNLKBfCBc+FujsRrwwYqwLIonIXdVEuwL6f
YVP++/JfBW051Q8dl2ue6gRa9jXbrKuMF87XxeZs8KoOkgRdCoApu4/fDrQxdxEjW3AJPsUwYB4/
Vk3+LgAup9VLDZ/ux7DrSbepmRFcnQCXrgvZ1B5OzjZDkH+yy67eZ8OEQRsqr8mKyx2U8FkvTa1c
daOUZR3Z+oBrMe5hF3phYMUeoE1x9mOiB77virPvzy1N/4g3d/wAzPOQOEQYXR+sqgveMu5f9mK5
AzVqMe+/MvsetTWZKjDvX0/j98/yP+O/6Ib7BQF8HNcOkuS26hPOE0BN/3TygiStqoDcf91sYylH
16EnkRQ/WINaYo6gZNQcsA7a8kVTh240WPwFf2D/2Kq5Q5nhT8ORSeuywwi3DNidqamKfIiODN5G
e1LATYPXoTSN5fRXkvuasGuLT/21PI8EeMiygBmgukD5ADw/Lti+LvuiPmhqCMtPq14lco9rcGLW
lXYboeOtl389Qm9g10OK+MJeQexcD61xFz/DS2pRiXpUFWc/z6dCUr+4eXCBNN0eB4jW3gEeh5Zj
dqtkdraX/0GIibJbLl2Eu22zUxh276Akdu3sg5+nXmoqQicfM1FUTEgxDw32qr4MZ0owiLAP4oo6
NxmBEIHTlHiSWJjNgqgmTrR3cu5PKpEGwF04adHPh558EI/hKd6Lt8/PP1P5h1EmO+gHyCPjt7Gr
ktrxjJlSNFr8wTTIxeG2hQZ0wFFykZ7VDCGjDyldZiytkIU8povXWxO3Q8PTFolOLf5x9kzxYE7i
9CtBUPOXhiqsiV7mKZ+VgQcTrKIKFMI5zoTDGGhseitYsL/6d/bizvXyJNtRgu5Odb0c3bdb2Uz0
2z5G4HsvcLHOMcRBpBEIfCcdlC6tDKV+X+yOA/Pno9SOuj3AItc54rN5VWMnD8LIU5QgXfdTfL7J
Z59IU29PuZRGPmUkvYq7YFRVUplgNtguD812jJCMl8nbXislWFOM7s/1OLsbM4cbUHBOxxpEuv+W
IUBtvnALYpob3qbUoidlKojhhEcUxa5Ky3Y+0pvcFAKhkemn48mZN/V/Cv9NLS2Hrb4fYvazBAT9
CN6CuQK8BSqHrt5OtRpXcz+ILiPIq4qGv6iVnaYKzTTOoBlPeGsUG0lAV6R9HJ/mec2b4s/GAGlt
De5U2SM8LNPCa+AlkE1QHwofYkhfx1Y2ALW2vl2rEtUzFz9UwKiIiBqTo9lQ6a9jfIckOn4TjcHc
C+xOrd4YS5ysskHmQ+svkxhsY6N4zuXG60IT3kKWxCpHmpPUMQEcUgn08RdzWHex1uM1vs/SIQwZ
xpRZjcZB2uUVs5szpOIk3pzF1eQMP0De/1r3leTL2fyV8ikUvsGaybXV7iBNfx+39GIqP6wKLQ8L
r9/ajWQ3AZ4sDHVoLf9Tqy+LQLxxZQuckrY+4VSkzYD4/T5OyXS7dWNedqbPNjiUhIXu5IRsOHhF
fLl+Ym/kzDOHtc87IEjmMMsoLzM1RoMc9y8wK78I8gbroZsuoXNCetiGzXmXMTc3QMGFj+bJjJJp
Gde8BL182QuHsqh5MYrqeqR2MKkDkYxzgs6pl6Cik/WBiQ+XA7qJ+lyXt9YTXdBPk876IMEQUEku
2xSdoVTYgYMOgjEN5Y6EjJvifPtbOGKPyJAkToFtFlEWJ8d7MftsdDbXRAZFsoaj3OW4eq3BbIvN
cbw4cdbUyZZgV6TtVBLhou1VjUM2DsLtxTPHWnXE8S1hDOc1sZJZ3vGbn6ggaqR9hhdesGxGcxLb
TqJooL5TbIOhA70XKsVRfF2WmM9aPMk9Kc7h4dWiZEbqvCg33JWPglb3IhN7umhrCYEaS7mTtK4s
pkgzb+EmUoHptG/IRPi932oGyvkpyVu2AFHEQvfF9oq1ZpzRbGzV30KDZqVg5WVafmco+nmzteFr
CAWBBAJVtsO0pjuXQXqTn34KAy2M9tjwgYstn7A0nfuxsRO3kfAvqAS2dMZ5Ezs5QrjRsL89fZJN
TMY5pov3ZSCe7W/W6D6m4UoXt8rEH3ollW/eEY/VtDmbM+WT1FG6Qh+oUfIWMnX5H/QXu5Xk9ALY
JVPSy4KyBR96Ba1Uw2+9RiHyy5Hid+LUSFuJPEwQjanr2kjleHOpNK7I7CezyE8PQdowEWt/1I10
ESDnQP6t0POJ0vvbFbSw4trQ4JL39Qv6OtG8pULpIcJeOKA/Oc1MD+hz+oqAzw89o/jPY6wOstpj
IeU5ZRlAdnlOPjGI6Yu8iJgBau80+TU+8LPenirV5PGOhaHPp/6A9gz3JLPMtZnGxceDKwAwJEGr
Ah71IsTIW19Bg16ad7omNsv79udasF3fFJ/R+3u1B7hyyX6AaSqU2981A3ua7d5IDHuyEZLInkRt
7d70nLbu+JzioUeiT4gQnWmLVChG8JG7QoLMFWH3AGlzJ2CrLHcbr9uNbMkZLl1V3lg1eOmGok4h
lh62KlX/4m/aIvFQH2cdwWhzTgkRc+AOxKfR8yjRclT2bljeB76KlojJbQuiyF9QxS20B40I94dC
3ejzKMzLhbwF9tjYsDD8o76/cvtMF8U3tYMcAhXQ7eWwbfP3NuRyrJvl0YJAgCrMSzeqr3hIs1yE
JazJ6+QSYIgDBImp6Z1IIynKcVT57fk6U2PZakV8gkbrvDerbF8dHEt55yMjrE6a2jWmcku18hFZ
vrTVuWikbnTQlRkouEblYRMHV+zkbnyP8ymw3j6CetqZHAWuIFwVEXI+evAsG9BikdXcJFw/ah0N
GDyUxMcOx4T0aqpT3fPV9b/u/uIKG3mYA3qE9PCkTjQFCpGznOMIhUhYl0pB5nqu+0hneb+flfuM
xL9vyBKheoauIvDCgGxLIvl4cAa2CD94QrMFBVBQEUh+GAdPrNwQ1jTtaA7ugSK+WKanjWE9ItCZ
EZG0MTzAq23nzmqY19mYNz/dh8tI31GENfLyXy+W5QT63BXbbuSahwAjXqkW/XFjx346N5+O76l7
wBr7oZevzS4b5bdb67CvUW9hML43L6pQrfvyWiAcC2VV8O43jKzgtDsAVDXTvqv8YEeK4kPQbOQH
3G2BWQo7itnlVWXUW1+kGj4iJAs9GuoxZer3kY6xz8U63V1X1kn6rglKKO3WpuNRFjsyyWaVhOm4
FGe01PaxBpNC8SuzQQ27qB9JiMcOZlOEWJMrc2W7/S4JEtt2UIIslGVwDmLokkXc/rTFIQMRN+dW
3KrKBUInDpZAm20xW7n/+k/AoqsIQPmhTNM8S40au5gVyyuD7SmMjWe+1IK02bUdkuevjTNXEgjE
IPgN6QaD3OssxrPIbJTRqmPIQ44iMcYcNhmAqE4I7KKP2GzjIf7nrdYyuerIBMPFQoykX/M3F2Ra
Sl7+q797KEO0Fk61+scqCNgd9t5uHajyuy8JF5TY/eC7YE9/xSQZuzEBxgdtoVQB3FYQgapW0fes
+seSc6qBoPBa9OHeszCGtG7OwxQYIrwGuOthFCVb0DynMXe0zgOIEOnt3YqNiYwgGoGRRNcFbVSg
NscOpu5KgLjOsSh9Vr+npzN6A6gkCHuMdtvQ89HZSzIu4Lc4TNk20TVI79nukqsoQ/ZCELazFkfC
Gj0853uOUxtcHOWpRb2RTUo0/9h/hzWAeMtl335UFX+aiTGzfGciHPsokDUCDxhpjo6lH/J0YMEI
U62ZgL4KZpMZMfnHo0uodYvABk7pm8r3aifu40C7VzwmeBuYeyJ3t8TLrwMf+wVurBOfjct6ycsa
DYNKPhXGUgcx4eus5pjGaHUzMGPSGatC4q1NcdKB
`protect end_protected
|
mit
|
a42a8e5767ecd5d67b53938f74eb2ff6
| 0.953914 | 1.83101 | false | false | false | false |
zebarnabe/music-keyboard-vhdl
|
src/main/AudioSynth.vhd
| 1 | 3,680 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:33:56 06/30/2015
-- Design Name:
-- Module Name: AudioSynth - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
-- library UNISIM;
-- use UNISIM.VComponents.all;
entity AudioSynth is
Port ( clk : in STD_LOGIC;
JA : inout STD_LOGIC_VECTOR (3 downto 0);
KEYBO : in STD_LOGIC_VECTOR (7 downto 0);
KEYBI : out STD_LOGIC_VECTOR (3 downto 0);
--btn : in STD_LOGIC_VECTOR (3 downto 0);
led : out STD_LOGIC_VECTOR (7 downto 0);
cat : out STD_LOGIC_VECTOR (7 downto 0);
an : out STD_LOGIC_VECTOR (3 downto 0));
end AudioSynth;
architecture Behavioral of AudioSynth is
component keyboardDriver
port(clk : in STD_LOGIC;
--btn : in STD_LOGIC_VECTOR (3 downto 0);
KEYBO : in STD_LOGIC_VECTOR (7 downto 0);
KEYBI : out STD_LOGIC_VECTOR (3 downto 0);
keyBank1 : out STD_LOGIC_VECTOR (7 downto 0);
keyBank2 : out STD_LOGIC_VECTOR (7 downto 0);
keyBank3 : out STD_LOGIC_VECTOR (7 downto 0);
keyBank4 : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component keyMatrixLED
port(keyMatrix : in STD_LOGIC_VECTOR (31 downto 0);
led : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component segDispDriver
port(clk : in STD_LOGIC;
dig1 : in STD_LOGIC_VECTOR (7 downto 0);
dig2 : in STD_LOGIC_VECTOR (7 downto 0);
dig3 : in STD_LOGIC_VECTOR (7 downto 0);
dig4 : in STD_LOGIC_VECTOR (7 downto 0);
cat : out STD_LOGIC_VECTOR (7 downto 0);
an : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component periodMap
port ( clk : in STD_LOGIC;
key : in STD_LOGIC_VECTOR (31 downto 0);
sig : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component PWM
port ( clk : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (7 downto 0);
output : out STD_LOGIC);
end component;
signal keyBank1 : STD_LOGIC_VECTOR (7 downto 0);
signal keyBank2 : STD_LOGIC_VECTOR (7 downto 0);
signal keyBank3 : STD_LOGIC_VECTOR (7 downto 0);
signal keyBank4 : STD_LOGIC_VECTOR (7 downto 0);
signal keyMatrix : STD_LOGIC_VECTOR (31 downto 0);
signal sig: STD_LOGIC_VECTOR(7 downto 0);
begin
keyboardDriverInstance: keyboardDriver port map (
clk => clk,
--btn => btn,
KEYBO => KEYBO,
KEYBI => KEYBI,
keyBank1 => keyBank1,
keyBank2 => keyBank2,
keyBank3 => keyBank3,
keyBank4 => keyBank4
);
ledDriverInstance: keyMatrixLED port map (
keyMatrix => keyMatrix,
led => led
);
segDispDriverInstance: segDispDriver port map (
clk => clk,
dig1 => keyBank1,
dig2 => keyBank2,
dig3 => keyBank3,
dig4 => keyBank4,
cat => cat,
an => an
);
periodMapInstance: periodMap port map (
clk => clk,
key => keyMatrix,
sig => sig
);
PWMInstance : PWM port map (
clk => clk,
input => sig,
output => JA(0)
);
JA(2) <= JA(0);
JA(1) <= '0';
JA(3) <= '0';
keyMatrix <= keyBank1 & keyBank2 & keyBank3 & keyBank4;
end Behavioral;
|
gpl-2.0
|
454e35cf104fb76f6bf1697071b1c918
| 0.597554 | 3.607843 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/second/second.vhd
| 1 | 11,933 |
--!
--! \file second.vhd
--!
--! \author Ariane Keller
--! \date 29.07.2009
-- Demo file for the multibus. This file will be executed in slot 1.
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity second is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32;
C_NR_SLOTS : integer := 3
);
port (
-- user defined signals: use the signal names defined in the system.ucf file!
-- user defined signals only work if they are before the reconos signals!
-- Signals for the Multibus
ready_1 : out std_logic;
req_1 : out std_logic_vector(0 to 3 -1);
grant_1 : in std_logic_vector(0 to 3 - 1);
data_1 : out std_logic_vector(0 to 3 * 32 - 1);
sof_1 : out std_logic_vector(0 to C_NR_SLOTS - 1);
eof_1 : out std_logic_vector(0 to C_NR_SLOTS - 1);
src_rdy_1 : out std_logic_vector(0 to C_NR_SLOTS - 1);
dst_rdy_1 : in std_logic_vector(0 to C_NR_SLOTS - 1);
busdata_1 : in std_logic_vector(0 to 32 - 1);
bussof_1 : in std_logic;
buseof_1 : in std_logic;
bus_dst_rdy_1 : out std_logic;
bus_src_rdy_1 : in std_logic;
--- end user defined ports
-- normal reconOS signals
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- second ram
o_RAMAddr_x : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData_x : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData_x : in std_logic_vector(0 to C_BURST_DWIDTH-1); -- 32 bit
o_RAMWE_x : out std_logic;
o_RAMClk_x : out std_logic
);
end second;
architecture Behavioral of second is
-------------
-- constants
------------
constant C_MBOX_HANDLE_SW_HW : std_logic_vector(0 to 31) := X"00000000";
constant C_MBOX_HANDLE_HW_SW : std_logic_vector(0 to 31) := X"00000001";
-----------------
-- state machines
-----------------
type os_state is ( STATE_INIT,
STATE_SEND_ANSWER,
STATE_GET_COMMAND,
STATE_DECODE);
signal os_sync_state : os_state := STATE_INIT;
type s_state is ( S_STATE_INIT,
S_STATE_WAIT,
S_STATE_LOCK,
S_STATE_SEND_FIRST,
S_STATE_INTERM);
signal send_to_0_state : s_state;
signal send_to_0_state_next : s_state;
signal send_to_1_state : s_state;
signal send_to_1_state_next : s_state;
signal send_to_2_state : s_state;
signal send_to_2_state_next : s_state;
type r_state is ( R_STATE_INIT,
R_STATE_COUNT);
signal receive_state : r_state;
signal receive_state_next : r_state;
---------------------
-- Signal declaration
---------------------
-- bus signals (for communication between hw threats
signal to_0_data : std_logic_vector(0 to 32 - 1);
signal to_1_data : std_logic_vector(0 to 32 - 1);
signal to_2_data : std_logic_vector(0 to 32 - 1);
signal to_0_sof : std_logic;
signal to_1_sof : std_logic;
signal to_2_sof : std_logic;
signal to_1_eof : std_logic;
signal to_2_eof : std_logic;
signal to_0_eof : std_logic;
signal received_counter : natural;
signal received_counter_next: natural;
signal start_to_0 : std_logic;
signal s_0_counter : natural;
signal s_0_counter_next : natural;
signal start_to_1 : std_logic;
signal s_1_counter : natural;
signal s_1_counter_next : natural;
signal start_to_2 : std_logic;
signal s_2_counter : natural;
signal s_2_counter_next : natural;
--end signal declaration
begin
--default assignements
-- we don't need the memories
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWE <= '0';
o_RAMClk <= '0';
o_RAMAddr_x <= (others => '0');
o_RAMData_x <= (others => '0');
o_RAMWE_x <= '0';
o_RAMClk_x <= '0';
data_1 <= to_0_data & to_1_data & to_2_data;
ready_1 <= '0'; -- unused?
-----------------
-- State machines
-----------------
receiving : process(busdata_1, bussof_1, buseof_1, bus_src_rdy_1,
receive_state, received_counter)
begin
bus_dst_rdy_1 <= '1';
receive_state_next <= receive_state;
received_counter_next <= received_counter;
case receive_state is
when R_STATE_INIT =>
received_counter_next <= 0;
receive_state_next <= R_STATE_COUNT;
when R_STATE_COUNT =>
if bussof_1 = '1' then
received_counter_next <= received_counter + 1;
end if;
end case;
end process;
send_to_0 : process(start_to_0, send_to_0_state, s_0_counter, grant_1)
begin
src_rdy_1(0) <= '0';
to_0_data <= (others => '0');
sof_1(0) <= '0';
eof_1(0) <= '0';
req_1(0) <= '0';
send_to_0_state_next <= send_to_0_state;
s_0_counter_next <= s_0_counter;
case send_to_0_state is
when S_STATE_INIT =>
send_to_0_state_next <= S_STATE_WAIT;
s_0_counter_next <= 0;
when S_STATE_WAIT =>
if start_to_0 = '1' then
send_to_0_state_next <= S_STATE_LOCK;
end if;
when S_STATE_LOCK =>
req_1(0) <= '1';--req has to be high as long as we send packets.
if grant_1(0) = '0' then
send_to_0_state_next <= S_STATE_LOCK;
else
send_to_0_state_next <= S_STATE_SEND_FIRST;
end if;
when S_STATE_SEND_FIRST =>
src_rdy_1(0) <= '1';
sof_1(0) <= '1';
to_0_data <= (others => '1');
s_0_counter_next <= s_0_counter + 1;
send_to_0_state_next <= S_STATE_INTERM;
req_1(0) <= '1';
when S_STATE_INTERM =>
req_1(0) <= '1';
src_rdy_1(0) <= '1';
to_0_data <= (others => '0');
if s_0_counter = 15 then
s_0_counter_next <= 0;
send_to_0_state_next <= S_STATE_WAIT;
eof_1(0) <= '1';
else
s_0_counter_next <= s_0_counter + 1;
end if;
when others =>
send_to_0_state_next <= S_STATE_INIT;
end case;
end process;
send_to_1 : process(start_to_1, send_to_1_state, s_1_counter, grant_1)
begin
src_rdy_1(1) <= '0';
to_1_data <= (others => '0');
sof_1(1) <= '0';
eof_1(1) <= '0';
req_1(1) <= '0';
send_to_1_state_next <= send_to_1_state;
s_1_counter_next <= s_1_counter;
case send_to_1_state is
when S_STATE_INIT =>
send_to_1_state_next <= S_STATE_WAIT;
s_1_counter_next <= 0;
when S_STATE_WAIT =>
if start_to_1 = '1' then
send_to_1_state_next <= S_STATE_LOCK;
end if;
when S_STATE_LOCK =>
req_1(1) <= '1';
if grant_1(1) = '0' then
send_to_1_state_next <= S_STATE_LOCK;
else
send_to_1_state_next <= S_STATE_SEND_FIRST;
end if;
when S_STATE_SEND_FIRST =>
src_rdy_1(1) <= '1';
sof_1(1) <= '1';
to_1_data <= (others => '1');
s_1_counter_next <= s_1_counter + 1;
send_to_1_state_next <= S_STATE_INTERM;
req_1(1) <= '1';
when S_STATE_INTERM =>
req_1(1) <= '1';
src_rdy_1(1) <= '1';
to_1_data <= (others => '0');
if s_1_counter = 15 then
s_1_counter_next <= 0;
send_to_1_state_next <= S_STATE_WAIT;
eof_1(1) <= '1';
else
s_1_counter_next <= s_1_counter + 1;
end if;
when others =>
send_to_1_state_next <= S_STATE_INIT;
end case;
end process;
send_to_2 : process(start_to_2, send_to_2_state, s_2_counter, grant_1)
begin
src_rdy_1(2) <= '0';
to_2_data <= (others => '0');
sof_1(2) <= '0';
eof_1(2) <= '0';
req_1(2) <= '0';
send_to_2_state_next <= send_to_2_state;
s_2_counter_next <= s_2_counter;
case send_to_2_state is
when S_STATE_INIT =>
send_to_2_state_next <= S_STATE_WAIT;
s_2_counter_next <= 0;
when S_STATE_WAIT =>
if start_to_2 = '1' then
send_to_2_state_next <= S_STATE_LOCK;
end if;
when S_STATE_LOCK =>
req_1(2) <= '1';
if grant_1(2) = '0' then
send_to_2_state_next <= S_STATE_LOCK;
else
send_to_2_state_next <= S_STATE_SEND_FIRST;
end if;
when S_STATE_SEND_FIRST =>
src_rdy_1(2) <= '1';
sof_1(2) <= '1';
to_2_data <= (others => '1');
s_2_counter_next <= s_2_counter + 1;
send_to_2_state_next <= S_STATE_INTERM;
req_1(2) <= '1';
when S_STATE_INTERM =>
req_1(2) <= '1';
src_rdy_1(2) <= '1';
to_2_data <= (others => '0');
if s_2_counter = 15 then
s_2_counter_next <= 0;
send_to_2_state_next <= S_STATE_WAIT;
eof_1(2) <= '1';
else
s_2_counter_next <= s_2_counter + 1;
end if;
when others =>
send_to_2_state_next <= S_STATE_INIT;
end case;
end process;
-- memzing process
-- updates all the registers
proces_mem : process(clk, reset)
begin
if reset = '1' then
send_to_0_state <= S_STATE_INIT;
s_0_counter <= 0;
send_to_1_state <= S_STATE_INIT;
s_1_counter <= 0;
send_to_2_state <= S_STATE_INIT;
s_2_counter <= 0;
receive_state <= R_STATE_INIT;
received_counter <= 0;
elsif rising_edge(clk) then
send_to_0_state <= send_to_0_state_next;
s_0_counter <= s_0_counter_next;
send_to_1_state <= send_to_1_state_next;
s_1_counter <= s_1_counter_next;
send_to_2_state <= send_to_2_state_next;
s_2_counter <= s_2_counter_next;
receive_state <= receive_state_next;
received_counter <= received_counter_next;
end if;
end process;
-- OS synchronization state machine
-- this has to have this special format!
state_proc : process(clk, reset)
variable success : boolean;
variable done : boolean;
variable sw_command : std_logic_vector(0 to C_OSIF_DATA_WIDTH - 1);
begin
if reset = '1' then
reconos_reset_with_signature(o_osif, i_osif, X"ABCDEF01");
os_sync_state <= STATE_INIT;
start_to_0 <= '0';
start_to_1 <= '0';
start_to_2 <= '0';
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case os_sync_state is
when STATE_INIT =>
os_sync_state <= STATE_GET_COMMAND;
start_to_0 <= '0';
start_to_1 <= '0';
start_to_2 <= '0';
when STATE_SEND_ANSWER =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MBOX_HANDLE_HW_SW,
std_logic_vector(to_unsigned(received_counter,C_OSIF_DATA_WIDTH)));
if done then
os_sync_state <= STATE_GET_COMMAND;
end if;
when STATE_GET_COMMAND =>
reconos_mbox_get(done, success, o_osif, i_osif, C_MBOX_HANDLE_SW_HW, sw_command);
if done and success then
os_sync_state <= STATE_DECODE;
end if;
when STATE_DECODE =>
--default: command not known
os_sync_state <= STATE_GET_COMMAND;
-- element 0 indicates whether this thread should send to slot 0,
-- element 1 indicates whether this thread should send to slot 1,
-- element 6 indicates whether the receive counter from the bus interface
-- should be reported
if sw_command(6) = '1' then
os_sync_state <= STATE_SEND_ANSWER;
else
if sw_command(0) = '1' then
start_to_0 <= '1';
else
start_to_0 <= '0';
end if;
if sw_command(1) = '1' then
start_to_1 <= '1';
else
start_to_1 <= '0';
end if;
if sw_command(2) = '1' then
start_to_2 <= '1';
else
start_to_2 <= '0';
end if;
end if;
when others =>
os_sync_state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
7a384bfce6f008f8d046ebaf5f387577
| 0.568172 | 2.658868 | false | false | false | false |
iti-luebeck/RTeasy1
|
src/main/resources/vhdltmpl/mult.vhd
| 3 | 27,202 |
-- VHDL model of UNNAMED
-- generated by RTeasy
PACKAGE rteasy_functions IS
FUNCTION bool_signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN boolean;
FUNCTION signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_le (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_gt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_ge (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_eq (a, b : std_logic_vector) RETURN std_logic_vector;
FUNCTION signed_ne (a, b : std_logic_vector) RETURN std_logic_vector;
END rteasy_functions;
PACKAGE BODY rteasy_functions IS
-- signed relative comparison functions
FUNCTION bool_signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN boolean IS
BEGIN
IF a(sign_index) = b(sign_index) THEN
RETURN a < b;
ELSE
RETURN a(sign_index) = '1';
END IF;
END bool_signed_lt;
FUNCTION signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF bool_signed_lt(a,b,sign_index) THEN RETURN "1";
ELSE RETURN "0";
END IF;
END signed_lt;
FUNCTION signed_le (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF (a = b) OR bool_signed_lt(a,b,sign_index) THEN RETURN "1";
ELSE RETURN "0";
END IF;
END signed_le;
FUNCTION signed_gt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF (a = b) OR bool_signed_lt(a,b,sign_index) THEN RETURN "0";
ELSE RETURN "1";
END IF;
END signed_gt;
FUNCTION signed_ge (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector IS
BEGIN
IF bool_signed_lt(a,b,sign_index) THEN RETURN "0";
ELSE RETURN "1";
END IF;
END signed_ge;
FUNCTION signed_eq (a, b : std_logic_vector) RETURN std_logic_vector IS
BEGIN
IF a = b THEN RETURN "1";
ELSE RETURN "0";
END IF;
END signed_eq;
FUNCTION signed_ne (a, b : std_logic_vector) RETURN std_logic_vector IS
BEGIN
IF a = b THEN RETURN "0";
ELSE RETURN "1";
END IF;
END signed_ne;
END rteasy_functions;
-- generic components
-- D-Flip-Flop register component
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dff_reg IS
GENERIC(width : positive; triggering_edge : bit);
PORT(
CLK, RESET : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END dff_reg;
ARCHITECTURE behavioural OF dff_reg IS
BEGIN
gen_rising_edge: IF triggering_edge='1' GENERATE
reg_proc_rising: PROCESS(CLK,RESET)
BEGIN
IF RESET='1' THEN OUTPUT <= (OTHERS => '0');
ELSIF rising_edge(CLK) THEN OUTPUT <= INPUT; END IF;
END PROCESS;
END GENERATE;
gen_falling_edge: IF triggering_edge='0' GENERATE
reg_proc_falling: PROCESS(CLK,RESET)
BEGIN
IF RESET='1' THEN OUTPUT <= (OTHERS => '0');
ELSIF falling_edge(CLK) THEN OUTPUT <= INPUT; END IF;
END PROCESS;
END GENERATE;
END behavioural;
-- Tri-State driver component
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY tristate IS
GENERIC(width : positive);
PORT(
ENABLE : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END tristate;
ARCHITECTURE primitive OF tristate IS
BEGIN
OUTPUT <= INPUT WHEN ENABLE='1' ELSE (OTHERS => 'Z');
END primitive;
-- CONTROL UNIT
-- combinatorial circuit for state transition function
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_cu_statetrans_net IS
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
NEXTSTATE : OUT std_logic_vector(1 DOWNTO 0)
);
CONSTANT endstate : std_logic_vector(1 DOWNTO 0) := "11";
END UNNAMED_cu_statetrans_net;
ARCHITECTURE behavioural OF UNNAMED_cu_statetrans_net IS
BEGIN
statetrans: PROCESS(I,STATE)
BEGIN
CASE STATE IS
WHEN "00" => -- BEGIN:
NEXTSTATE <= "01";
WHEN "01" =>
NEXTSTATE <= "10";
WHEN "10" => -- LOOP:
IF I(0)='1' THEN -- if FAKTOR <> 0 then goto LOOP fi
NEXTSTATE <= "10";
ELSE
NEXTSTATE <= endstate;
END IF;
WHEN OTHERS =>
NEXTSTATE <= endstate;
END CASE;
END PROCESS;
END behavioural;
-- combinatorial circuit for output function
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_cu_output_net IS
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
C : OUT std_logic_vector(0 TO 5)
);
END UNNAMED_cu_output_net;
ARCHITECTURE behavioural OF UNNAMED_cu_output_net IS
BEGIN
output: PROCESS(I,STATE)
BEGIN
CASE STATE IS
WHEN "00" => -- BEGIN:
C(0) <= '1';
C(1) <= '1';
C(2) <= '0';
C(3) <= '0';
C(4) <= '0';
C(5) <= '0';
WHEN "01" =>
C(0) <= '0';
C(1) <= '0';
C(2) <= '1';
C(3) <= '0';
C(4) <= '0';
C(5) <= '0';
WHEN "10" => -- LOOP:
C(0) <= '0';
C(1) <= '0';
C(2) <= '0';
-- if FAKTOR <> 0 then ERG <- ERG + A fi
C(3) <= I(0);
-- if FAKTOR <> 0 then FAKTOR <- FAKTOR - 1 fi
C(4) <= I(0);
-- if not FAKTOR <> 0 then OUTBUS <- ERG fi
C(5) <= NOT (I(0));
WHEN OTHERS =>
C <= (OTHERS => '0');
END CASE;
END PROCESS;
END behavioural;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_cu IS
PORT(
CLK, RESET : IN std_logic;
C : OUT std_logic_vector(0 TO 5);
I : IN std_logic_vector(0 TO 0)
);
END UNNAMED_cu;
ARCHITECTURE struct OF UNNAMED_cu IS
SIGNAL I_BUFFERED : std_logic_vector(0 TO 0);
SIGNAL C_SIG : std_logic_vector(0 TO 5);
SIGNAL STATE, NEXTSTATE : std_logic_vector(1 DOWNTO 0);
COMPONENT dff_reg
GENERIC(width : positive; triggering_edge : bit);
PORT(
CLK, RESET : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : dff_reg USE ENTITY WORK.dff_reg(behavioural);
COMPONENT UNNAMED_cu_statetrans_net
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
NEXTSTATE : OUT std_logic_vector(1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_cu_statetrans_net USE ENTITY
WORK.UNNAMED_cu_statetrans_net(behavioural);
COMPONENT UNNAMED_cu_output_net
PORT(
I : IN std_logic_vector(0 TO 0);
STATE : IN std_logic_vector(1 DOWNTO 0);
C : OUT std_logic_vector(0 TO 5)
);
END COMPONENT;
FOR ALL : UNNAMED_cu_output_net USE ENTITY
WORK.UNNAMED_cu_output_net(behavioural);
BEGIN
-- instantiate condition buffer register
condbuf_register: dff_reg
GENERIC MAP(width => 1, triggering_edge => '1')
PORT MAP(CLK => CLK, RESET => RESET, INPUT => I, OUTPUT => I_BUFFERED);
-- instantiate state register
state_register: dff_reg
GENERIC MAP(width => 2, triggering_edge => '1')
PORT MAP(CLK => CLK, RESET => RESET, INPUT => NEXTSTATE, OUTPUT => STATE);
-- instantiate circuit for state transition function
statetrans: UNNAMED_cu_statetrans_net
PORT MAP(I => I_BUFFERED, STATE => STATE, NEXTSTATE => NEXTSTATE);
-- instantiate circuit for output function driving control signals
output: UNNAMED_cu_output_net
PORT MAP(I => I_BUFFERED, STATE => STATE, C => C_SIG);
-- only drive control signals when CLK='0' to avoid driving hazards to
-- operation unit
C <= C_SIG WHEN CLK='0' ELSE (OTHERS => '0');
END struct;
-- OPERATION UNIT
-- circuits realizing register-transfer operations
-- realization of RT operation A <- INBUS
-- triggered by control signal C(0)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C0_circuit IS
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C0_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C0_circuit IS
BEGIN
-- INBUS
OUTPUT <= bus_INBUS_0_7(0 TO 7);
END primitive;
-- realization of RT operation ERG <- 0
-- triggered by control signal C(1)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C1_circuit IS
PORT(
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C1_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C1_circuit IS
BEGIN
-- 0
OUTPUT <= "00000000";
END primitive;
-- realization of RT operation FAKTOR <- INBUS
-- triggered by control signal C(2)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C2_circuit IS
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C2_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C2_circuit IS
BEGIN
-- INBUS
OUTPUT <= bus_INBUS_0_7(0 TO 7);
END primitive;
-- realization of RT operation ERG <- ERG + A
-- triggered by control signal C(3)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C3_circuit IS
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
reg_A_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END UNNAMED_rtop_C3_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C3_circuit IS
BEGIN
-- ERG + A
OUTPUT <= ("0" & reg_ERG_out_0_7(0 TO 7)) + ("0" & reg_A_out_0_7(0 TO 7));
END primitive;
-- realization of RT operation FAKTOR <- FAKTOR - 1
-- triggered by control signal C(4)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C4_circuit IS
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END UNNAMED_rtop_C4_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C4_circuit IS
BEGIN
-- FAKTOR - 1
OUTPUT <= ("0" & reg_FAKTOR_out_0_7(0 TO 7)) + ((not ("000000001")) + "000000001");
END primitive;
-- realization of RT operation OUTBUS <- ERG
-- triggered by control signal C(5)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_rtop_C5_circuit IS
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END UNNAMED_rtop_C5_circuit;
ARCHITECTURE primitive OF UNNAMED_rtop_C5_circuit IS
BEGIN
-- ERG
OUTPUT <= reg_ERG_out_0_7(0 TO 7);
END primitive;
-- circuits realizing conditions
-- realization of condition FAKTOR <> 0
-- driving condition signal I(0)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rteasy_functions.ALL;
ENTITY UNNAMED_cond_I0_circuit IS
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(0 DOWNTO 0)
);
END UNNAMED_cond_I0_circuit;
ARCHITECTURE primitive OF UNNAMED_cond_I0_circuit IS
BEGIN
-- FAKTOR <> 0
OUTPUT <= signed_ne(("0" & reg_FAKTOR_out_0_7(0 TO 7)), ("000000000"), 8);
END primitive;
-- register logic circuits
-- register logic for A
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY reg_A_logic_circuit IS
PORT(
C0 : IN std_logic;
rtop_C0_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END reg_A_logic_circuit;
ARCHITECTURE primitive OF reg_A_logic_circuit IS
BEGIN
TO_reg(0) <= rtop_C0_out_7_0(7) WHEN C0 = '1'
ELSE FROM_reg(0);
TO_reg(1) <= rtop_C0_out_7_0(6) WHEN C0 = '1'
ELSE FROM_reg(1);
TO_reg(2) <= rtop_C0_out_7_0(5) WHEN C0 = '1'
ELSE FROM_reg(2);
TO_reg(3) <= rtop_C0_out_7_0(4) WHEN C0 = '1'
ELSE FROM_reg(3);
TO_reg(4) <= rtop_C0_out_7_0(3) WHEN C0 = '1'
ELSE FROM_reg(4);
TO_reg(5) <= rtop_C0_out_7_0(2) WHEN C0 = '1'
ELSE FROM_reg(5);
TO_reg(6) <= rtop_C0_out_7_0(1) WHEN C0 = '1'
ELSE FROM_reg(6);
TO_reg(7) <= rtop_C0_out_7_0(0) WHEN C0 = '1'
ELSE FROM_reg(7);
END primitive;
-- register logic for ERG
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY reg_ERG_logic_circuit IS
PORT(
C1, C3 : IN std_logic;
rtop_C1_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C3_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END reg_ERG_logic_circuit;
ARCHITECTURE primitive OF reg_ERG_logic_circuit IS
BEGIN
TO_reg(0) <= rtop_C1_out_7_0(7) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(7) WHEN C3 = '1'
ELSE FROM_reg(0);
TO_reg(1) <= rtop_C1_out_7_0(6) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(6) WHEN C3 = '1'
ELSE FROM_reg(1);
TO_reg(2) <= rtop_C1_out_7_0(5) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(5) WHEN C3 = '1'
ELSE FROM_reg(2);
TO_reg(3) <= rtop_C1_out_7_0(4) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(4) WHEN C3 = '1'
ELSE FROM_reg(3);
TO_reg(4) <= rtop_C1_out_7_0(3) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(3) WHEN C3 = '1'
ELSE FROM_reg(4);
TO_reg(5) <= rtop_C1_out_7_0(2) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(2) WHEN C3 = '1'
ELSE FROM_reg(5);
TO_reg(6) <= rtop_C1_out_7_0(1) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(1) WHEN C3 = '1'
ELSE FROM_reg(6);
TO_reg(7) <= rtop_C1_out_7_0(0) WHEN C1 = '1'
ELSE rtop_C3_out_7_0(0) WHEN C3 = '1'
ELSE FROM_reg(7);
END primitive;
-- register logic for FAKTOR
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY reg_FAKTOR_logic_circuit IS
PORT(
C2, C4 : IN std_logic;
rtop_C2_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C4_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END reg_FAKTOR_logic_circuit;
ARCHITECTURE primitive OF reg_FAKTOR_logic_circuit IS
BEGIN
TO_reg(0) <= rtop_C2_out_7_0(7) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(7) WHEN C4 = '1'
ELSE FROM_reg(0);
TO_reg(1) <= rtop_C2_out_7_0(6) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(6) WHEN C4 = '1'
ELSE FROM_reg(1);
TO_reg(2) <= rtop_C2_out_7_0(5) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(5) WHEN C4 = '1'
ELSE FROM_reg(2);
TO_reg(3) <= rtop_C2_out_7_0(4) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(4) WHEN C4 = '1'
ELSE FROM_reg(3);
TO_reg(4) <= rtop_C2_out_7_0(3) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(3) WHEN C4 = '1'
ELSE FROM_reg(4);
TO_reg(5) <= rtop_C2_out_7_0(2) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(2) WHEN C4 = '1'
ELSE FROM_reg(5);
TO_reg(6) <= rtop_C2_out_7_0(1) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(1) WHEN C4 = '1'
ELSE FROM_reg(6);
TO_reg(7) <= rtop_C2_out_7_0(0) WHEN C2 = '1'
ELSE rtop_C4_out_7_0(0) WHEN C4 = '1'
ELSE FROM_reg(7);
END primitive;
-- bus zero driver logic circuits
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- bus zero driver logic for OUTBUS
ENTITY bus_OUTBUS_zero_driver_logic_circuit IS
PORT(
C5 : IN std_logic; -- driving control signals
TO_bus : OUT std_logic_vector (0 TO 7)
);
END bus_OUTBUS_zero_driver_logic_circuit;
ARCHITECTURE primitive OF bus_OUTBUS_zero_driver_logic_circuit IS
BEGIN
TO_bus(0) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(1) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(2) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(3) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(4) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(5) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(6) <= '0' WHEN NOT C5='1' ELSE 'Z';
TO_bus(7) <= '0' WHEN NOT C5='1' ELSE 'Z';
END primitive;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- bus zero driver logic for INBUS
ENTITY bus_INBUS_zero_driver_logic_circuit IS
PORT(
TO_bus : OUT std_logic_vector (0 TO 7)
);
END bus_INBUS_zero_driver_logic_circuit;
ARCHITECTURE primitive OF bus_INBUS_zero_driver_logic_circuit IS
BEGIN
TO_bus(0) <= '0';
TO_bus(1) <= '0';
TO_bus(2) <= '0';
TO_bus(3) <= '0';
TO_bus(4) <= '0';
TO_bus(5) <= '0';
TO_bus(6) <= '0';
TO_bus(7) <= '0';
END primitive;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED_ou IS
PORT(
CLK, RESET : IN std_logic;
C : IN std_logic_vector(0 TO 5);
I : OUT std_logic_vector(0 TO 0)
);
END UNNAMED_ou;
ARCHITECTURE struct OF UNNAMED_ou IS
-- signal declarations
SIGNAL CLK_SIG, RESET_SIG : std_logic;
SIGNAL C_SIG : std_logic_vector(0 TO 5);
SIGNAL I0 : std_logic_vector(0 DOWNTO 0);
SIGNAL bus_OUTBUS : std_logic_vector (0 TO 7);
SIGNAL bus_INBUS : std_logic_vector (0 TO 7);
SIGNAL reg_A_in : std_logic_vector (0 TO 7) := (OTHERS => 'L');
SIGNAL reg_A_out : std_logic_vector (0 TO 7) := (OTHERS => '0');
SIGNAL reg_ERG_in : std_logic_vector (0 TO 7) := (OTHERS => 'L');
SIGNAL reg_ERG_out : std_logic_vector (0 TO 7) := (OTHERS => '0');
SIGNAL reg_FAKTOR_in : std_logic_vector (0 TO 7) := (OTHERS => 'L');
SIGNAL reg_FAKTOR_out : std_logic_vector (0 TO 7) := (OTHERS => '0');
-- D-flipflop register component declaration
COMPONENT dff_reg
GENERIC(width : positive; triggering_edge : bit);
PORT(
CLK, RESET : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : dff_reg USE ENTITY WORK.dff_reg(behavioural);
-- register logic component declarations
COMPONENT reg_A_logic_circuit
PORT(
C0 : IN std_logic;
rtop_C0_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : reg_A_logic_circuit USE ENTITY WORK.reg_A_logic_circuit(primitive);
COMPONENT reg_ERG_logic_circuit
PORT(
C1, C3 : IN std_logic;
rtop_C1_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C3_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : reg_ERG_logic_circuit USE ENTITY WORK.reg_ERG_logic_circuit(primitive);
COMPONENT reg_FAKTOR_logic_circuit
PORT(
C2, C4 : IN std_logic;
rtop_C2_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
rtop_C4_out_7_0 : IN std_logic_vector(7 DOWNTO 0);
FROM_reg : IN std_logic_vector (0 TO 7);
TO_reg : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : reg_FAKTOR_logic_circuit USE ENTITY WORK.reg_FAKTOR_logic_circuit(primitive);
-- bus zero driver logic component declarations
COMPONENT bus_OUTBUS_zero_driver_logic_circuit
PORT(
C5 : IN std_logic; -- driving control signals
TO_bus : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : bus_OUTBUS_zero_driver_logic_circuit USE ENTITY WORK.bus_OUTBUS_zero_driver_logic_circuit(primitive);
COMPONENT bus_INBUS_zero_driver_logic_circuit
PORT(
TO_bus : OUT std_logic_vector (0 TO 7)
);
END COMPONENT;
FOR ALL : bus_INBUS_zero_driver_logic_circuit USE ENTITY WORK.bus_INBUS_zero_driver_logic_circuit(primitive);
COMPONENT tristate
GENERIC(width : positive);
PORT(
ENABLE : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : tristate USE ENTITY WORK.tristate(primitive);
-- function for input forcing (to 0 and 1)
FUNCTION forceSL (b : std_logic) RETURN std_logic IS
BEGIN
CASE b IS
WHEN '1'|'H' => RETURN '1';
WHEN OTHERS => RETURN '0';
END CASE;
END forceSL;
-- declarations for register-transfer circuits and signals
-- RT operation A <- INBUS
-- triggered by control signal C(0)
SIGNAL rtop_C0_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C0_circuit
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C0_circuit USE ENTITY WORK.UNNAMED_rtop_C0_circuit(primitive);
-- RT operation ERG <- 0
-- triggered by control signal C(1)
SIGNAL rtop_C1_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C1_circuit
PORT(
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C1_circuit USE ENTITY WORK.UNNAMED_rtop_C1_circuit(primitive);
-- RT operation FAKTOR <- INBUS
-- triggered by control signal C(2)
SIGNAL rtop_C2_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C2_circuit
PORT(
bus_INBUS_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C2_circuit USE ENTITY WORK.UNNAMED_rtop_C2_circuit(primitive);
-- RT operation ERG <- ERG + A
-- triggered by control signal C(3)
SIGNAL rtop_C3_out : std_logic_vector(8 DOWNTO 0);
COMPONENT UNNAMED_rtop_C3_circuit
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
reg_A_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C3_circuit USE ENTITY WORK.UNNAMED_rtop_C3_circuit(primitive);
-- RT operation FAKTOR <- FAKTOR - 1
-- triggered by control signal C(4)
SIGNAL rtop_C4_out : std_logic_vector(8 DOWNTO 0);
COMPONENT UNNAMED_rtop_C4_circuit
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(8 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C4_circuit USE ENTITY WORK.UNNAMED_rtop_C4_circuit(primitive);
-- RT operation OUTBUS <- ERG
-- triggered by control signal C(5)
SIGNAL rtop_C5_out : std_logic_vector(7 DOWNTO 0);
COMPONENT UNNAMED_rtop_C5_circuit
PORT(
reg_ERG_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_rtop_C5_circuit USE ENTITY WORK.UNNAMED_rtop_C5_circuit(primitive);
-- COMPONENT declarations for condition circuits
-- condition FAKTOR <> 0
-- driving condition signal I(0)
COMPONENT UNNAMED_cond_I0_circuit
PORT(
reg_FAKTOR_out_0_7 : IN std_logic_vector(0 TO 7);
OUTPUT : OUT std_logic_vector(0 DOWNTO 0)
);
END COMPONENT;
FOR ALL : UNNAMED_cond_I0_circuit USE ENTITY WORK.UNNAMED_cond_I0_circuit(primitive);
BEGIN
CLK_SIG <= CLK; RESET_SIG <= RESET; C_SIG <= C;
-- register logic instantiations
-- register A
-- component instantiation for register A
reg_A: dff_reg
GENERIC MAP(triggering_edge => '1', width => 8)
PORT MAP(CLK => CLK_SIG, RESET => RESET_SIG,
INPUT => reg_A_in,
OUTPUT => reg_A_out);
reg_A_logic: reg_A_logic_circuit
PORT MAP(
C0 => C_SIG(0),
rtop_C0_out_7_0 => rtop_C0_out(7 DOWNTO 0),
FROM_reg => reg_A_out,
TO_reg => reg_A_in);
-- register ERG
-- component instantiation for register ERG
reg_ERG: dff_reg
GENERIC MAP(triggering_edge => '1', width => 8)
PORT MAP(CLK => CLK_SIG, RESET => RESET_SIG,
INPUT => reg_ERG_in,
OUTPUT => reg_ERG_out);
reg_ERG_logic: reg_ERG_logic_circuit
PORT MAP(
C1 => C_SIG(1),
C3 => C_SIG(3),
rtop_C1_out_7_0 => rtop_C1_out(7 DOWNTO 0),
rtop_C3_out_7_0 => rtop_C3_out(7 DOWNTO 0),
FROM_reg => reg_ERG_out,
TO_reg => reg_ERG_in);
-- register FAKTOR
-- component instantiation for register FAKTOR
reg_FAKTOR: dff_reg
GENERIC MAP(triggering_edge => '1', width => 8)
PORT MAP(CLK => CLK_SIG, RESET => RESET_SIG,
INPUT => reg_FAKTOR_in,
OUTPUT => reg_FAKTOR_out);
reg_FAKTOR_logic: reg_FAKTOR_logic_circuit
PORT MAP(
C2 => C_SIG(2),
C4 => C_SIG(4),
rtop_C2_out_7_0 => rtop_C2_out(7 DOWNTO 0),
rtop_C4_out_7_0 => rtop_C4_out(7 DOWNTO 0),
FROM_reg => reg_FAKTOR_out,
TO_reg => reg_FAKTOR_in);
-- bus zero driver logic logic instantiations
bus_OUTBUS_zero_driver_logic: bus_OUTBUS_zero_driver_logic_circuit
PORT MAP(
C5 => C_SIG(5),
TO_bus => bus_OUTBUS);
bus_INBUS_zero_driver_logic: bus_INBUS_zero_driver_logic_circuit
PORT MAP(
TO_bus => bus_INBUS);
-- instantiations for register-transfer circuits
-- RT operation A <- INBUS
-- triggered by control signal C(0)
rtop_C0: UNNAMED_rtop_C0_circuit
PORT MAP(
bus_INBUS_0_7 => bus_INBUS(0 TO 7),
OUTPUT => rtop_C0_out);
-- RT operation ERG <- 0
-- triggered by control signal C(1)
rtop_C1: UNNAMED_rtop_C1_circuit
PORT MAP(
OUTPUT => rtop_C1_out);
-- RT operation FAKTOR <- INBUS
-- triggered by control signal C(2)
rtop_C2: UNNAMED_rtop_C2_circuit
PORT MAP(
bus_INBUS_0_7 => bus_INBUS(0 TO 7),
OUTPUT => rtop_C2_out);
-- RT operation ERG <- ERG + A
-- triggered by control signal C(3)
rtop_C3: UNNAMED_rtop_C3_circuit
PORT MAP(
reg_ERG_out_0_7 => reg_ERG_out(0 TO 7),
reg_A_out_0_7 => reg_A_out(0 TO 7),
OUTPUT => rtop_C3_out);
-- RT operation FAKTOR <- FAKTOR - 1
-- triggered by control signal C(4)
rtop_C4: UNNAMED_rtop_C4_circuit
PORT MAP(
reg_FAKTOR_out_0_7 => reg_FAKTOR_out(0 TO 7),
OUTPUT => rtop_C4_out);
-- RT operation OUTBUS <- ERG
-- triggered by control signal C(5)
rtop_C5: UNNAMED_rtop_C5_circuit
PORT MAP(
reg_ERG_out_0_7 => reg_ERG_out(0 TO 7),
OUTPUT => rtop_C5_out);
tristate_OUTBUS_0_7_C5: tristate
GENERIC MAP(width => 8)
PORT MAP(
ENABLE => C(5),
INPUT => rtop_C5_out(7 DOWNTO 0),
OUTPUT => bus_OUTBUS(0 TO 7));
-- instantiations of condition circuits
-- condition FAKTOR <> 0
-- driving condition signal I(0)
I(0) <= I0(0);
cond_I0: UNNAMED_cond_I0_circuit
PORT MAP(
reg_FAKTOR_out_0_7 => reg_FAKTOR_in(0 TO 7),
OUTPUT => I0);
END struct;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY UNNAMED IS
PORT(
CLK, RESET : IN std_logic
);
END UNNAMED;
ARCHITECTURE struct OF UNNAMED IS
SIGNAL CLK_SIGNAL, RESET_SIGNAL : std_logic;
SIGNAL C : std_logic_vector(0 to 5);
SIGNAL I : std_logic_vector(0 to 0);
COMPONENT UNNAMED_cu
PORT (
CLK, RESET : IN std_logic;
C : OUT std_logic_vector(0 to 5);
I : IN std_logic_vector(0 to 0)
);
END COMPONENT;
FOR ALL : UNNAMED_cu USE ENTITY WORK.UNNAMED_cu(struct);
COMPONENT UNNAMED_ou
PORT (
CLK, RESET : IN std_logic;
C : IN std_logic_vector(0 to 5);
I : OUT std_logic_vector(0 to 0)
);
END COMPONENT;
FOR ALL : UNNAMED_ou USE ENTITY WORK.UNNAMED_ou(struct);
BEGIN
CLK_SIGNAL <= CLK;
RESET_SIGNAL <= RESET;
Control_Unit: UNNAMED_cu
PORT MAP(
CLK => CLK_SIGNAL,
RESET => RESET_SIGNAL,
C => C,
I => I
);
Operation_Unit: UNNAMED_ou
PORT MAP(
CLK => CLK_SIGNAL,
RESET => RESET_SIGNAL,
C => C,
I => I
);
END struct;
|
bsd-3-clause
|
88012c2fa22be4ad3e3db5f5bd0800a6
| 0.629255 | 2.986605 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.srcs/sources_1/ip/FontROM/sim/FontROM.vhd
| 1 | 5,703 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dist_mem_gen_v8_0_9;
USE dist_mem_gen_v8_0_9.dist_mem_gen_v8_0_9;
ENTITY FontROM IS
PORT (
a : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END FontROM;
ARCHITECTURE FontROM_arch OF FontROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF FontROM_arch: ARCHITECTURE IS "yes";
COMPONENT dist_mem_gen_v8_0_9 IS
GENERIC (
C_FAMILY : STRING;
C_ADDR_WIDTH : INTEGER;
C_DEFAULT_DATA : STRING;
C_DEPTH : INTEGER;
C_HAS_CLK : INTEGER;
C_HAS_D : INTEGER;
C_HAS_DPO : INTEGER;
C_HAS_DPRA : INTEGER;
C_HAS_I_CE : INTEGER;
C_HAS_QDPO : INTEGER;
C_HAS_QDPO_CE : INTEGER;
C_HAS_QDPO_CLK : INTEGER;
C_HAS_QDPO_RST : INTEGER;
C_HAS_QDPO_SRST : INTEGER;
C_HAS_QSPO : INTEGER;
C_HAS_QSPO_CE : INTEGER;
C_HAS_QSPO_RST : INTEGER;
C_HAS_QSPO_SRST : INTEGER;
C_HAS_SPO : INTEGER;
C_HAS_WE : INTEGER;
C_MEM_INIT_FILE : STRING;
C_ELABORATION_DIR : STRING;
C_MEM_TYPE : INTEGER;
C_PIPELINE_STAGES : INTEGER;
C_QCE_JOINED : INTEGER;
C_QUALIFY_WE : INTEGER;
C_READ_MIF : INTEGER;
C_REG_A_D_INPUTS : INTEGER;
C_REG_DPRA_INPUT : INTEGER;
C_SYNC_ENABLE : INTEGER;
C_WIDTH : INTEGER;
C_PARSER_TYPE : INTEGER
);
PORT (
a : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
i_ce : IN STD_LOGIC;
qspo_ce : IN STD_LOGIC;
qdpo_ce : IN STD_LOGIC;
qdpo_clk : IN STD_LOGIC;
qspo_rst : IN STD_LOGIC;
qdpo_rst : IN STD_LOGIC;
qspo_srst : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
qspo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
qdpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT dist_mem_gen_v8_0_9;
BEGIN
U0 : dist_mem_gen_v8_0_9
GENERIC MAP (
C_FAMILY => "artix7",
C_ADDR_WIDTH => 14,
C_DEFAULT_DATA => "0",
C_DEPTH => 16384,
C_HAS_CLK => 0,
C_HAS_D => 0,
C_HAS_DPO => 0,
C_HAS_DPRA => 0,
C_HAS_I_CE => 0,
C_HAS_QDPO => 0,
C_HAS_QDPO_CE => 0,
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_RST => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_QSPO => 0,
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QSPO_SRST => 0,
C_HAS_SPO => 1,
C_HAS_WE => 0,
C_MEM_INIT_FILE => "FontROM.mif",
C_ELABORATION_DIR => "./",
C_MEM_TYPE => 0,
C_PIPELINE_STAGES => 0,
C_QCE_JOINED => 0,
C_QUALIFY_WE => 0,
C_READ_MIF => 1,
C_REG_A_D_INPUTS => 0,
C_REG_DPRA_INPUT => 0,
C_SYNC_ENABLE => 1,
C_WIDTH => 1,
C_PARSER_TYPE => 1
)
PORT MAP (
a => a,
d => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
dpra => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)),
clk => '0',
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qspo_srst => '0',
qdpo_srst => '0',
spo => spo
);
END FontROM_arch;
|
mit
|
3616cf3eb49934967652ab597f2e7d0f
| 0.62511 | 3.425225 | false | false | false | false |
luebbers/reconos
|
core/pcores/xps_osif_v2_01_a/hdl/vhdl/mem_plb46.vhd
| 1 | 31,388 |
--!
--! \file mem_plb46.vhd
--!
--! Memory bus interface for the 64-bit PLB v34.
--!
--! \author Enno Luebbers <[email protected]>
--! \date 08.12.2008
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 08.12.2008 Enno Luebbers File created.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
library xps_osif_v2_01_a;
use xps_osif_v2_01_a.all;
entity mem_plb46 is
generic
(
-- Bus protocol parameters
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
--C_NUM_CE : integer := 2;
C_BURST_AWIDTH : integer := 13 -- 1024 x 64 Bit = 8192 Bytes = 2^13 Bytes
);
port
(
clk : in std_logic;
reset : in std_logic;
-- data interface ---------------------------
-- burst mem interface
o_burstAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_burstData : out std_logic_vector(0 to C_PLB_DWIDTH-1);
i_burstData : in std_logic_vector(0 to C_PLB_DWIDTH-1);
o_burstWE : out std_logic;
o_burstBE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
-- single word data input/output
i_singleData : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- osif2bus
o_singleData : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- bus2osif
-- control interface ------------------------
-- addresses for master transfers
i_localAddr : in std_logic_vector(0 to C_AWIDTH-1);
i_targetAddr : in std_logic_vector(0 to C_AWIDTH-1);
-- single word transfer requests
i_singleRdReq : in std_logic;
i_singleWrReq : in std_logic;
-- burst transfer requests
i_burstRdReq : in std_logic;
i_burstWrReq : in std_logic;
i_burstLen : in std_logic_vector(0 to 11); -- number of bytes to transfer (0..4096)
-- status outputs
o_busy : out std_logic;
o_rdDone : out std_logic;
o_wrDone : out std_logic;
-- PLBv34 bus interface -----------------------------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstLastAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_MstBE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
IP2Bus_MstBurst : out std_logic;
IP2Bus_MstBusReset : out std_logic;
IP2Bus_MstBusLock : out std_logic;
IP2Bus_MstNum : out std_logic_vector(0 to 11);
IP2Bus_MstRdReq : out std_logic;
IP2Bus_MstWrReq : out std_logic;
-- LocalLink Interface
Bus2IP_MstRd_d : in std_logic_vector(0 to C_PLB_DWIDTH-1);
Bus2IP_MstRd_rem : in std_logic_vector(0 to C_PLB_DWIDTH/8-1);
Bus2IP_MstRd_sof_n : in std_logic;
Bus2IP_MstRd_eof_n : in std_logic;
Bus2IP_MstRd_src_rdy_n : in std_logic;
Bus2IP_MstRd_src_dsc_n : in std_logic;
IP2Bus_MstRd_dst_rdy_n : out std_logic;
IP2Bus_MstRd_dst_dsc_n : out std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_PLB_DWIDTH-1);
IP2Bus_MstWr_rem : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
IP2Bus_MstWr_sof_n : out std_logic;
IP2Bus_MstWr_eof_n : out std_logic;
IP2Bus_MstWr_src_rdy_n : out std_logic;
IP2Bus_MstWr_src_dsc_n : out std_logic;
Bus2IP_MstWr_dst_rdy_n : in std_logic;
Bus2IP_MstWr_dst_dsc_n : in std_logic
);
end entity mem_plb46;
architecture arch of mem_plb46 is
constant BYTES_PER_BEAT : integer := C_PLB_DWIDTH/8;
-- signals for master model command interface state machine
type CMD_CNTL_SM_TYPE is (CMD_IDLE, CMD_RUN, CMD_WAIT_FOR_DATA, CMD_DONE);
signal mst_cmd_sm_state : CMD_CNTL_SM_TYPE;
signal mst_cmd_sm_set_done : std_logic;
signal mst_cmd_sm_set_error : std_logic;
signal mst_cmd_sm_set_timeout : std_logic;
signal mst_cmd_sm_busy : std_logic;
signal mst_cmd_sm_clr_go : std_logic;
signal mst_cmd_sm_rd_req : std_logic;
signal mst_cmd_sm_wr_req : std_logic;
signal mst_cmd_sm_reset : std_logic;
signal mst_cmd_sm_bus_lock : std_logic;
signal mst_cmd_sm_ip2bus_addr : std_logic_vector(0 to C_PLB_AWIDTH-1);
signal mst_cmd_sm_ip2bus_be : std_logic_vector(0 to C_PLB_DWIDTH/8-1);
signal mst_cmd_sm_xfer_type : std_logic;
signal mst_cmd_sm_xfer_length : std_logic_vector(0 to 11);
signal mst_cmd_sm_start_rd_llink : std_logic;
signal mst_cmd_sm_start_wr_llink : std_logic;
-- signals for master model read locallink interface state machine
type RD_LLINK_SM_TYPE is (LLRD_IDLE, LLRD_GO);
signal mst_llrd_sm_state : RD_LLINK_SM_TYPE;
signal mst_llrd_sm_dst_rdy : std_logic;
-- signals for master model write locallink interface state machine
type WR_LLINK_SM_TYPE is (LLWR_IDLE, LLWR_SNGL_INIT, LLWR_SNGL, LLWR_BRST_INIT, LLWR_BRST, LLWR_BRST_LAST_BEAT);
signal mst_llwr_sm_state : WR_LLINK_SM_TYPE;
signal mst_llwr_sm_src_rdy : std_logic;
signal mst_llwr_sm_sof : std_logic;
signal mst_llwr_sm_eof : std_logic;
signal mst_llwr_byte_cnt : integer;
signal bram_offset : integer;
signal mst_fifo_valid_write_xfer : std_logic;
signal mst_fifo_valid_read_xfer : std_logic;
signal mst_fifo_valid_read_xfer_d1 : std_logic;
signal mst_xfer_length : std_logic_vector(0 to 11);
signal mst_cntl_rd_req : std_logic;
signal mst_cntl_wr_req : std_logic;
signal mst_cntl_bus_lock : std_logic;
signal mst_cntl_burst : std_logic;
signal mst_ip2bus_addr : std_logic_vector(0 to C_PLB_AWIDTH-1);
signal mst_ip2bus_be : std_logic_vector(0 to 7); -- FIXME: Hardcoded for 64 bit master
signal mst_go : std_logic;
signal xfer_cross_wrd_bndry : std_logic;
signal rolled_MstRd_d : std_logic_vector(0 to C_PLB_DWIDTH-1);
signal rolled_mst_ip2bus_be : std_logic_vector(0 to 7);
signal be_offset : integer range 0 to 7;
signal prefetch_data : std_logic_vector(0 to C_PLB_DWIDTH-1) ;
signal burstData_current : std_logic_vector(0 to C_PLB_DWIDTH-1) ;
signal prefetch_first : std_logic;
signal save_first : std_logic;
begin
-- get byte enable offset from target address
be_offset <= TO_INTEGER(ieee.numeric_std.unsigned(i_targetAddr(C_AWIDTH-3 to C_AWIDTH-1)));
mst_reg : process(Bus2IP_Clk, Bus2IP_Reset)
constant BE_32 : std_logic_vector := X"F0";
begin
if Bus2IP_Reset = '1' then
mst_xfer_length <= (others => '0');
mst_cntl_rd_req <= '0';
mst_cntl_wr_req <= '0';
mst_ip2bus_addr <= (others => '0');
mst_ip2bus_be <= (others => '0');
mst_cntl_burst <= '0';
xfer_cross_wrd_bndry <= '0';
mst_go <= '0';
elsif rising_edge(Bus2IP_Clk) then
if (i_burstRdReq = '1' or i_burstWrReq = '1') then -- if incoming burst request
mst_xfer_length <= i_burstLen(3 to 11) & "000"; -- burst length in bytes
mst_cntl_rd_req <= i_burstRdReq; -- read request
mst_cntl_wr_req <= i_burstWrReq; -- write request
mst_ip2bus_addr <= i_targetAddr; -- target address
mst_cntl_burst <= '1'; -- burst
xfer_cross_wrd_bndry <= '0'; -- bursts can't cross word boundary
mst_ip2bus_be <= X"00"; -- bursts do not look at BE
mst_go <= '1';
elsif (i_singleRdReq = '1' or i_singleWrReq = '1') then
mst_cntl_rd_req <= i_singleRdReq; -- read request
mst_cntl_wr_req <= i_singleWrReq; -- write request
mst_ip2bus_addr <= i_targetAddr; -- target address
mst_cntl_burst <= '0'; -- no burst
mst_ip2bus_be <= std_logic_vector(ieee.numeric_std.unsigned(BE_32) srl be_offset); -- calc byte enables from address
if be_offset > 4 then
-- 32 Bit transfer across 64 Bit boundary, we need to split this
xfer_cross_wrd_bndry <= '1';
end if;
mst_go <= '1';
elsif mst_cmd_sm_set_done = '1' and xfer_cross_wrd_bndry = '1' then -- if last transfer was a single word that crossed a 64bit boundary
xfer_cross_wrd_bndry <= '0'; -- repeat transfer with remaining data
mst_ip2bus_addr <= i_targetAddr + 8-be_offset; -- new target address
mst_ip2bus_be <= std_logic_vector(ieee.numeric_std.unsigned(BE_32) sll 8-be_offset); -- remaining byte enables
mst_go <= '1';
elsif mst_cmd_sm_clr_go = '1' then
mst_go <= '0';
end if;
end if;
end process;
-- command_decoder protocol to mst_* protocol conversion assignments
mst_cntl_bus_lock <= '0'; -- never lock the bus
-- user logic master command interface assignments
IP2Bus_MstRdReq <= mst_cmd_sm_rd_req;
IP2Bus_MstWrReq <= mst_cmd_sm_wr_req;
IP2Bus_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_MstBE <= mst_cmd_sm_ip2bus_be;
IP2Bus_MstBurst <= mst_cmd_sm_xfer_type;
IP2Bus_MstNum <= mst_cmd_sm_xfer_length;
IP2Bus_MstBusLock <= mst_cmd_sm_bus_lock;
IP2Bus_MstBusReset <= mst_cmd_sm_reset;
-- handshake output signals
o_busy <= mst_cmd_sm_busy or mst_go or i_singleRdReq or i_singleWrReq or i_burstRdReq or i_burstWrReq or mst_cmd_sm_set_done;
o_rdDone <= mst_cmd_sm_set_done and mst_cntl_rd_req and not xfer_cross_wrd_bndry;
o_wrDone <= mst_cmd_sm_set_done and mst_cntl_wr_req and not xfer_cross_wrd_bndry;
--implement master command interface state machine
MASTER_CMD_SM_PROC : process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
-- reset condition
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_xfer_type <= '0';
mst_cmd_sm_xfer_length <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '0';
mst_cmd_sm_start_rd_llink <= '0';
mst_cmd_sm_start_wr_llink <= '0';
else
-- default condition
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_xfer_type <= '0';
mst_cmd_sm_xfer_length <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '1';
mst_cmd_sm_start_rd_llink <= '0';
mst_cmd_sm_start_wr_llink <= '0';
-- state transition
case mst_cmd_sm_state is
-- waiting for transfer
when CMD_IDLE =>
if (mst_go = '1') then -- new transfer initiated?
mst_cmd_sm_state <= CMD_RUN; -- go to RUN state
mst_cmd_sm_clr_go <= '1'; -- clear go register (REMOVEME)
if (mst_cntl_rd_req = '1') then -- read request?
mst_cmd_sm_start_rd_llink <= '1'; -- start ll read
elsif (mst_cntl_wr_req = '1') then -- write request?
mst_cmd_sm_start_wr_llink <= '1'; -- start ll write
end if;
else
mst_cmd_sm_state <= CMD_IDLE; -- otherwise, stay here and do nothing
mst_cmd_sm_busy <= '0';
end if;
-- transfer initiated
when CMD_RUN =>
if (Bus2IP_Mst_CmdAck = '1' and Bus2IP_Mst_Cmplt = '0') then -- command acknowledged and not completed?
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA; -- go to WAIT_FOR_DATA state
elsif (Bus2IP_Mst_Cmplt = '1') then -- command completed?
mst_cmd_sm_state <= CMD_DONE; -- go to DONE state
if (Bus2IP_Mst_Cmd_Timeout = '1') then -- was it a timeout?
-- PLB address phase timeout
mst_cmd_sm_set_error <= '1'; -- set error and timeout flags
mst_cmd_sm_set_timeout <= '1';
elsif (Bus2IP_Mst_Error = '1') then -- was it an error
-- PLB data transfer error
mst_cmd_sm_set_error <= '1'; -- set only the error flag
end if;
else
mst_cmd_sm_state <= CMD_RUN; -- if it wasn't acknowledged or completed yet (i.e. new request)
mst_cmd_sm_rd_req <= mst_cntl_rd_req; -- set read and write request flags
mst_cmd_sm_wr_req <= mst_cntl_wr_req;
mst_cmd_sm_ip2bus_addr <= mst_ip2bus_addr; -- set target address
mst_cmd_sm_ip2bus_be <= mst_ip2bus_be; -- set byte enables
mst_cmd_sm_xfer_type <= mst_cntl_burst; -- set transfer type
mst_cmd_sm_xfer_length <= mst_xfer_length; -- set transfer length (in bytes?)
mst_cmd_sm_bus_lock <= mst_cntl_bus_lock; -- set bus lock (always 0?)
end if; -- and stay in RUN state (i.e. wait for acceptance/abort)
-- transfer request accepted, transfer in progress
when CMD_WAIT_FOR_DATA =>
if (Bus2IP_Mst_Cmplt = '1') then -- transfer completed?
mst_cmd_sm_state <= CMD_DONE; -- go to DONE state
else -- otherwise
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA; -- stay here
end if;
-- transfer completed or aborted
when CMD_DONE =>
mst_cmd_sm_state <= CMD_IDLE; -- go to IDLE state
mst_cmd_sm_set_done <= '1'; -- signal that we're done
mst_cmd_sm_busy <= '0'; -- and not busy
-- default catchall
when others =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CMD_SM_PROC;
----------------------------------------------------
-- LOCAL LINK INTERFACE
----------------------------------------------------
-- user logic master read locallink interface assignments
IP2Bus_MstRd_dst_rdy_n <= not(mst_llrd_sm_dst_rdy);
IP2Bus_MstRd_dst_dsc_n <= '1'; -- do not throttle data
-- implement a simple state machine to enable the
-- read locallink interface to transfer data
LLINK_RD_SM_PROCESS : process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
-- reset condition
mst_llrd_sm_state <= LLRD_IDLE;
mst_llrd_sm_dst_rdy <= '0'; -- not ready to read data
else
-- default condition
mst_llrd_sm_state <= LLRD_IDLE;
mst_llrd_sm_dst_rdy <= '0'; -- not ready to read data
-- state transition
case mst_llrd_sm_state is
when LLRD_IDLE =>
if (mst_cmd_sm_start_rd_llink = '1') then -- if we got start signal from master FSM
mst_llrd_sm_state <= LLRD_GO; -- go to GO state
else
mst_llrd_sm_state <= LLRD_IDLE; -- otherwise stay here and keep waiting
end if;
when LLRD_GO =>
-- done, end of packet
if (mst_llrd_sm_dst_rdy = '1' and -- if we are ready to receive
Bus2IP_MstRd_src_rdy_n = '0' and -- the sender is ready to send
Bus2IP_MstRd_eof_n = '0') then -- and the sender is done sending
mst_llrd_sm_state <= LLRD_IDLE; -- we're done
-- not done yet, continue receiving data
else -- otherwise
mst_llrd_sm_state <= LLRD_GO; -- stay in this state
mst_llrd_sm_dst_rdy <= '1'; -- and be ready to receive
end if;
-- default catchall
when others =>
mst_llrd_sm_state <= LLRD_IDLE;
end case;
end if;
else
null;
end if;
end process LLINK_RD_SM_PROCESS;
-- user logic master write locallink interface assignments
IP2Bus_MstWr_src_rdy_n <= not(mst_llwr_sm_src_rdy);
IP2Bus_MstWr_src_dsc_n <= '1'; -- do not throttle data
IP2Bus_MstWr_rem <= (others => '0'); -- no remainder mask
IP2Bus_MstWr_sof_n <= not(mst_llwr_sm_sof);
IP2Bus_MstWr_eof_n <= not(mst_llwr_sm_eof);
-- implement a simple state machine to enable the
-- write locallink interface to transfer data
LLINK_WR_SM_PROC : process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
-- reset condition
mst_llwr_sm_state <= LLWR_IDLE;
mst_llwr_sm_src_rdy <= '0';
mst_llwr_sm_sof <= '0';
mst_llwr_sm_eof <= '0';
mst_llwr_byte_cnt <= 0;
else
-- default condition
mst_llwr_sm_state <= LLWR_IDLE;
mst_llwr_sm_src_rdy <= '0';
mst_llwr_sm_sof <= '0';
mst_llwr_sm_eof <= '0';
mst_llwr_byte_cnt <= 0;
-- state transition
case mst_llwr_sm_state is
-- wait for start of transfer
when LLWR_IDLE =>
if (mst_cmd_sm_start_wr_llink = '1' and mst_cntl_burst = '0') then -- single write request?
mst_llwr_sm_state <= LLWR_SNGL_INIT;
elsif (mst_cmd_sm_start_wr_llink = '1' and mst_cntl_burst = '1') then -- burst write request?
mst_llwr_sm_state <= LLWR_BRST_INIT;
else
mst_llwr_sm_state <= LLWR_IDLE;
end if;
-- init single transfer
when LLWR_SNGL_INIT =>
mst_llwr_sm_state <= LLWR_SNGL;
mst_llwr_sm_src_rdy <= '1'; -- ready to send
mst_llwr_sm_sof <= '1'; -- signal single transfer by asserting both SOF and EOF
mst_llwr_sm_eof <= '1';
-- do single transfer
when LLWR_SNGL =>
-- destination discontinue write
if (Bus2IP_MstWr_dst_dsc_n = '0' and Bus2IP_MstWr_dst_rdy_n = '0') then -- if discontinue from target
mst_llwr_sm_state <= LLWR_IDLE; -- reset back to IDLE state
mst_llwr_sm_src_rdy <= '0';
mst_llwr_sm_eof <= '0';
-- single data beat transfer complete
elsif (mst_fifo_valid_read_xfer = '1') then -- if local memory read has been completed
mst_llwr_sm_state <= LLWR_IDLE; -- go back to IDLE state
mst_llwr_sm_src_rdy <= '0';
mst_llwr_sm_sof <= '0';
mst_llwr_sm_eof <= '0';
-- wait on destination
else
mst_llwr_sm_state <= LLWR_SNGL; -- otherwise keep trying to transfer single word
mst_llwr_sm_src_rdy <= '1';
mst_llwr_sm_sof <= '1';
mst_llwr_sm_eof <= '1';
end if;
-- init burst transfer
when LLWR_BRST_INIT =>
mst_llwr_sm_state <= LLWR_BRST;
mst_llwr_sm_src_rdy <= '1';
mst_llwr_sm_sof <= '1';
mst_llwr_byte_cnt <= CONV_INTEGER(mst_xfer_length);
-- do burst transfer
when LLWR_BRST =>
if (mst_fifo_valid_read_xfer = '1') then -- if a word has been transferred (i.e. we are actively writing)
mst_llwr_sm_sof <= '0'; -- deassert SOF signal
else
mst_llwr_sm_sof <= mst_llwr_sm_sof;
end if;
-- destination discontinue write
if (Bus2IP_MstWr_dst_dsc_n = '0' and -- if discontinue from target
Bus2IP_MstWr_dst_rdy_n = '0') then
mst_llwr_sm_state <= LLWR_IDLE; -- reset to IDLE state
mst_llwr_sm_src_rdy <= '1'; -- and properly terminate transfer
mst_llwr_sm_eof <= '1';
-- last data beat write
elsif (mst_fifo_valid_read_xfer = '1' and -- if this was the second to last beat to transfer
(mst_llwr_byte_cnt-BYTES_PER_BEAT) <= BYTES_PER_BEAT) then
mst_llwr_sm_state <= LLWR_BRST_LAST_BEAT; -- go to LAST_BEAT state
mst_llwr_sm_src_rdy <= '1'; -- and signal termination of transfer
mst_llwr_sm_eof <= '1';
-- wait on destination
else
mst_llwr_sm_state <= LLWR_BRST; -- otherwise keep writing data
mst_llwr_sm_src_rdy <= '1';
-- decrement write transfer counter if it's a valid write
if (mst_fifo_valid_read_xfer = '1') then
mst_llwr_byte_cnt <= mst_llwr_byte_cnt - BYTES_PER_BEAT;
else
mst_llwr_byte_cnt <= mst_llwr_byte_cnt;
end if;
end if;
-- do last beat of write burst
when LLWR_BRST_LAST_BEAT =>
-- destination discontinue write
if (Bus2IP_MstWr_dst_dsc_n = '0' and -- if discontinue from target
Bus2IP_MstWr_dst_rdy_n = '0') then
mst_llwr_sm_state <= LLWR_IDLE; -- reset to IDLE state
mst_llwr_sm_src_rdy <= '0'; -- and mark ourselves as not ready (?)
-- last data beat done
elsif (mst_fifo_valid_read_xfer = '1') then -- if this transfer was successful
mst_llwr_sm_state <= LLWR_IDLE; -- reset to IDLE state
mst_llwr_sm_src_rdy <= '0';
-- wait on destination
else
mst_llwr_sm_state <= LLWR_BRST_LAST_BEAT; -- otherwise keep trying to send
mst_llwr_sm_src_rdy <= '1';
mst_llwr_sm_eof <= '1';
end if;
-- default catchall
when others =>
mst_llwr_sm_state <= LLWR_IDLE;
end case;
end if;
else
null;
end if;
end process LLINK_WR_SM_PROC;
-- determine whether a data beat was successfully written
mst_fifo_valid_write_xfer <= not(Bus2IP_MstRd_src_rdy_n) and mst_llrd_sm_dst_rdy;
mst_fifo_valid_read_xfer <= not(Bus2IP_MstWr_dst_rdy_n) and mst_llwr_sm_src_rdy;
-- connect burst ram
o_burstAddr <= i_localAddr(C_AWIDTH-C_BURST_AWIDTH to C_AWIDTH-1) + bram_offset;
o_burstData <= Bus2IP_MstRd_d;
o_burstWE <= mst_cntl_rd_req and mst_cntl_burst and mst_fifo_valid_write_xfer;
o_burstBE <= (others => '1');
-- delay read enable for edge detection and prefetch
mst_fifo_valid_read_xfer_d1 <= mst_fifo_valid_read_xfer when rising_edge(clk) else mst_fifo_valid_read_xfer_d1;
-- prefetch data from burst ram for contiguous writes
prefetch : process(clk, reset)
begin
if reset = '1' then
prefetch_data <= (others => '0');
elsif rising_edge(clk) then
if mst_fifo_valid_read_xfer_d1 = '1' or save_first = '1' then
prefetch_data <= i_burstData;
end if;
end if;
end process;
-- on the first beat of a back-to-back transfer, use the prefetched data, otherwise use the RAM output
burstData_current <= prefetch_data when mst_fifo_valid_read_xfer_d1 = '0' and mst_fifo_valid_read_xfer = '1' else i_burstData;
-- generate address signals for burst ram
burst_addr : process(clk, reset)
begin
if reset = '1' then
bram_offset <= 0;
save_first <= '0';
prefetch_first <= '0';
elsif rising_edge(clk) then
save_first <= '0';
if i_burstRdReq = '1' then -- new burst request
bram_offset <= 0;
elsif i_burstWrReq = '1' then -- new burst request
bram_offset <= 0;
prefetch_first <= '1';
elsif prefetch_first = '1' then
bram_offset <= bram_offset + BYTES_PER_BEAT;
prefetch_first <= '0';
save_first <= '1';
elsif mst_fifo_valid_write_xfer = '1' or mst_fifo_valid_read_xfer = '1' then
bram_offset <= bram_offset + BYTES_PER_BEAT;
end if;
end if;
end process;
-- multiplex burst ram and single data register to bus (possibly shifted)
IP2Bus_MstWr_d <= burstData_current when mst_cntl_burst = '1' else
std_logic_vector(ieee.numeric_std.unsigned(i_singleData & X"00000000") ror be_offset*8);
-- implement single data register
rolled_MstRd_d <= std_logic_vector(ieee.numeric_std.unsigned(Bus2IP_MstRd_d) rol be_offset*8);
rolled_mst_ip2bus_be <= std_logic_vector(ieee.numeric_std.unsigned(mst_ip2bus_be) rol be_offset);
single_reg : process(Bus2IP_Clk, Bus2IP_Reset, mst_ip2bus_be)
variable bit_enable : std_logic_vector(0 to C_DWIDTH-1);
variable assembled_data : std_logic_vector(0 to C_DWIDTH-1);
begin
for i in 0 to 3 loop
bit_enable(i*8 to i*8+7) := (others => rolled_mst_ip2bus_be(i));
end loop;
if Bus2IP_Reset = '1' then
assembled_data := (others => '0');
elsif rising_edge(Bus2IP_Clk) then
if (mst_cntl_rd_req = '1' and mst_cntl_burst = '0' and mst_fifo_valid_write_xfer = '1') then
assembled_data := (assembled_data and (not bit_enable)) or (rolled_MstRd_d(0 to C_DWIDTH-1) and bit_enable);
end if;
end if;
o_singleData <= assembled_data;
end process;
end arch;
|
gpl-3.0
|
a307d1780879f590a97597bccdfb10c6
| 0.485982 | 3.839041 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/BRAM/BRAM_fifo_pkg.vhd
| 1 | 14,650 |
-------------------------------------------------------------------------------
--
-- Module : BRAM_fifo_pkg.vhd
--
-- Version : 1.2
--
-- Last Update : 2005-06-29
--
-- Project : Parameterizable LocalLink FIFO
--
-- Description : Package of Block SelectRAM FIFO components
--
-- Designer : Wen Ying Wei, Davy Huang
--
-- Company : Xilinx, Inc.
--
-- Disclaimer : XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2005 Xilinx, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package BRAM_fifo_pkg is
component BRAM_fifo
generic (
BRAM_MACRO_NUM: integer := 1;
WR_DWIDTH: integer := 32;
RD_DWIDTH: integer := 32;
RD_REM_WIDTH: integer:=2;
WR_REM_WIDTH: integer:=2;
USE_LENGTH: boolean := false;
glbtm: time:=2 ns
);
port (
-- Reset
fifo_gsr_in: in std_logic;
-- clocks
write_clock_in: in std_logic;
read_clock_in: in std_logic;
-- signals tranceiving from User Application using standardized
-- specification for FifO interface
read_data_out: out std_logic_vector(RD_DWIDTH-1 downto 0);
read_rem_out: out std_logic_vector(RD_REM_WIDTH-1 downto 0);
read_sof_out_n: out std_logic;
read_eof_out_n: out std_logic;
read_enable_in: in std_logic;
-- signals trasceiving from Aurora
write_data_in: in std_logic_vector(WR_DWIDTH-1 downto 0);
write_rem_in: in std_logic_vector(WR_REM_WIDTH-1 downto 0);
write_sof_in_n: in std_logic;
write_eof_in_n: in std_logic;
write_enable_in: in std_logic;
-- FifO status signals
fifostatus_out: out std_logic_vector(3 downto 0);
full_out: out std_logic;
empty_out: out std_logic;
data_valid_out: out std_logic;
len_out: out std_logic_vector(15 downto 0);
len_rdy_out: out std_logic;
len_err_out: out std_logic);
end component;
component BRAM_macro is
generic (
BRAM_MACRO_NUM : integer := 1; --Number of BRAM Blocks.
--Allowed: 1, 2, 4, 8, 16
WR_DWIDTH : integer := 32; --FIFO write data width.
--Allowed: 8, 16, 32, 64
RD_DWIDTH : integer := 32; --FIFO read data width.
--Allowed: 8, 16, 32, 64
WR_REM_WIDTH : integer := 2; --log2(WR_DWIDTH/8)
RD_REM_WIDTH : integer := 2; --log2(RD_DWIDTH/8)
RD_PAD_WIDTH : integer := 1;
RD_ADDR_FULL_WIDTH: integer := 10;
RD_ADDR_WIDTH : integer := 9;
ADDR_MINOR_WIDTH: integer := 1;
WR_PAD_WIDTH : integer := 1;
WR_ADDR_FULL_WIDTH: integer := 10;
WR_ADDR_WIDTH : integer := 9;
glbtm : time := 1 ns );
port (
-- Reset
fifo_gsr: in std_logic;
-- clocks
wr_clk: in std_logic;
rd_clk: in std_logic;
rd_allow: in std_logic;
rd_allow_minor: in std_logic;
rd_addr_full: in std_logic_vector(RD_PAD_WIDTH+RD_ADDR_FULL_WIDTH-1 downto 0);
rd_addr_minor: in std_logic_vector(ADDR_MINOR_WIDTH-1 downto 0);
rd_addr: in std_logic_vector(RD_PAD_WIDTH + RD_ADDR_WIDTH -1 downto 0);
rd_data: out std_logic_vector(RD_DWIDTH -1 downto 0);
rd_rem: out std_logic_vector(RD_REM_WIDTH-1 downto 0);
rd_sof_n: out std_logic;
rd_eof_n: out std_logic;
wr_allow: in std_logic;
wr_allow_minor: in std_logic;
wr_addr: in std_logic_vector(WR_PAD_WIDTH + WR_ADDR_WIDTH-1 downto 0);
wr_addr_minor: in std_logic_vector(ADDR_MINOR_WIDTH-1 downto 0);
wr_addr_full: in std_logic_vector(WR_PAD_WIDTH + WR_ADDR_FULL_WIDTH-1 downto 0);
wr_data: in std_logic_vector(WR_DWIDTH-1 downto 0);
wr_rem: in std_logic_vector(WR_REM_WIDTH-1 downto 0);
wr_sof_n: in std_logic;
wr_eof_n: in std_logic
);
end component;
component BRAM_S8_S72
port (ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (63 downto 0);
DIPB : in std_logic_vector (7 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (63 downto 0);
DOPB : out std_logic_vector(7 downto 0));
end component;
component BRAM_S18_S72
port (ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (63 downto 0);
DIPB : in std_logic_vector (7 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector(1 downto 0);
DOB : out std_logic_vector (63 downto 0);
DOPB : out std_logic_vector(7 downto 0));
end component;
component BRAM_S36_S72
port (ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (63 downto 0);
DIPB : in std_logic_vector (7 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (63 downto 0);
DOPB : out std_logic_vector(7 downto 0));
end component;
component BRAM_S72_S72
port (ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (63 downto 0);
DIPA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (63 downto 0);
DIPB : in std_logic_vector (7 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (63 downto 0);
DOPA : out std_logic_vector(7 downto 0);
DOB : out std_logic_vector (63 downto 0);
DOPB : out std_logic_vector(7 downto 0));
end component;
component BRAM_S8_S144
port (ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (127 downto 0);
DIPB : in std_logic_vector (15 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (127 downto 0);
DOPB : out std_logic_vector(15 downto 0));
end component;
component BRAM_S16_S144
port (ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (127 downto 0);
DIPB : in std_logic_vector (15 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (127 downto 0);
DOPB : out std_logic_vector(15 downto 0));
end component;
component BRAM_S36_S144
port (ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (127 downto 0);
DIPB : in std_logic_vector (15 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (127 downto 0);
DOPB : out std_logic_vector(15 downto 0));
end component;
component BRAM_S72_S144
port (ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (63 downto 0);
DIPA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (127 downto 0);
DIPB : in std_logic_vector (15 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (63 downto 0);
DOPA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (127 downto 0);
DOPB : out std_logic_vector(15 downto 0));
end component;
component BRAM_S144_S144
port (ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (127 downto 0);
DIPA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (127 downto 0);
DIPB : in std_logic_vector (15 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (127 downto 0);
DOPA : out std_logic_vector(15 downto 0);
DOB : out std_logic_vector (127 downto 0);
DOPB : out std_logic_vector(15 downto 0));
end component;
end BRAM_fifo_pkg;
|
gpl-3.0
|
2b270b13d9326c3f51cadadda7f94e41
| 0.451195 | 4.192902 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_unbounded_func.vhd
| 3 | 1,953 |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Basic test for functions that work with unbounded vectors as return
-- and param types.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vhdl_unbounded_func_pkg.all;
package included_pkg is
function negator(word_i : std_logic_vector) return std_logic_vector;
end included_pkg;
package body included_pkg is
function negator(word_i : std_logic_vector) return std_logic_vector is
variable word_o : std_logic_vector (word_i'left downto word_i'right);
begin
for I in word_i'range loop
word_o (I) := not word_i(I);
end loop;
return word_o;
end function;
end included_pkg;
entity vhdl_unbounded_func is
end vhdl_unbounded_func;
architecture test of vhdl_unbounded_func is
signal test_out1 : std_logic_vector(9 downto 0);
signal test_out2 : std_logic_vector(5 downto 0);
signal neg_test_out1 : std_logic_vector(9 downto 0);
signal neg_test_out2 : std_logic_vector(5 downto 0);
begin
test_out1 <= f_manch_encoder(B"11101");
test_out2 <= f_manch_encoder(B"001");
neg_test_out1 <= negator(test_out1);
neg_test_out2 <= negator(test_out2);
end test;
|
gpl-2.0
|
16ecd82aa0374c639a3c34e471ccf5eb
| 0.723502 | 3.4875 | false | true | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_sa1_test2.vhd
| 8 | 2,573 |
library ieee;
use ieee.std_logic_1164.all;
package work6 is
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in std_logic;
s_o, c_o: out std_logic);
end component fa1;
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic);
end component;
-- doing nothing at the moment
constant N: integer range 0 to 16 := 4;
end package work6;
-- a 1-bit Moore-type adder to be used in
-- a serial adder FSM-driven architecture
-- ________ _____
-- a_i -->| |------>|D Q|---> s_o
-- b_i -->| FA1 | | |
-- | |--- | |
-- ---> |_______| | |_____|
--rst __|_______________________|
-- | | |
-- | | |
-- | | | ______
-- | | ---->|D Q|---
-- | | | | |
-- | | | | |
-- | | |_____| |
-- | |____________| |
-- |________________________________|
--
library ieee;
use ieee.std_logic_1164.all;
use work.work6.all;
entity sa1 is
port (clk, reset: in std_logic;
a_i, b_i: in std_logic;
s_o: out std_logic
);
end entity sa1;
architecture sa1_rtl of sa1 is
signal sum, carry, carry_reg: std_logic;
begin
a1: fa1 port map (c_i => carry_reg,
a_i => a_i,
b_i => b_i,
s_o => sum,
c_o => carry
);
f1: fdc port map (clk => clk, reset => reset, d => sum, q => s_o);
f2: fdc port map (clk => clk, reset => reset, d => carry, q => carry_reg);
end architecture sa1_rtl;
-- a one bit full adder written according to
-- textbook's boolean equations
library ieee;
use ieee.std_logic_1164.all;
entity fa1 is
port (a_i, b_i, c_i: in std_logic;
s_o, c_o: out std_logic
);
end entity fa1;
architecture fa1_rtl of fa1 is
begin
s_o <= a_i xor b_i xor c_i;
c_o <= (a_i and b_i) or (c_i and (a_i xor b_i));
end architecture fa1_rtl;-- a D-type flip-flop with synchronous reset
library ieee;
use ieee.std_logic_1164.all;
entity fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic
);
end fdc;
architecture fdc_rtl of fdc is
begin
i_finish: process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end fdc_rtl;
|
gpl-2.0
|
ccabb28b32b4614e1afd01f654d8a4ed
| 0.458997 | 3.059453 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/MouseCtl.vhd
| 1 | 48,813 |
------------------------------------------------------------------------
-- mouse_controller.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- This file contains a controller for a ps/2 compatible mouse device.
-- This controller uses the ps2interface module.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web for understanding how
-- to interface a ps/2 mouse:
-- http://www.computer-engineering.org/ps2mouse/
-- This controller is implemented as described in the above article.
-- The mouse controller receives bytes from the ps2interface which, in
-- turn, receives them from the mouse device. Data is received on the
-- rx_data input port, and is validated by the read signal. read is
-- active for one clock period when new byte available on rx_data. Data
-- is sent to the ps2interface on the tx_data output port and validated
-- by the write output signal. 'write' should be active for one clock
-- period when tx_data contains the command or data to be sent to the
-- mouse. ps2interface wraps the byte in a 11 bits packet that is sent
-- through the ps/2 port using the ps/2 protocol. Similarly, when the
-- mouse sends data, the ps2interface receives 11 bits for every byte,
-- extracts the byte from the ps/2 frame, puts it on rx_data and
-- activates read for one clock period. If an error occurs when sending
-- or receiving a frame from the mouse, the err input goes high for one
-- clock period. When this occurs, the controller enters reset state.
-- When in reset state, the controller resets the mouse and begins an
-- initialization procedure that consists of tring to put mouse in
-- scroll mode (enables wheel if the mouse has one), setting the
-- resolution of the mouse, the sample rate and finally enables
-- reporting. Implicitly the mouse, after a reset or imediately after a
-- reset, does not send data packets on its own. When reset(or power-up)
-- the mouse enters reset state, where it performs a test, called the
-- bat test (basic assurance test), when this test is done, it sends
-- the result: AAh for test ok, FCh for error. After this it sends its
-- ID which is 00h. When this is done, the mouse enters stream mode,
-- but with reporting disabled (movement data packets are not sent).
-- To enable reporting the enable data reporting command (F4h) must be
-- sent to the mouse. After this command is sent, the mouse will send
-- movement data packets when the mouse is moved or the status of the
-- button changes.
-- After sending a command or a byte following a command, the mouse
-- must respond with ack (FAh). For managing the intialization
-- procedure and receiving the movement data packets, a FSM is used.
-- When the fpga is powered up or the logic is reset using the global
-- reset, the FSM enters reset state. From this state, the FSM will
-- transition to a series of states used to initialize the mouse. When
-- initialization is complete, the FSM remains in state read_byte_1,
-- waiting for a movement data packet to be sent. This is the idle
-- state if the FSM. When a byte is received in this state, this is
-- the first byte of the 3 bytes sent in a movement data packet (4 bytes
-- if mouse in scrolling mode). After reading the last byte from the
-- packet, the FSM enters mark_new_event state and sets new_event high.
-- After that FSM enterss read_byte_1 state, resets new_event and waits
-- for a new packet.
-- After a packet is received, new_event is set high for one clock
-- period to "inform" the clients of this controller a new packet was
-- received and processed.
-- During the initialization procedure, the controller tries to put the
-- mouse in scroll mode (activates wheel, if mouse has one). This is
-- done by successively setting the sample rate to 200, then to 100, and
-- lastly to 80. After this is done, the mouse ID is requested by
-- sending get device ID command (F2h). If the received ID is 00h than
-- the mouse does not have a wheel. If the received ID is 03h than the
-- mouse is in scroll mode, and when sending movement data packets
-- (after enabling data reporting) it will include z movement data.
-- If the mouse is in normal, non-scroll mode, the movement data packet
-- consists of 3 successive bytes. This is their format:
--
--
--
-- bits 7 6 5 4 3 2 1 0
-- -------------------------------------------------
-- byte 1 | YOVF| XOVF|YSIGN|XSIGN| 1 | MBTN| RBTN| LBTN|
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 2 | X MOVEMENT |
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 3 | Y MOVEMENT |
-- -------------------------------------------------
-- OVF = overflow
-- BTN = button
-- M = middle
-- R = right
-- L = left
--
-- When scroll mode is enabled, the mouse send 4 byte movement packets.
-- bits 7 6 5 4 3 2 1 0
-- -------------------------------------------------
-- byte 1 | YOVF| XOVF|YSIGN|XSIGN| 1 | MBTN| RBTN| LBTN|
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 2 | X MOVEMENT |
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 3 | Y MOVEMENT |
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 4 | Z MOVEMENT |
-- -------------------------------------------------
-- x and y movement counters are represented on 8 bits, 2's complement
-- encoding. The first bit (sign bit) of the counters are the xsign and
-- ysign bit from the first packet, the rest of the bits are the second
-- byte for the x movement and the third byte for y movement. For the
-- z movement the range is -8 -> +7 and only the 4 least significant
-- bits from z movement are valid, the rest are sign extensions.
-- The x and y movements are in range: -256 -> +255
-- The mouse uses as axes origin the lower-left corner. For the purpose
-- of displaying a mouse cursor on the screen, the controller inverts
-- the y axis to move the axes origin in the upper-left corner. This
-- is done by negating the y movement value (following the 2s complement
-- encoding). The movement data received from the mouse are delta
-- movements, the data represents the movement of the mouse relative
-- to the last position. The controller keeps track of the position of
-- the mouse relative to the upper-left corner. This is done by keeping
-- the mouse position in two registers x_pos and y_pos and adding the
-- delta movements to their value. The addition uses saturation. That
-- means the value of the mouse position will not exceed certain bounds
-- and will not rollover the a margin. For example, if the mouse is at
-- the left margin and is moved left, the x position remains at the left
-- margin(0). The lower bound is always 0 for both x and y movement.
-- The upper margin can be set using input pins: value, setmax_x,
-- setmax_y. To set the upper bound of the x movement counter, the new
-- value is placed on the value input pins and setmax_x is activated
-- for at least one clock period. Similarly for y movement counter, but
-- setmax_y is activated instead. Notice that value has 10 bits, and so
-- the maximum value for a bound is 1023.
-- The position of the mouse (x_pos and y_pos) can be set at any time,
-- by placing the x or y position on the value input pins and activating
-- the setx, or sety respectively, for at least one clock period. This
-- is useful for setting an original position of the mouse different
-- from (0,0).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- clk - global clock signal (100MHz)
-- rst - global reset signal
-- xpos - output pin, 10 bits
-- - the x position of the mouse relative to the upper
-- - left corner
-- ypos - output pin, 10 bits
-- - the y position of the mouse relative to the upper
-- - left corner
-- zpos - output pin, 4 bits
-- - last delta movement on z axis
-- left - output pin, high if the left mouse button is pressed
-- middle - output pin, high if the middle mouse button is
-- - pressed
-- right - output pin, high if the right mouse button is
-- - pressed
-- new_event - output pin, active one clock period after receiving
-- - and processing one movement data packet.
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
-- the mouse_controller entity declaration
-- read above for behavioral description and port definitions.
entity MouseCtl is
generic
(
SYSCLK_FREQUENCY_HZ : integer := 100000000;
CHECK_PERIOD_MS : integer := 500; -- Period in miliseconds to check if the mouse is present
TIMEOUT_PERIOD_MS : integer := 100 -- Timeout period in miliseconds when the mouse presence is checked
);
port(
clk : in std_logic;
rst : in std_logic;
xpos : out std_logic_vector(11 downto 0);
ypos : out std_logic_vector(11 downto 0);
zpos : out std_logic_vector(3 downto 0);
left : out std_logic;
middle : out std_logic;
right : out std_logic;
new_event : out std_logic;
value : in std_logic_vector(11 downto 0);
setx : in std_logic;
sety : in std_logic;
setmax_x : in std_logic;
setmax_y : in std_logic;
ps2_clk : inout std_logic;
ps2_data : inout std_logic
);
end MouseCtl;
architecture Behavioral of MouseCtl is
------------------------------------------------------------------------
-- Ps2 Interface component declaration
------------------------------------------------------------------------
COMPONENT Ps2Interface
PORT(
ps2_clk : inout std_logic;
ps2_data : inout std_logic;
clk : in std_logic;
rst : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
write_data : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
read_data : out std_logic;
busy : out std_logic;
err : out std_logic
);
END COMPONENT;
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- constants defining commands to send or received from the mouse
constant FA: std_logic_vector(7 downto 0) := "11111010"; -- 0xFA(ACK)
constant FF: std_logic_vector(7 downto 0) := "11111111"; -- 0xFF(RESET)
constant AA: std_logic_vector(7 downto 0) := "10101010"; -- 0xAA(BAT_OK)
constant OO: std_logic_vector(7 downto 0) := "00000000"; -- 0x00(ID)
-- (atention: name is 2 letters O not zero)
-- command to read id
constant READ_ID : std_logic_vector(7 downto 0) := x"F2";
-- command to enable mouse reporting
-- after this command is sent, the mouse begins sending data packets
constant ENABLE_REPORTING : std_logic_vector(7 downto 0) := x"F4";
-- command to set the mouse resolution
constant SET_RESOLUTION : std_logic_vector(7 downto 0) := x"E8";
-- the value of the resolution to send after sending SET_RESOLUTION
constant RESOLUTION : std_logic_vector(7 downto 0) := x"03";
-- (8 counts/mm)
-- command to set the mouse sample rate
constant SET_SAMPLE_RATE : std_logic_vector(7 downto 0) := x"F3";
-- the value of the sample rate to send after sending SET_SAMPLE_RATE
constant SAMPLE_RATE : std_logic_vector(7 downto 0) := x"28";
-- (40 samples/s)
-- default maximum value for the horizontal mouse position
constant DEFAULT_MAX_X : std_logic_vector(11 downto 0) := x"4FF";
-- 1279
-- default maximum value for the vertical mouse position
constant DEFAULT_MAX_Y : std_logic_vector(11 downto 0) := x"3FF";
-- 1023
-- Mouse check tick constants
constant CHECK_PERIOD_CLOCKS : integer := ((CHECK_PERIOD_MS*1000000)/(1000000000/SYSCLK_FREQUENCY_HZ));
constant TIMEOUT_PERIOD_CLOCKS : integer := ((TIMEOUT_PERIOD_MS*1000000)/(1000000000/SYSCLK_FREQUENCY_HZ));
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- after doing the enable scroll mouse procedure, if the ID returned by
-- the mouse is 03 (scroll mouse enabled) then this register will be set
-- If '1' then the mouse is in scroll mode, else mouse is in simple
-- mouse mode.
signal haswheel: std_logic := '0';
-- horizontal and veritcal mouse position
-- origin of axes is upper-left corner
-- the origin of axes the mouse uses is the lower-left corner
-- The y-axis is inverted, by making negative the y movement received
-- from the mouse (if it was positive it becomes negative
-- and vice versa)
signal x_pos,y_pos: std_logic_vector(11 downto 0) := (others => '0');
-- active when an overflow occurred on the x and y axis
-- bits 6 and 7 from the first byte received from the mouse
signal x_overflow,y_overflow: std_logic := '0';
-- active when the x,y movement is negative
-- bits 4 and 5 from the first byte received from the mouse
signal x_sign,y_sign: std_logic := '0';
-- 2's complement value for incrementing the x_pos,y_pos
-- y_inc is the negated value from the mouse in the third byte
signal x_inc,y_inc: std_logic_vector(7 downto 0) := (others => '0');
-- active for one clock period, indicates new delta movement received
-- on x,y axis
signal x_new,y_new: std_logic := '0';
-- maximum value for x and y position registers(x_pos,y_pos)
signal x_max: std_logic_vector(11 downto 0) := DEFAULT_MAX_X;
signal y_max: std_logic_vector(11 downto 0) := DEFAULT_MAX_Y;
-- active when left,middle,right mouse button is down
signal left_down,middle_down,right_down: std_logic := '0';
-- the FSM states
-- states that begin with "reset" are part of the reset procedure.
-- states that end in "_wait_ack" are states in which ack is waited
-- as response to sending a byte to the mouse.
-- read behavioral description above for details.
type fsm_state is
(
reset,reset_wait_ack,reset_wait_bat_completion,reset_wait_id,
reset_set_sample_rate_200,reset_set_sample_rate_200_wait_ack,
reset_send_sample_rate_200,reset_send_sample_rate_200_wait_ack,
reset_set_sample_rate_100,reset_set_sample_rate_100_wait_ack,
reset_send_sample_rate_100,reset_send_sample_rate_100_wait_ack,
reset_set_sample_rate_80,reset_set_sample_rate_80_wait_ack,
reset_send_sample_rate_80,reset_send_sample_rate_80_wait_ack,
reset_read_id,reset_read_id_wait_ack,reset_read_id_wait_id,
reset_set_resolution,reset_set_resolution_wait_ack,
reset_send_resolution,reset_send_resolution_wait_ack,
reset_set_sample_rate_40,reset_set_sample_rate_40_wait_ack,
reset_send_sample_rate_40,reset_send_sample_rate_40_wait_ack,
reset_enable_reporting,reset_enable_reporting_wait_ack,
read_byte_1,read_byte_2,read_byte_3,read_byte_4,
check_read_id,check_read_id_wait_ack,check_read_id_wait_id,
mark_new_event
);
-- holds current state of the FSM
signal state: fsm_state := reset;
-- PS2 Interface and Mouse Controller interconnection signals
-- read_data - from ps2interface
-- - active one clock period when new data received
-- - and available on rx_data
-- err - from ps2interface
-- - active one clock period when error occurred when
-- - receiving or sending data.
-- rx_data - 8 bits, from ps2interface
-- - the byte received from the mouse.
-- tx_data - 8 bits, to ps2interface
-- - byte to be sent to the mouse
-- write_data - to ps2interface
-- - active one clock period when sending a byte to the
-- - ps2interface.
signal read_data : std_logic;
signal err : std_logic;
signal rx_data: std_logic_vector (7 downto 0);
signal tx_data: std_logic_vector (7 downto 0);
signal write_data : std_logic;
-- Periodic checking counter, reset and tick signal
-- The periodic checking counter acts as a watchdog, periodically
-- reading the Mouse ID, therefore checking if the mouse is present
-- If there is no answer, after the timeout period passed, then the
-- state machine is reinitialized
signal periodic_check_cnt : integer range 0 to (CHECK_PERIOD_CLOCKS - 1) := 0;
signal reset_periodic_check_cnt : STD_LOGIC := '0';
signal periodic_check_tick : STD_LOGIC := '0';
-- Self-blocking Timeout checking counter, reset and timeout indication signal
signal timeout_cnt : integer range 0 to (TIMEOUT_PERIOD_CLOCKS - 1) := 0;
signal reset_timeout_cnt : STD_LOGIC := '0';
signal timeout : STD_LOGIC := '0';
begin
Inst_Ps2Interface: Ps2Interface
PORT MAP
(
ps2_clk => ps2_clk,
ps2_data => ps2_data,
clk => clk,
rst => rst,
tx_data => tx_data,
write_data => write_data,
rx_data => rx_data,
read_data => read_data,
busy => open,
err => err
);
-- Create the periodic_check_cnt counter
Count_periodic_check: process (clk, periodic_check_cnt, reset_periodic_check_cnt)
begin
if clk'EVENT AND clk = '1' then
if reset_periodic_check_cnt = '1' then
periodic_check_cnt <= 0;
elsif periodic_check_cnt = (CHECK_PERIOD_CLOCKS - 1) then
periodic_check_cnt <= 0;
else
periodic_check_cnt <= periodic_check_cnt + 1;
end if;
end if;
end process Count_periodic_check;
periodic_check_tick <= '1' when periodic_check_cnt = (CHECK_PERIOD_CLOCKS - 1) else '0';
-- Create the timeout counter
Count_timeout: process (clk, timeout_cnt, reset_timeout_cnt)
begin
if clk'EVENT AND clk = '1' then
if reset_timeout_cnt = '1' then
timeout_cnt <= 0;
elsif timeout_cnt = (TIMEOUT_PERIOD_CLOCKS - 1) then
timeout_cnt <= (TIMEOUT_PERIOD_CLOCKS - 1);
else
timeout_cnt <= timeout_cnt + 1;
end if;
end if;
end process Count_timeout;
timeout <= '1' when timeout_cnt = (TIMEOUT_PERIOD_CLOCKS - 1) else '0';
-- left output the state of the left_down register
left <= left_down when rising_edge(clk);
-- middle output the state of the middle_down register
middle <= middle_down when rising_edge(clk);
-- right output the state of the right_down register
right <= right_down when rising_edge(clk);
-- xpos output is the horizontal position of the mouse
-- it has the range: 0-x_max
xpos <= x_pos(11 downto 0) when rising_edge(clk);
-- ypos output is the vertical position of the mouse
-- it has the range: 0-y_max
ypos <= y_pos(11 downto 0) when rising_edge(clk);
-- sets the value of x_pos from another module when setx is active
-- else, computes the new x_pos from the old position when new x
-- movement detected by adding the delta movement in x_inc, or by
-- adding 256 or -256 when overflow occurs.
set_x: process(clk)
variable x_inter: std_logic_vector(11 downto 0);
variable inc: std_logic_vector(11 downto 0);
begin
if(rising_edge(clk)) then
-- if setx active, set new x_pos value
if(setx = '1') then
x_pos <= value;
-- if delta movement received from mouse
elsif(x_new = '1') then
-- if negative movement on x axis
if(x_sign = '1') then
-- if overflow occurred
if(x_overflow = '1') then
-- inc is -256
inc := "111000000000";
else
-- inc is sign extended x_inc
inc := "1111" & x_inc;
end if;
-- intermediary horizontal position
x_inter := x_pos + inc;
-- if first bit of x_inter is 1
-- then negative overflow occurred and
-- new x position is 0.
-- Note: x_pos and x_inter have 11 bits,
-- and because xpos has only 10, when
-- first bit becomes 1, this is considered
-- a negative number when moving left
if(x_inter(11) = '1') then
x_pos <= (others => '0');
else
x_pos <= x_inter;
end if;
-- if positive movement on x axis
else
-- if overflow occurred
if(x_overflow = '1') then
-- inc is 256
inc := "000100000000";
else
-- inc is sign extended x_inc
inc := "0000" & x_inc;
end if;
-- intermediary horizontal position
x_inter := x_pos + inc;
-- if x_inter is greater than x_max
-- then positive overflow occurred and
-- new x position is x_max.
if(x_inter > ('0' & x_max)) then
x_pos <= x_max;
else
x_pos <= x_inter;
end if;
end if;
end if;
end if;
end process set_x;
-- sets the value of y_pos from another module when sety is active
-- else, computes the new y_pos from the old position when new y
-- movement detected by adding the delta movement in y_inc, or by
-- adding 256 or -256 when overflow occurs.
set_y: process(clk)
variable y_inter: std_logic_vector(11 downto 0);
variable inc: std_logic_vector(11 downto 0);
begin
if(rising_edge(clk)) then
-- if sety active, set new y_pos value
if(sety = '1') then
y_pos <= value;
-- if delta movement received from mouse
elsif(y_new = '1') then
-- if negative movement on y axis
-- Note: axes origin is upper-left corner
if(y_sign = '1') then
-- if overflow occurred
if(y_overflow = '1') then
-- inc is -256
inc := "111100000000";
else
-- inc is sign extended y_inc
inc := "1111" & y_inc;
end if;
-- intermediary vertical position
y_inter := y_pos + inc;
-- if first bit of y_inter is 1
-- then negative overflow occurred and
-- new y position is 0.
-- Note: y_pos and y_inter have 11 bits,
-- and because ypos has only 10, when
-- first bit becomes 1, this is considered
-- a negative number when moving upward
if(y_inter(11) = '1') then
y_pos <= (others => '0');
else
y_pos <= y_inter;
end if;
-- if positive movement on y axis
else
-- if overflow occurred
if(y_overflow = '1') then
-- inc is 256
inc := "000100000000";
else
-- inc is sign extended y_inc
inc := "0000" & y_inc;
end if;
-- intermediary vertical position
y_inter := y_pos + inc;
-- if y_inter is greater than y_max
-- then positive overflow occurred and
-- new y position is y_max.
if(y_inter > (y_max)) then
y_pos <= y_max;
else
y_pos <= y_inter;
end if;
end if;
end if;
end if;
end process set_y;
-- sets the maximum value of the x movement register, stored in x_max
-- when setmax_x is active, max value should be on value input pin
set_max_x: process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
x_max <= DEFAULT_MAX_X;
elsif(setmax_x = '1') then
x_max <= value;
end if;
end if;
end process set_max_x;
-- sets the maximum value of the y movement register, stored in y_max
-- when setmax_y is active, max value should be on value input pin
set_max_y: process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
y_max <= DEFAULT_MAX_Y;
elsif(setmax_y = '1') then
y_max <= value;
end if;
end if;
end process set_max_y;
-- Synchronous one process fsm to handle the communication
-- with the mouse.
-- When reset and at start-up it enters reset state
-- where it begins the procedure of initializing the mouse.
-- After initialization is complete, it waits packets from
-- the mouse.
-- Read at Behavioral decription for details.
manage_fsm: process(clk,rst)
begin
-- when reset occurs, give signals default values.
if(rst = '1') then
state <= reset;
haswheel <= '0';
x_overflow <= '0';
y_overflow <= '0';
x_sign <= '0';
y_sign <= '0';
x_inc <= (others => '0');
y_inc <= (others => '0');
x_new <= '0';
y_new <= '0';
new_event <= '0';
left_down <= '0';
middle_down <= '0';
right_down <= '0';
reset_periodic_check_cnt <= '1';
reset_timeout_cnt <= '1';
elsif(rising_edge(clk)) then
-- at every rising edge of the clock, this signals
-- are reset, thus assuring that they are active
-- for one clock period only if a state sets then
-- because the fsm will transition from the state
-- that set them on the next rising edge of clock.
write_data <= '0';
x_new <= '0';
y_new <= '0';
case state is
-- if just powered-up, reset occurred or some error in
-- transmision encountered, then fsm will transition to
-- this state. Here the RESET command (FF) is sent to the
-- mouse, and various signals receive their default values
-- From here the FSM transitions to a series of states that
-- perform the mouse initialization procedure. All this
-- state are prefixed by "reset_". After sending a byte
-- to the mouse, it respondes by sending ack (FA). All
-- states that wait ack from the mouse are postfixed by
-- "_wait_ack".
-- Read at Behavioral decription for details.
when reset =>
haswheel <= '0';
x_overflow <= '0';
y_overflow <= '0';
x_sign <= '0';
y_sign <= '0';
x_inc <= (others => '0');
y_inc <= (others => '0');
x_new <= '0';
y_new <= '0';
left_down <= '0';
middle_down <= '0';
right_down <= '0';
tx_data <= FF;
write_data <= '1';
reset_periodic_check_cnt <= '1';
reset_timeout_cnt <= '1';
state <= reset_wait_ack;
-- wait ack for the reset command.
-- when received transition to reset_wait_bat_completion.
-- if error occurs go to reset state.
when reset_wait_ack =>
if(read_data = '1') then
-- if received ack
if(rx_data = FA) then
state <= reset_wait_bat_completion;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_wait_ack;
end if;
-- wait for bat completion test
-- mouse should send AA if test is successful
when reset_wait_bat_completion =>
if(read_data = '1') then
if(rx_data = AA) then
state <= reset_wait_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_wait_bat_completion;
end if;
-- the mouse sends its id after performing bat test
-- the mouse id should be 00
when reset_wait_id =>
if(read_data = '1') then
if(rx_data = OO) then
state <= reset_set_sample_rate_200;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_wait_id;
end if;
-- with this state begins the enable wheel mouse
-- procedure. The procedure consists of setting
-- the sample rate of the mouse first 200, then 100
-- then 80. After this is done, the mouse id is
-- requested and if the mouse id is 03, then
-- mouse is in wheel mode and will send 4 byte packets
-- when reporting is enabled.
-- If the id is 00, the mouse does not have a wheel
-- and will send 3 byte packets when reporting is enabled.
-- This state issues the set_sample_rate command to the
-- mouse.
when reset_set_sample_rate_200 =>
tx_data <= SET_SAMPLE_RATE;
write_data <= '1';
state <= reset_set_sample_rate_200_wait_ack;
-- wait ack for set sample rate command
when reset_set_sample_rate_200_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_200;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_200_wait_ack;
end if;
-- send the desired sample rate (200 = 0xC8)
when reset_send_sample_rate_200 =>
tx_data <= "11001000"; -- 0xC8
write_data <= '1';
state <= reset_send_sample_rate_200_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_200_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_set_sample_rate_100;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_200_wait_ack;
end if;
-- send the sample rate command
when reset_set_sample_rate_100 =>
tx_data <= SET_SAMPLE_RATE;
write_data <= '1';
state <= reset_set_sample_rate_100_wait_ack;
-- wait ack for sending the sample rate command
when reset_set_sample_rate_100_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_100;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_100_wait_ack;
end if;
-- send the desired sample rate (100 = 0x64)
when reset_send_sample_rate_100 =>
tx_data <= "01100100"; -- 0x64
write_data <= '1';
state <= reset_send_sample_rate_100_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_100_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_set_sample_rate_80;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_100_wait_ack;
end if;
-- send set sample rate command
when reset_set_sample_rate_80 =>
tx_data <= SET_SAMPLE_RATE;
write_data <= '1';
state <= reset_set_sample_rate_80_wait_ack;
-- wait ack for sending the sample rate command
when reset_set_sample_rate_80_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_80;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_80_wait_ack;
end if;
-- send desired sample rate (80 = 0x50)
when reset_send_sample_rate_80 =>
tx_data <= "01010000"; -- 0x50
write_data <= '1';
state <= reset_send_sample_rate_80_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_80_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_read_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_80_wait_ack;
end if;
-- now the procedure for enabling wheel mode is done
-- the mouse id is read to determine is mouse is in
-- wheel mode.
-- Read ID command is sent to the mouse.
when reset_read_id =>
tx_data <= READ_ID;
write_data <= '1';
state <= reset_read_id_wait_ack;
-- wait ack for sending the read id command
when reset_read_id_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_read_id_wait_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_read_id_wait_ack;
end if;
-- received the mouse id
-- if the id is 00, then the mouse does not have
-- a wheel and haswheel is reset
-- if the id is 03, then the mouse is in scroll mode
-- and haswheel is set.
-- if anything else is received or an error occurred
-- then the FSM transitions to reset state.
when reset_read_id_wait_id =>
if(read_data = '1') then
if(rx_data = "000000000") then
-- the mouse does not have a wheel
haswheel <= '0';
state <= reset_set_resolution;
elsif(rx_data = "00000011") then -- 0x03
-- the mouse is in scroll mode
haswheel <= '1';
state <= reset_set_resolution;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_read_id_wait_id;
end if;
-- send the set resolution command to the mouse
when reset_set_resolution =>
tx_data <= SET_RESOLUTION;
write_data <= '1';
state <= reset_set_resolution_wait_ack;
-- wait ack for sending the set resolution command
when reset_set_resolution_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_send_resolution;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_resolution_wait_ack;
end if;
-- send the desired resolution (0x03 = 8 counts/mm)
when reset_send_resolution =>
tx_data <= RESOLUTION;
write_data <= '1';
state <= reset_send_resolution_wait_ack;
-- wait ack for sending the resolution
when reset_send_resolution_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_set_sample_rate_40;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_resolution_wait_ack;
end if;
-- send the set sample rate command
when reset_set_sample_rate_40 =>
tx_data <= SET_SAMPLE_RATE;
write_data <= '1';
state <= reset_set_sample_rate_40_wait_ack;
-- wait ack for sending the set sample rate command
when reset_set_sample_rate_40_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_40;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_40_wait_ack;
end if;
-- send the desired sampele rate.
-- 40 samples per second is sent.
when reset_send_sample_rate_40 =>
tx_data <= SAMPLE_RATE;
write_data <= '1';
state <= reset_send_sample_rate_40_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_40_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_enable_reporting;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_40_wait_ack;
end if;
-- in this state enable reporting command is sent
-- to the mouse. Before this point, the mouse
-- does not send packets. Only after issuing this
-- command, the mouse begins sending data packets,
-- 3 byte packets if it doesn't have a wheel and
-- 4 byte packets if it is in scroll mode.
when reset_enable_reporting =>
tx_data <= ENABLE_REPORTING;
write_data <= '1';
state <= reset_enable_reporting_wait_ack;
-- wait ack for sending the enable reporting command
when reset_enable_reporting_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= read_byte_1;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_enable_reporting_wait_ack;
end if;
-- this is idle state of the FSM after the
-- initialization is complete.
-- Here the first byte of a packet is waited.
-- The first byte contains the state of the
-- buttons, the sign of the x and y movement
-- and overflow information about these movements
-- First byte looks like this:
-- 7 6 5 4 3 2 1 0
------------------------------------------------------
-- | Y OVF | X OVF | Y SIGN | X SIGN | 1 | M | R | L |
------------------------------------------------------
when read_byte_1 =>
-- Start periodic check counter
reset_periodic_check_cnt <= '0';
-- reset new_event when back in idle state.
new_event <= '0';
-- reset last z delta movement
zpos <= (others => '0');
if(read_data = '1') then
-- mouse button states
left_down <= rx_data(0);
middle_down <= rx_data(2);
right_down <= rx_data(1);
-- sign of the movement data
x_sign <= rx_data(4);
-- y sign is changed to invert the y axis
-- because the mouse uses the lower-left corner
-- as axes origin and it is placed in the upper-left
-- corner by this inversion (suitable for displaying
-- a mouse cursor on the screen).
-- y movement data from the third packet must be
-- also negated.
y_sign <= not rx_data(5);
-- overflow status of the x and y movement
x_overflow <= rx_data(6);
y_overflow <= rx_data(7);
-- transition to state read_byte_2
state <= read_byte_2;
elsif periodic_check_tick = '1' then -- Check periodically if the mouse is present
state <= check_read_id;
else
-- no byte received yet.
state <= read_byte_1;
end if;
-- wait the second byte of the packet
-- this byte contains the x movement counter.
when read_byte_2 =>
if(read_data = '1') then
-- put the delta movement in x_inc
x_inc <= rx_data;
-- signal the arrival of new x movement data.
x_new <= '1';
-- go to state read_byte_3.
state <= read_byte_3;
elsif periodic_check_tick = '1' then -- Check periodically if the mouse is present
state <= check_read_id;
elsif(err = '1') then
state <= reset;
else
-- byte not received yet.
state <= read_byte_2;
end if;
-- wait the third byte of the data, that
-- contains the y data movement counter.
-- negate its value, for the axis to be
-- inverted.
-- If mouse is in scroll mode, transition
-- to read_byte_4, else go to mark_new_event
when read_byte_3 =>
if(read_data = '1') then
-- when y movement is 0, then ignore
if(rx_data /= "00000000") then
-- 2's complement positive numbers
-- become negative and vice versa
y_inc <= (not rx_data) + "00000001";
y_new <= '1';
end if;
-- if the mouse has a wheel then transition
-- to read_byte_4, else go to mark_new_event
if(haswheel = '1') then
state <= read_byte_4;
else
state <= mark_new_event;
end if;
elsif periodic_check_tick = '1' then -- Check periodically if the mouse is present
state <= check_read_id;
elsif(err = '1') then
state <= reset;
else
state <= read_byte_3;
end if;
-- only reached when mouse is in scroll mode
-- wait for the fourth byte to arrive
-- fourth byte contains the z movement counter
-- only least significant 4 bits are relevant
-- the rest are sign extension.
when read_byte_4 =>
if(read_data = '1') then
-- zpos is the delta movement on z
zpos <= rx_data(3 downto 0);
-- packet completly received,
-- go to mark_new_event
state <= mark_new_event;
elsif periodic_check_tick = '1' then -- Check periodically if the mouse is present
state <= check_read_id;
elsif(err = '1') then
state <= reset;
else
state <= read_byte_4;
end if;
-- From timer to time determined by the CHECK_TICK_PERIOD_MS,
-- Read ID command is sent to the mouse.
when check_read_id =>
-- Start the timeout counter
reset_timeout_cnt <= '0';
tx_data <= READ_ID;
write_data <= '1';
state <= check_read_id_wait_ack;
-- wait ack for sending the read id command
when check_read_id_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= check_read_id_wait_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
elsif (timeout = '1') then -- Timeout ocurred, so the mouse is not present, go to the reset state
state <= reset;
else
state <= check_read_id_wait_ack;
end if;
-- received the mouse id
-- It means that the mouse is present and reading data
-- can continue
-- if anything else is received or timeout or an error occurred
-- then the FSM transitions to reset state.
when check_read_id_wait_id =>
if(read_data = '1') then
if(rx_data = "000000000") or (rx_data = "00000011") then
-- The mouse is present, so reset the timeout counter
reset_timeout_cnt <= '1';
state <= read_byte_1;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
elsif (timeout = '1') then-- Timeout ocurred, so the mouse is not present, go to the reset state
state <= reset;
else
state <= check_read_id_wait_id;
end if;
-- set new_event high
-- it will be reset in next state
-- informs client new packet received and processed
when mark_new_event =>
new_event <= '1';
state <= read_byte_1;
-- if invalid transition occurred, reset
when others =>
state <= reset;
end case;
end if;
end process manage_fsm;
end Behavioral;
|
gpl-3.0
|
27aa66e7338fcc0cede43d900046d450
| 0.51306 | 4.474152 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/thermal_monitor_v1_03_a/hdl/vhdl/ring_oscillator.vhd
| 1 | 3,068 |
----------------------------------------------------------------------------------
-- Company: University of Paderborn
-- Engineer: Markus Happe
--
-- Create Date: 15:04:59 02/09/2011
-- Design Name:
-- Module Name: ring_oscillator - Behavioral
-- Project Name: Thermal Sensor Net
-- Target Devices: Virtex 6 ML605
-- Tool versions: 12.3
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity ring_oscillator is
-- generic for size of ring oscillator ( = number of inverters)
generic ( C_OSC_SIZE : integer := 11);
port (
-- reset
rst : in std_logic;
-- enable
osc_en : in std_logic;
-- outgoing signal
osc_out : out std_logic);
end ring_oscillator;
architecture Behavioral of ring_oscillator is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
component delay_comp is
port ( rst : in std_logic;
x_in : in std_logic;
x_out : out std_logic);
end component;
component inv_comp is
port ( rst : in std_logic;
x_in : in std_logic;
x_out : out std_logic);
end component;
signal x : std_logic_vector (1*C_OSC_SIZE downto 0);
attribute KEEP : string;
attribute KEEP of x : signal is "true";
signal toggle : std_logic;
signal clk_div2 : std_logic;
attribute INIT : string;
attribute INIT of div2_lut : label is "1";
begin
osc_out <= clk_div2;
toggle_flop: FD
port map ( D => toggle,
Q => clk_div2,
C => x(0)
);
div2_lut: LUT2
--synthesies translate_off
generic map (INIT => X"1")
--synthesies translate_on
port map( I0 => rst,
I1 => clk_div2,
O => toggle
);
out_lut: AND2
port map( I0 => osc_en,
I1 => x(1*C_OSC_SIZE),
O => x(0)
);
-- ring oscillator
ring : for i in 0 to C_OSC_SIZE - 1 generate
begin
-- delay_1 : delay_comp
-- port map(
-- rst => rst,
-- x_in => x(0+(i*3)),
-- x_out => x(1+(i*3))
-- );
--
-- delay_2 : delay_comp
-- port map(
-- rst => rst,
-- x_in => x(1+(i*3)),
-- x_out => x(2+(i*3))
-- );
-- delay_3 : delay_comp
-- port map(
-- rst => rst,
-- x_in => x(2+(i*5)),
-- x_out => x(3+(i*5))
-- );
--
-- delay_4 : delay_comp
-- port map(
-- rst => rst,
-- x_in => x(3+(i*5)),
-- x_out => x(4+(i*5))
-- );
inv_1 : inv_comp
port map(
rst => rst,
x_in => x(0+(i*1)),
x_out => x(1+(i*1))
);
end generate ring;
end Behavioral;
|
gpl-3.0
|
14f53692c0ce03d84ece57504db41f2e
| 0.466754 | 3.36035 | false | false | false | false |
dries007/Basys3
|
VGA/VGA.srcs/sources_1/new/DBounce.vhd
| 1 | 2,330 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04.03.2016 11:38:15
-- Design Name:
-- Module Name: DBounce - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity DBounce is
Port(
clk, nreset : in std_logic;
button_in : in std_logic;
DB_out : buffer std_logic
);
end DBounce;
architecture arch of DBounce is
constant N : integer := 21; -- 2^20 * 1/(33MHz) = 32ms
signal q_reg, q_next : unsigned(N-1 downto 0);
signal DFF1, DFF2 : std_logic;
signal q_reset, q_add : std_logic;
begin
-- COUNTER FOR TIMING
q_next <= (others => '0') when q_reset = '1' else -- resets the counter
q_reg + 1 when q_add = '1' else -- increment count if commanded
q_reg;
-- SYNCHRO REG UPDATE
process(clk, nreset)
begin
if(rising_edge(clk)) then
if(nreset = '0') then
q_reg <= (others => '0'); -- reset counter
else
q_reg <= q_next; -- update counter reg
end if;
end if;
end process;
-- Flip Flop Inputs
process(clk, button_in)
begin
if(rising_edge(clk)) then
if(nreset = '0') then
DFF1 <= '0';
DFF2 <= '0';
else
DFF1 <= button_in;
DFF2 <= DFF1;
end if;
end if;
end process;
q_reset <= DFF1 xor DFF2; -- if DFF1 and DFF2 are different q_reset <= '1';
-- Counter Control Based on MSB of counter, q_reg
process(clk, q_reg, DB_out)
begin
if(rising_edge(clk)) then
q_add <= not(q_reg(N-1)); -- enables the counter whe msb is not '1'
if(q_reg(N-1) = '1') then
DB_out <= DFF2;
else
DB_out <= DB_out;
end if;
end if;
end process;
end arch;
|
mit
|
318232add3dde4ead8fad0826b98dc1c
| 0.457511 | 3.758065 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.srcs/sources_1/new/top.vhd
| 1 | 221,124 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.Font.all;
entity top is
Port (
vgaRed : out std_logic_vector (3 downto 0);
vgaGreen : out std_logic_vector (3 downto 0);
vgaBlue : out std_logic_vector (3 downto 0);
Hsync : out std_logic;
Vsync : out std_logic;
PS2Clk : in std_logic;
PS2Data : in std_logic;
--led : out std_logic_vector (15 downto 0);
clk : in std_logic
);
end top;
architecture Behavioral of top is
-- CONSTANTS ----------------------------------------------------
constant COLS : integer := 160;
constant ROWS : integer := 64;
constant CHARS : integer := COLS * ROWS;
constant ROM_SIZE : integer := CHARS * 2;
constant CPU_FREQ : integer := 9_000_000;
-- CLOCK --------------------------------------------------------
component ClockDivider
port (
clk : in std_logic;
clk_vga : out std_logic;
clk_cpu : out std_logic;
clk_2cpu : out std_logic
);
end component;
signal clk_vga : std_logic := '0';
signal clk_cpu : std_logic := '0';
signal clk_2cpu : std_logic := '0';
signal clk_10 : std_logic := '0';
signal clk_2 : std_logic := '0';
signal clk_1 : std_logic := '0';
signal clk_1k : std_logic := '0';
-- VGA controller -----------------------------------------------
component Vga
Port (
clk : in std_logic;
hSync : out std_logic;
vSync : out std_logic;
vgaRed : out std_logic_vector (3 downto 0);
vgaGreen : out std_logic_vector (3 downto 0);
vgaBlue : out std_logic_vector (3 downto 0);
fbOutAddr : out std_logic_vector(13 downto 0);
fbOutDat : in std_logic_vector(7 downto 0)
);
end component;
signal vga_addr : std_logic_vector(13 downto 0) := (others =>'0');
signal vga_dat : std_logic_vector(7 downto 0) := (others =>'0');
-- FRAMEBUFFER --------------------------------------------------
-- NEEDS to run at 2x CPU freq, for 1 CPU cycle mem access
component Framebuffer is
port (
clka : in std_logic;
ena : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(13 downto 0);
dina : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0);
clkb : in std_logic;
web : in std_logic_vector(0 downto 0);
addrb : in std_logic_vector(13 downto 0);
dinb : in std_logic_vector(7 downto 0);
doutb : out std_logic_vector(7 downto 0)
);
end component;
signal fb_a_we : std_logic_vector(0 downto 0) := (others =>'0');
signal fb_a_addr : std_logic_vector(13 downto 0) := (others =>'0');
signal fb_a_dat_in : std_logic_vector(7 downto 0) := (others =>'0');
signal fb_a_dat_out : std_logic_vector(7 downto 0) := (others =>'0');
signal fb_a_en : std_logic := '0';
-- ROM --------------------------------------------------
-- NEEDS to run at 2x CPU freq, for 1 CPU cycle mem access
component Rom is
port (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end component;
signal rom_addr : std_logic_vector(14 downto 0) := (others =>'0');
signal rom_dat : std_logic_vector(7 downto 0) := (others =>'0');
-- KEYBOARD CONTROLLER ------------------------------------------
-- NEEDS to be at CPU freq
component ps2_keyboard_to_ascii is
Generic
(
CLK_FREQ : integer := CPU_FREQ
);
Port
(
clk : in std_logic; --system clock input
ps2_clk : in std_logic; --clock signal from ps2 keyboard
ps2_data : in std_logic; --data signal from ps2 keyboard
ascii_new : out std_logic; --output flag indicating new ascii value
ascii_code : out std_logic_vector(6 downto 0) --ascii value
);
end component;
signal kb_event : std_logic := '0';
signal kb_acsii : std_logic_vector(6 downto 0) := (others => '0');
-- RNG ----------------------------------------------------------
component Prng is
Generic
(
BITS : integer := 16
);
Port
(
seed : in std_logic_vector (16-1 downto 0);
seed_en : in std_logic;
clk : in std_logic;
rnd : out std_logic_vector (16-1 downto 0)
);
end component;
signal rng_seed : std_logic_vector(15 downto 0) := (others =>'0');
signal rng_seed_en : std_logic := '0';
signal rng_out : std_logic_vector(15 downto 0) := (others =>'0');
-- MISC ---------------------------------------------------------
-- runtime in ms
signal runtime : unsigned(32 downto 0) := (others => '0');
-- FUNCTIONS ----------------------------------------------------
function index_delta(current : integer range 0 to CHARS; delta : integer range -CHARS to CHARS := 1; modulo : integer range 0 to CHARS := CHARS) return integer is
begin
return (current + delta) mod modulo;
end index_delta;
function pad_string(input : string; size : positive; char : character := character'val(0)) return string is
variable tmp: string(1 to size) := (others => NUL);
begin
if input'length >= size then
tmp := input(1 to size);
else
tmp(1 to input'length) := input;
tmp(input'length + 1 to size) := (others => char);
end if;
return tmp;
end pad_string;
function ascii_i(i : integer range -999_999 to 999_999; didget : integer range 0 to 10 := 0; inverted : boolean := false; sign : boolean := false) return std_logic_vector(7 downto 0) is
variable tmp : std_logic_vector(7 downto 0) := (others => '0');
begin
if inverted then
tmp(7) := '1';
end if;
if sign then
if i > 0 then
tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('+'), 7));
else
tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('-'), 7));
end if;
else
tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('0') + ((i mod (10 ** (didget + 1))) / (10 ** didget)), 7));
end if;
return tmp;
end ascii_i;
--------------------------------------------------------
begin -- BEGIN
--------------------------------------------------------
clock0: ClockDivider
port map (
clk => clk,
clk_vga => clk_vga,
clk_cpu => clk_cpu,
clk_2cpu => clk_2cpu
);
-- Slow clock devider
process (clk_cpu)
constant MAX : integer := CPU_FREQ/2;
variable i : integer range 0 to MAX := 0;
begin
if rising_edge(clk_cpu) then
if i < MAX then
i := i + 1;
else
i := 0;
end if;
if i = 0 then
clk_1 <= not(clk_1);
end if;
if i mod (MAX / 2) = 0 then
clk_2 <= not(clk_2);
end if;
if i mod (MAX / 1000) = 0 then
clk_1k <= not(clk_1k);
end if;
if i mod (MAX / 10) = 0 then
clk_10 <= not(clk_10);
end if;
end if;
end process;
-- VGA controller -----------------------------------------------
vga0: Vga
port map (
clk => clk_vga,
hSync => Hsync,
vSync => Vsync,
vgaRed => vgaRed,
vgaGreen => vgaGreen,
vgaBlue => vgaBlue,
fbOutAddr => vga_addr,
fbOutDat => vga_dat
);
-- FRAMEBUFFER --------------------------------------------------
frameBuffer0: Framebuffer
port map (
clka => clk_2cpu,
ena => fb_a_en,
wea => fb_a_we,
addra => fb_a_addr,
dina => fb_a_dat_in,
douta => fb_a_dat_out,
clkb => clk_vga,
web => "0",
addrb => vga_addr,
dinb => x"00",
doutb => vga_dat
);
-- ROM ----------------------------------------------------------
rom0: Rom
port map (
clka => clk_2cpu,
addra => rom_addr,
douta => rom_dat
);
-- RNG ----------------------------------------------------------
prng0: Prng
port map (
seed => rng_seed,
seed_en => rng_seed_en,
clk => clk_cpu,
rnd => rng_out
);
-- KEYBOARD CONTROLLER ------------------------------------------
keyboard0: ps2_keyboard_to_ascii
port map (
clk => clk_cpu,
ps2_clk => PS2Clk,
ps2_data => PS2Data,
ascii_new => kb_event,
ascii_code => kb_acsii
);
-- MISC ---------------------------------------------------------
-- runtime counter
process (clk_1k)
begin
if rising_edge(clk_1k) then
runtime <= runtime + 1;
end if;
end process;
--led <= clk_1 & clk_2 & std_logic_vector(runtime(17 downto 4));
-- CPU ---------------------------------------------------------
process (clk_cpu)
-- State stack system
constant STATE_STACK_MAX : integer := 15;
type state_type is (COPY, COPY2, RESET, ERROR, ERROR_STUCK, WRITE, READ, READ_MENU, BLANK,
-- SCROLL, SCROLL_W,
GAME_R_0, GAME_R_ROLL, GAME_R_PLACE_START, GAME_R_PLACE_BET, GAME_R_PLACE_SAVE,
GAME_HL_0, GAME_HL_BET, GAME_HL_BET_2
);
type state_type_arry is array(STATE_STACK_MAX downto 0) of state_type;
variable state_index : integer range 0 to STATE_STACK_MAX := 0;
variable state : state_type_arry := (others => RESET);
-- Frame buffer index (also used as loop counter)
variable fb_index : integer range 0 to CHARS := 0;
-- Could have used enum, but then had to convert to ints anyway
constant GAMES : integer := 2; -- count of
constant GAME_R : integer := 0;
constant GAME_HL : integer := 1;
variable game : integer range 0 to GAMES-1 := 0;
variable money : integer range 0 to 999_999_99 := 1_000_00; -- in cents
variable rnd : integer range 0 to 36; -- used for storing last rnd number from both games
variable input : integer range 0 to 1_000_00 := 0; -- used to read a number from keyboard & for menu structures
variable input_max : integer range 0 to 1_000_00 := 1_000_00; -- used to limit the input
variable msg_inverted : std_logic := '0'; -- invert the text aka set the first bit
variable msg : string(1 to CHARS); -- maximum of 160 characters, used by WRITE
variable msg_index : integer range 0 to CHARS := 0; -- used by WRITE to store internal position within the msg
-- STUFF FOR ROULETTE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
constant R_MONEY_START : integer := 3132; -- For printing the $ --- ---.-- string
constant R_RND_START : integer := 3108; -- For printing the rolled number
-- stack-like system for placing bets
constant BETS_MAX : integer := 25; -- place maximum of 25 bets per game
type bet_type is
record
kind : integer range 0 to 8; -- type of bet, but type is a reserved keyword. vhdl naming is torture 0=NONE 1=Plein 2=Cheval(Horizontal) 3=Cheval(Vertical) 4=Trans 5=TransSimple 6=Carre 7=Colonne 8=Simple
number : integer range 0 to 36; -- meaning depends on type of bet
money : integer range 0 to 1_000_00; -- max bet per bet
end record;
type bets_type is array (BETS_MAX downto 0) of bet_type;
variable bets_index : integer range 0 to BETS_MAX := 0;
variable bets : bets_type;
-- STUFF FOR HL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
constant HL_MONEY_START : integer := 3129; -- fb index for printing the $ --- ---.-- string
constant HL_FIRST_CARD : integer := 3788; -- fb index for printing the first card
constant HL_SECOND_CARD : integer := 4108; -- fb index for printing the second card
variable card_first : integer range 2 to 12 := 2;
variable bet_higher : boolean := true;
variable bet_money : integer range 0 to 1_000_00 := 0;
begin
if rising_edge(clk_cpu) then
rng_seed_en <= '0';
fb_a_en <= '0';
fb_a_we <= "0";
case state(state_index) is
---------------------------------------------
when COPY =>
fb_index := 0;
rom_addr <= std_logic_vector(to_unsigned(CHARS * game, 15));
state(state_index) := COPY2;
when COPY2 =>
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(fb_index, 14));
fb_a_dat_in <= rom_dat;
fb_index := index_delta(fb_index);
rom_addr <= std_logic_vector(to_unsigned(CHARS * game + fb_index, 15));
if fb_index = 0 then
state_index := state_index - 1;
end if;
---------------------------------------------
when RESET =>
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(game * COLS + 23 * COLS + 70, 14));
fb_a_dat_in <= x"10"; -- '>' indicator arrow
if kb_event = '1' then
case '0' & kb_acsii is
-- vhdl syntax is strang. ()'s are required to make it show up as a boolean?
when (x"01") | (x"38") => -- up or 8
fb_a_dat_in <= x"20"; -- space
game := index_delta(game, modulo => GAMES);
when (x"02") | (x"32") => -- down or 2
fb_a_dat_in <= x"20"; -- space
game := index_delta(game, delta => -1, modulo => GAMES);
when x"0d" => -- enter
rng_seed <= std_logic_vector(runtime(15 downto 0));
rng_seed_en <= '1';
case game is
when GAME_R =>
state(state_index) := GAME_R_0; -- override current status, we don't need to come back.
when GAME_HL =>
state(state_index) := GAME_HL_0; -- override current status, we don't need to come back.
end case;
state_index := state_index + 1; state(state_index) := COPY; -- But first, copy the game screen
when others =>
-- nop
end case;
end if;
---------------------------------------------
when GAME_HL_0 =>
fb_index := index_delta(fb_index); -- by default +1 index
case fb_index is
when 1 =>
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(HL_MONEY_START, 14));
fb_a_dat_in <= ascii_i(money, 7);
when 2 =>
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(HL_MONEY_START + 1, 14));
fb_a_dat_in <= ascii_i(money, 6);
when 3 =>
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(HL_MONEY_START + 2, 14));
fb_a_dat_in <= ascii_i(money, 5);
when 4 => -- Space, so skip '+ 3'
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(HL_MONEY_START + 4, 14));
fb_a_dat_in <= ascii_i(money, 4);
when 5 =>
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(HL_MONEY_START + 5, 14));
fb_a_dat_in <= ascii_i(money, 3);
when 6 =>
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(HL_MONEY_START + 6, 14));
fb_a_dat_in <= ascii_i(money, 2);
when 7 => -- Dot, so skip '+ 7'
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(HL_MONEY_START + 8, 14));
fb_a_dat_in <= ascii_i(money, 1);
when 8 =>
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(HL_MONEY_START + 9, 14));
fb_a_dat_in <= ascii_i(money, 0);
when 10 => -- pick number (2 -> 12)
card_first := 2 + (to_integer(unsigned(rng_out)) mod 11);
when 20 =>
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(HL_FIRST_CARD, 14));
fb_a_dat_in <= ascii_i(card_first, 1);
when 21 =>
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(HL_FIRST_CARD + 1, 14));
fb_a_dat_in <= ascii_i(card_first, 0);
when COLS * 49 =>
msg := pad_string(" Bet higher", msg'LENGTH);
state_index := state_index + 1; state(state_index) := WRITE;
when COLS * 50 =>
msg := pad_string(" Bet lower", msg'LENGTH);
state_index := state_index + 1; state(state_index) := WRITE;
when COLS * 51 =>
input_max := 2;
input := 0;
state_index := state_index + 1; state(state_index) := READ_MENU;
when COLS * 51 + 1 =>
if input = 1 then -- 0 = higher, 1 = lower
bet_higher := false;
else
bet_higher := true;
end if;
state(state_index) := GAME_HL_BET;
fb_index := COLS * 49; -- start of blanking
state_index := state_index + 1; state(state_index) := BLANK; -- blank from line 49 to last-1 line
when others =>
end case;
if money < 100 then
state(state_index) := ERROR_STUCK; -- override return state
state_index := state_index + 1; state(state_index) := WRITE; -- put next state on stack
msg_inverted := '1';
msg := pad_string("You are out of money...", msg'LENGTH);
fb_index := 0;
end if;
---------------------------------------------
when GAME_HL_BET =>
state(state_index) := GAME_HL_BET_2; -- after amount, save & go back to main menu
input := 0; -- reset
if money > 1_000_00 then -- can't bet more then you have
input_max := 1_000_00;
else
input_max := money;
end if;
state_index := state_index + 1; state(state_index) := READ; -- read = state after write
fb_index := COLS * 49; -- position question
msg := pad_string(" Amount? (Max 1 000.00 $) ", msg'LENGTH);
state_index := state_index + 1; state(state_index) := WRITE;
---------------------------------------------
when GAME_HL_BET_2 =>
fb_index := index_delta(fb_index); -- by default +1 index
case fb_index is
when COLS * 50 =>
money := money - input;
bet_money := input;
rnd := 1 + (to_integer(unsigned(rng_out)) mod 13); -- pick number (1 -> 13)
when COLS * 50 + 1 =>
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(HL_SECOND_CARD, 14));
fb_a_dat_in <= ascii_i(rnd, 1);
when COLS * 50 + 2 =>
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(HL_SECOND_CARD + 1, 14));
fb_a_dat_in <= ascii_i(rnd, 0);
when COLS * 50 + 3 =>
if rnd = card_first then -- 1:1 payout
money := money + bet_money;
state(state_index) := GAME_HL_0; -- go back to main menu
fb_index := COLS * 49; -- start of blanking
state_index := state_index + 1; state(state_index) := BLANK; -- blank from line 49 to last-1 line
end if;
when COLS * 50 + 4 =>
if rnd < card_first then
fb_index := COLS * 51 - 1; -- -1 for default +1
else
fb_index := COLS * 52 - 1; -- -1 for default +1
end if;
when COLS * 51 => ------------------ RND < FIRST CARD aka LOWER
if bet_higher then -- you lost
state(state_index) := GAME_HL_0; -- go back to main menu
fb_index := COLS * 49; -- start of blanking
state_index := state_index + 1; state(state_index) := BLANK; -- blank from line 49 to last-1 line
end if;
when COLS * 51 + 1 => -- you won, but how much?
case card_first is
when 2 => money := money + ((bet_money * 107) / 10); -- *x/10 because no floating point stuff
when 3 => money := money + ((bet_money * 53) / 10);
when 4 => money := money + ((bet_money * 35) / 10);
when 5 => money := money + ((bet_money * 26) / 10);
when 6 => money := money + ((bet_money * 21) / 10);
when 7 => money := money + ((bet_money * 17) / 10);
when 8 => money := money + ((bet_money * 15) / 10);
when 9 => money := money + ((bet_money * 13) / 10);
when 10 to 12 => money := money + ((bet_money * 11) / 10);
end case;
state(state_index) := GAME_HL_0; -- go back to main menu
fb_index := COLS * 49; -- start of blanking
state_index := state_index + 1; state(state_index) := BLANK; -- blank from line 49 to last-1 line
when COLS * 52 => ------------------ RND > FIRST CARD aka HIGER
if not bet_higher then -- you lost
state(state_index) := GAME_HL_0; -- go back to main menu
fb_index := COLS * 49; -- start of blanking
state_index := state_index + 1; state(state_index) := BLANK; -- blank from line 49 to last-1 line
end if;
when COLS * 52 + 1 => -- you won, but how much?
case card_first is
when 12 => money := money + ((bet_money * 107) / 10);
when 11 => money := money + ((bet_money * 53) / 10);
when 10 => money := money + ((bet_money * 35) / 10);
when 9 => money := money + ((bet_money * 26) / 10);
when 8 => money := money + ((bet_money * 21) / 10);
when 7 => money := money + ((bet_money * 17) / 10);
when 6 => money := money + ((bet_money * 15) / 10);
when 5 => money := money + ((bet_money * 13) / 10);
when 2 to 4 => money := money + ((bet_money * 11) / 10);
end case;
state(state_index) := GAME_HL_0; -- go back to main menu
fb_index := COLS * 49; -- start of blanking
state_index := state_index + 1; state(state_index) := BLANK; -- blank from line 49 to last-1 line
when others =>
end case;
---------------------------------------------
when GAME_R_0 =>
-- by default +1 index & enable write to fb
fb_index := index_delta(fb_index);
fb_a_en <= '1';
fb_a_we <= "1";
case fb_index is -- start with 1 because of the default +1
when 1 =>
fb_a_addr <= std_logic_vector(to_unsigned(R_MONEY_START, 14));
fb_a_dat_in <= ascii_i(money, 7);
when 2 =>
fb_a_addr <= std_logic_vector(to_unsigned(R_MONEY_START + 1, 14));
fb_a_dat_in <= ascii_i(money, 6);
when 3 =>
fb_a_addr <= std_logic_vector(to_unsigned(R_MONEY_START + 2, 14));
fb_a_dat_in <= ascii_i(money, 5);
when 4 => -- Space, so skip '+ 3'
fb_a_addr <= std_logic_vector(to_unsigned(R_MONEY_START + 4, 14));
fb_a_dat_in <= ascii_i(money, 4);
when 5 =>
fb_a_addr <= std_logic_vector(to_unsigned(R_MONEY_START + 5, 14));
fb_a_dat_in <= ascii_i(money, 3);
when 6 =>
fb_a_addr <= std_logic_vector(to_unsigned(R_MONEY_START + 6, 14));
fb_a_dat_in <= ascii_i(money, 2);
when 7 => -- Dot, so skip '+ 7'
fb_a_addr <= std_logic_vector(to_unsigned(R_MONEY_START + 8, 14));
fb_a_dat_in <= ascii_i(money, 1);
when 8 =>
fb_a_addr <= std_logic_vector(to_unsigned(R_MONEY_START + 9, 14));
fb_a_dat_in <= ascii_i(money, 0);
when 10 =>
fb_a_addr <= std_logic_vector(to_unsigned(R_RND_START, 14));
fb_a_dat_in <= ascii_i(rnd, 1);
when 11 =>
fb_a_addr <= std_logic_vector(to_unsigned(R_RND_START + 1, 14));
fb_a_dat_in <= ascii_i(rnd, 0);
-- Show number of bets placed
when 20 =>
fb_a_addr <= std_logic_vector(to_unsigned(COLS*19 + 149, 14));
fb_a_dat_in <= ascii_i(bets_index, 1);
when 21 =>
fb_a_addr <= std_logic_vector(to_unsigned(COLS*19 + 150, 14));
fb_a_dat_in <= ascii_i(bets_index, 0);
-- -- ============================================================ PYTHON GENERATED VHDL ============================================================
-- -- This code should generate 25 bets with names: ('Plain', 'Cheval H', 'Cheval V', 'Trans', 'Trans S', 'Carre', 'Colonne', 'Simple')
-- when COLS*21 + COLS*0 + 0 => if bets_index <= 0 then fb_index := COLS*21 + COLS*1 - 1; end if;-- skip this row
-- when COLS*21 + COLS*0 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*0 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*0 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*0 + 113, 14)); fb_a_dat_in <= ascii_i(bets(0).money, 5);
-- when COLS*21 + COLS*0 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*0 + 115, 14)); fb_a_dat_in <= ascii_i(bets(0).money, 4);
-- when COLS*21 + COLS*0 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*0 + 116, 14)); fb_a_dat_in <= ascii_i(bets(0).money, 3);
-- when COLS*21 + COLS*0 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*0 + 117, 14)); fb_a_dat_in <= ascii_i(bets(0).money, 2);
-- when COLS*21 + COLS*0 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*0 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*0 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*0 + 119, 14)); fb_a_dat_in <= ascii_i(bets(0).money, 1);
-- when COLS*21 + COLS*0 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*0 + 120, 14)); fb_a_dat_in <= ascii_i(bets(0).money, 0);
-- when COLS*21 + COLS*0 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*0 + 122, 14));
-- case bets(0).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*0 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*0 + 123, 14));
-- case bets(0).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*0 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*0 + 124, 14));
-- case bets(0).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*0 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*0 + 125, 14));
-- case bets(0).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*0 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*0 + 126, 14));
-- case bets(0).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*0 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*0 + 127, 14));
-- case bets(0).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*0 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*0 + 128, 14));
-- case bets(0).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*0 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*0 + 129, 14));
-- case bets(0).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*0 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*0 + 131, 14)); fb_a_dat_in <= ascii_i(bets(0).number, 1);
-- when COLS*21 + COLS*0 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*0 + 132, 14)); fb_a_dat_in <= ascii_i(bets(0).number, 0);
-- when COLS*21 + COLS*1 + 0 => if bets_index <= 1 then fb_index := COLS*21 + COLS*2 - 1; end if;-- skip this row
-- when COLS*21 + COLS*1 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*1 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*1 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*1 + 113, 14)); fb_a_dat_in <= ascii_i(bets(1).money, 5);
-- when COLS*21 + COLS*1 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*1 + 115, 14)); fb_a_dat_in <= ascii_i(bets(1).money, 4);
-- when COLS*21 + COLS*1 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*1 + 116, 14)); fb_a_dat_in <= ascii_i(bets(1).money, 3);
-- when COLS*21 + COLS*1 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*1 + 117, 14)); fb_a_dat_in <= ascii_i(bets(1).money, 2);
-- when COLS*21 + COLS*1 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*1 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*1 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*1 + 119, 14)); fb_a_dat_in <= ascii_i(bets(1).money, 1);
-- when COLS*21 + COLS*1 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*1 + 120, 14)); fb_a_dat_in <= ascii_i(bets(1).money, 0);
-- when COLS*21 + COLS*1 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*1 + 122, 14));
-- case bets(1).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*1 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*1 + 123, 14));
-- case bets(1).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*1 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*1 + 124, 14));
-- case bets(1).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*1 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*1 + 125, 14));
-- case bets(1).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*1 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*1 + 126, 14));
-- case bets(1).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*1 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*1 + 127, 14));
-- case bets(1).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*1 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*1 + 128, 14));
-- case bets(1).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*1 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*1 + 129, 14));
-- case bets(1).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*1 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*1 + 131, 14)); fb_a_dat_in <= ascii_i(bets(1).number, 1);
-- when COLS*21 + COLS*1 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*1 + 132, 14)); fb_a_dat_in <= ascii_i(bets(1).number, 0);
-- when COLS*21 + COLS*2 + 0 => if bets_index <= 2 then fb_index := COLS*21 + COLS*3 - 1; end if;-- skip this row
-- when COLS*21 + COLS*2 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*2 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*2 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*2 + 113, 14)); fb_a_dat_in <= ascii_i(bets(2).money, 5);
-- when COLS*21 + COLS*2 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*2 + 115, 14)); fb_a_dat_in <= ascii_i(bets(2).money, 4);
-- when COLS*21 + COLS*2 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*2 + 116, 14)); fb_a_dat_in <= ascii_i(bets(2).money, 3);
-- when COLS*21 + COLS*2 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*2 + 117, 14)); fb_a_dat_in <= ascii_i(bets(2).money, 2);
-- when COLS*21 + COLS*2 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*2 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*2 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*2 + 119, 14)); fb_a_dat_in <= ascii_i(bets(2).money, 1);
-- when COLS*21 + COLS*2 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*2 + 120, 14)); fb_a_dat_in <= ascii_i(bets(2).money, 0);
-- when COLS*21 + COLS*2 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*2 + 122, 14));
-- case bets(2).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*2 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*2 + 123, 14));
-- case bets(2).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*2 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*2 + 124, 14));
-- case bets(2).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*2 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*2 + 125, 14));
-- case bets(2).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*2 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*2 + 126, 14));
-- case bets(2).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*2 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*2 + 127, 14));
-- case bets(2).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*2 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*2 + 128, 14));
-- case bets(2).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*2 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*2 + 129, 14));
-- case bets(2).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*2 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*2 + 131, 14)); fb_a_dat_in <= ascii_i(bets(2).number, 1);
-- when COLS*21 + COLS*2 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*2 + 132, 14)); fb_a_dat_in <= ascii_i(bets(2).number, 0);
-- when COLS*21 + COLS*3 + 0 => if bets_index <= 3 then fb_index := COLS*21 + COLS*4 - 1; end if;-- skip this row
-- when COLS*21 + COLS*3 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*3 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*3 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*3 + 113, 14)); fb_a_dat_in <= ascii_i(bets(3).money, 5);
-- when COLS*21 + COLS*3 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*3 + 115, 14)); fb_a_dat_in <= ascii_i(bets(3).money, 4);
-- when COLS*21 + COLS*3 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*3 + 116, 14)); fb_a_dat_in <= ascii_i(bets(3).money, 3);
-- when COLS*21 + COLS*3 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*3 + 117, 14)); fb_a_dat_in <= ascii_i(bets(3).money, 2);
-- when COLS*21 + COLS*3 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*3 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*3 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*3 + 119, 14)); fb_a_dat_in <= ascii_i(bets(3).money, 1);
-- when COLS*21 + COLS*3 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*3 + 120, 14)); fb_a_dat_in <= ascii_i(bets(3).money, 0);
-- when COLS*21 + COLS*3 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*3 + 122, 14));
-- case bets(3).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*3 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*3 + 123, 14));
-- case bets(3).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*3 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*3 + 124, 14));
-- case bets(3).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*3 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*3 + 125, 14));
-- case bets(3).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*3 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*3 + 126, 14));
-- case bets(3).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*3 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*3 + 127, 14));
-- case bets(3).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*3 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*3 + 128, 14));
-- case bets(3).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*3 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*3 + 129, 14));
-- case bets(3).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*3 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*3 + 131, 14)); fb_a_dat_in <= ascii_i(bets(3).number, 1);
-- when COLS*21 + COLS*3 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*3 + 132, 14)); fb_a_dat_in <= ascii_i(bets(3).number, 0);
-- when COLS*21 + COLS*4 + 0 => if bets_index <= 4 then fb_index := COLS*21 + COLS*5 - 1; end if;-- skip this row
-- when COLS*21 + COLS*4 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*4 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*4 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*4 + 113, 14)); fb_a_dat_in <= ascii_i(bets(4).money, 5);
-- when COLS*21 + COLS*4 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*4 + 115, 14)); fb_a_dat_in <= ascii_i(bets(4).money, 4);
-- when COLS*21 + COLS*4 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*4 + 116, 14)); fb_a_dat_in <= ascii_i(bets(4).money, 3);
-- when COLS*21 + COLS*4 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*4 + 117, 14)); fb_a_dat_in <= ascii_i(bets(4).money, 2);
-- when COLS*21 + COLS*4 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*4 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*4 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*4 + 119, 14)); fb_a_dat_in <= ascii_i(bets(4).money, 1);
-- when COLS*21 + COLS*4 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*4 + 120, 14)); fb_a_dat_in <= ascii_i(bets(4).money, 0);
-- when COLS*21 + COLS*4 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*4 + 122, 14));
-- case bets(4).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*4 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*4 + 123, 14));
-- case bets(4).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*4 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*4 + 124, 14));
-- case bets(4).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*4 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*4 + 125, 14));
-- case bets(4).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*4 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*4 + 126, 14));
-- case bets(4).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*4 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*4 + 127, 14));
-- case bets(4).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*4 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*4 + 128, 14));
-- case bets(4).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*4 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*4 + 129, 14));
-- case bets(4).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*4 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*4 + 131, 14)); fb_a_dat_in <= ascii_i(bets(4).number, 1);
-- when COLS*21 + COLS*4 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*4 + 132, 14)); fb_a_dat_in <= ascii_i(bets(4).number, 0);
-- when COLS*21 + COLS*5 + 0 => if bets_index <= 5 then fb_index := COLS*21 + COLS*6 - 1; end if;-- skip this row
-- when COLS*21 + COLS*5 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*5 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*5 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*5 + 113, 14)); fb_a_dat_in <= ascii_i(bets(5).money, 5);
-- when COLS*21 + COLS*5 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*5 + 115, 14)); fb_a_dat_in <= ascii_i(bets(5).money, 4);
-- when COLS*21 + COLS*5 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*5 + 116, 14)); fb_a_dat_in <= ascii_i(bets(5).money, 3);
-- when COLS*21 + COLS*5 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*5 + 117, 14)); fb_a_dat_in <= ascii_i(bets(5).money, 2);
-- when COLS*21 + COLS*5 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*5 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*5 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*5 + 119, 14)); fb_a_dat_in <= ascii_i(bets(5).money, 1);
-- when COLS*21 + COLS*5 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*5 + 120, 14)); fb_a_dat_in <= ascii_i(bets(5).money, 0);
-- when COLS*21 + COLS*5 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*5 + 122, 14));
-- case bets(5).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*5 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*5 + 123, 14));
-- case bets(5).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*5 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*5 + 124, 14));
-- case bets(5).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*5 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*5 + 125, 14));
-- case bets(5).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*5 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*5 + 126, 14));
-- case bets(5).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*5 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*5 + 127, 14));
-- case bets(5).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*5 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*5 + 128, 14));
-- case bets(5).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*5 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*5 + 129, 14));
-- case bets(5).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*5 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*5 + 131, 14)); fb_a_dat_in <= ascii_i(bets(5).number, 1);
-- when COLS*21 + COLS*5 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*5 + 132, 14)); fb_a_dat_in <= ascii_i(bets(5).number, 0);
-- when COLS*21 + COLS*6 + 0 => if bets_index <= 6 then fb_index := COLS*21 + COLS*7 - 1; end if;-- skip this row
-- when COLS*21 + COLS*6 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*6 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*6 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*6 + 113, 14)); fb_a_dat_in <= ascii_i(bets(6).money, 5);
-- when COLS*21 + COLS*6 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*6 + 115, 14)); fb_a_dat_in <= ascii_i(bets(6).money, 4);
-- when COLS*21 + COLS*6 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*6 + 116, 14)); fb_a_dat_in <= ascii_i(bets(6).money, 3);
-- when COLS*21 + COLS*6 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*6 + 117, 14)); fb_a_dat_in <= ascii_i(bets(6).money, 2);
-- when COLS*21 + COLS*6 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*6 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*6 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*6 + 119, 14)); fb_a_dat_in <= ascii_i(bets(6).money, 1);
-- when COLS*21 + COLS*6 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*6 + 120, 14)); fb_a_dat_in <= ascii_i(bets(6).money, 0);
-- when COLS*21 + COLS*6 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*6 + 122, 14));
-- case bets(6).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*6 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*6 + 123, 14));
-- case bets(6).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*6 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*6 + 124, 14));
-- case bets(6).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*6 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*6 + 125, 14));
-- case bets(6).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*6 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*6 + 126, 14));
-- case bets(6).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*6 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*6 + 127, 14));
-- case bets(6).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*6 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*6 + 128, 14));
-- case bets(6).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*6 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*6 + 129, 14));
-- case bets(6).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*6 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*6 + 131, 14)); fb_a_dat_in <= ascii_i(bets(6).number, 1);
-- when COLS*21 + COLS*6 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*6 + 132, 14)); fb_a_dat_in <= ascii_i(bets(6).number, 0);
-- when COLS*21 + COLS*7 + 0 => if bets_index <= 7 then fb_index := COLS*21 + COLS*8 - 1; end if;-- skip this row
-- when COLS*21 + COLS*7 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*7 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*7 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*7 + 113, 14)); fb_a_dat_in <= ascii_i(bets(7).money, 5);
-- when COLS*21 + COLS*7 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*7 + 115, 14)); fb_a_dat_in <= ascii_i(bets(7).money, 4);
-- when COLS*21 + COLS*7 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*7 + 116, 14)); fb_a_dat_in <= ascii_i(bets(7).money, 3);
-- when COLS*21 + COLS*7 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*7 + 117, 14)); fb_a_dat_in <= ascii_i(bets(7).money, 2);
-- when COLS*21 + COLS*7 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*7 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*7 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*7 + 119, 14)); fb_a_dat_in <= ascii_i(bets(7).money, 1);
-- when COLS*21 + COLS*7 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*7 + 120, 14)); fb_a_dat_in <= ascii_i(bets(7).money, 0);
-- when COLS*21 + COLS*7 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*7 + 122, 14));
-- case bets(7).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*7 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*7 + 123, 14));
-- case bets(7).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*7 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*7 + 124, 14));
-- case bets(7).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*7 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*7 + 125, 14));
-- case bets(7).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*7 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*7 + 126, 14));
-- case bets(7).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*7 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*7 + 127, 14));
-- case bets(7).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*7 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*7 + 128, 14));
-- case bets(7).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*7 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*7 + 129, 14));
-- case bets(7).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*7 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*7 + 131, 14)); fb_a_dat_in <= ascii_i(bets(7).number, 1);
-- when COLS*21 + COLS*7 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*7 + 132, 14)); fb_a_dat_in <= ascii_i(bets(7).number, 0);
-- when COLS*21 + COLS*8 + 0 => if bets_index <= 8 then fb_index := COLS*21 + COLS*9 - 1; end if;-- skip this row
-- when COLS*21 + COLS*8 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*8 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*8 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*8 + 113, 14)); fb_a_dat_in <= ascii_i(bets(8).money, 5);
-- when COLS*21 + COLS*8 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*8 + 115, 14)); fb_a_dat_in <= ascii_i(bets(8).money, 4);
-- when COLS*21 + COLS*8 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*8 + 116, 14)); fb_a_dat_in <= ascii_i(bets(8).money, 3);
-- when COLS*21 + COLS*8 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*8 + 117, 14)); fb_a_dat_in <= ascii_i(bets(8).money, 2);
-- when COLS*21 + COLS*8 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*8 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*8 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*8 + 119, 14)); fb_a_dat_in <= ascii_i(bets(8).money, 1);
-- when COLS*21 + COLS*8 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*8 + 120, 14)); fb_a_dat_in <= ascii_i(bets(8).money, 0);
-- when COLS*21 + COLS*8 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*8 + 122, 14));
-- case bets(8).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*8 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*8 + 123, 14));
-- case bets(8).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*8 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*8 + 124, 14));
-- case bets(8).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*8 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*8 + 125, 14));
-- case bets(8).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*8 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*8 + 126, 14));
-- case bets(8).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*8 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*8 + 127, 14));
-- case bets(8).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*8 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*8 + 128, 14));
-- case bets(8).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*8 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*8 + 129, 14));
-- case bets(8).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*8 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*8 + 131, 14)); fb_a_dat_in <= ascii_i(bets(8).number, 1);
-- when COLS*21 + COLS*8 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*8 + 132, 14)); fb_a_dat_in <= ascii_i(bets(8).number, 0);
-- when COLS*21 + COLS*9 + 0 => if bets_index <= 9 then fb_index := COLS*21 + COLS*10 - 1; end if;-- skip this row
-- when COLS*21 + COLS*9 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*9 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*9 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*9 + 113, 14)); fb_a_dat_in <= ascii_i(bets(9).money, 5);
-- when COLS*21 + COLS*9 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*9 + 115, 14)); fb_a_dat_in <= ascii_i(bets(9).money, 4);
-- when COLS*21 + COLS*9 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*9 + 116, 14)); fb_a_dat_in <= ascii_i(bets(9).money, 3);
-- when COLS*21 + COLS*9 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*9 + 117, 14)); fb_a_dat_in <= ascii_i(bets(9).money, 2);
-- when COLS*21 + COLS*9 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*9 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*9 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*9 + 119, 14)); fb_a_dat_in <= ascii_i(bets(9).money, 1);
-- when COLS*21 + COLS*9 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*9 + 120, 14)); fb_a_dat_in <= ascii_i(bets(9).money, 0);
-- when COLS*21 + COLS*9 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*9 + 122, 14));
-- case bets(9).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*9 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*9 + 123, 14));
-- case bets(9).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*9 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*9 + 124, 14));
-- case bets(9).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*9 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*9 + 125, 14));
-- case bets(9).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*9 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*9 + 126, 14));
-- case bets(9).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*9 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*9 + 127, 14));
-- case bets(9).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*9 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*9 + 128, 14));
-- case bets(9).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*9 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*9 + 129, 14));
-- case bets(9).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*9 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*9 + 131, 14)); fb_a_dat_in <= ascii_i(bets(9).number, 1);
-- when COLS*21 + COLS*9 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*9 + 132, 14)); fb_a_dat_in <= ascii_i(bets(9).number, 0);
-- when COLS*21 + COLS*10 + 0 => if bets_index <= 10 then fb_index := COLS*21 + COLS*11 - 1; end if;-- skip this row
-- when COLS*21 + COLS*10 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*10 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*10 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*10 + 113, 14)); fb_a_dat_in <= ascii_i(bets(10).money, 5);
-- when COLS*21 + COLS*10 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*10 + 115, 14)); fb_a_dat_in <= ascii_i(bets(10).money, 4);
-- when COLS*21 + COLS*10 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*10 + 116, 14)); fb_a_dat_in <= ascii_i(bets(10).money, 3);
-- when COLS*21 + COLS*10 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*10 + 117, 14)); fb_a_dat_in <= ascii_i(bets(10).money, 2);
-- when COLS*21 + COLS*10 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*10 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*10 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*10 + 119, 14)); fb_a_dat_in <= ascii_i(bets(10).money, 1);
-- when COLS*21 + COLS*10 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*10 + 120, 14)); fb_a_dat_in <= ascii_i(bets(10).money, 0);
-- when COLS*21 + COLS*10 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*10 + 122, 14));
-- case bets(10).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*10 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*10 + 123, 14));
-- case bets(10).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*10 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*10 + 124, 14));
-- case bets(10).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*10 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*10 + 125, 14));
-- case bets(10).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*10 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*10 + 126, 14));
-- case bets(10).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*10 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*10 + 127, 14));
-- case bets(10).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*10 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*10 + 128, 14));
-- case bets(10).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*10 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*10 + 129, 14));
-- case bets(10).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*10 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*10 + 131, 14)); fb_a_dat_in <= ascii_i(bets(10).number, 1);
-- when COLS*21 + COLS*10 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*10 + 132, 14)); fb_a_dat_in <= ascii_i(bets(10).number, 0);
-- when COLS*21 + COLS*11 + 0 => if bets_index <= 11 then fb_index := COLS*21 + COLS*12 - 1; end if;-- skip this row
-- when COLS*21 + COLS*11 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*11 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*11 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*11 + 113, 14)); fb_a_dat_in <= ascii_i(bets(11).money, 5);
-- when COLS*21 + COLS*11 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*11 + 115, 14)); fb_a_dat_in <= ascii_i(bets(11).money, 4);
-- when COLS*21 + COLS*11 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*11 + 116, 14)); fb_a_dat_in <= ascii_i(bets(11).money, 3);
-- when COLS*21 + COLS*11 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*11 + 117, 14)); fb_a_dat_in <= ascii_i(bets(11).money, 2);
-- when COLS*21 + COLS*11 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*11 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*11 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*11 + 119, 14)); fb_a_dat_in <= ascii_i(bets(11).money, 1);
-- when COLS*21 + COLS*11 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*11 + 120, 14)); fb_a_dat_in <= ascii_i(bets(11).money, 0);
-- when COLS*21 + COLS*11 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*11 + 122, 14));
-- case bets(11).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*11 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*11 + 123, 14));
-- case bets(11).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*11 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*11 + 124, 14));
-- case bets(11).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*11 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*11 + 125, 14));
-- case bets(11).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*11 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*11 + 126, 14));
-- case bets(11).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*11 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*11 + 127, 14));
-- case bets(11).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*11 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*11 + 128, 14));
-- case bets(11).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*11 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*11 + 129, 14));
-- case bets(11).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*11 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*11 + 131, 14)); fb_a_dat_in <= ascii_i(bets(11).number, 1);
-- when COLS*21 + COLS*11 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*11 + 132, 14)); fb_a_dat_in <= ascii_i(bets(11).number, 0);
-- when COLS*21 + COLS*12 + 0 => if bets_index <= 12 then fb_index := COLS*21 + COLS*13 - 1; end if;-- skip this row
-- when COLS*21 + COLS*12 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*12 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*12 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*12 + 113, 14)); fb_a_dat_in <= ascii_i(bets(12).money, 5);
-- when COLS*21 + COLS*12 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*12 + 115, 14)); fb_a_dat_in <= ascii_i(bets(12).money, 4);
-- when COLS*21 + COLS*12 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*12 + 116, 14)); fb_a_dat_in <= ascii_i(bets(12).money, 3);
-- when COLS*21 + COLS*12 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*12 + 117, 14)); fb_a_dat_in <= ascii_i(bets(12).money, 2);
-- when COLS*21 + COLS*12 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*12 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*12 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*12 + 119, 14)); fb_a_dat_in <= ascii_i(bets(12).money, 1);
-- when COLS*21 + COLS*12 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*12 + 120, 14)); fb_a_dat_in <= ascii_i(bets(12).money, 0);
-- when COLS*21 + COLS*12 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*12 + 122, 14));
-- case bets(12).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*12 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*12 + 123, 14));
-- case bets(12).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*12 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*12 + 124, 14));
-- case bets(12).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*12 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*12 + 125, 14));
-- case bets(12).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*12 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*12 + 126, 14));
-- case bets(12).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*12 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*12 + 127, 14));
-- case bets(12).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*12 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*12 + 128, 14));
-- case bets(12).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*12 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*12 + 129, 14));
-- case bets(12).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*12 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*12 + 131, 14)); fb_a_dat_in <= ascii_i(bets(12).number, 1);
-- when COLS*21 + COLS*12 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*12 + 132, 14)); fb_a_dat_in <= ascii_i(bets(12).number, 0);
-- when COLS*21 + COLS*13 + 0 => if bets_index <= 13 then fb_index := COLS*21 + COLS*14 - 1; end if;-- skip this row
-- when COLS*21 + COLS*13 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*13 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*13 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*13 + 113, 14)); fb_a_dat_in <= ascii_i(bets(13).money, 5);
-- when COLS*21 + COLS*13 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*13 + 115, 14)); fb_a_dat_in <= ascii_i(bets(13).money, 4);
-- when COLS*21 + COLS*13 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*13 + 116, 14)); fb_a_dat_in <= ascii_i(bets(13).money, 3);
-- when COLS*21 + COLS*13 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*13 + 117, 14)); fb_a_dat_in <= ascii_i(bets(13).money, 2);
-- when COLS*21 + COLS*13 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*13 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*13 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*13 + 119, 14)); fb_a_dat_in <= ascii_i(bets(13).money, 1);
-- when COLS*21 + COLS*13 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*13 + 120, 14)); fb_a_dat_in <= ascii_i(bets(13).money, 0);
-- when COLS*21 + COLS*13 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*13 + 122, 14));
-- case bets(13).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*13 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*13 + 123, 14));
-- case bets(13).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*13 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*13 + 124, 14));
-- case bets(13).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*13 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*13 + 125, 14));
-- case bets(13).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*13 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*13 + 126, 14));
-- case bets(13).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*13 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*13 + 127, 14));
-- case bets(13).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*13 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*13 + 128, 14));
-- case bets(13).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*13 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*13 + 129, 14));
-- case bets(13).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*13 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*13 + 131, 14)); fb_a_dat_in <= ascii_i(bets(13).number, 1);
-- when COLS*21 + COLS*13 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*13 + 132, 14)); fb_a_dat_in <= ascii_i(bets(13).number, 0);
-- when COLS*21 + COLS*14 + 0 => if bets_index <= 14 then fb_index := COLS*21 + COLS*15 - 1; end if;-- skip this row
-- when COLS*21 + COLS*14 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*14 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*14 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*14 + 113, 14)); fb_a_dat_in <= ascii_i(bets(14).money, 5);
-- when COLS*21 + COLS*14 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*14 + 115, 14)); fb_a_dat_in <= ascii_i(bets(14).money, 4);
-- when COLS*21 + COLS*14 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*14 + 116, 14)); fb_a_dat_in <= ascii_i(bets(14).money, 3);
-- when COLS*21 + COLS*14 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*14 + 117, 14)); fb_a_dat_in <= ascii_i(bets(14).money, 2);
-- when COLS*21 + COLS*14 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*14 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*14 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*14 + 119, 14)); fb_a_dat_in <= ascii_i(bets(14).money, 1);
-- when COLS*21 + COLS*14 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*14 + 120, 14)); fb_a_dat_in <= ascii_i(bets(14).money, 0);
-- when COLS*21 + COLS*14 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*14 + 122, 14));
-- case bets(14).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*14 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*14 + 123, 14));
-- case bets(14).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*14 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*14 + 124, 14));
-- case bets(14).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*14 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*14 + 125, 14));
-- case bets(14).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*14 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*14 + 126, 14));
-- case bets(14).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*14 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*14 + 127, 14));
-- case bets(14).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*14 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*14 + 128, 14));
-- case bets(14).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*14 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*14 + 129, 14));
-- case bets(14).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*14 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*14 + 131, 14)); fb_a_dat_in <= ascii_i(bets(14).number, 1);
-- when COLS*21 + COLS*14 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*14 + 132, 14)); fb_a_dat_in <= ascii_i(bets(14).number, 0);
-- when COLS*21 + COLS*15 + 0 => if bets_index <= 15 then fb_index := COLS*21 + COLS*16 - 1; end if;-- skip this row
-- when COLS*21 + COLS*15 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*15 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*15 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*15 + 113, 14)); fb_a_dat_in <= ascii_i(bets(15).money, 5);
-- when COLS*21 + COLS*15 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*15 + 115, 14)); fb_a_dat_in <= ascii_i(bets(15).money, 4);
-- when COLS*21 + COLS*15 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*15 + 116, 14)); fb_a_dat_in <= ascii_i(bets(15).money, 3);
-- when COLS*21 + COLS*15 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*15 + 117, 14)); fb_a_dat_in <= ascii_i(bets(15).money, 2);
-- when COLS*21 + COLS*15 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*15 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*15 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*15 + 119, 14)); fb_a_dat_in <= ascii_i(bets(15).money, 1);
-- when COLS*21 + COLS*15 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*15 + 120, 14)); fb_a_dat_in <= ascii_i(bets(15).money, 0);
-- when COLS*21 + COLS*15 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*15 + 122, 14));
-- case bets(15).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*15 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*15 + 123, 14));
-- case bets(15).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*15 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*15 + 124, 14));
-- case bets(15).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*15 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*15 + 125, 14));
-- case bets(15).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*15 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*15 + 126, 14));
-- case bets(15).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*15 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*15 + 127, 14));
-- case bets(15).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*15 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*15 + 128, 14));
-- case bets(15).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*15 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*15 + 129, 14));
-- case bets(15).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*15 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*15 + 131, 14)); fb_a_dat_in <= ascii_i(bets(15).number, 1);
-- when COLS*21 + COLS*15 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*15 + 132, 14)); fb_a_dat_in <= ascii_i(bets(15).number, 0);
-- when COLS*21 + COLS*16 + 0 => if bets_index <= 16 then fb_index := COLS*21 + COLS*17 - 1; end if;-- skip this row
-- when COLS*21 + COLS*16 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*16 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*16 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*16 + 113, 14)); fb_a_dat_in <= ascii_i(bets(16).money, 5);
-- when COLS*21 + COLS*16 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*16 + 115, 14)); fb_a_dat_in <= ascii_i(bets(16).money, 4);
-- when COLS*21 + COLS*16 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*16 + 116, 14)); fb_a_dat_in <= ascii_i(bets(16).money, 3);
-- when COLS*21 + COLS*16 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*16 + 117, 14)); fb_a_dat_in <= ascii_i(bets(16).money, 2);
-- when COLS*21 + COLS*16 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*16 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*16 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*16 + 119, 14)); fb_a_dat_in <= ascii_i(bets(16).money, 1);
-- when COLS*21 + COLS*16 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*16 + 120, 14)); fb_a_dat_in <= ascii_i(bets(16).money, 0);
-- when COLS*21 + COLS*16 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*16 + 122, 14));
-- case bets(16).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*16 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*16 + 123, 14));
-- case bets(16).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*16 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*16 + 124, 14));
-- case bets(16).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*16 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*16 + 125, 14));
-- case bets(16).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*16 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*16 + 126, 14));
-- case bets(16).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*16 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*16 + 127, 14));
-- case bets(16).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*16 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*16 + 128, 14));
-- case bets(16).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*16 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*16 + 129, 14));
-- case bets(16).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*16 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*16 + 131, 14)); fb_a_dat_in <= ascii_i(bets(16).number, 1);
-- when COLS*21 + COLS*16 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*16 + 132, 14)); fb_a_dat_in <= ascii_i(bets(16).number, 0);
-- when COLS*21 + COLS*17 + 0 => if bets_index <= 17 then fb_index := COLS*21 + COLS*18 - 1; end if;-- skip this row
-- when COLS*21 + COLS*17 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*17 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*17 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*17 + 113, 14)); fb_a_dat_in <= ascii_i(bets(17).money, 5);
-- when COLS*21 + COLS*17 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*17 + 115, 14)); fb_a_dat_in <= ascii_i(bets(17).money, 4);
-- when COLS*21 + COLS*17 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*17 + 116, 14)); fb_a_dat_in <= ascii_i(bets(17).money, 3);
-- when COLS*21 + COLS*17 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*17 + 117, 14)); fb_a_dat_in <= ascii_i(bets(17).money, 2);
-- when COLS*21 + COLS*17 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*17 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*17 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*17 + 119, 14)); fb_a_dat_in <= ascii_i(bets(17).money, 1);
-- when COLS*21 + COLS*17 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*17 + 120, 14)); fb_a_dat_in <= ascii_i(bets(17).money, 0);
-- when COLS*21 + COLS*17 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*17 + 122, 14));
-- case bets(17).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*17 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*17 + 123, 14));
-- case bets(17).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*17 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*17 + 124, 14));
-- case bets(17).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*17 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*17 + 125, 14));
-- case bets(17).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*17 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*17 + 126, 14));
-- case bets(17).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*17 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*17 + 127, 14));
-- case bets(17).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*17 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*17 + 128, 14));
-- case bets(17).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*17 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*17 + 129, 14));
-- case bets(17).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*17 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*17 + 131, 14)); fb_a_dat_in <= ascii_i(bets(17).number, 1);
-- when COLS*21 + COLS*17 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*17 + 132, 14)); fb_a_dat_in <= ascii_i(bets(17).number, 0);
-- when COLS*21 + COLS*18 + 0 => if bets_index <= 18 then fb_index := COLS*21 + COLS*19 - 1; end if;-- skip this row
-- when COLS*21 + COLS*18 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*18 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*18 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*18 + 113, 14)); fb_a_dat_in <= ascii_i(bets(18).money, 5);
-- when COLS*21 + COLS*18 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*18 + 115, 14)); fb_a_dat_in <= ascii_i(bets(18).money, 4);
-- when COLS*21 + COLS*18 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*18 + 116, 14)); fb_a_dat_in <= ascii_i(bets(18).money, 3);
-- when COLS*21 + COLS*18 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*18 + 117, 14)); fb_a_dat_in <= ascii_i(bets(18).money, 2);
-- when COLS*21 + COLS*18 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*18 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*18 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*18 + 119, 14)); fb_a_dat_in <= ascii_i(bets(18).money, 1);
-- when COLS*21 + COLS*18 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*18 + 120, 14)); fb_a_dat_in <= ascii_i(bets(18).money, 0);
-- when COLS*21 + COLS*18 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*18 + 122, 14));
-- case bets(18).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*18 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*18 + 123, 14));
-- case bets(18).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*18 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*18 + 124, 14));
-- case bets(18).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*18 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*18 + 125, 14));
-- case bets(18).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*18 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*18 + 126, 14));
-- case bets(18).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*18 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*18 + 127, 14));
-- case bets(18).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*18 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*18 + 128, 14));
-- case bets(18).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*18 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*18 + 129, 14));
-- case bets(18).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*18 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*18 + 131, 14)); fb_a_dat_in <= ascii_i(bets(18).number, 1);
-- when COLS*21 + COLS*18 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*18 + 132, 14)); fb_a_dat_in <= ascii_i(bets(18).number, 0);
-- when COLS*21 + COLS*19 + 0 => if bets_index <= 19 then fb_index := COLS*21 + COLS*20 - 1; end if;-- skip this row
-- when COLS*21 + COLS*19 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*19 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*19 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*19 + 113, 14)); fb_a_dat_in <= ascii_i(bets(19).money, 5);
-- when COLS*21 + COLS*19 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*19 + 115, 14)); fb_a_dat_in <= ascii_i(bets(19).money, 4);
-- when COLS*21 + COLS*19 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*19 + 116, 14)); fb_a_dat_in <= ascii_i(bets(19).money, 3);
-- when COLS*21 + COLS*19 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*19 + 117, 14)); fb_a_dat_in <= ascii_i(bets(19).money, 2);
-- when COLS*21 + COLS*19 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*19 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*19 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*19 + 119, 14)); fb_a_dat_in <= ascii_i(bets(19).money, 1);
-- when COLS*21 + COLS*19 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*19 + 120, 14)); fb_a_dat_in <= ascii_i(bets(19).money, 0);
-- when COLS*21 + COLS*19 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*19 + 122, 14));
-- case bets(19).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*19 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*19 + 123, 14));
-- case bets(19).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*19 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*19 + 124, 14));
-- case bets(19).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*19 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*19 + 125, 14));
-- case bets(19).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*19 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*19 + 126, 14));
-- case bets(19).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*19 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*19 + 127, 14));
-- case bets(19).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*19 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*19 + 128, 14));
-- case bets(19).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*19 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*19 + 129, 14));
-- case bets(19).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*19 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*19 + 131, 14)); fb_a_dat_in <= ascii_i(bets(19).number, 1);
-- when COLS*21 + COLS*19 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*19 + 132, 14)); fb_a_dat_in <= ascii_i(bets(19).number, 0);
-- when COLS*21 + COLS*20 + 0 => if bets_index <= 20 then fb_index := COLS*21 + COLS*21 - 1; end if;-- skip this row
-- when COLS*21 + COLS*20 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*20 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*20 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*20 + 113, 14)); fb_a_dat_in <= ascii_i(bets(20).money, 5);
-- when COLS*21 + COLS*20 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*20 + 115, 14)); fb_a_dat_in <= ascii_i(bets(20).money, 4);
-- when COLS*21 + COLS*20 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*20 + 116, 14)); fb_a_dat_in <= ascii_i(bets(20).money, 3);
-- when COLS*21 + COLS*20 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*20 + 117, 14)); fb_a_dat_in <= ascii_i(bets(20).money, 2);
-- when COLS*21 + COLS*20 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*20 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*20 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*20 + 119, 14)); fb_a_dat_in <= ascii_i(bets(20).money, 1);
-- when COLS*21 + COLS*20 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*20 + 120, 14)); fb_a_dat_in <= ascii_i(bets(20).money, 0);
-- when COLS*21 + COLS*20 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*20 + 122, 14));
-- case bets(20).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*20 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*20 + 123, 14));
-- case bets(20).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*20 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*20 + 124, 14));
-- case bets(20).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*20 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*20 + 125, 14));
-- case bets(20).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*20 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*20 + 126, 14));
-- case bets(20).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*20 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*20 + 127, 14));
-- case bets(20).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*20 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*20 + 128, 14));
-- case bets(20).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*20 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*20 + 129, 14));
-- case bets(20).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*20 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*20 + 131, 14)); fb_a_dat_in <= ascii_i(bets(20).number, 1);
-- when COLS*21 + COLS*20 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*20 + 132, 14)); fb_a_dat_in <= ascii_i(bets(20).number, 0);
-- when COLS*21 + COLS*21 + 0 => if bets_index <= 21 then fb_index := COLS*21 + COLS*22 - 1; end if;-- skip this row
-- when COLS*21 + COLS*21 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*21 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*21 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*21 + 113, 14)); fb_a_dat_in <= ascii_i(bets(21).money, 5);
-- when COLS*21 + COLS*21 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*21 + 115, 14)); fb_a_dat_in <= ascii_i(bets(21).money, 4);
-- when COLS*21 + COLS*21 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*21 + 116, 14)); fb_a_dat_in <= ascii_i(bets(21).money, 3);
-- when COLS*21 + COLS*21 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*21 + 117, 14)); fb_a_dat_in <= ascii_i(bets(21).money, 2);
-- when COLS*21 + COLS*21 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*21 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*21 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*21 + 119, 14)); fb_a_dat_in <= ascii_i(bets(21).money, 1);
-- when COLS*21 + COLS*21 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*21 + 120, 14)); fb_a_dat_in <= ascii_i(bets(21).money, 0);
-- when COLS*21 + COLS*21 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*21 + 122, 14));
-- case bets(21).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*21 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*21 + 123, 14));
-- case bets(21).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*21 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*21 + 124, 14));
-- case bets(21).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*21 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*21 + 125, 14));
-- case bets(21).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*21 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*21 + 126, 14));
-- case bets(21).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*21 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*21 + 127, 14));
-- case bets(21).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*21 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*21 + 128, 14));
-- case bets(21).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*21 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*21 + 129, 14));
-- case bets(21).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*21 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*21 + 131, 14)); fb_a_dat_in <= ascii_i(bets(21).number, 1);
-- when COLS*21 + COLS*21 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*21 + 132, 14)); fb_a_dat_in <= ascii_i(bets(21).number, 0);
-- when COLS*21 + COLS*22 + 0 => if bets_index <= 22 then fb_index := COLS*21 + COLS*23 - 1; end if;-- skip this row
-- when COLS*21 + COLS*22 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*22 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*22 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*22 + 113, 14)); fb_a_dat_in <= ascii_i(bets(22).money, 5);
-- when COLS*21 + COLS*22 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*22 + 115, 14)); fb_a_dat_in <= ascii_i(bets(22).money, 4);
-- when COLS*21 + COLS*22 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*22 + 116, 14)); fb_a_dat_in <= ascii_i(bets(22).money, 3);
-- when COLS*21 + COLS*22 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*22 + 117, 14)); fb_a_dat_in <= ascii_i(bets(22).money, 2);
-- when COLS*21 + COLS*22 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*22 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*22 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*22 + 119, 14)); fb_a_dat_in <= ascii_i(bets(22).money, 1);
-- when COLS*21 + COLS*22 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*22 + 120, 14)); fb_a_dat_in <= ascii_i(bets(22).money, 0);
-- when COLS*21 + COLS*22 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*22 + 122, 14));
-- case bets(22).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*22 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*22 + 123, 14));
-- case bets(22).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*22 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*22 + 124, 14));
-- case bets(22).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*22 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*22 + 125, 14));
-- case bets(22).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*22 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*22 + 126, 14));
-- case bets(22).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*22 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*22 + 127, 14));
-- case bets(22).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*22 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*22 + 128, 14));
-- case bets(22).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*22 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*22 + 129, 14));
-- case bets(22).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*22 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*22 + 131, 14)); fb_a_dat_in <= ascii_i(bets(22).number, 1);
-- when COLS*21 + COLS*22 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*22 + 132, 14)); fb_a_dat_in <= ascii_i(bets(22).number, 0);
-- when COLS*21 + COLS*23 + 0 => if bets_index <= 23 then fb_index := COLS*21 + COLS*24 - 1; end if;-- skip this row
-- when COLS*21 + COLS*23 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*23 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*23 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*23 + 113, 14)); fb_a_dat_in <= ascii_i(bets(23).money, 5);
-- when COLS*21 + COLS*23 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*23 + 115, 14)); fb_a_dat_in <= ascii_i(bets(23).money, 4);
-- when COLS*21 + COLS*23 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*23 + 116, 14)); fb_a_dat_in <= ascii_i(bets(23).money, 3);
-- when COLS*21 + COLS*23 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*23 + 117, 14)); fb_a_dat_in <= ascii_i(bets(23).money, 2);
-- when COLS*21 + COLS*23 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*23 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*23 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*23 + 119, 14)); fb_a_dat_in <= ascii_i(bets(23).money, 1);
-- when COLS*21 + COLS*23 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*23 + 120, 14)); fb_a_dat_in <= ascii_i(bets(23).money, 0);
-- when COLS*21 + COLS*23 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*23 + 122, 14));
-- case bets(23).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*23 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*23 + 123, 14));
-- case bets(23).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*23 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*23 + 124, 14));
-- case bets(23).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*23 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*23 + 125, 14));
-- case bets(23).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*23 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*23 + 126, 14));
-- case bets(23).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*23 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*23 + 127, 14));
-- case bets(23).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*23 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*23 + 128, 14));
-- case bets(23).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*23 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*23 + 129, 14));
-- case bets(23).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*23 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*23 + 131, 14)); fb_a_dat_in <= ascii_i(bets(23).number, 1);
-- when COLS*21 + COLS*23 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*23 + 132, 14)); fb_a_dat_in <= ascii_i(bets(23).number, 0);
-- when COLS*21 + COLS*24 + 0 => if bets_index <= 24 then fb_index := COLS*21 + COLS*25 - 1; end if;-- skip this row
-- when COLS*21 + COLS*24 + 1 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*24 + 111, 14)); fb_a_dat_in <= x"24"; -- $
-- when COLS*21 + COLS*24 + 2 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*24 + 113, 14)); fb_a_dat_in <= ascii_i(bets(24).money, 5);
-- when COLS*21 + COLS*24 + 3 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*24 + 115, 14)); fb_a_dat_in <= ascii_i(bets(24).money, 4);
-- when COLS*21 + COLS*24 + 4 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*24 + 116, 14)); fb_a_dat_in <= ascii_i(bets(24).money, 3);
-- when COLS*21 + COLS*24 + 5 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*24 + 117, 14)); fb_a_dat_in <= ascii_i(bets(24).money, 2);
-- when COLS*21 + COLS*24 + 6 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*24 + 118, 14)); fb_a_dat_in <= x"2e"; -- .
-- when COLS*21 + COLS*24 + 7 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*24 + 119, 14)); fb_a_dat_in <= ascii_i(bets(24).money, 1);
-- when COLS*21 + COLS*24 + 8 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*24 + 120, 14)); fb_a_dat_in <= ascii_i(bets(24).money, 0);
-- when COLS*21 + COLS*24 + 9 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*24 + 122, 14));
-- case bets(24).kind is
-- when 1 => fb_a_dat_in <= x"50"; -- P
-- when 2 => fb_a_dat_in <= x"43"; -- C
-- when 3 => fb_a_dat_in <= x"43"; -- C
-- when 4 => fb_a_dat_in <= x"54"; -- T
-- when 5 => fb_a_dat_in <= x"54"; -- T
-- when 6 => fb_a_dat_in <= x"43"; -- C
-- when 7 => fb_a_dat_in <= x"43"; -- C
-- when 8 => fb_a_dat_in <= x"53"; -- S
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*24 + 10 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*24 + 123, 14));
-- case bets(24).kind is
-- when 1 => fb_a_dat_in <= x"6c"; -- l
-- when 2 => fb_a_dat_in <= x"68"; -- h
-- when 3 => fb_a_dat_in <= x"68"; -- h
-- when 4 => fb_a_dat_in <= x"72"; -- r
-- when 5 => fb_a_dat_in <= x"72"; -- r
-- when 6 => fb_a_dat_in <= x"61"; -- a
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"69"; -- i
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*24 + 11 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*24 + 124, 14));
-- case bets(24).kind is
-- when 1 => fb_a_dat_in <= x"61"; -- a
-- when 2 => fb_a_dat_in <= x"65"; -- e
-- when 3 => fb_a_dat_in <= x"65"; -- e
-- when 4 => fb_a_dat_in <= x"61"; -- a
-- when 5 => fb_a_dat_in <= x"61"; -- a
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6c"; -- l
-- when 8 => fb_a_dat_in <= x"6d"; -- m
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*24 + 12 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*24 + 125, 14));
-- case bets(24).kind is
-- when 1 => fb_a_dat_in <= x"69"; -- i
-- when 2 => fb_a_dat_in <= x"76"; -- v
-- when 3 => fb_a_dat_in <= x"76"; -- v
-- when 4 => fb_a_dat_in <= x"6e"; -- n
-- when 5 => fb_a_dat_in <= x"6e"; -- n
-- when 6 => fb_a_dat_in <= x"72"; -- r
-- when 7 => fb_a_dat_in <= x"6f"; -- o
-- when 8 => fb_a_dat_in <= x"70"; -- p
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*24 + 13 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*24 + 126, 14));
-- case bets(24).kind is
-- when 1 => fb_a_dat_in <= x"6e"; -- n
-- when 2 => fb_a_dat_in <= x"61"; -- a
-- when 3 => fb_a_dat_in <= x"61"; -- a
-- when 4 => fb_a_dat_in <= x"73"; -- s
-- when 5 => fb_a_dat_in <= x"73"; -- s
-- when 6 => fb_a_dat_in <= x"65"; -- e
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"6c"; -- l
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*24 + 14 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*24 + 127, 14));
-- case bets(24).kind is
-- when 2 => fb_a_dat_in <= x"6c"; -- l
-- when 3 => fb_a_dat_in <= x"6c"; -- l
-- when 7 => fb_a_dat_in <= x"6e"; -- n
-- when 8 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*24 + 15 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*24 + 128, 14));
-- case bets(24).kind is
-- when 5 => fb_a_dat_in <= x"53"; -- S
-- when 7 => fb_a_dat_in <= x"65"; -- e
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*24 + 16 =>
-- fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*24 + 129, 14));
-- case bets(24).kind is
-- when 2 => fb_a_dat_in <= x"48"; -- H
-- when 3 => fb_a_dat_in <= x"56"; -- V
-- when others => fb_a_dat_in <= x"20"; -- space
-- end case;
-- when COLS*21 + COLS*24 + 17 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*24 + 131, 14)); fb_a_dat_in <= ascii_i(bets(24).number, 1);
-- when COLS*21 + COLS*24 + 18 => fb_a_addr <= std_logic_vector(to_unsigned(COLS*21 + COLS*24 + 132, 14)); fb_a_dat_in <= ascii_i(bets(24).number, 0);
-- -- ============================================================ END OF PYTHON GENERATED VHDL ============================================================
when COLS * 49 => -- line 49 is 2 lines below the last line of the 'image'
fb_a_en <= '0';
fb_a_we <= "0";
msg := pad_string(" Roll", msg'LENGTH);
state_index := state_index + 1; state(state_index) := WRITE;
when COLS * 50 =>
fb_a_en <= '0';
fb_a_we <= "0";
if bets_index = BETS_MAX then
fb_index := COLS * 57 - 1; -- skip over all the other options, out of betspace
else
msg := pad_string(" Place plein bet", msg'LENGTH);
state_index := state_index + 1; state(state_index) := WRITE;
end if;
when COLS * 51 =>
fb_a_en <= '0';
fb_a_we <= "0";
msg := pad_string(" Place horizontal cheval bet", msg'LENGTH);
state_index := state_index + 1; state(state_index) := WRITE;
when COLS * 52 =>
fb_a_en <= '0';
fb_a_we <= "0";
msg := pad_string(" Place vertical cheval bet", msg'LENGTH);
state_index := state_index + 1; state(state_index) := WRITE;
when COLS * 53 =>
fb_a_en <= '0';
fb_a_we <= "0";
msg := pad_string(" Place transversale bet", msg'LENGTH);
state_index := state_index + 1; state(state_index) := WRITE;
when COLS * 54 =>
fb_a_en <= '0';
fb_a_we <= "0";
msg := pad_string(" Place transversale simple bet", msg'LENGTH);
state_index := state_index + 1; state(state_index) := WRITE;
when COLS * 55 =>
fb_a_en <= '0';
fb_a_we <= "0";
msg := pad_string(" Place carre bet", msg'LENGTH);
state_index := state_index + 1; state(state_index) := WRITE;
when COLS * 56 =>
fb_a_en <= '0';
fb_a_we <= "0";
msg := pad_string(" Place colonne bet", msg'LENGTH);
state_index := state_index + 1; state(state_index) := WRITE;
when COLS * 57 =>
fb_a_en <= '0';
fb_a_we <= "0";
msg := pad_string(" Place chance simple bet", msg'LENGTH);
state_index := state_index + 1; state(state_index) := WRITE;
when COLS * 58 =>
if bets_index = BETS_MAX then
input_max := 1; -- only roll option was printed
else
input_max := 9; -- normal
end if;
input := 0;
state_index := state_index + 1; state(state_index) := READ_MENU;
when COLS * 58 + 1 => -- only get here once done read_menu
fb_a_en <= '0';
fb_a_we <= "0";
if input = 0 then -- if roll
state(state_index) := GAME_R_ROLL; -- override return state
else -- if place bet
bets(bets_index).kind := input;
state(state_index) := GAME_R_PLACE_START; -- override return state
end if;
fb_index := COLS * 49; -- start of blanking
state_index := state_index + 1; state(state_index) := BLANK; -- blank from line 49 to last-1 line
when others => -- after writes
fb_a_en <= '0';
fb_a_we <= "0";
end case;
if money < 100 then
state(state_index) := ERROR_STUCK; -- override return state
state_index := state_index + 1; state(state_index) := WRITE; -- put next state on stack
msg_inverted := '1';
msg := pad_string("You are out of money...", msg'LENGTH);
fb_index := 0;
end if;
---------------------------------------------
when GAME_R_PLACE_START =>
case bets(bets_index).kind is
when 1 => -- plein
state(state_index) := GAME_R_PLACE_BET; -- after number, read amount
input_max := 36;
input := 0;
state_index := state_index + 1; state(state_index) := READ; -- Read after the write
fb_index := COLS * 49;
msg := pad_string(" Number? (0 - 36) ", msg'LENGTH);
state_index := state_index + 1; state(state_index) := WRITE;
when 2 to 6 => -- cheval H or V, trans, trans simple or carre
state(state_index) := GAME_R_PLACE_BET; -- after number, read amount
input_max := 36;
input := 0;
state_index := state_index + 1; state(state_index) := READ; -- Read after the write
fb_index := COLS * 49;
msg := pad_string(" First number? (0 - 36) ", msg'LENGTH);
state_index := state_index + 1; state(state_index) := WRITE;
when 7 => -- colonne
state(state_index) := GAME_R_PLACE_BET; -- after input, read amount
input_max := 6;
input := 0;
state_index := state_index + 1; state(state_index) := READ_MENU; -- Read after the write
fb_index := COLS * 49;
msg := pad_string(" R1" & lf & " R2" & lf & " R3" & lf & " 12P" & lf & " 12M" & lf & " 12D" & lf , msg'LENGTH);
state_index := state_index + 1; state(state_index) := WRITE;
when 8 => -- simple
state(state_index) := GAME_R_PLACE_BET; -- after input, read amount
input_max := 6;
input := 0;
state_index := state_index + 1; state(state_index) := READ_MENU; -- Read after the write
fb_index := COLS * 49;
msg := pad_string(" Noir" & lf & " Rouge" & lf & " Pair" & lf & " Impair" & lf & " Manque" & lf & " Passe" & lf , msg'LENGTH);
state_index := state_index + 1; state(state_index) := WRITE;
when others =>
state(state_index) := ERROR; -- ??
end case;
---------------------------------------------
when GAME_R_PLACE_BET =>
state(state_index) := GAME_R_PLACE_SAVE; -- after amount, save & go back to main menu
bets(bets_index).number := input; -- save the input
input := 0; -- reset
if money > 1_000_00 then -- can't bet more then you have
input_max := 1_000_00;
else
input_max := money;
end if;
state_index := state_index + 1; state(state_index) := READ; -- read = state after write
fb_index := COLS * 49; -- position question
msg := pad_string(" Amount? (Max 1 000.00 $) ", msg'LENGTH);
state_index := state_index + 1; state(state_index) := WRITE;
---------------------------------------------
when GAME_R_PLACE_SAVE =>
money := money - input;
bets(bets_index).money := input; -- save input
bets_index := bets_index + 1; -- finalize bet
state(state_index) := GAME_R_0; -- go back to main menu
fb_index := COLS * 49; -- start of blanking
state_index := state_index + 1; state(state_index) := BLANK; -- blank from line 49 to last-1 line
---------------------------------------------
when GAME_R_ROLL =>
fb_index := index_delta(fb_index); -- by default +1 index
case fb_index is -- start with 1 because of the default +1
when 1 => -- do actual rnd number getting
rnd := to_integer(unsigned(rng_out)) mod 37;
bets_index := 0;
when 2 =>
-- todo: compare each bet, and reset them
bets_index := 0;
state(state_index) := GAME_R_0;
state_index := state_index + 1; state(state_index) := COPY; -- Clear the list
when others =>
-- nop
end case;
---------------------------------------------
when READ => -- No cursor, easy numeric input.
if kb_event = '1' then -- kb event, handle that
case kb_acsii is
when "0001000" => -- backspace
input := input / 10;
when "0001101" => -- enter
msg_index := 0;
state_index := state_index - 1; -- pop one of the state stack
when "0110000" => -- 0
input := input * 10;
if input > input_max then
input := input_max;
end if;
when "0110001" => -- 1
input := input * 10 + 1;
if input > input_max then
input := input_max;
end if;
when "0110010" => -- 2
input := input * 10 + 2;
if input > input_max then
input := input_max;
end if;
when "0110011" => -- 3
input := input * 10 + 3;
if input > input_max then
input := input_max;
end if;
when "0110100" => -- 4
input := input * 10 + 4;
if input > input_max then
input := input_max;
end if;
when "0110101" => -- 5
input := input * 10 + 5;
if input > input_max then
input := input_max;
end if;
when "0110110" => -- 6
input := input * 10 + 6;
if input > input_max then
input := input_max;
end if;
when "0110111" => -- 7
input := input * 10 + 7;
if input > input_max then
input := input_max;
end if;
when "0111000" => -- 8
input := input * 10 + 8;
if input > input_max then
input := input_max;
end if;
when "0111001" => -- 9
input := input * 10 + 9;
if input > input_max then
input := input_max;
end if;
when others =>
-- nop
end case;
else -- No kb event, print input (abuses msg_index to get a secondary loop counter. Uses fb_index as actual frame buffer pointer)
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(fb_index + msg_index, 14));
if input_max > 99 then -- money
case msg_index is
when 0 => fb_a_dat_in <= x"24"; -- $
when 1 => fb_a_dat_in <= ascii_i(input, 5);
when 2 => fb_a_dat_in <= ascii_i(input, 4);
when 3 => fb_a_dat_in <= ascii_i(input, 3);
when 4 => fb_a_dat_in <= ascii_i(input, 2);
when 5 => fb_a_dat_in <= x"2e"; -- .
when 6 => fb_a_dat_in <= ascii_i(input, 1);
when 7 => fb_a_dat_in <= ascii_i(input, 0);
when others => -- never gets here.
end case;
msg_index := index_delta(msg_index, modulo => 8);
else -- any other number (always < 99)
case msg_index is
when 0 => fb_a_dat_in <= ascii_i(input, 1);
when 1 => fb_a_dat_in <= ascii_i(input, 0);
when others => -- never gets here.
end case;
msg_index := index_delta(msg_index, modulo => 2);
end if;
end if;
---------------------------------------------
when READ_MENU =>
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(input * COLS + (49 * COLS + 1), 14)); -- line (49 + menu) + 1
fb_a_dat_in <= x"10"; -- '>' indicator arrow
if kb_event = '1' then
case '0' & kb_acsii is
-- vhdl syntax is strange. ()'s are required to make it show up as a boolean?
when (x"01") | (x"38") => -- up or 8
fb_a_dat_in <= x"20"; -- space
input := index_delta(input, delta => -1, modulo => input_max);
when (x"02") | (x"32") => -- down or 2
fb_a_dat_in <= x"20"; -- space
input := index_delta(input, modulo => input_max);
when x"0d" => -- enter
-- fb_index := COLS * 49; -- start of blanking
-- state(state_index) := BLANK; -- blank from line 49 to last-1 line
state_index := state_index - 1;
when others =>
-- nop
end case;
end if;
---------------------------------------------
when ERROR_STUCK =>
--
when ERROR =>
state(state_index) := ERROR_STUCK; -- override return state
state_index := state_index + 1; state(state_index) := WRITE; -- put next state on stack
msg_inverted := '1';
msg := pad_string("Internal error occured.", msg'LENGTH);
fb_index := 0;
---------------------------------------------
when WRITE =>
fb_a_en <= '1';
fb_a_we <= "1";
case character'pos(msg(msg_index + 1)) is
when 10 | 13 =>
if fb_index mod COLS = COLS - 1 then
msg_index := index_delta(msg_index, modulo => msg'LENGTH);
end if;
fb_a_dat_in <= msg_inverted & "0100000"; -- space
when others =>
fb_a_dat_in <= msg_inverted & std_logic_vector(to_unsigned(character'pos(msg(msg_index + 1)), 7));
msg_index := index_delta(msg_index, modulo => msg'LENGTH);
end case;
fb_a_addr <= std_logic_vector(to_unsigned(fb_index, 14));
fb_index := index_delta(fb_index);
if msg_index = 0 or character'pos(msg(msg_index + 1)) = 0 then -- message ran out or character is null
msg_index := 0;
msg_inverted := '0';
state_index := state_index - 1; -- pop one of the state stack
end if;
-- if fb_index = 0 then
-- state_index := state_index + 1; state(state_index) := SCROLL; -- put next state on stack
-- end if;
---------------------------------------------
when BLANK => -- Clear from fb_index to last line, then reset fb_index to 0
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(fb_index, 14));
fb_a_dat_in <= x"00";
fb_index := index_delta(fb_index);
if fb_index = CHARS - COLS then -- don't kill the last line
fb_index := 0; -- reset index, to facilitate the use as loop counter
state_index := state_index - 1; -- pop one of the state stack
end if;
---------------------------------------------
-- when SCROLL => -- move all of the screen up one row, read part
-- fb_a_en <= '1';
-- -- Read next line's char
-- fb_a_addr <= std_logic_vector(to_unsigned((fb_index + COLS) mod CHARS, 14));
-- state(state_index) := SCROLL_W; -- override current state
-- when SCROLL_W => -- Write part of scroll state
-- fb_a_en <= '1';
-- -- Write current char
-- fb_a_we <= "1";
-- fb_a_addr <= std_logic_vector(to_unsigned(fb_index, 14));
-- -- Last line is special
-- if fb_index > INPUT_LINE then
-- fb_a_dat_in <= x"00";
-- -- Last character is the exit condition
-- if fb_index = CHARS - 1 then
-- -- Wrap fb_index to fist col, last line
-- fb_index := INPUT_LINE;
-- state_index := state_index - 1; -- pop one of the state stack
-- -- Last line doesn't need to go back to read the mem
-- else
-- fb_index := index_delta(fb_index);
-- state(state_index) := SCROLL_W; -- override return state
-- end if;
-- -- Copy data
-- else
-- fb_index := index_delta(fb_index);
-- fb_a_dat_in <= fb_a_dat_out;
-- state(state_index) := SCROLL; -- override return state
-- end if;
---------------------------------------------
when others => -- WTF?
state(state_index) := ERROR; -- override return state
state_index := state_index + 1; state(state_index) := WRITE; -- put next state on stack
msg := pad_string("Illegal state", msg'LENGTH);
end case;
end if;
end process;
end Behavioral;
|
mit
|
9db715721ab711ecb241f57b4f02242c
| 0.390026 | 3.260983 | false | false | false | false |
luebbers/reconos
|
support/templates/bfmsim_xps_osif_v2_01_a/simulation/behavioral/bfm_memory_wrapper.vhd
| 4 | 6,409 |
-------------------------------------------------------------------------------
-- bfm_memory_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_slave_bfm_v1_00_a;
use plbv46_slave_bfm_v1_00_a.all;
entity bfm_memory_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MIRQ : out std_logic_vector(0 to 1)
);
end bfm_memory_wrapper;
architecture STRUCTURE of bfm_memory_wrapper is
component plbv46_slave_bfm is
generic (
PLB_SLAVE_SIZE : std_logic_vector(0 to 1);
PLB_SLAVE_NUM : std_logic_vector(0 to 3);
PLB_SLAVE_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE_ADDR_HI_1 : std_logic_vector(0 to 31);
C_SPLB_DWIDTH : integer;
C_SPLB_NUM_MASTERS : integer;
C_SPLB_MID_WIDTH : integer
);
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1))
);
end component;
begin
bfm_memory : plbv46_slave_bfm
generic map (
PLB_SLAVE_SIZE => B"10",
PLB_SLAVE_NUM => B"0000",
PLB_SLAVE_ADDR_LO_0 => X"10000000",
PLB_SLAVE_ADDR_HI_0 => X"1000ffff",
PLB_SLAVE_ADDR_LO_1 => X"20000000",
PLB_SLAVE_ADDR_HI_1 => X"2000ffff",
C_SPLB_DWIDTH => 128,
C_SPLB_NUM_MASTERS => 2,
C_SPLB_MID_WIDTH => 1
)
port map (
PLB_CLK => PLB_CLK,
PLB_RESET => PLB_RESET,
SYNCH_OUT => SYNCH_OUT,
SYNCH_IN => SYNCH_IN,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_msize => PLB_msize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_UABus => PLB_UABus,
PLB_ABus => PLB_ABus,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_rdpendReq => PLB_rdpendReq,
PLB_wrpendReq => PLB_wrpendReq,
PLB_rdpendPri => PLB_rdpendPri,
PLB_wrpendPri => PLB_wrpendPri,
PLB_reqPri => PLB_reqPri,
Sl_addrAck => Sl_addrAck,
Sl_ssize => Sl_ssize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MIRQ => Sl_MIRQ
);
end architecture STRUCTURE;
|
gpl-3.0
|
5a07f81289e28f192655d2ddd6e3ee58
| 0.587611 | 3.171202 | false | false | false | false |
makestuff/vhdl
|
memctrl/toplevel.vhdl
| 1 | 1,233 |
--
-- Copyright (C) 2011 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.memctrl_pkg.all;
entity toplevel is
port(
mcOp_in : in std_logic_vector(1 downto 0);
a_in : in std_logic;
b_in : in std_logic;
x_out : out std_logic
);
end entity;
architecture behavioural of toplevel is
signal mcOp : MCOpType;
begin
u1: memctrl
port map(
mcOp_in => mcOp,
a_in => a_in,
b_in => b_in,
x_out => x_out
);
mcOp <=
MC_READ when mcOp_in = "01" else
MC_WRITE when mcOp_in = "10" else
MC_NOP;
end architecture;
|
gpl-3.0
|
6aa503dff43bf1dde0cf2e2813fd4558
| 0.698297 | 3.219321 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/ml403/ml403_light_pr/pcores/lisipif_master_v1_00_c/hdl/vhdl/lipif_mst_read.vhd
| 1 | 7,579 |
--------------------------------------------------------------------------------
-- Company: Lehrstuhl Integrierte Systeme - TUM
-- Engineer: Johannes Zeppenfeld
--
-- Project Name: LIS-IPIF
-- Module Name: lipif_slv_read
-- Architectures: lipif_slv_read_rtl
-- Description:
--
-- Dependencies:
-- lipif_mst_pipeliner
--
-- Notes:
-- When Sl_rdBTerm is asserted at the end of a primary transfer,
-- M_rdBurst must be set according to the secondary transfer in
-- the following cycle.
-- M_rdBurst may not be set until after AddrAck!!!
--
-- Revision:
-- 11.4.2006 - File Created
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library lisipif_master_v1_00_c;
use lisipif_master_v1_00_c.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lipif_mst_read is
generic (
C_NUM_WIDTH : integer := 5;
C_EN_SRL16 : boolean := true;
C_EN_FAST_ABORT : boolean := false
);
port (
clk : in std_logic;
reset : in std_logic;
-- Control Signals to/from Arbiter
xfer_rdy_o : out std_logic;
xfer_init_i : in std_logic;
xfer_ack_i : in std_logic;
xfer_rearb_i : in std_logic;
xfer_retry_o : out std_logic;
xfer_abort_o : out std_logic;
-- LIS-IPIC Transfer Signals
M_rdNum_i : in std_logic_vector(C_NUM_WIDTH-1 downto 0);
M_rdRearb_o : out std_logic;
M_rdAbort_i : in std_logic;
M_rdError_o : out std_logic;
M_rdData_o : out std_logic_vector(63 downto 0);
M_rdAck_o : out std_logic;
M_rdComp_o : out std_logic;
-- PLB Signals
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
M_rdBurst : out std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63)
);
end lipif_mst_read;
architecture lipif_mst_read_rtl of lipif_mst_read is
-- Pipebuf primary control signals
signal prim_valid : std_logic;
signal prim_last : std_logic;
signal prim_ack : std_logic;
signal prim_ack_p : std_logic;
signal prim_comp : std_logic;
-- Transfer termination requests from IP/PLB
signal mst_term : std_logic;
signal mst_term_r : std_logic; -- Track until transfer complete
signal plb_term : std_logic;
-- Burst will continue through next cycle
signal prim_burst_nxt : std_logic;
signal pipe_burst_nxt : std_logic;
begin
-- Generate PLB read burst signal (M_rdBurst)
-- TIMING(18%) M_rdBurst is a register, so no problem
-- TODO: When C_EN_FAST_ABORT, M_rdBurst must respond with M_rdAbort
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
M_rdBurst <= '0';
else
-- Burst must display pipelined value in response to PLB terminate
if(PLB_MRdBTerm='1') then
M_rdBurst <= pipe_burst_nxt;
-- Burst must go low in response to IP abort
elsif(M_rdAbort_i='1') then
M_rdBurst <= '0';
-- Update burst signal at start of transfer, or with each data ack
-- TODO: M_rdBurst may not be asserted until xfer_ack_i
elsif(xfer_init_i='1' or PLB_MRdDAck='1') then
M_rdBurst <= prim_burst_nxt;
end if;
end if;
end if;
end process;
-- process(plb_term, mst_term_r, prim_last, pipe_burst, pipe_valid) begin
-- if(plb_term='1') then
-- M_rdBurst <= pipe_burst and pipe_valid;
-- else
-- M_rdBurst <= not mst_term_r and not prim_last;
-- end if;
-- end process;
-- Assert prim_comp to complete transfer:
-- * with last d-ack of transfer
-- * with next d-ack when plb_term or mst_term are asserted
-- * with mst_term when primary transfer not acknowledged
process(PLB_MRdDAck, prim_last, plb_term, mst_term, prim_ack) begin
if(PLB_MRdDAck='1') then
prim_comp <= prim_last or plb_term or mst_term;
else
prim_comp <= mst_term and not prim_ack;
end if;
end process;
-- Latch IP termination request until completion of transfer
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
mst_term_r <= '0';
else
if(prim_comp='1') then
mst_term_r <= '0';
elsif(M_rdAbort_i='1') then
mst_term_r <= '1';
end if;
end if;
end if;
end process;
-- When not C_EN_FAST_ABORT, assert terminate signal immediately only if rearbitrating
NEN_FAST_ABORT: if(not C_EN_FAST_ABORT) generate
mst_term <= M_rdAbort_i when(xfer_rearb_i='1' and prim_ack_p='0') else mst_term_r;
end generate NEN_FAST_ABORT;
-- When C_EN_FAST_ABORT, always pass M_rdAbort_i through
EN_FAST_ABORT: if(C_EN_FAST_ABORT) generate
mst_term <= '1' when(mst_term_r='1') else M_rdAbort_i;
end generate EN_FAST_ABORT;
-- Wait until one cycle after prim_ack goes low before rearbitrating
M_rdRearb_o <= xfer_rearb_i and not prim_ack_p;
-- Control signals to arbiter (Affect arbiter only!)
xfer_retry_o <= xfer_rearb_i and not prim_ack_p;
xfer_abort_o <= mst_term and prim_valid and not prim_ack;
-- Various registers
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
M_rdData_o <= (others=>'0');
M_rdAck_o <= '0';
M_rdComp_o <= '0';
M_rdError_o <= '0';
plb_term <= '0';
else
M_rdAck_o <= PLB_MRdDAck;
if(PLB_MRdDAck='1') then
M_rdData_o <= PLB_MRdDBus;
end if;
-- Generate delayed prim_ack for rearbitration signal generation
prim_ack_p <= prim_ack;
-- IPIC's complete signal is pipeliner's complete signal delayed
M_rdComp_o <= prim_comp;
-- Error occurred if transfer completes before all data was transferred,
-- or if transfer was never acknowledged
M_rdError_o <= prim_comp and (not prim_last or not prim_ack);
-- Keep track of previous termination request by slave
-- Since PLB_MRdBTerm may already be asserted for a following transfer
-- with the last data item, give priority to asserting plb_term
if(PLB_MRdBTerm='1') then
plb_term <= '1';
elsif(prim_comp='1') then
plb_term <= '0';
end if;
end if;
end if;
end process;
-- Instantiate the request pipeliner
pipeliner_0: entity lisipif_master_v1_00_c.lipif_mst_pipeliner
generic map (
C_NUM_WIDTH => C_NUM_WIDTH
)
port map (
clk => clk,
reset => reset,
xfer_num_i => M_rdNum_i,
xfer_adv_i => PLB_MRdDAck,
xfer_nxt_i => prim_comp,
xfer_req_i => xfer_init_i,
xfer_ack_i => xfer_ack_i,
xfer_rdy_o => xfer_rdy_o,
prim_valid_o => prim_valid,
prim_last_o => prim_last,
prim_ack_o => prim_ack,
prim_nburst_o => prim_burst_nxt,
pipe_nburst_o => pipe_burst_nxt
);
end lipif_mst_read_rtl;
|
gpl-3.0
|
80c64e947f5713652b74550ab2244c98
| 0.564191 | 3.593646 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/ll_fifo_BRAM.vhd
| 1 | 9,049 |
-------------------------------------------------------------------------------
--
-- Module : ll_fifo_BRAM.vhd
--
-- Version : 1.2
--
-- Last Update : 2005-06-29
--
-- Project : Parameterizable LocalLink FIFO
--
-- Description : Top Level of LocalLink FIFO in BRAM implementation
--
-- Designer : Wen Ying Wei, Davy Huang
--
-- Company : Xilinx, Inc.
--
-- Disclaimer : XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2005 Xilinx, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.BRAM_fifo_pkg.all;
entity ll_fifo_BRAM is
generic (
BRAM_MACRO_NUM : integer:=1; --Number of BRAMs. Values Allowed: 1, 2, 4, 8, 16
WR_DWIDTH : integer:= 8; --FIFO write data width, allowable values are
--8, 16, 32, 64, 128.
RD_DWIDTH : integer:= 8; --FIFO read data width, allowable values are
--8, 16, 32, 64, 128.
WR_REM_WIDTH : integer:= 1; --Width of remaining data to transmitting side
RD_REM_WIDTH : integer:= 1; --Width of remaining data to receiving side
USE_LENGTH: boolean :=true;
glbtm : time:= 1 ns);
port (
-- Reset
reset: in std_logic;
-- clocks
write_clock_in: in std_logic;
read_clock_in: in std_logic;
-- signals tranceiving from User Application using standardized specification
-- for FIFO interface
data_in: in std_logic_vector(WR_DWIDTH-1 downto 0);
rem_in: in std_logic_vector(WR_REM_WIDTH-1 downto 0);
sof_in_n: in std_logic;
eof_in_n: in std_logic;
src_rdy_in_n: in std_logic;
dst_rdy_out_n: out std_logic;
-- signals trasceiving from Aurora
data_out: out std_logic_vector(RD_DWIDTH-1 downto 0);
rem_out: out std_logic_vector(RD_REM_WIDTH-1 downto 0);
sof_out_n: out std_logic;
eof_out_n: out std_logic;
src_rdy_out_n: out std_logic;
dst_rdy_in_n: in std_logic;
-- FIFO status signals
fifostatus_out: out std_logic_vector(3 downto 0);
-- Length Status
len_rdy_out: out std_logic;
len_out: out std_logic_vector(15 downto 0);
len_err_out: out std_logic);
end ll_fifo_BRAM;
architecture ll_fifo_BRAM_rtl of ll_fifo_BRAM is
signal gsr: std_logic;
signal gnd: std_logic := '0';
signal pwr: std_logic := '1';
signal rd_clk: std_logic;
signal wr_clk: std_logic;
signal rd_data: std_logic_vector(RD_DWIDTH-1 downto 0) := (others => '0');
signal wr_data: std_logic_vector(WR_DWIDTH-1 downto 0) := (others => '0');
signal rd_rem: std_logic_vector(RD_REM_WIDTH-1 downto 0) := (others => '0');
signal wr_rem: std_logic_vector(WR_REM_WIDTH-1 downto 0) := (others => '0');
signal rd_sof_n: std_logic;
signal rd_eof_n: std_logic;
signal wr_sof_n: std_logic;
signal wr_eof_n: std_logic;
signal src_rdy_i: std_logic;
signal full: std_logic;
signal empty: std_logic;
signal dst_rdy_i: std_logic;
signal empty_p: std_logic;
signal prefetch: std_logic;
signal fifostatus: std_logic_vector(3 downto 0);
signal data_valid: std_logic;
signal len: std_logic_vector(15 downto 0);
signal len_rdy: std_logic;
signal len_err: std_logic;
signal empty_falling_edge: std_logic;
signal prefetch_allow: std_logic;
begin
gsr <= reset;
rd_clk <= read_clock_in;
wr_clk <= write_clock_in;
---------------------------------------
wr_data <= data_in;
wr_rem <= rem_in;
wr_sof_n <= sof_in_n;
wr_eof_n <= eof_in_n;
src_rdy_i <= not src_rdy_in_n;
dst_rdy_out_n <= full;
----- From User ---------------------
data_out <= rd_data;
rem_out <= rd_rem;
sof_out_n <= rd_sof_n;
eof_out_n <= rd_eof_n;
dst_rdy_i <= (not dst_rdy_in_n) or prefetch;
src_rdy_out_n <= not data_valid;
----- Flow control signals -----------
fifostatus_out <= fifostatus;
len_rdy_out <= len_rdy;
len_out <= len;
len_err_out <= len_err;
-----------------------------------------------------------------------------
B_RAM_FIFO: BRAM_fifo
generic map (
BRAM_MACRO_NUM => BRAM_MACRO_NUM,
WR_DWIDTH => WR_DWIDTH,
RD_DWIDTH => RD_DWIDTH,
RD_REM_WIDTH => RD_REM_WIDTH,
WR_REM_WIDTH => WR_REM_WIDTH,
USE_LENGTH => USE_LENGTH,
glbtm => glbtm)
port map
(
fifo_gsr_in => gsr,
write_clock_in => wr_clk,
read_clock_in => rd_clk,
read_data_out => rd_data,
read_rem_out => rd_rem,
read_sof_out_n => rd_sof_n,
read_eof_out_n => rd_eof_n,
read_enable_in => dst_rdy_i,
write_data_in => wr_data,
write_rem_in => wr_rem,
write_sof_in_n => wr_sof_n,
write_eof_in_n => wr_eof_n,
write_enable_in => src_rdy_i,
fifostatus_out => fifostatus,
full_out => full,
empty_out => empty,
data_valid_out => data_valid,
len_out => len,
len_rdy_out => len_rdy,
len_err_out => len_err);
--------------------------------------------------------------------
-- Generate PREFETCH
--------------------------------------------------------------------
prefetch_proc: process (gsr, rd_clk)
begin
if (gsr = '1') then
prefetch_allow <= '1' after glbtm;
elsif (rd_clk'EVENT and rd_clk = '1') then
if dst_rdy_in_n = '0' and empty = '1' then
prefetch_allow <= '1' after glbtm;
elsif dst_rdy_in_n = '1' and empty_falling_edge = '1' then
prefetch_allow <= '0' after glbtm;
elsif dst_rdy_in_n = '0' and empty = '0' then
prefetch_allow <= '0' after glbtm;
end if;
end if;
end process prefetch_proc;
empty_falling_edge <= (empty_p and (not empty));
prefetch <= empty_falling_edge and prefetch_allow;
empty_p_proc: process (gsr, rd_clk) -- Delayed empty signal
begin
if (gsr = '1') then
empty_p <= '1';
elsif (rd_clk'EVENT and rd_clk ='1') then
empty_p <= empty after glbtm;
end if;
end process empty_p_proc;
end ll_fifo_BRAM_rtl;
|
gpl-3.0
|
0d47a5a438abb1df671b0e829ff80ce1
| 0.445795 | 4.16046 | false | false | false | false |
five-elephants/hw-neural-sampling
|
virtex5/clockgen.vhdl
| 1 | 2,546 |
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use unisim.vcomponents.all; -- xilinx component declarations
entity clockgen is
port (
ext_clk, async_resetb : in std_ulogic;
clk, sync_reset : out std_ulogic
);
end clockgen;
architecture virtex5 of clockgen is
------------------------------------------------------------
-- local signals
------------------------------------------------------------
signal clk_i : std_ulogic;
signal locked : std_ulogic;
signal clock_from_ibufg : std_ulogic;
signal reset, reset_sync : std_ulogic;
signal clkfb : std_ulogic;
signal clk_to_bufg : std_ulogic;
signal reset_cond : std_ulogic;
begin
clk <= clk_i;
------------------------------------------------------------
-- clock generation
------------------------------------------------------------
clock_pin_ibufg: ibufg
port map(
I => ext_clk,
O => clock_from_ibufg
);
------------------------------------------------------------
-- reset synchronizer
------------------------------------------------------------
reset_synchronizer: process ( clock_from_ibufg, async_resetb )
begin
if async_resetb = '0' then
reset <= '1';
reset_sync <= '1';
elsif rising_edge(clk_i) then
reset <= reset_sync;
reset_sync <= '0';
end if;
end process;
------------------------------------------------------------
------------------------------------------------------------
-- PLL
------------------------------------------------------------
pll_inst: pll_base
generic map (
clkfbout_mult => 6,
clkout0_divide => 6,
clkin_period => 10.0
)
port map (
clkin => clock_from_ibufg,
rst => reset,
clkfbout => clkfb,
clkfbin => clkfb,
clkout0 => clk_to_bufg,
clkout1 => open,
clkout2 => open,
clkout3 => open,
clkout4 => open,
clkout5 => open,
locked => locked
);
gen_clk_bufg: bufg
port map (
I => clk_to_bufg,
O => clk_i
);
------------------------------------------------------------
-- synchronous reset output
------------------------------------------------------------
reset_cond <= not locked or reset;
------------------------------------------------------------
sync_rst_out: process ( clk_i, reset_cond )
begin
if reset_cond = '1' then
sync_reset <= '1';
elsif rising_edge(clk_i) then
sync_reset <= '0';
end if;
end process;
------------------------------------------------------------
end virtex5;
|
apache-2.0
|
eb8c4a1cd015dadb4d2acb7f970abf6e
| 0.408877 | 4.75 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/work7/bigcount.vhd
| 4 | 623 |
library ieee;
use ieee.std_logic_1164.all;
use work.work7.all;
entity bigcount is
port (clk, reset: in std_logic;
count: out std_logic_vector (24 downto 0)
);
end entity bigcount;
architecture bigcount_rtl of bigcount is
signal d, t, q, myreset: std_logic;
begin
d <= t xor q;
myreset <= reset or t;
f1: fdc port map (clk => clk, reset => reset, d => d, q => q);
tb: timebase port map (CLOCK => clk, RESET => myreset, ENABLE => '1', TICK => t, COUNT_VALUE => open );
counting: timebase port map (CLOCK => clk, RESET => reset, ENABLE => q, TICK => open, COUNT_VALUE => count );
end bigcount_rtl;
|
gpl-2.0
|
77204a63cdc9f56ae51caea92a3a13e5
| 0.640449 | 3.115 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/DRAM/DRAM_fifo_pkg.vhd
| 1 | 7,120 |
-------------------------------------------------------------------------------
--
-- Module : DRAM_fifo_pkg.vhd
--
-- Version : 1.2
--
-- Last Update : 2005-06-29
--
-- Project : Parameterizable LocalLink FIFO
--
-- Description : Package of Distributed RAM FIFO components
--
-- Designer : Wen Ying Wei, Davy Huang
--
-- Company : Xilinx, Inc.
--
-- Disclaimer : XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2005 Xilinx, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package DRAM_fifo_pkg is
component DRAM_fifo
generic (
DRAM_DEPTH: integer;
WR_DWIDTH: integer;
RD_DWIDTH: integer;
RD_REM_WIDTH: integer;
WR_REM_WIDTH: integer;
USE_LENGTH: boolean;
glbtm: time
);
port (
-- Reset
FIFO_GSR_IN: in std_logic;
-- clocks
WRITE_CLOCK_IN: in std_logic;
READ_CLOCK_IN: in std_logic;
-- signals tranceiving from User Application using standardized
-- specification for FifO interface
READ_DATA_OUT: out std_logic_vector(RD_DWIDTH-1 downto 0);
READ_REM_OUT: out std_logic_vector(RD_REM_WIDTH-1 downto 0);
READ_SOF_OUT_N: out std_logic;
READ_EOF_OUT_N: out std_logic;
READ_ENABLE_IN: in std_logic;
-- signals trasceiving from Aurora
WRITE_DATA_IN: in std_logic_vector(WR_DWIDTH-1 downto 0);
WRITE_REM_IN: in std_logic_vector(WR_REM_WIDTH-1 downto 0);
WRITE_SOF_IN_N: in std_logic;
WRITE_EOF_IN_N: in std_logic;
WRITE_ENABLE_IN: in std_logic;
-- FifO status signals
FIFOSTATUS_OUT: out std_logic_vector(3 downto 0);
FULL_OUT: out std_logic;
EMPTY_OUT: out std_logic;
DATA_VALID_OUT: out std_logic;
LEN_OUT: out std_logic_vector(15 downto 0);
LEN_RDY_OUT: out std_logic;
LEN_ERR_OUT: out std_logic);
end component;
component DRAM_macro is
generic (
DRAM_DEPTH : integer := 16; -- FIFO depth, default is 16,
-- allowable values are 16, 32,
-- 64, 128.
WR_DWIDTH : integer := 32; --FIFO write data width.
--Allowed: 8, 16, 32, 64
RD_DWIDTH : integer := 32; --FIFO read data width.
--Allowed: 8, 16, 32, 64
WR_REM_WIDTH : integer := 2; --log2(WR_DWIDTH/8)
RD_REM_WIDTH : integer := 2; --log2(RD_DWIDTH/8)
RD_ADDR_MINOR_WIDTH : integer := 1;
RD_ADDR_WIDTH : integer := 9;
WR_ADDR_MINOR_WIDTH : integer := 1;
WR_ADDR_WIDTH : integer := 9;
CTRL_WIDTH: integer := 3;
glbtm : time := 1 ns );
port (
-- Reset
fifo_gsr: in std_logic;
-- clocks
wr_clk: in std_logic;
rd_clk: in std_logic;
rd_allow: in std_logic;
rd_allow_minor: in std_logic;
rd_addr_minor: in std_logic_vector(RD_ADDR_MINOR_WIDTH-1 downto 0);
rd_addr: in std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
rd_data: out std_logic_vector(RD_DWIDTH -1 downto 0);
rd_rem: out std_logic_vector(RD_REM_WIDTH-1 downto 0);
rd_sof_n: out std_logic;
rd_eof_n: out std_logic;
wr_allow: in std_logic;
wr_allow_minor: in std_logic;
wr_allow_minor_p: in std_logic;
wr_addr: in std_logic_vector(WR_ADDR_WIDTH-1 downto 0);
wr_addr_minor: in std_logic_vector(WR_ADDR_MINOR_WIDTH-1 downto 0);
wr_data: in std_logic_vector(WR_DWIDTH-1 downto 0);
wr_rem: in std_logic_vector(WR_REM_WIDTH-1 downto 0);
wr_sof_n: in std_logic;
wr_eof_n: in std_logic;
wr_sof_n_p: in std_logic;
wr_eof_n_p: in std_logic;
ctrl_wr_buf: out std_logic_vector(CTRL_WIDTH-1 downto 0)
);
end component;
component RAM_64nX1
generic (
RAM_NUM : integer; -- 4, 8
ADDR_WIDTH : integer -- equal to ceiling[log2(RAM_NUM * 64)]
);
port (
DI : in std_logic;
WEn : in std_logic;
WCLK : in std_logic;
Ad : in std_logic_vector(ADDR_WIDTH-1 downto 0);
DRA : in std_logic_vector(ADDR_WIDTH-1 downto 0);
DO : out std_logic;
SO : out std_logic);
end component;
end DRAM_fifo_pkg;
|
gpl-3.0
|
ae4f62a23c69d34b712f6880622032cd
| 0.427669 | 4.500632 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/gxor.vhd
| 4 | 909 |
library ieee;
use ieee.std_logic_1164.all;
entity gxor is
port (a, b: in std_logic;
z : out std_logic);
end gxor;
architecture gxor_rtl of gxor is
begin
z <= a xor b;
end architecture gxor_rtl;
library ieee;
use ieee.std_logic_1164.all;
entity gxor_reduce is
generic (half_width: integer := 4);
port (a: in std_logic_vector (2*half_width-1 downto 0);
ar: out std_logic);
end gxor_reduce;
architecture gxor_reduce_rtl of gxor_reduce is
component gxor is
port (a, b: in std_logic;
z : out std_logic);
end component;
--type path is array (0 to size/2) of std_logic;
signal x_int: std_logic_vector (2*half_width downto 0);
begin
x_int(2*half_width) <= '0'; -- MSB
gen_xor: for i in 2*half_width downto 1 generate
each_gate: gxor port map (a => x_int(i), b => a(i-1), z => x_int(i-1) );
end generate;
ar <= x_int(0);
end architecture gxor_reduce_rtl;
|
gpl-2.0
|
4001d1c057823123b4b34cfdf3f8b745
| 0.649065 | 2.822981 | false | false | false | false |
luebbers/reconos
|
tests/benchmarks/mutex/hw/src/hwt_mutex.vhd
| 1 | 14,608 |
--
-- hwt_mutex.vhd: measure time for mutex_lock/unlock() operation
--
-- This HW thread measures the time it takes to execute a mutex_unlock()
-- operation from hardware.
-- To avoid side effects caused by activity of the delegate after returnung
-- from a mutex_unlock() call, this thread waits a defined number of clock
-- cycles between consecutive calls to reconos_mutex_unlock(). This number can
-- be configured using the init_data value. A typical value is 100000, which
-- is equivalent to a millisecond.
--
-- This HW thread uses the dcr_timebase core to do consistent and synchronized
-- measurements of elapsed bus clock cycles.
--
-- Author Enno Luebbers <[email protected]>
-- Date 12.02.2008
--
-- For detailed documentation of the functions, see the associated header
-- file or the documentation (if such a header exists).
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group
--
-- (C) Copyright University of Paderborn 2007. Permission to copy,
-- use, modify, sell and distribute this software is granted provided
-- this copyright notice appears in all copies. This software is
-- provided "as is" without express or implied warranty, and with no
-- claim as to its suitability for any purpose.
--
---------------------------------------------------------------------------
-- Major Changes:
--
-- 12.02.2008 Enno Luebbers File created
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.all;
entity hwt_mutex is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector( 0 to C_BURST_AWIDTH-1 );
o_RAMData : out std_logic_vector( 0 to C_BURST_DWIDTH-1 );
i_RAMData : in std_logic_vector( 0 to C_BURST_DWIDTH-1 );
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- time base
i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end entity;
architecture Behavioral of hwt_mutex is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
constant C_MUTEX : std_logic_vector(31 downto 0) := X"00000000";
constant C_SEM_POST : std_logic_vector(31 downto 0) := X"00000001";
constant C_SEM_WAIT : std_logic_vector(31 downto 0) := X"00000002";
constant C_MBOX_RESULT : std_logic_vector(31 downto 0) := X"00000003";
type t_state is ( STATE_INIT, -- get initial data (delay in clocks)
STATE_WAIT_BEFORE_LOCK, -- wait before measuring
STATE_MUTEX_LOCK, -- lock mutex
STATE_MEASURE_LOCK, -- measure elapsed time
STATE_WAIT_AFTER_LOCK, -- wait after measuring
STATE_SEM_POST, -- post semaphore
STATE_SEM_WAIT, -- wait for semaphore from main()
STATE_WAIT_BEFORE_UNLOCK, -- wait before measuring
STATE_MUTEX_UNLOCK, -- unlock mutex
STATE_MEASURE_UNLOCK, -- measure elapsed time
STATE_WAIT_AFTER_UNLOCK, -- wait after measuring
STATE_PUT_LOCK_START, -- post elapsed time to software mbox
STATE_PUT_LOCK_STOP,
STATE_PUT_UNLOCK_START,
STATE_PUT_UNLOCK_STOP,
STATE_EXIT); -- exit
signal state : t_state;
signal counter : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal reset_counter : std_logic := '1';
begin
state_proc: process( clk, reset )
variable delay : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable lock_start : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable lock_stop : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable unlock_start : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable unlock_stop : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable retval : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable done : boolean := false;
variable success : boolean := false;
begin
if reset = '1' then
reconos_reset( o_osif, i_osif );
state <= STATE_INIT;
reset_counter <= '1';
lock_start := (others => '0');
lock_stop := (others => '0');
unlock_start := (others => '0');
unlock_stop := (others => '0');
retval := (others => '0');
elsif rising_edge( clk ) then
reconos_begin( o_osif, i_osif );
if reconos_ready( i_osif ) then
case state is
when STATE_INIT =>
reconos_get_init_data(done, o_osif, i_osif, delay);
reset_counter <= '1';
if done then
state <= STATE_WAIT_BEFORE_LOCK;
end if;
when STATE_WAIT_BEFORE_LOCK =>
reset_counter <= '0';
if counter >= delay then
reset_counter <= '1';
lock_start := i_timeBase;
state <= STATE_MUTEX_LOCK;
end if;
when STATE_MUTEX_LOCK =>
reconos_mutex_lock(done, success, o_osif, i_osif, C_MUTEX);
if done then
if success then
state <= STATE_MEASURE_LOCK;
else
retval := X"0000_0001"; -- mutex lock failed
state <= STATE_EXIT;
end if;
end if;
when STATE_MEASURE_LOCK =>
lock_stop := i_timeBase;
state <= STATE_WAIT_AFTER_LOCK;
when STATE_WAIT_AFTER_LOCK =>
reset_counter <= '0';
if counter >= delay then
reset_counter <= '1';
state <= STATE_SEM_POST;
end if;
when STATE_SEM_POST =>
reconos_sem_post(o_osif, i_osif, C_SEM_POST);
state <= STATE_SEM_WAIT;
when STATE_SEM_WAIT =>
reconos_sem_wait(o_osif, i_osif, C_SEM_WAIT);
state <= STATE_WAIT_BEFORE_UNLOCK;
when STATE_WAIT_BEFORE_UNLOCK =>
reset_counter <= '0';
if counter >= delay then
reset_counter <= '1';
unlock_start := i_timeBase;
state <= STATE_MUTEX_UNLOCK;
end if;
when STATE_MUTEX_UNLOCK =>
reconos_mutex_unlock(o_osif, i_osif, C_MUTEX);
state <= STATE_MEASURE_UNLOCK;
when STATE_MEASURE_UNLOCK =>
unlock_stop := i_timeBase;
state <= STATE_WAIT_AFTER_UNLOCK;
when STATE_WAIT_AFTER_UNLOCK =>
reset_counter <= '0';
if counter >= delay then
reset_counter <= '1';
state <= STATE_PUT_LOCK_START;
end if;
when STATE_PUT_LOCK_START =>
reconos_mbox_put(done,
success,
o_osif,
i_osif,
C_MBOX_RESULT,
lock_start);
if done then
if success then
state <= STATE_PUT_LOCK_STOP;
else
retval := X"0000_0002"; -- first mbox_put failed
state <= STATE_EXIT;
end if;
end if;
when STATE_PUT_LOCK_STOP =>
reconos_mbox_put(done,
success,
o_osif,
i_osif,
C_MBOX_RESULT,
lock_stop);
if done then
if success then
state <= STATE_PUT_UNLOCK_START;
else
retval := X"0000_0003"; -- second mbox_put failed
state <= STATE_EXIT;
end if;
end if;
when STATE_PUT_UNLOCK_START =>
reconos_mbox_put(done,
success,
o_osif,
i_osif,
C_MBOX_RESULT,
unlock_start);
if done then
if success then
state <= STATE_PUT_UNLOCK_STOP;
else
retval := X"0000_0004"; -- third mbox_put failed
state <= STATE_EXIT;
end if;
end if;
when STATE_PUT_UNLOCK_STOP =>
reconos_mbox_put(done,
success,
o_osif,
i_osif,
C_MBOX_RESULT,
unlock_stop);
if done then
if success then
retval := X"0000_0000"; -- all is well
state <= STATE_EXIT;
else
retval := X"0000_0005"; -- fourth mbox_put failed
state <= STATE_EXIT;
end if;
end if;
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, retval);
end case;
end if;
end if;
end process;
--
-- counter process to wait cycles
--
counter_proc : process(clk, reset)
begin
if reset = '1' then
counter <= (others => '0');
elsif rising_edge(clk) then
if reset_counter = '1' then
counter <= (others => '0');
else
counter <= counter + 1;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
66f045d3dfc917de4df6c10ca1dee055
| 0.347549 | 6.179357 | false | false | false | false |
oetr/FPGA-I2C-Slave
|
I2C_minion_TB_001_ideal.vhd
| 1 | 14,870 |
-----------------------------------------------------------------------------
-- Title : I2C_minion Testbench
-----------------------------------------------------------------------------
-- File : I2C_minion_TB_001_ideal
-- Author : Peter Samarin <[email protected]>
-----------------------------------------------------------------------------
-- Copyright (c) 2019 Peter Samarin
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.txt_util.all;
------------------------------------------------------------------------
entity I2C_minion_TB_001_ideal is
end I2C_minion_TB_001_ideal;
------------------------------------------------------------------------
architecture Testbench of I2C_minion_TB_001_ideal is
constant T : time := 20 ns; -- clk period
constant TH_I2C : time := 100 ns; -- i2c clk quarter period(kbis)
constant T_MUL : integer := 2; -- i2c clk quarter period(kbis)
constant T_HALF : integer := (TH_I2C*T_MUL*2) / T; -- i2c halfclk period
constant T_QUARTER : integer := (TH_I2C*T_MUL) / T; -- i2c quarterclk period
signal clk : std_logic := '1';
signal rst : std_logic := '1';
signal scl : std_logic := 'Z';
signal sda : std_logic := 'Z';
signal state_dbg : integer := 0;
signal received_data : std_logic_vector(7 downto 0) := (others => '0');
signal ack : std_logic := '0';
signal read_req : std_logic := '0';
signal data_to_master : std_logic_vector(7 downto 0) := (others => '0');
signal data_valid : std_logic := '0';
signal data_from_master : std_logic_vector(7 downto 0) := (others => '0');
signal data_from_master_reg : std_logic_vector(7 downto 0) := (others => '0');
shared variable seed1 : positive := 1000;
shared variable seed2 : positive := 2000;
-- simulation control
shared variable ENDSIM : boolean := false;
begin
---- Design Under Verification -----------------------------------------
DUV : entity work.I2C_minion
generic map (
MINION_ADDR => "0000011",
USE_INPUT_DEBOUNCING => false)
port map (
-- I2C
scl => scl,
sda => sda,
-- default signals
clk => clk,
rst => rst,
-- user interface
read_req => read_req,
data_to_master => data_to_master,
data_valid => data_valid,
data_from_master => data_from_master);
---- DUT clock running forever ----------------------------
process
begin
if ENDSIM = false then
clk <= '0';
wait for T/2;
clk <= '1';
wait for T/2;
else
wait;
end if;
end process;
---- Reset asserted for T/2 ------------------------------
rst <= '1', '0' after T/2;
----------------------------------------------------------
-- Save data received from the master in a register
----------------------------------------------------------
process (clk) is
begin
if rising_edge(clk) then
if data_valid = '1' then
data_from_master_reg <= data_from_master;
end if;
end if;
end process;
----- Test vector generation -------------------------------------------
TESTS : process is
-- half clock
procedure i2c_wait_half_clock is
begin
for i in 0 to T_HALF loop
wait until rising_edge(clk);
end loop;
end procedure i2c_wait_half_clock;
-- quarter clock
procedure i2c_wait_quarter_clock is
begin
for i in 0 to T_QUARTER loop
wait until rising_edge(clk);
end loop;
end procedure i2c_wait_quarter_clock;
-- Write Bit
procedure i2c_send_bit (
constant a_bit : in std_logic) is
begin
scl <= '0';
if a_bit = '0' then
sda <= '0';
else
sda <= 'Z';
end if;
i2c_wait_quarter_clock;
scl <= 'Z';
i2c_wait_half_clock;
scl <= '0';
i2c_wait_quarter_clock;
end procedure i2c_send_bit;
-- Read Bit
procedure i2c_receive_bit (
variable a_bit : out std_logic) is
begin
scl <= '0';
sda <= 'Z';
i2c_wait_quarter_clock;
scl <= 'Z';
i2c_wait_quarter_clock;
if sda = '0' then
a_bit := '0';
else
a_bit := '1';
end if;
i2c_wait_quarter_clock;
scl <= '0';
i2c_wait_quarter_clock;
end procedure i2c_receive_bit;
-- Write Byte
procedure i2c_send_byte (
constant a_byte : in std_logic_vector(7 downto 0)) is
begin
for i in 7 downto 0 loop
i2c_send_bit(a_byte(i));
end loop;
end procedure i2c_send_byte;
-- Address
procedure i2c_send_address (
constant address : in std_logic_vector(6 downto 0)) is
begin
for i in 6 downto 0 loop
i2c_send_bit(address(i));
end loop;
end procedure i2c_send_address;
-- Read Byte
procedure i2c_receive_byte (
signal a_byte : out std_logic_vector(7 downto 0)) is
variable a_bit : std_logic;
variable accu : std_logic_vector(7 downto 0) := (others => '0');
begin
for i in 7 downto 0 loop
i2c_receive_bit(a_bit);
accu(i) := a_bit;
end loop;
a_byte <= accu;
end procedure i2c_receive_byte;
-- START
procedure i2c_start is
begin
scl <= 'Z';
sda <= '0';
i2c_wait_half_clock;
scl <= 'Z';
i2c_wait_quarter_clock;
scl <= '0';
i2c_wait_quarter_clock;
end procedure i2c_start;
-- STOP
procedure i2c_stop is
begin
scl <= '0';
sda <= '0';
i2c_wait_quarter_clock;
scl <= 'Z';
i2c_wait_quarter_clock;
sda <= 'Z';
i2c_wait_half_clock;
i2c_wait_half_clock;
end procedure i2c_stop;
-- send write
procedure i2c_set_write is
begin
i2c_send_bit('0');
end procedure i2c_set_write;
-- send read
procedure i2c_set_read is
begin
i2c_send_bit('1');
end procedure i2c_set_read;
-- read ACK
procedure i2c_read_ack (signal ack : out std_logic) is
begin
scl <= '0';
sda <= 'Z';
i2c_wait_quarter_clock;
scl <= 'Z';
if sda = '0' then
ack <= '1';
else
ack <= '0';
assert false report "No ACK received: expected '0'" severity note;
end if;
i2c_wait_half_clock;
scl <= '0';
i2c_wait_quarter_clock;
end procedure i2c_read_ack;
-- write NACK
procedure i2c_write_nack is
begin
scl <= '0';
sda <= 'Z';
i2c_wait_quarter_clock;
scl <= 'Z';
i2c_wait_half_clock;
scl <= '0';
i2c_wait_quarter_clock;
end procedure i2c_write_nack;
-- write ACK
procedure i2c_write_ack is
begin
scl <= '0';
sda <= '0';
i2c_wait_quarter_clock;
scl <= 'Z';
i2c_wait_half_clock;
scl <= '0';
i2c_wait_quarter_clock;
end procedure i2c_write_ack;
-- write to I2C bus
procedure i2c_write (
constant address : in std_logic_vector(6 downto 0);
constant data : in std_logic_vector(7 downto 0)) is
begin
state_dbg <= 0;
i2c_start;
state_dbg <= 1;
i2c_send_address(address);
state_dbg <= 2;
i2c_set_write;
state_dbg <= 3;
-- dummy read ACK--don't care, because we are testing
-- I2C minion
i2c_read_ack(ack);
if ack = '0' then
state_dbg <= 6;
i2c_stop;
ack <= '0';
return;
end if;
state_dbg <= 4;
i2c_send_byte(data);
state_dbg <= 5;
i2c_read_ack(ack);
state_dbg <= 6;
i2c_stop;
end procedure i2c_write;
-- write to I2C bus
procedure i2c_quick_write (
constant address : in std_logic_vector(6 downto 0);
constant data : in std_logic_vector(7 downto 0)) is
begin
state_dbg <= 0;
i2c_start;
state_dbg <= 1;
i2c_send_address(address);
state_dbg <= 2;
i2c_set_write;
state_dbg <= 3;
-- dummy read ACK--don't care, because we are testing
-- I2C minion
i2c_read_ack(ack);
if ack = '0' then
state_dbg <= 6;
i2c_stop;
ack <= '0';
return;
end if;
state_dbg <= 4;
i2c_send_byte(data);
state_dbg <= 5;
i2c_read_ack(ack);
scl <= '0';
sda <= '0';
i2c_wait_quarter_clock;
scl <= 'Z';
sda <= 'Z';
i2c_wait_quarter_clock;
end procedure i2c_quick_write;
-- read I2C bus
procedure i2c_write_bytes (
constant address : in std_logic_vector(6 downto 0);
constant nof_bytes : in integer range 0 to 1023) is
variable data : std_logic_vector(7 downto 0) := (others => '0');
begin
state_dbg <= 0;
i2c_start;
state_dbg <= 1;
i2c_send_address(address);
state_dbg <= 2;
i2c_set_write;
state_dbg <= 3;
i2c_read_ack(ack);
if ack = '0' then
i2c_stop;
return;
end if;
ack <= '0';
for i in 0 to nof_bytes-1 loop
state_dbg <= 4;
i2c_send_byte(std_logic_vector(to_unsigned(i, 8)));
state_dbg <= 5;
i2c_read_ack(ack);
if ack = '0' then
i2c_stop;
return;
end if;
ack <= '0';
end loop;
state_dbg <= 6;
i2c_stop;
end procedure i2c_write_bytes;
-- read from I2C bus
procedure i2c_read (
constant address : in std_logic_vector(6 downto 0);
signal data : out std_logic_vector(7 downto 0)) is
begin
state_dbg <= 0;
i2c_start;
state_dbg <= 1;
i2c_send_address(address);
state_dbg <= 2;
i2c_set_read;
state_dbg <= 3;
-- dummy read ACK--don't care, because we are testing
-- I2C minion
i2c_read_ack(ack);
if ack = '0' then
state_dbg <= 6;
i2c_stop;
return;
end if;
ack <= '0';
state_dbg <= 4;
i2c_receive_byte(data);
state_dbg <= 5;
i2c_write_nack;
state_dbg <= 6;
i2c_stop;
end procedure i2c_read;
-- read from I2C bus
procedure i2c_quick_read (
constant address : in std_logic_vector(6 downto 0);
signal data : out std_logic_vector(7 downto 0)) is
begin
state_dbg <= 0;
i2c_start;
state_dbg <= 1;
i2c_send_address(address);
state_dbg <= 2;
i2c_set_read;
state_dbg <= 3;
-- dummy read ACK--don't care, because we are testing
-- I2C minion
i2c_read_ack(ack);
if ack = '0' then
state_dbg <= 6;
i2c_stop;
return;
end if;
ack <= '0';
state_dbg <= 4;
i2c_receive_byte(data);
state_dbg <= 5;
i2c_write_nack;
scl <= '0';
sda <= '0';
i2c_wait_quarter_clock;
scl <= 'Z';
sda <= 'Z';
i2c_wait_quarter_clock;
end procedure i2c_quick_read;
-- read I2C bus
procedure i2c_read_bytes (
constant address : in std_logic_vector(6 downto 0);
constant nof_bytes : in integer range 0 to 1023;
signal data : out std_logic_vector(7 downto 0)) is
begin
state_dbg <= 0;
i2c_start;
state_dbg <= 1;
i2c_send_address(address);
state_dbg <= 2;
i2c_set_read;
state_dbg <= 3;
i2c_read_ack(ack);
if ack = '0' then
state_dbg <= 6;
i2c_stop;
return;
end if;
for i in 0 to nof_bytes-1 loop
-- dummy read ACK--don't care, because we are testing
-- I2C minion
state_dbg <= 4;
i2c_receive_byte(data);
state_dbg <= 5;
if i < nof_bytes-1 then
i2c_write_ack;
else
i2c_write_nack;
end if;
end loop;
state_dbg <= 6;
i2c_stop;
end procedure i2c_read_bytes;
begin
print("");
print("------------------------------------------------------------");
print("----------------- I2C_minion_TB_001_ideal ------------------");
print("------------------------------------------------------------");
scl <= 'Z';
sda <= 'Z';
print("----------------- Testing a single write ------------------");
i2c_write("0000011", "11111111");
assert data_from_master_reg = "11111111"
report "test: 0 not passed"
severity warning;
print("----------------- Testing a single write ------------------");
i2c_write("0000011", "11111010");
assert data_from_master_reg = "11111010"
report "test: 0 not passed"
severity warning;
print("----------------- Testing repeated writes -----------------");
wait until rising_edge(clk);
for i in 0 to 127 loop
i2c_write("0000011", std_logic_vector(to_unsigned(i, 8)));
assert i = to_integer(unsigned(data_from_master_reg))
report "writing test: " & integer'image(i) & " not passed"
severity warning;
end loop;
print("----------------- Testing repeated reads ------------------");
for i in 0 to 127 loop
data_to_master <= std_logic_vector(to_unsigned(i, 8));
i2c_read("0000011", received_data);
assert i = to_integer(unsigned(received_data))
report "reading test: " & integer'image(i) & " not passed" & "test"
severity warning;
end loop;
--------------------------------------------------------
-- Quick read/write
--------------------------------------------------------
print("----------------- Testing quick write --------------------");
i2c_quick_write("0000011", "10101010");
i2c_quick_write("0000011", "10101011");
i2c_quick_write("0000011", "10101111");
data_to_master <= std_logic_vector(to_unsigned(255, 8));
i2c_quick_read("0000011", received_data);
state_dbg <= 6;
i2c_stop;
--------------------------------------------------------
-- Reads, writes from wrong minion addresses
-- this should cause some assertion notes (needs manual
-- confirmation)
--------------------------------------------------------
print("----------------- Testing wrong addresses -----------------");
print("-> The following 3 tests should all fail");
print("[0] ---------------");
i2c_write_bytes("1000011", 100);
print("[1] ---------------");
i2c_read ("0101101", received_data);
print("[2] ---------------");
i2c_read_bytes ("0000010", 300, received_data);
wait until rising_edge(clk);
ENDSIM := true;
print("Simulation end...");
print("");
wait;
end process;
end Testbench;
|
mit
|
4d9502721e2c26804398ca227d85f6c6
| 0.487424 | 3.597871 | false | false | false | false |
bzero/freezing-spice
|
src/decode.vhd
| 2 | 8,974 |
library ieee;
use ieee.std_logic_1164.all;
use work.common.all;
use work.decode_pkg.all;
entity decoder is
port (insn : in word;
decoded : inout decoded_t); -- decoded data
end entity decoder;
architecture behavioral of decoder is
-- Enumerated types
type imm_type_t is (IMM_NONE, IMM_I, IMM_S, IMM_B, IMM_U, IMM_J);
begin -- architecture behavioral
-- purpose: decode the RISCV instruction
-- type : combinational
-- inputs : insn
-- outputs: decode
decode_proc : process (insn) is
variable opcode : std_logic_vector(6 downto 0);
variable funct3 : std_logic_vector(2 downto 0);
variable imm_type : imm_type_t := IMM_NONE;
begin -- process decode_proc
-- defaults & important fields
opcode := insn(6 downto 0);
funct3 := insn(14 downto 12);
decoded.rs1 <= insn(19 downto 15);
decoded.rs2 <= insn(24 downto 20);
decoded.rd <= insn(11 downto 7);
decoded.opcode <= opcode;
decoded.rs1_rd <= '0';
decoded.rs2_rd <= '0';
decoded.alu_func <= ALU_NONE;
decoded.op2_src <= '0';
decoded.insn_type <= OP_ILLEGAL;
decoded.load_type <= LOAD_NONE;
decoded.store_type <= STORE_NONE;
decoded.imm <= (others => '0');
decoded.rs1_rd <= '0';
decoded.rs2_rd <= '0';
decoded.use_imm <= '0';
decoded.branch_type <= BRANCH_NONE;
case (opcode) is
-- Load Upper Immediate
when c_op_lui =>
decoded.insn_type <= OP_LUI;
imm_type := IMM_U;
-- Add Upper Immediate to PC
when c_op_auipc =>
decoded.insn_type <= OP_AUIPC;
imm_type := IMM_U;
-- Jump And Link
when c_op_jal =>
decoded.insn_type <= OP_JAL;
decoded.alu_func <= ALU_ADD;
imm_type := IMM_J;
-- Jump And Link Register
when c_op_jalr =>
decoded.insn_type <= OP_JALR;
decoded.alu_func <= ALU_ADD;
imm_type := IMM_I;
decoded.rs1_rd <= '1';
-- Branch to target address, if condition is met
when c_op_branch =>
decoded.insn_type <= OP_BRANCH;
decoded.alu_func <= ALU_ADD;
imm_type := IMM_B;
decoded.rs1_rd <= '1';
decoded.rs2_rd <= '1';
case (funct3) is
when "000" => decoded.branch_type <= BEQ;
when "001" => decoded.branch_type <= BNE;
when "100" => decoded.branch_type <= BLT;
when "101" => decoded.branch_type <= BGE;
when "110" => decoded.branch_type <= BLTU;
when "111" => decoded.branch_type <= BGEU;
when others => null;
end case;
-- load data from memory
when c_op_load =>
decoded.insn_type <= OP_LOAD;
imm_type := IMM_I;
decoded.rs1_rd <= '1';
case (funct3) is
when "000" => decoded.load_type <= LB;
when "001" => decoded.load_type <= LH;
when "010" => decoded.load_type <= LW;
when "100" => decoded.load_type <= LBU;
when "101" => decoded.load_type <= LHU;
when others => null;
end case;
-- store data to memory
when c_op_store =>
decoded.insn_type <= OP_STORE;
imm_type := IMM_S;
decoded.rs1_rd <= '1';
decoded.rs2_rd <= '1';
case (funct3) is
when "000" => decoded.store_type <= SB;
when "001" => decoded.store_type <= SH;
when "010" => decoded.store_type <= SW;
when others => null;
end case;
-- perform computation with immediate value and a register
when c_op_imm =>
decoded.insn_type <= OP_ALU;
decoded.op2_src <= '1';
imm_type := IMM_I;
decoded.rs1_rd <= '1';
decoded.use_imm <= '1';
case (funct3) is
when "000" => decoded.alu_func <= ALU_ADD;
when "001" => decoded.alu_func <= ALU_SLL;
when "010" => decoded.alu_func <= ALU_SLT;
when "011" => decoded.alu_func <= ALU_SLTU;
when "100" => decoded.alu_func <= ALU_XOR;
when "110" => decoded.alu_func <= ALU_OR;
when "111" => decoded.alu_func <= ALU_AND;
when "101" =>
if (insn(30) = '1') then
decoded.alu_func <= ALU_SRA;
else
decoded.alu_func <= ALU_SRL;
end if;
when others => null;
end case;
-- perform computation with two register values
when c_op_reg =>
decoded.insn_type <= OP_ALU;
decoded.rs1_rd <= '1';
decoded.rs2_rd <= '1';
case (funct3) is
when "000" =>
if (insn(30) = '1') then
decoded.alu_func <= ALU_SUB;
else
decoded.alu_func <= ALU_ADD;
end if;
when "001" => decoded.alu_func <= ALU_SLL;
when "010" => decoded.alu_func <= ALU_SLT;
when "011" => decoded.alu_func <= ALU_SLTU;
when "100" => decoded.alu_func <= ALU_XOR;
when "101" =>
if (insn(30) = '1') then
decoded.alu_func <= ALU_SRA;
else
decoded.alu_func <= ALU_SRL;
end if;
when "110" => decoded.alu_func <= ALU_OR;
when "111" => decoded.alu_func <= ALU_AND;
when others => null;
end case;
-- @TODO other insnructions
--when c_op_misc_mem =>
-- insn_type <= OP_FENCE;
--when c_op_system =>
-- insn_type <= OP_SYSTEM;
when others =>
decoded.insn_type <= OP_ILLEGAL;
end case;
-- decode and sign-extend the immediate value
case imm_type is
when IMM_I =>
for i in 31 downto 11 loop
decoded.imm(i) <= insn(31);
end loop;
decoded.imm(10 downto 5) <= insn(30 downto 25);
decoded.imm(4 downto 1) <= insn(24 downto 21);
decoded.imm(0) <= insn(20);
when IMM_S =>
for i in 31 downto 11 loop
decoded.imm(i) <= insn(31);
end loop; -- i
decoded.imm(10 downto 5) <= insn(30 downto 25);
decoded.imm(4 downto 1) <= insn(11 downto 8);
decoded.imm(0) <= insn(7);
when IMM_B =>
for i in 31 downto 13 loop
decoded.imm(i) <= insn(31);
end loop; -- i
decoded.imm(12) <= insn(31);
decoded.imm(11) <= insn(7);
decoded.imm(10 downto 5) <= insn(30 downto 25);
decoded.imm(4 downto 1) <= insn(11 downto 8);
decoded.imm(0) <= '0';
when IMM_U =>
decoded.imm(31) <= insn(31);
decoded.imm(30 downto 20) <= insn(30 downto 20);
decoded.imm(19 downto 12) <= insn(19 downto 12);
decoded.imm(11 downto 0) <= (others => '0');
when IMM_J =>
for i in 31 downto 20 loop
decoded.imm(i) <= insn(31);
end loop; -- i
decoded.imm(19 downto 12) <= insn(19 downto 12);
decoded.imm(11) <= insn(20);
decoded.imm(10 downto 5) <= insn(30 downto 25);
decoded.imm(4 downto 1) <= insn(24 downto 21);
decoded.imm(0) <= '0';
when others => decoded.imm <= (others => '0');
end case;
end process decode_proc;
end architecture behavioral;
|
bsd-3-clause
|
b2b0b747ed466ead315c2ded913d233f
| 0.415868 | 4.267237 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.srcs/sources_1/ip/FrameBuffer/FrameBuffer_sim_netlist.vhdl
| 1 | 105,068 |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Thu May 5 01:21:06 2016
-- Host : Dries007-Arch running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/dries/Projects/Basys3/FPGA-Z/FPGA-Z.srcs/sources_1/ip/FrameBuffer/FrameBuffer_sim_netlist.vhdl
-- Design : FrameBuffer
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 2 downto 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end FrameBuffer_blk_mem_gen_mux;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_mux is
signal \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0\ : STD_LOGIC;
signal \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0\ : STD_LOGIC;
signal \no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1_n_0\ : STD_LOGIC;
signal sel_pipe : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1\ : label is "soft_lutpair0";
begin
\douta[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOADO(0),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0),
O => douta(0)
);
\douta[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOADO(1),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1),
O => douta(1)
);
\douta[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOADO(2),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2),
O => douta(2)
);
\douta[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOADO(3),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3),
O => douta(3)
);
\douta[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOADO(4),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4),
O => douta(4)
);
\douta[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOADO(5),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5),
O => douta(5)
);
\douta[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOADO(6),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6),
O => douta(6)
);
\douta[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOADO(7),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7),
O => douta(7)
);
\no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => addra(0),
I1 => ena,
I2 => sel_pipe(0),
O => \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0\
);
\no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => addra(1),
I1 => ena,
I2 => sel_pipe(1),
O => \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0\
);
\no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => addra(2),
I1 => ena,
I2 => sel_pipe(2),
O => \no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1_n_0\
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0\,
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0\,
Q => sel_pipe(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => \no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1_n_0\,
Q => sel_pipe(2),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_mux__parameterized0\ is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOBDO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 2 downto 0 );
clkb : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_mux__parameterized0\ : entity is "blk_mem_gen_mux";
end \FrameBuffer_blk_mem_gen_mux__parameterized0\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_mux__parameterized0\ is
signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\ : STD_LOGIC;
signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\ : STD_LOGIC;
signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[2]\ : STD_LOGIC;
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
\doutb[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(0),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0),
O => doutb(0)
);
\doutb[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(1),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1),
O => doutb(1)
);
\doutb[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(2),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2),
O => doutb(2)
);
\doutb[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(3),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3),
O => doutb(3)
);
\doutb[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(4),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4),
O => doutb(4)
);
\doutb[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(5),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5),
O => doutb(5)
);
\doutb[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(6),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6),
O => doutb(6)
);
\doutb[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(7),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7),
O => doutb(7)
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\,
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\,
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[2]\,
Q => sel_pipe_d1(2),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(0),
Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\,
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(1),
Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\,
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(2),
Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[2]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_prim_wrapper_init is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end FrameBuffer_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202B80",
INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_04 => X"802B202020202020202020202020202020202020202020202020202020202020",
INIT_05 => X"4646464646464646464646464646464646462020202020202020202020202B2B",
INIT_06 => X"2020202020202020202020505050505050505050505050505050505046464646",
INIT_07 => X"2041414120202020202020202020202020202047474747474747474747474747",
INIT_08 => X"5A20202020202020202020202020202020202020202020202020202020202020",
INIT_09 => X"2B2B2020202020202020202020205A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A",
INIT_0A => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A462020202020202020202020202020",
INIT_0B => X"47474720202020202020503A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A50463A3A3A",
INIT_0C => X"413A3A3A412020202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A3A",
INIT_0D => X"5A20202020202020202020202020202020202020202020202020202020202020",
INIT_0E => X"20202020202020202020202020205A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A",
INIT_0F => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A462020202020202020202020202020",
INIT_10 => X"3A3A3A474720202020503A3A3A3A3A5050505050503A3A3A3A3A3A50463A3A3A",
INIT_11 => X"3A3A3A3A3A4120202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A3A",
INIT_12 => X"5A20202020202020202020202020202020202020202020202020202020202041",
INIT_13 => X"20202020202020202020202020205A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A",
INIT_14 => X"3A4646464646464646463A3A3A3A3A3A46462020202020202020202020202020",
INIT_15 => X"3A3A3A3A3A472020503A3A3A3A3A502020202020503A3A3A3A3A5050463A3A3A",
INIT_16 => X"3A3A3A3A3A3A41202020202020202020202020473A3A3A3A4747474747474747",
INIT_17 => X"5A2020202020202020202020202020202020202020202020202020202020413A",
INIT_18 => X"2020202020202020202020202020205A3A3A3A3A3A5A5A5A5A5A5A5A5A3A3A3A",
INIT_19 => X"464620202020202020463A3A3A3A3A4620202020202020202020202020202020",
INIT_1A => X"473A3A3A3A3A4720503A3A3A3A3A502020202020503A3A3A3A50202046464646",
INIT_1B => X"3A3A3A3A3A3A3A41202020202020202020202047474747474720202020202020",
INIT_1C => X"5A20202020202020202020202020202020202020202020202020202020413A3A",
INIT_1D => X"202020202020202020202020202020205A3A3A3A3A3A5A20202020205A5A5A5A",
INIT_1E => X"202020202020202020463A3A3A3A3A4620202020202020202020202020202020",
INIT_1F => X"20473A3A3A3A3A47503A3A3A3A3A502020202020503A3A3A3A50202020202020",
INIT_20 => X"3A3A413A3A3A3A3A412020202020202020202020202020202020202020202020",
INIT_21 => X"20202020202020202020202020202020202020202020202020202020413A3A3A",
INIT_22 => X"2020202020202020202020202020202020205A3A3A3A3A3A5A20202020202020",
INIT_23 => X"4646464646464646463A3A3A3A3A3A4620202020202020202020202020202020",
INIT_24 => X"20473A3A3A3A3A4720503A3A3A3A3A5050505050503A3A3A3A50202020202046",
INIT_25 => X"3A4120413A3A3A3A3A4120202020202020202020202020202020202020202020",
INIT_26 => X"202020202020202020202020202020202020202020202020202020413A3A3A3A",
INIT_27 => X"202020202020202020202020202020202020205A3A3A3A3A3A5A202020202020",
INIT_28 => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A4620202020202020202020202020202020",
INIT_29 => X"20473A3A3A3A3A47202050503A3A3A3A3A3A3A3A3A3A3A3A3A50202020202046",
INIT_2A => X"41202020413A3A3A3A3A41202020202020202047474747474747474747202020",
INIT_2B => X"20202D2D2D2D2D2D2D2D2D2D2D2D2D2D2D202020202020202020413A3A3A3A3A",
INIT_2C => X"20202020202020202020202020202020202020205A3A3A3A3A3A5A2020202020",
INIT_2D => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A4620202020202020202020202020202020",
INIT_2E => X"20473A3A3A3A3A47202020205050505050505050503A3A3A3A50202020202046",
INIT_2F => X"2020202020413A3A3A3A3A4120202020202020473A3A3A3A3A3A3A3A47202020",
INIT_30 => X"20202D3A3A3A3A3A3A3A3A3A3A3A3A3A2D2020202020202020413A3A3A3A3A41",
INIT_31 => X"2020202020202020202020202020202020202020205A3A3A3A3A3A5A20202020",
INIT_32 => X"4646464646464646463A3A3A3A3A3A4620202020202020202020202020202020",
INIT_33 => X"20473A3A3A3A3A47202020202020202020202020503A3A3A3A50202020202046",
INIT_34 => X"414141414141413A3A3A3A3A41202020202020473A3A3A3A4747474747202020",
INIT_35 => X"20202D2D2D2D2D2D2D2D2D2D2D2D2D2D2D20202020202020413A3A3A3A3A4141",
INIT_36 => X"202020202020202020202020202020202020202020205A3A3A3A3A3A5A202020",
INIT_37 => X"202020202020202020463A3A3A3A3A4620202020202020202020202020202020",
INIT_38 => X"20473A3A3A3A3A47202020202020202020202020503A3A3A3A50202020202020",
INIT_39 => X"3A3A3A3A3A3A3A3A3A3A3A3A3A412020202020473A3A3A3A4720202020202020",
INIT_3A => X"2020202020202020202020202020202020202020202020413A3A3A3A3A3A3A3A",
INIT_3B => X"20202020202020202020202020202020202020202020205A3A3A3A3A3A5A2020",
INIT_3C => X"202020202020202020463A3A3A3A3A4620202020202020202020202020202020",
INIT_3D => X"473A3A3A3A3A4720202020202020202020202020503A3A3A3A50202020202020",
INIT_3E => X"4141414141414141413A3A3A3A3A4120202020473A3A3A3A4720202020202020",
INIT_3F => X"5A202020202020202020202020202020202020202020413A3A3A3A3A41414141",
INIT_40 => X"20202020202020202020202020205A5A5A5A5A20202020205A3A3A3A3A3A5A5A",
INIT_41 => X"2020202020202046463A3A3A3A3A3A3A46462020202020202020202020202020",
INIT_42 => X"3A3A3A3A3A4720202020202020202020202050503A3A3A3A3A3A505020202020",
INIT_43 => X"202020202020202020413A3A3A3A3A41202020473A3A3A3A4747474747474747",
INIT_44 => X"5A2020202020202020202020202020202020202020413A3A3A3A3A4120202020",
INIT_45 => X"20202020202020202020202020205A3A3A3A5A5A5A5A5A5A5A5A3A3A3A3A3A3A",
INIT_46 => X"2020202020202046463A3A3A3A3A3A3A3A462020202020202020202020202020",
INIT_47 => X"3A3A3A474720202020202020202020202020503A3A3A3A3A3A3A3A5020202020",
INIT_48 => X"20202020202020202020413A3A3A3A3A412020473A3A3A3A3A3A3A3A3A3A3A3A",
INIT_49 => X"5A20202020202020202020202020202020202020413A3A3A3A3A412020202020",
INIT_4A => X"20202020202020202020202020205A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A",
INIT_4B => X"2020202020202046463A3A3A3A3A3A3A3A462020202020202020202020202020",
INIT_4C => X"474747202020202020202020202020202020503A3A3A3A3A3A3A3A5020202020",
INIT_4D => X"2020202020202020202020413A3A3A3A3A4120473A3A3A4747473A3A3A3A3A3A",
INIT_4E => X"5A202020202020202020202020202020202020413A3A3A3A3A41202020202020",
INIT_4F => X"20202020202020202020202020205A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A",
INIT_50 => X"2020202020202046464646464646464646462020202020202020202020202020",
INIT_51 => X"2020202020202020202020202020202020205050505050505050505020202020",
INIT_52 => X"2020202020202020202020204141414141414147474747202020474747474747",
INIT_53 => X"5A20202020202020202020202020202020204141414141414120202020202020",
INIT_54 => X"20202020202020202020202020205A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A",
INIT_55 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_56 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_57 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_58 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_59 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5B => X"2041475046206E41202020202020202020202020202020202020202020202020",
INIT_5C => X"6D656C706D692033206E6F697372655620656E696863614D2D5A206465736162",
INIT_5D => X"20202020202020202020202020202020202020202020202E6E6F697461746E65",
INIT_5E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_60 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_61 => X"202E7475706E69207478657420726F662064616F6279656B2061206573552020",
INIT_62 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_63 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_64 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_65 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_66 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_67 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_68 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_69 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6B => X"20202E2E2E65756E69746E6F63206F742079656B20796E612073736572502020",
INIT_6C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_70 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_71 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_72 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_73 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_74 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_75 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_76 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_77 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_78 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_79 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[7]\(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\,
ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => addrb(12),
I1 => addrb(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_04 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_05 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_06 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_07 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_08 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_09 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_10 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_11 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_12 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_13 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_14 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_15 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_16 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_17 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_18 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_19 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_20 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_21 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_22 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_23 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_24 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_25 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_26 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_27 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_28 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_29 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_30 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_31 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_32 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_33 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_34 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_35 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_36 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_37 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_38 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_39 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_40 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_41 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_42 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_43 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_44 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_45 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_46 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_47 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_48 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_49 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_50 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_51 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_52 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_53 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_54 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_55 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_56 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_57 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_58 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_59 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_60 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_61 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_62 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_63 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_64 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_65 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_66 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_67 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_68 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_69 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_70 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_71 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_72 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_73 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_74 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_75 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_76 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_77 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_78 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_79 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[7]\(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0_n_0\,
ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0_n_0\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => addra(12),
I1 => ena,
I2 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => addrb(13),
I1 => addrb(12),
O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_33\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_35\ : STD_LOGIC;
signal ram_ena : STD_LOGIC;
signal ram_enb : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_04 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_05 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_06 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_07 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_08 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_09 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_10 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_11 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_12 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_13 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_14 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_15 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_16 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_17 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_18 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_19 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_20 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_21 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_22 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_23 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_24 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_25 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_26 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_27 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_28 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_29 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_30 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_31 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_32 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_33 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_34 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_35 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_36 => X"2020202020202020202020202020202020202020202020202020202020202B2B",
INIT_37 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_38 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_39 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3A => X"2B2B202020202020202020202020202020202020202020202020202020202020",
INIT_3B => X"2020202020202020202020202020202020202020202020202020202020202B80",
INIT_3C => X"6867697279706F43202020202020202020202020202020202020202020202020",
INIT_3D => X"656972642F2F3A707474683C2037303073656972442036313032202943282074",
INIT_3E => X"20202020202020202020202020202020202020202020203E74656E2E37303073",
INIT_3F => X"802B202020202020202020202020202020202020202020202020202020202020",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(13 downto 3) => addra(10 downto 0),
ADDRARDADDR(2 downto 0) => B"000",
ADDRBWRADDR(13 downto 3) => addrb(10 downto 0),
ADDRBWRADDR(2 downto 0) => B"000",
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DIADI(15 downto 8) => B"00000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(15 downto 8) => B"00000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 8),
DOBDO(7 downto 0) => DOBDO(7 downto 0),
DOPADOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_33\,
DOPBDOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1),
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_35\,
ENARDEN => ram_ena,
ENBWREN => ram_enb,
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 2) => B"00",
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => addra(12),
I1 => addra(11),
I2 => addra(13),
I3 => ena,
O => ram_ena
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addrb(11),
I1 => addrb(13),
I2 => addrb(12),
O => ram_enb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_prim_width is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end FrameBuffer_blk_mem_gen_prim_width;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.FrameBuffer_blk_mem_gen_prim_wrapper_init
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
\doutb[7]\(7 downto 0) => \doutb[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \FrameBuffer_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
\doutb[7]\(7 downto 0) => \doutb[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \FrameBuffer_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(7 downto 0) => DOBDO(7 downto 0),
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
ena => ena,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_generic_cstr is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end FrameBuffer_blk_mem_gen_generic_cstr;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_generic_cstr is
signal ram_douta : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ram_doutb : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \ramloop[1].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_9\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_9\ : STD_LOGIC;
begin
\has_mux_a.A\: entity work.FrameBuffer_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7) => \ramloop[1].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6) => \ramloop[1].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5) => \ramloop[1].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4) => \ramloop[1].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3) => \ramloop[1].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2) => \ramloop[1].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1) => \ramloop[1].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0) => \ramloop[1].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7 downto 0) => ram_douta(7 downto 0),
DOADO(7) => \ramloop[2].ram.r_n_0\,
DOADO(6) => \ramloop[2].ram.r_n_1\,
DOADO(5) => \ramloop[2].ram.r_n_2\,
DOADO(4) => \ramloop[2].ram.r_n_3\,
DOADO(3) => \ramloop[2].ram.r_n_4\,
DOADO(2) => \ramloop[2].ram.r_n_5\,
DOADO(1) => \ramloop[2].ram.r_n_6\,
DOADO(0) => \ramloop[2].ram.r_n_7\,
addra(2 downto 0) => addra(13 downto 11),
clka => clka,
douta(7 downto 0) => douta(7 downto 0),
ena => ena
);
\has_mux_b.B\: entity work.\FrameBuffer_blk_mem_gen_mux__parameterized0\
port map (
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7) => \ramloop[1].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6) => \ramloop[1].ram.r_n_9\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5) => \ramloop[1].ram.r_n_10\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4) => \ramloop[1].ram.r_n_11\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3) => \ramloop[1].ram.r_n_12\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2) => \ramloop[1].ram.r_n_13\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1) => \ramloop[1].ram.r_n_14\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0) => \ramloop[1].ram.r_n_15\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7 downto 0) => ram_doutb(7 downto 0),
DOBDO(7) => \ramloop[2].ram.r_n_8\,
DOBDO(6) => \ramloop[2].ram.r_n_9\,
DOBDO(5) => \ramloop[2].ram.r_n_10\,
DOBDO(4) => \ramloop[2].ram.r_n_11\,
DOBDO(3) => \ramloop[2].ram.r_n_12\,
DOBDO(2) => \ramloop[2].ram.r_n_13\,
DOBDO(1) => \ramloop[2].ram.r_n_14\,
DOBDO(0) => \ramloop[2].ram.r_n_15\,
addrb(2 downto 0) => addrb(13 downto 11),
clkb => clkb,
doutb(7 downto 0) => doutb(7 downto 0)
);
\ramloop[0].ram.r\: entity work.FrameBuffer_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
\douta[7]\(7 downto 0) => ram_douta(7 downto 0),
\doutb[7]\(7 downto 0) => ram_doutb(7 downto 0),
ena => ena,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[1].ram.r\: entity work.\FrameBuffer_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
\douta[7]\(7) => \ramloop[1].ram.r_n_0\,
\douta[7]\(6) => \ramloop[1].ram.r_n_1\,
\douta[7]\(5) => \ramloop[1].ram.r_n_2\,
\douta[7]\(4) => \ramloop[1].ram.r_n_3\,
\douta[7]\(3) => \ramloop[1].ram.r_n_4\,
\douta[7]\(2) => \ramloop[1].ram.r_n_5\,
\douta[7]\(1) => \ramloop[1].ram.r_n_6\,
\douta[7]\(0) => \ramloop[1].ram.r_n_7\,
\doutb[7]\(7) => \ramloop[1].ram.r_n_8\,
\doutb[7]\(6) => \ramloop[1].ram.r_n_9\,
\doutb[7]\(5) => \ramloop[1].ram.r_n_10\,
\doutb[7]\(4) => \ramloop[1].ram.r_n_11\,
\doutb[7]\(3) => \ramloop[1].ram.r_n_12\,
\doutb[7]\(2) => \ramloop[1].ram.r_n_13\,
\doutb[7]\(1) => \ramloop[1].ram.r_n_14\,
\doutb[7]\(0) => \ramloop[1].ram.r_n_15\,
ena => ena,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[2].ram.r\: entity work.\FrameBuffer_blk_mem_gen_prim_width__parameterized1\
port map (
DOADO(7) => \ramloop[2].ram.r_n_0\,
DOADO(6) => \ramloop[2].ram.r_n_1\,
DOADO(5) => \ramloop[2].ram.r_n_2\,
DOADO(4) => \ramloop[2].ram.r_n_3\,
DOADO(3) => \ramloop[2].ram.r_n_4\,
DOADO(2) => \ramloop[2].ram.r_n_5\,
DOADO(1) => \ramloop[2].ram.r_n_6\,
DOADO(0) => \ramloop[2].ram.r_n_7\,
DOBDO(7) => \ramloop[2].ram.r_n_8\,
DOBDO(6) => \ramloop[2].ram.r_n_9\,
DOBDO(5) => \ramloop[2].ram.r_n_10\,
DOBDO(4) => \ramloop[2].ram.r_n_11\,
DOBDO(3) => \ramloop[2].ram.r_n_12\,
DOBDO(2) => \ramloop[2].ram.r_n_13\,
DOBDO(1) => \ramloop[2].ram.r_n_14\,
DOBDO(0) => \ramloop[2].ram.r_n_15\,
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
ena => ena,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_top is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_top : entity is "blk_mem_gen_top";
end FrameBuffer_blk_mem_gen_top;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_top is
begin
\valid.cstr\: entity work.FrameBuffer_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
ena => ena,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_v8_3_1_synth is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_v8_3_1_synth : entity is "blk_mem_gen_v8_3_1_synth";
end FrameBuffer_blk_mem_gen_v8_3_1_synth;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_v8_3_1_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.FrameBuffer_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
ena => ena,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_v8_3_1 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "Estimated Power for IP : 4.61856 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "FrameBuffer.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "FrameBuffer.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "blk_mem_gen_v8_3_1";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "yes";
end FrameBuffer_blk_mem_gen_v8_3_1;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_v8_3_1 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.FrameBuffer_blk_mem_gen_v8_3_1_synth
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
ena => ena,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of FrameBuffer : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of FrameBuffer : entity is "FrameBuffer,blk_mem_gen_v8_3_1,{}";
attribute core_generation_info : string;
attribute core_generation_info of FrameBuffer : entity is "FrameBuffer,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=FrameBuffer.mif,C_INIT_FILE=FrameBuffer.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=10240,C_READ_DEPTH_A=10240,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=10240,C_READ_DEPTH_B=10240,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.61856 mW}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of FrameBuffer : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of FrameBuffer : entity is "blk_mem_gen_v8_3_1,Vivado 2015.4";
end FrameBuffer;
architecture STRUCTURE of FrameBuffer is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 4.61856 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "FrameBuffer.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "FrameBuffer.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 10240;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 10240;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 10240;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 10240;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.FrameBuffer_blk_mem_gen_v8_3_1
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(7 downto 0) => B"00000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
|
mit
|
0261830907d967c6d0fc3faf1c2fc19d
| 0.688526 | 3.411742 | false | false | false | false |
dries007/Basys3
|
VGA/VGA.srcs/sources_1/ip/dist_mem_gen_0/synth/dist_mem_gen_0.vhd
| 1 | 6,885 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dist_mem_gen_v8_0_9;
USE dist_mem_gen_v8_0_9.dist_mem_gen_v8_0_9;
ENTITY dist_mem_gen_0 IS
PORT (
a : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(1023 DOWNTO 0)
);
END dist_mem_gen_0;
ARCHITECTURE dist_mem_gen_0_arch OF dist_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dist_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT dist_mem_gen_v8_0_9 IS
GENERIC (
C_FAMILY : STRING;
C_ADDR_WIDTH : INTEGER;
C_DEFAULT_DATA : STRING;
C_DEPTH : INTEGER;
C_HAS_CLK : INTEGER;
C_HAS_D : INTEGER;
C_HAS_DPO : INTEGER;
C_HAS_DPRA : INTEGER;
C_HAS_I_CE : INTEGER;
C_HAS_QDPO : INTEGER;
C_HAS_QDPO_CE : INTEGER;
C_HAS_QDPO_CLK : INTEGER;
C_HAS_QDPO_RST : INTEGER;
C_HAS_QDPO_SRST : INTEGER;
C_HAS_QSPO : INTEGER;
C_HAS_QSPO_CE : INTEGER;
C_HAS_QSPO_RST : INTEGER;
C_HAS_QSPO_SRST : INTEGER;
C_HAS_SPO : INTEGER;
C_HAS_WE : INTEGER;
C_MEM_INIT_FILE : STRING;
C_ELABORATION_DIR : STRING;
C_MEM_TYPE : INTEGER;
C_PIPELINE_STAGES : INTEGER;
C_QCE_JOINED : INTEGER;
C_QUALIFY_WE : INTEGER;
C_READ_MIF : INTEGER;
C_REG_A_D_INPUTS : INTEGER;
C_REG_DPRA_INPUT : INTEGER;
C_SYNC_ENABLE : INTEGER;
C_WIDTH : INTEGER;
C_PARSER_TYPE : INTEGER
);
PORT (
a : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(1023 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
i_ce : IN STD_LOGIC;
qspo_ce : IN STD_LOGIC;
qdpo_ce : IN STD_LOGIC;
qdpo_clk : IN STD_LOGIC;
qspo_rst : IN STD_LOGIC;
qdpo_rst : IN STD_LOGIC;
qspo_srst : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(1023 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(1023 DOWNTO 0);
qspo : OUT STD_LOGIC_VECTOR(1023 DOWNTO 0);
qdpo : OUT STD_LOGIC_VECTOR(1023 DOWNTO 0)
);
END COMPONENT dist_mem_gen_v8_0_9;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF dist_mem_gen_0_arch: ARCHITECTURE IS "dist_mem_gen_v8_0_9,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF dist_mem_gen_0_arch : ARCHITECTURE IS "dist_mem_gen_0,dist_mem_gen_v8_0_9,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF dist_mem_gen_0_arch: ARCHITECTURE IS "dist_mem_gen_0,dist_mem_gen_v8_0_9,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_ADDR_WIDTH=12,C_DEFAULT_DATA=0,C_DEPTH=4096,C_HAS_CLK=0,C_HAS_D=0,C_HAS_DPO=0,C_HAS_DPRA=0,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=0,C_MEM_INIT_FILE=dist_mem_gen_0.mif,C_ELABORATION_DIR=./,C_MEM_TYPE=0,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=1,C_REG_A_D_INPUTS=0,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=1024,C_PARSER_TYPE=1}";
BEGIN
U0 : dist_mem_gen_v8_0_9
GENERIC MAP (
C_FAMILY => "artix7",
C_ADDR_WIDTH => 12,
C_DEFAULT_DATA => "0",
C_DEPTH => 4096,
C_HAS_CLK => 0,
C_HAS_D => 0,
C_HAS_DPO => 0,
C_HAS_DPRA => 0,
C_HAS_I_CE => 0,
C_HAS_QDPO => 0,
C_HAS_QDPO_CE => 0,
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_RST => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_QSPO => 0,
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QSPO_SRST => 0,
C_HAS_SPO => 1,
C_HAS_WE => 0,
C_MEM_INIT_FILE => "dist_mem_gen_0.mif",
C_ELABORATION_DIR => "./",
C_MEM_TYPE => 0,
C_PIPELINE_STAGES => 0,
C_QCE_JOINED => 0,
C_QUALIFY_WE => 0,
C_READ_MIF => 1,
C_REG_A_D_INPUTS => 0,
C_REG_DPRA_INPUT => 0,
C_SYNC_ENABLE => 1,
C_WIDTH => 1024,
C_PARSER_TYPE => 1
)
PORT MAP (
a => a,
d => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1024)),
dpra => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
clk => '0',
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qspo_srst => '0',
qdpo_srst => '0',
spo => spo
);
END dist_mem_gen_0_arch;
|
mit
|
a6597bf6e60502257f2ab63eb9ce2306
| 0.644009 | 3.129545 | false | false | false | false |
luebbers/reconos
|
support/templates/bfmsim_xps_osif_v2_01_a/simulation/behavioral/plb_bus_wrapper.vhd
| 1 | 14,698 |
-------------------------------------------------------------------------------
-- plb_bus_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_00_a;
use plb_v46_v1_00_a.all;
entity plb_bus_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 0);
MPLB_Rst : out std_logic_vector(0 to 1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 63);
M_UABus : in std_logic_vector(0 to 63);
M_BE : in std_logic_vector(0 to 31);
M_RNW : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_busLock : in std_logic_vector(0 to 1);
M_TAttribute : in std_logic_vector(0 to 31);
M_lockErr : in std_logic_vector(0 to 1);
M_MSize : in std_logic_vector(0 to 3);
M_priority : in std_logic_vector(0 to 3);
M_rdBurst : in std_logic_vector(0 to 1);
M_request : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_wrBurst : in std_logic_vector(0 to 1);
M_wrDBus : in std_logic_vector(0 to 255);
Sl_addrAck : in std_logic_vector(0 to 0);
Sl_MRdErr : in std_logic_vector(0 to 1);
Sl_MWrErr : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 0);
Sl_rdComp : in std_logic_vector(0 to 0);
Sl_rdDAck : in std_logic_vector(0 to 0);
Sl_rdDBus : in std_logic_vector(0 to 127);
Sl_rdWdAddr : in std_logic_vector(0 to 3);
Sl_rearbitrate : in std_logic_vector(0 to 0);
Sl_SSize : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 0);
Sl_wrBTerm : in std_logic_vector(0 to 0);
Sl_wrComp : in std_logic_vector(0 to 0);
Sl_wrDAck : in std_logic_vector(0 to 0);
Sl_MIRQ : in std_logic_vector(0 to 1);
PLB_MIRQ : out std_logic_vector(0 to 1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 15);
PLB_MAddrAck : out std_logic_vector(0 to 1);
PLB_MTimeout : out std_logic_vector(0 to 1);
PLB_MBusy : out std_logic_vector(0 to 1);
PLB_MRdErr : out std_logic_vector(0 to 1);
PLB_MWrErr : out std_logic_vector(0 to 1);
PLB_MRdBTerm : out std_logic_vector(0 to 1);
PLB_MRdDAck : out std_logic_vector(0 to 1);
PLB_MRdDBus : out std_logic_vector(0 to 255);
PLB_MRdWdAddr : out std_logic_vector(0 to 7);
PLB_MRearbitrate : out std_logic_vector(0 to 1);
PLB_MWrBTerm : out std_logic_vector(0 to 1);
PLB_MWrDAck : out std_logic_vector(0 to 1);
PLB_MSSize : out std_logic_vector(0 to 3);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 0);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 127);
PLB_wrPrim : out std_logic_vector(0 to 0);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 1);
PLB_SMWrErr : out std_logic_vector(0 to 1);
PLB_SMBusy : out std_logic_vector(0 to 1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 127);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
PLB2OPB_rearb : in std_logic_vector(0 to 0);
Bus_Error_Det : out std_logic
);
end plb_bus_wrapper;
architecture STRUCTURE of plb_bus_wrapper is
component plb_v46 is
generic (
C_PLBV46_NUM_MASTERS : integer;
C_PLBV46_NUM_SLAVES : integer;
C_PLBV46_MID_WIDTH : integer;
C_PLBV46_AWIDTH : integer;
C_PLBV46_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_NUM_CLK_PLB2OPB_REARB : integer;
C_ADDR_PIPELINING_TYPE : integer;
C_FAMILY : string;
C_P2P : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1);
M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 );
Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1);
PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
PLB2OPB_rearb : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Bus_Error_Det : out std_logic
);
end component;
begin
plb_bus : plb_v46
generic map (
C_PLBV46_NUM_MASTERS => 2,
C_PLBV46_NUM_SLAVES => 1,
C_PLBV46_MID_WIDTH => 1,
C_PLBV46_AWIDTH => 32,
C_PLBV46_DWIDTH => 128,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 0,
C_IRQ_ACTIVE => '1',
C_NUM_CLK_PLB2OPB_REARB => 5,
C_ADDR_PIPELINING_TYPE => 1,
C_FAMILY => "virtex5",
C_P2P => 0
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
SPLB_Rst => SPLB_Rst,
MPLB_Rst => MPLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_UABus => M_UABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
Sl_MIRQ => Sl_MIRQ,
PLB_MIRQ => PLB_MIRQ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_rdPendPri => PLB_rdPendPri,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
PLB2OPB_rearb => PLB2OPB_rearb,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
|
gpl-3.0
|
17d15fb72708f9ccd3c42245b817b2fa
| 0.610763 | 3.031766 | false | false | false | false |
luebbers/reconos
|
demos/particle_filter_framework/hw/src/user_processes/uf_prediction.vhd
| 1 | 16,604 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : P R E D I C T I O N
--
--
-- The particles are loaded into the local RAM by the Framework.
-- The 8kb local RAM is filled with as many particles as possible.
-- There will not be any space between the particles.
--
-- The user of the framework knows how a particle is defined and
-- he defines here, how the next state is going to be predicted.
-- In the end the user has to overwrite every particle with the
-- sampled particle.
--
-- If this has be done for every particle, the finshed signal
-- has to be set to '1'. A new run of the prediction will be
-- started if new particles are loaded to the local RAM and
-- the signal particles_loaded is equal to '1'.
--
-- Because this function depends on parameter, additional
-- parameter can be given to the framework, which copies
-- them into the first 128 byte of the local RAM.
--
------------------------------------------------------------------------------------
entity uf_prediction is
generic (
C_TASK_BURST_AWIDTH : integer := 11;
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- start signal for the prediction user process
particles_loaded : in std_logic;
-- number of particles in local RAM
number_of_particles : in integer;
-- size of one particle
particle_size : in integer;
-- if every particle is sampled, this signal has to be set to '1'
finished : out std_logic
);
end uf_prediction;
architecture Behavioral of uf_prediction is
component pseudo_random is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
enable : in STD_LOGIC;
load : in STD_LOGIC;
seed : in STD_LOGIC_VECTOR(31 downto 0);
pseudoR : out STD_LOGIC_VECTOR(31 downto 0));
end component;
-- GRANULARITY
constant GRANULARITY :integer := 16384;
-- factors for prediction fucntion
constant A1: integer := 2;
constant A2: integer := -1;
constant B0: integer := 1;
-- local RAM read/write address
signal local_ram_address : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
signal particle_start_address : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- particle counter
signal counter : integer := 0;
-- signals for new values
signal x_new : integer := 0;
signal y_new : integer := 0;
signal s_new : integer := 0;
-- particle data
signal x : integer := 0;
signal y : integer := 0;
signal s : integer := 0;
signal x_old : integer := 0;
signal y_old : integer := 0;
signal s_old : integer := 0;
signal x0 : integer := -1;
signal y0 : integer := -1;
-- parameters
signal SIZE_X : integer := 480;
signal SIZE_Y : integer := 360;
signal TRANS_X_STD : integer := 16384;
signal TRANS_Y_STD : integer := 8192;
signal TRANS_S_STD : integer := 16;
-- temporary signals
signal tmp1 : integer := 0;
signal tmp2 : integer := 0;
signal tmp3 : integer := 0;
signal tmp4 : integer := 0;
signal tmp5 : integer := 0;
signal tmp6 : integer := 0;
-- states
type t_state is (STATE_INIT,
STATE_LOAD_PARAMETER_1, STATE_LOAD_PARAMETER_2, STATE_LOAD_SIZE_X,
STATE_LOAD_SIZE_Y, STATE_LOAD_TRANS_X_STD, STATE_LOAD_TRANS_Y_STD,
STATE_LOAD_TRANS_S_STD, STATE_SAMPLING, STATE_LOAD_PARTICLE_DECISION,
STATE_LOAD_PARTICLE_1, STATE_LOAD_PARTICLE_2,
STATE_LOAD_X, STATE_LOAD_Y, STATE_LOAD_S,
STATE_LOAD_XP, STATE_LOAD_YP, STATE_LOAD_YP_2, STATE_LOAD_SP,
STATE_LOAD_SP_2, STATE_LOAD_X0, STATE_LOAD_Y0,
STATE_CALCULATE_NEW_DATA_1, STATE_CALCULATE_NEW_DATA_2, STATE_CALCULATE_NEW_DATA_3,
STATE_CALCULATE_NEW_DATA_4, STATE_CALCULATE_NEW_DATA_5, STATE_CALCULATE_NEW_DATA_6,
STATE_CALCULATE_NEW_DATA_7, STATE_WRITE_X, STATE_WRITE_Y, STATE_WRITE_S,
STATE_WRITE_XP, STATE_WRITE_YP, STATE_WRITE_SP,
STATE_FINISH);
-- current state
signal state : t_state := STATE_INIT;
-- needed for pseudo random entity
signal enable_pseudo : std_logic := '0';
signal load : std_logic := '0';
signal seed : std_logic_vector(31 downto 0) := (others => '0');
signal pseudoR : std_logic_vector(31 downto 0) := (others => '0');
-- pseudo number as integer;
signal pseudo : integer := 0;
begin
pseudo_r : pseudo_random
port map (reset=>reset, clk=>clk, enable=>enable_pseudo, load=>load, seed=>seed, pseudoR=>pseudoR);
-- burst ram interface
o_RAMClk <= clk;
state_proc : process(clk, reset)
begin
if (reset = '1') then
seed <= X"7A3E0426";
load <= '1';
enable_pseudo <= '1';
state <= STATE_INIT;
finished <= '0';
x0 <= -1;
elsif rising_edge(clk) then
enable_pseudo <= enable;
load <= '0';
if init = '1' then
state <= STATE_INIT;
finished <= '0';
o_RAMData <= (others=>'0');
o_RAMWE <= '0';
o_RAMAddr <= (others => '0');
elsif enable = '1' then
case state is
--! init data
when STATE_INIT =>
local_ram_address <= (others => '0');
counter <= 0;
finished <= '0';
o_RAMWE <= '0';
if (particles_loaded = '1') then
-- TODO: C H A N G E !!! (3 of 3)
-- CHANGE BACK !!! (2 of 2)
state <= STATE_LOAD_PARAMETER_1;
--state <= STATE_SAMPLING;
end if;
--! load parameter 1/2
when STATE_LOAD_PARAMETER_1 =>
o_RAMWE <= '0';
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_PARAMETER_2;
--! load parameter 2/2
when STATE_LOAD_PARAMETER_2 =>
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_SIZE_X;
--! load parameter SIZE_X
when STATE_LOAD_SIZE_X =>
SIZE_X <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_SIZE_Y;
--! load parameter SIZE_Y
when STATE_LOAD_SIZE_Y =>
SIZE_Y <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_TRANS_X_STD;
--! load parameter TRANS_X_STD
when STATE_LOAD_TRANS_X_STD =>
TRANS_X_STD <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_TRANS_Y_STD;
--! load parameter TRANS_Y_STD
when STATE_LOAD_TRANS_Y_STD =>
TRANS_Y_STD <= TO_INTEGER(SIGNED(i_RAMData));
state <= STATE_LOAD_TRANS_S_STD;
--! load parameter TRANS_S_STD
when STATE_LOAD_TRANS_S_STD =>
TRANS_S_STD <= TO_INTEGER(SIGNED(i_RAMData));
state <= STATE_SAMPLING;
when STATE_SAMPLING =>
-- first 32 are saved for parameter, the 33th is the first weight
-- => 33 - the first x value
local_ram_address <= "00000100001";
particle_start_address <= "00000100001";
o_RAMWE <= '0';
finished <= '0';
counter <= 0;
--x0 <= -1;
state <= STATE_LOAD_PARTICLE_DECISION;
--! decision if another particle has to be sampled
when STATE_LOAD_PARTICLE_DECISION =>
o_RAMWE <= '0';
if (counter < number_of_particles) then
state <= STATE_LOAD_PARTICLE_1;
local_ram_address <= particle_start_address;
else
state <= STATE_FINISH;
end if;
--! load particle data 1/2
when STATE_LOAD_PARTICLE_1 =>
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_PARTICLE_2;
--! load particle data 2/2
when STATE_LOAD_PARTICLE_2 =>
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_X;
--! load particle data: x
when STATE_LOAD_X =>
x <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_Y;
--! load particle data: y
when STATE_LOAD_Y =>
y <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_S;
--! load particle data: s
when STATE_LOAD_S =>
s <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
pseudo <= TO_INTEGER(SIGNED(pseudoR));
state <= STATE_LOAD_XP;
--! load particle data: xp
when STATE_LOAD_XP =>
x_old <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
pseudo <= pseudo / 16;
state <= STATE_LOAD_YP;
--! load particle data: yp
when STATE_LOAD_YP =>
y_old <= TO_INTEGER(SIGNED(i_RAMData));
pseudo <= TO_INTEGER(SIGNED(pseudoR));
--tmp2 <= pseudo mod 16384;
----tmp2 <= pseudo mod 65536;
tmp2 <= pseudo mod 32768;
state <= STATE_LOAD_YP_2;
--! load particle data: yp
when STATE_LOAD_YP_2 =>
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
--tmp2 <= tmp2 - 8192;
----tmp2 <= tmp2 - 32768;
tmp2 <= tmp2 - 16384;
state <= STATE_LOAD_SP;
--! load particle data: sp
when STATE_LOAD_SP =>
s_old <= TO_INTEGER(SIGNED(i_RAMData));
pseudo <= TO_INTEGER(SIGNED(pseudoR));
----tmp4 <= pseudo mod 8192;
tmp4 <= pseudo mod 32768;
--tmp4 <= pseudo mod 16384;
state <= STATE_LOAD_SP_2;
--! load particle data: sp
when STATE_LOAD_SP_2 =>
----tmp4 <= tmp4 - 4096;
tmp4 <= tmp4 - 16384;
--tmp4 <= tmp4 - 8192;
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
if (x0 > -1 ) then
-- x0, y0 loaded before
state <= STATE_CALCULATE_NEW_DATA_1;
else
-- x0, y0 not loaded yet
state <= STATE_LOAD_X0;
end if;
--! load particle data: x0
when STATE_LOAD_X0 =>
x0 <= TO_INTEGER(SIGNED(i_RAMData));
state <= STATE_LOAD_Y0;
--! load particle data: y0
when STATE_LOAD_Y0 =>
y0 <= TO_INTEGER(SIGNED(i_RAMData));
state <= STATE_CALCULATE_NEW_DATA_1;
--! calculate new data (1/7)
--
-- x_new = A1 * (x - x0) + A2 * (x_old - x0)
-- + B0 * pseudo_gaussian (TRANS_X_STD) + p->x0;
--
-- y_new and s_new are calculated in a similar way
-- this equation is splitted up into four states
--
-- A 6th and 7th state is used for correction
--
when STATE_CALCULATE_NEW_DATA_1 =>
-- calculate new x
x_new <= x - x0;
tmp1 <= x_old - x0;
--tmp2 <= (pseudo mod 16384) - 8192; -- calculated with different pseudonumber
-- calcualte new y
y_new <= y - y0;
tmp3 <= y_old - y0;
--tmp4 <= (pseudo mod 8192) - 4096; -- calculated with different pseudonumber
-- calculate new s
s_new <= s - GRANULARITY;
tmp5 <= s_old - GRANULARITY;
tmp6 <= pseudo mod 16;
--tmp6 <= pseudo mod 64;
state <= STATE_CALCULATE_NEW_DATA_2;
--! calculate new data (2/7)
when STATE_CALCULATE_NEW_DATA_2 =>
tmp6 <= tmp6 - 8;
--tmp6 <= tmp6 - 32;
state <= STATE_CALCULATE_NEW_DATA_3;
--! calculate new data (3/7)
when STATE_CALCULATE_NEW_DATA_3 =>
-- calculate new x
x_new <= A1 * x_new;
tmp1 <= A2 * tmp1;
tmp2 <= - B0 * tmp2;
-- calculate new y
y_new <= A1 * y_new;
tmp3 <= A2 * tmp3;
tmp4 <= B0 * tmp4;
-- calculate new s
s_new <= A1 * s_new;
tmp5 <= A2 * tmp5;
tmp6 <= B0 * tmp6;
state <= STATE_CALCULATE_NEW_DATA_4;
--! calculate new data (4/7)
when STATE_CALCULATE_NEW_DATA_4 =>
-- calcualte new x
x_new <= x_new + tmp1;
tmp2 <= tmp2 + x0;
-- calcualte new y
y_new <= y_new + tmp3;
tmp4 <= tmp4 + y0;
-- calcualte new s
s_new <= s_new + tmp5;
tmp6 <= tmp6 + GRANULARITY;
state <= STATE_CALCULATE_NEW_DATA_5;
--! calculate new data (5/7)
when STATE_CALCULATE_NEW_DATA_5 =>
-- calculate new x
x_new <= x_new + tmp2;
-- calculate new y
y_new <= y_new + tmp4;
-- calculate new s
s_new <= s_new + tmp6;
state <= STATE_CALCULATE_NEW_DATA_6;
--! calculate new data (6/7): correction
when STATE_CALCULATE_NEW_DATA_6 =>
-- correct new x
if (x_new < 0) then
x_new <= 0;
elsif ((SIZE_X * GRANULARITY) <= x_new) then
x_new <= SIZE_X * GRANULARITY;
end if;
-- correct new y
if (y_new < 0) then
y_new <= 0;
elsif ((SIZE_Y * GRANULARITY) <= y_new) then
y_new <= SIZE_Y * GRANULARITY;
end if;
-- correct new s
if (s_new < 0) then
s_new <= 0;
elsif (s_new <= (GRANULARITY / 8)) then
s_new <= GRANULARITY / 8;
elsif ((8*GRANULARITY) <= s_new) then
s_new <= 8 * GRANULARITY;
end if;
state <= STATE_CALCULATE_NEW_DATA_7;
--! calculate new data (7/7): correction
when STATE_CALCULATE_NEW_DATA_7 =>
-- correct new x
if (x_new = (SIZE_X * GRANULARITY)) then
x_new <= x_new - 1;
end if;
-- correct new y
if (y_new = (SIZE_Y * GRANULARITY)) then
y_new <= y_new - 1;
end if;
state <= STATE_WRITE_X;
--! write sampled particle: x
when STATE_WRITE_X =>
o_RAMWE <= '1';
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(x_new, C_TASK_BURST_DWIDTH));
o_RAMAddr <= particle_start_address;
state <= STATE_WRITE_Y;
--! write sampled particle: y
when STATE_WRITE_Y =>
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(y_new, C_TASK_BURST_DWIDTH));
o_RAMAddr <= particle_start_address + 1;
state <= STATE_WRITE_S;
--! write sampled particle: s
when STATE_WRITE_S =>
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(s_new, C_TASK_BURST_DWIDTH));
o_RAMAddr <= particle_start_address + 2;
state <= STATE_WRITE_XP;
--! write sampled particle: xp
when STATE_WRITE_XP =>
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(x, C_TASK_BURST_DWIDTH));
o_RAMAddr <= particle_start_address + 3;
state <= STATE_WRITE_YP;
--! write sampled particle: yp
when STATE_WRITE_YP =>
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(y, C_TASK_BURST_DWIDTH));
o_RAMAddr <= particle_start_address + 4;
state <= STATE_WRITE_SP;
--! write sampled particle: sp
when STATE_WRITE_SP =>
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(s, C_TASK_BURST_DWIDTH));
o_RAMAddr <= particle_start_address + 5;
particle_start_address <= particle_start_address + particle_size;
counter <= counter + 1;
state <= STATE_LOAD_PARTICLE_DECISION;
-- write finished signal
when STATE_FINISH =>
o_RAMWE <= '0';
finished <= '1';
if (particles_loaded = '1') then
state <= STATE_SAMPLING;
end if;
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
da13c23089d791ceab937fa8a59cc2bf
| 0.54776 | 3.439818 | false | false | false | false |
five-elephants/hw-neural-sampling
|
input_sum.vhdl
| 1 | 954 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sampling.all;
entity input_sum is
generic (
num_samplers : integer := 1
);
port (
clk, reset : in std_ulogic;
phase : in phase_t;
state : in state_array_t(1 to num_samplers);
weights : in weight_array_t(1 to num_samplers);
sum : out signed(sum_in_size(num_samplers)-1 downto 0)
);
end input_sum;
architecture rtl of input_sum is
subtype sum_in_t is
signed(sum_in_size(num_samplers)-1 downto 0);
begin
------------------------------------------------------------
summation: process ( state, weights )
variable acc : sum_in_t;
begin
acc := to_signed(0, acc'length);
for i in 1 to num_samplers loop
if state(i) = '1' then
acc := acc + resize(weights(i), acc'length);
end if;
end loop;
sum <= acc;
end process;
------------------------------------------------------------
end rtl;
|
apache-2.0
|
6d13c7dd9eae73120ce2094845c32f35
| 0.544025 | 3.559701 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/thermal_monitor_v1_03_a/hdl/vhdl/thermal_monitor.vhd
| 1 | 21,806 |
------------------------------------------------------------------------------
-- thermal_monitor.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: thermal_monitor.vhd
-- Version: 1.03.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Fri Feb 11 10:21:47 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library thermal_monitor_v1_03_a;
use thermal_monitor_v1_03_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity thermal_monitor is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- DO NOT EDIT ABOVE THIS LINE ---------------------
sample_clk : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of sample_clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity thermal_monitor;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of thermal_monitor is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 144;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity thermal_monitor_v1_03_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
sample_clk => sample_clk
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
gpl-3.0
|
e5736bcea3b3d448749c1adcf4651b05
| 0.449418 | 4.498865 | false | false | false | false |
db-electronics/SMSFlashCart
|
src/SMSMapper.vhd
| 1 | 5,520 |
--*************************************************************
-- db Mapper
-- Copyright 2015 Rene Richard
-- DEVICE : EPM3064ATC100-10
--*************************************************************
--
-- Description:
-- This is a VHDL implementation of an SMS Sega Mapper
-- it is intended to be used on the db Electronics SMS Homebrew Carts
-- Supported Flash Memory Configurations:
-- 2Mbit (1x 2Mbit)
-- 4Mbit (1x 4Mbit)
-- 8Mbit (1x 4Mbit)
-- Support RAM Configurations
-- 32KB
--
-- for a complete description of SMS Mappers, go to http://www.smspower.org/Development/Mappers
--*************************************************************
--
-- RAM and Misc. Register
-- $FFFC
-- bit 7: ROM Write Enable
-- when '1' writes to ROM (i.e. Flash) are enabled
-- when '0' writes to mapper registers are enabled
-- bit 3: RAM Enable
-- when '1' RAM will be mapped into slot 2, overriding any ROM banking via $ffff
-- when '0' ROM banking is effective
-- bit 2: RAM Bank Select
-- when '1' maps the upper 16KB of RAM into slot 2
-- when '0' maps the lower 16KB of RAM into slot 2
--*************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SMSMapper is
generic(
SLOT0ENABLE : boolean := true;
SLOT1ENABLE : boolean := true
);
port (
--input from sms
ADDR_p : in std_logic_vector(15 downto 0);
DATA_p : in std_logic_vector(7 downto 0);
nRST_p : in std_logic;
nWR_p : in std_logic;
nCE_p : in std_logic;
--output to ROM
nROMWE_p : out std_logic;
nROMCE_p : out std_logic;
ROMADDR1914_p : out std_logic_vector(5 downto 0);
--output to serial EEPROM
EE_CS_p : out std_logic;
EE_SO_p : out std_logic;
EE_SI_p : out std_logic;
EE_SCK_p : out std_logic;
--output to SRAM
nSRAMCE_p : out std_logic;
nSRAMWE_p : out std_logic;
SRAMADDR14_p : out std_logic
);
end entity;
architecture SMSMapper_a of SMSMapper is
--internal data and address signals for easy write back if ever needed
signal datain_s : std_logic_vector(7 downto 0);
signal addr_s : std_logic_vector(15 downto 0);
--Mapper slot registers, fitter will optimize any unused bits
signal romSlot1_s : std_logic_vector(5 downto 0);
signal romSlot2_s : std_logic_vector(5 downto 0);
signal mapAddr_s : std_logic_vector(5 downto 0);
--internal rom signals
signal romWrEn_s : std_logic;
signal nRomCE_s : std_logic;
signal nRomWE_s : std_logic;
--RAM mapping signals
signal ramEn_s : std_logic;
signal ramBank_s : std_logic;
begin
--internal data and address signals
addr_s <= ADDR_p;
datain_s <= DATA_p;
--output mapping to ROM and RAM
SRAMADDR14_p <= ramBank_s;
--high order address bits and WE and CE must be open-drain to meet 5V requirements
-- 1K pull-up on each of these lines
ROMADDR1914_p(0) <= '0' when mapAddr_s(0) = '0' else 'Z';
ROMADDR1914_p(1) <= '0' when mapAddr_s(1) = '0' else 'Z';
ROMADDR1914_p(2) <= '0' when mapAddr_s(2) = '0' else 'Z';
ROMADDR1914_p(3) <= '0' when mapAddr_s(3) = '0' else 'Z';
ROMADDR1914_p(4) <= '0' when mapAddr_s(4) = '0' else 'Z';
ROMADDR1914_p(5) <= '0' when mapAddr_s(5) = '0' else 'Z';
--ROM Write Gating with bit7 of $FFFC
nRomWE_s <= nWR_p when romWrEn_s = '1' else '1';
nROMWE_p <= '0' when nRomWE_s = '0' else 'Z';
nROMCE_p <= '0' when nRomCE_s = '0' else 'Z';
--default values for now, todo later
EE_CS_p <= '1';
EE_SO_p <= '1';
EE_SI_p <= '1';
EE_SCK_p <= '1';
--RAM mapping and miscellaneous functions register
ram0: process( nRST_p, nWR_p, nCE_p, addr_s )
begin
if nRST_p = '0' then
romWrEn_s <= '0';
ramEn_s <= '0';
ramBank_s <= '0';
--nWR rises before address and mreq on Z80
elsif falling_edge(nWR_p) then
if addr_s = x"FFFC" and nCE_p = '0' then
romWrEn_s <= datain_s(7);
ramEn_s <= datain_s(3);
ramBank_s <= datain_s(2);
end if;
end if;
end process;
--mapper registers
mappers: process( nRST_p, nWR_p, nCE_p, addr_s)
begin
if nRST_p = '0' then
romSlot1_s <= "000001";
romSlot2_s <= "000010";
--nWR rises before address and mreq on Z80
elsif falling_edge(nWR_p) then
if nCE_p = '0' then
case addr_s is
when x"FFFE" =>
romSlot1_s <= datain_s(5 downto 0);
when x"FFFF" =>
romSlot2_s <= datain_s(5 downto 0);
when others =>
null;
end case;
end if;
end if;
end process;
--banking select
--only looks at address, this way the address setup and hold times can be respected
banking: process( addr_s )
begin
mapAddr_s <= (others=>'0');
case addr_s(15 downto 14) is
when "01" =>
mapAddr_s <= romSlot1_s(5 downto 0);
when "10" =>
mapAddr_s <= romSlot2_s(5 downto 0);
when others =>
mapAddr_s <= (others=>'0');
end case;
end process;
--drive chip select lines
chipSelect: process( addr_s, ramEn_s, nCE_p )
begin
nSRAMWE_p <= '1';
nSRAMCE_p <= '1';
nRomCE_s <= '1';
case addr_s(15 downto 14) is
--slot 0
when "00" =>
nRomCE_s <= nCE_p;
--slot 1
when "01" =>
nRomCE_s <= nCE_p;
--slot 2
when "10" =>
--RAM mapping has priority in Slot 2
if ramEn_s = '1' then
nSRAMCE_p <= nCE_p;
nSRAMWE_p <= nWR_p;
else
--select upper or lower ROM based on A19
nRomCE_s <= nCE_p;
end if;
when others =>
--don't drive anything in slot 4
nSRAMWE_p <= '1';
nSRAMCE_p <= '1';
nRomCE_s <= '1';
end case;
end process;
end SMSMapper_a;
|
gpl-2.0
|
5820ddbfd970822c1f932f2db9eff230
| 0.590036 | 2.684825 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/sSegDisplay.vhd
| 1 | 3,011 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Mircea Dabacan
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 13:13:49 12/16/2010
-- Design Name:
-- Module Name: sSegDisplay - Behavioral
-- Description:
-- This module represents the seven-segment display multiplexer
-- Because the pattern to be displayed does not contain numerical or
-- alphabetical characters representable on a seven-segment display,
-- the incoming data is NOT encoded to seven-segment code,
-- instead the incoming data is sent directly to the cathodes,
-- according to the diagram shown below
-- Segment encoding
-- 0
-- ---
-- 5 | | 1
-- --- <- 6
-- 4 | | 2
-- ---
-- 3
-- Decimal Point = 7
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all; -- add to do arithmetic operations
use IEEE.std_logic_arith.all; -- add to do arithmetic operations
entity sSegDisplay is
Port(ck : in std_logic; -- 100MHz system clock
number : in std_logic_vector (63 downto 0); -- eight digit number to be displayed
seg : out std_logic_vector (7 downto 0); -- display cathodes
an : out std_logic_vector (7 downto 0)); -- display anodes (active-low, due to transistor complementing)
end sSegDisplay;
architecture Behavioral of sSegDisplay is
signal cnt: std_logic_vector(19 downto 0); -- divider counter for ~95.3Hz refresh rate (with 100MHz main clock)
signal hex: std_logic_vector(7 downto 0); -- hexadecimal digit
signal intAn: std_logic_vector(7 downto 0); -- internal signal representing anode data
begin
-- Assign outputs
an <= intAn;
seg <= hex;
clockDivider: process(ck)
begin
if ck'event and ck = '1' then
cnt <= cnt + '1';
end if;
end process clockDivider;
-- Anode Select
with cnt(19 downto 17) select -- 100MHz/2^20 = 95.3Hz
intAn <=
"11111110" when "000",
"11111101" when "001",
"11111011" when "010",
"11110111" when "011",
"11101111" when "100",
"11011111" when "101",
"10111111" when "110",
"01111111" when others;
-- Digit Select
with cnt(19 downto 17) select -- 100MHz/2^20 = 95.3Hz
hex <=
number(7 downto 0) when "000",
number(15 downto 8) when "001",
number(23 downto 16) when "010",
number(31 downto 24) when "011",
number(39 downto 32) when "100",
number(47 downto 40) when "101",
number(55 downto 48) when "110",
number(63 downto 56) when others;
end Behavioral;
|
gpl-3.0
|
16184565a605838a63180a7208aeaec5
| 0.55264 | 4.041611 | false | false | false | false |
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