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elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/saed32/clkgen_saed32.vhd
| 1 | 5,043 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkgen_saed32
-- File: clkgen_saed32.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
-- Description: Clock generator for SAED32
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity clkgen_saed32 is
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic); -- unscaled 2X clock
end;
architecture struct of clkgen_saed32 is
component PLL
port (
-- VDD25 : in std_logic;
-- DVDD : inout std_logic;
-- VSSA : in std_logic;
-- AVDD : inout std_logic;
REF_CLK : in std_logic;
FB_CLK : in std_logic;
FB_MODE : in std_logic;
PLL_BYPASS : in std_logic;
CLK_4X : out std_logic;
CLK_2X : out std_logic;
CLK_1X : out std_logic);
end component;
-----------------------------------------------------------------------------
-- attributes
-----------------------------------------------------------------------------
attribute DONT_TOUCH : Boolean;
attribute DONT_TOUCH of pll0 : label is True;
begin
pll0 : PLL port map (
-- VDD25 => '1',
-- DVDD => open,
-- VSSA => '0',
-- AVDD => open,
REF_CLK => clkin,
FB_CLK => cgi.pllref,
FB_MODE => cgi.pllctrl(1),
PLL_BYPASS => cgi.pllctrl(0),
CLK_4X => clk4x,
CLK_2X => clk2x,
CLK_1X => clk
);
cgo.clklock <= '1';
sdclk <= '0';
pciclk <= '0';
cgo.pcilock <= '1';
clk1xu <= '0';
clk2xu <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
--library saed32;
--use saed32.CGLPPSX4_LVT;
-- pragma translate_on
entity clkand_saed32 is
port (
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0');
end clkand_saed32;
architecture rtl of clkand_saed32 is
component CGLPPSX4_LVT
port (
GCLK : out std_ulogic;
CLK : in std_ulogic;
EN : in std_ulogic;
SE : in std_ulogic
);
end component;
attribute DONT_TOUCH : Boolean;
attribute DONT_TOUCH of gate : label is True;
begin
gate: CGLPPSX4_LVT port map (GCLK => o , CLK => i , EN => en, SE => tsten);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
--library saed32;
--use saed32.MUX21X1_LVT;
-- pragma translate_on
entity clkmux_saed32 is
port (
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end clkmux_saed32;
architecture rtl of clkmux_saed32 is
component MUX21X1_LVT
port (
Y : out std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
S0 : in std_ulogic
);
end component;
attribute DONT_TOUCH : Boolean;
attribute DONT_TOUCH of m0 : label is True;
begin
m0: MUX21X1_LVT port map (A1 => i0 , A2 => i1 , S0 => sel, Y => o);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
--library saed32;
--use saed32.INVX4_LVT;
-- pragma translate_on
entity clkinv_saed32 is
port (
i : in std_ulogic;
o : out std_ulogic);
end clkinv_saed32;
architecture rtl of clkinv_saed32 is
component INVX4_LVT
port (
Y : out std_ulogic;
A : in std_ulogic
);
end component;
attribute DONT_TOUCH : Boolean;
attribute DONT_TOUCH of gate : label is True;
begin
gate: INVX4_LVT port map (A => i , Y => o);
end rtl;
|
gpl-2.0
|
b5afea81a543abdd3cec8e90560d2bd3
| 0.553837 | 3.497226 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/clkmux.vhd
| 1 | 4,006 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkmux
-- File: clkmux.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Glitch-free clock multiplexer
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allclkgen.all;
entity clkmux is
generic(tech : integer := 0;
rsel : integer range 0 to 1 := 0); -- registered sel
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic;
rst : in std_ulogic := '1'
);
end entity;
architecture rtl of clkmux is
signal seli, sel0, sel1, cg0, cg1 : std_ulogic;
begin
rs : if rsel = 1 generate
rsproc : process(i0)
begin
if rising_edge(i0) then seli <= sel; end if;
end process;
end generate;
cs : if rsel = 0 generate seli <= sel; end generate;
tec : if has_clkmux(tech) = 1 generate
xil : if is_unisim(tech) = 1 generate
buf : clkmux_unisim port map(sel => seli, I0 => i0, I1 => i1, O => o);
end generate;
rhl : if tech = rhlib18t generate
buf : clkmux_rhlib18t port map(sel => seli, I0 => i0, I1 => i1, O => o);
end generate;
ut13 : if tech = ut130 generate
x0 : clkmux_ut130hbd port map (i0 => i0, i1 => i1, sel => sel, o => o);
end generate;
n2x : if tech = easic45 generate
mux : clkmux_n2x port map (i0 => i0, i1 => i1, sel => sel, o => o);
end generate;
ut90n : if tech = ut90 generate
x0 : clkmux_ut90nhbd port map (i0 => i0, i1 => i1, sel => seli, o => o);
end generate;
saed : if tech = saed32 generate
x0 : clkmux_saed32 port map (i0 => i0, i1 => i1, sel => seli, o => o);
end generate;
rhs : if tech = rhs65 generate
x0 : clkmux_rhs65 port map (i0 => i0, i1 => i1, sel => seli, o => o);
end generate;
dar : if tech = dare generate
x0 : clkmux_dare port map (i0 => i0, i1 => i1, sel => seli, o => o);
end generate;
rhu : if tech = rhumc generate
x0 : clkmux_rhumc port map (i0 => i0, i1 => i1, sel => seli, o => o);
end generate;
noxil : if not((is_unisim(tech) = 1) or (tech = rhlib18t) or (tech = ut130) or
(tech = easic45) or (tech = ut90) or (tech = saed32) or (tech = rhs65) or (tech = dare) or (tech = rhumc)) generate
o <= i0 when seli = '0' else i1;
end generate;
end generate;
gen : if has_clkmux(tech) = 0 generate
p0 : process(i0, rst)
begin
if rst = '0' then
sel0 <= '1';
elsif falling_edge(i0) then
sel0 <= (not seli) and (not sel1);
end if;
end process;
p1 : process(i1, rst)
begin
if rst = '0' then
sel1 <= '0';
elsif falling_edge(i1) then
sel1 <= seli and (not sel0);
end if;
end process;
cg0 <= i0 and sel0;
cg1 <= i1 and sel1;
o <= cg0 or cg1;
end generate;
end architecture;
|
gpl-2.0
|
d5954800272f2f078fabe476e2742bcc
| 0.565152 | 3.450474 | false | false | false | false |
BOT-Man-JL/BUPT-Projects
|
2-2-Digital-Logic/Control.vhd
| 1 | 1,145 |
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Entity Control Is
Port (
clk_i: In std_logic;
clr_o: Out std_logic;
enable_o: Out std_logic;
blink_o: Out std_logic
);
End Entity;
Architecture fControl Of Control Is
Signal g_clk: std_logic;
Signal clr_t: std_logic;
Signal enable_t: std_logic;
Signal blink_t: std_logic;
Begin
Process (clk_i)
Variable tmp: Integer Range 0 to 1000;
Begin
If clk_i'Event And clk_i = '1' Then
If tmp = 999 Then
tmp := 0;
g_clk <= '1';
Else
tmp := tmp + 1;
g_clk <= '0';
End If;
End If;
End Process;
Process (g_clk)
Variable count: Integer Range 0 to 1000;
Begin
If g_clk'Event And g_clk = '1' Then
If count = 999 Then
count := 0;
enable_t <= Not enable_t;
clr_t <= '0';
Elsif enable_t = '1' Then
count := count + 1;
clr_t <= '0';
blink_t <= '1';
Elsif count > 499 Then
count := count + 1;
clr_t <= '1';
blink_t <= '0';
Else
count := count + 1;
blink_t <= '1';
End If;
End If;
End Process;
clr_o <= clr_t;
enable_o <= enable_t;
blink_o <= blink_t;
End Architecture;
|
gpl-3.0
|
2bfec52d83d36dc2eec4c3b24e7bf746
| 0.588646 | 2.550111 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/umc18/pads_umc18.vhd
| 1 | 8,553 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: umcpads_gen
-- File: umcpads_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UMC pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package umcpads is
-- input pad
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-up
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-down
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
-- schmitt input pad
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
-- output pads
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
-- tri-state output pads
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
-- bidirectional pads
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.ICMT3V;
use umc18.ICMT3VPU;
use umc18.ICMT3VPD;
use umc18.ISTRT3V;
-- pragma translate_on
entity umc_inpad is
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of umc_inpad is
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
begin
norm : if filter = 0 generate
ip : ICMT3V port map (a => pad, z => o);
end generate;
pu : if filter = pullup generate
ip : ICMT3VPU port map (a => pad, z => o);
end generate;
pd : if filter = pulldown generate
ip : ICMT3VPD port map (a => pad, z => o);
end generate;
sch : if filter = schmitt generate
ip : ISTRT3V port map (a => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.BICM3V4;
use umc18.BICM3V12;
use umc18.BICM3V24;
-- pragma translate_on
entity umc_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of umc_iopad is
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : BICM3V4 port map (a => i, en => en, io => pad, z => o);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : BICM3V12 port map (a => i, en => en, io => pad, z => o);
end generate;
f24 : if (strength > 16) generate
op : BICM3V24 port map (a => i, en => en, io => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCM3V4;
use umc18.OCM3V12;
use umc18.OCM3V24;
-- pragma translate_on
entity umc_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of umc_outpad is
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCM3V4 port map (a => i, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCM3V12 port map (a => i, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCM3V24 port map (a => i, z => pad);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCMTR4;
use umc18.OCMTR12;
use umc18.OCMTR24;
-- pragma translate_on
entity umc_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of umc_toutpad is
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCMTR4 port map (a => i, en => en, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCMTR12 port map (a => i, en => en, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCMTR24 port map (a => i, en => en, z => pad);
end generate;
end;
library umc18;
-- pragma translate_off
use umc18.LVDS_Driver;
use umc18.LVDS_Receiver;
use umc18.LVDS_Biasmodule;
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity umc_lvds_combo is
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic);
end ;
architecture rtl of umc_lvds_combo is
component LVDS_Driver port ( A, Vref, HI : in std_logic; Z, ZN : out std_logic); end component;
component LVDS_Receiver port ( A, AN : in std_logic; Z : out std_logic); end component;
component LVDS_Biasmodule port ( RefR : in std_logic; Vref, HI : out std_logic); end component;
signal vref, hi : std_logic;
begin
lvds_bias: LVDS_Biasmodule port map (lvdsref, vref, hi);
swloop : for i in 0 to width-1 generate
spw_rxd_pad : LVDS_Receiver port map (idpadp(i), idpadn(i), idval(i));
spw_rxs_pad : LVDS_Receiver port map (ispadp(i), ispadn(i), isval(i));
spw_txd_pad : LVDS_Driver port map (odval(i), vref, hi, odpadp(i), odpadn(i));
spw_txs_pad : LVDS_Driver port map (osval(i), vref, hi, ospadp(i), ospadn(i));
end generate;
end;
|
gpl-2.0
|
f66dcb8e20bc796f3af022f4a633d75e
| 0.653689 | 3.254566 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/cypress/ssram/cy7c1380d.vhd
| 4 | 26,441 |
--***************************************************************************************
--
-- File Name: CY7C1380_PL_SCD.vhd
-- Version: 1.0
-- Date: December 22nd, 2004
-- Model: BUS Functional
-- Simulator: Modelsim
--
--
-- Queries: MPD Applications
-- Website: www.cypress.com/support
-- Company: Cypress Semiconductor
-- Part #: CY7C1380D (512K x 36)
--
-- Description: Cypress 18Mb Synburst SRAM (Pipelined SCD)
--
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright(c) Cypress Semiconductor, 2004
-- All rights reserved
--
-- Rev Date Changes
-- --- ---------- ---------------------------------------
-- 1.0 12/22/2004 - New Model
-- - New Test Bench
-- - New Test Vectors
--
--***************************************************************************************
-- Timings for Different Speed Bins (sb): 250MHz, 225MHz, 200MHz, 167MHz, 133MHz
LIBRARY ieee, grlib, work;
USE ieee.std_logic_1164.all;
-- USE ieee.std_logic_unsigned.all;
-- Use IEEE.Std_Logic_Arith.all;
USE work.package_utility.all;
use grlib.stdlib.all;
use grlib.stdio.all;
use ieee.std_logic_1164.all;
use std.textio.all;
entity CY7C1380D is
GENERIC (
fname : string := "prom.srec"; -- File to read from
-- Constant Parameters
addr_bits : INTEGER := 19; -- This is external address
data_bits : INTEGER := 36;
--Clock timings for 250Mhz
Cyp_tCO : TIME := 2.6 ns; -- Data Output Valid After CLK Rise
Cyp_tCYC : TIME := 4.0 ns; -- Clock cycle time
Cyp_tCH : TIME := 1.7 ns; -- Clock HIGH time
Cyp_tCL : TIME := 1.7 ns; -- Clock LOW time
Cyp_tCHZ : TIME := 2.6 ns; -- Clock to High-Z
Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
Cyp_tOEHZ : TIME := 2.6 ns; -- OE# HIGH to Output High-Z
Cyp_tOELZ : TIME := 0.0 ns; -- OE# LOW to Output Low-Z
Cyp_tOEV : TIME := 2.6 ns; -- OE# LOW to Output Valid
Cyp_tAS : TIME := 1.2 ns; -- Address Set-up Before CLK Rise
Cyp_tADS : TIME := 1.2 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
Cyp_tADVS : TIME := 1.2 ns; -- ADV# Set-up Before CLK Rise
Cyp_tWES : TIME := 1.2 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
Cyp_tDS : TIME := 1.2 ns; -- Data Input Set-up Before CLK Rise
Cyp_tCES : TIME := 1.2 ns; -- Chip Enable Set-up
Cyp_tAH : TIME := 0.3 ns; -- Address Hold After CLK Rise
Cyp_tADH : TIME := 0.3 ns; -- ADSC#, ADSP# Hold After CLK Rise
Cyp_tADVH : TIME := 0.3 ns; -- ADV# Hold After CLK Rise
Cyp_tWEH : TIME := 0.3 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
Cyp_tDH : TIME := 0.3 ns; -- Data Input Hold After CLK Rise
Cyp_tCEH : TIME := 0.3 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 225Mhz
-- Cyp_tCO : TIME := 2.8 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 4.4 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 2.8 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 2.8 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 2.8 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 200Mhz
-- Cyp_tCO : TIME := 3.0 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 5.0 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.0 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 3.0 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 3.0 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 167Mhz
-- Cyp_tCO : TIME := 3.4 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 6.0 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.2 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.2 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.4 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 3.4 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 3.4 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 133Mhz
-- Cyp_tCO : TIME := 4.2 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 7.5 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.5 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.5 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.4 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 4.0 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 4.2 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
);
PORT (iZZ : IN STD_LOGIC;
iMode : IN STD_LOGIC;
iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0);
inGW : IN STD_LOGIC;
inBWE : IN STD_LOGIC;
inBWd : IN STD_LOGIC;
inBWc : IN STD_LOGIC;
inBWb : IN STD_LOGIC;
inBWa : IN STD_LOGIC;
inCE1 : IN STD_LOGIC;
iCE2 : IN STD_LOGIC;
inCE3 : IN STD_LOGIC;
inADSP : IN STD_LOGIC;
inADSC : IN STD_LOGIC;
inADV : IN STD_LOGIC;
inOE : IN STD_LOGIC;
ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0);
iCLK : IN STD_LOGIC);
end CY7C1380D;
ARCHITECTURE CY7C1380D_arch OF CY7C1380D IS
signal Read_reg_o1, Read_reg1 : STD_LOGIC;
signal WrN_reg1 : STD_LOGIC;
signal ADSP_N_o : STD_LOGIC;
signal pipe_reg1, ce_reg1,pcsr_write1, ctlr_write1 : STD_LOGIC;
signal Sys_clk : STD_LOGIC := '0';
signal test : STD_LOGIC;
signal dout, din1 : STD_LOGIC_VECTOR (data_bits-1 downto 0);
signal ce : STD_LOGIC;
signal Write_n : STD_LOGIC;
signal Read : STD_LOGIC;
signal bwa_n1 : STD_LOGIC;
signal bwb_n1 : STD_LOGIC;
signal bwc_n1 : STD_LOGIC;
signal bwd_n1 : STD_LOGIC;
signal latch_addr : STD_LOGIC;
signal addr_reg_read1,addr_reg_write1,addr_reg_in1 : STD_LOGIC_VECTOR (addr_bits-1 downto 0);
signal OeN_HZ : STD_LOGIC;
signal OeN_DataValid : STD_LOGIC;
signal OeN_efct : STD_LOGIC;
signal WR_HZ : STD_LOGIC;
signal WR_LZ : STD_LOGIC;
signal WR_efct : STD_LOGIC;
signal CE_HZ : STD_LOGIC;
signal CE_LZ : STD_LOGIC;
signal Pipe_efct : STD_LOGIC;
signal RD_HZ : STD_LOGIC;
signal RD_LZ : STD_LOGIC;
signal RD_efct : STD_LOGIC;
begin
ce <= ((not inCE1) and (iCE2) and (not inCE3));
Write_n <= not((((not inBWa) OR (not inBWb) OR (not inBWc) OR (not inBWd)) AND (not inBWE)) OR (not inGW));
Read <= (((inBWa AND inBWb AND inBWc AND inBWd) AND (not inBWE)) OR (inGW AND inBWE) OR (( not inADSP) AND ce));
bwa_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWa))));
bwb_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWb))));
bwc_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWc))));
bwd_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWd))));
latch_addr <= ((not inADSC) OR ((not inADSP) AND (not inCE1)));
OeN_efct <= OeN_DataValid when (inOE = '0') else OeN_HZ;
WR_efct <= WR_LZ when (WrN_reg1 = '0') else WR_HZ;
Pipe_efct <= CE_LZ when ((ce_reg1 = '1') and (pipe_reg1 = '1')) else CE_HZ;
RD_efct <= CE_LZ when (Read_reg_o1 = '1') else CE_HZ ;
Process (Read_reg_o1)
begin
if (Read_reg_o1 = '0') then
RD_HZ <= '0' after Cyp_tCHZ;
RD_LZ <= '0' after Cyp_tCLZ;
elsif (Read_reg_o1 = '1') then
RD_HZ <= '1' after Cyp_tCHZ;
RD_LZ <= '1' after Cyp_tCLZ;
else
RD_HZ <= 'X' after Cyp_tCHZ;
RD_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
Process (pipe_reg1)
begin
if (pipe_reg1 = '1') then
CE_LZ <= '1' after Cyp_tCLZ;
elsif (pipe_reg1 = '0') then
CE_LZ <= '0' after Cyp_tCLZ;
else
CE_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
-- System Clock Decode
Process (iclk)
variable Sys_clk1 : std_logic := '0';
begin
if (rising_edge (iclk)) then
Sys_clk1 := not iZZ;
end if;
if (falling_edge (iCLK)) then
Sys_clk1 := '0';
end if;
Sys_clk <= Sys_clk1;
end process;
Process (WrN_reg1)
begin
if (WrN_reg1 = '1') then
WR_HZ <= '1' after Cyp_tCHZ;
WR_LZ <= '1' after Cyp_tCLZ;
elsif (WrN_reg1 = '0') then
WR_HZ <= '0' after Cyp_tCHZ;
WR_LZ <= '0' after Cyp_tCLZ;
else
WR_HZ <= 'X' after Cyp_tCHZ;
WR_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
Process (inOE)
begin
if (inOE = '1') then
OeN_HZ <= '1' after Cyp_tOEHZ;
OeN_DataValid <= '1' after Cyp_tOEV;
elsif (inOE = '0') then
OeN_HZ <= '0' after Cyp_tOEHZ;
OeN_DataValid <= '0' after Cyp_tOEV;
else
OeN_HZ <= 'X' after Cyp_tOEHZ;
OeN_DataValid <= 'X' after Cyp_tOEV;
end if;
end process;
process (ce_reg1, pipe_reg1)
begin
if ((ce_reg1 = '0') or (pipe_reg1 = '0')) then
CE_HZ <= '0' after Cyp_tCHZ;
elsif ((ce_reg1 = '1') and (pipe_reg1 = '1')) then
CE_HZ <= '1' after Cyp_tCHZ;
else
CE_HZ <= 'X' after Cyp_tCHZ;
end if;
end process;
Process (Sys_clk)
TYPE memory_array IS ARRAY ((2**addr_bits -1) DOWNTO 0) OF STD_LOGIC_VECTOR ((data_bits/4) - 1 DOWNTO 0);
variable Read_reg_o : std_logic;
variable Read_reg : std_logic;
variable pcsr_write, ctlr_write : std_logic;
variable WrN_reg : std_logic;
variable latch_addr_old, latch_addr_current : std_logic;
variable addr_reg_in, addr_reg_read, addr_reg_write : std_logic_vector (addr_bits -1 downto 0) := (others => '0');
variable bcount, first_addr : std_logic_vector (1 downto 0) := "00";
variable bwa_reg,bwb_reg,bwc_reg,bwd_reg, pipe_reg, ce_reg : std_logic;
variable din : std_logic_vector (data_bits-1 downto 0);
variable first_addr_int : integer;
variable bank0 : memory_array;
variable bank1 : memory_array;
variable bank2 : memory_array;
variable bank3 : memory_array;
variable FIRST : boolean := true;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable CH : character;
variable ai : integer := 0;
variable L1 : line;
begin
if FIRST then
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
std.textio.read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
hread(L1, recdata);
ai := conv_integer(recaddr)/4;
for i in 0 to 3 loop
bank3 (ai+i) := "0000" & recdata((i*32) to (i*32+4));
bank2 (ai+i) := recdata((i*32+5) to (i*32+13));
bank1 (ai+i) := recdata((i*32+14) to (i*32+22));
bank0 (ai+i) := recdata((i*32+23) to (i*32+31));
end loop;
end if;
end if;
end if;
end loop;
FIRST := false;
end if;
if rising_edge (Sys_clk) then
if (Write_n = '0') then
Read_reg_o := '0';
else
Read_reg_o := Read_reg;
end if;
if (Write_n = '0') then
Read_reg := '0';
else
Read_reg := Read;
end if;
Read_reg1 <= Read_reg;
Read_reg_o1 <= Read_reg_o;
if (Read_reg = '1') then
pcsr_write := '0';
ctlr_write := '0';
end if;
-- Write Register
if (Read_reg_o = '1') then
WrN_reg := '1';
else
WrN_reg := Write_n;
end if;
WrN_reg1 <= WrN_reg;
latch_addr_old := latch_addr_current;
latch_addr_current := latch_addr;
if (latch_addr_old = '1' and (Write_n = '0') and ADSP_N_o = '0') then
pcsr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
elsif (latch_addr_current = '1' and (Write_n = '0') and inADSP = '1' and inADSC = '0') then
ctlr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
end if;
-- ADDRess Register
if (latch_addr = '1') then
addr_reg_in := iADDR;
bcount := iADDR (1 downto 0);
first_addr := iADDR (1 downto 0);
end if;
addr_reg_in1 <= addr_reg_in;
-- ADSP_N Previous-Cycle Register
ADSP_N_o <= inADSP;
pcsr_write1 <= pcsr_write;
ctlr_write1 <= ctlr_write;
first_addr_int := CONV_INTEGER1 (first_addr);
-- Binary Counter and Logic
if ((iMode = '0') and (inADV = '0') and (latch_addr = '0')) then -- Linear Burst
bcount := (bcount + '1'); -- Advance Counter
elsif ((iMode = '1') and (inADV = '0') and (latch_addr = '0')) then -- Interleaved Burst
if ((first_addr_int REM 2) = 0) then
bcount := (bcount + '1'); -- Increment Counter
elsif ((first_addr_int REM 2) = 1) then
bcount := (bcount - '1'); -- Decrement Counter
end if;
end if;
-- Read ADDRess
addr_reg_read := addr_reg_write;
addr_reg_read1 <= addr_reg_read;
-- Write ADDRess
addr_reg_write := addr_reg_in ((addr_bits - 1) downto 2) & bcount(1) & bcount(0);
addr_reg_write1 <= addr_reg_write;
-- Byte Write Register
bwa_reg := not bwa_n1;
bwb_reg := not bwb_n1;
bwc_reg := not bwc_n1;
bwd_reg := not bwd_n1;
-- Enable Register
pipe_reg := ce_reg;
-- Enable Register
if (latch_addr = '1') then
ce_reg := ce;
end if;
pipe_reg1 <= pipe_reg;
ce_reg1 <= ce_reg;
-- Input Register
if ((ce_reg = '1') and ((bwa_n1 ='0') or (bwb_n1 = '0') or (bwc_n1 = '0') or (bwd_n1 = '0')) and
((pcsr_write = '1') or (ctlr_write = '1'))) then
din := ioDQ;
end if;
din1 <= din;
-- Byte Write Driver
if ((ce_reg = '1') and (bwa_reg = '1')) then
bank0 (CONV_INTEGER1 (addr_reg_write)) := din (8 downto 0);
end if;
if ((ce_reg = '1') and (bwb_reg = '1')) then
bank1 (CONV_INTEGER1 (addr_reg_write)) := din (17 downto 9);
end if;
if ((ce_reg = '1') and (bwc_reg = '1')) then
bank2 (CONV_INTEGER1 (addr_reg_write)) := din (26 downto 18);
end if;
if ((ce_reg = '1') and (bwd_reg = '1')) then
bank3 (CONV_INTEGER1 (addr_reg_write)) := din (35 downto 27);
end if;
-- Output Registers
if ((Write_n = '0') or (pipe_reg = '0')) then
dout (35 downto 0) <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" after Cyp_tCHZ;
elsif (Read_reg_o = '1') then
dout ( 8 downto 0) <= bank0 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (17 downto 9) <= bank1 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (26 downto 18) <= bank2 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (35 downto 27) <= bank3 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
end if;
end if;
end process;
-- Output Buffers
ioDQ <= dout when ((inOE ='0') and (iZZ='0') and (Pipe_efct='1') and (RD_efct='1') and (WR_efct='1'))
else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
clk_check : PROCESS
VARIABLE clk_high, clk_low : TIME := 0 ns;
BEGIN
WAIT ON iClk;
IF iClk = '1' AND NOW >= Cyp_tCYC THEN
ASSERT (NOW - clk_low >= Cyp_tCH)
REPORT "Clk width low - tCH violation"
SEVERITY ERROR;
ASSERT (NOW - clk_high >= Cyp_tCYC)
REPORT "Clk period high - tCYC violation"
SEVERITY ERROR;
clk_high := NOW;
ELSIF iClk = '0' AND NOW /= 0 ns THEN
ASSERT (NOW - clk_high >= Cyp_tCL)
REPORT "Clk width high - tCL violation"
SEVERITY ERROR;
ASSERT (NOW - clk_low >= Cyp_tCYC)
REPORT "Clk period low - tCYC violation"
SEVERITY ERROR;
clk_low := NOW;
END IF;
END PROCESS;
-- Check for Setup Timing Violation
setup_check : PROCESS
BEGIN
WAIT ON iClk;
IF iClk = '1' THEN
ASSERT (iAddr'LAST_EVENT >= Cyp_tAS)
REPORT "Addr - tAS violation"
SEVERITY ERROR;
ASSERT (inGW'LAST_EVENT >= Cyp_tWES)
REPORT "GW# - tWES violation"
SEVERITY ERROR;
ASSERT (inBWE'LAST_EVENT >= Cyp_tWES)
REPORT "BWE# - tWES violation"
SEVERITY ERROR;
ASSERT (inCe1'LAST_EVENT >= Cyp_tWES)
REPORT "CE1# - tWES violation"
SEVERITY ERROR;
ASSERT (iCe2'LAST_EVENT >= Cyp_tWES)
REPORT "CE2 - tWES violation"
SEVERITY ERROR;
ASSERT (inCe3'LAST_EVENT >= Cyp_tWES)
REPORT "CE3# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdv'LAST_EVENT >= Cyp_tADVS)
REPORT "ADV# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdsp'LAST_EVENT >= Cyp_tADVS)
REPORT "ADSP# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdsc'LAST_EVENT >= Cyp_tADVS)
REPORT "ADSC# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwa'LAST_EVENT >= Cyp_tWES)
REPORT "BWa# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwb'LAST_EVENT >= Cyp_tWES)
REPORT "BWb# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwc'LAST_EVENT >= Cyp_tWES)
REPORT "BWc# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwd'LAST_EVENT >= Cyp_tWES)
REPORT "BWd# - tWES violation"
SEVERITY ERROR;
ASSERT (ioDq'LAST_EVENT >= Cyp_tDS)
REPORT "Dq - tDS violation"
SEVERITY ERROR;
END IF;
END PROCESS;
-- Check for Hold Timing Violation
hold_check : PROCESS
BEGIN
WAIT ON iClk'DELAYED(Cyp_tAH), iClk'DELAYED(Cyp_tWEH), iClk'DELAYED(Cyp_tDH);
IF iClk'DELAYED(Cyp_tAH) = '1' THEN
ASSERT (iAddr'LAST_EVENT > Cyp_tAH)
REPORT "Addr - tAH violation"
SEVERITY ERROR;
END IF;
IF iClk'DELAYED(Cyp_tDH) = '1' THEN
ASSERT (ioDq'LAST_EVENT > Cyp_tDH)
REPORT "Dq - tDH violation"
SEVERITY ERROR;
END IF;
IF iClk'DELAYED(Cyp_tWEH) = '1' THEN
ASSERT (inCe1'LAST_EVENT > Cyp_tWEH)
REPORT "CE1# - tWEH violation"
SEVERITY ERROR;
ASSERT (iCe2'LAST_EVENT > Cyp_tWEH)
REPORT "CE2 - tWEH violation"
SEVERITY ERROR;
ASSERT (inCe3'LAST_EVENT > Cyp_tWEH)
REPORT "CE3 - tWEH violation"
SEVERITY ERROR;
ASSERT (inAdv'LAST_EVENT > Cyp_tWEH)
REPORT "ADV# - tWEH violation"
SEVERITY ERROR;
ASSERT (inADSP'LAST_EVENT > Cyp_tWEH)
REPORT "ADSP# - tWEH violation"
SEVERITY ERROR;
ASSERT (inADSC'LAST_EVENT > Cyp_tWEH)
REPORT "ADSC# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwa'LAST_EVENT > Cyp_tWEH)
REPORT "BWa# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwb'LAST_EVENT > Cyp_tWEH)
REPORT "BWb# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwc'LAST_EVENT > Cyp_tWEH)
REPORT "BWc# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwd'LAST_EVENT > Cyp_tWEH)
REPORT "BWd# - tWEH violation"
SEVERITY ERROR;
END IF;
END PROCESS;
end CY7C1380D_arch;
|
gpl-2.0
|
f532329a1180075baf8ab2832ccb6a00
| 0.492455 | 3.408663 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/srmmu/mmutlb.vhd
| 1 | 21,804 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmutlb
-- File: mmutlb.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU TLB logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmutlb is
generic (
tech : integer range 0 to NTECH := 0;
entries : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 1;
mmupgsz : integer range 0 to 5 := 0;
scantest : integer := 0;
ramcbits: integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
tlbi : in mmutlb_in_type;
tlbo : out mmutlb_out_type;
two : in mmutw_out_type;
twi : out mmutw_in_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end mmutlb;
architecture rtl of mmutlb is
constant M_TLB_FASTWRITE : integer range 0 to 3 :=
conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
constant entries_log : integer := log2(entries);
constant entries_max : std_logic_vector(entries_log-1 downto 0) :=
conv_std_logic_vector(entries-1, entries_log);
type states is (idle, match, walk, pack, flush, sync, diag, dofault);
type tlb_rtype is record
s2_tlbstate : states;
s2_entry : std_logic_vector(entries_log-1 downto 0);
s2_hm : std_logic;
s2_needsync : std_logic;
s2_data : std_logic_vector(31 downto 0);
s2_isid : mmu_idcache;
s2_su : std_logic;
s2_read : std_logic;
s2_flush : std_logic;
s2_ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
walk_use : std_logic;
walk_transdata : mmuidc_data_out_type;
walk_fault : mmutlbfault_out_type;
nrep : std_logic_vector(entries_log-1 downto 0);
tpos : std_logic_vector(entries_log-1 downto 0);
touch : std_logic;
sync_isw : std_logic;
tlbmiss : std_logic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
constant RRES : tlb_rtype := (
s2_tlbstate => idle,
s2_entry => (others => '0'),
s2_hm => '0',
s2_needsync => '0',
s2_data => (others => '0'),
s2_isid => id_icache,
s2_su => '0',
s2_read => '0',
s2_flush => '0',
s2_ctx => (others => '0'),
walk_use => '0',
walk_transdata => mmuidco_zero,
walk_fault => mmutlbfault_out_zero,
nrep => (others => '0'),
tpos => (others => '0'),
touch => '0',
sync_isw => '0',
tlbmiss => '0');
signal c,r : tlb_rtype;
-- tlb cams
component mmutlbcam
generic (
tlb_type : integer range 0 to 3 := 1;
mmupgsz : integer range 0 to 5 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
tlbcami : in mmutlbcam_in_type;
tlbcamo : out mmutlbcam_out_type
);
end component;
signal tlbcami : mmutlbcami_a (entries-1 downto 0);
signal tlbcamo : mmutlbcamo_a (entries-1 downto 0);
-- least recently used
component mmulru
generic (
entries : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
lrui : in mmulru_in_type;
lruo : out mmulru_out_type
);
end component;
signal lrui : mmulru_in_type;
signal lruo : mmulru_out_type;
-- data-ram syncram signals
signal dr1_addr : std_logic_vector(entries_log-1 downto 0);
signal dr1_datain : std_logic_vector(29 downto 0);
signal dr1_dataout : std_logic_vector(29 downto 0);
signal dr1_enable : std_logic;
signal dr1_write : std_logic;
begin
p0: process (rst, r, tlbi, two, tlbcamo, dr1_dataout, lruo)
variable v : tlb_rtype;
variable finish, selstate : std_logic;
variable cam_hitaddr : std_logic_vector(entries_log-1 downto 0);
variable cam_hit_all : std_logic;
variable mtag,ftag : tlbcam_tfp;
-- tlb cam input
variable tlbcam_trans_op : std_logic;
variable tlbcam_write_op : std_logic_vector(entries-1 downto 0);
variable tlbcam_flush_op : std_logic;
-- tw inputs
variable twi_walk_op_ur : std_logic;
variable twi_data : std_logic_vector(31 downto 0);
variable twi_areq_ur : std_logic;
variable twi_aaddr : std_logic_vector(31 downto 0);
variable twi_adata : std_logic_vector(31 downto 0);
variable two_error : std_logic;
-- lru inputs
variable lrui_touch : std_logic;
variable lrui_touchmin : std_logic;
variable lrui_pos : std_logic_vector(entries_log-1 downto 0);
-- syncram inputs
variable dr1write : std_logic;
-- hit tlbcam's output
variable ACC : std_logic_vector(2 downto 0);
variable PTE : std_logic_vector(31 downto 0);
variable LVL : std_logic_vector(1 downto 0);
variable CAC : std_logic;
variable NEEDSYNC : std_logic;
-- wb hit tlbcam's output
variable wb_i_entry : integer range 0 to entries-1;
variable wb_ACC : std_logic_vector(2 downto 0);
variable wb_PTE : std_logic_vector(31 downto 0);
variable wb_LVL : std_logic_vector(1 downto 0);
variable wb_CAC : std_logic;
variable wb_fault_pro, wb_fault_pri : std_logic;
variable wb_WBNEEDSYNC : std_logic;
variable twACC : std_logic_vector(2 downto 0);
variable tWLVL : std_logic_vector(1 downto 0);
variable twPTE : std_logic_vector(31 downto 0);
variable twNEEDSYNC : std_logic;
variable tlbcam_tagin : tlbcam_tfp;
variable tlbcam_tagwrite : tlbcam_reg;
variable store : std_logic;
variable reppos : std_logic_vector(entries_log-1 downto 0);
variable i_entry : integer range 0 to entries-1;
variable i_reppos : integer range 0 to entries-1;
variable fault_pro, fault_pri : std_logic;
variable fault_mexc, fault_trans, fault_inv, fault_access : std_logic;
variable transdata : mmuidc_data_out_type;
variable fault : mmutlbfault_out_type;
variable savewalk : std_logic;
variable tlbo_s1finished : std_logic;
variable wb_transdata : mmuidc_data_out_type;
variable cam_addr : std_logic_vector(31 downto 0);
begin
v := r; v.tlbmiss := '0';
cam_addr := tlbi.transdata.data;
wb_i_entry := 0;
wb_ACC := (others => '0');
wb_PTE := (others => '0');
wb_LVL := (others => '0');
wb_CAC := '0';
wb_fault_pro := '0';
wb_fault_pri := '0';
wb_WBNEEDSYNC := '0';
if (M_TLB_FASTWRITE /= 0) and (tlbi.trans_op = '0') then
cam_addr := tlbi.transdata.wb_data;
end if;
wb_transdata.finish := '0';
wb_transdata.data := (others => '0');
wb_transdata.cache := '0';
wb_transdata.accexc := '0';
finish := '0';
selstate := '0';
cam_hitaddr := (others => '0');
cam_hit_all := '0';
mtag.TYP := (others => '0');
mtag.I1 := (others => '0');
mtag.I2 := (others => '0');
mtag.I3 := (others => '0');
mtag.CTX := (others => '0');
mtag.M := '0';
ftag.TYP := (others => '0');
ftag.I1 := (others => '0');
ftag.I2 := (others => '0');
ftag.I3 := (others => '0');
ftag.CTX := (others => '0');
ftag.M := '0';
tlbcam_trans_op := '0';
tlbcam_write_op := (others => '0');
tlbcam_flush_op := '0';
twi_walk_op_ur := '0';
twi_data := (others => '0');
twi_areq_ur := '0';
twi_aaddr := (others => '0');
twi_adata := (others => '0');
two_error := '0';
lrui_touch:= '0';
lrui_touchmin:= '0';
lrui_pos := (others => '0');
dr1write := '0';
ACC := (others => '0');
PTE := (others => '0');
LVL := (others => '0');
CAC := '0';
NEEDSYNC := '0';
twACC := (others => '0');
tWLVL := (others => '0');
twPTE := (others => '0');
twNEEDSYNC := '0';
tlbcam_tagin.TYP := (others => '0');
tlbcam_tagin.I1 := (others => '0');
tlbcam_tagin.I2 := (others => '0');
tlbcam_tagin.I3 := (others => '0');
tlbcam_tagin.CTX := (others => '0');
tlbcam_tagin.M := '0';
tlbcam_tagwrite.ET := (others => '0');
tlbcam_tagwrite.ACC := (others => '0');
tlbcam_tagwrite.M := '0';
tlbcam_tagwrite.R := '0';
tlbcam_tagwrite.SU := '0';
tlbcam_tagwrite.VALID := '0';
tlbcam_tagwrite.LVL := (others => '0');
tlbcam_tagwrite.I1 := (others => '0');
tlbcam_tagwrite.I2 := (others => '0');
tlbcam_tagwrite.I3 := (others => '0');
tlbcam_tagwrite.CTX := (others => '0');
tlbcam_tagwrite.PPN := (others => '0');
tlbcam_tagwrite.C := '0';
store := '0';
reppos := (others => '0');
fault_pro := '0';
fault_pri := '0';
fault_mexc := '0';
fault_trans := '0';
fault_inv := '0';
fault_access := '0';
transdata.finish := '0';
transdata.data := (others => '0');
transdata.cache := '0';
transdata.accexc := '0';
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
fault.fault_lvl := (others => '0');
fault.fault_su := '0';
fault.fault_read := '0';
fault.fault_isid := id_dcache;
fault.fault_addr := (others => '0');
savewalk := '0';
tlbo_s1finished := '0';
tlbcam_trans_op := '0'; tlbcam_write_op := (others => '0'); tlbcam_flush_op := '0';
lrui_touch := '0'; lrui_touchmin := '0'; lrui_pos := (others => '0');
dr1write := '0';
fault_pro := '0'; fault_pri := '0'; fault_mexc := '0'; fault_trans := '0'; fault_inv := '0'; fault_access := '0';
twi_walk_op_ur := '0'; twi_areq_ur := '0'; twi_aaddr := dr1_dataout&"00";
finish := '0';
store := '0'; savewalk := '0'; tlbo_s1finished := '0';
selstate := '0';
cam_hitaddr := (others => '0');
cam_hit_all := '0';
NEEDSYNC := '0';
for i in entries-1 downto 0 loop
NEEDSYNC := NEEDSYNC or tlbcamo(i).NEEDSYNC;
if (tlbcamo(i).hit) = '1' then
cam_hitaddr(entries_log-1 downto 0) := cam_hitaddr(entries_log-1 downto 0) or conv_std_logic_vector(i, entries_log);
cam_hit_all := '1';
end if;
end loop;
-- tlbcam write operation
tlbcam_tagwrite := TLB_CreateCamWrite( two.data, r.s2_read, two.lvl, r.s2_ctx, r.s2_data);
-- replacement position
reppos := (others => '0');
if tlb_rep = 0 then
reppos := lruo.pos(entries_log-1 downto 0);
v.touch := '0';
elsif tlb_rep = 1 then
reppos := r.nrep;
end if;
i_reppos := conv_integer(reppos);
-- tw
two_error := two.fault_mexc or two.fault_trans or two.fault_inv;
twACC := two.data(PTE_ACC_U downto PTE_ACC_D);
twLVL := two.lvl;
twPTE := two.data;
twNEEDSYNC := (not two.data(PTE_R)) or ((not r.s2_read) and (not two.data(PTE_M))); -- tw : writeback on next flush
case r.s2_tlbstate is
when idle =>
if (tlbi.s2valid) = '1' then
if r.s2_flush = '1' then
v.s2_tlbstate := pack;
else
v.walk_fault.fault_pri := '0';
v.walk_fault.fault_pro := '0';
v.walk_fault.fault_access := '0';
v.walk_fault.fault_trans := '0';
v.walk_fault.fault_inv := '0';
v.walk_fault.fault_mexc := '0';
if (r.s2_hm and not tlbi.mmctrl1.tlbdis ) = '1' then
if r.s2_needsync = '1' then
v.s2_tlbstate := sync;
else
finish := '1';
end if;
if tlb_rep = 0 then
v.tpos := r.s2_entry; v.touch := '1'; -- touch lru
end if;
else
v.s2_entry := reppos;
v.s2_tlbstate := walk; v.tlbmiss := '1';
if tlb_rep = 0 then
lrui_touchmin := '1'; -- lru element consumed
end if;
end if;
end if;
end if;
when walk =>
if (two.finish = '1') then
if ( two_error ) = '0' then
tlbcam_write_op := decode(r.s2_entry);
dr1write := '1';
TLB_CheckFault( twACC, r.s2_isid, r.s2_su, r.s2_read, v.walk_fault.fault_pro, v.walk_fault.fault_pri );
end if;
TLB_MergeData( mmupgsz, tlbi.mmctrl1, two.lvl , two.data, r.s2_data, v.walk_transdata.data );
v.walk_transdata.cache := two.data(PTE_C);
v.walk_fault.fault_lvl := two.fault_lvl;
v.walk_fault.fault_access := '0';
v.walk_fault.fault_mexc := two.fault_mexc;
v.walk_fault.fault_trans := two.fault_trans;
v.walk_fault.fault_inv := two.fault_inv;
v.walk_use := '1';
if ( twNEEDSYNC = '0' or two_error = '1') then
v.s2_tlbstate := pack;
else
v.s2_tlbstate := sync;
v.sync_isw := '1';
end if;
if tlb_rep = 1 then
if (r.nrep = entries_max) then v.nrep := (others => '0');
else v.nrep := r.nrep + 1;
end if;
end if;
else
twi_walk_op_ur := '1';
end if;
when pack =>
v.s2_flush := '0';
v.walk_use := '0';
finish := '1';
v.s2_tlbstate := idle;
when sync =>
tlbcam_trans_op := '1';
if ( v.sync_isw = '1') then
-- pte address is currently written to syncram, wait one cycle before issuing twi_areq_ur
v.sync_isw := '0';
else
if (two.finish = '1') then
v.s2_tlbstate := pack;
v.walk_fault.fault_mexc := two.fault_mexc;
if (two.fault_mexc) = '1' then
v.walk_use := '1';
end if;
else
twi_areq_ur := '1';
end if;
end if;
when others =>
v .s2_tlbstate := idle;
end case;
if selstate = '1' then
if tlbi.trans_op = '1' then
elsif tlbi.flush_op = '1' then
end if;
end if;
i_entry := conv_integer(r.s2_entry);
ACC := tlbcamo(i_entry).pteout(PTE_ACC_U downto PTE_ACC_D);
PTE := tlbcamo(i_entry).pteout;
LVL := tlbcamo(i_entry).LVL;
CAC := tlbcamo(i_entry).pteout(PTE_C);
transdata.cache := CAC;
TLB_CheckFault( ACC, r.s2_isid, r.s2_su, r.s2_read, fault_pro, fault_pri );
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
if finish = '1' and (r.s2_flush = '0') then --protect flush path
fault.fault_pro := fault_pro;
fault.fault_pri := fault_pri;
fault.fault_access := fault_access;
fault.fault_mexc := fault_mexc;
fault.fault_trans := fault_trans;
fault.fault_inv := fault_inv;
end if;
if (M_TLB_FASTWRITE /= 0) then
wb_i_entry := conv_integer(cam_hitaddr(entries_log-1 downto 0));
wb_ACC := tlbcamo(wb_i_entry).pteout(PTE_ACC_U downto PTE_ACC_D);
wb_PTE := tlbcamo(wb_i_entry).pteout;
wb_LVL := tlbcamo(wb_i_entry).LVL;
wb_CAC := tlbcamo(wb_i_entry).pteout(PTE_C);
wb_WBNEEDSYNC := tlbcamo(wb_i_entry).WBNEEDSYNC;
wb_transdata.cache := wb_CAC;
TLB_MergeData( mmupgsz, tlbi.mmctrl1, wb_LVL, wb_PTE, tlbi.transdata.data, wb_transdata.data );
TLB_CheckFault( wb_ACC, tlbi.transdata.isid, tlbi.transdata.su, tlbi.transdata.read, wb_fault_pro, wb_fault_pri );
wb_transdata.accexc := wb_fault_pro or wb_fault_pri or wb_WBNEEDSYNC or (not cam_hit_all);
end if;
--# merge data
TLB_MergeData( mmupgsz, tlbi.mmctrl1, LVL, PTE, r.s2_data, transdata.data );
--# reset
if (not ASYNC_RESET) and (not RESET_ALL) and (rst = '0') then
v.s2_flush := '0';
v.s2_tlbstate := idle;
if tlb_rep = 1 then
v.nrep := (others => '0');
end if;
if tlb_rep = 0 then
v.touch := '0';
end if;
v.sync_isw := '0';
end if;
if (finish = '1') or (tlbi.s2valid = '0') then
tlbo_s1finished := '1';
v.s2_hm := cam_hit_all;
v.s2_entry := cam_hitaddr(entries_log-1 downto 0);
v.s2_needsync := NEEDSYNC;
v.s2_data := tlbi.transdata.data;
v.s2_read := tlbi.transdata.read;
v.s2_su := tlbi.transdata.su;
v.s2_isid := tlbi.transdata.isid;
v.s2_flush := tlbi.flush_op;
v.s2_ctx := tlbi.mmctrl1.ctx;
end if;
-- translation operation tag
mtag := TLB_CreateCamTrans( cam_addr, tlbi.transdata.read, tlbi.mmctrl1.ctx );
tlbcam_tagin := mtag;
-- flush/(probe) operation tag
ftag := TLB_CreateCamFlush( r.s2_data, tlbi.mmctrl1.ctx );
if (r.s2_flush = '1') then
tlbcam_tagin := ftag;
end if;
if r.walk_use = '1' then
transdata := r.walk_transdata;
fault := r.walk_fault;
end if;
fault.fault_read := r.s2_read;
fault.fault_su := r.s2_su;
fault.fault_isid := r.s2_isid;
fault.fault_addr := r.s2_data;
transdata.finish := finish;
transdata.accexc := '0';
twi_adata := PTE;
--# drive signals
tlbo.wbtransdata <= wb_transdata;
tlbo.transdata <= transdata;
tlbo.fault <= fault;
tlbo.nexttrans <= store;
tlbo.s1finished <= tlbo_s1finished;
twi.walk_op_ur <= twi_walk_op_ur;
twi.data <= r.s2_data;
twi.areq_ur <= twi_areq_ur;
twi.adata <= twi_adata;
twi.aaddr <= twi_aaddr;
twi.tlbmiss <= r.tlbmiss;
if tlb_rep = 0 then
lrui.flush <= r.s2_flush;
lrui.touch <= r.touch;
lrui.touchmin <= lrui_touchmin;
lrui.pos <= (others => '0');
lrui.pos(entries_log-1 downto 0) <= r.tpos;
lrui.mmctrl1 <= tlbi.mmctrl1;
end if;
dr1_addr <= r.s2_entry;
dr1_datain <= two.addr(31 downto 2);
dr1_enable <= '1';
dr1_write <= dr1write;
for i in entries-1 downto 0 loop
tlbcami(i).mmctrl <= tlbi.mmctrl1;
tlbcami(i).tagin <= tlbcam_tagin;
tlbcami(i).trans_op <= tlbi.trans_op; --tlbcam_trans_op;
tlbcami(i).wb_op <= tlbi.wb_op; --tlbcam_trans_op;
tlbcami(i).flush_op <= r.s2_flush;
tlbcami(i).mmuen <= tlbi.mmctrl1.e;
tlbcami(i).tagwrite <= tlbcam_tagwrite;
tlbcami(i).write_op <= tlbcam_write_op(i);
tlbcami(i).mset <= '0';
end loop; -- i
c <= v;
end process p0;
syncrregs : if not ASYNC_RESET generate
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
end if;
end if;
end process p1;
end generate;
asyncrregs : if ASYNC_RESET generate
p1: process (clk, rst)
begin
if rst = '0' then
r <= RRES;
elsif rising_edge(clk) then
r <= c;
end if;
end process p1;
end generate;
-- tag-cam tlb entries
tlbcam0: for i in entries-1 downto 0 generate
tag0 : mmutlbcam
generic map ( tlb_type, mmupgsz )
port map (rst, clk, tlbcami(i), tlbcamo(i));
end generate tlbcam0;
-- data-ram syncram
dataram : syncram
generic map ( tech => tech, dbits => 30, abits => entries_log, testen => scantest, custombits => ramcbits)
port map ( clk, dr1_addr, dr1_datain, dr1_dataout, dr1_enable, dr1_write,
testin
);
-- lru
lru0: if tlb_rep = 0 generate
lru : mmulru
generic map ( entries => entries)
port map ( clk, rst, lrui, lruo );
end generate lru0;
end rtl;
|
gpl-2.0
|
9c824930b3e866b359bc4ed35359bf29
| 0.530132 | 3.335985 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml40x/leon3mp.vhd
| 1 | 28,065 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.ddrpkg.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
sys_rst_in : in std_ulogic;
sys_clk : in std_ulogic; -- 100 MHz main clock
sysace_clk_in : in std_ulogic; -- System ACE clock
plb_error : out std_logic; -- IU error mode
opb_error : out std_logic; -- DSU active
flash_a23 : out std_ulogic;
sram_flash_addr : out std_logic_vector(22 downto 0);
sram_flash_data : inout std_logic_vector(31 downto 0);
sram_cen : out std_logic;
sram_bw : out std_logic_vector (0 to 3);
sram_flash_oe_n : out std_ulogic;
sram_flash_we_n : out std_ulogic;
flash_ce : out std_logic;
sram_clk : out std_ulogic;
sram_clk_fb : in std_ulogic;
sram_mode : out std_ulogic;
sram_adv_ld_n : out std_ulogic;
--pragma translate_off
iosn : out std_ulogic;
--pragma translate_on
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (3 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (3 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (31 downto 0); -- ddr data
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
gpio : inout std_logic_vector(26 downto 0); -- I/O port
phy_gtx_clk : out std_logic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_int_n : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
ps2_keyb_clk : inout std_logic;
ps2_keyb_data : inout std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
tft_lcd_clk : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
usb_csn : out std_logic;
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
sace_usb_a : out std_logic_vector(6 downto 0);
sace_mpce : out std_ulogic;
sace_usb_d : inout std_logic_vector(15 downto 0);
sace_usb_oen : out std_ulogic;
sace_usb_wen : out std_ulogic;
sysace_mpirq : in std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART
+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, srclkl : std_ulogic;
signal clkm_90, clkm_180, clkm_270 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal ethclk, egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
signal clkvga, clk1x, video_clk, dac_clk : std_ulogic;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
constant IOAEN : integer := CFG_DDRSP;
signal stati : ahbstat_in_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_preserve of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of sysace_clk_in_pad : label is true;
signal romsn : std_ulogic;
constant SPW_LOOP_BACK : integer := 0;
begin
usb_csn <= '1';
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb;
ssrref_pad : clkpad generic map (tech => padtech)
port map (sram_clk_fb, ssrclkfb);
clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (sys_clk, lclk);
srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, srclkl);
sysace_clk_in_pad : clkpad generic map (tech => padtech)
port map (sysace_clk_in, clkace);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo, open, clk1x);
clkgen1 : clkgen -- Ethernet 1G PHY clock generator
generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
egtx_clk_pad : outpad generic map (tech => padtech)
port map (phy_gtx_clk, egtx_clk);
resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock and cgo2.clklock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML401,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (plb_error, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsui.enable <= '1';
-- dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.break <= gpioo.val(11); -- South Button
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
dsuact_pad : outpad generic map (tech => padtech) port map (opb_error, ndsuact);
ndsuact <= not dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
dui.rxd <= rxd1 when gpioo.val(21) = '1' else '1';
end generate;
txd1 <= duo.txd when gpioo.val(21) = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
memi.brdyn <= '1'; memi.bexcn <= '1';
ssr0 : if CFG_SSCTRL = 1 generate
ssrctrl0 : ssrctrl generic map (hindex => 3, pindex => 0, ramaddr => 16#600#)
port map (rstn, clkm, ahbsi, ahbso(3), apbi, apbo(0), memi, memo);
end generate;
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 16#C00#, rammask => 16#FF0#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open);
end generate;
romsn <= not memo.romsn(0);
sram_adv_ld_n_pad : outpad generic map (tech => padtech)
port map (sram_adv_ld_n, gnd(0));
sram_mode_pad : outpad generic map (tech => padtech)
port map (sram_mode, gnd(0));
addr_pad : outpadv generic map (width => 23, tech => padtech)
port map (sram_flash_addr, memo.address(24 downto 2));
addr23_pad : outpad generic map (tech => padtech)
port map (flash_a23, gnd(0));
rams_pad : outpad generic map ( tech => padtech)
port map (sram_cen, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (flash_ce, romsn);
oen_pad : outpad generic map (tech => padtech)
port map (sram_flash_oe_n, memo.oen);
--pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (sram_bw, memo.wrn);
wri_pad : outpad generic map (tech => padtech)
port map (sram_flash_we_n, memo.writen);
data_pads : iopadvv generic map (tech => padtech, width => 32)
port map (sram_flash_data, memo.data, memo.vbdrive, memi.data);
ddrsp0 : if (CFG_DDRSP /= 0) generate
-- phyiconf => 1 = no diff pads for DDR clock pairs
ddrc0 : ddrspa generic map ( fabtech => CFG_FABTECH, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/10, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 32,
phyiconf => 1)
port map (
rst, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(0),
ddr_clkv, ddr_clkbv, open, ddr_clk_fb,
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkb <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 4, hirq => 10,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(4), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
sace_usb_a_pads : outpadv generic map (width => 7, tech => padtech)
port map (sace_usb_a, aceo.addr);
sace_mpce_pad : outpad generic map (tech => padtech)
port map (sace_mpce, aceo.cen);
sace_usb_d_pads : iopadv generic map (tech => padtech, width => 16)
port map (sace_usb_d, aceo.do, aceo.doen, acei.di);
sace_usb_oen_pad : outpad generic map (tech => padtech)
port map (sace_usb_oen, aceo.oen);
sace_usb_wen_pad : outpad generic map (tech => padtech)
port map (sace_usb_wen, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0'; u1i.ctsn <= '0';
u1i.rxd <= rxd1 when gpioo.val(21) = '0' else '1';
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 4*(1000000000/BOARD_FREQ), clk1 => 2*(1000000000/BOARD_FREQ),
clk2 => 1000000000/CPU_FREQ, burstlen => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadiv : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, CFG_FABTECH) port map (video_clk, clkvga);
dac_clk <= not clkvga;
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
video_clock_pad : outpad generic map ( tech => padtech)
port map (tft_lcd_clk, dac_clk);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 27)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
gpio_pads : iopadvv generic map (tech => padtech, width => 27)
port map (gpio, gpioo.dout(26 downto 0), gpioo.oen(26 downto 0),
gpioi.din(26 downto 0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
emdint_pad : inpad generic map (tech => padtech)
port map (phy_int_n, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Avnet ML401 (Virtex4 LX25) Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
972d50e1059abc049e56653e89d57772
| 0.579726 | 3.408842 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/l2cache/v2-pkg/l2cache.vhd
| 1 | 3,152 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: l2cache
-- File: libcache.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: L2-Cache component declaration
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
package l2cache is
component l2c is
generic (
hslvidx : integer := 0;
hmstidx : integer := 0;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
cached : integer := 16#0000#;
hirq : integer := 0;
cen : integer range 0 to 1 := 0;
hproten : integer range 0 to 1 := 0;
wp : integer range 0 to 1 := 0;
repl : integer range 0 to 1 := 0;
ways : integer range 1 to 4 := 1;
linesize : integer range 16 to 64 := 32;
waysize : integer range 1 to 512 := 1;
memtech : integer range 0 to NTECH := 0;
bbuswidth : integer := 128;
bioaddr : integer := 16#000#;
biomask : integer := 16#000#;
sbus : integer := 0;
mbus : integer := 1;
stat : integer range 0 to 2 := 0;
scantest : integer := 0;
arch : integer := 0;
mtrr : integer := 0;
edacen : integer range 0 to 1 := 0;
rmw : integer range 0 to 1 := 0;
ft : integer range 0 to 1 := 0;
fttiming : integer range 0 to 1 := 0;
wbmask : integer range 0 to 16#FFFF# := 16#FFFF#;
debug : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsov: in ahb_slv_out_vector;
sto : out std_logic_vector(10 downto 0);
debugo: out std_logic_vector(255*debug downto 0)
);
end component;
end;
package body l2cache is
end;
|
gpl-2.0
|
4ad82c0f5c89a97b66a4c1e7c94f39d0
| 0.563769 | 3.820606 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/iopad_ds.vhd
| 1 | 5,112 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad_ds
-- File: iopad_ds.vhd
-- Author: Nils Johan Wessman - Gaisler Research
-- Description: differential io pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iopad_ds is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; term : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iopad_ds is
signal oen : std_ulogic;
begin
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_ds_pads(tech) = 0 or
tech = axcel or tech = axdsp or tech = rhlib18t or
tech = ut25 or tech = ut130 generate
padp <= transport i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0' and slew = 0 else i when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
padn <= transport not i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0' and slew = 0 else not i when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
o <= to_X01(padp)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if is_unisim(tech) = 1 generate
x0 : unisim_iopad_ds generic map (level, slew, voltage, strength)
port map (padp, padn, i, oen, o);
end generate;
pa3 : if (tech = apa3) generate
x0 : apa3_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
igl2 : if (tech = igloo2) generate
x0 : igloo2_iopad_ds port map (padp, padn, i, oen, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_iopad_ds generic map (level, slew, voltage, strength)
port map (padp, padn, i, oen, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_dsv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopad_dsv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en, o(j));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_dsvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopad_dsvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en(j), o(j));
end generate;
end;
|
gpl-2.0
|
bea08aae57ae3d9d584d2902610f7657
| 0.62989 | 3.39217 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/cypress/ssram/package_utility.vhd
| 6 | 2,040 |
--****************************************************************
--** MODEL : package_utility **
--** COMPANY : Cypress Semiconductor **
--** REVISION: 1.0 Created new package utility model **
--** **
--****************************************************************
Library ieee,work;
Use ieee.std_logic_1164.all;
-- Use IEEE.Std_Logic_Arith.all;
use ieee.numeric_std.all;
-- Use IEEE.std_logic_TextIO.all;
--- Use work.package_timing.all;
Library Std;
Use STD.TextIO.all;
Package package_utility is
FUNCTION convert_string( S: in STRING) RETURN STD_LOGIC_VECTOR;
FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER;
End; -- package package_utility
Package body package_utility is
------------------------------------------------------------------------------------------------
--Converts string into std_logic_vector
------------------------------------------------------------------------------------------------
FUNCTION convert_string(S: in STRING) RETURN STD_LOGIC_VECTOR IS
VARIABLE result : STD_LOGIC_VECTOR(S'RANGE);
BEGIN
FOR i IN S'RANGE LOOP
IF S(i) = '0' THEN
result(i) := '0';
ELSIF S(i) = '1' THEN
result(i) := '1';
ELSIF S(i) = 'X' THEN
result(i) := 'X';
ELSE
result(i) := 'Z';
END IF;
END LOOP;
RETURN result;
END convert_string;
------------------------------------------------------------------------------------------------
--Converts std_logic_vector into integer
------------------------------------------------------------------------------------------------
FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
BEGIN
FOR i IN S'RANGE LOOP
IF S(i) = '1' THEN
result := result + (2**i);
ELSIF S(i) = '0' THEN
result := result;
ELSE
result := 0;
END IF;
END LOOP;
RETURN result;
END CONV_INTEGER1;
end package_utility;
|
gpl-2.0
|
1495149034e389304fb07f1b1717bb7f
| 0.439706 | 4.129555 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/grlib/amba/amba.vhd
| 1 | 50,128 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: amba
-- File: amba.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Modified by: Jan Andersson, Aeroflex Gaisler
-- Description: AMBA 2.0 bus signal definitions + support for plug&play
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
package amba is
-------------------------------------------------------------------------------
-- AMBA configuration
-------------------------------------------------------------------------------
-- AHBDW - AHB data with
--
-- Valid values are 32, 64, 128 and 256
--
-- The value here sets the width of the AMBA AHB data vectors for all
-- cores in the library.
--
constant AHBDW : integer := CFG_AHBDW;
-- CORE_ACDM - Enable AMBA Compliant Data Muxing in cores
--
-- Valid values are 0 and 1
--
-- 0: All GRLIB cores that use the ahbread* programs defined in this package
-- will read their data from the low part of the AHB data vector.
--
-- 1: All GRLIB cores that use the ahbread* programs defined in this package
-- will select valid data, as defined in the AMBA AHB standard, from the
-- AHB data vectors based on the address input. If a core uses a function
-- that does not have the address input, a failure will be asserted.
--
constant CORE_ACDM : integer := CFG_AHB_ACDM;
constant NAHBMST : integer := 16; -- maximum AHB masters
constant NAHBSLV : integer := 16; -- maximum AHB slaves
constant NAPBSLV : integer := 16; -- maximum APB slaves
constant NAHBIRQ : integer := 32; -- maximum interrupts
constant NAHBAMR : integer := 4; -- maximum address mapping registers
constant NAHBIR : integer := 4; -- maximum AHB identification registers
constant NAHBCFG : integer := NAHBIR + NAHBAMR; -- words in AHB config block
constant NAPBIR : integer := 1; -- maximum APB configuration words
constant NAPBAMR : integer := 1; -- maximum APB configuration words
constant NAPBCFG : integer := NAPBIR + NAPBAMR; -- words in APB config block
constant NBUS : integer := 4;
-- Number of test vector bits
constant NTESTINBITS : integer := 4+GRLIB_CONFIG_ARRAY(grlib_techmap_testin_extra);
-------------------------------------------------------------------------------
-- AMBA interface type declarations and constant
-------------------------------------------------------------------------------
subtype amba_config_word is std_logic_vector(31 downto 0);
type ahb_config_type is array (0 to NAHBCFG-1) of amba_config_word;
type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word;
-- AHB master inputs
type ahb_mst_in_type is record
hgrant : std_logic_vector(0 to NAHBMST-1); -- bus grant
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(AHBDW-1 downto 0); -- read data bus
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
testin : std_logic_vector(NTESTINBITS-1 downto 0); -- test vector for syncrams
end record;
-- AHB master outputs
type ahb_mst_out_type is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(AHBDW-1 downto 0); -- write data bus
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
hconfig : ahb_config_type; -- memory access reg.
hindex : integer range 0 to NAHBMST-1; -- diagnostic use only
end record;
-- AHB slave inputs
type ahb_slv_in_type is record
hsel : std_logic_vector(0 to NAHBSLV-1); -- slave select
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
htrans : std_logic_vector(1 downto 0); -- transfer type
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hwdata : std_logic_vector(AHBDW-1 downto 0); -- write data bus
hprot : std_logic_vector(3 downto 0); -- protection control
hready : std_ulogic; -- transfer done
hmaster : std_logic_vector(3 downto 0); -- current master
hmastlock : std_ulogic; -- locked access
hmbsel : std_logic_vector(0 to NAHBAMR-1); -- memory bank select
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
testin : std_logic_vector(NTESTINBITS-1 downto 0); -- test vector for syncrams
end record;
-- AHB slave outputs
type ahb_slv_out_type is record
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(AHBDW-1 downto 0); -- read data bus
hsplit : std_logic_vector(NAHBMST-1 downto 0); -- split completion
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
hconfig : ahb_config_type; -- memory access reg.
hindex : integer range 0 to NAHBSLV-1; -- diagnostic use only
end record;
-- array types
type ahb_mst_out_vector_type is array (natural range <>) of ahb_mst_out_type;
type ahb_mst_in_vector_type is array (natural range <>) of ahb_mst_in_type;
type ahb_slv_out_vector_type is array (natural range <>) of ahb_slv_out_type;
type ahb_slv_in_vector_type is array (natural range <>) of ahb_slv_in_type;
subtype ahb_mst_out_vector is ahb_mst_out_vector_type(NAHBMST-1 downto 0);
subtype ahb_slv_out_vector is ahb_slv_out_vector_type(NAHBSLV-1 downto 0);
subtype ahb_mst_in_vector is ahb_mst_in_vector_type(NAHBMST-1 downto 0);
subtype ahb_slv_in_vector is ahb_slv_in_vector_type(NAHBSLV-1 downto 0);
type ahb_mst_out_bus_vector is array (0 to NBUS-1) of ahb_mst_out_vector;
type ahb_slv_out_bus_vector is array (0 to NBUS-1) of ahb_slv_out_vector;
-------------------------------------------------------------------------------
-- Misc. types shared between AMBA IP cores
-------------------------------------------------------------------------------
type amba_stat_type is record
idle : std_ulogic; -- HTRANS_IDLE
busy : std_ulogic; -- HTRANS_BUSY
nseq : std_ulogic; -- HTRANS_NONSEQ
seq : std_ulogic; -- HTRANS_SEQ
read : std_ulogic; -- Read access
write : std_ulogic; -- Write access
hsize : std_logic_vector(5 downto 0); -- 8WORD downto BYTE
ws : std_ulogic; -- Wait state
-- req : std_ulogic; -- Req without gnt
retry : std_ulogic; -- RETRY response
split : std_ulogic; -- SPLIT response
spdel : std_ulogic; -- Wait after SPLIT
locked : std_ulogic; -- Locked access
hmaster: std_logic_vector(3 downto 0); -- master
end record;
-- constants
constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
constant HTRANS_BUSY: std_logic_vector(1 downto 0) := "01";
constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
constant HBURST_SINGLE: std_logic_vector(2 downto 0) := "000";
constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
constant HBURST_WRAP4: std_logic_vector(2 downto 0) := "010";
constant HBURST_INCR4: std_logic_vector(2 downto 0) := "011";
constant HBURST_WRAP8: std_logic_vector(2 downto 0) := "100";
constant HBURST_INCR8: std_logic_vector(2 downto 0) := "101";
constant HBURST_WRAP16: std_logic_vector(2 downto 0) := "110";
constant HBURST_INCR16: std_logic_vector(2 downto 0) := "111";
constant HSIZE_BYTE: std_logic_vector(2 downto 0) := "000";
constant HSIZE_HWORD: std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
constant HSIZE_DWORD: std_logic_vector(2 downto 0) := "011";
constant HSIZE_4WORD: std_logic_vector(2 downto 0) := "100";
constant HSIZE_8WORD: std_logic_vector(2 downto 0) := "101";
constant HSIZE_16WORD: std_logic_vector(2 downto 0) := "110";
constant HSIZE_32WORD: std_logic_vector(2 downto 0) := "111";
constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
-- APB slave inputs
type apb_slv_in_type is record
psel : std_logic_vector(0 to NAPBSLV-1); -- slave select
penable : std_ulogic; -- strobe
paddr : std_logic_vector(31 downto 0); -- address bus (byte)
pwrite : std_ulogic; -- write
pwdata : std_logic_vector(31 downto 0); -- write data bus
pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
testin : std_logic_vector(NTESTINBITS-1 downto 0); -- test vector for syncrams
end record;
-- APB slave outputs
type apb_slv_out_type is record
prdata : std_logic_vector(31 downto 0); -- read data bus
pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
pconfig : apb_config_type; -- memory access reg.
pindex : integer range 0 to NAPBSLV -1; -- diag use only
end record;
-- array types
type apb_slv_out_vector is array (0 to NAPBSLV-1) of apb_slv_out_type;
-- support for plug&play configuration
constant AMBA_CONFIG_VER0 : std_logic_vector(1 downto 0) := "00";
subtype amba_vendor_type is integer range 0 to 16#ff#;
subtype amba_device_type is integer range 0 to 16#3ff#;
subtype amba_version_type is integer range 0 to 16#3f#;
subtype amba_cfgver_type is integer range 0 to 3;
subtype amba_irq_type is integer range 0 to NAHBIRQ-1;
subtype ahb_addr_type is integer range 0 to 16#fff#;
constant zx : std_logic_vector(31 downto 0) := (others => '0');
constant zahbdw : std_logic_vector(AHBDW-1 downto 0) := (others => '0');
constant zxirq : std_logic_vector(NAHBIRQ-1 downto 0) := (others => '0');
constant zy : std_logic_vector(0 to 31) := (others => '0');
constant ztestin : std_logic_vector(NTESTINBITS-1 downto 0) := (others => '0');
constant apb_none : apb_slv_out_type :=
(zx, zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbm_none : ahb_mst_out_type := ( '0', '0', "00", zx,
'0', "000", "000", "0000", zahbdw, zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbm_in_none : ahb_mst_in_type := ((others => '0'), '0', (others => '0'),
zahbdw, zxirq(NAHBIRQ-1 downto 0), '0', '0', '0', '0', ztestin);
constant ahbs_none : ahb_slv_out_type := (
'1', "00", zahbdw, zx(NAHBMST-1 downto 0), zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbs_in_none : ahb_slv_in_type := (
zy(0 to NAHBSLV-1), zx, '0', "00", "000", "000", zahbdw,
"0000", '1', "0000", '0', zy(0 to NAHBAMR-1), zxirq(NAHBIRQ-1 downto 0),
'0', '0', '0', '0', ztestin);
constant ahbsv_none : ahb_slv_out_vector := (others => ahbs_none);
constant apb_slv_in_none : apb_slv_in_type := ((others => '0'), '0', (others => '0'),
'0', (others => '0'), (others => '0'),
'0', '0', '0', '0', ztestin);
constant amba_stat_none : amba_stat_type :=
('0', '0', '0', '0', '0', '0', (others => '0'),
'0', '0', '0', '0', '0', (others => '0'));
-------------------------------------------------------------------------------
-- Subprograms
-------------------------------------------------------------------------------
function ahb_device_reg(vendor : amba_vendor_type; device : amba_device_type;
cfgver : amba_cfgver_type; version : amba_version_type;
interrupt : amba_irq_type)
return std_logic_vector;
function ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return std_logic_vector;
function ahb_membar_opt(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type; enable : integer)
return std_logic_vector;
function ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return std_logic_vector;
function apb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return std_logic_vector;
function ahb_slv_dec_cache(haddr : std_logic_vector(31 downto 0);
ahbso : ahb_slv_out_vector; cached : integer)
return std_ulogic;
function ahb_slv_dec_pfetch(haddr : std_logic_vector(31 downto 0);
ahbso : ahb_slv_out_vector)
return std_ulogic;
function ahb_membar_size (addrmask : ahb_addr_type) return integer;
function ahb_iobar_size (addrmask : ahb_addr_type) return integer;
function apb_membar_size (addrmask : ahb_addr_type) return integer;
function ahbdrivedata (hdata : std_logic_vector) return std_logic_vector;
function ahbselectdata (hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2); hsize : std_logic_vector(2 downto 0))
return std_logic_vector;
function ahbreadword (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector;
procedure ahbreadword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(31 downto 0));
function ahbreadword (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector;
procedure ahbreadword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(31 downto 0));
function ahbreaddword (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector;
procedure ahbreaddword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(63 downto 0));
function ahbreaddword (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector;
procedure ahbreaddword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(63 downto 0));
function ahbread4word (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector;
procedure ahbread4word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(127 downto 0));
function ahbread4word (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector;
procedure ahbread4word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(127 downto 0));
function ahbread8word (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector;
procedure ahbread8word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(255 downto 0));
function ahbread8word (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector;
procedure ahbread8word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(255 downto 0));
function ahbreaddata (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector;
function ahbreaddata (
hdata : std_logic_vector(AHBDW-1 downto 0);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector;
procedure ahbmomux (
signal ai : in ahb_mst_out_type;
signal ao : out ahb_mst_out_type;
signal en : in std_ulogic);
procedure ahbsomux (
signal ai : in ahb_slv_out_type;
signal ao : out ahb_slv_out_type;
signal en : in std_ulogic);
procedure apbsomux (
signal ai : in apb_slv_out_type;
signal ao : out apb_slv_out_type;
signal en : in std_ulogic);
-------------------------------------------------------------------------------
-- Components
-------------------------------------------------------------------------------
component ahbctrl
generic (
defmast : integer := 0; -- default master
split : integer := 0; -- split support
rrobin : integer := 0; -- round-robin arbitration
timeout : integer range 0 to 255 := 0; -- HREADY timeout
ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address
iomask : ahb_addr_type := 16#fff#; -- I/O area address mask
cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address
cfgmask : ahb_addr_type := 16#ff0#; -- config area address mask
nahbm : integer range 1 to NAHBMST := NAHBMST; -- number of masters
nahbs : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves
ioen : integer range 0 to 15 := 1; -- enable I/O area
disirq : integer range 0 to 1 := 0; -- disable interrupt routing
fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts
debug : integer range 0 to 2 := 2; -- print config to console
fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding
icheck : integer range 0 to 1 := 1;
devid : integer := 0; -- unique device ID
enbusmon : integer range 0 to 1 := 0; --enable bus monitor
assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings
asserterr : integer range 0 to 1 := 0; --enable assertions for errors
hmstdisable : integer := 0; --disable master checks
hslvdisable : integer := 0; --disable slave checks
arbdisable : integer := 0; --disable arbiter checks
mprio : integer := 0; --master with highest priority
mcheck : integer range 0 to 2 := 1; --check memory map for intersects
ccheck : integer range 0 to 1 := 1; --perform sanity checks on pnp config
acdm : integer := 0; --AMBA compliant data muxing (for hsize > word)
index : integer := 0; --index for trace print-out
ahbtrace : integer := 0; --AHB trace enable
hwdebug : integer := 0;
fourgslv : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
msti : out ahb_mst_in_type;
msto : in ahb_mst_out_vector;
slvi : out ahb_slv_in_type;
slvo : in ahb_slv_out_vector;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
scanen : in std_ulogic := '0';
testoen : in std_ulogic := '1';
testsig : in std_logic_vector(1+GRLIB_CONFIG_ARRAY(grlib_techmap_testin_extra) downto 0) := (others => '0')
);
end component;
component ahbxb is
generic(
defmast : integer := 0; -- default master
timeout : integer range 0 to 255 := 0; -- HREADY timeout
ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address
iomask : ahb_addr_type := 16#fff#; -- I/O area address mask
cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address
cfgmask : ahb_addr_type := 16#ff0#; -- config area address mask
nahbm : integer range 1 to NAHBMST := NAHBMST; -- number of masters
nahbs : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves
ioen : integer range 0 to 15 := 1; -- enable I/O area
disirq : integer range 0 to 1 := 0; -- disable interrupt routing
fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts
debug : integer range 0 to 2 := 2; -- report cores to console
fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding
icheck : integer range 0 to 1 := 1;
devid : integer := 0; -- unique device ID
enbusmon : integer range 0 to 1 := 0; --enable bus monitor
assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings
asserterr : integer range 0 to 1 := 0; --enable assertions for errors
hmstdisable : integer := 0; --disable master checks
hslvdisable : integer := 0; --disable slave checks
arbdisable : integer := 0; --disable arbiter checks
mprio : integer := 0; --master with highest priority
mcheck : integer range 0 to 2 := 1; --check memory map for intersects
ccheck : integer range 0 to 1 := 1; --perform sanity checks on pnp config
index : integer := 0; --Index for trace print-out
ahbtrace : integer := 0; --AHB trace enable
hwdebug : integer := 0; --Hardware debug
fourgslv : integer := 0; --1=Single slave with single 4 GB bar
l2en : integer := 0; --enable l2 cache multiport decoding
l2bhindex : integer range 0 to NAHBSLV := 0; --base index for the l2 cache slaves
l2num : integer := 4; --number of l2 caches in system
l2linesize : integer := 32;--number of bytes in an l2 cache line
l2hmbsel : integer := 0 --index of L2 memory back
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
msti : out ahb_mst_in_vector;
msto : in ahb_mst_out_vector;
slvi : out ahb_slv_in_vector;
slvo : in ahb_slv_out_vector;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
scanen : in std_ulogic := '0';
testoen : in std_ulogic := '1';
testsig : in std_logic_vector(1+GRLIB_CONFIG_ARRAY(grlib_techmap_testin_extra) downto 0) := (others => '0')
);
end component;
component apbctrl
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
nslaves : integer range 1 to NAPBSLV := NAPBSLV;
debug : integer range 0 to 2 := 2; -- print config to console
icheck : integer range 0 to 1 := 1;
enbusmon : integer range 0 to 1 := 0;
asserterr : integer range 0 to 1 := 0;
assertwarn : integer range 0 to 1 := 0;
pslvdisable : integer := 0;
mcheck : integer range 0 to 1 := 1;
ccheck : integer range 0 to 1 := 1
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_slv_in_type;
ahbo : out ahb_slv_out_type;
apbi : out apb_slv_in_type;
apbo : in apb_slv_out_vector
);
end component;
component ahbctrl_mb
generic (
defmast : integer := 0; -- default master
split : integer := 0; -- split support
rrobin : integer := 0; -- round-robin arbitration
timeout : integer range 0 to 255 := 0; -- HREADY timeout
ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address
iomask : ahb_addr_type := 16#fff#; -- I/O area address mask
cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address
cfgmask : ahb_addr_type := 16#ff0#; -- config area address mask
nahbm : integer range 1 to NAHBMST := NAHBMST; -- number of masters
nahbs : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves
ioen : integer range 0 to 15 := 1; -- enable I/O area
disirq : integer range 0 to 1 := 0; -- disable interrupt routing
fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts
debug : integer range 0 to 2 := 2; -- report cores to console
fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding
busndx : integer range 0 to 3 := 0;
icheck : integer range 0 to 1 := 1;
devid : integer := 0; -- unique device ID
enbusmon : integer range 0 to 1 := 0; --enable bus monitor
assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings
asserterr : integer range 0 to 1 := 0; --enable assertions for errors
hmstdisable : integer := 0; --disable master checks
hslvdisable : integer := 0; --disable slave checks
arbdisable : integer := 0; --disable arbiter checks
mprio : integer := 0; --master with highest priority
mcheck : integer range 0 to 2 := 1; --check memory map for intersect
ccheck : integer range 0 to 1 := 1; --perform sanity checks on pnp config
acdm : integer := 0 --AMBA compliant data muxing (for hsize > word)
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
msti : out ahb_mst_in_type;
msto : in ahb_mst_out_bus_vector;
slvi : out ahb_slv_in_type;
slvo : in ahb_slv_out_bus_vector;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
scanen : in std_ulogic := '0';
testoen : in std_ulogic := '1'
);
end component;
component ahbdefmst
generic ( hindex : integer range 0 to NAHBMST-1 := 0);
port ( ahbmo : out ahb_mst_out_type);
end component;
type ahb_dma_in_type is record
address : std_logic_vector(31 downto 0);
wdata : std_logic_vector(AHBDW-1 downto 0);
start : std_ulogic;
burst : std_ulogic;
write : std_ulogic;
busy : std_ulogic;
irq : std_ulogic;
size : std_logic_vector(2 downto 0);
end record;
type ahb_dma_out_type is record
start : std_ulogic;
active : std_ulogic;
ready : std_ulogic;
retry : std_ulogic;
mexc : std_ulogic;
haddr : std_logic_vector(9 downto 0);
rdata : std_logic_vector(AHBDW-1 downto 0);
end record;
component ahbmst
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := 1;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in ahb_dma_in_type;
dmao : out ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
-- pragma translate_off
component ahbmon is
generic(
asserterr : integer range 0 to 1 := 1;
assertwarn : integer range 0 to 1 := 1;
hmstdisable : integer := 0;
hslvdisable : integer := 0;
arbdisable : integer := 0;
nahbm : integer range 0 to NAHBMST := NAHBMST;
nahbs : integer range 0 to NAHBSLV := NAHBSLV;
ebterm : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : in ahb_mst_out_vector;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
err : out std_ulogic);
end component;
component apbmon is
generic(
asserterr : integer range 0 to 1 := 1;
assertwarn : integer range 0 to 1 := 1;
pslvdisable : integer := 0;
napb : integer range 0 to NAPBSLV := NAPBSLV
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : in apb_slv_out_vector;
err : out std_ulogic);
end component;
component ambamon is
generic(
asserterr : integer range 0 to 1 := 1;
assertwarn : integer range 0 to 1 := 1;
hmstdisable : integer := 0;
hslvdisable : integer := 0;
pslvdisable : integer := 0;
arbdisable : integer := 0;
nahbm : integer range 0 to NAHBMST := NAHBMST;
nahbs : integer range 0 to NAHBSLV := NAHBSLV;
napb : integer range 0 to NAPBSLV := NAPBSLV;
ebterm : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : in ahb_mst_out_vector;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
apbi : in apb_slv_in_type;
apbo : in apb_slv_out_vector;
err : out std_ulogic);
end component;
subtype vendor_description is string(1 to 24);
subtype device_description is string(1 to 31);
type device_table_type is array (0 to 1023) of device_description;
type vendor_library_type is record
vendorid : amba_vendor_type;
vendordesc : vendor_description;
device_table : device_table_type;
end record;
type device_array is array (0 to 255) of vendor_library_type;
-- pragma translate_on
end;
package body amba is
function ahb_device_reg(vendor : amba_vendor_type; device : amba_device_type;
cfgver : amba_cfgver_type; version : amba_version_type;
interrupt : amba_irq_type)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
case cfgver is
when 0 =>
cfg(31 downto 24) := std_logic_vector(to_unsigned(vendor, 8));
cfg(23 downto 12) := std_logic_vector(to_unsigned(device, 12));
cfg(11 downto 10) := std_logic_vector(to_unsigned(cfgver, 2));
cfg( 9 downto 5) := std_logic_vector(to_unsigned(version, 5));
cfg( 4 downto 0) := std_logic_vector(to_unsigned(interrupt, 5));
when others => cfg := (others => '0');
end case;
return(cfg);
end;
function ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
cfg(31 downto 20) := std_logic_vector(to_unsigned(memaddr, 12));
cfg(19 downto 16) := "00" & prefetch & cache;
cfg(15 downto 4) := std_logic_vector(to_unsigned(addrmask, 12));
cfg( 3 downto 0) := "0010";
return(cfg);
end;
function ahb_membar_opt(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type; enable : integer)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
cfg := (others => '0');
if enable /= 0 then
return (ahb_membar(memaddr, prefetch, cache, addrmask));
else return(cfg); end if;
end;
function ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
cfg(31 downto 20) := std_logic_vector(to_unsigned(memaddr, 12));
cfg(19 downto 16) := "0000";
cfg(15 downto 4) := std_logic_vector(to_unsigned(addrmask, 12));
cfg( 3 downto 0) := "0011";
return(cfg);
end;
function apb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
cfg(31 downto 20) := std_logic_vector(to_unsigned(memaddr, 12));
cfg(19 downto 16) := "0000";
cfg(15 downto 4) := std_logic_vector(to_unsigned(addrmask, 12));
cfg( 3 downto 0) := "0001";
return(cfg);
end;
function ahb_slv_dec_cache(haddr : std_logic_vector(31 downto 0);
ahbso : ahb_slv_out_vector; cached : integer)
return std_ulogic is
variable hcache : std_ulogic;
variable ctbl : std_logic_vector(15 downto 0);
begin
hcache := '0'; ctbl := (others => '0');
if cached = 0 then
for i in 0 to NAHBSLV-1 loop
for j in NAHBAMR to NAHBCFG-1 loop
if (ahbso(i).hconfig(j)(16) = '1') and
(ahbso(i).hconfig(j)(15 downto 4) /= "000000000000")
then
if (haddr(31 downto 20) and ahbso(i).hconfig(j)(15 downto 4)) =
(ahbso(i).hconfig(j)(31 downto 20) and ahbso(i).hconfig(j)(15 downto 4)) then
hcache := '1';
end if;
end if;
end loop;
end loop;
else
ctbl := conv_std_logic_vector(cached, 16);
hcache := ctbl(conv_integer(haddr(31 downto 28)));
end if;
return(hcache);
end;
function ahb_slv_dec_pfetch(haddr : std_logic_vector(31 downto 0);
ahbso : ahb_slv_out_vector)
return std_ulogic is
variable pfetch : std_ulogic;
begin
pfetch := '0';
for i in 0 to NAHBSLV-1 loop
for j in NAHBAMR to NAHBCFG-1 loop
if ((ahbso(i).hconfig(j)(17) = '1') and
(ahbso(i).hconfig(j)(15 downto 4) /= "000000000000"))
then
if (haddr(31 downto 20) and ahbso(i).hconfig(j)(15 downto 4)) =
(ahbso(i).hconfig(j)(31 downto 20) and ahbso(i).hconfig(j)(15 downto 4)) then
pfetch := '1';
end if;
end if;
end loop;
end loop;
return(pfetch);
end;
function ahb_membar_size (addrmask : ahb_addr_type) return integer is
begin
if addrmask = 0 then return 0; end if;
return (4096 - addrmask) * 1024 * 1024;
end;
function ahb_iobar_size (addrmask : ahb_addr_type) return integer is
begin
return (4096 - addrmask) * 256;
end;
function apb_membar_size (addrmask : ahb_addr_type) return integer is
begin
return ahb_iobar_size(addrmask);
end;
-- purpose: Duplicates 'hdata' to suite AHB data width. If the input vector's
-- length exceeds AHBDW the low part is returned.
function ahbdrivedata (
hdata : std_logic_vector)
return std_logic_vector is
variable data : std_logic_vector(AHBDW-1 downto 0);
begin -- ahbdrivedata
if AHBDW < hdata'length then
data := hdata(AHBDW+hdata'low-1 downto hdata'low);
else
for i in 0 to AHBDW/hdata'length-1 loop
data(hdata'length-1+hdata'length*i downto hdata'length*i) := hdata;
end loop;
end if;
return data;
end ahbdrivedata;
-- Takes in AHB data vector 'hdata' and returns valid data on the full
-- data vector output based on 'haddr' and 'hsize' inputs together with
-- GRLIB AHB bus width. The function works down to word granularity.
function ahbselectdata (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
variable ret : std_logic_vector(AHBDW-1 downto 0);
begin -- ahbselectdata
ret := hdata;
case hsize is
when HSIZE_8WORD =>
if AHBDW = 256 then ret := hdata; end if;
when HSIZE_4WORD =>
if AHBDW = 256 then
if haddr(4) = '0' then ret := ahbdrivedata(hdata(AHBDW-1 downto AHBDW/2));
else ret := ahbdrivedata(hdata(AHBDW/2-1 downto 0)); end if;
end if;
when HSIZE_DWORD =>
if AHBDW = 256 then
case haddr(4 downto 3) is
when "00" => ret := ahbdrivedata(hdata(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => ret := ahbdrivedata(hdata(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => ret := ahbdrivedata(hdata(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => ret := ahbdrivedata(hdata(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
elsif AHBDW = 128 then
if haddr(3) = '0' then ret := ahbdrivedata(hdata(AHBDW-1 downto AHBDW/2));
else ret := ahbdrivedata(hdata(AHBDW/2-1 downto 0)); end if;
end if;
when others =>
if AHBDW = 256 then
case haddr(4 downto 2) is
when "000" => ret := ahbdrivedata(hdata(8*(AHBDW/8)-1 downto 7*(AHBDW/8)));
when "001" => ret := ahbdrivedata(hdata(7*(AHBDW/8)-1 downto 6*(AHBDW/8)));
when "010" => ret := ahbdrivedata(hdata(6*(AHBDW/8)-1 downto 5*(AHBDW/8)));
when "011" => ret := ahbdrivedata(hdata(5*(AHBDW/8)-1 downto 4*(AHBDW/8)));
when "100" => ret := ahbdrivedata(hdata(4*(AHBDW/8)-1 downto 3*(AHBDW/8)));
when "101" => ret := ahbdrivedata(hdata(3*(AHBDW/8)-1 downto 2*(AHBDW/8)));
when "110" => ret := ahbdrivedata(hdata(2*(AHBDW/8)-1 downto 1*(AHBDW/8)));
when others => ret := ahbdrivedata(hdata(1*(AHBDW/8)-1 downto 0*(AHBDW/8)));
end case;
elsif AHBDW = 128 then
case haddr(3 downto 2) is
when "00" => ret := ahbdrivedata(hdata(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => ret := ahbdrivedata(hdata(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => ret := ahbdrivedata(hdata(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => ret := ahbdrivedata(hdata(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
elsif AHBDW = 64 then
if haddr(2) = '0' then ret := ahbdrivedata(hdata(AHBDW-1 downto AHBDW/2));
else ret := ahbdrivedata(hdata(AHBDW/2-1 downto 0)); end if;
end if;
end case;
return ret;
end ahbselectdata;
-- Description of ahbread* functions and procedures.
--
-- The ahbread* subprograms with an 'haddr' input selects the valid slice of
-- data from the AHB data vector, 'hdata', based on the 'haddr' input if
-- CORE_ACDM is set to 1 (see top of this package). Otherwise the low part of
-- the AHB data vector will be returned.
--
-- The ahbread* subprograms that do not have a 'haddr' input will always
-- return the low slice of the 'hdata' input. These subprograms will assert a
-- failure if CORE_ACDM is set to 1.
--
function ahbreadword (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector is
variable data : std_logic_vector(31 downto 0);
begin
if CORE_ACDM = 1 then data := ahbselectdata(hdata, haddr, HSIZE_WORD)(31 downto 0);
else data := hdata(31 downto 0); end if;
return data;
end ahbreadword;
procedure ahbreadword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(31 downto 0)) is
begin
data := ahbreadword(hdata, haddr);
end ahbreadword;
function ahbreadword (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector is
variable data : std_logic_vector(31 downto 0);
begin
-- pragma translate_off
assert CORE_ACDM = 0
report "ahbreadword without address input used when CORE_ACDM /= 0"
severity failure;
-- pragma translate_on
data := hdata(31 downto 0);
return data;
end ahbreadword;
procedure ahbreadword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(31 downto 0)) is
begin
data := ahbreadword(hdata);
end ahbreadword;
function ahbreaddword (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector is
variable data : std_logic_vector(255 downto 0);
begin
-- pragma translate_off
assert AHBDW > 32
report "ahbreaddword can not be used in system with AHB data width < 64"
severity failure;
-- pragma translate_on
if AHBDW = 256 then
if CORE_ACDM = 1 then
data(AHBDW/4-1 downto 0) :=
ahbselectdata(hdata, haddr, HSIZE_DWORD)(AHBDW/4-1 downto 0);
else
data(AHBDW/4-1 downto 0) := hdata(AHBDW/4-1 downto 0);
end if;
elsif AHBDW = 128 then
if CORE_ACDM = 1 then
data(AHBDW/2-1 downto 0) :=
ahbselectdata(hdata, haddr, HSIZE_DWORD)(AHBDW/2-1 downto 0);
else
data(AHBDW/2-1 downto 0) := hdata(AHBDW/2-1 downto 0);
end if;
elsif AHBDW = 64 then
if CORE_ACDM = 1 then
data(AHBDW-1 downto 0) :=
ahbselectdata(hdata, haddr, HSIZE_DWORD)(AHBDW-1 downto 0);
else
data(AHBDW-1 downto 0) := hdata(AHBDW-1 downto 0);
end if;
end if;
return data(63 downto 0);
end ahbreaddword;
procedure ahbreaddword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(63 downto 0)) is
begin
data := ahbreaddword(hdata, haddr);
end ahbreaddword;
function ahbreaddword (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector is
variable data : std_logic_vector(255 downto 0);
begin
-- pragma translate_off
assert AHBDW > 32
report "ahbreaddword can not be used in system with AHB data width < 64"
severity failure;
assert CORE_ACDM = 0
report "ahbreaddword without address input used when CORE_ACDM /= 0"
severity failure;
-- pragma translate_on
if AHBDW = 256 then
data(AHBDW/4-1 downto 0) := hdata(AHBDW/4-1 downto 0);
elsif AHBDW = 128 then
data(AHBDW/2-1 downto 0) := hdata(AHBDW/2-1 downto 0);
elsif AHBDW = 64 then
data(AHBDW-1 downto 0) := hdata(AHBDW-1 downto 0);
end if;
return data(63 downto 0);
end ahbreaddword;
procedure ahbreaddword (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(63 downto 0)) is
begin
data := ahbreaddword(hdata);
end ahbreaddword;
function ahbread4word (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector is
variable data : std_logic_vector(255 downto 0);
begin
-- pragma translate_off
assert AHBDW > 64
report "ahbread4word can not be used in system with AHB data width < 128 bits"
severity failure;
-- pragma translate_on
if AHBDW = 256 then
if CORE_ACDM = 1 then
data(AHBDW/2-1 downto 0) :=
ahbselectdata(hdata, haddr, HSIZE_4WORD)(AHBDW/2-1 downto 0);
else
data(AHBDW/2-1 downto 0) := hdata(AHBDW/2-1 downto 0);
end if;
elsif AHBDW = 128 then
if CORE_ACDM = 1 then
data(AHBDW-1 downto 0) :=
ahbselectdata(hdata, haddr, HSIZE_4WORD)(AHBDW-1 downto 0);
else
data(AHBDW-1 downto 0) := hdata(AHBDW-1 downto 0);
end if;
end if;
return data(127 downto 0);
end ahbread4word;
procedure ahbread4word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(127 downto 0)) is
begin
data := ahbread4word(hdata, haddr);
end ahbread4word;
function ahbread4word (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector is
variable data : std_logic_vector(255 downto 0);
begin
-- pragma translate_off
assert AHBDW > 64
report "ahbread4word can not be used in system with AHB data width < 128 bits"
severity failure;
assert CORE_ACDM = 0
report "ahbread4word without address input used when CORE_ACDM /= 0"
severity failure;
-- pragma translate_on
if AHBDW = 256 then
data(AHBDW/2-1 downto 0) := hdata(AHBDW/2-1 downto 0);
elsif AHBDW = 128 then
data(AHBDW-1 downto 0) := hdata(AHBDW-1 downto 0);
end if;
return data(127 downto 0);
end ahbread4word;
procedure ahbread4word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(127 downto 0)) is
begin
data := ahbread4word(hdata);
end ahbread4word;
function ahbread8word (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector is
variable data : std_logic_vector(AHBDW-1 downto 0);
begin
-- pragma translate_off
assert AHBDW > 128
report "ahbread8word can not be used in system with AHB data width < 256 bits"
severity failure;
-- pragma translate_on
if CORE_ACDM = 1 then
data(AHBDW-1 downto 0) := ahbselectdata(hdata, haddr, HSIZE_8WORD)(AHBDW-1 downto 0);
else
data(AHBDW-1 downto 0) := hdata(AHBDW-1 downto 0);
end if;
return data;
end ahbread8word;
procedure ahbread8word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(255 downto 0)) is
begin
data := ahbread8word(hdata, haddr);
end ahbread8word;
function ahbread8word (
hdata : std_logic_vector(AHBDW-1 downto 0))
return std_logic_vector is
variable data : std_logic_vector(AHBDW-1 downto 0);
begin
-- pragma translate_off
assert AHBDW > 128
report "ahbread8word can not be used in system with AHB data width < 256 bits"
severity failure;
assert CORE_ACDM = 0
report "ahbread8word without address input used when CORE_ACDM /= 0"
severity failure;
-- pragma translate_on
data(AHBDW-1 downto 0) := hdata(AHBDW-1 downto 0);
return data;
end ahbread8word;
procedure ahbread8word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
data : out std_logic_vector(255 downto 0)) is
begin
data := ahbread8word(hdata);
end ahbread8word;
function ahbreaddata (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
begin
case hsize is
when HSIZE_8WORD =>
return ahbread8word(hdata, haddr);
when HSIZE_4WORD =>
return ahbread4word(hdata, haddr);
when HSIZE_DWORD =>
return ahbreaddword(hdata, haddr);
when others => null;
end case;
return ahbreadword(hdata, haddr);
end ahbreaddata;
function ahbreaddata (
hdata : std_logic_vector(AHBDW-1 downto 0);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
begin
case hsize is
when HSIZE_8WORD =>
return ahbread8word(hdata);
when HSIZE_4WORD =>
return ahbread4word(hdata);
when HSIZE_DWORD =>
return ahbreaddword(hdata);
when others => null;
end case;
return ahbreadword(hdata);
end ahbreaddata;
-- a*mux below drives their amba output records with the amba input record if
-- the en input is '1'. Otherwise the amba output record is driven to an idle
-- state. Plug'n'play information is kept constant.
procedure ahbmomux (
signal ai : in ahb_mst_out_type;
signal ao : out ahb_mst_out_type;
signal en : in std_ulogic) is
begin
if en = '1' then ao <= ai;
else ao <= ahbm_none; end if;
ao.haddr <= ai.haddr;
ao.hwrite <= ai.hwrite;
ao.hsize <= ai.hsize;
ao.hprot <= ai.hprot;
ao.hwdata <= ai.hwdata;
ao.hconfig <= ai.hconfig;
ao.hindex <= ai.hindex;
end ahbmomux;
procedure ahbsomux (
signal ai : in ahb_slv_out_type;
signal ao : out ahb_slv_out_type;
signal en : in std_ulogic) is
begin
if en = '1' then ao <= ai;
else ao <= ahbs_none; end if;
ao.hrdata <= ai.hrdata;
ao.hconfig <= ai.hconfig;
ao.hindex <= ai.hindex;
end ahbsomux;
procedure apbsomux (
signal ai : in apb_slv_out_type;
signal ao : out apb_slv_out_type;
signal en : in std_ulogic) is
begin
if en = '1' then ao <= ai;
else ao <= apb_none; end if;
ao.prdata <= ai.prdata;
ao.pconfig <= ai.pconfig;
ao.pindex <= ai.pindex;
end apbsomux;
end;
|
gpl-2.0
|
ce052057c987e8a73c88a23bce33c780
| 0.58991 | 3.750973 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/skew_outpad.vhd
| 1 | 2,121 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: skew_outpad
-- File: skew_outpad.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity skew_outpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end;
architecture rtl of skew_outpad is
signal padx, gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
gen0 : if has_pads(tech) = 0 generate
pad <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when slew = 0 else i;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_skew_outpad generic map (level, slew, voltage, strength, skew) port map (pad, i, rst, o);
end generate;
end;
|
gpl-2.0
|
bd51aeda370a11169cf92b550306c38a
| 0.619048 | 3.964486 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-jopdesign-ep1c12/cycore12.vhd
| 3 | 9,236 |
--
-- cycore12_top.vhd
--
-- top level for cycore borad
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cycore12 is
generic (
exta_width : integer := 3; -- length of exta part in JOP microcode
io_addr_bits : integer := 7; -- address bits of internal io
ram_cnt : integer := 2; -- clock cycles for external ram
-- rom_cnt : integer := 3; -- clock cycles for external rom OK for 20 MHz
rom_cnt : integer := 15; -- clock cycles for external rom for 100 MHz
jpc_width : integer := 12; -- address bits of java bytecode pc = cache size
block_bits : integer := 4 -- 2*block_bits is number of cache blocks
);
port (
clk : in std_logic;
--
-- serial interface
--
ser_txd : out std_logic;
ser_rxd : in std_logic;
ser_ncts : in std_logic;
ser_nrts : out std_logic;
--
-- watchdog
--
wd : out std_logic;
freeio : out std_logic;
--
-- two ram banks
--
rama_a : out std_logic_vector(17 downto 0);
rama_d : inout std_logic_vector(15 downto 0);
rama_ncs : out std_logic;
rama_noe : out std_logic;
rama_nlb : out std_logic;
rama_nub : out std_logic;
rama_nwe : out std_logic;
ramb_a : out std_logic_vector(17 downto 0);
ramb_d : inout std_logic_vector(15 downto 0);
ramb_ncs : out std_logic;
ramb_noe : out std_logic;
ramb_nlb : out std_logic;
ramb_nub : out std_logic;
ramb_nwe : out std_logic;
--
-- config/program flash and big nand flash
--
fl_a : out std_logic_vector(18 downto 0);
fl_d : inout std_logic_vector(7 downto 0);
fl_ncs : out std_logic;
fl_ncsb : out std_logic;
fl_noe : out std_logic;
fl_nwe : out std_logic;
fl_rdy : in std_logic;
--
-- I/O pins of board
--
io_b : inout std_logic_vector(10 downto 1);
io_l : inout std_logic_vector(20 downto 1);
io_r : inout std_logic_vector(20 downto 1);
io_t : inout std_logic_vector(6 downto 1)
);
end cycore12;
architecture rtl of cycore12 is
--
-- components:
--
component pll is
generic (multiply_by : natural; divide_by : natural);
port (
inclk0 : in std_logic;
c0 : out std_logic
);
end component;
component leon3mp is
port (
resetn : in std_ulogic;
clk : in std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(7 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emddis : out std_logic;
epwrdwn : out std_ulogic;
ereset : out std_ulogic;
esleep : out std_ulogic;
epause : out std_ulogic;
pci_rst : inout std_ulogic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
can_stb : out std_ulogic;
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2)
);
end component;
--
-- Signals
--
signal clk_int : std_logic;
signal int_res : std_logic;
signal not_int_res : std_logic;
signal res_cnt : unsigned(2 downto 0) := "000"; -- for the simulation
signal ramsn, ramoen : std_logic_vector(4 downto 0);
signal wd_out : std_logic;
-- for generation of internal reset
attribute altera_attribute : string;
attribute altera_attribute of res_cnt : signal is "POWER_UP_LEVEL=LOW";
--
-- LEON3 signals
--
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ram_dout_en : std_logic;
signal ram_ncs : std_logic;
signal ram_nwe : std_logic;
signal ram_noe : std_logic;
signal oen : std_logic;
signal writen : std_logic;
begin
--
-- intern reset
-- no extern reset, epm7064 has too less pins
--
process(clk_int)
begin
if rising_edge(clk_int) then
if (res_cnt/="111") then
res_cnt <= res_cnt+1;
end if;
int_res <= not res_cnt(0) or not res_cnt(1) or not res_cnt(2);
end if;
end process;
not_int_res <= not int_res;
--
-- components
--
-- pll_inst : pll generic map(
-- multiply_by => pll_mult,
-- divide_by => pll_div
-- )
-- port map (
-- inclk0 => clk,
-- c0 => clk_int
-- );
clk_int <= clk;
-- sp_ov indicates stack overflow
-- We can use the wd LED
-- wd <= sp_ov;
cmp_leon: leon3mp
port map (
resetn => not_int_res,
clk => clk_int,
pllref => '0',
errorn => open,
address => address,
data(15 downto 0) => rama_d,
data(31 downto 16) => ramb_d,
sa => open,
sd => open,
sdclk => open,
sdcke => open,
sdcsn => open,
sdwen => open,
sdrasn => open,
sdcasn => open,
sddqm => open,
dsutx => ser_txd,
dsurx => ser_rxd,
dsuen => '1',
dsubre => '0',
dsuact => open,
-- unused pins to not optimize serial line away
txd1 => wd,
rxd1 => fl_rdy,
txd2 => open,
rxd2 => '0',
ramsn => ramsn,
ramoen => ramoen,
rwen => open,
oen => open,
writen => ram_nwe,
read => open,
iosn => open,
romsn => open,
gpio => open,
emdio => open,
etx_clk => '0',
erx_clk => '0',
erxd => (others => '0'),
erx_dv => '0',
erx_er => '0',
erx_col => '0',
erx_crs => '0',
etxd => open,
etx_en => open,
etx_er => open,
emdc => open,
emddis => open,
epwrdwn => open,
ereset => open,
esleep => open,
epause => open,
pci_rst => open,
pci_clk => '0',
pci_gnt => '0',
pci_idsel => '0',
pci_lock => open,
pci_ad => open,
pci_cbe => open,
pci_frame => open,
pci_irdy => open,
pci_trdy => open,
pci_devsel => open,
pci_stop => open,
pci_perr => open,
pci_par => open,
pci_req => open,
pci_serr => open,
pci_host => '0',
pci_66 => '0',
pci_arb_req => (others => '0'),
pci_arb_gnt => open,
can_txd => open,
can_rxd => '0',
can_stb => open,
spw_clk => '0',
spw_rxd => (others => '0'),
spw_rxdn => (others => '0'),
spw_rxs => (others => '0'),
spw_rxsn => (others => '0'),
spw_txd => open,
spw_txdn => open,
spw_txs => open,
spw_txsn => open
);
ser_nrts <= '0';
ram_ncs <= ramsn(0);
ram_noe <= ramoen(0);
rama_a <= address(19 downto 2);
rama_ncs <= ram_ncs;
rama_noe <= ram_noe;
rama_nwe <= ram_nwe;
rama_nlb <= '0';
rama_nub <= '0';
ramb_a <= address(19 downto 2);
ramb_ncs <= ram_ncs;
ramb_noe <= ram_noe;
ramb_nwe <= ram_nwe;
ramb_nlb <= '0';
ramb_nub <= '0';
freeio <= 'Z';
fl_ncs <= '1';
fl_ncsb <= '1';
end rtl;
|
gpl-2.0
|
35c49d0d1d7f5421509c8f9f51645068
| 0.563447 | 2.727702 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-terasic-de4/ddr2if.vhd
| 1 | 9,430 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
entity ddr2if is
generic (
hindex: integer;
haddr: integer := 16#400#;
hmask: integer := 16#000#;
ahbbits: integer := ahbdw;
burstlen: integer := 8
);
port (
pll_ref_clk : in std_ulogic;
global_reset_n : in std_ulogic;
mem_a : out std_logic_vector(13 downto 0);
mem_ba : out std_logic_vector(2 downto 0);
mem_ck : out std_logic_vector(1 downto 0);
mem_ck_n : out std_logic_vector(1 downto 0);
mem_cke : out std_logic;
mem_cs_n : out std_logic;
mem_dm : out std_logic_vector(7 downto 0);
mem_ras_n : out std_logic;
mem_cas_n : out std_logic;
mem_we_n : out std_logic;
mem_dq : inout std_logic_vector(63 downto 0);
mem_dqs : inout std_logic_vector(7 downto 0);
mem_dqs_n : inout std_logic_vector(7 downto 0);
mem_odt : out std_logic;
ahb_clk : in std_ulogic;
ahb_rst : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
oct_rdn : in std_logic;
oct_rup : in std_logic
);
end;
architecture rtl of ddr2if is
component ddr2ctrl is
port (
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
global_reset_n : in std_logic := '0'; -- global_reset.reset_n
soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n
afi_clk : out std_logic; -- afi_clk.clk
afi_half_clk : out std_logic; -- afi_half_clk.clk
afi_reset_n : out std_logic; -- afi_reset.reset_n
afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n
mem_a : out std_logic_vector(13 downto 0); -- memory.mem_a
mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
mem_dq : inout std_logic_vector(63 downto 0) := (others => '0'); -- .mem_dq
mem_dqs : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
avl_ready : out std_logic; -- avl.waitrequest_n
avl_burstbegin : in std_logic := '0'; -- .beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => '0'); -- .address
avl_rdata_valid : out std_logic; -- .readdatavalid
avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
avl_wdata : in std_logic_vector(255 downto 0) := (others => '0'); -- .writedata
avl_be : in std_logic_vector(31 downto 0) := (others => '0'); -- .byteenable
avl_read_req : in std_logic := '0'; -- .read
avl_write_req : in std_logic := '0'; -- .write
avl_size : in std_logic_vector(3 downto 0) := (others => '0'); -- .burstcount
local_init_done : out std_logic; -- status.local_init_done
local_cal_success : out std_logic; -- .local_cal_success
local_cal_fail : out std_logic; -- .local_cal_fail
oct_rdn : in std_logic := '0'; -- oct.rdn
oct_rup : in std_logic := '0' -- .rup
);
end component ddr2ctrl;
signal vcc: std_ulogic;
signal afi_clk, afi_half_clk, afi_reset_n: std_ulogic;
signal local_init_done, local_cal_success, local_cal_fail: std_ulogic;
signal ck_p_arr, ck_n_arr : std_logic_vector(1 downto 0);
signal ras_n_arr, cas_n_arr, we_n_arr, odt_arr, cke_arr, cs_arr: std_logic_vector(0 downto 0);
signal avlsi: ddravl_slv_in_type;
signal avlso: ddravl_slv_out_type;
signal rdata, wdata : std_logic_vector(255 downto 0);
signal be: std_logic_vector(31 downto 0);
begin
vcc <= '1';
mem_ras_n <= ras_n_arr(0);
mem_cas_n <= cas_n_arr(0);
mem_we_n <= we_n_arr(0);
mem_ck <= ck_p_arr;
mem_ck_n <= ck_n_arr;
mem_cke <= cke_arr(0);
mem_cs_n <= cs_arr(0);
mem_odt <= odt_arr(0);
avlso.rdata(255 downto 0) <= rdata(255 downto 0);
wdata <= avlsi.wdata(255 downto 0);
be <= avlsi.be(31 downto 0);
ctrl0: ddr2ctrl
port map (
pll_ref_clk => pll_ref_clk,
global_reset_n => global_reset_n,
soft_reset_n => vcc,
afi_clk => afi_clk,
afi_half_clk => afi_half_clk,
afi_reset_n => afi_reset_n,
afi_reset_export_n => open,
mem_a => mem_a,
mem_ba => mem_ba,
mem_ck => ck_p_arr,
mem_ck_n => ck_n_arr,
mem_cke => cke_arr,
mem_cs_n => cs_arr,
mem_dm => mem_dm,
mem_ras_n => ras_n_arr,
mem_cas_n => cas_n_arr,
mem_we_n => we_n_arr,
mem_dq => mem_dq,
mem_dqs => mem_dqs,
mem_dqs_n => mem_dqs_n,
mem_odt => odt_arr,
avl_ready => avlso.ready,
avl_burstbegin => avlsi.burstbegin,
avl_addr => avlsi.addr(24 downto 0),
avl_rdata_valid => avlso.rdata_valid,
avl_rdata => rdata,
avl_wdata => wdata,
avl_be => be,
avl_read_req => avlsi.read_req,
avl_write_req => avlsi.write_req,
avl_size => avlsi.size,
local_init_done => local_init_done,
local_cal_success => local_cal_success,
local_cal_fail => local_cal_fail,
oct_rdn => oct_rdn,
oct_rup => oct_rup
);
avlso.rdata(avlso.rdata'high downto 256) <= (others => '0');
ahb2avl0: ahb2avl_async
generic map (
hindex => hindex,
haddr => haddr,
hmask => hmask,
burstlen => burstlen,
nosync => 0,
ahbbits => ahbbits,
avldbits => 256,
avlabits => 25
)
port map (
rst_ahb => ahb_rst,
clk_ahb => ahb_clk,
ahbsi => ahbsi,
ahbso => ahbso,
rst_avl => afi_reset_n,
clk_avl => afi_clk,
avlsi => avlsi,
avlso => avlso
);
end;
|
gpl-2.0
|
3c2fdd969c666610507bc6a84307ab4b
| 0.447084 | 3.743549 | false | false | false | false |
aortiz49/MIPS-Processor
|
Hardware/single_cycle.vhd
| 1 | 4,108 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity single_cycle is
port (
clk : in std_logic;
pc_rst : in std_logic;
programCounter : out std_logic_vector(31 downto 0);
instruction_out : out std_logic_vector(31 downto 0);
instr_addr : out std_logic_vector(7 downto 0)
);
end single_cycle;
architecture bhv of single_cycle is
signal pc_inc4 : std_logic_vector(31 downto 0);
signal pc_out : std_logic_vector(31 downto 0);
signal instruction : std_logic_vector(31 downto 0);
signal ALU_out : std_logic_vector(31 downto 0);
signal regFileOut1 : std_logic_vector(31 downto 0);
signal regFileOut0 : std_logic_vector(31 downto 0);
signal extendOut : std_logic_vector(31 downto 0);
signal ALUMux_out : std_logic_vector(31 downto 0);
signal extendIn : std_logic_vector(15 downto 0);
signal address : std_logic_vector(7 downto 0);
signal opCode : std_logic_vector(5 downto 0);
signal funct : std_logic_vector(5 downto 0);
signal rs : std_logic_vector(4 downto 0);
signal rt : std_logic_vector(4 downto 0);
signal rd : std_logic_vector(4 downto 0);
signal writeReg : std_logic_vector(4 downto 0);
signal shamt_in : std_logic_vector(4 downto 0);
signal shamt_out : std_logic_vector(4 downto 0);
signal ALUcontrol : std_logic_vector(3 downto 0);
signal ALUOp : std_logic_vector(2 downto 0);
signal regWrite : std_logic;
signal shdir : std_logic;
signal C,Z,S,V : std_logic;
signal regDst : std_logic;
signal ExtOp : std_logic;
signal ALUsrc : std_logic;
begin
rs <= instruction(25 downto 21);
rt <= instruction(20 downto 16);
rd <= instruction(15 downto 11);
address <= pc_out(9 downto 2);
opcode <= instruction(31 downto 26);
funct <= instruction(5 downto 0);
extendIn <= instruction(15 downto 0);
shamt_in <= instruction(10 downto 6);
pc: entity work. programCounter
port map(clk => clk,
rst => pc_rst,
input => pc_inc4,
output => pc_out );
extender: entity work.extender
port map(in0 => extendIn,
ExtOp => ExtOp,
out0 => extendOut);
pc_add: entity work.add32
port map(in1 => pc_out,
in0 => x"00000004",
sum => pc_inc4 );
alu: entity work.alu32
port map(ia => regFileOut1,
ib => ALUMux_out,
shamt => shamt_out,
shdir => shdir,
C => C,
control => ALUcontrol,
output => ALU_out,
Z => Z,
S => S,
V => V );
aluMux: entity work.mux_gen
generic map(width => 32)
port map(in1 => extendOut,
in0 => regFileOut0,
sel => ALUsrc,
output => ALUMux_out);
regFile: entity work.register_file
port map(clk => clk,
data => ALU_out,
rst => pc_rst,
reg_write => writeReg,
wr_en => regWrite,
reg_read1 => rs,
reg_read0 => rt,
output1 => regFileout1,
output0 => regFileout0 );
regDstMux: entity work.mux_gen
generic map(width => 5)
port map(in1 => rd,
in0 => rt,
sel => regDst,
output => writeReg);
instructionMem: entity work.instruction
port map(address => address,
clock => clk,
q => instruction);
mainController: entity work.main_control
port map(op_code => opCode,
RegDst => RegDst,
ALUsrc => ALUsrc,
RegWrite => RegWrite,
ALUOp => ALUOp,
ExtOp => ExtOp);
aluController: entity work.alu_control
port map(ALUop => ALUop,
funct => funct,
shamt_in => shamt_in,
shamt_out => shamt_out,
control => ALUcontrol,
shdir => shdir);
programCounter <= pc_out;
instruction_out <= instruction;
instr_addr <= address;
end bhv;
|
mit
|
cdecc23a568315a61f4f04ed3269af19
| 0.555501 | 2.725946 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep3c25/leon3mp.vhd
| 1 | 17,964 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- flash/ssram bus
address : out std_logic_vector(25 downto 1);
data : inout std_logic_vector(31 downto 0);
romsn : out std_ulogic;
oen : out std_logic;
writen : out std_logic;
rstoutn : out std_ulogic;
ssram_cen : out std_logic;
ssram_wen : out std_logic;
ssram_bw : out std_logic_vector (0 to 3);
ssram_oen : out std_ulogic;
ssram_clk : out std_ulogic;
ssram_adscn : out std_ulogic;
-- ssram_adsp_n : out std_ulogic;
-- ssram_adv_n : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
ddr_clk : out std_logic;
ddr_clkn : out std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console/debug UART
rxd1 : in std_logic;
txd1 : out std_logic;
gpio : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi, smemi : memory_in_type;
signal memo, smemo : memory_out_type;
signal wpo : wprot_out_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
-- attribute syn_keep : boolean;
-- attribute syn_preserve : boolean;
-- attribute syn_keep of clkml : signal is true;
-- attribute syn_preserve of clkml : signal is true;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, ssram_clkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal lclk, lclkout : std_ulogic;
signal dsubre : std_ulogic;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => 1,
freq => freq)
port map (clkin => lclk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => ssram_clkl, pciclk => open,
cgi => cgi, cgo => cgo);
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (ssram_clk, ssram_clkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn);
rstoutn <= resetn;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 :mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
ramaddr => 16#400#+16#600#*CFG_DDRSP, rammask =>16#F00#, srbanks => 1,
sden => 0, ram16 => 1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
ssr0 : if CFG_SSCTRL = 1 generate
ssrctrl0 : ssrctrl generic map (hindex => 0, pindex => 0,
iomask => 0, ramaddr => 16#400#+16#600#*CFG_DDRSP,
bus16 => CFG_SSCTRLP16)
port map (rstn, clkm, ahbsi, ahbso(0), apbi, apbo(0), memi, memo);
end generate;
mg0 : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) = 0 generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech) port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) /= 0 generate -- prom/sram pads
addr_pad : outpadv generic map (width => 25, tech => padtech)
port map (address, memo.address(25 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
-- ssram_adv_n_pad : outpad generic map (tech => padtech)
-- port map (ssram_adv_n, vcc(0));
-- ssram_adsp_n_pad : outpad generic map (tech => padtech)
-- port map (ssram_adsp_n, gnd(0));
ssram_adscn_pad : outpad generic map (tech => padtech)
port map (ssram_adscn, gnd(0));
ssrams_pad : outpad generic map ( tech => padtech)
port map (ssram_cen, memo.ramsn(0));
ssram_oen_pad : outpad generic map (tech => padtech)
port map (ssram_oen, memo.oen);
ssram_rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (ssram_bw, memo.wrn);
ssram_wri_pad : outpad generic map (tech => padtech)
port map (ssram_wen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 32)
port map (data(31 downto 0), memo.data(31 downto 0),
memo.vbdrive, memi.data(31 downto 0));
end generate;
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 3, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, rskew => CFG_DDRSP_RSKEW,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 16, regoutput => 1)
port map (
resetn, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(3),
ddr_clkv, ddr_clkbv, open, gnd(0),
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkn <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
ddrsp1 : if (CFG_DDRSP = 0) generate
ddr_cke <= '0'; ddr_csb <= '1'; lock <= '1';
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
upads : if CFG_AHB_UART = 0 generate
u1i.rxd <= rxd1; txd1 <= u1o.txd;
end generate;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
gpioi.din(i) <= gpio(i);
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP3C25 SSRAM/DDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
af190dfb47a0bdb27b7a3e783d9cc10f
| 0.544923 | 3.756587 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/grfpw_net.vhd
| 1 | 36,524 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grfpw_net
-- File: grfpw_net.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: GRFPU / GRLFPC netlist wrapper
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.gencomp.all;
entity grfpw_net is
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end;
architecture rtl of grfpw_net is
component grfpw_0_unisim
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
-- disasen : in std_logic);
end component;
component grfpw_0_altera
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grfpw_0_stratixii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grfpw_0_cycloneiii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grfpw_0_stratixiii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grfpw_tsmc90
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
--cpo_restart : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw_tm65gplus
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
--cpo_restart : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw_cust1
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
--cpo_restart : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of u0_tsmc90 : label is TRUE;
attribute DONT_TOUCH of u0_tm65gplus : label is TRUE;
-- signal disasen : std_logic;
begin
-- disasen <= '1' when disas /= 0 else '0';
uni : if (is_unisim(tech) = 1) generate
grfpw0 : grfpw_0_unisim
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2);--, disasen);
end generate;
alt : if (tech = altera) generate -- Cyclone, Stratix V, Cyclone V
grfpw0 : grfpw_0_altera
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
strtx : if (tech = stratix1) or (tech = stratix2) generate
grfpw0 : grfpw_0_stratixii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
strtxiii : if (tech = stratix3) or (tech = stratix4) generate
grfpw0 : grfpw_0_stratixiii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
cyc3 : if (tech = cyclone3) generate
grfpw0 : grfpw_0_cycloneiii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
u0_tsmc90 : if tech = tsmc90 generate
grfpw0 : grfpw_tsmc90
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
u0_tm65gplus : if tech = tm65gplus generate
grfpw0 : grfpw_tm65gplus
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
u0_cust1 : if tech = custom1 generate
grfpw0 : grfpw_cust1
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
end;
|
gpl-2.0
|
6f2ee460febefb8bba5b0e88507ea736
| 0.617128 | 2.700081 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/sim/pwm_check.vhd
| 1 | 31,904 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: pwm_check
-- File: pwm_check.vhd
-- Author: Jonas Ekergarn - Aeroflex Gaisler (parts are copied from
-- grtestmod.vhd)
-- Description: Simulation unit that examines the PWMs generated by the GRPWM
-- when software/leon3/grpwm.c is run. Note that pwm_check
-- requires that the system includes an I/O memory interface
-- and that grtestmod.vhd is instantiated in the system testbench.
-- If the subtests in software/leon3/grpwm.c is modified then the
-- configuration below and the procedure verify_subtest must be
-- changed as well.
-------------------------------------------------------------------------------
-- pragma translate_off
library ieee, grlib, gaisler;
use ieee.std_logic_1164.all;
use std.textio.all;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
use gaisler.sim.all;
entity pwm_check is
port (
clk : in std_ulogic;
address : in std_logic_vector(21 downto 2);
data : inout std_logic_vector(31 downto 0);
iosn : in std_ulogic;
oen : in std_ulogic;
writen : in std_ulogic;
pwm : in std_logic_vector(15 downto 0)
);
end;
architecture sim of pwm_check is
signal ior, iow : std_ulogic;
signal addr : std_logic_vector(21 downto 2);
signal ldata : std_logic_vector(31 downto 0);
signal pwmh : std_logic_vector(1 downto 0);
signal pwmh0 : integer := 0;
signal pwmh1 : integer := 1;
-----------------------------------------------------------------------------
-- Configuration of the PWMs that should be verified
-----------------------------------------------------------------------------
-- Number of "useful" words in the waveform ram. The core will read address
-- 0 - (STX_WRAMSIZE-1).
constant ST3_WRAMSIZE : integer := 32;
constant ST4_WRAMSIZE : integer := 32;
-- Number of periods to verify for each subtest. Verification of the very
-- first period after PWM is started is skipped because there is no way of
-- knowing exactly when it starts. It is assumed that the first period is
-- correct. If it isn't then the verification of the other periods will fail
-- as well.
constant ST1_NPER : integer := 10;
constant ST2_NPER : integer := 10;
constant ST3_NPER : integer := 2*ST3_WRAMSIZE;
constant ST4_NPER : integer := 2*ST4_WRAMSIZE;
type st1_vector is array (0 to ST1_NPER) of integer;
type st2_vector is array (0 to ST2_NPER) of integer;
type st3_vector is array (0 to ST3_NPER) of integer;
type st4_vector is array (0 to ST4_NPER) of integer;
type st1_array is array (0 to 7) of st1_vector;
type st2_array is array (0 to 7) of st2_vector;
type st3_array is array (0 to 7) of st3_vector;
type st4_array is array (0 to 7) of st4_vector;
type wram_type is array (0 to 8191) of integer;
-- Polarity for each PWM in the different subtests
constant ST1_POL : std_logic_vector(7 downto 0) := (others=>'1');
constant ST2_POL : std_logic_vector(7 downto 0) := (others=>'1');
constant ST3_POL : std_logic_vector(7 downto 0) := (others=>'1');
constant ST4_POL : std_logic_vector(7 downto 0) := (others=>'1');
-- Period, compare, and dead band values for each pwm period in subtest 1,
-- in clock cycles
constant ST1_PER : st1_array := (
0 => (others=>200),
1 => (others=>201),
2 => (others=>202),
3 => (others=>203),
4 => (others=>204),
5 => (others=>205),
6 => (others=>206),
7 => (others=>207));
constant ST1_COMPA : st1_array := (
0 => (others=>100),
1 => (others=>101),
2 => (others=>102),
3 => (others=>103),
4 => (others=>104),
5 => (others=>105),
6 => (others=>106),
7 => (others=>107));
constant ST1_DB : st1_array := (
0 => (others=>10),
1 => (others=>11),
2 => (others=>12),
3 => (others=>13),
4 => (others=>14),
5 => (others=>15),
6 => (others=>16),
7 => (others=>17));
-- Period, compare, and dead band values for each pwm period in subtest 2,
-- in clock cycles
constant ST2_PER : st2_array := (
0 => (others=>200),
1 => (others=>202),
2 => (others=>204),
3 => (others=>206),
4 => (others=>208),
5 => (others=>210),
6 => (others=>212),
7 => (others=>214));
constant ST2_COMPA : st2_array := (
0 => (others=>50),
1 => (others=>51),
2 => (others=>52),
3 => (others=>53),
4 => (others=>54),
5 => (others=>55),
6 => (others=>56),
7 => (others=>57));
constant ST2_DB : st2_array := (
0 => (others=>10),
1 => (others=>11),
2 => (others=>12),
3 => (others=>13),
4 => (others=>14),
5 => (others=>15),
6 => (others=>16),
7 => (others=>17));
-- Period, compare, and dead band values for each pwm period in subtest 3,
-- in clock cycles. (Only the PWM with the highest index is active during
-- subtest 3, but since we here don't know how many PWM outputs there are,
-- all get the same value)
constant ST3_WRAM : wram_type := (
32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,
56,57,58,59,60,61,62,63,
others=>0);
constant ST3_PER : st3_array := (
0 => (others=>200),
1 => (others=>200),
2 => (others=>200),
3 => (others=>200),
4 => (others=>200),
5 => (others=>200),
6 => (others=>200),
7 => (others=>200));
constant ST3_DB : st3_array := (
0 => (others=>10),
1 => (others=>10),
2 => (others=>10),
3 => (others=>10),
4 => (others=>10),
5 => (others=>10),
6 => (others=>10),
7 => (others=>10));
-- Period, compare, and dead band values for each pwm period in subtest 4,
-- in clock cycles. (Only the PWM with the highest index is active during
-- subtest 4, but since we here don't know how many PWM outputs there are,
-- all get the same value)
constant ST4_WRAM : wram_type := (
32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,
56,57,58,59,60,61,62,63,
others=>0);
constant ST4_PER : st4_array := (
0 => (others=>200),
1 => (others=>200),
2 => (others=>200),
3 => (others=>200),
4 => (others=>200),
5 => (others=>200),
6 => (others=>200),
7 => (others=>200));
constant ST4_DB : st4_array := (
0 => (others=>10),
1 => (others=>10),
2 => (others=>10),
3 => (others=>10),
4 => (others=>10),
5 => (others=>10),
6 => (others=>10),
7 => (others=>10));
type pwm_int_array is array (0 to 7) of integer;
type pwm_bool_array is array (0 to 7) of boolean;
procedure verify_subtest (
constant subtest : in integer;
constant npwm : in integer range 1 to 8;
signal clk : in std_ulogic;
signal pwm : in std_logic_vector(15 downto 0);
signal pwmh : in std_logic_vector(1 downto 0)) is
variable cnt : pwm_int_array := (others=>0);
variable cnt2 : pwm_int_array := (others=>0);
variable pcnt : pwm_int_array := (others=>0);
variable parta : pwm_bool_array := (others=>false);
variable partb : pwm_bool_array := (others=>false);
variable partc : pwm_bool_array := (others=>false);
variable partd : pwm_bool_array := (others=>false);
variable done : pwm_bool_array := (others=>false);
variable ST2_COMPB : st2_array;
variable ST4_COMPB : st4_array;
variable addr : integer;
variable il, ih : integer;
begin
case subtest is
when 1 =>
-------------------------------------------------------------------------
-- Subtest 1: npwm assymmetric PWM pairs are generated, all with
-- different periods, compare values, and dead band values. Verify
-- periods, compare matches, and dead band times.
-------------------------------------------------------------------------
for i in 0 to 7 loop
if npwm < i+1 then done(i) := true; end if;
-- no dead band time is inserted in the very first pwm period after
-- startup
parta(i) := true;
end loop;
while not(done(0) and done(1) and done(2) and done(3) and
done(4) and done(5) and done(6) and done(7)) loop
wait until rising_edge(clk);
for i in 0 to npwm-1 loop
cnt(i) := cnt(i)+1;
end loop;
wait until (pwm'event or falling_edge(clk));
if clk = '1' then
for i in 0 to npwm-1 loop
if (not done(i)) then
if (not parta(i)) then
-- pwm is in time period between period start and when paired
-- output goes active (after dead band time)
if pwm(2*i+1) = ST1_POL(i) then
parta(i) := true;
if pcnt(i) /= 0 then
if cnt(i) /= ST1_DB(i)(pcnt(i)) then
Print("ERROR: Wrong dead band (1) detected for pwm " &
tost(i+1) & " in period = " & tost(pcnt(i)) &
". Is " & tost(cnt(i)) & ", should be " &
tost(ST1_DB(i)(pcnt(i))));
end if;
end if;
end if;
elsif (not partb(i)) then
-- pwm is in time period between paired output going active and
-- paired output going inactive
if pwm(2*i+1) = (not ST1_POL(i)) then
partb(i) := true;
if pcnt(i) /= 0 then
if cnt(i) /= ST1_COMPA(i)(pcnt(i)) then
Print("ERROR: Wrong compare match detected for pwm " &
tost(i+1) & " in period = " & tost(pcnt(i)) &
". Is " & tost(cnt(i)) & ", should be " &
tost(ST1_COMPA(i)(pcnt(i))));
end if;
if ST1_DB(i)(pcnt(i)) = 0 then
partc(i) := true;
if pwm(2*i) /= ST1_POL(i) then
Print("ERROR: Both outputs did not switch simultaneously"
& " even though dead band time was zero");
end if;
end if;
end if;
end if;
elsif (not partc(i)) then
-- pwm is in time period between paired output going inactive and
-- output going active (after dead band time)
if pwm(2*i) = ST1_POL(i) then
partc(i) := true;
if pcnt(i) /= 0 then
if cnt(i) /= (ST1_COMPA(i)(pcnt(i)) +
ST1_DB(i)(pcnt(i))) then
Print("ERROR: Wrong dead band (2) time detected for pwm " &
tost(i+1) & " in period = " & tost(pcnt(i)) &
". Is " & tost(cnt(i)-ST1_COMPA(i)(pcnt(i))) &
", should be " & tost(ST1_DB(i)(pcnt(i))));
end if;
end if;
end if;
else
-- pwm is in time period between output going active and period end
-- (output going inactive)
if pwm(2*i) = (not ST1_POL(i)) then
parta(i) := false; partb(i) := false; partc(i) := false;
if pcnt(i) /= 0 then
if cnt(i) /= ST1_PER(i)(pcnt(i)) then
Print("ERROR: Wrong PWM period detected for pwm " &
tost(i+1) & " in period = " & tost(pcnt(i)) &
". Is " & tost(cnt(i)) & ", should be " &
tost(ST1_PER(i)(pcnt(i))));
end if;
end if;
if pcnt(i) = ST1_NPER then
done(i) := true;
end if;
pcnt(i) := pcnt(i)+1;
cnt(i) := 0;
if pcnt(i) < ST1_NPER then
if ST1_DB(i)(pcnt(i)) = 0 then
parta(i) := true;
if pwm(2*i+1) /= ST1_POL(i) then
Print("ERROR: Both outputs did not switch simultaneously"
& " even though dead band time was zero");
end if;
end if;
end if;
end if;
end if;
end if;
end loop;
end if;
end loop;
when 2 =>
-------------------------------------------------------------------------
-- Subtest 2: npwm symmetric PWM pairs are generated, all with
-- different periods, compare values, and dead band values. Verify
-- periods, compare matches, and dead band times
-------------------------------------------------------------------------
for i in 0 to 7 loop
for j in 0 to ST2_NPER loop
ST2_COMPB(i)(j) := ST2_PER(i)(j)-ST2_COMPA(i)(j);
end loop;
if npwm < i+1 then done(i) := true; end if;
end loop;
while not(done(0) and done(1) and done(2) and done(3) and
done(4) and done(5) and done(6) and done(7)) loop
wait until rising_edge(clk);
for i in 0 to npwm-1 loop
cnt(i) := cnt(i)+1; cnt2(i) := cnt2(i)+1;
end loop;
wait until (pwm'event or falling_edge(clk));
if clk = '1' then
for i in 0 to npwm-1 loop
if (not done(i)) then
if (not parta(i)) then
-- pwm is in time period between period start and when paired
-- output goes inactive
if pwm(2*i+1) = (not ST2_POL(i)) then
parta(i) := true;
if pcnt(i) /= 0 then
if cnt(i) /= ST2_COMPA(i)(pcnt(i)) then
Print("ERROR: Wrong compare match 1 detected for pwm " &
tost(i+1) & " in period = " & tost(pcnt(i)) &
". Is " & tost(cnt(i)) & ", should be " &
tost(ST2_COMPA(i)(pcnt(i))));
end if;
if ST2_DB(i)(pcnt(i)) = 0 then
partb(i) := true;
if pwm(2*i) /= ST2_POL(i) then
Print("ERROR: Both outputs did not switch simultaneously"
& " even though dead band time was zero");
end if;
end if;
end if;
end if;
elsif (not partb(i)) then
-- pwm is in time period between paired output going inactive and
-- output going active (after dead band time)
if pwm(2*i) = ST2_POL(i) then
partb(i) := true;
if pcnt(i) /= 0 then
if cnt(i) /= (ST2_COMPA(i)(pcnt(i)) +
ST2_DB(i)(pcnt(i))) then
Print("ERROR: Wrong dead band (1) time detected for pwm " &
tost(i+1) & " in period = " & tost(pcnt(i)) &
". Is " & tost(cnt(i)-ST2_COMPA(i)(pcnt(i))) &
", should be " & tost(ST2_DB(i)(pcnt(i))));
end if;
end if;
end if;
elsif (not partc(i)) then
-- pwm is in time period between output going active and
-- output going inactive
if pwm(2*i) = (not ST2_POL(i)) then
partc(i) := true;
if pcnt(i) /= 0 then
if cnt(i) /= ST2_COMPB(i)(pcnt(i)) then
Print("ERROR: Wrong compare match (2) detected for pwm " &
tost(i+1) & " in period = " & tost(pcnt(i)) &
". Is " & tost(cnt(i)) & ", should be " &
tost(ST2_COMPB(i)(pcnt(i))));
end if;
if ST2_DB(i)(pcnt(i)) = 0 then
partd(i) := true;
if pwm(2*i+1) /= ST2_POL(i) then
Print("ERROR: Both outputs did not switch simultaneously"
& " even though dead band time was zero");
end if;
end if;
else
if ST2_DB(i)(0) = 0 then
cnt2(i) := 0;
partd(i) := true;
end if;
end if;
end if;
elsif (not partd(i)) then
-- pwm is in time period between output going inactive and
-- paired output going active (after dead band time)
if pwm(2*i+1) = ST2_POL(i) then
partd(i) := true;
if pcnt(i) /= 0 then
if cnt(i) /= (ST2_COMPB(i)(pcnt(i)) +
ST2_DB(i)(pcnt(i))) then
Print("ERROR: Wrong dead band (2) time detected for pwm " &
tost(i+1) & " in period = " & tost(pcnt(i)) &
". Is " & tost(cnt(i)-ST2_COMPB(i)(pcnt(i))) &
", should be " & tost(ST2_DB(i)(pcnt(i))));
end if;
else
cnt2(i) := 0;
end if;
end if;
end if;
end if;
end loop;
end if;
for i in 0 to npwm-1 loop
if (not done(i)) then
if partd(i) then
-- pwm is in time period between paired output going active
-- and period end
if pcnt(i) /= 0 then
if cnt(i) = ST2_PER(i)(pcnt(i)) then
parta(i) := false; partb(i) := false;
partc(i) := false; partd(i) := false;
pcnt(i) := pcnt(i)+1;
cnt(i) := 0;
end if;
else
if (cnt2(i)+ST2_COMPB(i)(0)+ST2_DB(i)(0)) =
ST2_PER(i)(0) then
parta(i) := false; partb(i) := false;
partc(i) := false; partd(i) := false;
pcnt(i) := pcnt(i)+1;
cnt(i) := 0;
end if;
end if;
if pcnt(i) = ST2_NPER then
done(i) := true;
end if;
end if;
end if;
end loop;
end loop;
when 3 =>
-------------------------------------------------------------------------
-- Subtest 3: One asymmetric waveform PWM is generated. Verify period,
-- compare matches and dead band time
-------------------------------------------------------------------------
parta(npwm-1) := true;
while not done(npwm-1) loop
wait until rising_edge(clk);
cnt(npwm-1) := cnt(npwm-1)+1;
wait until (pwmh'event or falling_edge(clk));
if clk = '1' then
addr := pcnt(npwm-1) - (pcnt(npwm-1)/ST3_WRAMSIZE)*ST3_WRAMSIZE;
if (not parta(npwm-1)) then
-- pwm is in time period between period start and when paired
-- output goes active (after dead band time)
if pwmh(1) = ST3_POL(npwm-1) then
parta(npwm-1) := true;
if pcnt(npwm-1) /= 0 then
if cnt(npwm-1) /= ST3_DB(npwm-1)(pcnt(npwm-1)) then
Print("ERROR: Wrong dead band (1) detected for pwm " &
tost((npwm-1)+1) & " in period = " & tost(pcnt(npwm-1)) &
". Is " & tost(cnt(npwm-1)) & ", should be " &
tost(ST3_DB(npwm-1)(pcnt(npwm-1))));
end if;
end if;
end if;
elsif (not partb(npwm-1)) then
-- pwm is in time period between paired output going active and
-- paired output going inactive
if pwmh(1) = (not ST3_POL(npwm-1)) then
partb(npwm-1) := true;
if pcnt(npwm-1) /= 0 then
if cnt(npwm-1) /= ST3_WRAM(addr) then
Print("ERROR: Wrong compare match detected for pwm " &
tost((npwm-1)+1) & " in period = " & tost(pcnt(npwm-1)) &
". Is " & tost(cnt(npwm-1)) & ", should be " &
tost(ST3_WRAM(addr)));
end if;
if ST3_DB(npwm-1)(pcnt(npwm-1)) = 0 then
partc(npwm-1) := true;
if pwmh(0) /= ST3_POL(npwm-1) then
Print("ERROR: Both outputs did not switch simultaneously"
& " even though dead band time was zero");
end if;
end if;
end if;
end if;
elsif (not partc(npwm-1)) then
-- pwm is in time period between paired output going inactive and
-- output going active (after dead band time)
if pwmh(0) = ST3_POL(npwm-1) then
partc(npwm-1) := true;
if pcnt(npwm-1) /= 0 then
if cnt(npwm-1) /= (ST3_WRAM(addr) +
ST3_DB(npwm-1)(pcnt(npwm-1))) then
Print("ERROR: Wrong dead band (2) time detected for pwm " &
tost((npwm-1)+1) & " in period = " & tost(pcnt(npwm-1)) &
". Is " & tost(cnt(npwm-1)-ST3_WRAM(addr)) &
", should be " & tost(ST3_DB(npwm-1)(pcnt(npwm-1))));
end if;
end if;
end if;
else
-- pwm is in time period between output going active and period end
-- (output going inactive)
if pwmh(0) = (not ST3_POL(npwm-1)) then
parta(npwm-1) := false; partb(npwm-1) := false; partc(npwm-1) := false;
if pcnt(npwm-1) /= 0 then
if cnt(npwm-1) /= ST3_PER(npwm-1)(pcnt(npwm-1)) then
Print("ERROR: Wrong PWM period detected for pwm " &
tost((npwm-1)+1) & " in period = " & tost(pcnt(npwm-1)) &
". Is " & tost(cnt(npwm-1)) & ", should be " &
tost(ST3_PER(npwm-1)(pcnt(npwm-1))));
end if;
end if;
if pcnt(npwm-1) = ST3_NPER then
done(npwm-1) := true;
end if;
pcnt(npwm-1) := pcnt(npwm-1)+1;
cnt(npwm-1) := 0;
if pcnt(npwm-1) < ST3_NPER then
if ST3_DB(npwm-1)(pcnt(npwm-1)) = 0 then
parta(npwm-1) := true;
if pwmh(1) /= ST3_POL(npwm-1) then
Print("ERROR: Both outputs did not switch simultaneously"
& " even though dead band time was zero");
end if;
end if;
end if;
end if;
end if;
end if;
end loop;
when 4 =>
-------------------------------------------------------------------------
-- Subtest 4: One symmetric waveform PWM is generated. Verify period,
-- compare matches, and dead band time
-------------------------------------------------------------------------
for j in 0 to ST4_NPER loop
addr := j - (j/ST4_WRAMSIZE)*ST4_WRAMSIZE;
ST4_COMPB(npwm-1)(j) := ST4_PER(npwm-1)(j)-ST4_WRAM(addr);
end loop;
while not done(npwm-1) loop
wait until rising_edge(clk);
cnt(npwm-1) := cnt(npwm-1)+1; cnt2(npwm-1) := cnt2(npwm-1)+1;
wait until (pwmh'event or falling_edge(clk));
if clk = '1' then
addr := pcnt(npwm-1) - (pcnt(npwm-1)/ST4_WRAMSIZE)*ST4_WRAMSIZE;
if (not parta(npwm-1)) then
-- pwm is in time period between period start and when paired
-- output goes inactive
if pwmh(1) = (not ST4_POL(npwm-1)) then
parta(npwm-1) := true;
if pcnt(npwm-1) /= 0 then
if cnt(npwm-1) /= ST4_WRAM(addr) then
Print("ERROR: Wrong compare match 1 detected for pwm " &
tost(npwm-1+1) & " in period = " & tost(pcnt(npwm-1)) &
". Is " & tost(cnt(npwm-1)) & ", should be " &
tost(ST4_WRAM(addr)));
end if;
if ST4_DB(npwm-1)(pcnt(npwm-1)) = 0 then
partb(npwm-1) := true;
if pwmh(0) /= ST4_POL(npwm-1) then
Print("ERROR: Both outputs did not switch simultaneously"
& " even though dead band time was zero");
end if;
end if;
end if;
end if;
elsif (not partb(npwm-1)) then
-- pwm is in time period between paired output going inactive and
-- output going active (after dead band time)
if pwmh(0) = ST4_POL(npwm-1) then
partb(npwm-1) := true;
if pcnt(npwm-1) /= 0 then
if cnt(npwm-1) /= (ST4_WRAM(addr) +
ST4_DB(npwm-1)(pcnt(npwm-1))) then
Print("ERROR: Wrong dead band (1) time detected for pwm " &
tost(npwm-1+1) & " in period = " & tost(pcnt(npwm-1)) &
". Is " & tost(cnt(npwm-1)-ST4_WRAM(addr)) &
", should be " & tost(ST4_DB(npwm-1)(pcnt(npwm-1))));
end if;
end if;
end if;
elsif (not partc(npwm-1)) then
-- pwm is in time period between output going active and
-- output going inactive
if pwmh(0) = (not ST4_POL(npwm-1)) then
partc(npwm-1) := true;
if pcnt(npwm-1) /= 0 then
if cnt(npwm-1) /= ST4_COMPB(npwm-1)(pcnt(npwm-1)) then
Print("ERROR: Wrong compare match (2) detected for pwm " &
tost(npwm-1+1) & " in period = " & tost(pcnt(npwm-1)) &
". Is " & tost(cnt(npwm-1)) & ", should be " &
tost(ST4_COMPB(npwm-1)(pcnt(npwm-1))));
end if;
if ST4_DB(npwm-1)(pcnt(npwm-1)) = 0 then
partd(npwm-1) := true;
if pwmh(1) /= ST4_POL(npwm-1) then
Print("ERROR: Both outputs did not switch simultaneously"
& " even though dead band time was zero");
end if;
end if;
else
if ST4_DB(npwm-1)(0) = 0 then
cnt2(npwm-1) := 0;
partd(npwm-1) := true;
end if;
end if;
end if;
elsif (not partd(npwm-1)) then
-- pwm is in time period between output going inactive and
-- paired output going active (after dead band time)
if pwmh(1) = ST4_POL(npwm-1) then
partd(npwm-1) := true;
if pcnt(npwm-1) /= 0 then
if cnt(npwm-1) /= (ST4_COMPB(npwm-1)(pcnt(npwm-1)) +
ST4_DB(npwm-1)(pcnt(npwm-1))) then
Print("ERROR: Wrong dead band (2) time detected for pwm " &
tost(npwm-1+1) & " in period = " & tost(pcnt(npwm-1)) &
". Is " & tost(cnt(npwm-1)-ST4_COMPB(npwm-1)(pcnt(npwm-1))) &
", should be " & tost(ST4_DB(npwm-1)(pcnt(npwm-1))));
end if;
else
cnt2(npwm-1) := 0;
end if;
end if;
end if;
end if;
if partd(npwm-1) then
-- pwm is in time period between paired output going active
-- and period end
if pcnt(npwm-1) /= 0 then
if cnt(npwm-1) = ST4_PER(npwm-1)(pcnt(npwm-1)) then
parta(npwm-1) := false; partb(npwm-1) := false;
partc(npwm-1) := false; partd(npwm-1) := false;
pcnt(npwm-1) := pcnt(npwm-1)+1;
cnt(npwm-1) := 0;
end if;
else
if (cnt2(npwm-1)+ST4_COMPB(npwm-1)(0)+ST4_DB(npwm-1)(0)) =
ST4_PER(npwm-1)(0) then
parta(npwm-1) := false; partb(npwm-1) := false;
partc(npwm-1) := false; partd(npwm-1) := false;
pcnt(npwm-1) := pcnt(npwm-1)+1;
cnt(npwm-1) := 0;
end if;
end if;
if pcnt(npwm-1) = ST4_NPER then
done(npwm-1) := true;
end if;
end if;
end loop;
when others => null;
end case;
end verify_subtest;
begin
ior <= iosn or oen;
iow <= iosn or writen;
data <= (others => 'Z');
addr <= to_X01(address) when rising_edge(clk) else addr;
ldata <= to_X01(data) when rising_edge(clk) else ldata;
pwmh <= pwm(pwmh1 downto pwmh0);
process
variable vid, did, subtest : integer;
variable npwm : integer := 8;
begin
pwmh0 <= 2*(npwm-1);
pwmh1 <= 2*(npwm-1)+1;
wait until ((rising_edge(ior) nor falling_edge(ior)) and rising_edge(iow));
case addr(7 downto 2) is
when "000000" =>
vid := conv_integer(ldata(31 downto 24));
did := conv_integer(ldata(23 downto 12));
when "000010" =>
subtest := conv_integer(ldata(7 downto 0));
if vid = VENDOR_GAISLER and did = GAISLER_PWM then
if subtest > 246 then
-- set npwm
npwm := 255 - subtest;
else
verify_subtest(subtest, npwm, clk, pwm, pwmh);
end if;
end if;
when others =>
end case;
end process;
end sim;
-- pragma translate_on
|
gpl-2.0
|
4849071ba2301fe223a66bdea7758b80
| 0.4459 | 4.003514 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml403/config.vhd
| 1 | 6,455 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex4;
constant CFG_MEMTECH : integer := virtex4;
constant CFG_PADTECH : integer := virtex4;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex4;
constant CFG_CLKMUL : integer := (13);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (1);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 1;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 1;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (64);
constant CFG_DDRSP_RSKEW : integer := (0);
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0FFFE#;
constant CFG_GRGPIO_WIDTH : integer := (14);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
681841a7382df1284e3675a0e85badc3
| 0.644926 | 3.614222 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica02_SumadorRestador4Bits/top_sumadorcompleto.vhd
| 1 | 953 |
library ieee;
use ieee.std_logic_1164.all;
use pack_sum_completo.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
-- Entidad
entity eTopSumCompleto is
port(
acarreoI_tsc: in std_logic;
entrada1_tsc: in std_logic;
entrada2_tsc: in std_logic;
resultado_tsc: out std_logic;
acarreoO_tsc: out std_logic);
end;
-- Arquitectura
architecture aTopSumCompleto of eTopSumCompleto is
signal suma1, acarreo1, acarreo2: std_logic;
begin
U3: eww port map(
entrada1_or => acarreo2,
entrada2_or => acarreo1,
salida_or => acarreoO_tsc);
U4: eTopSumMedio port map(
entrada1_tsm => acarreoI_tsc,
entrada2_tsm => suma1,
resultado_tsm => resultado_tsc,
acarreo_tsm => acarreo2);
U5: eTopSumMedio port map(
entrada1_tsm => entrada1_tsc,
entrada2_tsm => entrada2_tsc,
resultado_tsm => suma1,
acarreo_tsm => acarreo1);
end aTopSumCompleto;
|
apache-2.0
|
5d0e065240373156cb2f433aa306dca8
| 0.675761 | 3.145215 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/cycloneiii/alt/actrlout.vhd
| 3 | 2,084 |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library cycloneiii;
use cycloneiii.all;
entity actrlout is
generic(
power_up : string := "high"
);
port(
clk : in std_logic;
i : in std_logic;
o : out std_logic
);
end;
architecture rtl of actrlout is
component cycloneiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic;
dfflo : out std_logic;
dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal clk_reg : std_logic;
signal clk_buf, clk_bufn : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
out_reg0 : cycloneiii_ddio_out
generic map(
power_up => power_up,--"high",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_out"
)
port map(
datainlo => i,
datainhi => i,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => o,
dfflo => open,
dffhi => open--,
--devclrn => vcc,
--devpor => vcc
);
end;
|
gpl-2.0
|
a25228ac5934727d3634d5619566b542
| 0.420825 | 4.007692 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/pci/grpci2/grpci2_phy_wrapper.vhd
| 1 | 14,422 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
library gaisler;
use gaisler.pci.all;
use work.pcilib2.all;
entity grpci2_phy_wrapper is
generic(
tech : integer := DEFMEMTECH;
oepol : integer := 0;
bypass : integer range 0 to 1 := 1;
netlist : integer := 0;
scantest: integer := 0;
iotest : integer := 0
);
port(
pciclk : in std_logic;
pcii : in pci_in_type;
phyi : in grpci2_phy_in_type;
pcio : out pci_out_type;
phyo : out grpci2_phy_out_type;
iotmact : in std_ulogic;
iotmoe : in std_ulogic;
iotdout : in std_logic_vector(44 downto 0);
iotdin : out std_logic_vector(45 downto 0)
);
end;
architecture wrapper of grpci2_phy_wrapper is
attribute dont_touch : boolean;
attribute dont_touch of net : label is true;
begin
rtl : if netlist = 0 generate
phy0 : grpci2_phy
generic map( tech => tech, oepol => oepol,
bypass => bypass, netlist => netlist,
scantest => scantest, iotest => iotest)
port map(
pciclk => pciclk,
pcii => pcii,
phyi => phyi,
pcio => pcio,
phyo => phyo,
iotmact => iotmact,
iotmoe => iotmoe,
iotdout => iotdout,
iotdin => iotdin
);
end generate;
net : if netlist /= 0 generate
phy0 : grpci2_phy_net
generic map( tech => tech, oepol => oepol,
bypass => bypass, netlist => netlist)
port map(
pciclk => pciclk,
--pcii : in pci_in_type,
pcii_rst => pcii.rst,
pcii_gnt => pcii.gnt,
pcii_idsel => pcii.idsel,
pcii_ad => pcii.ad,
pcii_cbe => pcii.cbe,
pcii_frame => pcii.frame,
pcii_irdy => pcii.irdy,
pcii_trdy => pcii.trdy,
pcii_devsel => pcii.devsel,
pcii_stop => pcii.stop,
pcii_lock => pcii.lock,
pcii_perr => pcii.perr,
pcii_serr => pcii.serr,
pcii_par => pcii.par,
pcii_host => pcii.host,
pcii_pci66 => pcii.pci66,
pcii_pme_status => pcii.pme_status,
pcii_int => pcii.int,
--phyi : in grpci2_phy_in_type,
phyi_pcirstout => phyi.pcirstout,
phyi_pciasyncrst => phyi.pciasyncrst,
phyi_pcisoftrst => phyi.pcisoftrst,
phyi_pciinten => phyi.pciinten,
phyi_m_request => phyi.m_request,
phyi_m_mabort => phyi.m_mabort,
phyi_pr_m_fstate => phyi.pr_m_fstate,
phyi_pr_m_cfifo_0_data => phyi.pr_m_cfifo(0).data,
phyi_pr_m_cfifo_0_last => phyi.pr_m_cfifo(0).last,
phyi_pr_m_cfifo_0_stlast => phyi.pr_m_cfifo(0).stlast,
phyi_pr_m_cfifo_0_hold => phyi.pr_m_cfifo(0).hold,
phyi_pr_m_cfifo_0_valid => phyi.pr_m_cfifo(0).valid,
phyi_pr_m_cfifo_0_err => phyi.pr_m_cfifo(0).err,
phyi_pr_m_cfifo_1_data => phyi.pr_m_cfifo(1).data,
phyi_pr_m_cfifo_1_last => phyi.pr_m_cfifo(1).last,
phyi_pr_m_cfifo_1_stlast => phyi.pr_m_cfifo(1).stlast,
phyi_pr_m_cfifo_1_hold => phyi.pr_m_cfifo(1).hold,
phyi_pr_m_cfifo_1_valid => phyi.pr_m_cfifo(1).valid,
phyi_pr_m_cfifo_1_err => phyi.pr_m_cfifo(1).err,
phyi_pr_m_cfifo_2_data => phyi.pr_m_cfifo(2).data,
phyi_pr_m_cfifo_2_last => phyi.pr_m_cfifo(2).last,
phyi_pr_m_cfifo_2_stlast => phyi.pr_m_cfifo(2).stlast,
phyi_pr_m_cfifo_2_hold => phyi.pr_m_cfifo(2).hold,
phyi_pr_m_cfifo_2_valid => phyi.pr_m_cfifo(2).valid,
phyi_pr_m_cfifo_2_err => phyi.pr_m_cfifo(2).err,
phyi_pv_m_cfifo_0_data => phyi.pv_m_cfifo(0).data,
phyi_pv_m_cfifo_0_last => phyi.pv_m_cfifo(0).last,
phyi_pv_m_cfifo_0_stlast => phyi.pv_m_cfifo(0).stlast,
phyi_pv_m_cfifo_0_hold => phyi.pv_m_cfifo(0).hold,
phyi_pv_m_cfifo_0_valid => phyi.pv_m_cfifo(0).valid,
phyi_pv_m_cfifo_0_err => phyi.pv_m_cfifo(0).err,
phyi_pv_m_cfifo_1_data => phyi.pv_m_cfifo(1).data,
phyi_pv_m_cfifo_1_last => phyi.pv_m_cfifo(1).last,
phyi_pv_m_cfifo_1_stlast => phyi.pv_m_cfifo(1).stlast,
phyi_pv_m_cfifo_1_hold => phyi.pv_m_cfifo(1).hold,
phyi_pv_m_cfifo_1_valid => phyi.pv_m_cfifo(1).valid,
phyi_pv_m_cfifo_1_err => phyi.pv_m_cfifo(1).err,
phyi_pv_m_cfifo_2_data => phyi.pv_m_cfifo(2).data,
phyi_pv_m_cfifo_2_last => phyi.pv_m_cfifo(2).last,
phyi_pv_m_cfifo_2_stlast => phyi.pv_m_cfifo(2).stlast,
phyi_pv_m_cfifo_2_hold => phyi.pv_m_cfifo(2).hold,
phyi_pv_m_cfifo_2_valid => phyi.pv_m_cfifo(2).valid,
phyi_pv_m_cfifo_2_err => phyi.pv_m_cfifo(2).err,
phyi_pr_m_addr => phyi.pr_m_addr,
phyi_pr_m_cbe_data => phyi.pr_m_cbe_data,
phyi_pr_m_cbe_cmd => phyi.pr_m_cbe_cmd,
phyi_pr_m_first => phyi.pr_m_first,
phyi_pv_m_term => phyi.pv_m_term,
phyi_pr_m_ltimer => phyi.pr_m_ltimer,
phyi_pr_m_burst => phyi.pr_m_burst,
phyi_pr_m_abort => phyi.pr_m_abort,
phyi_pr_m_perren => phyi.pr_m_perren,
phyi_pr_m_done_fifo => phyi.pr_m_done_fifo,
phyi_t_abort => phyi.t_abort,
phyi_t_ready => phyi.t_ready,
phyi_t_retry => phyi.t_retry,
phyi_pr_t_state => phyi.pr_t_state,
phyi_pv_t_state => phyi.pv_t_state,
phyi_pr_t_fstate => phyi.pr_t_fstate,
phyi_pr_t_cfifo_0_data => phyi.pr_t_cfifo(0).data,
phyi_pr_t_cfifo_0_last => phyi.pr_t_cfifo(0).last,
phyi_pr_t_cfifo_0_stlast => phyi.pr_t_cfifo(0).stlast,
phyi_pr_t_cfifo_0_hold => phyi.pr_t_cfifo(0).hold,
phyi_pr_t_cfifo_0_valid => phyi.pr_t_cfifo(0).valid,
phyi_pr_t_cfifo_0_err => phyi.pr_t_cfifo(0).err,
phyi_pr_t_cfifo_1_data => phyi.pr_t_cfifo(1).data,
phyi_pr_t_cfifo_1_last => phyi.pr_t_cfifo(1).last,
phyi_pr_t_cfifo_1_stlast => phyi.pr_t_cfifo(1).stlast,
phyi_pr_t_cfifo_1_hold => phyi.pr_t_cfifo(1).hold,
phyi_pr_t_cfifo_1_valid => phyi.pr_t_cfifo(1).valid,
phyi_pr_t_cfifo_1_err => phyi.pr_t_cfifo(1).err,
phyi_pr_t_cfifo_2_data => phyi.pr_t_cfifo(2).data,
phyi_pr_t_cfifo_2_last => phyi.pr_t_cfifo(2).last,
phyi_pr_t_cfifo_2_stlast => phyi.pr_t_cfifo(2).stlast,
phyi_pr_t_cfifo_2_hold => phyi.pr_t_cfifo(2).hold,
phyi_pr_t_cfifo_2_valid => phyi.pr_t_cfifo(2).valid,
phyi_pr_t_cfifo_2_err => phyi.pr_t_cfifo(2).err,
phyi_pv_t_diswithout => phyi.pv_t_diswithout,
phyi_pr_t_stoped => phyi.pr_t_stoped,
phyi_pr_t_lcount => phyi.pr_t_lcount,
phyi_pr_t_first_word => phyi.pr_t_first_word,
phyi_pr_t_cur_acc_0_read => phyi.pr_t_cur_acc_0_read,
phyi_pv_t_hold_write => phyi.pv_t_hold_write,
phyi_pv_t_hold_reset => phyi.pv_t_hold_reset,
phyi_pr_conf_comm_perren => phyi.pr_conf_comm_perren,
phyi_pr_conf_comm_serren => phyi.pr_conf_comm_serren,
--pcio : out pci_out_type,
pcio_aden => pcio.aden,
pcio_vaden => pcio.vaden,
pcio_cbeen => pcio.cbeen,
pcio_frameen => pcio.frameen,
pcio_irdyen => pcio.irdyen,
pcio_trdyen => pcio.trdyen,
pcio_devselen => pcio.devselen,
pcio_stopen => pcio.stopen,
pcio_ctrlen => pcio.ctrlen,
pcio_perren => pcio.perren,
pcio_paren => pcio.paren,
pcio_reqen => pcio.reqen,
pcio_locken => pcio.locken,
pcio_serren => pcio.serren,
pcio_inten => pcio.inten,
pcio_vinten => pcio.vinten,
pcio_req => pcio.req,
pcio_ad => pcio.ad,
pcio_cbe => pcio.cbe,
pcio_frame => pcio.frame,
pcio_irdy => pcio.irdy,
pcio_trdy => pcio.trdy,
pcio_devsel => pcio.devsel,
pcio_stop => pcio.stop,
pcio_perr => pcio.perr,
pcio_serr => pcio.serr,
pcio_par => pcio.par,
pcio_lock => pcio.lock,
pcio_power_state => pcio.power_state,
pcio_pme_enable => pcio.pme_enable,
pcio_pme_clear => pcio.pme_clear,
pcio_int => pcio.int,
pcio_rst => pcio.rst,
--phyo : out grpci2_phy_out_type
phyo_pciv_rst => phyo.pciv.rst,
phyo_pciv_gnt => phyo.pciv.gnt,
phyo_pciv_idsel => phyo.pciv.idsel,
phyo_pciv_ad => phyo.pciv.ad,
phyo_pciv_cbe => phyo.pciv.cbe,
phyo_pciv_frame => phyo.pciv.frame,
phyo_pciv_irdy => phyo.pciv.irdy,
phyo_pciv_trdy => phyo.pciv.trdy,
phyo_pciv_devsel => phyo.pciv.devsel,
phyo_pciv_stop => phyo.pciv.stop,
phyo_pciv_lock => phyo.pciv.lock,
phyo_pciv_perr => phyo.pciv.perr,
phyo_pciv_serr => phyo.pciv.serr,
phyo_pciv_par => phyo.pciv.par,
phyo_pciv_host => phyo.pciv.host,
phyo_pciv_pci66 => phyo.pciv.pci66,
phyo_pciv_pme_status => phyo.pciv.pme_status,
phyo_pciv_int => phyo.pciv.int,
phyo_pr_m_state => phyo.pr_m_state,
phyo_pr_m_last => phyo.pr_m_last,
phyo_pr_m_hold => phyo.pr_m_hold,
phyo_pr_m_term => phyo.pr_m_term,
phyo_pr_t_hold => phyo.pr_t_hold,
phyo_pr_t_stop => phyo.pr_t_stop,
phyo_pr_t_abort => phyo.pr_t_abort,
phyo_pr_t_diswithout => phyo.pr_t_diswithout,
phyo_pr_t_addr_perr => phyo.pr_t_addr_perr,
phyo_pcirsto => phyo.pcirsto,
phyo_pr_po_ad => phyo.pr_po.ad,
phyo_pr_po_aden => phyo.pr_po.aden,
phyo_pr_po_cbe => phyo.pr_po.cbe,
phyo_pr_po_cbeen => phyo.pr_po.cbeen,
phyo_pr_po_frame => phyo.pr_po.frame,
phyo_pr_po_frameen => phyo.pr_po.frameen,
phyo_pr_po_irdy => phyo.pr_po.irdy,
phyo_pr_po_irdyen => phyo.pr_po.irdyen,
phyo_pr_po_trdy => phyo.pr_po.trdy,
phyo_pr_po_trdyen => phyo.pr_po.trdyen,
phyo_pr_po_stop => phyo.pr_po.stop,
phyo_pr_po_stopen => phyo.pr_po.stopen,
phyo_pr_po_devsel => phyo.pr_po.devsel,
phyo_pr_po_devselen => phyo.pr_po.devselen,
phyo_pr_po_par => phyo.pr_po.par,
phyo_pr_po_paren => phyo.pr_po.paren,
phyo_pr_po_perr => phyo.pr_po.perr,
phyo_pr_po_perren => phyo.pr_po.perren,
phyo_pr_po_lock => phyo.pr_po.lock,
phyo_pr_po_locken => phyo.pr_po.locken,
phyo_pr_po_req => phyo.pr_po.req,
phyo_pr_po_reqen => phyo.pr_po.reqen,
phyo_pr_po_serren => phyo.pr_po.serren,
phyo_pr_po_inten => phyo.pr_po.inten,
phyo_pr_po_vinten => phyo.pr_po.vinten,
phyo_pio_rst => phyo.pio.rst,
phyo_pio_gnt => phyo.pio.gnt,
phyo_pio_idsel => phyo.pio.idsel,
phyo_pio_ad => phyo.pio.ad,
phyo_pio_cbe => phyo.pio.cbe,
phyo_pio_frame => phyo.pio.frame,
phyo_pio_irdy => phyo.pio.irdy,
phyo_pio_trdy => phyo.pio.trdy,
phyo_pio_devsel => phyo.pio.devsel,
phyo_pio_stop => phyo.pio.stop,
phyo_pio_lock => phyo.pio.lock,
phyo_pio_perr => phyo.pio.perr,
phyo_pio_serr => phyo.pio.serr,
phyo_pio_par => phyo.pio.par,
phyo_pio_host => phyo.pio.host,
phyo_pio_pci66 => phyo.pio.pci66,
phyo_pio_pme_status => phyo.pio.pme_status,
phyo_pio_int => phyo.pio.int,
phyo_poo_ad => phyo.poo.ad,
phyo_poo_aden => phyo.poo.aden,
phyo_poo_cbe => phyo.poo.cbe,
phyo_poo_cbeen => phyo.poo.cbeen,
phyo_poo_frame => phyo.poo.frame,
phyo_poo_frameen => phyo.poo.frameen,
phyo_poo_irdy => phyo.poo.irdy,
phyo_poo_irdyen => phyo.poo.irdyen,
phyo_poo_trdy => phyo.poo.trdy,
phyo_poo_trdyen => phyo.poo.trdyen,
phyo_poo_stop => phyo.poo.stop,
phyo_poo_stopen => phyo.poo.stopen,
phyo_poo_devsel => phyo.poo.devsel,
phyo_poo_devselen => phyo.poo.devselen,
phyo_poo_par => phyo.poo.par,
phyo_poo_paren => phyo.poo.paren,
phyo_poo_perr => phyo.poo.perr,
phyo_poo_perren => phyo.poo.perren,
phyo_poo_lock => phyo.poo.lock,
phyo_poo_locken => phyo.poo.locken,
phyo_poo_req => phyo.poo.req,
phyo_poo_reqen => phyo.poo.reqen,
phyo_poo_serren => phyo.poo.serren,
phyo_poo_inten => phyo.poo.inten,
phyo_poo_vinten => phyo.poo.vinten
);
end generate;
end;
|
gpl-2.0
|
82b8b4c9f898c3208373727d49b74efc
| 0.488282 | 3.183664 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/ddr/ddr1spax_ddr.vhd
| 1 | 40,530 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr1spax_ddr
-- File: ddr1spax_ddr.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Merged 16/32/64-bit DDR/mobile-DDR backend
-- Based on ddrsp*a and ddr2spax_ddr
--------------------------------------------------------------------------------
-- Added features from the original ddrspa:
-- * Separated AHB,DDR parts of controller like for DDR2SPA
-- * 64/32/16 bit interfaces in the same entity
-- * Checkbit support for use with ft_ddr2spax_ahb front-end.
-- * Extended timing fields plus tRAS setting to meet DDR400 timing.
-- * Configurable burst length
-- * Support for PHY:s with read data valid signaling and extra latency
-- Incompatibility/differences to the original ddrspa:
-- * The mobile DDR had an undocumented feature that tRFC was extended with 8
-- cycles if the TRP bit was set. This is replaced by the extended
-- timing fields.
-- * ddrsp16a used a separate read-clock supplied only from the Spartan PHY.
-- * Reads/writes are made as multiple length-2 burst commands.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ddr1spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
nosync : integer := 0;
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
hasdqvalid : integer := 0;
readdly : integer := 0;
regoutput : integer := 1;
ddr400 : integer := 1;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end ddr1spax_ddr;
architecture rtl of ddr1spax_ddr is
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(ddrbits*2);
constant l2ddr_burstlen: integer := l2blen-l2ddrw;
-- constant oepols: std_logic := tosl(oepol);
-- Write buffer dimensions
-- Write buffer is addressable down to 32-bit level on write (AHB) side.
constant wbuf_rabits: integer := 1+l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant wbuf_rdbits: integer := 2*ddrbits;
-- Read buffer dimensions
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := 2*(ddrbits+chkbits);
type ddrstate is (dsidle,dsact1,dsact2,dsact3,dswr1,dswr2,dswr3,dswr4,dswr5,dswr6,
dsrd1,dsrd2,dsrd3,dsrd4,dsreg1,dsreg2,dscmd1,dscmd2,dspdown1,dspdown2,dsref1,
dssrr1,dssrr2);
type ddrinitstate is (disrstdel,disidle,disrun,disfinished);
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(4 downto 0);
trp : std_logic_vector(1 downto 0); -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
ds : std_logic_vector(5 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
mobileen : std_logic; -- Mobile SD support, Mobile SD enabled
txsr : std_logic_vector(5 downto 0); -- Exit Self Refresh timing
txp : std_logic_vector(1 downto 0); -- Exit Power-Down timing
tcke : std_logic; -- Clock enable timing
cl : std_logic; -- CAS latency 2/3 (0/1)
conf : std_logic_vector(63 downto 0); -- PHY control
tras : std_logic_vector(1 downto 0); -- tRAS minimum (6-9 cycles)
twr : std_logic; -- tWR write recovery, 2/3 cycles
end record;
type ddr_reg_type is record
s : ddrstate;
initstate : ddrinitstate;
cfg : sdram_cfg_type;
resp,resp2 : ddr_response_type;
req1,req2 : ddr_request_type;
start1,start2 : std_logic;
start3 : std_logic;
ramaddr : std_logic_vector(rbuf_wabits-1 downto 0);
readpipe : std_logic_vector(4+readdly downto 0);
initpos : std_logic_vector(2 downto 0);
cmdctr : std_logic_vector(7 downto 0);
readdone : std_logic;
refctr : std_logic_vector(17 downto 0);
refpend : std_logic;
idlectr : std_logic_vector(3 downto 0);
pdowns : std_logic_vector(1 downto 0);
sdo_casn : std_logic;
sdo_rasn : std_logic;
sdo_wen : std_logic;
sdo_csn : std_logic_vector(1 downto 0);
sdo_ba : std_logic_vector(1 downto 0);
sdo_address : std_logic_vector(14 downto 0);
sdo_data : std_logic_vector(2*ddrbits-1 downto 0);
sdo_dqm : std_logic_vector(ddrbits/4-1 downto 0);
sdo_cb : std_logic_vector(2*chkbits downto 0);
sdo_ck : std_logic_vector(2 downto 0);
sdo_bdrive : std_logic;
sdo_qdrive : std_logic;
end record;
signal dr,ndr: ddr_reg_type;
constant onev: std_logic_vector(15 downto 0) := x"FFFF";
constant zerov: std_logic_vector(15 downto 0) := x"0000";
signal arst : std_ulogic;
begin
arst <= testrst when (scantest/=0 and ddr_syncrst=0) and testen='1' else ddr_rst;
ddrcomb: process(ddr_rst,sdi,request,frequest,start_tog,dr,wbrdata,testen,testoen,reqsel)
variable dv: ddr_reg_type;
variable o: ddrctrl_out_type;
variable rbw: std_logic;
variable rbwd: std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
variable vstart, vstartd, vdone, incdone: std_logic;
variable vrctr: std_logic_vector(3 downto 0);
variable vreq,vreqf: ddr_request_type;
variable regsd1 : std_logic_vector(31 downto 0);
variable regsd2 : std_logic_vector(31 downto 0);
variable regsd3 : std_logic_vector(31 downto 0);
variable lastreadcmd: std_logic;
variable lastwrite : std_logic;
variable vmaskfirst, vmasklast: std_logic_vector(ddrbits/4-1 downto 0);
variable ea: std_logic_vector(3 downto 2);
variable inc_sdoaddr, inc_ramaddr: std_logic;
variable datavalid: std_logic;
variable vcsf: std_logic_vector(1 downto 0);
variable vrowf: std_logic_vector(14 downto 0);
variable vbankf: std_logic_vector(1 downto 0);
variable vcol,vcoladdr: std_logic_vector(14 downto 1);
variable seqin,seqout: std_logic_vector(3 downto 0);
variable regrdata: std_logic_vector(2*ddrbits-1 downto 0);
variable regad: std_logic_vector(2 downto 0);
variable wrdreg1,wrdreg2,wrdreg3: std_logic_vector(31 downto 0);
variable reqselv: std_logic_vector(3 downto 0);
begin
---------------------------------------------------------------------------
-- Init vars
---------------------------------------------------------------------------
dv := dr;
o := ddrctrl_out_none;
o.bdrive := '1'; o.qdrive := '1';
vdone := dr.resp.done_tog or dr.resp2.done_tog;
vrctr := dr.resp.rctr_gray or dr.resp2.rctr_gray;
incdone := '0';
lastreadcmd := '0';
lastwrite := '0';
reqselv := reqsel & reqsel & reqsel & reqsel;
-- Config registers
regsd1 := (others => '0');
regsd1(31 downto 15) := dr.cfg.refon & dr.cfg.trp(0) & dr.cfg.trfc(2 downto 0) &
dr.cfg.trcd & dr.cfg.bsize & dr.cfg.csize & dr.cfg.command &
dr.cfg.dllrst & dr.cfg.renable & dr.cfg.cke;
regsd1(11 downto 0) := dr.cfg.refresh;
regsd2 := (others => '0');
regsd2(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd2(14 downto 12) := conv_std_logic_vector(log2(ddrbits/8),3);
if mobile/=0 then regsd2(15):='1'; end if;-- Mobile DDR support
regsd2(19 downto 16) := conv_std_logic_vector(confapi, 4);
regsd3 := (others => '0');
regsd3(31) := dr.cfg.mobileen; -- Mobile DDR enable
regsd3(30) := dr.cfg.cl;
regsd3(24 downto 19) := dr.cfg.tcke & dr.cfg.txsr(3 downto 0) & dr.cfg.txp(0);
regsd3(18 downto 16) := dr.cfg.pmode;
regsd3( 7 downto 0) := dr.cfg.ds(2 downto 0) & dr.cfg.tcsr(1 downto 0)
& dr.cfg.pasr(2 downto 0);
-- Extended timing fields for DDR400
if ddr400 /= 0 then
regsd2(20) := '1'; -- Ext. fields available
regsd3(29 downto 28) := dr.cfg.tras;
regsd3(27 downto 26) := dr.cfg.txsr(5 downto 4);
regsd3(25) := dr.cfg.txp(1);
regsd3(11) := dr.cfg.twr;
regsd3(10) := dr.cfg.trp(1);
regsd3(9 downto 8) := dr.cfg.trfc(4 downto 3);
end if;
-- Data path
rbw := '0';
rbwd := (others => '0');
rbwd(ddrbits-1 downto 0) := sdi.data(ddrbits-1 downto 0);
rbwd(2*ddrbits+chkbits-1 downto ddrbits+chkbits) :=
sdi.data(2*ddrbits-1 downto ddrbits);
if chkbits > 0 then
rbwd(ddrbits+chkbits-1 downto ddrbits) := sdi.cb(chkbits-1 downto 0);
rbwd(2*(ddrbits+chkbits)-1 downto 2*ddrbits+chkbits) :=
sdi.cb(2*chkbits-1 downto chkbits);
end if;
dv.sdo_data(ddrbits-1 downto 0) := wbrdata(ddrbits-1 downto 0);
dv.sdo_data(2*ddrbits-1 downto ddrbits) :=
wbrdata(2*ddrbits+chkbits-1 downto ddrbits+chkbits);
dv.sdo_cb(chkbits) := '0'; -- dummy bit just to ensure length>0
if chkbits > 0 then
dv.sdo_cb(chkbits-1 downto 0) := wbrdata(ddrbits+chkbits-1 downto ddrbits);
dv.sdo_cb(2*chkbits-1 downto chkbits) :=
wbrdata(2*(ddrbits+chkbits)-1 downto 2*ddrbits+chkbits);
end if;
---------------------------------------------------------------------------
-- Request handling logic
---------------------------------------------------------------------------
-- Sync request inputs
dv.req1 := request;
dv.req2 := dr.req1;
dv.start1 := start_tog;
dv.start2 := dr.start1;
dv.start3 := dr.start2;
vstart := dr.start2;
vstartd := dr.start3;
vreq := dr.req2;
vreqf := dr.req1;
if nosync/=0 then
vstart:=start_tog;
vstartd:=start_tog;
vreq:=request;
vreqf:=request;
end if;
if nosync > 1 then
vreqf := frequest;
end if;
-- Address muxing
vcsf(0) := genmux(dr.cfg.bsize, vreqf.startaddr(30 downto 23));
vcsf(1) := not vcsf(0);
vbankf := genmux(dr.cfg.bsize, vreqf.startaddr(29 downto 22)) &
genmux(dr.cfg.bsize, vreqf.startaddr(28 downto 21));
case dr.cfg.csize is
when "00" => vrowf := vreqf.startaddr(19+l2ddrw downto 5+l2ddrw);
when "01" => vrowf := vreqf.startaddr(20+l2ddrw downto 6+l2ddrw);
when "10" => vrowf := vreqf.startaddr(21+l2ddrw downto 7+l2ddrw);
when others => vrowf := vreqf.startaddr(22+l2ddrw downto 8+l2ddrw);
end case;
vcol := vreq.startaddr(l2ddrw+10 downto l2ddrw-3);
-- vcoladdr==vcol when dr.ramaddr==lsb of vcol
vcoladdr := vcol(14 downto rbuf_wabits+1) & dr.ramaddr;
-- Generate data mask
-- Mask for 32-bit and larger bursts and single access
vmaskfirst := (others => '0');
vmasklast := (others => '0');
ea := vreq.endaddr(3 downto 2);
if vreq.hsize(1 downto 0)="11" then ea(2):='1'; end if;
if vreq.hsize(2)='1' then ea(3 downto 2):="11"; end if;
case ddrbits is
when 64 =>
-- 64-bit DDR width
case vreq.startaddr(3 downto 2) is
when "11" => vmaskfirst := "1111111111110000";
when "10" => vmaskfirst := "1111111100000000";
when "01" => vmaskfirst := "1111000000000000";
when others => vmaskfirst := "0000000000000000";
end case;
case ea(3 downto 2) is
when "11" => vmasklast := "0000000000000000";
when "10" => vmasklast := "0000000000001111";
when "01" => vmasklast := "0000000011111111";
when others => vmasklast := "0000111111111111";
end case;
if vreq.hsize(2 downto 1)="00" then
if vreq.startaddr(1)='1' then
vmaskfirst := vmaskfirst or "1100110011001100";
else
vmaskfirst := vmaskfirst or "0011001100110011";
end if;
end if;
if vreq.hsize="000" then
if vreq.startaddr(0)='1' then
vmaskfirst := vmaskfirst or "1010101010101010";
else
vmaskfirst := vmaskfirst or "0101010101010101";
end if;
end if;
when 32 =>
-- 32-bit DDR width
case vreq.startaddr(2) is
when '1' => vmaskfirst := "11110000";
when others => vmaskfirst := "00000000";
end case;
case ea(2) is
when '1' => vmasklast := "00000000";
when others => vmasklast := "00001111";
end case;
if vreq.hsize(2 downto 1)="00" then
if vreq.startaddr(1)='1' then
vmaskfirst := vmaskfirst or "11001100";
else
vmaskfirst := vmaskfirst or "00110011";
end if;
end if;
if vreq.hsize="000" then
if vreq.startaddr(0)='1' then
vmaskfirst := vmaskfirst or "10101010";
else
vmaskfirst := vmaskfirst or "01010101";
end if;
end if;
when others =>
-- 16-bit DDR width
if vreq.hsize(2 downto 1)="00" then
if vreq.startaddr(1)='1' then
vmaskfirst := vmaskfirst or "1100";
else
vmaskfirst := vmaskfirst or "0011";
end if;
end if;
if vreq.hsize="000" then
if vreq.startaddr(0)='1' then
vmaskfirst := vmaskfirst or "1010";
else
vmaskfirst := vmaskfirst or "0101";
end if;
end if;
end case;
-- Register read/write data muxing
regrdata := (others => '0');
case ddrbits is
when 64 =>
regad := vreq.startaddr(4 downto 2);
regrdata := regsd1 & regsd2 & regsd3 & x"00000000";
if confapi /= 0 and regad(2)='1' then
regrdata(95 downto 32) := dr.cfg.conf(31 downto 0) & dr.cfg.conf(63 downto 32);
end if;
wrdreg1 := wbrdata(128+chkbits-1 downto 96+chkbits);
wrdreg2 := wbrdata(96+chkbits-1 downto 64+chkbits);
wrdreg3 := wbrdata(63 downto 32);
when 32 =>
regad := dr.ramaddr(1 downto 0) & vreq.startaddr(2);
if regad(1)='0' then
regrdata := regsd1 & regsd2;
if confapi /= 0 and regad(2)='1' then
regrdata := regsd1 & dr.cfg.conf(31 downto 0);
end if;
else
regrdata := regsd3 & regsd2;
if confapi /= 0 and regad(2)='1' then
regrdata := dr.cfg.conf(63 downto 0);
end if;
end if;
wrdreg1 := wbrdata(64+chkbits-1 downto 32+chkbits);
wrdreg2 := wbrdata(31 downto 0);
wrdreg3 := wbrdata(64+chkbits-1 downto 32+chkbits);
when others =>
regad := dr.ramaddr(2 downto 0);
case regad is
when "000"|"100" => regrdata := regsd1;
when "001" => regrdata := regsd2;
when "010" => regrdata := regsd3;
when "101" =>
if confapi /= 0 then
regrdata := dr.cfg.conf(31 downto 0);
else
regrdata := regsd2;
end if;
when "110" =>
if confapi /= 0 then
regrdata := dr.cfg.conf(63 downto 32);
else
regrdata := regsd3;
end if;
when others => regrdata := regsd3;
end case;
wrdreg1 := wbrdata(31+chkbits downto 16+chkbits) & wbrdata(15 downto 0);
wrdreg2 := wbrdata(31+chkbits downto 16+chkbits) & wbrdata(15 downto 0);
wrdreg3 := wbrdata(31+chkbits downto 16+chkbits) & wbrdata(15 downto 0);
end case;
---------------------------------------------------------------------------
-- Main DDR-SDRAM access FSM
---------------------------------------------------------------------------
dv.sdo_ck := "111";
dv.sdo_rasn := '1';
dv.sdo_casn := '1';
dv.sdo_wen := '1';
dv.sdo_dqm := (others => '1');
dv.sdo_bdrive := '1';
dv.sdo_qdrive := '1';
inc_sdoaddr := '0';
inc_ramaddr := '0';
dv.readpipe := dr.readpipe(3+readdly downto 0) & '0';
datavalid := '0';
if hasdqvalid/=0 then
datavalid := sdi.datavalid;
if dr.s/=dsrd1 and dr.s/=dsrd2 and dr.s/=dsrd3 and dr.s/=dsrd4 and dr.s/=dssrr2 then
datavalid := '0';
end if;
end if;
if hasdqvalid=0 then
if dr.cfg.cl='0' then
datavalid := dr.readpipe(3+readdly);
else
datavalid := dr.readpipe(4+readdly);
end if;
end if;
if datavalid='1' and dr.s/=dsidle then
inc_ramaddr := '1';
rbw := '1';
vrctr(l2ddr_burstlen-1 downto 0) :=
nextgray(vrctr(l2ddr_burstlen-1 downto 0));
if dr.ramaddr=onev(dr.ramaddr'length-1 downto 0) then
dv.readdone := '1';
incdone:='1';
vrctr := "0000";
end if;
end if;
if dr.sdo_address((l2blen-l2ddrw) downto 1)=onev((l2blen-l2ddrw) downto 1) then
lastreadcmd := '1';
end if;
if dr.ramaddr=vreq.endaddr((l2blen-3)-1 downto (l2ddrw-3)) then
lastwrite := '1';
end if;
-- Update EMR when ds, tcsr or pasr change
if dr.cfg.command="000" and
( dr.cfg.ds(2 downto 0) /= dr.cfg.ds(5 downto 3) or
dr.cfg.tcsr(1 downto 0) /= dr.cfg.tcsr(3 downto 2) or
dr.cfg.pasr(2 downto 0) /= dr.cfg.pasr(5 downto 3) ) then
dv.cfg.command := "111";
end if;
-- Auto-refresh counter
dv.refctr := std_logic_vector(unsigned(dr.refctr)+1);
if (dr.refctr(11 downto 0)=dr.cfg.refresh and dr.cfg.refon='1') then
dv.refpend := '1';
dv.refctr := (others => '0');
end if;
if dr.initstate/=disrstdel and (dr.cfg.refon='0' or dr.cfg.pmode(1)='1') then
dv.refpend := '0';
dv.refctr := (others => '0');
end if;
dv.idlectr := "0000";
dv.pdowns(0) := '0';
if not (dr.cmdctr=(dr.cmdctr'range => '0')) and dr.pdowns(0)='0' then
dv.cmdctr := std_logic_vector(unsigned(dr.cmdctr)-1);
end if;
case dr.s is
when dsidle =>
vrctr := "0000";
dv.sdo_ck := "111";
if dr.cfg.pmode /= "000" then
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
end if;
dv.sdo_csn := "11";
if dr.refpend='1' then
dv.sdo_csn := "00";
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.s := dsref1;
dv.refpend := '0';
elsif vstart /= vdone and dr.cfg.renable='0' then
-- Transfer
dv.sdo_csn := vcsf;
dv.sdo_address := vrowf;
dv.sdo_ba := vbankf;
dv.sdo_rasn := '0' or vreqf.hio;
dv.s := dsact1;
elsif dr.cfg.command /= "000" then
dv.s := dscmd1;
elsif dr.idlectr="1111" then
dv.s := dspdown1;
end if;
when dsact1 =>
dv.ramaddr := vcol(rbuf_wabits downto 1);
if ddr400 /= 0 then
dv.cmdctr(2 downto 0) := "1" & dr.cfg.tras; -- t(RAS)-2t(CK) = TRAS+6-2 = TRAS+4
else
dv.cmdctr(2 downto 0) := "10" & dr.cfg.trcd;
end if;
dv.readdone := '0';
if dr.cfg.trcd='1' then
dv.s := dsact2;
else
dv.s := dsact3;
end if;
if vreq.hio='1' then
dv.s := dsreg1;
end if;
when dsact2 =>
dv.s := dsact3;
when dsact3 =>
dv.sdo_casn := '0';
dv.sdo_wen := not vreq.hwrite;
dv.sdo_qdrive := not vreq.hwrite;
-- dv.sdo_address := vcol(12 downto 10) & '0' & vcol(9 downto 1) & '0';
-- Since part of column is stored in ramaddr in dsact1, use that to
-- reduce fanout on vreq.startaddr
dv.sdo_address := vcoladdr(13 downto 10) & '0' & vcoladdr(9 downto 1) & '0';
if vreq.hwrite='1' then
dv.s := dswr1;
else
dv.s := dsrd1;
dv.readpipe(0) := '1';
end if;
when dswr1 =>
-- NOP,NOP,[WR]: issue either WR+D or NOP+D
dv.sdo_bdrive := '0';
dv.sdo_qdrive := '0';
inc_sdoaddr := '1';
inc_ramaddr := '1';
if lastwrite='1' then
dv.sdo_dqm := vmaskfirst or vmasklast;
dv.s := dswr3;
else
dv.sdo_casn := '0';
dv.sdo_wen := '0';
dv.sdo_dqm := vmaskfirst;
dv.s := dswr2;
end if;
when dswr2 =>
dv.sdo_dqm := (others => '0');
dv.sdo_bdrive := '0';
dv.sdo_qdrive := '0';
inc_sdoaddr := '1';
inc_ramaddr := '1';
if lastwrite='0' then
dv.sdo_casn := '0';
dv.sdo_wen := '0';
else
dv.s := dswr3;
dv.sdo_dqm := vmasklast;
end if;
when dswr3 =>
-- ...,WR+D,WR+D,[NOP+D]: issue NOP
dv.sdo_qdrive := '0';
dv.sdo_dqm := (others => '1');
dv.s := dswr4;
incdone := '1';
when dswr4 =>
-- Issue more NOP:s to meet tWR
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
if dr.idlectr(0)=dr.cfg.twr then
dv.s := dswr5;
end if;
when dswr5 =>
-- Issue NOP:s until tRAS met.
if dr.cmdctr(2 downto 0)="000" then
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.s := dswr6;
end if;
when dswr6 =>
-- PRE: issue one or two NOP:s depending on trp setting
if dr.idlectr(1 downto 0)=dr.cfg.trp then
dv.s := dsidle;
else
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
end if;
when dsrd1 =>
inc_sdoaddr := '1';
if lastreadcmd='0' then
dv.sdo_casn := '0';
dv.readpipe(0):='1';
elsif dr.cmdctr(2 downto 0)="000" then
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.s := dsrd3;
else
dv.s := dsrd2;
end if;
when dsrd2 =>
if dr.cmdctr(2 downto 0)="000" then
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.s := dsrd3;
end if;
when dsrd3 =>
if dr.idlectr(1 downto 0)=dr.cfg.trp then
if dv.readdone='1' then
dv.s := dsidle;
else
dv.s := dsrd4;
end if;
else
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
end if;
when dsrd4 =>
if dv.readdone='1' then
dv.s := dsidle;
end if;
when dsreg1 =>
rbw := '1';
rbwd(2*ddrbits+chkbits-1 downto ddrbits+chkbits) := regrdata(2*ddrbits-1 downto ddrbits);
rbwd(ddrbits-1 downto 0) := regrdata(ddrbits-1 downto 0);
if vreq.hwrite='1' then
dv.s := dsreg2;
elsif regad="100" and dr.cfg.mobileen='1' then
dv.sdo_address := (others => '0');
dv.sdo_ba := "01";
dv.sdo_csn := "10";
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.sdo_wen := '0';
dv.s := dssrr1;
dv.cmdctr(0) := '1';
null;
else
incdone := '1';
dv.s := dsidle;
end if;
when dsreg2 =>
case regad is
when "000" =>
dv.cfg.refon := wrdreg1(31);
dv.cfg.trp(0) := wrdreg1(30);
dv.cfg.trfc(2 downto 0) := wrdreg1(29 downto 27);
dv.cfg.trcd := wrdreg1(26);
dv.cfg.bsize := wrdreg1(25 downto 23);
dv.cfg.csize := wrdreg1(22 downto 21);
dv.cfg.command := wrdreg1(20 downto 18);
dv.cfg.dllrst := wrdreg1(17);
dv.cfg.renable := wrdreg1(16);
dv.cfg.cke := wrdreg1(15);
dv.cfg.refresh := wrdreg1(11 downto 0);
when "010" =>
dv.cfg.mobileen := wrdreg3(31);
dv.cfg.cl := wrdreg3(30);
dv.cfg.tcke := wrdreg3(24);
dv.cfg.txsr(3 downto 0) := wrdreg3(23 downto 20);
dv.cfg.txp(0) := wrdreg3(19);
dv.cfg.pmode := wrdreg3(18 downto 16);
dv.cfg.ds (5 downto 3) := wrdreg3(7 downto 5);
dv.cfg.tcsr(3 downto 2) := wrdreg3(4 downto 3);
dv.cfg.pasr(5 downto 3) := wrdreg3(2 downto 0);
-- Extended DDR400 fields
dv.cfg.tras := wrdreg3(29 downto 28);
dv.cfg.txsr(5 downto 4) := wrdreg3(27 downto 26);
dv.cfg.txp(1) := wrdreg3(25);
dv.cfg.twr := wrdreg3(11);
dv.cfg.trp(1) := wrdreg3(10);
dv.cfg.trfc(4 downto 3) := wrdreg3(9 downto 8);
when "101" =>
if confapi /= 0 then
dv.cfg.conf(31 downto 0) := wrdreg2;
end if;
when "110" =>
if confapi /= 0 then
dv.cfg.conf(63 downto 32) := wrdreg3;
end if;
when others =>
null;
end case;
incdone := '1';
dv.s := dsidle;
when dscmd1 =>
dv.sdo_csn := (others => '0');
dv.sdo_address(10) := '1';
dv.cfg.command := "000";
dv.s := dscmd2;
case dr.cfg.command is
when "010" => -- PRECHARGE ALL
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.cmdctr(1 downto 0) := "11";
when "100" => -- AUTO-REFRESH
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.cmdctr(4 downto 0) := dr.cfg.trfc;
when "110" => -- MODE REGISTER
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.sdo_wen := '0';
dv.sdo_ba := "00";
dv.sdo_address := "00000000" & "01" & dr.cfg.cl & "0001";
if dr.cfg.mobileen='0' then
dv.sdo_address(8) := dr.cfg.dllrst;
end if;
if dr.cfg.dllrst='1' then
dv.cmdctr := std_logic_vector(to_unsigned(200,dr.cmdctr'length));
end if;
when "111" => -- EXT. MODE REGISTER
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.sdo_wen := '0';
if dr.cfg.mobileen='1' then
dv.sdo_ba := "10";
dv.sdo_address := "0000000" & dr.cfg.ds(5 downto 3) & dr.cfg.tcsr(3 downto 2)
& dr.cfg.pasr(5 downto 3);
else
dv.sdo_ba := "01";
dv.sdo_address := "000000000000000"; -- bit0=0 -> DLL enable
end if;
dv.cfg.pasr(2 downto 0) := dr.cfg.pasr(5 downto 3);
dv.cfg.ds(2 downto 0) := dr.cfg.ds(5 downto 3);
dv.cfg.tcsr(1 downto 0) := dr.cfg.tcsr(3 downto 2);
when others => null;
end case;
when dscmd2 =>
if dr.cmdctr=(dr.cmdctr'range => '0') then
dv.s := dsidle;
end if;
when dspdown1 =>
dv.sdo_csn := "00";
if dr.cfg.pmode(0)='1' or dr.cfg.pmode(1)='1' then
dv.cfg.cke := '0';
end if;
if dr.cfg.pmode(1)='1' then
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
end if;
if dr.cfg.pmode(2)='1' and dr.cfg.pmode(0)='1' then
dv.sdo_wen := '0';
end if;
if dr.cfg.pmode(0)='1' then
dv.cmdctr(1 downto 0) := dr.cfg.txp;
end if;
if dr.cfg.pmode(1)='1' then
if dr.cfg.mobileen='1' then
dv.cmdctr(5 downto 0) := dr.cfg.txsr;
else
dv.cmdctr(7 downto 0) := std_logic_vector(to_unsigned(200,8));
end if;
end if;
dv.pdowns(1) := '0';
dv.s := dspdown2;
when dspdown2 =>
dv.pdowns(0) := '1';
if dr.pdowns(0)='0' and dr.cmdctr=(dr.cmdctr'range => '0') then
dv.pdowns(1):='1';
end if;
if dr.cfg.pmode(2)='1' and dr.cfg.pmode(0)='0' then
dv.sdo_ck := "000";
end if;
if dr.cfg.pmode(1)='1' then
dv.refpend := '1';
end if;
if (dr.refpend='1' and dr.cfg.pmode(1)='0') or vstart /= vdone then
if (dr.pdowns(0) or not dr.cfg.tcke)='1' then
dv.cfg.cke := '1';
if dr.pdowns(1)='1' then
dv.s := dsidle;
else
dv.s := dscmd2;
dv.pdowns(0) := '0';
end if;
end if;
end if;
when dsref1 =>
dv.s := dscmd2;
dv.cmdctr(4 downto 0) := dr.cfg.trfc;
when dssrr1 =>
if dr.cmdctr(0)='0' then
dv.sdo_casn := '0';
dv.readpipe(0):='1';
dv.s := dssrr2;
end if;
when dssrr2 =>
if datavalid='1' then
incdone := '1';
dv.s := dsidle;
end if;
end case;
if inc_sdoaddr='1' then
dv.sdo_address(l2blen-l2ddrw downto 1) :=
std_logic_vector(unsigned(dr.sdo_address(l2blen-l2ddrw downto 1))+1);
end if;
if inc_ramaddr='1' then
dv.ramaddr := std_logic_vector(unsigned(dr.ramaddr)+1);
end if;
-- Update the done flags
dv.resp.done_tog := (dr.resp.done_tog xor incdone) and (not reqsel);
dv.resp.rctr_gray := vrctr and (not reqselv);
dv.resp2.done_tog := (dr.resp2.done_tog xor incdone) and reqsel;
dv.resp2.rctr_gray := vrctr and reqselv;
---------------------------------------------------------------------------
-- DDR Init Sequence FSM
---------------------------------------------------------------------------
-- Command sequence lookup table
seqin := dr.cfg.mobileen & dr.initpos;
case seqin is
-- Mobile DDR
when "1100" => seqout := "0010"; -- PRECHARGE ALL
when "1011" => seqout := "0100"; -- AUTO REFRESH #1
when "1010" => seqout := "0100"; -- AUTO REFRESH #2
when "1001" => seqout := "0110"; -- MODE REG
when "1000" => seqout := "0111"; -- EXT MODE REG
-- Normal DDR
when "0110" => seqout := "0010"; -- PRECHARGE ALL
when "0101" => seqout := "0111"; -- EXT MODE REG En DLL
when "0100" => seqout := "1110"; -- MODE REG Rst DLL
when "0011" => seqout := "0010"; -- PRECHARGE ALL
when "0010" => seqout := "0100"; -- AUTO REFRESH #1
when "0001" => seqout := "0100"; -- AUTO REFRESH #2
when "0000" => seqout := "0110"; -- MODE REG NoRst DLL
when others => seqout := "0000";
end case;
case dr.initstate is
when disrstdel =>
if dr.refctr=std_logic_vector(to_unsigned(MHz*rstdel,dr.refctr'length)) then
dv.initstate := disidle;
if pwron=0 then dv.cfg.renable:='0'; end if;
end if;
-- Bypass reset delay by writing anything to regsd2
if vstartd='1' and (vreq.hio='1' and vreq.hwrite='1' and vreq.endaddr(4 downto 2)="001") then
dv.initstate := disidle;
if pwron=0 then dv.cfg.renable:='0'; end if;
end if;
when disidle =>
if dr.cfg.renable='1' then
dv.cfg.cke := '1';
if dr.cfg.cke='1' then
dv.initpos := "111";
dv.initstate := disrun;
end if;
end if;
when disrun =>
if dr.cfg.command="000" then
dv.cfg.dllrst := seqout(3);
dv.cfg.command := seqout(2 downto 0);
dv.initpos := std_logic_vector(unsigned(dr.initpos)-1);
if dr.initpos="000" then
dv.initstate := disfinished;
end if;
end if;
when disfinished =>
if dr.cfg.command="000" then
dv.cfg.renable := '0';
dv.cfg.refon := '1';
dv.initstate := disidle;
end if;
end case;
---------------------------------------------------------------------------
-- Reset
---------------------------------------------------------------------------
if ddr_rst='0' then
dv.s := dsidle;
dv.cmdctr := (others => '0');
dv.refctr := (others => '0');
dv.resp := ddr_response_none;
dv.resp2 := ddr_response_none;
dv.initstate := disrstdel;
dv.refpend := '0';
-- Reset cfg record
dv.cfg.command := "000";
dv.cfg.csize := conv_std_logic_vector(col-9, 2);
dv.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
dv.cfg.refon := '0';
dv.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
dv.cfg.dllrst := '0';
dv.cfg.pasr := (others => '0');
dv.cfg.tcsr := (others => '0');
dv.cfg.ds := (others => '0');
dv.cfg.pmode := (others => '0');
dv.cfg.txsr := conv_std_logic_vector(120*MHz/1000, 6);
dv.cfg.txp := "01";
dv.cfg.cl := '0'; -- CL = 3/2 -- ****
dv.cfg.tcke := '1';
if MHz > 100 then
dv.cfg.trcd := '1';
else dv.cfg.trcd := '0';
end if;
if MHz > 100 then
dv.cfg.trp := "01";
else dv.cfg.trp := "00";
end if;
dv.cfg.renable := '1'; -- Updated in disrstdel state
if mobile >= 2 then
dv.cfg.mobileen := '1'; -- Default: Mobile DDR
else dv.cfg.mobileen := '0';
end if;
if mobile >= 2 then
dv.cfg.trfc := conv_std_logic_vector(98*MHz/1000-2, 5);
else dv.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 5);
end if;
if ddr_syncrst /= 0 then
dv.sdo_ck := "000";
if mobile >= 2 then
dv.cfg.cke := '1';
else dv.cfg.cke := '0';
end if;
end if;
if confapi /= 0 then
dv.cfg.conf(31 downto 0) := conv_std_logic_vector(conf0, 32); --x"0000A0A0";
dv.cfg.conf(63 downto 32) := conv_std_logic_vector(conf1, 32); --x"00060606";
else
dv.cfg.conf := (others => '0');
end if;
if MHz > 175 then
dv.cfg.tras := "10";
elsif MHz > 150 then
dv.cfg.tras := "01";
else
dv.cfg.tras := "00";
end if;
if MHz > 133 then
dv.cfg.twr := '1';
else
dv.cfg.twr := '0';
end if;
dv.sdo_csn := "11";
dv.sdo_dqm := (others => '1');
dv.sdo_wen := '1';
dv.sdo_rasn := '1';
dv.sdo_casn := '1';
-- Extra reset for X-sensitive techs
dv.ramaddr := (others => '0');
end if;
---------------------------------------------------------------------------
-- Static logic/forced regs, etc
---------------------------------------------------------------------------
-- Force mobile disable/enabled
if mobile=0 then dv.cfg.mobileen := '0'; end if;
if mobile=3 then dv.cfg.mobileen := '1'; end if;
if mobile=0 then
dv.cfg.pasr := (others => '0');
dv.cfg.tcsr := (others => '0');
dv.cfg.ds := (others => '0');
dv.cfg.pmode := (others => '0');
dv.cfg.txp := "00";
dv.cfg.txsr := (others => '0');
dv.cfg.tcke := '0';
end if;
if ddr400=0 then
dv.cfg.tras := "00";
dv.cfg.txsr(5 downto 4) := "00";
dv.cfg.txp(1) := '0';
dv.cfg.trp(1) := '0';
dv.cfg.trfc(4 downto 3) := "00";
dv.cfg.twr := '0';
end if;
-- Assign sdo
o.bdrive := '1'; o.qdrive := '1'; --Temp.
o.sdck := dr.sdo_ck;
if ddr_syncrst/=0 and phyptctrl/=0 then
o.sdck := o.sdck and (o.sdck'range => ddr_rst);
end if;
if regoutput /= 0 then
o.casn := dr.sdo_casn;
o.rasn := dr.sdo_rasn;
o.sdwen := dr.sdo_wen;
o.sdcsn := dr.sdo_csn;
o.ba := '0' & dr.sdo_ba;
o.address := dr.sdo_address;
o.sdcke := (others => dr.cfg.cke);
if ddr_syncrst /= 0 and phyptctrl /= 0 then
if ddr_rst='0' then
if mobile >= 2 then o.sdcke := (others => '1');
else o.sdcke := (others => '0');
end if;
end if;
end if;
o.data(2*ddrbits-1 downto 0) := dr.sdo_data;
o.dqm(ddrbits/4-1 downto 0) := dr.sdo_dqm;
if chkbits > 0 then
o.cb(2*chkbits-1 downto 0) := dr.sdo_cb(2*chkbits-1 downto 0);
end if;
o.bdrive := dr.sdo_bdrive;
o.qdrive := dr.sdo_qdrive;
else
o.casn := dv.sdo_casn;
o.rasn := dv.sdo_rasn;
o.sdwen := dv.sdo_wen;
o.sdcsn := dv.sdo_csn;
o.ba := '0' & dv.sdo_ba;
o.address := dv.sdo_address;
o.sdcke := (others => dv.cfg.cke);
o.data(2*ddrbits-1 downto 0) := dv.sdo_data;
o.dqm(ddrbits/4-1 downto 0) := dv.sdo_dqm;
if chkbits > 0 then
o.cb(2*chkbits-1 downto 0) := dv.sdo_cb(2*chkbits-1 downto 0);
end if;
o.bdrive := dv.sdo_bdrive;
o.qdrive := dv.sdo_qdrive;
end if;
for x in 7 downto 0 loop
o.cbdqm(x) := o.dqm(2*x);
end loop;
-- Diag access
if vreq.maskcb='1' then
o.cbdqm := (others => '1');
end if;
if vreq.maskdata='1' then
o.dqm := (others => '1');
end if;
if scantest/=0 and phyptctrl/=0 then
if testen='1' then
o.bdrive := testoen;
o.qdrive := testoen;
end if;
end if;
---------------------------------------------------------------------------
-- Drive outputs
---------------------------------------------------------------------------
ndr <= dv;
sdo <= o;
response <= dr.resp;
response2 <= dr.resp2;
rbwrite <= rbw;
rbwaddr <= dr.ramaddr;
rbwdata <= rbwd;
wbraddr <= vdone & dv.ramaddr;
end process;
ddrregs: process(clk_ddr,arst)
begin
if rising_edge(clk_ddr) then
dr <= ndr;
end if;
if ddr_syncrst=0 and arst='0' then
dr.sdo_ck <= "000";
if mobile >= 2 then
dr.cfg.cke <= '1';
else dr.cfg.cke <= '0';
end if;
end if;
end process;
end;
|
gpl-2.0
|
5a39573d8fec08b6b6d6b54b2d65504f
| 0.508907 | 3.52098 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/cypress/ssram/components.vhd
| 3 | 6,170 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Package: components
-- File: components.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Component declaration of Cypress sync-sram
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package components is
component cy7c1354
generic (
fname : string := "ram.srec"; -- File to read from
-- Constant parameters
addr_bits : INTEGER := 18;
data_bits : INTEGER := 36;
-- Timing parameters for -5 (225 Mhz)
tCYC : TIME := 4.4 ns;
tCH : TIME := 1.8 ns;
tCL : TIME := 1.8 ns;
tCO : TIME := 2.8 ns;
tAS : TIME := 1.4 ns;
tCENS : TIME := 1.4 ns;
tWES : TIME := 1.4 ns;
tDS : TIME := 1.4 ns;
tAH : TIME := 0.4 ns;
tCENH : TIME := 0.4 ns;
tWEH : TIME := 0.4 ns;
tDH : TIME := 0.4 ns
-- Timing parameters for -5 (200 Mhz)
--tCYC : TIME := 5.0 ns;
--tCH : TIME := 2.0 ns;
--tCL : TIME := 2.0 ns;
--tCO : TIME := 3.2 ns;
--tAS : TIME := 1.5 ns;
--tCENS : TIME := 1.5 ns;
--tWES : TIME := 1.5 ns;
--tDS : TIME := 1.5 ns;
--tAH : TIME := 0.5 ns;
--tCENH : TIME := 0.5 ns;
--tWEH : TIME := 0.5 ns;
--tDH : TIME := 0.5 ns
-- Timing parameters for -5 (166 Mhz)
--tCYC : TIME := 6.0 ns;
--tCH : TIME := 2.4 ns;
--tCL : TIME := 2.4 ns;
--tCO : TIME := 3.5 ns;
--tAS : TIME := 1.5 ns;
--tCENS : TIME := 1.5 ns;
--tWES : TIME := 1.5 ns;
--tDS : TIME := 1.5 ns;
--tAH : TIME := 0.5 ns;
--tCENH : TIME := 0.5 ns;
--tWEH : TIME := 0.5 ns;
--tDH : TIME := 0.5 ns
);
-- Port Declarations
PORT (
Dq : INOUT STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0); -- Data I/O
Addr : IN STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0); -- Address
Mode : IN STD_LOGIC := '1'; -- Burst Mode
Clk : IN STD_LOGIC; -- Clk
CEN_n : IN STD_LOGIC; -- CEN#
AdvLd_n : IN STD_LOGIC; -- Adv/Ld#
Bwa_n : IN STD_LOGIC; -- Bwa#
Bwb_n : IN STD_LOGIC; -- BWb#
Bwc_n : IN STD_LOGIC; -- Bwc#
Bwd_n : IN STD_LOGIC; -- BWd#
Rw_n : IN STD_LOGIC; -- RW#
Oe_n : IN STD_LOGIC; -- OE#
Ce1_n : IN STD_LOGIC; -- CE1#
Ce2 : IN STD_LOGIC; -- CE2
Ce3_n : IN STD_LOGIC; -- CE3#
Zz : IN STD_LOGIC -- Snooze Mode
);
end component;
component CY7C1380D
GENERIC (
fname : string := "ram.srec"; -- File to read from
-- Constant Parameters
addr_bits : INTEGER := 19; -- This is external address
data_bits : INTEGER := 36;
--Clock timings for 250Mhz
Cyp_tCO : TIME := 2.6 ns; -- Data Output Valid After CLK Rise
Cyp_tCYC : TIME := 4.0 ns; -- Clock cycle time
Cyp_tCH : TIME := 1.7 ns; -- Clock HIGH time
Cyp_tCL : TIME := 1.7 ns; -- Clock LOW time
Cyp_tCHZ : TIME := 2.6 ns; -- Clock to High-Z
Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
Cyp_tOEHZ : TIME := 2.6 ns; -- OE# HIGH to Output High-Z
Cyp_tOELZ : TIME := 0.0 ns; -- OE# LOW to Output Low-Z
Cyp_tOEV : TIME := 2.6 ns; -- OE# LOW to Output Valid
Cyp_tAS : TIME := 1.2 ns; -- Address Set-up Before CLK Rise
Cyp_tADS : TIME := 1.2 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
Cyp_tADVS : TIME := 1.2 ns; -- ADV# Set-up Before CLK Rise
Cyp_tWES : TIME := 1.2 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
Cyp_tDS : TIME := 1.2 ns; -- Data Input Set-up Before CLK Rise
Cyp_tCES : TIME := 1.2 ns; -- Chip Enable Set-up
Cyp_tAH : TIME := 0.3 ns; -- Address Hold After CLK Rise
Cyp_tADH : TIME := 0.3 ns; -- ADSC#, ADSP# Hold After CLK Rise
Cyp_tADVH : TIME := 0.3 ns; -- ADV# Hold After CLK Rise
Cyp_tWEH : TIME := 0.3 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
Cyp_tDH : TIME := 0.3 ns; -- Data Input Hold After CLK Rise
Cyp_tCEH : TIME := 0.3 ns -- Chip Enable Hold After CLK Rise
);
PORT (iZZ : IN STD_LOGIC;
iMode : IN STD_LOGIC;
iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0);
inGW : IN STD_LOGIC;
inBWE : IN STD_LOGIC;
inBWd : IN STD_LOGIC;
inBWc : IN STD_LOGIC;
inBWb : IN STD_LOGIC;
inBWa : IN STD_LOGIC;
inCE1 : IN STD_LOGIC;
iCE2 : IN STD_LOGIC;
inCE3 : IN STD_LOGIC;
inADSP : IN STD_LOGIC;
inADSC : IN STD_LOGIC;
inADV : IN STD_LOGIC;
inOE : IN STD_LOGIC;
ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0);
iCLK : IN STD_LOGIC);
end component;
end;
-- pragma translate_on
|
gpl-2.0
|
c12e8c3acbb51dbe0093cb538cc3f767
| 0.438898 | 3.377121 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-sp605/testbench.vhd
| 1 | 16,716 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
pcie_target_simulation : integer := 0; -- set to 1 to test pci express, only if pcie_target is enabled
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := 40;
signal address : std_logic_vector(24 downto 0);
signal data : std_logic_vector(15 downto 0);
signal button : std_logic_vector(3 downto 0) := "0000";
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal ctsn1, rtsn1 : std_ulogic;
signal ctsn2, rtsn2 : std_ulogic;
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal phy_mii_int_n : std_ulogic;
signal clk27 : std_ulogic := '0';
signal clk200p : std_ulogic := '0';
signal clk200n : std_ulogic := '1';
signal clk33 : std_ulogic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic := '0';
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr3_tdqs_n : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_dq2 : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_reset_n: std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal sysace_mpa : std_logic_vector(6 downto 0);
signal sysace_mpce : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal sysace_mpoe : std_ulogic;
signal sysace_mpwe : std_ulogic;
signal sysace_d : std_logic_vector(7 downto 0);
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(3 downto 0); -- I/O port
signal led : std_logic_vector(3 downto 0); -- I/O port
constant lresp : boolean := false;
-----------------------------------------------------FOR PCIE---------------
function REF_CLK_HALF_CYCLE(FREQ_SEL : integer) return integer is
begin
case FREQ_SEL is
when 0 => return 5000; -- 100 MHz / 5000 ps half-cycle
when 1 => return 4000; -- 125 MHz / 4000 ps half-cycle
when others => return 1; -- invalid case
end case;
end REF_CLK_HALF_CYCLE;
component xilinx_pcie_2_0_rport_v6 is
generic
(
REF_CLK_FREQ : integer := 0;
ALLOW_X8_GEN2 : boolean := FALSE;
PL_FAST_TRAIN : boolean := FALSE;
LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
DEVICE_ID : bit_vector := X"0007";
LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08";
LTSSM_MAX_LINK_WIDTH : bit_vector := X"08";
LINK_CAP_MAX_LINK_WIDTH_int : integer := 8;
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2";
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
USER_CLK_FREQ : integer := 3;
VC0_TX_LASTPACKET : integer := 31;
VC0_RX_RAM_LIMIT : bit_vector := X"03FF";
VC0_TOTAL_CREDITS_CD : integer := 154;
VC0_TOTAL_CREDITS_PD : integer := 154
);
port (
sys_clk : in std_logic;
sys_reset_n : in std_logic;
pci_exp_rxn : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_rxp : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_txn : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_txp : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0)
);
end component xilinx_pcie_2_0_rport_v6;
component sys_clk_gen is
generic
(
HALFCYCLE : integer := 500;
OFFSET : integer := 0
);
port
(
sys_clk : out std_logic
);
end component sys_clk_gen;
component sys_clk_gen_ds is
generic
(
HALFCYCLE : integer := 500;
OFFSET : integer := 0
);
port
(
sys_clk_p : out std_logic;
sys_clk_n : out std_logic
);
end component sys_clk_gen_ds;
--
-- System reset
--
signal sys_reset_n : std_logic;
--
-- System clocks
--
signal rp_sys_clk : std_logic;
signal ep_sys_clk_p : std_logic;
signal ep_sys_clk_n : std_logic;
--
-- PCI-Express Serial Interconnect
--
signal ep_pci_exp_txn : std_logic_vector(0 downto 0);
signal ep_pci_exp_txp : std_logic_vector(0 downto 0);
signal rp_pci_exp_txn : std_logic_vector(0 downto 0);
signal rp_pci_exp_txp : std_logic_vector(0 downto 0);
--
-- Misc. signals
--
signal led_0 : std_logic;
signal led_1 : std_logic;
signal led_2 : std_logic;
-----------------------------------------------pcie end--------------
begin
-- clock and reset
clk27 <= not clk27 after ct * 1 ns;
clk33 <= not clk33 after 15 ns;
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
rst <= not dsurst;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
button <= "0000";
switch <= "0000";
---------------------pcie----------------------------------------------
pcie_sim: if pcie_target_simulation = 1 generate
RP : xilinx_pcie_2_0_rport_v6
generic map (
REF_CLK_FREQ => 1,
PL_FAST_TRAIN => TRUE,
ALLOW_X8_GEN2 => FALSE,
LINK_CAP_MAX_LINK_SPEED => X"1",
DEVICE_ID => X"0007",
LINK_CAP_MAX_LINK_WIDTH => X"01",
LTSSM_MAX_LINK_WIDTH => X"01",
LINK_CAP_MAX_LINK_WIDTH_int => 1,
LINK_CTRL2_TARGET_LINK_SPEED => X"1",
DEV_CAP_MAX_PAYLOAD_SUPPORTED => 2,
USER_CLK_FREQ => 3,
VC0_TX_LASTPACKET => 31,
VC0_RX_RAM_LIMIT => X"03FF",
VC0_TOTAL_CREDITS_CD => 154,
VC0_TOTAL_CREDITS_PD => 154
)
port map (
-- SYS Inteface
sys_clk => rp_sys_clk,
sys_reset_n => sys_reset_n,
-- PCI-Express Interface
pci_exp_txn => rp_pci_exp_txn,
pci_exp_txp => rp_pci_exp_txp,
pci_exp_rxn => ep_pci_exp_txn,
pci_exp_rxp => ep_pci_exp_txp
);
--
-- Generate system clocks and reset
--
CLK_GEN_RP : sys_clk_gen
generic map (
HALFCYCLE => REF_CLK_HALF_CYCLE(1),
OFFSET => 0
)
port map (
sys_clk => rp_sys_clk
);
CLK_GEN_EP : sys_clk_gen_ds
generic map (
HALFCYCLE => REF_CLK_HALF_CYCLE(1),
OFFSET => 0
)
port map (
sys_clk_p => ep_sys_clk_p,
sys_clk_n => ep_sys_clk_n
);
BOARD_INIT : process
begin
report("[" & time'image(now) & "] : System Reset Asserted...");
sys_reset_n <= '0';
for n in 0 to 499 loop
wait until rising_edge(ep_sys_clk_p);
end loop;
report("[" & time'image(now) & "] : System Reset De-asserted...");
sys_reset_n <= '1';
wait until falling_edge(sys_reset_n); -- forever
end process BOARD_INIT;
end generate;
--------------------------------------pcie---------------------------
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk27, clk200p, clk200n, clk33, address(24 downto 1),
data, oen, writen, romsn,
ddr_clk, ddr_clkb, ddr_cke, ddr_odt, ddr_reset_n, ddr_we, ddr_ras, ddr_cas, ddr_dm,
ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_rzq, ddr_zio,
txd1, rxd1, ctsn1, rtsn1, button,
switch, led,
phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data,
phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, phy_mii_int_n,
iic_scl, iic_sda, ddc_scl, ddc_sda,
dvi_iic_scl, dvi_iic_sda,
tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
spi_sel_n, spi_clk, spi_mosi, ep_pci_exp_txn(0), ep_pci_exp_txp(0), rp_pci_exp_txn(0),
rp_pci_exp_txp(0), ep_sys_clk_p, ep_sys_clk_n, sys_reset_n,
sysace_mpa, sysace_mpce, sysace_mpirq, sysace_mpoe,
sysace_mpwe, sysace_d
);
-- prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
-- port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
-- writen, oen);
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 24, fname => promfile)
port map (address(24 downto 1), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
address(0) <= '0';
u1 : ddr3ram
generic map (
width => 16, abits => 13, fname => sdramfile,
speedbin => 3,
ldguard => 1
)
port map (
ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb, odt => ddr_odt,
rasn => ddr_ras, casn => ddr_cas, wen => ddr_we,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, resetn => ddr_reset_n,
dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn,
doload => led(2)
);
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
phy_mii_data <= 'H';
p0: phy
generic map (address => 7)
port map(phy_rst_n, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data,
phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en,
phy_tx_er, phy_mii_clk, phy_gtx_clk);
end generate;
sysace_mpirq <= '0';
sysace_d <= (others => 'Z');
iuerr : process
begin
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
end ;
|
gpl-2.0
|
338c17ae04658a1f49dc6881bd03e8b5
| 0.558148 | 3.054266 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/fmf/flash/s25fl064a.vhd
| 3 | 52,107 |
-------------------------------------------------------------------------------
-- File Name: s25fl064a.vhd
-------------------------------------------------------------------------------
-- Copyright (C) 2005-2007 Free Model Foundry; http://www.FreeModelFoundry.com
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 G.Gojanovic 05 May 11 Inital Release
-- V1.1 D.Randjelovic 06 Apr 11 MSB of latched address is ignored
-- V1.2 D.Randjelovic 06 May 04 Page Program Command used with the
-- single byte data corrected.
-- Release from Deep Power Down when
-- Electronic Signature is not read
-- fixed
-- V1.3 D.Stanojkovic 07 Jul 02 Correction to enable testing in NCSim
--
-------------------------------------------------------------------------------
-- PART DESCRIPTION:
--
-- Library: FLASH
-- Technology: Flash Memory
-- Part: S25FL064A
--
-- Description: 64 Megabit Serial Flash Memory with 50MHz SPI Bus Interface
--
-------------------------------------------------------------------------------
-- Comments :
-- When testing with NCSim default value for TimingModel in
-- generic list should be removed, otherwise backannotation of this value
-- will not be done properly
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Known Bugs:
--
-------------------------------------------------------------------------------
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
USE STD.textio.ALL;
USE IEEE.VITAL_timing.ALL;
USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF; USE FMF.gen_utils.ALL;
USE FMF.conversions.ALL;
-------------------------------------------------------------------------------
-- ENTITY DECLARATION
-------------------------------------------------------------------------------
ENTITY s25fl064a IS
GENERIC (
-- tipd delays: interconnect path delays
tipd_SCK : VitalDelayType01 := VitalZeroDelay01;
tipd_SI : VitalDelayType01 := VitalZeroDelay01;
tipd_CSNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_HOLDNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_WNeg : VitalDelayType01 := VitalZeroDelay01;
-- tpd delays
tpd_SCK_SO : VitalDelayType01Z := UnitDelay01Z;--tV
tpd_CSNeg_SO : VitalDelayType01Z := UnitDelay01Z;--tDIS
tpd_HOLDNeg_SO : VitalDelayType01Z := UnitDelay01Z;--tLZ,tHZ
--tsetup values
tsetup_SI_SCK : VitalDelayType := UnitDelay; --tsuDAT /
tsetup_CSNeg_SCK : VitalDelayType := UnitDelay; --tCSS /
tsetup_HOLDNeg_SCK : VitalDelayType := UnitDelay; --tHD /
tsetup_WNeg_CSNeg : VitalDelayType := UnitDelay; --tWPS \
--thold values
thold_SI_SCK : VitalDelayType := UnitDelay; --thdDAT /
thold_CSNeg_SCK : VitalDelayType := UnitDelay; --tCSH /
thold_HOLDNeg_SCK : VitalDelayType := UnitDelay; --tCD /
thold_WNeg_CSNeg : VitalDelayType := UnitDelay; --tWPH \
--tpw values: pulse width
tpw_SCK_posedge : VitalDelayType := UnitDelay; --tWH
tpw_SCK_negedge : VitalDelayType := UnitDelay; --tWL
tpw_CSNeg_posedge : VitalDelayType := UnitDelay; --tCS
-- tperiod min (calculated as 1/max freq)
tperiod_SCK_rd : VitalDelayType := UnitDelay; -- fSCK=33MHz
tperiod_SCK_fast_rd : VitalDelayType := UnitDelay; -- fSCK=50MHz
-- tdevice values: values for internal delays
-- Page Program Operation
tdevice_PP : VitalDelayType := 3 ms; --tPP
--Sector Erase Operation
tdevice_SE : VitalDelayType := 3 sec; --tSE
--Bulk Erase Operation
tdevice_BE : VitalDelayType := 384 sec; --tBE
--Write Status Register Operation
tdevice_WR : VitalDelayType := 60 ms; --tW
--Deep Power Down
tdevice_DP : VitalDelayType := 3 us; --tDP
--Release from Software Protect Mode
tdevice_RES : VitalDelayType := 30 us; --tRES
--VCC (min) to CS# Low
tdevice_PU : VitalDelayType := 10 ms;
-- generic control parameters
InstancePath : STRING := DefaultInstancePath;
TimingChecksOn : BOOLEAN := DefaultTimingChecks;
MsgOn : BOOLEAN := DefaultMsgOn;
XOn : BOOLEAN := DefaultXon;
-- memory file to be loaded
mem_file_name : STRING := "s25fl064a.mem";
UserPreload : BOOLEAN := FALSE; --TRUE;
LongTimming : BOOLEAN := TRUE;
-- For FMF SDF technology file usage
TimingModel : STRING := DefaultTimingModel
);
PORT (
SCK : IN std_ulogic := 'U'; --serial clock input
SI : IN std_ulogic := 'U'; --serial data input
CSNeg : IN std_ulogic := 'U'; -- chip select input
HOLDNeg : IN std_ulogic := 'U'; -- hold input
WNeg : IN std_ulogic := 'U'; -- write protect input
SO : OUT std_ulogic := 'U' --serial data output
);
ATTRIBUTE VITAL_LEVEL0 of s25fl064a : ENTITY IS TRUE;
END s25fl064a;
-------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
-------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of s25fl064a IS
ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral : ARCHITECTURE IS TRUE;
CONSTANT PartID : STRING := "s25fl064a";
CONSTANT MaxData : NATURAL := 16#FF#; --255;
CONSTANT SecSize : NATURAL := 16#FFFF#; --65535
CONSTANT SecNum : NATURAL := 127;
CONSTANT HiAddrBit : NATURAL := 22;
CONSTANT AddrRANGE : NATURAL := 16#7FFFFF#;
CONSTANT BYTE : NATURAL := 8;
--Electronic Signature
CONSTANT ES : NATURAL := 16#16#;
--Device ID
--Manufacturer Identification && Memory Type && Memory Capacity
CONSTANT DeviceID : NATURAL := 16#010216#;
-- interconnect path delay signals
SIGNAL SCK_ipd : std_ulogic := 'U';
SIGNAL SI_ipd : std_ulogic := 'U';
SIGNAL CSNeg_ipd : std_ulogic := 'U';
SIGNAL HOLDNeg_ipd : std_ulogic := 'U';
SIGNAL WNeg_ipd : std_ulogic := 'U';
--- internal delays
SIGNAL PP_in : std_ulogic := '0';
SIGNAL PP_out : std_ulogic := '0';
SIGNAL PU_in : std_ulogic := '0';
SIGNAL PU_out : std_ulogic := '0';
SIGNAL SE_in : std_ulogic := '0';
SIGNAL SE_out : std_ulogic := '0';
SIGNAL BE_in : std_ulogic := '0';
SIGNAL BE_out : std_ulogic := '0';
SIGNAL WR_in : std_ulogic := '0';
SIGNAL WR_out : std_ulogic := '0';
SIGNAL DP_in : std_ulogic := '0';
SIGNAL DP_out : std_ulogic := '0';
SIGNAL RES_in : std_ulogic := '0';
SIGNAL RES_out : std_ulogic := '0';
BEGIN
---------------------------------------------------------------------------
-- Internal Delays
---------------------------------------------------------------------------
-- Artificial VITAL primitives to incorporate internal delays
PP :VitalBuf(PP_out, PP_in, (tdevice_PP ,UnitDelay));
PU :VitalBuf(PU_out, PU_in, (tdevice_PU ,UnitDelay));
SE :VitalBuf(SE_out, SE_in, (tdevice_SE ,UnitDelay));
BE :VitalBuf(BE_out, BE_in, (tdevice_BE ,UnitDelay));
WR :VitalBuf(WR_out, WR_in, (tdevice_WR ,UnitDelay));
DP :VitalBuf(DP_out, DP_in, (tdevice_DP ,UnitDelay));
RES :VitalBuf(RES_out, RES_in, (tdevice_RES ,UnitDelay));
---------------------------------------------------------------------------
-- Wire Delays
---------------------------------------------------------------------------
WireDelay : BLOCK
BEGIN
w_1 : VitalWireDelay (SCK_ipd, SCK, tipd_SCK);
w_2 : VitalWireDelay (SI_ipd, SI, tipd_SI);
w_3 : VitalWireDelay (CSNeg_ipd, CSNeg, tipd_CSNeg);
w_4 : VitalWireDelay (HOLDNeg_ipd, HOLDNeg, tipd_HOLDNeg);
w_5 : VitalWireDelay (WNeg_ipd, WNeg, tipd_WNeg);
END BLOCK;
---------------------------------------------------------------------------
-- Main Behavior Block
---------------------------------------------------------------------------
Behavior: BLOCK
-- State Machine : State_Type
TYPE state_type IS (IDLE,
DP_DOWN,
WRITE_SR,
SECTOR_ER,
BULK_ER,
PAGE_PG
);
-- Instruction Type
TYPE instruction_type IS (NONE,
WREN,
WRDI,
WRSR,
RDSR,
READ,
RDID,
FAST_READ,
SE,
BE,
PP,
DP,
RES_READ_ES
);
TYPE WByteType IS ARRAY (0 TO 255) OF INTEGER RANGE -1 TO MaxData;
--Flash Memory Array
TYPE MemArray IS ARRAY (0 TO AddrRANGE) OF INTEGER RANGE -1 TO MaxData;
---------------------------------------------------------------------------
-- memory declaration
---------------------------------------------------------------------------
SHARED VARIABLE Mem : MemArray := (OTHERS => MaxData);
-- states
SIGNAL current_state : state_type;
SIGNAL next_state : state_type;
SIGNAL WByte : WByteType := (others => 0);
SIGNAL Instruct : instruction_type;
--zero delay signal
SIGNAL SO_zd : std_logic :='Z';
--HOLD delay on output data
SIGNAL SO_z : std_logic :='Z';
-- powerup
SIGNAL PoweredUp : std_logic := '0';
SHARED VARIABLE Status_reg : std_logic_vector(7 downto 0)
:= (others => '0');
SIGNAL Status_reg_in : std_logic_vector(7 downto 0)
:= (others => '0');
ALIAS WEL :std_logic IS Status_reg(1);
ALIAS WIP :std_logic IS Status_reg(0);
ALIAS BP0 :std_logic IS Status_reg(2);
ALIAS BP1 :std_logic IS Status_reg(3);
ALIAS BP2 :std_logic IS Status_reg(4);
ALIAS SRWD :std_logic IS Status_reg(7);
--Command Register
SIGNAL write : std_logic := '0';
SIGNAL read_out : std_logic := '0';
SIGNAL fast_rd : boolean := true;
SIGNAL rd : boolean := false;
SIGNAL change_addr : std_logic := '0';
--FSM control signals
SIGNAL PDONE : std_logic := '1'; -- Page Prog. Done
SIGNAL PSTART : std_logic := '0'; --Start Page Programming
SIGNAL WDONE : std_logic := '1'; -- Write. Done
SIGNAL WSTART : std_logic := '0'; --Start Write
SIGNAL ESTART : std_logic := '0'; --Start Erase
SIGNAL EDONE : std_logic := '1'; --Erase Done
SIGNAL SA : NATURAL RANGE 0 TO SecNum := 0;
SIGNAL Byte_number : NATURAL RANGE 0 TO 255 := 0;
SHARED VARIABLE Sec_Prot : std_logic_vector(SecNum downto 0) :=
(OTHERS => '0');
SIGNAL Address : NATURAL RANGE 0 TO AddrRANGE := 0;
-- timing check violation
SIGNAL Viol : X01 := '0';
PROCEDURE ADDRHILO_SEC(
VARIABLE AddrLOW : INOUT NATURAL RANGE 0 to ADDRRange;
VARIABLE AddrHIGH : INOUT NATURAL RANGE 0 to ADDRRange;
VARIABLE Addr : NATURAL) IS
VARIABLE sector : NATURAL RANGE 0 TO SecNum;
BEGIN
sector := Addr/16#10000#;
AddrLOW := sector*16#10000#;
AddrHIGH := sector*16#10000# + 16#0FFFF#;
END AddrHILO_SEC;
PROCEDURE ADDRHILO_PG(
VARIABLE AddrLOW : INOUT NATURAL RANGE 0 to ADDRRange;
VARIABLE AddrHIGH : INOUT NATURAL RANGE 0 to ADDRRange;
VARIABLE Addr : NATURAL) IS
VARIABLE page : NATURAL RANGE 0 TO 65535;
BEGIN
page := Addr/16#100#;
AddrLOW := Page*16#100#;
AddrHIGH := Page*16#100# + 16#FF#;
END AddrHILO_PG;
BEGIN
----------------------------------------------------------------------------
--Power Up time;
---------------------------------------------------------------------------
PoweredUp <= '1' AFTER tdevice_PU;
---------------------------------------------------------------------------
-- VITAL Timing Checks Procedures
---------------------------------------------------------------------------
VITALTimingCheck: PROCESS(SI_ipd, SCK_ipd, CSNeg_ipd, HOLDNeg_ipd,
WNeg_ipd)
-- Timing Check Variables
VARIABLE Tviol_SI_SCK : X01 := '0';
VARIABLE TD_SI_SCK : VitalTimingDataType;
VARIABLE Tviol_HOLD_SCK : X01 := '0';
VARIABLE TD_HOLD_SCK : VitalTimingDataType;
VARIABLE Tviol_CS_SCK : X01 := '0';
VARIABLE TD_CS_SCK : VitalTimingDataType;
VARIABLE Tviol_WS_CS : X01 := '0';
VARIABLE TD_WS_CS : VitalTimingDataType;
VARIABLE Tviol_WH_CS : X01 := '0';
VARIABLE TD_WH_CS : VitalTimingDataType;
VARIABLE Pviol_CS : X01 := '0';
VARIABLE PD_CS : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_SCK : X01 := '0';
VARIABLE PD_SCK : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_SCK_rd : X01 := '0';
VARIABLE PD_SCK_rd : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_SCK_fast_rd: X01 := '0';
VARIABLE PD_SCK_fast_rd : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Violation : X01 := '0';
BEGIN
---------------------------------------------------------------------------
-- Timing Check Section
---------------------------------------------------------------------------
IF (TimingChecksOn) THEN
-- Setup/Hold Check between SI and SCK
VitalSetupHoldCheck (
TestSignal => SI_ipd,
TestSignalName => "SI",
RefSignal => SCK_ipd,
RefSignalName => "SCK",
SetupHigh => tsetup_SI_SCK,
SetupLow => tsetup_SI_SCK,
HoldHigh => thold_SI_SCK,
HoldLow => thold_SI_SCK,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_SI_SCK,
Violation => Tviol_SI_SCK
);
-- Setup/Hold Check between HOLD# and SCK /
VitalSetupHoldCheck (
TestSignal => HOLDNeg_ipd,
TestSignalName => "HOLD#",
RefSignal => SCK_ipd,
RefSignalName => "SCK",
SetupLow => tsetup_HOLDNeg_SCK,
HoldLow => thold_HOLDNeg_SCK,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_HOLD_SCK,
Violation => Tviol_HOLD_SCK
);
-- Setup/Hold Check between CS# and SCK
VitalSetupHoldCheck (
TestSignal => CSNeg_ipd,
TestSignalName => "CS#",
RefSignal => SCK_ipd,
RefSignalName => "SCK",
SetupHigh => tsetup_CSNeg_SCK,
SetupLow => tsetup_CSNeg_SCK,
HoldHigh => thold_CSNeg_SCK,
HoldLow => thold_CSNeg_SCK,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_CS_SCK,
Violation => Tviol_CS_SCK
);
-- Setup Check between W# and CS# \
VitalSetupHoldCheck (
TestSignal => WNeg_ipd,
TestSignalName => "W#",
RefSignal => CSNeg_ipd,
RefSignalName => "CS#",
SetupHigh => tsetup_WNeg_CSNeg,
CheckEnabled => true,
RefTransition => '\',
HeaderMsg => InstancePath & PartID,
TimingData => TD_WS_CS,
Violation => Tviol_WS_CS
);
-- Hold Check between W# and CS# /
VitalSetupHoldCheck (
TestSignal => WNeg_ipd,
TestSignalName => "W#",
RefSignal => CSNeg_ipd,
RefSignalName => "CS#",
HoldHigh => thold_WNeg_CSNeg,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_WH_CS,
Violation => Tviol_WH_CS
);
-- Period Check CS# m
VitalPeriodPulseCheck (
TestSignal => CSNeg_ipd,
TestSignalName => "CS#",
PulseWidthHigh => tpw_CSNeg_posedge,
PeriodData => PD_CS,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_CS,
HeaderMsg => InstancePath & PartID,
CheckEnabled => true );
-- Period Check SCK for everything but READ
VitalPeriodPulseCheck (
TestSignal => SCK_ipd,
TestSignalName => "SCK",
PulseWidthLow => tpw_SCK_negedge,
PulseWidthHigh => tpw_SCK_posedge,
PeriodData => PD_SCK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_SCK,
HeaderMsg => InstancePath & PartID,
CheckEnabled => true );
-- Period Check SCK for READ
VitalPeriodPulseCheck (
TestSignal => SCK_ipd,
TestSignalName => "SCK",
Period => tperiod_SCK_rd,
PeriodData => PD_SCK_rd,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_SCK_rd,
HeaderMsg => InstancePath & PartID,
CheckEnabled => rd );
-- Period Check SCK for other than READ
VitalPeriodPulseCheck (
TestSignal => SCK_ipd,
TestSignalName => "SCK",
Period => tperiod_SCK_fast_rd,
PeriodData => PD_SCK_fast_rd,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_SCK_fast_rd,
HeaderMsg => InstancePath & PartID,
CheckEnabled => fast_rd );
Violation := Tviol_SI_SCK OR
Tviol_HOLD_SCK OR
Tviol_CS_SCK OR
Tviol_WS_CS OR
Tviol_WH_CS OR
Pviol_SCK OR
Pviol_SCK_rd OR
Pviol_SCK_fast_rd OR
Pviol_CS;
Viol <= Violation;
ASSERT Violation = '0'
REPORT InstancePath & partID & ": simulation may be" &
" inaccurate due to timing violations"
SEVERITY WARNING;
END IF;
END PROCESS VITALTimingCheck;
----------------------------------------------------------------------------
-- sequential process for FSM state transition
----------------------------------------------------------------------------
StateTransition : PROCESS(next_state, PoweredUp)
BEGIN
IF PoweredUp = '1' THEN
current_state <= next_state;
END IF;
END PROCESS StateTransition;
---------------------------------------------------------------------------
-- Write cycle decode
---------------------------------------------------------------------------
BusCycleDecode : PROCESS(SCK_ipd, CSNeg_ipd, HOLDNeg_ipd, SI_ipd, RES_in)
TYPE bus_cycle_type IS (STAND_BY,
CODE_BYTE,
ADDRESS_BYTES,
DUMMY_BYTES,
DATA_BYTES
);
VARIABLE bus_cycle_state : bus_cycle_type;
VARIABLE data_cnt : NATURAL := 0;
VARIABLE addr_cnt : NATURAL := 0;
VARIABLE code_cnt : NATURAL := 0;
VARIABLE dummy_cnt : NATURAL := 0;
VARIABLE bit_cnt : NATURAL := 0;
VARIABLE Data_in : std_logic_vector(2047 downto 0)
:= (others => '0');
VARIABLE code : std_logic_vector(7 downto 0);
VARIABLE code_in : std_logic_vector(7 downto 0);
VARIABLE Byte_slv : std_logic_vector(7 downto 0);
VARIABLE addr_bytes : std_logic_vector(HiAddrBit downto 0);
VARIABLE Address_in : std_logic_vector(23 downto 0);
BEGIN
CASE bus_cycle_state IS
WHEN STAND_BY =>
IF falling_edge(CSNeg_ipd) THEN
Instruct <= NONE;
write <= '1';
code_cnt := 0;
addr_cnt := 0;
data_cnt := 0;
dummy_cnt := 0;
bus_cycle_state := CODE_BYTE;
END IF;
WHEN CODE_BYTE =>
IF rising_edge(SCK_ipd) AND HOLDNeg_ipd = '1' THEN
Code_in(code_cnt) := SI_ipd;
code_cnt := code_cnt + 1;
IF code_cnt = BYTE THEN
--MSB first
FOR I IN 7 DOWNTO 0 LOOP
code(i) := code_in(7-i);
END LOOP;
CASE code IS
WHEN "00000110" =>
Instruct <= WREN;
bus_cycle_state := DATA_BYTES;
WHEN "00000100" =>
Instruct <= WRDI;
bus_cycle_state := DATA_BYTES;
WHEN "00000001" =>
Instruct <= WRSR;
bus_cycle_state := DATA_BYTES;
WHEN "00000101" =>
Instruct <= RDSR;
bus_cycle_state := DATA_BYTES;
WHEN "00000011" =>
Instruct <= READ;
bus_cycle_state := ADDRESS_BYTES;
WHEN "00001011" =>
Instruct <= FAST_READ;
bus_cycle_state := ADDRESS_BYTES;
WHEN "10011111" =>
Instruct <= RDID;
bus_cycle_state := DATA_BYTES;
WHEN "10101011" =>
Instruct <= RES_READ_ES;
bus_cycle_state := DUMMY_BYTES;
WHEN "11011000" =>
Instruct <= SE;
bus_cycle_state := ADDRESS_BYTES;
WHEN "11000111" =>
Instruct <= BE;
bus_cycle_state := DATA_BYTES;
WHEN "00000010" =>
Instruct <= PP;
bus_cycle_state := ADDRESS_BYTES;
WHEN "10111001" =>
Instruct <= DP;
bus_cycle_state := DATA_BYTES;
WHEN others =>
null;
END CASE;
END IF;
END IF;
WHEN ADDRESS_BYTES =>
IF rising_edge(SCK_ipd) AND HOLDNeg_ipd = '1' THEN
Address_in(addr_cnt) := SI_ipd;
addr_cnt := addr_cnt + 1;
IF addr_cnt = 3*BYTE THEN
FOR I IN 23 DOWNTO 23-HiAddrBit LOOP
addr_bytes(23-i) := Address_in(i);
END LOOP;
Address <= to_nat(addr_bytes);
change_addr <= '1','0' AFTER 1 ns;
IF Instruct = FAST_READ THEN
bus_cycle_state := DUMMY_BYTES;
ELSE
bus_cycle_state := DATA_BYTES;
END IF;
END IF;
END IF;
WHEN DUMMY_BYTES =>
IF rising_edge(SCK_ipd) AND HOLDNeg_ipd = '1' THEN
dummy_cnt := dummy_cnt + 1;
IF dummy_cnt = BYTE THEN
IF Instruct = FAST_READ THEN
bus_cycle_state := DATA_BYTES;
END IF;
ELSIF dummy_cnt = 3*BYTE THEN
bus_cycle_state := DATA_BYTES;
END IF;
END IF;
IF rising_edge(CSNeg_ipd) THEN
bus_cycle_state := STAND_BY;
IF HOLDNeg_ipd = '1' AND Instruct = RES_READ_ES THEN
write <= '0';
END IF;
END IF;
WHEN DATA_BYTES =>
IF falling_edge(SCK_ipd) AND CSNeg_ipd = '0'
AND HOLDNeg_ipd = '1' THEN
IF Instruct = READ OR Instruct = RES_READ_ES
OR Instruct = FAST_READ OR Instruct = RDSR
OR Instruct = RDID THEN
read_out <= '1', '0' AFTER 1 ns;
END IF;
END IF;
IF rising_edge(SCK_ipd) AND HOLDNeg_ipd = '1' THEN
IF data_cnt > 2047 THEN
--In case of PP, if more than 256 bytes are
--sent to the device
IF bit_cnt = 0 THEN
FOR I IN 0 TO (255*BYTE - 1) LOOP
Data_in(i) := Data_in(i+8);
END LOOP;
END IF;
Data_in(2040 + bit_cnt) := SI_ipd;
bit_cnt := bit_cnt + 1;
IF bit_cnt = 8 THEN
bit_cnt := 0;
END IF;
data_cnt := data_cnt + 1;
ELSE
Data_in(data_cnt) := SI_ipd;
data_cnt := data_cnt + 1;
bit_cnt := 0;
END IF;
END IF;
IF rising_edge(CSNeg_ipd) THEN
bus_cycle_state := STAND_BY;
IF HOLDNeg_ipd = '1' THEN
CASE Instruct IS
WHEN WREN | WRDI | DP | BE | SE =>
IF data_cnt = 0 THEN
write <= '0';
END IF;
WHEN RDID | RES_READ_ES =>
write <= '0';
WHEN WRSR =>
IF data_cnt = 8 THEN
write <= '0';
Status_reg_in <= Data_in(7 downto 0);
--MSB first
END IF;
WHEN PP =>
IF ((data_cnt mod 8) = 0 AND
data_cnt > 0) THEN
write <= '0';
FOR I IN 0 TO 255 LOOP
FOR J IN 7 DOWNTO 0 LOOP
Byte_slv(j) :=
Data_in((i*8) + (7-j));
END LOOP;
WByte(i) <= to_nat(Byte_slv);
END LOOP;
IF data_cnt > 256*BYTE THEN
Byte_number <= 255;
ELSE
Byte_number <= data_cnt/8-1;
END IF;
END IF;
WHEN others =>
null;
END CASE;
END IF;
END IF;
END CASE;
END PROCESS BusCycleDecode;
---------------------------------------------------------------------------
-- Timing control for the Page Program
---------------------------------------------------------------------------
ProgTime : PROCESS(PSTART)
VARIABLE pob : time;
BEGIN
IF LongTimming THEN
pob := tdevice_PP;
ELSE
pob := tdevice_PP / 100;
END IF;
IF rising_edge(PSTART) AND PDONE = '1' THEN
IF NOT Sec_Prot(SA) = '1' THEN
PDONE <= '0', '1' AFTER pob;
END IF;
END IF;
END PROCESS ProgTime;
---------------------------------------------------------------------------
-- Timing control for the Write Status Register
---------------------------------------------------------------------------
WriteTime : PROCESS(WSTART)
VARIABLE wob : time;
BEGIN
IF LongTimming THEN
wob := tdevice_WR;
ELSE
wob := tdevice_WR / 100;
END IF;
IF rising_edge(WSTART) AND WDONE = '1' THEN
WDONE <= '0', '1' AFTER wob;
END IF;
END PROCESS WriteTime;
---------------------------------------------------------------------------
-- Timing control for the Bulk Erase
---------------------------------------------------------------------------
ErsTime : PROCESS(ESTART)
VARIABLE seo : time;
VARIABLE beo : time;
VARIABLE duration : time;
BEGIN
IF LongTimming THEN
seo := tdevice_SE;
beo := tdevice_BE;
ELSE
seo := tdevice_SE / 100;
beo := tdevice_BE / 100;
END IF;
IF rising_edge(ESTART) AND EDONE = '1' THEN
IF Instruct = BE THEN
duration := beo;
ELSE --Instruct = SE
duration := seo;
END IF;
EDONE <= '0', '1' AFTER duration;
END IF;
END PROCESS ErsTime;
CheckCEOnPowerUP :PROCESS
BEGIN
IF CSNeg /= '1' THEN
REPORT InstancePath & partID &
": Device is selected during Power Up"
SEVERITY WARNING;
END IF;
WAIT;
END PROCESS;
---------------------------------------------------------------------------
-- Main Behavior Process
-- combinational process for next state generation
---------------------------------------------------------------------------
StateGen :PROCESS(write, CSNeg, WDONE, PDONE, EDONE)
VARIABLE sect : NATURAL RANGE 0 TO SecNum;
BEGIN
-----------------------------------------------------------------------
-- Functionality Section
-----------------------------------------------------------------------
CASE current_state IS
WHEN IDLE =>
IF falling_edge(write) THEN
IF Instruct = WRSR AND WEL = '1'
AND not(SRWD = '1' AND WNeg = '0') THEN
-- can not execute if HPM is entered
-- or if WEL bit is zero
next_state <= WRITE_SR;
ELSIF Instruct = PP AND WEL = '1' THEN
sect := Address / 16#10000#;
IF Sec_Prot(sect) = '0' THEN
next_state <= PAGE_PG;
END IF;
ELSIF Instruct = SE AND WEL = '1' THEN
sect := Address / 16#10000#;
IF Sec_Prot(sect) = '0' THEN
next_state <= SECTOR_ER;
END IF;
ELSIF Instruct = BE AND WEL = '1' AND
(BP0 = '0' AND BP1 = '0' AND BP2 = '0') THEN
next_state <= BULK_ER;
ELSIF Instruct = DP THEN
next_state <= DP_DOWN;
ELSE
next_state <= IDLE;
END IF;
END IF;
WHEN WRITE_SR =>
IF rising_edge(WDONE) THEN
next_state <= IDLE;
END IF;
WHEN PAGE_PG =>
IF rising_edge(PDONE) THEN
next_state <= IDLE;
END IF;
WHEN BULK_ER | SECTOR_ER =>
IF rising_edge(EDONE) THEN
next_state <= IDLE;
END IF;
WHEN DP_DOWN =>
IF falling_edge(write) AND Instruct = RES_READ_ES THEN
next_state <= IDLE;
END IF;
END CASE;
END PROCESS StateGen;
---------------------------------------------------------------------------
--FSM Output generation and general funcionality
---------------------------------------------------------------------------
Functional : PROCESS(write,read_out, WDONE, PDONE, EDONE, current_state,
CSNeg_ipd, HOLDNeg_ipd, Instruct, Address, WByte,
RES_out, change_addr, PoweredUp, WNeg_ipd)
TYPE WDataType IS ARRAY (0 TO 255) OF INTEGER RANGE -1 TO MaxData;
VARIABLE WData : WDataType:= (OTHERS => 0);
VARIABLE oe : boolean := FALSE;
VARIABLE AddrLo : NATURAL;
VARIABLE AddrHi : NATURAL;
VARIABLE Addr : NATURAL;
VARIABLE read_cnt : NATURAL;
VARIABLE read_addr : NATURAL RANGE 0 TO AddrRANGE;
VARIABLE data_out : std_logic_vector(7 downto 0);
VARIABLE ident_out : std_logic_vector(23 downto 0);
VARIABLE old_bit : std_logic_vector(7 downto 0);
VARIABLE new_bit : std_logic_vector(7 downto 0);
VARIABLE old_int : INTEGER RANGE -1 to MaxData;
VARIABLE new_int : INTEGER RANGE -1 to MaxData;
VARIABLE wr_cnt : NATURAL RANGE 0 TO 255;
VARIABLE sect : NATURAL RANGE 0 TO SecNum;
VARIABLE BP : std_logic_vector(2 downto 0) := "000";
BEGIN
-----------------------------------------------------------------------
-- Functionality Section
-----------------------------------------------------------------------
oe := rising_edge(read_out) AND PoweredUp = '1';
IF Instruct'EVENT THEN
read_cnt := 0;
fast_rd <= true;
rd <= false;
END IF;
IF rising_edge(change_addr) THEN
read_addr := Address;
END IF;
IF RES_out'EVENT AND RES_out = '1' THEN
RES_in <= '0';
END IF;
CASE current_state IS
WHEN IDLE =>
IF falling_edge(write) THEN
read_cnt := 0;
IF RES_in = '1' THEN
ASSERT false
REPORT InstancePath & partID & "Command results" &
" can be corrupted, a delay of tRES" &
" currently in progress."
SEVERITY WARNING;
END IF;
IF Instruct = WREN THEN
WEL := '1';
ELSIF Instruct = WRDI THEN
WEL := '0';
ELSIF Instruct = WRSR AND WEL = '1'
AND not(SRWD = '1' AND WNeg_ipd = '0') THEN
-- can not execute if HPM is entered
-- or if WEL bit is zero
WSTART <= '1', '0' AFTER 1 ns;
WIP := '1';
ELSIF Instruct = PP AND WEL = '1' THEN
sect := Address / 16#10000#;
IF Sec_Prot(sect) = '0' THEN
PSTART <= '1', '0' AFTER 1 ns;
WIP := '1';
SA <= sect;
Addr := Address;
wr_cnt := Byte_number;
FOR I IN wr_cnt DOWNTO 0 LOOP
IF Viol /= '0' AND Sec_Prot(SA) /= '0' THEN
WData(i) := -1;
ELSE
WData(i) := WByte(i);
END IF;
END LOOP;
END IF;
ELSIF Instruct = SE AND WEL = '1' THEN
sect := Address / 16#10000#;
IF Sec_Prot(sect) = '0' THEN
ESTART <= '1', '0' AFTER 1 ns;
WIP := '1';
Addr := Address;
END IF;
ELSIF Instruct = BE AND WEL = '1' AND
(BP0 = '0' AND BP1 = '0' AND BP2 = '0') THEN
ESTART <= '1', '0' AFTER 1 ns;
WIP := '1';
END IF;
ELSIF oe AND RES_in = '0' THEN
IF Instruct = RDSR THEN
--Read Status Register
SO_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
ELSIF Instruct = READ OR Instruct = FAST_READ THEN
--Read Memory array
IF Instruct = READ THEN
fast_rd <= false;
rd <= true;
END IF;
data_out := to_slv(Mem(read_addr),8);
SO_zd <= data_out(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
IF read_addr = AddrRANGE THEN
read_addr := 0;
ELSE
read_addr := read_addr + 1;
END IF;
END IF;
ELSIF Instruct = RDID THEN
--Read Device ID
--can be terminated by driving CSNeg high
--at any time
ident_out := to_slv(DeviceID,24);
SO_zd <= ident_out(23-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 24 THEN
read_cnt := 0;
END IF;
ELSIF Instruct = RES_READ_ES THEN
--Read Electronic Signature
data_out := to_slv(ES,8);
SO_zd <= data_out(7 - read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
ELSIF oe AND RES_in = '1' THEN
SO_zd <= 'X';
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
ASSERT false
REPORT InstancePath & partID & "Command results" &
" can be corrupted, a delay of tRES" &
" currently in progress."
SEVERITY WARNING;
END IF;
WHEN WRITE_SR =>
IF oe AND Instruct = RDSR THEN
SO_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
IF WDONE = '1' THEN
WIP := '0';
WEL := '0';
SRWD := Status_reg_in(0);--MSB first
BP2 := Status_reg_in(3);
BP1 := Status_reg_in(4);
BP0 := Status_reg_in(5);
BP := BP2 & BP1 & BP0;
CASE BP IS
WHEN "000" =>
Sec_Prot := (others => '0');
WHEN "001" =>
Sec_Prot(127) := '1';
Sec_Prot(126) := '1';
Sec_Prot(125 downto 0) := (others => '0');
WHEN "010" =>
Sec_Prot(127 downto 124):= (others => '1');
Sec_Prot(123 downto 0) := (others => '0');
WHEN "011" =>
Sec_Prot(127 downto 120):= to_slv(16#FF#,8);
Sec_Prot(119 downto 0) := (others => '0');
WHEN "100" =>
Sec_Prot(127 downto 112):= to_slv(16#FFFF#,16);
Sec_Prot(111 downto 0) := (others => '0');
WHEN "101" =>
Sec_Prot(127 downto 112):= to_slv(16#FFFF#,16);
Sec_Prot(111 downto 96):= to_slv(16#FFFF#,16);
Sec_Prot(95 downto 0) := (others => '0');
WHEN "110" =>
Sec_Prot(127 downto 112):= to_slv(16#FFFF#,16);
Sec_Prot(111 downto 96):= to_slv(16#FFFF#,16);
Sec_Prot(95 downto 80):= to_slv(16#FFFF#,16);
Sec_Prot(79 downto 64):= to_slv(16#FFFF#,16);
Sec_Prot(63 downto 0) := (others => '0');
WHEN others =>
Sec_Prot := (others => '1');
END CASE;
END IF;
WHEN PAGE_PG =>
IF oe AND Instruct = RDSR THEN
SO_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
ADDRHILO_PG(AddrLo, AddrHi, Addr);
IF (Addr + wr_cnt) > AddrHi THEN
wr_cnt := AddrHi - Addr;
END IF;
FOR I IN Addr TO Addr + wr_cnt LOOP
new_int := WData(i-Addr);
old_int := Mem(i);
IF new_int > -1 THEN
new_bit := to_slv(new_int,8);
IF old_int > -1 THEN
old_bit := to_slv(old_int,8);
FOR j IN 0 TO 7 LOOP
IF old_bit(j) = '0' THEN
new_bit(j) := '0';
END IF;
END LOOP;
new_int := to_nat(new_bit);
END IF;
WData(i-Addr) := new_int;
ELSE
WData(i-Addr) := -1;
END IF;
END LOOP;
FOR I IN Addr TO Addr + wr_cnt LOOP
Mem (i) := -1;
END LOOP;
IF PDONE = '1' THEN
WIP := '0';
WEL := '0';
FOR i IN Addr TO Addr + wr_cnt LOOP
Mem(i) := WData(i-Addr);
END LOOP;
END IF;
WHEN SECTOR_ER =>
IF oe AND Instruct = RDSR THEN
SO_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
ADDRHILO_SEC(AddrLo, AddrHi, Addr);
FOR i IN AddrLo TO AddrHi LOOP
Mem(i) := -1;
END LOOP;
IF EDONE = '1' THEN
WIP := '0';
WEL := '0';
FOR i IN AddrLo TO AddrHi LOOP
Mem(i) := MaxData;
END LOOP;
END IF;
WHEN BULK_ER =>
IF oe AND Instruct = RDSR THEN
SO_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
FOR i IN 0 TO AddrRANGE LOOP
Mem(i) := -1;
END LOOP;
IF EDONE = '1' THEN
WIP := '0';
WEL := '0';
FOR i IN 0 TO AddrRANGE LOOP
Mem(i) := MaxData;
END LOOP;
END IF;
WHEN DP_DOWN =>
IF falling_edge(write) THEN
IF Instruct = RES_READ_ES THEN
RES_in <= '1';
END IF;
ELSIF oe AND Instruct = RES_READ_ES THEN
--Read Electronic Signature
data_out := to_slv(ES,8);
SO_zd <= data_out(7 - read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
END CASE;
--Output Disable Control
IF (CSNeg_ipd = '1') THEN
SO_zd <= 'Z';
END IF;
END PROCESS Functional;
HOLD_FRAME_ON_SO_ZD : PROCESS( SO_zd, HOLDNeg_ipd)
BEGIN
IF (HOLDNeg_ipd = '0') THEN
SO_z <= 'Z';
ELSE
SO_z <= SO_zd;
END IF;
END PROCESS HOLD_FRAME_ON_SO_ZD;
---------------------------------------------------------------------------
---- File Read Section - Preload Control
---------------------------------------------------------------------------
MemPreload : PROCESS
-- text file input variables
FILE mem_file : text is mem_file_name;
VARIABLE ind : NATURAL := 0;
VARIABLE buf : line;
BEGIN
---------------------------------------------------------------------------
--s25fl016a memory preload file format -----------------------------------
---------------------------------------------------------------------------
-- / - comment
-- @aaaaaa - <aaaaaa> stands for address
-- dd - <dd> is byte to be written at Mem(aaaaaa++)
-- (aaaaaa is incremented at every load)
-- only first 1-7 columns are loaded. NO empty lines !!!!!!!!!!!!!!!!
---------------------------------------------------------------------------
-- memory preload
IF (mem_file_name /= "none" AND UserPreload) THEN
ind := 0;
Mem := (OTHERS => MaxData);
WHILE (not ENDFILE (mem_file)) LOOP
READLINE (mem_file, buf);
IF buf(1) = '/' THEN
NEXT;
ELSIF buf(1) = '@' THEN
ind := h(buf(2 to 7)); --address
IF ind > AddrRANGE THEN
ASSERT false
REPORT "Given preload address is out of" &
"memory address range"
SEVERITY warning;
END IF;
ELSE
IF ind <= AddrRANGE THEN
Mem(ind) := h(buf(1 to 2));
END IF;
IF ind < AddrRANGE THEN
ind := ind + 1;
END IF;
END IF;
END LOOP;
END IF;
WAIT;
END PROCESS MemPreload;
SO_OUT: PROCESS(SO_z)
VARIABLE SO_GlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01Z (
OutSignal => SO,
OutSignalName => "SO",
OutTemp => SO_z,
GlitchData => SO_GlitchData,
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => SCK_ipd'LAST_EVENT,
PathDelay => VitalExtendtofillDelay(tpd_SCK_SO),
PathCondition => SO_z /= 'Z'),
1 => (InputChangeTime => CSNeg_ipd'LAST_EVENT,
PathDelay => tpd_CSNeg_SO,
PathCondition => CSNeg_ipd = '1'),
2 => (InputChangeTime => HOLDNeg_ipd'LAST_EVENT,
PathDelay => tpd_HOLDNeg_SO,
PathCondition => TRUE)
)
);
END PROCESS SO_OUT;
END BLOCK behavior;
END vhdl_behavioral;
|
gpl-2.0
|
4adbf1f414ad80c4eaeae2a8f521b291
| 0.378145 | 5.280401 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica02_SumadorRestador4Bits/top_sumador.vhd
| 1 | 2,704 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use pack_sum.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
-- Entidad
entity eTopSum is
port(
carry: in std_logic;
entradas1: in std_logic_vector(3 downto 0);
entradas2: in std_logic_vector(3 downto 0);
salidas: out std_logic_vector(3 downto 0);
overflow: out std_logic);
attribute loc: string;
attribute loc of carry: signal is "p104";
attribute loc of entradas1: signal is "p125, p124, p123, p122";
attribute loc of entradas2: signal is "p121, p120, p117, p110";
attribute loc of salidas: signal is "p21, p22, p23, p24";
attribute loc of overflow: signal is "p12";
end;
-- Arquitectura
architecture aTopSum of eTopSum is
signal sb, cs, sa: std_logic_vector(3 downto 0);
signal sao: std_logic;
begin
U6: eXor port map(
entrada1_xor => carry,
entrada2_xor => entradas2(0),
salida_xor => sb(0));
U7: eXor port map(
entrada1_xor => carry,
entrada2_xor => entradas2(1),
salida_xor => sb(1));
U8: eXor port map(
entrada1_xor => carry,
entrada2_xor => entradas2(2),
salida_xor => sb(2));
U9: eXor port map(
entrada1_xor => carry,
entrada2_xor => entradas2(3),
salida_xor => sb(3));
U10: eTopSumCompleto port map(
acarreoI_tsc => carry,
entrada1_tsc => entradas1(0),
entrada2_tsc => sb(0),
acarreoO_tsc => cs(0),
resultado_tsc => sa(0));
U11: eTopSumCompleto port map(
acarreoI_tsc => cs(0),
entrada1_tsc => entradas1(1),
entrada2_tsc => sb(1),
acarreoO_tsc => cs(1),
resultado_tsc => sa(1));
U12: eTopSumCompleto port map(
acarreoI_tsc => cs(1),
entrada1_tsc => entradas1(2),
entrada2_tsc => sb(2),
acarreoO_tsc => cs(2),
resultado_tsc => sa(2));
U13: eTopSumCompleto port map(
acarreoI_tsc => cs(2),
entrada1_tsc => entradas1(3),
entrada2_tsc => sb(3),
acarreoO_tsc => cs(3),
resultado_tsc => sa(3));
U14: eAnd port map(
entrada1_and => sao,
entrada2_and => sa(0),
salida_and => salidas(0));
U15: eAnd port map(
entrada1_and => sao,
entrada2_and => sa(1),
salida_and => salidas(1));
U16: eAnd port map(
entrada1_and => sao,
entrada2_and => sa(2),
salida_and => salidas(2));
U17: eAnd port map(
entrada1_and => sao,
entrada2_and => sa(3),
salida_and => salidas(3));
U18: eXnor port map(
entrada1_xnor => cs(3),
entrada2_xnor => cs(2),
salida_xnor => sao);
U19: eXor port map(
entrada1_xor => cs(3),
entrada2_xor => cs(2),
salida_xor => overflow);
end aTopSum;
|
apache-2.0
|
e0425a6a0a72f410b5075ada6febd844
| 0.612796 | 2.879659 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/pci/grpci2/grpci2.vhd
| 1 | 268,624 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grpci2
-- File: grpci2.vhd
-- Author: Nils-Johan Wessman - Aeroflex Gaisler
-- Description: PCI master and target interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.dftlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
use work.pcilib2.all;
entity grpci2 is
generic (
memtech : integer := DEFMEMTECH;
tbmemtech : integer := DEFMEMTECH; -- For trace buffers
oepol : integer := 0;
hmindex : integer := 0;
hdmindex : integer := 0;
hsindex : integer := 0;
haddr : integer := 0;
hmask : integer := 0;
ioaddr : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
irq : integer := 0;
irqmode : integer range 0 to 3 := 0;
master : integer range 0 to 1 := 1;
target : integer range 0 to 1 := 1;
dma : integer range 0 to 1 := 1;
tracebuffer : integer range 0 to 16384 := 0;
confspace : integer range 0 to 1 := 1;
vendorid : integer := 16#0000#;
deviceid : integer := 16#0000#;
classcode : integer := 16#000000#;
revisionid : integer := 16#00#;
cap_pointer : integer := 16#40#;
ext_cap_pointer : integer := 16#00#;
iobase : integer := 16#FFF#;
extcfg : integer := 16#0000000#;
bar0 : integer range 0 to 31 := 28;
bar1 : integer range 0 to 31 := 0;
bar2 : integer range 0 to 31 := 0;
bar3 : integer range 0 to 31 := 0;
bar4 : integer range 0 to 31 := 0;
bar5 : integer range 0 to 31 := 0;
bar0_map : integer := 16#000000#;
bar1_map : integer := 16#000000#;
bar2_map : integer := 16#000000#;
bar3_map : integer := 16#000000#;
bar4_map : integer := 16#000000#;
bar5_map : integer := 16#000000#;
bartype : integer range 0 to 65535 := 16#0000#;
barminsize : integer range 5 to 31 := 12;
fifo_depth : integer range 3 to 7 := 3;
fifo_count : integer range 2 to 4 := 2;
conv_endian : integer range 0 to 1 := 1; -- 1: little (PCI) <~> big (AHB), 0: big (PCI) <=> big (AHB)
deviceirq : integer range 0 to 1 := 1;
deviceirqmask : integer range 0 to 15 := 16#0#;
hostirq : integer range 0 to 1 := 1;
hostirqmask : integer range 0 to 15 := 16#0#;
nsync : integer range 0 to 2 := 2; -- with nsync = 0, wrfst needed on syncram...
hostrst : integer range 0 to 2 := 0; -- 0: PCI reset is never driven, 1: PCI reset is driven from AHB reset if host, 2: PCI reset is always driven from AHB reset
bypass : integer range 0 to 1 := 1;
ft : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
debug : integer range 0 to 1 := 0;
tbapben : integer range 0 to 1 := 0;
tbpindex : integer := 0;
tbpaddr : integer := 0;
tbpmask : integer := 16#F00#;
netlist : integer range 0 to 1 := 0; -- Use PHY netlist
multifunc : integer range 0 to 1 := 0; -- Enables Multi-function support
multiint : integer range 0 to 1 := 0;
masters : integer := 16#FFFF#;
mf1_deviceid : integer := 16#0000#;
mf1_classcode : integer := 16#000000#;
mf1_revisionid : integer := 16#00#;
mf1_bar0 : integer range 0 to 31 := 0;
mf1_bar1 : integer range 0 to 31 := 0;
mf1_bar2 : integer range 0 to 31 := 0;
mf1_bar3 : integer range 0 to 31 := 0;
mf1_bar4 : integer range 0 to 31 := 0;
mf1_bar5 : integer range 0 to 31 := 0;
mf1_bartype : integer range 0 to 65535 := 16#0000#;
mf1_bar0_map : integer := 16#000000#;
mf1_bar1_map : integer := 16#000000#;
mf1_bar2_map : integer := 16#000000#;
mf1_bar3_map : integer := 16#000000#;
mf1_bar4_map : integer := 16#000000#;
mf1_bar5_map : integer := 16#000000#;
mf1_cap_pointer : integer := 16#40#;
mf1_ext_cap_pointer : integer := 16#00#;
mf1_extcfg : integer := 16#0000000#;
mf1_masters : integer := 16#0000#;
iotest : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
dirq : in std_logic_vector(3 downto 0);
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbdmi : in ahb_mst_in_type;
ahbdmo : out ahb_mst_out_type;
ptarst : out std_logic;
tbapbi : in apb_slv_in_type := apb_slv_in_none;
tbapbo : out apb_slv_out_type;
debugo : out std_logic_vector(debug*255 downto 0)
);
end;
architecture rtl of grpci2 is
-- PHY =>
signal phyi : grpci2_phy_in_type;
signal phyo : grpci2_phy_out_type;
signal sig_m_request, sig_m_mabort, sig_t_abort, sig_t_ready, sig_t_retry : std_logic;
signal sig_pr_conf_comm_serren, sig_pr_conf_comm_perren : std_logic;
signal sig_soft_rst : std_logic_vector(2 downto 0);
-- PHY <=
constant PT_DEPTH : integer := 5 + log2(tracebuffer/32);
constant HIOMASK : integer := 16#E00# - 16#200#*conv_integer(conv_std_logic(tracebuffer/=0));
constant MST_ACC_CNT : integer := fifo_count - 1;
constant RAM_LATENCY : integer := 1 + ram_raw_latency(memtech); -- Delay FIFO readout one extra write clock cycle for some technologies
type pci_bars_type is array (0 to 5) of std_logic_vector(31 downto 0);
constant pci_bars_none : pci_bars_type := (others => (others => '0'));
type pci_config_space_type is record
bar : pci_bars_type;
comm : pci_config_command_type;
stat : pci_config_status_type;
ltimer : std_logic_vector(7 downto 0);
iline : std_logic_vector(7 downto 0);
pta_map : pci_bars_type; -- PCI to AHB mapping for each PCI bar
bar_mask : pci_bars_type; -- PCI bar mask (bar size)
cfg_map : std_logic_vector(31 downto 0);-- Map extended PCI configuration space to AHB address
end record;
constant pci_config_space_none : pci_config_space_type := (pci_bars_none, pci_config_command_none, pci_config_status_none, (others => '0'), (others => '0'), pci_bars_none, pci_bars_none, (others => '0'));
type pci_config_space_multi_type is array (0 to multifunc) of pci_config_space_type;
type pci_fifo_out_type is record
data : std_logic_vector(31 downto 0);
err : std_logic_vector(3 downto 0);
end record;
constant pci_fifo_out_none : pci_fifo_out_type := ((others => '0'), (others => '0'));
type pci_fifo_in_type is record
en : std_logic; -- Read/write enable for fifo
addr : std_logic_vector((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0); -- Fifo address
data : std_logic_vector(31 downto 0); -- Fifo input data
end record;
constant pci_fifo_in_none : pci_fifo_in_type := ('0', zero32((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0), (others => '0'));
type pci_g_acc_trans_type is record
pending : std_logic; -- Access pending (valid)
addr : std_logic_vector(31 downto 0); -- Access start address
acctype : std_logic_vector(3 downto 0); -- Access type (conf_read/write, io_read/write, data_read/write)
accmode : std_logic_vector(2 downto 0); -- Access mode (use cancel, use length, burst)
size : std_logic_vector(2 downto 0); -- Access size
offset : std_logic_vector(1 downto 0); -- Access byte offset
index : integer range 0 to FIFO_COUNT-1;-- FIFO index for first data
length : std_logic_vector(15 downto 0); -- Access length
func : std_logic_vector(2 downto 0); -- The master belongs to this PCI function
--
cbe : std_logic_vector(3 downto 0); -- Byte enable (size and offset)
endianess : std_logic; -- PCI bus endianess
end record;
constant pci_g_acc_trans_none : pci_g_acc_trans_type := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), 0, (others => '0'), (others => '0'), (others => '0'), '0');
type pci_g_acc_status_trans_type is record
done : std_logic; -- Access done
status : std_logic_vector(3 downto 0); -- Access status
count : std_logic_vector(15 downto 0);-- Access transfer count
end record;
constant pci_g_acc_status_trans_none : pci_g_acc_status_trans_type := ('0', (others => '0'), (others => '0'));
type pci_g_acc_status_trans_multi_type is array (0 to 1) of pci_g_acc_status_trans_type;
constant pci_g_acc_status_trans_multi_none : pci_g_acc_status_trans_multi_type := (others => pci_g_acc_status_trans_none);
type pci_g_fifo_trans_type is record
pending : std_logic_vector(2 downto 0); -- FIFO pending (valid)
start : std_logic_vector(FIFO_DEPTH-1 downto 0);-- FIFO start address (first valid data)
stop : std_logic_vector(FIFO_DEPTH-1 downto 0);-- FIFO stop address (last valid data)
firstf : std_logic; -- First FIFO
lastf : std_logic; -- Last FIFO
status : std_logic_vector(3 downto 0); -- Error status
--
last_cbe : std_logic_vector(3 downto 0); -- Byte enable of last data
end record;
constant pci_g_fifo_trans_none : pci_g_fifo_trans_type := ((others => '0'), zero32(FIFO_DEPTH-1 downto 0), zero32(FIFO_DEPTH-1 downto 0), '0', '0', (others => '0'), (others => '0'));
type pci_g_acc_trans_multi_type is array (0 to 1) of pci_g_acc_trans_type;
constant pci_g_acc_trans_multi_none : pci_g_acc_trans_multi_type := (others => pci_g_acc_trans_none);
type pci_g_acc_trans_vector_type is array (0 to 3) of pci_g_acc_trans_type;
constant pci_g_acc_trans_vector_none : pci_g_acc_trans_vector_type := (others => pci_g_acc_trans_none);
type pci_g_acc_trans_vector_multi_type is array (0 to 1) of pci_g_acc_trans_vector_type;
constant pci_g_acc_trans_vector_multi_none : pci_g_acc_trans_vector_multi_type := (others => pci_g_acc_trans_vector_none);
type pci_g_fifo_trans_vector_type is array (0 to FIFO_COUNT-1) of pci_g_fifo_trans_type;
constant pci_g_fifo_trans_vector_none: pci_g_fifo_trans_vector_type := (others => pci_g_fifo_trans_none);
type pci_g_fifo_trans_vector_multi_type is array (0 to 1) of pci_g_fifo_trans_vector_type;
constant pci_g_fifo_trans_vector_multi_none : pci_g_fifo_trans_vector_multi_type := (others => pci_g_fifo_trans_vector_none);
subtype pci_g_fifo_ack_trans_vector_type is std_logic_vector(FIFO_COUNT-1 downto 0);
constant pci_g_fifo_ack_trans_vector_none : pci_g_fifo_ack_trans_vector_type := (others => '0');
type pci_g_fifo_ack_trans_vector_multi_type is array (0 to 1) of pci_g_fifo_ack_trans_vector_type;
constant pci_g_fifo_ack_trans_vector_multi_none : pci_g_fifo_ack_trans_vector_multi_type := (others => pci_g_fifo_ack_trans_vector_none);
type pci_master_acc_type is record
pending : std_logic; -- Access valid
addr : std_logic_vector(31 downto 0); -- Access start address
cmd : std_logic_vector(3 downto 0); -- Access type (conf_read/write, io_read/write, data_read/write)
cbe : std_logic_vector(3 downto 0); -- Byte enable (size and offset)
endianess : std_logic; -- PCI bus endianess
mode : std_logic_vector(2 downto 0); -- Mode[use length, burst]
length : std_logic_vector(15 downto 0); -- Access length
active : std_logic_vector(1 downto 0); -- [1]: access has data to transfer, [0]: access active
done : std_logic_vector(2 downto 0); -- [2]: access terminated by error, [1]:(PCI master write: all pending fifos acked), [0]: access done
status : std_logic_vector(2 downto 0); -- Error status
first : std_logic; -- First data in access
func : integer range 0 to multifunc; -- PCI function accessed
--
fifo_index : integer range 0 to FIFO_COUNT-1;-- FIFO index for first data
fifo_addr : std_logic_vector(FIFO_DEPTH-1 downto 0); -- Fifo address
fifo_wen : std_logic; -- FIFO write enable
fifo_ren : std_logic; -- FIFO read enable
end record;
constant pci_master_acc_none : pci_master_acc_type := ('0', (others => '0'), (others => '0'), (others => '0'), '0', (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', 0, 0, zero32(FIFO_DEPTH-1 downto 0), '0', '0');
type pci_master_acc_multi_type is array (0 to 1) of pci_master_acc_type;
constant pci_master_acc_multi_none : pci_master_acc_multi_type := (pci_master_acc_none, pci_master_acc_none);
constant acc_sel_ahb : integer := 0;
constant acc_sel_dma : integer := 1;
type ahb_master_acc_type is record
pending : std_logic; -- Access valid
addr : std_logic_vector(31 downto 0); -- Access start address
cbe : std_logic_vector(3 downto 0); -- Access byte enable (size and offset)
endianess : std_logic; -- PCI bus endianess
acctype : std_logic_vector(3 downto 0); --
mode : std_logic_vector(2 downto 0); -- Mode[use length, burst]
length : std_logic_vector(15 downto 0); -- Access length
burst : std_logic; -- Same as accmode(0);
--
fifo_index : integer range 0 to FIFO_COUNT-1;-- FIFO index for first data
fifo_addr : std_logic_vector((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0); -- Fifo address
fifo_wen : std_logic; -- FIFO write enable
fifo_ren : std_logic; -- FIFO read enable
fifo_wdata : std_logic_vector(31 downto 0);
end record;
constant ahb_master_acc_none : ahb_master_acc_type := ('0', (others => '0'), (others => '0'), '0', (others => '0'), (others => '0'),
(others => '0'), '0', 0, (others => '0'), '0', '0', (others => '0'));
type pci_fifo_type is record
index : integer range 0 to FIFO_COUNT-1;-- FIFO index
ctrl : pci_fifo_in_type; -- FIFO RAM control signal
end record;
constant pci_fifo_none : pci_fifo_type := (0, pci_fifo_in_none);
type pci_access_type is record
addr : std_logic_vector(31 downto 0); -- Access address
ready : std_logic; -- Data ready
pending : std_logic; -- Access saved and pending
read : std_logic; -- Target read / write access
burst : std_logic; -- Burst access
retry : std_logic; -- Access terminated with retry
acc_type: std_logic_vector(1 downto 0); -- Access type: 00: memory, 10: configuration space, 11: mapping registers, 01: ext conf space mapped to AHB
bar : std_logic_vector(5 downto 0); -- PCI bar accessed
func : integer range 0 to multifunc; -- PCI function accessed
match : std_logic; -- Access matching pending access
continue: std_logic; -- Burst may continue
newacc : std_logic; -- New access, discard old data
oldburst: std_logic; -- When "new access" store last burst
impcfgreg: std_logic; -- Indicates if the current Configuration Space register is implemented
end record;
constant pci_access_none : pci_access_type := ((others => '0'), '0', '0', '0', '0', '0', (others => '0'), (others => '0'), 0, '0', '0', '0', '0', '1');
type pci_access_vector_type is array (0 to 1) of pci_access_type;
constant pci_access_vector_none : pci_access_vector_type := (others => pci_access_none);
type pci_target_type is record
state : pci_target_state_type;
fstate : pci_target_fifo_state_type;
cfifo : pci_core_fifo_vector_type; -- Core FIFO
atp : pci_fifo_type; -- AMBA to PCI FIFO
pta : pci_fifo_type; -- PCI to AMBA FIFO
addr : std_logic_vector(31 downto 0);-- Used as FIFO address during write
cur_acc : pci_access_vector_type; -- Current PCI access
lcount : std_logic_vector(2 downto 0); -- Target latency counter 8 clocks (initial latency should 16 clocks)
preload : std_logic; -- Preload the internal FIFO
preload_count : std_logic_vector(1 downto 0); -- Counter used when preloading the internal FIFO
stop : std_logic;
stoped : std_logic;
hold : std_logic_vector(0 downto 0);
hold_fifo : std_logic;
hold_reset : std_logic;
hold_write : std_logic;
first : std_logic_vector(1 downto 0); -- Used to mark first fifo. bit[1]: first fifo in transfer, bit[0]: first word in fifo
conf_addr : std_logic_vector(3 downto 0);
first_word : std_logic; -- Indicate first word in access
diswithout : std_logic; -- Disconnect without data
addr_perr : std_logic; -- Address Parity Error detected
abort : std_logic; -- Target abort
retry : std_logic;
discard : std_logic;
accbuf : pci_g_acc_trans_vector_type; -- PCI target to AHB master access buffer
blen : std_logic_vector(15 downto 0);-- PCI target burst length boundary
blenmask : std_logic_vector(15 downto 0);-- PCI target burst length boundary mask
saverfifo : std_logic; -- Save prefetched FIFO until next PCI access in case of target termination (disconnect without data)
discardtimeren : std_logic; -- Enable/Disable discard timer
discardtimer : std_logic_vector(15 downto 0);-- Discard prefetched data after 2^15 PCI clock cycles
end record;
constant pci_target_none : pci_target_type := (
pt_idle, ptf_idle, pci_core_fifo_vector_none, pci_fifo_none, pci_fifo_none,
(others => '0'), pci_access_vector_none, (others => '0'), '0', (others => '0'), '0', '0',
(others => '0'), '0', '0', '0', (others => '0'), (others => '0'),
'0', '0', '0', '0', '0', '0', pci_g_acc_trans_vector_none, (others => '0'),
(others => '0'), '0', '0', (others => '0'));
type pci_master_type is record
state : pci_master_state_type;
fstate : pci_master_fifo_state_type;
cfifo : pci_core_fifo_vector_type; -- Core FIFO
abort : std_logic_vector(1 downto 0); -- Master/Target abort [0]: master or target abort; [1]: 1 = target abort, 0 = master abort
ltimer : std_logic_vector(7 downto 0); -- PCI master latency timer
framedel : std_logic; -- Delayed frame
devsel_tout : std_logic_vector(2 downto 0); -- Devsel time out conter;
devsel_asserted : std_logic; -- Devsel asserted;
addr : std_logic_vector(31 downto 0);-- PCI state address
cbe_data : std_logic_vector(3 downto 0);
cbe_cmd : std_logic_vector(3 downto 0);
hold : std_logic_vector(1 downto 0); -- Hold transfer due to no available fifo
hold_fifo : std_logic; -- Hold FIFO due to no available fifo
done_fifo : std_logic; -- No more FIFO Available
done_trans : std_logic; -- No more data in FIFO (transfer done)
term : std_logic_vector(1 downto 0); -- Terminate transfer
done : std_logic; -- Transfer done
first : std_logic_vector(1 downto 0); -- First word in current access
last : std_logic_vector(1 downto 0); -- Last word in transfer
preload : std_logic;
preload_count : std_logic_vector(1 downto 0);
afull : std_logic; -- FIFO almost full on read
afullcnt : std_logic_vector(1 downto 0); -- Counter for the three last word in FIFO on read
burst : std_logic; -- Read burst access => signle accecc or preload
perren : std_logic_vector(1 downto 0); -- bit[0]: Drive output enable for Parity error, bit[1] delayed bit[0]
detectperr : std_logic_vector(1 downto 0); -- bit[2] = 1: Detect Parity error on write
twist : std_logic; -- On for PCI configuration space access, otherwise = pr.pta_trans.ca_twist
first_word : std_logic; -- Indicate first word in access
waitonstop : std_logic;
acc : pci_master_acc_multi_type; -- DMA/AHB slave => PCI master accesses
acc_sel : integer range 0 to 1; -- Active access, 0 = AHB slave; 1 = DMA
acc_cnt : integer range 0 to MST_ACC_CNT; -- Access transfer count (FIFO), for switching DMA/AHB-slave
acc_switch : std_logic; -- Access switching DMA/AHB-slave
fifo_addr : std_logic_vector((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0); -- Fifo address
fifo_wdata : std_logic_vector(31 downto 0);
fifo_switch : std_logic;
end record;
constant pci_master_none : pci_master_type := (
pm_idle, pmf_idle, pci_core_fifo_vector_none, (others => '0'), (others => '0'), '0',
(others => '0'), '0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0',
'0', '0', (others => '0'), '0', (others => '0'), (others => '0'), '0', (others => '0'), '0',
(others => '0'), '0', (others => '0'), (others => '0'), '0', '0', '0', pci_master_acc_multi_none,
0, 0, '0', zero32((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0), (others => '0'), '0');
type pci_trace_to_apb_trans_type is record
enable : std_logic;
armed : std_logic;
wrap : std_logic;
taddr : std_logic_vector(PT_DEPTH-1 downto 0);
start_ack : std_logic;
stop_ack : std_logic;
--
dbg_ad : std_logic_vector(31 downto 0);
dbg_sig : std_logic_vector(16 downto 0);
dbg_cur_ad : std_logic_vector(31 downto 0);
dbg_cur_acc : std_logic_vector(8 downto 0);
end record;
constant pci_trace_to_apb_trans_none : pci_trace_to_apb_trans_type := ('0', '0', '0', zero32(PT_DEPTH-1 downto 0), '0', '0',
(others => '0'), (others => '0'), (others => '0'), (others => '0'));
type apb_to_pci_trace_trans_type is record
start : std_logic;
stop : std_logic;
mode : std_logic_vector(3 downto 0);
count : std_logic_vector(PT_DEPTH-1 downto 0);
tcount : std_logic_vector(7 downto 0);
ad : std_logic_vector(31 downto 0);
admask : std_logic_vector(31 downto 0);
sig : std_logic_vector(16 downto 0);
sigmask : std_logic_vector(16 downto 0);
end record;
constant apb_to_pci_trace_trans_none : apb_to_pci_trace_trans_type := ('0', '0', (others => '0'), zero32(PT_DEPTH-1 downto 0),
(others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
type pci_trace_type is record
addr : std_logic_vector(PT_DEPTH-1 downto 0);
count : std_logic_vector(PT_DEPTH-1 downto 0);
tcount : std_logic_vector(7 downto 0);
end record;
constant pci_trace_none : pci_trace_type := (zero32(PT_DEPTH-1 downto 0), zero32(PT_DEPTH-1 downto 0), (others => '0'));
type pci_msd_acc_cancel_acc_multi_type is array (0 to 1) of std_logic_vector(2 downto 0);
type pci_to_ahb_trans_type is record
-- PCI target <=> AHB master
tm_acc : pci_g_acc_trans_type; -- AHB master access (read/write) [PCI target]
tm_acc_cancel : std_logic; -- Cancel access [PCI target]
tm_acc_done_ack : std_logic; -- Ack access done [PCI target]
tm_fifo : pci_g_fifo_trans_vector_type; -- PCI target => AHB master FIFO
tm_fifo_ack : pci_g_fifo_ack_trans_vector_type; -- AHB master => PCI target FIFO ack
-- PCI master <=> AHB slave / DMA
msd_acc_ack : std_logic_vector(0 to 1); -- PCI master access ack [AHB/DMA]
--msd_acc_cancel_ack : std_logic_vector(0 to 1); -- Cancel access ack [AHB/DMA]
msd_acc_cancel_ack : pci_msd_acc_cancel_acc_multi_type; -- Cancel access ack [AHB/DMA]
msd_acc_done : pci_g_acc_status_trans_multi_type; -- Access status [AHB/DMA]
msd_fifo : pci_g_fifo_trans_vector_multi_type; -- PCI master => AHB/DMA slave FIFO
msd_fifo_ack : pci_g_fifo_ack_trans_vector_multi_type; -- AHB/DMA slave => PCI master FIFO ack
-- PCI config space <=> AHB
ca_host : std_logic;
ca_pcimsten : std_logic_vector(0 to multifunc);
ca_twist : std_logic; -- 1: byte twisting litle (PCI) <~> big (AHB), 0: big (PCI) <=> big (AHB)
-- PCI system
pa_serr : std_logic;
pa_discardtout: std_logic;
rst_ack : std_logic_vector(2 downto 0);
end record;
type ahb_to_pci_trans_type is record
-- PCI target <=> AHB master
tm_acc_ack : std_logic; -- AHB master access ack [PCI target]
tm_acc_cancel_ack : std_logic_vector(2 downto 0); -- Cancel access ack [PCI target]
tm_acc_done : pci_g_acc_status_trans_type; -- Access status [PCI target]
tm_fifo : pci_g_fifo_trans_vector_type; -- AHB master => PCI target FIFO
tm_fifo_ack : pci_g_fifo_ack_trans_vector_type; -- PCI target => AHB master FIFO ack
-- PCI master <=> AHB slave / DMA
msd_acc : pci_g_acc_trans_multi_type; -- PCI master access (read/write) [AHB/DMA]
msd_acc_cancel : std_logic_vector(1 downto 0); -- Cancel access [AHB/DMA]
msd_acc_done_ack : std_logic_vector(1 downto 0); -- Ack access done [AHB/DMA]
msd_fifo : pci_g_fifo_trans_vector_multi_type; -- AHB/DMA slave => PCI master FIFO
msd_fifo_ack : pci_g_fifo_ack_trans_vector_multi_type; -- PCI master => AHB/DMA slave FIFO ack
-- PCI system
pa_serr_rst : std_logic;
pa_discardtout_rst: std_logic;
rst : std_logic_vector(2 downto 0);
mstswdis : std_logic;
end record;
type pci_sync_type is array (1 to 2) of ahb_to_pci_trans_type;
type ahb_sync_type is array (1 to 2) of pci_to_ahb_trans_type;
type pci_trace_sync_type is array (1 to 2) of apb_to_pci_trace_trans_type;
type apb_sync_type is array (1 to 2) of pci_trace_to_apb_trans_type;
type ahb_to_pci_map_type is array (0 to 15) of std_logic_vector(31 downto 0);
constant ahb_to_pci_map_none : ahb_to_pci_map_type := (others => (others => '0'));
-- Calculate AADDR_WIDTH for HMASK
function calc_aaddr_width(di : in integer) return integer is
variable bits : integer;
begin
if di = 16#800# then bits := 31;
elsif di = 16#c00# then bits := 30;
elsif di = 16#e00# then bits := 29;
elsif di = 16#f00# then bits := 28;
elsif di = 16#f80# then bits := 27;
elsif di = 16#fc0# then bits := 26;
elsif di = 16#fe0# then bits := 25;
elsif di = 16#ff0# then bits := 24;
elsif di = 16#ff8# then bits := 23;
elsif di = 16#ffc# then bits := 22;
elsif di = 16#ffe# then bits := 21;
elsif di = 16#fff# then bits := 20;
else bits := 4; end if;
return bits;
end function;
constant AADDR_WIDTH : integer := calc_aaddr_width(hmask);
type pci_reg_type is record
conf : pci_config_space_multi_type;-- Configuration Space
po : pci_reg_out_type; -- PCI output signals
m : pci_master_type; -- PCI Master
t : pci_target_type; -- PCI Target
pta_trans : pci_to_ahb_trans_type;-- Signals between PCI clock domain and AHB clock domain (need synchronisation)
sync : pci_sync_type;
pt : pci_trace_type;
ptta_trans: pci_trace_to_apb_trans_type;
pt_sync : pci_trace_sync_type;
pciinten : std_logic_vector(3 downto 0); -- Drives output enable for INTA..D
pci66 : std_logic_vector(1 downto 0);
debug : std_logic_vector(31 downto 0);
end record;
subtype AHB_FIFO_BITS is natural range FIFO_DEPTH + 1 downto 2;
type amba_master_state_type is (am_idle, am_read, am_write, am_error);
type amba_master_type is record
state : amba_master_state_type;
first : std_logic_vector(2 downto 0); -- First data in access (mark starting fifo)
done : std_logic_vector(2 downto 0);
stop : std_logic;
dmai0 : dma_ahb_in_type;
dma_hold : std_logic;
active : std_logic;
retry : std_logic;
retry_blen: std_logic_vector(15 downto 0);
retry_size: std_logic_vector(1 downto 0);
retry_offset: std_logic_vector(1 downto 0);
acc : ahb_master_acc_type; -- PCI target => AHB master accesses
hold : std_logic_vector(2 downto 0);
last : std_logic_vector(2 downto 0);
faddr : std_logic_vector(AHB_FIFO_BITS);
blen : std_logic_vector(15 downto 0);
end record;
constant amba_master_none : amba_master_type := (
am_idle, (others => '0'), (others => '0'), '0', dma_ahb_in_none, '0', '0', '0', (others => '0'), (others => '0'),
(others => '0'), ahb_master_acc_none, (others => '0'), (others => '0'), (others => '0'), (others => '0'));
type amba_slave_state_type is (as_idle, as_checkpcimst, as_read, as_write, as_pcitrace);
type amba_slave_type is record
state : amba_slave_state_type;
atp : pci_fifo_type;
pta : pci_fifo_type;
hready : std_logic;
hwrite : std_logic;
hsel : std_logic;
hmbsel : std_logic_vector(0 to 2);
hresp : std_logic_vector(1 downto 0);
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
hmaster : std_logic_vector(3 downto 0);
hburst : std_logic;
haddr : std_logic_vector(31 downto 0);
retry : std_logic;
first : std_logic; -- First access in transfer
firstf : std_logic; -- First fifo
pending : std_logic_vector(1 downto 0);
addr : std_logic_vector(31 downto 0);
offset : std_logic_vector(1 downto 0);
master : std_logic_vector(3 downto 0);
write : std_logic;
oneword : std_logic;
burst : std_logic;
config : std_logic;
io : std_logic;
size : std_logic_vector(2 downto 0);
start : std_logic;
hrdata : std_logic_vector(31 downto 0);
continue : std_logic;
discard : std_logic;
atp_map : ahb_to_pci_map_type;
io_map : std_logic_vector(31 downto 16);
cfg_bus : std_logic_vector(23 downto 16);
cfg_status: std_logic_vector(1 downto 0);
io_cfg_burst : std_logic_vector(1 downto 0); -- Alow burst on PCI IO / CONF
erren : std_logic; -- Enables AHB error response for Master/Target abort
parerren : std_logic; -- Enables AHB error response for PAR error
accbuf : pci_g_acc_trans_vector_type; -- AHB slave to PCI master access buffer
blen : std_logic_vector(7 downto 0); -- AHB slave prefetch burst length
blenmask : std_logic_vector(15 downto 0); -- AHB slave prefetch length AHB master mask
done_fifo : std_logic_vector(1 downto 0);
tb_ren : std_logic; -- PCI trace buffer read enable
fakehost : std_logic; -- Fake device in system slot (HOST)
stoppciacc: std_logic;
end record;
constant amba_slave_none : amba_slave_type := (
as_idle, pci_fifo_none, pci_fifo_none, '1', '0', '0', (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), '0', (others => '0'), '0', '0', '0',
(others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', '0', '0',
(others => '0'), '0', (others => '0'), '0', '0', ahb_to_pci_map_none, (others => '0'),
(others => '0'), (others => '0'), (others => '0'), '0', '0', pci_g_acc_trans_vector_none,
(others => '0'), (others => '0'), (others => '0'), '0', '0', '0');
type irq_reg_type is record
device_mask : std_logic_vector(3 downto 0);
device_force : std_logic;
host_mask : std_logic_vector(3 downto 0);
host_status : std_logic_vector(3 downto 0);
host_pirq_vl : std_logic_vector(3 downto 0);
host_pirq_l : std_logic;
access_en : std_logic; -- Enables IRQ for Master/Target abort and PAR error
access_status: std_logic_vector(2 downto 0);
access_pirq : std_logic;
access_pirq_l: std_logic;
system_en : std_logic; -- Enables IRQ for System error
system_status: std_logic_vector(1 downto 0);
system_pirq : std_logic;
system_pirq_l: std_logic;
dma_pirq_l : std_logic;
irqen : std_logic;
end record;
constant irq_reg_none : irq_reg_type := (
(others => '0'), '0', (others => '0'), (others => '0'), (others => '0'),
'0', '0', (others => '0'), '0', '0', '0', (others => '0'), '0', '0', '0', '0');
type dma_state_type is (dma_idle, dma_read_desc, dma_next_channel, dma_write_status, dma_read, dma_write, dma_error);
type dma_desc_type is record
en : std_logic;
irqen : std_logic;
write : std_logic;
tw : std_logic;
desctype: std_logic_vector(1 downto 0);
cio : std_logic_vector(1 downto 0);
len : std_logic_vector(15 downto 0);
ch : std_logic_vector(31 downto 0);
nextch : std_logic_vector(31 downto 0);
addr : std_logic_vector(31 downto 0);
nextdesc: std_logic_vector(31 downto 0);
cnt : std_logic_vector(15 downto 0);
emptych : std_logic;
chcnt : std_logic_vector(2 downto 0);
paddr : std_logic_vector(31 downto 0);
aaddr : std_logic_vector(31 downto 0);
acctype : std_logic_vector(3 downto 0);
chid : std_logic_vector(2 downto 0);
end record;
constant dma_desc_none : dma_desc_type := (
'0', '0', '0', '0', (others => '0'), (others => '0'), (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
type dma_reg_type is record
state : dma_state_type;
dmai1 : dma_ahb_in_type;
desc : dma_desc_type;
dtp : pci_fifo_type;
ptd : pci_fifo_type;
rcnt : std_logic_vector(1 downto 0);
en : std_logic;
err : std_logic_vector(2 downto 0);
errlen : std_logic_vector(15 downto 0);
numch : std_logic_vector(2 downto 0);
dma_hold : std_logic_vector(2 downto 0);
dma_last : std_logic_vector(2 downto 0);
newfifo : std_logic;
active : std_logic;
done : std_logic_vector(1 downto 0);
faddr : std_logic_vector(AHB_FIFO_BITS);
first : std_logic_vector(2 downto 0);
retry : std_logic;
retry_len : std_logic_vector(15 downto 0);
addr : std_logic_vector(31 downto 0);
irq : std_logic;
irqen : std_logic;
irqstatus : std_logic_vector(1 downto 0);
len : std_logic_vector(15 downto 0);
errstatus : std_logic_vector(4 downto 0); -- DMA error status
irqch : std_logic_vector(7 downto 0); -- DMA Channel irq status
running : std_logic; -- DMA is running
end record;
constant dma_reg_none : dma_reg_type := (
dma_idle, dma_ahb_in_none, dma_desc_none, pci_fifo_none, pci_fifo_none,
(others => '0'), '0', (others => '0'), (others => '0'), (others => '0'),
(others => '0'), (others => '0'), '0', '0', (others => '0'), zero32(AHB_FIFO_BITS),
(others => '0'), '0', (others => '0'), (others => '0'), '0', '0', (others => '0'),
(others => '0'), (others => '0'), (others => '0'), '0');
type amba_reg_type is record
m : amba_master_type;
atp_trans : ahb_to_pci_trans_type;
sync : ahb_sync_type;
s : amba_slave_type;
irq : irq_reg_type;
dma : dma_reg_type;
atpt_trans: apb_to_pci_trace_trans_type;
apb_sync : apb_sync_type;
apb_pt_stat : std_logic_vector(31 downto 0);
apb_pr_conf_0_pta_map : pci_bars_type; -- PCI to AHB mapping for each PCI bar (read only)
debug : std_logic_vector(31 downto 0);
debug_pr : std_logic_vector(31 downto 0);
debuga : std_logic_vector(31 downto 0);
end record;
constant REVISION : amba_version_type := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GRPCI2, 0, REVISION, irq),
1 => apb_iobar(paddr, pmask));
-- APB DEBUG
constant tbpconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GRPCI2_TB, 0, REVISION, 0),
1 => apb_iobar(tbpaddr, tbpmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GRPCI2, 0, REVISION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
5 => ahb_iobar (ioaddr, HIOMASK),
others => zero32);
constant oeon : std_logic := conv_std_logic_vector(oepol,1)(0);
constant oeoff : std_logic := not conv_std_logic_vector(oepol,1)(0);
constant ones32 : std_logic_vector(31 downto 0) := (others => '1');
signal pr, prin : pci_reg_type;
signal pi, piin : pci_in_type; -- Registered PCI signals.
signal pcirstout : std_logic; -- PCI reset
signal pciasyncrst, pciasyncrst_comb : std_logic; -- PCI asynchronous reset
signal pcirst : std_logic_vector(2 downto 0); -- PCI reset
signal pciinten,pciinten_pad : std_logic_vector(3 downto 0);
signal pcisig : std_logic_vector(16 downto 0);
signal po, poin, po_keep : pci_reg_out_type; -- PCI output signals (to drive pads)
signal poin_keep : std_logic_vector(90 downto 0);
signal raden, rinaden, rinaden_tmp : std_logic_vector(31 downto 0);
signal pr_pta_trans_gated : pci_to_ahb_trans_type; -- PCI Target => AHB Master pending gated with pcirst
signal tm_fifoo_atp : pci_fifo_out_type; -- FIFO output data
signal ms_fifoo_atp : pci_fifo_out_type; -- FIFO output data
signal tm_fifoo_pta : pci_fifo_out_type;
signal ms_fifoo_pta : pci_fifo_out_type;
signal md_fifoo_dtp : pci_fifo_out_type; -- DMA FIFO output data
signal md_fifoo_ptd : pci_fifo_out_type;
signal pt_fifoo_ad : pci_fifo_out_type; -- PCI trace output data
signal pt_fifoo_sig : pci_fifo_out_type;
-- Scan test support
signal scanen : std_logic;
signal testin : std_logic_vector(TESTIN_WIDTH-1 downto 0);
signal scan_prin_t_atp_ctrl_en : std_logic;
signal scan_ar_m_acc_fifo_wen : std_logic;
signal scan_arin_m_acc_fifo_ren : std_logic;
signal scan_pr_t_pta_ctrl_en : std_logic;
signal scan_prin_m_acc_acc_sel_ahb_fifo_ren : std_logic;
signal scan_ar_s_atp_ctrl_en : std_logic;
signal scan_arin_s_pta_ctrl_en : std_logic;
signal scan_pr_m_acc_acc_sel_ahb_fifo_wen : std_logic;
signal scan_prin_m_acc_acc_sel_dma_fifo_ren : std_logic;
signal scan_ar_dma_dtp_ctrl_en : std_logic;
signal scan_arin_dma_ptd_ctrl_en : std_logic;
signal scan_pr_m_acc_acc_sel_dma_fifo_wen : std_logic;
signal scan_tb_ren : std_logic;
signal scan_pr_ptta_trans_enable : std_logic;
signal tb_addr : std_logic_vector(31 downto 0); -- Trace Buffer address
signal tb_ren : std_logic; -- Trace Buffer read enable
signal ar, arin : amba_reg_type;
signal dmao0, dmao1 : dma_ahb_out_type;
signal disabled_dmai : dma_ahb_in_type;
signal ahbmo_con : ahb_mst_out_type; -- Connect AHB-master to ahbmo
signal lpcim_rst, lpcit_rst, lpci_rst: std_ulogic;
signal lahbm_rst, lahbs_rst, lahb_rst: std_ulogic;
signal iotmdin: std_logic_vector(45 downto 0);
signal iotmdout: std_logic_vector(44 downto 0);
signal iotmact, iotmoe: std_ulogic;
attribute sync_set_reset of lpcim_rst : signal is "true";
attribute sync_set_reset of lpcit_rst : signal is "true";
attribute sync_set_reset of lpci_rst : signal is "true";
attribute sync_set_reset of pcirst : signal is "true";
--attribute sync_set_reset of rst : signal is "true";
attribute sync_set_reset of lahbm_rst : signal is "true";
attribute sync_set_reset of lahbs_rst : signal is "true";
attribute sync_set_reset of lahb_rst : signal is "true";
type bar_size_type is array (0 to 5) of integer range 0 to 31;
constant func0_bar_size : bar_size_type := (bar0, bar1, bar2, bar3, bar4, bar5);
constant func1_bar_size : bar_size_type := (mf1_bar0, mf1_bar1, mf1_bar2, mf1_bar3, mf1_bar4, mf1_bar5);
constant none_bar_size : bar_size_type := (0, 0, 0, 0, 0, 0);
type bar_size_vector_type is array (0 to 7) of bar_size_type;
constant bar_size : bar_size_vector_type := (func0_bar_size, func1_bar_size, none_bar_size, none_bar_size,
none_bar_size, none_bar_size, none_bar_size, none_bar_size);
constant func0_bar_type : std_logic_vector(15 downto 0) := conv_std_logic_vector(bartype,16);
constant func1_bar_type : std_logic_vector(15 downto 0) := conv_std_logic_vector(mf1_bartype,16);
constant func0_bar_prefetch : std_logic_vector(5 downto 0) := func0_bar_type(5 downto 0);
constant func1_bar_prefetch : std_logic_vector(5 downto 0) := func1_bar_type(5 downto 0);
type bar_prefetch_vector_type is array (0 to 7) of std_logic_vector(5 downto 0);
constant bar_prefetch : bar_prefetch_vector_type := (func0_bar_prefetch, func1_bar_prefetch, (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'));
constant func0_bar_io : std_logic_vector(5 downto 0) := func0_bar_type(13 downto 8);
constant func1_bar_io : std_logic_vector(5 downto 0) := func1_bar_type(13 downto 8);
constant bar_io : bar_prefetch_vector_type := (func0_bar_io, func1_bar_io, (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'));
type conf_int_vector_type is array (0 to 7) of integer;
constant deviceid_vector : conf_int_vector_type := (deviceid, mf1_deviceid, 0, 0, 0, 0, 0, 0);
constant classcode_vector : conf_int_vector_type := (classcode, mf1_classcode, 0, 0, 0, 0, 0, 0);
constant revisionid_vector : conf_int_vector_type := (revisionid, mf1_revisionid, 0, 0, 0, 0, 0, 0);
constant cap_pointer_vector : conf_int_vector_type := (cap_pointer, mf1_cap_pointer, 0, 0, 0, 0, 0, 0);
constant ext_cap_pointer_vector : conf_int_vector_type := (ext_cap_pointer, mf1_ext_cap_pointer, 0, 0, 0, 0, 0, 0);
constant extcfg_vector : conf_int_vector_type := (extcfg, mf1_extcfg, 0, 0, 0, 0, 0, 0);
type conf_vector16_vector_type is array (0 to 7) of std_logic_vector(15 downto 0);
constant masters_vector : conf_vector16_vector_type := (conv_std_logic_vector(masters, 16), conv_std_logic_vector(mf1_masters, 16),
x"0000", x"0000", x"0000", x"0000", x"0000", x"0000");
constant deviceirq_vector : conf_int_vector_type := (1*deviceirq, (1+1*multiint)*deviceirq, (1+2*multiint)*deviceirq, (1+3*multiint)*deviceirq,
1*deviceirq, (1+1*multiint)*deviceirq, (1+2*multiint)*deviceirq, (1+3*multiint)*deviceirq);
type default_bar_map_type is array (0 to 7) of pci_bars_type;
constant default_bar_map : default_bar_map_type := ((conv_std_logic_vector(bar0_map, 24)&x"00", conv_std_logic_vector(bar1_map, 24)&x"00",
conv_std_logic_vector(bar2_map, 24)&x"00", conv_std_logic_vector(bar3_map, 24)&x"00",
conv_std_logic_vector(bar4_map, 24)&x"00", conv_std_logic_vector(bar5_map, 24)&x"00"),
(conv_std_logic_vector(mf1_bar0_map, 24)&x"00", conv_std_logic_vector(mf1_bar1_map, 24)&x"00",
conv_std_logic_vector(mf1_bar2_map, 24)&x"00", conv_std_logic_vector(mf1_bar3_map, 24)&x"00",
conv_std_logic_vector(mf1_bar4_map, 24)&x"00", conv_std_logic_vector(mf1_bar5_map, 24)&x"00"),
pci_bars_none, pci_bars_none, pci_bars_none, pci_bars_none, pci_bars_none, pci_bars_none);
function blenmask_size(barminsize : in integer)
return integer is
variable res : integer;
begin
res := 16;
if barminsize < 16 then res := barminsize; end if;
return (res - 1);
end function;
function set_pta_addr(paddr : in std_logic_vector(31 downto 0);
pta_map : in pci_bars_type;
bar : in std_logic_vector(5 downto 0);
bar_mask: in pci_bars_type;
barminsize : in integer)
return std_logic_vector is
variable res : std_logic_vector(31 downto 0);
begin
res := paddr;
for i in 0 to 5 loop
if bar(i) = '1' then
res(31 downto barminsize) := (pta_map(i)(31 downto barminsize) and bar_mask(i)(31 downto barminsize)) or
(paddr(31 downto barminsize) and not bar_mask(i)(31 downto barminsize));
end if;
end loop;
return res;
end function;
function byte_twist(di : in std_logic_vector(31 downto 0); twist : in std_logic) return std_logic_vector is
variable do : std_logic_vector(31 downto 0);
begin
if twist = '1' then
for i in 0 to 3 loop
do(31-i*8 downto 24-i*8) := di(31-(3-i)*8 downto 24-(3-i)*8);
end loop;
else
do := di;
end if;
return do;
end function;
function set_size_from_cbe(cbe : in std_logic_vector(3 downto 0))
return std_logic_vector is
variable res : std_logic_vector(1 downto 0);
begin
case cbe is
when "0111" => res := "00";
when "1011" => res := "00";
when "1101" => res := "00";
when "1110" => res := "00";
when "0011" => res := "01";
when "1100" => res := "01";
when others => res := "10";
end case;
return res;
end function;
function set_addr_from_cbe(cbe : in std_logic_vector(3 downto 0);
twist: in std_logic)
return std_logic_vector is
variable res : std_logic_vector(1 downto 0);
begin
if twist = '1' then -- Little (PCI) to big (AHB) endian
case cbe is
when "0111" => res := "11";
when "1011" => res := "10";
when "1101" => res := "01";
when "1110" => res := "00";
when "0011" => res := "10";
when "1100" => res := "00";
when others => res := "00";
end case;
else -- Big (PCI) to big (AHB) endian
case cbe is
when "0111" => res := "00";
when "1011" => res := "01";
when "1101" => res := "10";
when "1110" => res := "11";
when "0011" => res := "00";
when "1100" => res := "10";
when others => res := "00";
end case;
end if;
return res;
end function;
function set_cbe_from_size_addr(size : in std_logic_vector(2 downto 0);
addr : in std_logic_vector(1 downto 0);
twist : in std_logic)
return std_logic_vector is
variable res : std_logic_vector(3 downto 0);
begin
if twist = '1' then
if size = "000" then -- byte
case addr is
when "11" => res := "0111";
when "10" => res := "1011";
when "01" => res := "1101";
when others => res := "1110";
end case;
elsif size = "001" then -- half word
case addr is
when "10" => res := "0011";
when others => res := "1100";
end case;
else
res := "0000";
end if;
else
if size = "000" then -- byte
case addr is
when "11" => res := "1110";
when "10" => res := "1101";
when "01" => res := "1011";
when others => res := "0111";
end case;
elsif size = "001" then -- half word
case addr is
when "10" => res := "1100";
when others => res := "0011";
end case;
else
res := "0000";
end if;
end if;
return res;
end function;
function set_atp_addr(haddr : in std_logic_vector(31 downto 0);
atp_map : in ahb_to_pci_map_type;
hmaster : in std_logic_vector(3 downto 0);
size : in integer)
return std_logic_vector is
variable res : std_logic_vector(31 downto 0);
variable i : integer;
begin
i := conv_integer(hmaster);
res := haddr;
if AADDR_WIDTH /= 4 then
res(31 downto size) := atp_map(i)(31 downto size);
end if;
return res;
end function;
function set_pci_conf_addr(addr : in std_logic_vector(31 downto 0);
cfg_bus : in std_logic_vector(23 downto 16))
return std_logic_vector is
variable res : std_logic_vector(31 downto 0);
variable i : integer range 0 to 21;
begin
res := (others => '0');
i := conv_integer(addr(15 downto 11));
if cfg_bus = zero32(23 downto 16) then -- Type 0 config
if i /= 0 then
res(10 + i) := '1';
end if;
res(10 downto 2) := addr(10 downto 2); -- Function number [10:8], Register address [7:2]
res(0) := '0'; -- Type
else -- Type 1 config
res(23 downto 16) := cfg_bus;
res(15 downto 2) := addr(15 downto 2); -- Function number [10:8], Register address [7:2]
res(0) := '1'; -- Type
end if;
return res;
end function;
function set_pci_io_addr(addr : in std_logic_vector(31 downto 0);
io_map : in std_logic_vector(31 downto 16))
return std_logic_vector is
variable res : std_logic_vector(31 downto 0);
begin
res := io_map & addr(15 downto 0);
return res;
end function;
function set_pci_io_byte_addr(addr : in std_logic_vector(1 downto 0);
size : in std_logic_vector(2 downto 0);
twist : in std_logic)
return std_logic_vector is
variable res : std_logic_vector(1 downto 0);
begin
if twist = '1' then
res := addr;
else
if size = "010" then
res := "00";
elsif size = "001" then
case addr is
when "00" => res := "10";
when others => res := "00";
end case;
else
case addr is
when "00" => res := "11";
when "01" => res := "10";
when "10" => res := "01";
when "11" => res := "00";
when others => res := "00";
end case;
end if;
end if;
return res;
end function;
begin
-- PHY =>
pciphy0 : grpci2_phy_wrapper
generic map(tech => memtech, oepol => oepol,
bypass => bypass, netlist => netlist,
scantest => scantest, iotest => iotest)
port map(
pciclk => pciclk,
pcii => pcii,
phyi => phyi,
pcio => pcio,
phyo => phyo,
iotmact => iotmact,
iotmoe => iotmoe,
iotdout => iotmdout,
iotdin => iotmdin
);
phyi.pciasyncrst <= pciasyncrst;
phyi.pcisoftrst <= sig_soft_rst;
phyi.pcirstout <= pcirstout;
phyi.pciinten <= pciinten_pad;
phyi.m_request <= sig_m_request;
phyi.m_mabort <= sig_m_mabort;
phyi.pr_m_fstate <= pr.m.fstate;
phyi.pr_m_cfifo <= pr.m.cfifo;
phyi.pv_m_cfifo <= prin.m.cfifo;
phyi.pr_m_addr <= pr.m.addr;
phyi.pr_m_cbe_data <= pr.m.cbe_data;
phyi.pr_m_cbe_cmd <= pr.m.cbe_cmd;
phyi.pr_m_first <= pr.m.first(1 downto 0);
phyi.pv_m_term <= prin.m.term(1 downto 0);
phyi.pr_m_ltimer <= pr.m.ltimer;
phyi.pr_m_burst <= pr.m.burst;
phyi.pr_m_abort <= pr.m.abort(0 downto 0);
phyi.pr_m_perren <= pr.m.perren(0 downto 0);
phyi.pr_m_done_fifo <= pr.m.done_fifo;
phyi.t_abort <= sig_t_abort;
phyi.t_ready <= sig_t_ready;
phyi.t_retry <= sig_t_retry;
phyi.pr_t_state <= pr.t.state;
phyi.pv_t_state <= prin.t.state;
phyi.pr_t_fstate <= pr.t.fstate;
phyi.pr_t_cfifo <= pr.t.cfifo;
phyi.pv_t_diswithout <= prin.t.diswithout;
phyi.pr_t_stoped <= pr.t.stoped;
phyi.pr_t_lcount <= pr.t.lcount;
phyi.pr_t_first_word <= pr.t.first_word;
phyi.pr_t_cur_acc_0_read <= pr.t.cur_acc(0).read;
phyi.pv_t_hold_write <= prin.t.hold_write;
phyi.pv_t_hold_reset <= prin.t.hold_reset;
phyi.pr_conf_comm_perren <= sig_pr_conf_comm_perren;
phyi.pr_conf_comm_serren <= sig_pr_conf_comm_serren; -- SERR# only asserted for address parity error
phyi.testen <= ahbsi.testen when scantest=1 else '0';
phyi.testoen <= ahbsi.testoen;
phyi.testrst <= ahbsi.testrst;
pcirst <= (others => phyo.pcirsto(0));
pi <= phyo.pio;
po <= phyo.poo;
-- PHY <=
disabled_dmai <= ('0', '0', (others => '0'), (others => '0'), (others => '0'), '0', '0');
scanen <= (ahbsi.testen and ahbsi.scanen) when (scantest = 1) else '0';
testin <= ahbsi.testen & "0" & ahbsi.testin(TESTIN_WIDTH-3 downto 0);
pciasyncrst <= ahbsi.testrst when (scantest = 1) and (ahbsi.testen = '1') else pcii.rst;
pciasyncrst_comb <= pcii.rst; -- Version used in comb logic, don't mux in testrst
hostrst2 : if hostrst = 2 generate
pcirstout <= rst and not ar.atp_trans.rst(2);
end generate;
hostrst1 : if hostrst = 1 generate
pcirstout <= rst and not ar.atp_trans.rst(2) when pcii.host = '0' else '1';
end generate;
hostrst0 : if hostrst = 0 generate
pcirstout <= '1';
end generate;
-- Propagate PCI reset to AMBA for peripheral devices
ptarst <= pcii.rst when pcii.host = '1' and hostrst /= 2 else '1';
-- PCI trace signal
pcisig <= pi.cbe &
pi.frame & pi.irdy & pi.trdy & pi.stop &
pi.devsel & pi.par & pi.perr & pi.serr &
pi.idsel & pr.po.req & pi.gnt & pi.lock &
pi.rst; -- & "000";
pcomb : process(pr, pi, pcirst(0), pcii, ar.atp_trans, tm_fifoo_atp, ms_fifoo_atp, md_fifoo_dtp, pcirstout, pciinten, pcisig, ar.atpt_trans,
phyo, pciasyncrst_comb, lpcim_rst, lpcit_rst, lpci_rst, iotmact)
variable pv : pci_reg_type;
variable atp_trans : ahb_to_pci_trans_type;
variable pci : pci_in_type;
variable t_hit : std_logic; -- Target bar address match
variable t_chit : std_logic; -- Target configuration space hit
variable t_bar : std_logic_vector(5 downto 0); -- PCI bar with hit
variable t_func : integer range 0 to multifunc;
variable t_ready : std_logic; -- Backend ready to send/receive data
variable t_abort : std_logic; -- Stop PCI access
variable t_retry : std_logic; -- Stop PCI access
variable t_index : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable t_cad : std_logic_vector(31 downto 0); -- Data from PCI Configuration Space Header
variable conf_func : integer range 0 to 7;
variable all_func_serren : std_logic;
variable t_acc_type : std_logic_vector(1 downto 0);
variable t_acc_impcfgreg: std_logic;
variable t_acc_burst: std_logic;
variable t_acc_read : std_logic;
variable tm_acc_pending : std_logic;
variable tm_acc_cancel : std_logic;
variable tm_acc_done : std_logic;
variable tm_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable tm_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable tm_fifo : pci_g_fifo_trans_vector_type;
variable accbufindex : integer range 0 to 3;
-- PCI master
variable m_request : std_logic;
variable m_ready : std_logic;
variable m_mabort : std_logic; -- Master abort
variable m_tabort : std_logic; -- Target abort
variable m_index : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable m_func : integer range 0 to multifunc;
variable acc : pci_master_acc_type;
variable accdone : std_logic; -- Renamed to be synthesized with XST
variable acc_cancel : std_logic;
variable acc_switch : std_logic;
variable fifo : pci_g_fifo_trans_vector_type;
variable fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable fifo_nindex : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable msd_acc : pci_g_acc_trans_multi_type;
variable ms_acc_pending : std_logic;
variable ms_acc_done : std_logic;
variable ms_acc_cancel : std_logic;
variable ms_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable ms_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable ms_fifo : pci_g_fifo_trans_vector_type;
variable md_acc_pending : std_logic;
variable md_acc_done : std_logic;
variable md_acc_cancel : std_logic;
variable md_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable md_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable md_fifo : pci_g_fifo_trans_vector_type;
-- PCI trace
variable pt_start : std_logic;
variable pt_stop : std_logic;
variable atpt_trans : apb_to_pci_trace_trans_type;
variable pt_setup : apb_to_pci_trace_trans_type;
constant z : std_logic_vector(48 downto 0) := (others => '0');
-- Soft reset
variable pci_target_rst : std_logic;
variable pci_master_rst : std_logic;
variable pci_hard_rst : std_logic;
begin
-- --------------------------------------------------------------------------------
-- Global defaults
-- --------------------------------------------------------------------------------
-- Defaults
pv := pr;
pv.pta_trans.ca_host := pcii.host;
pv.pci66(0) := pcii.pci66; pv.pci66(1) := pr.pci66(0);
-- FIFO and PCI<=>AHB sync
pv.sync(1) := ar.atp_trans; pv.sync(2) := pr.sync(1);
if nsync = 0 then atp_trans := ar.atp_trans;
else atp_trans := pr.sync(nsync); end if;
-- PCI soft reset
pv.pta_trans.rst_ack(0) := atp_trans.rst(0);
pv.pta_trans.rst_ack(1) := atp_trans.rst(1);
pci_target_rst := not pr.pta_trans.rst_ack(0) and (pr.pta_trans.rst_ack(0) xor atp_trans.rst(0));
pci_master_rst := not pr.pta_trans.rst_ack(1) and (pr.pta_trans.rst_ack(1) xor atp_trans.rst(1));
pci_hard_rst := atp_trans.rst(2);
pci := phyo.pciv;
if (pr.po.perr = '0' -- Parity Error detected
and (pr.m.perren /= "00")) then -- During master read
pv.conf(pr.m.acc(pr.m.acc_sel).func).stat.dpe := '1';
end if;
if (pr.po.perr = '0' -- Parity Error detected
and ((pr.t.state = pt_s_data or pr.t.state = pt_turn_ar) and pr.t.cur_acc(0).read = '0')) -- Write to target
or (pr.t.addr_perr = '1') then -- Parity Error in Address phase
pv.conf(pr.t.cur_acc(0).func).stat.dpe := '1';
end if;
-- Signaled System Error
for j in 0 to multifunc loop
if pr.conf(j).comm.perren = '1' and pr.conf(j).comm.serren = '1' and pr.po.serren = oeon then
pv.conf(j).stat.sse := '1';
end if;
end loop;
-- SERR to AHB
if atp_trans.pa_serr_rst = '1' then
pv.pta_trans.pa_serr := '1';
elsif pi.serr = '0' then
pv.pta_trans.pa_serr := '0';
end if;
-- --------------------------------------------------------------------------------
-- PCI master defaults
-- --------------------------------------------------------------------------------
-- Default
m_request := '0';
m_ready := '0';
m_ready := '1';
pv.m.fifo_switch := '0';
pv.m.acc(0).fifo_ren := '0'; -- read enable [AHB]
pv.m.acc(0).fifo_wen := '0'; -- write enable [AHB]
pv.m.acc(1).fifo_ren := '0'; -- read enable [DMA]
pv.m.acc(1).fifo_wen := '0'; -- write enable [DMA]
pv.m.fifo_wdata := byte_twist(pi.ad, pr.m.twist);
pv.m.framedel := pr.po.frame;
ms_acc_pending := atp_trans.msd_acc(0).pending xor pr.pta_trans.msd_acc_ack(0);
ms_acc_done := atp_trans.msd_acc_done_ack(0) xor pr.pta_trans.msd_acc_done(0).done;
ms_acc_cancel := atp_trans.msd_acc_cancel(0) xor pr.pta_trans.msd_acc_cancel_ack(0)(0);
-- Stop_ack also needs to be delayed when pending is delayed
pv.pta_trans.msd_acc_cancel_ack(0)(1) := pr.pta_trans.msd_acc_cancel_ack(0)(0);
pv.pta_trans.msd_acc_cancel_ack(0)(2) := pr.pta_trans.msd_acc_cancel_ack(0)(1);
for i in 0 to FIFO_COUNT-1 loop
ms_fifo_pending(i) := atp_trans.msd_fifo(0)(i).pending(RAM_LATENCY) xor pr.pta_trans.msd_fifo_ack(0)(i);
ms_fifo_empty(i) := not (pr.pta_trans.msd_fifo(0)(i).pending(0) xor atp_trans.msd_fifo_ack(0)(i));
-- To set pending when data is stored in fifo, with this stop_ack also needs to be delayed
pv.pta_trans.msd_fifo(0)(i).pending(1) := pr.pta_trans.msd_fifo(0)(i).pending(0);
pv.pta_trans.msd_fifo(0)(i).pending(2) := pr.pta_trans.msd_fifo(0)(i).pending(1);
end loop;
ms_fifo := ar.atp_trans.msd_fifo(0);
msd_acc(0) := ar.atp_trans.msd_acc(0);
md_acc_pending := atp_trans.msd_acc(1).pending xor pr.pta_trans.msd_acc_ack(1);
md_acc_done := atp_trans.msd_acc_done_ack(1) xor pr.pta_trans.msd_acc_done(1).done;
md_acc_cancel := atp_trans.msd_acc_cancel(1) xor pr.pta_trans.msd_acc_cancel_ack(1)(0);
-- Stop_ack also needs to be delayed when pending is delayed
pv.pta_trans.msd_acc_cancel_ack(1)(1) := pr.pta_trans.msd_acc_cancel_ack(1)(0);
pv.pta_trans.msd_acc_cancel_ack(1)(2) := pr.pta_trans.msd_acc_cancel_ack(1)(1);
for i in 0 to FIFO_COUNT-1 loop
md_fifo_pending(i) := atp_trans.msd_fifo(1)(i).pending(RAM_LATENCY) xor pr.pta_trans.msd_fifo_ack(1)(i);
md_fifo_empty(i) := not (pr.pta_trans.msd_fifo(1)(i).pending(0) xor atp_trans.msd_fifo_ack(1)(i));
-- To set pending when data is stored in fifo, with this stop_ack also needs to be delayed
pv.pta_trans.msd_fifo(1)(i).pending(1) := pr.pta_trans.msd_fifo(1)(i).pending(0);
pv.pta_trans.msd_fifo(1)(i).pending(2) := pr.pta_trans.msd_fifo(1)(i).pending(1);
end loop;
md_fifo := ar.atp_trans.msd_fifo(1);
msd_acc(1) := ar.atp_trans.msd_acc(1);
-- PCI master function
m_func := pr.m.acc(pr.m.acc_sel).func;
-- --------------------------------------------------------------------------------
-- PCI master core
-- --------------------------------------------------------------------------------
if master /= 0 or dma /= 0 then -- PCI master enabled
-- First
if pr.m.state = pm_idle or pr.m.state = pm_turn_ar or pr.m.state = pm_dr_bus then
pv.m.first(0) := '1';
else
pv.m.first(0) := '0';
end if;
pv.m.first(1) := pr.m.first(0);
-- Master Data Parity Error
if pr.m.state = pm_m_data then
if pr.m.fstate = pmf_read then
pv.m.perren(0) := '1';
elsif pr.m.fstate = pmf_fifo then
pv.m.detectperr(0) := '1';
end if;
else
pv.m.perren(0) := '0';
pv.m.detectperr(0) := '0';
end if;
pv.m.perren(1) := pr.m.perren(0);
pv.m.detectperr(1) := pr.m.detectperr(0);
if pr.conf(m_func).comm.perren = '1' and -- Parity error response bit[6] = 1
((pr.m.perren /= "00" and pr.po.perr = '0') -- Parity error is signaled by master on read
or (pr.m.detectperr(1) = '1' and pci.perr = '0')) then-- Parity error is signaled by target on write
pv.conf(m_func).stat.mdpe := '1';
pv.m.acc(pr.m.acc_sel).status(0) := '1';
end if;
-- PCI master latency timer
if (pr.m.framedel and not pr.po.frame) = '1' then
pv.m.ltimer := pr.conf(m_func).ltimer;
elsif pr.m.ltimer /= x"00" and pr.po.frame = '0' then
pv.m.ltimer := pr.m.ltimer - 1;
end if;
-- Devsel time out counter (and master abort signaling)
if pci.devsel = '0' then pv.m.devsel_asserted := '1'; end if;
if (pr.m.framedel and not pr.po.frame) = '1' then
pv.m.devsel_tout := "100";
pv.m.devsel_asserted := '0';
elsif pr.m.devsel_asserted = '1' then
pv.m.devsel_tout := "100";
elsif pr.m.devsel_tout /= "000" then
pv.m.devsel_tout := pr.m.devsel_tout - 1;
end if;
if (pr.m.devsel_tout = "000" and pr.m.devsel_asserted = '0') and pi.devsel = '1' and pr.m.state = pm_m_data then m_mabort := '1'; pv.conf(m_func).stat.rma := '1'; else m_mabort := '0'; end if; -- Master abort -- delayed mabort one cycle (to reduce pci.devsel timing path)
if pi.devsel = '1' and pi.stop = '0' and pr.m.state = pm_s_tar then m_tabort := '1'; pv.conf(m_func).stat.rta := '1'; else m_tabort := '0'; end if; -- Target abort
if (pr.m.state = pm_m_data and m_mabort = '1') or (pr.m.state = pm_s_tar and m_tabort = '1') then
pv.m.abort(0) := '1';
pv.m.abort(1) := m_tabort;
elsif pr.m.state = pm_s_tar or pr.m.state = pm_idle or pr.m.state = pm_dr_bus then
pv.m.abort := (others => '0');
end if;
if pr.m.abort(0) = '1' then pv.m.abort(0) := '0'; end if;
-- Access acknowledge and arbitration [AHB/DMA]
for i in 0 to 1*dma loop
if ((ms_acc_pending = '1' and i = acc_sel_ahb) or (md_acc_pending = '1' and i = acc_sel_dma)) and pr.m.acc(i).pending = '0' then
pv.pta_trans.msd_acc_ack(i) := atp_trans.msd_acc(i).pending;
pv.m.acc(i).pending := '1';
pv.m.acc(i).active := (others => '0');
pv.m.acc(i).done := (others => '0');
pv.m.acc(i).status := (others => '0');
pv.m.acc(i).first := '1';
pv.m.acc(i).addr := msd_acc(i).addr(31 downto 2) & "00";
pv.m.acc(i).func := conv_integer(msd_acc(i).func);
pv.m.acc(i).cmd := msd_acc(i).acctype;
pv.m.acc(i).mode := msd_acc(i).accmode;
pv.m.acc(i).fifo_index := msd_acc(i).index;
if msd_acc(i).acctype(0) = '1' then
pv.m.acc(i).length := (others => '0');
else
pv.m.acc(i).length := msd_acc(i).length;
end if;
if msd_acc(i).acctype = CONF_READ or msd_acc(i).acctype = CONF_WRITE then -- Config
if i = acc_sel_ahb then pv.m.acc(i).endianess := '1'; -- Endianess is not set for AHB slave
else pv.m.acc(i).endianess := msd_acc(i).endianess; end if; -- Endianess is set for DMA
pv.m.acc(i).addr := msd_acc(i).addr; -- PCI CONF address set in AHB slave
pv.m.acc(i).cbe := set_cbe_from_size_addr(msd_acc(i).size, msd_acc(i).offset(1 downto 0), '1'); -- Set CBE depending on AHB size and address
elsif msd_acc(i).acctype = IO_READ or msd_acc(i).acctype = IO_WRITE then -- IO
if i = acc_sel_ahb then pv.m.acc(i).endianess := pr.pta_trans.ca_twist; -- Endianess is not set for AHB slave
else pv.m.acc(i).endianess := msd_acc(i).endianess; end if; -- Endianess is set for DMA
pv.m.acc(i).addr(1 downto 0) := set_pci_io_byte_addr(msd_acc(i).offset(1 downto 0), msd_acc(i).size, pr.pta_trans.ca_twist); -- PCI IO used byte address
pv.m.acc(i).cbe := set_cbe_from_size_addr(msd_acc(i).size, msd_acc(i).offset(1 downto 0), pr.pta_trans.ca_twist); -- Set CBE depending on AHB size and address
else -- Mem
if i = acc_sel_ahb then pv.m.acc(i).endianess := pr.pta_trans.ca_twist; -- Endianess is not set for AHB slave
else pv.m.acc(i).endianess := msd_acc(i).endianess; end if; -- Endianess is set for DMA
pv.m.acc(i).cbe := set_cbe_from_size_addr(msd_acc(i).size, msd_acc(i).offset(1 downto 0), pr.pta_trans.ca_twist); -- Set CBE depending on AHB size and address
end if;
end if;
if pr.m.acc(i).pending = '1' and pr.m.acc(i).active(1) = '0' and pr.m.acc(i).done(0) = '1' and pr.m.acc(i).cmd(0) = '1' then -- Status pending
if pr.m.acc(i).done(2 downto 1) = "10" then
if (i = acc_sel_ahb and ms_fifo_pending(pr.m.acc(i).fifo_index) = '1') or (i = acc_sel_dma and md_fifo_pending(pr.m.acc(i).fifo_index) = '1') then
if pr.m.acc(i).fifo_index /= FIFO_COUNT-1 then pv.m.acc(i).fifo_index := pr.m.acc(i).fifo_index + 1;
else pv.m.acc(i).fifo_index := 0; end if;
pv.pta_trans.msd_fifo_ack(i)(pr.m.acc(i).fifo_index) := not pv.pta_trans.msd_fifo_ack(i)(pr.m.acc(i).fifo_index);
if (i = acc_sel_ahb and ms_fifo(pr.m.acc(i).fifo_index).lastf = '1') or (i = acc_sel_dma and md_fifo(pr.m.acc(i).fifo_index).lastf = '1') then
pv.m.acc(i).done(1) := '1';
end if;
end if;
elsif ((ms_acc_done = '0' and i = acc_sel_ahb) or (md_acc_done = '0' and i = acc_sel_dma)) then
pv.pta_trans.msd_acc_done(i).done := not pr.pta_trans.msd_acc_done(i).done;
pv.pta_trans.msd_acc_done(i).status(2 downto 0) := pr.m.acc(i).status;
if pr.m.acc(i).cmd = CONF_WRITE then pv.pta_trans.msd_acc_done(i).status(3) := '1'; -- Status(3) indicates CONF_WRITE
else pv.pta_trans.msd_acc_done(i).status(3) := '0'; end if;
pv.pta_trans.msd_acc_done(i).count := pr.m.acc(i).length;
pv.m.acc(i).pending := '0';
end if;
end if;
-- Access canceled
if pr.m.acc(i).pending = '1' and pr.m.acc(i).active = "10" and pr.m.acc(i).cmd(0) = '0' then
if ((ms_acc_cancel = '1' and i = acc_sel_ahb) or (md_acc_cancel = '1' and i = acc_sel_dma)) then
pv.m.acc(i).done(0) := '1';
pv.m.acc(i).active(1) := '0';
end if;
end if;
if pr.m.acc(i).pending = '1' and pr.m.acc(i).active(1) = '0' and pr.m.acc(i).done(0) = '1' and pr.m.acc(i).cmd(0) = '0' then -- Status pending
if pr.m.acc(i).done(1 downto 0) = "01" then
if ((ms_acc_cancel = '1' and i = acc_sel_ahb) or (md_acc_cancel = '1' and i = acc_sel_dma)) then
pv.m.acc(pr.m.acc_sel).done(1) := '1';
for j in 0 to FIFO_COUNT-1 loop
if (i = acc_sel_ahb and ms_fifo_empty(j) = '0') or (i = acc_sel_dma and md_fifo_empty(j) = '0') then
pv.pta_trans.msd_fifo(i)(j).pending(0) := not pr.pta_trans.msd_fifo(i)(j).pending(0);
else
pv.pta_trans.msd_fifo(i)(j).pending(0) := pr.pta_trans.msd_fifo(i)(j).pending(0);
end if;
end loop;
end if;
else
pv.pta_trans.msd_acc_cancel_ack(i)(0) := atp_trans.msd_acc_cancel(i);
pv.m.acc(i).pending := '0';
end if;
end if;
end loop;
-- control access switching
if atp_trans.mstswdis = '0' then
if (pr.m.acc_sel = acc_sel_dma and pr.m.acc(0).pending = '1' and pr.m.acc(0).done(0) = '0'
and ((pr.m.acc(0).cmd(0) and ms_fifo_pending(pr.m.acc(0).fifo_index))
or (not pr.m.acc(0).cmd(0) and ms_fifo_empty(pr.m.acc(0).fifo_index))) = '1')
or
(pr.m.acc_sel = acc_sel_ahb and pr.m.acc(1).pending = '1' and pr.m.acc(1).done(0) = '0'
and ((pr.m.acc(1).cmd(0) and md_fifo_pending(pr.m.acc(1).fifo_index))
or (not pr.m.acc(1).cmd(0) and md_fifo_empty(pr.m.acc(1).fifo_index))) = '1')
then
if pr.m.acc_cnt = MST_ACC_CNT then
pv.m.acc_switch := '1';
end if;
end if;
else
pv.m.acc_switch := '0';
end if;
acc_switch := pv.m.acc_switch;
if ((pr.m.acc(0).pending = '1' and pr.m.acc(0).done(0) = '0'
and ms_acc_cancel = '0' and pr.m.acc(1).active(0) = '0'
and ((pr.m.acc(0).cmd(0) and ms_fifo_pending(pr.m.acc(0).fifo_index))
or (not pr.m.acc(0).cmd(0) and ms_fifo_empty(pr.m.acc(0).fifo_index))) = '1')
and not (pr.m.acc_switch = '1' and pr.m.acc_sel = acc_sel_ahb))
or pr.m.acc(0).active(0) = '1' then
acc := pr.m.acc(0);
accdone := ms_acc_done;
acc_cancel := ms_acc_cancel;
pv.m.acc_sel := acc_sel_ahb;
fifo_pending := ms_fifo_pending;
fifo_empty := ms_fifo_empty;
fifo := ms_fifo;
if pr.m.acc_sel = acc_sel_dma then
pv.m.acc_cnt := 0;
pv.m.acc_switch := '0';
end if;
elsif (pr.m.acc(1).pending = '1' and pr.m.acc(1).done(0) = '0'
and md_acc_cancel = '0' and pr.m.acc(0).active(0) = '0'
and ((pr.m.acc(1).cmd(0) and md_fifo_pending(pr.m.acc(1).fifo_index))
or (not pr.m.acc(1).cmd(0) and md_fifo_empty(pr.m.acc(1).fifo_index))) = '1')
or pr.m.acc(1).active(0) = '1' then
acc := pr.m.acc(1);
accdone := md_acc_done;
acc_cancel := md_acc_cancel;
pv.m.acc_sel := acc_sel_dma;
fifo_pending := md_fifo_pending;
fifo_empty := md_fifo_empty;
fifo := md_fifo;
if pr.m.acc_sel = acc_sel_ahb then
pv.m.acc_cnt := 0;
pv.m.acc_switch := '0';
end if;
else
acc := pci_master_acc_none;
accdone := '0';
acc_cancel := '0';
pv.m.acc_sel := acc_sel_ahb;
fifo_pending := (others => '0');
fifo_empty := (others => '0');
fifo := ms_fifo;
pv.m.acc_cnt := 0;
pv.m.acc_switch := '0';
end if;
if acc.fifo_index /= FIFO_COUNT-1 then fifo_nindex := (acc.fifo_index + 1);
else fifo_nindex := 0; end if;
-- FIFO state machine
case pr.m.fstate is
when pmf_idle =>
pv.m.waitonstop := '0';
pv.m.done := '0';
pv.m.done_fifo := '0';
pv.m.done_trans := '0';
pv.m.term := (others => '0');
pv.m.preload := '0';
pv.m.preload_count := (others => '0');
pv.m.afull := '0';
pv.m.afullcnt := (others => '0');
if acc.pending = '1' then
pv.m.addr := acc.addr;
pv.m.twist := acc.endianess;
pv.m.cbe_cmd := acc.cmd;
pv.m.cbe_data := acc.cbe;
pv.m.burst := acc.mode(0);
pv.m.acc_cnt := 0;
if acc.cmd(0) = '1' then -- Write access
pv.m.fstate := pmf_fifo;
pv.m.fifo_addr := conv_std_logic_vector(acc.fifo_index, log2(FIFO_COUNT)) & fifo(acc.fifo_index).start; -- Set fifo start address
else -- Read access
pv.m.fstate := pmf_read;
end if;
pv.m.acc(pv.m.acc_sel).active := "11";
end if;
when pmf_fifo =>
pv.m.acc(pr.m.acc_sel).fifo_ren := fifo_pending(acc.fifo_index);
if pr.m.term = "00" and pr.m.last(0) = '0' and pr.m.done = '0' and (pr.m.cfifo(0).valid = '1' or pr.m.hold(0) = '1')
and m_mabort = '0' and pr.m.abort(0) = '0' then -- request bus if not: latency timer count out; last data phase; transfer done
m_request := '1';
end if;
if (fifo_pending(acc.fifo_index) = '1') and pr.m.done = '0' then -- preload data
pv.m.preload := '1';
pv.m.hold_fifo := '0';
end if;
if ((pi.trdy or pi.irdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar)) or pr.m.preload = '1' or (pr.m.abort(0)) = '1' then
if ((pi.trdy or pi.irdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar)) or (pr.m.abort(0)) = '1' then
pv.m.cfifo(0) := pr.m.cfifo(1); pv.m.cfifo(1) := pr.m.cfifo(2); -- Preload master core fifo
elsif pr.m.preload = '1' then
if pr.m.cfifo(0).valid = '0' then
pv.m.cfifo(0) := pr.m.cfifo(1); pv.m.cfifo(1) := pr.m.cfifo(2); -- Preload master core fifo
elsif pr.m.cfifo(0).valid = '1' and pr.m.cfifo(1).valid = '0' then
pv.m.cfifo(1) := pr.m.cfifo(2); -- Preload master core fifo
end if;
end if;
if pr.m.acc(0).active(0) = '1' then
pv.m.cfifo(2).data := byte_twist(ms_fifoo_atp.data, acc.endianess); -- shifting in data from backend fifo
elsif pr.m.acc(1).active(0) = '1' then
pv.m.cfifo(2).data := byte_twist(md_fifoo_dtp.data, acc.endianess); -- shifting in data from DMA fifo
end if;
if pr.m.done_fifo = '0' and fifo_pending(acc.fifo_index) = '1' then
if pr.m.fifo_addr(FIFO_DEPTH-1 downto 0) = fifo(acc.fifo_index).stop then -- Mark last word
if pr.m.acc_cnt /= MST_ACC_CNT then pv.m.acc_cnt := pr.m.acc_cnt + 1; end if; -- Switch DAM/AHB-slave after MST_ACC_CNT FIFOs
pv.m.fifo_switch := '1';
pv.m.acc(pr.m.acc_sel).fifo_index := fifo_nindex;
pv.pta_trans.msd_fifo_ack(pr.m.acc_sel)(acc.fifo_index) := fifo(acc.fifo_index).pending(RAM_LATENCY); -- Ack the fifo (done using this data)
pv.m.fifo_addr := conv_std_logic_vector(fifo_nindex, log2(FIFO_COUNT)) & zero32(FIFO_DEPTH-1 downto 0); -- New fifo address (should be ok with [index & zero] or & fifo(fifo_nindex).start)
if fifo_pending(fifo_nindex) = '0' or acc_switch = '1' then -- If no fifo pending => idle
pv.m.cfifo(2).last := '1';
pv.m.done_fifo := '1';
else
pv.m.cfifo(2).hold := '0';
pv.m.cfifo(2).last := '0';
end if;
if fifo(acc.fifo_index).lastf = '1' then -- Last fifo, transfer is done
pv.m.cfifo(2).last := '1';
pv.m.done_fifo := '1';
pv.m.done_trans := '1';
end if;
else
pv.m.cfifo(2).hold := '0';
pv.m.cfifo(2).last := '0';
if pr.m.done_fifo = '0' and fifo_pending(acc.fifo_index) = '1' then
pv.m.fifo_addr(FIFO_DEPTH-1 downto 0) := pr.m.fifo_addr(FIFO_DEPTH-1 downto 0) + 1; -- inc backend fifo address
end if;
end if;
else
pv.m.cfifo(2).hold := '0';
pv.m.cfifo(2).last := '0';
end if;
pv.m.cfifo(2).stlast := '0';
if fifo_pending(acc.fifo_index) = '1' and pr.m.done_fifo = '0' then -- Adding valid data to CFIFO
pv.m.cfifo(2).valid := '1';
else
pv.m.cfifo(2).valid := '0';
pv.m.cfifo(2).last := '0';
pv.m.cfifo(2).stlast := '0';
pv.m.cfifo(2).hold := '0';
end if;
end if;
if (pv.m.cfifo(0).valid = '1' and pv.m.cfifo(1).valid = '1' and pv.m.cfifo(2).valid = '1')
or (pv.m.cfifo(0).valid = '1' and pr.m.done_fifo = '1' and not (pv.m.cfifo(1).valid = '0' and pv.m.cfifo(2).valid = '1')) then
pv.m.preload := '0';
if pr.m.cfifo(0).hold = '1' and pv.m.cfifo(1).valid = '1' then pv.m.cfifo(0).hold := '0'; end if;
if pr.m.cfifo(1).hold = '1' and pv.m.cfifo(2).valid = '1' then pv.m.cfifo(1).hold := '0'; end if;
end if;
if pr.m.abort(0) = '1' then -- Empty core FIFO on master/target abort
for i in 0 to 2 loop
pv.m.cfifo(i).valid := '0';
end loop;
end if;
if ((pi.trdy or pi.irdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar)) or (pr.m.abort(0)) = '1' then
pv.m.addr := pr.m.addr + 4;
if acc.mode(1) = '1' and pr.m.abort(0) = '0' then -- Use acc.length
pv.m.acc(pr.m.acc_sel).length := pr.m.acc(pr.m.acc_sel).length + 1;
end if;
if pr.m.last(1) = '1' or pr.m.abort(0) = '1' then pv.m.done := '1'; end if; -- Last data phase is done => transfer done
-- Signal ERROR to AHB
if pr.m.abort(0) = '1' then
pv.m.acc(pr.m.acc_sel).done(2) := '1'; -- Error
pv.m.acc(pr.m.acc_sel).status(2 downto 1) := (not pr.m.abort(1) or m_mabort) & (pr.m.abort(1) or m_tabort); -- Error type: Master abort, Target abort, (PAR error)
end if;
end if;
if (pr.m.state = pm_s_tar or pr.m.state = pm_turn_ar) then
pv.m.term := (others => '0'); m_request := '0';
end if;
if pr.m.done = '1' then
pv.m.fstate := pmf_idle;
pv.m.acc(pr.m.acc_sel).active(0) := '0';
pv.m.acc(pr.m.acc_sel).addr := pr.m.addr;
if pr.m.done_trans = '1' or acc.done(2) = '1' then
pv.m.acc(pr.m.acc_sel).active(1) := '0';
pv.m.acc(pr.m.acc_sel).done(0) := '1';
if pr.m.done_trans = '1' then pv.m.acc(pr.m.acc_sel).done(1) := '1'; end if;
if accdone = '0' and pr.m.done_trans = '1' then
pv.pta_trans.msd_acc_done(pr.m.acc_sel).done := not pr.pta_trans.msd_acc_done(pr.m.acc_sel).done;
pv.pta_trans.msd_acc_done(pr.m.acc_sel).status(2 downto 0) := pv.m.acc(pr.m.acc_sel).status; -- use pv.. (par error detection)
if pr.m.acc(pr.m.acc_sel).cmd = CONF_WRITE then pv.pta_trans.msd_acc_done(pr.m.acc_sel).status(3) := '1'; -- Status(3) indicates CONF_WRITE
else pv.pta_trans.msd_acc_done(pr.m.acc_sel).status(3) := '0'; end if;
pv.pta_trans.msd_acc_done(pr.m.acc_sel).count := pr.m.acc(pr.m.acc_sel).length;
pv.m.acc(pr.m.acc_sel).pending := '0';
end if;
end if;
end if;
if pi.stop = '0' and pr.m.state /= pm_idle then m_request := '0'; end if; -- Second deasserted req cycle
when pmf_read =>
if pr.m.term(0) = '0' and m_mabort = '0' and pr.m.abort(0) = '0' and (pi.stop = '1' or pr.m.first(0) = '1') and pr.m.waitonstop = '0' then -- request bus if not: latency timer count out; no empty fifo to fill
m_request := '1'; -- request should be deasserted earlier
end if;
if pr.m.burst = '0' then -- Single access, only one data phase
if pr.po.frame = '0' then
pv.m.term(0) := '1';
elsif (pi.trdy and not pi.stop) = '1' then -- retry
pv.m.term := (others => '0');
end if;
end if;
if (pi.irdy or pi.trdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_s_tar or pr.m.state = pm_turn_ar)then
pv.m.addr := pr.m.addr + 4;
if acc.mode(1) = '1' then -- Use acc.length
pv.m.acc(pr.m.acc_sel).length := pr.m.acc(pr.m.acc_sel).length - 1;
end if;
if pr.m.addr(AHB_FIFO_BITS) = ones32(FIFO_DEPTH-1 downto 0) or pr.m.burst = '0' or (acc.mode(1) = '1' and acc.length = x"0000") then
if pr.m.acc_cnt /= MST_ACC_CNT then pv.m.acc_cnt := pr.m.acc_cnt + 1; end if; -- Switch DMA/AHB-slave after MST_ACC_CNT FIFOs
pv.m.fifo_switch := '1';
pv.m.acc(pr.m.acc_sel).fifo_index := fifo_nindex;
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).pending(0) := not pr.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).pending(0);
pv.m.acc(pr.m.acc_sel).first := '0';
if acc.first = '1' then
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).firstf := '1';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).start := acc.addr(AHB_FIFO_BITS);
else
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).firstf := '0';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).start := (others => '0');
end if;
if (acc.mode(1) = '1' and acc.length = x"0000") or pr.m.burst = '0' then
pv.m.acc(pr.m.acc_sel).done(0) := '1';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).lastf := '1';
else
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).lastf := '0';
end if;
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).status := (others => '0');
end if;
pv.m.acc(pr.m.acc_sel).fifo_wen := '1';
pv.m.fifo_addr := conv_std_logic_vector(acc.fifo_index, log2(FIFO_COUNT)) & pr.m.addr(AHB_FIFO_BITS);
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).stop := pv.m.fifo_addr(FIFO_DEPTH-1 downto 0);
if ((fifo_empty(fifo_nindex) = '0' or acc_switch = '1') and pr.m.fifo_addr(FIFO_DEPTH-1 downto 0) = conv_std_logic_vector((conv_integer(ones32(FIFO_DEPTH-1 downto 0)) - 3), FIFO_DEPTH)) -- terminate access when 3 words left to store in FIFO or 3 word left i transfer
or (acc.mode(1) = '1' and acc.length = x"0002") then
pv.m.term(0) := '1';
pv.m.afull := '1'; -- almost full
pv.m.afullcnt := "00"; -- reset full counter
end if;
if pr.m.afull = '1' then -- when transfer is terminated, count data phases (1 - 3)
if pr.m.afullcnt = "01" then
pv.m.afullcnt := (others => '0');
pv.m.afull := '0';
else
pv.m.afullcnt := pr.m.afullcnt + 1;
end if;
end if;
end if;
if (pr.m.afull = '1' and pr.m.afullcnt = "01" and pr.m.first(0) = '1' and pr.m.state = pm_addr)
or (pr.m.afull = '1' and pr.m.afullcnt = "00" and pr.m.state = pm_m_data) -- terminate first or second data phase depending on space left in fifo
or (acc.mode(1) = '1' and ((acc.length = x"0000" and pr.m.state = pm_addr) or (acc.length = x"0001" and pr.m.state = pm_m_data)))then pv.m.term(0) := '1'; end if; -- DMA 1 or 2 word to complete transfer
if pr.m.term(0) = '1' and fifo_empty(acc.fifo_index) = '1' and (pr.m.state = pm_idle or pr.m.state = pm_dr_bus) then
pv.m.term := (others => '0'); -- Start new access when a fifo becomes empty
end if;
if pr.m.state = pm_s_tar and fifo_empty(acc.fifo_index) = '1' and pv.m.fifo_switch = '0' then pv.m.term(0) := '0'; end if; -- If disconnected, rerequest the bus if fifo is available (but not if fifo switch)
if (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar) and pi.irdy = '0' and (pi.trdy = '0' or (pi.stop = '0' and pi.devsel = '1')) then pv.m.first_word := '0'; end if;
if (acc.done(0) = '1' and (pv.m.first_word = '0' or acc.done(2) = '1'))
or ((pr.m.acc_switch = '1' or fifo_empty(acc.fifo_index) = '0') and pr.m.fifo_switch = '1') then -- Transfer read is done (or no empty fifo), cancelled or access arbitration
m_request := '0';
pv.m.term(0) := '1';
if ((pi.frame and pi.irdy) = '1' and (pr.m.state = pm_idle or pr.m.state = pm_dr_bus)) then
pv.m.fstate := pmf_idle;
pv.m.term := (others => '0');
pv.m.acc(pr.m.acc_sel).active(0) := '0';
pv.m.acc(pr.m.acc_sel).addr := pr.m.addr;
if acc.done(0) = '1' then
pv.m.acc(pr.m.acc_sel).active(1) := '0';
if acc.mode(2) = '0' or acc.mode(0) = '0' then
pv.m.acc(pr.m.acc_sel).pending := '0';
pv.m.acc(pr.m.acc_sel).done(1) := '1';
else
pv.m.acc(pr.m.acc_sel).done(1) := '0';
end if;
end if;
end if;
end if;
-- Access canceled
if acc_cancel = '1' then
pv.m.acc(pr.m.acc_sel).done(0) := '1';
end if;
-- Access aborted by PCI error
if pr.m.abort(0) = '1' and pr.m.acc(pr.m.acc_sel).done(2) = '0' then
pv.m.acc(pr.m.acc_sel).done(0) := '1';
pv.m.acc(pr.m.acc_sel).done(2) := '1'; -- error
pv.m.acc(pr.m.acc_sel).fifo_index := fifo_nindex;
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).pending(0) := not pr.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).pending(0);
pv.m.acc(pr.m.acc_sel).first := '0';
if acc.first = '1' then
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).firstf := '1';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).start := acc.addr(AHB_FIFO_BITS);
else
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).firstf := '0';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).start := (others => '0');
end if;
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).lastf := '1';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).status := '0' & (not pr.m.abort(1) or m_mabort) & (pr.m.abort(1) or m_tabort) & '0'; -- Error type: Master abort, Target abort, (PAR error)
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).stop := pr.m.addr(AHB_FIFO_BITS);
end if;
-- Set PAR error status
if pr.m.fifo_switch = '1' then
pv.pta_trans.msd_fifo(pr.m.acc_sel)(conv_integer(pr.m.fifo_addr(pr.m.fifo_addr'left downto FIFO_DEPTH))).status(0) := pv.m.acc(pr.m.acc_sel).status(0);
pv.m.acc(pr.m.acc_sel).status(0) := '0';
end if;
when others =>
end case;
-- New (Master state machine is moed to PHY)
if pr.m.state = pm_addr then pv.m.first_word := '1'; end if;
end if; -- PCI master enabled
-- --------------------------------------------------------------------------------
-- PCI target defaults
-- --------------------------------------------------------------------------------
-- Defaults
t_hit := '0'; t_chit := '0';
pv.t.cur_acc(0).newacc := '0';
pv.t.hold_reset := '1';
t_cad := (others => '0');
pv.t.first_word := '0';
t_ready := '0'; t_retry := '0';
t_abort := pr.t.stop;
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "00";
t_acc_impcfgreg := '1';
-- FIFO (Block RAM enable(read)/write)
pv.t.atp.ctrl.en := '0'; -- read enable
pv.t.pta.ctrl.en := '0'; -- write enable
pv.t.pta.ctrl.data := byte_twist(pi.ad, pr.pta_trans.ca_twist);
tm_acc_pending := pr.pta_trans.tm_acc.pending xor atp_trans.tm_acc_ack;
tm_acc_cancel := pr.pta_trans.tm_acc_cancel xor atp_trans.tm_acc_cancel_ack(RAM_LATENCY);
tm_acc_done := pr.pta_trans.tm_acc_done_ack xor atp_trans.tm_acc_done.done;
for i in 0 to FIFO_COUNT-1 loop
tm_fifo_pending(i) := atp_trans.tm_fifo(i).pending(RAM_LATENCY) xor pr.pta_trans.tm_fifo_ack(i);
tm_fifo_empty(i) := not (pr.pta_trans.tm_fifo(i).pending(0) xor atp_trans.tm_fifo_ack(i));
pv.pta_trans.tm_fifo(i).pending(1) := pr.pta_trans.tm_fifo(i).pending(0);
pv.pta_trans.tm_fifo(i).pending(2) := pr.pta_trans.tm_fifo(i).pending(1);
end loop;
tm_fifo := ar.atp_trans.tm_fifo;
accbufindex := 0;
-- Not used
if tm_acc_done = '1' then
pv.pta_trans.tm_acc_done_ack := atp_trans.tm_acc_done.done;
end if;
-- --------------------------------------------------------------------------------
-- PCI target core
-- --------------------------------------------------------------------------------
if target /= 0 then -- PCI target enabled
-- Target latency counter
if pv.t.state = pt_s_data and pr.po.trdy = '1' and pr.t.lcount /= "111" then
pv.t.lcount := pr.t.lcount + 1;
elsif pr.po.trdy = '0' then
pv.t.lcount := (others => '0');
end if;
-- select next fifo
if pr.t.cur_acc(0).read = '1' then
if pr.t.atp.index /= FIFO_COUNT-1 then t_index := (pr.t.atp.index + 1);
else t_index := 0; end if;
else
if pr.t.pta.index /= FIFO_COUNT-1 then t_index := (pr.t.pta.index + 1);
else t_index := 0; end if;
end if;
-- PCI BAR address matching
t_bar := (others => '0'); t_func := 0;
for j in 0 to multifunc loop
for i in 0 to 5 loop
if (pi.ad(31 downto barminsize) and pr.conf(j).bar_mask(i)(31 downto barminsize)) =
(pr.conf(j).bar(i)(31 downto barminsize) and pr.conf(j).bar_mask(i)(31 downto barminsize)) and
pr.conf(j).bar_mask(i)(31) = '1' then
if pr.conf(j).bar_mask(i)(0) = '0' and (pi.cbe = MEM_READ or pi.cbe = MEM_R_MULT or pi.cbe = MEM_R_LINE
or pi.cbe = MEM_WRITE or pi.cbe = MEM_W_INV) then
t_hit := pr.conf(j).comm.memen; -- Only hit if memory access is enabled
t_bar(i) := '1';
t_func := j;
elsif pr.conf(j).bar_mask(i)(0) = '1' and (pi.cbe = IO_READ or pi.cbe = IO_WRITE) then
t_hit := pr.conf(j).comm.ioen; -- Only hit if io access is enabled
t_bar(i) := '1';
t_func := j;
end if;
end if;
end loop;
end loop;
-- Configuration hit when IDSEL or self config (AD[31:11]=0 => no IDSEL) and in host slot
if ((pi.idsel = '1' or (pi.ad(31 downto 11) = zero32(31 downto 11) and pi.host = '0')) -- IDSEL asserted
and (pi.cbe = CONF_READ or pi.cbe = CONF_WRITE)) and pi.ad(1 downto 0) = "00" -- Command = config read or write, Type = 0
and pi.ad(10 downto 8) <= conv_std_logic_vector(multifunc, 3) then -- Respond to implemented function
t_chit := '1';
end if;
-- Read prefetch discard timer
if atp_trans.pa_discardtout_rst = '1' then
pv.pta_trans.pa_discardtout := '0';
end if;
if pr.t.cur_acc(0).pending = '1' and pr.t.discardtimeren = '1' then
if pr.t.discardtimer = x"0000" then
if pr.t.state = pt_idle then
pv.pta_trans.pa_discardtout := '1';
pv.t.cur_acc(0).pending := '0';
pv.t.cur_acc(0).newacc := '1';
pv.t.cur_acc(0).oldburst := pr.t.cur_acc(0).burst;
end if;
else
pv.t.discardtimer := pr.t.discardtimer - 1;
end if;
end if;
-- Access buffer
if tm_acc_pending = '0' and pr.t.accbuf(0).pending = '1' then
pv.pta_trans.tm_acc := pr.t.accbuf(0);
pv.pta_trans.tm_acc.pending := not pr.pta_trans.tm_acc.pending;
pv.t.accbuf(0) := pr.t.accbuf(1);
pv.t.accbuf(1) := pr.t.accbuf(2);
pv.t.accbuf(2) := pr.t.accbuf(3);
pv.t.accbuf(3).pending := '0';
end if;
pv.pciinten := (others => oeoff);
for i in 0 to 3 loop
if i <= multifunc then
pv.conf(i).stat.intsta := conv_std_logic(pciinten(i) /= oeoff);
if pr.conf(i).comm.intdis = '0' then
pv.pciinten(i) := pciinten(i);
end if;
else
pv.conf(0).stat.intsta := conv_std_logic(pciinten(i) /= oeoff);
if pr.conf(0).comm.intdis = '0' then
pv.pciinten(i) := pciinten(i);
end if;
end if;
end loop;
if multiint = 0 then
if oeoff = '1' then
pciinten_pad(0) <= andv(pr.pciinten);
else
pciinten_pad(0) <= orv(pr.pciinten);
end if;
pciinten_pad(3 downto 1) <= (others => oeoff);
else
pciinten_pad <= pr.pciinten;
end if;
-- PCI Configuration Space Header
conf_func := 0;
if conv_integer(pr.t.cur_acc(0).addr(10 downto 8)) <= multifunc then
conf_func := conv_integer(pr.t.cur_acc(0).addr(10 downto 8));
end if;
-- read
if pr.t.cur_acc(0).impcfgreg = '1' then
if pr.t.cur_acc(0).acc_type(0) = '0' then
case pr.t.conf_addr is
when "0000" => -- Device and Vendor ID
t_cad := conv_std_logic_vector(deviceid_vector(conf_func),16) & conv_std_logic_vector(vendorid,16);
when "0001" => -- Status and Command
t_cad := pr.conf(conf_func).stat.dpe & pr.conf(conf_func).stat.sse & pr.conf(conf_func).stat.rma & pr.conf(conf_func).stat.rta &
pr.conf(conf_func).stat.sta & "01" & pr.conf(conf_func).stat.mdpe & "00"& pr.pci66(1) &
"1"& pr.conf(conf_func).stat.intsta &"000" &
"00000" & pr.conf(conf_func).comm.intdis & "0" & pr.conf(conf_func).comm.serren & "0" & pr.conf(conf_func).comm.perren & "0" &
pr.conf(conf_func).comm.mwien & "0" & pr.conf(conf_func).comm.msten & pr.conf(conf_func).comm.memen & pr.conf(conf_func).comm.ioen;
when "0010" => -- Class Code and Revision ID
t_cad := conv_std_logic_vector(classcode_vector(conf_func),24) & conv_std_logic_vector(revisionid_vector(conf_func),8);
when "0011" => -- BIST, Header Type, Latency Timer and Cache Line Size
t_cad := "00000000" & conv_std_logic(multifunc /= 0) & "0000000" & pr.conf(conf_func).ltimer & "00000000";
when "0100" => -- BAR0
t_cad := pr.conf(conf_func).bar(0);
--t_cad(3) := bar_prefetch(0);
t_cad(3) := pr.conf(conf_func).bar_mask(0)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(0)(0);
when "0101" => -- BAR1
t_cad := pr.conf(conf_func).bar(1);
--t_cad(3) := bar_prefetch(1);
t_cad(3) := pr.conf(conf_func).bar_mask(1)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(1)(0);
when "0110" => -- BAR2
t_cad := pr.conf(conf_func).bar(2);
--t_cad(3) := bar_prefetch(2);
t_cad(3) := pr.conf(conf_func).bar_mask(2)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(2)(0);
when "0111" => -- BAR3
t_cad := pr.conf(conf_func).bar(3);
--t_cad(3) := bar_prefetch(3);
t_cad(3) := pr.conf(conf_func).bar_mask(3)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(3)(0);
when "1000" => -- BAR4
t_cad := pr.conf(conf_func).bar(4);
--t_cad(3) := bar_prefetch(4);
t_cad(3) := pr.conf(conf_func).bar_mask(4)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(4)(0);
when "1001" => -- BAR5
t_cad := pr.conf(conf_func).bar(5);
--t_cad(3) := bar_prefetch(5);
t_cad(3) := pr.conf(conf_func).bar_mask(5)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(5)(0);
when "1010" => -- Cardbus CIS Pointer
t_cad := (others => '0');
when "1011" => -- Subsystem ID and Subsystem Vendor ID
t_cad := (others => '0');
when "1100" => -- Expansion ROM Base Address
t_cad := (others => '0');
when "1101" => -- Reserved and Capabillities Pointer
t_cad := (others => '0');
t_cad(7 downto 0) := conv_std_logic_vector(cap_pointer_vector(conf_func), 8);
when "1110" => -- Reserved
t_cad := (others => '0');
when "1111" => -- Max_Lat, Min_Gnt, Interrupt Pin and Interrupt Line
t_cad := x"00" & x"00" & (x"0"&"0"&conv_std_logic_vector(deviceirq_vector(conf_func), 3)) & pr.conf(conf_func).iline;
when others =>
t_cad := (others => '0');
end case;
else -- Mapping register
case pr.t.conf_addr is
when "0000" =>
t_cad := x"0040" & conv_std_logic_vector(ext_cap_pointer_vector(conf_func), 8) & x"09";
when "0001" =>
t_cad := pr.conf(conf_func).pta_map(0);
when "0010" =>
t_cad := pr.conf(conf_func).pta_map(1);
when "0011" =>
t_cad := pr.conf(conf_func).pta_map(2);
when "0100" =>
t_cad := pr.conf(conf_func).pta_map(3);
when "0101" =>
t_cad := pr.conf(conf_func).pta_map(4);
when "0110" =>
t_cad := pr.conf(conf_func).pta_map(5);
when "0111" =>
t_cad := pr.conf(conf_func).cfg_map;
when "1000" =>
t_cad := conv_std_logic_vector(iobase, 12) & x"0000"&"00"&pr.t.discardtimeren&pr.pta_trans.ca_twist; -- AHB IO base address (used to find P&P information) and byte twisting
when "1001" =>
t_cad := pr.conf(conf_func).bar_mask(0);
when "1010" =>
t_cad := pr.conf(conf_func).bar_mask(1);
when "1011" =>
t_cad := pr.conf(conf_func).bar_mask(2);
when "1100" =>
t_cad := pr.conf(conf_func).bar_mask(3);
when "1101" =>
t_cad := pr.conf(conf_func).bar_mask(4);
when "1110" =>
t_cad := pr.conf(conf_func).bar_mask(5);
when "1111" =>
t_cad := pr.t.saverfifo & "000" & x"000" & pr.t.blenmask; -- Burst lenght boundary mask
when others =>
t_cad := (others => '0');
end case;
end if;
end if;
-- write
if (pi.irdy or pi.trdy) = '0' and pr.t.cur_acc(0).acc_type(1) = '1' and pr.t.cur_acc(0).impcfgreg = '1' and
pr.t.cur_acc(0).read = '0' and pr.t.fstate = ptf_cwrite then
-- Support for all CBE combinations
if pi.cbe(3) = '0' then t_cad(31 downto 24) := pi.ad(31 downto 24); end if;
if pi.cbe(2) = '0' then t_cad(23 downto 16) := pi.ad(23 downto 16); end if;
if pi.cbe(1) = '0' then t_cad(15 downto 8) := pi.ad(15 downto 8); end if;
if pi.cbe(0) = '0' then t_cad( 7 downto 0) := pi.ad( 7 downto 0); end if;
if pr.t.cur_acc(0).acc_type(0) = '0'then
case pr.t.conf_addr is
--when "0000" => -- Device and Vendor ID
when "0001" => -- Status and Command
-- Command register
pv.conf(conf_func).comm.ioen := t_cad(0);
pv.conf(conf_func).comm.memen := t_cad(1);
if MASTER = 1 then
pv.conf(conf_func).comm.msten := t_cad(2);
pv.pta_trans.ca_pcimsten(conf_func) := pv.conf(conf_func).comm.msten;
end if;
pv.conf(conf_func).comm.mwien := t_cad(4);
pv.conf(conf_func).comm.perren := t_cad(6);
pv.conf(conf_func).comm.serren := t_cad(8);
pv.conf(conf_func).comm.intdis := t_cad(10);
-- Status register, sticky bits
pv.conf(conf_func).stat.mdpe := pr.conf(conf_func).stat.mdpe and not t_cad(24);
pv.conf(conf_func).stat.sta := pr.conf(conf_func).stat.sta and not t_cad(27);
pv.conf(conf_func).stat.rta := pr.conf(conf_func).stat.rta and not t_cad(28);
pv.conf(conf_func).stat.rma := pr.conf(conf_func).stat.rma and not t_cad(29);
pv.conf(conf_func).stat.sse := pr.conf(conf_func).stat.sse and not t_cad(30);
pv.conf(conf_func).stat.dpe := pr.conf(conf_func).stat.dpe and not t_cad(31);
--when "0010" => -- Class Code and Revision ID
when "0011" => -- BIST, Header Type, Latency Timer and Cache Line Size
pv.conf(conf_func).ltimer := t_cad(15 downto 8);
when "0100" => -- BAR0
if bar_size(conf_func)(0) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(0);
pv.conf(conf_func).bar(0)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0101" => -- BAR1
if bar_size(conf_func)(1) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(1);
pv.conf(conf_func).bar(1)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0110" => -- BAR2
if bar_size(conf_func)(2) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(2);
pv.conf(conf_func).bar(2)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0111" => -- BAR3
if bar_size(conf_func)(3) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(3);
pv.conf(conf_func).bar(3)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "1000" => -- BAR4
if bar_size(conf_func)(4) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(4);
pv.conf(conf_func).bar(4)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "1001" => -- BAR5
if bar_size(conf_func)(5) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(5);
pv.conf(conf_func).bar(5)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
--when "1010" => -- Cardbus CIS Pointer
--when "1011" => -- Subsystem ID and Subsystem Vendor ID
--when "1100" => -- Expansion ROM Base Address
--when "1101" => -- Reserved and Capabillities Pointer
--when "1110" => -- Reserved
when "1111" => -- Max_Lat, Min_Gnt, Interrupt Pin and Interrupt Line
pv.conf(conf_func).iline := t_cad(7 downto 0);
when others =>
end case;
else -- Mapping registers
case pr.t.conf_addr is
when "0001" =>
if bar_size(conf_func)(0) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(0);
pv.conf(conf_func).pta_map(0)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0010" =>
if bar_size(conf_func)(1) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(1);
pv.conf(conf_func).pta_map(1)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0011" =>
if bar_size(conf_func)(2) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(2);
pv.conf(conf_func).pta_map(2)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0100" =>
if bar_size(conf_func)(3) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(3);
pv.conf(conf_func).pta_map(3)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0101" =>
if bar_size(conf_func)(4) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(4);
pv.conf(conf_func).pta_map(4)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0110" =>
if bar_size(conf_func)(5) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(5);
pv.conf(conf_func).pta_map(5)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0111" =>
pv.conf(conf_func).cfg_map(31 downto 8) := t_cad(31 downto 8);
when "1000" =>
pv.t.discardtimeren := t_cad(1);
pv.pta_trans.ca_twist := t_cad(0);
when "1001" =>
if bar_size(conf_func)(0) /= 0 then
pv.conf(conf_func).bar_mask(0)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(0)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(0)(0) := t_cad(0);
end if;
when "1010" =>
if bar_size(conf_func)(1) /= 0 then
pv.conf(conf_func).bar_mask(1)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(1)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(1)(0) := t_cad(0);
end if;
when "1011" =>
if bar_size(conf_func)(2) /= 0 then
pv.conf(conf_func).bar_mask(2)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(2)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(2)(0) := t_cad(0);
end if;
when "1100" =>
if bar_size(conf_func)(3) /= 0 then
pv.conf(conf_func).bar_mask(3)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(3)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(3)(0) := t_cad(0);
end if;
when "1101" =>
if bar_size(conf_func)(4) /= 0 then
pv.conf(conf_func).bar_mask(4)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(4)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(4)(0) := t_cad(0);
end if;
when "1110" =>
if bar_size(conf_func)(5) /= 0 then
pv.conf(conf_func).bar_mask(5)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(5)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(5)(0) := t_cad(0);
end if;
when "1111" =>
pv.t.blenmask(blenmask_size(barminsize) downto FIFO_DEPTH) := t_cad(blenmask_size(barminsize) downto FIFO_DEPTH);
pv.t.saverfifo := t_cad(31);
when others =>
end case;
end if;
end if;
-- FIFO State machine
case pr.t.fstate is
when ptf_idle =>
pv.t.first := (others => '1');
pv.t.preload := '0';
pv.t.preload_count := (others => '0');
pv.t.diswithout := '0';
if pr.t.cur_acc(0).pending = '1' then
if pr.t.cur_acc(0).read = '1' then -- Memory and Config read
pv.t.fstate := ptf_fifo;
pv.t.atp.ctrl.addr := conv_std_logic_vector(pr.t.atp.index, log2(FIFO_COUNT)) & pr.t.cur_acc(0).addr(FIFO_DEPTH+1 downto 2);
else
if pr.t.cur_acc(0).acc_type(1) = '1' then -- Config write
pv.t.fstate := ptf_cwrite;
pv.t.conf_addr := pr.t.cur_acc(0).addr(5 downto 2);
t_ready := '1';
elsif tm_fifo_empty(pr.t.pta.index) = '1' then -- Memory write
-- Burst length (only burst up to this boundary)
pv.t.blen := ((not pr.t.cur_acc(0).addr(17 downto 2)) and pr.t.blenmask);
pv.t.fstate := ptf_write;
t_ready := '1';
pv.t.pta.ctrl.addr := conv_std_logic_vector(pr.t.pta.index, log2(FIFO_COUNT)) & pr.t.cur_acc(0).addr(FIFO_DEPTH+1 downto 2);
if pr.t.cur_acc(0).acc_type(0) = '0' then -- memory access
pv.t.addr := set_pta_addr(pr.t.cur_acc(0).addr, pr.conf(pr.t.cur_acc(0).func).pta_map, pr.t.cur_acc(0).bar, pr.conf(pr.t.cur_acc(0).func).bar_mask, barminsize);
else
pv.t.addr := pr.conf(conf_func).cfg_map(31 downto 8) & pr.t.cur_acc(0).addr(7 downto 0);
end if;
else
t_retry := '1';
pv.t.fstate := ptf_idle;
pv.t.cur_acc(0).pending := '0';
end if;
end if;
if pr.t.cur_acc(0).acc_type(1) = '0' and -- Access to AHB
( (pr.t.cur_acc(0).read = '1') -- Read
or (pr.t.cur_acc(0).read = '0' and tm_fifo_empty(pr.t.pta.index) = '1')) then -- Write
if tm_acc_pending = '0' and pr.t.accbuf(0).pending = '0' then
pv.pta_trans.tm_acc.pending := not pr.pta_trans.tm_acc.pending;
if pr.t.cur_acc(0).acc_type(0) = '0' then -- memory access
pv.pta_trans.tm_acc.addr := set_pta_addr(pr.t.cur_acc(0).addr, pr.conf(pr.t.cur_acc(0).func).pta_map, pr.t.cur_acc(0).bar, pr.conf(pr.t.cur_acc(0).func).bar_mask, barminsize);
else
pv.pta_trans.tm_acc.addr := pr.conf(conf_func).cfg_map(31 downto 8) & pr.t.cur_acc(0).addr(7 downto 0);
end if;
pv.pta_trans.tm_acc.acctype := "000" & not pr.t.cur_acc(0).read; -- acctype(0) = write
pv.pta_trans.tm_acc.accmode := "00" & pr.t.cur_acc(0).burst;
pv.pta_trans.tm_acc.size := (others => '0'); -- not used
pv.pta_trans.tm_acc.offset := (others => '0'); -- not used
if pr.t.cur_acc(0).read = '1' then pv.pta_trans.tm_acc.index := pr.t.atp.index;
else pv.pta_trans.tm_acc.index := pr.t.pta.index; end if;
pv.pta_trans.tm_acc.length := ((not pr.t.cur_acc(0).addr(17 downto 2)) and pr.t.blenmask);
pv.pta_trans.tm_acc.cbe := pi.cbe;
pv.pta_trans.tm_acc.endianess := pr.pta_trans.ca_twist;
else
accbufindex := 0;
for i in 3 downto 0 loop
if pv.t.accbuf(i).pending = '0' then accbufindex := i; end if;
end loop;
pv.t.accbuf(accbufindex).pending := '1';
if pr.t.cur_acc(0).acc_type(0) = '0' then -- memory access
pv.t.accbuf(accbufindex).addr := set_pta_addr(pr.t.cur_acc(0).addr, pr.conf(pr.t.cur_acc(0).func).pta_map, pr.t.cur_acc(0).bar, pr.conf(pr.t.cur_acc(0).func).bar_mask, barminsize);
else
pv.t.accbuf(accbufindex).addr := pr.conf(conf_func).cfg_map(31 downto 8) & pr.t.cur_acc(0).addr(7 downto 0);
end if;
pv.t.accbuf(accbufindex).acctype := "000" & not pr.t.cur_acc(0).read; -- acctype(0) = write
pv.t.accbuf(accbufindex).accmode := "00" & pr.t.cur_acc(0).burst;
pv.t.accbuf(accbufindex).size := (others => '0'); -- not used
pv.t.accbuf(accbufindex).offset := (others => '0'); -- not used
if pr.t.cur_acc(0).read = '1' then pv.t.accbuf(accbufindex).index := pr.t.atp.index;
else pv.t.accbuf(accbufindex).index := pr.t.pta.index; end if;
pv.t.accbuf(accbufindex).length := ((not pr.t.cur_acc(0).addr(17 downto 2)) and pr.t.blenmask);
pv.t.accbuf(accbufindex).cbe := pi.cbe;
pv.t.accbuf(accbufindex).endianess := pr.pta_trans.ca_twist;
end if;
end if;
end if;
when ptf_fifo =>
pv.t.atp.ctrl.en := tm_fifo_pending(pr.t.atp.index);
if (pr.t.hold(0) = '0' or pr.t.first_word = '1') and pr.t.cfifo(0).valid = '1' then
t_ready := '1';
end if;
if pr.t.cur_acc(0).newacc = '1' or
(tm_acc_cancel = '1' and pr.t.cur_acc(0).acc_type(1) = '0') or
pr.t.cur_acc(0).read = '0' then
t_ready := '0';
end if;
if (tm_acc_cancel = '0' and tm_fifo_pending(pr.t.atp.index) = '1') or pr.t.preload = '1' or pr.t.cur_acc(0).acc_type(1) = '1' then -- FIFO pending or Config access
pv.t.preload := '1';
if pr.t.preload = '0' then pv.t.hold_fifo := '0'; end if;
end if;
if ((pi.trdy or pi.irdy) = '0' and pr.t.state = pt_s_data) or pr.t.preload = '1' then
if (pi.trdy or pi.irdy) = '0' and pr.t.state = pt_s_data then
pv.t.cfifo(0) := pr.t.cfifo(1); pv.t.cfifo(1) := pr.t.cfifo(2); -- Preload target core fifo
pv.t.cur_acc(0).addr := pr.t.cur_acc(0).addr + 4;
elsif pr.t.preload = '1' then
if pr.t.cfifo(0).valid = '0' then
pv.t.cfifo(0) := pr.t.cfifo(1); pv.t.cfifo(1) := pr.t.cfifo(2); -- Preload target core fifo
elsif pr.t.cfifo(0).valid = '1' and pr.t.cfifo(1).valid = '0' then
pv.t.cfifo(1) := pr.t.cfifo(2); -- Preload target core fifo
end if;
end if;
if pr.t.cur_acc(0).acc_type(1) = '0' then -- Memory access
pv.t.cfifo(2).data := byte_twist(tm_fifoo_atp.data, pr.pta_trans.ca_twist); -- shifting in data from backend fifo
else
pv.t.cfifo(2).data := t_cad; -- Configuration access
end if;
if pr.t.cur_acc(0).acc_type(1) = '0' then -- Memory access
if tm_fifo_pending(pr.t.atp.index) = '1' then
if pr.t.atp.ctrl.addr(FIFO_DEPTH-1 downto 0) = tm_fifo(pr.t.atp.index).stop and pr.t.hold_fifo = '0' then -- Mark last word
pv.t.atp.index := t_index;
pv.t.atp.ctrl.addr := conv_std_logic_vector(pv.t.atp.index, log2(FIFO_COUNT)) & zero32(FIFO_DEPTH-1 downto 0); -- Reset backend fifo address
pv.pta_trans.tm_fifo_ack(pr.t.atp.index) := tm_fifo(pr.t.atp.index).pending(RAM_LATENCY); -- Ack the fifo (done using this data)
if tm_fifo_pending(t_index) = '1' then
pv.t.cfifo(2).hold := '0';
else
pv.t.cfifo(2).hold := '1';
pv.t.hold_fifo := '1';
-- Disconnect on last fifo
if tm_fifo(pr.t.atp.index).lastf = '1' then pv.t.cfifo(2).stlast := '1'; end if;
-- Disable fifo read
pv.t.atp.ctrl.en := '0';
end if;
else
pv.t.cfifo(2).hold := '0';
if pr.t.hold_fifo = '0' then
pv.t.atp.ctrl.addr := conv_std_logic_vector(pv.t.atp.index, log2(FIFO_COUNT)) & pr.t.atp.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1; -- inc backend fifo address
end if;
end if;
if pr.t.atp.ctrl.addr(FIFO_DEPTH-1 downto 0) = tm_fifo(pr.t.atp.index).stop and tm_fifo(pr.t.atp.index).status /= "0000" then
pv.t.cfifo(2).err := '1';
else
pv.t.cfifo(2).err := '0';
end if;
end if;
else -- Configuration access
if pr.t.conf_addr = "1110" then
pv.t.cfifo(2).stlast := '1';
else
pv.t.cfifo(2).stlast := '0';
end if;
if pr.t.conf_addr = "1111" then
pv.t.cfifo(2).hold := '1';
if pr.t.preload_count = "00" then pv.t.cfifo(2).stlast := '1'; end if;
else
pv.t.cfifo(2).hold := '0';
pv.t.conf_addr := pr.t.conf_addr + 1; -- inc backend fifo address
end if;
pv.t.cfifo(2).err := '0';
end if;
if (tm_fifo_pending(pr.t.atp.index) = '1' or pr.t.cur_acc(0).acc_type(1) = '1') and pr.t.hold_fifo = '0' then
pv.t.cfifo(2).valid := '1';
else
pv.t.cfifo(2).valid := '0';
end if;
end if;
if (pv.t.cfifo(0).valid = '1' and pv.t.cfifo(1).valid = '1' and pv.t.cfifo(2).valid = '1')
or (pv.t.cfifo(0).valid = '1' and pr.t.cfifo(0).valid = '0')
or (pv.t.cfifo(0).valid = '1' and pr.t.cfifo(0).hold = '1' and pv.t.cfifo(1).valid = '1') then
pv.t.preload := '0';
if pr.t.preload = '1' or (pr.t.hold_fifo = '1' and pv.t.hold_fifo = '0') then
pv.t.hold_reset := '0';
if pr.t.cfifo(0).hold = '1' and pv.t.cfifo(1).valid = '1' then pv.t.cfifo(0).hold := '0'; end if;
if pr.t.cfifo(1).hold = '1' and pv.t.cfifo(2).valid = '1' then pv.t.cfifo(1).hold := '0'; end if;
if pr.t.cfifo(2).hold = '1' and tm_fifo_pending(pr.t.atp.index) = '1' then pv.t.cfifo(2).hold := '0'; end if;
end if;
end if;
if (pr.t.state = pt_turn_ar and pr.t.cur_acc(0).pending = '0' and pr.t.cur_acc(0).continue = '0')
or (pr.t.cur_acc(0).newacc = '1')
or ((pr.t.abort = '1' or pr.t.diswithout = '1') and (pr.t.state = pt_backoff or pr.t.state = pt_turn_ar))
then
if pr.t.cur_acc(0).burst = '1' and pr.t.abort = '0' then
if pr.t.cur_acc(0).acc_type(1) = '0' or pr.t.cur_acc(0).read = '0' or pr.t.cur_acc(0).pending = '0' then
pv.t.fstate := ptf_idle;
end if;
else
pv.t.fstate := ptf_idle;
if pr.t.abort = '1' then pv.t.cur_acc(0).pending := '0'; end if;
if pr.t.cur_acc(0).burst = '1' then pv.pta_trans.tm_acc_cancel := not pr.pta_trans.tm_acc_cancel; end if;
end if;
pv.t.hold_reset := '0';
for i in 0 to 2 loop
pv.t.cfifo(i).valid := '0';
pv.t.cfifo(i).hold := '0';
pv.t.cfifo(i).stlast := '0';
pv.t.cfifo(i).last := '0';
pv.t.cfifo(i).err := '0';
end loop;
if (pr.t.cur_acc(0).pending = '0' and pr.t.cur_acc(0).acc_type(1) = '0' and pr.t.cur_acc(0).burst = '1') or
(pr.t.cur_acc(0).newacc = '1' and pr.t.cur_acc(0).oldburst = '1') then
pv.pta_trans.tm_acc_cancel := not pr.pta_trans.tm_acc_cancel;
end if;
end if;
when ptf_cwrite =>
if pr.t.hold(0) = '0' then -- can maybe be optimized
t_ready := '1';
end if;
if pr.t.state = pt_turn_ar then
pv.t.fstate := ptf_idle;
pv.t.hold_reset := '0';
end if;
if (pi.trdy or pi.irdy) = '0' then
if pr.t.conf_addr /= "1111" then -- Config access
pv.t.conf_addr := pr.t.conf_addr + 1; -- inc backend fifo address
end if;
end if;
when ptf_write =>
if pr.t.hold(0) = '0' then -- can maybe be optimized
t_ready := '1';
elsif tm_fifo_empty(pr.t.pta.index) = '1' and pr.t.hold_write = '0' then
t_ready := '1';
pv.t.hold_reset := '0';
end if;
if (pr.t.addr(AHB_FIFO_BITS) = ones32(FIFO_DEPTH-1 downto 0) and pr.t.first(0) = '1' and
(tm_fifo_empty(t_index) = '0' or pr.t.blen = x"0000")) or
((pi.trdy or pi.irdy) = '0' and pr.t.blen = x"0001") or
pr.t.cur_acc(0).burst = '0' then
pv.t.diswithout := '1';
end if;
if pr.t.state = pt_turn_ar then
pv.t.fstate := ptf_idle;
pv.t.hold_reset := '0';
end if;
if (pi.trdy or pi.irdy) = '0' then
pv.t.pta.ctrl.en := '1';
pv.t.pta.ctrl.addr := conv_std_logic_vector(pr.t.pta.index, log2(FIFO_COUNT)) & pr.t.addr(AHB_FIFO_BITS);
if pi.cbe /= ones32(3 downto 0) or pr.t.first(0) = '1' then
pv.t.first(0) := '0';
pv.pta_trans.tm_fifo(pr.t.pta.index).stop := pr.t.addr(AHB_FIFO_BITS);
pv.pta_trans.tm_fifo(pr.t.pta.index).last_cbe := pi.cbe;
end if;
if pr.t.first(0) = '1' then -- First data in this fifo
pv.pta_trans.tm_fifo(pr.t.pta.index).start := pr.t.addr(AHB_FIFO_BITS);
end if;
pv.t.addr := pr.t.addr + 4; -- inc backend fifo address
if pr.t.blen /= zero32(15 downto 0) then
pv.t.blen := pr.t.blen - 1;
end if;
if pr.t.addr(AHB_FIFO_BITS) /= ones32(FIFO_DEPTH-1 downto 0) and pi.frame = '0' and pr.t.diswithout = '0' and pi.stop = '1' then
if pr.t.addr(AHB_FIFO_BITS) = conv_std_logic_vector((conv_integer(ones32(FIFO_DEPTH-1 downto 0)) - 1), FIFO_DEPTH) then
if tm_fifo_empty(t_index) = '0' then
pv.t.hold_write := '1';
t_ready := '0';
pv.t.diswithout := '1';
end if;
end if;
else
pv.t.first(0) := '1';
pv.t.first(1) := '0';
pv.t.hold_write := '0';
pv.t.pta.index := t_index;
pv.pta_trans.tm_fifo(pr.t.pta.index).pending(0) := not pr.pta_trans.tm_fifo(pr.t.pta.index).pending(0);
pv.pta_trans.tm_fifo(pr.t.pta.index).status := (others => '0');
if pr.t.first(1) = '1' then pv.pta_trans.tm_fifo(pr.t.pta.index).firstf := '1';
else pv.pta_trans.tm_fifo(pr.t.pta.index).firstf := '0'; end if;
if pi.frame = '1' or pr.t.diswithout = '1' then pv.pta_trans.tm_fifo(pr.t.pta.index).lastf := '1'; -- Mark last fifo
else pv.pta_trans.tm_fifo(pr.t.pta.index).lastf := '0'; end if;
end if;
end if;
when others =>
end case;
-- PCI State machine
case pr.t.state is
when pt_idle => -- The bus is in idle state
pv.t.hold_write := '0';
pv.t.lcount := (others => '0'); -- reset latency counter
pv.t.stoped := '0';
pv.t.retry := '0';
if pi.frame = '0' then
if t_hit = '1' or t_chit = '1' then
pv.t.state := pt_s_data;
pv.t.first_word := '1';
case pi.cbe is
when CONF_READ =>
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "10";
pv.t.conf_addr := pi.ad(5 downto 2);
if pi.ad(7 downto 4) >= "0100" then
if ext_cap_pointer_vector(conf_func) /= 16#00# then
t_acc_type := "01";
else
t_acc_impcfgreg := '0';
end if;
if pi.ad(7 downto 4) >= conv_std_logic_vector(cap_pointer, 8)(7 downto 4)
and pi.ad(7 downto 4) < conv_std_logic_vector(cap_pointer + 16#40#, 8)(7 downto 4) then
t_acc_type := "11";
t_acc_impcfgreg := '1';
end if;
end if;
when CONF_WRITE =>
t_acc_read := '0';
t_acc_burst := '1';
t_acc_type := "10";
pv.t.conf_addr := pi.ad(5 downto 2);
if pi.ad(7 downto 4) >= "0100" then
if ext_cap_pointer_vector(conf_func) /= 16#00# then
t_acc_type := "01";
else
t_acc_impcfgreg := '0';
end if;
if pi.ad(7 downto 4) >= conv_std_logic_vector(cap_pointer, 8)(7 downto 4)
and pi.ad(7 downto 4) < conv_std_logic_vector(cap_pointer + 16#40#, 8)(7 downto 4) then
t_acc_type := "11";
t_acc_impcfgreg := '1';
end if;
end if;
when MEM_READ =>
t_acc_read := '1';
t_acc_burst := '0';
t_acc_type := "00";
when MEM_WRITE | MEM_W_INV =>
t_acc_read := '0';
-- Burst ordering: Linear Incrementing
if pi.ad(1 downto 0) = "00" then t_acc_burst := '1';
else t_acc_burst := '0'; end if;
t_acc_type := "00";
when IO_READ =>
t_acc_read := '1';
t_acc_burst := '0';
t_acc_type := "00";
when IO_WRITE =>
t_acc_read := '0';
t_acc_burst := '0';
t_acc_type := "00";
when MEM_R_MULT | MEM_R_LINE =>
t_acc_read := '1';
-- Burst ordering: Linear Incrementing
if pi.ad(1 downto 0) = "00" then t_acc_burst := '1';
else t_acc_burst := '0'; end if;
t_acc_type := "00";
when others =>
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "00";
end case;
if (pr.t.cur_acc(0).pending = '1' or pr.t.cur_acc(0).continue = '1') and pr.t.cur_acc(0).addr = pi.ad
and t_acc_read = '1' and pr.t.cur_acc(0).acc_type(1) = '0' then
pv.t.cur_acc(0).match := '1';
pv.t.cur_acc(0).pending := '1';
pv.t.discardtimer := (others => '1');
elsif pr.t.cur_acc(0).pending = '0' then -- Save new access
pv.t.cur_acc(0).addr := pi.ad;
pv.t.cur_acc(0).pending := '1';
pv.t.cur_acc(0).retry := '0';
pv.t.cur_acc(0).read := t_acc_read;
pv.t.cur_acc(0).burst := t_acc_burst;
pv.t.cur_acc(0).acc_type := t_acc_type;
pv.t.cur_acc(0).impcfgreg := t_acc_impcfgreg;
pv.t.cur_acc(0).bar := t_bar;
pv.t.cur_acc(0).func := t_func;
pv.t.cur_acc(0).match := '0';
pv.t.discardtimer := (others => '1');
if pr.t.cur_acc(0).continue = '1' then
pv.t.cur_acc(0).newacc := '1';
pv.t.cur_acc(0).oldburst := pr.t.cur_acc(0).burst;
end if;
else
pv.t.cur_acc(0).match := '0';
end if;
pv.t.cur_acc(0).continue := '0';
else
pv.t.state := pt_b_busy;
end if;
end if;
when pt_b_busy => -- Wait for the current transaction to complete and bus return
-- to idle sate
if (pi.frame and pi.irdy) = '1' then
pv.t.state := pt_idle;
end if;
when pt_s_data => -- Target is transfering data
if (pi.frame and not pi.irdy and ( not pi.trdy or not pi.stop)) = '1' then
pv.t.state := pt_turn_ar;
pv.t.retry := '0';
if pr.t.cur_acc(0).pending = '0' and pr.t.cur_acc(0).acc_type(1) = '0' and
pr.t.cur_acc(0).read = '1' and pi.trdy = '1' and pi.stop = '0' and pr.t.stop = '0' and
pr.t.cur_acc(0).burst = '1' and pr.t.discardtimer /= x"0000" then
if pr.t.saverfifo = '1' then -- FIFO is saved until next access (disconnect without data).
-- If the next access is not the read continuing, the prefetched data is discarded.
pv.t.cur_acc(0).continue := '1';
end if;
end if;
elsif (not pi.frame and not pi.stop) = '1' then
pv.t.state := pt_backoff;
pv.t.retry := '0';
if pr.t.cur_acc(0).pending = '0' and pr.t.cur_acc(0).acc_type(1) = '0' and
pr.t.cur_acc(0).read = '1' and pr.t.stop = '0' and pr.t.stop = '0' and
pr.t.cur_acc(0).burst = '1' and pr.t.discardtimer /= x"0000" then
if pr.t.saverfifo = '1' then -- FIFO is saved until next access (disconnect without data).
-- If the next access is not the read continuing, the prefetched data is discarded.
pv.t.cur_acc(0).continue := '1';
end if;
end if;
end if;
if (not pi.irdy and not pi.trdy) = '1' then pv.t.cur_acc(0).pending := '0'; end if; -- Data transfered, reset pending
-- can maybe be optimized
if ((pr.t.cfifo(0).valid = '0' or pr.t.cur_acc(0).match = '0') and
pr.t.cur_acc(0).pending = '1' and pr.t.cur_acc(0).acc_type(1) = '0' and pr.t.cur_acc(0).read = '1') or
pr.t.retry = '1' then t_retry := '1'; pv.t.retry := '1'; end if;
-- CFIFO valid again after FIFO switch (First word in continued access), to reassert trdy
if pr.t.fstate = ptf_fifo and pr.t.preload = '1' and pr.t.first_word = '0' and
pr.t.cfifo(0).valid = '0' and pr.t.cfifo(1).valid = '1' then
pv.t.first_word := '1';
end if;
-- When FIFO is saved until next access (disconnect without data)
-- the first_word signal needs to be set one extra cycle to be valid the cycle before
-- FIFO state-machine moves to FIFO write state
if pr.t.fstate = ptf_fifo and pr.t.first_word = '1' and
pr.t.cur_acc(0).pending = '1' and pr.t.cur_acc(0).newacc = '1' and
pr.t.cur_acc(0).read = '0' then
if pr.t.saverfifo = '1' then
pv.t.first_word := '1';
end if;
end if;
when pt_backoff => -- STOP# is asserted, waiting on deasserted FRAME#
if pi.frame = '1' then
pv.t.state := pt_turn_ar;
end if;
when pt_turn_ar => -- Deassert active signals before tri-state
-- from idle
pv.t.hold_write := '0';
pv.t.lcount := (others => '0'); -- reset latency counter
pv.t.stoped := '0';
pv.t.retry := '0';
if pi.frame = '1' then
pv.t.state := pt_idle;
elsif pi.frame = '0' then
if t_hit = '1' or t_chit = '1' then
pv.t.state := pt_s_data;
pv.t.first_word := '1';
case pi.cbe is
when CONF_READ =>
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "10";
pv.t.conf_addr := pi.ad(5 downto 2);
if pi.ad(7 downto 4) >= "0100" then
if ext_cap_pointer_vector(conf_func) /= 16#00# then
t_acc_type := "01";
else
t_acc_impcfgreg := '0';
end if;
if pi.ad(7 downto 4) >= conv_std_logic_vector(cap_pointer, 8)(7 downto 4)
and pi.ad(7 downto 4) < conv_std_logic_vector(cap_pointer + 16#40#, 8)(7 downto 4) then
t_acc_type := "11";
t_acc_impcfgreg := '1';
end if;
end if;
when CONF_WRITE =>
t_acc_read := '0';
t_acc_burst := '1';
t_acc_type := "10";
pv.t.conf_addr := pi.ad(5 downto 2);
if pi.ad(7 downto 4) >= "0100" then
if ext_cap_pointer_vector(conf_func) /= 16#00# then
t_acc_type := "01";
else
t_acc_impcfgreg := '0';
end if;
if pi.ad(7 downto 4) >= conv_std_logic_vector(cap_pointer, 8)(7 downto 4)
and pi.ad(7 downto 4) < conv_std_logic_vector(cap_pointer + 16#40#, 8)(7 downto 4) then
t_acc_type := "11";
t_acc_impcfgreg := '1';
end if;
end if;
when MEM_READ =>
t_acc_read := '1';
t_acc_burst := '0';
t_acc_type := "00";
when MEM_WRITE | MEM_W_INV =>
t_acc_read := '0';
-- Burst ordering: Linear Incrementing
if pi.ad(1 downto 0) = "00" then t_acc_burst := '1';
else t_acc_burst := '0'; end if;
t_acc_type := "00";
when IO_READ =>
t_acc_read := '1';
t_acc_burst := '0';
t_acc_type := "00";
when IO_WRITE =>
t_acc_read := '0';
t_acc_burst := '0';
t_acc_type := "00";
when MEM_R_MULT | MEM_R_LINE =>
t_acc_read := '1';
-- Burst ordering: Linear Incrementing
if pi.ad(1 downto 0) = "00" then t_acc_burst := '1';
else t_acc_burst := '0'; end if;
t_acc_type := "00";
when others =>
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "00";
end case;
if (pr.t.cur_acc(0).pending = '1' or pr.t.cur_acc(0).continue = '1') and pr.t.cur_acc(0).addr = pi.ad and t_acc_read = '1' and pr.t.cur_acc(0).acc_type(1) = '0' then
pv.t.cur_acc(0).match := '1';
pv.t.cur_acc(0).pending := '1';
pv.t.discardtimer := (others => '1');
elsif pr.t.cur_acc(0).pending = '0' then -- Save new access
pv.t.cur_acc(0).addr := pi.ad;
pv.t.cur_acc(0).pending := '1';
pv.t.cur_acc(0).retry := '0';
pv.t.cur_acc(0).read := t_acc_read;
pv.t.cur_acc(0).burst := t_acc_burst;
pv.t.cur_acc(0).acc_type := t_acc_type;
pv.t.cur_acc(0).impcfgreg := t_acc_impcfgreg;
pv.t.cur_acc(0).bar := t_bar;
pv.t.cur_acc(0).func := t_func;
pv.t.cur_acc(0).match := '0';
pv.t.discardtimer := (others => '1');
if pr.t.cur_acc(0).continue = '1' then
pv.t.cur_acc(0).newacc := '1';
pv.t.cur_acc(0).oldburst := pr.t.cur_acc(0).burst;
end if;
else
pv.t.cur_acc(0).match := '0';
end if;
pv.t.cur_acc(0).continue := '0';
else
pv.t.state := pt_b_busy;
end if;
end if;
when others =>
end case;
if pr.t.fstate = ptf_idle then pv.t.hold_reset := '0'; end if;
if pr.po.stop = '0' then pv.t.stoped := '1'; end if;
end if; -- PCI target enabled
-- --------------------------------------------------------------------------------
-- PCI trace
-- --------------------------------------------------------------------------------
-- sync
pv.pt_sync(1) := ar.atpt_trans; pv.pt_sync(2) := pr.pt_sync(1);
if nsync = 0 then atpt_trans := ar.atpt_trans;
else atpt_trans := pr.pt_sync(nsync); end if;
pt_setup := ar.atpt_trans;
pv.ptta_trans.start_ack := atpt_trans.start;
pv.ptta_trans.stop_ack := atpt_trans.stop;
pt_start := not pr.ptta_trans.start_ack and (pr.ptta_trans.start_ack xor atpt_trans.start);
pt_stop := not pr.ptta_trans.stop_ack and (pr.ptta_trans.stop_ack xor atpt_trans.stop);
if tracebuffer /= 0 then -- PCI trace buffer enabled
if pr.ptta_trans.enable = '1' then -- PCI tracing
pv.pt.addr := pr.pt.addr + 1;
if pr.ptta_trans.armed = '1' then -- Check for match
if ((((pi.ad & pcisig) xor (pt_setup.ad & pt_setup.sig)) and (pt_setup.admask & pt_setup.sigmask)) = z) then
if pr.pt.tcount = x"00" then
pv.ptta_trans.armed := '0'; -- Start saving trace
pv.ptta_trans.taddr := pr.pt.addr;
else pv.pt.tcount := pr.pt.tcount - 1; end if;
end if;
if pr.pt.addr = pr.ptta_trans.taddr then pv.ptta_trans.wrap := '1'; end if;
else
if pr.pt.count = zero32(PT_DEPTH-1 downto 0) then pv.ptta_trans.enable := '0'; -- Trace done
else pv.pt.count := pr.pt.count - 1; end if;
end if;
end if;
if pt_stop = '1' then -- Start PCI tracing
pv.ptta_trans.enable := '0';
if pr.ptta_trans.enable = '1' then
pv.ptta_trans.taddr := pr.pt.addr;
end if;
end if;
if pt_start = '1' then -- Start PCI tracing
pv.ptta_trans.enable := '1';
pv.ptta_trans.armed := '1';
pv.ptta_trans.wrap := '0';
pv.pt.count := pt_setup.count;
pv.pt.tcount := pt_setup.tcount;
end if;
--
pv.ptta_trans.dbg_ad := pi.ad;
pv.ptta_trans.dbg_sig := pcisig;
pv.ptta_trans.dbg_cur_ad := pr.t.cur_acc(0).addr;
pv.ptta_trans.dbg_cur_acc := pr.t.cur_acc(0).oldburst &
pr.t.cur_acc(0).acc_type &
pr.t.cur_acc(0).read &
pr.t.cur_acc(0).continue &
pr.t.cur_acc(0).burst &
pr.t.cur_acc(0).newacc &
pr.t.cur_acc(0).match &
pr.t.cur_acc(0).pending;
end if; -- PCI trace buffer enabled
-- --------------------------------------------------------------------------------
-- PCI debug
-- --------------------------------------------------------------------------------
--[31:30] ms_fifo_pending
--[29:28] ms_fifo_empty
--[37:36] tm_fifo_pending
--[25:24] tm_fifo_empty
--[ :23] ms_acc_pending;
--[ :22] ms_acc_cancel;
--[ :21] ms_acc_done;
--[ :20] md_acc_pending;
--[ :19] md_acc_cancel;
--[ :18] md_acc_done;
--[ :17] tm_acc_pending;
--[ :16] tm_acc_cancel;
--[ :15] tm_acc_done;
--[14:12] t.state
--[11: 8] t.fstate
--[ 7: 4] m.state
--[ 3: 0] m.fstate
pv.debug(31 downto 30) := ms_fifo_pending(1 downto 0);
pv.debug(29 downto 28) := ms_fifo_empty(1 downto 0);
pv.debug(27 downto 26) := tm_fifo_pending(1 downto 0);
pv.debug(25 downto 24) := tm_fifo_empty(1 downto 0);
pv.debug( 23) := ms_acc_pending;
pv.debug( 22) := ms_acc_cancel;
pv.debug( 21) := ms_acc_done;
pv.debug( 20) := md_acc_pending;
pv.debug( 19) := md_acc_cancel;
pv.debug( 18) := md_acc_done;
pv.debug( 17) := tm_acc_pending;
pv.debug( 16) := tm_acc_cancel;
pv.debug( 15) := tm_acc_done;
case pr.t.state is
when pt_idle => pv.debug(14 downto 12) := "000";
when pt_b_busy => pv.debug(14 downto 12) := "001";
when pt_s_data => pv.debug(14 downto 12) := "010";
when pt_backoff => pv.debug(14 downto 12) := "011";
when pt_turn_ar => pv.debug(14 downto 12) := "100";
when others => pv.debug(14 downto 12) := "111";
end case;
case pr.t.fstate is
when ptf_idle => pv.debug(11 downto 8) := "0000";
when ptf_fifo => pv.debug(11 downto 8) := "0001";
when ptf_cwrite => pv.debug(11 downto 8) := "0010";
when ptf_write => pv.debug(11 downto 8) := "0011";
when others => pv.debug(11 downto 8) := "1111";
end case;
case pr.m.state is
when pm_idle => pv.debug(7 downto 4) := "0000";
when pm_addr => pv.debug(7 downto 4) := "0001";
when pm_m_data => pv.debug(7 downto 4) := "0010";
when pm_turn_ar => pv.debug(7 downto 4) := "0011";
when pm_s_tar => pv.debug(7 downto 4) := "0100";
when pm_dr_bus => pv.debug(7 downto 4) := "0101";
when others => pv.debug(7 downto 4) := "1111";
end case;
case pr.m.fstate is
when pmf_idle => pv.debug(3 downto 0) := "0000";
when pmf_fifo => pv.debug(3 downto 0) := "0001";
when pmf_read => pv.debug(3 downto 0) := "0010";
when others => pv.debug(3 downto 0) := "1111";
end case;
debugo <= (others => '0');
-- --------------------------------------------------------------------------------
-- PCI reset
-- --------------------------------------------------------------------------------
-- PCI master
lpcim_rst <= pcirst(0) and not pci_master_rst and not pci_hard_rst;
if lpcim_rst = '0' then
-- state
pv.m.fstate := pmf_idle;
for i in 0 to 2 loop
pv.m.cfifo(i).last := '0';
pv.m.cfifo(i).stlast := '0';
pv.m.cfifo(i).hold := '0';
pv.m.cfifo(i).valid := '0';
pv.m.cfifo(i).err := '0';
end loop;
-- core
pv.m.devsel_asserted := '1';
pv.m.abort := (others => '0');
pv.m.hold := (others => '0');
pv.m.hold_fifo := '0';
pv.m.term := (others => '0');
pv.m.acc_cnt := 0;
pv.m.acc_switch := '0';
for i in 0 to 1 loop
pv.m.acc(i).pending := '0';
pv.m.acc(i).active := (others => '0');
pv.m.acc(i).fifo_index := 0;
end loop;
pv.m.fifo_addr := (others => '0');
pv.m.addr := (others => '0'); -- X-prop fix
-- trans
for i in 0 to 1 loop
pv.pta_trans.msd_acc_ack(i) := '0';
pv.pta_trans.msd_acc_cancel_ack(i) := (others => '0');
pv.pta_trans.msd_acc_done(i).done := '0';
for j in 0 to FIFO_COUNT-1 loop
pv.pta_trans.msd_fifo(i)(j).pending := (others => '0');
end loop;
pv.pta_trans.msd_fifo_ack(i) := (others => '0');
end loop;
end if;
-- PCI target
lpcit_rst <= pcirst(0) and not pci_target_rst and not pci_hard_rst;
if lpcit_rst = '0' then
-- state
pv.t.fstate := ptf_idle;
for i in 0 to 2 loop
pv.t.cfifo(i).last := '0';
pv.t.cfifo(i).stlast := '0';
pv.t.cfifo(i).hold := '0';
pv.t.cfifo(i).valid := '0';
pv.t.cfifo(i).err := '0';
end loop;
pv.t.cfifo(0).data := (others => '0'); -- X-prop fix
pv.t.cfifo(1).data := (others => '0'); -- X-prop fix
pv.t.atp.ctrl.addr := (others => '0'); -- X-prop fix
pv.t.cur_acc(0).addr(31) := '0'; -- X-prop fix
-- core
pv.t.discardtimeren := '1';
pv.t.hold := (others => '0');
pv.t.hold_fifo := '0';
pv.t.stop := '0';
pv.t.addr_perr := '0';
pv.t.cur_acc(0).pending := '0';
pv.t.cur_acc(0).continue := '0';
pv.t.cur_acc(0).read := '0';
pv.t.cur_acc(0).impcfgreg := '1';
pv.t.atp.index := 0;
pv.t.pta.index := 0;
pv.t.blenmask := (others => '0');
pv.t.blenmask(blenmask_size(barminsize) downto 0) := (others => '1');
pv.t.saverfifo := '0';
for i in 0 to 3 loop
pv.t.accbuf(i).pending := '0';
end loop;
-- trans
for i in 0 to FIFO_COUNT-1 loop
pv.pta_trans.tm_fifo(i).pending := (others => '0');
end loop;
pv.pta_trans.tm_fifo_ack := (others => '0');
pv.pta_trans.tm_acc.pending := '0';
pv.pta_trans.tm_acc_cancel := '0';
pv.pta_trans.tm_acc_done_ack := '0';
end if;
-- PCI reset
lpci_rst <= pcirst(0) and not pci_hard_rst;
if lpci_rst = '0' then
-- Master state
pv.m.state := pm_idle;
-- Target state
pv.t.state := pt_idle;
-- PCI signals
pv.po.frame := '1'; pv.po.irdy := '1'; pv.po.req := '1';
pv.po.trdy := '1'; pv.po.stop := '1';
pv.po.perr := '1'; pv.po.devsel := '1';
-- PCI system
pv.pta_trans.pa_serr := '1';
pv.pta_trans.pa_discardtout := '0';
-- Configuration space
for j in 0 to multifunc loop
pv.conf(j).comm.ioen := '0';
pv.conf(j).comm.memen := '0';
pv.conf(j).comm.msten := '0';
pv.conf(j).comm.mwien := '0';
pv.conf(j).comm.perren := '0';
pv.conf(j).comm.serren := '0';
pv.conf(j).comm.intdis := '0';
pv.conf(j).stat.intsta := '0';
pv.conf(j).stat.mdpe := '0';
pv.conf(j).stat.sta := '0';
pv.conf(j).stat.rta := '0';
pv.conf(j).stat.rma := '0';
pv.conf(j).stat.sse := '0';
pv.conf(j).stat.dpe := '0';
--pv.conf.clsize := (others => '0');
pv.conf(j).ltimer := (others => '0');
pv.conf(j).iline := (others => '0');
for i in 0 to 5 loop
pv.conf(j).bar(i) := (others => '0');
pv.conf(j).pta_map(i) := default_bar_map(j)(i);
pv.conf(j).bar_mask(i) := (others => '0');
pv.conf(j).bar_mask(i)(31 downto bar_size(j)(i)) := ones32(31 downto bar_size(j)(i));
pv.conf(j).bar_mask(i)(3) := bar_prefetch(j)(i);
pv.conf(j).bar_mask(i)(0) := bar_io(j)(i);
if bar_size(j)(i) <= 1 then pv.conf(j).bar_mask(i) := (others => '0'); end if;
end loop;
pv.conf(j).cfg_map := conv_std_logic_vector(extcfg_vector(j),28) & "0000";
end loop;
pv.pta_trans.ca_pcimsten := (others => '0');
pv.pta_trans.ca_twist := conv_std_logic_vector(conv_endian, 1)(0);
-- PCI trace
pv.ptta_trans.enable := '0';
pv.ptta_trans.armed := '0';
pv.ptta_trans.start_ack := '0';
pv.ptta_trans.stop_ack := '0';
pv.pt.addr := (others => '0');
end if;
if pcirst(0) = '0' then
pv.pta_trans.rst_ack := (others => '0');
end if;
-- Disabled parts
if target = 0 then -- PCI targer disabled
pv.t := pci_target_none;
pv.pta_trans.tm_acc := pci_g_acc_trans_none;
pv.pta_trans.tm_acc_cancel := '0';
pv.pta_trans.tm_acc_done_ack := '0';
pv.pta_trans.tm_fifo := pci_g_fifo_trans_vector_none;
pv.pta_trans.tm_fifo_ack := pci_g_fifo_ack_trans_vector_none;
pv.po.trdy := '1'; pv.po.trdyen := oeoff; pv.po.stop := '1'; pv.po.stopen := oeoff;
pv.po.devsel := '1'; pv.po.devsel := oeoff;
for j in 0 to multifunc loop
pv.conf(j).comm.memen := '0';
pv.conf(j).stat.sta := '0';
for i in 0 to 5 loop
pv.conf(j).bar(i) := (others => '0');
end loop;
if master /= 0 and confspace = 0 then -- No Configuration Space but PCI master => master enabled
pv.conf(j).comm.msten := '1'; pv.pta_trans.ca_pcimsten := (others => '1');
end if;
end loop;
end if;
if master = 0 and dma = 0 then -- PCI master disabled
pv.m := pci_master_none;
pv.pta_trans.msd_acc_ack(0) := '0';
pv.pta_trans.msd_acc_cancel_ack(0) := (others => '0');
pv.pta_trans.msd_acc_done(0) := pci_g_acc_status_trans_none;
pv.pta_trans.msd_fifo(0) := pci_g_fifo_trans_vector_none;
pv.pta_trans.msd_fifo_ack(0) := pci_g_fifo_ack_trans_vector_none;
pv.po.irdy := '1'; pv.po.irdyen := oeoff; pv.po.frame := '1'; pv.po.frameen := oeoff;
pv.po.req := '1'; pv.po.reqen := oeoff;
pv.po.cbe := (others => '0'); pv.po.cbeen := (others => oeoff);
for j in 0 to multifunc loop
pv.conf(j).comm.msten := '0'; pv.pta_trans.ca_pcimsten := (others => '0');
pv.conf(j).comm.mwien := '0';
pv.conf(j).stat.mdpe := '0';
pv.conf(j).stat.rta := '0';
pv.conf(j).stat.rma := '0';
end loop;
end if;
if dma = 0 then -- DMA disabled
pv.m.acc(1) := pci_master_acc_none;
pv.pta_trans.msd_acc_ack(1) := '0';
pv.pta_trans.msd_acc_cancel_ack(1) := (others => '0');
pv.pta_trans.msd_acc_done(1) := pci_g_acc_status_trans_none;
pv.pta_trans.msd_fifo(1) := pci_g_fifo_trans_vector_none;
pv.pta_trans.msd_fifo_ack(1) := pci_g_fifo_ack_trans_vector_none;
end if;
if tracebuffer = 0 then -- PCI trace buffer disabled
pv.pt := pci_trace_none;
pv.ptta_trans := pci_trace_to_apb_trans_none;
end if;
if dma = 0 and master = 0 and target = 0 then
pv.po.par := '1'; pv.po.paren := oeoff; pv.po.perr := '1'; pv.po.perren := oeoff;
pv.po.serren := oeoff; pv.po.inten := oeoff; pv.po.vinten := (others => oeoff);
pv.po.ad := (others => '0'); pv.po.aden := (others => oeoff);
for j in 0 to multifunc loop
pv.conf(j).stat.sse := '0';
pv.conf(j).stat.dpe := '0';
pv.conf(j).comm.perren := '0';
pv.conf(j).comm.serren := '0';
end loop;
end if;
-- --------------
prin <= pv;
-- PHY =>
sig_m_request <= m_request;
sig_m_mabort <= m_mabort;
sig_t_abort <= t_abort;
sig_t_ready <= t_ready;
sig_t_retry <= t_retry;
sig_soft_rst <= pci_hard_rst & pci_master_rst & pci_target_rst;
all_func_serren := '0';
for j in 0 to multifunc loop
all_func_serren := all_func_serren or pr.conf(j).comm.serren;
end loop;
sig_pr_conf_comm_serren <= all_func_serren;
if pr.m.perren /= "00" then
sig_pr_conf_comm_perren <= pr.conf(pr.m.acc(pr.m.acc_sel).func).comm.perren;
else
sig_pr_conf_comm_perren <= pr.conf(pr.t.cur_acc(0).func).comm.perren;
end if;
-- PHY <=
-- Gate PCI target => AHB master pending with pcirst
pr_pta_trans_gated <= pr.pta_trans;
pr_pta_trans_gated.tm_acc.pending <= pr.pta_trans.tm_acc.pending and pciasyncrst_comb;
end process;
acomb : process(ar, rst, pr_pta_trans_gated, dmao0, dmao1, tm_fifoo_pta, ms_fifoo_pta, md_fifoo_ptd, ahbsi, apbi, dirq, pcii.int, pt_fifoo_ad, pt_fifoo_sig, pr.ptta_trans, pcisig, lahbm_rst, lahbs_rst, lahb_rst, iotmact)
variable av : amba_reg_type;
variable pta_trans: pci_to_ahb_trans_type;
variable first : std_logic;
variable tm_nindex : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable tm_acc : pci_g_acc_trans_type;
variable tm_acc_pending : std_logic;
variable tm_acc_done : std_logic;
variable tm_acc_cancel : std_logic;
variable tm_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable tm_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable tm_fifo : pci_g_fifo_trans_vector_type;
-- AHB slave
variable slv_access : std_logic;
variable tb_access : std_logic;
variable ms_index : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable blen : std_logic_vector(15 downto 0);
variable ms_acc_pending : std_logic;
variable ms_acc_cancel : std_logic;
variable ms_acc_done : std_logic;
variable ms_acc_done_status : pci_g_acc_status_trans_type;
variable ms_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable ms_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable ms_fifo : pci_g_fifo_trans_vector_type;
variable accbufindex : integer range 0 to 3;
variable ms_func : std_logic_vector(2 downto 0);
variable ms_vifunc : integer range 0 to multifunc;
-- APB slave
variable apbaddr : std_logic_vector(6 downto 2);
variable prdata : std_logic_vector(31 downto 0);
variable pirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable c_blenmask_update : std_logic;
variable ptta_trans : pci_trace_to_apb_trans_type;
variable pt_status : pci_trace_to_apb_trans_type;
-- DMA
variable md_index : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable md_acc_pending : std_logic;
variable md_acc_cancel : std_logic;
variable md_acc_done : std_logic;
variable md_acc_done_status : pci_g_acc_status_trans_type;
variable md_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable md_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable md_fifo : pci_g_fifo_trans_vector_type;
-- Soft reset
variable pci_master_rst : std_logic;
variable pci_target_rst : std_logic;
variable pci_hard_rst : std_logic;
-- APB DEBUG
variable tbapbaddr : std_logic_vector(6 downto 2);
variable tbprdata : std_logic_vector(31 downto 0);
variable tbpirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
-- --------------------------------------------------------------------------------
-- AHB global defaults
-- --------------------------------------------------------------------------------
-- defaults
av := ar;
av.irq.access_pirq := '0';
av.irq.system_pirq := '0';
-- FIFO and AHB<=>PCI sync
av.sync(1) := pr_pta_trans_gated; av.sync(2) := ar.sync(1);
if nsync = 0 then pta_trans := pr_pta_trans_gated;
else pta_trans := ar.sync(nsync); end if;
-- PCI trace <=> APB sync
av.apb_sync(1) := pr.ptta_trans; av.apb_sync(2) := ar.apb_sync(1);
if nsync = 0 then ptta_trans := pr.ptta_trans;
else ptta_trans := ar.apb_sync(nsync); end if;
pt_status := pr.ptta_trans;
if tracebuffer = 0 then -- PCI trace buffer disabled
av.atpt_trans.start := '0'; av.atpt_trans.stop := '0'; av.atpt_trans.mode := (others => '0');
av.atpt_trans.count := (others => '0'); av.atpt_trans.tcount := (others => '0');
av.atpt_trans.ad := (others => '0'); av.atpt_trans.admask := (others => '0');
av.atpt_trans.sig := (others => '0'); av.atpt_trans.sigmask := (others => '0');
else
if ptta_trans.start_ack = '1' then av.atpt_trans.start := '0'; end if;
if ptta_trans.stop_ack = '1' then av.atpt_trans.stop := '0'; end if;
end if;
-- Soft reset
if pta_trans.rst_ack(0) = '1' then av.atp_trans.rst(0) := '0'; end if; -- PCI-target/AHB-master reset
if pta_trans.rst_ack(1) = '1' then av.atp_trans.rst(1) := '0'; end if; -- PCI-master/AHB-slave reset
pci_target_rst := pta_trans.rst_ack(0) or ar.atp_trans.rst(0);
pci_master_rst := pta_trans.rst_ack(1) or ar.atp_trans.rst(1);
pci_hard_rst := ar.atp_trans.rst(2);
-- --------------------------------------------------------------------------------
-- AHB master defaults
-- --------------------------------------------------------------------------------
-- FIFO enable(read)/write
av.m.acc.fifo_ren := '0';
av.m.acc.fifo_wen := '0';
av.m.acc.fifo_wdata := dmao0.data;
av.m.dmai0.noreq := '0';
tm_acc_pending := pta_trans.tm_acc.pending xor ar.atp_trans.tm_acc_ack;
tm_acc_done := pta_trans.tm_acc_done_ack xor ar.atp_trans.tm_acc_done.done;
tm_acc_cancel := pta_trans.tm_acc_cancel xor ar.atp_trans.tm_acc_cancel_ack(0);
-- Stop_ack also needs to be delayed when pending is delayed
av.atp_trans.tm_acc_cancel_ack(1) := ar.atp_trans.tm_acc_cancel_ack(0);
av.atp_trans.tm_acc_cancel_ack(2) := ar.atp_trans.tm_acc_cancel_ack(1);
for i in 0 to FIFO_COUNT-1 loop
tm_fifo_pending(i) := pta_trans.tm_fifo(i).pending(RAM_LATENCY) xor ar.atp_trans.tm_fifo_ack(i);
tm_fifo_empty(i) := not (ar.atp_trans.tm_fifo(i).pending(0) xor pta_trans.tm_fifo_ack(i));
-- To set pending when data is stored in fifo, with this stop_ack also needs to be delayed
av.atp_trans.tm_fifo(i).pending(1) := ar.atp_trans.tm_fifo(i).pending(0);
av.atp_trans.tm_fifo(i).pending(2) := ar.atp_trans.tm_fifo(i).pending(1);
end loop;
tm_fifo := pr_pta_trans_gated.tm_fifo;
tm_acc := pr_pta_trans_gated.tm_acc;
-- --------------------------------------------------------------------------------
-- AHB master core
-- --------------------------------------------------------------------------------
if target /= 0 then -- PCI target enabled
-- Select next fifo
if ar.m.acc.fifo_index /= FIFO_COUNT-1 then tm_nindex := ar.m.acc.fifo_index + 1;
else tm_nindex := 0; end if;
-- latch PCI target access
if tm_acc_pending = '1' and ar.m.acc.pending = '0' then
av.atp_trans.tm_acc_ack := pta_trans.tm_acc.pending;
av.m.acc.pending := '1';
av.m.acc.addr := tm_acc.addr;
av.m.acc.mode := tm_acc.accmode;
av.m.acc.burst := tm_acc.accmode(0);
av.m.acc.cbe := tm_acc.cbe;
av.m.acc.endianess := tm_acc.endianess;
av.m.acc.length := tm_acc.length;
av.m.acc.fifo_index := tm_acc.index;
av.m.acc.acctype := tm_acc.acctype;
end if;
-- AHB master state machine
case ar.m.state is
when am_idle =>
av.m.done := (others => '0');
av.m.stop := '0';
av.m.dmai0.req := '0';
av.m.dmai0.burst := '1';
av.m.dma_hold := '0';
av.m.active := '0';
av.m.retry := '0';
if ar.m.acc.pending = '1' then
av.m.dmai0.addr := ar.m.acc.addr;
av.m.dmai0.size := set_size_from_cbe(ar.m.acc.cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(ar.m.acc.cbe, ar.m.acc.endianess);
-- Burst length (only burst up to this boundary)
av.m.blen := ar.m.acc.length;
if ar.m.acc.acctype(0) = '1' then -- Write
av.m.state := am_write;
av.m.first := "010";
av.m.hold := (others => '1');
elsif ar.m.acc.acctype(0) = '0' then -- Read
av.m.state := am_read;
av.m.first := "001";
av.m.hold := (others => '0');
av.m.dmai0.write := '0';
av.m.dmai0.req := '1';
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & ar.m.acc.addr(AHB_FIFO_BITS); -- Set fifo start address
av.m.faddr := av.m.acc.addr(AHB_FIFO_BITS);
if ar.m.acc.burst = '0' then
av.m.dmai0.size := set_size_from_cbe(ar.m.acc.cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(ar.m.acc.cbe, ar.m.acc.endianess);
av.m.dmai0.burst := '0'; -- sinlge access
else
av.m.dmai0.size := "10";
av.m.dmai0.addr(1 downto 0) := "00";
end if;
end if;
end if;
if tm_acc_cancel = '1' then
av.atp_trans.tm_acc_cancel_ack(0) := pta_trans.tm_acc_cancel;
end if;
when am_read =>
if tm_fifo_empty(ar.m.acc.fifo_index) = '1' and ar.m.hold(0) = '1' and ar.m.done(0) = '0' and ar.m.active = '0' then
av.m.dmai0.req := '1';
av.m.hold := (others => '0');
end if;
if tm_acc_cancel = '1' then
av.m.done(2) := '1';
end if;
if dmao0.grant = '1' then
av.m.active := '1';
av.m.dmai0.addr := ar.m.dmai0.addr + 4;
if ar.m.blen /= zero32(15 downto 0) then
av.m.blen := ar.m.blen - 1;
end if;
if ar.m.dmai0.addr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) or ar.m.done(2) = '1' or ar.m.acc.burst = '0' then
if tm_fifo_empty(tm_nindex) = '0' then
av.m.dmai0.req := '0';
av.m.hold(0) := '1';
end if;
if ar.m.done(2) = '1' or ar.m.acc.burst = '0' or ar.m.blen = zero32(15 downto 0) then
av.m.dmai0.req := '0';
av.m.done(1) := '1';
end if;
end if;
-- Retry save & restore
av.m.retry := '0';
-- Save len for retry
av.m.retry_blen := ar.m.blen;
-- Restore len for retry
if ar.m.retry = '1' then
av.m.blen := ar.m.retry_blen;
end if;
elsif dmao0.retry = '1' then
av.m.dmai0.req := '1';
av.m.dmai0.addr := ar.m.dmai0.addr - 4;
--av.m.blen := ar.m.blen + 1;
av.m.done(1) := '0';
-- Retry save & restore
av.m.retry := '1';
-- Save len for retry
av.m.retry_blen := ar.m.blen;
-- Restore len for retry
av.m.blen := ar.m.retry_blen;
end if;
if dmao0.ready = '1' then
if dmao0.grant = '0' then av.m.active := '0'; end if;
if ar.m.faddr(AHB_FIFO_BITS) /= ones32(AHB_FIFO_BITS) and ar.m.done(1) = '0' then
av.m.faddr(AHB_FIFO_BITS) := ar.m.faddr(AHB_FIFO_BITS) + 1;
else -- Last word in fifo
av.m.faddr(AHB_FIFO_BITS) := (others => '0');
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).pending(0) := not ar.atp_trans.tm_fifo(ar.m.acc.fifo_index).pending(0);
if ar.m.first(0) = '1' then -- Mark first fifo in transfer
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).firstf := '1';
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).start := ar.m.acc.addr(AHB_FIFO_BITS);
av.m.first(0) := '0';
else
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).start := (others => '0');
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).firstf := '0';
end if;
if ar.m.done(1) = '1' then -- Mark last fifo in transfer
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).lastf := '1';
av.m.done(0) := '1';
else
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).lastf := '0';
end if;
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).stop := ar.m.faddr(AHB_FIFO_BITS);
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).status := (others => '0'); -- Not used
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).last_cbe := (others => '0'); -- Not used
end if;
av.m.acc.fifo_wen := '1';
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & ar.m.faddr(AHB_FIFO_BITS);
elsif dmao0.error = '1' then
av.m.active := '0';
av.m.dmai0.req := '0';
av.m.done(0) := '1';
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
if ar.m.first(0) = '1' then -- Mark first fifo in transfer
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).firstf := '1';
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).start := ar.m.acc.addr(AHB_FIFO_BITS);
av.m.first(0) := '0';
else
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).firstf := '0';
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).start := (others => '0');
end if;
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).lastf := '1';
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).stop := ar.m.faddr(AHB_FIFO_BITS);
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).pending(0) := not ar.atp_trans.tm_fifo(ar.m.acc.fifo_index).pending(0);
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).status(0) := '1'; -- AHB error
av.m.acc.fifo_wen := '1';
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & ar.m.faddr(AHB_FIFO_BITS);
end if;
-- to deassert req on last address phase
if av.m.dmai0.addr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) then av.m.dmai0.noreq := '1'; end if;
if ar.m.done(2) = '1' and ar.m.active = '0' and dmao0.grant = '0' then
av.m.dmai0.req := '0';
av.m.done := (others => '1');
end if;
if ar.m.done(0) = '1' then
av.m.dmai0.req := '0';
if ar.m.done(2) = '1' or ar.m.acc.burst = '0' then
if ar.m.done(2) = '1' then
for i in 0 to FIFO_COUNT-1 loop
if tm_fifo_empty(i) = '0' then
av.atp_trans.tm_fifo(i).pending(0) := not ar.atp_trans.tm_fifo(i).pending(0);
else
av.atp_trans.tm_fifo(i).pending(0) := ar.atp_trans.tm_fifo(i).pending(0);
end if;
end loop;
end if;
av.m.state := am_idle;
av.m.acc.pending := '0';
end if;
end if;
when am_write =>
av.m.acc.fifo_ren := tm_fifo_pending(ar.m.acc.fifo_index);
av.m.dmai0.write := '1';
av.m.first(0) := '0';
if tm_fifo_pending(ar.m.acc.fifo_index) = '1' and ar.m.hold(0) = '1' and ar.m.active = '0' and ar.m.done(0) = '0' and ar.m.first(2) = '0' then
av.m.first(0) := '1';
av.m.first(2) := '1';
av.m.hold := "000";
av.m.last := "000";
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & tm_fifo(ar.m.acc.fifo_index).start; -- Set fifo start address
av.m.faddr := tm_fifo(ar.m.acc.fifo_index).start; -- Set fifo start address
if ar.m.first(1) = '1' then
av.m.first(1) := '0';
end if;
-- Last access is non-word or first/last is no-data
if tm_fifo(ar.m.acc.fifo_index).start = tm_fifo(ar.m.acc.fifo_index).stop then
if ar.m.acc.cbe = ones32(3 downto 0) then
av.m.done(0) := '1';
av.m.first(0) := '0';
av.m.dmai0.req := '0';
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
elsif tm_fifo(ar.m.acc.fifo_index).last_cbe /= ar.m.acc.cbe then
av.m.dmai0.size := set_size_from_cbe(tm_fifo(ar.m.acc.fifo_index).last_cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(tm_fifo(ar.m.acc.fifo_index).last_cbe, ar.m.acc.endianess);
av.m.dmai0.burst := '0';
end if;
elsif ar.m.acc.cbe = ones32(3 downto 0) then
av.m.dmai0.addr := ar.m.dmai0.addr + 4;
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & (tm_fifo(ar.m.acc.fifo_index).start + 1); -- Set fifo start address
av.m.faddr := (tm_fifo(ar.m.acc.fifo_index).start + 1); -- Set fifo start address
end if;
end if;
if ar.m.first(0) = '1' then -- Latch first word in fifo
av.m.dmai0.req := '1';
if ar.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) /= tm_fifo(ar.m.acc.fifo_index).stop then
av.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) := ar.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) + 1;
else
av.m.hold(0) := '1';
if tm_fifo(ar.m.acc.fifo_index).lastf = '1' then
av.m.last(0) := '1';
if tm_fifo(ar.m.acc.fifo_index).status /= "0000" then
av.m.done(0) := '1';
av.m.dmai0.req := '0';
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
end if;
end if;
end if;
av.m.dmai0.data := tm_fifoo_pta.data;
end if;
if dmao0.grant = '1' then
av.m.active := '1';
av.m.dmai0.addr := ar.m.dmai0.addr + 4;
av.m.faddr := ar.m.faddr + 1;
av.m.retry := '0';
if (ar.m.active = '1' and ar.m.faddr = tm_fifo(ar.m.acc.fifo_index).stop) or ar.m.hold(1 downto 0) /= "00" or ar.m.done(0) = '1' then
if (ar.m.active = '1' and (tm_fifo_pending(tm_nindex) = '0' or tm_fifo(ar.m.acc.fifo_index).lastf = '1')) or ar.m.hold(1 downto 0) /= "00" or ar.m.done(0) = '1' then
av.m.dmai0.req := '0';
av.m.hold(0) := '1';
if tm_fifo(ar.m.acc.fifo_index).lastf = '1' then av.m.last(0) := '1'; end if;
end if;
if tm_fifo_pending(tm_nindex) = '1' then
if tm_fifo(tm_nindex).start = tm_fifo(tm_nindex).stop and tm_fifo(tm_nindex).last_cbe = ones32(3 downto 0) then
av.m.dmai0.req := '0';
av.m.hold(0) := '1';
end if;
end if;
end if;
-- Last access is non-word
if av.m.faddr(AHB_FIFO_BITS) = tm_fifo(ar.m.acc.fifo_index).stop and tm_fifo(ar.m.acc.fifo_index).last_cbe /= ar.m.acc.cbe then
av.m.dmai0.size := set_size_from_cbe(tm_fifo(ar.m.acc.fifo_index).last_cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(tm_fifo(ar.m.acc.fifo_index).last_cbe, ar.m.acc.endianess);
av.m.dmai0.burst := '0';
elsif (tm_fifo(ar.m.acc.fifo_index).lastf = '0' and tm_fifo_pending(tm_nindex) = '1' and
av.m.faddr(AHB_FIFO_BITS) = zero32(AHB_FIFO_BITS) and tm_fifo(tm_nindex).stop = zero32(AHB_FIFO_BITS) and
tm_fifo(tm_nindex).last_cbe /= ar.m.acc.cbe) then
av.m.dmai0.size := set_size_from_cbe(tm_fifo(tm_nindex).last_cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(tm_fifo(tm_nindex).last_cbe, ar.m.acc.endianess);
av.m.dmai0.burst := '0';
end if;
-- Save size and offset for retry
av.m.retry_size := ar.m.dmai0.size;
av.m.retry_offset := ar.m.dmai0.addr(1 downto 0);
-- Restore size and offset for retry
if ar.m.retry = '1' then
av.m.dmai0.size := ar.m.retry_size;
av.m.dmai0.addr(1 downto 0) := ar.m.retry_offset;
end if;
elsif dmao0.retry = '1' then
av.m.dmai0.req := '1';
av.m.dmai0.addr := ar.m.dmai0.addr - 4;
av.m.faddr := ar.m.faddr - 1;
av.m.retry := '1';
-- Save size and offset for retry
av.m.retry_size := ar.m.dmai0.size;
av.m.retry_offset := ar.m.dmai0.addr(1 downto 0);
-- Restore size and offset for retry
av.m.dmai0.size := ar.m.retry_size;
av.m.dmai0.addr(1 downto 0) := ar.m.retry_offset;
end if;
if dmao0.ready = '1' then
av.m.first(2) := '0';
if dmao0.grant = '0' and ar.m.dmai0.req = '0' then av.m.active := '0'; end if;
if ar.m.hold(1 downto 0) = "00" then
av.m.dmai0.data := tm_fifoo_pta.data;
av.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) := ar.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) + 1;
end if;
if tm_fifo_pending(ar.m.acc.fifo_index) = '1' and ar.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) = tm_fifo(ar.m.acc.fifo_index).stop and
ar.m.hold(1 downto 0) /= "11" and ar.m.done(0) = '0' then
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
av.m.acc.fifo_addr := conv_std_logic_vector(av.m.acc.fifo_index, log2(FIFO_COUNT)) & tm_fifo(tm_nindex).start; -- Set fifo start address
if tm_fifo_pending(tm_nindex) = '0' or ar.m.hold(0) = '1' then
av.m.hold(1) := '1';
end if;
if tm_fifo(ar.m.acc.fifo_index).lastf = '1' or ar.m.last(1 downto 0) /= "00" then -- Transfer done
av.m.done(0) := '1';
end if;
end if;
elsif dmao0.error = '1' then
av.m.active := '0';
av.m.dmai0.req := '0';
if ar.m.done(0) = '0' then
if tm_fifo_pending(ar.m.acc.fifo_index) = '1' and tm_fifo(ar.m.acc.fifo_index).lastf = '1' then
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
av.m.done(0) := '1';
else
av.m.state := am_error;
end if;
end if;
end if;
if ar.m.done(0) = '1' and ar.m.active = '0' then
av.m.state := am_idle;
av.m.acc.pending := '0';
end if;
if av.m.dmai0.addr(AHB_FIFO_BITS) = tm_fifo(ar.m.acc.fifo_index).stop or ar.m.done(0) = '1' then av.m.dmai0.noreq := '1'; end if; -- to deassert req on last address phase
when am_error =>
if tm_fifo_pending(ar.m.acc.fifo_index) = '1' and ar.m.done(0) = '0' then
if tm_fifo(ar.m.acc.fifo_index).lastf = '1' then
av.m.done(0) := '1';
end if;
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
end if;
if ar.m.done(0) = '1' then
av.m.state := am_idle;
av.m.acc.pending := '0';
end if;
when others =>
end case;
end if; -- PCI target enabled
-- --------------------------------------------------------------------------------
-- AHB slave defaults
-- --------------------------------------------------------------------------------
-- Default
av.s.hready := '1'; slv_access := '0'; tb_access := '0'; av.s.hresp := HRESP_OKAY;
av.s.retry := '0';
av.s.atp.ctrl.en := '0';
av.s.atp.ctrl.data := ahbreadword(ahbsi.hwdata);
av.s.pta.ctrl.en := '0';
av.s.stoppciacc := '0';
ms_acc_pending := ar.atp_trans.msd_acc(0).pending xor pta_trans.msd_acc_ack(0);
ms_acc_cancel := ar.atp_trans.msd_acc_cancel(0) xor pta_trans.msd_acc_cancel_ack(0)(RAM_LATENCY);
ms_acc_done := ar.atp_trans.msd_acc_done_ack(0) xor pta_trans.msd_acc_done(0).done;
for i in 0 to FIFO_COUNT-1 loop
ms_fifo_pending(i) := pta_trans.msd_fifo(0)(i).pending(RAM_LATENCY) xor ar.atp_trans.msd_fifo_ack(0)(i);
ms_fifo_empty(i) := not (ar.atp_trans.msd_fifo(0)(i).pending(0) xor pta_trans.msd_fifo_ack(0)(i));
av.atp_trans.msd_fifo(0)(i).pending(1) := ar.atp_trans.msd_fifo(0)(i).pending(0);
av.atp_trans.msd_fifo(0)(i).pending(2) := ar.atp_trans.msd_fifo(0)(i).pending(1);
end loop;
ms_fifo := pr_pta_trans_gated.msd_fifo(0);
ms_acc_done_status := pr_pta_trans_gated.msd_acc_done(0);
accbufindex := 0;
-- PCI function number
ms_func := ar.s.atp_map(conv_integer(ar.s.hmaster))(2 downto 0);
ms_vifunc := conv_integer(ar.s.atp_map(conv_integer(av.s.hmaster))(2 downto 0));
if multifunc = 0 then ms_func := (others => '0'); ms_vifunc := 0; end if;
-- --------------------------------------------------------------------------------
-- AHB slave core
-- --------------------------------------------------------------------------------
if master /= 0 then -- PCI master enabled
if ms_acc_done = '1' then -- Handle PCI error on AHB to PCI write
av.atp_trans.msd_acc_done_ack(0) := pta_trans.msd_acc_done(0).done;
if ms_acc_done_status.status(3) = '1' then -- PCI configuration access done
av.s.cfg_status(1) := '1';
if ms_acc_done_status.status(2 downto 0) /= "000" then av.s.cfg_status(0) := '1'; end if;
else
if ar.irq.access_en = '1' and ms_acc_done_status.status(2 downto 0) /= "000" then av.irq.access_pirq := '1'; end if;
av.irq.access_status := ar.irq.access_status or ms_acc_done_status.status(2 downto 0);
end if;
end if;
-- Select next fifo
if ar.s.state = as_write then
if ar.s.atp.index /= FIFO_COUNT-1 then ms_index := ar.s.atp.index + 1;
else ms_index := 0; end if;
else
if ar.s.pta.index /= FIFO_COUNT-1 then ms_index := ar.s.pta.index + 1;
else ms_index := 0; end if;
end if;
-- Access buffer
if ms_acc_pending = '0' and ar.s.accbuf(0).pending = '1' then
av.atp_trans.msd_acc(0) := ar.s.accbuf(0);
av.atp_trans.msd_acc(0).pending := not ar.atp_trans.msd_acc(0).pending;
av.s.accbuf(0) := ar.s.accbuf(1);
av.s.accbuf(1) := ar.s.accbuf(2);
av.s.accbuf(2) := ar.s.accbuf(3);
av.s.accbuf(3).pending := '0';
end if;
-- Set prefetch burst length
blen := x"00" & ar.s.blen;
-- AHB access latchning
if (ahbsi.hready and ahbsi.hsel(hsindex) and ahbsi.htrans(1)) = '1' then
slv_access := '1';
av.s.haddr := ahbsi.haddr; av.s.hwrite := ahbsi.hwrite;
av.s.hsel := ahbsi.hsel(hsindex); av.s.hmbsel := ahbsi.hmbsel(0 to 2);
av.s.htrans := ahbsi.htrans; av.s.hsize := ahbsi.hsize;
av.s.hburst := ahbsi.hburst(0);
av.s.hmaster := ahbsi.hmaster;
end if;
-- PCI trace buffer access
if tracebuffer /= 0 then
if (ahbsi.hsel(hsindex) and ahbsi.hmbsel(1) and ahbsi.haddr(17) and ahbsi.htrans(1)) = '1' then
tb_access := '1';
end if;
end if;
-- Second retry/error cycle
if ar.s.retry = '1' then
if ar.s.hresp = HRESP_ERROR then
av.s.hresp := HRESP_ERROR;
else
av.s.hresp := HRESP_RETRY;
if ar.s.pending = "00" and ar.s.hwrite = '0' and ar.s.start = '0' and ar.s.stoppciacc = '0' then
av.s.pending := "01";
av.s.addr := ar.s.haddr;
av.s.write := ar.s.hwrite;
av.s.master := ar.s.hmaster;
av.s.burst := ar.s.hburst;
av.s.size := ar.s.hsize;
av.s.config := (not ar.s.hmbsel(0) and ar.s.haddr(16));
av.s.io := (not ar.s.hmbsel(0) and not ar.s.haddr(16));
av.s.pta.ctrl.addr := conv_std_logic_vector(ar.s.pta.index, log2(FIFO_COUNT)) & ar.s.haddr(AHB_FIFO_BITS);
-- Change to sigle access on PCI IO and PCI CONF
if ar.s.io_cfg_burst(0) = '0' and av.s.config = '1' then av.s.burst := '0'; end if;
if ar.s.io_cfg_burst(1) = '0' and av.s.io = '1' then av.s.burst := '0'; end if;
-- Use blen if less than 1k limit and AHB-master is unmasked, else use 1k limit
if (not av.s.addr(9 downto 2)) < ar.s.blen(7 downto 0) or ar.s.blenmask(conv_integer(av.s.master)) = '0' then blen(7 downto 0) := (not av.s.addr(9 downto 2)); end if;
if ar.s.continue = '0' then
if ar.s.hmbsel(0) = '0' then -- config access and io access
if ar.s.haddr(16) = '1' then
av.s.addr := set_pci_conf_addr(ar.s.haddr, ar.s.cfg_bus);
else av.s.addr := set_pci_io_addr(ar.s.haddr, ar.s.io_map); end if;
else
av.s.addr := set_atp_addr(ar.s.haddr, ar.s.atp_map, ar.s.hmaster, AADDR_WIDTH);
end if;
if ms_acc_pending = '0' and ar.s.accbuf(0).pending = '0' then
av.atp_trans.msd_acc(0).pending := not ar.atp_trans.msd_acc(0).pending;
av.atp_trans.msd_acc(0).addr := av.s.addr;
av.atp_trans.msd_acc(0).func := ms_func; -- set PCI function
if av.s.config = '1' then av.atp_trans.msd_acc(0).acctype := CONF_READ;
elsif av.s.io = '1' then av.atp_trans.msd_acc(0).acctype := IO_READ;
else
if av.s.burst = '1' then av.atp_trans.msd_acc(0).acctype := MEM_R_MULT;
else av.atp_trans.msd_acc(0).acctype := MEM_READ; end if;
end if;
av.atp_trans.msd_acc(0).accmode := av.s.burst & '1' & av.s.burst;
av.atp_trans.msd_acc(0).size := av.s.size;
av.atp_trans.msd_acc(0).offset := ar.s.haddr(1 downto 0);
av.atp_trans.msd_acc(0).index := ar.s.pta.index;
av.atp_trans.msd_acc(0).length := blen;
av.atp_trans.msd_acc(0).cbe := (others => '0'); -- not used
av.atp_trans.msd_acc(0).endianess := '0'; -- not used
else
accbufindex := 0;
for i in 3 downto 0 loop
if av.s.accbuf(i).pending = '0' then accbufindex := i; end if;
end loop;
av.s.accbuf(accbufindex).pending := '1';
av.s.accbuf(accbufindex).addr := av.s.addr;
av.s.accbuf(accbufindex).func := ms_func; -- set PCI function
if av.s.config = '1' then av.s.accbuf(accbufindex).acctype := CONF_READ;
elsif av.s.io = '1' then av.s.accbuf(accbufindex).acctype := IO_READ;
else
if av.s.burst = '1' then av.s.accbuf(accbufindex).acctype := MEM_R_MULT;
else av.s.accbuf(accbufindex).acctype := MEM_READ; end if;
end if;
av.s.accbuf(accbufindex).accmode := av.s.burst & '1' & av.s.burst;
av.s.accbuf(accbufindex).size := av.s.size;
av.s.accbuf(accbufindex).offset := ar.s.haddr(1 downto 0);
av.s.accbuf(accbufindex).index := ar.s.pta.index;
av.s.accbuf(accbufindex).length := blen;
av.s.accbuf(accbufindex).cbe := (others => '0'); -- not used
av.s.accbuf(accbufindex).endianess := '0'; -- not used
end if;
end if;
end if;
end if;
end if;
if ms_fifo_pending(ar.s.pta.index) = '1' and ar.s.pending = "01" and ar.s.discard = '0' then
av.s.done_fifo := (others => '0');
av.s.pending := "10";
av.s.pta.ctrl.addr := conv_std_logic_vector(ar.s.pta.index, log2(FIFO_COUNT)) & ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0);
elsif ar.s.pending = "10" then
av.s.pending := "11";
av.s.pta.ctrl.addr := conv_std_logic_vector(ar.s.pta.index, log2(FIFO_COUNT)) & (ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1);
av.s.hrdata := ms_fifoo_pta.data;
if ms_fifo(ar.s.pta.index).start = ms_fifo(ar.s.pta.index).stop then
av.s.oneword := '1';
av.s.pta.ctrl.addr := conv_std_logic_vector(ar.s.pta.index, log2(FIFO_COUNT)) & ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0);
if ms_fifo_pending(ms_index) = '0' then av.s.done_fifo(0) := '1'; end if;
if ms_fifo(ar.s.pta.index).lastf = '1' then av.s.done_fifo(1) := '1'; end if;
else av.s.oneword := '0'; end if;
end if;
-- FIFO read enable
av.s.pta.ctrl.en := ms_fifo_pending(ar.s.pta.index);
-- Discard unused fifo data
if ar.s.discard = '1' then
if ms_acc_cancel = '0' then
-- moved to PCI master
av.s.discard := '0';
end if;
end if;
-- AHB slave state machine
case ar.s.state is
when as_idle =>
av.s.continue := '0';
av.s.first := '1';
av.s.firstf := '1';
av.s.tb_ren := '0';
if slv_access = '1' then
if tb_access = '1' then -- PCI trace
av.s.hready := '0';
av.s.state := as_pcitrace;
av.s.tb_ren := '1';
else
if av.s.hwrite = '1' and ms_fifo_empty(ar.s.atp.index) = '1' and
pta_trans.ca_pcimsten(ms_vifunc) = '1' and (pci_hard_rst or pci_master_rst) = '0' then -- Write
av.s.state := as_write;
elsif ar.s.pending(1) = '1' and ar.s.master = ahbsi.hmaster and
(pci_hard_rst or pci_master_rst) = '0' then -- Read
if (ms_fifo(ar.s.pta.index).status(2 downto 1) /= "00" and
ms_fifo(ar.s.pta.index).start = ms_fifo(ar.s.pta.index).stop) or -- Master/Target abort
(ms_fifo(ar.s.pta.index).status(0) = '1') then -- PAR error
if ar.s.config = '1' then -- Master/target abort during PCI config access
av.s.state := as_read;
av.s.cfg_status := "11";
else
if ar.s.erren = '1' and ms_fifo(ar.s.pta.index).status(2 downto 1) /= "00" and
ms_fifo(ar.s.pta.index).start = ms_fifo(ar.s.pta.index).stop then
av.s.hready := '0';
av.s.hresp := HRESP_ERROR;
av.s.retry := '1';
end if;
if ar.s.parerren = '1' and ms_fifo(ar.s.pta.index).status(0) = '1' then
av.s.hready := '0';
av.s.hresp := HRESP_ERROR;
av.s.retry := '1';
end if;
if ar.s.burst = '1' then
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
av.s.discard := '1';
else
av.s.pta.index := ms_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(0)(ar.s.pta.index) := pta_trans.msd_fifo(0)(ar.s.pta.index).pending(RAM_LATENCY);
end if;
av.s.pending := (others => '0');
if ar.irq.access_en = '1' then av.irq.access_pirq := '1'; end if; -- If enabled, generate irq on error
av.irq.access_status := ar.irq.access_status or ms_fifo(ar.s.pta.index).status(2 downto 0); -- Update irq status
end if;
else
if ar.s.config = '1' then av.s.cfg_status(1) := '1'; end if;
av.s.state := as_read;
end if;
elsif ms_fifo_empty(ar.s.atp.index) = '1' and pta_trans.ca_pcimsten(ms_vifunc) = '0' and
(pci_hard_rst or pci_master_rst) = '0' then
av.s.state := as_checkpcimst;
av.s.hready := '0';
elsif (pci_hard_rst or pci_master_rst) = '1' then -- Error during reset
av.s.hresp := HRESP_ERROR;
av.s.hready := '0';
av.s.retry := '1';
else -- Retry
av.s.hresp := HRESP_RETRY;
av.s.hready := '0';
av.s.retry := '1';
end if;
end if;
end if;
when as_checkpcimst =>
if ar.s.hmbsel(0) = '0' and ar.s.haddr(16) = '1' and
((ar.s.haddr(15 downto 11) = zero32(15 downto 11) and pta_trans.ca_host = '0') or ar.s.fakehost = '1') then
if ar.s.hwrite = '1' then
av.s.state := as_write;
else
av.s.hresp := HRESP_RETRY;
av.s.hready := '0';
av.s.retry := '1';
av.s.state := as_idle;
end if;
else
av.s.hresp := HRESP_ERROR;
av.s.hready := '0';
av.s.retry := '1';
av.s.state := as_idle;
end if;
when as_read =>
av.s.pending := (others => '0');
if ar.s.hready = '1' then
if ar.s.htrans(1) = '1' then
if ms_fifo_pending(ar.s.pta.index) = '1' then
if ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) = ms_fifo(ar.s.pta.index).stop or ar.s.burst = '0' or ar.s.oneword = '1' then
av.s.pta.index := ms_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(0)(ar.s.pta.index) := pta_trans.msd_fifo(0)(ar.s.pta.index).pending(RAM_LATENCY);
if ms_fifo_pending(ms_index) = '0' then av.s.done_fifo(0) := '1'; end if;
if ms_fifo(ar.s.pta.index).lastf = '1' then av.s.done_fifo(1) := '1'; end if;
end if;
end if;
av.s.hrdata := ms_fifoo_pta.data;
av.s.pta.ctrl.addr := conv_std_logic_vector(av.s.pta.index, log2(FIFO_COUNT)) & (ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1);
end if;
if ahbsi.htrans(1) = '1' and ahbsi.hsel(hsindex) = '1' then
if ahbsi.htrans(0) = '0' then
if ahbsi.hwrite = '1' and ms_fifo_empty(ar.s.atp.index) = '1' then -- new write access
av.s.state := as_write;
if ar.s.burst = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
end if;
else -- retry
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
av.s.state := as_idle;
if ar.s.burst = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
end if;
end if;
end if;
if ms_fifo_pending(ar.s.pta.index) = '1' and
((ms_fifo(ar.s.pta.index).status(2 downto 1) /= "00" and -- Master/Target abort
ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) = ms_fifo(ar.s.pta.index).stop) or
(ms_fifo(ar.s.pta.index).status(0) = '1')) then -- PAR error
if ar.s.config = '1' then -- No AHB error for PCI Config Space
av.s.cfg_status := "11";
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
else
if ar.s.erren = '1' and ms_fifo(ar.s.pta.index).status(2 downto 1) /= "00" and
ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) = ms_fifo(ar.s.pta.index).stop then
av.s.hready := '0';
av.s.hresp := HRESP_ERROR;
av.s.retry := '1';
end if;
if ar.s.parerren = '1' and ms_fifo(ar.s.pta.index).status(0) = '1' then
av.s.hready := '0';
av.s.hresp := HRESP_ERROR;
av.s.retry := '1';
end if;
av.irq.access_status := ar.irq.access_status or ms_fifo(ar.s.pta.index).status(2 downto 0); -- Update irq status
if ar.irq.access_en = '1' then av.irq.access_pirq := '1'; end if; -- If enabled, generate irq on error
end if;
av.s.state := as_idle;
if ar.s.burst = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
end if;
elsif (ahbsi.hwrite = '0' and ar.s.done_fifo(0) = '1') or ar.s.burst = '0' or ar.s.oneword = '1' then -- no pending fifo => retry
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
av.s.stoppciacc := not pta_trans.ca_pcimsten(ms_vifunc);
if ar.s.burst = '1' and ahbsi.htrans(0) = '1' then
if ar.s.done_fifo(1) = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
else
av.s.continue := '1'; -- Only for continuing bursts
end if;
end if;
av.s.state := as_idle;
end if;
elsif ahbsi.hsel(hsindex) = '0' or ahbsi.htrans(0) = '0' then -- idle
av.s.state := as_idle;
if ar.s.burst = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
end if;
end if;
end if;
when as_write =>
av.s.first := '0';
if ar.s.first = '1' then -- Store fifo start address
if ar.s.hmbsel(0) = '0' then -- mem/io/config access
if ar.s.haddr(16) = '1' then
av.s.addr := set_pci_conf_addr(ar.s.haddr, ar.s.cfg_bus);
av.s.offset := ar.s.haddr(1 downto 0);
else av.s.addr := set_pci_io_addr(ar.s.haddr, ar.s.io_map); end if;
else
av.s.addr := set_atp_addr(ar.s.haddr, ar.s.atp_map, ar.s.hmaster, AADDR_WIDTH);
end if;
av.s.size := ar.s.hsize;
av.s.config := (not ar.s.hmbsel(0) and ar.s.haddr(16));
av.s.io := (not ar.s.hmbsel(0) and not ar.s.haddr(16));
if ms_acc_pending = '0' and ar.s.accbuf(0).pending = '0' then
av.atp_trans.msd_acc(0).pending := not ar.atp_trans.msd_acc(0).pending;
av.atp_trans.msd_acc(0).addr := av.s.addr;
av.atp_trans.msd_acc(0).func := ms_func; -- set PCI function
if av.s.config = '1' then av.atp_trans.msd_acc(0).acctype := CONF_WRITE;
elsif av.s.io = '1' then av.atp_trans.msd_acc(0).acctype := IO_WRITE;
else av.atp_trans.msd_acc(0).acctype := MEM_WRITE; end if;
av.atp_trans.msd_acc(0).accmode := "00" & ar.s.hburst;
av.atp_trans.msd_acc(0).size := av.s.size;
av.atp_trans.msd_acc(0).offset := ar.s.haddr(1 downto 0);
av.atp_trans.msd_acc(0).index := ar.s.atp.index;
av.atp_trans.msd_acc(0).length := (others => '0'); -- not used
av.atp_trans.msd_acc(0).cbe := (others => '0'); -- not used
av.atp_trans.msd_acc(0).endianess := '0'; -- not used
else
accbufindex := 0;
for i in 3 downto 0 loop
if av.s.accbuf(i).pending = '0' then accbufindex := i; end if;
end loop;
av.s.accbuf(accbufindex).pending := '1';
av.s.accbuf(accbufindex).addr := av.s.addr;
av.s.accbuf(accbufindex).func := ms_func; -- set PCI function
if av.s.config = '1' then av.s.accbuf(accbufindex).acctype := CONF_WRITE;
elsif av.s.io = '1' then av.s.accbuf(accbufindex).acctype := IO_WRITE;
else av.s.accbuf(accbufindex).acctype := MEM_WRITE; end if;
av.s.accbuf(accbufindex).accmode := "00" & ar.s.hburst;
av.s.accbuf(accbufindex).size := av.s.size;
av.s.accbuf(accbufindex).offset := ar.s.haddr(1 downto 0);
av.s.accbuf(accbufindex).index := ar.s.atp.index;
av.s.accbuf(accbufindex).length := (others => '0'); -- not used
av.s.accbuf(accbufindex).cbe := (others => '0'); -- not used
av.s.accbuf(accbufindex).endianess := '0'; -- not used
end if;
end if;
if ar.s.hready = '1' then
if ar.s.htrans(1) = '1' then
if ar.s.haddr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) or ahbsi.htrans(0) = '0' then
av.s.firstf := '0';
av.s.atp.index := ms_index; -- Go to next fifo
av.atp_trans.msd_fifo(0)(ar.s.atp.index).pending(0) := not ar.atp_trans.msd_fifo(0)(ar.s.atp.index).pending(0);
if ar.s.firstf = '1' then
av.atp_trans.msd_fifo(0)(ar.s.atp.index).start := av.s.addr(AHB_FIFO_BITS);
av.atp_trans.msd_fifo(0)(ar.s.atp.index).firstf := '1';
else
av.atp_trans.msd_fifo(0)(ar.s.atp.index).start := (others => '0');
av.atp_trans.msd_fifo(0)(ar.s.atp.index).firstf := '0';
end if;
av.atp_trans.msd_fifo(0)(ar.s.atp.index).stop := ar.s.haddr(AHB_FIFO_BITS);
av.atp_trans.msd_fifo(0)(ar.s.atp.index).lastf := not ahbsi.htrans(0) or not ms_fifo_empty(ms_index);
av.atp_trans.msd_fifo(0)(ar.s.atp.index).status := (others => '0'); -- Not used
av.atp_trans.msd_fifo(0)(ar.s.atp.index).last_cbe := (others => '0'); -- Not used
end if;
av.s.atp.ctrl.en := '1';
av.s.atp.ctrl.addr := conv_std_logic_vector(ar.s.atp.index, log2(FIFO_COUNT)) & ar.s.haddr(AHB_FIFO_BITS);
end if;
if ahbsi.htrans(1) = '1' and ahbsi.hsel(hsindex) = '1' then
if ahbsi.htrans(0) = '0' then
if ahbsi.hwrite = '1' and ms_fifo_empty(ms_index) = '1' then -- new write access
av.s.first := '1';
av.s.firstf := '1';
else -- retry
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
av.s.state := as_idle;
end if;
end if;
if ahbsi.hwrite = '1' and ar.s.haddr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) and ms_fifo_empty(ms_index) = '0' then -- no empty fifo => retry
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
av.s.state := as_idle;
end if;
elsif ahbsi.hsel(hsindex) = '0' or ahbsi.htrans(0) = '0' then -- idle
av.s.state := as_idle;
end if;
end if;
when as_pcitrace =>
if ar.s.hready = '1' then
if tb_access = '1' then
av.s.hready := '0';
av.s.tb_ren := '1';
else
av.s.state := as_idle;
if ahbsi.htrans(1) = '1' and ahbsi.hsel(hsindex) = '1' then
av.s.hready := '0';
av.s.retry := '1';
av.s.hresp := HRESP_RETRY;
end if;
end if;
else
av.s.tb_ren := '0';
if ar.s.tb_ren = '0' then
av.s.hready := '1';
if ar.s.haddr(16) = '0' then
av.s.hrdata := pt_fifoo_ad.data;
else
av.s.hrdata := zero32(31 downto 20) & pt_fifoo_sig.data(16 downto 0) & "000";
end if;
else
av.s.hready := '0';
end if;
end if;
when others =>
end case;
end if; -- PCI master enabled
-- --------------------------------------------------------------------------------
-- DMA defaults
-- --------------------------------------------------------------------------------
av.dma.irq := '0';
-- FIFO enable(read)/write
av.dma.ptd.ctrl.en := '0';
av.dma.dtp.ctrl.en := '0';
av.dma.dtp.ctrl.data := dmao1.data;
av.dma.dmai1.noreq := '0';
av.dma.desc.addr(3 downto 0) := (others => '0');
md_acc_pending := ar.atp_trans.msd_acc(1).pending xor pta_trans.msd_acc_ack(1);
md_acc_cancel := ar.atp_trans.msd_acc_cancel(1) xor pta_trans.msd_acc_cancel_ack(1)(RAM_LATENCY);
md_acc_done := ar.atp_trans.msd_acc_done_ack(1) xor pta_trans.msd_acc_done(1).done;
for i in 0 to FIFO_COUNT-1 loop
md_fifo_pending(i) := pta_trans.msd_fifo(1)(i).pending(RAM_LATENCY) xor ar.atp_trans.msd_fifo_ack(1)(i);
md_fifo_empty(i) := not (ar.atp_trans.msd_fifo(1)(i).pending(0) xor pta_trans.msd_fifo_ack(1)(i));
av.atp_trans.msd_fifo(1)(i).pending(1) := ar.atp_trans.msd_fifo(1)(i).pending(0);
av.atp_trans.msd_fifo(1)(i).pending(2) := ar.atp_trans.msd_fifo(1)(i).pending(1);
end loop;
md_fifo := pr_pta_trans_gated.msd_fifo(1);
md_acc_done_status := pr_pta_trans_gated.msd_acc_done(1);
-- --------------------------------------------------------------------------------
-- DMA core
-- --------------------------------------------------------------------------------
if dma /= 0 then -- DMA enabled
-- Select next fifo
if ar.dma.state = dma_read then
if ar.dma.dtp.index /= FIFO_COUNT-1 then md_index := ar.dma.dtp.index + 1;
else md_index := 0; end if;
else
if ar.dma.ptd.index /= FIFO_COUNT-1 then md_index := ar.dma.ptd.index + 1;
else md_index := 0; end if;
end if;
case ar.dma.state is
when dma_idle =>
av.dma.err := (others => '0');
av.dma.running := '0';
av.dma.dmai1.req := '0';
av.dma.dmai1.write := '0';
av.dma.dmai1.burst := '1';
av.dma.dmai1.addr := ar.dma.desc.addr;
av.dma.desc.chcnt := ar.dma.numch;
if ar.dma.errstatus /= "00000" then
av.dma.en := '0';
elsif ar.dma.en = '1' then
av.dma.state := dma_read_desc;
av.dma.rcnt := (others => '0');
av.dma.dmai1.req := '1';
av.dma.dmai1.size := "10";
av.dma.running := '1';
end if;
when dma_read_desc =>
av.dma.active := '0';
av.dma.dma_hold := (others => '0');
av.dma.done := (others => '0');
av.dma.first(0) := '1';
av.dma.retry := '0';
if ar.dma.rcnt = "11" and ar.dma.desc.desctype /= "01"
and (ar.dma.desc.emptych = '0' or ar.dma.desc.chcnt = "000") then av.dma.dmai1.req := '0';
else av.dma.dmai1.req := '1'; end if;
av.dma.dmai1.burst := '1';
if dmao1.grant = '1' then
av.dma.dmai1.addr := ar.dma.dmai1.addr + 4;
if ar.dma.dmai1.addr(3 downto 2) = "11" then
if ar.dma.desc.desctype = "01" then
av.dma.dmai1.addr := dmao1.data;
elsif ar.dma.desc.emptych = '1' then
av.dma.desc.addr := ar.dma.desc.nextch;
av.dma.dmai1.addr := ar.dma.desc.nextch;
if ar.dma.desc.chcnt = "000" then
av.dma.dmai1.req := '0';
end if;
else
av.dma.dmai1.req := '0';
end if;
end if;
elsif dmao1.retry = '1' then
av.dma.dmai1.addr := ar.dma.dmai1.addr - 4;
end if;
if av.dma.dmai1.addr(3 downto 2) = "11" then av.dma.dmai1.noreq := '1'; end if;
if dmao1.ready = '1' then
av.dma.err := (others => '0');
av.dma.rcnt := ar.dma.rcnt + 1;
case ar.dma.rcnt is
when "00" => -- Ctrl
av.dma.desc.en := dmao1.data(31);
av.dma.desc.irqen := dmao1.data(30);
av.dma.desc.write := dmao1.data(29);
av.dma.desc.tw := dmao1.data(28);
av.dma.desc.cio := dmao1.data(27 downto 26);
av.dma.desc.acctype := dmao1.data(25 downto 22);
av.dma.desc.desctype := dmao1.data(21 downto 20);
-- dmao1.data(19) = err
av.dma.desc.len := dmao1.data(15 downto 0);
when "01" => -- PCI address / Next DMA CH
if ar.dma.desc.desctype = "01" then
av.dma.desc.ch := ar.dma.desc.addr;
av.dma.desc.nextch := dmao1.data;
av.dma.desc.cnt := ar.dma.desc.len;
av.dma.desc.chid := ar.dma.desc.acctype(2 downto 0);
av.dma.desc.emptych := '1';
else
if ar.dma.desc.en = '1' then
av.dma.desc.emptych := '0';
end if;
av.dma.desc.paddr := dmao1.data;
end if;
when "10" => -- AHB address / Next desc
if ar.dma.desc.desctype = "01" then
av.dma.desc.addr := dmao1.data;
else
av.dma.desc.aaddr := dmao1.data;
end if;
when "11" => -- Next desc / ----
if ar.dma.desc.en = '1' then
if ar.dma.desc.desctype = "00" then
av.dma.desc.chcnt := ar.dma.numch;
av.dma.desc.nextdesc := dmao1.data;
if ar.dma.desc.write = '1' then -- AHB read => PCI write
av.dma.state := dma_read;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '0';
av.dma.dmai1.addr := ar.dma.desc.aaddr;
if ar.dma.desc.len /= x"0000" then av.dma.dmai1.burst := '1';
else av.dma.dmai1.burst := '0'; end if;
av.dma.dmai1.size := "10"; -- 32-bit access -- add support for unaligned accesses
av.dma.dtp.ctrl.addr := conv_std_logic_vector(ar.dma.dtp.index, log2(FIFO_COUNT)) & ar.dma.desc.aaddr(AHB_FIFO_BITS); -- Set fifo start address
av.dma.faddr := ar.dma.desc.aaddr(AHB_FIFO_BITS);
av.dma.len := (others => '0');
av.dma.errlen := (others => '0');
else -- PCI read => AHB write
av.dma.state := dma_write;
av.dma.first := "010";
av.dma.dma_hold := "111";
av.dma.addr := ar.dma.desc.aaddr;
av.dma.len := (others => '0');
av.dma.errlen := (others => '0');
end if;
-- Setup access [Read and Write]
av.atp_trans.msd_acc(1).pending := not ar.atp_trans.msd_acc(1).pending;
av.atp_trans.msd_acc(1).addr := ar.dma.desc.paddr;
av.atp_trans.msd_acc(1).func := "000"; -- DMA uses PCI function 0
if ar.dma.desc.write = '1' then -- AHB read => PCI write
av.atp_trans.msd_acc(1).index := ar.dma.dtp.index;
if ar.dma.desc.cio = "01" then -- PCI IO access
av.atp_trans.msd_acc(1).acctype := IO_WRITE;
elsif ar.dma.desc.cio = "01" then -- PCI Configuration access
av.atp_trans.msd_acc(1).acctype := CONF_WRITE;
else -- PCI Memory access
av.atp_trans.msd_acc(1).acctype := MEM_WRITE;
end if;
else
av.atp_trans.msd_acc(1).index := ar.dma.ptd.index;
if ar.dma.desc.cio = "01" then -- PCI IO access
av.atp_trans.msd_acc(1).acctype := IO_READ;
elsif ar.dma.desc.cio = "01" then -- PCI Configuration access
av.atp_trans.msd_acc(1).acctype := CONF_READ;
else -- PCI Memory access
if ar.dma.desc.len /= x"0000" then
av.atp_trans.msd_acc(1).acctype := MEM_R_MULT;
else
av.atp_trans.msd_acc(1).acctype := MEM_READ;
end if;
end if;
end if;
if ar.dma.desc.len /= x"0000" then
av.atp_trans.msd_acc(1).accmode := "011";
else
av.atp_trans.msd_acc(1).accmode := "010";
end if;
av.atp_trans.msd_acc(1).size := "010"; -- add size support
av.atp_trans.msd_acc(1).offset := ar.dma.desc.paddr(1 downto 0);
av.atp_trans.msd_acc(1).length := ar.dma.desc.len;
av.atp_trans.msd_acc(1).cbe := (others => '0'); -- not used
av.atp_trans.msd_acc(1).endianess := av.dma.desc.tw;
end if;
else
if ar.dma.desc.emptych = '0' then
av.dma.state := dma_next_channel;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.addr := ar.dma.desc.ch + 8;
av.dma.dmai1.data := ar.dma.desc.nextdesc;
else
if ar.dma.desc.chcnt = "000" then
av.dma.en := '0';
av.dma.state := dma_idle;
else
av.dma.desc.chcnt := ar.dma.desc.chcnt - 1;
end if;
end if;
end if;
when others =>
end case;
elsif dmao1.error = '1' then
av.dma.en := '0';
av.dma.state := dma_idle;
av.dma.dmai1.req := '0';
av.dma.irq := '1'; av.dma.irqstatus(0) := '1';
av.dma.errstatus(0) := '1';
end if;
when dma_next_channel =>
if dmao1.grant = '1' then
av.dma.dmai1.req := '0';
elsif dmao1.retry = '1' then
av.dma.dmai1.req := '1';
end if;
if dmao1.ready = '1' then
av.dma.state := dma_read_desc;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '0';
av.dma.dmai1.burst := '1';
av.dma.desc.addr := ar.dma.desc.nextch;
av.dma.dmai1.addr := ar.dma.desc.nextch;
elsif dmao1.error = '1' then
av.dma.en := '0';
av.dma.state := dma_idle;
av.dma.dmai1.req := '0';
av.dma.irq := '1'; av.dma.irqstatus(0) := '1';
end if;
when dma_write_status =>
if dmao1.grant = '1' then
if ar.dma.desc.cnt = x"0001" then -- Next Channel
av.dma.dmai1.addr := ar.dma.desc.ch + 8;
else
av.dma.dmai1.req := '0';
end if;
elsif dmao1.retry = '1' then
av.dma.dmai1.req := '1';
av.dma.dmai1.addr := ar.dma.desc.addr;
end if;
if dmao1.ready = '1' then
if ar.dma.err /= "000" then
av.dma.en := '0';
av.dma.state := dma_idle;
av.dma.irq := '1'; av.dma.irqstatus(0) := '1';
else
if ar.dma.desc.irqen = '1' then
av.dma.irq := '1';
av.dma.irqstatus(1) := '1';
av.dma.irqch(conv_integer(ar.dma.desc.chid)) := '1';
end if;
if ar.dma.en = '0' then -- DMA disabled
av.dma.state := dma_idle;
av.dma.desc.addr := ar.dma.desc.nextdesc;
else
if ar.dma.desc.cnt = x"0001" then -- Next Channel
av.dma.state := dma_next_channel;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.data := ar.dma.desc.nextdesc;
else -- Next Desc
if ar.dma.desc.cnt /= x"0000" then
av.dma.desc.cnt := av.dma.desc.cnt - 1;
end if;
av.dma.state := dma_read_desc;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '0';
av.dma.dmai1.burst := '1';
av.dma.desc.addr := ar.dma.desc.nextdesc;
av.dma.dmai1.addr := ar.dma.desc.nextdesc;
end if;
end if;
end if;
elsif dmao1.error = '1' then
av.dma.en := '0';
av.dma.state := dma_idle;
av.dma.dmai1.req := '0';
av.dma.irq := '1'; av.dma.irqstatus(0) := '1';
av.dma.errstatus(0) := '1';
end if;
when dma_read => -- AHB read => PCI write
if md_fifo_empty(ar.dma.dtp.index) = '1' and ar.dma.dma_hold(0) = '1' and ar.dma.done(0) = '0' and ar.dma.active = '0' then
av.dma.dmai1.req := '1';
av.dma.dma_hold(1 downto 0) := "00";
end if;
if dmao1.grant = '1' then
av.dma.active := '1';
av.dma.dmai1.addr := ar.dma.dmai1.addr + 4;
if ar.dma.len /= ar.dma.desc.len then
av.dma.len := ar.dma.len + 1;
end if;
if ar.dma.dmai1.addr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) or ar.dma.len = ar.dma.desc.len then
if md_fifo_empty(md_index) = '0' then
av.dma.dmai1.req := '0';
av.dma.dma_hold(0) := '1';
end if;
if ar.dma.len = ar.dma.desc.len then
av.dma.dmai1.req := '0';
av.dma.done(1) := '1';
end if;
end if;
-- Retry save & restore
av.dma.retry := '0';
-- Save len for retry
av.dma.retry_len := ar.dma.len;
-- Restore len for retry
if ar.dma.retry = '1' then
av.dma.len := ar.dma.retry_len;
end if;
elsif dmao1.retry = '1' then
av.dma.dmai1.req := '1';
av.dma.dmai1.addr := ar.dma.dmai1.addr - 4;
--av.dma.len := ar.dma.len - 1;
av.dma.done(1) := '0';
-- Retry save & restore
av.dma.retry := '1';
-- Save len for retry
av.dma.retry_len := ar.dma.len;
-- Restore len for retry
av.dma.len := ar.dma.retry_len;
end if;
if dmao1.ready = '1' then
if ar.dma.errlen /= ar.dma.desc.len then
av.dma.errlen := ar.dma.errlen + 1;
end if;
if dmao1.grant = '0' then av.dma.active := '0'; end if;
if ar.dma.faddr(AHB_FIFO_BITS) /= ones32(AHB_FIFO_BITS) and ar.dma.done(1) = '0' then -- Store data in fifo
av.dma.faddr(AHB_FIFO_BITS) := ar.dma.faddr(AHB_FIFO_BITS) + 1;
else -- Last word in fifo
av.dma.faddr(AHB_FIFO_BITS) := (others => '0');
av.dma.dtp.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).pending(0) := not ar.atp_trans.msd_fifo(1)(ar.dma.dtp.index).pending(0);
if ar.dma.first(0) = '1' then -- Mark first fifo in transfer
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).firstf := '1';
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).start := ar.dma.desc.aaddr(AHB_FIFO_BITS);
av.dma.first(0) := '0';
else
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).start := (others => '0');
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).firstf := '0';
end if;
if ar.dma.done(1) = '1' then -- Mark last fifo in transfer
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).lastf := '1';
av.dma.done(0) := '1';
else
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).lastf := '0';
end if;
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).stop := ar.dma.faddr(AHB_FIFO_BITS);
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).status := (others => '0'); -- Not used
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).last_cbe := (others => '0'); -- Not used
end if;
av.dma.dtp.ctrl.en := '1';
av.dma.dtp.ctrl.addr := conv_std_logic_vector(ar.dma.dtp.index, log2(FIFO_COUNT)) & ar.dma.faddr(AHB_FIFO_BITS);
elsif dmao1.error = '1' then
av.dma.active := '0';
av.dma.dmai1.req := '0';
av.dma.done(0) := '1';
av.dma.err(0) := '1';
av.dma.dtp.index := md_index; -- Go to next fifo
if ar.dma.first(0) = '1' then -- Mark first fifo in transfer
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).firstf := '1';
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).start := ar.dma.desc.aaddr(AHB_FIFO_BITS);
av.dma.first(0) := '0';
else
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).firstf := '0';
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).start := (others => '0');
end if;
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).lastf := '1';
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).stop := ar.dma.faddr(AHB_FIFO_BITS);
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).pending(0) := not ar.atp_trans.msd_fifo(1)(ar.dma.dtp.index).pending(0);
av.dma.dtp.ctrl.en := '1';
av.dma.dtp.ctrl.addr := conv_std_logic_vector(ar.dma.dtp.index, log2(FIFO_COUNT)) & ar.dma.faddr(AHB_FIFO_BITS);
end if;
if av.dma.dmai1.addr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) or av.dma.len = ar.dma.desc.len then av.dma.dmai1.noreq := '1'; end if; -- to deassert req on last address phase
if ar.dma.done(0) = '1' then
av.dma.dmai1.req := '0';
if md_acc_done = '1' then
av.atp_trans.msd_acc_done_ack(1) := not ar.atp_trans.msd_acc_done_ack(1);
av.dma.state := dma_write_status;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.addr := ar.dma.desc.addr;
av.dma.dmai1.data := (others => '0');
av.dma.dmai1.data(30) := ar.dma.desc.irqen;
av.dma.dmai1.data(29) := ar.dma.desc.write;
av.dma.dmai1.data(28) := ar.dma.desc.tw;
av.dma.dmai1.data(21 downto 20) := ar.dma.desc.desctype;
if ar.dma.err(0) = '1' then
av.dma.dmai1.data(19) := '1';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
av.dma.errstatus(1) := '1';
elsif md_acc_done_status.status /= "0000" then
av.dma.err(2) := '1';
av.dma.dmai1.data(19) := '1';
av.dma.dmai1.data(15 downto 0) := md_acc_done_status.count;
av.dma.errstatus(4 downto 2) := md_acc_done_status.status(2 downto 0);
else
av.dma.dmai1.data(19) := '0';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
end if;
end if;
end if;
when dma_write => -- PCI read => AHB write
av.dma.ptd.ctrl.en := md_fifo_pending(ar.dma.ptd.index);
av.dma.dmai1.write := '1';
av.dma.first(0) := '0';
if md_fifo_pending(ar.dma.ptd.index) = '1' and ar.dma.dma_hold(0) = '1' and ar.dma.active = '0' and ar.dma.done(0) = '0' and ar.dma.first(2) = '0' then
av.dma.first(0) := '1';
av.dma.first(2) := '1';
av.dma.dma_hold := "000";
av.dma.dma_last := "000";
av.dma.newfifo := '0';
av.dma.ptd.ctrl.addr := conv_std_logic_vector(ar.dma.ptd.index, log2(FIFO_COUNT)) & md_fifo(ar.dma.ptd.index).start; -- Set fifo start address
av.dma.faddr := md_fifo(ar.dma.ptd.index).start; -- Set fifo start address
if ar.dma.first(1) = '1' then
av.dma.first(1) := '0';
av.dma.dmai1.addr := ar.dma.addr;
av.dma.dmai1.size := "10";
av.dma.dmai1.addr(1 downto 0) := "00";
end if;
end if;
if ar.dma.first(0) = '1' then -- Latch first word in fifo
av.dma.dmai1.req := '1';
if ar.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) /= md_fifo(ar.dma.ptd.index).stop then
av.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) := ar.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1;
else
av.dma.dma_hold(0) := '1';
if md_fifo(ar.dma.ptd.index).lastf = '1' then
av.dma.dma_last(0) := '1';
if md_fifo(ar.dma.ptd.index).status /= "0000" then
av.dma.done(0) := '1';
av.dma.dmai1.req := '0';
av.dma.err(2) := '1'; -- PCI error
av.dma.errlen := ar.dma.errlen;
av.dma.ptd.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(1)(ar.dma.ptd.index) := pta_trans.msd_fifo(1)(ar.dma.ptd.index).pending(RAM_LATENCY);
av.dma.errstatus(4 downto 2) := md_fifo(ar.dma.ptd.index).status(2 downto 0);
end if;
end if;
end if;
av.dma.dmai1.data := md_fifoo_ptd.data;
end if;
if dmao1.grant = '1' then
av.dma.active := '1';
av.dma.newfifo := '0';
av.dma.dmai1.addr := ar.dma.dmai1.addr + 4;
av.dma.faddr := ar.dma.faddr + 1;
if (ar.dma.active = '1' and ar.dma.faddr = md_fifo(ar.dma.ptd.index).stop) or ar.dma.dma_hold(1 downto 0) /= "00" or ar.dma.done(0) = '1' then
if (ar.dma.active = '1' and md_fifo_pending(md_index) = '0') or ar.dma.dma_hold(1 downto 0) /= "00" or ar.dma.done(0) = '1' then
av.dma.dmai1.req := '0';
av.dma.dma_hold(0) := '1';
end if;
end if;
elsif dmao1.retry = '1' then
av.dma.dmai1.req := '1';
av.dma.dmai1.addr := ar.dma.dmai1.addr - 4;
av.dma.faddr := ar.dma.faddr - 1;
end if;
if dmao1.ready = '1' then
av.dma.first(2) := '0';
if ar.dma.errlen /= ar.dma.desc.len then
av.dma.errlen := ar.dma.errlen + 1;
end if;
if dmao1.grant = '0' and ar.dma.dmai1.req = '0' then av.dma.active := '0'; end if;
if ar.dma.dma_hold(1 downto 0) = "00" then
av.dma.dmai1.data := md_fifoo_ptd.data;
av.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) := ar.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1;
end if;
if md_fifo_pending(ar.dma.ptd.index) = '1' and ar.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) = md_fifo(ar.dma.ptd.index).stop and
ar.dma.dma_hold(1 downto 0) /= "11" and ar.dma.done(0) = '0' then
av.dma.ptd.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(1)(ar.dma.ptd.index) := pta_trans.msd_fifo(1)(ar.dma.ptd.index).pending(RAM_LATENCY);
av.dma.ptd.ctrl.addr := conv_std_logic_vector(av.dma.ptd.index, log2(FIFO_COUNT)) & md_fifo(md_index).start; -- Set fifo start address
if md_fifo_pending(md_index) = '0' or ar.dma.dma_hold(0) = '1' then
av.dma.dma_hold(1) := '1';
end if;
if md_fifo(ar.dma.ptd.index).lastf = '1' or ar.dma.dma_last(1 downto 0) /= "00" then -- Transfer done
av.dma.done(0) := '1';
if md_fifo(ar.dma.ptd.index).status /= "0000" then
av.dma.err(2) := '1'; -- PCI error
av.dma.errlen := ar.dma.errlen;
av.dma.errstatus(4 downto 2) := md_fifo(ar.dma.ptd.index).status(2 downto 0);
end if;
end if;
end if;
elsif dmao1.error = '1' then
av.dma.err(0) := '1';
av.dma.errstatus(1) := '1';
av.dma.active := '0';
av.dma.dmai1.req := '0';
if ar.dma.done(0) = '0' then
if md_fifo_pending(ar.dma.ptd.index) = '1' and md_fifo(ar.dma.ptd.index).lastf = '1' then
av.dma.ptd.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(1)(ar.dma.ptd.index) := pta_trans.msd_fifo(1)(ar.dma.ptd.index).pending(RAM_LATENCY);
av.dma.done(0) := '1';
else
av.dma.state := dma_error;
end if;
end if;
end if;
if ar.dma.done(0) = '1' and ar.dma.active = '0' then
av.dma.state := dma_write_status;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.addr := ar.dma.desc.addr;
av.dma.dmai1.data := (others => '0');
av.dma.dmai1.data(30) := ar.dma.desc.irqen;
av.dma.dmai1.data(29) := ar.dma.desc.write;
av.dma.dmai1.data(28) := ar.dma.desc.tw;
av.dma.dmai1.data(21 downto 20) := ar.dma.desc.desctype;
if ar.dma.err(0) = '1' or ar.dma.err(2) = '1' then
av.dma.dmai1.data(19) := '1';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
else
av.dma.dmai1.data(19) := '0';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
end if;
end if;
if av.dma.dmai1.addr(AHB_FIFO_BITS) = md_fifo(ar.dma.ptd.index).stop or ar.dma.done(0) = '1' then av.dma.dmai1.noreq := '1'; end if; -- to deassert req on last address phase
when dma_error => -- Wait for last fifo
if md_fifo_pending(ar.dma.ptd.index) = '1' and ar.dma.done(0) = '0' then
if md_fifo(ar.dma.ptd.index).lastf = '1' then
av.dma.done(0) := '1';
end if;
av.dma.ptd.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(1)(ar.dma.ptd.index) := pta_trans.msd_fifo(1)(ar.dma.ptd.index).pending(RAM_LATENCY);
end if;
if ar.dma.done(0) = '1' then
av.dma.state := dma_write_status;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.addr := ar.dma.desc.addr;
av.dma.dmai1.data := (others => '0');
av.dma.dmai1.data(30) := ar.dma.desc.irqen;
av.dma.dmai1.data(29) := ar.dma.desc.write;
av.dma.dmai1.data(28) := ar.dma.desc.tw;
av.dma.dmai1.data(21 downto 20) := ar.dma.desc.desctype;
if ar.dma.err(0) = '1' or ar.dma.err(2) = '1' then
av.dma.dmai1.data(19) := '1';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
else
av.dma.dmai1.data(19) := '0';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
end if;
end if;
when others =>
end case;
end if; -- DMA enabled
-- --------------------------------------------------------------------------------
-- IRQ
-- --------------------------------------------------------------------------------
pirq := (others => '0');
-- PCI device driving PCI INTA
if deviceirq = 1 then
pciinten(0) <= oeoff xor (ar.irq.device_mask(0) and (ar.irq.device_force or dirq(0)));
pciinten(1) <= oeoff xor (ar.irq.device_mask(1) and (ar.irq.device_force or dirq(1)));
pciinten(2) <= oeoff xor (ar.irq.device_mask(2) and (ar.irq.device_force or dirq(2)));
pciinten(3) <= oeoff xor (ar.irq.device_mask(3) and (ar.irq.device_force or dirq(3)));
else
av.irq.device_mask := (others => '0');
av.irq.device_force := '0';
pciinten <= (others => oeoff);
end if;
-- PCI host sampling PCI INTA..D
if hostirq = 1 then
av.irq.host_pirq_vl := (pcii.int(3) or not ar.irq.host_mask(3))
& (pcii.int(2) or not ar.irq.host_mask(2))
& (pcii.int(1) or not ar.irq.host_mask(1))
& (pcii.int(0) or not ar.irq.host_mask(0));
av.irq.host_pirq_l := not ( av.irq.host_pirq_vl(0) and av.irq.host_pirq_vl(1)
and av.irq.host_pirq_vl(2) and av.irq.host_pirq_vl(3));
av.irq.host_status := pcii.int(3)
& pcii.int(2)
& pcii.int(1)
& pcii.int(0);
else
av.irq.host_mask := (others => '0');
av.irq.host_status := (others => '0');
av.irq.host_pirq_vl:= (others => '0');
av.irq.host_pirq_l := '0';
end if;
-- System error irq (SERR)
if pta_trans.pa_serr = '1' and ar.atp_trans.pa_serr_rst = '1' then
av.irq.system_status(0) := '0';
av.atp_trans.pa_serr_rst := '0';
elsif pta_trans.pa_serr = '0' then
av.irq.system_status(0) := '1';
if ar.irq.system_en = '1' and ar.irq.system_status(0) = '0' then
av.irq.system_pirq := '1';
end if;
end if;
-- System error irq (Discard time out)
if pta_trans.pa_discardtout = '0' and ar.atp_trans.pa_discardtout_rst = '1' then
av.irq.system_status(1) := '0';
av.atp_trans.pa_discardtout_rst := '0';
elsif pta_trans.pa_discardtout = '1' then
av.irq.system_status(1) := '1';
if ar.irq.system_en = '1' and ar.irq.system_status(1) = '0' then
av.irq.system_pirq := '1';
end if;
end if;
-- Level IRQ
av.irq.system_pirq_l := ar.irq.system_en and orv(ar.irq.system_status);
av.irq.access_pirq_l := ar.irq.access_en and orv(ar.irq.access_status);
av.irq.dma_pirq_l := ar.dma.irqen and orv(ar.dma.irqstatus);
if irqmode = 0 then -- PCI INTA..D, Error irq and DMA irq on the same interrupt
pirq(irq) := ar.irq.host_pirq_l or ar.irq.access_pirq_l or ar.irq.dma_pirq_l or ar.irq.system_pirq_l; -- All level irq
elsif irqmode = 1 then -- PCI INTA..D and Error irq on the same interrupt. DMA irq no next interrupt
pirq(irq) := ar.irq.host_pirq_l or ar.irq.access_pirq_l or ar.irq.system_pirq_l;
pirq(irq+1) := (ar.dma.irqen and ar.dma.irq);
elsif irqmode = 2 then -- PCI INTA..D on separate interrupt, Error irq and DMA irq on first interrupt
pirq(irq) := not ar.irq.host_pirq_vl(0) or ar.irq.access_pirq_l or ar.irq.dma_pirq_l or ar.irq.system_pirq_l;
pirq(irq+1) := not ar.irq.host_pirq_vl(1);
pirq(irq+2) := not ar.irq.host_pirq_vl(2);
pirq(irq+3) := not ar.irq.host_pirq_vl(3);
else --if irqmode = 3 then -- PCI INTA..D on separate interrupt, Error irq on first interrupt, DMA irq on interrupt after PCI INTD
pirq(irq) := not ar.irq.host_pirq_vl(0) or ar.irq.access_pirq_l or ar.irq.system_pirq_l;
pirq(irq+1) := not ar.irq.host_pirq_vl(1);
pirq(irq+2) := not ar.irq.host_pirq_vl(2);
pirq(irq+3) := not ar.irq.host_pirq_vl(3);
pirq(irq+4) := (ar.dma.irqen and ar.dma.irq);
end if;
-- --------------------------------------------------------------------------------
-- APB Slave
-- --------------------------------------------------------------------------------
av.apb_pt_stat := zero32(15 downto PT_DEPTH) & pt_status.taddr
& pt_status.armed & ptta_trans.enable & pt_status.wrap & "0"
& conv_std_logic_vector(PT_DEPTH, 8)
& "00" & ar.atpt_trans.stop & ar.atpt_trans.start;
av.debug_pr := pr.debug;
av.apb_pr_conf_0_pta_map := pr.conf(0).pta_map;
prdata := (others => '0');
apbaddr := apbi.paddr(6 downto 2);
if iotest/=0 and iotmact='0' then av.debuga(5 downto 0) := "000000"; end if;
if (apbi.psel(pindex) and apbi.penable) = '1' then
if apbi.paddr(7) = '0' then -- PCI core and DMA
case apbaddr is
when "00000" => -- 0x00 Control
prdata(31 downto 29) := ar.atp_trans.rst(2 downto 0);
prdata( 28) := '0';
prdata( 27) := ar.irq.system_en;
prdata( 26) := ar.s.parerren;
prdata( 25) := ar.s.erren;
prdata( 24) := ar.irq.access_en;
prdata(23 downto 16) := ar.s.cfg_bus;
prdata(15 downto 12) := (others => '0'); -- RESERVED
prdata( 11) := ar.atp_trans.mstswdis;
prdata(10 downto 9) := ar.s.io_cfg_burst;
prdata( 8) := ar.irq.device_force;
prdata( 7 downto 4) := ar.irq.device_mask;
prdata( 3 downto 0) := ar.irq.host_mask;
if apbi.pwrite = '1' then
av.atp_trans.rst(2) := apbi.pwdata(31);
av.atp_trans.rst(1 downto 0) := ar.atp_trans.rst(1 downto 0) or apbi.pwdata(30 downto 29);
av.irq.system_en := apbi.pwdata( 27);
av.s.parerren := apbi.pwdata( 26);
av.s.erren := apbi.pwdata( 25);
av.irq.access_en := apbi.pwdata( 24);
av.s.cfg_bus := apbi.pwdata(23 downto 16);
-- := apbi.pwdata(15 downto 12);
av.atp_trans.mstswdis:= apbi.pwdata( 11);
av.s.io_cfg_burst := apbi.pwdata(10 downto 9);
av.irq.device_force := apbi.pwdata( 8);
av.irq.device_mask := apbi.pwdata( 7 downto 4);
av.irq.host_mask := apbi.pwdata( 3 downto 0);
end if;
when "00001" => -- 0x04 Status
prdata(31) := (pta_trans.ca_host and not ar.s.fakehost);
prdata(30) := conv_std_logic(master/=0);
prdata(29) := conv_std_logic(target/=0);
prdata(28) := conv_std_logic(dma/=0);
prdata(27) := conv_std_logic(deviceirq/=0);
prdata(26) := conv_std_logic(hostirq/=0);
prdata(25 downto 24) := conv_std_logic_vector(irqmode, 2);
prdata(23) := conv_std_logic(tracebuffer/=0);
prdata(22 downto 22) := (others => '0'); -- RESERVED
prdata( 21) := ar.s.fakehost;
prdata(20 downto 19) := ar.s.cfg_status;
prdata(18 downto 17) := ar.irq.system_status;
prdata(16 downto 12) := ar.dma.irqstatus & ar.irq.access_status;
prdata(11 downto 8) := ar.irq.host_status;
prdata( 7 downto 5) := (others => '0');-- conv_std_logic_vector(dma_fifo_depth, 2);
prdata( 4 downto 2) := conv_std_logic_vector(fifo_depth, 3);
prdata( 1 downto 0) := conv_std_logic_vector(fifo_count, 2);
if apbi.pwrite = '1' then
av.s.fakehost := ar.s.fakehost xor apbi.pwdata(21);
av.s.cfg_status(0) := ar.s.cfg_status(0) and not (apbi.pwdata(20) or apbi.pwdata(19)); -- Clear cfg_status
av.s.cfg_status(1) := ar.s.cfg_status(1) and not (apbi.pwdata(20) or apbi.pwdata(19)); -- Clear cfg_status
av.atp_trans.pa_discardtout_rst := ar.atp_trans.pa_discardtout_rst or apbi.pwdata(18);
av.atp_trans.pa_serr_rst := ar.atp_trans.pa_serr_rst or apbi.pwdata(17);
av.dma.irqstatus := ar.dma.irqstatus and not apbi.pwdata(16 downto 15);
av.irq.access_status := ar.irq.access_status and not apbi.pwdata(14 downto 12);
end if;
when "00010" => -- 0x08 AHB slave burst lenght and AHB-master mask
if apbi.pwrite = '1' then
av.s.blen := apbi.pwdata(7 downto 0);
av.s.blenmask := apbi.pwdata(31 downto 16);
end if;
prdata(31 downto 0) := ar.s.blenmask & zero32(15 downto 8) & ar.s.blen;
when "00011" => -- 0x0c AHB to PCI IO map
if apbi.pwrite = '1' then
av.s.io_map := apbi.pwdata(31 downto 16);
end if;
prdata(31 downto 0) := ar.s.io_map & zero32(15 downto 0);
when "00100" => -- 0x10 DMA Control
if apbi.pwrite = '1' then
av.dma.irqch := ar.dma.irqch and not apbi.pwdata(19 downto 12);
av.dma.errstatus := ar.dma.errstatus and not apbi.pwdata(11 downto 7);
if apbi.pwdata(31) = '1' then -- Safety guard for update of control fields
av.dma.numch := apbi.pwdata(6 downto 4);
av.dma.irqen := apbi.pwdata(1);
end if;
av.dma.en := (ar.dma.en and not apbi.pwdata(2)) or apbi.pwdata(0); -- bit[2] = disable/stop bit[0] = enable/start
end if;
prdata(31) := '1';
prdata(30 downto 0) := (others => '0');
prdata(19 downto 12) := ar.dma.irqch;
prdata(11 downto 7) := ar.dma.errstatus;
prdata(6 downto 4) := ar.dma.numch;
prdata(3) := ar.dma.running;
prdata(2) := '0';
prdata(1) := ar.dma.irqen;
prdata(0) := ar.dma.en;
when "00101" => -- 0x14 DMA Data desc
if apbi.pwrite = '1' then
av.dma.desc.addr(31 downto 4) := apbi.pwdata(31 downto 4);
end if;
prdata(31 downto 0) := ar.dma.desc.addr;
when "00110" => -- 0x18 DMA Channel desc
prdata(31 downto 0) := ar.dma.desc.ch;
when "00111" => -- 0x1c Reserved
prdata(31 downto 0) := ar.debuga;
if apbi.pwrite = '1' then
av.debuga := apbi.pwdata;
end if;
when "01000" => -- 0x20 PCI BAR0 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(0);
when "01001" => -- 0x24 PCI BAR1 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(1);
when "01010" => -- 0x28 PCI BAR2 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(2);
when "01011" => -- 0x2c PCI BAR3 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(3);
when "01100" => -- 0x30 PCI BAR4 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(4);
when "01101" => -- 0x34 PCI BAR5 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(5);
when "01110" => -- 0x38 Reserved
--prdata(31 downto 0) := (others => '0');
prdata := ar.debug;
when "01111" => -- 0x3c Reserved
--prdata(31 downto 0) := (others => '0');
prdata := ar.debug_pr;
when "10000" => -- 0x40 AHB master00 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(0)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(0)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(0);
when "10001" => -- 0x44 AHB master01 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(1)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(1)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(1);
when "10010" => -- 0x48 AHB master02 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(2)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(2)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(2);
when "10011" => -- 0x4c AHB master03 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(3)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(3)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(3);
when "10100" => -- 0x50 AHB master04 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(4)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(4)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(4);
when "10101" => -- 0x54 AHB master05 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(5)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(5)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(5);
when "10110" => -- 0x58 AHB master06 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(6)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(6)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(6);
when "10111" => -- 0x5c AHB master07 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(7)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(7)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(7);
when "11000" => -- 0x60 AHB master08 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(8)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(8)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(8);
when "11001" => -- 0x64 AHB master09 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(9)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(9)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(9);
when "11010" => -- 0x68 AHB master10 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(10)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(10)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(10);
when "11011" => -- 0x6c AHB master11 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(11)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(11)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(11);
when "11100" => -- 0x70 AHB master12 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(12)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(12)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(12);
when "11101" => -- 0x74 AHB master13 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(13)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(13)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(13);
when "11110" => -- 0x78 AHB master14 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(14)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(14)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(14);
when "11111" => -- 0x7c AHB master15 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(15)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(15)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(15);
when others =>
prdata(31 downto 0) := (others => '0');
end case;
elsif tracebuffer /= 0 then -- PCI trace buffer enabled
case apbaddr is
when "00000" => -- 0x80 PCI trace control & status
if apbi.pwrite = '1' then
av.atpt_trans.start := ar.atpt_trans.start or apbi.pwdata(0);
av.atpt_trans.stop := ar.atpt_trans.stop or apbi.pwdata(1);
end if;
prdata(31 downto 0) := ar.apb_pt_stat;
when "00001" => -- 0x84 PCI trace count & mode
if apbi.pwrite = '1' then
av.atpt_trans.mode := apbi.pwdata(27 downto 24);
av.atpt_trans.tcount := apbi.pwdata(23 downto 16);
av.atpt_trans.count := apbi.pwdata(PT_DEPTH-1 downto 0);
end if;
prdata(31 downto 0) := x"0" & ar.atpt_trans.mode & ar.atpt_trans.tcount & zero32(15 downto PT_DEPTH) & ar.atpt_trans.count;
when "00010" => -- 0x88 PCI trace AD pattern
if apbi.pwrite = '1' then
av.atpt_trans.ad := apbi.pwdata;
end if;
prdata(31 downto 0) := ar.atpt_trans.ad;
when "00011" => -- 0x8c PCI trace AD mask
if apbi.pwrite = '1' then
av.atpt_trans.admask := apbi.pwdata;
end if;
prdata(31 downto 0) := ar.atpt_trans.admask;
when "00100" => -- 0x90 PCI trace Signal pattern
if apbi.pwrite = '1' then
av.atpt_trans.sig := apbi.pwdata(19 downto 3);
end if;
prdata(31 downto 0) := x"000" & ar.atpt_trans.sig & "000";
when "00101" => -- 0x94 PCI trace Signal mask
if apbi.pwrite = '1' then
av.atpt_trans.sigmask := apbi.pwdata(19 downto 3);
end if;
prdata(31 downto 0) := x"000" & ar.atpt_trans.sigmask & "000";
when "00110" => -- 0x98 PCI AD
prdata(31 downto 0) := ptta_trans.dbg_ad;
when "00111" => -- 0x9c PCI Ctrl signal
prdata(19 downto 0) := ptta_trans.dbg_sig & "000";
prdata(31 downto 16) := (others => '0');
when "01000" => -- 0xA0 tmp target cur addr
prdata(31 downto 0) := ptta_trans.dbg_cur_ad;
when "01001" => -- 0xA4 tmp target cur state
prdata(31 downto 8) := (others => '0');
prdata(8 downto 0) := ptta_trans.dbg_cur_acc;
when others =>
prdata(31 downto 0) := (others => '0');
end case;
end if;
end if;
apbo.pirq <= pirq;
apbo.prdata <= prdata;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
-- --------------------------------------------------------------------------------
-- APB DEBUG Slave
-- --------------------------------------------------------------------------------
tb_ren <= ar.s.tb_ren;
tb_addr <= ar.s.haddr;
tbpirq := (others => '0');
tbprdata := (others => '0');
tbapbaddr := tbapbi.paddr(6 downto 2);
if tbapben = 1 then
if (tbapbi.psel(tbpindex) and tbapbi.paddr(17)) = '1' then
tb_ren <= '1'; tb_addr <= tbapbi.paddr;
end if;
if (tbapbi.psel(tbpindex) and tbapbi.penable) = '1' then
if tbapbi.paddr(17) = '1' then
if tbapbi.paddr(16) = '0' then
tbprdata := pt_fifoo_ad.data;
else
tbprdata := zero32(31 downto 20) & pt_fifoo_sig.data(16 downto 0) & "000";
end if;
else
if tbapbi.paddr(7) = '0' then -- PCI core and DMA
case tbapbaddr is
when "01110" => -- 0x38 Reserved
--prdata(31 downto 0) := (others => '0');
tbprdata := ar.debug;
when "01111" => -- 0x3c Reserved
--prdata(31 downto 0) := (others => '0');
tbprdata := ar.debug_pr;
when others =>
tbprdata(31 downto 0) := (others => '0');
end case;
elsif tracebuffer /= 0 then -- PCI trace buffer enabled
case tbapbaddr is
when "00000" => -- 0x80 PCI trace control & status
if tbapbi.pwrite = '1' then
av.atpt_trans.start := ar.atpt_trans.start or tbapbi.pwdata(0);
av.atpt_trans.stop := ar.atpt_trans.stop or tbapbi.pwdata(1);
end if;
tbprdata(31 downto 0) := ar.apb_pt_stat;
when "00001" => -- 0x84 PCI trace count & mode
if tbapbi.pwrite = '1' then
av.atpt_trans.mode := tbapbi.pwdata(27 downto 24);
av.atpt_trans.tcount := tbapbi.pwdata(23 downto 16);
av.atpt_trans.count := tbapbi.pwdata(PT_DEPTH-1 downto 0);
end if;
tbprdata(31 downto 0) := x"0" & ar.atpt_trans.mode & ar.atpt_trans.tcount & zero32(15 downto PT_DEPTH) & ar.atpt_trans.count;
when "00010" => -- 0x88 PCI trace AD pattern
if tbapbi.pwrite = '1' then
av.atpt_trans.ad := tbapbi.pwdata;
end if;
tbprdata(31 downto 0) := ar.atpt_trans.ad;
when "00011" => -- 0x8c PCI trace AD mask
if tbapbi.pwrite = '1' then
av.atpt_trans.admask := tbapbi.pwdata;
end if;
tbprdata(31 downto 0) := ar.atpt_trans.admask;
when "00100" => -- 0x90 PCI trace Signal pattern
if tbapbi.pwrite = '1' then
av.atpt_trans.sig := tbapbi.pwdata(19 downto 3);
end if;
tbprdata(31 downto 0) := x"000" & ar.atpt_trans.sig & "000";
when "00101" => -- 0x94 PCI trace Signal mask
if tbapbi.pwrite = '1' then
av.atpt_trans.sigmask := tbapbi.pwdata(19 downto 3);
end if;
tbprdata(31 downto 0) := x"000" & ar.atpt_trans.sigmask & "000";
when "00110" => -- 0x98 PCI AD
tbprdata(31 downto 0) := ptta_trans.dbg_ad;
when "00111" => -- 0x9c PCI Ctrl signal
tbprdata(19 downto 0) := ptta_trans.dbg_sig & "000";
tbprdata(31 downto 16) := (others => '0');
when "01000" => -- 0xA0 tmp target cur addr
tbprdata(31 downto 0) := ptta_trans.dbg_cur_ad;
when "01001" => -- 0xA4 tmp target cur state
tbprdata(31 downto 8) := (others => '0');
tbprdata(8 downto 0) := ptta_trans.dbg_cur_acc;
when others =>
tbprdata(31 downto 0) := (others => '0');
end case;
end if;
end if;
end if;
tbapbo.pirq <= tbpirq;
tbapbo.prdata <= tbprdata;
tbapbo.pconfig <= tbpconfig;
tbapbo.pindex <= tbpindex;
else
tbapbo <= apb_none;
end if;
-- --------------------------------------------------------------------------------
-- AHB global signal assignments
-- --------------------------------------------------------------------------------
ahbso.hready <= ar.s.hready;
ahbso.hresp <= ar.s.hresp;
ahbso.hrdata <= ahbdrivedata(ar.s.hrdata);
ahbso.hindex <= hsindex;
ahbso.hconfig <= hconfig;
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
if master = 0 then
ahbso <= ahbs_none;
end if;
-- --------------------------------------------------------------------------------
-- AHB debug
-- --------------------------------------------------------------------------------
--[31:30] s_pending
--[29:28] s_empty
--[27:26] tm_pending
--[25:24] tm_empty
--[ :23] ms_acc_pending
--[ :22] ms_acc_cancel
--[ :21] ms_acc_done
--[ :20] tm_acc_pending
--[ :19] tm_acc_cancel
--[ :18] tm_acc_done
--[ :17] md_acc_pending
--[ :16] md_acc_cancel
--[ :15] md_acc_done
--[ :14] ..
--[13:12] dma_done
--[11:10] s_pending
--[ 9: 7] m_done
--[ 6: 4] dma.state
--[ 3: 2] m.state
--[ 1: 0] s.state
av.debug(31 downto 30) := ms_fifo_pending(1 downto 0);
av.debug(29 downto 28) := ms_fifo_empty(1 downto 0);
av.debug(27 downto 26) := tm_fifo_pending(1 downto 0);
av.debug(25 downto 24) := tm_fifo_empty(1 downto 0);
av.debug( 23) := ms_acc_pending;
av.debug( 22) := ms_acc_cancel;
av.debug( 21) := ms_acc_done;
av.debug( 20) := tm_acc_pending;
av.debug( 19) := tm_acc_cancel;
av.debug( 18) := tm_acc_done;
av.debug( 17) := md_acc_pending;
av.debug( 16) := md_acc_cancel;
av.debug( 15) := md_acc_done;
av.debug( 14) := '0';
av.debug(13 downto 12) := ar.dma.done;
av.debug(11 downto 10) := ar.s.pending;
av.debug( 9 downto 7) := ar.m.done;
case ar.dma.state is
when dma_idle => av.debug(6 downto 4) := "000";
when dma_read_desc => av.debug(6 downto 4) := "001";
when dma_next_channel => av.debug(6 downto 4) := "010";
when dma_write_status => av.debug(6 downto 4) := "011";
when dma_read => av.debug(6 downto 4) := "100";
when dma_write => av.debug(6 downto 4) := "101";
when dma_error => av.debug(6 downto 4) := "110";
end case;
case ar.m.state is
when am_idle => av.debug(3 downto 2) := "00";
when am_read => av.debug(3 downto 2) := "01";
when am_write => av.debug(3 downto 2) := "10";
when am_error => av.debug(3 downto 2) := "11";
when others => av.debug(3 downto 2) := "00";
end case;
case ar.s.state is
when as_idle => av.debug(1 downto 0) := "00";
when as_checkpcimst => av.debug(1 downto 0) := "01";
when as_read => av.debug(1 downto 0) := "10";
when as_write => av.debug(1 downto 0) := "11";
when others => av.debug(1 downto 0) := "00";
end case;
-- --------------------------------------------------------------------------------
-- AHB reset
-- --------------------------------------------------------------------------------
-- AHB master
lahbm_rst <= rst and not pci_target_rst and not pci_hard_rst;
if lahbm_rst = '0' then
av.m.state := am_idle;
av.m.acc.fifo_index := 0;
av.m.acc.pending := '0';
av.m.retry := '0';
av.m.dmai0.addr := (others => '0');
av.atp_trans.mstswdis := '0';
av.atp_trans.tm_acc_ack := '0';
av.atp_trans.tm_acc_cancel_ack := (others => '0');
av.atp_trans.tm_acc_done.done := '0';
for i in 0 to FIFO_COUNT-1 loop
av.atp_trans.tm_fifo(i).pending := (others => '0');
end loop;
av.atp_trans.tm_fifo_ack := (others => '0');
end if;
-- AHB slave
lahbs_rst <= rst and not pci_master_rst and not pci_hard_rst;
if lahbs_rst = '0' then
av.s.state := as_idle;
av.s.atp.index := 0;
av.s.pta.index := 0;
av.s.pending := (others => '0');
av.s.discard := '0';
av.s.start := '0';
av.s.cfg_bus := (others => '0');
av.s.cfg_status := (others => '0');
av.s.parerren := '0';
av.s.erren := '0';
av.s.blen := (others => '1');
av.s.blenmask := (others => '0');
av.s.io_cfg_burst := (others => '0');
av.s.fakehost := '0';
for i in 0 to 3 loop
av.s.accbuf(i).pending := '0';
end loop;
for j in 0 to FIFO_COUNT-1 loop
av.atp_trans.msd_fifo(0)(j).pending := (others => '0');
end loop;
av.atp_trans.msd_fifo_ack(0) := (others => '0');
av.atp_trans.msd_acc(0).pending := '0';
av.atp_trans.msd_acc_cancel(0) := '0';
av.atp_trans.msd_acc_done_ack(0) := '0';
for i in 0 to 15 loop
if multifunc = 0 then
av.s.atp_map(i)(2 downto 0) := "000";
else
for j in 0 to multifunc loop
if masters_vector(j)(i) = '1' then
av.s.atp_map(i)(2 downto 0) := conv_std_logic_vector(j, 3);
end if;
end loop;
end if;
end loop;
end if;
-- DMA
if lahbs_rst = '0' then
av.dma.state := dma_idle;
av.dma.en := '0';
av.dma.irq := '0';
av.dma.irqen := '0';
av.dma.irqstatus := (others => '0');
av.dma.errstatus := (others => '0');
av.dma.irqch := (others => '0');
av.dma.desc.chid := (others => '0');
av.dma.dtp.index := 0;
av.dma.ptd.index := 0;
for j in 0 to FIFO_COUNT-1 loop
av.atp_trans.msd_fifo(1)(j).pending := (others => '0');
end loop;
av.atp_trans.msd_fifo_ack(1) := (others => '0');
av.atp_trans.msd_acc(1).pending := '0';
av.atp_trans.msd_acc_cancel(1) := '0';
av.atp_trans.msd_acc_done_ack(1) := '0';
end if;
-- AHB reset
lahb_rst <= rst and not pci_hard_rst;
if lahb_rst = '0' then
if deviceirq = 1 then
av.irq.device_mask := conv_std_logic_vector(deviceirqmask, 4);
av.irq.device_force := '0';
end if;
if hostirq = 1 then
av.irq.host_mask := conv_std_logic_vector(hostirqmask, 4);
av.irq.host_status := (others => '0');
av.irq.host_pirq_vl := (others => '0');
end if;
av.irq.irqen := '0';
av.irq.access_en := '0';
av.irq.access_status := (others => '0');
av.irq.system_en := '0';
av.irq.system_status := (others => '0');
av.atp_trans.pa_serr_rst := '0';
av.atp_trans.pa_discardtout_rst := '0';
-- APB (PCI trace)
av.atpt_trans.start := '0';
av.atpt_trans.stop := '1';
-- Soft reset
av.atp_trans.rst(1 downto 0) := (others => '0');
end if;
if rst = '0' then
-- Hard reset
av.atp_trans.rst(2) := '0';
if iotest /= 0 then
av.debuga(5 downto 0) := "000000";
end if;
end if;
-- Disabled parts
if target = 0 then -- PCI targer disabled
av.m := amba_master_none;
av.atp_trans.tm_acc_ack := '0';
av.atp_trans.tm_acc_cancel_ack := (others => '0');
av.atp_trans.tm_acc_done := pci_g_acc_status_trans_none;
av.atp_trans.tm_fifo := pci_g_fifo_trans_vector_none;
av.atp_trans.tm_fifo_ack := pci_g_fifo_ack_trans_vector_none;
end if;
if master = 0 then -- PCI master disabled
av.s := amba_slave_none;
av.atp_trans.msd_acc(0) := pci_g_acc_trans_none;
av.atp_trans.msd_acc_cancel(0) := '0';
av.atp_trans.msd_acc_done_ack(0) := '0';
av.atp_trans.msd_fifo(0) := pci_g_fifo_trans_vector_none;
av.atp_trans.msd_fifo_ack(0) := pci_g_fifo_ack_trans_vector_none;
end if;
if dma = 0 then -- DMA disabled
av.dma := dma_reg_none;
av.atp_trans.msd_acc(1) := pci_g_acc_trans_none;
av.atp_trans.msd_acc_cancel(1) := '0';
av.atp_trans.msd_acc_done_ack(1) := '0';
av.atp_trans.msd_fifo(1) := pci_g_fifo_trans_vector_none;
av.atp_trans.msd_fifo_ack(1) := pci_g_fifo_ack_trans_vector_none;
end if;
if tracebuffer = 0 then -- PCI trace buffer disabled
av.atpt_trans := apb_to_pci_trace_trans_none;
end if;
-- --------------
arin <= av;
end process;
preg : process(pciclk, phyo)
begin
if rising_edge(pciclk) then
pr <= prin;
end if;
-- PHY =>
pr.po <= phyo.pr_po;
pr.m.state <= phyo.pr_m_state;
pr.m.last <= phyo.pr_m_last;
pr.m.hold <= phyo.pr_m_hold;
pr.m.term <= phyo.pr_m_term;
pr.t.hold <= phyo.pr_t_hold;
pr.t.stop <= phyo.pr_t_stop;
pr.t.abort <= phyo.pr_t_abort;
pr.t.diswithout <= phyo.pr_t_diswithout;
pr.t.addr_perr <= phyo.pr_t_addr_perr;
-- PHY <=
end process;
areg : process(clk)
begin
if rising_edge(clk) then ar <= arin; end if;
end process;
-- AHB master
target_ahbm0 : if target /= 0 generate
ahbm0 : grpci2_ahb_mst generic map (hindex => hmindex, devid => GAISLER_GRPCI2, version => REVISION)
port map (rst, clk, ahbmi, ahbmo_con, ar.m.dmai0, dmao0, disabled_dmai, open);
ahbmo <= ahbmo_con;
end generate;
no_target_ahbm0 : if target = 0 generate
ahbmo <= ahbm_none;
end generate;
dma_ahbm0 : if dma /= 0 generate
ahbm1 : grpci2_ahb_mst generic map (hindex => hdmindex, devid => GAISLER_GRPCI2_DMA, version => REVISION)
port map (rst, clk, ahbdmi, ahbdmo, ar.dma.dmai1, dmao1, disabled_dmai, open);
end generate;
no_dma_ahbm0 : if dma = 0 generate
ahbdmo <= ahbm_none;
end generate;
target_fifo0 : if target /= 0 generate
scan_prin_t_atp_ctrl_en <= (prin.t.atp.ctrl.en and not scanen);
scan_ar_m_acc_fifo_wen <= (ar.m.acc.fifo_wen and not scanen);
scan_arin_m_acc_fifo_ren <= (arin.m.acc.fifo_ren and not scanen);
scan_pr_t_pta_ctrl_en <= (pr.t.pta.ctrl.en and not scanen);
ft0 : if ft /= 0 generate
-- AHB master to PCI target FIFO
atp_fifo0 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_t_atp_ctrl_en, prin.t.atp.ctrl.addr, tm_fifoo_atp.data,
clk, scan_ar_m_acc_fifo_wen, ar.m.acc.fifo_addr, ar.m.acc.fifo_wdata,
tm_fifoo_atp.err, testin
);
-- PCI target to AHB master FIFO
pta_fifo0 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_m_acc_fifo_ren, arin.m.acc.fifo_addr, tm_fifoo_pta.data,
pciclk, scan_pr_t_pta_ctrl_en, pr.t.pta.ctrl.addr, pr.t.pta.ctrl.data,
tm_fifoo_pta.err, testin
);
-- AHB master to PCI target FIFO
end generate;
noft0 : if ft = 0 generate
atp_fifo0 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, testen => scantest,
custombits => memtest_vlen)
port map (pciclk, scan_prin_t_atp_ctrl_en, prin.t.atp.ctrl.addr, tm_fifoo_atp.data,
clk, scan_ar_m_acc_fifo_wen, ar.m.acc.fifo_addr, ar.m.acc.fifo_wdata,
testin
);
-- PCI target to AHB master FIFO
pta_fifo0 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, testen => scantest,
custombits => memtest_vlen)
port map (clk, scan_arin_m_acc_fifo_ren, arin.m.acc.fifo_addr, tm_fifoo_pta.data,
pciclk, scan_pr_t_pta_ctrl_en, pr.t.pta.ctrl.addr, pr.t.pta.ctrl.data,
testin
);
end generate;
end generate;
master_fifo0 : if master /= 0 generate
scan_prin_m_acc_acc_sel_ahb_fifo_ren <= (prin.m.acc(acc_sel_ahb).fifo_ren and not scanen);
scan_ar_s_atp_ctrl_en <= (ar.s.atp.ctrl.en and not scanen);
scan_arin_s_pta_ctrl_en <= (arin.s.pta.ctrl.en and not scanen);
scan_pr_m_acc_acc_sel_ahb_fifo_wen <= (pr.m.acc(acc_sel_ahb).fifo_wen and not scanen);
ft0 : if ft /= 0 generate
-- AHB slave to PCI master FIFO
atp_fifo1 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_m_acc_acc_sel_ahb_fifo_ren, prin.m.fifo_addr, ms_fifoo_atp.data,
clk, scan_ar_s_atp_ctrl_en, ar.s.atp.ctrl.addr, ar.s.atp.ctrl.data,
ms_fifoo_atp.err
);
-- PCI master to AHB slave FIFO
pta_fifo1 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_s_pta_ctrl_en, arin.s.pta.ctrl.addr, ms_fifoo_pta.data,
pciclk, scan_pr_m_acc_acc_sel_ahb_fifo_wen, pr.m.fifo_addr, pr.m.fifo_wdata,
ms_fifoo_pta.err
);
end generate;
noft0 : if ft = 0 generate
-- AHB slave to PCI master FIFO
atp_fifo1 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_m_acc_acc_sel_ahb_fifo_ren, prin.m.fifo_addr, ms_fifoo_atp.data,
clk, scan_ar_s_atp_ctrl_en, ar.s.atp.ctrl.addr, ar.s.atp.ctrl.data,
testin
);
-- PCI master to AHB slave FIFO
pta_fifo1 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_s_pta_ctrl_en, arin.s.pta.ctrl.addr, ms_fifoo_pta.data,
pciclk, scan_pr_m_acc_acc_sel_ahb_fifo_wen, pr.m.fifo_addr, pr.m.fifo_wdata,
testin
);
end generate;
end generate;
dma_fifo0 : if dma /= 0 generate
scan_prin_m_acc_acc_sel_dma_fifo_ren <= (prin.m.acc(acc_sel_dma).fifo_ren and not scanen);
scan_ar_dma_dtp_ctrl_en <= (ar.dma.dtp.ctrl.en and not scanen);
scan_arin_dma_ptd_ctrl_en <= (arin.dma.ptd.ctrl.en and not scanen);
scan_pr_m_acc_acc_sel_dma_fifo_wen <= (pr.m.acc(acc_sel_dma).fifo_wen and not scanen);
ft0 : if ft /= 0 generate
-- DMA to PCI master FIFO
dtp_fifo2 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_m_acc_acc_sel_dma_fifo_ren, prin.m.fifo_addr, md_fifoo_dtp.data,
clk, scan_ar_dma_dtp_ctrl_en, ar.dma.dtp.ctrl.addr, ar.dma.dtp.ctrl.data,
md_fifoo_dtp.err, testin
);
-- PCI master to DMA
ptd_fifo2 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_dma_ptd_ctrl_en, arin.dma.ptd.ctrl.addr, md_fifoo_ptd.data,
pciclk, scan_pr_m_acc_acc_sel_dma_fifo_wen, pr.m.fifo_addr, pr.m.fifo_wdata,
md_fifoo_dtp.err, testin
);
end generate;
noft0 : if ft = 0 generate
-- DMA to PCI master FIFO
dtp_fifo2 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_m_acc_acc_sel_dma_fifo_ren, prin.m.fifo_addr, md_fifoo_dtp.data,
clk, scan_ar_dma_dtp_ctrl_en, ar.dma.dtp.ctrl.addr, ar.dma.dtp.ctrl.data,
testin
);
-- PCI master to DMA
ptd_fifo2 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_dma_ptd_ctrl_en, arin.dma.ptd.ctrl.addr, md_fifoo_ptd.data,
pciclk, scan_pr_m_acc_acc_sel_dma_fifo_wen, pr.m.fifo_addr, pr.m.fifo_wdata,
testin
);
end generate;
end generate;
-- PCI trace
trace_fifo0 : if tracebuffer /= 0 generate
scan_tb_ren <= (tb_ren and not scanen);
scan_pr_ptta_trans_enable <= (pr.ptta_trans.enable and not scanen);
pt_fifo0 : syncram_2p generic map (tech => tbmemtech, abits => PT_DEPTH, dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_tb_ren, tb_addr(PT_DEPTH+1 downto 2), pt_fifoo_ad.data,
pciclk, scan_pr_ptta_trans_enable, pr.pt.addr, pi.ad,
testin
);
pt_fifoo_ad.err <= (others => '0');
pt_fifo1 : syncram_2p generic map (tech => tbmemtech, abits => PT_DEPTH, dbits => 17, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_tb_ren, tb_addr(PT_DEPTH+1 downto 2), pt_fifoo_sig.data(16 downto 0),
pciclk, scan_pr_ptta_trans_enable, pr.pt.addr, pcisig,
testin
);
pt_fifoo_sig.err <= (others => '0');
end generate;
-- IO test module
iotgen : if iotest /= 0 generate
iotm : synciotest
generic map (ninputs => 2, noutputs => 1, nbidir => 44)
port map (
clk => pciclk,
rstn => pcii.rst,
datain => iotmdin,
dataout => iotmdout,
tmode => ar.debuga(5 downto 0),
tmodeact => iotmact,
tmodeoe => iotmoe
);
end generate;
iotngen : if iotest = 0 generate
iotmdout <= (others => '0');
iotmact <= '0';
iotmoe <= '0';
end generate;
--pragma translate_off
bootmsg : report_version
generic map ("grpci2" & tost(hmindex) &
": 32-bit PCI/AHB bridge rev, " & tost(REVISION) &
", " & tost(2**FIFO_DEPTH) & "-word FIFOs" & ", PCI trace: " & tost(((2**PT_DEPTH)*conv_integer(conv_std_logic(tracebuffer/=0)))));
--pragma translate_on
end;
|
gpl-2.0
|
4ba45a75fb553f8825556b9827ad04ae
| 0.517556 | 3.1314 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/cycloneiii/ddr_phy_cycloneiii.vhd
| 4 | 14,518 |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- CYCLONEIII DDR PHY --------------------------------------------
------------------------------------------------------------------
entity cycloneiii_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of cycloneiii_ddr_phy is
component apll IS
generic (
freq : integer := 200;
mult : integer := 8;
div : integer := 5;
rskew : integer := 0
);
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
phasestep : IN STD_LOGIC := '0';
phaseupdown : IN STD_LOGIC := '0';
scanclk : IN STD_LOGIC := '1';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC;
phasedone : out std_logic
);
END component;
component aclkout is
port(
clk : in std_logic;
ddr_clk : out std_logic;
ddr_clkn: out std_logic
);
end component;
component actrlout is
generic(
power_up : string := "high"
);
port(
clk : in std_logic;
i : in std_logic;
o : out std_logic
);
end component;
component adqsout is
port(
clk : in std_logic; -- clk90
dqs : in std_logic;
dqs_oe : in std_logic;
dqs_oct : in std_logic; -- gnd = disable
dqs_pad : out std_logic; -- DQS pad
dqsn_pad : out std_logic -- DQSN pad
);
end component;
component adqsin is
port(
dqs_pad : in std_logic; -- DQS pad
dqsn_pad : in std_logic; -- DQSN pad
dqs : out std_logic
);
end component;
component admout is
port(
clk : in std_logic; -- clk0
dm_h : in std_logic;
dm_l : in std_logic;
dm_pad : out std_logic -- DQ pad
);
end component;
component adqin is
port(
clk : in std_logic;
dq_pad : in std_logic; -- DQ pad
dq_h : out std_logic;
dq_l : out std_logic;
config_clk : in std_logic;
config_clken : in std_logic;
config_datain : in std_logic;
config_update : in std_logic
);
end component;
component adqout is
port(
clk : in std_logic; -- clk0
clk_oct : in std_logic; -- clk90
dq_h : in std_logic;
dq_l : in std_logic;
dq_oe : in std_logic;
dq_oct : in std_logic; -- gnd = disable
dq_pad : out std_logic -- DQ pad
);
end component;
signal reset : std_logic;
signal vcc, gnd, oe : std_ulogic;
signal locked, vlockl, lockl : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r, rclk : std_ulogic;
signal ckel, ckel2 : std_logic_vector(1 downto 0);
signal dqsin, dqsin_reg : std_logic_vector (7 downto 0); -- ddr dqs
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal dqsoenr : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal delayrst : std_logic_vector(3 downto 0);
signal phasedone : std_logic;
signal dqinl,dqinl2,dqinl3 : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqsin_tmp : std_logic;
type phy_r_type is record
delay : std_logic_vector(3 downto 0);
count : std_logic_vector(3 downto 0);
update : std_logic;
sdata : std_logic;
enable : std_logic;
update_delay : std_logic;
end record;
type phy_r_type_arr is array (7 downto 0) of phy_r_type;
signal r,rin : phy_r_type_arr;
signal rp : std_logic_vector(3 downto 0);
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
attribute syn_keep of dqsoenr : signal is true;
attribute syn_preserve of dqsoenr : signal is true;
attribute syn_keep of dqsin_reg : signal is true;
attribute syn_preserve of dqsin_reg : signal is true;
begin
-----------------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------------
oe <= not oen;
vcc <= '1'; gnd <= '0';
reset <= not rst;
ddr_clk_fb_out <= '0';
-- Optional DDR clock multiplication
pll0 : apll
generic map(
freq => MHz,
mult => clk_mul,
div => clk_div,
rskew => rskew
)
port map(
areset => reset,
inclk0 => clk,
phasestep => rp(1),
phaseupdown => rp(3),
scanclk => clk0r,
c0 => clk0r,
c1 => clk90r,
c2 => open, --clk180r,
c3 => open, --clk270r,
c4 => rclk,
locked => lockl,
phasedone => phasedone
);
clk180r <= not clk0r;
clk270r <= not clk90r;
clkout <= clk0r;
-----------------------------------------------------------------------------------
-- Lock delay
-----------------------------------------------------------------------------------
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
-- cnt(0) := dqsin_reg(7) or dqsin_reg(6) or dqsin_reg(5) or dqsin_reg(4) or -- dummy use of dqsin
-- dqsin_reg(3) or dqsin_reg(2) or dqsin_reg(1) or dqsin_reg(0);
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-----------------------------------------------------------------------------------
-- Generate external DDR clock
-----------------------------------------------------------------------------------
ddrclocks : for i in 0 to 2 generate
ddrclk_pad : aclkout port map(clk => clk90r, ddr_clk => ddr_clk(i), ddr_clkn => ddr_clkb(i));
end generate;
-----------------------------------------------------------------------------------
-- DDR single-edge control signals
-----------------------------------------------------------------------------------
-- CSN and CKE
ddrbanks : for i in 0 to 1 generate
ddr_csn_pad : actrlout port map(clk =>clk180r , i => csn(i), o => ddr_csb(i));
ckel(i) <= cke(i) and locked;
ddr_cke_pad : actrlout generic map(power_up => "low")
port map(clk =>clk0r , i => ckel(i), o => ddr_cke(i));
end generate;
-- RAS
ddr_rasn_pad : actrlout port map(clk =>clk180r , i => rasn, o => ddr_rasb);
-- CAS
ddr_casn_pad : actrlout port map(clk =>clk180r , i => casn, o => ddr_casb);
-- WEN
ddr_wen_pad : actrlout port map(clk =>clk180r , i => wen, o => ddr_web);
-- BA
bagen : for i in 0 to 1 generate
ddr_ba_pad : actrlout port map(clk =>clk180r , i => ba(i), o => ddr_ba(i));
end generate;
-- ADDRESS
dagen : for i in 0 to 13 generate
ddr_ad_pad : actrlout port map(clk =>clk180r , i => addr(i), o => ddr_ad(i));
end generate;
-----------------------------------------------------------------------------------
-- DQS generation
-----------------------------------------------------------------------------------
dqsgen : for i in 0 to dbits/8-1 generate
doen : process(clk180r)
begin if rising_edge(clk180r) then dqsoenr(i) <= dqsoen; end if; end process;
dsqreg : process(clk180r)
begin if rising_edge(clk180r) then dqsn(i) <= oe; end if; end process;
dqs_out_pad : adqsout port map(
clk => clk90r, -- clk90
dqs => dqsn(i),
dqs_oe => dqsoenr(i),
dqs_oct => gnd, -- gnd = disable
dqs_pad => ddr_dqs(i) -- DQS pad
);
-- dqs_in_pad : adqsin port map(
-- dqs_pad => ddr_dqs(i),
-- dqsn_pad => ddr_dqsn(i),
-- dqs => dqsin(i)
-- );
-- -- Dummy procces to sample dqsin
-- process(clk0r)
-- begin
-- if rising_edge(clk0r) then
-- dqsin_reg(i) <= dqsin(i);
-- end if;
-- end process;
end generate;
-----------------------------------------------------------------------------------
-- DQM generation
-----------------------------------------------------------------------------------
dmgen : for i in 0 to dbits/8-1 generate
ddr_dm_pad : admout port map(
clk => clk0r, -- clk0
dm_h => dm(i+dbits/8),
dm_l => dm(i),
dm_pad => ddr_dm(i) -- DQ pad
);
end generate;
-----------------------------------------------------------------------------------
-- Data bus
-----------------------------------------------------------------------------------
ddgen : for i in 0 to dbits-1 generate
-- DQ Input
dq_in_pad : adqin port map(
clk => rclk,--clk0r,
dq_pad => ddr_dq(i), -- DQ pad
dq_h => dqin(i), --dqinl(i),
dq_l => dqin(i+dbits),--dqin(i),
config_clk => clk0r,
config_clken => r(i/8).enable,--io_config_clkena,
config_datain => r(i/8).sdata,--io_config_datain,
config_update => r(i/8).update_delay--io_config_update
);
--dinq1 : process (clk0r)
--begin if rising_edge(clk0r) then dqin(i+dbits) <= dqinl(i); end if; end process;
-- DQ Output
dq_out_pad : adqout port map(
clk => clk0r, -- clk0
clk_oct => clk90r, -- clk90
dq_h => dqout(i+dbits),
dq_l => dqout(i),
dq_oe => oen,
dq_oct => gnd, -- gnd = disable
dq_pad => ddr_dq(i) -- DQ pad
);
end generate;
-----------------------------------------------------------------------------------
-- DEBUG
-----------------------------------------------------------------------------------
--debug(66 downto 59) <= dqsin_reg(7 downto 0);
--debug(58 downto 27) <= dqinl3(15 downto 0) & dqinl2(15 downto 0);
--debug(26 downto 25) <= dm(1 downto 0);
--debug(24 downto 11) <= addr(13 downto 0);
--debug(10) <= wen;
--debug(9) <= casn;
--debug(8) <= rasn;
----debug(7 downto 0);
--debug(3) <= rasn and not wen and not casn; -- write
--debug(2) <= rasn and wen and not casn; -- read
--debug(1) <= not rasn and wen and casn; -- act
--debug(0) <= clk0r;
-----------------------------------------------------------------------------------
-- Delay control
-----------------------------------------------------------------------------------
-- delay_control : for i in 0 to dbits/8-1 generate
-- process(r(i),cal_en(i), cal_inc(i), delayrst(3))
-- variable v : phy_r_type;
-- variable data : std_logic_vector(0 to 3);
-- begin
-- v := r(i);
-- data := r(i).delay;
-- v.update_delay := '0';
-- if cal_en(i) = '1' then
-- if cal_inc(i) = '1' then
-- v.delay := r(i).delay + 1;
-- else
-- v.delay := r(i).delay - 1;
-- end if;
-- v.update := '1';
-- v.count := (others => '0');
-- end if;
--
-- if r(i).update = '1' then
-- v.enable := '1';
-- v.sdata := '0';
--
-- if r(i).count <= "1011" then
-- v.count := r(i).count + 1;
-- end if;
--
-- if r(i).count <= "0011" then
-- v.sdata := data(conv_integer(r(i).count));
-- end if;
--
-- if r(i).count = "1011" then
-- v.update_delay := '1';
-- v.enable := '0';
-- v.update := '0';
-- end if;
-- end if;
--
-- if delayrst(3) = '0' then
-- v.delay := (others => '0');
-- v.count := (others => '0');
-- v.update := '0';
-- v.enable := '0';
-- end if;
--
-- rin(i) <= v;
-- end process;
--
-- end generate;
-- process(clk0r)
-- begin
-- if locked = '0' then
-- delayrst <= (others => '0');
-- elsif rising_edge(clk0r) then
-- delayrst <= delayrst(2 downto 0) & '1';
-- r <= rin;
-- -- PLL phase config
-- rp(0) <= cal_pll(0); rp(1) <= cal_pll(0) or rp(0);
-- rp(2) <= cal_pll(1); rp(3) <= cal_pll(1) or rp(2);
-- end if;
-- end process;
end;
|
gpl-2.0
|
0ce2a2b0be97e66e0bf08542f6e5c2d7
| 0.465147 | 3.444365 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/sim/ddr2ram.vhd
| 1 | 23,261 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2ram
-- File: ddr2ram.vhd
-- Author: Magnus Hjorth, Aeroflex Gaisler
-- Description: Generic simulation model of DDR2 SDRAM (JESD79-2C)
------------------------------------------------------------------------------
--pragma translate_off
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdio.hread;
use grlib.stdlib.all;
entity ddr2ram is
generic (
width: integer := 32;
abits: integer range 13 to 16 := 13;
babits: integer range 2 to 3 := 3;
colbits: integer range 9 to 11 := 9;
rowbits: integer range 1 to 16 := 13;
implbanks: integer range 1 to 8 := 1;
swap : integer := 0; -- byte swap during srec load
fname: string;
lddelay: time := (0 ns);
ldguard: integer range 0 to 1 := 0; -- 1: wait for doload input before
-- loading RAM
-- Speed bins: 0:DDR2-400C,1:400B,2:533C,3:533B,4:667D,5:667C,6:800E,7:800D,8:800C
-- 9:800+ (MT47H-25E)
speedbin: integer range 0 to 9 := 0;
density: integer range 1 to 5 := 3; -- 1:256M 2:512M 3:1G 4:2G 5:4G bits/chip
pagesize: integer range 1 to 2 := 1 -- 1K/2K page size (controls tRRD)
);
port (
ck: in std_ulogic;
ckn: in std_ulogic;
cke: in std_ulogic;
csn: in std_ulogic;
odt: in std_ulogic;
rasn: in std_ulogic;
casn: in std_ulogic;
wen: in std_ulogic;
dm: in std_logic_vector(width/8-1 downto 0);
ba: in std_logic_vector(babits-1 downto 0);
a: in std_logic_vector(abits-1 downto 0);
dq: inout std_logic_vector(width-1 downto 0);
dqs: inout std_logic_vector(width/8-1 downto 0);
dqsn: inout std_logic_vector(width/8-1 downto 0);
doload: in std_ulogic := '1'
);
end;
architecture sim of ddr2ram is
type moderegs is record
-- Mode register (0)
pd: std_ulogic;
wr: std_logic_vector(2 downto 0);
dllres: std_ulogic;
tm: std_ulogic;
caslat: std_logic_vector(2 downto 0);
bt: std_ulogic;
blen: std_logic_vector(2 downto 0);
-- Extended mode register 1
qoff: std_ulogic;
rdqsen: std_ulogic;
dqsndis: std_ulogic;
ocdprog: std_logic_vector(2 downto 0);
al: std_logic_vector(2 downto 0);
rtt: std_logic_vector(1 downto 0);
ds: std_ulogic;
dlldis: std_ulogic;
-- Extended mode register 2
srf: std_ulogic;
dccen: std_ulogic;
pasr: std_logic_vector(2 downto 0);
-- Extended mode register 3
emr3: std_logic_vector(abits-1 downto 0);
end record;
-- Mode registers as signal, useful for debugging
signal mr: moderegs;
-- Handshaking between command and DQ/DQS processes
signal read_en, write_en: boolean := false;
signal read_data, write_data: std_logic_vector(2*width-1 downto 0);
signal write_mask: std_logic_vector(width/4-1 downto 0);
signal initdone: boolean := false;
-- Small delta-t to adjust calculations for jitter tol.
constant deltat: time := 50 ps;
-- Timing parameters
constant tWR: time := 15 ns;
constant tMRD_ck: integer := 2;
constant tRTP: time := 7.5 ns;
type timetab is array (0 to 9) of time;
-- 400C 400B 533C 533B 667D 667C 800E 800D 800C MT-2.5E
constant tRAS : timetab := (45 ns, 40 ns, 45 ns, 45 ns, 45 ns, 45 ns, 45 ns, 45 ns, 45 ns, 40 ns);
constant tRP : timetab := (20 ns, 15 ns, 15 ns, 11.25 ns, 15 ns, 12 ns, 15 ns, 12.5 ns, 10 ns, 12.5 ns);
constant tRCD: timetab := tRP;
type timetab2 is array(1 to 5) of time;
constant tRFC: timetab2 := (75 ns, 105 ns, 127.5 ns, 195 ns, 327.5 ns);
type timetab3 is array(1 to 2) of time;
constant tRRD: timetab3 := (7.5 ns, 10 ns);
begin
-----------------------------------------------------------------------------
-- Init sequence checker
-----------------------------------------------------------------------------
initp: process
variable cyctr: integer := 0;
procedure checkcmd(crasn,ccasn,cwen: std_ulogic;
cba: std_logic_vector(1 downto 0);
ca: std_logic_vector(15 downto 0)) is
variable amatch: boolean;
begin
wait until rising_edge(ck);
cyctr := cyctr+1;
while cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')) loop
wait until rising_edge(ck);
cyctr := cyctr+1;
end loop;
amatch := true;
for x in a'range loop
if ca(x)/='-' and ca(x)/=a(x) then amatch:=false; end if;
end loop;
assert cke='1' and csn='0' and rasn=crasn and casn=ccasn and wen=cwen and
(cba="--" or cba=ba(1 downto 0)) and amatch
report "Wrong command during init sequence" severity warning;
end checkcmd;
variable t: time;
begin
initdone <= false;
-- Allow cke to be X or U for a while during sim start
if is_x(cke) then
wait until not is_x(cke);
end if;
assert cke='0' report "CKE not deasserted on power-up" severity warning;
wait until cke/='0' for 200 us;
assert cke='0' report "CKE raised with less than 200 us init delay" severity warning;
wait until cke/='0' and rising_edge(ck);
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
t := now;
-- Precharge all
checkcmd('0','1','0',"--","-----1----------");
assert (now-t) > 400 ns report "Less than 400 ns wait period after CKE high!" severity warning;
-- EMRS EMR2
checkcmd('0','0','0',"10","----------------");
-- EMRS EMR3
checkcmd('0','0','0',"11","----------------");
-- EMRS enable DLL
checkcmd('0','0','0',"01","000---000-------");
-- MRS reset DLL
checkcmd('0','0','0',"00","000----1--------");
cyctr := 0;
-- Precharge all
checkcmd('0','1','0',"--","-----1----------");
-- 2 x auto refresh
checkcmd('0','0','1',"--","----------------");
checkcmd('0','0','1',"--","----------------");
-- MRS !reset DLL
checkcmd('0','0','0',"00","-------0--------");
-- EMRS EMR1 OCD default, EMRS EMR1 exit OCD cal
-- (assume OCD impedance adjust not performed)
checkcmd('0','0','0',"01","------111-------");
assert cyctr >= 200 report "Less than 200 cycles (" & tost(cyctr) & ") between DLL reset and OCD cal" severity warning;
checkcmd('0','0','0',"01","------000-------");
initdone <= true;
wait;
end process;
-----------------------------------------------------------------------------
-- Command state machine
-----------------------------------------------------------------------------
cmdp: process(ck)
subtype coldata is std_logic_vector(width-1 downto 0);
type coldata_arr is array(0 to implbanks*(2**(colbits+rowbits))-1) of coldata;
variable memdata: coldata_arr;
procedure load_srec is
file TCF : text open read_mode is fname;
variable L1: line;
variable CH : character;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable recdatatemp : std_logic_vector(0 to 7);
variable col, coloffs, len: integer;
begin
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := to_integer(unsigned(reclen))-1;
recaddr := (others => '0');
case rectype is
when "0001" => hread(L1, recaddr(15 downto 0)); len := len - 2;
when "0010" => hread(L1, recaddr(23 downto 0)); len := len - 3;
when "0011" => hread(L1, recaddr); len := len - 4;
when others => next;
end case;
hread(L1, recdata(0 to len*8-1));
if swap=1 then -- byte swap during srec load
for i in 0 to 7 loop
recdatatemp := recdata(i*16 to i*16+7);
recdata(i*16 to i*16+7) := recdata(i*16+8 to i*16+15);
recdata(i*16+8 to i*16+15) := recdatatemp;
end loop;
end if;
col := to_integer(unsigned(recaddr(log2(width/8)+rowbits+colbits+1 downto log2(width/8))));
coloffs := 8*to_integer(unsigned(recaddr(log2(width/8)-1 downto 0)));
while len > width/8 loop
assert coloffs=0;
memdata(col) := recdata(0 to width-1);
col := col+1;
len := len-width/8;
recdata(0 to recdata'length-width-1) := recdata(width to recdata'length-1);
end loop;
memdata(col)(width-1-coloffs downto width-coloffs-len*8) := recdata(0 to len*8-1);
end if;
end if;
end if;
end loop;
end load_srec;
variable vmr: moderegs;
type bankstate is record
openrow: integer;
opentime: time;
closetime: time;
writetime: time;
readtime: time;
autopch: integer;
pchpush: boolean;
end record;
type bankstate_arr is array(natural range <>) of bankstate;
variable banks: bankstate_arr(7 downto 0) := (others => (-1, 0 ns, 0 ns, 0 ns, 0 ns, -1, false));
type int_arr is array(natural range <>) of integer;
type dataacc is record
r,w: boolean;
col: int_arr(0 to 1);
bank: integer;
end record;
type dataacc_arr is array(natural range <>) of dataacc;
variable accpipe: dataacc_arr(0 to 9);
variable cmd: std_logic_vector(2 downto 0);
variable bank: integer;
variable colv: unsigned(a'high-1 downto 0);
variable alow: unsigned(2 downto 0);
variable col: integer;
variable prev_re, re: time;
variable blen: integer;
variable lastref: time := 0 ns;
variable i, al, cl, wrap: integer;
variable b: boolean;
variable mrscount: integer := 0;
variable loaded: boolean := false;
procedure checktime(got, exp: time; gt: boolean; req: string) is
begin
assert (got + deltat > exp and gt) or (got-deltat < exp and not gt)
report (req & " violation, got: " & tost(got/(1 ps)) & " ps, exp: " & tost(exp/(1 ps)) & "ps")
severity warning;
end checktime;
begin
if rising_edge(ck) then
-- Update pipe regs
prev_re := re;
re := now;
accpipe(1 to accpipe'high) := accpipe(0 to accpipe'high-1);
accpipe(0).r:=false; accpipe(0).w:=false;
-- Parse MR fields
cmd := rasn & casn & wen;
if is_x(vmr.caslat) then cl:=0; else cl:=to_integer(unsigned(vmr.caslat)); end if;
if cl<2 or cl>6 then cl:=0; end if;
if is_x(vmr.al) then al:=0; else al:=to_integer(unsigned(vmr.al)); end if;
if al>5 then al:=0; end if;
if is_x(vmr.wr) then wrap:=0; else wrap:=1+to_integer(unsigned(vmr.wr)); end if;
if wrap<2 or wrap>6 then wrap:=0; end if;
-- Checks for all-bank commands
if mrscount > 0 then
mrscount := mrscount-1;
assert cke='1' and (csn='1' or cmd="111") report "tMRS violation!" severity warning;
end if;
if cke='1' and csn='0' and cmd/="111" then
checktime(now-lastref, tRFC(density), true, "tRFC");
end if;
-- Main command handler
if cke='1' and csn='0' then
case cmd is
when "111" => -- NOP
when "011" => -- RAS
assert initdone report "Opening row before init sequence done!" severity warning;
bank := to_integer(unsigned(ba));
assert banks(bank).openrow < 0
report "Row already open" severity warning;
checktime(now-banks(bank).closetime, tRP(speedbin), true, "tRP");
for x in 0 to 7 loop
checktime(now-banks(x).opentime, tRRD(pagesize), true, "tRRD");
end loop;
banks(bank).openrow := to_integer(unsigned(a(rowbits-1 downto 0)));
banks(bank).opentime := now;
when "101" | "100" => -- Read/Write
bank := to_integer(unsigned(ba));
-- Get additive latency
i := to_integer(unsigned(vmr.al));
assert banks(bank).openrow >= 0
report "Row not open" severity error;
checktime(now-banks(bank).opentime+al*(re-prev_re), tRCD(speedbin), true, "tRCD");
-- Allow interrupting read in case of middle of BL8 burst only
if (accpipe(3).r and accpipe(2).r and
not (accpipe(1).r or accpipe(1).w or accpipe(0).r or accpipe(0).w)) then
accpipe(3).r := false;
accpipe(2).r := false;
end if;
for x in 0 to 3 loop
assert not accpipe(x).r and not accpipe(x).w;
end loop;
if cmd(0)='1' then accpipe(3).r:=true; else accpipe(3).w:=true; end if;
colv := unsigned(std_logic_vector'(a(a'high downto 11) & a(9 downto 0)));
case vmr.blen is
when "010" => blen := 4;
when "011" => blen := 8;
when others => assert false report "Invalid burst length setting in MR!" severity error;
end case;
alow := unsigned(a(2 downto 0));
for x in 0 to blen-1 loop
accpipe(3-x/2).bank := bank;
if cmd(0)='1' then accpipe(3-x/2).r:=true; else accpipe(3-x/2).w:=true; end if;
if vmr.bt='0' then -- Sequential
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) + x;
else -- Interleaved
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) xor to_unsigned(x,log2(blen));
end if;
col := to_integer(unsigned(ba))*(2**(colbits+rowbits)) +
banks(bank).openrow * (2**colbits) + to_integer(colv(colbits-1 downto 0));
accpipe(3-x/2).col(x mod 2) := col;
end loop;
-- Auto precharge
if a(10)='1' then
if cmd(0)='1' then
banks(bank).autopch := al+blen/2;
else
banks(bank).autopch := cl+al-1+blen/2+wrap;
end if;
banks(bank).pchpush := true;
end if;
when "110" => -- Reserved (Burst terminate on DDR1)
assert false report "Invalid command RAS=1 CAS=1 WE=0" severity warning;
when "010" => -- Precharge
if a(10)='0' then bank := to_integer(unsigned(ba)); else bank:=0; end if;
for x in 3 downto 0 loop -- FIXME potential window which isn't checked if AL>0
assert (not (accpipe(x).r or accpipe(x).w)) or (a(10)='0' and bank/=accpipe(x).bank)
report "Precharging bank with access in progress"
severity warning;
end loop;
for x in 0 to (2**babits)-1 loop
if a(10)='1' or ba=std_logic_vector(to_unsigned(x,babits)) then
assert banks(x).autopch<0
report "Precharging bank that is auto-precharged!" severity note;
assert a(10)='1' or banks(x).openrow >= 0
report "Precharging single bank that is in idle state!" severity note;
banks(x).autopch := 0; -- Handled below case statement
banks(x).pchpush := false;
end if;
end loop;
when "001" => -- Auto refresh
for x in 0 to 7 loop
assert banks(x).openrow < 0
report "Bank in wrong state for auto refresh!" severity warning;
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
lastref := now;
when "000" => -- MRS
for x in 0 to 7 loop
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
bank := to_integer(unsigned(ba));
case bank is
when 0 =>
vmr.pd := a(12);
vmr.wr := a(11 downto 9);
vmr.dllres := a(8);
vmr.tm := a(7);
vmr.caslat := a(6 downto 4);
vmr.bt := a(3);
vmr.blen := a(2 downto 0);
when 1 =>
vmr.qoff := a(12);
vmr.rdqsen := a(11);
vmr.dqsndis := a(10);
vmr.ocdprog := a(9 downto 7);
vmr.al := a(5 downto 3);
vmr.rtt := a(6) & a(2);
vmr.ds := a(1);
vmr.dlldis := a(0);
when 2 =>
vmr.srf := a(7);
vmr.dccen := a(3);
vmr.pasr := a(2 downto 0);
when 3 =>
vmr.emr3 := a;
when others =>
assert false report ("MRS to invalid bank addr: " & std_logic'image(ba(1)) & std_logic'image(ba(0))) severity warning;
end case;
mrscount := tMRD_ck-1;
when others =>
assert false report ("Invalid command: " & std_logic'image(rasn) & std_logic'image(casn) & std_logic'image(wen)) severity warning;
end case;
end if;
-- Manual or auto precharge handling
for x in 0 to 7 loop
if banks(x).autopch=0 then
if banks(x).pchpush and (now-banks(x).opentime-deltat) < tRAS(speedbin) then
-- Auto delay auto-precharge to satisfy tRAS/tRC
banks(x).autopch := banks(x).autopch+1;
elsif banks(x).pchpush and (now-banks(x).readtime-deltat) < tRTP then
-- Auto delay auto-precharge to satisfy tRTP
banks(x).autopch := banks(x).autopch+1;
else
checktime(now-banks(x).writetime, tWR, true, "tWR");
checktime(now-banks(x).opentime, tRAS(speedbin), true, "tRAS");
checktime(now-banks(x).readtime, tRTP, true, "tRTP");
banks(x).openrow := -1;
banks(x).closetime := now;
end if;
end if;
if banks(x).autopch >= 0 then
banks(x).autopch := banks(x).autopch - 1;
end if;
end loop;
-- Read/write management
if not loaded and lddelay < now and (ldguard=0 or doload='1') then
load_srec;
loaded := true;
end if;
if accpipe(2+cl+al).r then
assert cl>1 report "Incorrect CL setting!" severity warning;
read_en <= true;
-- print("Reading from col " & tost(accpipe(2+i).col(0)) & " and " & tost(accpipe(2+i).col(1)));
-- col0 <= accpipe(2+i).col(0); col1 <= accpipe(2+i).col(1);
read_data <= memdata(accpipe(2+cl+al).col(0)) & memdata(accpipe(2+cl+al).col(1));
else
read_en <= false;
end if;
-- tRTP is counted from read command + AL for BL4, read command + AL + 2
-- for BL8. This check covers both cases by writing readtime on the next-to-last
-- transfer.
if accpipe(3+al).r and accpipe(2+al).r and accpipe(3+al).bank=accpipe(2+al).bank then
banks(accpipe(2+al).bank).readtime := now;
end if;
write_en <= accpipe(1+cl+al).w or accpipe(2+cl+al).w;
if accpipe(3+cl+al).w then
assert not is_x(write_mask) report "Write error!";
for x in 0 to 1 loop
for b in width/8-1 downto 0 loop
if write_mask((1-x)*width/8+b)='0' then
memdata(accpipe(3+cl+al).col(x))(8*b+7 downto 8*b) :=
write_data( (1-x)*width+b*8+7 downto (1-x)*width+b*8);
end if;
end loop;
end loop;
banks(accpipe(3+cl+al).bank).writetime := now;
end if;
end if;
mr <= vmr;
end process;
-----------------------------------------------------------------------------
-- DQS/DQ handling and data sampling process
-----------------------------------------------------------------------------
dqproc: process
variable rdata: std_logic_vector(2*width-1 downto 0);
variable hdata: std_logic_vector(width-1 downto 0);
variable hmask: std_logic_vector(width/8-1 downto 0);
variable prevdqs: std_logic_vector(width/8-1 downto 0);
begin
dq <= (others => 'Z');
dqs <= (others => 'Z');
dqsn <= (others => 'Z');
wait until read_en or write_en;
assert not (read_en and write_en);
if read_en then
dqs <= (others => '0');
dqsn <= (others => '1');
wait until falling_edge(ck);
while read_en loop
rdata := read_data;
wait until rising_edge(ck);
dqs <= (others => '1');
dqsn <= (others => '0');
dq <= rdata(2*width-1 downto width);
wait until falling_edge(ck);
dqs <= (others => '0');
dqsn <= (others => '1');
dq <= rdata(width-1 downto 0);
end loop;
wait until rising_edge(ck);
else
wait until falling_edge(ck);
assert (to_X01(dqs)=(dqs'range => '0')) or ((to_X01(dqs)=(dqs'range => '1')) and (to_X01(dm)=(dm'range => '1') or dm=(dm'range => 'Z')));
while write_en loop
prevdqs := to_X01(dqs);
wait until to_X01(dqs) /= prevdqs or not write_en or rising_edge(ck);
if rising_edge(ck) then
write_data <= (others => 'X');
write_mask <= (others => 'X');
end if;
for x in dqs'range loop
if prevdqs(x)='0' and to_X01(dqs(x))='1' then
hdata(8*x+7 downto 8*x) := dq(8*x+7 downto 8*x);
hmask(x) := dm(x);
elsif prevdqs(x)='1' and to_X01(dqs(x))='0' then
write_data(width+8*x+7 downto width+8*x) <= hdata(8*x+7 downto 8*x);
write_data(8*x+7 downto 8*x) <= dq(8*x+7 downto 8*x);
write_mask(width/8+x) <= hmask(x);
write_mask(x) <= dm(x);
end if;
end loop;
end loop;
end if;
end process;
end;
-- pragma translate_on
|
gpl-2.0
|
0ad22edbdd7d65998567e1f2ef91ac76
| 0.530502 | 3.683452 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep1c20/clkgen_ep1c20board.vhd
| 1 | 3,181 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library techmap;
use techmap.allclkgen.all;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
------------------------------------------------------------------
-- Altera Cyclone ep1c20 clock generator ---------------------------------------
------------------------------------------------------------------
entity clkgen_ep1c20board is
generic (
tech : integer := DEFFABTECH;
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
freq : integer := 50000);
port (
clkin : in std_logic;
clkout : out std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
sdclk : out std_logic; -- SDRAM clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_ep1c20board is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal s_clk : std_logic;
signal intclk : std_ulogic;
begin
gen : if (tech = inferred)
generate
intclk <= clkin;
sdclk <= not intclk when SDINVCLK = 1 else intclk;
clk <= intclk; clkn <= not intclk;
cgo.clklock <= '1'; cgo.pcilock <= '1';
end generate;
alt : if (tech /= inferred) generate
pll1 : altera_pll
generic map (clk_mul, clk_div, freq)
port map ( inclk0 => clkin, e0 => clkout, c0 => open,
locked => open);
pll2 : altera_pll
generic map (clk_mul, clk_div, freq)
port map ( inclk0 => cgi.pllref, e0 => sdclk, c0 => s_clk,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_ep1c20board" & ": EP1C20 board sdram/pci clock generator, version " & tost(VERSION),
"clkgen_ep1c20board" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
|
gpl-2.0
|
dbf9457b7db454a25b77c05e1152a932
| 0.572461 | 3.971286 | false | false | false | false |
lunod/lt24_ctrl
|
rtl/cpt_pix.vhd
| 1 | 2,854 |
---------------------------------------------------------------------------
-- This file is part of lt24ctrl, a video controler IP core for Terrasic
-- LT24 LCD display
-- Copyright (C) 2017 Ludovic Noury <[email protected]>
--
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------------------------------------
entity cpt_pix is
port(clk : in std_logic;
resetn : in std_logic;
clr_cptpix: in std_logic;
inc_cptpix: in std_logic;
end_cptpix: out std_logic;
x : out std_logic_vector(7 downto 0); -- [0:239]
y : out std_logic_vector(8 downto 0)); -- [0:319]
end entity cpt_pix;
---------------------------------------------------------------------------
architecture rtl of cpt_pix is
constant X_PIXELS: natural := 240;
constant Y_PIXELS: natural := 320;
signal cpt_x: unsigned(x'range);
signal cpt_y: unsigned(y'range);
begin
update_cpt: process(clk, resetn)
begin
if resetn = '0' then
cpt_x <= (others => '0');
cpt_y <= (others => '0');
end_cptpix <= '0';
elsif rising_edge(clk) then
if clr_cptpix = '1' then
cpt_x <= (others => '0');
cpt_y <= (others => '0');
end_cptpix <= '0';
elsif inc_cptpix = '1' then
-- DFFs on output signals to minimise critical path
if (cpt_y = Y_PIXELS - 1) and (cpt_x = X_PIXELS - 2) then
end_cptpix <= '1';
else
end_cptpix <= '0';
end if;
if cpt_x = X_PIXELS - 1 then
cpt_x <= (others => '0');
if cpt_y = Y_PIXELS - 1 then
cpt_y <= (others => '0');
else
cpt_y <= cpt_y + 1;
end if; -- cpt_y = Y_PIXELS - 1
else
cpt_x <= cpt_x + 1;
end if; -- cpt_x = X_PIXELS - 1
end if; -- if clr_cptpix = '1'
end if; -- if resetn = '0'
end process update_cpt;
x <= std_logic_vector(cpt_x);
y <= std_logic_vector(cpt_y);
end architecture rtl;
---------------------------------------------------------------------------
|
lgpl-3.0
|
e63e47027791bc8de6db99b81d38f72f
| 0.50911 | 3.872456 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/comp200.vhd
| 1 | 1,354 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity comp200 is
port(
clkcmp2: in std_logic ;
codopcmp2: in std_logic_vector ( 3 downto 0 );
portAcmp2: in std_logic_vector ( 7 downto 0 );
inFlagcmp2: in std_logic;
outcmp2: out std_logic_vector ( 7 downto 0 );
outFlagcmp2: out std_logic );
end;
architecture comp20 of comp200 is
begin
pcomp2: process(codopcmp2, portAcmp2)
begin
if(codopcmp2 = "0111") then
outcmp2 <= not(portAcmp2)+1;
outFlagcmp2 <= '1';
else
outcmp2 <= (others => 'Z');
outFlagcmp2 <= 'Z';
end if;
end process pcomp2;
-- pnand: process(clknd, codopnd, inFlagnd)
-- --variable auxnd: bit:='0';
-- begin
-- if (clknd = '1') then
----clknd'event and
-- if (codopnd = "0100") then
-- if (inFlagnd = '1') then
-- --if (auxnd = '0') then
-- --auxnd:= '1';
-- outnd <= portAnd nand portBnd;
-- outFlagnd <= '1';
-- --end if;
-- else
-- outFlagnd <= '0';
-- end if;
-- else
-- outnd <= (others => 'Z');
-- outFlagnd <= 'Z';
-- --auxnd:='0';
-- end if;
-- end if;
-- end process pnand;
end comp20;
|
apache-2.0
|
fd39e72f80a33ac32e1cdfacb4f4acba
| 0.505908 | 3.008889 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/memctrl/sdctrl64.vhd
| 1 | 29,780 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdctrl
-- File: sdctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: 64-bit SDRAM memory controller.
-- Supports HSIZE_DWORD AMBA accesses when connected to
-- AHB data bus wider than 32 bits.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity sdctrl64 is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of sdctrl64 is
constant WPROTEN : boolean := wprot = 1;
constant SDINVCLK : boolean := invclk = 1;
constant REVISION : integer := 0;
constant PM_PD : std_logic_vector(2 downto 0) := "001";
constant PM_SR : std_logic_vector(2 downto 0) := "010";
constant PM_DPD : std_logic_vector(2 downto 0) := "101";
constant std_rammask: Std_Logic_Vector(31 downto 20) :=
Conv_Std_Logic_Vector(hmask, 12);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SDCTRL64, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4, wr5, sidle,
sref, pd, dpd);
type icycletype is (iidle, pre, ref, lmode, emode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
cke : std_ulogic; -- Clock enable
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
nbdrive : std_ulogic;
burst : std_ulogic;
wprothit : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(63 downto 0);
hwdata : std_logic_vector(63 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(3 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(3 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
address : std_logic_vector(16 downto 1); -- memory address
idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
pwron : std_ulogic;
end record;
signal r, ri : reg_type;
signal rbdrive, ribdrive : std_logic_vector(63 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
ctrl : process(rst, ahbsi, r, sdi, rbdrive)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec0 : std_ulogic;
variable adec1 : std_ulogic;
variable rams : std_logic_vector(3 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable dout : std_logic_vector(63 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(63 downto 0);
variable bdrive : std_ulogic;
variable lline : std_logic_vector(2 downto 0);
variable haddr_tmp : std_logic_vector(31 downto 0);
variable arefresh : std_logic;
variable hwdata : std_logic_vector(63 downto 0);
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.hresp := HRESP_OKAY; vbdrive := rbdrive; arefresh := '0';
-- lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
lline := '1' & not r.cfg.casdel & '1';
v.hrdata(63 downto 0) := sdi.data(63 downto 0);
-- Select input data depending on AHB DW and AMBA data mux settings
if AHBDW = 32 then
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
else
hwdata := ahbreaddword(ahbsi.hwdata, r.haddr(4 downto 2));
end if;
v.hwdata := hwdata;
-- AHB access
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := v.hio;
end if;
v.haddr := ahbsi.haddr;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
v.haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr;
htrans := r.htrans; hwrite := r.hwrite;
else
haddr := ahbsi.haddr;
htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if fast = 1 then haddr := r.haddr; end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- main state
case r.size is
when "00" =>
case r.haddr(2 downto 0) is
when "000" => dqm := "01111111";
when "001" => dqm := "10111111";
when "010" => dqm := "11011111";
when "011" => dqm := "11101111";
when "100" => dqm := "11110111";
when "101" => dqm := "11111011";
when "110" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
case r.haddr(2 downto 1) is
when "00" => dqm := "00111111";
when "01" => dqm := "11001111";
when "10" => dqm := "11110011";
when others => dqm := "11111100";
end case;
when "10" =>
if r.hwrite = '0' then dqm := "00000000";
elsif r.haddr(2) = '0' then dqm := "00001111";
else dqm := "11110000"; end if;
when others => dqm := "00000000";
end case;
-- main FSM
case r.mstate is
when midle =>
if ((v.hsel and htrans(1) and not v.hio) = '1') then
if (r.sdstate = sidle) and (r.cfg.command = "000")
and (r.cmstate = midle) and (v.hio = '0')
then
if fast = 0 then startsd := '1'; else v.startsd := '1'; end if;
v.mstate := active;
elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
and (r.cfg.command = "000") and (r.cmstate = midle) and (v.hio = '0')
then
v.startsd := '1';
if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
v.hresp := HRESP_ERROR;
else
v.mstate := active;
end if;
end if;
end if;
when others => null;
end case;
startsd := startsd or r.startsd;
-- generate row and column address size
case r.cfg.csize is
when "00" => raddr := haddr(23 downto 11);
when "01" => raddr := haddr(24 downto 12);
when "10" => raddr := haddr(25 downto 13);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(27 downto 15);
else raddr := haddr(26 downto 14); end if;
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(29 downto 21)) &
genmux(r.cfg.bsize, haddr(28 downto 20));
-- generate chip select
adec0 := genmux(r.cfg.bsize, haddr(29 downto 22));
adec1 := genmux(r.cfg.bsize, haddr(30 downto 23));
rams := (adec1 and adec0) & (adec1 and not adec0) & (not adec1 and adec0) & (not adec1 and not adec0);
-- sdram access FSM
if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
v.address(16 downto 1) := ba & raddr & '0';
v.sdcsn := not rams(3 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
case r.cfg.pmode is
when PM_SR =>
v.cfg.cke := '0'; v.sdstate := sref;
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
when PM_DPD =>
v.cfg.cke := '0'; v.sdstate := dpd;
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
when others =>
end case;
end if;
when act1 =>
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
end if;
if WPROTEN then
v.wprothit := sdi.wprot;
if sdi.wprot = '1' then v.hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
v.address(14 downto 1) := r.haddr(14 downto 13) & '0' & r.haddr(12 downto 2);
v.dqm := dqm; v.burst := r.hready;
if r.hwrite = '1' then
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0';
if ahbsi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '1';
v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '1'; v.casn := '1';
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.dqm := dqm;
v.address(14 downto 2) := r.haddr(14 downto 13) & '0' & r.haddr(12 downto 3);
if ((((r.burst and r.hready) = '1') and (r.htrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))) then
v.hready := ahbsi.htrans(0) and ahbsi.htrans(1) and r.hready;
if ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (r.trfc(2 downto 1) = "00") then
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
end if;
when wr3 =>
if (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "1111"; v.rasn := '1'; v.sdwen := '1'; v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when wr4 =>
v.sdcsn := "1111"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
when wr5 =>
v.sdstate := sidle; v.idlecnt := (others => '1');
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if (ahbsi.htrans = "11") then
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
when rd7 =>
v.casn := '1';
if r.cfg.casdel = '1' then
v.sdstate := rd2;
if (ahbsi.htrans = "11") then
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
else
v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
else
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
else
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "1111"; v.dqm := (others => '1');
else
if (ahbsi.htrans = "11") then
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (ahbsi.htrans /= "11") or (r.sdcsn = "1111") or
((r.haddr(5 downto 2) = ("111" & not r.size(0))) and (r.cfg.command = "100")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "1111") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
else
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when sref =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
if r.trfc = "0000" then -- Minimum duration (= tRAS)
v.cfg.cke := '1';
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
end if;
if r.cfg.cke = '1' then
if (r.idlecnt = "0000") then -- tXSR ns with NOP
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.sref_tmpcom := r.cfg.command;
v.cfg.command := "100";
end if;
else
v.idlecnt := r.cfg.txsr;
end if;
end if;
when pd =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
v.cfg.cke := '1';
v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when dpd =>
v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
v.cfg.renable := '0';
if (startsd = '1' and r.hio = '0') then
v.hready := '1'; -- ack all accesses with Error response
v.startsd := '0';
v.hresp := HRESP_ERROR;
elsif r.cfg.pmode /= PM_DPD then
v.cfg.cke := '1';
if r.cfg.cke = '1' then
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.cfg.renable := '1';
end if;
end if;
when others =>
v.sdstate := sidle; v.idlecnt := (others => '1');
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "010" => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when "100" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "110" => -- Lodad Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0000";
when "111" => -- Load Ext-Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
& r.cfg.pasr(2 downto 0);
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; --v.cfg.command := "000";
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
when leadout =>
if r.trfc = "0000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
v.cfg.cke := '1';
if (r.cfg.renable = '1' or (pwron /= 0 and r.pwron = '1')) and r.cfg.cke = '1' then
v.cfg.command := "010"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.mobileen = "11" then
v.cfg.command := "111"; v.istate := emode;
else
v.istate := finish;
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := finish;
end if;
when others =>
if pwron /= 0 then v.pwron := '0'; end if;
if r.cfg.renable = '0' and r.sdstate /= dpd then
v.istate := iidle;
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
if (r.hsel and r.hio and not r.hready) = '1' then v.hready := '1'; end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
-- pragma translate_off
if not is_x(r.cfg.refresh) then
-- pragma translate_on
if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "100";
arefresh := '1';
end if;
end if;
-- pragma translate_off
end if;
-- pragma translate_on
-- AHB register access
if (r.hsel and r.hio and r.hwrite and r.htrans(1)) = '1' then
if r.haddr(3 downto 2) = "00" then
v.cfg.command := hwdata(20 downto 18);
v.cfg.csize := hwdata(22 downto 21);
v.cfg.bsize := hwdata(25 downto 23);
v.cfg.casdel := hwdata(26);
v.cfg.trfc := hwdata(29 downto 27);
v.cfg.trp := hwdata(30);
v.cfg.renable := hwdata(31);
v.cfg.refresh := hwdata(14 downto 0);
v.refresh := (others => '0');
elsif r.haddr(3 downto 2) = "01" then
if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := hwdata(31); end if;
if r.cfg.pmode = "000" then
v.cfg.cke := hwdata(30);
end if;
if r.cfg.mobileen(1) = '1' then
v.cfg.txsr := hwdata(23 downto 20);
v.cfg.pmode := hwdata(18 downto 16);
v.cfg.ds(3 downto 2) := hwdata( 6 downto 5);
v.cfg.tcsr(3 downto 2) := hwdata( 4 downto 3);
v.cfg.pasr(5 downto 3) := hwdata( 2 downto 0);
end if;
end if;
end if;
-- Disable CS and DPD when Mobile SDR is Disabled
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
-- Update EMR when ds, tcsr or pasr change
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
end if;
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
end if;
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
end if;
end if;
regsd := (others => '0');
if r.haddr(3 downto 2) = "00" then
regsd(31 downto 18) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command;
regsd(16) := r.cfg.mobileen(1);
regsd(15) := '1'; -- 64-bit support
regsd(14 downto 0) := r.cfg.refresh;
elsif r.haddr(3 downto 2) = "01" then
regsd(31) := r.cfg.mobileen(0);
regsd(30) := r.cfg.cke;
regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
end if;
if (r.hsel and r.hio) = '1' then dout := regsd & regsd;
else
dout := r.hrdata;
-- Possibly duplicate data for reads < HSIZE_DWORD since the system may
-- not be fully AMBA compliant and other cores may expect that the valid
-- WORD is present on 31:0 of AMBA HRDATA.
if andv(r.size) /= '1' and r.haddr(2) = '0' then
dout(31 downto 0) := r.hrdata(63 downto 32);
if r.hready = '1' then v.hrdata := r.hrdata; end if;
end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "000";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
v.cfg.renable := '0';
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.startsd := '0';
if pwron /= 0 then v.pwron := '1'; end if;
if mobile >= 2 then v.cfg.mobileen := "11";
elsif mobile = 1 then v.cfg.mobileen := "10";
else v.cfg.mobileen := "00"; end if;
v.cfg.txsr := (others => '1');
v.cfg.pmode := (others => '0');
v.cfg.ds := (others => '0');
v.cfg.tcsr := (others => '0');
v.cfg.pasr := (others => '0');
if mobile >= 2 then v.cfg.cke := '0';
else v.cfg.cke := '1'; end if;
v.sref_tmpcom := "000";
v.idlecnt := (others => '1');
v.hio := '0';
end if;
if pwron = 0 then v.pwron := '0'; end if;
if not WPROTEN then v.wprothit := '0'; end if;
ri <= v;
ribdrive <= vbdrive;
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(dout);
end process;
--sdo.sdcke <= (others => '1');
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
sdo.cb <= (others => '0'); sdo.ba <= (others => '0');
sdo.cal_en <= (others => '0'); sdo.sdck <= (others => '0');
sdo.cal_pll <= (others => '0'); sdo.cal_inc <= (others => '0');
sdo.conf <= (others => '0'); sdo.odt <= (others => '0');
sdo.oct <= '0';
sdo.qdrive <= '0';
sdo.ce <= '0';
sdo.moben <= '0';
sdo.cal_rst <= '0';
sdo.vcbdrive <= (others => '0');
sdo.cbdqm <= (others => '0');
sdo.cbcal_en <= (others => '0');
sdo.cbcal_inc <= (others => '0');
sdo.read_pend <= (others => '0');
sdo.regwdata <= (others => '0');
sdo.regwrite <= (others => '0');
sdo.dqs_gate <= '0';
sdo.nbdrive <= '0';
regs : process(clk, rst) begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive;
if rst = '0' then r.icnt <= (others => '0'); end if;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
end if;
end process;
rgen : if not SDINVCLK generate
sdo.address <= r.address(16 downto 2);
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= r.sdcsn(1 downto 0);
sdo.xsdcsn <= "1111" & r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
sdo.data <= zero64 & r.hwdata;
end generate;
ngen : if SDINVCLK generate
nregs : process(clk, rst) begin
if falling_edge(clk) then
sdo.address <= r.address(16 downto 2);
if oepol = 1 then sdo.bdrive <= r.nbdrive;
else sdo.bdrive <= r.bdrive; end if;
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= r.sdcsn(1 downto 0);
sdo.xsdcsn <= "1111" & r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
sdo.data(63 downto 0) <= r.hwdata;
end if;
if rst = '0' then sdo.sdcsn <= (others => '1'); end if;
end process;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("sdctrl64" & tost(hindex) &
": 64-bit PC133 SDRAM controller rev " & tost(REVISION));
-- pragma translate_on
end;
|
gpl-2.0
|
06d05ebbeb80a40da5989e550765d020
| 0.525487 | 3.240831 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaFinal/osc03.vhd
| 1 | 733 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity osc03 is
port(
osc_dis: in std_logic ;
tmr_rst: in std_logic ;
osc_out: out std_logic ;
tmr_out: out std_logic );
end;
architecture osc0 of osc03 is
component OSCTIMER
generic (TIMER_DIV : string);
port(
DYNOSCDIS : in STD_ULOGIC;
TIMERRES : in STD_ULOGIC;
OSCOUT : out STD_ULOGIC;
TIMEROUT : out STD_ULOGIC);
end component;
begin
inst11: OSCTIMER
generic map (TIMER_DIV => "1048576")
port map (
DYNOSCDIS => osc_dis,
TIMERRES => tmr_rst,
OSCOUT => osc_out,
TIMEROUT => tmr_out);
end osc0;
|
apache-2.0
|
9e43b6ceb04104f8811460e737cd090f
| 0.59618 | 2.979675 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702/leon3mp.vhd
| 1 | 23,887 |
-----------------------------------------------------------------------------
-- LEON3 Zc702 Demonstration design
-- Copyright (C) 2012 Fredrik Ringhage, Aeroflex Gaisler
-- Modifed by Jiri Gaisler to provide working AXI interface, 2014-04-05
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.config.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false
);
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB : inout std_logic;
processing_system7_0_PS_CLK : inout std_logic;
processing_system7_0_PS_PORB : inout std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : inout std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
component leon3_zc702_stub
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
S_AXI_GP0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_arready : out STD_LOGIC;
S_AXI_GP0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arvalid : in STD_LOGIC;
S_AXI_GP0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_awready : out STD_LOGIC;
S_AXI_GP0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awvalid : in STD_LOGIC;
S_AXI_GP0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_bready : in STD_LOGIC;
S_AXI_GP0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_bvalid : out STD_LOGIC;
S_AXI_GP0_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_rlast : out STD_LOGIC;
S_AXI_GP0_rready : in STD_LOGIC;
S_AXI_GP0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_rvalid : out STD_LOGIC;
S_AXI_GP0_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_wid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_wlast : in STD_LOGIC;
S_AXI_GP0_wready : out STD_LOGIC;
S_AXI_GP0_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_wvalid : in STD_LOGIC
);
end component;
constant maxahbm : integer := (CFG_LEON3*CFG_NCPU)+CFG_AHB_JTAG;
constant maxahbs : integer := 8;
constant maxapbs : integer := 16;
signal vcc, gnd : std_logic;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rsti, rst : std_ulogic;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
constant BOARD_FREQ : integer := 83333; -- CLK0 frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ;
signal stati : ahbstat_in_type;
constant CIDSZ : integer := 6;
constant CLENSZ : integer := 4;
signal S_AXI_GP0_araddr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_arburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_arcache : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_arid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_arlen : STD_LOGIC_VECTOR ( CLENSZ-1 downto 0 );
signal S_AXI_GP0_arlock : STD_LOGIC_VECTOR ( 1 downto 0 ); --
signal S_AXI_GP0_arprot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_arqos : STD_LOGIC_VECTOR ( 3 downto 0 ); --
signal S_AXI_GP0_awqos : STD_LOGIC_VECTOR ( 3 downto 0 ); --
signal S_AXI_GP0_arready : STD_LOGIC;
signal S_AXI_GP0_arsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_arvalid : STD_LOGIC;
signal S_AXI_GP0_awaddr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_awburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_awcache : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_awid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_awlen : STD_LOGIC_VECTOR ( CLENSZ-1 downto 0 );
signal S_AXI_GP0_awlock : STD_LOGIC_VECTOR ( 1 downto 0 ); --
signal S_AXI_GP0_awprot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_awready : STD_LOGIC;
signal S_AXI_GP0_awsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_awvalid : STD_LOGIC;
signal S_AXI_GP0_bid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_bready : STD_LOGIC;
signal S_AXI_GP0_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_bvalid : STD_LOGIC;
signal S_AXI_GP0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_rid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_rlast : STD_LOGIC;
signal S_AXI_GP0_rready : STD_LOGIC;
signal S_AXI_GP0_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_rvalid : STD_LOGIC;
signal S_AXI_GP0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_wlast : STD_LOGIC;
signal S_AXI_GP0_wready : STD_LOGIC;
signal S_AXI_GP0_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_wvalid : STD_LOGIC;
signal S_AXI_GP0_wid : STD_LOGIC_VECTOR ( 5 downto 0 ); --
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
reset_pad : inpad generic map (level => cmos, voltage => x18v, tech => padtech)
port map (button(0), rsti);
rstn <= rst and not rsti;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
nahbm => maxahbm, nahbs => maxahbs)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon3_0 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
nocpu : if CFG_LEON3 = 0 generate dbgo(0) <= dbgo_none; end generate;
led1_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v) port map (led(1), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= gpioi.din(0);
end generate;
dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v) port map (led(0), dsuo.active);
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_LEON3*CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_LEON3*CFG_NCPU),
open, open, open, open, open, open, open, gnd);
end generate;
leon3_zc702_stub_i : leon3_zc702_stub
port map (
DDR_ck_p => processing_system7_0_DDR_Clk,
DDR_ck_n => processing_system7_0_DDR_Clk_n,
DDR_cke => processing_system7_0_DDR_CKE,
DDR_cs_n => processing_system7_0_DDR_CS_n,
DDR_ras_n => processing_system7_0_DDR_RAS_n,
DDR_cas_n => processing_system7_0_DDR_CAS_n,
DDR_we_n => processing_system7_0_DDR_WEB_pin,
DDR_ba => processing_system7_0_DDR_BankAddr,
DDR_addr => processing_system7_0_DDR_Addr,
DDR_odt => processing_system7_0_DDR_ODT,
DDR_reset_n => processing_system7_0_DDR_DRSTB,
DDR_dq => processing_system7_0_DDR_DQ,
DDR_dm => processing_system7_0_DDR_DM,
DDR_dqs_p => processing_system7_0_DDR_DQS,
DDR_dqs_n => processing_system7_0_DDR_DQS_n,
FCLK_CLK0 => clkm,
FCLK_RESET0_N => rst,
FIXED_IO_mio => processing_system7_0_MIO,
FIXED_IO_ps_srstb => processing_system7_0_PS_SRSTB,
FIXED_IO_ps_clk => processing_system7_0_PS_CLK,
FIXED_IO_ps_porb => processing_system7_0_PS_PORB,
FIXED_IO_ddr_vrn => processing_system7_0_DDR_VRN,
FIXED_IO_ddr_vrp => processing_system7_0_DDR_VRP,
S_AXI_GP0_araddr => S_AXI_GP0_araddr,
S_AXI_GP0_arburst(1 downto 0) => S_AXI_GP0_arburst(1 downto 0),
S_AXI_GP0_arcache(3 downto 0) => S_AXI_GP0_arcache(3 downto 0),
S_AXI_GP0_arid => S_AXI_GP0_arid,
S_AXI_GP0_arlen => S_AXI_GP0_arlen,
S_AXI_GP0_arlock => S_AXI_GP0_arlock,
S_AXI_GP0_arprot(2 downto 0) => S_AXI_GP0_arprot(2 downto 0),
S_AXI_GP0_arqos => S_AXI_GP0_arqos,
S_AXI_GP0_awqos => S_AXI_GP0_awqos,
S_AXI_GP0_arready => S_AXI_GP0_arready,
S_AXI_GP0_arsize(2 downto 0) => S_AXI_GP0_arsize(2 downto 0),
S_AXI_GP0_arvalid => S_AXI_GP0_arvalid,
S_AXI_GP0_awaddr => S_AXI_GP0_awaddr,
S_AXI_GP0_awburst(1 downto 0) => S_AXI_GP0_awburst(1 downto 0),
S_AXI_GP0_awcache(3 downto 0) => S_AXI_GP0_awcache(3 downto 0),
S_AXI_GP0_awid => S_AXI_GP0_awid,
S_AXI_GP0_awlen => S_AXI_GP0_awlen,
S_AXI_GP0_awlock => S_AXI_GP0_awlock,
S_AXI_GP0_awprot(2 downto 0) => S_AXI_GP0_awprot(2 downto 0),
S_AXI_GP0_awready => S_AXI_GP0_awready,
S_AXI_GP0_awsize(2 downto 0) => S_AXI_GP0_awsize(2 downto 0),
S_AXI_GP0_awvalid => S_AXI_GP0_awvalid,
S_AXI_GP0_bid => S_AXI_GP0_bid,
S_AXI_GP0_bready => S_AXI_GP0_bready,
S_AXI_GP0_bresp(1 downto 0) => S_AXI_GP0_bresp(1 downto 0),
S_AXI_GP0_bvalid => S_AXI_GP0_bvalid,
S_AXI_GP0_rdata(31 downto 0) => S_AXI_GP0_rdata(31 downto 0),
S_AXI_GP0_rid => S_AXI_GP0_rid,
S_AXI_GP0_rlast => S_AXI_GP0_rlast,
S_AXI_GP0_rready => S_AXI_GP0_rready,
S_AXI_GP0_rresp(1 downto 0) => S_AXI_GP0_rresp(1 downto 0),
S_AXI_GP0_rvalid => S_AXI_GP0_rvalid,
S_AXI_GP0_wdata(31 downto 0) => S_AXI_GP0_wdata(31 downto 0),
S_AXI_GP0_wid => S_AXI_GP0_wid,
S_AXI_GP0_wlast => S_AXI_GP0_wlast,
S_AXI_GP0_wready => S_AXI_GP0_wready,
S_AXI_GP0_wstrb(3 downto 0) => S_AXI_GP0_wstrb(3 downto 0),
S_AXI_GP0_wvalid => S_AXI_GP0_wvalid
);
ahb2axi0 : entity work.ahb2axi
generic map(
hindex => 3, haddr => 16#400#, hmask => 16#F00#,
pindex => 0, paddr => 0, cidsz => CIDSZ, clensz => CLENSZ)
port map(
rstn => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(3),
apbi => apbi,
apbo => apbo(0),
M_AXI_araddr => S_AXI_GP0_araddr,
M_AXI_arburst(1 downto 0) => S_AXI_GP0_arburst(1 downto 0),
M_AXI_arcache(3 downto 0) => S_AXI_GP0_arcache(3 downto 0),
M_AXI_arid => S_AXI_GP0_arid,
M_AXI_arlen => S_AXI_GP0_arlen,
M_AXI_arlock => S_AXI_GP0_arlock,
M_AXI_arprot(2 downto 0) => S_AXI_GP0_arprot(2 downto 0),
M_AXI_arqos => S_AXI_GP0_arqos,
M_AXI_arready => S_AXI_GP0_arready,
M_AXI_arsize(2 downto 0) => S_AXI_GP0_arsize(2 downto 0),
M_AXI_arvalid => S_AXI_GP0_arvalid,
M_AXI_awaddr => S_AXI_GP0_awaddr,
M_AXI_awburst(1 downto 0) => S_AXI_GP0_awburst(1 downto 0),
M_AXI_awcache(3 downto 0) => S_AXI_GP0_awcache(3 downto 0),
M_AXI_awid => S_AXI_GP0_awid,
M_AXI_awlen => S_AXI_GP0_awlen,
M_AXI_awlock => S_AXI_GP0_awlock,
M_AXI_awprot(2 downto 0) => S_AXI_GP0_awprot(2 downto 0),
M_AXI_awqos => S_AXI_GP0_awqos,
M_AXI_awready => S_AXI_GP0_awready,
M_AXI_awsize(2 downto 0) => S_AXI_GP0_awsize(2 downto 0),
M_AXI_awvalid => S_AXI_GP0_awvalid,
M_AXI_bid => S_AXI_GP0_bid,
M_AXI_bready => S_AXI_GP0_bready,
M_AXI_bresp(1 downto 0) => S_AXI_GP0_bresp(1 downto 0),
M_AXI_bvalid => S_AXI_GP0_bvalid,
M_AXI_rdata(31 downto 0) => S_AXI_GP0_rdata(31 downto 0),
M_AXI_rid => S_AXI_GP0_rid,
M_AXI_rlast => S_AXI_GP0_rlast,
M_AXI_rready => S_AXI_GP0_rready,
M_AXI_rresp(1 downto 0) => S_AXI_GP0_rresp(1 downto 0),
M_AXI_rvalid => S_AXI_GP0_rvalid,
M_AXI_wdata(31 downto 0) => S_AXI_GP0_wdata(31 downto 0),
M_AXI_wlast => S_AXI_GP0_wlast,
M_AXI_wready => S_AXI_GP0_wready,
M_AXI_wstrb(3 downto 0) => S_AXI_GP0_wstrb(3 downto 0),
M_AXI_wvalid => S_AXI_GP0_wvalid
);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
irqgen : if CFG_LEON3 = 1 generate
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
end generate;
irqctrl : if (CFG_IRQ3_ENABLE + CFG_LEON3) /= 2 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => 0)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8), gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 8 to 10 generate
pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (button(i-8+1), gpioi.din(i)); -- Use +1 because button(0) is used for reset
end generate;
pio_pads3 : for i in 11 to 14 generate
pio_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (led(i-11+4), gpioo.dout(i));
end generate;
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
hready_pad : outpad generic map (level => cmos, voltage => x33v, tech => padtech)
port map (led(2), ahbmi.hready);
rsti_pad : outpad generic map (level => cmos, voltage => x33v, tech => padtech)
port map (led(3), rsti);
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(0));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0_gen : if (testahb = true) generate
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
end generate;
-- pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (maxahbs+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx zc702 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
653bf8a433643a22ae6345035e6382c9
| 0.56985 | 3.241113 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/cycloneiii/cycloneiii_ddr_phy.vhd
| 1 | 22,053 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cycloneiii_ddr_phy
-- File: cycloneiii_ddr_phy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Altera FPGAs
------------------------------------------------------------------------------
LIBRARY cycloneiii;
USE cycloneiii.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_cyciii_adqs_n7i2 IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC := '0';
oe : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1');
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1')
);
END altdqs_cyciii_adqs_n7i2;
ARCHITECTURE RTL OF altdqs_cyciii_adqs_n7i2 IS
-- ATTRIBUTE synthesis_clearbox : boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_cyciii_dll1_delayctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cyciii_dll1_dqsupdate : STD_LOGIC;
SIGNAL wire_cyciii_dll1_offsetctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cyciii_io2a_combout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_datain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_ddiodatain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_dqsbusout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_oe : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_outclk : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_outclkena : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL delay_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL dqs_update : STD_LOGIC;
SIGNAL offset_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT cycloneiii_dll
GENERIC
(
DELAY_BUFFER_MODE : STRING := "low";
DELAY_CHAIN_LENGTH : NATURAL := 12;
DELAYCTRLOUT_MODE : STRING := "normal";
INPUT_FREQUENCY : STRING;
JITTER_REDUCTION : STRING := "false";
OFFSETCTRLOUT_MODE : STRING := "static";
SIM_LOOP_DELAY_INCREMENT : NATURAL := 0;
SIM_LOOP_INTRINSIC_DELAY : NATURAL := 0;
SIM_VALID_LOCK : NATURAL := 5;
SIM_VALID_LOCKCOUNT : NATURAL := 0;
STATIC_DELAY_CTRL : NATURAL := 0;
STATIC_OFFSET : STRING;
USE_UPNDNIN : STRING := "false";
USE_UPNDNINCLKENA : STRING := "false";
lpm_type : STRING := "cycloneiii_dll"
);
PORT
(
addnsub : IN STD_LOGIC := '1';
aload : IN STD_LOGIC := '0';
clk : IN STD_LOGIC;
delayctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
dqsupdate : OUT STD_LOGIC;
offset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
offsetctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
upndnin : IN STD_LOGIC := '0';
upndninclkena : IN STD_LOGIC := '1';
upndnout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiii_io
GENERIC
(
BUS_HOLD : STRING := "false";
DDIO_MODE : STRING := "none";
DDIOINCLK_INPUT : STRING := "negated_inclk";
DQS_CTRL_LATCHES_ENABLE : STRING := "false";
DQS_DELAY_BUFFER_MODE : STRING := "none";
DQS_EDGE_DETECT_ENABLE : STRING := "false";
DQS_INPUT_FREQUENCY : STRING := "unused";
DQS_OFFSETCTRL_ENABLE : STRING := "false";
DQS_OUT_MODE : STRING := "none";
DQS_PHASE_SHIFT : NATURAL := 0;
EXTEND_OE_DISABLE : STRING := "false";
GATED_DQS : STRING := "false";
INCLK_INPUT : STRING := "normal";
INPUT_ASYNC_RESET : STRING := "none";
INPUT_POWER_UP : STRING := "low";
INPUT_REGISTER_MODE : STRING := "none";
INPUT_SYNC_RESET : STRING := "none";
OE_ASYNC_RESET : STRING := "none";
OE_POWER_UP : STRING := "low";
OE_REGISTER_MODE : STRING := "none";
OE_SYNC_RESET : STRING := "none";
OPEN_DRAIN_OUTPUT : STRING := "false";
OPERATION_MODE : STRING;
OUTPUT_ASYNC_RESET : STRING := "none";
OUTPUT_POWER_UP : STRING := "low";
OUTPUT_REGISTER_MODE : STRING := "none";
OUTPUT_SYNC_RESET : STRING := "none";
SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
lpm_type : STRING := "cycloneiii_io"
);
PORT
(
areset : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
datain : IN STD_LOGIC := '0';
ddiodatain : IN STD_LOGIC := '0';
ddioinclk : IN STD_LOGIC := '0';
ddioregout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
dqsbusout : OUT STD_LOGIC;
dqsupdateen : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC := '0';
inclkena : IN STD_LOGIC := '1';
linkin : IN STD_LOGIC := '0';
linkout : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
outclk : IN STD_LOGIC := '0';
outclkena : IN STD_LOGIC := '1';
padio : INOUT STD_LOGIC;
regout : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0';
terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
delay_ctrl <= wire_cyciii_dll1_delayctrlout;
dll_delayctrlout <= delay_ctrl;
dqinclk <= wire_cyciii_io2a_dqsbusout;
dqs_update <= wire_cyciii_dll1_dqsupdate;
dqsundelayedout <= wire_cyciii_io2a_combout;
offset_ctrl <= wire_cyciii_dll1_offsetctrlout;
cyciii_dll1 : cycloneiii_dll
GENERIC MAP (
DELAY_BUFFER_MODE => "low",
DELAY_CHAIN_LENGTH => 12,
DELAYCTRLOUT_MODE => "normal",
INPUT_FREQUENCY => period, --"10000ps",
JITTER_REDUCTION => "false",
OFFSETCTRLOUT_MODE => "static",
SIM_LOOP_DELAY_INCREMENT => 132,
SIM_LOOP_INTRINSIC_DELAY => 3840,
SIM_VALID_LOCK => 1,
SIM_VALID_LOCKCOUNT => 46,
STATIC_OFFSET => "0",
USE_UPNDNIN => "false",
USE_UPNDNINCLKENA => "false"
)
PORT MAP (
clk => inclk,
delayctrlout => wire_cyciii_dll1_delayctrlout,
dqsupdate => wire_cyciii_dll1_dqsupdate,
offsetctrlout => wire_cyciii_dll1_offsetctrlout
);
wire_cyciii_io2a_datain <= dqs_datain_h;
wire_cyciii_io2a_ddiodatain <= dqs_datain_l;
wire_cyciii_io2a_oe <= oe;
wire_cyciii_io2a_outclk <= outclk;
wire_cyciii_io2a_outclkena <= outclkena;
loop0 : FOR i IN 0 TO width-1 GENERATE
cyciii_io2a : cycloneiii_io
GENERIC MAP (
DDIO_MODE => "output",
DQS_CTRL_LATCHES_ENABLE => "true",
DQS_DELAY_BUFFER_MODE => "low",
DQS_EDGE_DETECT_ENABLE => "false",
DQS_INPUT_FREQUENCY => period, --"10000ps",
DQS_OFFSETCTRL_ENABLE => "true",
DQS_OUT_MODE => "delay_chain3",
DQS_PHASE_SHIFT => 9000,
EXTEND_OE_DISABLE => "false",
GATED_DQS => "false",
OE_ASYNC_RESET => "none",
OE_POWER_UP => "low",
OE_REGISTER_MODE => "register",
OE_SYNC_RESET => "none",
OPEN_DRAIN_OUTPUT => "false",
OPERATION_MODE => "bidir",
OUTPUT_ASYNC_RESET => "none",
OUTPUT_POWER_UP => "low",
OUTPUT_REGISTER_MODE => "register",
OUTPUT_SYNC_RESET => "none",
SIM_DQS_DELAY_INCREMENT => 22,
SIM_DQS_INTRINSIC_DELAY => 960,
SIM_DQS_OFFSET_INCREMENT => 11,
TIE_OFF_OE_CLOCK_ENABLE => "false",
TIE_OFF_OUTPUT_CLOCK_ENABLE => "false"
)
PORT MAP (
combout => wire_cyciii_io2a_combout(i),
datain => wire_cyciii_io2a_datain(i),
ddiodatain => wire_cyciii_io2a_ddiodatain(i),
delayctrlin => delay_ctrl,
dqsbusout => wire_cyciii_io2a_dqsbusout(i),
dqsupdateen => dqs_update,
oe => wire_cyciii_io2a_oe(i),
offsetctrlin => offset_ctrl,
outclk => wire_cyciii_io2a_outclk(i),
outclkena => wire_cyciii_io2a_outclkena(i),
padio => dqs_padio(i)
);
END GENERATE loop0;
END RTL; --altdqs_cyciii_adqs_n7i2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_cyciii IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END;
ARCHITECTURE RTL OF altdqs_cyciii IS
-- ATTRIBUTE synthesis_clearbox: boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire3_bv : BIT_VECTOR (width-1 downto 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (width-1 downto 0);
COMPONENT altdqs_cyciii_adqs_n7i2
generic (width : integer := 2; period : string := "10000ps");
PORT (
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0);
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END COMPONENT;
BEGIN
sub_wire3_bv(width-1 downto 0) <= (others => '1');
sub_wire3 <= To_stdlogicvector(sub_wire3_bv);
dll_delayctrlout <= sub_wire0(5 DOWNTO 0);
dqinclk <= not sub_wire1(width-1 downto 0);
dqsundelayedout <= sub_wire2(width-1 downto 0);
altdqs_cyciii_adqs_n7i2_component : altdqs_cyciii_adqs_n7i2
generic map (width, period)
PORT MAP (
outclk => outclk,
outclkena => sub_wire3,
oe => oe,
dqs_datain_h => dqs_datain_h,
inclk => inclk,
dqs_datain_l => dqs_datain_l,
dll_delayctrlout => sub_wire0,
dqinclk => sub_wire1,
dqsundelayedout => sub_wire2,
dqs_padio => dqs_padio
);
END RTL;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
------------------------------------------------------------------
-- CYCLONEIII DDR PHY --------------------------------------------
------------------------------------------------------------------
entity cycloneiii_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of cycloneiii_ddr_phy is
signal vcc, gnd, dqsn, oe, lockl : std_logic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal clk4, clk5 : std_logic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal gndv : std_logic_vector (dbits-1 downto 0); -- ddr dqs
signal pclkout : std_logic_vector (5 downto 1);
signal ddr_clkin : std_logic_vector(0 to 2);
signal dqinclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsnv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
component altdqs_cyciii
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END component;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 13) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769")); -- 120 & 130 MHz
type periodtype is array (10 to 13) of string(1 to 6);
constant periodstr : periodtype := ("9999ps", "9090ps", "8333ps", "7692ps");
begin
oe <= not oen; vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
mclk <= clk;
-- clkout <= clk_270r;
-- clkout <= clk_0r when DDR_FREQ >= 110 else clk_270r;
clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : altpll
generic map (
intended_device_family => "CycloneIII",
operation_mode => "NORMAL",
inclk0_input_frequency => 1000000/MHz,
inclk1_input_frequency => 1000000/MHz,
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
-- clk3_phase_shift => "6250", clk2_phase_shift => "4167", clk1_phase_shift => "2083"
-- clk3_phase_shift => "7500", clk2_phase_shift => "5000", clk1_phase_shift => "2500"
)
port map ( inclk(0) => mclk, inclk(1) => gnd, clk(0) => clk_0r,
clk(1) => clk_90r, clk(2) => clk_180r, clk(3) => clk_270r,
clk(4) => clk4, clk(5) => clk5, locked => lockl);
rstdel : process (mclk, rst, lockl)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
-- fbclkpad : altddio_out generic map (width => 1)
-- port map ( datain_h(0) => vcc, datain_l(0) => gnd,
-- outclock => clk90r, dataout(0) => ddr_clk_fb_out);
ddrclocks : for i in 0 to 2 generate
clkpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => vcc, datain_l(0) => gnd,
outclock => clk90r, dataout(0) => ddr_clk(i));
clknpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => gnd, datain_l(0) => vcc,
outclock => clk90r, dataout(0) => ddr_clkb(i));
end generate;
csnpads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h => csn(1 downto 0), datain_l => csn(1 downto 0),
outclock => clk0r, dataout => ddr_csb(1 downto 0));
ckepads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h => ckel(1 downto 0), datain_l => ckel(1 downto 0),
outclock => clk0r, dataout => ddr_cke(1 downto 0));
ddrbanks : for i in 0 to 1 generate
ckel(i) <= cke(i) and locked;
end generate;
rasnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => rasn, datain_l(0) => rasn,
outclock => clk0r, dataout(0) => ddr_rasb);
casnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => casn, datain_l(0) => casn,
outclock => clk0r, dataout(0) => ddr_casb);
wenpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => wen, datain_l(0) => wen,
outclock => clk0r, dataout(0) => ddr_web);
dmpads : altddio_out generic map (width => dbits/8,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map (
datain_h => dm(dbits/8*2-1 downto dbits/8),
datain_l => dm(dbits/8-1 downto 0),
outclock => clk0r, dataout => ddr_dm
);
bapads : altddio_out generic map (width => 2)
port map (
datain_h => ba, datain_l => ba,
outclock => clk0r, dataout => ddr_ba
);
addrpads : altddio_out generic map (width => 14)
port map (
datain_h => addr, datain_l => addr,
outclock => clk0r, dataout => ddr_ad
);
-- DQS generation
dqsnv <= (others => dqsn);
dqsoclk <= (others => clk90r);
altdqs0 : altdqs_cyciii generic map (dbits/8, periodstr(DDR_FREQ/10))
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv(dbits/8-1 downto 0),
inclk => clk270r, oe => ddr_dqsoen, outclk => dqsoclk,
dll_delayctrlout => open, dqinclk => dqinclk, dqs_padio => ddr_dqs,
dqsundelayedout => open );
-- Data bus
dqgen : for i in 0 to dbits/8-1 generate
qi : altddio_bidir generic map (width => 8, oe_reg =>"REGISTERED",
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map (
datain_l => dqout(i*8+7 downto i*8),
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
inclock => dqinclk(i), --clk270r,
outclock => clk0r, oe => oe,
dataout_h => dqin(i*8+7 downto i*8),
dataout_l => dqin(i*8+7+dbits downto dbits+i*8), --dqinl(i*8+7 downto i*8),
padio => ddr_dq(i*8+7 downto i*8));
end generate;
dqsreg : process(clk180r)
begin
if rising_edge(clk180r) then
dqsn <= oe;
end if;
end process;
oereg : process(clk0r)
begin
if rising_edge(clk0r) then
ddr_dqsoen(dbits/8-1 downto 0) <= (others => not dqsoen);
end if;
end process;
end;
|
gpl-2.0
|
4b6451597776ae30fdf1739c589d164a
| 0.62971 | 2.972102 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/shiftr00.vhd
| 1 | 1,394 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shiftr00 is
port(
clkcshr: in std_logic ;
codopcshr: in std_logic_vector ( 3 downto 0 );
portAcshr: in std_logic_vector ( 7 downto 0 );
inFlagcshr: in std_logic;
outcshr: out std_logic_vector ( 7 downto 0 );
outFlagcshr: out std_logic );
end;
architecture shiftr0 of shiftr00 is
begin
pshr: process(codopcshr, portAcshr)
begin
if(codopcshr = "1010") then
outcshr(7) <= '0';
outcshr(6 downto 0) <= portAcshr(7 downto 1);
outFlagcshr <= '1';
else
outcshr <= (others => 'Z');
outFlagcshr <= 'Z';
end if;
end process pshr;
-- pnand: process(clknd, codopnd, inFlagnd)
-- --variable auxnd: bit:='0';
-- begin
-- if (clknd = '1') then
----clknd'event and
-- if (codopnd = "0100") then
-- if (inFlagnd = '1') then
-- --if (auxnd = '0') then
-- --auxnd:= '1';
-- outnd <= portAnd nand portBnd;
-- outFlagnd <= '1';
-- --end if;
-- else
-- outFlagnd <= '0';
-- end if;
-- else
-- outnd <= (others => 'Z');
-- outFlagnd <= 'Z';
-- --auxnd:='0';
-- end if;
-- end if;
-- end process pnand;
end shiftr0;
|
apache-2.0
|
7e17f294252ef868a1cf99ddcf1e4b90
| 0.506456 | 3.077263 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/leon3v3/iu3.vhd
| 1 | 138,879 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libfpu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 1;
dsets : integer range 1 to 4 := 1;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 2;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 0;
clk2x : integer := 0;
bp : integer range 0 to 2 := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
tbo_2p : in tracebuf_2p_out_type;
tbi_2p : out tracebuf_2p_in_type;
sclk : in std_ulogic
);
attribute sync_set_reset of rstn : signal is "true";
end;
architecture rtl of iu3 is
function get_tbuf(tracebuf_2p: boolean; tbuf: integer) return integer is
begin
if (TRACEBUF_2P) then
return(tbuf-64);
else
return(tbuf);
end if;
end function get_tbuf;
constant ISETMSB : integer := log2x(isets)-1;
constant DSETMSB : integer := log2x(dsets)-1;
constant RFBITS : integer range 6 to 10 := log2(NWIN+1) + 4;
constant NWINLOG2 : integer range 1 to 5 := log2(NWIN);
constant CWPOPT : boolean := (NWIN = (2**NWINLOG2));
constant CWPMIN : std_logic_vector(NWINLOG2-1 downto 0) := (others => '0');
constant CWPMAX : std_logic_vector(NWINLOG2-1 downto 0) :=
conv_std_logic_vector(NWIN-1, NWINLOG2);
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := (cp = 1);
constant MULEN : boolean := (v8 /= 0);
constant MULTYPE: integer := (v8 / 16);
constant DIVEN : boolean := (v8 /= 0);
constant MACEN : boolean := (mac = 1);
constant MACPIPE: boolean := (mac = 1) and (v8/2 = 1);
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := (dsu = 1);
constant TRACEBUF : boolean := (tbuf /= 0);
constant TRACEBUF_2P : boolean := (tbuf > 64);
constant TBUFBITS : integer := 10 + log2(get_tbuf(TRACEBUF_2P, tbuf)) - 4;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := (pwd /= 0); --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := (is_fpga(FABTECH) /= 0);
constant DYNRST : boolean := (rstaddr = 16#FFFFF#);
constant CASAEN : boolean := (notag = 0) and (lddel = 1);
signal BPRED : std_logic;
signal BLOCKBPMISS: std_logic;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto PCLOW);
subtype rfatype is std_logic_vector(RFBITS-1 downto 0);
subtype cwptype is std_logic_vector(NWINLOG2-1 downto 0);
type icdtype is array (0 to isets-1) of word;
type dcdtype is array (0 to dsets-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock, dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(ISETMSB downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
divrdy: std_ulogic;
pcheld: std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
bp, nobp : std_ulogic;
bpimiss : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
bp : std_ulogic;
rfe1, rfe2 : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
casa : std_ulogic;
casaz : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(DSETMSB downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
ipmask : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(TBUFBITS-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
tfilt : std_logic_vector(3 downto 0); -- trace filter
cfc : std_logic_vector(6 downto 0); -- control-flow change
tlim : std_logic_vector(2 downto 0);
tov : std_ulogic;
tovb : std_ulogic;
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(NWIN-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
dbp : std_ulogic; -- disable branch prediction
dbprepl: std_ulogic; -- Disable speculative Icache miss/replacement
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
function dbgexc(
r : registers; dbgi : l3_debug_in_type;
trap : std_ulogic;
tt : std_logic_vector(7 downto 0);
dsur : dsu_registers) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(TBUFBITS-1 downto 0);
tfilt : out std_logic_vector(3 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := (others => '0');
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0'; tfilt := dsur.tfilt;
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1' and dbg.daddr(2) = '0' ) and TRACEBUF then -- trace buffer control reg
tbufcnt := dbg.ddata(TBUFBITS-1 downto 0);
tfilt := dbg.ddata(31 downto 28);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := (others => '0');
addr(RFBITS-1 downto 0) := dbg.daddr(RFBITS+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(NWINLOG2-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(NWIN-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto PCLOW);
when "0101" => -- NPC
npc := dbg.ddata(31 downto PCLOW);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
if bp = 2 then s.dbp := dbg.ddata(27); end if;
if bp = 2 then s.dbprepl := dbg.ddata(25); end if;
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if MACEN then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := zero32;
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if bp = 2 then asr17(27) := r.w.s.dbp; end if;
if notag = 0 then asr17(26) := '1'; end if; -- CASA and tagged arith
if bp = 2 then asr17(25) := r.w.s.dbprepl; end if;
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if v8 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(nwin-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
tbufo_2p : in tracebuf_2p_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := (others => '0'); cwp := (others => '0');
cwp(NWINLOG2-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if TRACEBUF then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if dbgi.daddr(2) = '0' then
data(TBUFBITS-1 downto 0) := dsur.tbufcnt;
data(31 downto 28) := dsur.tfilt;
else
data(23) := dsur.tov;
data(26 downto 24) := dsur.tlim;
data(27) := dsur.tovb;
end if;
else
if TRACEBUF_2P then
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo_2p.data(127 downto 96);
when "01" => data := tbufo_2p.data(95 downto 64);
when "10" => data := tbufo_2p.data(63 downto 32);
when others => data := tbufo_2p.data(31 downto 0);
end case;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
if dbgi.daddr(11) = '0' then
data := rfo.data1(31 downto 0);
else data := rfo.data2(31 downto 0); end if;
else
data := fpo.dbg.data;
end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(IMPL, 4) & conv_std_logic_vector(VER, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(NWIN-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto PCLOW) := r.f.pc;
when "0101" =>
data(31 downto PCLOW) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif MACEN and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
function itfilt (inst : word; filter : std_logic_vector(3 downto 0); trap, cfc : std_logic) return std_ulogic is
variable tren : std_ulogic;
begin
tren := '0';
case filter is
when "0001" => -- Bicc, SETHI
if inst(31 downto 30) = "00" then tren := '1'; end if;
when "0010" => -- Control-flow change
if (inst(31 downto 30) = "01") -- Call
or ((inst(31 downto 30) = "00") and (inst(23 downto 22) /= "00")) --Bicc
or ((inst(31 downto 30) = "10") and (inst(24 downto 19) = JMPL)) --Jmpl
or ((inst(31 downto 30) = "10") and (inst(24 downto 19) = RETT)) --Rett
or (trap = '1') or (cfc = '1')
then tren := '1'; end if;
when "0100" => -- Call
if inst(31 downto 30) = "01" then tren := '1'; end if;
when "1000" => -- Normal instructions
if inst(31 downto 30) = "10" then tren := '1'; end if;
when "1100" => -- LDST
if inst(31 downto 30) = "11" then tren := '1'; end if;
when "1101" => -- LDST from alternate space
if inst(31 downto 30) = "11" and inst(24 downto 23) = "01" then tren := '1'; end if;
when "1110" => -- LDST from alternate space 0x80 - 0xFF
if inst(31 downto 30) = "11" and inst(24 downto 23) = "01" and inst(12) = '1' then tren := '1'; end if;
when others => tren := '1';
end case;
return(tren);
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(TBUFBITS-1 downto 0);
ov : out std_ulogic;
di : out tracebuf_in_type;
di_2p : out tracebuf_2p_in_type;
ierr : in std_ulogic;
derr : in std_ulogic
) is
variable meminst : std_ulogic;
variable tfen : std_ulogic;
variable vdi_2p : tracebuf_2p_in_type;
variable vdi : tracebuf_in_type;
variable indata : std_logic_vector(255 downto 0);
variable write : std_logic_vector(7 downto 0);
variable tov : std_ulogic;
begin
vdi_2p := tracebuf_2p_in_type_none;
vdi := tracebuf_in_type_none;
indata := (others => '0');
write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
tov := vdsu.tov;
if TRACEBUF then
if dbgi.tenable = '1' then
if dsur.tbufcnt(TBUFBITS-1 downto TBUFBITS-3) = dsur.tlim(2 downto 0) then
tov := '1';
end if;
end if;
indata(127) := tov;
indata(126) := not r.x.ctrl.pv;
indata(125 downto 96) := dbgi.timer(29 downto 0);
indata(95 downto 64) := res;
indata(63 downto 34) := r.x.ctrl.pc(31 downto 2);
indata(33) := trap;
indata(32) := error;
indata(31 downto 0) := r.x.ctrl.inst;
vdi.addr(TBUFBITS-1 downto 0) := dsur.tbufcnt;
vdi.data := indata;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
vdi.enable := '1';
vdi.addr(TBUFBITS-1 downto 0) := dbgi.daddr(TBUFBITS-1+4 downto 4);
vdi_2p.renable := '1';
vdi_2p.raddr(TBUFBITS-1 downto 0) := dbgi.daddr(TBUFBITS-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => write(3) := '1';
when "01" => write(2) := '1';
when "10" => write(1) := '1';
when others => write(0) := '1';
end case;
indata(127 downto 0) := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
vdi.write := write;
vdi.data := indata;
vdi_2p.renable := '0';
vdi_2p.write := write;
vdi_2p.waddr(TBUFBITS-1 downto 0) := dbgi.daddr(TBUFBITS-1+4 downto 4);
vdi_2p.data := indata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug and
itfilt(r.x.ctrl.inst, dsur.tfilt, trap, dsur.cfc(4))) = '1' then
vdi.enable := holdn;
vdi.write := (others => '1');
vdi_2p.write := (others => '1');
vdi_2p.waddr(TBUFBITS-1 downto 0) := dsur.tbufcnt;
vdi_2p.data := indata;
tbufcnt := dsur.tbufcnt + 1;
end if;
if TRACEBUF_2P and ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
vdi_2p.renable := '1';
vdi_2p.raddr(TBUFBITS-1 downto 0) := dbgi.daddr(TBUFBITS-1+4 downto 4);
end if;
end if;
ov := tov;
di := vdi;
di_2p := vdi_2p;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if DBGUNIT then
if (r.x.rstate = dsu2)
then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant dc_in_res : dc_in_type := (
signed => '0',
enaddr => '0',
read => '0',
write => '0',
lock => '0',
dsuen => '0',
size => (others => '0'),
asi => (others => '0'));
constant pipeline_ctrl_res : pipeline_ctrl_type := (
pc => (others => '0'),
inst => (others => '0'),
cnt => (others => '0'),
rd => (others => '0'),
tt => (others => '0'),
trap => '0',
annul => '1',
wreg => '0',
wicc => '0',
wy => '0',
ld => '0',
pv => '0',
rett => '0');
constant fpc_res : pctype := conv_std_logic_vector(rstaddr, 20) & zero32(11 downto PCLOW);
constant fetch_reg_res : fetch_reg_type := (
pc => fpc_res, -- Needs special handling
branch => '0'
);
constant decode_reg_res : decode_reg_type := (
pc => (others => '0'),
inst => (others => (others => '0')),
cwp => (others => '0'),
set => (others => '0'),
mexc => '0',
cnt => (others => '0'),
pv => '0',
annul => '1',
inull => '0',
step => '0',
divrdy => '0',
pcheld => '0'
);
constant regacc_reg_res : regacc_reg_type := (
ctrl => pipeline_ctrl_res,
rs1 => (others => '0'),
rfa1 => (others => '0'),
rfa2 => (others => '0'),
rsel1 => (others => '0'),
rsel2 => (others => '0'),
rfe1 => '0',
rfe2 => '0',
cwp => (others => '0'),
imm => (others => '0'),
ldcheck1 => '0',
ldcheck2 => '0',
ldchkra => '1',
ldchkex => '1',
su => '1',
et => '0',
wovf => '0',
wunf => '0',
ticc => '0',
jmpl => '0',
step => '0',
mulstart => '0',
divstart => '0',
bp => '0',
nobp => '0',
bpimiss => '0'
);
constant execute_reg_res : execute_reg_type := (
ctrl => pipeline_ctrl_res,
op1 => (others => '0'),
op2 => (others => '0'),
aluop => (others => '0'),
alusel => "11",
aluadd => '1',
alucin => '0',
ldbp1 => '0',
ldbp2 => '0',
invop2 => '0',
shcnt => (others => '0'),
sari => '0',
shleft => '0',
ymsb => '0',
rd => (others => '0'),
jmpl => '0',
su => '0',
et => '0',
cwp => (others => '0'),
icc => (others => '0'),
mulstep => '0',
mul => '0',
mac => '0',
bp => '0',
rfe1 => '0',
rfe2 => '0'
);
constant memory_reg_res : memory_reg_type := (
ctrl => pipeline_ctrl_res,
result => (others => '0'),
y => (others => '0'),
icc => (others => '0'),
nalign => '0',
dci => dc_in_res,
werr => '0',
wcwp => '0',
irqen => '0',
irqen2 => '0',
mac => '0',
divz => '0',
su => '0',
mul => '0',
casa => '0',
casaz => '0'
);
function xnpc_res return std_logic_vector is
begin
if v8 /= 0 then return "100"; end if;
return "011";
end function xnpc_res;
constant exception_reg_res : exception_reg_type := (
ctrl => pipeline_ctrl_res,
result => (others => '0'),
y => (others => '0'),
icc => (others => '0'),
annul_all => '1',
data => (others => (others => '0')),
set => (others => '0'),
mexc => '0',
dci => dc_in_res,
laddr => (others => '0'),
rstate => run, -- Has special handling
npc => xnpc_res,
intack => '0',
ipend => '0',
mac => '0',
debug => '0', -- Has special handling
nerror => '0',
ipmask => '0'
);
constant DRES : dsu_registers := (
tt => (others => '0'),
err => '0',
tbufcnt => (others => '0'),
asi => (others => '0'),
crdy => (others => '0'),
tfilt => (others => '0'),
cfc => (others => '0'),
tlim => (others => '0'),
tov => '0',
tovb => '0'
);
constant IRES : irestart_register := (
addr => (others => '0'), pwd => '0'
);
constant PRES : pwd_register_type := (
pwd => '0', -- Needs special handling
error => '0'
);
--constant special_register_res : special_register_type := (
-- cwp => zero32(NWINLOG2-1 downto 0),
-- icc => (others => '0'),
-- tt => (others => '0'),
-- tba => fpc_res(31 downto 12),
-- wim => (others => '0'),
-- pil => (others => '0'),
-- ec => '0',
-- ef => '0',
-- ps => '1',
-- s => '1',
-- et => '0',
-- y => (others => '0'),
-- asr18 => (others => '0'),
-- svt => '0',
-- dwt => '0',
-- dbp => '0'
-- );
--XST workaround:
function special_register_res return special_register_type is
variable s : special_register_type;
begin
s.cwp := zero32(NWINLOG2-1 downto 0);
s.icc := (others => '0');
s.tt := (others => '0');
s.tba := fpc_res(31 downto 12);
s.wim := (others => '0');
s.pil := (others => '0');
s.ec := '0';
s.ef := '0';
s.ps := '1';
s.s := '1';
s.et := '0';
s.y := (others => '0');
s.asr18 := (others => '0');
s.svt := '0';
s.dwt := '0';
s.dbp := '0';
s.dbprepl := '1';
return s;
end function special_register_res;
--constant write_reg_res : write_reg_type := (
-- s => special_register_res,
-- result => (others => '0'),
-- wa => (others => '0'),
-- wreg => '0',
-- except => '0'
-- );
-- XST workaround:
function write_reg_res return write_reg_type is
variable w : write_reg_type;
begin
w.s := special_register_res;
w.result := (others => '0');
w.wa := (others => '0');
w.wreg := '0';
w.except := '0';
return w;
end function write_reg_res;
constant RRES : registers := (
f => fetch_reg_res,
d => decode_reg_res,
a => regacc_reg_res,
e => execute_reg_res,
m => memory_reg_res,
x => exception_reg_res,
w => write_reg_res
);
constant exception_res : exception_type := (
pri => '0',
ill => '0',
fpdis => '0',
cpdis => '0',
wovf => '0',
wunf => '0',
ticc => '0'
);
constant wpr_none : watchpoint_register := (
addr => zero32(31 downto 2),
mask => zero32(31 downto 2),
exec => '0',
load => '0',
store => '0');
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(RFBITS-5 downto 0) :=
conv_std_logic_vector(NWIN, RFBITS-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(RFBITS -1 downto 4) := globals;
else
ra(NWINLOG2+3 downto 4) := cwp + ra(4);
if ra(RFBITS-1 downto 4) = globals then
ra(RFBITS-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type;
dsur : dsu_registers)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = Zero32(31 downto 2)) then
exc := '1';
end if;
end if;
end loop;
if DBGUNIT then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((((debug.dbreak and debug.bwatch) or r.a.step)) or
(debug.bwatch and dsur.tovb and dsur.tov)));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := zero32 & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := zero32; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not MACEN then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not MULEN then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not DIVEN then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY =>
if rd(4) = '1' and rd(3 downto 0) /= "0010" then -- %ASR16-17, %ASR19-31
privileged_inst := not r.a.su;
end if;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0);
if (npasi = 0) or (inst(12) = '0') then
privileged_inst := not r.a.su;
end if;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13);
if (npasi = 0) or (inst(12) = '0') then
privileged_inst := not r.a.su;
end if;
when CASA =>
if CASAEN then
illegal_inst := inst(13);
if (inst(12 downto 5) /= X"0A") then privileged_inst := not r.a.su; end if;
else illegal_inst := '1'; end if;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi, dsur);
trap := '1';
if r.a.ctrl.trap = '1' then tt := r.a.ctrl.tt;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if MACEN then wy := '1'; end if;
when UMULCC | SMULCC =>
if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if DIVEN and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or
(r.x.rstate = dsu2)
or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(NWINLOG2-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(NWIN-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(NWIN-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not CWPOPT) and (r.d.cwp = CWPMIN) then ncwp := CWPMAX;
else ncwp := r.d.cwp - 1 ; end if;
else
if (not CWPOPT) and (r.d.cwp = CWPMAX) then ncwp := CWPMIN;
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
function icc_valid(r : registers) return std_logic is
variable not_valid : std_logic;
begin
not_valid := '0';
if MULEN or DIVEN then
not_valid := r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul);
end if;
not_valid := not_valid or (r.a.ctrl.wicc or r.e.ctrl.wicc);
return(not not_valid);
end;
procedure bp_miss_ex(r : registers; icc : std_logic_vector(3 downto 0);
ex_bpmiss, ra_bpannul : out std_logic) is
variable miss : std_logic;
begin
miss := (not r.e.ctrl.annul) and r.e.bp and not branch_true(icc, r.e.ctrl.inst);
ra_bpannul := miss and r.e.ctrl.inst(29);
ex_bpmiss := miss;
end;
procedure bp_miss_ra(r : registers; ra_bpmiss, de_bpannul : out std_logic) is
variable miss : std_logic;
begin
miss := ((not r.a.ctrl.annul) and r.a.bp and icc_valid(r) and not branch_true(r.m.icc, r.a.ctrl.inst));
de_bpannul := miss and r.a.ctrl.inst(29);
ra_bpmiss := miss;
end;
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn, de_wcwp : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex, bp, nobp, de_fins_hold : out std_ulogic;
iperr : std_logic; icbpmiss: std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_logic;
variable icc_check_bp, y_hold, mul_hold, bicc_hold_bp, fins, call_hold : std_ulogic;
variable de_fins_holdx : std_ulogic;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0'; y_hold := '0'; bp := '0'; mul_hold := '0';
icc_check_bp := '0'; nobp := '0'; fins := '0'; call_hold := '0';
if (r.d.annul = '0') and (icbpmiss='0')
then
case op is
when CALL =>
call_hold := '1'; nobp := BPRED;
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check_bp := '1';
end if;
if (op2 = BICC) then nobp := BPRED; end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
nobp := BPRED;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if MACPIPE then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
when SDIV | SDIVCC | UDIV | UDIVCC =>
if DIVEN then y_check := '1'; nobp := op3(4); end if; -- no BP on divcc
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0'; fins := BPRED;
when JMPL => call_hold := '1'; nobp := BPRED;
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') and (op3(5) = '0') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" =>
ldcheck2 := not i;
if (op3(5) and op3(2) and not op3(3)) = '1' then ldcheck1 := '0'; ldcheck2 := '0'; end if; -- STF/STC
when others => ldchkex := '0';
if CASAEN and (op3(5 downto 3) = "111") then
ldcheck2 := '1';
elsif (op3(5) = '1') or ((op3(5) & op3(3 downto 1)) = "0110") -- LDST
then ldcheck1 := '0'; ldcheck2 := '0'; end if;
end case;
if op3(5) = '1' then fins := BPRED; end if; -- no BP on FPU/CP LD/ST
when others => null;
end case;
end if;
if MULEN or DIVEN then
chkmul := mulinsn;
mul_hold := (r.a.mulstart and r.a.ctrl.wicc) or (r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
if (MULTYPE = 0) and ((icc_check_bp and BPRED and r.a.ctrl.wicc and r.a.ctrl.wy) = '1')
then mul_hold := '1'; end if;
else chkmul := '0'; end if;
if DIVEN then
y_hold := y_check and (r.a.ctrl.wy or r.e.ctrl.wy);
chkmul := chkmul or divinsn;
end if;
bicc_hold := icc_check and not icc_valid(r);
bicc_hold_bp := icc_check_bp and not icc_valid(r);
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (MACPIPE and (r.e.mac = '1')) or ((MULTYPE = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
de_fins_holdx := BPRED and fins and (r.a.bp or r.e.bp); -- skip BP on FPU inst in branch target address
de_fins_hold := de_fins_holdx;
ldlock := ldlock or y_hold or fpc_lock or (BPRED and r.a.bp and r.a.ctrl.inst(29) and de_wcwp) or de_fins_holdx;
if ((icc_check_bp and BPRED) = '1') and ((r.a.nobp or mul_hold) = '0') then
bp := bicc_hold_bp;
else ldlock := ldlock or bicc_hold or bicc_hold_bp; end if;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic; rabpmiss, exbpmiss, iperr : std_logic;
icbpmiss, eocl: std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl, inhibit_current : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0'; inhibit_current := '0';
if (r.d.annul = '0') and not (icbpmiss = '1' and r.d.pcheld='0')
then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (CPEN and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (CPEN and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true or (BPRED and orv(cond) and not icc_valid(r)); end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul_next or annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if MULEN and (MULTYPE /= 0) then mulstart := '1'; end if;
if MULEN and (MULTYPE = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
case r.d.cnt is
when "00" =>
hold_pc := '1'; pv := '0';
if r.d.divrdy = '0' then
cnt := "01"; divstart := '1';
end if;
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
if (BLOCKBPMISS and (eocl or r.f.branch) and r.e.bp)='1' then
hold_pc := '1'; annul_current := '1';
end if;
when WRY =>
if PWRD1 then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD/CASA
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
(CASAEN and (op3(5 downto 4) = "11")) or -- CASA
((CPEN or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if icbpmiss='1' and r.d.annul='0' then
annul_current := '1'; annul_next := '1'; pv := '0'; hold_pc := '0';
end if;
if ((exbpmiss and r.a.ctrl.annul and r.d.pv and not hold_pc) = '1') then
annul_next := '1'; pv := '0';
end if;
if ((exbpmiss and not r.a.ctrl.annul and r.d.pv) = '1') then
annul_next := '1'; pv := '0'; annul_current := '1';
end if;
if ((exbpmiss and not r.a.ctrl.annul and not r.d.pv and not hold_pc) = '1') then
annul_next := '1'; pv := '0';
end if;
if ((exbpmiss and r.e.ctrl.inst(29) and not r.a.ctrl.annul and not r.d.pv ) = '1')
and (r.d.cnt = "01") then
annul_next := '1'; annul_current := '1'; pv := '0';
end if;
if (exbpmiss and r.e.ctrl.inst(29) and r.a.ctrl.annul and r.d.pv) = '1' then
annul_next := '1'; pv := '0'; inhibit_current := '1';
end if;
if (exbpmiss and r.e.ctrl.inst(29) and BLOCKBPMISS and r.a.bpimiss) = '1' then
annul_next := '1'; pv := '0';
end if;
if (rabpmiss and not r.a.ctrl.inst(29) and not r.d.annul and r.d.pv and not hold_pc) = '1' then
annul_next := '1'; pv := '0';
end if;
if (rabpmiss and r.a.ctrl.inst(29) and not r.d.annul and r.d.pv ) = '1' then
annul_next := '1'; pv := '0'; inhibit_current := '1';
end if;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or (ldlock and not inhibit_current) or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current or inhibit_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current and not inhibit_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if MULEN then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((CPEN or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA | CASA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(IMPL,4) &
conv_std_logic_vector(VER,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(NWINLOG2-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(NWIN-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_logic
) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0, i : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
rs1 := r.a.ctrl.inst(18 downto 14); i := r.a.ctrl.inst(13);
rs2 := r.a.ctrl.inst(4 downto 0); rd := r.a.ctrl.inst(29 downto 25);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if MULEN then mulins := '1'; end if;
when UMAC | SMAC =>
if MACEN then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if DIVEN then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA | CASA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(5) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB
end if;
if CASAEN and (r.m.casa = '1') then
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word; id : std_logic) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
if CASAEN and (r.a.ctrl.cnt = "10") and ((r.m.casa and not id) = '1') then ldbp := '1'; end if;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif (r.m.ctrl.wreg = '1') and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and (r.x.ctrl.wreg = '1') and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when LDST =>
if CASAEN and (r.m.casa = '1') and (r.a.ctrl.cnt = "10") then
cin := '1';
end if;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if DIVEN then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif MACPIPE and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
function st_align(size : std_logic_vector(1 downto 0); bpdata : word) return word is
variable edata : word;
begin
case size is
when "01" => edata := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
when "10" => edata := bpdata(15 downto 0) & bpdata(15 downto 0);
when others => edata := bpdata;
end case;
return(edata);
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if MULEN and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if MACEN then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz, mzero : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
variable azero : std_logic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
if addout(32 downto 1) = zero32 then azero := '1'; else azero := '0'; end if;
mzero := azero;
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
-- if aluresult = zero32 then icc(2) := '1'; end if;
icc(2) := azero;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = zero32 then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load, mcasa : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su, lock : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
mcasa := '0';
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when CASA => if CASAEN then dci.size := SZWORD; dci.lock := '1'; end if;
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if CPEN then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul or r.e.ctrl.trap) = '0' then
case op is
when CALL => link_pc := '1';
when FMT3 =>
if r.e.ctrl.trap = '0' then
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
end if;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP/CASA
load := op3(3) or not op3(2);
--dci.enaddr := '1';
dci.enaddr := (not op3(2)) or op3(2)
or (op3(3) and op3(2));
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if (CASAEN and (op3(5 downto 4) = "11")) or -- CASA
(op3(3 downto 2) = "11") then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP/CASA
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
if (CASAEN and (op3(5 downto 4) = "11")) then mcasa := '1'; end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not CPEN) then
dci.asi := r.e.ctrl.inst(12 downto 5);
if r.e.ctrl.inst(12 downto 10) /= "000" then dci.enaddr := '0'; end if;
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
if CASAEN and (r.m.casa = '1') and (r.e.ctrl.cnt = "10") then
edata2 := r.e.op1; eres2 := r.e.op1;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(DSETMSB downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(NWINLOG2-1 downto 0);
variable cwpx : std_logic_vector(5 downto NWINLOG2);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto NWINLOG2); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if (trap = '1') and (r.m.ctrl.pv = '1') then
if op = LDST then nullify := '1'; end if;
end if;
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if CPEN and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if CPEN and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if CPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if CPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif CPEN and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA | CASA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = zero32(31 downto 2)))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd
;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif MACEN and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
if bp = 2 then s.dbp := r.x.result(27); end if;
if bp = 2 then s.dbprepl := r.x.result(25); end if;
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
if pwrpsr = 0 or rd = "00000" then
s.cwp := r.x.result(NWINLOG2-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
end if;
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(NWIN-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not CWPOPT) and (r.w.s.cwp = CWPMIN) then s.cwp := CWPMAX;
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not CWPOPT) and (r.w.s.cwp = CWPMAX) then s.cwp := CWPMIN;
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not CWPOPT) and (r.w.s.cwp = CWPMAX) then s.cwp := CWPMIN;
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if MACPIPE and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif v8 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if v8 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if MULEN then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if MULEN then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if MACEN and not MACPIPE then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if DIVEN then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if DIVEN then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
begin
BPRED <= '0' when bp = 0 else '1' when bp = 1 else not r.w.s.dbp;
BLOCKBPMISS <= '0' when bp = 0 else '1' when bp = 1 else r.w.s.dbprepl;
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo, tbo_2p,
mulo, divo, dummy, rp, BPRED, BLOCKBPMISS)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable fe_pc, fe_npc : std_logic_vector(31 downto PCLOW);
variable npc : std_logic_vector(31 downto PCLOW);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable de_bpannul : std_ulogic;
variable de_fins_hold : std_ulogic;
variable de_iperr : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ra_bpmiss : std_ulogic;
variable ra_bpannul : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, ex_result3, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable ex_bpmiss : std_ulogic;
variable ex_cdata : std_logic_vector(31 downto 0);
variable ex_mulop1, ex_mulop2 : std_logic_vector(32 downto 0);
variable me_bp_res : word;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_newtt, xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable tbufi_2p : tracebuf_2p_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable xc_dflushl : std_ulogic;
variable xc_dcperr : std_ulogic;
variable st : std_ulogic;
variable icnt, fcnt : std_ulogic;
variable tbufcntx : std_logic_vector(TBUFBITS-1 downto 0);
variable tovx : std_ulogic;
variable bpmiss : std_ulogic;
begin
v := r; vwpr := wpr; vdsu := dsur; vp := rp;
xc_fpexack := '0'; sidle := '0';
fpcdbgwr := '0'; vir := ir; xc_rstn := rstn;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0'; xc_halt := '0'; icnt := '0'; fcnt := '0';
xc_waddr := (others => '0');
xc_waddr(RFBITS-1 downto 0) := r.x.ctrl.rd(RFBITS-1 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error; xc_dflushl := '0';
if r.x.mexc = '1' then xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else xc_vectt := "00" & r.x.ctrl.tt; end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 2) := r.w.s.tba & xc_vectt & "00";
else
xc_trap_address(31 downto 2) := r.w.s.tba & "00000000" & "00";
end if;
xc_trap_address(2 downto PCLOW) := (others => '0');
xc_wreg := '0'; v.x.annul_all := '0';
if (not r.x.ctrl.annul and r.x.ctrl.ld) = '1' then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else
xc_result := r.x.data(0);
end if;
elsif MACEN and MACPIPE and ((not r.x.ctrl.annul and r.x.mac) = '1') then
xc_result := mulo.result(31 downto 0);
else xc_result := r.x.result; end if;
xc_df_result := xc_result;
if DBGUNIT
then
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt, dsur);
if (dbgi.dsuen and dbgi.dbreak) = '0'then v.x.debug := '0'; end if;
else dbgm := '0'; v.x.debug := '0'; end if;
if PWRD2 then pwrd := powerdwn(r, xc_trap, rp); else pwrd := '0'; end if;
case r.x.rstate is
when run =>
if (dbgm
) /= '0' then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt; vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.npc := npc_find(r); vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
if (r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
if (r.x.ctrl.inst(31 downto 30) = FMT3) and
((r.x.ctrl.inst(24 downto 19) = FPOP1) or
(r.x.ctrl.inst(24 downto 19) = FPOP2))
then fcnt := holdn; end if;
end if;
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1'; xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1'; v.w.s.tt := xc_vectt; v.w.s.ps := r.w.s.s;
v.w.s.s := '1'; v.x.annul_all := '1'; v.x.rstate := trap;
xc_waddr := (others => '0');
xc_waddr(NWINLOG2 + 3 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
-- v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r); xc_wreg := '1';
xc_waddr := (others => '0');
xc_waddr(NWINLOG2 + 3 downto 0) := r.w.s.cwp & "0010";
if r.w.s.et = '1' then
v.w.s.et := '0'; v.x.rstate := run;
if (not CWPOPT) and (r.w.s.cwp = CWPMIN) then v.w.s.cwp := CWPMAX;
else v.w.s.cwp := r.w.s.cwp - 1 ; end if;
else
v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto PCLOW) := r.f.pc;
if DBGUNIT or PWRD2 or (smp /= 0)
then
xc_trap_address(31 downto PCLOW) := ir.addr;
vir.addr := npc_gen(r)(31 downto PCLOW);
v.x.rstate := dsu2;
end if;
if DBGUNIT then v.x.debug := r.x.debug; end if;
when dsu2 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto PCLOW) := r.f.pc;
if DBGUNIT or PWRD2 or (smp /= 0)
then
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if DBGUNIT then
if dbgi.reset = '1' then
if smp /=0 then vp.pwd := not irqi.run; else vp.pwd := '0'; end if;
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then v.x.debug := '1'; end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address,
vir.addr, vdsu.tbufcnt, vdsu.tfilt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
end if;
if r.x.ipend = '1' then vp.pwd := '0'; end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run; v.x.annul_all := '0'; vp.error := '0';
xc_trap_address(31 downto PCLOW) := ir.addr; v.x.debug := '0';
vir.pwd := '1';
end if;
if (smp /= 0) and (irqi.rst = '1') then
vp.pwd := '0'; vp.error := '0';
end if;
end if;
when others =>
end case;
if DBGUNIT and TRACEBUF then
if (dbgi.dsuen and dbgi.denable and dbgi.dwrite) = '1' then
if (dbgi.daddr(23 downto 20) = "0001" and dbgi.daddr(16) = '1' and
dbgi.daddr(2) = '1') then
vdsu.tov := dbgi.ddata(23);
vdsu.tlim := dbgi.ddata(26 downto 24);
vdsu.tovb := dbgi.ddata(27);
end if;
end if;
end if;
dci.flushl <= xc_dflushl;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tovx, tbufi, tbufi_2p, '0', xc_dcperr);
vdsu.tbufcnt := tbufcntx; vdsu.tov := tovx;
v.w.except := xc_exception; v.w.result := xc_result;
if (r.x.rstate = dsu2) then v.w.except := '0'; end if;
v.w.wa := xc_waddr(RFBITS-1 downto 0); v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result; rfi.waddr <= xc_waddr;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
irqo.idle <= '0';
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dbgo.fcnt <= fcnt;
dbgo.optype <= r.x.ctrl.inst(31 downto 30) & r.x.ctrl.inst(24 downto 21);
dci.intack <= r.x.intack and holdn;
if (not RESET_ALL) and (xc_rstn = '0') then
v.w.except := RRES.w.except; v.w.s.et := RRES.w.s.et;
v.w.s.svt := RRES.w.s.svt; v.w.s.dwt := RRES.w.s.dwt;
v.w.s.ef := RRES.w.s.ef;
if need_extra_sync_reset(fabtech) /= 0 then
v.w.s.cwp := RRES.w.s.cwp;
v.w.s.icc := RRES.w.s.icc;
end if;
v.w.s.dbp := RRES.w.s.dbp;
v.w.s.dbprepl := RRES.w.s.dbprepl;
v.x.ipmask := RRES.x.ipmask;
v.w.s.tba := RRES.w.s.tba;
v.x.annul_all := RRES.x.annul_all;
v.x.rstate := RRES.x.rstate; vir.pwd := IRES.pwd;
vp.pwd := PRES.pwd; v.x.debug := RRES.x.debug;
v.x.nerror := RRES.x.nerror;
if svt = 1 then v.w.s.tt := RRES.w.s.tt; end if;
if DBGUNIT then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1; v.x.debug := '1';
end if;
vdsu.tfilt := DRES.tfilt; vdsu.tovb := DRES.tovb;
end if;
if (index /= 0) and (irqi.run = '0') and (rstn = '0') then
v.x.rstate := dsu1; vp.pwd := '1';
end if;
v.x.npc := "100";
end if;
-- kill off unused regs
if not FPEN then v.w.s.ef := '0'; end if;
if not CPEN then v.w.s.ec := '0'; end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl; v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac; v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
st := '0';
if CASAEN and (r.m.casa = '1') and (r.m.ctrl.cnt = "00") then
v.x.ctrl.inst(4 downto 0) := r.a.ctrl.inst(4 downto 0); -- restore rs2 for trace log
end if;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush,
me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify,
v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap,
v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or st or not dco.mds) = '1' then
for i in 0 to dsets-1 loop
v.x.data(i) := dco.data(i);
end loop;
v.x.set := dco.set(DSETMSB downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size; me_laddr := r.x.laddr; me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size; me_laddr := v.x.laddr; me_signed := v.x.dci.signed;
end if;
if (lddel /= 2) then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
if (not RESET_ALL) and (is_fpga(fabtech) = 0) and (xc_rstn = '0') then
v.x.data := (others => (others => '0')); --v.x.ldc := '0';
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if MACEN and ((v.x.ctrl.annul or v.x.ctrl.trap) = '0') then
v.w.s.asr18 := me_asr18;
end if;
if (r.x.rstate = dsu2)
then
me_nullify2 := '0'; v.x.set := dco.set(DSETMSB downto 0);
end if;
if (not RESET_ALL) and (xc_rstn = '0') then
v.x.ctrl.trap := '0'; v.x.ctrl.annul := '1';
end if;
dci.maddress <= r.m.result;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.lock <= (r.m.dci.lock and not r.m.ctrl.annul);
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl; ex_op1 := r.e.op1; ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb; mul_op2 := ex_op2; ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp; ex_sari := r.e.sari;
v.m.su := r.e.su;
if MULTYPE = 3 then v.m.mul := r.e.mul; else v.m.mul := '0'; end if;
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0); ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2; ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2; ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then v.m.nalign := '0';
else v.m.nalign := '1'; end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load, v.m.casa);
ex_jump_address := ex_add_res(32 downto PCLOW+1);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res,
ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz, v.m.casaz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, ex_result3);
v.m.result := ex_result3;
cwp_ex(r, v.m.wcwp);
if CASAEN and (r.e.ctrl.cnt = "10") and ((r.m.casa and not v.m.casaz) = '1') then
me_nullify2 := '1';
end if;
dci.nullify <= me_nullify2;
ex_mulop1 := (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
ex_mulop2 := (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
if is_fpga(fabtech) = 0 and (r.e.mul = '0') then -- power-save for mul
-- if (r.e.mul = '0') then
ex_mulop1 := (others => '0'); ex_mulop2 := (others => '0');
end if;
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (DBGUNIT and (r.x.rstate = dsu2)) then v.m.ctrl.ld := '1'; end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
bp_miss_ex(r, r.m.icc, ex_bpmiss, ra_bpannul);
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl; v.e.jmpl := r.a.jmpl and not r.a.ctrl.trap;
v.e.ctrl.annul := r.a.ctrl.annul or ra_bpannul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul and not r.a.ctrl.trap;
v.e.ctrl.wreg := r.a.ctrl.wreg and not (ra_bpannul or v.x.annul_all);
v.e.su := r.a.su; v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not (ra_bpannul or v.x.annul_all);
v.e.rfe1 := r.a.rfe1; v.e.rfe2 := r.a.rfe2;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt,
v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, ex_result3, v.x.result, xc_df_result, zero32,
r.a.rsel1, v.e.ldbp1, ra_op1, '0');
op_mux(r, rfo.data2, ex_result3, v.x.result, xc_df_result, r.a.imm,
r.a.rsel2, ex_ldbp2, ra_op2, '1');
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2,
v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft,
v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2
);
cin_gen(r, v.m.icc(0), v.e.alucin);
bp_miss_ra(r, ra_bpmiss, de_bpannul);
v.e.bp := r.a.bp and not ra_bpmiss;
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
if ISETS > 1 then de_inst := r.d.inst(conv_integer(r.d.set));
else de_inst := r.d.inst(0); end if;
de_icc := r.m.icc; v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
if CASAEN and (de_inst(31 downto 30) = LDST) and (de_inst(24 downto 19) = CASA) then
case r.d.cnt is
when "00" | "01" => de_inst(4 downto 0) := "00000"; -- rs2=0
when others =>
end case;
end if;
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := (others => '0'); de_raddr2 := (others => '0');
if RS1OPT then
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(RFBITS-1 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(RFBITS-1 downto 0));
end if;
else
regaddr(r.d.cwp, v.a.rs1, de_raddr1(RFBITS-1 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(RFBITS-1 downto 0));
v.a.rfa1 := de_raddr1(RFBITS-1 downto 0);
v.a.rfa2 := de_raddr2(RFBITS-1 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
de_iperr := '0';
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst,
fpo.ldlock, v.e.mul, ra_div, de_wcwp, v.a.ldcheck1, v.a.ldcheck2, de_ldlock,
v.a.ldchkra, v.a.ldchkex, v.a.bp, v.a.nobp, de_fins_hold, de_iperr, ico.bpmiss);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst),
de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch,
v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv,
de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart,
ra_bpmiss, ex_bpmiss, de_iperr, ico.bpmiss, ico.eocl);
v.d.pcheld := de_hold_pc;
v.a.bp := v.a.bp and not v.a.ctrl.annul;
v.a.nobp := v.a.nobp and not v.a.ctrl.annul;
v.a.ctrl.inst := de_inst;
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1,
false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2,
imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
v.a.ctrl.wicc := v.a.ctrl.wicc and (not v.a.ctrl.annul)
;
v.a.ctrl.wreg := v.a.ctrl.wreg and (not v.a.ctrl.annul)
;
v.a.ctrl.rett := v.a.ctrl.rett and (not v.a.ctrl.annul)
;
v.a.ctrl.wy := v.a.ctrl.wy and (not v.a.ctrl.annul)
;
v.a.ctrl.trap := r.d.mexc
;
v.a.ctrl.tt := "000000";
if r.d.mexc = '1' then
v.a.ctrl.tt := "000001";
end if;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(RFBITS-1 downto 0) := r.a.rfa1;
de_raddr2(RFBITS-1 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1; de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1; de_ren2 := v.a.rfe2;
end if;
if DBGUNIT then
if (dbgi.denable = '1') and (r.x.rstate = dsu2) then
de_raddr1(RFBITS-1 downto 0) := dbgi.daddr(RFBITS+1 downto 2); de_ren1 := '1';
de_raddr2 := de_raddr1; de_ren2 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
end if;
rfi.wren <= (xc_wreg and holdn);
rfi.raddr1 <= de_raddr1; rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1;
rfi.ren2 <= de_ren2;
ici.inull <= de_inull
;
ici.flush <= me_iflush;
v.d.divrdy := divo.nready;
ici.fline <= r.x.ctrl.pc(31 downto 3);
ici.nobpmiss <= (r.a.bp or r.e.bp) and BLOCKBPMISS;
dbgo.bpmiss <= bpmiss and holdn;
if (xc_rstn = '0') then
v.d.cnt := (others => '0');
if need_extra_sync_reset(fabtech) /= 0 then
v.d.cwp := (others => '0');
end if;
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
bpmiss := ex_bpmiss or ra_bpmiss;
npc := r.f.pc; fe_pc := r.f.pc;
if ra_bpmiss = '1' then fe_pc := r.d.pc; end if;
if ex_bpmiss = '1' then fe_pc := r.a.ctrl.pc; end if;
fe_npc := zero32(31 downto PCLOW);
fe_npc(31 downto 2) := fe_pc(31 downto 2) + 1; -- Address incrementer
v.a.bpimiss := '0';
if (xc_rstn = '0') then
if (not RESET_ALL) then
v.f.pc := (others => '0'); v.f.branch := '0';
if DYNRST then v.f.pc(31 downto 12) := irqi.rstvec;
else
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
end if;
end if;
elsif xc_exception = '1' then -- exception
v.f.branch := '1'; v.f.pc := xc_trap_address;
npc := v.f.pc;
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc; v.f.branch := r.f.branch;
if bpmiss = '1' then
v.f.pc := fe_npc; v.f.branch := '1';
npc := v.f.pc;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
end if;
elsif (ex_jump and not bpmiss) = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
elsif (((ico.bpmiss and not r.d.annul) or r.a.bpimiss) and not bpmiss) = '1' then
v.f.pc := r.d.pc; v.f.branch := '1';
npc := v.f.pc;
v.a.bpimiss := ico.bpmiss and not r.d.annul;
elsif (de_branch and not bpmiss
) = '1'
then
v.f.pc := branch_address(de_inst, r.d.pc); v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := bpmiss; v.f.pc := fe_npc; npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
if (ico.mds and de_hold_pc) = '0' then
for i in 0 to isets-1 loop
v.d.inst(i) := ico.data(i); -- latch instruction
end loop;
v.d.set := ico.set(ISETMSB downto 0); -- latch instruction
v.d.mexc := ico.mexc; -- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
if DBGUNIT then -- DSU diagnostic read
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, tbo_2p, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
vdsu.cfc := dsur.cfc(5 downto 0) & r.f.branch;
end if;
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v; wprin <= vwpr; dsuin <= vdsu; irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul and
not r.a.ctrl.trap and not ra_bpannul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= ex_mulop1; --(ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= ex_mulop2; --(mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
if MACPIPE then muli.acc(39 downto 32) <= r.w.s.y(7 downto 0);
else muli.acc(39 downto 32) <= r.x.y(7 downto 0); end if;
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul and
not r.a.ctrl.trap and not ra_bpannul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else dsign := r.e.ctrl.inst(19); end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
if DBGUNIT then
dbgo.dsu <= '1'; dbgo.dsumode <= r.x.debug; dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
if TRACEBUF then
tbi <= tbufi;
if TRACEBUF_2P then tbi_2p <= tbufi_2p; else tbi_2p <= tracebuf_2p_in_type_none; end if;
else
tbi <= tracebuf_in_type_none;
tbi_2p <= tracebuf_2p_in_type_none;
end if;
else
dbgo.dsu <= '0'; dbgo.data <= (others => '0'); dbgo.crdy <= '0';
dbgo.dsumode <= '0'; tbi.addr <= (others => '0');
tbi.data <= (others => '0'); tbi.enable <= '0';
tbi.write <= (others => '0');
end if;
dbgo.error <= dummy and not r.x.nerror;
dbgo.istat <= ico.cstat;
dbgo.dstat <= dco.cstat;
dbgo.wbhold <= dco.wbhold;
dbgo.su <= r.w.s.s;
if FPEN then
if (r.x.rstate = dsu2) then vfpi.flush := '1'; else vfpi.flush := v.x.annul_all and holdn; end if;
vfpi.exack := xc_fpexack; vfpi.a_rs1 := r.a.rs1; vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt;
vfpi.d.annul := v.x.annul_all or de_bpannul or r.d.annul or de_fins_hold or (ico.bpmiss and not r.d.pcheld)
;
vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0'); vfpi.d.pc(31 downto PCLOW) := r.d.pc(31 downto PCLOW);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0'); vfpi.a.pc(31 downto PCLOW) := r.a.ctrl.pc(31 downto PCLOW);
vfpi.a.inst := r.a.ctrl.inst; vfpi.a.cnt := r.a.ctrl.cnt; vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul or (ex_bpmiss and r.e.ctrl.inst(29))
;
vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0'); vfpi.e.pc(31 downto PCLOW) := r.e.ctrl.pc(31 downto PCLOW);
vfpi.e.inst := r.e.ctrl.inst; vfpi.e.cnt := r.e.ctrl.cnt; vfpi.e.trap := r.e.ctrl.trap; vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0'); vfpi.m.pc(31 downto PCLOW) := r.m.ctrl.pc(31 downto PCLOW);
vfpi.m.inst := r.m.ctrl.inst; vfpi.m.cnt := r.m.ctrl.cnt; vfpi.m.trap := r.m.ctrl.trap; vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0'); vfpi.x.pc(31 downto PCLOW) := r.x.ctrl.pc(31 downto PCLOW);
vfpi.x.inst := r.x.ctrl.inst; vfpi.x.cnt := r.x.ctrl.cnt; vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul; vfpi.x.pv := r.x.ctrl.pv;
if (lddel = 2) then vfpi.lddata := r.x.data(conv_integer(r.x.set)); else vfpi.lddata := r.x.data(0); end if;
if (r.x.rstate = dsu2)
then vfpi.dbg.enable := dbgi.denable;
else vfpi.dbg.enable := '0'; end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22); -- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi; -- dummy, just to kill some warnings ...
end if;
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then
rp.error <= PRES.error;
if RESET_ALL then
if (index /= 0) and (irqi.run = '0') then
rp.pwd <= '1';
else
rp.pwd <= '0';
end if;
end if;
end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
if RESET_ALL then
r <= RRES;
if DYNRST then
r.f.pc(31 downto 12) <= irqi.rstvec;
r.w.s.tba <= irqi.rstvec;
end if;
if DBGUNIT then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
r.x.rstate <= dsu1; r.x.debug <= '1';
end if;
end if;
if (index /= 0) and irqi.run = '0' then
r.x.rstate <= dsu1;
end if;
else
r.w.s.s <= '1'; r.w.s.ps <= '1';
if need_extra_sync_reset(fabtech) /= 0 then
r.d.inst <= (others => (others => '0'));
r.x.mexc <= '0';
end if;
end if;
end if;
end if;
end process;
dsugen : if DBGUNIT generate
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if rstn = '0' then
if RESET_ALL then
dsur <= DRES;
elsif need_extra_sync_reset(fabtech) /= 0 then
dsur.err <= '0'; dsur.tbufcnt <= (others => '0'); dsur.tt <= (others => '0');
dsur.asi <= (others => '0'); dsur.crdy <= (others => '0');
end if;
end if;
end if;
end process;
end generate;
nodsugen : if not DBGUNIT generate
dsur.err <= '0'; dsur.tbufcnt <= (others => '0'); dsur.tt <= (others => '0');
dsur.asi <= (others => '0'); dsur.crdy <= (others => '0');
dsur.tfilt <= (others => '0'); dsur.cfc <= (others => '0');
dsur.tlim <= (others => '0'); dsur.tov <= '0'; dsur.tovb <= '0';
end generate;
irreg : if DBGUNIT or PWRD2
generate
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then ir <= irin; end if;
if RESET_ALL and rstn = '0' then ir <= IRES; end if;
end if;
end process;
end generate;
nirreg : if not (DBGUNIT or PWRD2
)
generate
ir.pwd <= '0'; ir.addr <= (others => '0');
end generate;
wpgen : for i in 0 to 3 generate
wpg0 : if nwp > i generate
wpreg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then wpr(i) <= wprin(i); end if;
if rstn = '0' then
if RESET_ALL then
wpr(i) <= wpr_none;
else
wpr(i).exec <= '0'; wpr(i).load <= '0'; wpr(i).store <= '0';
end if;
end if;
end if;
end process;
end generate;
wpg1 : if nwp <= i generate
wpr(i) <= wpr_none;
end generate;
end generate;
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
begin
if (fpu /= 0) then
op := r.x.ctrl.inst(31 downto 30); op3 := r.x.ctrl.inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
else
fpins := false; fpld := false;
end if;
valid := (((not r.x.ctrl.annul) and r.x.ctrl.pv) = '1') and (not ((fpins or fpld) and (r.x.ctrl.trap = '0')));
valid := valid and (holdn = '1');
if (disas = 1) and rising_edge(clk) and (rstn = '1') then
print_insn (index, r.x.ctrl.pc(31 downto 2) & "00", r.x.ctrl.inst,
rin.w.result, valid, r.x.ctrl.trap = '1', rin.w.wreg = '1',
rin.x.ipmask = '1');
end if;
end process;
-- pragma translate_on
dis0 : if disas < 2 generate dummy <= '1'; end generate;
dis2 : if disas > 1 generate
disasen <= '1' when disas /= 0 else '0';
cpu_index <= conv_std_logic_vector(index, 4);
x0 : cpu_disasx
port map (clk, rstn, dummy, r.x.ctrl.inst, r.x.ctrl.pc(31 downto 2),
rin.w.result, cpu_index, rin.w.wreg, r.x.ctrl.annul, holdn,
r.x.ctrl.pv, r.x.ctrl.trap, disasen);
end generate;
end;
|
gpl-2.0
|
a36cb241cf38a59217a9b68c79b32f9a
| 0.514289 | 3.127976 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-jopdesign-ep1c12/testbench.vhd
| 1 | 19,493 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART1 tx data
rxd2 : in std_logic; -- UART1 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(7 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emddis : out std_logic;
epwrdwn : out std_logic;
ereset : out std_logic;
esleep : out std_logic;
epause : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic;
can_rxd : in std_logic;
can_stb : out std_logic;
spw_clk : in std_logic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2)
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_logic;
signal oen : std_logic;
signal read : std_logic;
signal writen : std_logic;
signal brdyn : std_logic;
signal bexcn : std_logic;
signal wdog : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal test : std_logic;
signal error : std_logic;
signal gpio : std_logic_vector(7 downto 0);
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
signal clk2 : std_logic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal gtx_clk : std_logic;
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_logic;
signal can_rxd : std_logic;
signal can_stb : std_logic;
signal spw_clk : std_logic := '0';
signal spw_rxd : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxs : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txd : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txs : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant CFG_SD64 : integer := CFG_SDCTRL_SD64 + CFG_MCTRL_SD64;
begin
-- clock and reset
spw_clk <= not spw_clk after 20 ns;
spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0);
spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0);
spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1);
spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1);
spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2);
spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2);
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
can_rxd <= '1';
d3 : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, sdclk, error, address(27 downto 0), data,
sa, sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc, emddis, epwrdwn, ereset, esleep, epause,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd, can_stb, spw_clk, spw_rxd, spw_rxdn, spw_rxs,
spw_rxsn, spw_txd, spw_txdn, spw_txs, spw_txsn);
-- optional sdram
sd0 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
sd1 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
sd64 : if (CFG_SD64 /= 0) generate
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
rwen(0), ramoen(0));
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
gpl-2.0
|
461c655964d8ea3937a022c116d4560c
| 0.570666 | 3.039607 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/gencomp/netcomp.vhd
| 1 | 69,285 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: netcomp
-- File: netcomp.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler
-- Description: Declaration of netlists components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use work.gencomp.all;
package netcomp is
---------------------------------------------------------------------------
-- netlists ---------------------------------------------------------------
---------------------------------------------------------------------------
component grusbhc_net is
generic (
tech : integer := 0;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
isfpga : integer range 0 to 1 := 1;
memsel : integer := 0;
syncprst : integer range 0 to 1 := 0;
sysfreq : integer := 65000;
pcidev : integer range 0 to 1 := 0;
debug : integer := 0;
debug_abits : integer := 12);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- grusb_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
suspendm : out std_ulogic;
dbus16_8 : out std_ulogic;
dppulldown : out std_ulogic;
dmpulldown : out std_ulogic;
idpullup : out std_ulogic;
dischrgvbus : out std_ulogic;
chrgvbus : out std_ulogic;
txbitstuffenable : out std_ulogic;
txbitstuffenableh : out std_ulogic;
fslsserialmode : out std_ulogic;
txenablen : out std_ulogic;
txdat : out std_ulogic;
txse0 : out std_ulogic;
-- grusb_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
urstdrive : in std_logic_vector((nports-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic;
-- scan signals
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic;
-- debug signals
debug_raddr : out std_logic_vector(15 downto 0);
debug_waddr : out std_logic_vector(15 downto 0);
debug_wdata : out std_logic_vector(31 downto 0);
debug_we : out std_ulogic;
debug_rdata : in std_logic_vector(31 downto 0));
end component;
component grspwc_net
generic(
tech : integer := 0;
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspwc2_net is
generic(
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
tech : integer;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0;
interruptdist : integer range 0 to 32 := 0;
intscalerbits : integer range 0 to 31 := 0;
intisrtimerbits : integer range 0 to 31 := 0;
intiatimerbits : integer range 0 to 31 := 0;
intctimerbits : integer range 0 to 31 := 0;
tickinasync : integer range 0 to 1 := 0;
pnp : integer range 0 to 2 := 0;
pnpvendid : integer range 0 to 16#FFFF# := 0;
pnpprodid : integer range 0 to 16#FFFF# := 0;
pnpmajorver : integer range 0 to 16#FF# := 0;
pnpminorver : integer range 0 to 16#FF# := 0;
pnppatch : integer range 0 to 16#FF# := 0;
num_txdesc : integer range 64 to 512 := 64;
num_rxdesc : integer range 128 to 1024 := 128
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
txclk : in std_ulogic;
txclkn : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--time iface
tickin : in std_logic;
tickinraw : in std_logic;
timein : in std_logic_vector(7 downto 0);
tickindone : out std_logic;
tickout : out std_logic;
tickoutraw : out std_logic;
timeout : out std_logic_vector(7 downto 0);
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(5 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(5 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(5 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(5 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(9 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(9 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic;
testrst : in std_logic;
testen : in std_logic;
rxdav : out std_logic;
rxdataout : out std_logic_vector(8 downto 0);
loopback : out std_logic;
-- interrupt dist. default values
intpreload : in std_logic_vector(30 downto 0);
inttreload : in std_logic_vector(30 downto 0);
intiareload : in std_logic_vector(30 downto 0);
intcreload : in std_logic_vector(30 downto 0);
irqtxdefault : in std_logic_vector(4 downto 0);
--SpW PnP enable
pnpen : in std_ulogic;
pnpuvendid : in std_logic_vector(15 downto 0);
pnpuprodid : in std_logic_vector(15 downto 0);
pnpusn : in std_logic_vector(31 downto 0)
);
end component;
component grlfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component leon3_net
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0;
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
clk2x : integer := 1;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
-- ahbso : in ahb_slv_out_vector;
irqi_irl : in std_logic_vector(3 downto 0);
irqi_rst : in std_ulogic;
irqi_run : in std_ulogic;
irqi_rstvec : in std_logic_vector(31 downto 12);
irqi_iact : in std_ulogic;
irqi_index : in std_logic_vector(3 downto 0);
irqi_hrdrst : in std_ulogic;
irqo_intack : out std_ulogic;
irqo_irl : out std_logic_vector(3 downto 0);
irqo_pwd : out std_ulogic;
irqo_fpen : out std_ulogic;
irqo_idle : out std_ulogic;
dbgi_dsuen : in std_ulogic; -- DSU enable
dbgi_denable : in std_ulogic; -- diagnostic register access enablee
dbgi_dbreak : in std_ulogic; -- debug break-in
dbgi_step : in std_ulogic; -- single step
dbgi_halt : in std_ulogic; -- halt processor
dbgi_reset : in std_ulogic; -- reset processor
dbgi_dwrite : in std_ulogic; -- read/write
dbgi_daddr : in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata : in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa : in std_ulogic; -- break on IU trap
dbgi_btrape : in std_ulogic; -- break on IU trap
dbgi_berror : in std_ulogic; -- break on IU error mode
dbgi_bwatch : in std_ulogic; -- break on IU watchpoint
dbgi_bsoft : in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable : in std_ulogic;
dbgi_timer : in std_logic_vector(30 downto 0);
dbgo_data : out std_logic_vector(31 downto 0);
dbgo_crdy : out std_ulogic;
dbgo_dsu : out std_ulogic;
dbgo_dsumode : out std_ulogic;
dbgo_error : out std_ulogic;
dbgo_halt : out std_ulogic;
dbgo_pwd : out std_ulogic;
dbgo_idle : out std_ulogic;
dbgo_ipend : out std_ulogic;
dbgo_icnt : out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss : out std_ulogic;
dbgo_istat_tmiss : out std_ulogic;
dbgo_istat_chold : out std_ulogic;
dbgo_istat_mhold : out std_ulogic;
dbgo_dstat_cmiss : out std_ulogic;
dbgo_dstat_tmiss : out std_ulogic;
dbgo_dstat_chold : out std_ulogic;
dbgo_dstat_mhold : out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic;
-- fpui : out grfpu_in_type;
-- fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end component;
component ssrctrl_net
generic (
tech: Integer := 0;
bus16: Integer := 1);
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end component;
component ftsrctrl_net
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
rombanks : integer range 1 to 8 := 1;
rombanksz : integer range 0 to 15 := 15;
rombankszdef : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 0;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0;
prom8en : integer := 0;
netlist : integer := 0;
tech : integer := 0
);
port (
rst: in Std_ULogic;
clk: in Std_ULogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri_data: in Std_Logic_Vector(31 downto 0); -- Data bus address
sri_brdyn: in Std_Logic;
sri_bexcn: in Std_Logic;
sri_writen: in Std_Logic;
sri_wrn: in Std_Logic_Vector(3 downto 0);
sri_bwidth: in Std_Logic_Vector(1 downto 0);
sri_sd: in Std_Logic_Vector(63 downto 0);
sri_cb: in Std_Logic_Vector(15 downto 0);
sri_scb: in Std_Logic_Vector(15 downto 0);
sri_edac: in Std_Logic;
sro_address: out Std_Logic_Vector(31 downto 0);
sro_data: out Std_Logic_Vector(31 downto 0);
sro_sddata: out Std_Logic_Vector(63 downto 0);
sro_ramsn: out Std_Logic_Vector(7 downto 0);
sro_ramoen: out Std_Logic_Vector(7 downto 0);
sro_ramn: out Std_ULogic;
sro_romn: out Std_ULogic;
sro_mben: out Std_Logic_Vector(3 downto 0);
sro_iosn: out Std_Logic;
sro_romsn: out Std_Logic_Vector(7 downto 0);
sro_oen: out Std_Logic;
sro_writen: out Std_Logic;
sro_wrn: out Std_Logic_Vector(3 downto 0);
sro_bdrive: out Std_Logic_Vector(3 downto 0);
sro_vbdrive: out Std_Logic_Vector(31 downto 0); --vector bus drive
sro_svbdrive: out Std_Logic_Vector(63 downto 0); --vector bus drive sdram
sro_read: out Std_Logic;
sro_sa: out Std_Logic_Vector(14 downto 0);
sro_cb: out Std_Logic_Vector(15 downto 0);
sro_scb: out Std_Logic_Vector(15 downto 0);
sro_vcdrive: out Std_Logic_Vector(15 downto 0); --vector bus drive cb
sro_svcdrive: out Std_Logic_Vector(15 downto 0); --vector bus drive cb sdram
sro_ce: out Std_ULogic;
sdo_sdcke: out Std_Logic_Vector( 1 downto 0); -- clk en
sdo_sdcsn: out Std_Logic_Vector( 1 downto 0); -- chip sel
sdo_sdwen: out Std_ULogic; -- write en
sdo_rasn: out Std_ULogic; -- row addr stb
sdo_casn: out Std_ULogic; -- col addr stb
sdo_dqm: out Std_Logic_Vector(15 downto 0); -- data i/o mask
sdo_bdrive: out Std_ULogic; -- bus drive
sdo_qdrive: out Std_ULogic; -- bus drive
sdo_vbdrive: out Std_Logic_Vector(31 downto 0); -- vector bus drive
sdo_address: out Std_Logic_Vector(16 downto 2); -- address out
sdo_data: out Std_Logic_Vector(127 downto 0); -- data out
sdo_cb: out Std_Logic_Vector(15 downto 0);
sdo_ce: out Std_ULogic;
sdo_ba: out Std_Logic_Vector(2 downto 0)); -- bank address
end component;
component grlfpw4_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0;
wrt : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(63 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(63 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw4_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
fpuclk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(63 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(63 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component spictrl_net
generic (
tech : integer range 0 to NTECH := 0;
fdepth : integer range 1 to 7 := 1;
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1;
oepol : integer range 0 to 1 := 0;
odmode : integer range 0 to 1 := 0;
automode : integer range 0 to 1 := 0;
acntbits : integer range 1 to 32 := 32;
aslvsel : integer range 0 to 1 := 0;
twen : integer range 0 to 1 := 1;
maxwlen : integer range 0 to 15 := 0;
automask0 : integer := 0;
automask1 : integer := 0;
automask2 : integer := 0;
automask3 : integer := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0));
end component;
component leon4_net
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic;
gclk : in std_ulogic;
hclken : in std_ulogic;
rstn : in std_ulogic;
ahbix : in ahb_mst_in_type;
ahbox : out ahb_mst_out_type;
ahbsix : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqi_rstvec: in std_logic_vector(31 downto 12);
irqi_iact: in std_ulogic;
irqi_index: in std_logic_vector(3 downto 0);
irqi_hrdrst: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
irqo_idle: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(63 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic;
dbgo_ducnt : out std_ulogic);
end component;
component grpci2_phy_net is
generic(
tech : integer := DEFMEMTECH;
oepol : integer := 0;
bypass : integer range 0 to 1 := 1;
netlist : integer := 0
);
port(
pciclk : in std_logic;
pcii_rst : in std_ulogic;
pcii_gnt : in std_ulogic;
pcii_idsel : in std_ulogic;
pcii_ad : in std_logic_vector(31 downto 0);
pcii_cbe : in std_logic_vector(3 downto 0);
pcii_frame : in std_ulogic;
pcii_irdy : in std_ulogic;
pcii_trdy : in std_ulogic;
pcii_devsel : in std_ulogic;
pcii_stop : in std_ulogic;
pcii_lock : in std_ulogic;
pcii_perr : in std_ulogic;
pcii_serr : in std_ulogic;
pcii_par : in std_ulogic;
pcii_host : in std_ulogic;
pcii_pci66 : in std_ulogic;
pcii_pme_status : in std_ulogic;
pcii_int : in std_logic_vector(3 downto 0);
phyi_pcirstout : in std_logic;
phyi_pciasyncrst : in std_logic;
phyi_pcisoftrst : in std_logic_vector(2 downto 0);
phyi_pciinten : in std_logic_vector(3 downto 0);
phyi_m_request : in std_logic;
phyi_m_mabort : in std_logic;
phyi_pr_m_fstate : in std_logic_vector(1 downto 0);
phyi_pr_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_0_last : in std_logic;
phyi_pr_m_cfifo_0_stlast : in std_logic;
phyi_pr_m_cfifo_0_hold : in std_logic;
phyi_pr_m_cfifo_0_valid : in std_logic;
phyi_pr_m_cfifo_0_err : in std_logic;
phyi_pr_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_1_last : in std_logic;
phyi_pr_m_cfifo_1_stlast : in std_logic;
phyi_pr_m_cfifo_1_hold : in std_logic;
phyi_pr_m_cfifo_1_valid : in std_logic;
phyi_pr_m_cfifo_1_err : in std_logic;
phyi_pr_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_2_last : in std_logic;
phyi_pr_m_cfifo_2_stlast : in std_logic;
phyi_pr_m_cfifo_2_hold : in std_logic;
phyi_pr_m_cfifo_2_valid : in std_logic;
phyi_pr_m_cfifo_2_err : in std_logic;
phyi_pv_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_0_last : in std_logic;
phyi_pv_m_cfifo_0_stlast : in std_logic;
phyi_pv_m_cfifo_0_hold : in std_logic;
phyi_pv_m_cfifo_0_valid : in std_logic;
phyi_pv_m_cfifo_0_err : in std_logic;
phyi_pv_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_1_last : in std_logic;
phyi_pv_m_cfifo_1_stlast : in std_logic;
phyi_pv_m_cfifo_1_hold : in std_logic;
phyi_pv_m_cfifo_1_valid : in std_logic;
phyi_pv_m_cfifo_1_err : in std_logic;
phyi_pv_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_2_last : in std_logic;
phyi_pv_m_cfifo_2_stlast : in std_logic;
phyi_pv_m_cfifo_2_hold : in std_logic;
phyi_pv_m_cfifo_2_valid : in std_logic;
phyi_pv_m_cfifo_2_err : in std_logic;
phyi_pr_m_addr : in std_logic_vector(31 downto 0);
phyi_pr_m_cbe_data : in std_logic_vector(3 downto 0);
phyi_pr_m_cbe_cmd : in std_logic_vector(3 downto 0);
phyi_pr_m_first : in std_logic_vector(1 downto 0);
phyi_pv_m_term : in std_logic_vector(1 downto 0);
phyi_pr_m_ltimer : in std_logic_vector(7 downto 0);
phyi_pr_m_burst : in std_logic;
phyi_pr_m_abort : in std_logic_vector(0 downto 0);
phyi_pr_m_perren : in std_logic_vector(0 downto 0);
phyi_pr_m_done_fifo : in std_logic;
phyi_t_abort : in std_logic;
phyi_t_ready : in std_logic;
phyi_t_retry : in std_logic;
phyi_pr_t_state : in std_logic_vector(2 downto 0);
phyi_pv_t_state : in std_logic_vector(2 downto 0);
phyi_pr_t_fstate : in std_logic_vector(1 downto 0);
phyi_pr_t_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_0_last : in std_logic;
phyi_pr_t_cfifo_0_stlast : in std_logic;
phyi_pr_t_cfifo_0_hold : in std_logic;
phyi_pr_t_cfifo_0_valid : in std_logic;
phyi_pr_t_cfifo_0_err : in std_logic;
phyi_pr_t_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_1_last : in std_logic;
phyi_pr_t_cfifo_1_stlast : in std_logic;
phyi_pr_t_cfifo_1_hold : in std_logic;
phyi_pr_t_cfifo_1_valid : in std_logic;
phyi_pr_t_cfifo_1_err : in std_logic;
phyi_pr_t_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_2_last : in std_logic;
phyi_pr_t_cfifo_2_stlast : in std_logic;
phyi_pr_t_cfifo_2_hold : in std_logic;
phyi_pr_t_cfifo_2_valid : in std_logic;
phyi_pr_t_cfifo_2_err : in std_logic;
phyi_pv_t_diswithout : in std_logic;
phyi_pr_t_stoped : in std_logic;
phyi_pr_t_lcount : in std_logic_vector(2 downto 0);
phyi_pr_t_first_word : in std_logic;
phyi_pr_t_cur_acc_0_read : in std_logic;
phyi_pv_t_hold_write : in std_logic;
phyi_pv_t_hold_reset : in std_logic;
phyi_pr_conf_comm_perren : in std_logic;
phyi_pr_conf_comm_serren : in std_logic;
pcio_aden : out std_ulogic;
pcio_vaden : out std_logic_vector(31 downto 0);
pcio_cbeen : out std_logic_vector(3 downto 0);
pcio_frameen : out std_ulogic;
pcio_irdyen : out std_ulogic;
pcio_trdyen : out std_ulogic;
pcio_devselen : out std_ulogic;
pcio_stopen : out std_ulogic;
pcio_ctrlen : out std_ulogic;
pcio_perren : out std_ulogic;
pcio_paren : out std_ulogic;
pcio_reqen : out std_ulogic;
pcio_locken : out std_ulogic;
pcio_serren : out std_ulogic;
pcio_inten : out std_ulogic;
pcio_vinten : out std_logic_vector(3 downto 0);
pcio_req : out std_ulogic;
pcio_ad : out std_logic_vector(31 downto 0);
pcio_cbe : out std_logic_vector(3 downto 0);
pcio_frame : out std_ulogic;
pcio_irdy : out std_ulogic;
pcio_trdy : out std_ulogic;
pcio_devsel : out std_ulogic;
pcio_stop : out std_ulogic;
pcio_perr : out std_ulogic;
pcio_serr : out std_ulogic;
pcio_par : out std_ulogic;
pcio_lock : out std_ulogic;
pcio_power_state : out std_logic_vector(1 downto 0);
pcio_pme_enable : out std_ulogic;
pcio_pme_clear : out std_ulogic;
pcio_int : out std_ulogic;
pcio_rst : out std_ulogic;
phyo_pciv_rst : out std_ulogic;
phyo_pciv_gnt : out std_ulogic;
phyo_pciv_idsel : out std_ulogic;
phyo_pciv_ad : out std_logic_vector(31 downto 0);
phyo_pciv_cbe : out std_logic_vector(3 downto 0);
phyo_pciv_frame : out std_ulogic;
phyo_pciv_irdy : out std_ulogic;
phyo_pciv_trdy : out std_ulogic;
phyo_pciv_devsel : out std_ulogic;
phyo_pciv_stop : out std_ulogic;
phyo_pciv_lock : out std_ulogic;
phyo_pciv_perr : out std_ulogic;
phyo_pciv_serr : out std_ulogic;
phyo_pciv_par : out std_ulogic;
phyo_pciv_host : out std_ulogic;
phyo_pciv_pci66 : out std_ulogic;
phyo_pciv_pme_status : out std_ulogic;
phyo_pciv_int : out std_logic_vector(3 downto 0);
phyo_pr_m_state : out std_logic_vector(2 downto 0);
phyo_pr_m_last : out std_logic_vector(1 downto 0);
phyo_pr_m_hold : out std_logic_vector(1 downto 0);
phyo_pr_m_term : out std_logic_vector(1 downto 0);
phyo_pr_t_hold : out std_logic_vector(0 downto 0);
phyo_pr_t_stop : out std_logic;
phyo_pr_t_abort : out std_logic;
phyo_pr_t_diswithout : out std_logic;
phyo_pr_t_addr_perr : out std_logic;
phyo_pcirsto : out std_logic_vector(0 downto 0);
phyo_pr_po_ad : out std_logic_vector(31 downto 0);
phyo_pr_po_aden : out std_logic_vector(31 downto 0);
phyo_pr_po_cbe : out std_logic_vector(3 downto 0);
phyo_pr_po_cbeen : out std_logic_vector(3 downto 0);
phyo_pr_po_frame : out std_logic;
phyo_pr_po_frameen : out std_logic;
phyo_pr_po_irdy : out std_logic;
phyo_pr_po_irdyen : out std_logic;
phyo_pr_po_trdy : out std_logic;
phyo_pr_po_trdyen : out std_logic;
phyo_pr_po_stop : out std_logic;
phyo_pr_po_stopen : out std_logic;
phyo_pr_po_devsel : out std_logic;
phyo_pr_po_devselen : out std_logic;
phyo_pr_po_par : out std_logic;
phyo_pr_po_paren : out std_logic;
phyo_pr_po_perr : out std_logic;
phyo_pr_po_perren : out std_logic;
phyo_pr_po_lock : out std_logic;
phyo_pr_po_locken : out std_logic;
phyo_pr_po_req : out std_logic;
phyo_pr_po_reqen : out std_logic;
phyo_pr_po_serren : out std_logic;
phyo_pr_po_inten : out std_logic;
phyo_pr_po_vinten : out std_logic_vector(3 downto 0);
phyo_pio_rst : out std_ulogic;
phyo_pio_gnt : out std_ulogic;
phyo_pio_idsel : out std_ulogic;
phyo_pio_ad : out std_logic_vector(31 downto 0);
phyo_pio_cbe : out std_logic_vector(3 downto 0);
phyo_pio_frame : out std_ulogic;
phyo_pio_irdy : out std_ulogic;
phyo_pio_trdy : out std_ulogic;
phyo_pio_devsel : out std_ulogic;
phyo_pio_stop : out std_ulogic;
phyo_pio_lock : out std_ulogic;
phyo_pio_perr : out std_ulogic;
phyo_pio_serr : out std_ulogic;
phyo_pio_par : out std_ulogic;
phyo_pio_host : out std_ulogic;
phyo_pio_pci66 : out std_ulogic;
phyo_pio_pme_status : out std_ulogic;
phyo_pio_int : out std_logic_vector(3 downto 0);
phyo_poo_ad : out std_logic_vector(31 downto 0);
phyo_poo_aden : out std_logic_vector(31 downto 0);
phyo_poo_cbe : out std_logic_vector(3 downto 0);
phyo_poo_cbeen : out std_logic_vector(3 downto 0);
phyo_poo_frame : out std_logic;
phyo_poo_frameen : out std_logic;
phyo_poo_irdy : out std_logic;
phyo_poo_irdyen : out std_logic;
phyo_poo_trdy : out std_logic;
phyo_poo_trdyen : out std_logic;
phyo_poo_stop : out std_logic;
phyo_poo_stopen : out std_logic;
phyo_poo_devsel : out std_logic;
phyo_poo_devselen : out std_logic;
phyo_poo_par : out std_logic;
phyo_poo_paren : out std_logic;
phyo_poo_perr : out std_logic;
phyo_poo_perren : out std_logic;
phyo_poo_lock : out std_logic;
phyo_poo_locken : out std_logic;
phyo_poo_req : out std_logic;
phyo_poo_reqen : out std_logic;
phyo_poo_serren : out std_logic;
phyo_poo_inten : out std_logic;
phyo_poo_vinten : out std_logic_vector(3 downto 0)
);
end component;
end;
|
gpl-2.0
|
4c6d1925c6477d0d58ecb86934257cb6
| 0.531226 | 3.379426 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3mp/ahbrom.vhd
| 3 | 8,968 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2009 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800016";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A233";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539A89B";
when 16#00069# => romdata <= X"8410A260";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800006";
when 16#00074# => romdata <= X"033FFC00";
when 16#00075# => romdata <= X"82106100";
when 16#00076# => romdata <= X"0539A81B";
when 16#00077# => romdata <= X"8410A260";
when 16#00078# => romdata <= X"C4204000";
when 16#00079# => romdata <= X"05000080";
when 16#0007A# => romdata <= X"82100000";
when 16#0007B# => romdata <= X"80A0E000";
when 16#0007C# => romdata <= X"02800005";
when 16#0007D# => romdata <= X"01000000";
when 16#0007E# => romdata <= X"82004002";
when 16#0007F# => romdata <= X"10BFFFFC";
when 16#00080# => romdata <= X"8620E001";
when 16#00081# => romdata <= X"3D1003FF";
when 16#00082# => romdata <= X"BC17A3E0";
when 16#00083# => romdata <= X"BC278001";
when 16#00084# => romdata <= X"9C27A060";
when 16#00085# => romdata <= X"03100000";
when 16#00086# => romdata <= X"81C04000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
gpl-2.0
|
05c64a39fabb9f16da7e8d2e30a15fc0
| 0.580397 | 3.292217 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/cycloneiii/alt/admout.vhd
| 3 | 3,433 |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library cycloneiii;
use cycloneiii.all;
library altera;
use altera.all;
entity admout is
port(
clk : in std_logic; -- clk0
dm_h : in std_logic;
dm_l : in std_logic;
dm_pad : out std_logic -- DQ pad
);
end;
architecture rtl of admout is
component cycloneiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic;
dfflo : out std_logic;
dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component cycloneiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
port(
i : in std_logic := '0';
oe : in std_logic := '1';
--devoe : in std_logic := '1';
o : out std_logic;
obar : out std_logic--;
--seriesterminationcontrol : in std_logic_vector(15 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dm_reg : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
-- DM output register --------------------------------------------------------------
dm_reg0 : cycloneiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_out"
)
port map(
datainlo => dm_l,
datainhi => dm_h,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dm_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Out buffer (DM) ------------------------------------------------------------------
dm_buf0 : cycloneiii_io_obuf
generic map(
open_drain_output => "false",
bus_hold => "false",
lpm_type => "cycloneiii_io_obuf"
)
port map(
i => dm_reg,
oe => vcc,
--devoe => vcc,
o => dm_pad,
obar => open
--seriesterminationcontrol => gnd,
);
end;
|
gpl-2.0
|
be184cd4f5152c963de8967ace8abf5f
| 0.378678 | 4.356599 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep3c25/config.vhd
| 1 | 5,710 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (10);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (32);
constant CFG_DDRSP_RSKEW : integer := (2500);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#6#;
constant CFG_GRGPIO_WIDTH : integer := (3);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
7a70bbff60d46beecf99b962f9825906
| 0.643783 | 3.653231 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/grlib/util/util.vhd
| 1 | 2,385 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: util
-- File: util.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Misc utilities
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity report_version is
generic (msg1, msg2, msg3, msg4 : string := ""; mdel : integer := 4);
end;
architecture beh of report_version is
begin
x : process
begin
wait for mdel * 1 ns;
if (msg1 /= "") then print(msg1); end if;
if (msg2 /= "") then print(msg2); end if;
if (msg3 /= "") then print(msg3); end if;
if (msg4 /= "") then print(msg4); end if;
wait;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity report_design is
generic (msg1, fabtech, memtech : string := ""; mdel : integer := 4);
end;
architecture beh of report_design is
begin
x : report_version
generic map (
msg1 => msg1,
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & fabtech & ", memory library: " & memtech,
mdel => mdel);
end;
-- pragma translate_on
|
gpl-2.0
|
55059649b94e2f22111b741076ca9f40
| 0.608386 | 3.909836 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-sp605/leon3mp.vhd
| 1 | 35,652 |
-----------------------------------------------------------------------------
-- LEON3 Xilinx SP605 Demonstration design
-- Copyright (C) 2011 Jiri Gaisler, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.ODDR2;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.pcie.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk27 : in std_ulogic; -- 27 MHz clock
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
clk33 : in std_ulogic; -- 32 MHz clock from sysace
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(15 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_odt : out std_logic;
ddr_reset_n : out std_logic;
ddr_we : out std_ulogic; -- ddr write enable
ddr_ras : out std_ulogic; -- ddr ras
ddr_cas : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_dqs_n : inout std_logic_vector (1 downto 0); -- ddr dqs_n
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (2 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
ddr_rzq : inout std_ulogic;
ddr_zio : inout std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 ctsn
rtsn1 : out std_ulogic; -- UART1 trsn
button : inout std_logic_vector(3 downto 0); -- I/O port
switch : inout std_logic_vector(3 downto 0); -- I/O port
led : out std_logic_vector(3 downto 0); -- I/O port
phy_gtx_clk : out std_logic;
phy_mii_data : inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
phy_mii_int_n : in std_ulogic;
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
ddc_scl : inout std_ulogic;
ddc_sda : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic;
--pcie
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_d : inout std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
--attribute syn_netlist_hierarchy : boolean;
--attribute syn_netlist_hierarchy of rtl : architecture is false;
component ODDR2
generic (
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port (
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic := 'H';
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic := 'L';
S : in std_ulogic := 'L'
);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG+CFG_PCIEXP;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal egtx_clk :std_ulogic;
signal negtx_clk :std_ulogic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, ulock : std_ulogic;
signal lock, calib_done, clkml, lclk, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ethclk : std_ulogic;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal spmi2 : spimctrl_in_type;
signal spmo2 : spimctrl_out_type;
constant BOARD_FREQ : integer := 33000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_GRACECTRL;
constant DDR2_FREQ : integer := 200000; -- DDR2 input frequency in KHz
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
signal video_clk : std_ulogic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of clkm : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
ethclk <= lclk;
clk_pad : clkpad generic map (tech => padtech) port map (clk33, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, open, open);
reset_pad : inpad generic map (tech => padtech) port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, lock, rstn, rstraw);
lock <= cgo.clklock and calib_done when CFG_MIG_DDR2 = 1 else cgo.clklock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
ioen => IOAEN, nahbm => maxahbm, nahbs => 16)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
led1_pad : odpad generic map (tech => padtech) port map (led(1), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= button(3);
dsuact_pad : outpad generic map (tech => padtech) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl_gen : if CFG_MCTRL_LEON2 /= 0 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(24 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 16)
port map (data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
end generate;
nomctrl : if CFG_MCTRL_LEON2 = 0 generate
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc); --ahbso(0) <= ahbso_none;
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
-- pragma translate_on
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_DDR2 = 1) generate
ddrc : entity work.ahb2mig_sp605 generic map(
hindex => 4, haddr => 16#400#, hmask => 16#F80#,
pindex => 4, paddr => 4,
vgamst => CFG_SVGA_ENABLE, vgaburst => 64)
port map(
mcb3_dram_dq => ddr_dq,
mcb3_dram_a => ddr_ad,
mcb3_dram_ba => ddr_ba,
mcb3_dram_ras_n => ddr_ras,
mcb3_dram_cas_n => ddr_cas,
mcb3_dram_we_n => ddr_we,
mcb3_dram_odt => ddr_odt,
mcb3_dram_reset_n=> ddr_reset_n,
mcb3_dram_cke => ddr_cke,
mcb3_dram_dm => ddr_dm(0),
mcb3_dram_udqs => ddr_dqs(1),
mcb3_dram_udqs_n=> ddr_dqs_n(1),
mcb3_rzq => ddr_rzq,
mcb3_zio => ddr_zio,
mcb3_dram_udm => ddr_dm(1),
mcb3_dram_dqs => ddr_dqs(0),
mcb3_dram_dqs_n => ddr_dqs_n(0),
mcb3_dram_ck => ddr_clk,
mcb3_dram_ck_n => ddr_clkb,
ahbsi => ahbsi,
ahbso => ahbso(4),
ahbmi => vahbmi,
ahbmo => vahbmo,
apbi => apbi,
apbo => apbo(4),
calib_done => calib_done,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem_p => clk200p,
clk_mem_n => clk200n,
clk_125 => egtx_clk,
clk_50 => video_clk
);
end generate;
led(2) <= calib_done;
led(3) <= lock;
noddr : if CFG_MIG_DDR2 = 0 generate lock <= '1'; end generate;
-----------------PCI-EXPRESS-Master-Target------------------------------------------
pcie_mt : if CFG_PCIE_TYPE = 1 generate -- master/target without fifo
EP:pcie_master_target_sp605
generic map (
master => CFG_PCIE_SIM_MAS,
hmstndx => CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG,
hslvndx => 7,
abits => 21,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
nsync => 2, -- 1 or 2 sync regs between clocks
pcie_bar_mask => 16#FFE#,
haddr => 16#a00#,
hmask => 16#fff#,
pindex => 5,
paddr => 5,
pmask => 16#fff#
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(7),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5),
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG)
);
end generate;
----------------------------------------------------------------------
-----------------PCI-EXPRESS-Master-FIFO------------------------------------------
pcie_mf_dma : if CFG_PCIE_TYPE = 3 generate -- master with fifo and DMA
dma:pciedma
generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG,
dapbndx => 7, dapbaddr => 7,dapbmask => 16#FFF#, dapbirq => 4, blength => 12,
device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID,
slvndx => 7, apbndx => 5, apbaddr => 5, apbmask =>16#FFF#, haddr => 16#A00#, hmask => 16#FFF#,
nsync => 2, pcie_bar_mask => 16#FFE#
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
dapbo => apbo(7),
dahbmo =>ahbmo(CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG),
apbi =>apbi,
apbo =>apbo(5),
ahbmi =>ahbmi,
ahbsi =>ahbsi,
ahbso =>ahbso(7)
);
end generate;
pcie_mf: if CFG_PCIE_TYPE = 2 generate -- master with fifo
EP:pcie_master_fifo_sp605
generic map (
memtech => memtech,
hslvndx => 7,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
nsync => 2, -- 1 or 2 sync regs between clocks
pcie_bar_mask => 16#FFE#,
haddr => 16#A00#,
hmask => 16#fff#,
pindex => 5,
paddr => 5,
pmask => 16#fff#)
port map(
rst => rstn,
clk => clkm,
-- System In
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Expre
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(7),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5)
);
end generate;
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 3, hirq => 5, faddr => 16#e00#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(3), spmi, spmo);
-- MISO is shared with Flash data 0
spmi.miso <= memi.data(16);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
nospimc: if ((CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 1) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 0))generate
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, '0');
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, '0');
end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 8, hirq => 10,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT, mode => 2)
port map (rstn, clkm, lclk, ahbsi, ahbso(8), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
sysace_mpa_pads : outpadv generic map (width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_d_pads : iopadv generic map (tech => padtech, width => 8)
port map (sysace_d, aceo.do(7 downto 0), aceo.doen, acei.di(7 downto 0));
acei.di(15 downto 8) <= (others => '0');
sysace_mpoe_pad : outpad generic map (tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => 0)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
-- video_clk <= not ethclk;
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_JTAG,
clk0 => 20000, clk1 => 0, --1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk2 => 0, clk3 => 0, burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, vahbmi,
vahbmo, clk_sel);
end generate;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
-- b0 : techbuf generic map (2, fabtech) port map (clk50, video_clk);
dvi0 : entity work.svga2ch7301c generic map (tech => fabtech, dynamic => 1)
port map (clkm, vgao, video_clk, clkvga_p, clkvga_n,
lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 11)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 7)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 3 generate
pio_pad : iopad generic map (tech => padtech)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 4 to 6 generate
pio_pad : iopad generic map (tech => padtech)
port map (button(i-4), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
negtx_clk <= not egtx_clk;
x0 : ODDR2 port map ( Q => phy_gtx_clk, C0 => egtx_clk,
C1 => negtx_clk, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd);
e1 : grethm generic map( hindex => CFG_NCPU+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_JTAG), apbi => apbi, apbo => apbo(14),
ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
emdintn_pad : inpad generic map (tech => padtech)
port map (phy_mii_int_n, ethi.mdint);
ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 5, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG+CFG_PCIEXP) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx SP605 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
87cb9076cb4678b0e3ae05d8964c6dbe
| 0.548777 | 3.493239 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/ambatest/ahbtbp.vhd
| 1 | 37,048 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtbp
-- File: ahbtbp.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: AHB Testbench package
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
package ahbtbp is
type ahbtbm_ctrl_type is record
delay : std_logic_vector(7 downto 0);
dbgl : integer;
reset : std_logic;
use128 : integer;
end record;
type ahbtbm_access_type is record
haddr : std_logic_vector(31 downto 0);
hdata : std_logic_vector(31 downto 0);
hdata128 : std_logic_vector(127 downto 0);
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hprot : std_logic_vector(3 downto 0);
hwrite : std_logic;
ctrl : ahbtbm_ctrl_type;
end record;
type ahbtbm_status_type is record
err : std_logic;
ecount : std_logic_vector(15 downto 0);
eaddr : std_logic_vector(31 downto 0);
edatac : std_logic_vector(31 downto 0);
edatar : std_logic_vector(31 downto 0);
hresp : std_logic_vector(1 downto 0);
end record;
type ahbtbm_access_array_type is array (0 to 1) of ahbtbm_access_type;
type ahbtbm_ctrl_in_type is record
ac : ahbtbm_access_type;
end record;
type ahbtbm_ctrl_out_type is record
rst : std_logic;
clk : std_logic;
update : std_logic;
dvalid : std_logic;
hrdata : std_logic_vector(31 downto 0);
hrdata128 : std_logic_vector(127 downto 0);
status : ahbtbm_status_type;
end record;
type ahbtb_ctrl_type is record
i : ahbtbm_ctrl_in_type;
o : ahbtbm_ctrl_out_type;
end record;
constant ac_idle : ahbtbm_access_type :=
(haddr => x"00000000", hdata => x"00000000",
hdata128 => x"00000000000000000000000000000000",
htrans => "00", hburst =>"000", hsize => "000", hprot => "0000", hwrite => '0',
ctrl => (delay => x"00", dbgl => 100, reset =>'0', use128 => 0));
constant ctrli_idle : ahbtbm_ctrl_in_type :=(ac => ac_idle);
constant ctrlo_nodrive : ahbtbm_ctrl_out_type :=(rst => 'H', clk => 'H',
update => 'H', dvalid => 'H', hrdata => (others => 'H'), hrdata128 => (others => 'H'),
status => (err => 'H', ecount => (others => 'H'), eaddr => (others => 'H'),
edatac => (others => 'H'), edatar => (others => 'H'),
hresp => (others => 'H')));
impure function ptime return string;
-- pragma translate_off
-----------------------------------------------------------------------------
-- AHB testbench Master
-----------------------------------------------------------------------------
component ahbtbm is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := 0;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ctrli : in ahbtbm_ctrl_in_type;
ctrlo : out ahbtbm_ctrl_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end component;
-----------------------------------------------------------------------------
-- AHB testbench Slave
-----------------------------------------------------------------------------
component ahbtbs is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
-----------------------------------------------------------------------------
-- dprint (Debug print)
-----------------------------------------------------------------------------
procedure dprint(
constant doprint : in boolean := true;
constant s : in string);
procedure dprint(
constant s : in string);
-----------------------------------------------------------------------------
-- AMBATB Init
-----------------------------------------------------------------------------
procedure ahbtbminit(
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBATB DONE
-----------------------------------------------------------------------------
procedure ahbtbmdone(
constant stop: in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBATB Idle
-----------------------------------------------------------------------------
procedure ahbtbmidle(
constant sync: in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Start address
constant data : in std_logic_vector(31 downto 0); -- Start data
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(127 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(127 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(63 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(63 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
end ahbtbp;
package body ahbtbp is
impure function ptime return string is
variable s : string(1 to 20);
variable length : integer := tost(NOW / 1 ns)'length;
begin
s(1 to length + 9) :="Time: " & tost(NOW / 1 ns) & "ns ";
return s(1 to length + 9);
end function ptime;
-----------------------------------------------------------------------------
-- dprint (Debug print)
-----------------------------------------------------------------------------
procedure dprint(
constant doprint : in boolean := true;
constant s : in string) is
begin
if doprint = true then
print(s);
end if;
end procedure dprint;
procedure dprint(
constant s : in string) is
begin
print(s);
end procedure dprint;
-----------------------------------------------------------------------------
-- AHBTB init
-----------------------------------------------------------------------------
procedure ahbtbminit(
signal ctrl : inout ahbtb_ctrl_type) is
begin
ctrl.o <= ctrlo_nodrive;
ctrl.i <= ctrli_idle;
--ctrli.ac.hburst <= "000"; ctrli.ac.hsize <= "010";
--ctrli.ac.haddr <= x"00000000"; ctrli.ac.hdata <= x"00000000";
--ctrli.ac.htrans <= "00"; ctrli.ac.hwrite <= '0';
wait until ctrl.o.rst = '1';
print("**********************************************************");
print(" AHBTBM Testbench Init");
print("**********************************************************");
end procedure ahbtbminit;
-----------------------------------------------------------------------------
-- AMBTB DONE
-----------------------------------------------------------------------------
procedure ahbtbmdone(
constant stop: in integer;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
print("**********************************************************");
print(" AHBTBM Testbench Done");
print("**********************************************************");
wait for 100 ns;
assert stop = 0
report "ahbtb testbench done!"
severity FAILURE;
end procedure ahbtbmdone;
-----------------------------------------------------------------------------
-- AMBTB Idle
-----------------------------------------------------------------------------
procedure ahbtbmidle(
constant sync: in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
if sync = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
end if;
end procedure ahbtbmidle;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "000";
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type) is
variable vaddr : std_logic_vector(31 downto 0);
variable vdata : std_logic_vector(31 downto 0);
variable vhtrans : std_logic_vector(1 downto 0);
begin
--ctrl.o <= ctrlo_nodrive;
vaddr := address; vdata := data; vhtrans := "10";
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "001";
ctrl.i.ac.hprot <= "1110";
for i in 0 to count - 1 loop
ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata;
ctrl.i.ac.htrans <= vhtrans;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
vaddr := vaddr + x"4"; vdata := vdata + 1;
vhtrans := "11";
end loop;
ctrl.i <= ctrli_idle;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "000";
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type) is
variable vaddr : std_logic_vector(31 downto 0);
variable vdata : std_logic_vector(31 downto 0);
variable vhtrans : std_logic_vector(1 downto 0);
begin
--ctrl.o <= ctrlo_nodrive;
vaddr := address; vdata := data; vhtrans := "10";
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "001";
ctrl.i.ac.hprot <= "1110";
for i in 0 to count - 1 loop
ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata;
ctrl.i.ac.htrans <= vhtrans;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
vaddr := vaddr + x"4"; vdata := vdata + 1;
vhtrans := "11";
end loop;
ctrl.i <= ctrli_idle;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128write;
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128write;
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128read;
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128read;
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64write;
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64write;
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64read;
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64read;
-- pragma translate_on
end ahbtbp;
|
gpl-2.0
|
89f055563e2007b6dfc156c82ad67cdd
| 0.525615 | 3.838375 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/unisim/tap_unisim.vhd
| 1 | 24,347 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tap_xilinx
-- File: tap_xilinx.vhd
-- Author: Edvin Catovic, Jiri Gaisler - Gaisler Research
-- Description: Xilinx TAP controllers wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex_tap is
component BSCAN_VIRTEX
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_VIRTEX
port map (
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2; tapo_capt <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex2_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex2_tap is
component BSCAN_VIRTEX2
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_VIRTEX2
port map (CAPTURE => tapo_capt,
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_SPARTAN3;
-- pragma translate_on
entity spartan3_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of spartan3_tap is
component BSCAN_SPARTAN3
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_SPARTAN3
port map (CAPTURE => tapo_capt,
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_VIRTEX4;
-- pragma translate_on
entity virtex4_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex4_tap is
component BSCAN_VIRTEX4 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX4
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1
);
u1 : BSCAN_VIRTEX4
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_VIRTEX5;
-- pragma translate_on
entity virtex5_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex5_tap is
component BSCAN_VIRTEX5 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX5
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1
);
u1 : BSCAN_VIRTEX5
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex6_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex6_tap is
component BSCAN_VIRTEX6
generic (
DISABLE_JTAG : boolean := FALSE;
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX6
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCAN_VIRTEX6
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity spartan6_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of spartan6_tap is
component BSCAN_SPARTAN6
generic (
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_SPARTAN6
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCAN_SPARTAN6
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity kintex7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of kintex7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity artix7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of artix7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
|
gpl-2.0
|
da59a041d21ccb204943937a1e94905d
| 0.498337 | 3.750308 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/ddr/ddr2sp.in.vhd
| 4 | 1,229 |
-- DDR controller
constant CFG_DDR2SP : integer := CONFIG_DDR2SP;
constant CFG_DDR2SP_INIT : integer := CONFIG_DDR2SP_INIT;
constant CFG_DDR2SP_FREQ : integer := CONFIG_DDR2SP_FREQ;
constant CFG_DDR2SP_TRFC : integer := CONFIG_DDR2SP_TRFC;
constant CFG_DDR2SP_DATAWIDTH : integer := CONFIG_DDR2SP_DATAWIDTH;
constant CFG_DDR2SP_FTEN : integer := CONFIG_DDR2SP_FTEN;
constant CFG_DDR2SP_FTWIDTH : integer := CONFIG_DDR2SP_FTWIDTH;
constant CFG_DDR2SP_COL : integer := CONFIG_DDR2SP_COL;
constant CFG_DDR2SP_SIZE : integer := CONFIG_DDR2SP_MBYTE;
constant CFG_DDR2SP_DELAY0 : integer := CONFIG_DDR2SP_DELAY0;
constant CFG_DDR2SP_DELAY1 : integer := CONFIG_DDR2SP_DELAY1;
constant CFG_DDR2SP_DELAY2 : integer := CONFIG_DDR2SP_DELAY2;
constant CFG_DDR2SP_DELAY3 : integer := CONFIG_DDR2SP_DELAY3;
constant CFG_DDR2SP_DELAY4 : integer := CONFIG_DDR2SP_DELAY4;
constant CFG_DDR2SP_DELAY5 : integer := CONFIG_DDR2SP_DELAY5;
constant CFG_DDR2SP_DELAY6 : integer := CONFIG_DDR2SP_DELAY6;
constant CFG_DDR2SP_DELAY7 : integer := CONFIG_DDR2SP_DELAY7;
constant CFG_DDR2SP_NOSYNC : integer := CONFIG_DDR2SP_NOSYNC;
|
gpl-2.0
|
2fe11d16319c778191d0acf846fdc8f1
| 0.689992 | 3.103535 | false | true | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml605/ahb2mig_ml605.vhd
| 1 | 16,776 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2mig
-- File: ahb2mig.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: AHB wrapper for Xilinx Virtex6 DDR2/3 MIG
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package ml605 is
constant nCS_PER_RANK : integer := 1;
constant BANK_WIDTH : integer := 3;
constant CK_WIDTH : integer := 1;
constant CKE_WIDTH : integer := 1;
constant COL_WIDTH : integer := 10;
constant CS_WIDTH : integer := 1;
constant DM_WIDTH : integer := 8;
constant DQ_WIDTH : integer := 64;
constant DQS_WIDTH : integer := 8;
constant ROW_WIDTH : integer := 13;
constant PAYLOAD_WIDTH : integer := 64;
constant ADDR_WIDTH : integer := 27;
type mig_app_in_type is record
app_wdf_wren : std_logic;
app_wdf_data : std_logic_vector((4*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_mask : std_logic_vector((4*PAYLOAD_WIDTH)/8-1 downto 0);
app_wdf_end : std_logic;
app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : std_logic_vector(2 downto 0);
app_en : std_logic;
end record;
type mig_app_out_type is record
app_rdy : std_logic;
app_wdf_rdy : std_logic;
app_rd_data : std_logic_vector((4*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_valid : std_logic;
end record;
component ahb2mig_ml605
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#e00#;
MHz : integer := 100;
Mbyte : integer := 512;
nosync : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
migi : out mig_app_in_type;
migo : in mig_app_out_type
);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use work.ml605.all;
entity ahb2mig_ml605 is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#e00#;
MHz : integer := 100;
Mbyte : integer := 512;
nosync : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
migi : out mig_app_in_type;
migo : in mig_app_out_type
);
end;
architecture rtl of ahb2mig_ml605 is
constant REVISION : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type ddr_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
constant abuf : integer := 6;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
end record;
-- local registers
type mem is array(0 to 15) of std_logic_vector(31 downto 0);
type wrm is array(0 to 15) of std_logic_vector(3 downto 0);
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
startsd : std_ulogic;
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(127 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(2 downto 0);
acc : access_param;
sync : std_ulogic;
hwdata : mem;
write : wrm;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
hrdata : std_logic_vector(511 downto 0);
sync : std_ulogic;
dstate : ahb_state_type;
end record;
signal vcc, clk_ahb1, clk_ahb2 : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal hwdata, hwdatab : std_logic_vector(127 downto 0);
begin
vcc <= '1';
ahb_ctrl : process(rst, ahbsi, r, ra, migo, hwdata)
variable va : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable ready : std_logic;
variable tmp : std_logic_vector(3 downto 0);
variable waddr : integer;
variable rdata : std_logic_vector(127 downto 0);
begin
va := ra; va.hresp := HRESP_OKAY;
tmp := (others => '0');
case ra.raddr(3 downto 2) is
when "00" => rdata := r.hrdata(127 downto 0);
when "01" => rdata := r.hrdata(255 downto 128);
when "10" => rdata := r.hrdata(383 downto 256);
when others => rdata := r.hrdata(511 downto 384);
end case;
if AHBDW > 64 and ra.size = HSIZE_4WORD then
va.hrdata := rdata(31 downto 0) & rdata(63 downto 32) & rdata(95 downto 64) & rdata(127 downto 96);
elsif AHBDW > 32 and ra.size = HSIZE_DWORD then
if ra.raddr(1) = '1' then va.hrdata(63 downto 0) := rdata(95 downto 64) & rdata(127 downto 96);
else va.hrdata(63 downto 0) := rdata(31 downto 0) & rdata(63 downto 32); end if;
va.hrdata(127 downto 64) := va.hrdata(63 downto 0);
else
case ra.raddr(1 downto 0) is
when "00" => va.hrdata(31 downto 0) := rdata(31 downto 0);
when "01" => va.hrdata(31 downto 0) := rdata(63 downto 32);
when "10" => va.hrdata(31 downto 0) := rdata(95 downto 64);
when others => va.hrdata(31 downto 0) := rdata(127 downto 96);
end case;
va.hrdata(127 downto 32) := va.hrdata(31 downto 0) &
va.hrdata(31 downto 0) &
va.hrdata(31 downto 0);
end if;
if nosync = 0 then
va.sync := r.startsd;
if ra.startsd = ra.sync then ready := '1';
else ready := '0'; end if;
else
if ra.startsd = r.startsd then ready := '1';
else ready := '0'; end if;
end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.htrans := ahbsi.htrans; va.haddr := ahbsi.haddr;
va.size := ahbsi.hsize(2 downto 0); va.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
va.hsel := '1'; va.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then va.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
va.write := (others => "0000");
if ((va.hsel and va.htrans(1)) = '1') then
if va.hwrite = '0' then
va.state := rhold; va.startsd := not ra.startsd;
else
va.state := dwrite; va.hready := '1';
end if;
end if;
va.raddr := ra.haddr(7 downto 2);
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.acc := (va.haddr, va.size, va.hwrite);
end if;
when rhold =>
va.raddr := ra.haddr(7 downto 2);
if ready = '1' then
va.state := dread; va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
end if;
when dread =>
va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
if ((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.raddr(3 downto 0) = "0000") then
va.state := midle; va.hready := '0';
end if;
va.acc := (va.haddr, va.size, va.hwrite);
when dwrite =>
va.raddr := ra.haddr(7 downto 2); va.hready := '1';
if (((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.haddr(5 downto 2) = "1111")
or (AHBDW > 32 and ra.haddr(5 downto 2) = "1110" and andv(ra.size(1 downto 0)) = '1')
or (AHBDW > 64 and ra.haddr(5 downto 2) = "1100" and ra.size(2) = '1')) then
va.startsd := not ra.startsd; va.state := whold1;
va.hready := '0';
end if;
tmp := decode(ra.haddr(1 downto 0));
waddr := conv_integer(ra.haddr(5 downto 2));
va.hwdata(waddr) := hwdata(31 downto 0);
case ra.size is
when "000" => va.write(waddr) := tmp(0) & tmp(1) & tmp(2) & tmp(3);
when "001" => va.write(waddr) := tmp(0) & tmp(0) & tmp(2) & tmp(2);
when "010" => va.write(waddr) := "1111";
when "011" => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
when others => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.write(waddr+2) := "1111"; va.write(waddr+3) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
va.hwdata(waddr+2) := hwdata((95 mod AHBDW) downto (64 mod AHBDW));
va.hwdata(waddr+3) := hwdata((127 mod AHBDW) downto (96 mod AHBDW));
end case;
when whold1 =>
va.state := whold2;
when whold2 =>
if ready = '1' then
va.state := midle; va.acc := (va.haddr, va.size, va.hwrite);
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then va.hready := '1'; end if;
end if;
if rst = '0' then
va.hsel := '0';
va.hready := '1';
va.state := midle;
va.startsd := '0';
va.acc.hwrite := '0';
va.acc.haddr := (others => '0');
end if;
rai <= va;
end process;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= ahbdrivedata(ra.hrdata);
migi.app_addr <= '0' & ra.acc.haddr(28 downto 6) & "000";
ddr_ctrl : process(rst, r, ra, migo)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable app_en : std_ulogic;
variable app_cmd : std_logic_vector(2 downto 0);
variable app_wdf_mask : std_logic_vector(31 downto 0);
variable app_wdf_wren : std_ulogic;
variable app_wdf_end : std_ulogic;
variable app_wdf_data : std_logic_vector(255 downto 0);
begin
-- Variable default settings to avoid latches
v := r; app_en := '0'; app_cmd := "000";
app_wdf_wren := '0'; app_wdf_mask := ra.write(7) & ra.write(6) & ra.write(5) &
ra.write(4) & ra.write(3) & ra.write(2) & ra.write(1) & ra.write(0);
app_wdf_data := ra.hwdata(7) & ra.hwdata(6) & ra.hwdata(5) & ra.hwdata(4) &
ra.hwdata(3) & ra.hwdata(2) & ra.hwdata(1) & ra.hwdata(0);
if ra.acc.hwrite = '0' then app_cmd(0) := '1'; else app_cmd(0) := '0'; end if;
app_wdf_end := '0'; v.sync := ra.startsd;
if nosync = 0 then
if r.startsd /= r.sync then startsd := '1';
else startsd := '0'; end if;
else
if ra.startsd /= r.startsd then startsd := '1';
else startsd := '0'; end if;
end if;
case r.dstate is
when midle =>
if startsd = '1' then app_en := '1'; end if;
if (migo.app_rdy and app_en) = '1' then
if ra.acc.hwrite = '0' then v.dstate := dread;
else v.dstate := dwrite; end if;
end if;
when dread =>
if migo.app_rd_data_valid = '1' then
v.hrdata(255 downto 0) := migo.app_rd_data;
v.dstate := rhold;
end if;
when rhold =>
v.hrdata(511 downto 256) := migo.app_rd_data;
v.dstate := midle;
v.startsd := not r.startsd;
when dwrite =>
app_wdf_wren := '1';
if migo.app_wdf_rdy = '1' then
v.dstate := whold1;
end if;
when whold1 =>
app_wdf_wren := '1'; app_wdf_end := '1';
app_wdf_mask := ra.write(15) & ra.write(14) & ra.write(13) &
ra.write(12) & ra.write(11) & ra.write(10) & ra.write(9) & ra.write(8);
app_wdf_data := ra.hwdata(15) & ra.hwdata(14) & ra.hwdata(13) & ra.hwdata(12) &
ra.hwdata(11) & ra.hwdata(10) & ra.hwdata(9) & ra.hwdata(8);
if migo.app_wdf_rdy = '1' then
v.startsd := not r.startsd;
v.dstate := midle;
end if;
when others =>
end case;
-- reset
if rst = '0' then
v.startsd := '0';
end if;
ri <= v;
migi.app_cmd <= app_cmd;
migi.app_en <= app_en;
migi.app_wdf_wren <= app_wdf_wren;
migi.app_wdf_end <= app_wdf_end;
migi.app_wdf_mask <= not app_wdf_mask;
migi.app_wdf_data <= app_wdf_data;
end process;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
clk_ahb1 <= clk_ahb; clk_ahb2 <= clk_ahb1; -- sync clock deltas
ahbregs : process(clk_ahb2) begin
if rising_edge(clk_ahb2) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr, rst) begin
if rising_edge(clk_ddr) then
r <= ri;
end if;
end process;
-- Write data selection.
AHB32: if AHBDW = 32 generate
hwdata <= ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0) &
ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0);
end generate AHB32;
AHB64: if AHBDW = 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(63 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab(63 downto 0) <= ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(1 downto 0) = "11") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(31 downto 0) & hwdatab(63 downto 32);
end generate AHB64;
AHBWIDE: if AHBDW > 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(127 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab <= ahbread4word(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(2) = '1') else
(ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2))) when (ra.size = "011") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(95 downto 64) & hwdatab(127 downto 96);
end generate AHBWIDE;
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "mig2ahb" & tost(hindex) & ": 64-bit DDR2/3 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
|
gpl-2.0
|
7977ff265da86c9c7603c7a0693038c7
| 0.570458 | 3.279765 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/misc/gptimer.vhd
| 1 | 20,272 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gptimer
-- File: gptimer.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implemets a set of general-purpose timers with a
-- common prescaler. Then number of timers and the width of
-- the timers is propgrammable through generics
--
-- Revision 1 of this core merges functionality of the GRTIMET unit:
--
-- This unit also implements the use of an external clock source for the
-- timers.
--
-- This unit also implements a latching register for each timer, latching the
-- timer value on the occurence of an interrupt on the apbi.priq input. The
-- interrupt selection in possible via a mask register.
--
-- This unit also implements loading of all timers on the event of a selected
-- incoming interrupt.
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity gptimer is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
sepirq : integer := 0; -- use separate interrupts for each timer
sbits : integer := 16; -- scaler bits
ntimers : integer range 1 to 7 := 1; -- number of timers
nbits : integer := 32; -- timer bits
wdog : integer := 0;
ewdogen : integer := 0;
glatch : integer := 0;
gextclk : integer := 0;
gset : integer := 0;
gelatch : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpti : in gptimer_in_type;
gpto : out gptimer_out_type
);
end;
architecture rtl of gptimer is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_GPTIMER, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type timer_reg is record
enable : std_ulogic; -- enable counter
load : std_ulogic; -- load counter
restart : std_ulogic; -- restart counter
irqpen : std_ulogic; -- interrupt pending
irqen : std_ulogic; -- interrupt enable
irq : std_ulogic; -- interrupt pulse
chain : std_ulogic; -- chain with previous timer
value : std_logic_vector(nbits-1 downto 0);
reload : std_logic_vector(nbits-1 downto 0);
latch : std_logic_vector(glatch*(nbits-1) downto 0);
end record;
type timer_reg_vector is array (Natural range <> ) of timer_reg;
constant TBITS : integer := log2x(ntimers+1);
type registers is record
scaler : std_logic_vector(sbits-1 downto 0);
reload : std_logic_vector(sbits-1 downto 0);
tick : std_ulogic;
tsel : integer range 0 to ntimers;
timers : timer_reg_vector(1 to ntimers);
dishlt : std_ulogic;
wdogn : std_ulogic;
wdog : std_ulogic;
wdogdis : std_ulogic;
wdognmi : std_ulogic;
end record;
type registers2 is record
setdis : std_ulogic;
latchdis : std_ulogic;
elatchen : std_ulogic;
latchsel : std_logic_vector(NAHBIRQ-1 downto 0);
latchen : std_ulogic;
latchdel : std_ulogic;
extclken : std_ulogic;
extclk : std_logic_vector(2 downto 0);
seten : std_ulogic;
setdel : std_ulogic;
end record;
constant NMI : integer := 15;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
function RESVAL_FUNC return registers is
variable vres : registers;
begin
vres.scaler := (others => '1');
vres.reload := (others => '1');
vres.tick := '0';
vres.tsel := 0;
for i in 1 to ntimers loop
vres.timers(i).enable := '0';
vres.timers(i).load := '0';
vres.timers(i).restart := '0';
vres.timers(i).irqpen := '0';
vres.timers(i).irqen := '0';
vres.timers(i).irq := '0';
vres.timers(i).chain := '0';
vres.timers(i).value := (others => '0');
vres.timers(i).reload := (others => '0');
vres.timers(i).latch := (others => '0');
end loop;
if wdog /= 0 then
vres.timers(ntimers).enable := '1'; -- May be overriden by ewdogen
vres.timers(ntimers).load := '1';
vres.timers(ntimers).reload := conv_std_logic_vector(wdog, nbits);
vres.timers(ntimers).irqen := '1';
end if;
vres.dishlt := '0';
vres.wdogn := '1';
vres.wdog := '0';
vres.wdogdis := '0';
vres.wdognmi := '0';
return vres;
end function RESVAL_FUNC;
constant RESVAL : registers := RESVAL_FUNC;
constant RESVAL2 : registers2 := (
setdis => '0',
latchdis => '0',
elatchen => '0',
latchsel => (others => '0'),
latchen => '0',
latchdel => '0',
extclken => '0',
extclk => (others => '0'),
seten => '0',
setdel => '0');
signal r, rin : registers;
signal r2, rin2 : registers2;
begin
comb : process(rst, r, r2, apbi, gpti)
variable scaler : std_logic_vector(sbits downto 0);
variable readdata, timer1 : std_logic_vector(31 downto 0);
variable res, addin : std_logic_vector(nbits-1 downto 0);
variable v : registers;
variable z : std_ulogic;
variable vtimers : timer_reg_vector(0 to ntimers);
variable xirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable nirq : std_logic_vector(0 to ntimers-1);
variable tick : std_logic_vector(1 to 7);
variable latch : std_ulogic;
variable latchval : std_logic_vector(NAHBIRQ-1 downto 0);
variable latchd : std_ulogic;
variable v2 : registers2;
begin
v := r; v2 := r2; v.tick := '0'; tick := (others => '0'); latch := '0';
latchval := apbi.pirq; latchd := '0';
vtimers(0) := ('0', '0', '0', '0', '0', '0', '0',
zero32(nbits-1 downto 0), zero32(nbits-1 downto 0),
zero32(glatch*(nbits-1) downto 0));
vtimers(1 to ntimers) := r.timers; xirq := (others => '0');
for i in 1 to ntimers loop
v.timers(i).irq := '0'; v.timers(i).load := '0';
tick(i) := r.timers(i).irq;
end loop;
v.wdog := r.timers(ntimers).irqpen and not r.wdogdis;
v.wdogn := not v.wdog;
-- scaler operation
scaler := ('0' & r.scaler) - 1; -- decrement scaler
if gextclk = 1 then -- optional external timer clock
v2.extclk := r2.extclk(1 downto 0) & gpti.extclk;
end if;
if ((gextclk=0) or (gextclk=1 and r2.extclken='0') or
(gextclk=1 and r2.extclken='1' and r2.extclk(2 downto 1) = "01")) then
if (not gpti.dhalt or r.dishlt) = '1' then -- halt timers in debug mode
if (scaler(sbits) = '1') then
v.scaler := r.reload; v.tick := '1'; -- reload scaler
else v.scaler := scaler(sbits-1 downto 0); end if;
end if;
end if;
-- timer operation
if (r.tick = '1') or (r.tsel /= 0) then
if r.tsel = ntimers then v.tsel := 0;
else v.tsel := r.tsel + 1; end if;
end if;
res := vtimers(r.tsel).value - 1; -- decrement selected timer
if (res(nbits-1) = '1') and ((vtimers(r.tsel).value(nbits-1) = '0'))
then z := '1'; else z := '0'; end if; -- undeflow detect
-- update corresponding register and generate irq
for i in 1 to ntimers-1 loop nirq(i) := r.timers(i).irq; end loop;
nirq(0) := r.timers(ntimers).irq;
for i in 1 to ntimers loop
if i = r.tsel then
if (r.timers(i).enable = '1') and
(((r.timers(i).chain and nirq(i-1)) or not (r.timers(i).chain)) = '1')
then
v.timers(i).irq := z and not r.timers(i).load;
if (v.timers(i).irq and r.timers(i).irqen) = '1' then
v.timers(i).irqpen := '1';
end if;
v.timers(i).value := res;
if (z and not r.timers(i).load) = '1' then
v.timers(i).enable := r.timers(i).restart;
if r.timers(i).restart = '1' then
v.timers(i).value := r.timers(i).reload;
end if;
end if;
end if;
end if;
if r.timers(i).load = '1' then
v.timers(i).value := r.timers(i).reload;
end if;
end loop;
-- timer external set
if gset = 1 then
if gelatch /= 0 and r2.elatchen = '1' then
latchval := gpti.latchv;
end if;
if NAHBIRQ <= 32 then
for i in NAHBIRQ-1 downto 0 loop
latch := latch or (v2.latchsel(i) and latchval(i));
if gelatch = 2 then latchd := latchd or (v2.latchsel(i) and gpti.latchd(i)); end if;
end loop;
else
for i in 31 downto 0 loop
latch := latch or (v2.latchsel(i) and latchval(i));
if gelatch = 2 then latchd := latchd or (v2.latchsel(i) and gpti.latchd(i)); end if;
end loop;
end if;
if gelatch = 2 and (r2.seten = '1' and r2.elatchen = '1') then
if latchd = '1' then
v2.setdis := '1';
end if;
if r2.setdis = '1' and r.tsel = 0 then
v2.setdis := '0'; v2.seten := '0'; v2.setdel := '0';
end if;
end if;
if (latch='1' and r2.seten='1' and r.tsel = 0) or
(r2.setdel = '1' and r2.seten='1' and r.tsel = 0) then
for i in 1 to ntimers loop
v.timers(i).value := r.timers(i).reload;
end loop;
v2.setdel := '0';
if gelatch < 2 or (gelatch = 2 and (r2.elatchen = '0' or v2.setdis = '1')) then
v2.seten := '0';
if gelatch = 2 then v2.setdis := '0'; end if;
end if;
elsif latch='1' and r2.seten='1' and r.tsel /= 0 then
v2.setdel := '1';
end if;
end if;
if sepirq /= 0 then
for i in 1 to ntimers loop
xirq(i-1+pirq) := r.timers(i).irq and r.timers(i).irqen;
end loop;
else
for i in 1 to ntimers loop
xirq(pirq) := xirq(pirq) or (r.timers(i).irq and r.timers(i).irqen);
end loop;
end if;
if wdog /= 0 then
if (r.wdognmi and r.timers(ntimers).irq and r.timers(ntimers).irqen) = '1' then
xirq(NMI) := '1';
end if;
end if;
-- read registers
readdata := (others => '0');
case apbi.paddr(6 downto 2) is
when "00000" => readdata(sbits-1 downto 0) := r.scaler;
when "00001" => readdata(sbits-1 downto 0) := r.reload;
when "00010" =>
readdata(2 downto 0) := conv_std_logic_vector(ntimers, 3) ;
readdata(7 downto 3) := conv_std_logic_vector(pirq, 5) ;
if (sepirq /= 0) then readdata(8) := '1'; end if;
readdata(9) := r.dishlt;
if gextclk = 1 then readdata(10) := r2.extclken; end if;
if glatch = 1 then readdata(11) := r2.latchen; end if;
if gset = 1 then readdata(12) := r2.seten; end if;
if gelatch /= 0 then readdata(13) := r2.elatchen; end if;
when "00011" =>
if glatch = 1 then
if NAHBIRQ <= 32 then
for i in NAHBIRQ-1 downto 0 loop
readdata(i) := r2.latchsel(i);
end loop;
else
for i in 31 downto 0 loop
readdata(i) := r2.latchsel(i);
end loop;
end if;
end if;
when others =>
for i in 1 to ntimers loop
if conv_integer(apbi.paddr(6 downto 4)) = i then
case apbi.paddr(3 downto 2) is
when "00" => readdata(nbits-1 downto 0) := r.timers(i).value;
when "01" => readdata(nbits-1 downto 0) := r.timers(i).reload;
when "10" =>
if wdog /= 0 and i = ntimers then
readdata(8 downto 7) := r.wdogdis & r.wdognmi;
end if;
readdata(6 downto 0) :=
gpti.dhalt & r.timers(i).chain &
r.timers(i).irqpen & r.timers(i).irqen & r.timers(i).load &
r.timers(i).restart & r.timers(i).enable;
when "11" =>
if glatch = 1 then
readdata(glatch*(nbits-1) downto 0) := r.timers(i).latch;
end if;
when others =>
end case;
end if;
end loop;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(6 downto 2) is
when "00000" => v.scaler := apbi.pwdata(sbits-1 downto 0);
when "00001" => v.reload := apbi.pwdata(sbits-1 downto 0);
v.scaler := apbi.pwdata(sbits-1 downto 0);
when "00010" => v.dishlt := apbi.pwdata(9);
if gextclk = 1 then v2.extclken := apbi.pwdata(10); end if;
if glatch = 1 then v2.latchen := apbi.pwdata(11); end if;
if gset = 1 then v2.seten := apbi.pwdata(12); end if;
if gelatch /= 0 then v2.elatchen := apbi.pwdata(13); end if;
when "00011" =>
if glatch=1 then
if NAHBIRQ <= 32 then
for i in NAHBIRQ-1 downto 0 loop
v2.latchsel(i) := apbi.pwdata(i);
end loop;
else
for i in 31 downto 0 loop
v2.latchsel(i) := apbi.pwdata(i);
end loop;
end if;
end if;
when others =>
for i in 1 to ntimers loop
if conv_integer(apbi.paddr(6 downto 4)) = i then
case apbi.paddr(3 downto 2) is
when "00" => v.timers(i).value := apbi.pwdata(nbits-1 downto 0);
when "01" => v.timers(i).reload := apbi.pwdata(nbits-1 downto 0);
when "10" => if wdog /= 0 and i = ntimers then
v.wdogdis := apbi.pwdata(8);
v.wdognmi := apbi.pwdata(7);
end if;
v.timers(i).chain := apbi.pwdata(5);
v.timers(i).irqpen := v.timers(i).irqpen and not apbi.pwdata(4);
v.timers(i).irqen := apbi.pwdata(3);
v.timers(i).load := apbi.pwdata(2);
v.timers(i).restart := apbi.pwdata(1);
v.timers(i).enable := apbi.pwdata(0);
when others =>
end case;
end if;
end loop;
end case;
end if;
-- timer latches
if glatch=1 then
latch := '0'; latchd := '0';
if gelatch /= 0 and r2.elatchen = '1' then
latchval := gpti.latchv;
end if;
if NAHBIRQ <= 32 then
for i in NAHBIRQ-1 downto 0 loop
latch := latch or (v2.latchsel(i) and latchval(i));
if gelatch = 2 then latchd := latchd or (v2.latchsel(i) and gpti.latchd(i)); end if;
end loop;
else
for i in 31 downto 0 loop
latch := latch or (v2.latchsel(i) and latchval(i));
if gelatch = 2 then latchd := latchd or (v2.latchsel(i) and gpti.latchd(i)); end if;
end loop;
end if;
if gelatch /= 0 and (r2.latchen = '1' and r2.elatchen = '1') then
if latchd = '1' then
v2.latchdis := '1';
end if;
if r2.latchdis = '1' and r.tsel = 0 then
v2.latchdis := '0'; v2.latchen := '0'; v2.latchdel := '0';
end if;
end if;
if ((latch='1' and r2.latchen='1' and r.tsel = 0) or
(r2.latchdel = '1' and r2.latchen='1' and r.tsel = 0)) then
for i in 1 to ntimers loop
v.timers(i).latch := r.timers(i).value(glatch*(nbits-1) downto 0);
end loop;
v2.latchdel := '0';
if gelatch < 2 or (gelatch = 2 and (r2.elatchen = '0' or v2.latchdis = '1')) then
v2.latchen := '0';
if gelatch = 2 then v2.latchdis := '0'; end if;
end if;
elsif latch='1' and r2.latchen='1' and r.tsel /= 0 then
v2.latchdel := '1';
end if;
end if;
-- reset operation
if (not RESET_ALL) and (rst = '0') then
for i in 1 to ntimers loop
v.timers(i).enable := RESVAL.timers(i).enable;
v.timers(i).irqen := RESVAL.timers(i).irqen;
v.timers(i).irqpen := RESVAL.timers(i).irqpen;
v.timers(i).irq := RESVAL.timers(i).irq;
end loop;
v.scaler := RESVAL.scaler; v.reload := RESVAL.reload;
v.tsel := RESVAL.tsel; v.dishlt := RESVAL.dishlt;
v.timers(ntimers).irq := RESVAL.timers(ntimers).irq;
if (wdog /= 0) then
if ewdogen /= 0 then v.timers(ntimers).enable := gpti.wdogen;
else v.timers(ntimers).enable := RESVAL.timers(ntimers).enable; end if;
v.timers(ntimers).load := RESVAL.timers(ntimers).load;
v.timers(ntimers).reload := RESVAL.timers(ntimers).reload;
v.timers(ntimers).chain := RESVAL.timers(ntimers).chain;
v.timers(ntimers).irqen := RESVAL.timers(ntimers).irqen;
v.timers(ntimers).irqpen := RESVAL.timers(ntimers).irqpen;
v.timers(ntimers).restart := RESVAL.timers(ntimers).restart;
end if;
v.wdogdis := RESVAL.wdogdis; v.wdognmi := RESVAL.wdognmi;
if glatch = 1 then
for i in 1 to ntimers loop v.timers(i).latch := RESVAL.timers(i).latch; end loop;
if gelatch /= 0 then v2.elatchen := RESVAL2.elatchen; end if;
if gelatch = 2 then v2.setdis := '0'; v2.latchdis := '0'; end if;
v2.latchen := RESVAL2.latchen; v2.latchdel := RESVAL2.latchdel;
v2.latchsel := RESVAL2.latchsel;
end if;
if gextclk = 1 then
v2.extclken := RESVAL2.extclken;
v2.extclk := RESVAL2.extclk;
end if;
if gset = 1 then v2.seten := RESVAL2.seten; v2.setdel := RESVAL2.setdel; end if;
end if;
if wdog = 0 then v.wdogdis := '0'; v.wdognmi := '0'; end if;
if glatch = 0 then
for i in 1 to ntimers loop v.timers(i).latch := (others => '0'); end loop;
v2.latchen := '0'; v2.latchdel := '0'; v2.latchsel := (others => '0');
end if;
if glatch = 0 or gelatch = 0 then v2.elatchen := '0'; end if;
if glatch = 0 or gelatch < 2 then v2.latchdis := '0'; v2.setdis := '0'; end if;
if gextclk = 0 then v2.extclken := '0'; v2.extclk := (others => '0'); end if;
if gset = 0 then v2.seten := '0'; v2.setdel := '0'; end if;
timer1 := (others => '0'); timer1(nbits-1 downto 0) := r.timers(1).value;
rin <= v; rin2 <= v2;
apbo.prdata <= readdata; -- drive apb read bus
apbo.pirq <= xirq;
apbo.pindex <= pindex;
gpto.tick <= r.tick & tick;
gpto.timer1 <= timer1; -- output timer1 value for debugging
gpto.wdogn <= r.wdogn;
gpto.wdog <= r.wdog;
end process;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin; r2 <= rin2;
if RESET_ALL and rst = '0' then
r <= RESVAL; r2 <= RESVAL2;
if wdog /= 0 and ewdogen /= 0 then
r.timers(ntimers).enable <= gpti.wdogen;
end if;
end if;
end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("gptimer" & tost(pindex) &
": Timer Unit rev " & tost(REVISION) &
", " & tost(sbits) & "-bit scaler, " & tost(ntimers) &
" " & tost(nbits) & "-bit timers" & ", irq " & tost(pirq));
-- pragma translate_on
end;
|
gpl-2.0
|
06fc28d9b6f975e7d70c2522673bdf50
| 0.55441 | 3.407632 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/i2c/i2c2ahb_apb_gen.vhd
| 1 | 5,368 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb_apb_gen
-- File: i2c2ahb_apb_gen.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Generic wrapper for I2C-slave, see i2c2ahb_apb.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.i2c.all;
entity i2c2ahb_apb_gen is
generic (
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
--ahbi : in ahb_mst_in_type;
ahbi_hgrant : in std_ulogic;
ahbi_hready : in std_ulogic;
ahbi_hresp : in std_logic_vector(1 downto 0);
ahbi_hrdata : in std_logic_vector(AHBDW-1 downto 0);
--ahbo : out ahb_mst_out_type;
ahbo_hbusreq : out std_ulogic;
ahbo_hlock : out std_ulogic;
ahbo_htrans : out std_logic_vector(1 downto 0);
ahbo_haddr : out std_logic_vector(31 downto 0);
ahbo_hwrite : out std_ulogic;
ahbo_hsize : out std_logic_vector(2 downto 0);
ahbo_hburst : out std_logic_vector(2 downto 0);
ahbo_hprot : out std_logic_vector(3 downto 0);
ahbo_hwdata : out std_logic_vector(AHBDW-1 downto 0);
-- APB slave interface
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_irq : out std_logic;
-- I2C signals
--i2ci : in i2c_in_type;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
--i2co : out i2c_out_type
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end entity i2c2ahb_apb_gen;
architecture rtl of i2c2ahb_apb_gen is
-- AHB signals
signal ahbi : ahb_mst_in_type;
signal ahbo : ahb_mst_out_type;
-- APB signals
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_type;
-- I2C signals
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
begin
ahbi.hgrant(0) <= ahbi_hgrant;
ahbi.hgrant(1 to NAHBMST-1) <= (others => '0');
ahbi.hready <= ahbi_hready;
ahbi.hresp <= ahbi_hresp;
ahbi.hrdata <= ahbi_hrdata;
ahbo_hbusreq <= ahbo.hbusreq;
ahbo_hlock <= ahbo.hlock;
ahbo_htrans <= ahbo.htrans;
ahbo_haddr <= ahbo.haddr;
ahbo_hwrite <= ahbo.hwrite;
ahbo_hsize <= ahbo.hsize;
ahbo_hburst <= ahbo.hburst;
ahbo_hprot <= ahbo.hprot;
ahbo_hwdata <= ahbo.hwdata;
apbi.psel(0) <= apbi_psel;
apbi.psel(1 to NAPBSLV-1) <= (others => '0');
apbi.penable <= apbi_penable;
apbi.paddr <= apbi_paddr;
apbi.pwrite <= apbi_pwrite;
apbi.pwdata <= apbi_pwdata;
apbi.pirq <= (others => '0');
apbi.testen <= '0';
apbi.testrst <= '0';
apbi.scanen <= '0';
apbi.testoen <= '0';
apbo_prdata <= apbo.prdata;
apbo_irq <= apbo.pirq(0);
i2ci.scl <= i2ci_scl;
i2ci.sda <= i2ci_sda;
i2co_scl <= i2co.scl;
i2co_scloen <= i2co.scloen;
i2co_sda <= i2co.sda;
i2co_sdaoen <= i2co.sdaoen;
i2co_enable <= i2co.enable;
i2c0 : i2c2ahb_apb
generic map (
hindex => 0,
ahbaddrh => ahbaddrh, ahbaddrl => ahbaddrl,
ahbmaskh => ahbmaskh, ahbmaskl => ahbmaskl,
resen => resen,
pindex => 0, paddr => 0, pmask => 0, pirq => 0,
i2cslvaddr => i2cslvaddr, i2ccfgaddr => i2ccfgaddr,
oepol => oepol, filter => filter)
port map (rstn, clk, ahbi, ahbo, apbi, apbo, i2ci, i2co);
end architecture rtl;
|
gpl-2.0
|
00d89c2c1d0d1327dd1df176c027c91f
| 0.590164 | 3.263222 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/stratixii/clkgen_stratixii.vhd
| 1 | 6,742 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
-- pragma translate_off
use altera_mf.altpll;
-- pragma translate_on
entity stratix2_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of stratix2_pll is
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "CLK0" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Stratix II",
operation_mode => "ZERO_DELAY_BUFFER",
compensate_clock => "CLK2",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= clkout(2);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Stratix II",
operation_mode => "NORMAL",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= '0';
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_stratixii is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_stratixii is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
-- altera pll
component stratix2_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
e0 : out std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : stratix2_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_stratixii" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_stratixii" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
|
gpl-2.0
|
fd260f9f65202c3592a66bb39d365fa6
| 0.585583 | 3.513288 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/can/canmux.vhd
| 5 | 895 |
-----------------------------------------------------------------------------
-- Entity: pcifbackend
-- File: pcifbackend.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: CAN Multiplexer (to connect two CAN buses to one CAN core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity canmux is
port(
sel : in std_logic;
canrx : out std_logic;
cantx : in std_logic;
canrxv : in std_logic_vector(0 to 1);
cantxv : out std_logic_vector(0 to 1)
);
end;
architecture rtl of canmux is
begin
comb : process(sel, cantx, canrxv)
begin
if sel = '1' then
canrx <= canrxv(1);
cantxv(0) <= '1';
cantxv(1) <= cantx;
else
canrx <= canrxv(0);
cantxv(0) <= cantx;
cantxv(1) <= '1';
end if;
end process;
end;
|
gpl-2.0
|
a99dbb9349475d2305a768b2ea421831
| 0.487151 | 3.608871 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep3c25-eek/serializer.vhd
| 1 | 2,705 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Entity: serializer
-- File: serializer.vhd
-- Author: Jan Andersson - Gaisler Research AB
-- [email protected]
--
-- Description: Takes in three vectors and serializes them into one
-- output vector. Intended to be used to serialize
-- RGB VGA data.
--
library ieee;
use ieee.std_logic_1164.all;
entity serializer is
generic (
length : integer := 8 -- vector length
);
port (
clk : in std_ulogic;
sync : in std_ulogic;
ivec0 : in std_logic_vector((length-1) downto 0);
ivec1 : in std_logic_vector((length-1) downto 0);
ivec2 : in std_logic_vector((length-1) downto 0);
ovec : out std_logic_vector((length-1) downto 0)
);
end entity serializer;
architecture rtl of serializer is
type state_type is (vec0, vec1, vec2);
type sreg_type is record
state : state_type;
sync : std_logic_vector(1 downto 0);
end record;
signal r, rin : sreg_type;
begin -- rtl
comb: process (r, clk, sync, ivec0, ivec1, ivec2)
variable v : sreg_type;
begin -- process comb
v := r;
v.sync := r.sync(0) & sync;
case r.state is
when vec0 =>
ovec <= ivec0;
v.state := vec1;
when vec1 =>
ovec <= ivec1;
v.state := vec2;
when vec2 =>
ovec <= ivec2;
v.state := vec0;
end case;
if (r.sync(0) xor sync) = '1' then
v.state := vec1;
end if;
rin <= v;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
end rtl;
|
gpl-2.0
|
f98f3d25ff11f7b4a43361d399d05cf3
| 0.58854 | 3.756944 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-c5ekit/config.vhd
| 1 | 5,254 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := altera;
constant CFG_MEMTECH : integer := altera;
constant CFG_PADTECH : integer := altera;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 1 + 64*0;
constant CFG_ATBSZ : integer := 1;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- Gaisler Ethernet core
constant CFG_GRETH2 : integer := 1;
constant CFG_GRETH21G : integer := 0;
constant CFG_ETH2_FIFO : integer := 8;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#000F#;
constant CFG_GRGPIO_WIDTH : integer := (2);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
08839229c0cd4ee26b8874dc1adae48f
| 0.639703 | 3.615967 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica06_SumadorRestador8Bits/topha00txt.vhd
| 1 | 513 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ha00.all;
entity topha00 is
port(
A0: in std_logic ;
B0: in std_logic ;
S0: out std_logic ;
C0: out std_logic );
end;
architecture topha0 of topha00 is
begin
U0: and00 port map (Aa => A0,
Ba => B0,
Ya => C0);
U1: xor00 port map (Ax => A0,
Bx => B0,
Yx => S0);
end topha0;
|
apache-2.0
|
bd788a6cd586b51c622efaaa2bcb8860
| 0.504873 | 2.914773 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/memctrl/sdmctrl.vhd
| 1 | 25,532 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdmctrl
-- File: sdmctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: SDRAM memory controller to fit with LEON2 memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
entity sdmctrl is
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end;
architecture rtl of sdmctrl is
constant WPROTEN : boolean := (wprot /= 0);
constant SDINVCLK : boolean := (invclk /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant PM_PD : std_logic_vector(2 downto 0) := "001";
constant PM_SR : std_logic_vector(2 downto 0) := "010";
constant PM_DPD : std_logic_vector(2 downto 0) := "101";
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4, wr5, sidle, sref, pd, dpd);
type icycletype is (iidle, pre, ref, lmode, emode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
pageburst : std_ulogic;
mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
cke : std_ulogic; -- Clock enable
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
burst : std_ulogic;
busy : std_ulogic;
bdelay : std_ulogic;
wprothit : std_ulogic;
startsd : std_ulogic;
aload : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(3 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
bsel : std_ulogic;
haddr : std_logic_vector(31 downto 10);
-- only needed to keep address lines from switch too much
address : std_logic_vector(16 downto 2); -- memory address
idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
end record;
signal r, ri : reg_type;
begin
ctrl : process(rst, apbi, sdi, wpo, r)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable haddr : std_logic_vector(31 downto 0);
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec : std_ulogic;
variable busy : std_ulogic;
variable aload : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable hresp : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable lline : std_logic_vector(2 downto 0);
variable rline : std_logic_vector(2 downto 0);
variable lineburst : boolean;
variable arefresh : std_logic;
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.busy := '0'; hresp := HRESP_OKAY;
lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
rline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
arefresh := '0';
if sdi.hready = '1' then v.hsel := sdi.hsel; end if;
if (sdi.hready and sdi.hsel ) = '1' then
if sdi.htrans(1) = '1' then v.hready := '0'; end if;
end if;
if fast = 1 then haddr := sdi.rhaddr; else haddr := sdi.haddr; end if;
if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
lineburst := true;
else lineburst := false; end if;
-- main state
case sdi.hsize is
when "00" =>
case sdi.rhaddr(1 downto 0) is
when "00" => dqm := "11110111";
when "01" => dqm := "11111011";
when "10" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
if sdi.rhaddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if;
when others => dqm := "11110000";
end case;
if BUS64 and (r.bsel = '1') then
dqm := dqm(3 downto 0) & "1111";
end if;
-- main FSM
case r.mstate is
when midle =>
if (v.hsel and sdi.nhtrans(1)) = '1' then
if (r.sdstate = sidle) and (r.cfg.command = "000") and
(r.cmstate = midle) and (sdi.idle = '1')
then
if fast = 1 then v.startsd := '1'; else startsd := '1'; end if;
v.mstate := active;
elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
and (r.cfg.command = "000") and (r.cmstate = midle) --and (v.hio = '0')
then
v.startsd := '1';
if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
hresp := HRESP_ERROR;
else
v.mstate := active;
end if;
end if;
end if;
when others => null;
end case;
startsd := r.startsd or startsd;
-- generate row and column address size
case r.cfg.csize is
when "00" => raddr := haddr(22 downto 10);
when "01" => raddr := haddr(23 downto 11);
when "10" => raddr := haddr(24 downto 12);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
else raddr := haddr(25 downto 13); end if;
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
genmux(r.cfg.bsize, haddr(27 downto 20));
-- generate chip select
if BUS64 then
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
v.bsel := genmux(r.cfg.bsize, sdi.rhaddr(29 downto 22));
else
adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
end if;
if (sdi.srdis = '0') and (r.cfg.bsize = "111") then adec := not adec; end if;
rams := adec & not adec;
if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
-- sdram access FSM
case r.sdstate is
when sidle =>
v.bdelay := '0';
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
v.address(16 downto 2) := ba & raddr;
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
case r.cfg.pmode is
when PM_SR =>
v.cfg.cke := '0'; v.sdstate := sref;
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
when PM_DPD =>
v.cfg.cke := '0'; v.sdstate := dpd;
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
when others =>
end case;
end if;
when act1 =>
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; v.haddr := sdi.rhaddr(31 downto 10);
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1);
end if;
if WPROTEN then
v.wprothit := wpo.wprothit;
if wpo.wprothit = '1' then hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1);
if WPROTEN and (r.wprothit = '1') then
hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2);
v.dqm := dqm; v.burst := r.hready;
if sdi.hwrite = '1' then
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '1';
if sdi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
if WPROTEN and (r.wprothit = '1') then
hresp := HRESP_ERROR; v.hready := '1';
v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '0'; v.casn := '1';
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2);
if (((r.burst and r.hready) = '1') and (sdi.rhtrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))
then
v.hready := sdi.htrans(0) and sdi.htrans(1) and r.hready;
if ((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '0'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.hsel = '1') then
if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3;
elsif (r.trfc(2 downto 1) = "00") then
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
end if;
when wr3 =>
if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.sdwen = '1') and (r.hsel = '1') then
if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3;
elsif (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if r.trfc = "0000" then v.sdstate := sidle; end if;
end if;
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else
if r.trfc = "0000" then v.sdstate := sidle; end if;
end if;
when wr5 =>
if r.trfc = "0000" then v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if lineburst and (sdi.htrans = "11") then
if sdi.rhaddr(4 downto 2) = "111" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd7 =>
v.casn := '1';
if r.cfg.casdel = '1' then
v.sdstate := rd2;
if lineburst and (sdi.htrans = "11") then
if sdi.rhaddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else
v.sdstate := rd3;
if sdi.htrans /= "11" then
if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if sdi.rhaddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if sdi.htrans /= "11" then -- v.rasn := '0'; v.sdwen := '0';
if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if sdi.rhaddr(4 downto 2) = "101" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
elsif lineburst and (sdi.htrans = "11") and (r.casn = '1') then
if sdi.rhaddr(4 downto 2) = ("10" & not r.cfg.casdel) then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (sdi.htrans /= "11") or (r.sdcsn = "11") or
((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
elsif lineburst then
if (sdi.rhaddr(4 downto 2) = lline) and (r.casn = '1') then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when sref =>
if (startsd = '1') -- and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
if r.trfc = "0000" then -- Minimum duration (= tRAS)
v.cfg.cke := '1';
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
end if;
if r.cfg.cke = '1' then
if (r.idlecnt = "0000") then -- tXSR ns with NOP
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.sref_tmpcom := r.cfg.command;
v.cfg.command := "100";
end if;
else
v.idlecnt := r.cfg.txsr;
end if;
end if;
when pd =>
if (startsd = '1') -- and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
v.cfg.cke := '1';
v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when dpd =>
v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
v.cfg.renable := '0';
if (startsd = '1') then -- and r.hio = '0') then
v.hready := '1'; -- ack all accesses with Error response
v.startsd := '0';
hresp := HRESP_ERROR;
elsif r.cfg.pmode /= PM_DPD then
v.cfg.cke := '1';
if r.cfg.cke = '1' then
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.cfg.renable := '1';
end if;
end if;
when others =>
v.sdstate := sidle; v.idlecnt := (others => '1');
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "010" => -- precharge
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
end if;
when "100" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "110" =>
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
if lineburst then
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011";
else
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111";
end if;
end if;
when "111" => -- Load Ext-Mode Reg
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
& r.cfg.pasr(2 downto 0);
end if;
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; --v.cfg.command := "000";
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
when leadout =>
if r.trfc = "0000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
v.cfg.cke := '1';
if (sdi.idle and sdi.enable) = '1' and r.cfg.cke = '1' then
v.cfg.command := "010"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.mobileen = "11" then
v.cfg.command := "111"; v.istate := emode;
else
v.istate := finish;
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := finish;
end if;
when others =>
if sdi.enable = '0' and r.sdstate /= dpd then
v.istate := iidle;
end if;
end case;
if (sdi.hready and sdi.hsel ) = '1' then
if sdi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "100";
arefresh := '1';
end if;
end if;
-- APB register access
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
if pageburst = 2 then v.cfg.pageburst := apbi.pwdata(17); end if;
if sdi.enable = '1' then
v.cfg.command(2 downto 1) := apbi.pwdata(20 downto 19);
end if;
v.cfg.csize := apbi.pwdata(22 downto 21);
v.cfg.bsize := apbi.pwdata(25 downto 23);
v.cfg.casdel := apbi.pwdata(26);
v.cfg.trfc := apbi.pwdata(29 downto 27);
v.cfg.trp := apbi.pwdata(30);
v.cfg.renable := apbi.pwdata(31);
when "10" =>
v.cfg.refresh := apbi.pwdata(26 downto 12);
v.refresh := (others => '0');
when "11" =>
if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := apbi.pwdata(31); end if;
if r.cfg.pmode = "000" then
v.cfg.cke := apbi.pwdata(30);
end if;
if r.cfg.mobileen(1) = '1' then
if sdi.enable = '1' then
v.cfg.command(0) := apbi.pwdata(29);
end if;
v.cfg.txsr := apbi.pwdata(23 downto 20);
v.cfg.pmode := apbi.pwdata(18 downto 16);
v.cfg.ds(3 downto 2) := apbi.pwdata( 6 downto 5);
v.cfg.tcsr(3 downto 2) := apbi.pwdata( 4 downto 3);
v.cfg.pasr(5 downto 3) := apbi.pwdata( 2 downto 0);
end if;
when others =>
end case;
end if;
-- Disable CS and DPD when Mobile SDR is Disabled
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
-- Update EMR when ds, tcsr or pasr change
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
end if;
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
end if;
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
end if;
end if;
regsd := (others => '0');
case apbi.paddr(3 downto 2) is
when "01" =>
regsd(31 downto 19) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command(2 downto 1);
if not lineburst then regsd(17) := '1'; end if;
regsd(16) := r.cfg.mobileen(1);
when "11" =>
regsd(31) := r.cfg.mobileen(0);
regsd(30) := r.cfg.cke;
regsd(30) := r.cfg.command(0);
regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
when others =>
regsd(26 downto 12) := r.cfg.refresh;
end case;
sdmo.prdata <= regsd;
-- synchronise with sram/prom controller
if fast = 0 then
if (r.sdstate < wr4) or (v.hsel = '1') then v.busy := '1';end if;
else
if (r.sdstate < wr4) or (r.startsd = '1') then v.busy := '1';end if;
end if;
v.busy := v.busy or r.bdelay;
busy := v.busy or r.busy;
v.aload := r.busy and not v.busy;
aload := v.aload;
-- generate memory address
sdmo.address <= v.address;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "000";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
v.cfg.renable := '0';
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.startsd := '0';
if (pageburst = 2) then
v.cfg.pageburst := '0';
end if;
if mobile >= 2 then v.cfg.mobileen := "11";
elsif mobile = 1 then v.cfg.mobileen := "10";
else v.cfg.mobileen := "00"; end if;
v.cfg.txsr := (others => '1');
v.cfg.pmode := (others => '0');
v.cfg.ds := (others => '0');
v.cfg.tcsr := (others => '0');
v.cfg.pasr := (others => '0');
if mobile >= 2 then v.cfg.cke := '0';
else v.cfg.cke := '1'; end if;
v.sref_tmpcom := "000";
v.idlecnt := (others => '1');
end if;
ri <= v;
sdmo.bdrive <= v.bdrive;
--sdo.sdcke <= (others => '1');
sdo.sdcke <= (others => r.cfg.cke);
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
sdmo.busy <= busy;
sdmo.aload <= aload;
sdmo.hready <= r.hready;
sdmo.vhready <= v.hready;
sdmo.hresp <= hresp;
sdmo.hsel <= r.hsel;
sdmo.bsel <= r.bsel;
end process;
regs : process(clk,rst)
begin
if rising_edge(clk) then
r <= ri;
if rst = '0' then
r.icnt <= (others => '0');
end if;
end if;
if rst = '0' then
r.bdrive <= '0';
r.sdcsn <= (others => '1');
end if;
end process;
end;
|
gpl-2.0
|
daebe2ead5fa5d818bcc464825d30708
| 0.525497 | 3.133145 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/testgrouppolito/pr/sync_dprc.vhd
| 1 | 10,221 |
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: sync_dprc
-- File: sync_dprc.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: dprc sync mode (see the DPR IP-core user manual for operations details).
-- Last revision: 08/10/2014
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.DMA2AHB_Package.all;
library testgrouppolito;
use testgrouppolito.dprc_pkg.all;
entity sync_dprc is
port (
rstn : in std_ulogic; -- Asynchronous Reset input (active low)
clkm : in std_ulogic; -- Clock input
dmai : out DMA_In_Type; -- dma signals input
dmao : in DMA_Out_Type; -- dma signals output
icapi : out icap_in_type; -- icap input signals
icapo : in icap_out_type; -- icap output signals
apbregi : in dprc_apbregin_type; -- values from apb registers (control, address, rm_reset)
apbcontrol : out dprc_apbcontrol_type; -- control signals for apb register
rm_reset : out std_logic_vector(31 downto 0)); -- Reconfigurable modules reset (1 bit for each different reconfigurable partition);
end sync_dprc;
architecture syncdprc_rtl of sync_dprc is
type dprc_state is (IDLE, START, GRANTED, GRANTED_VERIFY, WAIT_WRITE_END, END_STATE, BUS_CNTL_ERROR, ICAP_ERROR_STATE, ABORT, ICAP_ERROR_LATENCY);
signal present_state, next_state : dprc_state;
type regs is record
c_grant : std_logic_vector(19 downto 0);
c_ready : std_logic_vector(19 downto 0);
c_latency : std_logic_vector(2 downto 0);
rm_reset : std_logic_vector(31 downto 0);
address : std_logic_vector(31 downto 0);
rst_persist : std_ulogic;
end record;
signal reg, regin : regs;
signal rstact : std_ulogic;
begin
-- fixed signals
dmai.Data <= (others => '0');
dmai.Beat <= HINCR;
dmai.Size <= HSIZE32;
dmai.Store <= '0'; --Only read transfer requests
dmai.Reset <= not(rstn);
dmai.Address <= reg.address;
rm_reset <= reg.rm_reset;
icapi.idata <= dmao.Data;
comb: process(dmao, icapo, apbregi, rstn, present_state, rstact, reg)
variable regv : regs;
begin
apbcontrol.timer_clear <= '0';
apbcontrol.status_clr <= '0';
dmai.Request <= '0';
dmai.Burst <= '0';
dmai.Lock <= '0';
apbcontrol.status_value <= (others=>'0');
apbcontrol.status_en <= '0';
apbcontrol.control_clr <= '0';
apbcontrol.timer_en <= '0';
icapi.cen <= '1';
icapi.wen <= '1';
rstact <= '0';
regv := reg;
case present_state is
when IDLE =>
if (apbregi.control/=X"00000000") then
next_state <= START;
apbcontrol.timer_clear <= '1'; -- clear timer register
apbcontrol.status_clr <= '1'; -- clear status register
regv.c_grant := apbregi.control(19 downto 0);
regv.c_ready := apbregi.control(19 downto 0);
regv.address := apbregi.address;
else
next_state <= IDLE;
end if;
when START =>
if (dmao.Grant and dmao.Ready)='1' then
next_state <= GRANTED;
else
next_state <= START;
end if;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
icapi.wen <= '0'; -- assert icap write enable
when GRANTED =>
if (icapo.odata(7) = '1') then -- if the ICAP is correctly initialized, then monitor ICAP status
next_state <= GRANTED_VERIFY;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
elsif (regv.c_grant=0) then -- if the number of granted requests is equal to the bitstream words, no more requests are needed
next_state <= WAIT_WRITE_END; -- This line is inserted to cover the case of Virtex-4 ICAP incorrect initialization during device programming with Impact
else
next_state <= GRANTED;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
end if;
icapi.wen <= '0'; -- assert icap write enable
icapi.cen <= not(dmao.Ready); --if valid data, write it into ICAP
when GRANTED_VERIFY =>
if (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors
next_state <= ICAP_ERROR_STATE;
elsif (regv.c_grant=0) then -- if the number of granted requests is equal to the bitstream words, no more requests are needed
next_state <= WAIT_WRITE_END;
else
next_state <= GRANTED_VERIFY;
dmai.Request <= '1'; -- Request data
dmai.Burst <= '1'; -- Burst transfer
dmai.Lock <= '1'; -- Locked transfer
end if;
icapi.wen <= '0'; -- assert icap write enable
icapi.cen <= not(dmao.Ready); --if valid data, write it into ICAP
when WAIT_WRITE_END =>
if (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors
next_state <= ICAP_ERROR_STATE;
elsif (regv.c_ready=0) then
next_state <= ICAP_ERROR_LATENCY;
else
next_state <= WAIT_WRITE_END;
end if;
icapi.wen <= '0'; -- assert icap write enable
icapi.cen <= not(dmao.Ready); --if valid data, write it into ICAP
when ICAP_ERROR_LATENCY =>
if (icapo.odata(7) = '0') then -- verify ICAP status for configuration errors
next_state <= ICAP_ERROR_STATE;
regv.c_latency := (others=>'0');
elsif (regv.c_latency=4) then
next_state <= END_STATE;
regv.c_latency := (others=>'0');
else
next_state <= ICAP_ERROR_LATENCY;
regv.c_latency := regv.c_latency+1;
end if;
icapi.wen <= '0';
when END_STATE =>
next_state <= IDLE;
apbcontrol.status_value(3 downto 0) <= "1111";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
regv.rst_persist := '0';
when BUS_CNTL_ERROR =>
next_state <= ABORT;
apbcontrol.status_value(3 downto 0) <= "0100";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
icapi.cen <= '0'; -- Start an 'abort configuration' sequence
regv.c_latency := (others=>'0');
when ICAP_ERROR_STATE =>
next_state <= ABORT;
apbcontrol.status_value(3 downto 0) <= "1000";
apbcontrol.status_en <= '1'; -- Write Status Register
apbcontrol.control_clr <= '1'; -- Clear Control Register
icapi.cen <= '0'; -- Start an 'abort configuration' sequence
regv.c_latency := (others=>'0');
when ABORT =>
if (regv.c_latency=4) then
next_state <= IDLE;
regv.c_latency := (others=>'0');
regv.rst_persist := '1';
else
next_state <= ABORT;
regv.c_latency := regv.c_latency+1;
end if;
icapi.cen <= '0'; -- continue abort sequence
end case;
if (present_state/=IDLE) then
apbcontrol.timer_en <= '1'; -- Enable timer
rstact <= '1';
if dmao.Ready='1' then
regv.c_ready:=regv.c_ready-1;
end if;
if dmao.Grant='1' then
regv.c_grant:=regv.c_grant-1;
regv.address:=regv.address+4;
end if;
end if;
if (dmao.Fault or dmao.Retry)='1' then
next_state <= BUS_CNTL_ERROR;
end if;
-- reconfigurable modules synchrounous reset generation (active high)
for i in 0 to 31 loop
regv.rm_reset(i) := not(rstn) or (apbregi.rm_reset(i) and (rstact or regv.rst_persist));
end loop;
-- registers assignment
regin <= regv;
end process;
reg_proc: process(rstn, clkm)
begin
if rstn='0' then
present_state <= IDLE;
reg.rm_reset <= (others=>'0');
reg.c_grant <= (others=>'0');
reg.c_ready <= (others=>'0');
reg.c_latency <= (others=>'0');
reg.address <= (others=>'0');
reg.rst_persist <= '0';
elsif rising_edge(clkm) then
present_state <= next_state;
reg <= regin;
end if;
end process;
end syncdprc_rtl;
|
gpl-2.0
|
ae661e3510a0ca7af798bcc571e706f9
| 0.589375 | 3.983242 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/jtag/jtagcom2.vhd
| 1 | 10,075 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: jtagcom
-- File: jtagcom.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: JTAG Debug Interface with AHB master interface
-- Redesigned to work for TCK both slower and faster than AHB
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libjtagcom.all;
use gaisler.misc.all;
entity jtagcom2 is
generic (
gatetech: integer := 0;
isel : integer range 0 to 1 := 0;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tapo : in tap_out_type;
tapi : out tap_in_type;
dmao : in ahb_dma_out_type;
dmai : out ahb_dma_in_type;
tckp : in std_ulogic;
tckn : in std_ulogic;
trst : in std_ulogic
);
attribute sync_set_reset of rst : signal is "true";
end;
architecture rtl of jtagcom2 is
constant ADDBITS : integer := 10;
constant NOCMP : boolean := (isel /= 0);
type tckpreg_type is record
addr : std_logic_vector(34 downto 0);
datashft : std_logic_vector(32 downto 0);
done_sync : std_ulogic;
prun : std_ulogic;
inshift : std_ulogic;
holdn : std_ulogic;
end record;
type tcknreg_type is record
run: std_ulogic;
done_sync1: std_ulogic;
qual_rdata: std_ulogic;
addrlo : std_logic_vector(ADDBITS-1 downto 2);
data : std_logic_vector(32 downto 0);
end record;
type ahbreg_type is record
run_sync: std_logic_vector(2 downto 0);
qual_dreg: std_ulogic;
qual_areg: std_ulogic;
areg: std_logic_vector(34 downto 0);
dreg: std_logic_vector(31 downto 0);
done: std_ulogic;
dmastart: std_ulogic;
wdone: std_ulogic;
end record;
signal ar, arin : ahbreg_type;
signal tpr, tprin: tckpreg_type;
signal tnr, tnrin: tcknreg_type;
signal qual_rdata, rdataq: std_logic_vector(31 downto 0);
signal qual_dreg, dregq: std_logic_vector(31 downto 0);
signal qual_areg, aregqin, aregq: std_logic_vector(34 downto 0);
attribute syn_keep: boolean;
attribute syn_keep of rdataq : signal is true;
attribute syn_keep of dregq : signal is true;
attribute syn_keep of aregq : signal is true;
----
attribute syn_preserve: boolean;
attribute syn_keep of ar : signal is true;
attribute syn_keep of tnr : signal is true;
attribute syn_keep of tpr : signal is true;
attribute syn_keep of arin : signal is true;
attribute syn_keep of tnrin : signal is true;
attribute syn_preserve of ar : signal is true;
attribute syn_preserve of tnr : signal is true;
attribute syn_preserve of tpr : signal is true;
attribute syn_preserve of rdataq : signal is true;
attribute syn_preserve of dregq : signal is true;
attribute syn_preserve of aregq : signal is true;
----
begin
rdqgen: for x in 31 downto 0 generate
rdq: grnand2 generic map (tech => gatetech) port map (ar.dreg(x), qual_rdata(x), rdataq(x));
end generate;
dqgen: for x in 31 downto 0 generate
dq: grnand2 generic map (tech => gatetech) port map (tnr.data(x), qual_dreg(x), dregq(x));
end generate;
aregqin <= tpr.addr(34 downto ADDBITS) &
tnr.addrlo(ADDBITS-1 downto 2) &
tpr.addr(1 downto 0);
aqgen: for x in 34 downto 0 generate
aq: grnand2 generic map (tech => gatetech) port map (aregqin(x), qual_areg(x), aregq(x));
end generate;
comb : process (rst, ar, tapo, dmao, tpr, tnr, aregq, dregq, rdataq)
variable av : ahbreg_type;
variable tpv : tckpreg_type;
variable tnv : tcknreg_type;
variable vdmai : ahb_dma_in_type;
variable asel, dsel : std_ulogic;
variable vtapi : tap_in_type;
variable write, seq : std_ulogic;
begin
av := ar; tpv := tpr; tnv := tnr;
---------------------------------------------------------------------------
-- TCK side logic
---------------------------------------------------------------------------
if NOCMP then
asel := tapo.asel; dsel := tapo.dsel;
else
if tapo.inst = conv_std_logic_vector(ainst, 8) then asel := '1'; else asel := '0'; end if;
if tapo.inst = conv_std_logic_vector(dinst, 8) then dsel := '1'; else dsel := '0'; end if;
end if;
vtapi.en := asel or dsel;
vtapi.tdo:=tpr.addr(0);
if dsel='1' then
vtapi.tdo:=tpr.datashft(0) and tpr.holdn;
end if;
write := tpr.addr(34); seq := tpr.datashft(32);
-- Sync regs using alternating phases
tnv.done_sync1 := ar.done;
tpv.done_sync := tnr.done_sync1;
-- Data CDC
qual_rdata <= (others => tnr.qual_rdata);
if tnr.qual_rdata='1' then tpv.datashft(32 downto 0) := '1' & (not rdataq); end if;
if tapo.capt='1' then tpv.addr(ADDBITS-1 downto 2) := tnr.addrlo; end if;
-- Track whether we're in the middle of shifting
if tapo.shift='1' then tpv.inshift:='1'; end if;
if tapo.upd='1' then tpv.inshift:='0'; end if;
if tapo.shift='1' then
if asel = '1' and tpr.prun='0' then tpv.addr(34 downto 0) := tapo.tdi & tpr.addr(34 downto 1); end if;
if dsel = '1' and tpr.holdn='1' then tpv.datashft(32 downto 0) := tapo.tdi & tpr.datashft(32 downto 1); end if;
end if;
if tnr.run='0' then tpv.holdn:='1'; end if;
tpv.prun := tnr.run;
if tpr.prun='0' then
tnv.qual_rdata := '0';
if tapo.shift='0' and tapo.upd = '1' then
if asel='1' then tnv.addrlo := tpr.addr(ADDBITS-1 downto 2); end if;
if dsel='1' then tnv.data := tpr.datashft; end if;
if (asel and not write) = '1' then tpv.holdn := '0'; tnv.run := '1'; end if;
if (dsel and (write or (not write and seq))) = '1' then
tnv.run := '1';
if (seq and not write) = '1' then
if tpr.inshift='1' then
tnv.addrlo := tnr.addrlo + 1;
end if;
tpv.holdn := '0';
end if;
end if;
end if;
else
if tpr.done_sync='1' and (tpv.inshift='0' or write='1') then
tnv.run := '0';
if write='0' then
tnv.qual_rdata := '1';
end if;
if (write and tnr.data(32)) = '1' then
tnv.addrlo := tnr.addrlo + 1;
end if;
end if;
end if;
if tapo.reset='1' then
tpv.inshift := '0';
tnv.run := '0';
end if;
---------------------------------------------------------------------------
-- AHB side logic
---------------------------------------------------------------------------
-- Sync regs and CDC transfer
av.run_sync := tnr.run & ar.run_sync(2) & ar.run_sync(1);
qual_dreg <= (others => ar.qual_dreg);
if ar.qual_dreg='1' then av.dreg:=not dregq; end if;
qual_areg <= (others => ar.qual_areg);
if ar.qual_areg='1' then av.areg:=not aregq; end if;
vdmai.address := ar.areg(31 downto 0);
vdmai.wdata := ahbdrivedata(ar.dreg(31 downto 0));
vdmai.start := '0'; vdmai.burst := '0';
vdmai.write := ar.areg(34);
vdmai.busy := '0'; vdmai.irq := '0';
vdmai.size := '0' & ar.areg(33 downto 32);
av.qual_dreg := '0';
av.qual_areg := '0';
vdmai.start := '0';
if ar.dmastart='1' then
if dmao.active='1' then
if dmao.ready='1' then
av.dreg := ahbreadword(dmao.rdata);
if ar.areg(34)='0' then
av.done := '1';
end if;
av.dmastart := '0';
end if;
else
vdmai.start := '1';
if ar.areg(34)='1' and ar.wdone='0' then
av.done := '1';
av.wdone := '1';
end if;
end if;
end if;
if ar.qual_areg='1' then
av.dmastart := '1';
av.wdone := '0';
end if;
if ar.run_sync(0)='1' and ar.qual_areg='0' and ar.dmastart='0' and ar.done='0' then
av.qual_dreg := '1';
av.qual_areg := '1';
end if;
if ar.run_sync(0)='0' and ar.done='1' then
av.done := '0';
end if;
if (rst = '0') then
av.qual_dreg := '0';
av.qual_areg := '0';
av.done := '0';
av.areg := (others => '0');
av.dreg := (others => '0');
av.dmastart := '0';
av.run_sync := (others => '0');
end if;
tprin <= tpv; tnrin <= tnv; arin <= av; dmai <= vdmai; tapi <= vtapi;
end process;
ahbreg : process(clk)
begin
if rising_edge(clk) then ar <= arin; end if;
end process;
tckpreg: process(tckp,trst)
begin
if rising_edge(tckp) then
tpr <= tprin;
end if;
if trst='0' then
tpr.done_sync <= '0';
tpr.prun <= '0';
tpr.inshift <= '0';
tpr.holdn <= '1';
tpr.datashft(0) <= '0';
end if;
end process;
tcknreg: process(tckn,trst)
begin
if rising_edge(tckn) then
tnr <= tnrin;
end if;
if trst='0' then
tnr.run <= '0';
tnr.done_sync1 <= '0';
tnr.qual_rdata <= '0';
end if;
end process;
end;
|
gpl-2.0
|
4e7d5a60a023d7e5eb0f9ee55facf4f1
| 0.563573 | 3.406018 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/ddr/ahb2avl_async.vhd
| 1 | 5,840 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2avl_async
-- File: ahb2avl_async.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Asynchronous AHB to Avalon-MM interface based on ddr2spa
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ahb2avl_async is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
avldbits : integer := 32;
avlabits : integer := 20
);
port (
rst_ahb : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
rst_avl : in std_ulogic;
clk_avl : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type
);
end;
architecture struct of ahb2avl_async is
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(avldbits);
constant l2ahbw: integer := log2(ahbbits);
-- Write buffer dimensions
constant wbuf_rabits_s: integer := 1+l2blen-l2ddrw;
constant wbuf_rabits_r: integer := wbuf_rabits_s;
constant wbuf_rdbits: integer := avldbits;
constant wbuf_wabits: integer := 1+l2blen-5;
constant wbuf_wdbits: integer := ahbbits;
-- Read buffer dimensions
constant rbuf_rabits: integer := l2blen-l2ahbw;
constant rbuf_rdbits: integer := wbuf_wdbits;
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := avldbits;
signal request : ddr_request_type;
signal start_tog : std_ulogic;
signal response : ddr_response_type;
signal wbwaddr: std_logic_vector(wbuf_wabits-1 downto 0);
signal wbwdata: std_logic_vector(wbuf_wdbits-1 downto 0);
signal wbraddr: std_logic_vector(wbuf_rabits_s-1 downto 0);
signal wbrdata: std_logic_vector(wbuf_rdbits-1 downto 0);
signal rbwaddr: std_logic_vector(rbuf_wabits-1 downto 0);
signal rbwdata: std_logic_vector(rbuf_wdbits-1 downto 0);
signal rbraddr: std_logic_vector(rbuf_rabits-1 downto 0);
signal rbrdata: std_logic_vector(rbuf_rdbits-1 downto 0);
signal wbwrite,wbwritebig,rbwrite: std_ulogic;
signal gnd: std_logic_vector(3 downto 0);
signal vcc: std_ulogic;
begin
gnd <= (others => '0');
vcc <= '1';
fe0: ddr2spax_ahb
generic map (
hindex => hindex,
haddr => haddr,
hmask => hmask,
ioaddr => 0,
iomask => 0,
burstlen => burstlen,
nosync => nosync,
ahbbits => ahbbits,
devid => GAISLER_AHB2AVLA,
ddrbits => avldbits/2
)
port map (
rst => rst_ahb,
clk_ahb => clk_ahb,
ahbsi => ahbsi,
ahbso => ahbso,
request => request,
start_tog => start_tog,
response => response,
wbwaddr => wbwaddr,
wbwdata => wbwdata,
wbwrite => wbwrite,
wbwritebig => wbwritebig,
rbraddr => rbraddr,
rbrdata => rbrdata,
hwidth => gnd(0),
beid => gnd(3 downto 0)
);
be0: ahb2avl_async_be
generic map (
avldbits => avldbits,
avlabits => avlabits,
ahbbits => ahbbits,
burstlen => burstlen,
nosync => nosync
)
port map (
rst => rst_avl,
clk => clk_avl,
avlsi => avlsi,
avlso => avlso,
request => request,
start_tog => start_tog,
response => response,
wbraddr => wbraddr,
wbrdata => wbrdata,
rbwaddr => rbwaddr,
rbwdata => rbwdata,
rbwrite => rbwrite
);
wbuf: ddr2buf
generic map (tech => 0, wabits => wbuf_wabits, wdbits => wbuf_wdbits,
rabits => wbuf_rabits_r, rdbits => wbuf_rdbits,
sepclk => 1, wrfst => 0, testen => 0)
port map ( rclk => clk_avl, renable => vcc, raddress => wbraddr(wbuf_rabits_r-1 downto 0),
dataout => wbrdata, wclk => clk_ahb, write => wbwrite,
writebig => wbwritebig, waddress => wbwaddr, datain => wbwdata,
testin => ahbsi.testin);
rbuf: ddr2buf
generic map (tech => 0, wabits => rbuf_wabits, wdbits => rbuf_wdbits,
rabits => rbuf_rabits, rdbits => rbuf_rdbits,
sepclk => 1, wrfst => 0, testen => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rbraddr,
dataout => rbrdata,
wclk => clk_avl, write => rbwrite,
writebig => '0', waddress => rbwaddr, datain => rbwdata,
testin => ahbsi.testin);
end;
|
gpl-2.0
|
85f900afea59687fce7c3fd53122c622
| 0.592808 | 3.937964 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/inferred/lpddr2_phy_inferred.vhd
| 1 | 10,244 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: generic_lpddr2phy_wo_pads
-- File: lpddr2_phy_inferred.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Generic LPDDR2/LPDDR3 PHY (simulation only), without pads
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity clkswitch is
port (clk1,clk2,sel: in std_ulogic;
clko: out std_ulogic);
end;
architecture sim of clkswitch is
signal c1en,c2en: std_ulogic := '0';
begin
clko <= (clk1 and c1en) or (clk2 and c2en);
p1: process(clk1)
begin
if falling_edge(clk1) then
c1en <= (not sel) and (not c2en);
end if;
end process;
p2: process(clk2)
begin
if falling_edge(clk2) then
c2en <= (sel) and (not c1en);
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity generic_lpddr2phy_wo_pads is
generic (
tech : integer := 0;
dbits : integer := 16;
nclk: integer := 3;
ncs: integer := 2;
clkratio: integer := 1;
scantest: integer := 0;
oepol: integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2 : in std_ulogic;
clkout : out std_ulogic;
clkoutret : in std_ulogic; -- clkout returned
clkout2 : out std_ulogic;
lock : out std_ulogic;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0);
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ca : in std_logic_vector (10*2*clkratio-1 downto 0);
cke : in std_logic_vector (ncs*clkratio-1 downto 0);
csn : in std_logic_vector (ncs*clkratio-1 downto 0);
dqin : out std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4*clkratio-1 downto 0); -- data mask
ckstop : in std_ulogic;
boot : in std_ulogic;
wrpend : in std_logic_vector(7 downto 0);
rdpend : in std_logic_vector(7 downto 0);
wrreq : out std_logic_vector(clkratio-1 downto 0);
rdvalid : out std_logic_vector(clkratio-1 downto 0);
refcal : in std_ulogic;
refcalwu : in std_ulogic;
refcaldone : out std_ulogic;
phycmd : in std_logic_vector(7 downto 0);
phycmden : in std_ulogic;
phycmdin : in std_logic_vector(31 downto 0);
phycmdout : out std_logic_vector(31 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture beh of generic_lpddr2phy_wo_pads is
component sim_pll
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
signal extclkb,extclkn,extclk,intclkb,intclkn,intclk: std_ulogic;
signal gextclk,gextclkn: std_ulogic;
signal clkoutb,clkoutn: std_ulogic;
signal llockb,llockn,llock: std_ulogic;
signal dqsout,dqsoen,dqsand,dqoen,dqsien,dqsiend: std_ulogic;
signal dqsin,dqsind: std_logic_vector(dbits/8-1 downto 0);
signal tmeas: time := 0 ns;
signal tdqsck: time := 0 ns;
begin
bootpll: sim_pll
generic map (clkmul => clkratio,
clkdiv1 => 1, clkphase1 => 180,
clkdiv2 => 1, clkphase2 => 90,
clkdiv3 => clkratio, clkphase3 => 0)
port map (i => clkin2, o1 => extclkb, o2 => intclkb,
o3 => clkoutb, lock => llockb, rst => rst);
pll0: sim_pll
generic map (clkmul => clkratio,
clkdiv1 => 1, clkphase1 => 180,
clkdiv2 => 1, clkphase2 => 90,
clkdiv3 => clkratio, clkphase3 => 0)
port map (i => clkin, o1 => extclkn, o2 => intclkn,
o3 => clkoutn, lock => llockn, rst => rst);
llock <= llockb and llockn;
lock <= llock;
clkout2 <= '0';
cs0: entity work.clkswitch port map (extclkn, extclkb, boot, extclk);
cs1: entity work.clkswitch port map (intclkn, intclkb, boot, intclk);
cs2: entity work.clkswitch port map (clkoutn, clkoutb, boot, clkout);
gextclk <= extclk and (llock and not ckstop);
gextclkn <= not gextclk;
dqsout <= gextclk and dqsand;
ddr_dqs_out <= (others => dqsout);
ddr_dqs_oen <= (others => dqsoen);
ddr_dqs_oen <= (others => dqsoen or (not rst) or (not llock)) when oepol=0 else
(others => (not dqsoen) and rst and llock);
ddr_dq_oen <= (others => dqoen or (not rst) or (not llock)) when oepol=0 else
(others => (not dqoen) and rst and llock);
ddr_clk <= (others => gextclk);
ddr_clkb <= (others => gextclkn);
dqsiend <= dqsien after tdqsck;
dqsin <= ddr_dqs_in when dqsiend='1' else (others => '0');
dqsind <= dqsin after tmeas * 0.25;
wrreq <= wrpend(1+clkratio-1-1 downto 1-1);
outregs: process(clkoutret,intclk,dqsind)
variable phase: integer;
variable wrpend_samp: std_logic_vector(1 downto 0);
variable rdpend_prev: std_ulogic;
type intarr is array(natural range <>) of integer;
variable dl: intarr(dbits/8-1 downto 0) := (others => 0);
variable dqq: std_logic_vector(3*dbits*2-1 downto 0);
variable lt: time := 0 ns;
variable dqsind_prev: std_logic_vector(dbits/8-1 downto 0) := (others => '0');
variable i: integer;
begin
if dqsind /= dqsind_prev then
for x in dqsind'range loop
if (dqsind(x)='1' and dqsind_prev(x)='0') or (dqsind(x)='0' and dqsind_prev(x)='1') then
for y in 5 downto 1 loop
dqq(x*8+dbits*y+7 downto x*8+dbits*y) := dqq(x*8+dbits*(y-1)+7 downto x*8+dbits*(y-1));
end loop;
dqq(x*8+7 downto x*8) := ddr_dq_in(x*8+7 downto x*8);
if dqsind(x)='0' then
dl(x) := dl(x)+1;
end if;
end if;
end loop;
dqsind_prev := dqsind;
end if;
if rising_edge(clkoutret) then
dqsien <= rdpend(1);
phase := 0;
wrpend_samp := wrpend(1 downto 0);
rdvalid <= (others => '0');
dqin <= (others => '-');
i := clkratio;
for x in dl'range loop
if dl(x)<i then i:=dl(x); end if;
end loop;
for x in dl'range loop
dl(x) := dl(x)-i;
end loop;
for x in 2*i-1 downto 0 loop
for y in dbits/8-1 downto 0 loop
dqin(x*dbits+y*8+7 downto x*dbits+y*8) <= dqq((x+dl(y))*dbits+y*8+7 downto (x+dl(y))*dbits+y*8);
end loop;
end loop;
rdvalid(i-1 downto 0) <= (others => '1');
end if;
if falling_edge(clkoutret) then
dqsoen <= not (wrpend_samp(1) or wrpend_samp(0));
rdpend_prev := rdpend(0);
end if;
if rising_edge(intclk) then
dqsand <= wrpend_samp(0);
dqoen <= not wrpend_samp(0);
tmeas <= now - lt;
lt := now;
end if;
if rising_edge(intclk) or falling_edge(intclk) then
-- DDR outputs
ddr_ca <= ca(ca'high-10*phase downto ca'high-10*phase-9);
ddr_dm <= dm(dm'high-dbits/8*phase downto dm'high+1-dbits/8*(phase+1));
ddr_dq_out <= dqout(dqout'high-dbits*phase downto dqout'high+1-dbits*(phase+1));
if rising_edge(intclk) then
-- SDR outputs
ddr_cke <= cke(cke'high-ncs*(phase/2) downto cke'high+1-ncs*(phase/2+1));
ddr_csb <= csn(csn'high-ncs*(phase/2) downto csn'high+1-ncs*(phase/2+1));
end if;
if phase < 2*clkratio-1 then
phase := phase+1;
end if;
end if;
end process;
dqsckproc: process
variable t: time;
begin
wait until dqsien='1';
loop
t := now;
if dqsin/=(dqsin'range => '0') then
wait until dqsin=(dqsin'range => '0');
end if;
wait until dqsin=(dqsin'range => '1');
tdqsck <= tdqsck + (now-t)-0.25*tmeas;
wait until dqsin=(dqsin'range => 'X') and dqsien='1';
end loop;
end process;
end;
|
gpl-2.0
|
69103d27de574bedccd294451aeb1be8
| 0.571652 | 3.375288 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep3c25-eek/config.vhd
| 1 | 7,025 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 1;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 1;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0039#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000011#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (32);
constant CFG_DDRSP_RSKEW : integer := (2500);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 64;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0#;
constant CFG_GRGPIO_WIDTH : integer := (5);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- PS/2 interface
constant CFG_PS2_ENABLE : integer := 1;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- LCD SVGA controller
constant CFG_LCD_ENABLE : integer := 1;
-- LCD 3-wire serial interface
constant CFG_LCD3T_ENABLE : integer := 1;
-- SVGA controller
constant CFG_SVGA_ENABLE : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
e4eed0ca3291c9fff0975182d5423637
| 0.647972 | 3.611825 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/misc/gracectrl.vhd
| 1 | 14,063 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: gracectrl
-- File: gracectrl.vhd
-- Author: Jan Andersson - Gaisler Research AB
-- Contact: [email protected]
-- Description: Provides a GRLIB AMBA AHB slave interface to Xilinx System ACE
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, gaisler;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use gaisler.misc.all;
entity gracectrl is
generic (
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
haddr : integer := 16#000#; -- Base address
hmask : integer := 16#fff#; -- Area mask
split : integer range 0 to 1 := 0; -- Enable AMBA SPLIT support
swap : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0; -- Output enable polarity
mode : integer range 0 to 2 := 0 -- 0: 16-bit mode only
-- 1: 8-bit mode only
-- 2: 8-bit, emulate 16-bit
);
port (
rstn : in std_ulogic;
clk : in std_ulogic; -- System (AMBA) clock
clkace : in std_ulogic; -- System ACE clock
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
acei : in gracectrl_in_type;
aceo : out gracectrl_out_type
);
end gracectrl;
architecture rtl of gracectrl is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant REVISION : amba_version_type := 0;
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_GRACECTRL, 0, REVISION, hirq),
-- 1 => conv_std_logic_vector(swap*4 + mode, 32),
4 => ahb_iobar(haddr, hmask), others => zero32);
constant OUTPUT : std_ulogic := conv_std_logic(oepol = 1);
constant INPUT : std_ulogic := not conv_std_logic(oepol = 1);
constant ACEDW : integer := 16-8*(mode mod 2);
-----------------------------------------------------------------------------
-- Functions
-----------------------------------------------------------------------------
-- purpose: swaps a hword if 'swap' is non-zero and mode is zero,
-- otherwise just propagate data
function condhswap (d : std_logic_vector)
return std_logic_vector is
variable dx : std_logic_vector(15 downto 0);
begin -- hswap
dx(ACEDW-1 downto 0) := d;
if swap /= 0 and mode = 0 then
return dx(7 downto 0) & dx(15 downto 8);
end if;
return dx;
end condhswap;
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type sys_sync_type is record
accdone : std_logic_vector(1 downto 0);
irq : std_logic_vector(2 downto 0);
end record;
type sys_reg_type is record
acc : std_ulogic; -- Perform access
active : std_ulogic; -- Access active
sync : sys_sync_type;
-- AHB
insplit : std_ulogic; -- SPLIT response issued
unsplit : std_ulogic; -- SPLIT complete not issued
irq : std_ulogic; -- Interrupt request
hwrite : std_ulogic;
hsel : std_ulogic;
hmbsel : std_logic_vector(0 to 1);
haddr : std_logic_vector(6 downto 0);
hready : std_ulogic;
wdata : std_logic_vector(ACEDW-1 downto 0);
hresp : std_logic_vector(1 downto 0);
splmst : std_logic_vector(log2(NAHBMST)-1 downto 0); -- SPLIT:ed master
hsplit : std_logic_vector(NAHBMST-1 downto 0); -- Other SPLIT:ed masters
ahbcancel : std_ulogic; -- Locked access cancels ongoing SPLIT
-- response
end record;
type ace_state_type is (idle, en, rd, done);
type ace_sync_type is record
acc : std_logic_vector(1 downto 0);
rstn : std_logic_vector(1 downto 0);
hwrite : std_logic_vector(1 downto 0);
dummy : std_logic_vector(1 downto 0);
end record;
type ace_reg_type is record
state : ace_state_type;
sync : ace_sync_type;
accdone : std_ulogic;
rdata : std_logic_vector(ACEDW-1 downto 0);
edone : std_ulogic;
aceo : gracectrl_out_type;
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal r, rin : sys_reg_type;
signal s, sin : ace_reg_type;
begin -- rtl
-----------------------------------------------------------------------------
-- System clock domain
-----------------------------------------------------------------------------
combsys: process (r, s, rstn, ahbsi, acei.irq)
variable v : sys_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable hsplit : std_logic_vector(NAHBMST-1 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
begin -- process comb
v := r; v.irq := '0'; irq := (others => '0'); irq(hirq) := r.irq;
v.hresp := HRESP_OKAY; v.hready := '1'; hsplit := (others => '0');
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
-- Sync
v.sync.accdone := r.sync.accdone(0) & s.accdone;
v.sync.irq := r.sync.irq(1 downto 0) & acei.irq;
-- AHB communication
if ahbsi.hready = '1' then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hmbsel := ahbsi.hmbsel(r.hmbsel'range);
if split = 0 or (not (r.active or r.acc) or ahbsi.hmastlock) = '1' then
v.hready := '0';
v.hwrite := ahbsi.hwrite;
v.haddr := ahbsi.haddr(6 downto 0);
v.hsel := '1';
if r.insplit = '0' then
v.acc := '1';
end if;
if split /= 0 then
if ahbsi.hmastlock = '0' then
v.hresp := HRESP_SPLIT;
v.splmst := ahbsi.hmaster;
v.unsplit := '1';
else
v.ahbcancel := r.insplit;
end if;
v.insplit := not ahbsi.hmastlock;
end if;
else
-- Core is busy, transfer is not locked respond with SPLIT
v.hready := '0';
if split /= 0 then
v.hresp := HRESP_SPLIT;
v.hsplit(conv_integer(ahbsi.hmaster)) := '1';
end if;
end if;
else
v.hsel := '0';
end if;
end if;
if (r.hready = '0') then
if (r.hresp = HRESP_OKAY) then v.hready := '0';
else v.hresp := r.hresp; end if;
end if;
if r.acc = '1' then
-- Propagate data
if r.active = '0' then
if mode /= 1 then
if r.haddr(1) = '0' then v.wdata := hwdata(ACEDW+15 downto 16);
else v.wdata := hwdata(ACEDW-1 downto 0); end if;
else
case r.haddr(1 downto 0) is
when "00" => v.wdata(7 downto 0) := hwdata(31 downto 24);
when "01" => v.wdata(7 downto 0) := hwdata(23 downto 16);
when "10" => v.wdata(7 downto 0) := hwdata(15 downto 8);
when others => v.wdata(7 downto 0) := hwdata(7 downto 0);
end case;
end if;
if mode = 2 then
-- Override writes to busmode register
if r.haddr(6 downto 1) = zero32(6 downto 1) then
v.wdata := (others => '0'); -- Byte
end if;
end if;
end if;
-- Remove access signal when access is done
if r.sync.accdone(1) = '1' then
v.acc := '0';
end if;
v.active := '1';
end if;
-- AMBA response when access is complete
if r.acc = '0' and r.sync.accdone(1) = '0' and r.active = '1' then
if split /= 0 and r.unsplit = '1' then
hsplit(conv_integer(r.splmst)) := '1';
v.unsplit := '0';
end if;
if ((split = 0 or v.ahbcancel = '0') and
(split = 0 or ahbsi.hmaster = r.splmst or r.insplit = '0') and
(((ahbsi.hsel(hindex) and ahbsi.hready and ahbsi.htrans(1)) = '1') or
((split = 0 or r.insplit = '0') and r.hready = '0' and r.hresp = HRESP_OKAY))) then
v.hresp := HRESP_OKAY;
if split /= 0 then
v.insplit := '0';
v.hsplit := r.hsplit;
end if;
v.hready := '1';
v.hsel := '0';
v.active := '0';
elsif split /= 0 and v.ahbcancel = '1' then
v.acc := '1';
v.ahbcancel := '0';
end if;
end if;
-- Interrupt request, not filtered, pulsed
if (not r.sync.irq(2) and r.sync.irq(1)) = '1' then
v.irq := '1';
end if;
-- Reset
if rstn = '0' then
v.acc := '0';
v.active := '0';
--
v.insplit := '0';
v.unsplit := '0';
v.hready := '1';
v.hwrite := '0';
v.hsel := '0';
v.hmbsel := (others => '0');
v.ahbcancel := '0';
end if;
if split = 0 then
v.insplit := '0';
v.unsplit := '0';
v.splmst := (others => '0');
v.hsplit := (others => '0');
v.ahbcancel := '0';
end if;
-- Update registers
rin <= v;
-- AHB slave output
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(s.rdata); -- Bad, but does not toggle much
ahbso.hconfig <= HCONFIG;
ahbso.hirq <= irq;
ahbso.hindex <= hindex;
ahbso.hsplit <= hsplit;
end process combsys;
regsys: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process regsys;
-----------------------------------------------------------------------------
-- System ACE clock domain
-----------------------------------------------------------------------------
combace: process (r, s, rstn, acei)
variable v : ace_reg_type;
begin -- process comb
v := s;
-- Synchronize inputs
v.sync.acc := s.sync.acc(0) & r.acc;
v.sync.rstn := s.sync.rstn(0) & rstn;
v.sync.hwrite := s.sync.hwrite(0) & r.hwrite;
if mode = 2 then
-- Fake reads from BUSMODE register?
v.sync.dummy := s.sync.dummy(0) & not orv(r.haddr(6 downto 1));
else
v.sync.dummy := (others => '0');
end if;
case s.state is
when idle =>
v.aceo.addr := r.haddr(6 downto 0);
if mode = 2 then v.aceo.do(7 downto 0) := r.wdata(7 downto 0);
else v.aceo.do(r.wdata'range) := condhswap(r.wdata); end if;
if s.sync.acc(1) = '1' then
v.aceo.cen := '0';
v.aceo.doen := INPUT xor r.hwrite;
v.state := en;
end if;
if mode = 2 then v.edone := '0'; end if;
when en =>
v.aceo.wen := not r.hwrite;
if s.sync.hwrite(1) = '1' then
v.state := done;
else
v.state := rd;
end if;
when rd =>
v.aceo.oen := '0';
v.state := done;
when done =>
v.aceo.oen := '1';
v.aceo.wen := '1';
if mode = 2 and s.edone = '0' then
-- Keep 16-bit address map
v.aceo.addr(0) := '1';
v.aceo.do(7 downto 0) := r.wdata(ACEDW-1 downto ACEDW-8);
v.rdata(7 downto 0) := acei.di(7 downto 0);
v.edone := '1';
v.state := en;
else
v.aceo.cen := '1';
if s.accdone = '0' then
if mode = 2 then
v.rdata(ACEDW-1 downto ACEDW-8) := acei.di(7 downto 0);
if s.sync.dummy(1) = '1' then -- Fake read
v.rdata := (others => '0'); v.rdata(0) := '1';
end if;
else
v.rdata := condhswap(acei.di)(s.rdata'range);
end if;
v.accdone := '1';
else
v.aceo.doen := INPUT;
end if;
if s.sync.acc(1) = '0' then
v.state := idle;
v.accdone := '0';
end if;
end if;
end case;
-- Reset
if s.sync.rstn(1) = '0' then
v.state := idle;
v.accdone := '0';
v.aceo.cen := '1';
v.aceo.wen := '1';
v.aceo.oen := '1';
v.aceo.doen := INPUT;
end if;
if mode = 1 then v.aceo.do(15 downto 8) := (others => '0'); end if;
if mode /= 2 then v.edone := '0'; end if;
-- Update registers
sin <= v;
-- Assign outputs to System ACE
aceo <= s.aceo;
end process combace;
regace: process (clkace)
begin -- process reg
if rising_edge(clkace) then
s <= sin;
end if;
end process regace;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"gracectrl" & tost(hindex) & ": System ACE I/F Controller, rev " &
tost(REVISION) & ", irq " & tost(hirq));
-- pragma translate_on
end rtl;
|
gpl-2.0
|
8fd94014d5459aacecaab2ffd4068bf6
| 0.485458 | 3.76016 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-ztex-ufm-115/ahb2mig_ztex.vhd
| 1 | 15,838 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_ztex
-- File: ahb2mig_ztex.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Spartan-6 MIG.
-- One bidir 32-bit port is used for the main AHB bus.
-------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <[email protected]>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2mig_ztex is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
MEMCLK_PERIOD : integer := 5000
);
port(
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
test_error : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
clk_mem : in std_logic
);
end ;
architecture rtl of ahb2mig_ztex is
component mig_37
generic(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 3
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic
);
end component;
type bstate_type is (idle, start, read1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
end record;
type mcb_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
cmd_bl : std_logic_vector(5 downto 0);
cmd_byte_addr : std_logic_vector(29 downto 0);
wr_full : std_logic;
wr_empty : std_logic;
wr_underrun : std_logic;
wr_error : std_logic;
wr_mask : std_logic_vector(3 downto 0);
wr_en : std_logic;
wr_data : std_logic_vector(31 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
rd_en : std_logic;
end record;
signal r, rin : reg_type;
signal i : mcb_type;
begin
comb: process( rst_n_syn, r, ahbsi, i )
variable v : reg_type;
variable wmask : std_logic_vector(3 downto 0);
variable wr_en : std_logic;
variable cmd_en : std_logic;
variable cmd_instr : std_logic_vector(2 downto 0);
variable rd_en : std_logic;
variable cmd_bl : std_logic_vector(5 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
begin
v := r; wr_en := '0'; cmd_en := '0'; cmd_instr := "000";
rd_en := '0';
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
if ahbsi.htrans(0) = '0' then v.haddr := ahbsi.haddr; end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
hwdata := ahbsi.hwdata(15 downto 0) & ahbsi.hwdata(31 downto 16);
case r.hsize(1 downto 0) is
when "00" => wmask := not decode(r.haddr(1 downto 0));
case r.haddr(1 downto 0) is
when "00" => wmask := "1101";
when "01" => wmask := "1110";
when "10" => wmask := "0111";
when others => wmask := "1011";
end case;
when "01" => wmask := not decode(r.haddr(1 downto 0));
wmask(3) := wmask(2); wmask(1) := wmask(0);
when others => wmask := "0000";
end case;
i.wr_mask <= wmask;
cmd_bl := r.cmd_bl;
case r.bstate is
when idle =>
if v.hsel = '1' then
v.bstate := start;
v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.haddr := ahbsi.haddr;
end if;
v.cmd_bl := (others => '0');
when start =>
if r.hwrite = '1' then
v.haddr := r.haddr;
if r.hready = '1' then
v.cmd_bl := r.cmd_bl + 1; v.hready := '1'; wr_en := '1';
if (ahbsi.htrans /= "11") then
if v.hsel = '1' then
if (ahbsi.hwrite = '0') or (i.wr_count >= "0000100") then
v.hready := '0';
else v.hready := '1'; end if;
else v.bstate := idle; end if;
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
cmd_en := '1';
elsif (i.cmd_full = '1') then
v.hready := '0';
elsif (i.wr_count >= "0101111") then
v.hready := '0'; cmd_en := '1';
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
end if;
else
if (i.cmd_full = '0') and (i.wr_count <= "0001111") then
v.hready := '1';
end if;
end if;
else
if i.cmd_full = '0' then
cmd_en := '1'; cmd_instr(0) := '1';
v.cmd_bl := "000" & not r.haddr(4 downto 2);
cmd_bl := v.cmd_bl;
v.bstate := read1;
end if;
end if;
when read1 =>
v.hready := '0';
if (r.rd_cnt = "000000") then -- flush data from previous line
if (i.rd_empty = '0') or ((r.hready = '1') and (ahbsi.htrans /= "11")) then
v.hrdata(31 downto 0) := i.rd_data(15 downto 0) & i.rd_data(31 downto 16);
v.hready := '1';
if (i.rd_empty = '0') then v.cmd_bl := r.cmd_bl - 1; rd_en := '1'; end if;
if (r.cmd_bl = "000000") or (ahbsi.htrans /= "11") then
if (ahbsi.hsel(hindex) = '1') and (ahbsi.htrans = "10") and (r.hready = '1') then
v.bstate := start; v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.cmd_bl := (others => '0');
else
v.bstate := idle;
end if;
if (i.rd_empty = '1') then v.rd_cnt := r.cmd_bl + 1;
else v.rd_cnt := r.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
readdata := (others => '0');
-- case apbi.paddr(5 downto 2) is
-- when "0000" => readdata(nbits-1 downto 0) := r.din2;
-- when "0001" => readdata(nbits-1 downto 0) := r.dout;
-- when others =>
-- end case;
readdata(20 downto 0) :=
i.rd_error & i.rd_overflow & i.wr_error & i.wr_underrun &
i.cmd_full & i.rd_full & i.rd_empty & i.wr_full & i.wr_empty &
r.rd_cnt & r.cmd_bl;
if (r.rd_cnt /= "000000") and (i.rd_empty = '0') then
rd_en := '1'; v.rd_cnt := r.rd_cnt - 1;
end if;
if rst_n_syn = '0' then
v.rd_cnt := "000000"; v.bstate := idle; v.hready := '1';
end if;
rin <= v;
apbo.prdata <= readdata;
i.rd_en <= rd_en;
i.wr_en <= wr_en;
i.cmd_bl <= cmd_bl;
i.cmd_en <= cmd_en;
i.cmd_instr <= cmd_instr;
i.wr_data <= hwdata;
end process;
i.cmd_byte_addr <= r.haddr(29 downto 2) & "00";
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r <= rin;
end if;
end process;
MCB_inst : entity work.mig_37 generic map(
C3_RST_ACT_LOW => 1,
-- pragma translate_off
C3_SIMULATION => "TRUE",
-- pragma translate_on
C3_MEM_ADDR_ORDER => "BANK_ROW_COLUMN",
C3_MEMCLK_PERIOD => MEMCLK_PERIOD
)
port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
c3_sys_clk => clk_mem,
c3_sys_rst_n => rst_n_async,
c3_calib_done => calib_done,
c3_clk0 => open,
c3_rst0 => open,
c3_p0_cmd_clk => clk_amba,
c3_p0_cmd_en => i.cmd_en,
c3_p0_cmd_instr => i.cmd_instr,
c3_p0_cmd_bl => i.cmd_bl,
c3_p0_cmd_byte_addr => i.cmd_byte_addr,
c3_p0_cmd_empty => i.cmd_empty,
c3_p0_cmd_full => i.cmd_full,
c3_p0_wr_clk => clk_amba,
c3_p0_wr_en => i.wr_en,
c3_p0_wr_mask => i.wr_mask,
c3_p0_wr_data => i.wr_data,
c3_p0_wr_full => i.wr_full,
c3_p0_wr_empty => i.wr_empty,
c3_p0_wr_count => i.wr_count,
c3_p0_wr_underrun => i.wr_underrun,
c3_p0_wr_error => i.wr_error,
c3_p0_rd_clk => clk_amba,
c3_p0_rd_en => i.rd_en,
c3_p0_rd_data => i.rd_data,
c3_p0_rd_full => i.rd_full,
c3_p0_rd_empty => i.rd_empty,
c3_p0_rd_count => i.rd_count,
c3_p0_rd_overflow => i.rd_overflow,
c3_p0_rd_error => i.rd_error
);
end;
|
gpl-2.0
|
e55d2bc7066d979d8d4fa855b0bfc365
| 0.506756 | 3.052814 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/leon3_net.vhd
| 1 | 83,829 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use work.gencomp.all;
entity leon3_net is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
clk2x : integer := 1;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
-- ahbso : in ahb_slv_out_vector;
irqi_irl : in std_logic_vector(3 downto 0);
irqi_rst : in std_ulogic;
irqi_run : in std_ulogic;
irqi_rstvec : in std_logic_vector(31 downto 12);
irqi_iact : in std_ulogic;
irqi_index : in std_logic_vector(3 downto 0);
irqi_hrdrst : in std_ulogic;
irqo_intack : out std_ulogic;
irqo_irl : out std_logic_vector(3 downto 0);
irqo_pwd : out std_ulogic;
irqo_fpen : out std_ulogic;
irqo_idle : out std_ulogic;
dbgi_dsuen : in std_ulogic; -- DSU enable
dbgi_denable : in std_ulogic; -- diagnostic register access enablee
dbgi_dbreak : in std_ulogic; -- debug break-in
dbgi_step : in std_ulogic; -- single step
dbgi_halt : in std_ulogic; -- halt processor
dbgi_reset : in std_ulogic; -- reset processor
dbgi_dwrite : in std_ulogic; -- read/write
dbgi_daddr : in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata : in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa : in std_ulogic; -- break on IU trap
dbgi_btrape : in std_ulogic; -- break on IU trap
dbgi_berror : in std_ulogic; -- break on IU error mode
dbgi_bwatch : in std_ulogic; -- break on IU watchpoint
dbgi_bsoft : in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable : in std_ulogic;
dbgi_timer : in std_logic_vector(30 downto 0);
dbgo_data : out std_logic_vector(31 downto 0);
dbgo_crdy : out std_ulogic;
dbgo_dsu : out std_ulogic;
dbgo_dsumode : out std_ulogic;
dbgo_error : out std_ulogic;
dbgo_halt : out std_ulogic;
dbgo_pwd : out std_ulogic;
dbgo_idle : out std_ulogic;
dbgo_ipend : out std_ulogic;
dbgo_icnt : out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss : out std_ulogic;
dbgo_istat_tmiss : out std_ulogic;
dbgo_istat_chold : out std_ulogic;
dbgo_istat_mhold : out std_ulogic;
dbgo_dstat_cmiss : out std_ulogic;
dbgo_dstat_tmiss : out std_ulogic;
dbgo_dstat_chold : out std_ulogic;
dbgo_dstat_mhold : out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic;
-- fpui : out grfpu_in_type;
-- fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end ;
architecture rtl of leon3_net is
signal disasen : std_ulogic;
component leon3ft_unisim
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 1 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 1 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port(
clk : in std_logic;
rstn : in std_logic;
ahbi_hgrant : in std_logic_vector (0 to 15);
ahbi_hready : in std_logic;
ahbi_hresp : in std_logic_vector (1 downto 0);
ahbi_hrdata : in std_logic_vector (31 downto 0);
ahbi_hirq : in std_logic_vector (31 downto 0);
ahbo_hbusreq : out std_logic;
ahbo_hlock : out std_logic;
ahbo_htrans : out std_logic_vector (1 downto 0);
ahbo_haddr : out std_logic_vector (31 downto 0);
ahbo_hwrite : out std_logic;
ahbo_hsize : out std_logic_vector (2 downto 0);
ahbo_hburst : out std_logic_vector (2 downto 0);
ahbo_hprot : out std_logic_vector (3 downto 0);
ahbo_hwdata : out std_logic_vector (31 downto 0);
ahbo_hirq : out std_logic_vector (31 downto 0);
ahbsi_hsel : in std_logic_vector (0 to 15);
ahbsi_haddr : in std_logic_vector (31 downto 0);
ahbsi_hwrite : in std_logic;
ahbsi_htrans : in std_logic_vector (1 downto 0);
ahbsi_hsize : in std_logic_vector (2 downto 0);
ahbsi_hburst : in std_logic_vector (2 downto 0);
ahbsi_hwdata : in std_logic_vector (31 downto 0);
ahbsi_hprot : in std_logic_vector (3 downto 0);
ahbsi_hready : in std_logic;
ahbsi_hmaster : in std_logic_vector (3 downto 0);
ahbsi_hmastlock : in std_logic;
ahbsi_hmbsel : in std_logic_vector (0 to 3);
ahbsi_hirq : in std_logic_vector (31 downto 0);
irqi_irl : in std_logic_vector (3 downto 0);
irqi_rst : in std_logic;
irqi_run : in std_logic;
irqo_intack : out std_logic;
irqo_irl : out std_logic_vector (3 downto 0);
irqo_pwd : out std_logic;
dbgi_dsuen : in std_logic;
dbgi_denable : in std_logic;
dbgi_dbreak : in std_logic;
dbgi_step : in std_logic;
dbgi_halt : in std_logic;
dbgi_reset : in std_logic;
dbgi_dwrite : in std_logic;
dbgi_daddr : in std_logic_vector (23 downto 2);
dbgi_ddata : in std_logic_vector (31 downto 0);
dbgi_btrapa : in std_logic;
dbgi_btrape : in std_logic;
dbgi_berror : in std_logic;
dbgi_bwatch : in std_logic;
dbgi_bsoft : in std_logic;
dbgi_tenable : in std_logic;
dbgi_timer : in std_logic_vector (30 downto 0);
dbgo_data : out std_logic_vector (31 downto 0);
dbgo_crdy : out std_logic;
dbgo_dsu : out std_logic;
dbgo_dsumode : out std_logic;
dbgo_error : out std_logic;
dbgo_halt : out std_logic;
dbgo_pwd : out std_logic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
disasen : in std_logic);
end component;
component leon3ft_axcelerator is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0);
port (
clk: in std_ulogic;
rstn: in std_ulogic;
ahbi_hgrant: in std_logic_vector(0 to NAHBMST-1); -- bus grant
ahbi_hready: in std_ulogic; -- transfer done
ahbi_hresp: in std_logic_vector(1 downto 0); -- response type
ahbi_hrdata: in std_logic_vector(31 downto 0); -- read data bus
ahbi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
ahbo_hbusreq: out std_ulogic; -- bus request
ahbo_hlock: out std_ulogic; -- lock request
ahbo_htrans: out std_logic_vector(1 downto 0); -- transfer type
ahbo_haddr: out std_logic_vector(31 downto 0); -- address bus (byte)
ahbo_hwrite: out std_ulogic; -- read/write
ahbo_hsize: out std_logic_vector(2 downto 0); -- transfer size
ahbo_hburst: out std_logic_vector(2 downto 0); -- burst type
ahbo_hprot: out std_logic_vector(3 downto 0); -- protection control
ahbo_hwdata: out std_logic_vector(31 downto 0); -- write data bus
ahbo_hirq: out std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
ahbsi_hsel: in std_logic_vector(0 to NAHBSLV-1); -- slave select
ahbsi_haddr: in std_logic_vector(31 downto 0); -- address bus (byte)
ahbsi_hwrite: in std_ulogic; -- read/write
ahbsi_htrans: in std_logic_vector(1 downto 0); -- transfer type
ahbsi_hsize: in std_logic_vector(2 downto 0); -- transfer size
ahbsi_hburst: in std_logic_vector(2 downto 0); -- burst type
ahbsi_hwdata: in std_logic_vector(31 downto 0); -- write data bus
ahbsi_hprot: in std_logic_vector(3 downto 0); -- protection control
ahbsi_hready: in std_ulogic; -- transfer done
ahbsi_hmaster: in std_logic_vector(3 downto 0); -- current master
ahbsi_hmastlock: in std_ulogic; -- locked access
ahbsi_hmbsel: in std_logic_vector(0 to NAHBAMR-1); -- memory bank select
ahbsi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_logic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
disasen : in std_logic);
end component;
component leon3ft_proasic3 is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0);
port (
clk: in std_ulogic;
rstn: in std_ulogic;
ahbi_hgrant: in std_logic_vector(0 to NAHBMST-1); -- bus grant
ahbi_hready: in std_ulogic; -- transfer done
ahbi_hresp: in std_logic_vector(1 downto 0); -- response type
ahbi_hrdata: in std_logic_vector(31 downto 0); -- read data bus
ahbi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
ahbo_hbusreq: out std_ulogic; -- bus request
ahbo_hlock: out std_ulogic; -- lock request
ahbo_htrans: out std_logic_vector(1 downto 0); -- transfer type
ahbo_haddr: out std_logic_vector(31 downto 0); -- address bus (byte)
ahbo_hwrite: out std_ulogic; -- read/write
ahbo_hsize: out std_logic_vector(2 downto 0); -- transfer size
ahbo_hburst: out std_logic_vector(2 downto 0); -- burst type
ahbo_hprot: out std_logic_vector(3 downto 0); -- protection control
ahbo_hwdata: out std_logic_vector(31 downto 0); -- write data bus
ahbo_hirq: out std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
ahbsi_hsel: in std_logic_vector(0 to NAHBSLV-1); -- slave select
ahbsi_haddr: in std_logic_vector(31 downto 0); -- address bus (byte)
ahbsi_hwrite: in std_ulogic; -- read/write
ahbsi_htrans: in std_logic_vector(1 downto 0); -- transfer type
ahbsi_hsize: in std_logic_vector(2 downto 0); -- transfer size
ahbsi_hburst: in std_logic_vector(2 downto 0); -- burst type
ahbsi_hwdata: in std_logic_vector(31 downto 0); -- write data bus
ahbsi_hprot: in std_logic_vector(3 downto 0); -- protection control
ahbsi_hready: in std_ulogic; -- transfer done
ahbsi_hmaster: in std_logic_vector(3 downto 0); -- current master
ahbsi_hmastlock: in std_ulogic; -- locked access
ahbsi_hmbsel: in std_logic_vector(0 to NAHBAMR-1); -- memory bank select
ahbsi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_logic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
disasen : in std_logic);
end component;
component leon3ft_proasic3e is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0);
port (
clk: in std_ulogic;
rstn: in std_ulogic;
ahbi_hgrant: in std_logic_vector(0 to NAHBMST-1); -- bus grant
ahbi_hready: in std_ulogic; -- transfer done
ahbi_hresp: in std_logic_vector(1 downto 0); -- response type
ahbi_hrdata: in std_logic_vector(31 downto 0); -- read data bus
ahbi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
ahbo_hbusreq: out std_ulogic; -- bus request
ahbo_hlock: out std_ulogic; -- lock request
ahbo_htrans: out std_logic_vector(1 downto 0); -- transfer type
ahbo_haddr: out std_logic_vector(31 downto 0); -- address bus (byte)
ahbo_hwrite: out std_ulogic; -- read/write
ahbo_hsize: out std_logic_vector(2 downto 0); -- transfer size
ahbo_hburst: out std_logic_vector(2 downto 0); -- burst type
ahbo_hprot: out std_logic_vector(3 downto 0); -- protection control
ahbo_hwdata: out std_logic_vector(31 downto 0); -- write data bus
ahbo_hirq: out std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
ahbsi_hsel: in std_logic_vector(0 to NAHBSLV-1); -- slave select
ahbsi_haddr: in std_logic_vector(31 downto 0); -- address bus (byte)
ahbsi_hwrite: in std_ulogic; -- read/write
ahbsi_htrans: in std_logic_vector(1 downto 0); -- transfer type
ahbsi_hsize: in std_logic_vector(2 downto 0); -- transfer size
ahbsi_hburst: in std_logic_vector(2 downto 0); -- burst type
ahbsi_hwdata: in std_logic_vector(31 downto 0); -- write data bus
ahbsi_hprot: in std_logic_vector(3 downto 0); -- protection control
ahbsi_hready: in std_ulogic; -- transfer done
ahbsi_hmaster: in std_logic_vector(3 downto 0); -- current master
ahbsi_hmastlock: in std_ulogic; -- locked access
ahbsi_hmbsel: in std_logic_vector(0 to NAHBAMR-1); -- memory bank select
ahbsi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_logic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
disasen : in std_logic);
end component;
component leon3ft_proasic3l is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0);
port (
clk: in std_ulogic;
rstn: in std_ulogic;
ahbi_hgrant: in std_logic_vector(0 to NAHBMST-1); -- bus grant
ahbi_hready: in std_ulogic; -- transfer done
ahbi_hresp: in std_logic_vector(1 downto 0); -- response type
ahbi_hrdata: in std_logic_vector(31 downto 0); -- read data bus
ahbi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
ahbo_hbusreq: out std_ulogic; -- bus request
ahbo_hlock: out std_ulogic; -- lock request
ahbo_htrans: out std_logic_vector(1 downto 0); -- transfer type
ahbo_haddr: out std_logic_vector(31 downto 0); -- address bus (byte)
ahbo_hwrite: out std_ulogic; -- read/write
ahbo_hsize: out std_logic_vector(2 downto 0); -- transfer size
ahbo_hburst: out std_logic_vector(2 downto 0); -- burst type
ahbo_hprot: out std_logic_vector(3 downto 0); -- protection control
ahbo_hwdata: out std_logic_vector(31 downto 0); -- write data bus
ahbo_hirq: out std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
ahbsi_hsel: in std_logic_vector(0 to NAHBSLV-1); -- slave select
ahbsi_haddr: in std_logic_vector(31 downto 0); -- address bus (byte)
ahbsi_hwrite: in std_ulogic; -- read/write
ahbsi_htrans: in std_logic_vector(1 downto 0); -- transfer type
ahbsi_hsize: in std_logic_vector(2 downto 0); -- transfer size
ahbsi_hburst: in std_logic_vector(2 downto 0); -- burst type
ahbsi_hwdata: in std_logic_vector(31 downto 0); -- write data bus
ahbsi_hprot: in std_logic_vector(3 downto 0); -- protection control
ahbsi_hready: in std_ulogic; -- transfer done
ahbsi_hmaster: in std_logic_vector(3 downto 0); -- current master
ahbsi_hmastlock: in std_ulogic; -- locked access
ahbsi_hmbsel: in std_logic_vector(0 to NAHBAMR-1); -- memory bank select
ahbsi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_logic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
disasen : in std_logic);
end component;
component leon3ft_atc18rha
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 1 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 1 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk: in std_ulogic;
gclk: in std_ulogic;
rstn: in std_ulogic;
ahbi_hgrant: in std_logic_vector(0 to NAHBMST-1); -- bus grant
ahbi_hready: in std_ulogic; -- transfer done
ahbi_hresp: in std_logic_vector(1 downto 0); -- response type
ahbi_hrdata: in std_logic_vector(31 downto 0); -- read data bus
ahbi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
ahbi_testen: in std_ulogic;
ahbi_testrst: in std_ulogic;
ahbi_scanen: in std_ulogic;
ahbi_testoen: in std_ulogic;
ahbo_hbusreq: out std_ulogic; -- bus request
ahbo_hlock: out std_ulogic; -- lock request
ahbo_htrans: out std_logic_vector(1 downto 0); -- transfer type
ahbo_haddr: out std_logic_vector(31 downto 0); -- address bus (byte)
ahbo_hwrite: out std_ulogic; -- read/write
ahbo_hsize: out std_logic_vector(2 downto 0); -- transfer size
ahbo_hburst: out std_logic_vector(2 downto 0); -- burst type
ahbo_hprot: out std_logic_vector(3 downto 0); -- protection control
ahbo_hwdata: out std_logic_vector(31 downto 0); -- write data bus
ahbo_hirq: out std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
ahbsi_hsel: in std_logic_vector(0 to NAHBSLV-1); -- slave select
ahbsi_haddr: in std_logic_vector(31 downto 0); -- address bus (byte)
ahbsi_hwrite: in std_ulogic; -- read/write
ahbsi_htrans: in std_logic_vector(1 downto 0); -- transfer type
ahbsi_hsize: in std_logic_vector(2 downto 0); -- transfer size
ahbsi_hburst: in std_logic_vector(2 downto 0); -- burst type
ahbsi_hwdata: in std_logic_vector(31 downto 0); -- write data bus
ahbsi_hprot: in std_logic_vector(3 downto 0); -- protection control
ahbsi_hready: in std_ulogic; -- transfer done
ahbsi_hmaster: in std_logic_vector(3 downto 0); -- current master
ahbsi_hmastlock: in std_ulogic; -- locked access
ahbsi_hmbsel: in std_logic_vector(0 to NAHBAMR-1); -- memory bank select
ahbsi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
disasen : in std_ulogic);
end component;
component leon3ft_cycloneiv
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi_hgrant: in std_logic_vector(0 to NAHBMST-1); -- bus grant
ahbi_hready: in std_ulogic; -- transfer done
ahbi_hresp: in std_logic_vector(1 downto 0); -- response type
ahbi_hrdata: in std_logic_vector(31 downto 0); -- read data bus
ahbi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
ahbi_testen: in std_ulogic;
ahbi_testrst: in std_ulogic;
ahbi_scanen: in std_ulogic;
ahbi_testoen: in std_ulogic;
ahbo_hbusreq: out std_ulogic; -- bus request
ahbo_hlock: out std_ulogic; -- lock request
ahbo_htrans: out std_logic_vector(1 downto 0); -- transfer type
ahbo_haddr: out std_logic_vector(31 downto 0); -- address bus (byte)
ahbo_hwrite: out std_ulogic; -- read/write
ahbo_hsize: out std_logic_vector(2 downto 0); -- transfer size
ahbo_hburst: out std_logic_vector(2 downto 0); -- burst type
ahbo_hprot: out std_logic_vector(3 downto 0); -- protection control
ahbo_hwdata: out std_logic_vector(31 downto 0); -- write data bus
ahbo_hirq: out std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
ahbsi_hsel: in std_logic_vector(0 to NAHBSLV-1); -- slave select
ahbsi_haddr: in std_logic_vector(31 downto 0); -- address bus (byte)
ahbsi_hwrite: in std_ulogic; -- read/write
ahbsi_htrans: in std_logic_vector(1 downto 0); -- transfer type
ahbsi_hsize: in std_logic_vector(2 downto 0); -- transfer size
ahbsi_hburst: in std_logic_vector(2 downto 0); -- burst type
ahbsi_hwdata: in std_logic_vector(31 downto 0); -- write data bus
ahbsi_hprot: in std_logic_vector(3 downto 0); -- protection control
ahbsi_hready: in std_ulogic; -- transfer done
ahbsi_hmaster: in std_logic_vector(3 downto 0); -- current master
ahbsi_hmastlock: in std_ulogic; -- locked access
ahbsi_hmbsel: in std_logic_vector(0 to NAHBAMR-1); -- memory bank select
ahbsi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
irqi_irl : in std_logic_vector(3 downto 0);
irqi_rst : in std_ulogic;
irqi_run : in std_ulogic;
irqi_rstvec : in std_logic_vector(31 downto 12);
irqi_iact : in std_ulogic;
irqi_index : in std_logic_vector(3 downto 0);
irqi_hrdrst : in std_ulogic;
irqo_intack : out std_ulogic;
irqo_irl : out std_logic_vector(3 downto 0);
irqo_pwd : out std_ulogic;
irqo_fpen : out std_ulogic;
irqo_idle : out std_ulogic;
dbgi_dsuen : in std_ulogic; -- DSU enable
dbgi_denable : in std_ulogic; -- diagnostic register access enablee
dbgi_dbreak : in std_ulogic; -- debug break-in
dbgi_step : in std_ulogic; -- single step
dbgi_halt : in std_ulogic; -- halt processor
dbgi_reset : in std_ulogic; -- reset processor
dbgi_dwrite : in std_ulogic; -- read/write
dbgi_daddr : in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata : in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa : in std_ulogic; -- break on IU trap
dbgi_btrape : in std_ulogic; -- break on IU trap
dbgi_berror : in std_ulogic; -- break on IU error mode
dbgi_bwatch : in std_ulogic; -- break on IU watchpoint
dbgi_bsoft : in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable : in std_ulogic;
dbgi_timer : in std_logic_vector(30 downto 0);
dbgo_data : out std_logic_vector(31 downto 0);
dbgo_crdy : out std_ulogic;
dbgo_dsu : out std_ulogic;
dbgo_dsumode : out std_ulogic;
dbgo_error : out std_ulogic;
dbgo_halt : out std_ulogic;
dbgo_pwd : out std_ulogic;
dbgo_idle : out std_ulogic;
dbgo_ipend : out std_ulogic;
dbgo_icnt : out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss : out std_ulogic;
dbgo_istat_tmiss : out std_ulogic;
dbgo_istat_chold : out std_ulogic;
dbgo_istat_mhold : out std_ulogic;
dbgo_dstat_cmiss : out std_ulogic;
dbgo_dstat_tmiss : out std_ulogic;
dbgo_dstat_chold : out std_ulogic;
dbgo_dstat_mhold : out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic;
-- fpui : out grfpu_in_type;
-- fpuo : in grfpu_out_type;
clken : in std_ulogic);
end component;
signal ahbi_hgrant: std_logic_vector(0 to NAHBMST-1);
signal ahbi_hready: std_ulogic;
signal ahbi_hresp: std_logic_vector(1 downto 0);
signal ahbi_hrdata: std_logic_vector(31 downto 0);
signal ahbi_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
signal ahbi_testen: std_ulogic;
signal ahbi_testrst: std_ulogic;
signal ahbi_scanen: std_ulogic;
signal ahbi_testoen: std_ulogic;
signal ahbo_hbusreq: std_ulogic;
signal ahbo_hlock: std_ulogic;
signal ahbo_htrans: std_logic_vector(1 downto 0);
signal ahbo_haddr: std_logic_vector(31 downto 0);
signal ahbo_hwrite: std_ulogic;
signal ahbo_hsize: std_logic_vector(2 downto 0);
signal ahbo_hburst: std_logic_vector(2 downto 0);
signal ahbo_hprot: std_logic_vector(3 downto 0);
signal ahbo_hwdata: std_logic_vector(31 downto 0);
signal ahbo_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
signal ahbsi_hsel: std_logic_vector(0 to NAHBSLV-1);
signal ahbsi_haddr: std_logic_vector(31 downto 0);
signal ahbsi_hwrite: std_ulogic;
signal ahbsi_htrans: std_logic_vector(1 downto 0);
signal ahbsi_hsize: std_logic_vector(2 downto 0);
signal ahbsi_hburst: std_logic_vector(2 downto 0);
signal ahbsi_hwdata: std_logic_vector(31 downto 0);
signal ahbsi_hprot: std_logic_vector(3 downto 0);
signal ahbsi_hready: std_ulogic;
signal ahbsi_hmaster: std_logic_vector(3 downto 0);
signal ahbsi_hmastlock: std_ulogic;
signal ahbsi_hmbsel: std_logic_vector(0 to NAHBAMR-1);
signal ahbsi_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
constant L3DI :integer := GAISLER_LEON3
;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, L3DI, 0, 3, 0),
others => zero32);
begin
disasen <= '1' when disas /= 0 else '0';
-- Plug&Play information
ahbo.hconfig <= hconfig;
ahbo.hindex <= hindex;
ax : if fabtech = axcel generate
-- pragma translate_off
assert false
report "LEON3 netlist: netlist for this technology is deprecated"
severity failure;
-- pragma translate_on
wrp: leon3ft_axcelerator
generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize)
port map(
clk => clk,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_rst => irqi_rst,
irqi_run => irqi_run,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer,
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
disasen => disasen);
end generate;
pa3 : if (fabtech = apa3) generate
-- pragma translate_off
assert false
report "LEON3 netlist: netlist for this technology is deprecated"
severity failure;
-- pragma translate_on
wrp: leon3ft_proasic3
generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize)
port map(
clk => clk,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_rst => irqi_rst,
irqi_run => irqi_run,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer,
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
disasen => disasen);
end generate;
pa3e : if (fabtech = apa3e) generate
-- pragma translate_off
assert false
report "LEON3 netlist: netlist for this technology is deprecated"
severity failure;
-- pragma translate_on
wrp: leon3ft_proasic3e
generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize)
port map(
clk => clk,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_rst => irqi_rst,
irqi_run => irqi_run,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer,
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
disasen => disasen);
end generate;
pa3l : if (fabtech = apa3l) generate
-- pragma translate_off
assert false
report "LEON3 netlist: netlist for this technology is deprecated"
severity failure;
-- pragma translate_on
wrp: leon3ft_proasic3l
generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize)
port map(
clk => clk,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_rst => irqi_rst,
irqi_run => irqi_run,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer,
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
disasen => disasen);
end generate;
xil : if (is_unisim(fabtech) = 1) generate
-- pragma translate_off
assert false
report "LEON3 netlist: netlist for this technology is deprecated"
severity failure;
-- pragma translate_on
wrp: leon3ft_unisim
generic map (fabtech => fabtech, fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize)
port map(
clk => clk,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_rst => irqi_rst,
irqi_run => irqi_run,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer,
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
disasen => disasen);
end generate;
atc : if fabtech = atc18rha generate
-- pragma translate_off
assert false
report "LEON3 netlist: netlist for this technology is deprecated"
severity failure;
-- pragma translate_on
wrp: leon3ft_atc18rha
generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize)
port map(
clk => clk,
gclk => gclk2,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbi_testen => ahbi_testen,
ahbi_testrst => ahbi_testrst,
ahbi_scanen => ahbi_scanen,
ahbi_testoen => ahbi_testoen,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_rst => irqi_rst,
irqi_run => irqi_run,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer,
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
disasen => disasen);
end generate;
cyciv : if fabtech = cyclone3 generate
wrp: leon3ft_cycloneiv
generic map (
hindex => hindex,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu,
v8 => v8,
cp => cp,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
iuft => iuft,
fpft => fpft,
cmft => cmft,
cached => cached,
scantest => scantest,
mmupgsz => mmupgsz,
bp => bp,
npasi => npasi,
pwrpsr => pwrpsr)
port map(
clk => clk,
gclk2 => gclk2,
gfclk2 => gfclk2,
clk2 => clk2,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbi_testen => ahbi_testen,
ahbi_testrst => ahbi_testrst,
ahbi_scanen => ahbi_scanen,
ahbi_testoen => ahbi_testoen,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_rst => irqi_rst,
irqi_run => irqi_run,
irqi_rstvec => irqi_rstvec,
irqi_iact => irqi_iact,
irqi_index => irqi_index,
irqi_hrdrst => irqi_hrdrst,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
irqo_fpen => irqo_fpen,
irqo_idle => irqo_idle,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer,
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
dbgo_fcnt => dbgo_fcnt,
dbgo_optype => dbgo_optype,
dbgo_bpmiss => dbgo_bpmiss,
dbgo_istat_cmiss => dbgo_istat_cmiss,
dbgo_istat_tmiss => dbgo_istat_tmiss,
dbgo_istat_chold => dbgo_istat_chold,
dbgo_istat_mhold => dbgo_istat_mhold,
dbgo_dstat_cmiss => dbgo_dstat_cmiss,
dbgo_dstat_tmiss => dbgo_dstat_tmiss,
dbgo_dstat_chold => dbgo_dstat_chold,
dbgo_dstat_mhold => dbgo_dstat_mhold,
dbgo_wbhold => dbgo_wbhold,
dbgo_su => dbgo_su,
clken => clken);
end generate;
ahbi_hgrant(0) <= ahbi.hgrant(hindex);
ahbi_hgrant(1 to NAHBMST-1) <= (others => '0');
ahbi_hready <= ahbi.hready;
ahbi_hresp <= ahbi.hresp;
ahbi_hrdata <= ahbi.hrdata(31 downto 0);
ahbi_hirq <= ahbi.hirq;
ahbi_testen <= ahbi.testen;
ahbi_testrst <= ahbi.testrst;
ahbi_scanen <= ahbi.scanen;
ahbi_testoen <= ahbi.testoen;
ahbo.hbusreq <= ahbo_hbusreq;
ahbo.hlock <= ahbo_hlock;
ahbo.htrans <= ahbo_htrans;
ahbo.haddr <= ahbo_haddr;
ahbo.hwrite <= ahbo_hwrite;
ahbo.hsize <= '0' & ahbo_hsize(1 downto 0);
ahbo.hburst <= "00" & ahbo_hburst(0);
ahbo.hprot <= ahbo_hprot;
ahbo.hwdata(31 downto 0) <= ahbo_hwdata;
ahbo.hirq <= (others => '0'); --ahbo_hirq;
ahbsi_hsel <= ahbsi.hsel;
ahbsi_haddr <= ahbsi.haddr;
ahbsi_hwrite <= ahbsi.hwrite;
ahbsi_htrans <= ahbsi.htrans;
ahbsi_hsize <= ahbsi.hsize;
ahbsi_hburst <= ahbsi.hburst;
ahbsi_hwdata <= ahbsi.hwdata(31 downto 0);
ahbsi_hprot <= ahbsi.hprot;
ahbsi_hready <= ahbsi.hready;
ahbsi_hmaster <= ahbsi.hmaster;
ahbsi_hmastlock <= ahbsi.hmastlock;
ahbsi_hmbsel <= ahbsi.hmbsel;
ahbsi_hirq <= ahbsi.hirq;
-- pragma translate_off
assert NAHBSLV=16
report "LEON3 netlist: Only NAHBSLV=16 supported by wrapper"
severity Failure;
-- pragma translate_on
end architecture;
|
gpl-2.0
|
d3c7c81a0639ac63206b3d05276b6e14
| 0.49119 | 3.989577 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/memctrl/sdctrl.vhd
| 1 | 29,776 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdctrl
-- File: sdctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 32-bit SDRAM memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity sdctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of sdctrl is
constant WPROTEN : boolean := wprot = 1;
constant SDINVCLK : boolean := invclk = 1;
constant BUS64 : boolean := (sdbits = 64);
constant REVISION : integer := 1;
constant PM_PD : std_logic_vector(2 downto 0) := "001";
constant PM_SR : std_logic_vector(2 downto 0) := "010";
constant PM_DPD : std_logic_vector(2 downto 0) := "101";
constant std_rammask: Std_Logic_Vector(31 downto 20) :=
Conv_Std_Logic_Vector(hmask, 12);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SDCTRL, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4, wr5, sidle,
sref, pd, dpd);
type icycletype is (iidle, pre, ref, lmode, emode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
pageburst : std_ulogic;
mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
cke : std_ulogic; -- Clock enable
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
nbdrive : std_ulogic;
burst : std_ulogic;
wprothit : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(sdbits-1 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(3 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
address : std_logic_vector(16 downto 2); -- memory address
bsel : std_ulogic;
idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
pwron : std_ulogic;
end record;
signal r, ri : reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
ctrl : process(rst, ahbsi, r, sdi, rbdrive)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable dout : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable lline : std_logic_vector(2 downto 0);
variable lineburst : boolean;
variable haddr_tmp : std_logic_vector(31 downto 0);
variable arefresh : std_logic;
variable hwdata : std_logic_vector(31 downto 0);
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.hresp := HRESP_OKAY; vbdrive := rbdrive; arefresh := '0';
v.hrdata(sdbits-1 downto sdbits-32) := sdi.data(sdbits-1 downto sdbits-32);
v.hrdata(31 downto 0) := sdi.data(31 downto 0);
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2)); v.hwdata := hwdata;
lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
lineburst := true;
else lineburst := false; end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := v.hio;
end if;
v.haddr := ahbsi.haddr;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
v.haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size;
htrans := r.htrans; hwrite := r.hwrite;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if fast = 1 then haddr := r.haddr; end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- main state
case r.size is
when "00" =>
case r.haddr(1 downto 0) is
when "00" => dqm := "11110111";
when "01" => dqm := "11111011";
when "10" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
if r.haddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if;
when others => dqm := "11110000";
end case;
if BUS64 and (r.bsel = '1') then dqm := dqm(3 downto 0) & "1111"; end if;
-- main FSM
case r.mstate is
when midle =>
if ((v.hsel and htrans(1) and not v.hio) = '1') then
if (r.sdstate = sidle) and (r.cfg.command = "000")
and (r.cmstate = midle) and (v.hio = '0')
then
if fast = 0 then startsd := '1'; else v.startsd := '1'; end if;
v.mstate := active;
elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
and (r.cfg.command = "000") and (r.cmstate = midle) and (v.hio = '0')
then
v.startsd := '1';
if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
v.hresp := HRESP_ERROR;
else
v.mstate := active;
end if;
end if;
end if;
when others => null;
end case;
startsd := startsd or r.startsd;
-- generate row and column address size
case r.cfg.csize is
when "00" => raddr := haddr(22 downto 10);
when "01" => raddr := haddr(23 downto 11);
when "10" => raddr := haddr(24 downto 12);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
else raddr := haddr(25 downto 13); end if;
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
genmux(r.cfg.bsize, haddr(27 downto 20));
-- generate chip select
if BUS64 then
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
v.bsel := genmux(r.cfg.bsize, r.haddr(29 downto 22));
else
adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
end if;
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
v.address(16 downto 2) := ba & raddr;
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
case r.cfg.pmode is
when PM_SR =>
v.cfg.cke := '0'; v.sdstate := sref;
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
when PM_DPD =>
v.cfg.cke := '0'; v.sdstate := dpd;
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
when others =>
end case;
end if;
when act1 =>
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
end if;
if WPROTEN then
v.wprothit := sdi.wprot;
if sdi.wprot = '1' then v.hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
v.dqm := dqm; v.burst := r.hready;
if r.hwrite = '1' then
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0';
if ahbsi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '1';
v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '1'; v.casn := '1';
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
if (((r.burst and r.hready) = '1') and (r.htrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))
then
v.hready := ahbsi.htrans(0) and ahbsi.htrans(1) and r.hready;
if ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (r.trfc(2 downto 1) = "00") then
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
end if;
when wr3 =>
if (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
when wr5 =>
v.sdstate := sidle; v.idlecnt := (others => '1');
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(4 downto 2) = "111" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd7 =>
v.casn := '1';
if r.cfg.casdel = '1' then
v.sdstate := rd2;
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else
v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if r.haddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if r.haddr(4 downto 2) = "101" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
elsif lineburst and (ahbsi.htrans = "11") and (r.casn = '1') then
if r.haddr(4 downto 2) = ("10" & not r.cfg.casdel) then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (ahbsi.htrans /= "11") or (r.sdcsn = "11") or
((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
elsif lineburst then
if (r.haddr(4 downto 2) = lline) and (r.casn = '1') then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when sref =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
if r.trfc = "0000" then -- Minimum duration (= tRAS)
v.cfg.cke := '1';
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
end if;
if r.cfg.cke = '1' then
if (r.idlecnt = "0000") then -- tXSR ns with NOP
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.sref_tmpcom := r.cfg.command;
v.cfg.command := "100";
end if;
else
v.idlecnt := r.cfg.txsr;
end if;
end if;
when pd =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
v.cfg.cke := '1';
v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when dpd =>
v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
v.cfg.renable := '0';
if (startsd = '1' and r.hio = '0') then
v.hready := '1'; -- ack all accesses with Error response
v.startsd := '0';
v.hresp := HRESP_ERROR;
elsif r.cfg.pmode /= PM_DPD then
v.cfg.cke := '1';
if r.cfg.cke = '1' then
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.cfg.renable := '1';
end if;
end if;
when others =>
v.sdstate := sidle; v.idlecnt := (others => '1');
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "010" => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when "100" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "110" => -- Lodad Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
if lineburst then
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011";
else
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111";
end if;
when "111" => -- Load Ext-Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
& r.cfg.pasr(2 downto 0);
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; --v.cfg.command := "000";
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
when leadout =>
if r.trfc = "0000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
v.cfg.cke := '1';
if (r.cfg.renable = '1' or (pwron /= 0 and r.pwron = '1')) and r.cfg.cke = '1' then
v.cfg.command := "010"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.mobileen = "11" then
v.cfg.command := "111"; v.istate := emode;
else
v.istate := finish;
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := finish;
end if;
when others =>
if pwron /= 0 then v.pwron := '0'; end if;
if r.cfg.renable = '0' and r.sdstate /= dpd then
v.istate := iidle;
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
if (r.hsel and r.hio and not r.hready) = '1' then v.hready := '1'; end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
-- pragma translate_off
if not is_x(r.cfg.refresh) then
-- pragma translate_on
if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "100";
arefresh := '1';
end if;
end if;
-- pragma translate_off
end if;
-- pragma translate_on
-- AHB register access
if (r.hsel and r.hio and r.hwrite and r.htrans(1)) = '1' then
if r.haddr(3 downto 2) = "00" then
if pageburst = 2 then v.cfg.pageburst := hwdata(17); end if;
v.cfg.command := hwdata(20 downto 18);
v.cfg.csize := hwdata(22 downto 21);
v.cfg.bsize := hwdata(25 downto 23);
v.cfg.casdel := hwdata(26);
v.cfg.trfc := hwdata(29 downto 27);
v.cfg.trp := hwdata(30);
v.cfg.renable := hwdata(31);
v.cfg.refresh := hwdata(14 downto 0);
v.refresh := (others => '0');
elsif r.haddr(3 downto 2) = "01" then
if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := hwdata(31); end if;
if r.cfg.pmode = "000" then
v.cfg.cke := hwdata(30);
end if;
if r.cfg.mobileen(1) = '1' then
v.cfg.txsr := hwdata(23 downto 20);
v.cfg.pmode := hwdata(18 downto 16);
v.cfg.ds(3 downto 2) := hwdata( 6 downto 5);
v.cfg.tcsr(3 downto 2) := hwdata( 4 downto 3);
v.cfg.pasr(5 downto 3) := hwdata( 2 downto 0);
end if;
end if;
end if;
-- Disable CS and DPD when Mobile SDR is Disabled
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
-- Update EMR when ds, tcsr or pasr change
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
end if;
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
end if;
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
end if;
end if;
regsd := (others => '0');
if r.haddr(3 downto 2) = "00" then
regsd(31 downto 18) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command;
if not lineburst then regsd(17) := '1'; end if;
regsd(16) := r.cfg.mobileen(1);
if BUS64 then regsd(15) := '1'; end if;
regsd(14 downto 0) := r.cfg.refresh;
elsif r.haddr(3 downto 2) = "01" then
regsd(31) := r.cfg.mobileen(0);
regsd(30) := r.cfg.cke;
regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
end if;
if (r.hsel and r.hio) = '1' then dout := regsd;
else
if BUS64 and r.bsel = '1' then dout := r.hrdata(63 downto 32);
else dout := r.hrdata(31 downto 0); end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "000";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
v.cfg.renable := '0';
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.bsel := '0';
v.startsd := '0';
if pwron /= 0 then v.pwron := '1'; end if;
if (pageburst = 2) then
v.cfg.pageburst := '0';
end if;
if mobile >= 2 then v.cfg.mobileen := "11";
elsif mobile = 1 then v.cfg.mobileen := "10";
else v.cfg.mobileen := "00"; end if;
v.cfg.txsr := (others => '1');
v.cfg.pmode := (others => '0');
v.cfg.ds := (others => '0');
v.cfg.tcsr := (others => '0');
v.cfg.pasr := (others => '0');
if mobile >= 2 then v.cfg.cke := '0';
else v.cfg.cke := '1'; end if;
v.sref_tmpcom := "000";
v.idlecnt := (others => '1');
v.hio := '0';
end if;
if pwron = 0 then v.pwron := '0'; end if;
if not WPROTEN then v.wprothit := '0'; end if;
ri <= v;
ribdrive <= vbdrive;
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(dout);
end process;
--sdo.sdcke <= (others => '1');
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
driveundriven : block
begin
sdo.qdrive <= '0';
sdo.nbdrive <= '0';
sdo.ce <= '0';
sdo.moben <= '0';
sdo.cal_rst <= '0';
sdo.oct <= '0';
sdo.dqs_gate <= '0';
sdo.xsdcsn <= (others => '1');
sdo.data(127 downto sdbits) <= (others => '0');
sdo.cb <= (others => '0');
sdo.ba <= (others => '0');
sdo.sdck <= (others => '0');
sdo.cal_en <= (others => '0');
sdo.cal_inc <= (others => '0');
sdo.cal_pll <= (others => '0');
sdo.odt <= (others => '0');
sdo.conf <= (others => '0');
sdo.vcbdrive <= (others => '0');
sdo.cbdqm <= (others => '0');
sdo.cbcal_en <= (others => '0');
sdo.cbcal_inc <= (others => '0');
sdo.read_pend <= (others => '0');
sdo.regwdata <= (others => '0');
sdo.regwrite <= (others => '0');
end block driveundriven;
regs : process(clk, rst) begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive;
if rst = '0' then r.icnt <= (others => '0'); end if;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
end if;
end process;
rgen : if not SDINVCLK generate
sdo.address <= r.address;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.vbdrive <= zero32 & rbdrive;
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
drivebus: for i in 0 to sdbits/64 generate
sdo.data(31+32*i downto 32*i) <= r.hwdata;
end generate;
end generate;
ngen : if SDINVCLK generate
nregs : process(clk, rst) begin
if falling_edge(clk) then
sdo.address <= r.address;
if oepol = 1 then sdo.bdrive <= r.nbdrive;
else sdo.bdrive <= r.bdrive; end if;
sdo.vbdrive <= zero32 & rbdrive;
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
for i in 0 to sdbits/64 loop
sdo.data(31+32*i downto 32*i) <= r.hwdata;
end loop;
end if;
if rst = '0' then sdo.sdcsn <= (others => '1'); end if;
end process;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("sdctrl" & tost(hindex) &
": PC133 SDRAM controller rev " & tost(REVISION));
-- pragma translate_on
end;
|
gpl-2.0
|
895c7f359cb9e8c9668a9399e42e6c38
| 0.524483 | 3.252786 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-sp601/ahbrom.vhd
| 6 | 3,101 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 17;
constant bytes : integer := 89996;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= romdata;
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"88100000";
when 16#00001# => romdata <= X"09100031";
when 16#00002# => romdata <= X"81C12314";
when 16#00003# => romdata <= X"01000000";
when 16#00004# => romdata <= X"A1480000";
when 16#00005# => romdata <= X"A7500000";
when 16#00006# => romdata <= X"10800836";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
gpl-2.0
|
51a31ea7540240fe8182cdb52ab722b3
| 0.581425 | 3.56847 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/leon3v3/dsu3.vhd
| 1 | 2,595 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dsu
-- File: dsu.vhd
-- Author: Jiri Gaisler, Edvin Catovic - Gaisler Research
-- Description: Combined LEON3 debug support and AHB trace unit
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
entity dsu3 is
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end;
architecture rtl of dsu3 is
signal gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
x0 : dsu3x generic map (hindex, haddr, hmask, ncpu, tbits, tech, irq, kbytes, 0, testen, bwidth, ahbpf)
port map (rst, gnd, clk, ahbmi, ahbsi, ahbso, ahbsi, dbgi, dbgo, dsui, dsuo, vcc
);
end;
|
gpl-2.0
|
557409a3b4c499488c8ec0f9edd5740e
| 0.589981 | 3.782799 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/buffer00.vhd
| 1 | 1,938 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity buffer00 is
port(
clkb: in std_logic;
enableb: in std_logic;
inFlagb2: in std_logic ;
inFlagb: in std_logic ;
inucb: in std_logic_vector ( 7 downto 0 );
inucb2: in std_logic_vector ( 7 downto 0 );
outucb: out std_logic_vector ( 7 downto 0 );
outFlagb: out std_logic );
end;
architecture buffer0 of buffer00 is
begin
pbuff: process(clkb, enableb, inucb)
begin
if(clkb = '1' and enableb = '1') then
outFlagb <= '1';
outucb <= inucb;
else
outFlagb <= '0';
outucb <= (others => '0');
end if;
end process pbuff;
--pbuff: process(clkb, inFlagb, inFlagb2, inucb, inucb2)
--begin
-- if (clkb'event and clkb = '1') then
-- if (inFlagb = '0' and inFlagb2 = '0') then
-- if (enableb = '1') then
-- outucb <= inucb;
-- outFlagb <= '1';
-- else
-- outucb <= (others => 'Z');
-- outFlagb <= 'Z';
-- end if;
-- elsif (inFlagb = '0' and inFlagb2 = '1') then
-- if (enableb = '1') then
-- outucb <= inucb2;
-- outFlagb <= '1';
-- else
-- outucb <= (others => 'Z');
-- outFlagb <= 'Z';
-- end if;
-- elsif (inFlagb = '1' and inFlagb2 = '0') then
-- if (enableb = '1') then
-- outucb <= inucb;
-- outFlagb <= '1';
-- else
-- outucb <= (others => 'Z');
-- outFlagb <= 'Z';
-- end if;
-- elsif (inFlagb = '1' and inFlagb2 = '1') then
-- if (enableb = '1') then
-- outucb <= inucb2;
-- outFlagb <= '1';
-- else
-- outucb <= (others => 'Z');
-- outFlagb <= 'Z';
-- end if;
-- end if;
-- end if;
--end process pbuff;
end buffer0;
|
apache-2.0
|
edb1fe9ad268deb540b42b8fe6d15ded
| 0.473168 | 3.19802 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/esa/pci/pcicomp.vhd
| 3 | 837 |
library ieee;
library grlib;
library techmap;
use grlib.amba.all;
use techmap.gencomp.all;
use ieee.std_logic_1164.all;
package pcicomp is
component pciarb is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
nb_agents : integer := 4;
apb_en : integer := 1;
netlist : integer := 0;
tech : integer := axcel;
reg : integer := 0);
port(
clk : in std_ulogic;
rst_n : in std_ulogic;
req_n : in std_logic_vector(0 to nb_agents-1);
frame_n : in std_logic;
gnt_n : out std_logic_vector(0 to nb_agents-1);
pclk : in std_ulogic;
prst_n : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
end package;
|
gpl-2.0
|
fb2f05bd38729a015ed3285db055a87f
| 0.542413 | 3.295276 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/misc/charrom.vhd
| 1 | 119,262 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: charrom
-- File: charrom.vhd
-- Author: Marcus Hellqvist
-- Description: Character ROM for video controller
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity charrom is
port(
clk : in std_ulogic;
addr : in std_logic_vector(11 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of charrom is
signal romdata : std_logic_vector(7 downto 0);
signal romaddr : std_logic_vector(11 downto 0);
begin
data <= romdata;
p0: process(clk)
begin
if rising_edge(clk) then
romaddr <= addr;
end if;
end process;
p1: process(romaddr)
begin
case conv_integer(romaddr) is
when 16#000# => romdata <= X"00"; --
when 16#100# => romdata <= X"00"; --
when 16#200# => romdata <= X"00"; --
when 16#300# => romdata <= X"00"; --
when 16#400# => romdata <= X"00"; --
when 16#500# => romdata <= X"00"; --
when 16#600# => romdata <= X"00"; --
when 16#700# => romdata <= X"00"; --
when 16#800# => romdata <= X"00"; --
when 16#900# => romdata <= X"00"; --
when 16#a00# => romdata <= X"00"; --
when 16#b00# => romdata <= X"00"; --
when 16#c00# => romdata <= X"00"; --
when 16#020# => romdata <= X"00"; --
when 16#120# => romdata <= X"00"; --
when 16#220# => romdata <= X"00"; --
when 16#320# => romdata <= X"00"; --
when 16#420# => romdata <= X"00"; --
when 16#520# => romdata <= X"00"; --
when 16#620# => romdata <= X"00"; --
when 16#720# => romdata <= X"00"; --
when 16#820# => romdata <= X"00"; --
when 16#920# => romdata <= X"00"; --
when 16#a20# => romdata <= X"00"; --
when 16#b20# => romdata <= X"00"; --
when 16#c20# => romdata <= X"00"; --
when 16#021# => romdata <= X"00"; -- !
when 16#121# => romdata <= X"00"; -- !
when 16#221# => romdata <= X"10"; -- !
when 16#321# => romdata <= X"10"; -- !
when 16#421# => romdata <= X"10"; -- !
when 16#521# => romdata <= X"10"; -- !
when 16#621# => romdata <= X"10"; -- !
when 16#721# => romdata <= X"10"; -- !
when 16#821# => romdata <= X"10"; -- !
when 16#921# => romdata <= X"00"; -- !
when 16#a21# => romdata <= X"10"; -- !
when 16#b21# => romdata <= X"00"; -- !
when 16#c21# => romdata <= X"00"; -- !
when 16#022# => romdata <= X"00"; -- "
when 16#122# => romdata <= X"00"; -- "
when 16#222# => romdata <= X"24"; -- "
when 16#322# => romdata <= X"24"; -- "
when 16#422# => romdata <= X"24"; -- "
when 16#522# => romdata <= X"00"; -- "
when 16#622# => romdata <= X"00"; -- "
when 16#722# => romdata <= X"00"; -- "
when 16#822# => romdata <= X"00"; -- "
when 16#922# => romdata <= X"00"; -- "
when 16#a22# => romdata <= X"00"; -- "
when 16#b22# => romdata <= X"00"; -- "
when 16#c22# => romdata <= X"00"; -- "
when 16#023# => romdata <= X"00"; -- #
when 16#123# => romdata <= X"00"; -- #
when 16#223# => romdata <= X"00"; -- #
when 16#323# => romdata <= X"24"; -- #
when 16#423# => romdata <= X"24"; -- #
when 16#523# => romdata <= X"7e"; -- #
when 16#623# => romdata <= X"24"; -- #
when 16#723# => romdata <= X"7e"; -- #
when 16#823# => romdata <= X"24"; -- #
when 16#923# => romdata <= X"24"; -- #
when 16#a23# => romdata <= X"00"; -- #
when 16#b23# => romdata <= X"00"; -- #
when 16#c23# => romdata <= X"00"; -- #
when 16#024# => romdata <= X"00"; -- $
when 16#124# => romdata <= X"00"; -- $
when 16#224# => romdata <= X"10"; -- $
when 16#324# => romdata <= X"3c"; -- $
when 16#424# => romdata <= X"50"; -- $
when 16#524# => romdata <= X"50"; -- $
when 16#624# => romdata <= X"38"; -- $
when 16#724# => romdata <= X"14"; -- $
when 16#824# => romdata <= X"14"; -- $
when 16#924# => romdata <= X"78"; -- $
when 16#a24# => romdata <= X"10"; -- $
when 16#b24# => romdata <= X"00"; -- $
when 16#c24# => romdata <= X"00"; -- $
when 16#025# => romdata <= X"00"; -- %
when 16#125# => romdata <= X"00"; -- %
when 16#225# => romdata <= X"22"; -- %
when 16#325# => romdata <= X"52"; -- %
when 16#425# => romdata <= X"24"; -- %
when 16#525# => romdata <= X"08"; -- %
when 16#625# => romdata <= X"08"; -- %
when 16#725# => romdata <= X"10"; -- %
when 16#825# => romdata <= X"24"; -- %
when 16#925# => romdata <= X"2a"; -- %
when 16#a25# => romdata <= X"44"; -- %
when 16#b25# => romdata <= X"00"; -- %
when 16#c25# => romdata <= X"00"; -- %
when 16#026# => romdata <= X"00"; -- &
when 16#126# => romdata <= X"00"; -- &
when 16#226# => romdata <= X"00"; -- &
when 16#326# => romdata <= X"00"; -- &
when 16#426# => romdata <= X"30"; -- &
when 16#526# => romdata <= X"48"; -- &
when 16#626# => romdata <= X"48"; -- &
when 16#726# => romdata <= X"30"; -- &
when 16#826# => romdata <= X"4a"; -- &
when 16#926# => romdata <= X"44"; -- &
when 16#a26# => romdata <= X"3a"; -- &
when 16#b26# => romdata <= X"00"; -- &
when 16#c26# => romdata <= X"00"; -- &
when 16#027# => romdata <= X"00"; -- '
when 16#127# => romdata <= X"00"; -- '
when 16#227# => romdata <= X"10"; -- '
when 16#327# => romdata <= X"10"; -- '
when 16#427# => romdata <= X"10"; -- '
when 16#527# => romdata <= X"00"; -- '
when 16#627# => romdata <= X"00"; -- '
when 16#727# => romdata <= X"00"; -- '
when 16#827# => romdata <= X"00"; -- '
when 16#927# => romdata <= X"00"; -- '
when 16#a27# => romdata <= X"00"; -- '
when 16#b27# => romdata <= X"00"; -- '
when 16#c27# => romdata <= X"00"; -- '
when 16#028# => romdata <= X"00"; -- (
when 16#128# => romdata <= X"00"; -- (
when 16#228# => romdata <= X"04"; -- (
when 16#328# => romdata <= X"08"; -- (
when 16#428# => romdata <= X"08"; -- (
when 16#528# => romdata <= X"10"; -- (
when 16#628# => romdata <= X"10"; -- (
when 16#728# => romdata <= X"10"; -- (
when 16#828# => romdata <= X"08"; -- (
when 16#928# => romdata <= X"08"; -- (
when 16#a28# => romdata <= X"04"; -- (
when 16#b28# => romdata <= X"00"; -- (
when 16#c28# => romdata <= X"00"; -- (
when 16#029# => romdata <= X"00"; -- )
when 16#129# => romdata <= X"00"; -- )
when 16#229# => romdata <= X"20"; -- )
when 16#329# => romdata <= X"10"; -- )
when 16#429# => romdata <= X"10"; -- )
when 16#529# => romdata <= X"08"; -- )
when 16#629# => romdata <= X"08"; -- )
when 16#729# => romdata <= X"08"; -- )
when 16#829# => romdata <= X"10"; -- )
when 16#929# => romdata <= X"10"; -- )
when 16#a29# => romdata <= X"20"; -- )
when 16#b29# => romdata <= X"00"; -- )
when 16#c29# => romdata <= X"00"; -- )
when 16#02a# => romdata <= X"00"; -- *
when 16#12a# => romdata <= X"00"; -- *
when 16#22a# => romdata <= X"24"; -- *
when 16#32a# => romdata <= X"18"; -- *
when 16#42a# => romdata <= X"7e"; -- *
when 16#52a# => romdata <= X"18"; -- *
when 16#62a# => romdata <= X"24"; -- *
when 16#72a# => romdata <= X"00"; -- *
when 16#82a# => romdata <= X"00"; -- *
when 16#92a# => romdata <= X"00"; -- *
when 16#a2a# => romdata <= X"00"; -- *
when 16#b2a# => romdata <= X"00"; -- *
when 16#c2a# => romdata <= X"00"; -- *
when 16#02b# => romdata <= X"00"; -- +
when 16#12b# => romdata <= X"00"; -- +
when 16#22b# => romdata <= X"00"; -- +
when 16#32b# => romdata <= X"00"; -- +
when 16#42b# => romdata <= X"10"; -- +
when 16#52b# => romdata <= X"10"; -- +
when 16#62b# => romdata <= X"7c"; -- +
when 16#72b# => romdata <= X"10"; -- +
when 16#82b# => romdata <= X"10"; -- +
when 16#92b# => romdata <= X"00"; -- +
when 16#a2b# => romdata <= X"00"; -- +
when 16#b2b# => romdata <= X"00"; -- +
when 16#c2b# => romdata <= X"00"; -- +
when 16#02c# => romdata <= X"00"; -- ,
when 16#12c# => romdata <= X"00"; -- ,
when 16#22c# => romdata <= X"00"; -- ,
when 16#32c# => romdata <= X"00"; -- ,
when 16#42c# => romdata <= X"00"; -- ,
when 16#52c# => romdata <= X"00"; -- ,
when 16#62c# => romdata <= X"00"; -- ,
when 16#72c# => romdata <= X"00"; -- ,
when 16#82c# => romdata <= X"00"; -- ,
when 16#92c# => romdata <= X"38"; -- ,
when 16#a2c# => romdata <= X"30"; -- ,
when 16#b2c# => romdata <= X"40"; -- ,
when 16#c2c# => romdata <= X"00"; -- ,
when 16#02d# => romdata <= X"00"; -- -
when 16#12d# => romdata <= X"00"; -- -
when 16#22d# => romdata <= X"00"; -- -
when 16#32d# => romdata <= X"00"; -- -
when 16#42d# => romdata <= X"00"; -- -
when 16#52d# => romdata <= X"00"; -- -
when 16#62d# => romdata <= X"7c"; -- -
when 16#72d# => romdata <= X"00"; -- -
when 16#82d# => romdata <= X"00"; -- -
when 16#92d# => romdata <= X"00"; -- -
when 16#a2d# => romdata <= X"00"; -- -
when 16#b2d# => romdata <= X"00"; -- -
when 16#c2d# => romdata <= X"00"; -- -
when 16#02e# => romdata <= X"00"; -- .
when 16#12e# => romdata <= X"00"; -- .
when 16#22e# => romdata <= X"00"; -- .
when 16#32e# => romdata <= X"00"; -- .
when 16#42e# => romdata <= X"00"; -- .
when 16#52e# => romdata <= X"00"; -- .
when 16#62e# => romdata <= X"00"; -- .
when 16#72e# => romdata <= X"00"; -- .
when 16#82e# => romdata <= X"00"; -- .
when 16#92e# => romdata <= X"10"; -- .
when 16#a2e# => romdata <= X"38"; -- .
when 16#b2e# => romdata <= X"10"; -- .
when 16#c2e# => romdata <= X"00"; -- .
when 16#02f# => romdata <= X"00"; -- /
when 16#12f# => romdata <= X"00"; -- /
when 16#22f# => romdata <= X"02"; -- /
when 16#32f# => romdata <= X"02"; -- /
when 16#42f# => romdata <= X"04"; -- /
when 16#52f# => romdata <= X"08"; -- /
when 16#62f# => romdata <= X"10"; -- /
when 16#72f# => romdata <= X"20"; -- /
when 16#82f# => romdata <= X"40"; -- /
when 16#92f# => romdata <= X"80"; -- /
when 16#a2f# => romdata <= X"80"; -- /
when 16#b2f# => romdata <= X"00"; -- /
when 16#c2f# => romdata <= X"00"; -- /
when 16#030# => romdata <= X"00"; -- 0
when 16#130# => romdata <= X"00"; -- 0
when 16#230# => romdata <= X"18"; -- 0
when 16#330# => romdata <= X"24"; -- 0
when 16#430# => romdata <= X"42"; -- 0
when 16#530# => romdata <= X"42"; -- 0
when 16#630# => romdata <= X"42"; -- 0
when 16#730# => romdata <= X"42"; -- 0
when 16#830# => romdata <= X"42"; -- 0
when 16#930# => romdata <= X"24"; -- 0
when 16#a30# => romdata <= X"18"; -- 0
when 16#b30# => romdata <= X"00"; -- 0
when 16#c30# => romdata <= X"00"; -- 0
when 16#031# => romdata <= X"00"; -- 1
when 16#131# => romdata <= X"00"; -- 1
when 16#231# => romdata <= X"10"; -- 1
when 16#331# => romdata <= X"30"; -- 1
when 16#431# => romdata <= X"50"; -- 1
when 16#531# => romdata <= X"10"; -- 1
when 16#631# => romdata <= X"10"; -- 1
when 16#731# => romdata <= X"10"; -- 1
when 16#831# => romdata <= X"10"; -- 1
when 16#931# => romdata <= X"10"; -- 1
when 16#a31# => romdata <= X"7c"; -- 1
when 16#b31# => romdata <= X"00"; -- 1
when 16#c31# => romdata <= X"00"; -- 1
when 16#032# => romdata <= X"00"; -- 2
when 16#132# => romdata <= X"00"; -- 2
when 16#232# => romdata <= X"3c"; -- 2
when 16#332# => romdata <= X"42"; -- 2
when 16#432# => romdata <= X"42"; -- 2
when 16#532# => romdata <= X"02"; -- 2
when 16#632# => romdata <= X"04"; -- 2
when 16#732# => romdata <= X"18"; -- 2
when 16#832# => romdata <= X"20"; -- 2
when 16#932# => romdata <= X"40"; -- 2
when 16#a32# => romdata <= X"7e"; -- 2
when 16#b32# => romdata <= X"00"; -- 2
when 16#c32# => romdata <= X"00"; -- 2
when 16#033# => romdata <= X"00"; -- 3
when 16#133# => romdata <= X"00"; -- 3
when 16#233# => romdata <= X"7e"; -- 3
when 16#333# => romdata <= X"02"; -- 3
when 16#433# => romdata <= X"04"; -- 3
when 16#533# => romdata <= X"08"; -- 3
when 16#633# => romdata <= X"1c"; -- 3
when 16#733# => romdata <= X"02"; -- 3
when 16#833# => romdata <= X"02"; -- 3
when 16#933# => romdata <= X"42"; -- 3
when 16#a33# => romdata <= X"3c"; -- 3
when 16#b33# => romdata <= X"00"; -- 3
when 16#c33# => romdata <= X"00"; -- 3
when 16#034# => romdata <= X"00"; -- 4
when 16#134# => romdata <= X"00"; -- 4
when 16#234# => romdata <= X"04"; -- 4
when 16#334# => romdata <= X"0c"; -- 4
when 16#434# => romdata <= X"14"; -- 4
when 16#534# => romdata <= X"24"; -- 4
when 16#634# => romdata <= X"44"; -- 4
when 16#734# => romdata <= X"44"; -- 4
when 16#834# => romdata <= X"7e"; -- 4
when 16#934# => romdata <= X"04"; -- 4
when 16#a34# => romdata <= X"04"; -- 4
when 16#b34# => romdata <= X"00"; -- 4
when 16#c34# => romdata <= X"00"; -- 4
when 16#035# => romdata <= X"00"; -- 5
when 16#135# => romdata <= X"00"; -- 5
when 16#235# => romdata <= X"7e"; -- 5
when 16#335# => romdata <= X"40"; -- 5
when 16#435# => romdata <= X"40"; -- 5
when 16#535# => romdata <= X"5c"; -- 5
when 16#635# => romdata <= X"62"; -- 5
when 16#735# => romdata <= X"02"; -- 5
when 16#835# => romdata <= X"02"; -- 5
when 16#935# => romdata <= X"42"; -- 5
when 16#a35# => romdata <= X"3c"; -- 5
when 16#b35# => romdata <= X"00"; -- 5
when 16#c35# => romdata <= X"00"; -- 5
when 16#036# => romdata <= X"00"; -- 6
when 16#136# => romdata <= X"00"; -- 6
when 16#236# => romdata <= X"1c"; -- 6
when 16#336# => romdata <= X"20"; -- 6
when 16#436# => romdata <= X"40"; -- 6
when 16#536# => romdata <= X"40"; -- 6
when 16#636# => romdata <= X"5c"; -- 6
when 16#736# => romdata <= X"62"; -- 6
when 16#836# => romdata <= X"42"; -- 6
when 16#936# => romdata <= X"42"; -- 6
when 16#a36# => romdata <= X"3c"; -- 6
when 16#b36# => romdata <= X"00"; -- 6
when 16#c36# => romdata <= X"00"; -- 6
when 16#037# => romdata <= X"00"; -- 7
when 16#137# => romdata <= X"00"; -- 7
when 16#237# => romdata <= X"7e"; -- 7
when 16#337# => romdata <= X"02"; -- 7
when 16#437# => romdata <= X"04"; -- 7
when 16#537# => romdata <= X"08"; -- 7
when 16#637# => romdata <= X"08"; -- 7
when 16#737# => romdata <= X"10"; -- 7
when 16#837# => romdata <= X"10"; -- 7
when 16#937# => romdata <= X"20"; -- 7
when 16#a37# => romdata <= X"20"; -- 7
when 16#b37# => romdata <= X"00"; -- 7
when 16#c37# => romdata <= X"00"; -- 7
when 16#038# => romdata <= X"00"; -- 8
when 16#138# => romdata <= X"00"; -- 8
when 16#238# => romdata <= X"3c"; -- 8
when 16#338# => romdata <= X"42"; -- 8
when 16#438# => romdata <= X"42"; -- 8
when 16#538# => romdata <= X"42"; -- 8
when 16#638# => romdata <= X"3c"; -- 8
when 16#738# => romdata <= X"42"; -- 8
when 16#838# => romdata <= X"42"; -- 8
when 16#938# => romdata <= X"42"; -- 8
when 16#a38# => romdata <= X"3c"; -- 8
when 16#b38# => romdata <= X"00"; -- 8
when 16#c38# => romdata <= X"00"; -- 8
when 16#039# => romdata <= X"00"; -- 9
when 16#139# => romdata <= X"00"; -- 9
when 16#239# => romdata <= X"3c"; -- 9
when 16#339# => romdata <= X"42"; -- 9
when 16#439# => romdata <= X"42"; -- 9
when 16#539# => romdata <= X"46"; -- 9
when 16#639# => romdata <= X"3a"; -- 9
when 16#739# => romdata <= X"02"; -- 9
when 16#839# => romdata <= X"02"; -- 9
when 16#939# => romdata <= X"04"; -- 9
when 16#a39# => romdata <= X"38"; -- 9
when 16#b39# => romdata <= X"00"; -- 9
when 16#c39# => romdata <= X"00"; -- 9
when 16#03a# => romdata <= X"00"; -- :
when 16#13a# => romdata <= X"00"; -- :
when 16#23a# => romdata <= X"00"; -- :
when 16#33a# => romdata <= X"00"; -- :
when 16#43a# => romdata <= X"10"; -- :
when 16#53a# => romdata <= X"38"; -- :
when 16#63a# => romdata <= X"10"; -- :
when 16#73a# => romdata <= X"00"; -- :
when 16#83a# => romdata <= X"00"; -- :
when 16#93a# => romdata <= X"10"; -- :
when 16#a3a# => romdata <= X"38"; -- :
when 16#b3a# => romdata <= X"10"; -- :
when 16#c3a# => romdata <= X"00"; -- :
when 16#03b# => romdata <= X"00"; -- ;
when 16#13b# => romdata <= X"00"; -- ;
when 16#23b# => romdata <= X"00"; -- ;
when 16#33b# => romdata <= X"00"; -- ;
when 16#43b# => romdata <= X"10"; -- ;
when 16#53b# => romdata <= X"38"; -- ;
when 16#63b# => romdata <= X"10"; -- ;
when 16#73b# => romdata <= X"00"; -- ;
when 16#83b# => romdata <= X"00"; -- ;
when 16#93b# => romdata <= X"38"; -- ;
when 16#a3b# => romdata <= X"30"; -- ;
when 16#b3b# => romdata <= X"40"; -- ;
when 16#c3b# => romdata <= X"00"; -- ;
when 16#03c# => romdata <= X"00"; -- <
when 16#13c# => romdata <= X"00"; -- <
when 16#23c# => romdata <= X"02"; -- <
when 16#33c# => romdata <= X"04"; -- <
when 16#43c# => romdata <= X"08"; -- <
when 16#53c# => romdata <= X"10"; -- <
when 16#63c# => romdata <= X"20"; -- <
when 16#73c# => romdata <= X"10"; -- <
when 16#83c# => romdata <= X"08"; -- <
when 16#93c# => romdata <= X"04"; -- <
when 16#a3c# => romdata <= X"02"; -- <
when 16#b3c# => romdata <= X"00"; -- <
when 16#c3c# => romdata <= X"00"; -- <
when 16#03d# => romdata <= X"00"; -- =
when 16#13d# => romdata <= X"00"; -- =
when 16#23d# => romdata <= X"00"; -- =
when 16#33d# => romdata <= X"00"; -- =
when 16#43d# => romdata <= X"00"; -- =
when 16#53d# => romdata <= X"7e"; -- =
when 16#63d# => romdata <= X"00"; -- =
when 16#73d# => romdata <= X"00"; -- =
when 16#83d# => romdata <= X"7e"; -- =
when 16#93d# => romdata <= X"00"; -- =
when 16#a3d# => romdata <= X"00"; -- =
when 16#b3d# => romdata <= X"00"; -- =
when 16#c3d# => romdata <= X"00"; -- =
when 16#03e# => romdata <= X"00"; -- >
when 16#13e# => romdata <= X"00"; -- >
when 16#23e# => romdata <= X"40"; -- >
when 16#33e# => romdata <= X"20"; -- >
when 16#43e# => romdata <= X"10"; -- >
when 16#53e# => romdata <= X"08"; -- >
when 16#63e# => romdata <= X"04"; -- >
when 16#73e# => romdata <= X"08"; -- >
when 16#83e# => romdata <= X"10"; -- >
when 16#93e# => romdata <= X"20"; -- >
when 16#a3e# => romdata <= X"40"; -- >
when 16#b3e# => romdata <= X"00"; -- >
when 16#c3e# => romdata <= X"00"; -- >
when 16#03f# => romdata <= X"00"; -- ?
when 16#13f# => romdata <= X"00"; -- ?
when 16#23f# => romdata <= X"3c"; -- ?
when 16#33f# => romdata <= X"42"; -- ?
when 16#43f# => romdata <= X"42"; -- ?
when 16#53f# => romdata <= X"02"; -- ?
when 16#63f# => romdata <= X"04"; -- ?
when 16#73f# => romdata <= X"08"; -- ?
when 16#83f# => romdata <= X"08"; -- ?
when 16#93f# => romdata <= X"00"; -- ?
when 16#a3f# => romdata <= X"08"; -- ?
when 16#b3f# => romdata <= X"00"; -- ?
when 16#c3f# => romdata <= X"00"; -- ?
when 16#040# => romdata <= X"00"; -- @
when 16#140# => romdata <= X"00"; -- @
when 16#240# => romdata <= X"3c"; -- @
when 16#340# => romdata <= X"42"; -- @
when 16#440# => romdata <= X"42"; -- @
when 16#540# => romdata <= X"4e"; -- @
when 16#640# => romdata <= X"52"; -- @
when 16#740# => romdata <= X"56"; -- @
when 16#840# => romdata <= X"4a"; -- @
when 16#940# => romdata <= X"40"; -- @
when 16#a40# => romdata <= X"3c"; -- @
when 16#b40# => romdata <= X"00"; -- @
when 16#c40# => romdata <= X"00"; -- @
when 16#041# => romdata <= X"00"; -- A
when 16#141# => romdata <= X"00"; -- A
when 16#241# => romdata <= X"18"; -- A
when 16#341# => romdata <= X"24"; -- A
when 16#441# => romdata <= X"42"; -- A
when 16#541# => romdata <= X"42"; -- A
when 16#641# => romdata <= X"42"; -- A
when 16#741# => romdata <= X"7e"; -- A
when 16#841# => romdata <= X"42"; -- A
when 16#941# => romdata <= X"42"; -- A
when 16#a41# => romdata <= X"42"; -- A
when 16#b41# => romdata <= X"00"; -- A
when 16#c41# => romdata <= X"00"; -- A
when 16#042# => romdata <= X"00"; -- B
when 16#142# => romdata <= X"00"; -- B
when 16#242# => romdata <= X"78"; -- B
when 16#342# => romdata <= X"44"; -- B
when 16#442# => romdata <= X"42"; -- B
when 16#542# => romdata <= X"44"; -- B
when 16#642# => romdata <= X"78"; -- B
when 16#742# => romdata <= X"44"; -- B
when 16#842# => romdata <= X"42"; -- B
when 16#942# => romdata <= X"44"; -- B
when 16#a42# => romdata <= X"78"; -- B
when 16#b42# => romdata <= X"00"; -- B
when 16#c42# => romdata <= X"00"; -- B
when 16#043# => romdata <= X"00"; -- C
when 16#143# => romdata <= X"00"; -- C
when 16#243# => romdata <= X"3c"; -- C
when 16#343# => romdata <= X"42"; -- C
when 16#443# => romdata <= X"40"; -- C
when 16#543# => romdata <= X"40"; -- C
when 16#643# => romdata <= X"40"; -- C
when 16#743# => romdata <= X"40"; -- C
when 16#843# => romdata <= X"40"; -- C
when 16#943# => romdata <= X"42"; -- C
when 16#a43# => romdata <= X"3c"; -- C
when 16#b43# => romdata <= X"00"; -- C
when 16#c43# => romdata <= X"00"; -- C
when 16#044# => romdata <= X"00"; -- D
when 16#144# => romdata <= X"00"; -- D
when 16#244# => romdata <= X"78"; -- D
when 16#344# => romdata <= X"44"; -- D
when 16#444# => romdata <= X"42"; -- D
when 16#544# => romdata <= X"42"; -- D
when 16#644# => romdata <= X"42"; -- D
when 16#744# => romdata <= X"42"; -- D
when 16#844# => romdata <= X"42"; -- D
when 16#944# => romdata <= X"44"; -- D
when 16#a44# => romdata <= X"78"; -- D
when 16#b44# => romdata <= X"00"; -- D
when 16#c44# => romdata <= X"00"; -- D
when 16#045# => romdata <= X"00"; -- E
when 16#145# => romdata <= X"00"; -- E
when 16#245# => romdata <= X"7e"; -- E
when 16#345# => romdata <= X"40"; -- E
when 16#445# => romdata <= X"40"; -- E
when 16#545# => romdata <= X"40"; -- E
when 16#645# => romdata <= X"78"; -- E
when 16#745# => romdata <= X"40"; -- E
when 16#845# => romdata <= X"40"; -- E
when 16#945# => romdata <= X"40"; -- E
when 16#a45# => romdata <= X"7e"; -- E
when 16#b45# => romdata <= X"00"; -- E
when 16#c45# => romdata <= X"00"; -- E
when 16#046# => romdata <= X"00"; -- F
when 16#146# => romdata <= X"00"; -- F
when 16#246# => romdata <= X"7e"; -- F
when 16#346# => romdata <= X"40"; -- F
when 16#446# => romdata <= X"40"; -- F
when 16#546# => romdata <= X"40"; -- F
when 16#646# => romdata <= X"78"; -- F
when 16#746# => romdata <= X"40"; -- F
when 16#846# => romdata <= X"40"; -- F
when 16#946# => romdata <= X"40"; -- F
when 16#a46# => romdata <= X"40"; -- F
when 16#b46# => romdata <= X"00"; -- F
when 16#c46# => romdata <= X"00"; -- F
when 16#047# => romdata <= X"00"; -- G
when 16#147# => romdata <= X"00"; -- G
when 16#247# => romdata <= X"3c"; -- G
when 16#347# => romdata <= X"42"; -- G
when 16#447# => romdata <= X"40"; -- G
when 16#547# => romdata <= X"40"; -- G
when 16#647# => romdata <= X"40"; -- G
when 16#747# => romdata <= X"4e"; -- G
when 16#847# => romdata <= X"42"; -- G
when 16#947# => romdata <= X"46"; -- G
when 16#a47# => romdata <= X"3a"; -- G
when 16#b47# => romdata <= X"00"; -- G
when 16#c47# => romdata <= X"00"; -- G
when 16#048# => romdata <= X"00"; -- H
when 16#148# => romdata <= X"00"; -- H
when 16#248# => romdata <= X"42"; -- H
when 16#348# => romdata <= X"42"; -- H
when 16#448# => romdata <= X"42"; -- H
when 16#548# => romdata <= X"42"; -- H
when 16#648# => romdata <= X"7e"; -- H
when 16#748# => romdata <= X"42"; -- H
when 16#848# => romdata <= X"42"; -- H
when 16#948# => romdata <= X"42"; -- H
when 16#a48# => romdata <= X"42"; -- H
when 16#b48# => romdata <= X"00"; -- H
when 16#c48# => romdata <= X"00"; -- H
when 16#049# => romdata <= X"00"; -- I
when 16#149# => romdata <= X"00"; -- I
when 16#249# => romdata <= X"7c"; -- I
when 16#349# => romdata <= X"10"; -- I
when 16#449# => romdata <= X"10"; -- I
when 16#549# => romdata <= X"10"; -- I
when 16#649# => romdata <= X"10"; -- I
when 16#749# => romdata <= X"10"; -- I
when 16#849# => romdata <= X"10"; -- I
when 16#949# => romdata <= X"10"; -- I
when 16#a49# => romdata <= X"7c"; -- I
when 16#b49# => romdata <= X"00"; -- I
when 16#c49# => romdata <= X"00"; -- I
when 16#04a# => romdata <= X"00"; -- J
when 16#14a# => romdata <= X"00"; -- J
when 16#24a# => romdata <= X"1f"; -- J
when 16#34a# => romdata <= X"04"; -- J
when 16#44a# => romdata <= X"04"; -- J
when 16#54a# => romdata <= X"04"; -- J
when 16#64a# => romdata <= X"04"; -- J
when 16#74a# => romdata <= X"04"; -- J
when 16#84a# => romdata <= X"04"; -- J
when 16#94a# => romdata <= X"44"; -- J
when 16#a4a# => romdata <= X"38"; -- J
when 16#b4a# => romdata <= X"00"; -- J
when 16#c4a# => romdata <= X"00"; -- J
when 16#04b# => romdata <= X"00"; -- K
when 16#14b# => romdata <= X"00"; -- K
when 16#24b# => romdata <= X"42"; -- K
when 16#34b# => romdata <= X"44"; -- K
when 16#44b# => romdata <= X"48"; -- K
when 16#54b# => romdata <= X"50"; -- K
when 16#64b# => romdata <= X"60"; -- K
when 16#74b# => romdata <= X"50"; -- K
when 16#84b# => romdata <= X"48"; -- K
when 16#94b# => romdata <= X"44"; -- K
when 16#a4b# => romdata <= X"42"; -- K
when 16#b4b# => romdata <= X"00"; -- K
when 16#c4b# => romdata <= X"00"; -- K
when 16#04c# => romdata <= X"00"; -- L
when 16#14c# => romdata <= X"00"; -- L
when 16#24c# => romdata <= X"40"; -- L
when 16#34c# => romdata <= X"40"; -- L
when 16#44c# => romdata <= X"40"; -- L
when 16#54c# => romdata <= X"40"; -- L
when 16#64c# => romdata <= X"40"; -- L
when 16#74c# => romdata <= X"40"; -- L
when 16#84c# => romdata <= X"40"; -- L
when 16#94c# => romdata <= X"40"; -- L
when 16#a4c# => romdata <= X"7e"; -- L
when 16#b4c# => romdata <= X"00"; -- L
when 16#c4c# => romdata <= X"00"; -- L
when 16#04d# => romdata <= X"00"; -- M
when 16#14d# => romdata <= X"00"; -- M
when 16#24d# => romdata <= X"82"; -- M
when 16#34d# => romdata <= X"82"; -- M
when 16#44d# => romdata <= X"c6"; -- M
when 16#54d# => romdata <= X"aa"; -- M
when 16#64d# => romdata <= X"92"; -- M
when 16#74d# => romdata <= X"92"; -- M
when 16#84d# => romdata <= X"82"; -- M
when 16#94d# => romdata <= X"82"; -- M
when 16#a4d# => romdata <= X"82"; -- M
when 16#b4d# => romdata <= X"00"; -- M
when 16#c4d# => romdata <= X"00"; -- M
when 16#04e# => romdata <= X"00"; -- N
when 16#14e# => romdata <= X"00"; -- N
when 16#24e# => romdata <= X"42"; -- N
when 16#34e# => romdata <= X"42"; -- N
when 16#44e# => romdata <= X"62"; -- N
when 16#54e# => romdata <= X"52"; -- N
when 16#64e# => romdata <= X"4a"; -- N
when 16#74e# => romdata <= X"46"; -- N
when 16#84e# => romdata <= X"42"; -- N
when 16#94e# => romdata <= X"42"; -- N
when 16#a4e# => romdata <= X"42"; -- N
when 16#b4e# => romdata <= X"00"; -- N
when 16#c4e# => romdata <= X"00"; -- N
when 16#04f# => romdata <= X"00"; -- O
when 16#14f# => romdata <= X"00"; -- O
when 16#24f# => romdata <= X"3c"; -- O
when 16#34f# => romdata <= X"42"; -- O
when 16#44f# => romdata <= X"42"; -- O
when 16#54f# => romdata <= X"42"; -- O
when 16#64f# => romdata <= X"42"; -- O
when 16#74f# => romdata <= X"42"; -- O
when 16#84f# => romdata <= X"42"; -- O
when 16#94f# => romdata <= X"42"; -- O
when 16#a4f# => romdata <= X"3c"; -- O
when 16#b4f# => romdata <= X"00"; -- O
when 16#c4f# => romdata <= X"00"; -- O
when 16#050# => romdata <= X"00"; -- P
when 16#150# => romdata <= X"00"; -- P
when 16#250# => romdata <= X"7c"; -- P
when 16#350# => romdata <= X"42"; -- P
when 16#450# => romdata <= X"42"; -- P
when 16#550# => romdata <= X"42"; -- P
when 16#650# => romdata <= X"7c"; -- P
when 16#750# => romdata <= X"40"; -- P
when 16#850# => romdata <= X"40"; -- P
when 16#950# => romdata <= X"40"; -- P
when 16#a50# => romdata <= X"40"; -- P
when 16#b50# => romdata <= X"00"; -- P
when 16#c50# => romdata <= X"00"; -- P
when 16#051# => romdata <= X"00"; -- Q
when 16#151# => romdata <= X"00"; -- Q
when 16#251# => romdata <= X"3c"; -- Q
when 16#351# => romdata <= X"42"; -- Q
when 16#451# => romdata <= X"42"; -- Q
when 16#551# => romdata <= X"42"; -- Q
when 16#651# => romdata <= X"42"; -- Q
when 16#751# => romdata <= X"42"; -- Q
when 16#851# => romdata <= X"52"; -- Q
when 16#951# => romdata <= X"4a"; -- Q
when 16#a51# => romdata <= X"3c"; -- Q
when 16#b51# => romdata <= X"02"; -- Q
when 16#c51# => romdata <= X"00"; -- Q
when 16#052# => romdata <= X"00"; -- R
when 16#152# => romdata <= X"00"; -- R
when 16#252# => romdata <= X"7c"; -- R
when 16#352# => romdata <= X"42"; -- R
when 16#452# => romdata <= X"42"; -- R
when 16#552# => romdata <= X"42"; -- R
when 16#652# => romdata <= X"7c"; -- R
when 16#752# => romdata <= X"50"; -- R
when 16#852# => romdata <= X"48"; -- R
when 16#952# => romdata <= X"44"; -- R
when 16#a52# => romdata <= X"42"; -- R
when 16#b52# => romdata <= X"00"; -- R
when 16#c52# => romdata <= X"00"; -- R
when 16#053# => romdata <= X"00"; -- S
when 16#153# => romdata <= X"00"; -- S
when 16#253# => romdata <= X"3c"; -- S
when 16#353# => romdata <= X"42"; -- S
when 16#453# => romdata <= X"40"; -- S
when 16#553# => romdata <= X"40"; -- S
when 16#653# => romdata <= X"3c"; -- S
when 16#753# => romdata <= X"02"; -- S
when 16#853# => romdata <= X"02"; -- S
when 16#953# => romdata <= X"42"; -- S
when 16#a53# => romdata <= X"3c"; -- S
when 16#b53# => romdata <= X"00"; -- S
when 16#c53# => romdata <= X"00"; -- S
when 16#054# => romdata <= X"00"; -- T
when 16#154# => romdata <= X"00"; -- T
when 16#254# => romdata <= X"fe"; -- T
when 16#354# => romdata <= X"10"; -- T
when 16#454# => romdata <= X"10"; -- T
when 16#554# => romdata <= X"10"; -- T
when 16#654# => romdata <= X"10"; -- T
when 16#754# => romdata <= X"10"; -- T
when 16#854# => romdata <= X"10"; -- T
when 16#954# => romdata <= X"10"; -- T
when 16#a54# => romdata <= X"10"; -- T
when 16#b54# => romdata <= X"00"; -- T
when 16#c54# => romdata <= X"00"; -- T
when 16#055# => romdata <= X"00"; -- U
when 16#155# => romdata <= X"00"; -- U
when 16#255# => romdata <= X"42"; -- U
when 16#355# => romdata <= X"42"; -- U
when 16#455# => romdata <= X"42"; -- U
when 16#555# => romdata <= X"42"; -- U
when 16#655# => romdata <= X"42"; -- U
when 16#755# => romdata <= X"42"; -- U
when 16#855# => romdata <= X"42"; -- U
when 16#955# => romdata <= X"42"; -- U
when 16#a55# => romdata <= X"3c"; -- U
when 16#b55# => romdata <= X"00"; -- U
when 16#c55# => romdata <= X"00"; -- U
when 16#056# => romdata <= X"00"; -- V
when 16#156# => romdata <= X"00"; -- V
when 16#256# => romdata <= X"82"; -- V
when 16#356# => romdata <= X"82"; -- V
when 16#456# => romdata <= X"44"; -- V
when 16#556# => romdata <= X"44"; -- V
when 16#656# => romdata <= X"44"; -- V
when 16#756# => romdata <= X"28"; -- V
when 16#856# => romdata <= X"28"; -- V
when 16#956# => romdata <= X"28"; -- V
when 16#a56# => romdata <= X"10"; -- V
when 16#b56# => romdata <= X"00"; -- V
when 16#c56# => romdata <= X"00"; -- V
when 16#057# => romdata <= X"00"; -- W
when 16#157# => romdata <= X"00"; -- W
when 16#257# => romdata <= X"82"; -- W
when 16#357# => romdata <= X"82"; -- W
when 16#457# => romdata <= X"82"; -- W
when 16#557# => romdata <= X"82"; -- W
when 16#657# => romdata <= X"92"; -- W
when 16#757# => romdata <= X"92"; -- W
when 16#857# => romdata <= X"92"; -- W
when 16#957# => romdata <= X"aa"; -- W
when 16#a57# => romdata <= X"44"; -- W
when 16#b57# => romdata <= X"00"; -- W
when 16#c57# => romdata <= X"00"; -- W
when 16#058# => romdata <= X"00"; -- X
when 16#158# => romdata <= X"00"; -- X
when 16#258# => romdata <= X"82"; -- X
when 16#358# => romdata <= X"82"; -- X
when 16#458# => romdata <= X"44"; -- X
when 16#558# => romdata <= X"28"; -- X
when 16#658# => romdata <= X"10"; -- X
when 16#758# => romdata <= X"28"; -- X
when 16#858# => romdata <= X"44"; -- X
when 16#958# => romdata <= X"82"; -- X
when 16#a58# => romdata <= X"82"; -- X
when 16#b58# => romdata <= X"00"; -- X
when 16#c58# => romdata <= X"00"; -- X
when 16#059# => romdata <= X"00"; -- Y
when 16#159# => romdata <= X"00"; -- Y
when 16#259# => romdata <= X"82"; -- Y
when 16#359# => romdata <= X"82"; -- Y
when 16#459# => romdata <= X"44"; -- Y
when 16#559# => romdata <= X"28"; -- Y
when 16#659# => romdata <= X"10"; -- Y
when 16#759# => romdata <= X"10"; -- Y
when 16#859# => romdata <= X"10"; -- Y
when 16#959# => romdata <= X"10"; -- Y
when 16#a59# => romdata <= X"10"; -- Y
when 16#b59# => romdata <= X"00"; -- Y
when 16#c59# => romdata <= X"00"; -- Y
when 16#05a# => romdata <= X"00"; -- Z
when 16#15a# => romdata <= X"00"; -- Z
when 16#25a# => romdata <= X"7e"; -- Z
when 16#35a# => romdata <= X"02"; -- Z
when 16#45a# => romdata <= X"04"; -- Z
when 16#55a# => romdata <= X"08"; -- Z
when 16#65a# => romdata <= X"10"; -- Z
when 16#75a# => romdata <= X"20"; -- Z
when 16#85a# => romdata <= X"40"; -- Z
when 16#95a# => romdata <= X"40"; -- Z
when 16#a5a# => romdata <= X"7e"; -- Z
when 16#b5a# => romdata <= X"00"; -- Z
when 16#c5a# => romdata <= X"00"; -- Z
when 16#05b# => romdata <= X"00"; -- [
when 16#15b# => romdata <= X"00"; -- [
when 16#25b# => romdata <= X"3c"; -- [
when 16#35b# => romdata <= X"20"; -- [
when 16#45b# => romdata <= X"20"; -- [
when 16#55b# => romdata <= X"20"; -- [
when 16#65b# => romdata <= X"20"; -- [
when 16#75b# => romdata <= X"20"; -- [
when 16#85b# => romdata <= X"20"; -- [
when 16#95b# => romdata <= X"20"; -- [
when 16#a5b# => romdata <= X"3c"; -- [
when 16#b5b# => romdata <= X"00"; -- [
when 16#c5b# => romdata <= X"00"; -- [
when 16#05c# => romdata <= X"00"; -- \
when 16#15c# => romdata <= X"00"; -- \
when 16#25c# => romdata <= X"80"; -- \
when 16#35c# => romdata <= X"80"; -- \
when 16#45c# => romdata <= X"40"; -- \
when 16#55c# => romdata <= X"20"; -- \
when 16#65c# => romdata <= X"10"; -- \
when 16#75c# => romdata <= X"08"; -- \
when 16#85c# => romdata <= X"04"; -- \
when 16#95c# => romdata <= X"02"; -- \
when 16#a5c# => romdata <= X"02"; -- \
when 16#b5c# => romdata <= X"00"; -- \
when 16#c5c# => romdata <= X"00"; -- \
when 16#05d# => romdata <= X"00"; -- ]
when 16#15d# => romdata <= X"00"; -- ]
when 16#25d# => romdata <= X"78"; -- ]
when 16#35d# => romdata <= X"08"; -- ]
when 16#45d# => romdata <= X"08"; -- ]
when 16#55d# => romdata <= X"08"; -- ]
when 16#65d# => romdata <= X"08"; -- ]
when 16#75d# => romdata <= X"08"; -- ]
when 16#85d# => romdata <= X"08"; -- ]
when 16#95d# => romdata <= X"08"; -- ]
when 16#a5d# => romdata <= X"78"; -- ]
when 16#b5d# => romdata <= X"00"; -- ]
when 16#c5d# => romdata <= X"00"; -- ]
when 16#05e# => romdata <= X"00"; -- ^
when 16#15e# => romdata <= X"00"; -- ^
when 16#25e# => romdata <= X"10"; -- ^
when 16#35e# => romdata <= X"28"; -- ^
when 16#45e# => romdata <= X"44"; -- ^
when 16#55e# => romdata <= X"00"; -- ^
when 16#65e# => romdata <= X"00"; -- ^
when 16#75e# => romdata <= X"00"; -- ^
when 16#85e# => romdata <= X"00"; -- ^
when 16#95e# => romdata <= X"00"; -- ^
when 16#a5e# => romdata <= X"00"; -- ^
when 16#b5e# => romdata <= X"00"; -- ^
when 16#c5e# => romdata <= X"00"; -- ^
when 16#05f# => romdata <= X"00"; -- _
when 16#15f# => romdata <= X"00"; -- _
when 16#25f# => romdata <= X"00"; -- _
when 16#35f# => romdata <= X"00"; -- _
when 16#45f# => romdata <= X"00"; -- _
when 16#55f# => romdata <= X"00"; -- _
when 16#65f# => romdata <= X"00"; -- _
when 16#75f# => romdata <= X"00"; -- _
when 16#85f# => romdata <= X"00"; -- _
when 16#95f# => romdata <= X"00"; -- _
when 16#a5f# => romdata <= X"00"; -- _
when 16#b5f# => romdata <= X"fe"; -- _
when 16#c5f# => romdata <= X"00"; -- _
when 16#060# => romdata <= X"00"; -- `
when 16#160# => romdata <= X"10"; -- `
when 16#260# => romdata <= X"08"; -- `
when 16#360# => romdata <= X"00"; -- `
when 16#460# => romdata <= X"00"; -- `
when 16#560# => romdata <= X"00"; -- `
when 16#660# => romdata <= X"00"; -- `
when 16#760# => romdata <= X"00"; -- `
when 16#860# => romdata <= X"00"; -- `
when 16#960# => romdata <= X"00"; -- `
when 16#a60# => romdata <= X"00"; -- `
when 16#b60# => romdata <= X"00"; -- `
when 16#c60# => romdata <= X"00"; -- `
when 16#061# => romdata <= X"00"; -- a
when 16#161# => romdata <= X"00"; -- a
when 16#261# => romdata <= X"00"; -- a
when 16#361# => romdata <= X"00"; -- a
when 16#461# => romdata <= X"00"; -- a
when 16#561# => romdata <= X"3c"; -- a
when 16#661# => romdata <= X"02"; -- a
when 16#761# => romdata <= X"3e"; -- a
when 16#861# => romdata <= X"42"; -- a
when 16#961# => romdata <= X"46"; -- a
when 16#a61# => romdata <= X"3a"; -- a
when 16#b61# => romdata <= X"00"; -- a
when 16#c61# => romdata <= X"00"; -- a
when 16#062# => romdata <= X"00"; -- b
when 16#162# => romdata <= X"00"; -- b
when 16#262# => romdata <= X"40"; -- b
when 16#362# => romdata <= X"40"; -- b
when 16#462# => romdata <= X"40"; -- b
when 16#562# => romdata <= X"5c"; -- b
when 16#662# => romdata <= X"62"; -- b
when 16#762# => romdata <= X"42"; -- b
when 16#862# => romdata <= X"42"; -- b
when 16#962# => romdata <= X"62"; -- b
when 16#a62# => romdata <= X"5c"; -- b
when 16#b62# => romdata <= X"00"; -- b
when 16#c62# => romdata <= X"00"; -- b
when 16#063# => romdata <= X"00"; -- c
when 16#163# => romdata <= X"00"; -- c
when 16#263# => romdata <= X"00"; -- c
when 16#363# => romdata <= X"00"; -- c
when 16#463# => romdata <= X"00"; -- c
when 16#563# => romdata <= X"3c"; -- c
when 16#663# => romdata <= X"42"; -- c
when 16#763# => romdata <= X"40"; -- c
when 16#863# => romdata <= X"40"; -- c
when 16#963# => romdata <= X"42"; -- c
when 16#a63# => romdata <= X"3c"; -- c
when 16#b63# => romdata <= X"00"; -- c
when 16#c63# => romdata <= X"00"; -- c
when 16#064# => romdata <= X"00"; -- d
when 16#164# => romdata <= X"00"; -- d
when 16#264# => romdata <= X"02"; -- d
when 16#364# => romdata <= X"02"; -- d
when 16#464# => romdata <= X"02"; -- d
when 16#564# => romdata <= X"3a"; -- d
when 16#664# => romdata <= X"46"; -- d
when 16#764# => romdata <= X"42"; -- d
when 16#864# => romdata <= X"42"; -- d
when 16#964# => romdata <= X"46"; -- d
when 16#a64# => romdata <= X"3a"; -- d
when 16#b64# => romdata <= X"00"; -- d
when 16#c64# => romdata <= X"00"; -- d
when 16#065# => romdata <= X"00"; -- e
when 16#165# => romdata <= X"00"; -- e
when 16#265# => romdata <= X"00"; -- e
when 16#365# => romdata <= X"00"; -- e
when 16#465# => romdata <= X"00"; -- e
when 16#565# => romdata <= X"3c"; -- e
when 16#665# => romdata <= X"42"; -- e
when 16#765# => romdata <= X"7e"; -- e
when 16#865# => romdata <= X"40"; -- e
when 16#965# => romdata <= X"42"; -- e
when 16#a65# => romdata <= X"3c"; -- e
when 16#b65# => romdata <= X"00"; -- e
when 16#c65# => romdata <= X"00"; -- e
when 16#066# => romdata <= X"00"; -- f
when 16#166# => romdata <= X"00"; -- f
when 16#266# => romdata <= X"1c"; -- f
when 16#366# => romdata <= X"22"; -- f
when 16#466# => romdata <= X"20"; -- f
when 16#566# => romdata <= X"20"; -- f
when 16#666# => romdata <= X"7c"; -- f
when 16#766# => romdata <= X"20"; -- f
when 16#866# => romdata <= X"20"; -- f
when 16#966# => romdata <= X"20"; -- f
when 16#a66# => romdata <= X"20"; -- f
when 16#b66# => romdata <= X"00"; -- f
when 16#c66# => romdata <= X"00"; -- f
when 16#067# => romdata <= X"00"; -- g
when 16#167# => romdata <= X"00"; -- g
when 16#267# => romdata <= X"00"; -- g
when 16#367# => romdata <= X"00"; -- g
when 16#467# => romdata <= X"00"; -- g
when 16#567# => romdata <= X"3a"; -- g
when 16#667# => romdata <= X"44"; -- g
when 16#767# => romdata <= X"44"; -- g
when 16#867# => romdata <= X"38"; -- g
when 16#967# => romdata <= X"40"; -- g
when 16#a67# => romdata <= X"3c"; -- g
when 16#b67# => romdata <= X"42"; -- g
when 16#c67# => romdata <= X"3c"; -- g
when 16#068# => romdata <= X"00"; -- h
when 16#168# => romdata <= X"00"; -- h
when 16#268# => romdata <= X"40"; -- h
when 16#368# => romdata <= X"40"; -- h
when 16#468# => romdata <= X"40"; -- h
when 16#568# => romdata <= X"5c"; -- h
when 16#668# => romdata <= X"62"; -- h
when 16#768# => romdata <= X"42"; -- h
when 16#868# => romdata <= X"42"; -- h
when 16#968# => romdata <= X"42"; -- h
when 16#a68# => romdata <= X"42"; -- h
when 16#b68# => romdata <= X"00"; -- h
when 16#c68# => romdata <= X"00"; -- h
when 16#069# => romdata <= X"00"; -- i
when 16#169# => romdata <= X"00"; -- i
when 16#269# => romdata <= X"00"; -- i
when 16#369# => romdata <= X"10"; -- i
when 16#469# => romdata <= X"00"; -- i
when 16#569# => romdata <= X"30"; -- i
when 16#669# => romdata <= X"10"; -- i
when 16#769# => romdata <= X"10"; -- i
when 16#869# => romdata <= X"10"; -- i
when 16#969# => romdata <= X"10"; -- i
when 16#a69# => romdata <= X"7c"; -- i
when 16#b69# => romdata <= X"00"; -- i
when 16#c69# => romdata <= X"00"; -- i
when 16#06a# => romdata <= X"00"; -- j
when 16#16a# => romdata <= X"00"; -- j
when 16#26a# => romdata <= X"00"; -- j
when 16#36a# => romdata <= X"04"; -- j
when 16#46a# => romdata <= X"00"; -- j
when 16#56a# => romdata <= X"0c"; -- j
when 16#66a# => romdata <= X"04"; -- j
when 16#76a# => romdata <= X"04"; -- j
when 16#86a# => romdata <= X"04"; -- j
when 16#96a# => romdata <= X"04"; -- j
when 16#a6a# => romdata <= X"44"; -- j
when 16#b6a# => romdata <= X"44"; -- j
when 16#c6a# => romdata <= X"38"; -- j
when 16#06b# => romdata <= X"00"; -- k
when 16#16b# => romdata <= X"00"; -- k
when 16#26b# => romdata <= X"40"; -- k
when 16#36b# => romdata <= X"40"; -- k
when 16#46b# => romdata <= X"40"; -- k
when 16#56b# => romdata <= X"44"; -- k
when 16#66b# => romdata <= X"48"; -- k
when 16#76b# => romdata <= X"70"; -- k
when 16#86b# => romdata <= X"48"; -- k
when 16#96b# => romdata <= X"44"; -- k
when 16#a6b# => romdata <= X"42"; -- k
when 16#b6b# => romdata <= X"00"; -- k
when 16#c6b# => romdata <= X"00"; -- k
when 16#06c# => romdata <= X"00"; -- l
when 16#16c# => romdata <= X"00"; -- l
when 16#26c# => romdata <= X"30"; -- l
when 16#36c# => romdata <= X"10"; -- l
when 16#46c# => romdata <= X"10"; -- l
when 16#56c# => romdata <= X"10"; -- l
when 16#66c# => romdata <= X"10"; -- l
when 16#76c# => romdata <= X"10"; -- l
when 16#86c# => romdata <= X"10"; -- l
when 16#96c# => romdata <= X"10"; -- l
when 16#a6c# => romdata <= X"7c"; -- l
when 16#b6c# => romdata <= X"00"; -- l
when 16#c6c# => romdata <= X"00"; -- l
when 16#06d# => romdata <= X"00"; -- m
when 16#16d# => romdata <= X"00"; -- m
when 16#26d# => romdata <= X"00"; -- m
when 16#36d# => romdata <= X"00"; -- m
when 16#46d# => romdata <= X"00"; -- m
when 16#56d# => romdata <= X"ec"; -- m
when 16#66d# => romdata <= X"92"; -- m
when 16#76d# => romdata <= X"92"; -- m
when 16#86d# => romdata <= X"92"; -- m
when 16#96d# => romdata <= X"92"; -- m
when 16#a6d# => romdata <= X"82"; -- m
when 16#b6d# => romdata <= X"00"; -- m
when 16#c6d# => romdata <= X"00"; -- m
when 16#06e# => romdata <= X"00"; -- n
when 16#16e# => romdata <= X"00"; -- n
when 16#26e# => romdata <= X"00"; -- n
when 16#36e# => romdata <= X"00"; -- n
when 16#46e# => romdata <= X"00"; -- n
when 16#56e# => romdata <= X"5c"; -- n
when 16#66e# => romdata <= X"62"; -- n
when 16#76e# => romdata <= X"42"; -- n
when 16#86e# => romdata <= X"42"; -- n
when 16#96e# => romdata <= X"42"; -- n
when 16#a6e# => romdata <= X"42"; -- n
when 16#b6e# => romdata <= X"00"; -- n
when 16#c6e# => romdata <= X"00"; -- n
when 16#06f# => romdata <= X"00"; -- o
when 16#16f# => romdata <= X"00"; -- o
when 16#26f# => romdata <= X"00"; -- o
when 16#36f# => romdata <= X"00"; -- o
when 16#46f# => romdata <= X"00"; -- o
when 16#56f# => romdata <= X"3c"; -- o
when 16#66f# => romdata <= X"42"; -- o
when 16#76f# => romdata <= X"42"; -- o
when 16#86f# => romdata <= X"42"; -- o
when 16#96f# => romdata <= X"42"; -- o
when 16#a6f# => romdata <= X"3c"; -- o
when 16#b6f# => romdata <= X"00"; -- o
when 16#c6f# => romdata <= X"00"; -- o
when 16#070# => romdata <= X"00"; -- p
when 16#170# => romdata <= X"00"; -- p
when 16#270# => romdata <= X"00"; -- p
when 16#370# => romdata <= X"00"; -- p
when 16#470# => romdata <= X"00"; -- p
when 16#570# => romdata <= X"5c"; -- p
when 16#670# => romdata <= X"62"; -- p
when 16#770# => romdata <= X"42"; -- p
when 16#870# => romdata <= X"62"; -- p
when 16#970# => romdata <= X"5c"; -- p
when 16#a70# => romdata <= X"40"; -- p
when 16#b70# => romdata <= X"40"; -- p
when 16#c70# => romdata <= X"40"; -- p
when 16#071# => romdata <= X"00"; -- q
when 16#171# => romdata <= X"00"; -- q
when 16#271# => romdata <= X"00"; -- q
when 16#371# => romdata <= X"00"; -- q
when 16#471# => romdata <= X"00"; -- q
when 16#571# => romdata <= X"3a"; -- q
when 16#671# => romdata <= X"46"; -- q
when 16#771# => romdata <= X"42"; -- q
when 16#871# => romdata <= X"46"; -- q
when 16#971# => romdata <= X"3a"; -- q
when 16#a71# => romdata <= X"02"; -- q
when 16#b71# => romdata <= X"02"; -- q
when 16#c71# => romdata <= X"02"; -- q
when 16#072# => romdata <= X"00"; -- r
when 16#172# => romdata <= X"00"; -- r
when 16#272# => romdata <= X"00"; -- r
when 16#372# => romdata <= X"00"; -- r
when 16#472# => romdata <= X"00"; -- r
when 16#572# => romdata <= X"5c"; -- r
when 16#672# => romdata <= X"22"; -- r
when 16#772# => romdata <= X"20"; -- r
when 16#872# => romdata <= X"20"; -- r
when 16#972# => romdata <= X"20"; -- r
when 16#a72# => romdata <= X"20"; -- r
when 16#b72# => romdata <= X"00"; -- r
when 16#c72# => romdata <= X"00"; -- r
when 16#073# => romdata <= X"00"; -- s
when 16#173# => romdata <= X"00"; -- s
when 16#273# => romdata <= X"00"; -- s
when 16#373# => romdata <= X"00"; -- s
when 16#473# => romdata <= X"00"; -- s
when 16#573# => romdata <= X"3c"; -- s
when 16#673# => romdata <= X"42"; -- s
when 16#773# => romdata <= X"30"; -- s
when 16#873# => romdata <= X"0c"; -- s
when 16#973# => romdata <= X"42"; -- s
when 16#a73# => romdata <= X"3c"; -- s
when 16#b73# => romdata <= X"00"; -- s
when 16#c73# => romdata <= X"00"; -- s
when 16#074# => romdata <= X"00"; -- t
when 16#174# => romdata <= X"00"; -- t
when 16#274# => romdata <= X"00"; -- t
when 16#374# => romdata <= X"20"; -- t
when 16#474# => romdata <= X"20"; -- t
when 16#574# => romdata <= X"7c"; -- t
when 16#674# => romdata <= X"20"; -- t
when 16#774# => romdata <= X"20"; -- t
when 16#874# => romdata <= X"20"; -- t
when 16#974# => romdata <= X"22"; -- t
when 16#a74# => romdata <= X"1c"; -- t
when 16#b74# => romdata <= X"00"; -- t
when 16#c74# => romdata <= X"00"; -- t
when 16#075# => romdata <= X"00"; -- u
when 16#175# => romdata <= X"00"; -- u
when 16#275# => romdata <= X"00"; -- u
when 16#375# => romdata <= X"00"; -- u
when 16#475# => romdata <= X"00"; -- u
when 16#575# => romdata <= X"44"; -- u
when 16#675# => romdata <= X"44"; -- u
when 16#775# => romdata <= X"44"; -- u
when 16#875# => romdata <= X"44"; -- u
when 16#975# => romdata <= X"44"; -- u
when 16#a75# => romdata <= X"3a"; -- u
when 16#b75# => romdata <= X"00"; -- u
when 16#c75# => romdata <= X"00"; -- u
when 16#076# => romdata <= X"00"; -- v
when 16#176# => romdata <= X"00"; -- v
when 16#276# => romdata <= X"00"; -- v
when 16#376# => romdata <= X"00"; -- v
when 16#476# => romdata <= X"00"; -- v
when 16#576# => romdata <= X"44"; -- v
when 16#676# => romdata <= X"44"; -- v
when 16#776# => romdata <= X"44"; -- v
when 16#876# => romdata <= X"28"; -- v
when 16#976# => romdata <= X"28"; -- v
when 16#a76# => romdata <= X"10"; -- v
when 16#b76# => romdata <= X"00"; -- v
when 16#c76# => romdata <= X"00"; -- v
when 16#077# => romdata <= X"00"; -- w
when 16#177# => romdata <= X"00"; -- w
when 16#277# => romdata <= X"00"; -- w
when 16#377# => romdata <= X"00"; -- w
when 16#477# => romdata <= X"00"; -- w
when 16#577# => romdata <= X"82"; -- w
when 16#677# => romdata <= X"82"; -- w
when 16#777# => romdata <= X"92"; -- w
when 16#877# => romdata <= X"92"; -- w
when 16#977# => romdata <= X"aa"; -- w
when 16#a77# => romdata <= X"44"; -- w
when 16#b77# => romdata <= X"00"; -- w
when 16#c77# => romdata <= X"00"; -- w
when 16#078# => romdata <= X"00"; -- x
when 16#178# => romdata <= X"00"; -- x
when 16#278# => romdata <= X"00"; -- x
when 16#378# => romdata <= X"00"; -- x
when 16#478# => romdata <= X"00"; -- x
when 16#578# => romdata <= X"42"; -- x
when 16#678# => romdata <= X"24"; -- x
when 16#778# => romdata <= X"18"; -- x
when 16#878# => romdata <= X"18"; -- x
when 16#978# => romdata <= X"24"; -- x
when 16#a78# => romdata <= X"42"; -- x
when 16#b78# => romdata <= X"00"; -- x
when 16#c78# => romdata <= X"00"; -- x
when 16#079# => romdata <= X"00"; -- y
when 16#179# => romdata <= X"00"; -- y
when 16#279# => romdata <= X"00"; -- y
when 16#379# => romdata <= X"00"; -- y
when 16#479# => romdata <= X"00"; -- y
when 16#579# => romdata <= X"42"; -- y
when 16#679# => romdata <= X"42"; -- y
when 16#779# => romdata <= X"42"; -- y
when 16#879# => romdata <= X"46"; -- y
when 16#979# => romdata <= X"3a"; -- y
when 16#a79# => romdata <= X"02"; -- y
when 16#b79# => romdata <= X"42"; -- y
when 16#c79# => romdata <= X"3c"; -- y
when 16#07a# => romdata <= X"00"; -- z
when 16#17a# => romdata <= X"00"; -- z
when 16#27a# => romdata <= X"00"; -- z
when 16#37a# => romdata <= X"00"; -- z
when 16#47a# => romdata <= X"00"; -- z
when 16#57a# => romdata <= X"7e"; -- z
when 16#67a# => romdata <= X"04"; -- z
when 16#77a# => romdata <= X"08"; -- z
when 16#87a# => romdata <= X"10"; -- z
when 16#97a# => romdata <= X"20"; -- z
when 16#a7a# => romdata <= X"7e"; -- z
when 16#b7a# => romdata <= X"00"; -- z
when 16#c7a# => romdata <= X"00"; -- z
when 16#07b# => romdata <= X"00"; -- {
when 16#17b# => romdata <= X"00"; -- {
when 16#27b# => romdata <= X"0e"; -- {
when 16#37b# => romdata <= X"10"; -- {
when 16#47b# => romdata <= X"10"; -- {
when 16#57b# => romdata <= X"08"; -- {
when 16#67b# => romdata <= X"30"; -- {
when 16#77b# => romdata <= X"08"; -- {
when 16#87b# => romdata <= X"10"; -- {
when 16#97b# => romdata <= X"10"; -- {
when 16#a7b# => romdata <= X"0e"; -- {
when 16#b7b# => romdata <= X"00"; -- {
when 16#c7b# => romdata <= X"00"; -- {
when 16#07c# => romdata <= X"00"; -- |
when 16#17c# => romdata <= X"00"; -- |
when 16#27c# => romdata <= X"10"; -- |
when 16#37c# => romdata <= X"10"; -- |
when 16#47c# => romdata <= X"10"; -- |
when 16#57c# => romdata <= X"10"; -- |
when 16#67c# => romdata <= X"10"; -- |
when 16#77c# => romdata <= X"10"; -- |
when 16#87c# => romdata <= X"10"; -- |
when 16#97c# => romdata <= X"10"; -- |
when 16#a7c# => romdata <= X"10"; -- |
when 16#b7c# => romdata <= X"00"; -- |
when 16#c7c# => romdata <= X"00"; -- |
when 16#07d# => romdata <= X"00"; -- }
when 16#17d# => romdata <= X"00"; -- }
when 16#27d# => romdata <= X"70"; -- }
when 16#37d# => romdata <= X"08"; -- }
when 16#47d# => romdata <= X"08"; -- }
when 16#57d# => romdata <= X"10"; -- }
when 16#67d# => romdata <= X"0c"; -- }
when 16#77d# => romdata <= X"10"; -- }
when 16#87d# => romdata <= X"08"; -- }
when 16#97d# => romdata <= X"08"; -- }
when 16#a7d# => romdata <= X"70"; -- }
when 16#b7d# => romdata <= X"00"; -- }
when 16#c7d# => romdata <= X"00"; -- }
when 16#07e# => romdata <= X"00"; -- ~
when 16#17e# => romdata <= X"00"; -- ~
when 16#27e# => romdata <= X"24"; -- ~
when 16#37e# => romdata <= X"54"; -- ~
when 16#47e# => romdata <= X"48"; -- ~
when 16#57e# => romdata <= X"00"; -- ~
when 16#67e# => romdata <= X"00"; -- ~
when 16#77e# => romdata <= X"00"; -- ~
when 16#87e# => romdata <= X"00"; -- ~
when 16#97e# => romdata <= X"00"; -- ~
when 16#a7e# => romdata <= X"00"; -- ~
when 16#b7e# => romdata <= X"00"; -- ~
when 16#c7e# => romdata <= X"00"; -- ~
when 16#0a0# => romdata <= X"00"; --
when 16#1a0# => romdata <= X"00"; --
when 16#2a0# => romdata <= X"00"; --
when 16#3a0# => romdata <= X"00"; --
when 16#4a0# => romdata <= X"00"; --
when 16#5a0# => romdata <= X"00"; --
when 16#6a0# => romdata <= X"00"; --
when 16#7a0# => romdata <= X"00"; --
when 16#8a0# => romdata <= X"00"; --
when 16#9a0# => romdata <= X"00"; --
when 16#aa0# => romdata <= X"00"; --
when 16#ba0# => romdata <= X"00"; --
when 16#ca0# => romdata <= X"00"; --
when 16#0a1# => romdata <= X"00"; -- ¡
when 16#1a1# => romdata <= X"00"; -- ¡
when 16#2a1# => romdata <= X"10"; -- ¡
when 16#3a1# => romdata <= X"00"; -- ¡
when 16#4a1# => romdata <= X"10"; -- ¡
when 16#5a1# => romdata <= X"10"; -- ¡
when 16#6a1# => romdata <= X"10"; -- ¡
when 16#7a1# => romdata <= X"10"; -- ¡
when 16#8a1# => romdata <= X"10"; -- ¡
when 16#9a1# => romdata <= X"10"; -- ¡
when 16#aa1# => romdata <= X"10"; -- ¡
when 16#ba1# => romdata <= X"00"; -- ¡
when 16#ca1# => romdata <= X"00"; -- ¡
when 16#0a2# => romdata <= X"00"; -- ¢
when 16#1a2# => romdata <= X"00"; -- ¢
when 16#2a2# => romdata <= X"10"; -- ¢
when 16#3a2# => romdata <= X"38"; -- ¢
when 16#4a2# => romdata <= X"54"; -- ¢
when 16#5a2# => romdata <= X"50"; -- ¢
when 16#6a2# => romdata <= X"50"; -- ¢
when 16#7a2# => romdata <= X"54"; -- ¢
when 16#8a2# => romdata <= X"38"; -- ¢
when 16#9a2# => romdata <= X"10"; -- ¢
when 16#aa2# => romdata <= X"00"; -- ¢
when 16#ba2# => romdata <= X"00"; -- ¢
when 16#ca2# => romdata <= X"00"; -- ¢
when 16#0a3# => romdata <= X"00"; -- £
when 16#1a3# => romdata <= X"00"; -- £
when 16#2a3# => romdata <= X"1c"; -- £
when 16#3a3# => romdata <= X"22"; -- £
when 16#4a3# => romdata <= X"20"; -- £
when 16#5a3# => romdata <= X"70"; -- £
when 16#6a3# => romdata <= X"20"; -- £
when 16#7a3# => romdata <= X"20"; -- £
when 16#8a3# => romdata <= X"20"; -- £
when 16#9a3# => romdata <= X"62"; -- £
when 16#aa3# => romdata <= X"dc"; -- £
when 16#ba3# => romdata <= X"00"; -- £
when 16#ca3# => romdata <= X"00"; -- £
when 16#0a4# => romdata <= X"00"; -- ¤
when 16#1a4# => romdata <= X"00"; -- ¤
when 16#2a4# => romdata <= X"00"; -- ¤
when 16#3a4# => romdata <= X"00"; -- ¤
when 16#4a4# => romdata <= X"42"; -- ¤
when 16#5a4# => romdata <= X"3c"; -- ¤
when 16#6a4# => romdata <= X"24"; -- ¤
when 16#7a4# => romdata <= X"24"; -- ¤
when 16#8a4# => romdata <= X"3c"; -- ¤
when 16#9a4# => romdata <= X"42"; -- ¤
when 16#aa4# => romdata <= X"00"; -- ¤
when 16#ba4# => romdata <= X"00"; -- ¤
when 16#ca4# => romdata <= X"00"; -- ¤
when 16#0a5# => romdata <= X"00"; -- ¥
when 16#1a5# => romdata <= X"00"; -- ¥
when 16#2a5# => romdata <= X"82"; -- ¥
when 16#3a5# => romdata <= X"82"; -- ¥
when 16#4a5# => romdata <= X"44"; -- ¥
when 16#5a5# => romdata <= X"28"; -- ¥
when 16#6a5# => romdata <= X"7c"; -- ¥
when 16#7a5# => romdata <= X"10"; -- ¥
when 16#8a5# => romdata <= X"7c"; -- ¥
when 16#9a5# => romdata <= X"10"; -- ¥
when 16#aa5# => romdata <= X"10"; -- ¥
when 16#ba5# => romdata <= X"00"; -- ¥
when 16#ca5# => romdata <= X"00"; -- ¥
when 16#0a6# => romdata <= X"00"; -- ¦
when 16#1a6# => romdata <= X"00"; -- ¦
when 16#2a6# => romdata <= X"10"; -- ¦
when 16#3a6# => romdata <= X"10"; -- ¦
when 16#4a6# => romdata <= X"10"; -- ¦
when 16#5a6# => romdata <= X"10"; -- ¦
when 16#6a6# => romdata <= X"00"; -- ¦
when 16#7a6# => romdata <= X"10"; -- ¦
when 16#8a6# => romdata <= X"10"; -- ¦
when 16#9a6# => romdata <= X"10"; -- ¦
when 16#aa6# => romdata <= X"10"; -- ¦
when 16#ba6# => romdata <= X"00"; -- ¦
when 16#ca6# => romdata <= X"00"; -- ¦
when 16#0a7# => romdata <= X"00"; -- §
when 16#1a7# => romdata <= X"18"; -- §
when 16#2a7# => romdata <= X"24"; -- §
when 16#3a7# => romdata <= X"20"; -- §
when 16#4a7# => romdata <= X"18"; -- §
when 16#5a7# => romdata <= X"24"; -- §
when 16#6a7# => romdata <= X"24"; -- §
when 16#7a7# => romdata <= X"18"; -- §
when 16#8a7# => romdata <= X"04"; -- §
when 16#9a7# => romdata <= X"24"; -- §
when 16#aa7# => romdata <= X"18"; -- §
when 16#ba7# => romdata <= X"00"; -- §
when 16#ca7# => romdata <= X"00"; -- §
when 16#0a8# => romdata <= X"00"; -- ¨
when 16#1a8# => romdata <= X"24"; -- ¨
when 16#2a8# => romdata <= X"24"; -- ¨
when 16#3a8# => romdata <= X"00"; -- ¨
when 16#4a8# => romdata <= X"00"; -- ¨
when 16#5a8# => romdata <= X"00"; -- ¨
when 16#6a8# => romdata <= X"00"; -- ¨
when 16#7a8# => romdata <= X"00"; -- ¨
when 16#8a8# => romdata <= X"00"; -- ¨
when 16#9a8# => romdata <= X"00"; -- ¨
when 16#aa8# => romdata <= X"00"; -- ¨
when 16#ba8# => romdata <= X"00"; -- ¨
when 16#ca8# => romdata <= X"00"; -- ¨
when 16#0a9# => romdata <= X"00"; -- ©
when 16#1a9# => romdata <= X"38"; -- ©
when 16#2a9# => romdata <= X"44"; -- ©
when 16#3a9# => romdata <= X"92"; -- ©
when 16#4a9# => romdata <= X"aa"; -- ©
when 16#5a9# => romdata <= X"a2"; -- ©
when 16#6a9# => romdata <= X"aa"; -- ©
when 16#7a9# => romdata <= X"92"; -- ©
when 16#8a9# => romdata <= X"44"; -- ©
when 16#9a9# => romdata <= X"38"; -- ©
when 16#aa9# => romdata <= X"00"; -- ©
when 16#ba9# => romdata <= X"00"; -- ©
when 16#ca9# => romdata <= X"00"; -- ©
when 16#0aa# => romdata <= X"00"; -- ª
when 16#1aa# => romdata <= X"00"; -- ª
when 16#2aa# => romdata <= X"38"; -- ª
when 16#3aa# => romdata <= X"04"; -- ª
when 16#4aa# => romdata <= X"3c"; -- ª
when 16#5aa# => romdata <= X"44"; -- ª
when 16#6aa# => romdata <= X"3c"; -- ª
when 16#7aa# => romdata <= X"00"; -- ª
when 16#8aa# => romdata <= X"7c"; -- ª
when 16#9aa# => romdata <= X"00"; -- ª
when 16#aaa# => romdata <= X"00"; -- ª
when 16#baa# => romdata <= X"00"; -- ª
when 16#caa# => romdata <= X"00"; -- ª
when 16#0ab# => romdata <= X"00"; -- «
when 16#1ab# => romdata <= X"00"; -- «
when 16#2ab# => romdata <= X"00"; -- «
when 16#3ab# => romdata <= X"12"; -- «
when 16#4ab# => romdata <= X"24"; -- «
when 16#5ab# => romdata <= X"48"; -- «
when 16#6ab# => romdata <= X"90"; -- «
when 16#7ab# => romdata <= X"48"; -- «
when 16#8ab# => romdata <= X"24"; -- «
when 16#9ab# => romdata <= X"12"; -- «
when 16#aab# => romdata <= X"00"; -- «
when 16#bab# => romdata <= X"00"; -- «
when 16#cab# => romdata <= X"00"; -- «
when 16#0ac# => romdata <= X"00"; -- ¬
when 16#1ac# => romdata <= X"00"; -- ¬
when 16#2ac# => romdata <= X"00"; -- ¬
when 16#3ac# => romdata <= X"00"; -- ¬
when 16#4ac# => romdata <= X"00"; -- ¬
when 16#5ac# => romdata <= X"00"; -- ¬
when 16#6ac# => romdata <= X"7e"; -- ¬
when 16#7ac# => romdata <= X"02"; -- ¬
when 16#8ac# => romdata <= X"02"; -- ¬
when 16#9ac# => romdata <= X"02"; -- ¬
when 16#aac# => romdata <= X"00"; -- ¬
when 16#bac# => romdata <= X"00"; -- ¬
when 16#cac# => romdata <= X"00"; -- ¬
when 16#0ad# => romdata <= X"00"; --
when 16#1ad# => romdata <= X"00"; --
when 16#2ad# => romdata <= X"00"; --
when 16#3ad# => romdata <= X"00"; --
when 16#4ad# => romdata <= X"00"; --
when 16#5ad# => romdata <= X"00"; --
when 16#6ad# => romdata <= X"3c"; --
when 16#7ad# => romdata <= X"00"; --
when 16#8ad# => romdata <= X"00"; --
when 16#9ad# => romdata <= X"00"; --
when 16#aad# => romdata <= X"00"; --
when 16#bad# => romdata <= X"00"; --
when 16#cad# => romdata <= X"00"; --
when 16#0ae# => romdata <= X"00"; -- ®
when 16#1ae# => romdata <= X"38"; -- ®
when 16#2ae# => romdata <= X"44"; -- ®
when 16#3ae# => romdata <= X"92"; -- ®
when 16#4ae# => romdata <= X"aa"; -- ®
when 16#5ae# => romdata <= X"aa"; -- ®
when 16#6ae# => romdata <= X"b2"; -- ®
when 16#7ae# => romdata <= X"aa"; -- ®
when 16#8ae# => romdata <= X"44"; -- ®
when 16#9ae# => romdata <= X"38"; -- ®
when 16#aae# => romdata <= X"00"; -- ®
when 16#bae# => romdata <= X"00"; -- ®
when 16#cae# => romdata <= X"00"; -- ®
when 16#0af# => romdata <= X"00"; -- ¯
when 16#1af# => romdata <= X"00"; -- ¯
when 16#2af# => romdata <= X"7e"; -- ¯
when 16#3af# => romdata <= X"00"; -- ¯
when 16#4af# => romdata <= X"00"; -- ¯
when 16#5af# => romdata <= X"00"; -- ¯
when 16#6af# => romdata <= X"00"; -- ¯
when 16#7af# => romdata <= X"00"; -- ¯
when 16#8af# => romdata <= X"00"; -- ¯
when 16#9af# => romdata <= X"00"; -- ¯
when 16#aaf# => romdata <= X"00"; -- ¯
when 16#baf# => romdata <= X"00"; -- ¯
when 16#caf# => romdata <= X"00"; -- ¯
when 16#0b0# => romdata <= X"00"; -- °
when 16#1b0# => romdata <= X"00"; -- °
when 16#2b0# => romdata <= X"18"; -- °
when 16#3b0# => romdata <= X"24"; -- °
when 16#4b0# => romdata <= X"24"; -- °
when 16#5b0# => romdata <= X"18"; -- °
when 16#6b0# => romdata <= X"00"; -- °
when 16#7b0# => romdata <= X"00"; -- °
when 16#8b0# => romdata <= X"00"; -- °
when 16#9b0# => romdata <= X"00"; -- °
when 16#ab0# => romdata <= X"00"; -- °
when 16#bb0# => romdata <= X"00"; -- °
when 16#cb0# => romdata <= X"00"; -- °
when 16#0b1# => romdata <= X"00"; -- ±
when 16#1b1# => romdata <= X"00"; -- ±
when 16#2b1# => romdata <= X"00"; -- ±
when 16#3b1# => romdata <= X"10"; -- ±
when 16#4b1# => romdata <= X"10"; -- ±
when 16#5b1# => romdata <= X"7c"; -- ±
when 16#6b1# => romdata <= X"10"; -- ±
when 16#7b1# => romdata <= X"10"; -- ±
when 16#8b1# => romdata <= X"00"; -- ±
when 16#9b1# => romdata <= X"7c"; -- ±
when 16#ab1# => romdata <= X"00"; -- ±
when 16#bb1# => romdata <= X"00"; -- ±
when 16#cb1# => romdata <= X"00"; -- ±
when 16#0b2# => romdata <= X"00"; -- ²
when 16#1b2# => romdata <= X"30"; -- ²
when 16#2b2# => romdata <= X"48"; -- ²
when 16#3b2# => romdata <= X"08"; -- ²
when 16#4b2# => romdata <= X"30"; -- ²
when 16#5b2# => romdata <= X"40"; -- ²
when 16#6b2# => romdata <= X"78"; -- ²
when 16#7b2# => romdata <= X"00"; -- ²
when 16#8b2# => romdata <= X"00"; -- ²
when 16#9b2# => romdata <= X"00"; -- ²
when 16#ab2# => romdata <= X"00"; -- ²
when 16#bb2# => romdata <= X"00"; -- ²
when 16#cb2# => romdata <= X"00"; -- ²
when 16#0b3# => romdata <= X"00"; -- ³
when 16#1b3# => romdata <= X"30"; -- ³
when 16#2b3# => romdata <= X"48"; -- ³
when 16#3b3# => romdata <= X"10"; -- ³
when 16#4b3# => romdata <= X"08"; -- ³
when 16#5b3# => romdata <= X"48"; -- ³
when 16#6b3# => romdata <= X"30"; -- ³
when 16#7b3# => romdata <= X"00"; -- ³
when 16#8b3# => romdata <= X"00"; -- ³
when 16#9b3# => romdata <= X"00"; -- ³
when 16#ab3# => romdata <= X"00"; -- ³
when 16#bb3# => romdata <= X"00"; -- ³
when 16#cb3# => romdata <= X"00"; -- ³
when 16#0b4# => romdata <= X"00"; -- ´
when 16#1b4# => romdata <= X"08"; -- ´
when 16#2b4# => romdata <= X"10"; -- ´
when 16#3b4# => romdata <= X"00"; -- ´
when 16#4b4# => romdata <= X"00"; -- ´
when 16#5b4# => romdata <= X"00"; -- ´
when 16#6b4# => romdata <= X"00"; -- ´
when 16#7b4# => romdata <= X"00"; -- ´
when 16#8b4# => romdata <= X"00"; -- ´
when 16#9b4# => romdata <= X"00"; -- ´
when 16#ab4# => romdata <= X"00"; -- ´
when 16#bb4# => romdata <= X"00"; -- ´
when 16#cb4# => romdata <= X"00"; -- ´
when 16#0b5# => romdata <= X"00"; -- µ
when 16#1b5# => romdata <= X"00"; -- µ
when 16#2b5# => romdata <= X"00"; -- µ
when 16#3b5# => romdata <= X"00"; -- µ
when 16#4b5# => romdata <= X"00"; -- µ
when 16#5b5# => romdata <= X"42"; -- µ
when 16#6b5# => romdata <= X"42"; -- µ
when 16#7b5# => romdata <= X"42"; -- µ
when 16#8b5# => romdata <= X"42"; -- µ
when 16#9b5# => romdata <= X"66"; -- µ
when 16#ab5# => romdata <= X"5a"; -- µ
when 16#bb5# => romdata <= X"40"; -- µ
when 16#cb5# => romdata <= X"00"; -- µ
when 16#0b6# => romdata <= X"00"; -- ¶
when 16#1b6# => romdata <= X"00"; -- ¶
when 16#2b6# => romdata <= X"3e"; -- ¶
when 16#3b6# => romdata <= X"74"; -- ¶
when 16#4b6# => romdata <= X"74"; -- ¶
when 16#5b6# => romdata <= X"74"; -- ¶
when 16#6b6# => romdata <= X"34"; -- ¶
when 16#7b6# => romdata <= X"14"; -- ¶
when 16#8b6# => romdata <= X"14"; -- ¶
when 16#9b6# => romdata <= X"14"; -- ¶
when 16#ab6# => romdata <= X"14"; -- ¶
when 16#bb6# => romdata <= X"00"; -- ¶
when 16#cb6# => romdata <= X"00"; -- ¶
when 16#0b7# => romdata <= X"00"; -- ·
when 16#1b7# => romdata <= X"00"; -- ·
when 16#2b7# => romdata <= X"00"; -- ·
when 16#3b7# => romdata <= X"00"; -- ·
when 16#4b7# => romdata <= X"00"; -- ·
when 16#5b7# => romdata <= X"00"; -- ·
when 16#6b7# => romdata <= X"18"; -- ·
when 16#7b7# => romdata <= X"00"; -- ·
when 16#8b7# => romdata <= X"00"; -- ·
when 16#9b7# => romdata <= X"00"; -- ·
when 16#ab7# => romdata <= X"00"; -- ·
when 16#bb7# => romdata <= X"00"; -- ·
when 16#cb7# => romdata <= X"00"; -- ·
when 16#0b8# => romdata <= X"00"; -- ¸
when 16#1b8# => romdata <= X"00"; -- ¸
when 16#2b8# => romdata <= X"00"; -- ¸
when 16#3b8# => romdata <= X"00"; -- ¸
when 16#4b8# => romdata <= X"00"; -- ¸
when 16#5b8# => romdata <= X"00"; -- ¸
when 16#6b8# => romdata <= X"00"; -- ¸
when 16#7b8# => romdata <= X"00"; -- ¸
when 16#8b8# => romdata <= X"00"; -- ¸
when 16#9b8# => romdata <= X"00"; -- ¸
when 16#ab8# => romdata <= X"00"; -- ¸
when 16#bb8# => romdata <= X"08"; -- ¸
when 16#cb8# => romdata <= X"18"; -- ¸
when 16#0b9# => romdata <= X"00"; -- ¹
when 16#1b9# => romdata <= X"20"; -- ¹
when 16#2b9# => romdata <= X"60"; -- ¹
when 16#3b9# => romdata <= X"20"; -- ¹
when 16#4b9# => romdata <= X"20"; -- ¹
when 16#5b9# => romdata <= X"20"; -- ¹
when 16#6b9# => romdata <= X"70"; -- ¹
when 16#7b9# => romdata <= X"00"; -- ¹
when 16#8b9# => romdata <= X"00"; -- ¹
when 16#9b9# => romdata <= X"00"; -- ¹
when 16#ab9# => romdata <= X"00"; -- ¹
when 16#bb9# => romdata <= X"00"; -- ¹
when 16#cb9# => romdata <= X"00"; -- ¹
when 16#0ba# => romdata <= X"00"; -- º
when 16#1ba# => romdata <= X"00"; -- º
when 16#2ba# => romdata <= X"30"; -- º
when 16#3ba# => romdata <= X"48"; -- º
when 16#4ba# => romdata <= X"48"; -- º
when 16#5ba# => romdata <= X"30"; -- º
when 16#6ba# => romdata <= X"00"; -- º
when 16#7ba# => romdata <= X"78"; -- º
when 16#8ba# => romdata <= X"00"; -- º
when 16#9ba# => romdata <= X"00"; -- º
when 16#aba# => romdata <= X"00"; -- º
when 16#bba# => romdata <= X"00"; -- º
when 16#cba# => romdata <= X"00"; -- º
when 16#0bb# => romdata <= X"00"; -- »
when 16#1bb# => romdata <= X"00"; -- »
when 16#2bb# => romdata <= X"00"; -- »
when 16#3bb# => romdata <= X"90"; -- »
when 16#4bb# => romdata <= X"48"; -- »
when 16#5bb# => romdata <= X"24"; -- »
when 16#6bb# => romdata <= X"12"; -- »
when 16#7bb# => romdata <= X"24"; -- »
when 16#8bb# => romdata <= X"48"; -- »
when 16#9bb# => romdata <= X"90"; -- »
when 16#abb# => romdata <= X"00"; -- »
when 16#bbb# => romdata <= X"00"; -- »
when 16#cbb# => romdata <= X"00"; -- »
when 16#0bc# => romdata <= X"00"; -- ¼
when 16#1bc# => romdata <= X"40"; -- ¼
when 16#2bc# => romdata <= X"c0"; -- ¼
when 16#3bc# => romdata <= X"40"; -- ¼
when 16#4bc# => romdata <= X"40"; -- ¼
when 16#5bc# => romdata <= X"42"; -- ¼
when 16#6bc# => romdata <= X"e6"; -- ¼
when 16#7bc# => romdata <= X"0a"; -- ¼
when 16#8bc# => romdata <= X"12"; -- ¼
when 16#9bc# => romdata <= X"1a"; -- ¼
when 16#abc# => romdata <= X"06"; -- ¼
when 16#bbc# => romdata <= X"00"; -- ¼
when 16#cbc# => romdata <= X"00"; -- ¼
when 16#0bd# => romdata <= X"00"; -- ½
when 16#1bd# => romdata <= X"40"; -- ½
when 16#2bd# => romdata <= X"c0"; -- ½
when 16#3bd# => romdata <= X"40"; -- ½
when 16#4bd# => romdata <= X"40"; -- ½
when 16#5bd# => romdata <= X"4c"; -- ½
when 16#6bd# => romdata <= X"f2"; -- ½
when 16#7bd# => romdata <= X"02"; -- ½
when 16#8bd# => romdata <= X"0c"; -- ½
when 16#9bd# => romdata <= X"10"; -- ½
when 16#abd# => romdata <= X"1e"; -- ½
when 16#bbd# => romdata <= X"00"; -- ½
when 16#cbd# => romdata <= X"00"; -- ½
when 16#0be# => romdata <= X"00"; -- ¾
when 16#1be# => romdata <= X"60"; -- ¾
when 16#2be# => romdata <= X"90"; -- ¾
when 16#3be# => romdata <= X"20"; -- ¾
when 16#4be# => romdata <= X"10"; -- ¾
when 16#5be# => romdata <= X"92"; -- ¾
when 16#6be# => romdata <= X"66"; -- ¾
when 16#7be# => romdata <= X"0a"; -- ¾
when 16#8be# => romdata <= X"12"; -- ¾
when 16#9be# => romdata <= X"1a"; -- ¾
when 16#abe# => romdata <= X"06"; -- ¾
when 16#bbe# => romdata <= X"00"; -- ¾
when 16#cbe# => romdata <= X"00"; -- ¾
when 16#0bf# => romdata <= X"00"; -- ¿
when 16#1bf# => romdata <= X"00"; -- ¿
when 16#2bf# => romdata <= X"10"; -- ¿
when 16#3bf# => romdata <= X"00"; -- ¿
when 16#4bf# => romdata <= X"10"; -- ¿
when 16#5bf# => romdata <= X"10"; -- ¿
when 16#6bf# => romdata <= X"20"; -- ¿
when 16#7bf# => romdata <= X"40"; -- ¿
when 16#8bf# => romdata <= X"42"; -- ¿
when 16#9bf# => romdata <= X"42"; -- ¿
when 16#abf# => romdata <= X"3c"; -- ¿
when 16#bbf# => romdata <= X"00"; -- ¿
when 16#cbf# => romdata <= X"00"; -- ¿
when 16#0c0# => romdata <= X"00"; -- À
when 16#1c0# => romdata <= X"10"; -- À
when 16#2c0# => romdata <= X"08"; -- À
when 16#3c0# => romdata <= X"00"; -- À
when 16#4c0# => romdata <= X"18"; -- À
when 16#5c0# => romdata <= X"24"; -- À
when 16#6c0# => romdata <= X"42"; -- À
when 16#7c0# => romdata <= X"42"; -- À
when 16#8c0# => romdata <= X"7e"; -- À
when 16#9c0# => romdata <= X"42"; -- À
when 16#ac0# => romdata <= X"42"; -- À
when 16#bc0# => romdata <= X"00"; -- À
when 16#cc0# => romdata <= X"00"; -- À
when 16#0c1# => romdata <= X"00"; -- Á
when 16#1c1# => romdata <= X"08"; -- Á
when 16#2c1# => romdata <= X"10"; -- Á
when 16#3c1# => romdata <= X"00"; -- Á
when 16#4c1# => romdata <= X"18"; -- Á
when 16#5c1# => romdata <= X"24"; -- Á
when 16#6c1# => romdata <= X"42"; -- Á
when 16#7c1# => romdata <= X"42"; -- Á
when 16#8c1# => romdata <= X"7e"; -- Á
when 16#9c1# => romdata <= X"42"; -- Á
when 16#ac1# => romdata <= X"42"; -- Á
when 16#bc1# => romdata <= X"00"; -- Á
when 16#cc1# => romdata <= X"00"; -- Á
when 16#0c2# => romdata <= X"00"; -- Â
when 16#1c2# => romdata <= X"18"; -- Â
when 16#2c2# => romdata <= X"24"; -- Â
when 16#3c2# => romdata <= X"00"; -- Â
when 16#4c2# => romdata <= X"18"; -- Â
when 16#5c2# => romdata <= X"24"; -- Â
when 16#6c2# => romdata <= X"42"; -- Â
when 16#7c2# => romdata <= X"42"; -- Â
when 16#8c2# => romdata <= X"7e"; -- Â
when 16#9c2# => romdata <= X"42"; -- Â
when 16#ac2# => romdata <= X"42"; -- Â
when 16#bc2# => romdata <= X"00"; -- Â
when 16#cc2# => romdata <= X"00"; -- Â
when 16#0c3# => romdata <= X"00"; -- Ã
when 16#1c3# => romdata <= X"32"; -- Ã
when 16#2c3# => romdata <= X"4c"; -- Ã
when 16#3c3# => romdata <= X"00"; -- Ã
when 16#4c3# => romdata <= X"18"; -- Ã
when 16#5c3# => romdata <= X"24"; -- Ã
when 16#6c3# => romdata <= X"42"; -- Ã
when 16#7c3# => romdata <= X"42"; -- Ã
when 16#8c3# => romdata <= X"7e"; -- Ã
when 16#9c3# => romdata <= X"42"; -- Ã
when 16#ac3# => romdata <= X"42"; -- Ã
when 16#bc3# => romdata <= X"00"; -- Ã
when 16#cc3# => romdata <= X"00"; -- Ã
when 16#0c4# => romdata <= X"00"; -- Ä
when 16#1c4# => romdata <= X"24"; -- Ä
when 16#2c4# => romdata <= X"24"; -- Ä
when 16#3c4# => romdata <= X"00"; -- Ä
when 16#4c4# => romdata <= X"18"; -- Ä
when 16#5c4# => romdata <= X"24"; -- Ä
when 16#6c4# => romdata <= X"42"; -- Ä
when 16#7c4# => romdata <= X"42"; -- Ä
when 16#8c4# => romdata <= X"7e"; -- Ä
when 16#9c4# => romdata <= X"42"; -- Ä
when 16#ac4# => romdata <= X"42"; -- Ä
when 16#bc4# => romdata <= X"00"; -- Ä
when 16#cc4# => romdata <= X"00"; -- Ä
when 16#0c5# => romdata <= X"00"; -- Å
when 16#1c5# => romdata <= X"18"; -- Å
when 16#2c5# => romdata <= X"24"; -- Å
when 16#3c5# => romdata <= X"18"; -- Å
when 16#4c5# => romdata <= X"18"; -- Å
when 16#5c5# => romdata <= X"24"; -- Å
when 16#6c5# => romdata <= X"42"; -- Å
when 16#7c5# => romdata <= X"42"; -- Å
when 16#8c5# => romdata <= X"7e"; -- Å
when 16#9c5# => romdata <= X"42"; -- Å
when 16#ac5# => romdata <= X"42"; -- Å
when 16#bc5# => romdata <= X"00"; -- Å
when 16#cc5# => romdata <= X"00"; -- Å
when 16#0c6# => romdata <= X"00"; -- Æ
when 16#1c6# => romdata <= X"00"; -- Æ
when 16#2c6# => romdata <= X"6e"; -- Æ
when 16#3c6# => romdata <= X"90"; -- Æ
when 16#4c6# => romdata <= X"90"; -- Æ
when 16#5c6# => romdata <= X"90"; -- Æ
when 16#6c6# => romdata <= X"9c"; -- Æ
when 16#7c6# => romdata <= X"f0"; -- Æ
when 16#8c6# => romdata <= X"90"; -- Æ
when 16#9c6# => romdata <= X"90"; -- Æ
when 16#ac6# => romdata <= X"9e"; -- Æ
when 16#bc6# => romdata <= X"00"; -- Æ
when 16#cc6# => romdata <= X"00"; -- Æ
when 16#0c7# => romdata <= X"00"; -- Ç
when 16#1c7# => romdata <= X"00"; -- Ç
when 16#2c7# => romdata <= X"3c"; -- Ç
when 16#3c7# => romdata <= X"42"; -- Ç
when 16#4c7# => romdata <= X"40"; -- Ç
when 16#5c7# => romdata <= X"40"; -- Ç
when 16#6c7# => romdata <= X"40"; -- Ç
when 16#7c7# => romdata <= X"40"; -- Ç
when 16#8c7# => romdata <= X"40"; -- Ç
when 16#9c7# => romdata <= X"42"; -- Ç
when 16#ac7# => romdata <= X"3c"; -- Ç
when 16#bc7# => romdata <= X"08"; -- Ç
when 16#cc7# => romdata <= X"10"; -- Ç
when 16#0c8# => romdata <= X"00"; -- È
when 16#1c8# => romdata <= X"10"; -- È
when 16#2c8# => romdata <= X"08"; -- È
when 16#3c8# => romdata <= X"00"; -- È
when 16#4c8# => romdata <= X"7e"; -- È
when 16#5c8# => romdata <= X"40"; -- È
when 16#6c8# => romdata <= X"40"; -- È
when 16#7c8# => romdata <= X"78"; -- È
when 16#8c8# => romdata <= X"40"; -- È
when 16#9c8# => romdata <= X"40"; -- È
when 16#ac8# => romdata <= X"7e"; -- È
when 16#bc8# => romdata <= X"00"; -- È
when 16#cc8# => romdata <= X"00"; -- È
when 16#0c9# => romdata <= X"00"; -- É
when 16#1c9# => romdata <= X"08"; -- É
when 16#2c9# => romdata <= X"10"; -- É
when 16#3c9# => romdata <= X"00"; -- É
when 16#4c9# => romdata <= X"7e"; -- É
when 16#5c9# => romdata <= X"40"; -- É
when 16#6c9# => romdata <= X"40"; -- É
when 16#7c9# => romdata <= X"78"; -- É
when 16#8c9# => romdata <= X"40"; -- É
when 16#9c9# => romdata <= X"40"; -- É
when 16#ac9# => romdata <= X"7e"; -- É
when 16#bc9# => romdata <= X"00"; -- É
when 16#cc9# => romdata <= X"00"; -- É
when 16#0ca# => romdata <= X"00"; -- Ê
when 16#1ca# => romdata <= X"18"; -- Ê
when 16#2ca# => romdata <= X"24"; -- Ê
when 16#3ca# => romdata <= X"00"; -- Ê
when 16#4ca# => romdata <= X"7e"; -- Ê
when 16#5ca# => romdata <= X"40"; -- Ê
when 16#6ca# => romdata <= X"40"; -- Ê
when 16#7ca# => romdata <= X"78"; -- Ê
when 16#8ca# => romdata <= X"40"; -- Ê
when 16#9ca# => romdata <= X"40"; -- Ê
when 16#aca# => romdata <= X"7e"; -- Ê
when 16#bca# => romdata <= X"00"; -- Ê
when 16#cca# => romdata <= X"00"; -- Ê
when 16#0cb# => romdata <= X"00"; -- Ë
when 16#1cb# => romdata <= X"24"; -- Ë
when 16#2cb# => romdata <= X"24"; -- Ë
when 16#3cb# => romdata <= X"00"; -- Ë
when 16#4cb# => romdata <= X"7e"; -- Ë
when 16#5cb# => romdata <= X"40"; -- Ë
when 16#6cb# => romdata <= X"40"; -- Ë
when 16#7cb# => romdata <= X"78"; -- Ë
when 16#8cb# => romdata <= X"40"; -- Ë
when 16#9cb# => romdata <= X"40"; -- Ë
when 16#acb# => romdata <= X"7e"; -- Ë
when 16#bcb# => romdata <= X"00"; -- Ë
when 16#ccb# => romdata <= X"00"; -- Ë
when 16#0cc# => romdata <= X"00"; -- Ì
when 16#1cc# => romdata <= X"20"; -- Ì
when 16#2cc# => romdata <= X"10"; -- Ì
when 16#3cc# => romdata <= X"00"; -- Ì
when 16#4cc# => romdata <= X"7c"; -- Ì
when 16#5cc# => romdata <= X"10"; -- Ì
when 16#6cc# => romdata <= X"10"; -- Ì
when 16#7cc# => romdata <= X"10"; -- Ì
when 16#8cc# => romdata <= X"10"; -- Ì
when 16#9cc# => romdata <= X"10"; -- Ì
when 16#acc# => romdata <= X"7c"; -- Ì
when 16#bcc# => romdata <= X"00"; -- Ì
when 16#ccc# => romdata <= X"00"; -- Ì
when 16#0cd# => romdata <= X"00"; -- Í
when 16#1cd# => romdata <= X"08"; -- Í
when 16#2cd# => romdata <= X"10"; -- Í
when 16#3cd# => romdata <= X"00"; -- Í
when 16#4cd# => romdata <= X"7c"; -- Í
when 16#5cd# => romdata <= X"10"; -- Í
when 16#6cd# => romdata <= X"10"; -- Í
when 16#7cd# => romdata <= X"10"; -- Í
when 16#8cd# => romdata <= X"10"; -- Í
when 16#9cd# => romdata <= X"10"; -- Í
when 16#acd# => romdata <= X"7c"; -- Í
when 16#bcd# => romdata <= X"00"; -- Í
when 16#ccd# => romdata <= X"00"; -- Í
when 16#0ce# => romdata <= X"00"; -- Î
when 16#1ce# => romdata <= X"18"; -- Î
when 16#2ce# => romdata <= X"24"; -- Î
when 16#3ce# => romdata <= X"00"; -- Î
when 16#4ce# => romdata <= X"7c"; -- Î
when 16#5ce# => romdata <= X"10"; -- Î
when 16#6ce# => romdata <= X"10"; -- Î
when 16#7ce# => romdata <= X"10"; -- Î
when 16#8ce# => romdata <= X"10"; -- Î
when 16#9ce# => romdata <= X"10"; -- Î
when 16#ace# => romdata <= X"7c"; -- Î
when 16#bce# => romdata <= X"00"; -- Î
when 16#cce# => romdata <= X"00"; -- Î
when 16#0cf# => romdata <= X"00"; -- Ï
when 16#1cf# => romdata <= X"44"; -- Ï
when 16#2cf# => romdata <= X"44"; -- Ï
when 16#3cf# => romdata <= X"00"; -- Ï
when 16#4cf# => romdata <= X"7c"; -- Ï
when 16#5cf# => romdata <= X"10"; -- Ï
when 16#6cf# => romdata <= X"10"; -- Ï
when 16#7cf# => romdata <= X"10"; -- Ï
when 16#8cf# => romdata <= X"10"; -- Ï
when 16#9cf# => romdata <= X"10"; -- Ï
when 16#acf# => romdata <= X"7c"; -- Ï
when 16#bcf# => romdata <= X"00"; -- Ï
when 16#ccf# => romdata <= X"00"; -- Ï
when 16#0d0# => romdata <= X"00"; -- Ð
when 16#1d0# => romdata <= X"00"; -- Ð
when 16#2d0# => romdata <= X"78"; -- Ð
when 16#3d0# => romdata <= X"44"; -- Ð
when 16#4d0# => romdata <= X"42"; -- Ð
when 16#5d0# => romdata <= X"42"; -- Ð
when 16#6d0# => romdata <= X"e2"; -- Ð
when 16#7d0# => romdata <= X"42"; -- Ð
when 16#8d0# => romdata <= X"42"; -- Ð
when 16#9d0# => romdata <= X"44"; -- Ð
when 16#ad0# => romdata <= X"78"; -- Ð
when 16#bd0# => romdata <= X"00"; -- Ð
when 16#cd0# => romdata <= X"00"; -- Ð
when 16#0d1# => romdata <= X"00"; -- Ñ
when 16#1d1# => romdata <= X"64"; -- Ñ
when 16#2d1# => romdata <= X"98"; -- Ñ
when 16#3d1# => romdata <= X"00"; -- Ñ
when 16#4d1# => romdata <= X"82"; -- Ñ
when 16#5d1# => romdata <= X"c2"; -- Ñ
when 16#6d1# => romdata <= X"a2"; -- Ñ
when 16#7d1# => romdata <= X"92"; -- Ñ
when 16#8d1# => romdata <= X"8a"; -- Ñ
when 16#9d1# => romdata <= X"86"; -- Ñ
when 16#ad1# => romdata <= X"82"; -- Ñ
when 16#bd1# => romdata <= X"00"; -- Ñ
when 16#cd1# => romdata <= X"00"; -- Ñ
when 16#0d2# => romdata <= X"00"; -- Ò
when 16#1d2# => romdata <= X"20"; -- Ò
when 16#2d2# => romdata <= X"10"; -- Ò
when 16#3d2# => romdata <= X"00"; -- Ò
when 16#4d2# => romdata <= X"7c"; -- Ò
when 16#5d2# => romdata <= X"82"; -- Ò
when 16#6d2# => romdata <= X"82"; -- Ò
when 16#7d2# => romdata <= X"82"; -- Ò
when 16#8d2# => romdata <= X"82"; -- Ò
when 16#9d2# => romdata <= X"82"; -- Ò
when 16#ad2# => romdata <= X"7c"; -- Ò
when 16#bd2# => romdata <= X"00"; -- Ò
when 16#cd2# => romdata <= X"00"; -- Ò
when 16#0d3# => romdata <= X"00"; -- Ó
when 16#1d3# => romdata <= X"08"; -- Ó
when 16#2d3# => romdata <= X"10"; -- Ó
when 16#3d3# => romdata <= X"00"; -- Ó
when 16#4d3# => romdata <= X"7c"; -- Ó
when 16#5d3# => romdata <= X"82"; -- Ó
when 16#6d3# => romdata <= X"82"; -- Ó
when 16#7d3# => romdata <= X"82"; -- Ó
when 16#8d3# => romdata <= X"82"; -- Ó
when 16#9d3# => romdata <= X"82"; -- Ó
when 16#ad3# => romdata <= X"7c"; -- Ó
when 16#bd3# => romdata <= X"00"; -- Ó
when 16#cd3# => romdata <= X"00"; -- Ó
when 16#0d4# => romdata <= X"00"; -- Ô
when 16#1d4# => romdata <= X"18"; -- Ô
when 16#2d4# => romdata <= X"24"; -- Ô
when 16#3d4# => romdata <= X"00"; -- Ô
when 16#4d4# => romdata <= X"7c"; -- Ô
when 16#5d4# => romdata <= X"82"; -- Ô
when 16#6d4# => romdata <= X"82"; -- Ô
when 16#7d4# => romdata <= X"82"; -- Ô
when 16#8d4# => romdata <= X"82"; -- Ô
when 16#9d4# => romdata <= X"82"; -- Ô
when 16#ad4# => romdata <= X"7c"; -- Ô
when 16#bd4# => romdata <= X"00"; -- Ô
when 16#cd4# => romdata <= X"00"; -- Ô
when 16#0d5# => romdata <= X"00"; -- Õ
when 16#1d5# => romdata <= X"64"; -- Õ
when 16#2d5# => romdata <= X"98"; -- Õ
when 16#3d5# => romdata <= X"00"; -- Õ
when 16#4d5# => romdata <= X"7c"; -- Õ
when 16#5d5# => romdata <= X"82"; -- Õ
when 16#6d5# => romdata <= X"82"; -- Õ
when 16#7d5# => romdata <= X"82"; -- Õ
when 16#8d5# => romdata <= X"82"; -- Õ
when 16#9d5# => romdata <= X"82"; -- Õ
when 16#ad5# => romdata <= X"7c"; -- Õ
when 16#bd5# => romdata <= X"00"; -- Õ
when 16#cd5# => romdata <= X"00"; -- Õ
when 16#0d6# => romdata <= X"00"; -- Ö
when 16#1d6# => romdata <= X"44"; -- Ö
when 16#2d6# => romdata <= X"44"; -- Ö
when 16#3d6# => romdata <= X"00"; -- Ö
when 16#4d6# => romdata <= X"7c"; -- Ö
when 16#5d6# => romdata <= X"82"; -- Ö
when 16#6d6# => romdata <= X"82"; -- Ö
when 16#7d6# => romdata <= X"82"; -- Ö
when 16#8d6# => romdata <= X"82"; -- Ö
when 16#9d6# => romdata <= X"82"; -- Ö
when 16#ad6# => romdata <= X"7c"; -- Ö
when 16#bd6# => romdata <= X"00"; -- Ö
when 16#cd6# => romdata <= X"00"; -- Ö
when 16#0d7# => romdata <= X"00"; -- ×
when 16#1d7# => romdata <= X"00"; -- ×
when 16#2d7# => romdata <= X"00"; -- ×
when 16#3d7# => romdata <= X"00"; -- ×
when 16#4d7# => romdata <= X"42"; -- ×
when 16#5d7# => romdata <= X"24"; -- ×
when 16#6d7# => romdata <= X"18"; -- ×
when 16#7d7# => romdata <= X"18"; -- ×
when 16#8d7# => romdata <= X"24"; -- ×
when 16#9d7# => romdata <= X"42"; -- ×
when 16#ad7# => romdata <= X"00"; -- ×
when 16#bd7# => romdata <= X"00"; -- ×
when 16#cd7# => romdata <= X"00"; -- ×
when 16#0d8# => romdata <= X"00"; -- Ø
when 16#1d8# => romdata <= X"02"; -- Ø
when 16#2d8# => romdata <= X"3c"; -- Ø
when 16#3d8# => romdata <= X"46"; -- Ø
when 16#4d8# => romdata <= X"4a"; -- Ø
when 16#5d8# => romdata <= X"4a"; -- Ø
when 16#6d8# => romdata <= X"52"; -- Ø
when 16#7d8# => romdata <= X"52"; -- Ø
when 16#8d8# => romdata <= X"52"; -- Ø
when 16#9d8# => romdata <= X"62"; -- Ø
when 16#ad8# => romdata <= X"3c"; -- Ø
when 16#bd8# => romdata <= X"40"; -- Ø
when 16#cd8# => romdata <= X"00"; -- Ø
when 16#0d9# => romdata <= X"00"; -- Ù
when 16#1d9# => romdata <= X"20"; -- Ù
when 16#2d9# => romdata <= X"10"; -- Ù
when 16#3d9# => romdata <= X"00"; -- Ù
when 16#4d9# => romdata <= X"42"; -- Ù
when 16#5d9# => romdata <= X"42"; -- Ù
when 16#6d9# => romdata <= X"42"; -- Ù
when 16#7d9# => romdata <= X"42"; -- Ù
when 16#8d9# => romdata <= X"42"; -- Ù
when 16#9d9# => romdata <= X"42"; -- Ù
when 16#ad9# => romdata <= X"3c"; -- Ù
when 16#bd9# => romdata <= X"00"; -- Ù
when 16#cd9# => romdata <= X"00"; -- Ù
when 16#0da# => romdata <= X"00"; -- Ú
when 16#1da# => romdata <= X"08"; -- Ú
when 16#2da# => romdata <= X"10"; -- Ú
when 16#3da# => romdata <= X"00"; -- Ú
when 16#4da# => romdata <= X"42"; -- Ú
when 16#5da# => romdata <= X"42"; -- Ú
when 16#6da# => romdata <= X"42"; -- Ú
when 16#7da# => romdata <= X"42"; -- Ú
when 16#8da# => romdata <= X"42"; -- Ú
when 16#9da# => romdata <= X"42"; -- Ú
when 16#ada# => romdata <= X"3c"; -- Ú
when 16#bda# => romdata <= X"00"; -- Ú
when 16#cda# => romdata <= X"00"; -- Ú
when 16#0db# => romdata <= X"00"; -- Û
when 16#1db# => romdata <= X"18"; -- Û
when 16#2db# => romdata <= X"24"; -- Û
when 16#3db# => romdata <= X"00"; -- Û
when 16#4db# => romdata <= X"42"; -- Û
when 16#5db# => romdata <= X"42"; -- Û
when 16#6db# => romdata <= X"42"; -- Û
when 16#7db# => romdata <= X"42"; -- Û
when 16#8db# => romdata <= X"42"; -- Û
when 16#9db# => romdata <= X"42"; -- Û
when 16#adb# => romdata <= X"3c"; -- Û
when 16#bdb# => romdata <= X"00"; -- Û
when 16#cdb# => romdata <= X"00"; -- Û
when 16#0dc# => romdata <= X"00"; -- Ü
when 16#1dc# => romdata <= X"24"; -- Ü
when 16#2dc# => romdata <= X"24"; -- Ü
when 16#3dc# => romdata <= X"00"; -- Ü
when 16#4dc# => romdata <= X"42"; -- Ü
when 16#5dc# => romdata <= X"42"; -- Ü
when 16#6dc# => romdata <= X"42"; -- Ü
when 16#7dc# => romdata <= X"42"; -- Ü
when 16#8dc# => romdata <= X"42"; -- Ü
when 16#9dc# => romdata <= X"42"; -- Ü
when 16#adc# => romdata <= X"3c"; -- Ü
when 16#bdc# => romdata <= X"00"; -- Ü
when 16#cdc# => romdata <= X"00"; -- Ü
when 16#0dd# => romdata <= X"00"; -- Ý
when 16#1dd# => romdata <= X"08"; -- Ý
when 16#2dd# => romdata <= X"10"; -- Ý
when 16#3dd# => romdata <= X"00"; -- Ý
when 16#4dd# => romdata <= X"44"; -- Ý
when 16#5dd# => romdata <= X"44"; -- Ý
when 16#6dd# => romdata <= X"28"; -- Ý
when 16#7dd# => romdata <= X"10"; -- Ý
when 16#8dd# => romdata <= X"10"; -- Ý
when 16#9dd# => romdata <= X"10"; -- Ý
when 16#add# => romdata <= X"10"; -- Ý
when 16#bdd# => romdata <= X"00"; -- Ý
when 16#cdd# => romdata <= X"00"; -- Ý
when 16#0de# => romdata <= X"00"; -- Þ
when 16#1de# => romdata <= X"00"; -- Þ
when 16#2de# => romdata <= X"40"; -- Þ
when 16#3de# => romdata <= X"7c"; -- Þ
when 16#4de# => romdata <= X"42"; -- Þ
when 16#5de# => romdata <= X"42"; -- Þ
when 16#6de# => romdata <= X"42"; -- Þ
when 16#7de# => romdata <= X"7c"; -- Þ
when 16#8de# => romdata <= X"40"; -- Þ
when 16#9de# => romdata <= X"40"; -- Þ
when 16#ade# => romdata <= X"40"; -- Þ
when 16#bde# => romdata <= X"00"; -- Þ
when 16#cde# => romdata <= X"00"; -- Þ
when 16#0df# => romdata <= X"00"; -- ß
when 16#1df# => romdata <= X"00"; -- ß
when 16#2df# => romdata <= X"38"; -- ß
when 16#3df# => romdata <= X"44"; -- ß
when 16#4df# => romdata <= X"44"; -- ß
when 16#5df# => romdata <= X"48"; -- ß
when 16#6df# => romdata <= X"50"; -- ß
when 16#7df# => romdata <= X"4c"; -- ß
when 16#8df# => romdata <= X"42"; -- ß
when 16#9df# => romdata <= X"42"; -- ß
when 16#adf# => romdata <= X"5c"; -- ß
when 16#bdf# => romdata <= X"00"; -- ß
when 16#cdf# => romdata <= X"00"; -- ß
when 16#0e0# => romdata <= X"00"; -- à
when 16#1e0# => romdata <= X"00"; -- à
when 16#2e0# => romdata <= X"10"; -- à
when 16#3e0# => romdata <= X"08"; -- à
when 16#4e0# => romdata <= X"00"; -- à
when 16#5e0# => romdata <= X"3c"; -- à
when 16#6e0# => romdata <= X"02"; -- à
when 16#7e0# => romdata <= X"3e"; -- à
when 16#8e0# => romdata <= X"42"; -- à
when 16#9e0# => romdata <= X"46"; -- à
when 16#ae0# => romdata <= X"3a"; -- à
when 16#be0# => romdata <= X"00"; -- à
when 16#ce0# => romdata <= X"00"; -- à
when 16#0e1# => romdata <= X"00"; -- á
when 16#1e1# => romdata <= X"00"; -- á
when 16#2e1# => romdata <= X"04"; -- á
when 16#3e1# => romdata <= X"08"; -- á
when 16#4e1# => romdata <= X"00"; -- á
when 16#5e1# => romdata <= X"3c"; -- á
when 16#6e1# => romdata <= X"02"; -- á
when 16#7e1# => romdata <= X"3e"; -- á
when 16#8e1# => romdata <= X"42"; -- á
when 16#9e1# => romdata <= X"46"; -- á
when 16#ae1# => romdata <= X"3a"; -- á
when 16#be1# => romdata <= X"00"; -- á
when 16#ce1# => romdata <= X"00"; -- á
when 16#0e2# => romdata <= X"00"; -- â
when 16#1e2# => romdata <= X"00"; -- â
when 16#2e2# => romdata <= X"18"; -- â
when 16#3e2# => romdata <= X"24"; -- â
when 16#4e2# => romdata <= X"00"; -- â
when 16#5e2# => romdata <= X"3c"; -- â
when 16#6e2# => romdata <= X"02"; -- â
when 16#7e2# => romdata <= X"3e"; -- â
when 16#8e2# => romdata <= X"42"; -- â
when 16#9e2# => romdata <= X"46"; -- â
when 16#ae2# => romdata <= X"3a"; -- â
when 16#be2# => romdata <= X"00"; -- â
when 16#ce2# => romdata <= X"00"; -- â
when 16#0e3# => romdata <= X"00"; -- ã
when 16#1e3# => romdata <= X"00"; -- ã
when 16#2e3# => romdata <= X"32"; -- ã
when 16#3e3# => romdata <= X"4c"; -- ã
when 16#4e3# => romdata <= X"00"; -- ã
when 16#5e3# => romdata <= X"3c"; -- ã
when 16#6e3# => romdata <= X"02"; -- ã
when 16#7e3# => romdata <= X"3e"; -- ã
when 16#8e3# => romdata <= X"42"; -- ã
when 16#9e3# => romdata <= X"46"; -- ã
when 16#ae3# => romdata <= X"3a"; -- ã
when 16#be3# => romdata <= X"00"; -- ã
when 16#ce3# => romdata <= X"00"; -- ã
when 16#0e4# => romdata <= X"00"; -- ä
when 16#1e4# => romdata <= X"00"; -- ä
when 16#2e4# => romdata <= X"24"; -- ä
when 16#3e4# => romdata <= X"24"; -- ä
when 16#4e4# => romdata <= X"00"; -- ä
when 16#5e4# => romdata <= X"3c"; -- ä
when 16#6e4# => romdata <= X"02"; -- ä
when 16#7e4# => romdata <= X"3e"; -- ä
when 16#8e4# => romdata <= X"42"; -- ä
when 16#9e4# => romdata <= X"46"; -- ä
when 16#ae4# => romdata <= X"3a"; -- ä
when 16#be4# => romdata <= X"00"; -- ä
when 16#ce4# => romdata <= X"00"; -- ä
when 16#0e5# => romdata <= X"00"; -- å
when 16#1e5# => romdata <= X"18"; -- å
when 16#2e5# => romdata <= X"24"; -- å
when 16#3e5# => romdata <= X"18"; -- å
when 16#4e5# => romdata <= X"00"; -- å
when 16#5e5# => romdata <= X"3c"; -- å
when 16#6e5# => romdata <= X"02"; -- å
when 16#7e5# => romdata <= X"3e"; -- å
when 16#8e5# => romdata <= X"42"; -- å
when 16#9e5# => romdata <= X"46"; -- å
when 16#ae5# => romdata <= X"3a"; -- å
when 16#be5# => romdata <= X"00"; -- å
when 16#ce5# => romdata <= X"00"; -- å
when 16#0e6# => romdata <= X"00"; -- æ
when 16#1e6# => romdata <= X"00"; -- æ
when 16#2e6# => romdata <= X"00"; -- æ
when 16#3e6# => romdata <= X"00"; -- æ
when 16#4e6# => romdata <= X"00"; -- æ
when 16#5e6# => romdata <= X"6c"; -- æ
when 16#6e6# => romdata <= X"12"; -- æ
when 16#7e6# => romdata <= X"7c"; -- æ
when 16#8e6# => romdata <= X"90"; -- æ
when 16#9e6# => romdata <= X"92"; -- æ
when 16#ae6# => romdata <= X"6c"; -- æ
when 16#be6# => romdata <= X"00"; -- æ
when 16#ce6# => romdata <= X"00"; -- æ
when 16#0e7# => romdata <= X"00"; -- ç
when 16#1e7# => romdata <= X"00"; -- ç
when 16#2e7# => romdata <= X"00"; -- ç
when 16#3e7# => romdata <= X"00"; -- ç
when 16#4e7# => romdata <= X"00"; -- ç
when 16#5e7# => romdata <= X"3c"; -- ç
when 16#6e7# => romdata <= X"42"; -- ç
when 16#7e7# => romdata <= X"40"; -- ç
when 16#8e7# => romdata <= X"40"; -- ç
when 16#9e7# => romdata <= X"42"; -- ç
when 16#ae7# => romdata <= X"3c"; -- ç
when 16#be7# => romdata <= X"08"; -- ç
when 16#ce7# => romdata <= X"10"; -- ç
when 16#0e8# => romdata <= X"00"; -- è
when 16#1e8# => romdata <= X"00"; -- è
when 16#2e8# => romdata <= X"10"; -- è
when 16#3e8# => romdata <= X"08"; -- è
when 16#4e8# => romdata <= X"00"; -- è
when 16#5e8# => romdata <= X"3c"; -- è
when 16#6e8# => romdata <= X"42"; -- è
when 16#7e8# => romdata <= X"7e"; -- è
when 16#8e8# => romdata <= X"40"; -- è
when 16#9e8# => romdata <= X"42"; -- è
when 16#ae8# => romdata <= X"3c"; -- è
when 16#be8# => romdata <= X"00"; -- è
when 16#ce8# => romdata <= X"00"; -- è
when 16#0e9# => romdata <= X"00"; -- é
when 16#1e9# => romdata <= X"00"; -- é
when 16#2e9# => romdata <= X"08"; -- é
when 16#3e9# => romdata <= X"10"; -- é
when 16#4e9# => romdata <= X"00"; -- é
when 16#5e9# => romdata <= X"3c"; -- é
when 16#6e9# => romdata <= X"42"; -- é
when 16#7e9# => romdata <= X"7e"; -- é
when 16#8e9# => romdata <= X"40"; -- é
when 16#9e9# => romdata <= X"42"; -- é
when 16#ae9# => romdata <= X"3c"; -- é
when 16#be9# => romdata <= X"00"; -- é
when 16#ce9# => romdata <= X"00"; -- é
when 16#0ea# => romdata <= X"00"; -- ê
when 16#1ea# => romdata <= X"00"; -- ê
when 16#2ea# => romdata <= X"18"; -- ê
when 16#3ea# => romdata <= X"24"; -- ê
when 16#4ea# => romdata <= X"00"; -- ê
when 16#5ea# => romdata <= X"3c"; -- ê
when 16#6ea# => romdata <= X"42"; -- ê
when 16#7ea# => romdata <= X"7e"; -- ê
when 16#8ea# => romdata <= X"40"; -- ê
when 16#9ea# => romdata <= X"42"; -- ê
when 16#aea# => romdata <= X"3c"; -- ê
when 16#bea# => romdata <= X"00"; -- ê
when 16#cea# => romdata <= X"00"; -- ê
when 16#0eb# => romdata <= X"00"; -- ë
when 16#1eb# => romdata <= X"00"; -- ë
when 16#2eb# => romdata <= X"24"; -- ë
when 16#3eb# => romdata <= X"24"; -- ë
when 16#4eb# => romdata <= X"00"; -- ë
when 16#5eb# => romdata <= X"3c"; -- ë
when 16#6eb# => romdata <= X"42"; -- ë
when 16#7eb# => romdata <= X"7e"; -- ë
when 16#8eb# => romdata <= X"40"; -- ë
when 16#9eb# => romdata <= X"42"; -- ë
when 16#aeb# => romdata <= X"3c"; -- ë
when 16#beb# => romdata <= X"00"; -- ë
when 16#ceb# => romdata <= X"00"; -- ë
when 16#0ec# => romdata <= X"00"; -- ì
when 16#1ec# => romdata <= X"00"; -- ì
when 16#2ec# => romdata <= X"20"; -- ì
when 16#3ec# => romdata <= X"10"; -- ì
when 16#4ec# => romdata <= X"00"; -- ì
when 16#5ec# => romdata <= X"30"; -- ì
when 16#6ec# => romdata <= X"10"; -- ì
when 16#7ec# => romdata <= X"10"; -- ì
when 16#8ec# => romdata <= X"10"; -- ì
when 16#9ec# => romdata <= X"10"; -- ì
when 16#aec# => romdata <= X"7c"; -- ì
when 16#bec# => romdata <= X"00"; -- ì
when 16#cec# => romdata <= X"00"; -- ì
when 16#0ed# => romdata <= X"00"; -- í
when 16#1ed# => romdata <= X"00"; -- í
when 16#2ed# => romdata <= X"10"; -- í
when 16#3ed# => romdata <= X"20"; -- í
when 16#4ed# => romdata <= X"00"; -- í
when 16#5ed# => romdata <= X"30"; -- í
when 16#6ed# => romdata <= X"10"; -- í
when 16#7ed# => romdata <= X"10"; -- í
when 16#8ed# => romdata <= X"10"; -- í
when 16#9ed# => romdata <= X"10"; -- í
when 16#aed# => romdata <= X"7c"; -- í
when 16#bed# => romdata <= X"00"; -- í
when 16#ced# => romdata <= X"00"; -- í
when 16#0ee# => romdata <= X"00"; -- î
when 16#1ee# => romdata <= X"00"; -- î
when 16#2ee# => romdata <= X"30"; -- î
when 16#3ee# => romdata <= X"48"; -- î
when 16#4ee# => romdata <= X"00"; -- î
when 16#5ee# => romdata <= X"30"; -- î
when 16#6ee# => romdata <= X"10"; -- î
when 16#7ee# => romdata <= X"10"; -- î
when 16#8ee# => romdata <= X"10"; -- î
when 16#9ee# => romdata <= X"10"; -- î
when 16#aee# => romdata <= X"7c"; -- î
when 16#bee# => romdata <= X"00"; -- î
when 16#cee# => romdata <= X"00"; -- î
when 16#0ef# => romdata <= X"00"; -- ï
when 16#1ef# => romdata <= X"00"; -- ï
when 16#2ef# => romdata <= X"48"; -- ï
when 16#3ef# => romdata <= X"48"; -- ï
when 16#4ef# => romdata <= X"00"; -- ï
when 16#5ef# => romdata <= X"30"; -- ï
when 16#6ef# => romdata <= X"10"; -- ï
when 16#7ef# => romdata <= X"10"; -- ï
when 16#8ef# => romdata <= X"10"; -- ï
when 16#9ef# => romdata <= X"10"; -- ï
when 16#aef# => romdata <= X"7c"; -- ï
when 16#bef# => romdata <= X"00"; -- ï
when 16#cef# => romdata <= X"00"; -- ï
when 16#0f0# => romdata <= X"00"; -- ð
when 16#1f0# => romdata <= X"24"; -- ð
when 16#2f0# => romdata <= X"18"; -- ð
when 16#3f0# => romdata <= X"28"; -- ð
when 16#4f0# => romdata <= X"04"; -- ð
when 16#5f0# => romdata <= X"3c"; -- ð
when 16#6f0# => romdata <= X"42"; -- ð
when 16#7f0# => romdata <= X"42"; -- ð
when 16#8f0# => romdata <= X"42"; -- ð
when 16#9f0# => romdata <= X"42"; -- ð
when 16#af0# => romdata <= X"3c"; -- ð
when 16#bf0# => romdata <= X"00"; -- ð
when 16#cf0# => romdata <= X"00"; -- ð
when 16#0f1# => romdata <= X"00"; -- ñ
when 16#1f1# => romdata <= X"00"; -- ñ
when 16#2f1# => romdata <= X"32"; -- ñ
when 16#3f1# => romdata <= X"4c"; -- ñ
when 16#4f1# => romdata <= X"00"; -- ñ
when 16#5f1# => romdata <= X"5c"; -- ñ
when 16#6f1# => romdata <= X"62"; -- ñ
when 16#7f1# => romdata <= X"42"; -- ñ
when 16#8f1# => romdata <= X"42"; -- ñ
when 16#9f1# => romdata <= X"42"; -- ñ
when 16#af1# => romdata <= X"42"; -- ñ
when 16#bf1# => romdata <= X"00"; -- ñ
when 16#cf1# => romdata <= X"00"; -- ñ
when 16#0f2# => romdata <= X"00"; -- ò
when 16#1f2# => romdata <= X"00"; -- ò
when 16#2f2# => romdata <= X"20"; -- ò
when 16#3f2# => romdata <= X"10"; -- ò
when 16#4f2# => romdata <= X"00"; -- ò
when 16#5f2# => romdata <= X"3c"; -- ò
when 16#6f2# => romdata <= X"42"; -- ò
when 16#7f2# => romdata <= X"42"; -- ò
when 16#8f2# => romdata <= X"42"; -- ò
when 16#9f2# => romdata <= X"42"; -- ò
when 16#af2# => romdata <= X"3c"; -- ò
when 16#bf2# => romdata <= X"00"; -- ò
when 16#cf2# => romdata <= X"00"; -- ò
when 16#0f3# => romdata <= X"00"; -- ó
when 16#1f3# => romdata <= X"00"; -- ó
when 16#2f3# => romdata <= X"08"; -- ó
when 16#3f3# => romdata <= X"10"; -- ó
when 16#4f3# => romdata <= X"00"; -- ó
when 16#5f3# => romdata <= X"3c"; -- ó
when 16#6f3# => romdata <= X"42"; -- ó
when 16#7f3# => romdata <= X"42"; -- ó
when 16#8f3# => romdata <= X"42"; -- ó
when 16#9f3# => romdata <= X"42"; -- ó
when 16#af3# => romdata <= X"3c"; -- ó
when 16#bf3# => romdata <= X"00"; -- ó
when 16#cf3# => romdata <= X"00"; -- ó
when 16#0f4# => romdata <= X"00"; -- ô
when 16#1f4# => romdata <= X"00"; -- ô
when 16#2f4# => romdata <= X"18"; -- ô
when 16#3f4# => romdata <= X"24"; -- ô
when 16#4f4# => romdata <= X"00"; -- ô
when 16#5f4# => romdata <= X"3c"; -- ô
when 16#6f4# => romdata <= X"42"; -- ô
when 16#7f4# => romdata <= X"42"; -- ô
when 16#8f4# => romdata <= X"42"; -- ô
when 16#9f4# => romdata <= X"42"; -- ô
when 16#af4# => romdata <= X"3c"; -- ô
when 16#bf4# => romdata <= X"00"; -- ô
when 16#cf4# => romdata <= X"00"; -- ô
when 16#0f5# => romdata <= X"00"; -- õ
when 16#1f5# => romdata <= X"00"; -- õ
when 16#2f5# => romdata <= X"32"; -- õ
when 16#3f5# => romdata <= X"4c"; -- õ
when 16#4f5# => romdata <= X"00"; -- õ
when 16#5f5# => romdata <= X"3c"; -- õ
when 16#6f5# => romdata <= X"42"; -- õ
when 16#7f5# => romdata <= X"42"; -- õ
when 16#8f5# => romdata <= X"42"; -- õ
when 16#9f5# => romdata <= X"42"; -- õ
when 16#af5# => romdata <= X"3c"; -- õ
when 16#bf5# => romdata <= X"00"; -- õ
when 16#cf5# => romdata <= X"00"; -- õ
when 16#0f6# => romdata <= X"00"; -- ö
when 16#1f6# => romdata <= X"00"; -- ö
when 16#2f6# => romdata <= X"24"; -- ö
when 16#3f6# => romdata <= X"24"; -- ö
when 16#4f6# => romdata <= X"00"; -- ö
when 16#5f6# => romdata <= X"3c"; -- ö
when 16#6f6# => romdata <= X"42"; -- ö
when 16#7f6# => romdata <= X"42"; -- ö
when 16#8f6# => romdata <= X"42"; -- ö
when 16#9f6# => romdata <= X"42"; -- ö
when 16#af6# => romdata <= X"3c"; -- ö
when 16#bf6# => romdata <= X"00"; -- ö
when 16#cf6# => romdata <= X"00"; -- ö
when 16#0f7# => romdata <= X"00"; -- ÷
when 16#1f7# => romdata <= X"00"; -- ÷
when 16#2f7# => romdata <= X"00"; -- ÷
when 16#3f7# => romdata <= X"10"; -- ÷
when 16#4f7# => romdata <= X"10"; -- ÷
when 16#5f7# => romdata <= X"00"; -- ÷
when 16#6f7# => romdata <= X"7c"; -- ÷
when 16#7f7# => romdata <= X"00"; -- ÷
when 16#8f7# => romdata <= X"10"; -- ÷
when 16#9f7# => romdata <= X"10"; -- ÷
when 16#af7# => romdata <= X"00"; -- ÷
when 16#bf7# => romdata <= X"00"; -- ÷
when 16#cf7# => romdata <= X"00"; -- ÷
when 16#0f8# => romdata <= X"00"; -- ø
when 16#1f8# => romdata <= X"00"; -- ø
when 16#2f8# => romdata <= X"00"; -- ø
when 16#3f8# => romdata <= X"00"; -- ø
when 16#4f8# => romdata <= X"02"; -- ø
when 16#5f8# => romdata <= X"3c"; -- ø
when 16#6f8# => romdata <= X"46"; -- ø
when 16#7f8# => romdata <= X"4a"; -- ø
when 16#8f8# => romdata <= X"52"; -- ø
when 16#9f8# => romdata <= X"62"; -- ø
when 16#af8# => romdata <= X"3c"; -- ø
when 16#bf8# => romdata <= X"40"; -- ø
when 16#cf8# => romdata <= X"00"; -- ø
when 16#0f9# => romdata <= X"00"; -- ù
when 16#1f9# => romdata <= X"00"; -- ù
when 16#2f9# => romdata <= X"20"; -- ù
when 16#3f9# => romdata <= X"10"; -- ù
when 16#4f9# => romdata <= X"00"; -- ù
when 16#5f9# => romdata <= X"44"; -- ù
when 16#6f9# => romdata <= X"44"; -- ù
when 16#7f9# => romdata <= X"44"; -- ù
when 16#8f9# => romdata <= X"44"; -- ù
when 16#9f9# => romdata <= X"44"; -- ù
when 16#af9# => romdata <= X"3a"; -- ù
when 16#bf9# => romdata <= X"00"; -- ù
when 16#cf9# => romdata <= X"00"; -- ù
when 16#0fa# => romdata <= X"00"; -- ú
when 16#1fa# => romdata <= X"00"; -- ú
when 16#2fa# => romdata <= X"08"; -- ú
when 16#3fa# => romdata <= X"10"; -- ú
when 16#4fa# => romdata <= X"00"; -- ú
when 16#5fa# => romdata <= X"44"; -- ú
when 16#6fa# => romdata <= X"44"; -- ú
when 16#7fa# => romdata <= X"44"; -- ú
when 16#8fa# => romdata <= X"44"; -- ú
when 16#9fa# => romdata <= X"44"; -- ú
when 16#afa# => romdata <= X"3a"; -- ú
when 16#bfa# => romdata <= X"00"; -- ú
when 16#cfa# => romdata <= X"00"; -- ú
when 16#0fb# => romdata <= X"00"; -- û
when 16#1fb# => romdata <= X"00"; -- û
when 16#2fb# => romdata <= X"18"; -- û
when 16#3fb# => romdata <= X"24"; -- û
when 16#4fb# => romdata <= X"00"; -- û
when 16#5fb# => romdata <= X"44"; -- û
when 16#6fb# => romdata <= X"44"; -- û
when 16#7fb# => romdata <= X"44"; -- û
when 16#8fb# => romdata <= X"44"; -- û
when 16#9fb# => romdata <= X"44"; -- û
when 16#afb# => romdata <= X"3a"; -- û
when 16#bfb# => romdata <= X"00"; -- û
when 16#cfb# => romdata <= X"00"; -- û
when 16#0fc# => romdata <= X"00"; -- ü
when 16#1fc# => romdata <= X"00"; -- ü
when 16#2fc# => romdata <= X"28"; -- ü
when 16#3fc# => romdata <= X"28"; -- ü
when 16#4fc# => romdata <= X"00"; -- ü
when 16#5fc# => romdata <= X"44"; -- ü
when 16#6fc# => romdata <= X"44"; -- ü
when 16#7fc# => romdata <= X"44"; -- ü
when 16#8fc# => romdata <= X"44"; -- ü
when 16#9fc# => romdata <= X"44"; -- ü
when 16#afc# => romdata <= X"3a"; -- ü
when 16#bfc# => romdata <= X"00"; -- ü
when 16#cfc# => romdata <= X"00"; -- ü
when 16#0fd# => romdata <= X"00"; -- ý
when 16#1fd# => romdata <= X"00"; -- ý
when 16#2fd# => romdata <= X"08"; -- ý
when 16#3fd# => romdata <= X"10"; -- ý
when 16#4fd# => romdata <= X"00"; -- ý
when 16#5fd# => romdata <= X"42"; -- ý
when 16#6fd# => romdata <= X"42"; -- ý
when 16#7fd# => romdata <= X"42"; -- ý
when 16#8fd# => romdata <= X"46"; -- ý
when 16#9fd# => romdata <= X"3a"; -- ý
when 16#afd# => romdata <= X"02"; -- ý
when 16#bfd# => romdata <= X"42"; -- ý
when 16#cfd# => romdata <= X"3c"; -- ý
when 16#0fe# => romdata <= X"00"; -- þ
when 16#1fe# => romdata <= X"00"; -- þ
when 16#2fe# => romdata <= X"00"; -- þ
when 16#3fe# => romdata <= X"40"; -- þ
when 16#4fe# => romdata <= X"40"; -- þ
when 16#5fe# => romdata <= X"5c"; -- þ
when 16#6fe# => romdata <= X"62"; -- þ
when 16#7fe# => romdata <= X"42"; -- þ
when 16#8fe# => romdata <= X"42"; -- þ
when 16#9fe# => romdata <= X"62"; -- þ
when 16#afe# => romdata <= X"5c"; -- þ
when 16#bfe# => romdata <= X"40"; -- þ
when 16#cfe# => romdata <= X"40"; -- þ
when 16#0ff# => romdata <= X"00"; -- ÿ
when 16#1ff# => romdata <= X"00"; -- ÿ
when 16#2ff# => romdata <= X"24"; -- ÿ
when 16#3ff# => romdata <= X"24"; -- ÿ
when 16#4ff# => romdata <= X"00"; -- ÿ
when 16#5ff# => romdata <= X"42"; -- ÿ
when 16#6ff# => romdata <= X"42"; -- ÿ
when 16#7ff# => romdata <= X"42"; -- ÿ
when 16#8ff# => romdata <= X"46"; -- ÿ
when 16#9ff# => romdata <= X"3a"; -- ÿ
when 16#aff# => romdata <= X"02"; -- ÿ
when 16#bff# => romdata <= X"42"; -- ÿ
when 16#cff# => romdata <= X"3c"; -- ÿ
when others => romdata <= (others => '0');
end case;
end process;
end architecture;
|
gpl-2.0
|
9b6978f1713c89a2ff47aa3d98cc9429
| 0.422171 | 2.936114 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/i2c/i2cslv.vhd
| 1 | 20,281 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2cslv
-- File: i2cslv.vhd
-- Author: Jan Andersson - Gaisler Research
-- [email protected]
--
-- Description: Simple I2C-slave with AMBA APB interface
--
-- Documentation of generics:
--
-- [hardaddr]
-- If this generic is set to 1 the core uses i2caddr as the hard coded address.
-- If hardaddr is set to 0 the core's address can be changed via the SLVADDR
-- register.
--
-- [tenbit]
-- Support for ten bit addresses.
--
-- [i2caddr]
-- The slave's (initial) i2c address.
--
-- [oepol]
-- Output enable polarity
--
-- [filter]
-- Length of filters used on SCL and SDA
--
-- The slave has four different modes operation. The mode is defined by the
-- value of the bits RMODE and TMODE.
-- RMODE TMODE I2CSLAVE Mode
-- 0 0 0
-- 0 1 1
-- 1 0 2
-- 1 1 3
--
-- RMODE 0:
-- The slave accepts one byte and NAKs all other transfers until software has
-- acknowledged the received byte.
-- RMODE 1:
-- The slave accepts one byte and keeps SCL low until software has acknowledged
-- the received byte
-- TMODE 0:
-- The slave transmits the same byte to all if the master requests more than
-- one byte in the transfer. The slave then NAKs all read requests unless the
-- Transmit Always Valid (TAV) bit in the control register is set.
-- TMODE 1:
-- The slave transmits one byte and then keeps SCL low until software has
-- acknowledged that the byte has been transmitted.
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.i2c.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
entity i2cslv is
generic (
-- APB generics
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0; -- interrupt index
-- I2C configuration
hardaddr : integer range 0 to 1 := 0; -- See description above
tenbit : integer range 0 to 1 := 0;
i2caddr : integer range 0 to 1023 := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2cslv;
architecture rtl of i2cslv is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
-- Core version
constant I2CSLV_REV : integer := 0;
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_I2CSLV, 0, I2CSLV_REV, pirq),
1 => apb_iobar(paddr, pmask));
-- Register addresses
constant SLV_ADDR : std_logic_vector(7 downto 2) := "000000";
constant CTRL_ADDR : std_logic_vector(7 downto 2) := "000001";
constant STS_ADDR : std_logic_vector(7 downto 2) := "000010";
constant MSK_ADDR : std_logic_vector(7 downto 2) := "000011";
constant RD_ADDR : std_logic_vector(7 downto 2) := "000100";
constant TD_ADDR : std_logic_vector(7 downto 2) := "000101";
-- Core configuration
constant TENBIT_SUPPORT : integer := tenbit;
constant I2CADDRLEN : integer := 7 + tenbit*3;
constant HARDCADDR : integer := hardaddr;
constant I2CSLVADDR : std_logic_vector((I2CADDRLEN-1) downto 0) :=
conv_std_logic_vector(i2caddr, I2CADDRLEN);
-- Misc constants
constant I2C_READ : std_ulogic := '1'; -- R/Wn bit
constant I2C_WRITE : std_ulogic := '0';
constant OEPOL_LEVEL : std_ulogic := conv_std_logic(oepol = 1);
constant I2C_LOW : std_ulogic := OEPOL_LEVEL; -- OE
constant I2C_HIZ : std_ulogic := not OEPOL_LEVEL;
constant I2C_ACK : std_ulogic := '0';
constant TENBIT_ADDR_START : std_logic_vector(4 downto 0) := "11110";
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type ctrl_reg_type is record -- Control register
rmode : std_ulogic; -- Receive mode
tmode : std_ulogic; -- Transmit mode
tv : std_ulogic; -- Transmit valid
tav : std_ulogic; -- Transmit always valid
en : std_ulogic; -- Enable
end record;
type sts_reg_type is record -- Status/Mask registers
rec : std_ulogic; -- Received byte
tra : std_ulogic; -- Transmitted byte
nak : std_ulogic; -- NAK'd address
end record;
type slvaddr_reg_type is record -- Slave address register
tba : std_ulogic; -- 10-bit address
slvaddr : std_logic_vector((I2CADDRLEN-1) downto 0);
end record;
type i2cslv_reg_bank is record -- APB registers
slvaddr : slvaddr_reg_type;
ctrl : ctrl_reg_type;
sts : sts_reg_type;
msk : sts_reg_type;
receive : std_logic_vector(7 downto 0);
transmit : std_logic_vector(7 downto 0);
end record;
type i2c_in_array is array (filter downto 0) of i2c_in_type;
type slv_state_type is (idle, checkaddr, check10bitaddr, sclhold,
movebyte, handshake);
type i2cslv_reg_type is record
slvstate : slv_state_type;
--
reg : i2cslv_reg_bank;
irq : std_ulogic;
-- Transfer phase
active : boolean;
addr : boolean;
transmit : boolean;
receive : boolean;
-- Shift register
sreg : std_logic_vector(7 downto 0);
cnt : std_logic_vector(2 downto 0);
-- Synchronizers for inputs SCL and SDA
scl : std_ulogic;
sda : std_ulogic;
i2ci : i2c_in_array;
-- Output enables
scloen : std_ulogic;
sdaoen : std_ulogic;
end record;
-----------------------------------------------------------------------------
-- Subprograms
-----------------------------------------------------------------------------
-- purpose: Compares the first byte of a received address with the slave's
-- address. The tba input determines if the slave is using a ten bit address.
function compaddr1stb (
ibyte : std_logic_vector(7 downto 0); -- I2C byte
sr : slvaddr_reg_type) -- slave address register
return boolean is
variable correct : std_logic_vector(7 downto 1);
begin -- compaddr1stb
if sr.tba = '1' then
correct(7 downto 3) := TENBIT_ADDR_START;
correct(2 downto 1):= sr.slvaddr((I2CADDRLEN-1) downto (I2CADDRLEN-2));
else
correct(7 downto 1) := sr.slvaddr(6 downto 0);
end if;
return ibyte(7 downto 1) = correct(7 downto 1);
end compaddr1stb;
-- purpose: Compares the 2nd byte of a ten bit address with the slave address
function compaddr2ndb (
ibyte : std_logic_vector(7 downto 0); -- I2C byte
slvaddr : std_logic_vector((I2CADDRLEN-1) downto 0)) -- slave address
return boolean is
begin -- compaddr2ndb
return ibyte((I2CADDRLEN-3) downto 0) = slvaddr((I2CADDRLEN-3) downto 0);
end compaddr2ndb;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- Register interface
signal r, rin : i2cslv_reg_type;
begin
comb: process (r, rstn, apbi, i2ci)
variable v : i2cslv_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable apbaddr : std_logic_vector(5 downto 0);
variable apbout : std_logic_vector(31 downto 0);
variable sclfilt : std_logic_vector(filter-1 downto 0);
variable sdafilt : std_logic_vector(filter-1 downto 0);
variable tba : boolean;
begin -- process comb
v := r; v.irq := '0'; irq := (others=>'0'); irq(pirq) := r.irq;
apbaddr := apbi.paddr(7 downto 2); apbout := (others => '0');
v.i2ci(0) := i2ci; v.i2ci(filter downto 1) := r.i2ci(filter-1 downto 0);
tba := false;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when SLV_ADDR =>
apbout(31) := r.reg.slvaddr.tba;
apbout((I2CADDRLEN-1) downto 0) := r.reg.slvaddr.slvaddr;
when CTRL_ADDR =>
apbout(4 downto 0) := r.reg.ctrl.rmode & r.reg.ctrl.tmode &
r.reg.ctrl.tv & r.reg.ctrl.tav & r.reg.ctrl.en;
when STS_ADDR =>
apbout(2 downto 0) := r.reg.sts.rec & r.reg.sts.tra & r.reg.sts.nak;
when MSK_ADDR =>
apbout(2 downto 0) := r.reg.msk.rec & r.reg.msk.tra & r.reg.msk.nak;
when RD_ADDR =>
v.reg.sts.rec := '0';
apbout(7 downto 0) := r.reg.receive;
when TD_ADDR =>
apbout(7 downto 0) := r.reg.transmit;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when SLV_ADDR =>
if HARDCADDR = 0 then
if TENBIT_SUPPORT = 1 then
v.reg.slvaddr.tba := apbi.pwdata(31);
end if;
v.reg.slvaddr.slvaddr := apbi.pwdata((I2CADDRLEN-1) downto 0);
end if;
when CTRL_ADDR =>
v.reg.ctrl.rmode := apbi.pwdata(4);
v.reg.ctrl.tmode := apbi.pwdata(3);
v.reg.ctrl.tv := apbi.pwdata(2);
v.reg.ctrl.tav := apbi.pwdata(1);
v.reg.ctrl.en := apbi.pwdata(0);
when STS_ADDR =>
v.reg.sts.tra := r.reg.sts.tra and not apbi.pwdata(1);
v.reg.sts.nak := r.reg.sts.nak and not apbi.pwdata(0);
when MSK_ADDR =>
v.reg.msk.rec := apbi.pwdata(2);
v.reg.msk.tra := apbi.pwdata(1);
v.reg.msk.nak := apbi.pwdata(0);
when TD_ADDR =>
v.reg.transmit := apbi.pwdata(7 downto 0);
when others => null;
end case;
end if;
----------------------------------------------------------------------------
-- Bus filtering
----------------------------------------------------------------------------
for i in 0 to filter-1 loop
sclfilt(i) := r.i2ci(i+1).scl; sdafilt(i) := r.i2ci(i+1).sda;
end loop; -- i
if andv(sclfilt) = '1' then v.scl := '1'; end if;
if orv(sclfilt) = '0' then v.scl := '0'; end if;
if andv(sdafilt) = '1' then v.sda := '1'; end if;
if orv(sdafilt) = '0' then v.sda := '0'; end if;
---------------------------------------------------------------------------
-- I2C slave control FSM
---------------------------------------------------------------------------
case r.slvstate is
when idle =>
-- Release bus
if (r.scl and not v.scl) = '1' then
v.sdaoen := I2C_HIZ;
end if;
when checkaddr =>
tba := r.reg.slvaddr.tba = '1';
if compaddr1stb(r.sreg, r.reg.slvaddr) then
if r.sreg(0) = I2C_READ then
if (not tba or (tba and r.active)) then
if r.reg.ctrl.tv = '1' then
-- Transmit data
v.transmit := true;
v.slvstate := handshake;
else
-- No data to transmit, NAK
if (not v.reg.sts.nak and r.reg.msk.nak) = '1' then
v.irq := '1';
end if;
v.reg.sts.nak := '1';
v.slvstate := idle;
end if;
else
-- Ten bit address with R/Wn = 1 and slave not previously
-- addressed.
v.slvstate := idle;
end if;
else
v.receive := not tba;
v.slvstate := handshake;
end if;
else
-- Slave address did not match
v.active := false;
v.slvstate := idle;
end if;
v.sreg := r.reg.transmit;
when check10bitaddr =>
if compaddr2ndb(r.sreg, r.reg.slvaddr.slvaddr) then
-- Slave has been addressed with a matching 10 bit address
-- If we receive a repeated start condition, matching address
-- and R/Wn = 1 we will transmit data. Without start condition we
-- will receive data.
v.addr := true;
v.active := true;
v.receive := true;
v.slvstate := handshake;
else
v.slvstate := idle;
end if;
when sclhold =>
-- This state is used when the device has been addressed to see if SCL
-- should be kept low until the receive register is free or the
-- transmit register is filled. It is also used when a data byte has
-- been transmitted or received to SCL low until software acknowledges
-- the transfer.
if (r.scl and not v.scl) = '1' then
v.scloen := I2C_LOW;
v.sdaoen := I2C_HIZ;
end if;
if ((r.receive and (not r.reg.sts.rec or not r.reg.ctrl.rmode) = '1') or
(r.transmit and (r.reg.ctrl.tv or not r.reg.ctrl.tmode) = '1')) then
v.slvstate := movebyte;
v.scloen := I2C_HIZ;
-- Falling edge that should be detected in movebyte may have passed
if r.transmit and v.scl = '0' then
v.sdaoen := r.sreg(7) xor OEPOL_LEVEL;
end if;
end if;
v.sreg := r.reg.transmit;
when movebyte =>
if (r.scl and not v.scl) = '1' then
if r.transmit then
v.sdaoen := r.sreg(7) xor OEPOL_LEVEL;
else
v.sdaoen := I2C_HIZ;
end if;
end if;
if (not r.scl and v.scl) = '1' then
v.sreg := r.sreg(6 downto 0) & r.sda;
if r.cnt = "111" then
if r.addr then
v.slvstate := checkaddr;
elsif r.receive nor r.transmit then
v.slvstate := check10bitaddr;
else
v.slvstate := handshake;
end if;
v.cnt := (others => '0');
else
v.cnt := r.cnt + 1;
end if;
end if;
when handshake =>
-- Falling edge
if (r.scl and not v.scl) = '1' then
if r.addr then
v.sdaoen := I2C_LOW;
elsif r.receive then
-- Receive, send ACK/NAK
-- Acknowledge byte if core has room in receive register
-- This code assumes that the core's receive register is free if we are
-- in RMODE 1. This should always be the case unless software has
-- reconfigured the core during operation.
if r.reg.sts.rec = '0' then
v.sdaoen := I2C_LOW;
v.reg.receive := r.sreg;
if r.reg.msk.rec = '1' then
v.irq := '1';
end if;
v.reg.sts.rec := '1';
else
-- NAK the byte, the master must abort the transfer
v.sdaoen := I2C_HIZ;
v.slvstate := idle;
end if;
else
-- Transmit, release bus
v.sdaoen := I2C_HIZ;
-- Byte transmitted, unset TV unless TAV is set.
v.reg.ctrl.tv := r.reg.ctrl.tav;
-- Set status bit and check if interrupt should be generated
if (not v.reg.sts.tra and r.reg.msk.tra) = '1' then
v.irq := '1';
end if;
v.reg.sts.tra := '1';
end if;
if not r.addr and r.receive and v.sdaoen = I2C_HIZ then
if (not v.reg.sts.nak and r.reg.msk.nak) = '1' then
v.irq := '1';
end if;
v.reg.sts.nak := '1';
end if;
end if;
-- Risinge edge
if (not r.scl and v.scl) = '1' then
if r.addr then
v.slvstate := movebyte;
else
if r.receive then
-- RMODE 0: Be ready to accept one more byte which will be NAK'd if
-- software has not read the receive register
-- RMODE 1: Keep SCL low until software has acknowledged received byte
if r.reg.ctrl.rmode = '0' then
v.slvstate := movebyte;
else
v.slvstate := sclhold;
end if;
else
-- Transmit, check ACK/NAK from master
-- If the master NAKs the transmitted byte the transfer has ended and
-- we should wait for the master's next action. If the master ACKs the
-- byte the core will act depending on tmode:
-- TMODE 0:
-- If the master ACKs the byte we must continue to transmit and will
-- transmit the same byte on all requests.
-- TMODE 1:
-- IF the master ACKs the byte we will keep SCL low until software has
-- put new transmit data into the transmit register.
if r.sda = I2C_ACK then
if r.reg.ctrl.tmode = '0' then
v.slvstate := movebyte;
else
v.slvstate := sclhold;
end if;
else
v.slvstate := idle;
end if;
end if;
end if;
v.addr := false;
v.sreg := r.reg.transmit;
end if;
end case;
if r.reg.ctrl.en = '1' then
-- STOP condition
if (r.scl and v.scl and not r.sda and v.sda) = '1' then
v.active := false;
v.slvstate := idle;
end if;
-- START or repeated START condition
if (r.scl and v.scl and r.sda and not v.sda) = '1' then
v.slvstate := movebyte;
v.cnt := (others => '0');
v.addr := true;
v.transmit := false;
v.receive := false;
end if;
end if;
----------------------------------------------------------------------------
-- Reset and idle operation
----------------------------------------------------------------------------
if rstn = '0' then
v.slvstate := idle;
v.reg.slvaddr.slvaddr := I2CSLVADDR;
if TENBIT_SUPPORT = 1 then v.reg.slvaddr.tba := '1';
else v.reg.slvaddr.tba := '0'; end if;
v.reg.ctrl.en := '0';
v.reg.sts := ('0', '0', '0');
v.scl := '0';
v.active := false;
v.scloen := I2C_HIZ; v.sdaoen := I2C_HIZ;
end if;
----------------------------------------------------------------------------
-- Signal assignments
----------------------------------------------------------------------------
-- Update registers
rin <= v;
-- Update outputs
apbo.prdata <= apbout;
apbo.pirq <= irq;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
i2co.scl <= '0';
i2co.scloen <= r.scloen;
i2co.sda <= '0';
i2co.sdaoen <= r.sdaoen;
i2co.enable <= r.reg.ctrl.en;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"i2cslv" & tost(pindex) & ": I2C slave rev " &
tost(I2CSLV_REV) & ", irq " & tost(pirq));
-- pragma translate_on
end architecture rtl;
|
gpl-2.0
|
b1bd239a3f6baabb06a96e029efca6ec
| 0.521523 | 3.850579 | false | false | false | false |
aortiz49/MIPS-Processor
|
Testbenches/registerFile_tb.vhd
| 1 | 1,899 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity registerFile_tb is
end registerFile_tb;
architecture behv of registerFile_tb is
component register_file
port (
clk : in std_logic;
data : in std_logic_vector (31 downto 0);
reg_write : in std_logic_vector(4 downto 0);
wr_en : in std_logic;
reg_read1 : in std_logic_vector(4 downto 0);
reg_read0 : in std_logic_vector(4 downto 0);
output1 : out std_logic_vector(31 downto 0);
output0 : out std_logic_vector(31 downto 0)
);
end component;
signal clk : std_logic := '0';
signal data : std_logic_vector (31 downto 0);
signal reg_write : std_logic_vector(4 downto 0);
signal wr_en : std_logic;
signal reg_read1 : std_logic_vector(4 downto 0);
signal reg_read0 : std_logic_vector(4 downto 0);
signal output1 : std_logic_vector(31 downto 0);
signal output0 : std_logic_vector(31 downto 0);
begin
reg_bank: register_file
port map (
clk => clk,
data => data,
reg_write => reg_write,
wr_en => wr_en,
reg_read1 => reg_read1,
reg_read0 => reg_read0,
output1 => output1,
output0 => output0
);
clk <= not clk after 10 ns;
process
begin
reg_read1 <="00";
reg_read0 <="00";
data <= x"EEEEAAAA";
reg_write <= conv_std_logic_vector(9, 5);
wr_en <='1';
wait for 20 ns;
data <= x"BABABABA";
reg_write <= "00000";
wr_en <='1';
wait for 20 ns;
data <= x"00000000";
reg_write <= "00000";
wr_en <='0';
wait for 20 ns;
data <= x"FFFFBABA";
reg_write <= "00000";
wr_en <='1';
wait for 20 ns;
data <= x"55555555";
reg_write <= "00000";
wr_en <='1';
wait for 20 ns;
data <= x"FEEDBEEF";
reg_write <= "00000";
wr_en <='1';
wait for 20 ns;
reg_read1 <="01001";
reg_read0 <="00000";
wr_en <='0';
wait for 20 ns;
reg_read1 <="00000";
reg_read0 <="00000";
wr_en <='0';
wait for 20 ns;
wait;
end process;
end behv;
|
mit
|
429d4587169aeef5ae496a9edd19c288
| 0.623486 | 2.472656 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/cycloneiii/alt/aclkout.vhd
| 3 | 4,519 |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library cycloneiii;
use cycloneiii.all;
entity aclkout is
port(
clk : in std_logic;
ddr_clk : out std_logic;
ddr_clkn: out std_logic
);
end;
architecture rtl of aclkout is
component cycloneiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic;
dfflo : out std_logic;
dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component cycloneiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
port(
i : in std_logic := '0';
oe : in std_logic := '1';
--devoe : in std_logic := '1';
o : out std_logic;
obar : out std_logic--;
--seriesterminationcontrol : in std_logic_vector(15 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal clk_reg, clkn_reg : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
out_reg0 : cycloneiii_ddio_out
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_out"
)
port map(
datainlo => gnd(0),
datainhi => vcc,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => clk_reg,
dfflo => open,
dffhi => open--,
--devclrn => vcc,
--devpor => vcc
);
outn_reg0 : cycloneiii_ddio_out
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_out"
)
port map(
datainlo => vcc,
datainhi => gnd(0),
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => clkn_reg,
dfflo => open,
dffhi => open--,
--devclrn => vcc,
--devpor => vcc
);
out_buf0 : cycloneiii_io_obuf
generic map(
open_drain_output => "false",
bus_hold => "false",
lpm_type => "cycloneiii_io_obuf"
)
port map(
i => clk_reg,
oe => vcc,
--devoe => vcc,
o => ddr_clk,
obar => open
--seriesterminationcontrol => gnd,
);
outn_buf0 : cycloneiii_io_obuf
generic map(
open_drain_output => "false",
bus_hold => "false",
lpm_type => "cycloneiii_io_obuf"
)
port map(
i => clkn_reg,
oe => vcc,
--devoe => vcc,
o => ddr_clkn,
obar => open
--seriesterminationcontrol => gnd,
);
end;
|
gpl-2.0
|
a312e2f832f8c12108997288096b762c
| 0.357159 | 4.630123 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-gr-xc6s/leon3mp.vhd
| 1 | 50,283 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic; -- 50 MHz main clock
clk2 : in std_ulogic; -- User clock
clk125 : in std_ulogic; -- 125 MHz clock from PHY
wdogn : out std_ulogic;
address : out std_logic_vector(24 downto 0);
data : inout std_logic_vector(31 downto 24);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_odt : out std_logic;
ddr_we : out std_ulogic; -- ddr write enable
ddr_ras : out std_ulogic; -- ddr ras
ddr_csn : out std_ulogic; -- ddr csn
ddr_cas : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (1 downto 0); -- ddr dqs n
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (2 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
ddr_rzq : inout std_ulogic;
ddr_zio : inout std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 ctsn
rtsn1 : out std_ulogic; -- UART1 trsn
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ctsn2 : in std_ulogic; -- UART2 ctsn
rtsn2 : out std_ulogic; -- UART2 rtsn
pio : inout std_logic_vector(17 downto 0); -- I/O port
genio : inout std_logic_vector(59 downto 0); -- I/O port
switch : in std_logic_vector(9 downto 0); -- I/O port
led : out std_logic_vector(3 downto 0); -- I/O port
erx_clk : in std_ulogic;
emdio : inout std_logic; -- ethernet PHY interface
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
emdint : in std_ulogic;
etx_clk : out std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
emdc : out std_ulogic;
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
ddc_scl : inout std_ulogic;
ddc_sda : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
spw_clk : in std_ulogic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic
);
end;
architecture rtl of leon3mp is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component IODELAY2
generic (
COUNTER_WRAPAROUND : string := "WRAPAROUND";
DATA_RATE : string := "SDR";
DELAY_SRC : string := "IO";
IDELAY2_VALUE : integer := 0;
IDELAY_MODE : string := "NORMAL";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
SERDES_MODE : string := "NONE";
SIM_TAPDELAY_VALUE : integer := 75
);
port (
BUSY : out std_ulogic;
DATAOUT : out std_ulogic;
DATAOUT2 : out std_ulogic;
DOUT : out std_ulogic;
TOUT : out std_ulogic;
CAL : in std_ulogic;
CE : in std_ulogic;
CLK : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
IOCLK0 : in std_ulogic;
IOCLK1 : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
constant use_eth_input_delay : integer := 1;
constant use_eth_output_delay : integer := 1;
constant use_eth_data_output_delay : integer := 1;
constant use_eth_input_delay_clk : integer := 0;
constant use_gtx_clk : integer := 0;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal leds : std_logic_vector(3 downto 0); -- I/O port
signal apbi, apbi2 : apb_slv_in_type;
signal apbo, apbo2 : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2, cgi3 : clkgen_in_type;
signal cgo, cgo2, cgo3 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gmiii, rgmiii, rgmiii_buf, rgmii_pad : eth_in_type;
signal gmiio, rgmiio : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal gpioi2 : gpio_in_type;
signal gpioo2 : gpio_out_type;
signal gpioi3 : gpio_in_type;
signal gpioo3 : gpio_out_type;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lock, calib_done, clkml, lclk, rst, ndsuact, wdogl : std_ulogic := '0';
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ethclk, ddr2clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal spmi2 : spimctrl_in_type;
signal spmo2 : spimctrl_out_type;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN;
constant DDR2_FREQ : integer := 200000; -- DDR2 input frequency in KHz
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(CFG_SPW_NUM*CFG_SPW_PORTS-1 downto 0);
signal stmp : std_logic_vector(CFG_SPW_NUM*CFG_SPW_PORTS-1 downto 0);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM*CFG_SPW_PORTS);
signal spw_rstn : std_ulogic;
signal spw_rstn_sync : std_ulogic;
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal rstgtxn : std_logic;
signal idelay_reset_cnt : std_logic_vector(3 downto 0);
signal idelay_cal_cnt : std_logic_vector(3 downto 0);
signal idelayctrl_reset : std_logic;
signal idelayctrl_cal : std_logic;
signal rgmiii_rx_clk_n : std_logic;
signal rgmiii_rx_clk_n_buf : std_logic;
signal rgmiio_tx_clk,rgmiio_tx_en : std_logic;
signal rgmiio_txd : std_logic_vector(3 downto 0);
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
constant SPW_LOOP_BACK : integer := 0;
signal video_clk, clk50, clk100, spw100 : std_logic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal clk_125, clk_125_pll, clk_125_bufg : std_ulogic;
signal nerror : std_ulogic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clk50 : signal is true;
attribute syn_preserve of clk50 : signal is true;
attribute keep of clk50 : signal is true;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
attribute syn_preserve of ddr2clk : signal is true;
attribute keep of ddr2clk : signal is true;
attribute syn_keep of ddr2clk : signal is true;
attribute syn_preserve of spw100 : signal is true;
attribute keep of spw100 : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of clkm : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
ddr2clk <= lclk;
ethclk <= lclk;
no_clk_mig : if CFG_MIG_DDR2 = 0 generate
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, clk50, clk100);
rst0 : rstgen -- reset generator
generic map(syncin => 1)
port map (rst, clkm, lock, rstn, rstraw);
end generate;
clk_mig : if CFG_MIG_DDR2 = 1 generate
clk50 <= clkm;
rstraw <= rst;
cgo.clklock <= '1';
end generate;
resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
lock <= cgo.clklock and calib_done;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 16)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE, CFG_BP,
CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
nerror <= dbgo(0).error;
led1_pad : odpad generic map (tech => padtech) port map (led(1), nerror);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (switch(7), dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (switch(8), dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 /= 0 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 25, tech => padtech)
port map (address, memo.address(24 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
bdr : for i in 0 to 0 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
nomctrl : if CFG_MCTRL_LEON2 = 0 generate
romsn <= '1'; ahbso(0) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
-- pragma translate_on
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr_csn <= '0';
mig_gen : if (CFG_MIG_DDR2 = 1) generate
ddrc : entity work.ahb2mig_grxc6s_2p
generic map(
hindex => 4, haddr => 16#400#, hmask => 16#F80#,
pindex => 0, paddr => 0, vgamst => CFG_SVGA_ENABLE, vgaburst => 64,
clkdiv => 10)
port map(
mcb3_dram_dq => ddr_dq,
mcb3_dram_a => ddr_ad,
mcb3_dram_ba => ddr_ba,
mcb3_dram_ras_n => ddr_ras,
mcb3_dram_cas_n => ddr_cas,
mcb3_dram_we_n => ddr_we,
mcb3_dram_odt => ddr_odt,
mcb3_dram_cke => ddr_cke,
mcb3_dram_dm => ddr_dm(0),
mcb3_dram_udqs => ddr_dqs(1),
mcb3_dram_udqs_n => ddr_dqsn(1),
mcb3_rzq => ddr_rzq,
mcb3_zio => ddr_zio,
mcb3_dram_udm => ddr_dm(1),
mcb3_dram_dqs => ddr_dqs(0),
mcb3_dram_dqs_n => ddr_dqsn(0),
mcb3_dram_ck => ddr_clk,
mcb3_dram_ck_n => ddr_clkb,
ahbsi => ahbsi,
ahbso => ahbso(4),
ahbmi => vahbmi,
ahbmo => vahbmo,
apbi => apbi2,
apbo => apbo2(0),
calib_done => calib_done,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem_n => ddr2clk,
clk_mem_p => ddr2clk,
test_error => open,
clk_125 => clk_125,
clk_100 => clk100
);
end generate;
noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate calib_done <= '1'; end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 3, hirq => 7, faddr => 16#e00#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(3), spmi, spmo);
-- MISO is shared with Flash data 0
spmi.miso <= memi.data(24);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
nospimc: if ((CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 1) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 0))generate
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, '0');
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, '0');
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
apb1 : apbctrl -- AHB/APB bridge
generic map (hindex => 13, haddr => CFG_APBADDR+1, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(13), apbi2, apbo2 );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
rts1_pad : outpad generic map (tech => padtech) port map (rtsn2, '0');
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
wden : if CFG_GPT_WDOGEN /= 0 generate
wdogl <= gpto.wdogn or not rstn;
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, wdogl);
end generate;
wddis : if CFG_GPT_WDOGEN = 0 generate
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, vcc);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
video_clk <= not ethclk;
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 20000, clk1 => 0, --1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk2 => 0, clk3 => 0, burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, vahbmi,
vahbmo, clk_sel);
end generate;
--b0 : techbuf generic map (2, fabtech) port map (clk50, video_clk);
video_clk <= clk50;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : entity work.svga2ch7301c generic map (tech => fabtech, dynamic => 1)
port map (clkm, vgao, video_clk, clkvga_p, clkvga_n,
lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 3)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 16)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
p0 : if (CFG_CAN = 0) or (CFG_CAN_NUM = 1) generate
pio_pads : for i in 1 to 2 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
p1 : if (CFG_CAN = 0) generate
pio_pads : for i in 4 to 5 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
pio_pad0 : iopad generic map (tech => padtech)
port map (pio(0), gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
pio_pad1 : iopad generic map (tech => padtech)
port map (pio(3), gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
pio_pads : for i in 6 to 15 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-- make an additonal 32 bit GPIO port for genio(31..0)
gpio1 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio1: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 32)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(11),
gpioi => gpioi2, gpioo => gpioo2);
pio_pads : for i in 0 to 31 generate
pio_pad : iopad generic map (tech => padtech)
port map (genio(i), gpioo2.dout(i), gpioo2.oen(i), gpioi2.din(i));
end generate;
end generate;
gpio2 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio2: grgpio
generic map(pindex => 12, paddr => 12, imask => CFG_GRGPIO_IMASK, nbits => 28)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(12),
gpioi => gpioi3, gpioo => gpioo3);
pio_pads : for i in 0 to 27 generate
pio_pad : iopad generic map (tech => padtech)
port map (genio(i+32), gpioo3.dout(i), gpioo3.oen(i), gpioi3.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 13, paddr => 13, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(13));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 6, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 1,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => gmiii, etho => gmiio);
end generate;
led(3 downto 2) <= not (gmiio.gbit & gmiio.speed);
noethindelay0 : if (use_eth_input_delay = 0) generate
rgmiii.rx_dv <= rgmiii_buf.rx_dv;
rgmiii.rxd <= rgmiii_buf.rxd;
end generate;
noethoutdelay0 : if (use_eth_output_delay = 0) generate
rgmiio_tx_clk <= rgmiio.tx_clk;
end generate;
noethdataoutdelay0 : if (use_eth_data_output_delay = 0) generate
rgmiio_tx_en <= rgmiio.tx_en;
rgmiio_txd <= rgmiio.txd(3 downto 0);
end generate;
ethindelay0 : if (use_eth_input_delay /= 0) generate
erx_clk0 : if (use_eth_input_delay_clk /= 0) generate
delay_rgmii_rx_clk : IODELAY2 generic map(
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
IDELAY_VALUE => 0 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => rgmiii_buf.rx_clk,
T => '1',
ODATAIN => '0',
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => rgmiii.rx_clk,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => OPEN
);
end generate;
delay_rgmii_rx_ctl0 : IODELAY2 generic map(
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
IDELAY_VALUE => 80 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => rgmiii_buf.rx_dv,
T => '1',
ODATAIN => '0',
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => rgmiii.rx_dv,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => OPEN
);
rgmii_rxd : for i in 0 to 3 generate
delay_rgmii_rxd0 : IODELAY2 generic map(
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
IDELAY_VALUE => 80 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => rgmiii_buf.rxd(i),
T => '1',
ODATAIN => '0',
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => rgmiii.rxd(i),
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => OPEN
);
end generate;
end generate;
ethoutdelay0 : if (use_eth_output_delay /= 0) generate
delay_rgmii_tx_clk0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
ODELAY_VALUE => 30 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.tx_clk,
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_tx_clk
);
end generate;
ethoutdatadelay0 : if (use_eth_data_output_delay /= 0) generate
delay_rgmii_tx_en0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
ODELAY_VALUE => 0
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.tx_en,
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_tx_en
);
rgmii_txd : for i in 0 to 3 generate
delay_rgmii_txd0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
ODELAY_VALUE => 0
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.txd(i),
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_txd(i)
);
end generate;
end generate;
rgmii0 : rgmii generic map (pindex => 15, paddr => 16#010#, pmask => 16#ff0#, tech => fabtech,
gmii => CFG_GRETH1G, debugmem => 1, abits => 8, no_clk_mux => 0,
pirq => 15, use90degtxclk => 0)
port map (rstn, gmiii, gmiio, rgmiii, rgmiio, clkm, rstn, apbi, apbo(15));
ethpads : if (CFG_GRETH = 1) generate -- eth pads
etxc_pad : outpad generic map (tech => padtech)
port map (etx_clk, rgmiio_tx_clk);
erx_clk1 : if (use_eth_input_delay_clk = 0) generate
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, rgmiii.rx_clk);
end generate;
erx_clk2 : if (use_eth_input_delay_clk /= 0) generate
erxc_pad : inpad generic map (tech => padtech)
port map (erx_clk, rgmii_pad.rx_clk);
erxc_bufg0 : BUFG port map (O => rgmiii_buf.rx_clk, I => rgmii_pad.rx_clk);
end generate;
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, rgmiii_buf.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, rgmiii_buf.rx_dv);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, rgmiio_txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, rgmiio_tx_en);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, rgmiio.mdio_o, rgmiio.mdio_oe, rgmiii.mdio_i);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, rgmiio.mdc);
emdint_pad : inpad generic map (tech => padtech)
port map (emdint, rgmiii.mdint);
gtx_clk0 : if (use_gtx_clk = 0) generate
-- Use MIG PLL
-- Add to UCF (only if there is no BUFG left):
-- PIN "ethpads.gtx_clk0.clk_125_bufg0.O" CLOCK_DEDICATED_ROUTE = FALSE;
clk_125_bufg0 : BUFG port map (O => clk_125_bufg, I => clk_125);
rgmiii.gtx_clk <= clk_125_bufg;
end generate;
gtx_clk1 : if (use_gtx_clk = 1) generate
-- Incoming 125Mhz ref clock
clk125_pad : clkpad generic map (tech => padtech, arch => 3)
port map (clk125, rgmiii.gtx_clk);
end generate;
gtx_clk2 : if (use_gtx_clk = 2) generate
-- Use Separate PLL
-- Add to UCF (only if there is no BUFG left):
-- PIN "ethpads.gtx_clk2.clkgen0/xc3s.v/bufg0.O" CLOCK_DEDICATED_ROUTE =FALSE;
-- PIN "ethpads.gtx_clk2.clk_125_bufg0.O" CLOCK_DEDICATED_ROUTE = FALSE;
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw;
clkgen0 : clkgen -- clock generator
generic map (clktech, 5, 2, CFG_MCTRL_SDEN,CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (clkm, clkm, clk_125_pll, open, open, open, open, cgi2, cgo2, open, open, open);
clk_125_bufg0 : BUFG port map (O => clk_125_bufg, I => clk_125_pll);
rgmiii.gtx_clk <= clk_125_bufg;
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Multi-core CAN ---------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 4, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(4), can_lrx, can_ltx );
can_tx_pad1 : iopad generic map (tech => padtech)
port map (pio(5), can_ltx(0), gnd, gpioi.din(5));
can_rx_pad1 : iopad generic map (tech => padtech)
port map (pio(4), gnd, vcc, can_lrx(0));
canpas : if CFG_CAN_NUM = 2 generate
can_tx_pad2 : iopad generic map (tech => padtech)
port map (pio(2), can_ltx(1), gnd, gpioi.din(2));
can_rx_pad2 : iopad generic map (tech => padtech)
port map (pio(1), gnd, vcc, can_lrx(1));
end generate;
end generate;
-- standby controlled by pio(3) and pio(0)
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
-- temporary, just to make sure the SPW pins are instantiated correctly
no_spw : if CFG_SPW_EN = 0 generate
pad_gen: for i in 0 to CFG_SPW_NUM-1 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x33v)
port map (spw_rxdp(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x33v)
port map (spw_rxsp(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txdp(i), spw_txdn(i), dtmp(i), gnd);
spw_txs_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txsp(i), spw_txsn(i), stmp(i), gnd);
end generate;
end generate;
spw : if CFG_SPW_EN > 0 generate
core0: if CFG_SPW_GRSPW = 1 generate
spw_rxtxclk <= clkm;
spw_rstn <= rstn;
end generate;
core1 : if CFG_SPW_GRSPW = 2 generate
spw_rxtxclk <= clk100;
spw_rstn_sync_proc : process(rstn,spw_rxtxclk)
begin
if rstn = '0' then
spw_rstn_sync <= '0';
spw_rstn <= '0';
elsif rising_edge(spw_rxtxclk) then
spw_rstn_sync <= '1';
spw_rstn <= spw_rstn_sync;
end if;
end process spw_rstn_sync_proc;
end generate;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT,
rxclkbuftype => 2)
port map(
rstn => spw_rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j*2+1 downto j*2),
dov => spwi(i).dv(j*2+1 downto j*2),
dconnect => spwi(i).dconnect(j*2+1 downto j*2),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j));
end generate;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dv(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
end generate;
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 2,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j),
ndo => spwi(i).nd(j*5+4 downto j*5),
dconnect => spwi(i).dconnect(j*2+1 downto j*2));
end generate spw_inputloop;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(1) <= '0'; -- For second port
spwi(i).d(3 downto 2) <= "00"; -- For GRSPW2 second port
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
end generate spw1_input;
sw0 : grspwm generic map(tech => memtech,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+i,
sysfreq => CPU_FREQ, usegen => 1,
pindex => 10+i, paddr => 10+i, pirq => 10+i,
nsync => 1, rmap => CFG_SPW_RMAP, rxunaligned => CFG_SPW_RXUNAL,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 2, dmachan => CFG_SPW_DMACHAN,
rmapbufs => CFG_SPW_RMAPBUF, ft => CFG_SPW_FT, ports => CFG_SPW_PORTS,
spwcore => CFG_SPW_GRSPW, netlist => CFG_SPW_NETLIST,
rxtx_sameclk => CFG_SPW_RTSAME, input_type => CFG_SPW_INPUT,
output_type => CFG_SPW_OUTPUT)
port map(rstn, clkm, spw_rxclk(i*CFG_SPW_PORTS), spw_rxclk(i*CFG_SPW_PORTS+1),
spw_rxtxclk, spw_rxtxclk, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+i),
apbi2, apbo2(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8) when CFG_SPW_GRSPW = 1
else conv_std_logic_vector(10-1, 8);
spwi(i).tickinraw <= '0';
spwi(i).timein <= (others => '0');
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
swportloop1: for j in 0 to CFG_SPW_PORTS-1 generate
spwlb0 : if SPW_LOOP_BACK = 1 generate
dtmp(i*CFG_SPW_PORTS+j) <= spwo(i).d(j); stmp(i*CFG_SPW_PORTS+j) <= spwo(i).s(j);
end generate;
nospwlb0 : if SPW_LOOP_BACK = 0 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x33v, 1)
port map (spw_rxdp(i*CFG_SPW_PORTS+j), spw_rxdn(i*CFG_SPW_PORTS+j), dtmp(i*CFG_SPW_PORTS+j));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x33v, 1)
port map (spw_rxsp(i*CFG_SPW_PORTS+j), spw_rxsn(i*CFG_SPW_PORTS+j), stmp(i*CFG_SPW_PORTS+j));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txdp(i*CFG_SPW_PORTS+j), spw_txdn(i*CFG_SPW_PORTS+j), spwo(i).d(j), gnd);
spw_txs_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txsp(i*CFG_SPW_PORTS+j), spw_txsn(i*CFG_SPW_PORTS+j), spwo(i).s(j), gnd);
end generate;
end generate;
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-XC6S-LX75 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
9b382350a50a140c908c5fd2f66a7d0a
| 0.551757 | 3.426206 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-jopdesign-ep1c12/ahbrom.vhd
| 6 | 6,733 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbram
-- File: ahbram.vhd
-- Author: Jiri Gaisler - Gaisler Reserch
-- Description: AHB ram. 0-waitstate read, 0/1-waitstate write.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 336;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03002040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"87444000";
when 16#0002D# => romdata <= X"8730E01C";
when 16#0002E# => romdata <= X"8688E00F";
when 16#0002F# => romdata <= X"12800015";
when 16#00030# => romdata <= X"03200000";
when 16#00031# => romdata <= X"84102233";
when 16#00032# => romdata <= X"C4204000";
when 16#00033# => romdata <= X"0539A81B";
when 16#00034# => romdata <= X"8410A260";
when 16#00035# => romdata <= X"C4206004";
when 16#00036# => romdata <= X"050003FC";
when 16#00037# => romdata <= X"C4206008";
when 16#00038# => romdata <= X"82103860";
when 16#00039# => romdata <= X"C4004000";
when 16#0003A# => romdata <= X"8530A00C";
when 16#0003B# => romdata <= X"03000004";
when 16#0003C# => romdata <= X"82106009";
when 16#0003D# => romdata <= X"80A04002";
when 16#0003E# => romdata <= X"12800006";
when 16#0003F# => romdata <= X"033FFC00";
when 16#00040# => romdata <= X"82106100";
when 16#00041# => romdata <= X"0539A81B";
when 16#00042# => romdata <= X"8410A260";
when 16#00043# => romdata <= X"C4204000";
when 16#00044# => romdata <= X"3D1003FF";
when 16#00045# => romdata <= X"BC17A3E0";
when 16#00046# => romdata <= X"9C27A060";
when 16#00047# => romdata <= X"03100000";
when 16#00048# => romdata <= X"81C04000";
when 16#00049# => romdata <= X"01000000";
when 16#0004A# => romdata <= X"01000000";
when 16#0004B# => romdata <= X"01000000";
when 16#0004C# => romdata <= X"01000000";
when 16#0004D# => romdata <= X"01000000";
when 16#0004E# => romdata <= X"01000000";
when 16#0004F# => romdata <= X"01000000";
when 16#00050# => romdata <= X"00000000";
when 16#00051# => romdata <= X"00000000";
when 16#00052# => romdata <= X"00000000";
when 16#00053# => romdata <= X"00000000";
when 16#00054# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
gpl-2.0
|
d3734e7f4ac651da74d7ca2cedec4664
| 0.585772 | 3.36987 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-xc7z020/leon3mp.vhd
| 1 | 23,854 |
-----------------------------------------------------------------------------
-- LEON3 Zedboard Demonstration design
-- Copyright (C) 2012 Fredrik Ringhage, Aeroflex Gaisler
-- Modifed by Jiri Gaisler to provide working AXI interface, 2014-04-05
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.config.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false
);
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB : inout std_logic;
processing_system7_0_PS_CLK : inout std_logic;
processing_system7_0_PS_PORB : inout std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : inout std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
component leon3_zedboard_stub
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
S_AXI_GP0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_arready : out STD_LOGIC;
S_AXI_GP0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arvalid : in STD_LOGIC;
S_AXI_GP0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_awready : out STD_LOGIC;
S_AXI_GP0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awvalid : in STD_LOGIC;
S_AXI_GP0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_bready : in STD_LOGIC;
S_AXI_GP0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_bvalid : out STD_LOGIC;
S_AXI_GP0_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_rlast : out STD_LOGIC;
S_AXI_GP0_rready : in STD_LOGIC;
S_AXI_GP0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_rvalid : out STD_LOGIC;
S_AXI_GP0_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_wid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_wlast : in STD_LOGIC;
S_AXI_GP0_wready : out STD_LOGIC;
S_AXI_GP0_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_wvalid : in STD_LOGIC
);
end component;
constant maxahbm : integer := (CFG_LEON3*CFG_NCPU)+CFG_AHB_JTAG;
constant maxahbs : integer := 8;
constant maxapbs : integer := 16;
signal vcc, gnd : std_logic;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rsti, rst : std_ulogic;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
constant BOARD_FREQ : integer := 83333; -- CLK0 frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ;
signal stati : ahbstat_in_type;
constant CIDSZ : integer := 6;
constant CLENSZ : integer := 4;
signal S_AXI_GP0_araddr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_arburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_arcache : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_arid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_arlen : STD_LOGIC_VECTOR ( CLENSZ-1 downto 0 );
signal S_AXI_GP0_arlock : STD_LOGIC_VECTOR ( 1 downto 0 ); --
signal S_AXI_GP0_arprot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_arqos : STD_LOGIC_VECTOR ( 3 downto 0 ); --
signal S_AXI_GP0_awqos : STD_LOGIC_VECTOR ( 3 downto 0 ); --
signal S_AXI_GP0_arready : STD_LOGIC;
signal S_AXI_GP0_arsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_arvalid : STD_LOGIC;
signal S_AXI_GP0_awaddr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_awburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_awcache : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_awid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_awlen : STD_LOGIC_VECTOR ( CLENSZ-1 downto 0 );
signal S_AXI_GP0_awlock : STD_LOGIC_VECTOR ( 1 downto 0 ); --
signal S_AXI_GP0_awprot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_awready : STD_LOGIC;
signal S_AXI_GP0_awsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_awvalid : STD_LOGIC;
signal S_AXI_GP0_bid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_bready : STD_LOGIC;
signal S_AXI_GP0_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_bvalid : STD_LOGIC;
signal S_AXI_GP0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_rid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_rlast : STD_LOGIC;
signal S_AXI_GP0_rready : STD_LOGIC;
signal S_AXI_GP0_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_rvalid : STD_LOGIC;
signal S_AXI_GP0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_wlast : STD_LOGIC;
signal S_AXI_GP0_wready : STD_LOGIC;
signal S_AXI_GP0_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_wvalid : STD_LOGIC;
signal S_AXI_GP0_wid : STD_LOGIC_VECTOR ( 5 downto 0 ); --
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
reset_pad : inpad generic map (level => cmos, voltage => x18v, tech => padtech)
port map (button(0), rsti);
rstn <= rst and not rsti;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
nahbm => maxahbm, nahbs => maxahbs)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon3_0 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
nocpu : if CFG_LEON3 = 0 generate dbgo(0) <= dbgo_none; end generate;
led1_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v) port map (led(1), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= gpioi.din(0);
end generate;
dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v) port map (led(0), dsuo.active);
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_LEON3*CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_LEON3*CFG_NCPU),
open, open, open, open, open, open, open, gnd);
end generate;
leon3_zedboard_stub_i : leon3_zedboard_stub
port map (
DDR_ck_p => processing_system7_0_DDR_Clk,
DDR_ck_n => processing_system7_0_DDR_Clk_n,
DDR_cke => processing_system7_0_DDR_CKE,
DDR_cs_n => processing_system7_0_DDR_CS_n,
DDR_ras_n => processing_system7_0_DDR_RAS_n,
DDR_cas_n => processing_system7_0_DDR_CAS_n,
DDR_we_n => processing_system7_0_DDR_WEB_pin,
DDR_ba => processing_system7_0_DDR_BankAddr,
DDR_addr => processing_system7_0_DDR_Addr,
DDR_odt => processing_system7_0_DDR_ODT,
DDR_reset_n => processing_system7_0_DDR_DRSTB,
DDR_dq => processing_system7_0_DDR_DQ,
DDR_dm => processing_system7_0_DDR_DM,
DDR_dqs_p => processing_system7_0_DDR_DQS,
DDR_dqs_n => processing_system7_0_DDR_DQS_n,
FCLK_CLK0 => clkm,
FCLK_RESET0_N => rst,
FIXED_IO_mio => processing_system7_0_MIO,
FIXED_IO_ps_srstb => processing_system7_0_PS_SRSTB,
FIXED_IO_ps_clk => processing_system7_0_PS_CLK,
FIXED_IO_ps_porb => processing_system7_0_PS_PORB,
FIXED_IO_ddr_vrn => processing_system7_0_DDR_VRN,
FIXED_IO_ddr_vrp => processing_system7_0_DDR_VRP,
S_AXI_GP0_araddr => S_AXI_GP0_araddr,
S_AXI_GP0_arburst(1 downto 0) => S_AXI_GP0_arburst(1 downto 0),
S_AXI_GP0_arcache(3 downto 0) => S_AXI_GP0_arcache(3 downto 0),
S_AXI_GP0_arid => S_AXI_GP0_arid,
S_AXI_GP0_arlen => S_AXI_GP0_arlen,
S_AXI_GP0_arlock => S_AXI_GP0_arlock,
S_AXI_GP0_arprot(2 downto 0) => S_AXI_GP0_arprot(2 downto 0),
S_AXI_GP0_arqos => S_AXI_GP0_arqos,
S_AXI_GP0_awqos => S_AXI_GP0_awqos,
S_AXI_GP0_arready => S_AXI_GP0_arready,
S_AXI_GP0_arsize(2 downto 0) => S_AXI_GP0_arsize(2 downto 0),
S_AXI_GP0_arvalid => S_AXI_GP0_arvalid,
S_AXI_GP0_awaddr => S_AXI_GP0_awaddr,
S_AXI_GP0_awburst(1 downto 0) => S_AXI_GP0_awburst(1 downto 0),
S_AXI_GP0_awcache(3 downto 0) => S_AXI_GP0_awcache(3 downto 0),
S_AXI_GP0_awid => S_AXI_GP0_awid,
S_AXI_GP0_awlen => S_AXI_GP0_awlen,
S_AXI_GP0_awlock => S_AXI_GP0_awlock,
S_AXI_GP0_awprot(2 downto 0) => S_AXI_GP0_awprot(2 downto 0),
S_AXI_GP0_awready => S_AXI_GP0_awready,
S_AXI_GP0_awsize(2 downto 0) => S_AXI_GP0_awsize(2 downto 0),
S_AXI_GP0_awvalid => S_AXI_GP0_awvalid,
S_AXI_GP0_bid => S_AXI_GP0_bid,
S_AXI_GP0_bready => S_AXI_GP0_bready,
S_AXI_GP0_bresp(1 downto 0) => S_AXI_GP0_bresp(1 downto 0),
S_AXI_GP0_bvalid => S_AXI_GP0_bvalid,
S_AXI_GP0_rdata(31 downto 0) => S_AXI_GP0_rdata(31 downto 0),
S_AXI_GP0_rid => S_AXI_GP0_rid,
S_AXI_GP0_rlast => S_AXI_GP0_rlast,
S_AXI_GP0_rready => S_AXI_GP0_rready,
S_AXI_GP0_rresp(1 downto 0) => S_AXI_GP0_rresp(1 downto 0),
S_AXI_GP0_rvalid => S_AXI_GP0_rvalid,
S_AXI_GP0_wdata(31 downto 0) => S_AXI_GP0_wdata(31 downto 0),
S_AXI_GP0_wid => S_AXI_GP0_wid,
S_AXI_GP0_wlast => S_AXI_GP0_wlast,
S_AXI_GP0_wready => S_AXI_GP0_wready,
S_AXI_GP0_wstrb(3 downto 0) => S_AXI_GP0_wstrb(3 downto 0),
S_AXI_GP0_wvalid => S_AXI_GP0_wvalid
);
ahb2axi0 : entity work.ahb2axi
generic map(
hindex => 3, haddr => 16#400#, hmask => 16#F00#,
pindex => 0, paddr => 0, cidsz => CIDSZ, clensz => CLENSZ)
port map(
rstn => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(3),
apbi => apbi,
apbo => apbo(0),
M_AXI_araddr => S_AXI_GP0_araddr,
M_AXI_arburst(1 downto 0) => S_AXI_GP0_arburst(1 downto 0),
M_AXI_arcache(3 downto 0) => S_AXI_GP0_arcache(3 downto 0),
M_AXI_arid => S_AXI_GP0_arid,
M_AXI_arlen => S_AXI_GP0_arlen,
M_AXI_arlock => S_AXI_GP0_arlock,
M_AXI_arprot(2 downto 0) => S_AXI_GP0_arprot(2 downto 0),
M_AXI_arqos => S_AXI_GP0_arqos,
M_AXI_arready => S_AXI_GP0_arready,
M_AXI_arsize(2 downto 0) => S_AXI_GP0_arsize(2 downto 0),
M_AXI_arvalid => S_AXI_GP0_arvalid,
M_AXI_awaddr => S_AXI_GP0_awaddr,
M_AXI_awburst(1 downto 0) => S_AXI_GP0_awburst(1 downto 0),
M_AXI_awcache(3 downto 0) => S_AXI_GP0_awcache(3 downto 0),
M_AXI_awid => S_AXI_GP0_awid,
M_AXI_awlen => S_AXI_GP0_awlen,
M_AXI_awlock => S_AXI_GP0_awlock,
M_AXI_awprot(2 downto 0) => S_AXI_GP0_awprot(2 downto 0),
M_AXI_awqos => S_AXI_GP0_awqos,
M_AXI_awready => S_AXI_GP0_awready,
M_AXI_awsize(2 downto 0) => S_AXI_GP0_awsize(2 downto 0),
M_AXI_awvalid => S_AXI_GP0_awvalid,
M_AXI_bid => S_AXI_GP0_bid,
M_AXI_bready => S_AXI_GP0_bready,
M_AXI_bresp(1 downto 0) => S_AXI_GP0_bresp(1 downto 0),
M_AXI_bvalid => S_AXI_GP0_bvalid,
M_AXI_rdata(31 downto 0) => S_AXI_GP0_rdata(31 downto 0),
M_AXI_rid => S_AXI_GP0_rid,
M_AXI_rlast => S_AXI_GP0_rlast,
M_AXI_rready => S_AXI_GP0_rready,
M_AXI_rresp(1 downto 0) => S_AXI_GP0_rresp(1 downto 0),
M_AXI_rvalid => S_AXI_GP0_rvalid,
M_AXI_wdata(31 downto 0) => S_AXI_GP0_wdata(31 downto 0),
M_AXI_wlast => S_AXI_GP0_wlast,
M_AXI_wready => S_AXI_GP0_wready,
M_AXI_wstrb(3 downto 0) => S_AXI_GP0_wstrb(3 downto 0),
M_AXI_wvalid => S_AXI_GP0_wvalid
);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
irqgen : if CFG_LEON3 = 1 generate
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
end generate;
irqctrl : if (CFG_IRQ3_ENABLE + CFG_LEON3) /= 2 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => 0)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 8 to 10 generate
pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (button(i-8+1), gpioi.din(i));
end generate;
pio_pads3 : for i in 11 to 14 generate
pio_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (led(i-11+4), gpioo.dout(i));
end generate;
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
hready_pad : outpad generic map (level => cmos, voltage => x33v, tech => padtech)
port map (led(2), ahbmi.hready);
rsti_pad : outpad generic map (level => cmos, voltage => x33v, tech => padtech)
port map (led(3), rsti);
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(0));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0_gen : if (testahb = true) generate
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
end generate;
-- pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (maxahbs+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx Zedboard Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
f46ca8f156029f9ede0a582927e9e80d
| 0.569925 | 3.243677 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-kc705/testbench.vhd
| 1 | 18,979 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := true;
USE_MIG_INTERFACE_MODEL : boolean := false
);
end;
architecture behav of testbench is
-- DDR3 Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
constant promfile : string := "prom.srec"; -- rom contents
constant ramfile : string := "ram.srec"; -- ram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0';
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(15 downto 0);
signal button : std_logic_vector(3 downto 0) := "0000";
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal adv : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal txd1 , rxd1 , dsurx : std_logic;
signal txd2 , rxd2 , dsutx : std_logic;
signal ctsn1 , rtsn1 , dsuctsn : std_ulogic;
signal ctsn2 , rtsn2 , dsurtsn : std_ulogic;
signal phy_gtxclk : std_logic := '0';
signal phy_txer : std_ulogic;
signal phy_txd : std_logic_vector(7 downto 0);
signal phy_txctl_txen : std_ulogic;
signal phy_txclk : std_ulogic;
signal phy_rxer : std_ulogic;
signal phy_rxd : std_logic_vector(7 downto 0);
signal phy_rxctl_rxdv : std_ulogic;
signal phy_rxclk : std_ulogic;
signal phy_reset : std_ulogic;
signal phy_mdio : std_logic;
signal phy_mdc : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_col : std_ulogic;
signal phy_int : std_ulogic;
signal phy_rxdl : std_logic_vector(7 downto 0);
signal phy_txdl : std_logic_vector(7 downto 0);
signal clk27 : std_ulogic := '0';
signal clk200p : std_ulogic := '0';
signal clk200n : std_ulogic := '1';
signal clk33 : std_ulogic := '0';
signal clkethp : std_ulogic := '0';
signal clkethn : std_ulogic := '1';
signal txp1 : std_logic;
signal txn : std_logic;
signal rxp : std_logic := '1';
signal rxn : std_logic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR3 memory
signal ddr3_dq : std_logic_vector(63 downto 0);
signal ddr3_dqs_p : std_logic_vector(7 downto 0);
signal ddr3_dqs_n : std_logic_vector(7 downto 0);
signal ddr3_addr : std_logic_vector(13 downto 0);
signal ddr3_ba : std_logic_vector(2 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_ck_p : std_logic_vector(0 downto 0);
signal ddr3_ck_n : std_logic_vector(0 downto 0);
signal ddr3_cke : std_logic_vector(0 downto 0);
signal ddr3_cs_n : std_logic_vector(0 downto 0);
signal ddr3_dm : std_logic_vector(7 downto 0);
signal ddr3_odt : std_logic_vector(0 downto 0);
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(3 downto 0); -- I/O port
signal led : std_logic_vector(6 downto 0); -- I/O port
constant lresp : boolean := false;
signal tdqs_n : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_rx_clk : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
reset : in std_ulogic;
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
address : out std_logic_vector(25 downto 0);
data : inout std_logic_vector(15 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
adv : out std_logic;
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
dsurx : in std_ulogic;
dsutx : out std_ulogic;
dsuctsn : in std_ulogic;
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(3 downto 0);
led : out std_logic_vector(6 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
phy_gtxclk : out std_logic;
--phy_txer : out std_ulogic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txctl_txen : out std_ulogic;
--phy_txclk : in std_ulogic;
--phy_rxer : in std_ulogic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxctl_rxdv : in std_ulogic;
phy_rxclk : in std_ulogic;
phy_reset : out std_ulogic;
phy_mdio : inout std_logic;
phy_mdc : out std_ulogic;
phy_int : in std_ulogic
);
end component;
begin
-- clock and reset
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
clkethp <= not clkethp after 4 ns;
clkethn <= not clkethp after 4 ns;
rst <= not dsurst;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
button <= "0000";
switch(2 downto 0) <= "000";
cpu : leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow,
testahb => testahb,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION,
USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL
)
port map (
reset => rst,
clk200p => clk200p,
clk200n => clk200n,
address => address,
data => data,
oen => oen,
writen => writen,
romsn => romsn,
adv => adv,
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
dsurx => dsurx,
dsutx => dsutx,
dsuctsn => dsuctsn,
dsurtsn => dsurtsn,
button => button,
switch => switch,
led => led,
iic_scl => iic_scl,
iic_sda => iic_sda,
gtrefclk_p => clkethp,
gtrefclk_n => clkethn,
phy_gtxclk => phy_gtxclk,
--phy_txer => phy_txer,
phy_txd => phy_txd(3 downto 0),
phy_txctl_txen => phy_txctl_txen,
--phy_txclk => phy_txclk,
--phy_rxer => phy_rxer,
phy_rxd => phy_rxd(3 downto 0)'delayed(2 ns),
phy_rxctl_rxdv => phy_rxctl_rxdv'delayed(2 ns),
phy_rxclk => phy_rxclk,
phy_reset => phy_reset,
phy_mdio => phy_mdio,
phy_mdc => phy_mdc,
phy_int => phy_int
);
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 22, fname => promfile)
port map (address(21 downto 0), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
-- Memory Models instantiations
gen_mem_model : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddr3mem : if (CFG_MIG_7SERIES = 1) generate
u1 : ddr3ram
generic map (
width => 64,
abits => 14,
colbits => 10,
rowbits => 10,
implbanks => 1,
fname => ramfile,
lddelay => (0 ns),
ldguard => 1,
speedbin => 9, --DDR3-1600K
density => 3,
pagesize => 1,
changeendian => 8)
port map (
ck => ddr3_ck_p(0),
ckn => ddr3_ck_n(0),
cke => ddr3_cke(0),
csn => ddr3_cs_n(0),
odt => ddr3_odt(0),
rasn => ddr3_ras_n,
casn => ddr3_cas_n,
wen => ddr3_we_n,
dm => ddr3_dm,
ba => ddr3_ba,
a => ddr3_addr,
resetn => ddr3_reset_n,
dq => ddr3_dq,
dqs => ddr3_dqs_p,
dqsn => ddr3_dqs_n,
doload => led(3)
);
end generate ddr3mem;
end generate gen_mem_model;
mig_mem_model : if (USE_MIG_INTERFACE_MODEL = true) generate
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
end generate mig_mem_model;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
phy_mdio <= 'H';
phy_int <= '0';
p0: phy
generic map (
address => 7,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
rmii => 0,
rgmii => 1
)
port map(phy_reset, phy_mdio, phy_txclk, phy_rxclk, phy_rxd,
phy_rxctl_rxdv, phy_rxer, phy_col, phy_crs, phy_txd,
phy_txctl_txen, phy_txer, phy_mdc, phy_gtxclk);
end generate;
iuerr : process
begin
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
if (USE_MIG_INTERFACE_MODEL /= true) then
wait on led(3); -- DDR3 Memory Init ready
end if;
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ; -- this should be a failure
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
switch(3) <= '0';
wait for 2500 ns;
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
dsurst <= '1';
switch(3) <= '1';
if (USE_MIG_INTERFACE_MODEL /= true) then
wait on led(3); -- Wait for DDR3 Memory Init ready
end if;
report "Start DSU transfer";
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- Reads from memory and DSU register to mimic GRMON during simulation
l1 : loop
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU read memory " & tost(w32);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU Break and Single Step register" & tost(w32);
end loop l1;
wait;
-- ** This is only kept for reference --
-- do test read and writes to DDR3 to check status
-- Write
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#01#, 16#23#, 16#45#, 16#67#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
txa(dsutx, 16#89#, 16#AB#, 16#CD#, 16#EF#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
txa(dsutx, 16#08#, 16#19#, 16#2A#, 16#3B#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
txa(dsutx, 16#4C#, 16#5D#, 16#6E#, 16#7F#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
report "* Read " & tost(w32);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
rxi(dsurx, w32, txp, lresp);
wait;
-- Register 0x90000000 (DSU Control Register)
-- Data 0x0000202e (b0010 0000 0010 1110)
-- [0] - Trace Enable
-- [1] - Break On Error
-- [2] - Break on IU watchpoint
-- [3] - Break on s/w break points
--
-- [4] - (Break on trap)
-- [5] - Break on error traps
-- [6] - Debug mode (Read mode only)
-- [7] - DSUEN (read mode)
--
-- [8] - DSUBRE (read mode)
-- [9] - Processor mode error (clears error)
-- [10] - processor halt (returns 1 if processor halted)
-- [11] - power down mode (return 1 if processor in power down mode)
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#80#, 16#02#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
end;
begin
dsuctsn <= '0';
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
gpl-2.0
|
6ecc68bbeebf19167f62a274c2a4b59e
| 0.527583 | 3.341962 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/rotr00.vhd
| 1 | 1,399 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rotr00 is
port(
clkrotr: in std_logic ;
codoprotr: in std_logic_vector ( 3 downto 0 );
portArotr: in std_logic_vector ( 7 downto 0 );
inFlagrotr: in std_logic;
outrotr: out std_logic_vector ( 7 downto 0 );
outFlagrotr: out std_logic );
end;
architecture rotr0 of rotr00 is
begin
protr: process(codoprotr, portArotr)
begin
if(codoprotr = "1100") then
outrotr(7) <= portArotr(0);
outrotr(6 downto 0) <= portArotr(7 downto 1);
outFlagrotr <= '1';
else
outrotr <= (others => 'Z');
outFlagrotr <= 'Z';
end if;
end process protr;
-- pnand: process(clknd, codopnd, inFlagnd)
-- --variable auxnd: bit:='0';
-- begin
-- if (clknd = '1') then
----clknd'event and
-- if (codopnd = "0100") then
-- if (inFlagnd = '1') then
-- --if (auxnd = '0') then
-- --auxnd:= '1';
-- outnd <= portAnd nand portBnd;
-- outFlagnd <= '1';
-- --end if;
-- else
-- outFlagnd <= '0';
-- end if;
-- else
-- outnd <= (others => 'Z');
-- outFlagnd <= 'Z';
-- --auxnd:='0';
-- end if;
-- end if;
-- end process pnand;
end rotr0;
|
apache-2.0
|
c98fd244ddc3ad8487546bdf9490baf9
| 0.506791 | 3.067982 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/pcie/pcie.vhd
| 3 | 8,694 |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use IEEE.NUMERIC_bit.all;
package pcie is
type pci_ahb_dma_in_type is record
address : std_logic_vector(31 downto 0);
wdata : std_logic_vector(31 downto 0);
start : std_ulogic;
burst : std_ulogic;
write : std_ulogic;
busy : std_ulogic;
irq : std_ulogic;
size : std_logic_vector(1 downto 0);
end record;
type pci_ahb_dma_out_type is record
start : std_ulogic;
active : std_ulogic;
ready : std_ulogic;
retry : std_ulogic;
mexc : std_ulogic;
haddr : std_logic_vector(9 downto 0);
rdata : std_logic_vector(31 downto 0);
end record;
type data_vector_to_check is array (natural range <>) of std_logic_vector(31 downto 0);
component pciedma is
generic (
fabtech : integer := DEFFABTECH;
memtech : integer := DEFMEMTECH;
dmstndx : integer := 0;
dapbndx : integer := 0;
dapbaddr : integer := 0;
dapbmask : integer := 16#fff#;
dapbirq : integer := 0;
blength : integer := 16;
abits : integer := 21;
dmaabits : integer := 26;
fifodepth : integer := 5; -- FIFO depth
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
slvndx : integer := 0;
apbndx : integer := 0;
apbaddr : integer := 0;
apbmask : integer := 16#fff#;
haddr : integer := 16#A00#;
hmask : integer := 16#FFF#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
pcie_bar_mask : integer := 16#ffe#;
lane_width : integer := 1;
Gen : integer := 1 );
port(
rst : in std_logic;
clk : in std_logic;
sys_clk_p : in std_logic;--check needed
sys_clk_n : in std_logic;--
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic_vector(lane_width-1 downto 0);
pci_exp_txn : out std_logic_vector(lane_width-1 downto 0);
pci_exp_rxp : in std_logic_vector(lane_width-1 downto 0);
pci_exp_rxn : in std_logic_vector(lane_width-1 downto 0);
-- trn_clk : out std_logic;
dapbo : out apb_slv_out_type;
dahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component pcie_master_target_virtex is
generic (
fabtech : integer := DEFFABTECH;
hmstndx : integer := 0;
hslvndx : integer := 0;
abits : integer := 21;
device_id : integer := 9; -- PCIE device ID
vendor_id : integer := 16#10EE#; -- PCIE vendor ID
pcie_bar_mask : integer := 16#FFE#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
haddr : integer := 0;
hmask : integer := 16#fff#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
Master : integer := 1;
lane_width : integer := 1;
Gen : integer := 1
);
port(
rst : in std_logic;
clk : in std_logic;
-- System Interface
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic_vector(lane_width-1 downto 0);
pci_exp_txn : out std_logic_vector(lane_width-1 downto 0);
pci_exp_rxp : in std_logic_vector(lane_width-1 downto 0);
pci_exp_rxn : in std_logic_vector(lane_width-1 downto 0);
-- AMBA Interface
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end component;
component pcie_master_fifo_virtex is
generic (
fabtech: integer := DEFFABTECH;
memtech: integer := DEFMEMTECH;
dmamst: integer := NAHBMST;
fifodepth: integer := 5; -- FIFO depth
hslvndx: integer := 0;
abits: integer := 21;
device_id: integer := 9; -- PCIE device ID
vendor_id: integer := 16#10EE#; -- PCIE vendor ID
pcie_bar_mask: integer := 16#FFE#;
nsync: integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
haddr: integer := 16#A00#;
hmask: integer := 16#fff#;
pindex: integer := 0;
paddr: integer := 0;
pmask: integer := 16#fff#;
lane_width: integer := 1;
Gen: integer := 1
);
port(
rst : in std_logic;
clk : in std_logic;
-- System Interface
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic_vector(lane_width-1 downto 0);
pci_exp_txn : out std_logic_vector(lane_width-1 downto 0);
pci_exp_rxp : in std_logic_vector(lane_width-1 downto 0);
pci_exp_rxn : in std_logic_vector(lane_width-1 downto 0);
-- AMBA Interface
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
function buffer_available(fabtech : integer;trn_tbuf_av : std_logic_vector(5 downto 0))return std_logic;
function conv_to_bitvector(Gen : in integer;width : in integer)return bit_vector;
function fn_usr_clk_frequency(lane_width : in integer;Gen : in integer) return integer;
function fn_TARGET_LINK_SPEED(lane_width : in integer;Gen : in integer) return bit_vector;
end;
package body pcie is
function buffer_available(fabtech : integer;
trn_tbuf_av : std_logic_vector(5 downto 0))
return std_logic is
variable s: std_logic;
begin
if fabtech = virtex5 then
if trn_tbuf_av(3 downto 0) = "1111" then
s := '0';
else
s := '1';
end if;
elsif fabtech = virtex6 then
if trn_tbuf_av < "000010" then
s := '1';
else
s := '0';
end if;
else
s := '1';
end if;
return s;
end function;
function conv_to_bitvector(Gen : in integer;width : in integer)
return bit_vector is
variable result : bit_vector(width-1 downto 0);
begin
result:=bit_vector(to_unsigned(Gen,width));
return result;
end function;
function fn_usr_clk_frequency(lane_width : in integer;Gen : in integer)
return integer is
variable result : integer;
begin
result := 1;
case lane_width is
when 1 =>
result := 1;
when 2 =>
if Gen = 1 then
result := 1;
else
result := 2;
end if;
when 4 =>
if Gen = 1 then
result := 2;
else
result := 3;
end if;
when 8 =>
result := 3;
when others =>
end case;
return result;
end function;
function fn_TARGET_LINK_SPEED(lane_width : in integer;Gen : in integer)
return bit_vector is
variable result : bit_vector(3 downto 0);
begin
result := x"0";
case lane_width is
when 1 =>
if Gen = 1 then
result := x"0";
else
result := x"2";
end if;
when 2 =>
if Gen = 1 then
result := x"0";
else
result := x"2";
end if;
when 4 =>
if Gen = 1 then
result := x"0";
else
result := x"2";
end if;
when 8 =>
result := x"0";
when others =>
end case;
return result;
end function;
end;
|
gpl-2.0
|
3097a56fea8584f5137f2fb86e261c1b
| 0.507131 | 3.732933 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/uart/dcom_uart.vhd
| 1 | 11,463 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dcom_uart
-- File: dcom_uart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Asynchronous UART with baud-rate detection.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity dcom_uart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ui : in uart_in_type;
uo : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in dcom_uart_in_type;
uarto : out dcom_uart_out_type
);
end;
architecture rtl of dcom_uart is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBUART, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type rxfsmtype is (idle, startbit, data, stopbit);
type txfsmtype is (idle, data);
type uartregs is record
rxen : std_ulogic; -- receiver enabled
dready : std_ulogic; -- data ready
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
thempty : std_ulogic; -- transmitter hold register empty
break : std_ulogic; -- break detected
ovf : std_ulogic; -- receiver overflow
frame : std_ulogic; -- framing error
rhold : std_logic_vector(7 downto 0);
rshift : std_logic_vector(7 downto 0);
tshift : std_logic_vector(9 downto 0);
thold : std_logic_vector(7 downto 0);
txstate : txfsmtype;
txclk : std_logic_vector(2 downto 0); -- tx clock divider
txtick : std_ulogic; -- tx clock (internal)
rxstate : rxfsmtype;
rxclk : std_logic_vector(2 downto 0); -- rx clock divider
rxdb : std_logic_vector(1 downto 0); -- rx data filtering buffer
rxtick : std_ulogic; -- rx clock (internal)
tick : std_ulogic; -- rx clock (internal)
scaler : std_logic_vector(17 downto 0);
brate : std_logic_vector(17 downto 0);
tcnt : std_logic_vector(1 downto 0); -- autobaud counter
rxf : std_logic_vector(4 downto 0); -- rx data filtering buffer
fedge : std_ulogic; -- rx falling edge
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : uartregs := (
rxen => '0', dready => '0', rsempty => '1', tsempty => '1', thempty => '1',
break => '0', ovf => '0', frame => '0', rhold => (others => '0'),
rshift => (others => '0'), tshift => (others => '1'), thold => (others => '0'),
txstate => idle, txclk => (others => '0'), txtick => '0', rxstate => idle,
rxclk => (others => '0'), rxdb => (others => '0'), rxtick => '0', tick => '0',
scaler => "111111111111111011", brate => (others => '1'), tcnt => (others => '0'),
rxf => (others => '0'), fedge => '0');
signal r, rin : uartregs;
begin
uartop : process(rst, r, apbi, uarti, ui )
variable rdata : std_logic_vector(31 downto 0);
variable scaler : std_logic_vector(17 downto 0);
variable rxclk, txclk : std_logic_vector(2 downto 0);
variable irxd : std_ulogic;
variable v : uartregs;
begin
v := r;
v.txtick := '0'; v.rxtick := '0'; v.tick := '0'; rdata := (others => '0');
v.rxdb(1) := r.rxdb(0);
-- scaler
if r.tcnt = "11" then scaler := r.scaler - 1;
else scaler := r.scaler + 1; end if;
if r.tcnt /= "11" then
if (r.rxdb(1) and not r.rxdb(0)) = '1' then v.fedge := '1'; end if;
if (r.fedge) = '1' then
v.scaler := scaler;
if (v.scaler(17) and not r.scaler(16)) = '1' then
v.scaler := "111111111111111011";
v.fedge := '0'; v.tcnt := "00";
end if;
end if;
if (r.rxdb(1) and r.fedge and not r.rxdb(0)) = '1' then
if (r.brate(17 downto 4)> r.scaler(17 downto 4)) then
v.brate := r.scaler; v.tcnt := "00";
end if;
v.scaler := "111111111111111011";
if (r.brate(17 downto 4) = r.scaler(17 downto 4)) then
v.tcnt := r.tcnt + 1;
if r.tcnt = "10" then
v.brate := "0000" & r.scaler(17 downto 4);
v.scaler := v.brate; v.rxen := '1';
end if;
end if;
end if;
else
if (r.break and r.rxdb(1)) = '1' then
v.scaler := "111111111111111011";
v.brate := (others => '1'); v.tcnt := "00";
v.break := '0'; v.rxen := '0';
end if;
end if;
if r.rxen = '1' then
v.scaler := scaler;
v.tick := scaler(15) and not r.scaler(15);
if v.tick = '1' then v.scaler := r.brate; end if;
end if;
-- read/write registers
if uarti.read = '1' then v.dready := '0'; end if;
case apbi.paddr(3 downto 2) is
when "01" =>
rdata(9 downto 0) := r.tcnt & r.rxdb(0) & r.frame & '0' & r.ovf &
r.break & r.thempty & r.tsempty & r.dready;
when "10" =>
rdata(1 downto 0) := (r.tcnt(1) or r.tcnt(0)) & r.rxen;
when others =>
rdata(17 downto 0) := r.brate;
end case;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
v.frame := apbi.pwdata(6);
v.ovf := apbi.pwdata(4);
v.break := apbi.pwdata(3);
when "10" =>
v.tcnt := apbi.pwdata(1) & apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "11" =>
v.brate := apbi.pwdata(17 downto 0);
v.scaler := apbi.pwdata(17 downto 0);
when others =>
end case;
end if;
-- tx clock
txclk := r.txclk + 1;
if r.tick = '1' then
v.txclk := txclk; v.txtick := r.txclk(2) and not txclk(2);
end if;
-- rx clock
rxclk := r.rxclk + 1;
if r.tick = '1' then
v.rxclk := rxclk; v.rxtick := r.rxclk(2) and not rxclk(2);
end if;
-- filter rx data
v.rxf(1 downto 0) := r.rxf(0) & ui.rxd; -- meta-stability filter
if ((r.tcnt /= "11") and (r.scaler(0 downto 0) = "1")) or
((r.tcnt = "11") and (r.tick = '1'))
then v.rxf(4 downto 2) := r.rxf(3 downto 1); end if;
v.rxdb(0) := (r.rxf(4) and r.rxf(3)) or (r.rxf(4) and r.rxf(2)) or
(r.rxf(3) and r.rxf(2));
irxd := r.rxdb(0);
-- transmitter operation
case r.txstate is
when idle => -- idle and stop bit state
if (r.txtick = '1') then v.tsempty := '1'; end if;
if (r.rxen and (not r.thempty) and r.txtick) = '1' then
v.tshift := '0' & r.thold & '0'; v.txstate := data;
v.thempty := '1';
v.tsempty := '0'; v.txclk := "00" & r.tick; v.txtick := '0';
end if;
when data => -- transmit data frame
if r.txtick = '1' then
v.tshift := '1' & r.tshift(9 downto 1);
if r.tshift(9 downto 1) = "111111110" then
v.tshift(0) := '1'; v.txstate := idle;
end if;
end if;
end case;
-- writing of tx data register must be done after tx fsm to get correct
-- operation of thempty flag
if uarti.write = '1' then
v.thold := uarti.data(7 downto 0); v.thempty := '0';
end if;
-- receiver operation
case r.rxstate is
when idle => -- wait for start bit
if ((not r.rsempty) and not r.dready) = '1' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
if (r.rxen and r.rxdb(1) and (not irxd)) = '1' then
v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
if v.rsempty = '0' then v.ovf := '1'; end if;
v.rsempty := '0'; v.rxtick := '0';
end if;
when startbit => -- check validity of start bit
if r.rxtick = '1' then
if irxd = '0' then
v.rshift := irxd & r.rshift(7 downto 1); v.rxstate := data;
else
v.rxstate := idle;
end if;
end if;
when data => -- receive data frame
if r.rxtick = '1' then
v.rshift := irxd & r.rshift(7 downto 1);
if r.rshift(0) = '0' then
v.rxstate := stopbit;
end if;
end if;
when stopbit => -- receive stop bit
if r.rxtick = '1' then
if irxd = '1' then
v.rsempty := '0';
if v.dready = '0' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
else
if r.rshift = "00000000" then
v.break := '1'; -- break
else
v.frame := '1'; -- framing error
end if;
v.rsempty := '1';
end if;
v.rxstate := idle;
end if;
when others =>
v.rxstate := idle;
end case;
-- reset operation
if not RESET_ALL and rst = '0' then
v.frame := RES.frame; v.rsempty := RES.rsempty;
v.ovf := RES.ovf; v.break := RES.break; v.thempty := RES.thempty;
v.tsempty := RES.tsempty; v.dready := RES.dready; v.fedge := RES.fedge;
v.txstate := RES.txstate; v.rxstate := RES.rxstate; v.tshift(0) := RES.tshift(0);
v.scaler := RES.scaler; v.brate := RES.brate;
v.rxen := RES.rxen; v.tcnt := RES.tcnt;
v.txclk := RES.txclk; v.rxclk := RES.rxclk;
end if;
-- update registers
rin <= v;
-- drive outputs
uo.txd <= r.tshift(0);
uo.scaler(31 downto 18) <= (others => '0');
uo.scaler(17 downto 0) <= r.brate;
uo.rtsn <= '0';
uo.rxen <= andv(r.tcnt);
uarto.dready <= r.dready;
uarto.tsempty <= r.tsempty;
uarto.thempty <= r.thempty;
uarto.lock <= r.tcnt(1) and r.tcnt(0);
uarto.enable <= r.rxen;
uarto.data <= r.rhold;
uo.txen <= '1'; uo.flow <= '0';
apbo.prdata <= rdata;
end process;
apbo.pirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
-- Sync. registers not reset
r.rxf <= rin.rxf;
end if;
end if;
end process;
end;
|
gpl-2.0
|
7f5fc38f2f6c8e7f531595d9561ed319
| 0.539039 | 3.294912 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-avnet-eval-xc4vlx60/ahb2mig_avnet_eval.vhd
| 1 | 18,915 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2mig
-- File: ahb2mig.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: AHB wrapper for Xilinx Virtex5 DDR2/3 MIG
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package avnet_eval is
constant APPDATA_WIDTH : integer := 32; -- # of usr read/write data bus bits.
constant ADDR_WIDTH : integer := 36; -- # of memory row and # of addr bits.
constant MIGHMASK : integer := 16#FE0#; -- AHB mask for 256 Mbyte memory
-- constant MIGHMASK : integer := 16#E00#; -- AHB mask for 512 Mbyte memory
-- constant MIGHMASK : integer := 16#C00#; -- AHB mask for 1024 Mbyte memory
type mig_app_in_type is record
app_wdf_wren : std_logic;
app_wdf_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
app_wdf_mask : std_logic_vector(APPDATA_WIDTH/8-1 downto 0);
app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
app_en : std_logic;
mig_rst : std_logic;
end record;
type mig_app_out_type is record
app_af_afull : std_logic;
app_wdf_afull : std_logic;
app_rd_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
app_rd_data_valid : std_logic;
end record;
end package;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use work.avnet_eval.all;
entity ahb2mig_avnet_eval is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#e00#;
MHz : integer := 100;
Mbyte : integer := 512;
nosync : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
rst_50 : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clk_50 : in std_ulogic;
init_done : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
migi : out mig_app_in_type;
migo : in mig_app_out_type
);
end;
architecture rtl of ahb2mig_avnet_eval is
constant REVISION : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type ddr_state_type is (midle, rhold1, rhold2, rhold3, rhold4, rhold5, rhold6, rhold7, dread,
whold1, whold2, whold3, whold4, whold5, whold6, whold7);
constant abuf : integer := 6;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
end record;
-- local registers
type mem is array(0 to 7) of std_logic_vector(31 downto 0);
type wrm is array(0 to 7) of std_logic_vector(3 downto 0);
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
startsd : std_ulogic;
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(127 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(2 downto 0);
acc : access_param;
sync : std_ulogic;
hwdata : mem;
write : wrm;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
hrdata : std_logic_vector(255 downto 0);
sync : std_ulogic;
dstate : ddr_state_type;
addr : std_logic_vector(2 downto 0);
end record;
signal vcc, clk_ahb1, clk_ahb2 : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal hwdata, hwdatab : std_logic_vector(127 downto 0);
signal rdel : std_logic_vector(25 downto 0);
begin
vcc <= '1';
ahb_ctrl : process(rst_ahb, ahbsi, r, ra, migo, hwdata)
variable va : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable ready : std_logic;
variable tmp : std_logic_vector(3 downto 0);
variable waddr : integer;
variable rdata : std_logic_vector(127 downto 0);
begin
va := ra; va.hresp := HRESP_OKAY;
tmp := (others => '0');
case ra.raddr(2 downto 2) is
when "0" => rdata := r.hrdata(127 downto 0);
when others => rdata := r.hrdata(255 downto 128);
end case;
if AHBDW > 64 and ra.size = HSIZE_4WORD then
va.hrdata := rdata(127 downto 0);
elsif AHBDW > 32 and ra.size = HSIZE_DWORD then
if ra.raddr(1) = '1' then va.hrdata(63 downto 0) := rdata(127 downto 64);
else va.hrdata(63 downto 0) := rdata(63 downto 0); end if;
va.hrdata(127 downto 64) := va.hrdata(63 downto 0);
else
case ra.raddr(1 downto 0) is
when "00" => va.hrdata(31 downto 0) := rdata(31 downto 0);
when "01" => va.hrdata(31 downto 0) := rdata(63 downto 32);
when "10" => va.hrdata(31 downto 0) := rdata(95 downto 64);
when others => va.hrdata(31 downto 0) := rdata(127 downto 96);
end case;
va.hrdata(127 downto 32) := va.hrdata(31 downto 0) &
va.hrdata(31 downto 0) &
va.hrdata(31 downto 0);
end if;
if nosync = 0 then
va.sync := r.startsd;
if ra.startsd = ra.sync then ready := '1';
else ready := '0'; end if;
else
if ra.startsd = r.startsd then ready := '1';
else ready := '0'; end if;
end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.htrans := ahbsi.htrans; va.haddr := ahbsi.haddr;
va.size := ahbsi.hsize(2 downto 0); va.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
va.hsel := '1'; va.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then va.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
va.write := (others => "0000");
if ((va.hsel and va.htrans(1)) = '1') then
if va.hwrite = '0' then
va.state := rhold; va.startsd := not ra.startsd;
else
va.state := dwrite; va.hready := '1';
end if;
end if;
va.raddr := ra.haddr(7 downto 2);
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.acc := (va.haddr, va.size, va.hwrite);
end if;
when rhold =>
va.raddr := ra.haddr(7 downto 2);
if ready = '1' then
va.state := dread; va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
end if;
when dread =>
va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
if ((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.raddr(2 downto 0) = "000") then
va.state := midle; va.hready := '0';
end if;
va.acc := (va.haddr, va.size, va.hwrite);
when dwrite =>
va.raddr := ra.haddr(7 downto 2); va.hready := '1';
if (((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.haddr(4 downto 2) = "111")
or (AHBDW > 32 and ra.haddr(5 downto 2) = "1110" and andv(ra.size(1 downto 0)) = '1')
or (AHBDW > 64 and ra.haddr(5 downto 2) = "1100" and ra.size(2) = '1')) then
va.startsd := not ra.startsd; va.state := whold1;
va.hready := '0';
end if;
tmp := decode(ra.haddr(1 downto 0));
waddr := conv_integer(ra.haddr(4 downto 2));
va.hwdata(waddr) := hwdata(31 downto 0);
case ra.size is
when "000" => va.write(waddr) := tmp(0) & tmp(1) & tmp(2) & tmp(3);
when "001" => va.write(waddr) := tmp(0) & tmp(0) & tmp(2) & tmp(2);
when "010" => va.write(waddr) := "1111";
when "011" => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
when others => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.write(waddr+2) := "1111"; va.write(waddr+3) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
va.hwdata(waddr+2) := hwdata((95 mod AHBDW) downto (64 mod AHBDW));
va.hwdata(waddr+3) := hwdata((127 mod AHBDW) downto (96 mod AHBDW));
end case;
when whold1 =>
va.state := whold2;
when whold2 =>
if ready = '1' then
va.state := midle; va.acc := (va.haddr, va.size, va.hwrite);
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then va.hready := '1'; end if;
end if;
if rst_ahb = '0' then
va.hsel := '0';
va.hready := '1';
va.state := midle;
va.startsd := '0';
va.acc.hwrite := '0';
va.acc.haddr := (others => '0');
end if;
rai <= va;
end process;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= ahbdrivedata(ra.hrdata);
-- delayed reset for the MIG, will not work otherwise ...
rstp : process(clk_50)
begin
if rising_edge(clk_50) then
if rdel(25) = '0' then rdel <= rdel + 1; end if;
if rst_50 = '0' then
rdel <= (others => '0');
-- pragma translate_off
rdel <= (25 => '0', 2 => '0', others => '1');
-- pragma translate_on
end if;
end if;
end process;
ddr_ctrl : process(rst_ddr, r, ra, migo, init_done, rdel)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable app_en : std_ulogic;
variable app_cmd : std_logic_vector(2 downto 0);
variable app_wdf_mask : std_logic_vector(APPDATA_WIDTH/8-1 downto 0);
variable app_wdf_wren : std_ulogic;
variable app_wdf_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
variable app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
begin
-- Variable default settings to avoid latches
v := r; app_en := '0'; app_cmd := "100"; app_wdf_wren := '0';
app_wdf_mask := (others => '0');
app_wdf_mask := ra.write(0);
app_wdf_data := (others => '0');
app_wdf_data(31 downto 0) := ra.hwdata(0);
if ra.acc.hwrite = '0' then app_cmd(0) := '1'; else app_cmd(0) := '0'; end if;
app_addr := '0' & app_cmd & "00000" & ra.acc.haddr(27 downto 5) & r.addr(0) & "000";
v.sync := ra.startsd;
if nosync = 0 then
if r.startsd /= r.sync then startsd := '1';
else startsd := '0'; end if;
else
if ra.startsd /= r.startsd then startsd := '1';
else startsd := '0'; end if;
end if;
case r.dstate is
when midle =>
v.addr := "00" & ra.acc.haddr(4); app_addr(3) := ra.acc.haddr(4);
if (startsd = '1') and (migo.app_af_afull = '0') and (init_done = '1') then
if ra.acc.hwrite = '0' then
if ra.acc.haddr(4) = '0' then
v.dstate := dread; v.addr := r.addr + 1;
else v.dstate := rhold4; end if;
app_en := '1';
elsif migo.app_wdf_afull = '0' then
if ra.acc.haddr(4) = '0' then
v.dstate := whold1; v.addr := r.addr + 1;
else
v.dstate := whold5;
app_wdf_mask(3 downto 0) := ra.write(4);
app_wdf_data(31 downto 0) := ra.hwdata(4);
end if;
app_en := '1'; app_wdf_wren := '1';
end if;
end if;
when dread =>
if r.addr(0) = '1' then
v.addr := r.addr + 1; app_en := '1';
end if;
if migo.app_rd_data_valid = '1' then
v.hrdata(31 downto 0) := migo.app_rd_data(31 downto 0);
v.dstate := rhold1;
end if;
when rhold1 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(63 downto 32) := migo.app_rd_data(31 downto 0);
v.dstate := rhold2;
end if;
when rhold2 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(95 downto 64) := migo.app_rd_data(31 downto 0);
v.dstate := rhold3;
end if;
when rhold3 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(127 downto 96) := migo.app_rd_data(31 downto 0);
v.dstate := rhold4;
end if;
when rhold4 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(159 downto 128) := migo.app_rd_data(31 downto 0);
v.dstate := rhold5;
end if;
when rhold5 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(191 downto 160) := migo.app_rd_data(31 downto 0);
v.dstate := rhold6;
end if;
when rhold6 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(223 downto 192) := migo.app_rd_data(31 downto 0);
v.dstate := rhold7;
end if;
when rhold7 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(255 downto 224) := migo.app_rd_data(31 downto 0);
v.dstate := midle;
v.startsd := not r.startsd;
end if;
when whold1 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(1);
app_wdf_data(31 downto 0) := ra.hwdata(1);
v.dstate := whold2;
when whold2 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(2);
app_wdf_data(31 downto 0) := ra.hwdata(2);
v.dstate := whold3;
when whold3 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(3);
app_wdf_data(31 downto 0) := ra.hwdata(3);
if (ra.write(4) = "0000") and (ra.write(5) = "0000") and (ra.write(6) = "0000") and
(ra.write(7) = "0000")
then v.startsd := not r.startsd; v.dstate := midle;
elsif migo.app_wdf_afull = '0' then v.dstate := whold4; app_en := '1'; end if;
when whold4 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(4);
app_wdf_data(31 downto 0) := ra.hwdata(4);
v.dstate := whold5;
when whold5 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(5);
app_wdf_data(31 downto 0) := ra.hwdata(5);
v.dstate := whold6;
when whold6 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(6);
app_wdf_data(31 downto 0) := ra.hwdata(6);
v.dstate := whold7;
when whold7 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(7);
app_wdf_data(31 downto 0) := ra.hwdata(7);
v.startsd := not r.startsd;
v.dstate := midle;
when others =>
end case;
-- reset
if rst_ddr = '0' then
v.startsd := '0';
app_en := '0';
v.dstate := midle;
v.addr := "000";
end if;
ri <= v;
migi.app_addr <= app_addr;
migi.app_en <= app_en;
migi.app_wdf_wren <= app_wdf_wren;
migi.app_wdf_mask <= not app_wdf_mask;
migi.app_wdf_data <= app_wdf_data;
migi.mig_rst <= rdel(25);
end process;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
clk_ahb1 <= clk_ahb; clk_ahb2 <= clk_ahb1; -- sync clock deltas
ahbregs : process(clk_ahb2) begin
if rising_edge(clk_ahb2) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr) begin
if rising_edge(clk_ddr) then
r <= ri;
end if;
end process;
-- Write data selection.
AHB32: if AHBDW = 32 generate
hwdata <= ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0) &
ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0);
end generate AHB32;
AHB64: if AHBDW = 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(63 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab(63 downto 0) <= ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(1 downto 0) = "11") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(31 downto 0) & hwdatab(63 downto 32);
end generate AHB64;
AHBWIDE: if AHBDW > 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(127 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab <= ahbread4word(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(2) = '1') else
(ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2))) when (ra.size = "011") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(95 downto 64) & hwdatab(127 downto 96);
end generate AHBWIDE;
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ahb2mig" & tost(hindex) & ": 32-bit DDR controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
|
gpl-2.0
|
3c622e96dc306237fefdf9034b9f84a2
| 0.57309 | 3.179526 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/adder8bita00.vhd
| 1 | 2,800 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use package8bita00.all;
entity adder8bita00 is
port(
Ai: in std_logic_vector ( 7 downto 0 );
Bi: in std_logic_vector ( 7 downto 0 );
SL: in std_logic ;
LED: out std_logic ;
So: out std_logic_vector ( 7 downto 0 ) );
end;
architecture adder8bita0 of adder8bita00 is
signal SB0, SB1, SB2, SB3, SB4, SB5, SB6, SB7: std_logic;
signal CS1, CS2, CS3, CS4, CS5, CS6, CS7, CS8: std_logic;
signal SA0, SA1, SA2, SA3, SA4, SA5, SA6, SA7: std_logic;
signal Bx0, Bx1, Bx2, Bx3, Bx4, Bx5, Bx6, Bx7: std_logic;
signal enablea: std_logic;
begin
A00: xora00 port map(Ax => SL, Bx => Bi(0), Yx => SB0);
A01: xora00 port map(Ax => SL, Bx => Bi(1), Yx => SB1);
A02: xora00 port map(Ax => SL, Bx => Bi(2), Yx => SB2);
A03: xora00 port map(Ax => SL, Bx => Bi(3), Yx => SB3);
A04: xora00 port map(Ax => SL, Bx => Bi(4), Yx => SB4);
A05: xora00 port map(Ax => SL, Bx => Bi(5), Yx => SB5);
A06: xora00 port map(Ax => SL, Bx => Bi(6), Yx => SB6);
A07: xora00 port map(Ax => SL, Bx => Bi(7), Yx => SB7);
A08: topfaa00 port map(A00 => Ai(0), B00 => SB0, C00 => SL, C01 => CS1, S00 => SA0);
A09: topfaa00 port map(A00 => Ai(1), B00 => SB1, C00 => CS1, C01 => CS2, S00 => SA1);
A10: topfaa00 port map(A00 => Ai(2), B00 => SB2, C00 => CS2, C01 => CS3, S00 => SA2);
A11: topfaa00 port map(A00 => Ai(3), B00 => SB3, C00 => CS3, C01 => CS4, S00 => SA3);
A12: topfaa00 port map(A00 => Ai(4), B00 => SB4, C00 => CS4, C01 => CS5, S00 => SA4);
A13: topfaa00 port map(A00 => Ai(5), B00 => SB5, C00 => CS5, C01 => CS6, S00 => SA5);
A14: topfaa00 port map(A00 => Ai(6), B00 => SB6, C00 => CS6, C01 => CS7, S00 => SA6);
A15: topfaa00 port map(A00 => Ai(7), B00 => SB7, C00 => CS7, C01 => CS8, S00 => SA7);
A16: xora00 port map(Bx => CS8, AX => CS7, Yx => LED);
A17: xnora00 port map(Bnx => CS8, Anx => CS7, Ynx => enablea);
A18: anda00 port map(Ba => SA0, Aa => enablea, Ya => So(0));
A19: anda00 port map(Ba => SA1, Aa => enablea, Ya => So(1));
A20: anda00 port map(Ba => SA2, Aa => enablea, Ya => So(2));
A21: anda00 port map(Ba => SA3, Aa => enablea, Ya => So(3));
A22: anda00 port map(Ba => SA4, Aa => enablea, Ya => So(4));
A23: anda00 port map(Ba => SA5, Aa => enablea, Ya => So(5));
A24: anda00 port map(Ba => SA6, Aa => enablea, Ya => So(6));
A25: anda00 port map(Ba => SA7, Aa => enablea, Ya => So(7));
end adder8bita0;
|
apache-2.0
|
f3c805250b3db1b7701e66e47d9392a3
| 0.513571 | 2.68714 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ac701/testbench.vhd
| 1 | 18,894 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := true;
USE_MIG_INTERFACE_MODEL : boolean := false
);
end;
architecture behav of testbench is
-- DDR3 Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
constant promfile : string := "prom.srec"; -- rom contents
constant ramfile : string := "ram.srec"; -- ram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0';
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal txd1 , rxd1 , dsurx : std_logic;
signal txd2 , rxd2 , dsutx : std_logic;
signal ctsn1 , rtsn1 , dsuctsn : std_ulogic;
signal ctsn2 , rtsn2 , dsurtsn : std_ulogic;
signal phy_gtxclk : std_logic := '0';
signal phy_txer : std_ulogic;
signal phy_txd : std_logic_vector(7 downto 0);
signal phy_txctl_txen : std_ulogic;
signal phy_txclk : std_ulogic;
signal phy_rxer : std_ulogic;
signal phy_rxd : std_logic_vector(7 downto 0);
signal phy_rxctl_rxdv : std_ulogic;
signal phy_rxclk : std_ulogic;
signal phy_reset : std_ulogic;
signal phy_mdio : std_logic;
signal phy_mdc : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_col : std_ulogic;
signal phy_int : std_ulogic;
signal phy_rxdl : std_logic_vector(7 downto 0);
signal phy_txdl : std_logic_vector(7 downto 0);
signal clk27 : std_ulogic := '0';
signal clk200p : std_ulogic := '0';
signal clk200n : std_ulogic := '1';
signal clk33 : std_ulogic := '0';
signal clkethp : std_ulogic := '0';
signal clkethn : std_ulogic := '1';
signal txp1 : std_logic;
signal txn : std_logic;
signal rxp : std_logic := '1';
signal rxn : std_logic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR3 memory
signal ddr3_dq : std_logic_vector(63 downto 0);
signal ddr3_dqs_p : std_logic_vector(7 downto 0);
signal ddr3_dqs_n : std_logic_vector(7 downto 0);
signal ddr3_addr : std_logic_vector(13 downto 0);
signal ddr3_ba : std_logic_vector(2 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_ck_p : std_logic_vector(0 downto 0);
signal ddr3_ck_n : std_logic_vector(0 downto 0);
signal ddr3_cke : std_logic_vector(0 downto 0);
signal ddr3_cs_n : std_logic_vector(0 downto 0);
signal ddr3_dm : std_logic_vector(7 downto 0);
signal ddr3_odt : std_logic_vector(0 downto 0);
-- SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_logic;
signal spi_miso : std_logic := '0';
signal spi_mosi : std_logic;
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(3 downto 0); -- I/O port
signal button : std_logic_vector(3 downto 0); -- I/O port
signal led : std_logic_vector(3 downto 0); -- I/O port
constant lresp : boolean := false;
signal tdqs_n : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_rx_clk : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
reset : in std_ulogic;
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
dsurx : in std_ulogic;
dsutx : out std_ulogic;
dsuctsn : in std_ulogic;
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(3 downto 0);
led : out std_logic_vector(3 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
phy_txclk : out std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txctl_txen : out std_ulogic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxctl_rxdv : in std_ulogic;
phy_rxclk : in std_ulogic;
phy_reset : out std_ulogic;
phy_mdio : inout std_logic;
phy_mdc : out std_ulogic;
sfp_clock_mux : out std_logic_vector(1 downto 0);
sdcard_spi_miso : in std_logic;
sdcard_spi_mosi : out std_logic;
sdcard_spi_cs_b : out std_logic;
sdcard_spi_clk : out std_logic
);
end component;
begin
-- clock and reset
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
clkethp <= not clkethp after 4 ns;
clkethn <= not clkethp after 4 ns;
rst <= not dsurst;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
button <= "0000";
switch(2 downto 0) <= "000";
cpu : leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow,
testahb => testahb,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION,
USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL
)
port map (
reset => rst,
clk200p => clk200p,
clk200n => clk200n,
spi_sel_n => spi_sel_n,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_mosi => spi_mosi,
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
dsurx => dsurx,
dsutx => dsutx,
dsuctsn => dsuctsn,
dsurtsn => dsurtsn,
button => button,
switch => switch,
led => led,
iic_scl => iic_scl,
iic_sda => iic_sda,
gtrefclk_p => clkethp,
gtrefclk_n => clkethn,
phy_txclk => phy_gtxclk,
phy_txd => phy_txd(3 downto 0),
phy_txctl_txen => phy_txctl_txen,
phy_rxd => phy_rxd(3 downto 0)'delayed(0 ns),
phy_rxctl_rxdv => phy_rxctl_rxdv'delayed(0 ns),
phy_rxclk => phy_rxclk'delayed(0 ns),
phy_reset => phy_reset,
phy_mdio => phy_mdio,
phy_mdc => phy_mdc,
sfp_clock_mux => OPEN ,
sdcard_spi_miso => '1',
sdcard_spi_mosi => OPEN ,
sdcard_spi_cs_b => OPEN ,
sdcard_spi_clk => OPEN
);
-- SPI memory model
spi_gen_model : if (CFG_SPIMCTRL = 1) generate
spi0 : spi_flash
generic map (
ftype => 3,
debug => 0,
readcmd => 16#0B#,
dummybyte => 0,
dualoutput => 0)
port map (
sck => spi_clk,
di => spi_mosi,
do => spi_miso,
csn => spi_sel_n,
sd_cmd_timeout => '0',
sd_data_timeout => '0');
end generate;
-- Memory Models instantiations
gen_mem_model : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddr3mem : if (CFG_MIG_7SERIES = 1) generate
u1 : ddr3ram
generic map (
width => 64,
abits => 14,
colbits => 10,
rowbits => 10,
implbanks => 1,
fname => ramfile,
lddelay => (0 ns),
ldguard => 1,
speedbin => 9, --DDR3-1600K
density => 3,
pagesize => 1,
changeendian => 8)
port map (
ck => ddr3_ck_p(0),
ckn => ddr3_ck_n(0),
cke => ddr3_cke(0),
csn => ddr3_cs_n(0),
odt => ddr3_odt(0),
rasn => ddr3_ras_n,
casn => ddr3_cas_n,
wen => ddr3_we_n,
dm => ddr3_dm,
ba => ddr3_ba,
a => ddr3_addr,
resetn => ddr3_reset_n,
dq => ddr3_dq,
dqs => ddr3_dqs_p,
dqsn => ddr3_dqs_n,
doload => led(3)
);
end generate ddr3mem;
end generate gen_mem_model;
mig_mem_model : if (USE_MIG_INTERFACE_MODEL = true) generate
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
end generate mig_mem_model;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
phy_mdio <= 'H';
phy_int <= '0';
p0: phy
generic map (
address => 7,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
rmii => 0,
rgmii => 1
)
port map(phy_reset, phy_mdio, phy_txclk, phy_rxclk, phy_rxd,
phy_rxctl_rxdv, phy_rxer, phy_col, phy_crs, phy_txd,
phy_txctl_txen, phy_txer, phy_mdc, phy_gtxclk);
end generate;
iuerr : process
begin
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
if (USE_MIG_INTERFACE_MODEL /= true) then
wait on led(3); -- DDR3 Memory Init ready
end if;
wait for 5000 ns;
wait for 100 us;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ; -- this should be a failure
end process;
--data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
switch(3) <= '0';
wait for 2500 ns;
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
dsurst <= '1';
switch(3) <= '1';
if (USE_MIG_INTERFACE_MODEL /= true) then
wait on led(3); -- Wait for DDR3 Memory Init ready
end if;
report "Start DSU transfer";
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- Reads from memory and DSU register to mimic GRMON during simulation
l1 : loop
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU read memory " & tost(w32);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU Break and Single Step register" & tost(w32);
end loop l1;
wait;
-- ** This is only kept for reference --
-- do test read and writes to DDR3 to check status
-- Write
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#01#, 16#23#, 16#45#, 16#67#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
txa(dsutx, 16#89#, 16#AB#, 16#CD#, 16#EF#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
txa(dsutx, 16#08#, 16#19#, 16#2A#, 16#3B#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
txa(dsutx, 16#4C#, 16#5D#, 16#6E#, 16#7F#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
report "* Read " & tost(w32);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
rxi(dsurx, w32, txp, lresp);
wait;
-- Register 0x90000000 (DSU Control Register)
-- Data 0x0000202e (b0010 0000 0010 1110)
-- [0] - Trace Enable
-- [1] - Break On Error
-- [2] - Break on IU watchpoint
-- [3] - Break on s/w break points
--
-- [4] - (Break on trap)
-- [5] - Break on error traps
-- [6] - Debug mode (Read mode only)
-- [7] - DSUEN (read mode)
--
-- [8] - DSUBRE (read mode)
-- [9] - Processor mode error (clears error)
-- [10] - processor halt (returns 1 if processor halted)
-- [11] - power down mode (return 1 if processor in power down mode)
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#80#, 16#02#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
end;
begin
dsuctsn <= '0';
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
gpl-2.0
|
850817c07a506b91a72c7b549e476179
| 0.52731 | 3.314155 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-gr-cpci-xc4v/testbench.vhd
| 1 | 15,934 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic := '1';
pci_int : inout std_logic_vector(3 downto 0);
pci_66 : in std_logic := '0'
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_logic;
signal oen : std_logic;
signal read : std_logic;
signal writen : std_logic;
signal brdyn : std_logic;
signal bexcn : std_logic;
signal wdogn : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal test : std_logic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
signal clk2 : std_logic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic;
signal gtx_clk : std_logic := '0';
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
signal led_cfg: std_logic_vector(2 downto 0);
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_rxd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_stb : std_logic;
signal spw_clk : std_logic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
spw_clk <= not spw_clk after 10 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
led_cfg<="000"; --put the phy in base10h mode
can_rxd <= (others => 'H'); bexcn <= '1'; wdogn <= 'H';
gpio(2 downto 0) <= "LHL";
gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H');
pci_arb_req <= "HHHH";
-- spacewire loop-back
spw_rxdp <= spw_txdp; spw_rxdn <= spw_txdn;
spw_rxsp <= spw_txsp; spw_rxsn <= spw_txsn;
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (rst, clk, sdclk, error, wdogn, address(27 downto 0), data,
sa, sd, sdclk, sdcke, sdcsn, sdwen,
sdrasn, sdcasn, sddqm, dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1,
txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, brdyn, bexcn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_int, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd,
spw_clk, spw_rxdp, spw_rxdn, spw_rxsp, spw_rxsn, spw_txdp,
spw_txdn, spw_txsp, spw_txsn
);
-- optional sdram
sd0 : if (CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
sd1 : if ((CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1)) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
sd64 : if (CFG_MCTRL_SD64 = 1) generate
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
rwen(0), ramoen(0));
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
-- data <= buskeep(data), (others => 'H') after 250 ns;
data <= buskeep(data) after 5 ns;
-- sd <= buskeep(sd), (others => 'H') after 250 ns;
sd <= buskeep(sd) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
gpl-2.0
|
650c2fe8885afc73b977a61c42e31558
| 0.573365 | 3.050153 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/shiftl00.vhd
| 1 | 1,394 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shiftl00 is
port(
clkcshl: in std_logic ;
codopcshl: in std_logic_vector ( 3 downto 0 );
portAcshl: in std_logic_vector ( 7 downto 0 );
inFlagcshl: in std_logic;
outcshl: out std_logic_vector ( 7 downto 0 );
outFlagcshl: out std_logic );
end;
architecture shiftl0 of shiftl00 is
begin
pshl: process(codopcshl, portAcshl)
begin
if(codopcshl = "1011") then
outcshl(0) <= '0';
outcshl(7 downto 1) <= portAcshl(6 downto 0);
outFlagcshl <= '1';
else
outcshl <= (others => 'Z');
outFlagcshl <= 'Z';
end if;
end process pshl;
-- pnand: process(clknd, codopnd, inFlagnd)
-- --variable auxnd: bit:='0';
-- begin
-- if (clknd = '1') then
----clknd'event and
-- if (codopnd = "0100") then
-- if (inFlagnd = '1') then
-- --if (auxnd = '0') then
-- --auxnd:= '1';
-- outnd <= portAnd nand portBnd;
-- outFlagnd <= '1';
-- --end if;
-- else
-- outFlagnd <= '0';
-- end if;
-- else
-- outnd <= (others => 'Z');
-- outFlagnd <= 'Z';
-- --auxnd:='0';
-- end if;
-- end if;
-- end process pnand;
end shiftl0;
|
apache-2.0
|
1250ebc11017c10e676000579cd3a843
| 0.506456 | 3.077263 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/spi/spictrl.in.vhd
| 4 | 806 |
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE;
constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM;
constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS;
constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO;
constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG;
constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE;
constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM;
constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL;
constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN;
constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN;
constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM;
constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT;
|
gpl-2.0
|
e301be5202bbdc27fcad607113bdba84
| 0.718362 | 3.912621 | false | true | false | false |
aortiz49/MIPS-Processor
|
Hardware/alu_mux.vhd
| 1 | 1,002 |
library ieee;
use ieee.std_logic_1164.all;
use work.MIPS_lib.all;
entity alu_mux is
port(
control : in std_logic_vector(3 downto 0);
sum_in : in std_logic;
sub_in : in std_logic;
and_in : in std_logic;
or_in : in std_logic;
nor_in : in std_logic;
slt_in : in std_logic;
sltu_in : in std_logic;
mux_out : out std_logic
);
end alu_mux;
architecture arch of alu_mux is
begin
process(control,sum_in,sub_in,and_in,or_in,nor_in,slt_in,sltu_in)
begin
case control is
when F_SUM =>
mux_out <= sum_in;
when F_SUB =>
mux_out <= sub_in; -- Same as sum, but this control signal enables add_sub and carry
when F_AND =>
mux_out <= and_in;
when F_OR =>
mux_out <= or_in;
when F_NOR =>
mux_out <= nor_in;
when F_SLT =>
mux_out <= slt_in;
when F_SLTU =>
mux_out <= sltu_in;
when others =>
mux_out <= '0'; -- removes inferred latch warnings
end case;
end process;
end arch;
|
mit
|
53742e1c005a2b3a436cd65ca85b211e
| 0.578842 | 2.414458 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/sim/ddrram.vhd
| 1 | 20,419 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrram
-- File: ddrram.vhd
-- Author: Magnus Hjorth, Aeroflex Gaisler
-- Description: Generic simulation model of DDR SDRAM (JESD79E)
------------------------------------------------------------------------------
--pragma translate_off
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdio.hread;
use grlib.stdlib.all;
entity ddrram is
generic (
width: integer := 32;
abits: integer range 12 to 14 := 12;
colbits: integer range 8 to 13 := 8;
rowbits: integer range 1 to 14 := 12;
implbanks: integer range 1 to 4 := 1;
fname: string;
lddelay: time := (0 ns);
speedbin: integer range 0 to 5 := 0; -- 0:DDR200,1:266,2:333,3:400C,4:400B,5:400A
density: integer range 0 to 3 := 0; -- 0:128Mbit 1:256Mbit 2:512Mbit 3:1Gbit / chip
igndqs: integer range 0 to 1 := 0
);
port (
ck: in std_ulogic;
cke: in std_ulogic;
csn: in std_ulogic;
rasn: in std_ulogic;
casn: in std_ulogic;
wen: in std_ulogic;
dm: in std_logic_vector(width/8-1 downto 0);
ba: in std_logic_vector(1 downto 0);
a: in std_logic_vector(abits-1 downto 0);
dq: inout std_logic_vector(width-1 downto 0);
dqs: inout std_logic_vector(width/8-1 downto 0)
);
end;
architecture sim of ddrram is
type moderegs is record
-- Mode register (0)
opmode: std_logic_vector(6 downto 0);
caslat: std_logic_vector(2 downto 0);
bt: std_ulogic;
blen: std_logic_vector(2 downto 0);
-- Extended mode register (1)
opmode1: std_logic_vector(10 downto 0);
res1: std_ulogic;
ds: std_ulogic;
dlldis: std_ulogic;
end record;
-- Mode registers as signal, useful for debugging
signal mr: moderegs;
-- Handshaking between command and DQ/DQS processes
signal read_en, write_en: boolean := false;
signal hcmode: boolean := false; -- Shift DQS/read data one cycle for CL=1.5/2.5
signal hcread_en: boolean := false; -- One cycle earlier for half-cycle mode read preamble gen
signal read_data, write_data: std_logic_vector(2*width-1 downto 0);
signal write_mask: std_logic_vector(width/4-1 downto 0);
signal initdone: boolean := false;
-- Small delta-t to adjust calculations for jitter tol.
constant deltat: time := 50 ps;
-- Timing parameters
constant tWR: time := 15 ns;
constant tMRD_ck: integer := 2;
type timetab is array (0 to 5) of time;
constant tRAS : timetab := (50 ns, 45 ns, 42 ns, 40 ns, 40 ns, 40 ns);
constant tRP : timetab := (20 ns, 20 ns, 18 ns, 18 ns, 15 ns, 15 ns);
constant tRCD: timetab := (20 ns, 20 ns, 18 ns, 18 ns, 15 ns, 15 ns);
constant tRRD: timetab := (15 ns, 15 ns, 12 ns, 10 ns, 10 ns, 10 ns);
constant tRFC_lt1G: timetab := (80 ns, 75 ns, 72 ns, 70 ns, 70 ns, 70 ns); --Assuming<1Gb
constant tRFC_mt1G: time := 120 ns;
function tRFC return time is
begin
if density < 3 then return tRFC_lt1G(speedbin);
else return tRFC_mt1G; end if;
end tRFC;
begin
-----------------------------------------------------------------------------
-- Init sequence checker
-----------------------------------------------------------------------------
initp: process
variable cyctr : integer := 0;
procedure checkcmd(crasn,ccasn,cwen: std_ulogic;
cba: std_logic_vector(1 downto 0);
a10,a8,a0: std_ulogic) is
begin
wait until rising_edge(ck);
cyctr := cyctr+1;
while cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')) loop
wait until rising_edge(ck);
cyctr := cyctr+1;
end loop;
assert cke='1' and csn='0' and rasn=crasn and casn=ccasn and wen=cwen and
(cba="--" or cba=ba) and (a10='-' or a10=a(10)) and (a8='-' or a8=a(8)) and
(a0='-' or a0=a(0))
report "Wrong command during init sequence" severity warning;
end checkcmd;
begin
initdone <= false;
-- Allow cke to be X or U for a while during sim start
if is_x(cke) then
wait until not is_x(cke);
end if;
assert cke='0' report "CKE not deasserted on power-up" severity warning;
wait until cke/='0' for 200 us;
assert cke='0' report "CKE raised with less than 200 us init delay" severity warning;
wait until cke/='0' and rising_edge(ck);
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
-- Precharge all
checkcmd('0','1','0',"--",'1','-','-');
-- EMRS enable DLL
checkcmd('0','0','0',"01",'-','-','0');
-- MRS reset DLL
checkcmd('0','0','0',"00",'-','1','-');
cyctr := 0;
-- 200 cycle NOP
-- Precharge all
checkcmd('0','1','0',"--",'1','-','-');
assert cyctr >= 200
report "Command issued too quickly after DLL reset" severity warning;
-- 2 x auto refresh
checkcmd('0','0','1',"--",'-','-','-');
checkcmd('0','0','1',"--",'-','-','-');
-- MRS !reset DLL
checkcmd('0','0','0',"00",'-','0','-');
initdone <= true;
wait;
end process;
-----------------------------------------------------------------------------
-- Command state machine
-----------------------------------------------------------------------------
cmdp: process(ck)
subtype coldata is std_logic_vector(width-1 downto 0);
type coldata_arr is array(0 to implbanks*(2**(colbits+rowbits))-1) of coldata;
variable memdata: coldata_arr;
procedure load_srec is
file TCF : text open read_mode is fname;
variable L1: line;
variable CH : character;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable col, coloffs, len: integer;
begin
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := to_integer(unsigned(reclen))-1;
recaddr := (others => '0');
case rectype is
when "0001" => hread(L1, recaddr(15 downto 0)); len := len - 2;
when "0010" => hread(L1, recaddr(23 downto 0)); len := len - 3;
when "0011" => hread(L1, recaddr); len := len - 4;
when others => next;
end case;
hread(L1, recdata(0 to len*8-1));
col := to_integer(unsigned(recaddr(log2(width/8)+rowbits+colbits+1 downto log2(width/8))));
coloffs := 8*to_integer(unsigned(recaddr(log2(width/8)-1 downto 0)));
while len > width/8 loop
assert coloffs=0;
memdata(col) := recdata(0 to width-1);
col := col+1;
len := len-width/8;
recdata(0 to recdata'length-width-1) := recdata(width to recdata'length-1);
end loop;
memdata(col)(width-1-coloffs downto width-coloffs-len*8) := recdata(0 to len*8-1);
end if;
end if;
end if;
end loop;
end load_srec;
variable vmr: moderegs := ((others => '0'), "UUU", 'U', "UUU", (others => '0'), '0', '0', '0');
type bankstate is record
openrow: integer;
opentime: time;
closetime: time;
writetime: time;
autopch: integer;
end record;
type bankstate_arr is array(natural range <>) of bankstate;
variable banks: bankstate_arr(3 downto 0) := (others => (-1, 0 ns, 0 ns, 0 ns, -1));
type int_arr is array(natural range <>) of integer;
type dataacc is record
r,w: boolean;
col: int_arr(0 to 1);
bank: integer;
end record;
type dataacc_arr is array(natural range <>) of dataacc;
variable accpipe: dataacc_arr(0 to 9);
variable cmd: std_logic_vector(2 downto 0);
variable bank: integer;
variable colv: unsigned(a'high-1 downto 0);
variable alow: unsigned(2 downto 0);
variable col: integer;
variable prev_re, re: time;
variable blen: integer;
variable lastref: time := 0 ns;
variable i: integer;
variable b: boolean;
variable mrscount: integer := 0;
variable loaded: boolean := false;
procedure checktime(got, exp: time; gt: boolean; req: string) is
begin
assert (got + deltat > exp and gt) or (got-deltat < exp and not gt)
report (req & " violation, got: " & tost(got/(1 ps)) & " ps, exp: " & tost(exp/(1 ps)) & "ps")
severity warning;
end checktime;
begin
if rising_edge(ck) then
-- Update pipe regs
prev_re := re;
re := now;
accpipe(1 to accpipe'high) := accpipe(0 to accpipe'high-1);
accpipe(0).r:=false; accpipe(0).w:=false;
-- Main command handler
cmd := rasn & casn & wen;
if mrscount > 0 then
mrscount := mrscount-1;
assert cke='1' and (csn='1' or cmd="111") report "tMRS violation!" severity warning;
end if;
if cke='1' and csn='0' and cmd/="111" then
checktime(now-lastref, tRFC, true, "tRFC");
end if;
if cke='1' and csn='0' then
case cmd is
when "111" => -- NOP
when "011" => -- RAS
assert initdone report "Opening row before init sequence done!" severity warning;
bank := to_integer(unsigned(ba));
assert banks(bank).openrow < 0
report "Row already open" severity warning;
checktime(now-banks(bank).closetime, tRP(speedbin), true, "tRP");
for x in 0 to 3 loop
checktime(now-banks(x).opentime, tRRD(speedbin), true, "tRRD");
end loop;
banks(bank).openrow := to_integer(unsigned(a(rowbits-1 downto 0)));
banks(bank).opentime := now;
when "101" | "100" => -- Read/Write
bank := to_integer(unsigned(ba));
assert banks(bank).openrow >= 0
report "Row not open" severity error;
checktime(now-banks(bank).opentime, tRCD(speedbin), true, "tRCD");
for x in 0 to 3 loop
-- Xilinx V4 MIG controller issues multiple overlapping load commands
-- during calibration, therefore this assertion is bypassed before
-- load-delay has passed.
assert (not accpipe(x).r and not accpipe(x).w) or (now < lddelay);
end loop;
if cmd(0)='1' then accpipe(3).r:=true; else accpipe(3).w:=true; end if;
colv := unsigned(std_logic_vector'(a(a'high downto 11) & a(9 downto 0)));
case vmr.blen is
when "001" => blen := 2;
when "010" => blen := 4;
when "011" => blen := 8;
when others => assert false report "Invalid burst length setting in MR!" severity error;
end case;
alow := unsigned(a(2 downto 0));
for x in 0 to blen-1 loop
accpipe(3-x/2).bank := bank;
if cmd(0)='1' then accpipe(3-x/2).r:=true; else accpipe(3-x/2).w:=true; end if;
if vmr.bt='0' then -- Sequential
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) + x;
else -- Interleaved
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) xor to_unsigned(x,log2(blen));
end if;
col := to_integer(unsigned(ba))*(2**(colbits+rowbits)) +
banks(bank).openrow * (2**colbits) + to_integer(colv(colbits-1 downto 0));
accpipe(3-x/2).col(x mod 2) := col;
end loop;
-- Auto precharge
if a(10)='1' then
if cmd(0)='1' then
banks(bank).autopch := blen/2;
else
banks(bank).autopch := 1+blen/2 + (tWR-deltat+(re-prev_re))/(re-prev_re);
end if;
end if;
when "110" => -- Burst terminate
assert not accpipe(3).w
report "Burst terminate on write burst!" severity warning;
assert banks(accpipe(3).bank).autopch<0
report "Burst terminate on read with auto-precharge!" severity warning;
assert accpipe(3).r
report "Burst terminate with no effect!" severity warning;
for x in 3 downto 0 loop
accpipe(x).r := false;
accpipe(x).w := false;
end loop;
when "010" => -- Precharge
for x in 3 downto 0 loop
accpipe(x).r := false;
accpipe(x).w := false;
end loop;
for x in 0 to 3 loop
if a(10)='1' or ba=std_logic_vector(to_unsigned(x,2)) then
assert banks(x).autopch<0
report "Precharging bank that is auto-precharged" severity note;
assert a(10)='1' or banks(x).openrow>=0
report "Precharging single bank that is in idle state" severity note;
banks(x).autopch := 0; -- Handled below
end if;
end loop;
when "001" => -- Auto refresh
for x in 0 to 3 loop
assert banks(x).openrow < 0
report "Bank in wrong state for auto refresh!" severity warning;
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
lastref := now;
when "000" => -- MRS
for x in 0 to 3 loop
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
case ba is
when "00" =>
vmr.opmode(a'high-7 downto 0) := a(a'high downto 7);
vmr.caslat := a(6 downto 4);
vmr.bt := a(3);
vmr.blen := a(2 downto 0);
when "01" =>
vmr.opmode1(a'high-3 downto 0) := a(a'high downto 3);
vmr.res1 := a(2);
vmr.ds := a(1);
vmr.dlldis := a(0);
when others =>
assert false report ("MRS to invalid bank addr: " & std_logic'image(ba(1)) & std_logic'image(ba(0))) severity warning;
end case;
mrscount := tMRD_ck-1;
when others =>
assert false report ("Invalid command: " & std_logic'image(rasn) & std_logic'image(casn) & std_logic'image(wen)) severity warning;
end case;
end if;
-- Manual or auto precharge
for x in 0 to 3 loop
if banks(x).autopch=0 then
checktime(now-banks(x).writetime, tWR, true, "tWR");
checktime(now-banks(x).opentime, tRAS(speedbin), true, "tRAS");
banks(x).openrow := -1;
banks(x).closetime := now;
end if;
if banks(x).autopch >= 0 then
banks(x).autopch := banks(x).autopch - 1;
end if;
end loop;
-- Read/write management
if not loaded and lddelay < now then
load_srec;
loaded := true;
end if;
case vmr.caslat is
when "010" => i := 2; b:=false; -- CL2
when "011" => i := 3; b:=false; -- CL3
when "101" => i := 2; b:=true; -- CL1.5
when "110" => i := 3; b:=true; -- CL2.5
when others => i := 1;
end case;
hcmode <= b;
if b then hcread_en <= accpipe(1+i).r; else hcread_en <= false; end if;
if accpipe(2+i).r then
assert i>1 report "Incorrect CL setting!" severity warning;
read_en <= true;
-- print("Reading from col " & tost(accpipe(2+i).col(0)) & " and " & tost(accpipe(2+i).col(1)));
-- col0 <= accpipe(2+i).col(0); col1 <= accpipe(2+i).col(1);
read_data <= memdata(accpipe(2+i).col(0)) & memdata(accpipe(2+i).col(1));
else
read_en <= false;
end if;
write_en <= accpipe(3).w or accpipe(4).w;
if accpipe(5).w and write_mask/=(write_mask'range => '1') then
assert not is_x(write_mask) report "Write error";
for x in 0 to 1 loop
for b in width/8-1 downto 0 loop
if write_mask((1-x)*width/8+b)='0' then
memdata(accpipe(5).col(x))(8*b+7 downto 8*b) :=
write_data( (1-x)*width+b*8+7 downto (1-x)*width+b*8);
end if;
end loop;
end loop;
banks(accpipe(5).bank).writetime := now;
end if;
end if;
mr <= vmr;
end process;
-----------------------------------------------------------------------------
-- DQS/DQ handling and data sampling process
-----------------------------------------------------------------------------
dqproc: process
variable rdata: std_logic_vector(2*width-1 downto 0);
variable hdata: std_logic_vector(width-1 downto 0);
variable hmask: std_logic_vector(width/8-1 downto 0);
variable prevdqs: std_logic_vector(width/8-1 downto 0);
begin
dq <= (others => 'Z');
dqs <= (others => 'Z');
wait until (hcmode and hcread_en) or read_en or write_en;
assert not ((read_en or hcread_en) and write_en);
if (read_en or hcread_en) then
if hcmode then
wait until falling_edge(ck);
end if;
dqs <= (others => '0');
wait until falling_edge(ck);
while read_en loop
rdata := read_data;
if not hcmode then
wait until rising_edge(ck);
end if;
dqs <= (others => '1');
dq <= rdata(2*width-1 downto width);
if hcmode then
wait until rising_edge(ck);
else
wait until falling_edge(ck);
end if;
dqs <= (others => '0');
dq <= rdata(width-1 downto 0);
if hcmode then
wait until falling_edge(ck);
end if;
end loop;
if not hcmode then
wait until rising_edge(ck);
end if;
else
wait until falling_edge(ck);
assert to_X01(dqs)=(dqs'range => '0') or igndqs/=0;
while write_en loop
prevdqs := to_X01(dqs);
if igndqs /= 0 then
wait on ck,write_en;
else
wait until to_X01(dqs) /= prevdqs or not write_en or rising_edge(ck);
end if;
if rising_edge(ck) then
-- Just to make sure missing DQS is not undetected
write_data <= (others => 'X');
write_mask <= (others => 'X');
end if;
for x in dqs'range loop
if (igndqs=0 and prevdqs(x)='0' and to_X01(dqs(x))='1') or (igndqs/=0 and rising_edge(ck)) then
hdata(8*x+7 downto 8*x) := dq(8*x+7 downto 8*x);
hmask(x) := dm(x);
elsif (igndqs=0 and prevdqs(x)='1' and to_X01(dqs(x))='0') or (igndqs/=0 and falling_edge(ck)) then
write_data(width+8*x+7 downto width+8*x) <= hdata(8*x+7 downto 8*x);
write_data(8*x+7 downto 8*x) <= dq(8*x+7 downto 8*x);
write_mask(width/8+x) <= hmask(x);
write_mask(x) <= dm(x);
end if;
end loop;
end loop;
end if;
end process;
end;
-- pragma translate_on
|
gpl-2.0
|
44500a835dbd98945268f6c84026d0ee
| 0.53269 | 3.7418 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gsi/ssram/core_burst.vhd
| 3 | 21,018 |
-- Copyright © 2006. GSI Technology
-- Jeff Daugherty
-- [email protected]
-- Version: 3.2
--
-- FileName: core.vhd
-- Unified Sram Core Model for Sync Burst/NBT Sram
--
-- Revision History:
-- 04/23/02 1.0 1) Created VHDL Core.VHD from Verilog Core.V
-- 06/05/02 1.1 1) added new signals, DELAY and tKQX. These signals will
-- be used to setup the Clock to Data Invalid spec.
-- 07/17/02 1.2 1) Fixed the JTAG State machine
-- 2) changed the SR register to shift out the MSB and shift
-- in the LSB
-- 09/25/02 1.3 1) Removed all nPE pin features
-- 2) Max number of Core addresses is now dynamic
-- 3) Max width of Core data is now dynamic
-- 4) Removed alll reference of JTAG from core, seperate JTAG
-- model file: GSI_JTAG
-- 01/10/03 1.4 1) Created a Write_Array process to remove race conditions
-- 2) Created a Read_Array proccess to remove race conditions
-- 02/20/03 1.5 1) Added We and Waddr to Read_Array sensitivity list.
-- 2) Changed the Read_Array process to look at the last
-- write's byte write setting and determine where to pull the
-- read data from, either coherency(byte write on) or the
-- array(byte write off).
-- 3) Added signal Iscd to fix SCD to the right state for NBT
-- 04/03/03 1.6 1) Added a write clock W_k to trigger the Write_Array function
-- 07/09/03 1.7 1) changed NBT write clock to clock off of we2.
-- 2) Delayed the internal clock by 1ns to control the write
-- 3) changed ce to take into account NBT mode
-- 07/23/03 1.8 1) Changed W_K to ignore the byte writes
-- 08/12/03 1.9 1) updated state machine to include seperate read and write
-- burst states
-- 2) Changed internal bytewrite signal to ignore nW
-- 10/29/03 2.0 1) updated the state machine, changed reference to suspend
-- to deselect.
-- 2) added timing functions to core
-- 03/25/04 2.1 1) Updated state machine. Added deselect and suspend states
-- 2) Fixed other issues with the state machine
-- 04/28/04 2.2 1) Rearranged state that determins Deselect, Burst and Suspend
--
-- 11/01/05 3.0 1) Created BurstRAM only Model
-- 06/21/06 3.1 1) Added Qswitch to control when the IOs turn on or off
-- 2) Delayed the Qxi inteernal data busses instead of the DQx
-- external Data busses.
-- 3) Added CLK_i2 to control the setting of Qswitch
-- 4) All these changes removed Negative time issue for some simulations
--07/18/06 3.2 1) Initialized ce and re to 0 so that Qswitch is not
-- undfined which can cause bus contention on startup.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library grlib;
use grlib.stdio.all;
ENTITY VHDL_BURST_CORE IS
GENERIC (
CONSTANT bank_size : integer ;-- *16M /4 bytes in parallel
CONSTANT A_size : integer;
CONSTANT DQ_size : integer;
fname : string := "ram.dat"; -- File to read from
index : integer := 0); -- Index
PORT (
SIGNAL A : IN std_logic_vector(A_size - 1 DOWNTO 0);-- address
SIGNAL DQa : INOUT std_logic_vector(DQ_size DOWNTO 1);-- byte A data
SIGNAL DQb : INOUT std_logic_vector(DQ_size DOWNTO 1);-- byte B data
SIGNAL DQc : INOUT std_logic_vector(DQ_size DOWNTO 1);-- byte C data
SIGNAL DQd : INOUT std_logic_vector(DQ_size DOWNTO 1);-- byte D data
SIGNAL DQe : inout std_logic_vector(DQ_size DOWNTO 1);-- byte E data
SIGNAL DQf : inout std_logic_vector(DQ_size DOWNTO 1);-- byte F data
SIGNAL DQg : inout std_logic_vector(DQ_size DOWNTO 1);-- byte G data
SIGNAL DQh : inout std_logic_vector(DQ_size DOWNTO 1);-- byte H data
SIGNAL nBa : IN std_logic;-- bank A write enable
SIGNAL nBb : IN std_logic;-- bank B write enable
SIGNAL nBc : IN std_logic;-- bank C write enable
SIGNAL nBd : IN std_logic;-- bank D write enable
SIGNAL nBe : IN std_logic;-- bank E write enable
SIGNAL nBf : IN std_logic;-- bank F write enable
SIGNAL nBg : IN std_logic;-- bank G write enable
SIGNAL nBh : IN std_logic;-- bank H write enable
SIGNAL CK : IN std_logic;-- clock
SIGNAL nBW : IN std_logic;-- byte write enable
SIGNAL nGW : IN std_logic;-- Global write enable
SIGNAL nE1 : IN std_logic;-- chip enable 1
SIGNAL E2 : IN std_logic;-- chip enable 2
SIGNAL nE3 : IN std_logic;-- chip enable 3
SIGNAL nG : IN std_logic;-- output enable
SIGNAL nADV : IN std_logic;-- Advance not / load
SIGNAL nADSC : IN std_logic;
SIGNAL nADSP : IN std_logic;
SIGNAL ZZ : IN std_logic;-- power down
SIGNAL nFT : IN std_logic;-- Pipeline / Flow through
SIGNAL nLBO : IN std_logic;-- Linear Burst Order
SIGNAL SCD : IN std_logic;
SIGNAL HighZ : std_logic_vector(DQ_size downto 1);
SIGNAL tKQ : time;
SIGNAL tKQX : time);
END VHDL_BURST_CORE;
LIBRARY GSI;
LIBRARY Std;
ARCHITECTURE GSI_BURST_CORE OF VHDL_BURST_CORE IS
USE GSI.FUNCTIONS.ALL;
USE Std.textio.ALL;
TYPE MEMORY_0 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_1 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_2 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_3 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_4 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_5 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_6 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_7 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
-- ******** Define Sram Operation Mode **********************
shared variable bank0 : MEMORY_0 ;
shared variable bank1 : MEMORY_1 ;
shared variable bank2 : MEMORY_2 ;
shared variable bank3 : MEMORY_3 ;
shared variable bank4 : MEMORY_4 ;
shared variable bank5 : MEMORY_5 ;
shared variable bank6 : MEMORY_6 ;
shared variable bank7 : MEMORY_7 ;
-- ---------------------------------------------------------------
-- Gated SRAM Clock
-- ---------------------------------------------------------------
SIGNAL clk_i : std_logic;
SIGNAL clk_i2 : std_logic;
-- ---------------------------------------------------------------
-- Combinatorial Logic
-- ---------------------------------------------------------------
SIGNAL E : std_logic;-- internal chip enable
SIGNAL ADV : std_logic;-- internal address advance
SIGNAL ADS : std_logic;
SIGNAL ADSP : std_logic;
SIGNAL ADSC : std_logic;
SIGNAL W : std_logic;
SIGNAL R : std_logic;
SIGNAL W_k : std_logic;
SIGNAL R_k : std_logic;
SIGNAL BW : std_logic_vector(7 DOWNTO 0);-- internal byte write enable
SIGNAL Qai : std_logic_vector(DQ_size - 1 DOWNTO 0);-- read data
SIGNAL Qbi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Qci : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Qdi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Qei : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Qfi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Qgi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Qhi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- read data
SIGNAL Dai : std_logic_vector(DQ_size - 1 DOWNTO 0);-- write data
SIGNAL Dbi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Dci : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Ddi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Dei : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Dfi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Dgi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Dhi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- write data
SIGNAL bwi : std_logic_vector(7 DOWNTO 0);
SIGNAL addr0 : std_logic_vector(A_size - 1 DOWNTO 0);-- saved address
SIGNAL addr1 : std_logic_vector(A_size - 1 DOWNTO 0);-- address buffer 1
SIGNAL baddr : std_logic_vector(A_size - 1 DOWNTO 0);-- burst memory address
SIGNAL waddr : std_logic_vector(A_size - 1 DOWNTO 0);-- write memory address
SIGNAL raddr : std_logic_vector(A_size - 1 DOWNTO 0);-- read memory address
SIGNAL bcnt : std_logic_vector(1 DOWNTO 0) := to_stdlogicvector(0, 2);-- burst counter
SIGNAL we0 : std_logic := '0';
SIGNAL re0 : std_logic := '0';
SIGNAL re1 : std_logic := '0';
SIGNAL re2 : std_logic := '0';
SIGNAL ce0 : std_logic := '0';
SIGNAL ce1 : std_logic := '0';
SIGNAL ce : std_logic := '0';
SIGNAL re : std_logic := '0';
SIGNAL oe : std_logic;
SIGNAL we : std_logic;
SIGNAL Qswitch: std_logic ;
SIGNAL state : string (9 DOWNTO 1) := "IDLE ";
SIGNAL Check_Time : time := 1 ns;
SIGNAL DELAY : time := 1 ns;
SIGNAL GUARD : boolean:= TRUE;
-- TIMING FUNCTIONS
function POSEDGE (SIGNAL s : std_ulogic) return BOOLEAN IS
begin
RETURN (s'EVENT AND ((To_X01(s'LAST_VALUE) = '0') OR (s = '1')));
end;
function NEGEDGE (SIGNAL s : std_ulogic) return BOOLEAN IS
begin
RETURN (s'EVENT AND ((To_X01(s'LAST_VALUE) = '1') OR (s = '0')) );
end;
-- END TIMING FUNCTIONS
PROCEDURE shiftnow (SIGNAL addr1 : INOUT std_logic_vector(A_size - 1 DOWNTO 0);
SIGNAL re2 : INOUT std_logic;
SIGNAL re1 : INOUT std_logic;
SIGNAL ce1 : INOUT std_logic;
SIGNAL Dai : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Dbi : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Dci : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Ddi : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Dei : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Dfi : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Dgi : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Dhi : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0))
IS
BEGIN
addr1 <= baddr;
re2 <= re1;
re1 <= re0;
ce1 <= ce0;
Dai <= DQa;
Dbi <= DQb;
Dci <= DQc;
Ddi <= DQd;
Dei <= DQe;
Dfi <= DQf;
Dgi <= DQg;
Dhi <= DQh;
END;
BEGIN
PROCESS
BEGIN
WAIT UNTIL POSEDGE(CK);
clk_i <= NOT ZZ after 100 ps;
clk_i2 <= NOT ZZ after 200 ps;
WAIT UNTIL NEGEDGE(CK);
clk_i <= '0' after 100 ps;
clk_i2 <= '0' after 200 ps;
END PROCESS;
-- ---------------------------------------------------------------
-- State Machine
-- ---------------------------------------------------------------
st : PROCESS
variable tstate : string(9 DOWNTO 1) :="DESELECT ";
variable twe0 : std_logic := '0';
variable tre0 : std_logic := '0';
variable tce0 : std_logic := '0';
BEGIN
WAIT UNTIL POSEDGE(CK);
CASE state IS
WHEN "DESELECT " =>
if (E = '1') then
--Checking for ADSC Control
if (ADSC = '1') then
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tre0 := R;
twe0 := W;
tce0 := '1';
addr0 <= A;
bwi <= BW;
bcnt <= to_stdlogicvector(0, 2);
tstate := "NEWCYCLE ";
end if;
-- Checking for ADSP Control
if (ADSP = '1') then
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tre0 := R;
tce0 := '1';
addr0 <= A;
bcnt <= to_stdlogicvector(0, 2);
tstate := "LATEWRITE";
end if;
END IF;
-- Checking for Deselect
if ((E /= '1' and ADSC = '1') or (nADSP and (E2 = '0' or nE3 = '1'))) then
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tstate := "DESELECT ";
twe0 := '0';
tre0 := '0';
tce0 := '0';
END IF;
-- **************************************************
WHEN "NEWCYCLE " | "BURST " | "SUSPBR " | "LATEWRITE" =>
--Checking for ADSC Control
if (ADSC = '1') then
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tre0 := R;
twe0 := W;
tce0 := '1';
addr0 <= A;
bwi <= BW;
bcnt <= to_stdlogicvector(0, 2);
tstate := "NEWCYCLE ";
end if;
-- Checking for ADSP Control
if (ADSP = '1') then
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tre0 := R;
tce0 := '1';
addr0 <= A;
bcnt <= to_stdlogicvector(0, 2);
tstate := "LATEWRITE";
end if;
-- Checking for Deselect
if ((E /= '1' and nADSC = '0') or (nADSP = '0' and (E2 = '0' or nE3 = '1'))) then
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tstate := "DESELECT ";
twe0 := '0';
tre0 := '0';
tce0 := '0';
end if;
-- Checking for Burst Start
if (ADSC = '0' and ADSP = '0' AND ADV = '1') THEN
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tstate := "BURST ";
if we0 = '1' then
twe0 := W;
tre0 := '0';
bwi <= BW;
end if;
if re0 = '1' then
twe0 := '0';
tre0 := R;
end if;
tce0 := '1';
bcnt <= to_stdlogicvector(bcnt + "01", 2);
end if;
-- Checking for a Suspended Burst
if (ADSC = '0' and ADSP = '0' AND ADV = '0') THEN
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tstate := "SUSPBR ";
if we0 = '1' or W = '1' then
twe0 := W;
tre0 := '0';
re1 <= '0';
bwi <= BW;
elsif re0 = '1' then
twe0 := '0';
tre0 := R;
end if;
tce0 := '1';
end if;
WHEN OTHERS =>
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tstate := "DESELECT ";
twe0 := '0';
tre0 := '0';
tce0 := '0';
bcnt <= to_stdlogicvector(0, 2);
END CASE;
state <= tstate;
we0 <= twe0;
re0 <= tre0;
ce0 <= tce0;
END PROCESS;
RAMINIT : process
-- variable MEMA : MEM;
variable L1 : line;
-- variable FIRST : boolean := true;
variable ADR : std_logic_vector(19 downto 0);
variable BUF : std_logic_vector(31 downto 0);
variable CH : character;
variable ai : integer := 0;
variable len : integer := 0;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
begin
if fname /= "" then
-- if clear = 1 then MEMA := (others => X"00"); end if;
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := to_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
recaddr(31 downto 20) := (others => '0');
when others => next;
end case;
hread(L1, recdata);
-- if index = 6 then
-- ai := to_integer(recaddr);
-- for i in 0 to 15 loop
-- MEMA(ai+i) := recdata((i*8) to (i*8+7));
-- end loop;
-- elsif (index = 4) or (index = 5) then
ai := to_integer(recaddr)/4;
for i in 0 to 3 loop
bank0(ai+i) := '0' & recdata((i*32+index*16) to (i*32+index*16+7));
bank1(ai+i) := '0' & recdata((i*32+index*16+8) to (i*32+index*16+15));
end loop;
-- else
-- ai := conv_integer(recaddr)/4;
-- for i in 0 to 3 loop
-- MEMA(ai+i) := recdata((i*32+index*8) to (i*32+index*8+7));
-- end loop;
-- end if;
end if;
end if;
end if;
end loop;
end if;
wait;
end process;
-- ---------------------------------------------------------------
-- Data IO Logic
-- ---------------------------------------------------------------
Write_Array: process (W_k)
begin -- process Write_Array
IF (POSEDGE(W_k)) THEN
IF (we = '1') THEN
IF bwi(0) = '1' THEN
bank0(to_integer(waddr)) := Dai;
END IF;
IF bwi(1) = '1' THEN
bank1(to_integer(waddr)) := Dbi;
END IF;
IF bwi(2) = '1' THEN
bank2(to_integer(waddr)) := Dci;
END IF;
IF bwi(3) = '1' THEN
bank3(to_integer(waddr)) := Ddi;
END IF;
IF bwi(4) = '1' THEN
bank4(to_integer(waddr)) := Dei;
END IF;
IF bwi(5) = '1' THEN
bank5(to_integer(waddr)) := Dfi;
END IF;
IF bwi(6) = '1' THEN
bank6(to_integer(waddr)) := Dgi;
END IF;
IF bwi(7) = '1' THEN
bank7(to_integer(waddr)) := Dhi;
END IF;
END IF;
END IF;
end process Write_Array;
Read_Array: process (r_k)
begin -- process Read_Array
IF (we = '0') then
Qai <= transport bank0(to_integer(raddr)) after DELAY - 200 ps;
Qbi <= transport bank1(to_integer(raddr)) after DELAY - 200 ps;
Qci <= transport bank2(to_integer(raddr)) after DELAY - 200 ps;
Qdi <= transport bank3(to_integer(raddr)) after DELAY - 200 ps;
Qei <= transport bank4(to_integer(raddr)) after DELAY - 200 ps;
Qfi <= transport bank5(to_integer(raddr)) after DELAY - 200 ps;
Qgi <= transport bank6(to_integer(raddr)) after DELAY - 200 ps;
Qhi <= transport bank7(to_integer(raddr)) after DELAY - 200 ps;
END IF;
end process Read_Array;
-- check it -t option is active and set correctly
time_ck : process (CLK_i)
begin
check_time <= CK'last_event;
assert check_time /= 0 ns report "Resolution needs to be set to 100ps for modelSIM use vsim -t 100ps <>" severity FAILURE;
end process time_ck;
ADS_SET : process (CLK_i)
begin
if posedge(clk_i) then
ADS <= ADSP OR ADSC;
end if;
end process ADS_SET;
q_switch : process (CLK_i2)
begin --read clock controls outputs
Qswitch <= transport re and ce after DELAY - 200 ps;
end process q_switch;
E <= (NOT nE1 AND E2 AND NOT nE3);
ADV <= not nADV;
ADSP <= NOT nADSP AND ( E2 or NOT nE3);
ADSC <= NOT nADSC AND ( not nE1 or E2 or NOT nE3);
W <= (NOT nGW OR NOT nBW );
W_k <=((NOT ADSP or not ADSC) AND (NOT nGW OR NOT nBW )) and clk_i after 100 ps;
R <= nGW and nBW;
R_k <= (TERNARY((ADS or ADV) and not W, TERNARY( nFT, re1, re0), '0') and clk_i) after 100 ps;
BW(0) <= not nGW or (NOT nBa and not nBW);
BW(1) <= not nGW or (NOT nBb and not nBW);
BW(2) <= not nGW or (NOT nBc and not nBW);
BW(3) <= not nGW or (NOT nBd and not nBW);
BW(4) <= not nGW or (NOT nBe and not nBW);
BW(5) <= not nGW or (NOT nBf and not nBW);
BW(6) <= not nGW or (NOT nBg and not nBW);
BW(7) <= not nGW or (NOT nBh and not nBW);
baddr <= to_stdlogicvector(TERNARY(nLBO, addr0(A_size - 1 DOWNTO 2) & (bcnt(1) XOR addr0(1)) &
(bcnt(0) XOR addr0(0)), addr0(A_size - 1 DOWNTO 2) & (addr0(1 DOWNTO 0) + bcnt)), A_size);
waddr <= to_stdlogicvector(TERNARY(not ADV, addr0, baddr), A_size);
raddr <= to_stdlogicvector(TERNARY(nFT, addr1, baddr), A_size);
we <= we0;
re <= TERNARY(nFT, re1, re0);
ce <= (TERNARY(not SCD AND re2 = '1', ce1, ce0));
oe <= re AND ce;
DELAY <= TERNARY(nG OR not ((we and re) or oe) OR ZZ, tKQ, tKQX);
DQa <= GUARDED TERNARY(Qswitch, Qai, HighZ);
DQb <= GUARDED TERNARY(Qswitch, Qbi, HighZ);
DQc <= GUARDED TERNARY(Qswitch, Qci, HighZ);
DQd <= GUARDED TERNARY(Qswitch, Qdi, HighZ);
DQe <= GUARDED TERNARY(Qswitch, Qei, HighZ);
DQf <= GUARDED TERNARY(Qswitch, Qfi, HighZ);
DQg <= GUARDED TERNARY(Qswitch, Qgi, HighZ);
DQh <= GUARDED TERNARY(Qswitch, Qhi, HighZ);
END GSI_BURST_CORE;
|
gpl-2.0
|
612d09a47bdfd6ce54beadd540bb7db2
| 0.543724 | 3.400971 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3mp/testbench.vhd
| 1 | 19,905 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use gaisler.jtagtst.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 21; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART1 tx data
rxd2 : in std_ulogic; -- UART1 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emddis : out std_logic;
epwrdwn : out std_logic;
ereset : out std_logic;
esleep : out std_logic;
epause : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
can_stb : out std_ulogic;
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2);
tck, tms, tdi : in std_ulogic;
tdo : out std_ulogic
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic;
signal gtx_clk : std_ulogic;
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_ulogic;
signal can_rxd : std_ulogic;
signal can_stb : std_ulogic;
signal spw_clk : std_ulogic := '0';
signal spw_rxd : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxs : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txd : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txs : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal tck, tms, tdi, tdo : std_ulogic;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant CFG_SD64 : integer := CFG_SDCTRL_SD64 + CFG_MCTRL_SD64;
begin
-- clock and reset
spw_clk <= not spw_clk after 20 ns;
spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0);
spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0);
spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1);
spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1);
spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2);
spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2);
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
--## can_rxd <= '1';
can_rxd <= can_txd; -- CAN LOOP BACK ##
d3 : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, sdclk, error, address(27 downto 0), data,
sa, sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc, emddis, epwrdwn, ereset, esleep, epause,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd, can_stb, spw_clk, spw_rxd, spw_rxdn, spw_rxs,
spw_rxsn, spw_txd, spw_txdn, spw_txs, spw_txsn, tck, tms, tdi, tdo);
-- optional sdram
sd0 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
sd1 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
sd64 : if (CFG_SD64 /= 0) generate
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sbanks : for k in 0 to srambanks-1 generate
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8),
ramsn(k), rwen(i), ramoen(k));
end generate;
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
jtagproc : process
begin
wait;
jtagcom(tdo, tck, tms, tdi, 100, 20, 16#40000000#, true);
wait;
end process;
end;
|
gpl-2.0
|
72f3b592adf3d1547b0d90644a61f63f
| 0.575484 | 3.042648 | false | false | false | false |
rhexsel/cmips
|
cMIPS/vhdl/packageMemory_simu.vhd
| 1 | 17,654 |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
package p_MEMORY is
-- To simplify (and accelerate) the RAM address decoding,
-- the BASE of the RAM addresses MUST be allocated at an
-- address which is at a different power of two than the ROM base.
-- Otherwise, the base must be subtracted from the address on every
-- reference, which means having an adder in the critical path.
-- Not good at all.
-- The address ranges for ROM, RAM and I/O must be distinct in the
-- uppermost 16 bits of the address (bits 31..16).
constant HI_SEL_BITS : integer := 31;
constant LO_SEL_BITS : integer := 16;
-- x_IO_ADDR_RANGE can have only ONE bit set, thus being a power of 2.
-- ACHTUNG: changing that definition may break some of the test programs.
-- begin DO NOT change these names as several scripts depend on them --
-- you may change the values, not names neither formatting --
constant x_INST_BASE_ADDR : reg32 := x"00000000";
constant x_INST_MEM_SZ : reg32 := x"00004000";
constant x_DATA_BASE_ADDR : reg32 := x"00040000";
constant x_DATA_MEM_SZ : reg32 := x"00020000";
constant x_IO_BASE_ADDR : reg32 := x"3c000000";
constant x_IO_MEM_SZ : reg32 := x"00002000";
constant x_IO_ADDR_RANGE : reg32 := x"00000020";
constant x_SDRAM_BASE_ADDR : reg32 := x"04000000";
constant x_SDRAM_MEM_SZ : reg32 := x"02000000";
constant x_EXCEPTION_0000 : reg32 := x"00000130"; -- TLBrefill
constant x_EXCEPTION_0100 : reg32 := x"00000200"; -- CacheError
constant x_EXCEPTION_0180 : reg32 := x"00000280"; -- generalExcpHandler
constant x_EXCEPTION_0200 : reg32 := x"00000400"; -- separInterrHandler
constant x_EXCEPTION_BFC0 : reg32 := x"000004E0"; -- NMI, soft-reset
constant x_ENTRY_POINT : reg32 := x"00000500"; -- main()
-- end DO NOT change these names --
constant INST_BASE_ADDR : integer := to_integer(signed(x_INST_BASE_ADDR));
constant INST_MEM_SZ : integer := to_integer(signed(x_INST_MEM_SZ));
constant INST_ADDRS_BITS : natural := log2_ceil(INST_MEM_SZ);
constant DATA_BASE_ADDR : integer := to_integer(signed(x_DATA_BASE_ADDR));
constant DATA_MEM_SZ : integer := to_integer(signed(x_DATA_MEM_SZ));
constant SDRAM_BASE_ADDR : integer := to_integer(signed(x_SDRAM_BASE_ADDR));
constant SDRAM_MEM_SZ : integer := to_integer(signed(x_SDRAM_MEM_SZ));
constant IO_BASE_ADDR : integer := to_integer(signed(x_IO_BASE_ADDR));
constant IO_MEM_SZ : integer := to_integer(signed(x_IO_MEM_SZ));
constant IO_ADDR_RANGE : integer := to_integer(signed(x_IO_ADDR_RANGE));
-- maximum number of IO devices, must be a power of two.
constant IO_MAX_NUM_DEVS : integer := 16;
constant IO_ADDR_BITS : integer := log2_ceil(IO_MAX_NUM_DEVS * IO_ADDR_RANGE);
-- I/O addresses are IO_ADDR_RANGE apart
constant IO_PRINT_ADDR : integer := IO_BASE_ADDR;
constant IO_STDOUT_ADDR : integer := IO_BASE_ADDR + 1*IO_ADDR_RANGE;
constant IO_STDIN_ADDR : integer := IO_BASE_ADDR + 2*IO_ADDR_RANGE;
constant IO_READ_ADDR : integer := IO_BASE_ADDR + 3*IO_ADDR_RANGE;
constant IO_WRITE_ADDR : integer := IO_BASE_ADDR + 4*IO_ADDR_RANGE;
constant IO_COUNT_ADDR : integer := IO_BASE_ADDR + 5*IO_ADDR_RANGE;
constant IO_FPU_ADDR : integer := IO_BASE_ADDR + 6*IO_ADDR_RANGE;
constant IO_UART_ADDR : integer := IO_BASE_ADDR + 7*IO_ADDR_RANGE;
constant IO_STATS_ADDR : integer := IO_BASE_ADDR + 8*IO_ADDR_RANGE;
constant IO_DSP7SEG_ADDR : integer := IO_BASE_ADDR + 9*IO_ADDR_RANGE;
constant IO_KEYBD_ADDR : integer := IO_BASE_ADDR + 10*IO_ADDR_RANGE;
constant IO_LCD_ADDR : integer := IO_BASE_ADDR + 11*IO_ADDR_RANGE;
constant IO_SDC_ADDR : integer := IO_BASE_ADDR + 12*IO_ADDR_RANGE;
constant IO_DMA_ADDR : integer := IO_BASE_ADDR + 13*IO_ADDR_RANGE;
constant IO_HIGHEST_ADDR : integer :=
IO_BASE_ADDR + (IO_MAX_NUM_DEVS - 1)*IO_ADDR_RANGE;
-- DATA CACHE parameters ================================================
-- The combination of capacity, associativity and block/line size
-- MUST be such that DC_INDEX_BITS >= 6 (64 sets/way)
constant DC_TOTAL_CAPACITY : natural := 2*1024;
constant DC_NUM_WAYS : natural := 1; -- direct mapped
constant DC_VIA_CAPACITY : natural := DC_TOTAL_CAPACITY / DC_NUM_WAYS;
constant DC_BTS_PER_WORD : natural := 32;
constant DC_BYTES_PER_WORD : natural := 4;
constant DC_WORDS_PER_BLOCK : natural := 4;
constant DC_NUM_WORDS : natural := DC_VIA_CAPACITY / DC_BYTES_PER_WORD;
constant DC_NUM_BLOCKS : natural := DC_NUM_WORDS / DC_WORDS_PER_BLOCK;
constant DC_INDEX_BITS : natural := log2_ceil( DC_NUM_BLOCKS );
constant DC_WORD_SEL_BITS : natural := log2_ceil( DC_WORDS_PER_BLOCK );
constant DC_BYTE_SEL_BITS : natural := log2_ceil( DC_BYTES_PER_WORD );
-- constants for CONFIG1 cop0 register (Table 8-24 pg 103)
constant DC_SETS_PER_WAY: reg3 :=
std_logic_vector(to_unsigned(DC_INDEX_BITS - 6, 3));
constant DC_LINE_SIZE: reg3 :=
std_logic_vector(to_unsigned(DC_WORD_SEL_BITS + 1, 3));
constant DC_ASSOCIATIVITY: reg3 :=
std_logic_vector(to_unsigned(DC_NUM_WAYS - 1, 3));
-- INSTRUCTION CACHE parameters =========================================
-- The combination of capacity, associativity and block/line size
-- MUST be such that IC_INDEX_BITS >= 6 (64 sets/via)
constant IC_TOTAL_CAPACITY : natural := 1024; -- 2*1024;
constant IC_NUM_WAYS : natural := 1; -- direct mapped
constant IC_VIA_CAPACITY : natural := IC_TOTAL_CAPACITY / IC_NUM_WAYS;
constant IC_BTS_PER_WORD : natural := 32;
constant IC_BYTES_PER_WORD : natural := 4;
constant IC_WORDS_PER_BLOCK : natural := 4;
constant IC_NUM_WORDS : natural := IC_VIA_CAPACITY / IC_BYTES_PER_WORD;
constant IC_NUM_BLOCKS : natural := IC_NUM_WORDS / IC_WORDS_PER_BLOCK;
constant IC_INDEX_BITS : natural := log2_ceil( IC_NUM_BLOCKS );
constant IC_WORD_SEL_BITS : natural := log2_ceil( IC_WORDS_PER_BLOCK );
constant IC_BYTE_SEL_BITS : natural := log2_ceil( IC_BYTES_PER_WORD );
-- constants for CONFIG1 cop0 register (Table 8-24 pg 103)
constant IC_SETS_PER_WAY: reg3 :=
std_logic_vector(to_unsigned(IC_INDEX_BITS - 6, 3));
constant IC_LINE_SIZE: reg3 :=
std_logic_vector(to_unsigned(IC_WORD_SEL_BITS + 1, 3));
constant IC_ASSOCIATIVITY: reg3 :=
std_logic_vector(to_unsigned(IC_NUM_WAYS - 1, 3));
-- constants to access the cache statistics counters
constant dcache_Stats_ref : reg3 := "000";
constant dcache_Stats_rdhit : reg3 := "001";
constant dcache_Stats_wrhit : reg3 := "010";
constant dcache_Stats_flush : reg3 := "011";
constant icache_Stats_ref : reg3 := "100";
constant icache_Stats_hit : reg3 := "101";
-- MMU parameters ========================================================
-- constants for CONFIG1 cop0 register (Table 8-24 pg 103)
constant MMU_CAPACITY : natural := 8;
constant MMU_CAPACITY_BITS : natural := log2_ceil( MMU_CAPACITY );
constant MMU_SIZE: reg6 :=
std_logic_vector(to_unsigned( (MMU_CAPACITY-1), 6) );
constant MMU_WIRED_INIT : reg32 := x"00000000";
constant VABITS : natural := 32;
constant PABITS : natural := 32;
constant PAGE_SZ : natural := 4096; -- 4k pages
constant PAGE_SZ_BITS : natural := log2_ceil( PAGE_SZ );
constant PPN_BITS : natural := PABITS - PAGE_SZ_BITS;
constant VA_HI_BIT : natural := 31; -- VAaddr in EntryHi 31..PG_size
constant VA_LO_BIT : natural := PAGE_SZ_BITS + 1; -- maps 2 phy-pages
constant ASID_HI_BIT : natural := 7; -- ASID in EntryHi 7..0
constant ASID_LO_BIT : natural := 0;
constant EHI_ASIDLO_BIT : natural := 0;
constant EHI_ASIDHI_BIT : natural := 7;
constant EHI_G_BIT : natural := 8;
constant EHI_ALO_BIT : natural := PAGE_SZ_BITS + 1; -- maps 2 phy-pages
constant EHI_AHI_BIT : natural := 31;
constant EHI_ZEROS : std_logic_vector(PAGE_SZ_BITS-EHI_G_BIT-1 downto 0) := (others => '0');
constant TAG_ASIDLO_BIT : natural := 0;
constant TAG_ASIDHI_BIT : natural := 7;
constant TAG_G_BIT : natural := 8;
constant TAG_Z_BIT : natural := 9;
constant TAG_ALO_BIT : natural := PAGE_SZ_BITS + 1; -- maps 2 phy-pages
constant TAG_AHI_BIT : natural := 31;
constant ELO_G_BIT : natural := 0;
constant ELO_V_BIT : natural := 1;
constant ELO_D_BIT : natural := 2;
constant ELO_CLO_BIT : natural := 3;
constant ELO_CHI_BIT : natural := 5;
constant ELO_ALO_BIT : natural := 6;
constant ELO_AHI_BIT : natural := ELO_ALO_BIT + PPN_BITS - 1;
constant DAT_G_BIT : natural := 0;
constant DAT_V_BIT : natural := 1;
constant DAT_D_BIT : natural := 2;
constant DAT_CLO_BIT : natural := 3;
constant DAT_CHI_BIT : natural := 5;
constant DAT_ALO_BIT : natural := 6;
constant DAT_AHI_BIT : natural := DAT_ALO_BIT + PPN_BITS - 1;
constant DAT_REG_BITS : natural := DAT_ALO_BIT + PPN_BITS;
constant ContextPTE_init : reg9 := b"000000000";
constant mmu_PageMask : reg32 := x"00001800"; -- pg 68, 4k pages only
subtype mmu_dat_reg is std_logic_vector (DAT_AHI_BIT downto 0);
subtype MMU_idx_bits is std_logic_vector(MMU_CAPACITY_BITS-1 downto 0);
constant MMU_idx_0s : std_logic_vector(30 downto MMU_CAPACITY_BITS) :=
(others => '0');
constant MMU_IDX_BIT : natural := 31; -- probe hit=1, miss=0
-- VA tags map a pair of PHY pages, thus VAddr is 1 bit less than (VABITS-1..PAGE_SZ_BITS)
constant tag_zeros : std_logic_vector(PAGE_SZ_BITS downto 0) := (others => '0');
constant tag_ones : std_logic_vector(VABITS-1 downto PAGE_SZ_BITS+1) := (others => '1');
constant tag_mask : reg32 := tag_ones & tag_zeros;
constant tag_g : reg32 := x"00000100";
-- physical addresses for 8 ROM pages
constant x_ROM_PPN_0 : reg32 := std_logic_vector(to_unsigned(INST_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_ROM_PPN_1 : reg32 := std_logic_vector(to_unsigned(INST_BASE_ADDR + 1*PAGE_SZ, 32));
constant x_ROM_PPN_2 : reg32 := std_logic_vector(to_unsigned(INST_BASE_ADDR + 2*PAGE_SZ, 32));
constant x_ROM_PPN_3 : reg32 := std_logic_vector(to_unsigned(INST_BASE_ADDR + 3*PAGE_SZ, 32));
constant x_ROM_PPN_4 : reg32 := std_logic_vector(to_unsigned(INST_BASE_ADDR + 4*PAGE_SZ, 32));
constant x_ROM_PPN_5 : reg32 := std_logic_vector(to_unsigned(INST_BASE_ADDR + 5*PAGE_SZ, 32));
constant x_ROM_PPN_6 : reg32 := std_logic_vector(to_unsigned(INST_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_ROM_PPN_7 : reg32 := std_logic_vector(to_unsigned(INST_BASE_ADDR + 7*PAGE_SZ, 32));
constant MMU_ini_tag_ROM0 : reg32 := (x_ROM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM0 : mmu_dat_reg :=
x_ROM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM1 : mmu_dat_reg :=
x_ROM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_ROM2 : reg32 := (x_ROM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM2 : mmu_dat_reg :=
x_ROM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM3 : mmu_dat_reg :=
x_ROM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_ROM4 : reg32 := (x_ROM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM4 : mmu_dat_reg :=
x_ROM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM5 : mmu_dat_reg :=
x_ROM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_ROM6 : reg32 := (x_ROM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM6 : mmu_dat_reg :=
x_ROM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM7 : mmu_dat_reg :=
x_ROM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 8 RAM pages
constant x_RAM_PPN_0 : reg32 := std_logic_vector(to_unsigned(DATA_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_RAM_PPN_1 : reg32 := std_logic_vector(to_unsigned(DATA_BASE_ADDR + 1*PAGE_SZ, 32));
constant x_RAM_PPN_2 : reg32 := std_logic_vector(to_unsigned(DATA_BASE_ADDR + 2*PAGE_SZ, 32));
constant x_RAM_PPN_3 : reg32 := std_logic_vector(to_unsigned(DATA_BASE_ADDR + 3*PAGE_SZ, 32));
constant x_RAM_PPN_4 : reg32 := std_logic_vector(to_unsigned(DATA_BASE_ADDR + 4*PAGE_SZ, 32));
constant x_RAM_PPN_5 : reg32 := std_logic_vector(to_unsigned(DATA_BASE_ADDR + 5*PAGE_SZ, 32));
constant x_RAM_PPN_6 : reg32 := std_logic_vector(to_unsigned(DATA_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_RAM_PPN_7 : reg32 := std_logic_vector(to_unsigned(DATA_BASE_ADDR + 7*PAGE_SZ, 32));
constant MMU_ini_tag_RAM0 : reg32 := (x_RAM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM0 : mmu_dat_reg :=
x_RAM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM1 : mmu_dat_reg :=
x_RAM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_RAM2 : reg32 := (x_RAM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM2 : mmu_dat_reg :=
x_RAM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM3 : mmu_dat_reg :=
x_RAM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_RAM4 : reg32 := (x_RAM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM4 : mmu_dat_reg :=
x_RAM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM5 : mmu_dat_reg :=
x_RAM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_RAM6 : reg32 := (x_RAM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM6 : mmu_dat_reg :=
x_RAM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM7 : mmu_dat_reg :=
x_RAM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 2 pages reserved for I/O devices
constant x_IO_PPN_0 : reg32 := std_logic_vector(to_unsigned(IO_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_IO_PPN_1 : reg32 := std_logic_vector(to_unsigned(IO_BASE_ADDR + 1*PAGE_SZ, 32));
constant MMU_ini_tag_IO : reg32 := (x_IO_BASE_ADDR and tag_mask) or tag_g;
constant MMU_ini_dat_IO0 : mmu_dat_reg :=
x_IO_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_IO1 : mmu_dat_reg :=
x_IO_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 8 SDRAM pages
constant x_SDRAM_PPN_0 : reg32 := std_logic_vector(to_unsigned(SDRAM_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_SDRAM_PPN_1 : reg32 := std_logic_vector(to_unsigned(SDRAM_BASE_ADDR + 1*PAGE_SZ, 32));
constant x_SDRAM_PPN_2 : reg32 := std_logic_vector(to_unsigned(SDRAM_BASE_ADDR + 2*PAGE_SZ, 32));
constant x_SDRAM_PPN_3 : reg32 := std_logic_vector(to_unsigned(SDRAM_BASE_ADDR + 3*PAGE_SZ, 32));
constant x_SDRAM_PPN_4 : reg32 := std_logic_vector(to_unsigned(SDRAM_BASE_ADDR + 4*PAGE_SZ, 32));
constant x_SDRAM_PPN_5 : reg32 := std_logic_vector(to_unsigned(SDRAM_BASE_ADDR + 5*PAGE_SZ, 32));
constant x_SDRAM_PPN_6 : reg32 := std_logic_vector(to_unsigned(SDRAM_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_SDRAM_PPN_7 : reg32 := std_logic_vector(to_unsigned(SDRAM_BASE_ADDR + 7*PAGE_SZ, 32));
constant MMU_ini_tag_SDR0 : reg32 := (x_SDRAM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR0 : mmu_dat_reg :=
x_SDRAM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR1 : mmu_dat_reg :=
x_SDRAM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR2 : reg32 := (x_SDRAM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR2 : mmu_dat_reg :=
x_SDRAM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR3 : mmu_dat_reg :=
x_SDRAM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR4 : reg32 := (x_SDRAM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR4 : mmu_dat_reg :=
x_SDRAM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR5 : mmu_dat_reg :=
x_SDRAM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR6 : reg32 := (x_SDRAM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR6 : mmu_dat_reg :=
x_SDRAM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR7 : mmu_dat_reg :=
x_SDRAM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
end p_MEMORY;
-- package body p_MEMORY is
-- end p_MEMORY;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
gpl-3.0
|
1a2c2e32e7bf7b19b66413e6f741109e
| 0.642404 | 2.966062 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-avnet-eval-xc4vlx25/leon3mp.vhd
| 1 | 21,946 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
ddrfreq : integer := 100000 -- frequency of ddr clock in kHz
);
port (
resetn : in std_ulogic;
resoutn : out std_logic;
clk_100mhz : in std_ulogic;
errorn : out std_ulogic;
-- prom interface
address : out std_logic_vector(21 downto 0);
data : inout std_logic_vector(15 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
romrstn : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(15 downto 0);
-- pragma translate_on
-- ddr memory
ddr_clk0 : out std_logic;
ddr_clk0b : out std_logic;
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke0 : out std_logic;
ddr_cs0b : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
-- UART for serial DCL/console I/O
serrx : in std_ulogic;
sertx : out std_ulogic;
rtsn : out std_ulogic;
ctsn : in std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- ethernet signals
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
erstn : out std_ulogic;
-- OLED display signals
disp_dcn : out std_ulogic;
disp_csn : out std_ulogic;
disp_rdn : out std_ulogic;
disp_wrn : out std_ulogic;
disp_d : inout std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal lclk : std_ulogic;
signal ddrclk, ddrrst, ddrclkfb : std_ulogic;
signal clkm, rstn, clkml, clk2x : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal tck, tms, tdi, tdo : std_ulogic;
-- signal dsubre : std_logic;
signal duart, ldsuen : std_logic;
signal rsertx, rserrx, rdsuen : std_logic;
signal rstraw : std_logic;
signal rstneg : std_logic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal lock : std_logic;
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector(13 downto 0); -- ddr address
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
romrstn <= rstn;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
rstneg <= not resetn;
rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw);
clk_pad : clkpad generic map (tech => padtech) port map (clk_100mhz, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, 0, 1, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0,
paddr => 0, srbanks => 1, ramaddr => 16#600#, rammask => 16#F00#, ram16 => 1 )
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (width => 22, tech => padtech)
port map (address, memo.address(22 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (testdata(15-i*8 downto 8-i*8), memo.data(15-i*8 downto 8-i*8),
memo.bdrive(i+2), memi.data(15-i*8 downto 8-i*8));
end generate;
-- pragma translate_on
bdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(15-i*8 downto 8-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- DDR memory controller -------------------------------------------
----------------------------------------------------------------------
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc : ddrspa generic map ( fabtech => virtex4, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, rskew => -95
-- pragma translate_off
* 0 -- disable clock skew during simulation
-- pragma translate_on
, clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000, ddrbits => 16)
port map (
rstneg, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(4),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0);
ddr_cke0 <= ddr_cke(0); ddr_cs0b <= ddr_csb(0);
ddr_ad <= ddr_adl(12 downto 0);
end generate;
noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => 12 --CFG_GRGPIO_WIDTH
)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
disp_csn_pad : outpad generic map (tech => padtech)
port map (disp_csn, gpioo.dout(8));
disp_dcn_pad : outpad generic map (tech => padtech)
port map (disp_dcn, gpioo.dout(9));
disp_rdn_pad : outpad generic map (tech => padtech)
port map (disp_rdn, gpioo.dout(10));
disp_wrn_pad : outpad generic map (tech => padtech)
port map (disp_wrn, gpioo.dout(11));
disp_d_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech)
port map (disp_d(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
phyrstadr => 3, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : inpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : inpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
erstn_pad : outpad generic map (tech => padtech)
port map (erstn, rstn);
end generate;
-----------------------------------------------------------------------
--- AHB DMA ----------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH,
-- pindex => 12, paddr => 12, dbuf => 32)
-- port map (rstn, clkm, apbi, apbo(12), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH));
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 9 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
resoutn <= rstn;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design for Avnet Virtex4 Eval board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
-- use switch 1 to multiplex DSU UART and UART1
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, ldsuen);
duart <= rdsuen when CFG_AHB_UART /= 0 else '0';
rxd1 <= txd1 when duart = '1' else rserrx;
rsertx <= duo.txd when duart = '1' else txd1;
dui.rxd <= rserrx when duart = '1' else '1';
led_rx <= not rserrx;
p1 : process(clkm)
begin
if rising_edge(clkm) then
sertx <= rsertx; rserrx <= serrx; rdsuen <= ldsuen;
rtsn <= '0';
led_tx <= not rsertx;
end if;
end process;
end rtl;
|
gpl-2.0
|
6c099164808d023c759bb92d9caa7ad6
| 0.538777 | 3.732948 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/esa/pci/pciarb.vhd
| 3 | 5,162 |
------------------------------------------------------------------------------
-- Entity: esa_pciarb
-- File: esa_pciarb.vhd
-- Author: Marko Isomaki
-- Description: GRLIB wrapper for the ESA PCI arbiter
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
library esa;
library techmap;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
use techmap.gencomp.all;
use techmap.netcomp.all;
use esa.pci_arb_pkg.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity pciarb is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
nb_agents : integer := 4;
apb_en : integer := 1;
netlist : integer := 0;
tech : integer := axcel;
reg : integer := 0);
port(
clk : in std_ulogic;
rst_n : in std_ulogic;
req_n : in std_logic_vector(0 to nb_agents-1);
frame_n : in std_logic;
gnt_n : out std_logic_vector(0 to nb_agents-1);
pclk : in std_ulogic;
prst_n : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end entity;
architecture rtl of pciarb is
component pci_arb is
generic(
NB_AGENTS : integer := 4;
ARB_SIZE : integer := 2;
APB_EN : integer := 1
);
port(
clk : in clk_type; -- clock
rst_n : in std_logic; -- async reset active low
req_n : in std_logic_vector(0 to NB_AGENTS-1); -- bus request
frame_n : in std_logic;
gnt_n : out std_logic_vector(0 to NB_AGENTS-1); -- bus grant
pclk : in clk_type; -- APB clock
prst_n : in std_logic; -- APB reset
pbi : in EAPB_Slv_In_Type; -- APB inputs
pbo : out EAPB_Slv_Out_Type -- APB outputs
);
end component;
component pci_arb_net is
generic (
nb_agents : integer := 4;
arb_size : integer := 2;
apb_en : integer := 1;
tech : integer := axcel
);
port (
clk : in std_logic; -- clock
rst_n : in std_logic; -- async reset active low
req_n : in std_logic_vector(0 to NB_AGENTS-1); -- bus request
frame_n : in std_logic;
gnt_n : out std_logic_vector(0 to NB_AGENTS-1); -- bus grant
pclk : in std_logic; -- APB clock
prst_n : in std_logic; -- APB reset
pbi_psel : in std_ulogic; -- slave select
pbi_penable: in std_ulogic; -- strobe
pbi_paddr : in std_logic_vector(31 downto 0); -- address bus (byte)
pbi_pwrite : in std_ulogic; -- write
pbi_pwdata : in std_logic_vector(31 downto 0); -- write data bus
pbo_prdata : out std_logic_vector(31 downto 0) -- read data bus
);
end component;
signal pbi : eapb_slv_in_type;
signal pbo : eapb_slv_out_type;
-- Added to latch frame and req in registers
signal frame_n_int : std_logic;
signal req_n_int : std_logic_vector(0 to NB_AGENTS-1);
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_PCIARB, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
begin
reg0 : if reg /= 0 generate
process(clk)
begin
if rising_edge(clk) then
frame_n_int <= frame_n;
req_n_int <= req_n;
end if;
end process;
end generate;
noreg0 : if reg = 0 generate
frame_n_int <= frame_n;
req_n_int <= req_n;
end generate;
rtl0 : if netlist = 0 generate
arb : pci_arb
generic map(
NB_AGENTS => nb_agents, ARB_SIZE => log2(nb_agents), APB_EN => apb_en)
port map(
clk => clk, rst_n => rst_n, req_n => req_n_int, frame_n => frame_n_int,
gnt_n => gnt_n, pclk => pclk, prst_n => prst_n, pbi => pbi, pbo => pbo);
end generate;
net0 : if netlist /= 0 generate
arb : pci_arb_net
generic map(
NB_AGENTS => nb_agents, ARB_SIZE => log2(nb_agents), APB_EN => apb_en,
tech => tech)
port map(
clk => clk, rst_n => rst_n, req_n => req_n_int, frame_n => frame_n_int,
gnt_n => gnt_n, pclk => pclk, prst_n => prst_n,
pbi_psel => pbi.psel,
pbi_penable => pbi.penable,
pbi_paddr => pbi.paddr,
pbi_pwrite => pbi.pwrite,
pbi_pwdata => pbi.pwdata,
pbo_prdata => pbo.prdata);
end generate;
apb_en1: if apb_en /= 0 generate
apbo.prdata <= pbo.prdata;
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
end generate apb_en1;
pbi.psel <= apbi.psel(pindex);
pbi.penable <= apbi.penable;
pbi.paddr <= apbi.paddr;
pbi.pwrite <= apbi.pwrite;
pbi.pwdata <= apbi.pwdata;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("pciarb" & tost(pindex) &
": PCI arbiter, " & tost(nb_agents) & " masters");
-- pragma translate_on
end architecture;
|
gpl-2.0
|
5a3a2ba2ea8d22db7d2bfe801c4560d5
| 0.535258 | 3.345431 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-ztex-ufm-111/leon3mp.vhd
| 1 | 16,656 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <[email protected]>
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
use work.config.all;
library unisim;
use unisim.vcomponents.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk48 : in std_ulogic;
errorn : out std_logic;
-- DDR SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
dsuact : out std_ulogic; -- Debug Unit break (connect to button)
-- AHB UART (debug link)
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- SD card
sd_dat : inout std_logic;
sd_cmd : inout std_logic;
sd_sck : inout std_logic;
sd_dat3 : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal clk200 : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal cgo_ddr : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal lclk, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 48000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk48_pad : clkpad generic map (tech => padtech) port map (clk48, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_DDR2 = 1) generate
clkgen_ddr : clkgen
generic map (fabtech, 25, 6, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clk200, open, open, open, open, cgi, cgo_ddr, open, open, open);
ddrc : entity work.ahb2mig_ztex generic map(
hindex => 4, haddr => 16#400#, hmask => CFG_MIG_HMASK,
pindex => 5, paddr => 5)
port map(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(5),
calib_done => lock,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem => clk200,
test_error => open
);
end generate;
noddr : if CFG_MIG_DDR2 = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- General purpose timer unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
-- NOTE:
-- GPIO pads are not instantiated here. If you want to use
-- GPIO then add a top-level port, update the UCF and
-- instantiate pads for the GPIO lines as is done in other
-- template designs.
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 9, paddr => 9, pmask => 16#fff#, pirq => 10,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => CFG_SPICTRL_ODMODE,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(9), spii, spio, slvsel);
miso_pad : iopad generic map (tech => padtech)
port map (sd_dat, spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (sd_cmd, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (sd_sck, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (sd_dat3, slvsel(0));
spii.spisel <= '1'; -- Master only
end generate spic;
nospic: if CFG_SPICTRL_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for ZTEX USB-FPGA Module 1.11",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
|
gpl-2.0
|
f26ad7f990c418e99627158b8acb30eb
| 0.534282 | 3.774303 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/esa/memoryctrl/memoryctrl.vhd
| 1 | 2,708 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Entity: memctrl
-- File: memctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory controller package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.memctrl.all;
package memoryctrl is
component mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end component;
end;
|
gpl-2.0
|
109ded447f1c5c8fc49a983967b5215d
| 0.555391 | 3.930334 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/xor00.vhd
| 1 | 1,344 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity xor00 is
port(
clkx: in std_logic ;
codopx: in std_logic_vector ( 3 downto 0 );
portAx: in std_logic_vector ( 7 downto 0 );
portBx: in std_logic_vector ( 7 downto 0 );
inFlagx: in std_logic ;
outx: out std_logic_vector ( 7 downto 0 );
outFlagx: out std_logic );
end;
architecture xor0 of xor00 is
begin
pxor: process(codopx, portAx, portBx)
begin
if(codopx = "1110") then
outx <= portAx xor portBx;
outFlagx <= '1';
else
outx <= (others => 'Z');
outFlagx <= 'Z';
end if;
end process pxor;
-- pxor: process(clkx, codopx, inFlagx)
-- --variable auxx: bit:='0';
-- begin
-- if (clkx = '1') then
----clkx'event and
-- if (codopx = "0001") then
-- if (inFlagx = '1') then
-- --if (auxx = '0') then
-- --auxx:='1';
-- outx <= portAx xor portBx;
-- outFlagx <= '1';
-- --end if;
-- else
-- outFlagx <= '0';
-- end if;
-- else
-- outx <= (others => 'Z');
-- outFlagx <= 'Z';
-- --auxx:='0';
-- end if;
-- end if;
-- end process pxor;
end xor0;
|
apache-2.0
|
4fa25d5c75cc2f8431f4b9a03af3a6b1
| 0.484375 | 2.896552 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml501/config.vhd
| 1 | 7,382 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex5;
constant CFG_MEMTECH : integer := virtex5;
constant CFG_PADTECH : integer := virtex5;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex5;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 8;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000030#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 0;
constant CFG_MIG_RANKS : integer := 1;
constant CFG_MIG_COLBITS : integer := 10;
constant CFG_MIG_ROWBITS : integer := 13;
constant CFG_MIG_BANKBITS: integer := 2;
constant CFG_MIG_HMASK : integer := 16#F00#;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (140);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (256);
constant CFG_DDR2SP_DELAY0 : integer := (15);
constant CFG_DDR2SP_DELAY1 : integer := (15);
constant CFG_DDR2SP_DELAY2 : integer := (15);
constant CFG_DDR2SP_DELAY3 : integer := (15);
constant CFG_DDR2SP_DELAY4 : integer := (15);
constant CFG_DDR2SP_DELAY5 : integer := (15);
constant CFG_DDR2SP_DELAY6 : integer := (15);
constant CFG_DDR2SP_DELAY7 : integer := (15);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0FFFE#;
constant CFG_GRGPIO_WIDTH : integer := (14);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- AMBA Wrapper for Xilinx System Monitor
constant CFG_GRSYSMON : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
18867f7af7f38b2cd899f71c0061acce
| 0.649824 | 3.550746 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-xc3sd-1800/leon3mp.vhd
| 1 | 25,006 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
reset_o1 : out std_ulogic;
reset_o2 : out std_ulogic;
clk_in : in std_ulogic;
clk_vga : in std_ulogic;
errorn : out std_ulogic;
-- PROM interface
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(7 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(23 downto 0);
-- pragma translate_on
-- DDR2 memory
ddr_clk : out std_logic_vector(1 downto 0);
ddr_clkb : out std_logic_vector(1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_we : out std_ulogic; -- write enable
ddr_ras : out std_ulogic; -- ras
ddr_cas : out std_ulogic; -- cas
ddr_dm : out std_logic_vector(3 downto 0); -- dm
ddr_dqs : inout std_logic_vector(3 downto 0); -- dqs
ddr_dqsn : inout std_logic_vector(3 downto 0); -- dqsn
ddr_ad : out std_logic_vector(12 downto 0); -- address
ddr_ba : out std_logic_vector(1 downto 0); -- bank address
ddr_dq : inout std_logic_vector(31 downto 0); -- data
ddr_odt : out std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
-- AHB Uart
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- Ethernet signals
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emdio : inout std_logic;
-- SVGA
vid_hsync : out std_logic;
vid_vsync : out std_logic;
vid_r : out std_logic_vector(3 downto 0);
vid_g : out std_logic_vector(3 downto 0);
vid_b : out std_logic_vector(3 downto 0);
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic;
-- Output signals to LEDs
led : out std_logic_vector(2 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal vgao : apbvga_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal lclk : std_ulogic;
signal lclk_vga : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of lclk_vga : signal is true;
attribute syn_preserve of lclk_vga : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 125000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
-- Glitch free reset that can be used for the Eth Phy and flash memory
reset_o1 <= rstn;
reset_o2 <= rstn;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk_pad : clkpad generic map (tech => padtech) port map (clk_in, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
led(2) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, rammask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "00";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc);
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (tech => padtech, width => 24)
port map (address, memo.address(23 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : iopadv generic map (tech => padtech, width => 24)
port map (testdata(23 downto 0), memo.data(23 downto 0),
memo.bdrive(1), memi.data(23 downto 0));
-- pragma translate_on
end generate;
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr2sp0 : if (CFG_DDR2SP /= 0) generate
ddrc0 : ddr2spa generic map ( fabtech => spartan3, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => BOARD_FREQ/1000, clkmul => 2, clkdiv => 2,
TRFC => CFG_DDR2SP_TRFC,
-- readdly must be 0 for simulation, but 1 for hardware
--pragma translate_off
readdly => 0,
--pragma translate_on
ahbfreq => CPU_FREQ/1000, col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE,
ddrbits => CFG_DDR2SP_DATAWIDTH, odten => 0)
port map ( cgo.clklock, rstn, lclk, clkm, vcc, lock, clkml, clkml, ahbsi, ahbso(4),
core_ddr_clk, core_ddr_clkb, ddr_clk_fb_out, ddr_clk_fb, core_ddr_cke,
core_ddr_csb, ddr_we, ddr_ras, ddr_cas, ddr_dm, ddr_dqs, ddr_dqsn,
core_ddr_ad, ddr_ba, ddr_dq, core_ddr_odt);
ddr_clk(1 downto 0) <= core_ddr_clk(1 downto 0);
ddr_clkb(1 downto 0) <= core_ddr_clkb(1 downto 0);
ddr_cke <= core_ddr_cke(0);
ddr_csb <= core_ddr_csb(0);
ddr_ad <= core_ddr_ad(12 downto 0);
ddr_odt <= core_ddr_odt(0);
end generate;
noddr : if (CFG_DDR2SP = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 7, hirq => 11, faddr => 16#e00#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(7), spmi, spmo);
-- MISO is shared with Flash data 0
spmi.miso <= memi.data(24);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
serrx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd1);
sertx_pad : outpad generic map (tech => padtech) port map (dsutx, txd1);
led(0) <= not rxd1;
led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-- There is no PS/2 port
apbo(5) <= apb_none;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 7, paddr => 7, pmask => 16#fff#, pirq => 11,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(7), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
-- MISO is shared with Flash data 0
spii.miso <= memi.data(24);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spio.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spio.sck);
slvsel_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0 generate
apbo(7) <= apb_none;
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, gnd);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, gnd);
slvsel_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, vcc);
end generate;
-----------------------------------------------------------------------
--- SVGA -------------------------------------------------------------
-----------------------------------------------------------------------
svga : if CFG_SVGA_ENABLE /= 0 generate
clk_vga_pad : clkpad generic map (tech => padtech) port map (clk_vga, lclk_vga);
svga0 : svgactrl
generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000,clk1 => 0, clk2 => 0, burstlen => 5)
port map(rstn, clkm, lclk_vga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (tech => padtech, width => 4)
port map (vid_r, vgao.video_out_r(7 downto 4));
video_out_g_pad : outpadv generic map (tech => padtech, width => 4)
port map (vid_g, vgao.video_out_g(7 downto 4));
video_out_b_pad : outpadv generic map (tech => padtech, width => 4)
port map (vid_b, vgao.video_out_b(7 downto 4));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Xilinx Spartan3A DSP 1800A board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
|
gpl-2.0
|
6f3577a64e49253130141c118cd791e4
| 0.533472 | 3.812471 | false | false | false | false |
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