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elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-nexys4ddr/leon3mp.vhd
| 1 | 36,012 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.ddrpkg.all;
--pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.BUFG;
use unisim.PLLE2_ADV;
use unisim.STARTUPE2;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
library testgrouppolito;
use testgrouppolito.dprc_pkg.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
sys_clk_i : in std_ulogic;
-- onBoard DDR2
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_ulogic;
ddr2_cas_n : out std_ulogic;
ddr2_we_n : out std_ulogic;
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
-- SPI
QspiCSn : out std_ulogic;
QspiDB : inout std_logic_vector(3 downto 0);
--pragma translate_off
QspiClk : out std_ulogic;
--pragma translate_on
-- 7 segment display
--seg : out std_logic_vector(6 downto 0);
--an : out std_logic_vector(7 downto 0);
-- LEDs
Led : out std_logic_vector(15 downto 0);
-- Switches
sw : in std_logic_vector(15 downto 0);
-- Buttons
btnCpuResetn : in std_ulogic;
btn : in std_logic_vector(4 downto 0);
-- VGA Connector
--vgaRed : out std_logic_vector(2 downto 0);
--vgaGreen : out std_logic_vector(2 downto 0);
--vgaBlue : out std_logic_vector(2 downto 1);
--Hsync : out std_ulogic;
--Vsync : out std_ulogic;
-- 12 pin connectors
--ja : inout std_logic_vector(7 downto 0);
--jb : inout std_logic_vector(7 downto 0);
--jc : inout std_logic_vector(7 downto 0);
--jd : inout std_logic_vector(7 downto 0);
-- SMSC ethernet PHY
eth_rstn : out std_ulogic;
eth_crsdv : in std_ulogic;
eth_refclk : out std_ulogic;
eth_txd : out std_logic_vector(1 downto 0);
eth_txen : out std_ulogic;
eth_rxd : in std_logic_vector(1 downto 0);
eth_rxerr : in std_ulogic;
eth_mdc : out std_ulogic;
eth_mdio : inout std_logic;
-- Pic USB-HID interface
--~ PS2KeyboardData : inout std_logic;
--~ PS2KeyboardClk : inout std_logic;
--~ PS2MouseData : inout std_logic;
--~ PS2MouseClk : inout std_logic;
--~ PicGpio : out std_logic_vector(1 downto 0);
-- USB-RS232 interface
uart_txd_in : in std_logic;
uart_rxd_out : out std_logic);
end;
architecture rtl of leon3mp is
component PLLE2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 5;
CLKFBOUT_PHASE : real := 0.0;
CLKIN1_PERIOD : real := 0.0;
CLKIN2_PERIOD : real := 0.0;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
STARTUP_WAIT : string := "FALSE"
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
component STARTUPE2
generic (
PROG_USR : string := "FALSE";
SIM_CCLK_FREQ : real := 0.0
);
port (
CFGCLK : out std_ulogic;
CFGMCLK : out std_ulogic;
EOS : out std_ulogic;
PREQ : out std_ulogic;
CLK : in std_ulogic;
GSR : in std_ulogic;
GTS : in std_ulogic;
KEYCLEARB : in std_ulogic;
PACK : in std_ulogic;
USRCCLKO : in std_ulogic;
USRCCLKTS : in std_ulogic;
USRDONEO : in std_ulogic;
USRDONETS : in std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component ahb2mig_7series_ddr2_dq16_ad13_ba3
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false);
port(
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_reset_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_i : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic);
end component ;
-- pragma translate_off
component ahbram_sim
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
fname : string := "ram.dat"
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component ;
-- pragma translate_on
signal CLKFBOUT : std_logic;
signal CLKFBIN : std_logic;
signal eth_pll_rst : std_logic;
signal eth_clk_nobuf : std_logic;
signal eth_clk90_nobuf : std_logic;
signal eth_clk : std_logic;
signal eth_clk90 : std_logic;
signal vcc : std_logic;
signal gnd : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo, cgo1 : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ndsuact : std_ulogic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal clkm : std_ulogic
-- pragma translate_off
:= '0'
-- pragma translate_on
;
signal clkm2x, clk200, clkfb, pllrst, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal btnCpuReset : std_logic;
signal lock, lock0 : std_logic;
signal clkinmig : std_logic;
signal ddr0_clkv : std_logic_vector(2 downto 0);
signal ddr0_clkbv : std_logic_vector(2 downto 0);
signal ddr0_cke : std_logic_vector(1 downto 0);
signal ddr0_csb : std_logic_vector(1 downto 0);
signal ddr0_odt : std_logic_vector(1 downto 0);
signal ddr0_addr : std_logic_vector(13 downto 0);
signal ddr0_clk_fb : std_logic;
signal clkref, calib_done, migrstn : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
----------------------------------------------------------------------
--- FIR component declaration --------------------------------------
----------------------------------------------------------------------
component fir_ahb_dma_apb is
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
technology : integer := virtex4);
port (
clk : in std_logic;
rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbin : in ahb_mst_in_type;
ahbout : out ahb_mst_out_type;
rm_reset: in std_logic
);
end component;
signal rm_reset : std_logic_vector(31 downto 0);
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
led(15 downto 6) <= (others =>'0'); -- unused leds off
btnCpuReset<= not btnCpuResetn;
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
pllrst <= not cgi.pllrst;
rst0 : rstgen generic map (acthigh => 1)
port map (btnCpuReset, clkm, lock, rstn, rstraw);
lock <= calib_done when CFG_MIG_7SERIES = 1 else cgo.clklock and lock0;
led(4) <= lock;
led(5) <= lock0;
rst1 : rstgen -- reset generator
generic map (acthigh => 1)
port map (btnCpuReset, clkm, lock, migrstn, open);
-- clock generator
clkgen_gen: if (CFG_MIG_7SERIES = 0) generate
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (sys_clk_i, gnd, clkm, open, clkm2x, open, open, cgi, cgo, open, open, open);
end generate;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_PRC*2,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
led(3) <= not dbgo(0).error;
led(2) <= not dsuo.active;
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ahbpf => CFG_AHBPF,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
--dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (uart_txd_in, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (uart_rxd_out, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- DDR2 Memory controller ------------------------------------------
----------------------------------------------------------------------
ddr2gen: if (CFG_DDR2SP = 1) and (CFG_MIG_7SERIES = 0) generate
ddrc : ddr2spa generic map (fabtech => fabtech, memtech => memtech,
hindex => 5, haddr => 16#400#, hmask => 16#F80#, ioaddr => 1, rstdel => 200, -- iomask generic default value
MHz => CPU_FREQ/1000, TRFC => CFG_DDR2SP_TRFC, clkmul => 12,
clkdiv => 6, col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE,
pwron => CFG_DDR2SP_INIT, ddrbits => CFG_DDR2SP_DATAWIDTH, raspipe => 0,
ahbfreq => CPU_FREQ/1000, readdly => 0, rskew => 0, oepol => 0,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7, -- cbdelayb0-3 generics not used in non-ft mode
numidelctrl => 1, norefclk => 1, -- dqsse, ahbbits, bigmem, nclk, scantest and octen default
nosync => CFG_DDR2SP_NOSYNC, eightbanks => 1, odten => 3, dqsgating => 0,
burstlen => 8, ft => CFG_DDR2SP_FTEN, ftbits => CFG_DDR2SP_FTWIDTH)
port map (
btnCpuResetn, rstn, clkm, clkm, clkm, lock0, clkml, clkml, ahbsi, ahbso(5),
ddr0_clkv, ddr0_clkbv, ddr0_clk_fb, ddr0_clk_fb,
ddr0_cke, ddr0_csb, ddr2_we_n, ddr2_ras_n, ddr2_cas_n,
ddr2_dm, ddr2_dqs_p, ddr2_dqs_n, ddr0_addr, ddr2_ba, ddr2_dq, ddr0_odt,open);
ddr2_addr <= ddr0_addr(12 downto 0);
ddr2_cke <= ddr0_cke(0 downto 0);
ddr2_cs_n <= ddr0_csb(0 downto 0);
ddr2_ck_p(0) <= ddr0_clkv(0);
ddr2_ck_n(0) <= ddr0_clkbv(0);
ddr2_odt <= ddr0_odt(0 downto 0);
end generate;
noddr2 : if (CFG_DDR2SP = 0) and (CFG_MIG_7SERIES = 0) generate lock0 <= '1'; end generate;
mig_gen : if (CFG_DDR2SP = 0) and (CFG_MIG_7SERIES = 1) generate
gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddrc : ahb2mig_7series_ddr2_dq16_ad13_ba3 generic map(
hindex => 5, haddr => 16#400#, hmask => 16#F80#, pindex => 5, paddr => 5,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL, SIMULATION => SIMULATION, USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL)
port map(
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_reset_n => open,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
ahbsi => ahbsi,
ahbso => ahbso(5),
apbi => apbi,
apbo => apbo(5),
calib_done => calib_done,
rst_n_syn => migrstn,
rst_n_async => cgo1.clklock,--rstraw,
clk_amba => clkm,
sys_clk_i => clkinmig,
clk_ref_i => clkref,
ui_clk => clkm, -- 70 MHz clk , DDR at 280 MHz (560 Mbps)
ui_clk_sync_rst => open);
clkgenmigref0 : clkgen
generic map (clktech, 16, 8, 0,CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (sys_clk_i, sys_clk_i, clkref, open, open, open, open, cgi, cgo, open, open, open);
clkgenmigin : clkgen
generic map (clktech, 14, 20, 0,CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (sys_clk_i, sys_clk_i, clkinmig, open, open, open, open, cgi, cgo1, open, open, open);
end generate gen_mig;
gen_mig_model : if (USE_MIG_INTERFACE_MODEL = true) generate
-- pragma translate_off
mig_ahbram : ahbram_sim
generic map (
hindex => 5,
haddr => 16#400#,
hmask => 16#F80#,
tech => 0,
kbytes => 1000,
pipe => 0,
maccsz => AHBDW,
fname => "ram.srec"
)
port map(
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(5)
);
ddr2_dq <= (others => 'Z');
ddr2_dqs_p <= (others => 'Z');
ddr2_dqs_n <= (others => 'Z');
ddr2_addr <= (others => '0');
ddr2_ba <= (others => '0');
ddr2_ras_n <= '0';
ddr2_cas_n <= '0';
ddr2_we_n <= '0';
ddr2_ck_p <= (others => '0');
ddr2_ck_n <= (others => '0');
ddr2_cke <= (others => '0');
ddr2_cs_n <= (others => '0');
ddr2_dm <= (others => '0');
ddr2_odt <= (others => '0');
--calib_done : out std_logic;
calib_done <= '1';
--ui_clk : out std_logic;
clkm <= not clkm after 13.333 ns;
--ui_clk_sync_rst : out std_logic
-- n/a
-- pragma translate_on
end generate gen_mig_model; end generate;
----------------------------------------------------------------------
--- SPI Memory controller -------------------------------------------
----------------------------------------------------------------------
spi_gen: if CFG_SPIMCTRL = 1 generate
-- OPTIONALY set the offset generic (only affect reads).
-- The first 4MB are used for loading the FPGA.
-- For dual ouptut: readcmd => 16#3B#, dualoutput => 1
spimctrl1 : spimctrl
generic map (hindex => 7, hirq => 7, faddr => 16#000#, fmask => 16#ff0#,
ioaddr => 16#700#, iomask => 16#fff#, spliten => CFG_SPLIT,
sdcard => CFG_SPIMCTRL_SDCARD, readcmd => CFG_SPIMCTRL_READCMD, dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT, scaler => CFG_SPIMCTRL_SCALER, altscaler => CFG_SPIMCTRL_ASCALER)
port map (rstn, clkm, ahbsi, ahbso(7), spmi, spmo);
QspiDB(3) <= '1'; QspiDB(2) <= '1';
-- spi_bdr : iopad generic map (tech => padtech)
-- port map (QspiDB(0), spmo.mosi, spmo.mosioen, spmi.mosi);
spi_mosi_pad : outpad generic map (tech => padtech)
port map (QspiDB(0), spmo.mosi);
spi_miso_pad : inpad generic map (tech => padtech)
port map (QspiDB(1), spmi.miso);
spi_slvsel0_pad : outpad generic map (tech => padtech)
port map (QspiCSn, spmo.csn);
-- MACRO for assigning the SPI output clock
spicclk: STARTUPE2
port map (--CFGCLK => open, CFGMCLK => open, EOS => open, PREQ => open,
CLK => '0', GSR => '0', GTS => '0', KEYCLEARB => '0', PACK => '0',
USRCCLKO => spmo.sck, USRCCLKTS => '0', USRDONEO => '1', USRDONETS => '0' );
--pragma translate_off
QspiClk <= spmo.sck;
--pragma translate_on
end generate;
nospi: if CFG_SPIMCTRL = 0 generate
ahbso(7) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
-- serrx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd1);
-- sertx_pad : outpad generic map (tech => padtech) port map (dsutx, txd1);
-- led(0) <= not rxd1;
-- led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G, rmii => 1)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
eth_rstn<=rstn;
end generate;
etxc_pad : outpad generic map (tech => padtech)
port map (eth_refclk, eth_clk);
ethpads : if (CFG_GRETH = 1) generate
emdio_pad : iopad generic map (tech => padtech)
port map (eth_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
ethi.rmii_clk<=eth_clk90;
erxd_pad : inpadv generic map (tech => padtech, width => 2) --8
port map (eth_rxd, ethi.rxd(1 downto 0));
erxer_pad : inpad generic map (tech => padtech)
port map (eth_rxerr, ethi.rx_er);
erxcr_pad : inpad generic map (tech => padtech)
port map (eth_crsdv, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 2)
port map (eth_txd, etho.txd(1 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (eth_txen, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (eth_mdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- DYNAMIC PARTIAL RECONFIGURATION ---------------------------------
-----------------------------------------------------------------------
prc : if CFG_PRC = 1 generate
p1 : dprc generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH, pindex => 14, paddr => 14, clk_sel => 1,
technology => CFG_FABTECH, crc_en => CFG_CRC_EN, words_block => CFG_WORDS_BLOCK, fifo_dcm_inst => CFG_DCM_FIFO, fifo_depth => CFG_DPR_FIFO)
port map(rstn => rstn, clkm => clkm, clkraw => '0', clk100 => sys_clk_i, ahbmi => ahbmi, ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH),
apbi => apbi, apbo => apbo(14), rm_reset => rm_reset);
--------------------------------------------------------------------
-- FIR component instantiation (for dprc demo) -------------------
--------------------------------------------------------------------
fir_ex : FIR_AHB_DMA_APB
generic map (hindex=>CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_PRC, pindex=>13, paddr=>13,
pmask=>16#fff#, technology =>CFG_FABTECH)
port map (rstn=>rstn, clk=>clkm, apbi=>apbi, apbo=>apbo(13), ahbin=>ahbmi,
ahbout=>ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_PRC), rm_reset => rm_reset(0));
end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_PRC*2+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Digilent NEXYS 4 DDR board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
-----------------------------------------------------------------------
--- Ethernet Clock Generation ---------------------------------------
-----------------------------------------------------------------------
ethclk : if CFG_GRETH = 1 generate
-- 50 MHz clock for output
bufgclk0 : BUFG port map (I => eth_clk_nobuf, O => eth_clk);
-- 50 MHz with +90 deg phase for Rx GRETH
bufgclk45 : BUFG port map (I => eth_clk90_nobuf, O => eth_clk90);
CLKFBIN <= CLKFBOUT;
eth_pll_rst <= not cgi.pllrst;
PLLE2_ADV_inst : PLLE2_ADV generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 8, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => 1000000.0/real(100000.0),
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => 16,
CLKOUT1_DIVIDE => 16,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 90.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => eth_clk_nobuf,
CLKOUT1 => eth_clk90_nobuf,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => open,
DRDY => open,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => open,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => sys_clk_i,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => eth_pll_rst,
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN
);
end generate;
end rtl;
|
gpl-2.0
|
9ef5cac69734a8d181677927f8c00704
| 0.517078 | 3.663106 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/gencomp/tech.in.vhd
| 2 | 356 |
-- Technology and synthesis options
constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
constant CFG_MEMTECH : integer := CFG_RAM_TECH;
constant CFG_PADTECH : integer := CFG_PAD_TECH;
constant CFG_TRANSTECH : integer := CFG_TRANS_TECH;
constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
|
gpl-2.0
|
aa04889ab4601183d8c4530b3449f8af
| 0.707865 | 3.490196 | false | true | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/srmmu/mmu.vhd
| 1 | 21,298 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: MMU
-- File: mmu.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: Leon3 MMU top level entity
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmu is
generic (
tech : integer range 0 to NTECH := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
mmupgsz : integer range 0 to 5 := 0;
scantest : integer := 0;
ramcbits : integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
mmudci : in mmudc_in_type;
mmudco : out mmudc_out_type;
mmuici : in mmuic_in_type;
mmuico : out mmuic_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end mmu;
architecture rtl of mmu is
constant MMUCTX_BITS : integer := M_CTX_SZ;
constant M_TLB_TYPE : integer range 0 to 1 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(1,2)); -- eather split or combined
constant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
constant M_ENT_I : integer range 2 to 64 := itlbnum; -- icache tlb entries: number
constant M_ENT_ILOG : integer := log2(M_ENT_I); -- icache tlb entries: address bits
constant M_ENT_D : integer range 2 to 64 := dtlbnum; -- dcache tlb entries: number
constant M_ENT_DLOG : integer := log2(M_ENT_D); -- dcache tlb entries: address bits
constant M_ENT_C : integer range 2 to 64 := M_ENT_I; -- i/dcache tlb entries: number
constant M_ENT_CLOG : integer := M_ENT_ILOG; -- i/dcache tlb entries: address bits
type mmu_op is record
trans_op : std_logic;
flush_op : std_logic;
diag_op : std_logic;
end record;
constant mmu_op_none : mmu_op := ('0', '0', '0');
type mmu_cmbpctrl is record
tlbowner : mmu_idcache;
tlbactive : std_logic;
op : mmu_op;
end record;
constant mmu_cmbpctrl_none : mmu_cmbpctrl := (id_icache, '0', mmu_op_none);
type mmu_rtype is record
cmb_s1 : mmu_cmbpctrl;
cmb_s2 : mmu_cmbpctrl;
splt_is1 : mmu_cmbpctrl;
splt_is2 : mmu_cmbpctrl;
splt_ds1 : mmu_cmbpctrl;
splt_ds2 : mmu_cmbpctrl;
twactive : std_logic; -- split tlb
twowner : mmu_idcache; -- split tlb
flush : std_logic;
mmctrl2 : mmctrl_type2;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
constant RRES : mmu_rtype := (
cmb_s1 => mmu_cmbpctrl_none,
cmb_s2 => mmu_cmbpctrl_none,
splt_is1 => mmu_cmbpctrl_none,
splt_is2 => mmu_cmbpctrl_none,
splt_ds1 => mmu_cmbpctrl_none,
splt_ds2 => mmu_cmbpctrl_none,
twactive => '0',
twowner => id_icache,
flush => '0',
mmctrl2 => mmctrl2_zero);
signal r, c : mmu_rtype;
-- tlb
component mmutlb
generic (
tech : integer range 0 to NTECH := 0;
entries : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
mmupgsz : integer range 0 to 5 := 0;
scantest : integer := 0;
ramcbits : integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
tlbi : in mmutlb_in_type;
tlbo : out mmutlb_out_type;
two : in mmutw_out_type;
twi : out mmutw_in_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end component;
signal tlbi_a0 : mmutlb_in_type;
signal tlbi_a1 : mmutlb_in_type;
signal tlbo_a0 : mmutlb_out_type;
signal tlbo_a1 : mmutlb_out_type;
signal twi_a : mmutwi_a(1 downto 0);
signal two_a : mmutwo_a(1 downto 0);
-- table walk
component mmutw
generic (
mmupgsz : integer range 0 to 5 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mmctrl1 : in mmctrl_type1;
twi : in mmutw_in_type;
two : out mmutw_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type
);
end component;
signal twi : mmutw_in_type;
signal two : mmutw_out_type;
signal mmctrl1 : mmctrl_type1;
begin
syncrregs : if not ASYNC_RESET generate
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
end if;
end if;
end process p1;
end generate;
asyncrregs : if ASYNC_RESET generate
p1: process (clk, rst)
begin
if rst = '0' then
r <= RRES;
elsif rising_edge(clk) then
r <= c;
end if;
end process p1;
end generate;
p0: process (rst, r, mmudci, mmuici, mcmmo, tlbo_a0, tlbo_a1, tlbi_a0, tlbi_a1, two_a, twi_a, two)
variable cmbtlbin : mmuidc_data_in_type;
variable cmbtlbout : mmutlb_out_type;
variable spltitlbin : mmuidc_data_in_type;
variable spltdtlbin : mmuidc_data_in_type;
variable spltitlbout : mmutlb_out_type;
variable spltdtlbout : mmutlb_out_type;
variable mmuico_transdata : mmuidc_data_out_type;
variable mmudco_transdata : mmuidc_data_out_type;
variable mmuico_grant : std_logic;
variable mmudco_grant : std_logic;
variable v : mmu_rtype;
variable twiv : mmutw_in_type;
variable twod, twoi : mmutw_out_type;
variable fault : mmutlbfault_out_type;
variable wbtransdata : mmuidc_data_out_type;
variable fs : mmctrl_fs_type;
variable fa : std_logic_vector(VA_I_SZ-1 downto 0);
begin
v := r;
wbtransdata.finish := '0';
wbtransdata.data := (others => '0');
wbtransdata.cache := '0';
wbtransdata.accexc := '0';
if (M_TLB_TYPE = 0) and (M_TLB_FASTWRITE /= 0) then
wbtransdata := tlbo_a1.wbtransdata;
end if;
cmbtlbin.data := (others => '0');
cmbtlbin.su := '0';
cmbtlbin.read := '0';
cmbtlbin.isid := id_dcache;
cmbtlbout.transdata.finish := '0';
cmbtlbout.transdata.data := (others => '0');
cmbtlbout.transdata.cache := '0';
cmbtlbout.transdata.accexc := '0';
cmbtlbout.fault.fault_pro := '0';
cmbtlbout.fault.fault_pri := '0';
cmbtlbout.fault.fault_access := '0';
cmbtlbout.fault.fault_mexc := '0';
cmbtlbout.fault.fault_trans := '0';
cmbtlbout.fault.fault_inv := '0';
cmbtlbout.fault.fault_lvl := (others => '0');
cmbtlbout.fault.fault_su := '0';
cmbtlbout.fault.fault_read := '0';
cmbtlbout.fault.fault_isid := id_dcache;
cmbtlbout.fault.fault_addr := (others => '0');
cmbtlbout.nexttrans := '0';
cmbtlbout.s1finished := '0';
mmuico_transdata.finish := '0';
mmuico_transdata.data := (others => '0');
mmuico_transdata.cache := '0';
mmuico_transdata.accexc := '0';
mmudco_transdata.finish := '0';
mmudco_transdata.data := (others => '0');
mmudco_transdata.cache := '0';
mmudco_transdata.accexc := '0';
mmuico_grant := '0';
mmudco_grant := '0';
twiv.walk_op_ur := '0';
twiv.areq_ur := '0';
twiv.data := (others => '0');
twiv.adata := (others => '0');
twiv.aaddr := (others => '0');
twod.finish := '0';
twod.data := (others => '0');
twod.addr := (others => '0');
twod.lvl := (others => '0');
twod.fault_mexc := '0';
twod.fault_trans := '0';
twod.fault_inv := '0';
twod.fault_lvl := (others => '0');
twoi.finish := '0';
twoi.data := (others => '0');
twoi.addr := (others => '0');
twoi.lvl := (others => '0');
twoi.fault_mexc := '0';
twoi.fault_trans := '0';
twoi.fault_inv := '0';
twoi.fault_lvl := (others => '0');
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
fault.fault_lvl := (others => '0');
fault.fault_su := '0';
fault.fault_read := '0';
fault.fault_isid := id_dcache;
fault.fault_addr := (others => '0');
fs.ow := '0';
fs.fav := '0';
fs.ft := (others => '0');
fs.at_ls := '0';
fs.at_id := '0';
fs.at_su := '0';
fs.l := (others => '0');
fs.ebe := (others => '0');
fa := (others => '0');
if M_TLB_TYPE = 0 then
spltitlbout := tlbo_a0;
spltdtlbout := tlbo_a1;
twod := two; twoi := two;
twod.finish := '0'; twoi.finish := '0';
spltdtlbin := mmudci.transdata;
spltitlbin := mmuici.transdata;
mmudco_transdata := spltdtlbout.transdata;
mmuico_transdata := spltitlbout.transdata;
-- d-tlb
if ((not r.splt_ds1.tlbactive) or spltdtlbout.s1finished) = '1' then
v.splt_ds1.tlbactive := '0';
v.splt_ds1.op.trans_op := '0';
v.splt_ds1.op.flush_op := '0';
if mmudci.trans_op = '1' then
mmudco_grant := '1';
v.splt_ds1.tlbactive := '1';
v.splt_ds1.op.trans_op := '1';
elsif mmudci.flush_op = '1' then
v.flush := '1';
mmudco_grant := '1';
v.splt_ds1.tlbactive := '1';
v.splt_ds1.op.flush_op := '1';
end if;
end if;
-- i-tlb
if ((not r.splt_is1.tlbactive) or spltitlbout.s1finished) = '1' then
v.splt_is1.tlbactive := '0';
v.splt_is1.op.trans_op := '0';
v.splt_is1.op.flush_op := '0';
if v.flush = '1' then
v.flush := '0';
v.splt_is1.tlbactive := '1';
v.splt_is1.op.flush_op := '1';
elsif mmuici.trans_op = '1' then
mmuico_grant := '1';
v.splt_is1.tlbactive := '1';
v.splt_is1.op.trans_op := '1';
end if;
end if;
if spltitlbout.transdata.finish = '1' and (r.splt_is2.op.flush_op = '0') then
fault := spltitlbout.fault;
end if;
if spltdtlbout.transdata.finish = '1' and (r.splt_is2.op.flush_op = '0') then
if (spltdtlbout.fault.fault_mexc or
spltdtlbout.fault.fault_trans or
spltdtlbout.fault.fault_inv or
spltdtlbout.fault.fault_pro or
spltdtlbout.fault.fault_pri or
spltdtlbout.fault.fault_access) = '1' then
fault := spltdtlbout.fault; -- overwrite icache fault
end if;
end if;
if spltitlbout.s1finished = '1' then
v.splt_is2 := r.splt_is1;
end if;
if spltdtlbout.s1finished = '1' then
v.splt_ds2 := r.splt_ds1;
end if;
if ( r.splt_is2.op.flush_op ) = '1' then
mmuico_transdata.finish := '0';
end if;
-- share tw
if two.finish = '1' then
v.twactive := '0';
end if;
if r.twowner = id_icache then
twiv := twi_a(0);
twoi.finish := two.finish;
else
twiv := twi_a(1);
twod.finish := two.finish;
end if;
if (v.twactive) = '0' then
if (twi_a(1).areq_ur or twi_a(1).walk_op_ur) = '1' then
v.twactive := '1';
v.twowner := id_dcache;
elsif (twi_a(0).areq_ur or twi_a(0).walk_op_ur) = '1' then
v.twactive := '1';
v.twowner := id_icache;
end if;
end if;
else
--# combined i/d cache: 1 tlb, 1 tw
-- share one tlb among i and d cache
cmbtlbout := tlbo_a0;
mmuico_grant := '0'; mmudco_grant := '0';
mmuico_transdata.finish := '0'; mmudco_transdata.finish := '0';
twiv := twi_a(0);
twod := two; twoi := two;
twod.finish := '0'; twoi.finish := '0';
-- twod.finish := two.finish;
twoi.finish := two.finish;
if ((not v.cmb_s1.tlbactive) or cmbtlbout.s1finished) = '1' then
v.cmb_s1.tlbactive := '0';
v.cmb_s1.op.trans_op := '0';
v.cmb_s1.op.flush_op := '0';
if (mmudci.trans_op or mmudci.flush_op or mmuici.trans_op) = '1' then
v.cmb_s1.tlbactive := '1';
end if;
if mmuici.trans_op = '1' then
mmuico_grant := '1';
v.cmb_s1.tlbowner := id_icache;
v.cmb_s1.op.trans_op := '1';
elsif mmudci.trans_op = '1' then
mmudco_grant := '1';
v.cmb_s1.tlbowner := id_dcache;
v.cmb_s1.op.trans_op := '1';
elsif mmudci.flush_op = '1' then
mmudco_grant := '1';
v.cmb_s1.tlbowner := id_dcache;
v.cmb_s1.op.flush_op := '1';
end if;
end if;
if (r.cmb_s1.tlbactive and not r.cmb_s2.tlbactive) = '1' then
end if;
if cmbtlbout.s1finished = '1' then
v.cmb_s2 := r.cmb_s1;
end if;
if r.cmb_s1.tlbowner = id_dcache then
cmbtlbin := mmudci.transdata;
else
cmbtlbin := mmuici.transdata;
end if;
if r.cmb_s2.tlbowner = id_dcache then
mmudco_transdata := cmbtlbout.transdata;
else
mmuico_transdata := cmbtlbout.transdata;
end if;
if cmbtlbout.transdata.finish = '1' and (r.cmb_s2.op.flush_op = '0') then
fault := cmbtlbout.fault;
end if;
end if;
-- # fault status register
if (mmudci.fsread) = '1' then
v.mmctrl2.valid := '0'; v.mmctrl2.fs.fav := '0';
end if;
-- SRMMU Fault Priorities
-- Pri Error
-------------------------
-- 1 Internal error
-- 2 Translation error
-- 3 Invalid address error
-- 4 Privilege violation error
-- 5 Protection error
-- 6 Access bus error
if (fault.fault_mexc) = '1' then
fs.ft := FS_FT_TRANS;
elsif (fault.fault_trans) = '1' then
fs.ft := FS_FT_TRANS;
elsif (fault.fault_inv) = '1' then
fs.ft := FS_FT_INV;
elsif (fault.fault_pri) = '1' then
fs.ft := FS_FT_PRI;
elsif (fault.fault_pro) = '1' then
fs.ft := FS_FT_PRO;
elsif (fault.fault_access) = '1' then
fs.ft := FS_FT_BUS;
else
fs.ft := FS_FT_NONE;
end if;
fs.ow := '0';
fs.l := fault.fault_lvl;
if fault.fault_isid = id_dcache then
fs.at_id := '0';
else
fs.at_id := '1';
end if;
fs.at_su := fault.fault_su;
fs.at_ls := not fault.fault_read;
fs.fav := '1';
fs.ebe := (others => '0');
fa := fault.fault_addr(VA_I_U downto VA_I_D);
if (fault.fault_mexc or
fault.fault_trans or
fault.fault_inv or
fault.fault_pro or
fault.fault_pri or
fault.fault_access) = '1' then
--# priority
--
if v.mmctrl2.valid = '1'then
if (fault.fault_mexc) = '1' then
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
else
-- An instruction or data access fault may not overwrite a
-- translation table access fault.
if (r.mmctrl2.fs.ft /= FS_FT_TRANS) then
if fault.fault_isid = id_dcache then
-- dcache, overwrite bit is cleared
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
else
-- icache
-- an inst access fault may not overwrite a data access fault:
if (not r.mmctrl2.fs.at_id) = '0' then
fs.ow := '1';
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
end if;
end if;
end if;
end if;
else
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
v.mmctrl2.valid := '1';
end if;
if (fault.fault_isid) = id_dcache then
mmudco_transdata.accexc := '1';
else
mmuico_transdata.accexc := '1';
end if;
end if;
-- # reset
if (not ASYNC_RESET) and ( not RESET_ALL ) and ( rst = '0' ) then
if M_TLB_TYPE = 0 then
v.splt_is1.tlbactive := RRES.splt_is1.tlbactive;
v.splt_is2.tlbactive := RRES.splt_is2.tlbactive;
v.splt_ds1.tlbactive := RRES.splt_ds1.tlbactive;
v.splt_ds2.tlbactive := RRES.splt_ds2.tlbactive;
v.splt_is1.op.trans_op := RRES.splt_is1.op.trans_op;
v.splt_is2.op.trans_op := RRES.splt_is2.op.trans_op;
v.splt_ds1.op.trans_op := RRES.splt_ds1.op.trans_op;
v.splt_ds2.op.trans_op := RRES.splt_ds2.op.trans_op;
v.splt_is1.op.flush_op := RRES.splt_is1.op.flush_op;
v.splt_is2.op.flush_op := RRES.splt_is2.op.flush_op;
v.splt_ds1.op.flush_op := RRES.splt_ds1.op.flush_op;
v.splt_ds2.op.flush_op := RRES.splt_ds2.op.flush_op;
else
v.cmb_s1.tlbactive := RRES.cmb_s1.tlbactive;
v.cmb_s2.tlbactive := RRES.cmb_s2.tlbactive;
v.cmb_s1.op.trans_op := RRES.cmb_s1.op.trans_op;
v.cmb_s2.op.trans_op := RRES.cmb_s2.op.trans_op;
v.cmb_s1.op.flush_op := RRES.cmb_s1.op.flush_op;
v.cmb_s2.op.flush_op := RRES.cmb_s2.op.flush_op;
end if;
v.flush := RRES.flush;
v.mmctrl2.valid := RRES.mmctrl2.valid;
v.twactive := RRES.twactive;
v.twowner := RRES.twowner;
end if;
-- drive signals
if M_TLB_TYPE = 0 then
tlbi_a0.trans_op <= r.splt_is1.op.trans_op;
tlbi_a0.flush_op <= r.splt_is1.op.flush_op;
tlbi_a0.transdata <= spltitlbin;
tlbi_a0.s2valid <= r.splt_is2.tlbactive;
tlbi_a0.mmctrl1 <= mmudci.mmctrl1;
tlbi_a0.wb_op <= '0';
tlbi_a1.trans_op <= r.splt_ds1.op.trans_op;
tlbi_a1.flush_op <= r.splt_ds1.op.flush_op;
tlbi_a1.transdata <= spltdtlbin;
tlbi_a1.s2valid <= r.splt_ds2.tlbactive;
tlbi_a1.mmctrl1 <= mmudci.mmctrl1;
tlbi_a1.wb_op <= mmudci.wb_op;
else
tlbi_a0.trans_op <= r.cmb_s1.op.trans_op;
tlbi_a0.flush_op <= r.cmb_s1.op.flush_op;
tlbi_a0.transdata <= cmbtlbin;
tlbi_a0.s2valid <= r.cmb_s2.tlbactive;
tlbi_a0.mmctrl1 <= mmudci.mmctrl1;
tlbi_a0.wb_op <= '0';
end if;
mmudco.transdata <= mmudco_transdata;
mmuico.transdata <= mmuico_transdata;
mmudco.grant <= mmudco_grant;
mmuico.grant <= mmuico_grant;
mmuico.tlbmiss <= twi_a(0).tlbmiss;
mmudco.mmctrl2 <= r.mmctrl2;
mmudco.wbtransdata <= wbtransdata;
twi <= twiv;
two_a(0) <= twoi;
two_a(1) <= twod;
mmctrl1 <= mmudci.mmctrl1;
c <= v;
end process p0;
tlbcomb0: if M_TLB_TYPE = 1 generate
-- i/d tlb
ctlb0 : mmutlb
generic map ( tech, M_ENT_C, 0, tlb_rep, mmupgsz, scantest, ramcbits )
port map (rst, clk, tlbi_a0, tlbo_a0, two_a(0), twi_a(0), testin
);
mmudco.tlbmiss <= twi_a(0).tlbmiss;
end generate tlbcomb0;
tlbsplit0: if M_TLB_TYPE = 0 generate
-- i tlb
itlb0 : mmutlb
generic map ( tech, M_ENT_I, 0, tlb_rep, mmupgsz, scantest, ramcbits )
port map (rst, clk, tlbi_a0, tlbo_a0, two_a(0), twi_a(0), testin
);
-- d tlb
dtlb0 : mmutlb
generic map ( tech, M_ENT_D, tlb_type, tlb_rep, mmupgsz, scantest, ramcbits )
port map (rst, clk, tlbi_a1, tlbo_a1, two_a(1), twi_a(1), testin
);
mmudco.tlbmiss <= twi_a(1).tlbmiss;
end generate tlbsplit0;
-- table walk component
tw0 : mmutw
generic map ( mmupgsz )
port map (rst, clk, mmctrl1, twi, two, mcmmo, mcmmi);
-- pragma translate_off
chk : process
begin
assert not ((M_TLB_TYPE = 1) and (M_TLB_FASTWRITE /= 0)) report
"Fast writebuffer only supported for combined cache"
severity failure;
wait;
end process;
-- pragma translate_on
end rtl;
|
gpl-2.0
|
df5229c16ba4aef234e7b54f5d0d6323
| 0.547751 | 3.229906 | false | false | false | false |
BOT-Man-JL/BUPT-Projects
|
2-2-Digital-Logic/Main.vhd
| 1 | 1,698 |
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Entity Main Is
Port (
clock: In std_logic;
input: In std_logic;
out0: Out std_logic_vector (6 downto 0);
out1: Out std_logic_vector (3 downto 0);
out2: Out std_logic_vector (3 downto 0);
out3: Out std_logic_vector (3 downto 0);
out4: Out std_logic_vector (3 downto 0);
out5: Out std_logic_vector (3 downto 0)
);
End Entity;
Architecture fMain Of Main Is
Component Control
Port (
clk_i: In std_logic;
clr_o: Out std_logic;
enable_o: Out std_logic;
blink_o: Out std_logic
);
End Component;
Component Counter
Port (
clk_i: In std_logic;
clr_i: In std_logic;
enable_i: In std_logic;
counting_o: Out std_logic_vector (23 downto 0)
);
End Component;
Component Display
Port (
counting_i: In std_logic_vector (23 downto 0);
blink_i: In std_logic;
out0_o: Out std_logic_vector (6 downto 0);
out1_o: Out std_logic_vector (3 downto 0);
out2_o: Out std_logic_vector (3 downto 0);
out3_o: Out std_logic_vector (3 downto 0);
out4_o: Out std_logic_vector (3 downto 0);
out5_o: Out std_logic_vector (3 downto 0)
);
End Component;
Signal g_clr: std_logic;
Signal g_enable: std_logic;
Signal g_blink: std_logic;
Signal g_counting: std_logic_vector (23 downto 0);
Begin
c1: Control Port Map
(
clk_i => clock,
clr_o => g_clr,
enable_o => g_enable,
blink_o => g_blink
);
c2: Counter Port Map
(
clk_i => input,
clr_i => g_clr,
enable_i => g_enable,
counting_o => g_counting
);
c3: Display Port Map
(
counting_i => g_counting,
blink_i => g_blink,
out0_o => out0,
out1_o => out1,
out2_o => out2,
out3_o => out3,
out4_o => out4,
out5_o => out5
);
End Architecture;
|
gpl-3.0
|
259341921fa8e112a89d096904de972b
| 0.661955 | 2.486091 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica01_FuncionesBasicas/ejercicio.vhd
| 1 | 1,885 |
library ieee;
use ieee.std_logic_1164.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
-- Primer dip-switch permite seleccionar la función a realizar
-- Función | Código
-- AND | 000
-- OR | 001
-- NOT | 010
-- XOR | 011
-- NAND | 100
-- NOR | 101
-- XNOR | 110
-- Entidad
entity Prac01 is
port(
seleccion1: in std_logic;
seleccion2: in std_logic;
seleccion3: in std_logic;
entrada1: in std_logic;
entrada2: in std_logic;
salida: out std_logic);
-- Loc = Location
attribute loc: string;
attribute loc of seleccion1: signal is "p125";
attribute loc of seleccion2: signal is "p124";
attribute loc of seleccion3: signal is "p123";
attribute loc of entrada1: signal is "p116";
attribute loc of entrada2: signal is "p115";
attribute loc of salida: signal is "p24";
end;
-- Arquitectura
architecture APrac01 of Prac01 is
begin
process(seleccion1, seleccion2, seleccion3, entrada1, entrada2) -- El proceso se ejecuta cada que uno de los parámetros cambia de valor
variable seleccion: std_logic_vector(2 downto 0); -- MSB a LSB porque estoy usando DOWNTO
begin
seleccion := seleccion1 & seleccion2 & seleccion3; -- Concatenando los valores de los interruptores de selección
case seleccion is
when "000" =>
salida <= entrada1 AND entrada2;
when "001" =>
salida <= entrada1 OR entrada2;
when "010" =>
salida <= NOT entrada1;
when "011" =>
salida <= entrada1 XOR entrada2;
when "100" =>
salida <= entrada1 NAND entrada2;
when "101" =>
salida <= entrada1 NOR entrada2;
when "110" =>
salida <= entrada1 XNOR entrada2;
when others =>
salida <= '1';
end case;
end process;
end APrac01;
|
apache-2.0
|
ab2b7af51d7f0135497a9a6d05dc9e0a
| 0.623936 | 3.686275 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-c5ekit/pllsim.vhd
| 1 | 1,479 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
entity syspll1 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
locked : out std_logic -- export
);
end;
architecture sim of syspll1 is
begin
p: process
variable vclk: std_logic := '0';
begin
outclk_0 <= vclk;
wait for 5.555 ns;
vclk := not vclk;
end process;
locked <= '0', '1' after 1 us;
end;
|
gpl-2.0
|
06020edf9e3cdab12b6bae5842dbc591
| 0.63286 | 3.861619 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-nuhorizons-3s1500/config.vhd
| 1 | 6,124 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#00f3#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#00002B#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 1;
constant CFG_CANIO : integer := 16#C00#;
constant CFG_CANIRQ : integer := (13);
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fffe#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
83952d753bbc8d3f7a91b701f6db7fb1
| 0.643697 | 3.606596 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep3c25-eek/testbench.vhd
| 1 | 14,752 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Altera Cyclone-III Embedded Evaluation Kit LEON3 Demonstration design test
-- Copyright (C) 2007 Jiri Gaisler, Gaisler Research
-- Adapted for EEK by Jan Andersson, Gaisler Research
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-3 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal ssram_cen : std_logic;
signal ssram_wen : std_logic;
signal ssram_bw : std_logic_vector (0 to 3);
signal ssram_oen : std_ulogic;
signal ssram_clk : std_ulogic;
signal ssram_adscn : std_ulogic;
signal ssram_adsp_n : std_ulogic;
signal ssram_adv_n : std_ulogic;
signal datazz : std_logic_vector(3 downto 0);
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clkin : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
-- Connections over HSMC connector
-- LCD touch panel display
signal hc_vd : std_logic;
signal hc_hd : std_logic;
signal hc_den : std_logic;
signal hc_nclk : std_logic;
signal hc_lcd_data : std_logic_vector(7 downto 0);
signal hc_grest : std_logic;
signal hc_scen : std_logic;
signal hc_sda : std_logic;
signal hc_adc_penirq_n : std_logic;
signal hc_adc_dout : std_logic;
signal hc_adc_busy : std_logic;
signal hc_adc_din : std_logic;
signal hc_adc_dclk : std_logic;
signal hc_adc_cs_n : std_logic;
-- Shared by video decoder and audio codec
signal hc_i2c_sclk : std_logic;
signal hc_i2c_sdat : std_logic;
-- Video decoder
signal hc_td_d : std_logic_vector(7 downto 0);
signal hc_td_hs : std_logic;
signal hc_td_vs : std_logic;
signal hc_td_27mhz : std_logic;
signal hc_td_reset : std_logic;
-- Audio codec
signal hc_aud_adclrck : std_logic;
signal hc_aud_adcdat : std_logic;
signal hc_aud_daclrck : std_logic;
signal hc_aud_dacdat : std_logic;
signal hc_aud_bclk : std_logic;
signal hc_aud_xck : std_logic;
-- SD card
signal hc_sd_dat : std_logic;
signal hc_sd_dat3 : std_logic;
signal hc_sd_cmd : std_logic;
signal hc_sd_clk : std_logic;
-- Ethernet PHY
signal hc_tx_d : std_logic_vector(3 downto 0);
signal hc_rx_d : std_logic_vector(3 downto 0);
signal hc_tx_clk : std_logic;
signal hc_rx_clk : std_logic;
signal hc_tx_en : std_logic;
signal hc_rx_dv : std_logic;
signal hc_rx_crs : std_logic;
signal hc_rx_err : std_logic;
signal hc_rx_col : std_logic;
signal hc_mdio : std_logic;
signal hc_mdc : std_logic;
signal hc_eth_reset_n : std_logic;
-- RX232 (console/debug UART)
signal hc_uart_rxd : std_logic;
signal hc_uart_txd : std_logic;
-- PS/2
signal hc_ps2_dat : std_logic;
signal hc_ps2_clk : std_logic;
-- VGA/DAC
signal hc_vga_data : std_logic_vector(9 downto 0);
signal hc_vga_clock : std_ulogic;
signal hc_vga_hs : std_ulogic;
signal hc_vga_vs : std_ulogic;
signal hc_vga_blank : std_ulogic;
signal hc_vga_sync : std_ulogic;
-- I2C EEPROM
signal hc_id_i2cscl : std_logic;
signal hc_id_i2cdat : std_logic;
-- Ethernet PHY sim model
signal phy_tx_er : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal hc_tx_dt : std_logic_vector(7 downto 0) := (others => '0');
signal hc_rx_dt : std_logic_vector(7 downto 0) := (others => '0');
constant lresp : boolean := false;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
ddr_clkin <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; hc_uart_rxd <= '1';
address(0) <= '0';
-- ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow )
port map (rst, clk, error,
address(25 downto 1), data, romsn, oen, writen, open,
ssram_cen, ssram_wen, ssram_bw, ssram_oen,
ssram_clk, ssram_adscn, iosn,
-- DDR
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
-- DSU
dsubren, dsuact,
-- I/O port
gpio,
-- LCD
hc_vd, hc_hd, hc_den, hc_nclk, hc_lcd_data, hc_grest, hc_scen,
hc_sda, hc_adc_penirq_n, hc_adc_dout, hc_adc_busy, hc_adc_din,
hc_adc_dclk, hc_adc_cs_n,
-- Shared by video decoder and audio codec
hc_i2c_sclk, hc_i2c_sdat,
-- Video decoder
hc_td_d, hc_td_hs, hc_td_vs, hc_td_27mhz, hc_td_reset,
-- Audio codec
hc_aud_adclrck, hc_aud_adcdat, hc_aud_daclrck, hc_aud_dacdat,
hc_aud_bclk, hc_aud_xck,
-- SD card
hc_sd_dat, hc_sd_dat3, hc_sd_cmd, hc_sd_clk,
-- Ethernet PHY
hc_tx_d, hc_rx_d, hc_tx_clk, hc_rx_clk, hc_tx_en, hc_rx_dv, hc_rx_crs,
hc_rx_err, hc_rx_col, hc_mdio, hc_mdc, hc_eth_reset_n,
-- RX232 (console/debug UART)
hc_uart_rxd, hc_uart_txd,
-- PS/2
hc_ps2_dat, hc_ps2_clk,
-- VGA/DAC
hc_vga_data, hc_vga_clock, hc_vga_hs, hc_vga_vs, hc_vga_blank, hc_vga_sync,
-- I2C EEPROM
hc_id_i2cscl, hc_id_i2cdat
);
-- I2C bus pull-ups
hc_i2c_sclk <= 'H'; hc_i2c_sdat <= 'H';
hc_id_i2cscl <= 'H'; hc_id_i2cdat <= 'H';
-- SD card signals
spiflashmod : spi_flash
generic map (ftype => 3, debug => 0, dummybyte => 0)
port map (sck => hc_sd_clk, di => hc_sd_cmd, do => hc_sd_dat, csn => hc_sd_dat3);
hc_sd_dat <= 'Z'; hc_sd_cmd <= 'Z';
-- hc_sd_dat <= hc_sd_cmd; -- Loopback
-- ddr0 : mt46v16m16
-- generic map (index => -1, fname => sdramfile)
-- port map(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
ddr0 : ddrram
generic map(width => 16, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 1)
port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
datazz <= "HHHH";
ssram_adsp_n <= '1'; ssram_adv_n <= '1';
ssram0 : cy7c1380d generic map (fname => sramfile)
port map(
ioDq(35 downto 32) => datazz, ioDq(31 downto 0) => data,
iAddr => address(20 downto 2), iMode => gnd,
inGW => vcc, inBWE => ssram_wen, inADV => ssram_adv_n,
inADSP => ssram_adsp_n, inADSC => ssram_adscn,
iClk => ssram_clk,
inBwa => ssram_bw(3), inBwb => ssram_bw(2),
inBwc => ssram_bw(1), inBwd => ssram_bw(0),
inOE => ssram_oen, inCE1 => ssram_cen,
iCE2 => vcc, inCE3 => gnd, iZz => gnd);
-- 16 bit prom
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31 downto 16),
gnd, gnd, romsn, writen, oen);
-- Ethernet PHY
hc_mdio <= 'H';
phy_tx_er <= '0';
phy_gtx_clk <= '0';
hc_tx_dt(3 downto 0) <= hc_tx_d;
hc_rx_d <= hc_rx_dt(3 downto 0);
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 1)
port map(hc_eth_reset_n, hc_mdio, hc_tx_clk, hc_rx_clk, hc_rx_dt, hc_rx_dv,
hc_rx_err, hc_rx_col, hc_rx_crs, hc_tx_dt, hc_tx_en, phy_tx_er, hc_mdc, phy_gtx_clk);
-- I2C memory
i0: i2c_slave_model
port map (hc_id_i2cscl, hc_id_i2cdat);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
gpl-2.0
|
e383c5440f01cdc04cd9d0e1b498b874
| 0.566635 | 3.004481 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/stratixiii/ddr_phy_stratixiii.vhd
| 4 | 22,934 |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- STRATIXIII DDR2 PHY ----------------------------------------------
------------------------------------------------------------------
entity stratixiii_ddr2_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0;
tech : integer := stratix3; odten : integer := 0; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- ddr address
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0);
oct : in std_logic
);
end;
architecture rtl of stratixiii_ddr2_phy is
component apll is
generic (
freq : integer := 200;
mult : integer := 8;
div : integer := 5;
rskew : integer := 0
);
port(
areset : in std_logic := '0';
inclk0 : in std_logic := '0';
phasestep : in std_logic := '0';
phaseupdown : in std_logic := '0';
scanclk : in std_logic := '1';
c0 : out std_logic ;
c1 : out std_logic ;
c2 : out std_logic ;
c3 : out std_logic ;
c4 : out std_logic ;
locked : out std_logic;
phasedone : out std_logic
);
end component;
component aclkout is
port(
clk : in std_logic;
ddr_clk : out std_logic;
ddr_clkn: out std_logic
);
end component;
component actrlout is
generic(
power_up : string := "high"
);
port(
clk : in std_logic;
i : in std_logic;
o : out std_logic
);
end component;
--component adqsout is
--port(
-- clk : in std_logic; -- clk90
-- dqs : in std_logic;
-- dqs_oe : in std_logic;
-- dqs_oct : in std_logic; -- gnd = disable
-- dqs_pad : out std_logic; -- DQS pad
-- dqsn_pad : out std_logic -- DQSN pad
--);
--end component;
--component adqsin is
--port(
-- dqs_pad : in std_logic; -- DQS pad
-- dqsn_pad : in std_logic; -- DQSN pad
-- dqs : out std_logic
--);
--end component;
component admout is
port(
clk : in std_logic; -- clk0
dm_h : in std_logic;
dm_l : in std_logic;
dm_pad : out std_logic -- DQ pad
);
end component;
--component adqin is
--port(
-- clk : in std_logic;
-- dq_pad : in std_logic; -- DQ pad
-- dq_h : out std_logic;
-- dq_l : out std_logic;
-- config_clk : in std_logic;
-- config_clken : in std_logic;
-- config_datain : in std_logic;
-- config_update : in std_logic
--);
--end component;
--component adqout is
--port(
-- clk : in std_logic; -- clk0
-- clk_oct : in std_logic; -- clk90
-- dq_h : in std_logic;
-- dq_l : in std_logic;
-- dq_oe : in std_logic;
-- dq_oct : in std_logic; -- gnd = disable
-- dq_pad : out std_logic -- DQ pad
--);
--end component;
component dq_dqs_inst is
port(
bidir_dq_input_data_in : in std_logic_vector (7 downto 0);
bidir_dq_input_data_out_high : out std_logic_vector (7 downto 0);
bidir_dq_input_data_out_low : out std_logic_vector (7 downto 0);
bidir_dq_io_config_ena : in std_logic_vector (7 downto 0);
bidir_dq_oct_in : in std_logic_vector (7 downto 0);
bidir_dq_oct_out : out std_logic_vector (7 downto 0);
bidir_dq_oe_in : in std_logic_vector (7 downto 0);
bidir_dq_oe_out : out std_logic_vector (7 downto 0);
bidir_dq_output_data_in_high : in std_logic_vector (7 downto 0);
bidir_dq_output_data_in_low : in std_logic_vector (7 downto 0);
bidir_dq_output_data_out : out std_logic_vector (7 downto 0);
bidir_dq_sreset : in std_logic_vector (7 downto 0);
config_clk : in std_logic;
config_datain : in std_logic;
config_update : in std_logic;
dq_input_reg_clk : in std_logic;
dq_output_reg_clk : in std_logic;
dqs_areset : in std_logic;
dqs_oct_in : in std_logic;
dqs_oct_out : out std_logic;
dqs_oe_in : in std_logic;
dqs_oe_out : out std_logic;
dqs_output_data_in_high : in std_logic;
dqs_output_data_in_low : in std_logic;
dqs_output_data_out : out std_logic;
dqs_output_reg_clk : in std_logic;
dqsn_oct_in : in std_logic;
dqsn_oct_out : out std_logic;
dqsn_oe_in : in std_logic;
dqsn_oe_out : out std_logic;
oct_reg_clk : in std_logic
);
end component;
component bidir_dq_iobuf_inst is
port(
datain : in std_logic_vector (7 downto 0);
dyn_term_ctrl : in std_logic_vector (7 downto 0);
oe : in std_logic_vector (7 downto 0);
dataio : inout std_logic_vector (7 downto 0);
dataout : out std_logic_vector (7 downto 0)
);
end component;
component bidir_dqs_iobuf_inst is
port(
datain : in std_logic_vector (0 downto 0);
dyn_term_ctrl : in std_logic_vector (0 downto 0);
dyn_term_ctrl_b : in std_logic_vector (0 downto 0);
oe : in std_logic_vector (0 downto 0);
oe_b : in std_logic_vector (0 downto 0);
dataio : inout std_logic_vector (0 downto 0);
dataio_b : inout std_logic_vector (0 downto 0);
dataout : out std_logic_vector (0 downto 0)
);
end component;
signal reset : std_logic;
signal vcc, gnd, oe : std_ulogic;
signal locked, vlockl, lockl : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r, rclk : std_ulogic;
signal ckel, ckel2 : std_logic_vector(1 downto 0);
signal odtl : std_logic_vector(1 downto 0);
signal dqsin, dqsin_reg : std_logic_vector (7 downto 0); -- ddr dqs
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal dqsoenr : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal delayrst : std_logic_vector(3 downto 0);
signal phasedone : std_logic;
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
-- altdq_dqs
signal bidir_dq_input_data_in : std_logic_vector (dbits-1 downto 0) := (others => '0');
signal bidir_dq_io_config_ena : std_logic_vector (dbits-1 downto 0) := (others => '1');
signal bidir_dq_oct_in : std_logic_vector (dbits-1 downto 0) := (others => '0');
signal bidir_dq_oct_out : std_logic_vector (dbits-1 downto 0);
signal bidir_dq_oe_in : std_logic_vector (dbits-1 downto 0) := (others => '0');
signal bidir_dq_oe_out : std_logic_vector (dbits-1 downto 0);
signal bidir_dq_output_data_out : std_logic_vector (dbits-1 downto 0);
signal bidir_dq_sreset : std_logic_vector (dbits-1 downto 0) := (others => '0');
signal dqs_areset : std_logic_vector (dbits/8-1 downto 0);
signal dqs_oct_out : std_logic_vector (dbits/8-1 downto 0);
signal dqs_oe_out : std_logic_vector (dbits/8-1 downto 0);
signal dqs_output_data_out : std_logic_vector (dbits/8-1 downto 0);
signal dqsn_oct_out : std_logic_vector (dbits/8-1 downto 0);
signal dqsn_oe_out : std_logic_vector (dbits/8-1 downto 0);
type phy_r_type is record
delay : std_logic_vector(3 downto 0);
count : std_logic_vector(3 downto 0);
update : std_logic;
sdata : std_logic;
enable : std_logic;
update_delay : std_logic;
end record;
type phy_r_type_arr is array (7 downto 0) of phy_r_type;
signal r,rin : phy_r_type_arr;
signal rp : std_logic_vector(8 downto 0);
signal rlockl : std_logic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
attribute syn_keep of dqsoenr : signal is true;
attribute syn_preserve of dqsoenr : signal is true;
attribute syn_keep of dqsin_reg : signal is true;
attribute syn_preserve of dqsin_reg : signal is true;
begin
-----------------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------------
oe <= not oen;
vcc <= '1'; gnd <= '0';
reset <= not rst;
-- Optional DDR clock multiplication
pll0 : apll
generic map(
freq => MHz,
mult => clk_mul,
div => clk_div,
rskew => rskew
)
port map(
areset => reset,
inclk0 => clk,
phasestep => rp(3),--rp(1),
phaseupdown => rp(8),--rp(3),
scanclk => clk0r,
c0 => clk0r,
c1 => clk90r,
c2 => open, --clk180r,
c3 => open, --clk270r,
c4 => rclk,
locked => lockl,
phasedone => phasedone
);
clk180r <= not clk0r;
clk270r <= not clk90r;
clkout <= clk0r;
-----------------------------------------------------------------------------------
-- Lock delay
-----------------------------------------------------------------------------------
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if rlockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
cnt(0) := dqsin_reg(7) or dqsin_reg(6) or dqsin_reg(5) or dqsin_reg(4) or -- dummy use of dqsin
dqsin_reg(3) or dqsin_reg(2) or dqsin_reg(1) or dqsin_reg(0);
-- pragma translate_off
cnt(0) := '0';
-- pragma translate_on
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if rlockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-----------------------------------------------------------------------------------
-- Generate external DDR clock
-----------------------------------------------------------------------------------
ddrclocks : for i in 0 to 2 generate
ddrclk_pad : aclkout port map(clk => clk90r, ddr_clk => ddr_clk(i), ddr_clkn => ddr_clkb(i));
end generate;
-----------------------------------------------------------------------------------
-- DDR single-edge control signals
-----------------------------------------------------------------------------------
-- ODT pads
odtgen : for i in 0 to 1 generate
odtl(i) <= locked and odt(i);
ddr_odt_pad : actrlout generic map(power_up => "low")
port map(clk =>clk180r , i => odtl(i), o => ddr_odt(i));
end generate;
-- CSN and CKE
ddrbanks : for i in 0 to 1 generate
ddr_csn_pad : actrlout port map(clk =>clk180r , i => csn(i), o => ddr_csb(i));
ckel(i) <= cke(i) and locked;
ddr_cke_pad : actrlout generic map(power_up => "low")
port map(clk =>clk0r , i => ckel(i), o => ddr_cke(i));
end generate;
-- RAS
ddr_rasn_pad : actrlout port map(clk =>clk180r , i => rasn, o => ddr_rasb);
-- CAS
ddr_casn_pad : actrlout port map(clk =>clk180r , i => casn, o => ddr_casb);
-- WEN
ddr_wen_pad : actrlout port map(clk =>clk180r , i => wen, o => ddr_web);
-- BA
bagen : for i in 0 to 1+eightbanks generate
ddr_ba_pad : actrlout port map(clk =>clk180r , i => ba(i), o => ddr_ba(i));
end generate;
-- ADDRESS
dagen : for i in 0 to 13 generate
ddr_ad_pad : actrlout port map(clk =>clk180r , i => addr(i), o => ddr_ad(i));
end generate;
-----------------------------------------------------------------------------------
-- DQM generation
-----------------------------------------------------------------------------------
dmgen : for i in 0 to dbits/8-1 generate
ddr_dm_pad : admout port map(
clk => clk0r, -- clk0
dm_h => dm(i+dbits/8),
dm_l => dm(i),
dm_pad => ddr_dm(i) -- DQ pad
);
end generate;
-----------------------------------------------------------------------------------
-- DQS generation (and DQ)
-----------------------------------------------------------------------------------
dqsgen : for i in 0 to dbits/8-1 generate
doen : process(clk180r)
begin
if reset = '1' then dqsoenr(i) <= '1';
elsif rising_edge(clk180r) then dqsoenr(i) <= dqsoen; end if;
end process;
dsqreg : process(clk180r)
begin if rising_edge(clk180r) then dqsn(i) <= oe; end if; end process;
-- dqs_out_pad : adqsout port map(
-- clk => clk90r, -- clk90
-- dqs => dqsn(i),
-- dqs_oe => dqsoenr(i),
-- dqs_oct => odt(0), --oct_reg(i),--gnd, -- gnd = disable
-- dqs_pad => ddr_dqs(i), -- DQS pad
-- dqsn_pad => ddr_dqsn(i) -- DQSN pad
-- );
--
-- dqs_in_pad : adqsin port map(
-- dqs_pad => ddr_dqs(i),
-- dqsn_pad => ddr_dqsn(i),
-- dqs => dqsin(i)
-- );
-- -- Dummy procces to sample dqsin
-- process(clk0r)
-- begin
-- if rising_edge(clk0r) then
-- dqsin_reg(i) <= dqsin(i);
-- end if;
-- end process;
-- altdq_dqs
bidir_dq_io_config_ena((i)*8+7 downto 0+(i)*8) <= (others => r(i).enable);
bidir_dq_oct_in((i)*8+7 downto 0+(i)*8) <= (others => oct);
bidir_dq_oe_in((i)*8+7 downto 0+(i)*8) <= (others => oen);
bidir_dq_sreset((i)*8+7 downto 0+(i)*8) <= (others => reset);
dqs_areset(i) <= reset;
dq_dqs : dq_dqs_inst port map(
bidir_dq_input_data_in => bidir_dq_input_data_in((i)*8+7 downto 0+(i)*8),
bidir_dq_input_data_out_high => dqin((i)*8+7 downto 0+(i)*8),
bidir_dq_input_data_out_low => dqin((i)*8+7+dbits downto 0+(i)*8+dbits),
bidir_dq_io_config_ena => bidir_dq_io_config_ena((i)*8+7 downto 0+(i)*8),
bidir_dq_oct_in => bidir_dq_oct_in((i)*8+7 downto 0+(i)*8),
bidir_dq_oct_out => bidir_dq_oct_out((i)*8+7 downto 0+(i)*8),
bidir_dq_oe_in => bidir_dq_oe_in((i)*8+7 downto 0+(i)*8),
bidir_dq_oe_out => bidir_dq_oe_out((i)*8+7 downto 0+(i)*8),
bidir_dq_output_data_in_high => dqout((i)*8+7+dbits downto 0+(i)*8+dbits),
bidir_dq_output_data_in_low => dqout((i)*8+7 downto 0+(i)*8),
bidir_dq_output_data_out => bidir_dq_output_data_out((i)*8+7 downto 0+(i)*8),
bidir_dq_sreset => bidir_dq_sreset((i)*8+7 downto 0+(i)*8),
config_clk => clk0r,
config_datain => r(i).sdata,
config_update => r(i).update_delay,
dq_input_reg_clk => rclk,
dq_output_reg_clk => clk0r,
dqs_areset => dqs_areset(i),
dqs_oct_in => oct,
dqs_oct_out => dqs_oct_out(i),
dqs_oe_in => dqsoenr(i),
dqs_oe_out => dqs_oe_out(i),
dqs_output_data_in_high => dqsn(i),
dqs_output_data_in_low => gnd,
dqs_output_data_out => dqs_output_data_out(i),
dqs_output_reg_clk => clk90r,
dqsn_oct_in => oct,
dqsn_oct_out => dqsn_oct_out(i),
dqsn_oe_in => dqsoenr(i),
dqsn_oe_out => dqsn_oe_out(i),
oct_reg_clk => clk90r
);
dq_pad : bidir_dq_iobuf_inst PORT map(
datain => bidir_dq_output_data_out((i)*8+7 downto 0+(i)*8),
dyn_term_ctrl => bidir_dq_oct_out((i)*8+7 downto 0+(i)*8),
oe => bidir_dq_oe_out((i)*8+7 downto 0+(i)*8),
dataio => ddr_dq((i)*8+7 downto (i)*8+0),
dataout => bidir_dq_input_data_in((i)*8+7 downto 0+(i)*8)
);
dqs_pad : bidir_dqs_iobuf_inst PORT map(
datain(0) => dqs_output_data_out(i),
dyn_term_ctrl(0) => dqs_oct_out(i),
dyn_term_ctrl_b(0) => dqsn_oct_out(i),
oe(0) => dqs_oe_out(i),
oe_b(0) => dqsn_oe_out(i),
dataio(0) => ddr_dqs(i),
dataio_b(0) => ddr_dqsn(i),
dataout(0) => dqsin(i)
);
-- Dummy procces to sample dqsin
process(clk0r)
begin
if rising_edge(clk0r) then
dqsin_reg(i) <= dqsin(i);
end if;
end process;
end generate;
-----------------------------------------------------------------------------------
-- Data bus
-----------------------------------------------------------------------------------
-- ddgen : for i in 0 to dbits-1 generate
-- -- DQ Input
-- dq_in_pad : adqin port map(
-- clk => rclk,--clk0r,
-- dq_pad => ddr_dq(i), -- DQ pad
-- dq_h => dqin(i), --dqinl(i),
-- dq_l => dqin(i+dbits),--dqin(i),
-- config_clk => clk0r,
-- config_clken => r(i/8).enable,--io_config_clkena,
-- config_datain => r(i/8).sdata,--io_config_datain,
-- config_update => r(i/8).update_delay--io_config_update
-- );
-- --dinq1 : process (clk0r)
-- --begin if rising_edge(clk0r) then dqin(i+dbits) <= dqinl(i); end if; end process;
--
-- -- DQ Output
-- dq_out_pad : adqout port map(
-- clk => clk0r, -- clk0
-- clk_oct => clk90r, -- clk90
-- dq_h => dqout(i+dbits),
-- dq_l => dqout(i),
-- dq_oe => oen,
-- dq_oct => odt(0),--gnd, -- gnd = disable
-- dq_pad => ddr_dq(i) -- DQ pad
-- );
-- end generate;
-----------------------------------------------------------------------------------
-- Delay control
-----------------------------------------------------------------------------------
delay_control : for i in 0 to dbits/8-1 generate
process(r(i),cal_en(i), cal_inc(i), delayrst(3))
variable v : phy_r_type;
variable data : std_logic_vector(0 to 3);
begin
v := r(i);
data := r(i).delay;
v.update_delay := '0';
if cal_en(i) = '1' then
if cal_inc(i) = '1' then
v.delay := r(i).delay + 1;
else
v.delay := r(i).delay - 1;
end if;
v.update := '1';
v.count := (others => '0');
end if;
if r(i).update = '1' then
v.enable := '1';
v.sdata := '0';
if r(i).count <= "1011" then
v.count := r(i).count + 1;
end if;
if r(i).count <= "0011" then
v.sdata := data(conv_integer(r(i).count));
end if;
if r(i).count = "1011" then
v.update_delay := '1';
v.enable := '0';
v.update := '0';
end if;
end if;
if delayrst(3) = '0' then
v.delay := (others => '0');
v.count := (others => '0');
v.update := '0';
v.enable := '0';
end if;
rin(i) <= v;
end process;
end generate;
process(clk0r)
begin
if locked = '0' then
delayrst <= (others => '0');
elsif rising_edge(clk0r) then
delayrst <= delayrst(2 downto 0) & '1';
r <= rin;
-- PLL phase config
-- Active puls is extended to be sampled vith scanclk = (ddr clock / 2)
--rp(0) <= cal_pll(0); rp(1) <= cal_pll(0) or rp(0);
rp(0) <= cal_pll(0); rp(1) <= rp(0); rp(2) <= rp(1); rp(3) <= cal_pll(0) or rp(0) or rp(1) or rp(2);
--rp(2) <= cal_pll(1); rp(3) <= cal_pll(1) or rp(2);
--rp(2) <= cal_pll(1); rp(4) <= cal_pll(1) or rp(2); rp(3) <= rp(4);
rp(4) <= cal_pll(1); rp(5) <= rp(4); rp(6) <= rp(5); rp(7) <= rp(6); rp(8) <= cal_pll(1) or rp(4) or rp(5) or rp(6) or rp(7);
end if;
end process;
process(lockl,clk0r)
begin
if lockl = '0' then
rlockl <= '0';
elsif rising_edge(clk0r) then
rlockl <= lockl;
end if;
end process;
end;
|
gpl-2.0
|
28b4a9a1275a084691c310f8e73dbb7d
| 0.484608 | 3.330526 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-asic/config.vhd
| 1 | 7,681 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := saed32;
constant CFG_MEMTECH : integer := saed32;
constant CFG_PADTECH : integer := saed32;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 1;
constant CFG_SCAN : integer := 1;
-- JTAG boundary-scan chain
constant CFG_BOUNDSCAN_EN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := saed32;
constant CFG_CLKMUL : integer := 2;
constant CFG_CLKDIV : integer := 2;
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (4);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 0;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 8;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (6);
constant CFG_SPICTRL_FIFO : integer := (4);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 1;
constant CFG_UART2_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (4);
constant CFG_GPT_SW : integer := (12);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 0;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FE#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
49f18c4431cc03c4df4694136c62a3d1
| 0.651868 | 3.61629 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gsi/ssram/functions.vhd
| 6 | 97,832 |
-----------------------------------------------------------
-- VHDL file for FUNCTIONs used in verilog2vhdl files
-- DO NOT MODIFY THIS FILE
-- Author : S.O
-- Date : March 14, 1995
-- Modification History --
-- 3/31/95 Added shift operations (S.O)
-- 4/6/95 Added arithmetic operations for std_logic_vectors (S.O)
-- 4/11/95 Added conversion functions
-- 10/5/95 added to_boolean conversions
-- 1/31/96 added funcs. for std_logic and std_logic
-- 2/28/96 added funcs. for TERNARY combinations
-- 4/18/96 added logical operations bet. std_logic_vector and integer/boolean
-- 7/9/96 modified all TERNARY functions with *ulogic* conditional
-----------------------------------------------------------
library ieee;
library GSI;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
package FUNCTIONS is
-- TYPE used in conversion function
TYPE direction is (LITTLE_ENDIAN, BIG_ENDIAN);
TYPE hex_digit IS ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A',
'B', 'C', 'D', 'E', 'F', 'a', 'b', 'c', 'd', 'e', 'f');
TYPE hex_number IS array (POSITIVE range <>) OF hex_digit;
TYPE hexstdlogic IS ARRAY (hex_digit'LOW TO hex_digit'HIGH) of std_logic_vector(3 DOWNTO 0);
-- This conversion table would not accept X or Z.
-- To convert a hex number with X or Z use to_stdlogicvector(hex : STRING).
--CONSTANT hex_to_stdlogic : hexstdlogic := (x"0", x"1", x"2", x"3", x"4", x"5",
-- x"6", x"7", x"8", x"9", x"A", x"B", x"C", x"D", x"E", x"F", x"A", x"B",
-- x"C", x"D", x"E", x"F");
-- Signals used for v2v
--SIGNAL v2v_std_logic : std_logic;
--SIGNAL v2v_sig_integer : integer;
--SIGNAL v2v_boolean : boolean;
--SIGNAL v2v_real : real;
-- FUNCTIONs for unary operations
FUNCTION U_AND(a : std_ulogic_vector) return std_ulogic;
FUNCTION U_AND(a : std_logic_vector) return std_logic;
FUNCTION U_NAND(a : std_ulogic_vector) return std_ulogic;
FUNCTION U_NAND(a : std_logic_vector) return std_logic;
FUNCTION U_OR(a : std_ulogic_vector) return std_ulogic;
FUNCTION U_OR(a : std_logic_vector) return std_logic;
FUNCTION U_NOR(a : std_ulogic_vector) return std_ulogic;
FUNCTION U_NOR(a : std_logic_vector) return std_logic;
FUNCTION U_XOR(a : std_ulogic_vector) return std_ulogic;
FUNCTION U_XOR(a : std_logic_vector) return std_logic;
FUNCTION U_XNOR(a : std_ulogic_vector) return std_ulogic;
FUNCTION U_XNOR(a : std_logic_vector) return std_logic;
-- FUNCTIONs for ternary operations
FUNCTION TERNARY(a,b,c : boolean) return boolean;
FUNCTION TERNARY(a : boolean; b,c : std_ulogic) return std_ulogic;
FUNCTION TERNARY(a : boolean; b,c : std_ulogic_vector) return std_ulogic_vector;
FUNCTION TERNARY(a : boolean; b,c : std_logic_vector) return std_logic_vector;
--pragma synthesis_off
FUNCTION TERNARY(a : boolean; b,c : real) return real;
FUNCTION TERNARY(a : boolean; b,c : time) return time;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : integer) return integer;
FUNCTION TERNARY(a : integer; b,c : std_ulogic) return std_ulogic;
FUNCTION TERNARY(a : integer; b,c : std_ulogic_vector) return std_ulogic_vector;
FUNCTION TERNARY(a : integer; b,c : std_logic_vector) return std_logic_vector;
--pragma synthesis_off
FUNCTION TERNARY(a : integer; b,c : real) return real;
FUNCTION TERNARY(a : integer; b,c : time) return time;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : std_ulogic) return std_ulogic;
FUNCTION TERNARY(a : std_ulogic; b,c : integer) return integer;
FUNCTION TERNARY(a : std_ulogic; b,c : std_ulogic_vector) return std_ulogic_vector;
FUNCTION TERNARY(a : std_ulogic; b,c : std_logic_vector) return std_logic_vector;
--pragma synthesis_off
FUNCTION TERNARY(a : std_ulogic; b,c : real) return real;
FUNCTION TERNARY(a : std_ulogic; b,c : time) return time;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : std_ulogic_vector) return std_ulogic_vector;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : integer) return integer;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : std_ulogic) return std_ulogic;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : std_logic_vector) return std_logic_vector;
--pragma synthesis_off
FUNCTION TERNARY(a : std_ulogic_vector; b,c : real) return real;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : time) return time;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : std_logic_vector) return std_logic_vector;
FUNCTION TERNARY(a : std_logic_vector; b,c : integer) return integer;
FUNCTION TERNARY(a : std_logic_vector; b,c : std_ulogic) return std_ulogic;
FUNCTION TERNARY(a : std_logic_vector; b,c : std_ulogic_vector) return std_ulogic_vector;
--pragma synthesis_off
FUNCTION TERNARY(a : std_logic_vector; b,c : real) return real;
FUNCTION TERNARY(a : std_logic_vector; b,c : time) return time;
FUNCTION TERNARY(a,b,c : real) return real;
FUNCTION TERNARY(a : real; b,c : std_ulogic) return std_ulogic;
FUNCTION TERNARY(a : real; b,c : std_ulogic_vector) return std_ulogic_vector;
FUNCTION TERNARY(a : real; b,c : std_logic_vector) return std_logic_vector;
FUNCTION TERNARY(a : real; b,c : integer) return integer;
FUNCTION TERNARY(a : real; b,c : time) return time;
--pragma synthesis_on
-- functions for TERNARY combination
FUNCTION TERNARY(a : std_ulogic; b : std_logic_vector; c: std_ulogic) return
std_logic_vector;
FUNCTION TERNARY(a : std_ulogic; b : std_ulogic; c: std_logic_vector) return
std_logic_vector;
FUNCTION TERNARY(a : std_ulogic; b : integer; c: std_ulogic) return
integer;
FUNCTION TERNARY(a : std_ulogic; b : std_ulogic; c: integer) return
integer;
FUNCTION TERNARY(a : integer; b : integer; c: std_ulogic) return
integer;
FUNCTION TERNARY(a : integer; b : std_ulogic; c: integer) return
integer;
FUNCTION TERNARY(a : integer; b : std_logic_vector; c: std_ulogic) return
std_logic_vector;
FUNCTION TERNARY(a : integer; b : std_ulogic; c: std_logic_vector) return
std_logic_vector;
--end functions for TERNARY combination
-- FUNCTIONS for shift operations
FUNCTION "sll" ( l : std_logic_vector; r : integer) RETURN std_logic_vector;
FUNCTION "sll" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector;
FUNCTION "srl" ( l : std_logic_vector; r : integer) RETURN std_logic_vector;
FUNCTION "srl" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector;
FUNCTION "sla" ( l : std_logic_vector; r : integer) RETURN std_logic_vector;
FUNCTION "sla" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector;
FUNCTION "sra" ( l : std_logic_vector; r : integer) RETURN std_logic_vector;
FUNCTION "sra" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector;
FUNCTION "rol" ( l : std_logic_vector; r : integer) RETURN std_logic_vector;
FUNCTION "rol" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector;
FUNCTION "ror" ( l : std_logic_vector; r : integer) RETURN std_logic_vector;
FUNCTION "ror" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector;
-- FUNCTIONs for integer operations
FUNCTION "not" (l: integer) return integer;
FUNCTION "and" (l,r: integer) return integer;
FUNCTION "nand" (l,r: integer) return integer;
FUNCTION "or" (l,r: integer) return integer;
FUNCTION "nor" (l,r: integer) return integer;
FUNCTION "xor" (l,r: integer) return integer;
FUNCTION "xnor" (l,r: integer) return integer;
FUNCTION "sll" (l,r: integer) return integer;
FUNCTION "srl" (l,r: integer) return integer;
-- FUNCTIONs for std_logic/std_ulogic_vector/std_logic_vector operations
-- FUNCTIONs for combination of Boolean and ints
FUNCTION "=" ( l : Boolean; r : natural ) RETURN boolean;
FUNCTION "/=" ( l : Boolean; r : natural ) RETURN boolean;
FUNCTION "=" ( l : integer; r : std_logic_vector ) RETURN boolean;
FUNCTION "/=" ( l : integer; r : std_logic_vector ) RETURN boolean;
FUNCTION "<" ( l : integer; r : std_logic_vector ) RETURN boolean;
FUNCTION ">" ( l : integer; r : std_logic_vector ) RETURN boolean;
FUNCTION "<=" ( l : integer; r : std_logic_vector ) RETURN boolean;
FUNCTION ">=" ( l : integer; r : std_logic_vector ) RETURN boolean;
FUNCTION "=" ( l : std_logic_vector; r : integer ) RETURN boolean;
FUNCTION "/=" ( l : std_logic_vector; r : integer ) RETURN boolean;
FUNCTION "<" ( l : std_logic_vector; r : integer ) RETURN boolean;
FUNCTION ">" ( l : std_logic_vector; r : integer ) RETURN boolean;
FUNCTION "<=" ( l : std_logic_vector; r : integer ) RETURN boolean;
FUNCTION ">=" ( l : std_logic_vector; r : integer ) RETURN boolean;
--logical functions between std_logic_vector and integer, std_logic_vector and boolean
FUNCTION "and" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "nand" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "or" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "nor" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "xor" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "and" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "nand" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "or" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "nor" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "xor" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "and" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector;
FUNCTION "nand" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector;
FUNCTION "or" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector;
FUNCTION "nor" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector;
FUNCTION "xor" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector;
FUNCTION "and" ( l : boolean; r : std_logic_vector ) RETURN boolean;
FUNCTION "nand" ( l : boolean; r : std_logic_vector ) RETURN boolean;
FUNCTION "or" ( l : boolean; r : std_logic_vector ) RETURN boolean;
FUNCTION "nor" ( l : boolean; r : std_logic_vector ) RETURN boolean;
FUNCTION "xor" ( l : boolean; r : std_logic_vector ) RETURN boolean;
--logical functions between std_logic_vector and integer, std_logic_vector and boolean
-- Added functions for std_logic, integer
FUNCTION "=" ( l : std_logic; r : integer ) RETURN boolean;
FUNCTION "/=" ( l : std_logic; r : integer ) RETURN boolean;
FUNCTION "<" ( l : std_logic; r : integer ) RETURN boolean;
FUNCTION ">" ( l : std_logic; r : integer ) RETURN boolean;
FUNCTION "<=" ( l : std_logic; r : integer ) RETURN boolean;
FUNCTION ">=" ( l : std_logic; r : integer ) RETURN boolean;
-- Functions for std_logic, integer
--pragma synthesis_off
-- arithmetic operations for real and int and int and real
FUNCTION "+" ( l : real; r : integer ) RETURN real;
FUNCTION "-" ( l : real; r : integer ) RETURN real;
FUNCTION "/" ( l : real; r : integer ) RETURN real;
FUNCTION "*" ( l : real; r : integer ) RETURN real;
FUNCTION "+" ( l : integer; r : real ) RETURN real;
FUNCTION "-" ( l : integer; r : real ) RETURN real;
FUNCTION "/" ( l : integer; r : real ) RETURN real;
FUNCTION "*" ( l : integer; r : real ) RETURN real;
-- end arithmetic operations for real and int and int and real
FUNCTION "=" ( l : real; r : integer ) RETURN boolean;
FUNCTION "/=" ( l : real; r : integer ) RETURN boolean;
FUNCTION "<" ( l : real; r : integer ) RETURN boolean;
FUNCTION ">" ( l : real; r : integer ) RETURN boolean;
FUNCTION "<=" ( l : real; r : integer ) RETURN boolean;
FUNCTION ">=" ( l : real; r : integer ) RETURN boolean;
FUNCTION "=" ( l : integer; r : real ) RETURN boolean;
FUNCTION "/=" ( l : integer; r : real ) RETURN boolean;
FUNCTION "<" ( l : integer; r : real ) RETURN boolean;
FUNCTION ">" ( l : integer; r : real ) RETURN boolean;
FUNCTION "<=" ( l : integer; r : real ) RETURN boolean;
FUNCTION ">=" ( l : integer; r : real ) RETURN boolean;
--pragma synthesis_on
FUNCTION "+" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "-" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "*" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "/" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "REM" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "+" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "-" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "*" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "/" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "REM" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "&" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "&" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector;
-- need logical functions bet. std_logic_vector and std_logic
FUNCTION "and" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "nand" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "or" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "nor" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "xor" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
--FUNCTION "xnor" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "and" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "nand" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "or" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "nor" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "xor" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
--FUNCTION "xnor" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
-- end logical functions for std_logic_vector and std_logic
-- need arith functions bet std_logic and std_logic
-- used only when the int can be 0 or 1
-- need arithmetic functions bet. std_logic_vector and std_logic
FUNCTION "+" ( l : std_logic; r : std_logic ) RETURN std_logic;
FUNCTION "-" ( l : std_logic; r : std_logic ) RETURN std_logic;
FUNCTION "*" ( l : std_logic; r : std_logic ) RETURN std_logic;
FUNCTION "/" ( l : std_logic; r : std_logic ) RETURN std_logic;
FUNCTION "REM" ( l : std_logic; r : std_logic ) RETURN std_logic;
-- need arithmetic functions bet. std_logic_vector and std_logic
FUNCTION "+" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "-" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "*" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "/" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "REM" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
-- need arithmetic func. between std_logic and std_logic_vector, caveat, returns type of 'r'
FUNCTION "+" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "-" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "*" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "/" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "REM" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "+" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "-" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "*" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "/" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "REM" ( l : integer; r : std_logic_vector ) RETURN integer;
-- need arith. functions bet std_logic and integer
FUNCTION "+" ( l : std_logic; r : integer ) RETURN integer;
FUNCTION "-" ( l : std_logic; r : integer ) RETURN integer;
FUNCTION "*" ( l : std_logic; r : integer ) RETURN integer;
FUNCTION "/" ( l : std_logic; r : integer ) RETURN integer;
FUNCTION "REM" ( l : std_logic; r : integer ) RETURN integer;
FUNCTION "and" ( l : std_logic; r : integer ) RETURN std_logic;
FUNCTION "nand" ( l : std_logic; r : integer ) RETURN std_logic;
FUNCTION "or" ( l : std_logic; r : integer ) RETURN std_logic;
FUNCTION "nor" ( l : std_logic; r : integer ) RETURN std_logic;
FUNCTION "xor" ( l : std_logic; r : integer ) RETURN std_logic;
FUNCTION "&" ( l : std_logic; r : integer ) RETURN std_logic_vector;
FUNCTION "xnor" ( l : std_logic; r : integer ) RETURN std_logic;
FUNCTION "and" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "nand" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "or" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "nor" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "xor" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "&" ( l : integer; r : std_logic ) RETURN std_logic_vector;
FUNCTION "xnor" ( l : integer; r : std_logic ) RETURN integer;
-- need functions for operations between std_logic and integer
FUNCTION "+" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "-" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "*" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "/" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "REM" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "and" ( l : std_logic; r : boolean ) RETURN std_logic;
FUNCTION "nand" ( l : std_logic; r : boolean ) RETURN std_logic;
FUNCTION "or" ( l : std_logic; r : boolean ) RETURN std_logic;
FUNCTION "nor" ( l : std_logic; r : boolean ) RETURN std_logic;
FUNCTION "xor" ( l : std_logic; r : boolean ) RETURN std_logic;
FUNCTION "&" ( l : std_logic; r : boolean ) RETURN std_logic_vector;
FUNCTION "xnor" ( l : std_logic; r : boolean ) RETURN std_logic;
FUNCTION "and" ( l : boolean; r : std_logic ) RETURN boolean;
FUNCTION "nand" ( l : boolean; r : std_logic ) RETURN boolean;
FUNCTION "or" ( l : boolean; r : std_logic ) RETURN boolean;
FUNCTION "nor" ( l : boolean; r : std_logic ) RETURN boolean;
FUNCTION "xor" ( l : boolean; r : std_logic ) RETURN boolean;
FUNCTION "&" ( l : boolean; r : std_logic ) RETURN std_logic_vector;
FUNCTION "xnor" ( l : boolean; r : std_logic ) RETURN boolean;
FUNCTION "and" ( l : integer; r : boolean ) RETURN integer;
FUNCTION "nand" ( l : integer; r : boolean ) RETURN integer;
FUNCTION "or" ( l : integer; r : boolean ) RETURN integer;
FUNCTION "nor" ( l : integer; r : boolean ) RETURN integer;
FUNCTION "xor" ( l : integer; r : boolean ) RETURN integer;
FUNCTION "&" ( l : integer; r : boolean ) RETURN std_logic_vector;
FUNCTION "xnor" ( l : integer; r : boolean ) RETURN integer;
FUNCTION "and" ( l : boolean; r : integer ) RETURN boolean;
FUNCTION "nand" ( l : boolean; r : integer ) RETURN boolean;
FUNCTION "or" ( l : boolean; r : integer ) RETURN boolean;
FUNCTION "nor" ( l : boolean; r : integer ) RETURN boolean;
FUNCTION "xor" ( l : boolean; r : integer ) RETURN boolean;
FUNCTION "&" ( l : boolean; r : integer ) RETURN std_logic_vector;
FUNCTION "xnor" ( l : boolean; r : integer ) RETURN boolean;
-- Overloaded function for text output
FUNCTION to_bitvector ( a : bit ) RETURN bit_vector;
FUNCTION to_bitvector ( a : std_ulogic ) RETURN bit_vector;
FUNCTION to_bitvector ( a : integer ) RETURN bit_vector;
--Conversion functions
FUNCTION to_stdlogicvector(l : integer; size : natural; dir : direction := LITTLE_ENDIAN) RETURN std_logic_vector;
FUNCTION to_stdlogicvector(l : std_logic_vector) RETURN std_logic_vector;
FUNCTION to_stdlogicvector(l : std_logic_vector; size : natural;dir : direction := little_endian ) RETURN std_logic_vector;
FUNCTION to_stdlogicvector ( hex : STRING ) RETURN std_logic_vector;
FUNCTION to_stdlogicvector(l : std_logic; size : natural) RETURN std_logic_vector;
FUNCTION to_stdlogicvector(l : boolean; size : natural) RETURN std_logic_vector;
FUNCTION to_integer(l : std_logic_vector; dir : direction := little_endian) RETURN integer;
FUNCTION to_integer(l : integer) RETURN integer;
FUNCTION to_integer(l : std_logic) RETURN integer;
FUNCTION to_integer(l : boolean) RETURN integer;
-- functions for resolving ambiguity
FUNCTION v2v_to_integer(l : std_logic_vector; dir : direction := little_endian) RETURN integer;
FUNCTION v2v_to_integer(l : integer) RETURN integer;
FUNCTION v2v_to_integer(l : std_logic) RETURN integer;
FUNCTION v2v_to_integer(l : boolean) RETURN integer;
FUNCTION to_stdlogic(l : integer) RETURN std_logic;
FUNCTION to_stdlogic(l : Boolean) RETURN std_logic;
FUNCTION to_stdlogic(l : std_logic) RETURN std_logic;
FUNCTION to_stdlogic(l : std_logic_vector) RETURN std_logic;
--pragma synthesis_off
FUNCTION to_real(l : integer) RETURN real;
FUNCTION to_real (l : real) RETURN real;
--pragma synthesis_on
FUNCTION to_boolean(l : std_logic) RETURN boolean;
FUNCTION to_boolean(l : integer) RETURN boolean;
FUNCTION to_boolean(l : std_logic_vector) RETURN boolean;
FUNCTION to_boolean(l : boolean) RETURN boolean;
end FUNCTIONS;
library ieee;
library GSI;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library grlib;
--use grlib.stdlib.all;
Package body FUNCTIONS is
--============= Local Subprograms (from numeric_std.vhd)=====================
function MAX (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end MAX;
function MIN (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end MIN;
-- unary operations
TYPE stdlogic_boolean_table is array(std_ulogic, std_ulogic) of boolean;
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
FUNCTION U_AND(a : std_ulogic_vector) return std_ulogic is
VARIABLE result : std_ulogic := '1';
begin
FOR i in a'RANGE LOOP
result := result and a(i);
END LOOP;
return result;
end U_AND;
FUNCTION U_AND(a : std_logic_vector) return std_logic is
VARIABLE result : std_logic := '1';
begin
FOR i in a'RANGE LOOP
result := result and a(i);
END LOOP;
return result;
end U_AND;
FUNCTION U_NAND(a : std_ulogic_vector) return std_ulogic is
VARIABLE result : std_ulogic := '1';
begin
FOR i in a'RANGE LOOP
result := result and a(i);
END LOOP;
return not(result);
end U_NAND;
FUNCTION U_NAND(a : std_logic_vector) return std_logic is
VARIABLE result : std_logic := '1';
begin
FOR i in a'RANGE LOOP
result := result and a(i);
END LOOP;
return not(result);
end U_NAND;
FUNCTION U_OR(a : std_ulogic_vector) return std_ulogic is
VARIABLE result : std_ulogic := '0';
begin
FOR i in a'RANGE LOOP
result := result or a(i);
END LOOP;
return result;
end U_OR;
FUNCTION U_OR(a : std_logic_vector) return std_logic is
VARIABLE result : std_logic := '0';
begin
FOR i in a'RANGE LOOP
result := result or a(i);
END LOOP;
return result;
end U_OR;
FUNCTION U_NOR(a : std_ulogic_vector) return std_ulogic is
VARIABLE result : std_ulogic := '0';
begin
FOR i in a'RANGE LOOP
result := result or a(i);
END LOOP;
return not(result);
end U_NOR;
FUNCTION U_NOR(a : std_logic_vector) return std_logic is
VARIABLE result : std_logic := '0';
begin
FOR i in a'RANGE LOOP
result := result or a(i);
END LOOP;
return not(result);
end U_NOR;
FUNCTION U_XOR(a : std_ulogic_vector) return std_ulogic is
VARIABLE result : std_ulogic := '0';
begin
FOR i in a'RANGE LOOP
result := result xor a(i);
END LOOP;
return result;
end U_XOR;
FUNCTION U_XOR(a : std_logic_vector) return std_logic is
VARIABLE result : std_logic := '0';
begin
FOR i in a'RANGE LOOP
result := result xor a(i);
END LOOP;
return result;
end U_XOR;
FUNCTION U_XNOR(a : std_ulogic_vector) return std_ulogic is
VARIABLE result : std_ulogic := '0';
begin
FOR i in a'RANGE LOOP
result := result xor a(i);
END LOOP;
return not(result);
end U_XNOR;
FUNCTION U_XNOR(a : std_logic_vector) return std_logic is
VARIABLE result : std_logic := '0';
begin
FOR i in a'RANGE LOOP
result := result xor a(i);
END LOOP;
return not(result);
end U_XNOR;
-- ternary operations
FUNCTION TERNARY(a,b,c : boolean) return boolean IS
begin
IF a = TRUE THEN
RETURN b;
ELSE
RETURN c;
END IF;
end TERNARY;
---------------------------------------------------
FUNCTION TERNARY(a : boolean; b,c : std_ulogic) return std_ulogic IS
begin
IF a = TRUE THEN
RETURN b;
ELSE
RETURN c;
END IF;
end TERNARY;
---------------------------------------------------
FUNCTION TERNARY(a : boolean; b,c : std_ulogic_vector) return std_ulogic_vector IS
begin
IF a = TRUE THEN
RETURN b;
ELSE
RETURN c;
END IF;
end TERNARY;
---------------------------------------------------
FUNCTION TERNARY(a : boolean; b,c : std_logic_vector) return std_logic_vector IS
begin
IF a = TRUE THEN
RETURN b;
ELSE
RETURN c;
END IF;
end TERNARY;
--pragma synthesis_off
---------------------------------------------------
FUNCTION TERNARY(a : boolean; b,c : real) return real IS
begin
IF a = TRUE THEN
RETURN b;
ELSE
RETURN c;
END IF;
end TERNARY;
---------------------------------------------------
FUNCTION TERNARY(a : boolean; b,c : time) return time IS
begin
IF a = TRUE THEN
RETURN b;
ELSE
RETURN c;
END IF;
end TERNARY;
--pragma synthesis_on
---------------------------------------------------
FUNCTION TERNARY(a,b,c : integer) return integer is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : integer; b,c : std_ulogic) return std_ulogic is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : integer; b,c : std_ulogic_vector) return std_ulogic_vector is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : integer; b,c : std_logic_vector) return std_logic_vector is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
--pragma synthesis_off
FUNCTION TERNARY(a : integer; b,c : real) return real is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : integer; b,c : time) return time is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : std_ulogic) return std_ulogic is
begin
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c;
--pragma synthesis_off
ELSIF (b = c AND NOT Is_X(b)) THEN
return b;
ELSE
return 'X';
--pragma synthesis_on
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic; b,c : integer) return integer is
begin
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c;
--pragma synthesis_off
ELSIF (b = c) THEN
return b;
ELSE
return 0;
--pragma synthesis_on
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic; b,c : std_ulogic_vector) return std_ulogic_vector is
--pragma synthesis_off
constant SIZE: NATURAL := MAX(b'LENGTH, c'LENGTH);
variable b01 : std_ulogic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable c01 : std_ulogic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable result : std_ulogic_vector(SIZE-1 downto 0);
--pragma synthesis_on
begin
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c;
--pragma synthesis_off
ELSIF (b = c AND NOT Is_X(b)) THEN
return b;
ELSE
b01(b'LENGTH-1 downto 0) := b;
c01(c'LENGTH-1 downto 0) := c;
FOR I IN SIZE-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
--pragma synthesis_on
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic; b,c : std_logic_vector) return std_logic_vector is
--pragma synthesis_off
constant SIZE: NATURAL := MAX(b'LENGTH, c'LENGTH);
variable b01 : std_logic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable c01 : std_logic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable result : std_logic_vector(SIZE-1 downto 0);
--pragma synthesis_on
begin
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c;
--pragma synthesis_off
ELSIF (b = c AND NOT Is_X(b)) THEN
return b;
ELSE
b01(b'LENGTH-1 downto 0) := b;
c01(c'LENGTH-1 downto 0) := c;
FOR I IN SIZE-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
--pragma synthesis_on
END IF;
end TERNARY;
--pragma synthesis_off
FUNCTION TERNARY(a : std_ulogic; b,c : real) return real is
begin
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c;
ELSIF (b = c) THEN
return b;
ELSE
return 0.0;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic; b,c : time) return time is
begin
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c;
ELSIF (b = c) THEN
return b;
ELSE
return 0 ns;
END IF;
end TERNARY;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : std_ulogic_vector) return std_ulogic_vector is
--pragma synthesis_off
constant SIZE: NATURAL := MAX(b'LENGTH, c'LENGTH);
variable b01 : std_ulogic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable c01 : std_ulogic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable result : std_ulogic_vector(SIZE-1 downto 0);
--pragma synthesis_on
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE
b01(b'LENGTH-1 downto 0) := b;
c01(c'LENGTH-1 downto 0) := c;
FOR I IN SIZE-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : integer) return integer is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 0;
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : std_ulogic) return std_ulogic is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 'X';
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : std_logic_vector) return std_logic_vector is
--pragma synthesis_off
constant SIZE: NATURAL := MAX(b'LENGTH, c'LENGTH);
variable b01 : std_logic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable c01 : std_logic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable result : std_logic_vector(SIZE-1 downto 0);
--pragma synthesis_on
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE
b01(b'LENGTH-1 downto 0) := b;
c01(c'LENGTH-1 downto 0) := c;
FOR I IN SIZE-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
--pragma synthesis_off
FUNCTION TERNARY(a : std_ulogic_vector; b,c : real) return real is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 0.0;
END IF;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : time) return time is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 0 ns;
END IF;
ELSE
return c;
END IF;
end TERNARY;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : std_logic_vector) return std_logic_vector is
--pragma synthesis_off
constant SIZE: NATURAL := MAX(b'LENGTH, c'LENGTH);
variable b01 : std_logic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable c01 : std_logic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable result : std_logic_vector(SIZE-1 downto 0);
--pragma synthesis_on
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE
b01(b'LENGTH-1 downto 0) := b;
c01(c'LENGTH-1 downto 0) := c;
FOR I IN SIZE-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_logic_vector; b,c : integer) return integer is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 0;
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_logic_vector; b,c : std_ulogic) return std_ulogic is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 'X';
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_logic_vector; b,c : std_ulogic_vector) return std_ulogic_vector is
--pragma synthesis_off
constant SIZE: NATURAL := MAX(b'LENGTH, c'LENGTH);
variable b01 : std_ulogic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable c01 : std_ulogic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable result : std_ulogic_vector(SIZE-1 downto 0);
--pragma synthesis_on
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE
b01(b'LENGTH-1 downto 0) := b;
c01(c'LENGTH-1 downto 0) := c;
FOR I IN SIZE-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
--pragma synthesis_off
FUNCTION TERNARY(a : std_logic_vector; b,c : real) return real is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 0.0;
END IF;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_logic_vector; b,c : time) return time is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 0 ns;
END IF;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a,b,c : real) return real is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : real; b,c : std_ulogic) return std_ulogic is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : real; b,c : std_ulogic_vector) return std_ulogic_vector is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : real; b,c : std_logic_vector) return std_logic_vector is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : real; b,c : integer) return integer is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : real; b,c : time) return time is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
--pragma synthesis_on
-- functions for TERNARY combination
FUNCTION TERNARY(a : std_ulogic; b : std_logic_vector; c: std_ulogic) return
std_logic_vector IS
variable c01 : std_logic_vector(b'LENGTH-1 downto 0) := (OTHERS => '0');
--pragma synthesis_off
variable b01 : std_logic_vector(b'LENGTH-1 downto 0) := b;
variable result : std_logic_vector(b'LENGTH-1 downto 0);
--pragma synthesis_on
BEGIN
c01(0) := c;
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c01;
--pragma synthesis_off
ELSIF (b01 = c01 AND NOT Is_X(b)) THEN
return b;
ELSE
FOR I IN b'LENGTH-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
--pragma synthesis_on
END IF;
END TERNARY;
FUNCTION TERNARY(a : std_ulogic; b : std_ulogic; c: std_logic_vector) return
std_logic_vector IS
variable b01 : std_logic_vector(c'LENGTH-1 downto 0) := (OTHERS => '0');
--pragma synthesis_off
variable c01 : std_logic_vector(c'LENGTH-1 downto 0) := c;
variable result : std_logic_vector(c'LENGTH-1 downto 0);
--pragma synthesis_on
BEGIN
b01(0) := b;
IF (a = '1') THEN
return b01;
ELSIF (a = '0') THEN
return c;
--pragma synthesis_off
ELSIF (b01 = c01 AND NOT Is_X(b01)) THEN
return b01;
ELSE
FOR I IN c'LENGTH-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
--pragma synthesis_on
END IF;
END TERNARY;
FUNCTION TERNARY(a : std_ulogic; b : integer; c: std_ulogic) return
integer IS
BEGIN
IF (a = '0') THEN
return to_integer(c);
ELSIF (a = '1') THEN
return b;
--pragma synthesis_off
ELSIF (b = to_integer(c) AND NOT Is_X(c)) THEN
return b;
ELSE
return 0;
--pragma synthesis_on
END IF;
END TERNARY;
FUNCTION TERNARY(a : std_ulogic; b : std_ulogic; c: integer) return
integer IS
BEGIN
IF (a = '0') THEN
return c;
ELSIF (a = '1') THEN
return to_integer(b);
--pragma synthesis_off
ELSIF (to_integer(b) = c AND NOT Is_X(b)) THEN
return c;
ELSE
return 0;
--pragma synthesis_on
END IF;
END TERNARY;
FUNCTION TERNARY(a : integer; b : integer; c: std_ulogic) return
integer IS
BEGIN
IF (a /= 0) THEN
return b;
ELSE
return to_integer(c);
END IF;
END TERNARY;
FUNCTION TERNARY(a : integer; b : std_ulogic; c: integer) return
integer IS
BEGIN
IF (a /= 0) THEN
return to_integer(b);
ELSE
return c;
END IF;
END TERNARY;
FUNCTION TERNARY(a : integer; b : std_logic_vector; c: std_ulogic) return
std_logic_vector IS
VARIABLE temp : std_logic_vector(0 downto 0);
BEGIN
IF (a /= 0) THEN
return b;
ELSE
temp(0) := c;
return temp;
END IF;
END TERNARY;
FUNCTION TERNARY(a : integer; b : std_ulogic; c: std_logic_vector) return
std_logic_vector IS
VARIABLE temp : std_logic_vector(0 downto 0);
BEGIN
IF (a /= 0) THEN
temp(0) := b;
return temp;
ELSE
return c;
END IF;
END TERNARY;
--end functions for TERNARY combination
-- FUNCTIONS for integer operations
FUNCTION "not" (l: integer) return integer is
VARIABLE temp : SIGNED(31 downto 0) := TO_SIGNED(l,32);
begin
return TO_INTEGER(NOT(temp));
end "not";
FUNCTION "and" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
VARIABLE temp2 : SIGNED(31 downto 0) := TO_SIGNED(r,32);
begin
return TO_INTEGER(temp1 AND temp2);
end "and";
FUNCTION "nand" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
VARIABLE temp2 : SIGNED(31 downto 0) := TO_SIGNED(r,32);
begin
return TO_INTEGER(temp1 NAND temp2);
end "nand";
FUNCTION "or" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
VARIABLE temp2 : SIGNED(31 downto 0) := TO_SIGNED(r,32);
begin
return TO_INTEGER(temp1 OR temp2);
end "or";
FUNCTION "nor" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
VARIABLE temp2 : SIGNED(31 downto 0) := TO_SIGNED(r,32);
begin
return TO_INTEGER(temp1 NOR temp2);
end "nor";
FUNCTION "xor" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
VARIABLE temp2 : SIGNED(31 downto 0) := TO_SIGNED(r,32);
begin
return TO_INTEGER(temp1 XOR temp2);
end "xor";
FUNCTION "xnor" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
VARIABLE temp2 : SIGNED(31 downto 0) := TO_SIGNED(r,32);
begin
return TO_INTEGER(temp1 XNOR temp2);
end "xnor";
FUNCTION "sll" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
begin
return TO_INTEGER(temp1 SLL r);
end "sll";
FUNCTION "srl" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
begin
return TO_INTEGER(temp1 SRL r);
end "srl";
-- functions for std_ulogic operations
-- first add all the tables needed
-- truth table for "=" function
CONSTANT eq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
-- truth table for "/=" function
CONSTANT neq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
-- truth table for "<" function
CONSTANT ltb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
-- truth table for ">" function
CONSTANT gtb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
-- truth table for "<=" function
CONSTANT leb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | X |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | W |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ) -- | D |
);
-- truth table for ">=" function
CONSTANT geb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 1 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | H |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ) -- | D |
);
CONSTANT lt_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
-- truth table for ">" function
CONSTANT gt_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
-- truth table for "<=" function
CONSTANT le_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | D |
);
-- truth table for ">=" function
CONSTANT ge_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', '1', 'U', 'U', 'U', '1', 'U', 'U' ), -- | U |
( 'U', 'X', '1', 'X', 'X', 'X', '1', 'X', 'X' ), -- | X |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', '1', 'X', 'X', 'X', '1', 'X', 'X' ), -- | Z |
( 'U', 'X', '1', 'X', 'X', 'X', '1', 'X', 'X' ), -- | W |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', '1', 'X', 'X', 'X', '1', 'X', 'X' ) -- | D |
);
FUNCTION "=" ( l : Boolean; r : natural ) RETURN Boolean is
begin
IF l = TRUE AND r = 1 THEN
return TRUE;
ELSIF l = FALSE AND r = 0 THEN
return TRUE;
ELSE
return FALSE;
END IF;
end "=";
FUNCTION "/=" ( l : Boolean; r : natural ) RETURN Boolean is
begin
return NOT (l = r);
end "/=";
-----------------------------------------------------------------
FUNCTION "=" ( l : integer; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l = SIGNED(r);
END "=";
-----------------------------------------------------------------
FUNCTION "/=" ( l : integer; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l /= SIGNED(r);
END "/=";
-----------------------------------------------------------------
FUNCTION "<" ( l : integer; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l < SIGNED(r);
END "<";
-----------------------------------------------------------------
FUNCTION ">" ( l : integer; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l > SIGNED(r);
END ">";
-----------------------------------------------------------------
FUNCTION "<=" ( l : integer; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l <= SIGNED(r);
END "<=";
-----------------------------------------------------------------
FUNCTION ">=" ( l : integer; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l >= SIGNED(r);
END ">=";
-----------------------------------------------------------------
FUNCTION "=" ( l : std_logic_vector; r : integer ) RETURN boolean IS
BEGIN
RETURN SIGNED(l) = r;
END "=";
-----------------------------------------------------------------
FUNCTION "/=" ( l : std_logic_vector; r : integer ) RETURN boolean IS
BEGIN
RETURN SIGNED(l) /= r;
END "/=";
-----------------------------------------------------------------
FUNCTION "<" ( l : std_logic_vector; r : integer ) RETURN boolean IS
BEGIN
RETURN SIGNED(l) < r;
END "<";
-----------------------------------------------------------------
FUNCTION ">" ( l : std_logic_vector; r : integer ) RETURN boolean IS
BEGIN
RETURN SIGNED(l) > r;
END ">";
-----------------------------------------------------------------
FUNCTION "<=" ( l : std_logic_vector; r : integer ) RETURN boolean IS
BEGIN
RETURN SIGNED(l) <= r;
END "<=";
-----------------------------------------------------------------
FUNCTION ">=" ( l : std_logic_vector; r : integer ) RETURN boolean IS
BEGIN
RETURN SIGNED(l) >= r;
END ">=";
-----------------------------------------------------------------
--logical functions between std_logic_vector and integer, std_logic_vector and boolean
FUNCTION "and" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
BEGIN
RETURN l and to_stdlogicvector(l, 32);
END;
-----------------------------------------------------------------
FUNCTION "nand" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector IS
BEGIN
RETURN l nand to_stdlogicvector(l, 32);
END;
-----------------------------------------------------------------
FUNCTION "or" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector IS
BEGIN
RETURN l or to_stdlogicvector(l, 32);
END;
-----------------------------------------------------------------
FUNCTION "nor" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector IS
BEGIN
RETURN l nor to_stdlogicvector(l, 32);
END;
-----------------------------------------------------------------
FUNCTION "xor" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector IS
BEGIN
RETURN l xor to_stdlogicvector(l, 32);
END;
-----------------------------------------------------------------
FUNCTION "and" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN l and v2v_to_integer(r);
END;
-----------------------------------------------------------------
FUNCTION "nand" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN l nand v2v_to_integer(r);
END;
-----------------------------------------------------------------
FUNCTION "or" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN l or v2v_to_integer(r);
END;
-----------------------------------------------------------------
FUNCTION "nor" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN l nor v2v_to_integer(r);
END;
-----------------------------------------------------------------
FUNCTION "xor" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN l xor v2v_to_integer(r);
END;
-----------------------------------------------------------------
FUNCTION "and" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN l and to_stdlogicvector(r,32);
END;
-----------------------------------------------------------------
FUNCTION "nand" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN l nand to_stdlogicvector(r,32);
END;
-----------------------------------------------------------------
FUNCTION "or" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN l or to_stdlogicvector(r,32);
END;
-----------------------------------------------------------------
FUNCTION "nor" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN l nor to_stdlogicvector(r,32);
END;
-----------------------------------------------------------------
FUNCTION "xor" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN l xor to_stdlogicvector(r,32);
END;
-----------------------------------------------------------------
FUNCTION "and" ( l : boolean; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l and to_boolean(r);
END;
-----------------------------------------------------------------
FUNCTION "nand" ( l : boolean; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l nand to_boolean(r);
END;
-----------------------------------------------------------------
FUNCTION "or" ( l : boolean; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l or to_boolean(r);
END;
-----------------------------------------------------------------
FUNCTION "nor" ( l : boolean; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l nor to_boolean(r);
END;
-----------------------------------------------------------------
FUNCTION "xor" ( l : boolean; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l xor to_boolean(r);
END;
--logical functions between std_logic_vector and integer, std_logic_vector and boolean
-----------------------------------------------------------------
-- Added functions for std_logic, integer
FUNCTION "=" ( l : std_logic; r : integer ) RETURN boolean IS
BEGIN
RETURN to_integer(l) = r;
END "=";
-----------------------------------------------------------------
FUNCTION "/=" ( l : std_logic; r : integer ) RETURN boolean IS
BEGIN
RETURN to_integer(l) /= r;
END "/=";
-----------------------------------------------------------------
FUNCTION "<" ( l : std_logic; r : integer ) RETURN boolean IS
BEGIN
RETURN to_integer(l) < r;
END "<";
-----------------------------------------------------------------
FUNCTION ">" ( l : std_logic; r : integer ) RETURN boolean IS
BEGIN
RETURN to_integer(l) > r;
END ">";
-----------------------------------------------------------------
FUNCTION "<=" ( l : std_logic; r : integer ) RETURN boolean IS
BEGIN
RETURN to_integer(l) <= r;
END "<=";
-----------------------------------------------------------------
FUNCTION ">=" ( l : std_logic; r : integer ) RETURN boolean IS
BEGIN
RETURN to_integer(l) >= r;
END ">=";
-----------------------------------------------------------------
-- Functions for std_logic, integer
-----------------------------------------------------------------
--pragma synthesis_off
-- arithmetic operations for real and int and int and real
FUNCTION "+" ( l : real; r : integer ) RETURN real IS
BEGIN
RETURN l + to_real(r);
END;
FUNCTION "-" ( l : real; r : integer ) RETURN real IS
BEGIN
RETURN l - to_real(r);
END;
FUNCTION "/" ( l : real; r : integer ) RETURN real IS
BEGIN
RETURN l / to_real(r);
END;
FUNCTION "*" ( l : real; r : integer ) RETURN real IS
BEGIN
RETURN l * to_real(r);
END ;
FUNCTION "+" ( l : integer; r : real ) RETURN real IS
BEGIN
RETURN to_real(l) + r;
END;
FUNCTION "-" ( l : integer; r : real ) RETURN real IS
BEGIN
RETURN to_real(l) - r;
END;
FUNCTION "/" ( l : integer; r : real ) RETURN real IS
BEGIN
RETURN to_real(l) / l;
END;
FUNCTION "*" ( l : integer; r : real ) RETURN real IS
BEGIN
RETURN to_real(l) * r;
END;
-- end arithmetic operations for real and int and int and real
-----------------------------------------------------------------
FUNCTION "=" ( l : real; r : integer ) RETURN boolean IS
BEGIN
RETURN INTEGER(l) = r;
END "=";
-----------------------------------------------------------------
FUNCTION "/=" ( l : real; r : integer ) RETURN boolean IS
BEGIN
RETURN INTEGER(l) /= r;
END "/=";
-----------------------------------------------------------------
FUNCTION "<" ( l : real; r : integer ) RETURN boolean IS
BEGIN
RETURN INTEGER(l) < r;
END "<";
-----------------------------------------------------------------
FUNCTION ">" ( l : real; r : integer ) RETURN boolean IS
BEGIN
RETURN INTEGER(l) > r;
END ">";
-----------------------------------------------------------------
FUNCTION "<=" ( l : real; r : integer ) RETURN boolean IS
BEGIN
RETURN INTEGER(l) <= r;
END "<=";
-----------------------------------------------------------------
FUNCTION ">=" ( l : real; r : integer ) RETURN boolean IS
BEGIN
RETURN INTEGER(l) >= r;
END ">=";
-----------------------------------------------------------------
FUNCTION "=" ( l : integer; r : real ) RETURN boolean IS
BEGIN
RETURN l = INTEGER(r);
END "=";
-----------------------------------------------------------------
FUNCTION "/=" ( l : integer; r : real ) RETURN boolean IS
BEGIN
RETURN l /= INTEGER(r);
END "/=";
-----------------------------------------------------------------
FUNCTION "<" ( l : integer; r : real ) RETURN boolean IS
BEGIN
RETURN l < INTEGER(r);
END "<";
-----------------------------------------------------------------
FUNCTION ">" ( l : integer; r : real ) RETURN boolean IS
BEGIN
RETURN l > INTEGER(r);
END ">";
-----------------------------------------------------------------
FUNCTION "<=" ( l : integer; r : real ) RETURN boolean IS
BEGIN
RETURN l <= INTEGER(r);
END "<=";
-----------------------------------------------------------------
FUNCTION ">=" ( l : integer; r : real ) RETURN boolean IS
BEGIN
RETURN l >= INTEGER(r);
END ">=";
--pragma synthesis_on
-----------------------------------------------------------------
FUNCTION "+" ( l, r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(UNSIGNED(l) + UNSIGNED(r));
end "+";
------------------------------------------------------------------
FUNCTION "-" ( l, r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(UNSIGNED(l) - UNSIGNED(r));
end "-";
------------------------------------------------------------------
FUNCTION "*" ( l, r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(UNSIGNED(l) * UNSIGNED(r));
end "*";
------------------------------------------------------------------
FUNCTION "/" ( l, r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(UNSIGNED(l) / UNSIGNED(r));
end "/";
------------------------------------------------------------------
FUNCTION "REM" ( l, r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(UNSIGNED(l) rem UNSIGNED(r));
end "REM";
------------------------------------------------------------------
FUNCTION "+" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) + r);
end "+";
------------------------------------------------------------------
FUNCTION "-" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) - r);
end "-";
------------------------------------------------------------------
FUNCTION "*" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) * r);
end "*";
------------------------------------------------------------------
FUNCTION "/" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) / r);
end "/";
------------------------------------------------------------------
FUNCTION "REM" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) rem r);
end "REM";
------------------------------------------------------------------
FUNCTION "&" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
begin
return l & to_stdlogic(r);
end "&";
------------------------------------------------------------------
FUNCTION "&" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector is
begin
return l & to_stdlogic(r);
end "&";
------------------------------------------------------------------
FUNCTION "+" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) + to_integer(r));
end "+";
------------------------------------------------------------------
FUNCTION "-" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) - to_integer(r));
end "-";
------------------------------------------------------------------
FUNCTION "*" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) * to_integer(r));
end "*";
------------------------------------------------------------------
FUNCTION "/" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) / to_integer(r));
end "/";
------------------------------------------------------------------
FUNCTION "REM" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) rem to_integer(r));
end "REM";
------------------------------------------------------------------
FUNCTION "+" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(to_integer(l) + SIGNED(r));
END "+";
------------------------------------------------------------------
FUNCTION "-" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(to_integer(l) - SIGNED(r));
END "-";
------------------------------------------------------------------
FUNCTION "*" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(to_integer(l) * SIGNED(r));
END "*";
------------------------------------------------------------------
FUNCTION "/" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(to_integer(l) / SIGNED(r));
END "/";
------------------------------------------------------------------
FUNCTION "REM" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(to_integer(l) REM SIGNED(r));
END "REM";
-------------------------------------------------------------
-- need logical functions bet. std_logic_vector and std_logic
FUNCTION "and" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN l and to_stdlogicvector(r, l'length);
END "and";
--------------------------------------------------------------
FUNCTION "nand" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN l nand to_stdlogicvector(r, l'length);
END "nand";
--------------------------------------------------------------
FUNCTION "or" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN l or to_stdlogicvector(r, l'length);
END "or";
--------------------------------------------------------------
FUNCTION "nor" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN l nor to_stdlogicvector(r, l'length);
END "nor";
--------------------------------------------------------------
FUNCTION "xor" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN l xor to_stdlogicvector(r, l'length);
END "xor";
--------------------------------------------------------------
FUNCTION "xnor" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN NOT(l xor to_stdlogicvector(r, l'length));
END "xnor";
--------------------------------------------------------------
FUNCTION "and" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogicvector(l, r'length) and r;
END "and";
--------------------------------------------------------------
FUNCTION "nand" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogicvector(l, r'length) nand r;
END "nand";
--------------------------------------------------------------
FUNCTION "or" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogicvector(l, r'length) or r;
END "or";
--------------------------------------------------------------
FUNCTION "nor" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogicvector(l, r'length) nor r;
END "nor";
--------------------------------------------------------------
FUNCTION "xor" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogicvector(l, r'length) xor r;
END "xor";
--------------------------------------------------------------
FUNCTION "xnor" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN NOT(to_stdlogicvector(l, r'length) xor r);
END "xnor";
--------------------------------------------------------------
-- end logical functions for std_logic_vector and std_logic
------------------------------------------------------------------
-- need arith functions bet std_logic and std_logic
-- used only when the int can be 0 or 1
-- need arithmetic functions bet. std_logic_vector and std_logic
FUNCTION "+" ( l : std_logic; r : std_logic ) RETURN std_logic IS
BEGIN
return to_stdlogic(to_integer(l) + to_integer(r));
END "+";
FUNCTION "-" ( l : std_logic; r : std_logic ) RETURN std_logic IS
BEGIN
return to_stdlogic(to_integer(l) - to_integer(r));
END "-";
FUNCTION "*" ( l : std_logic; r : std_logic ) RETURN std_logic IS
BEGIN
return to_stdlogic(to_integer(l) * to_integer(r));
END "*";
FUNCTION "/" ( l : std_logic; r : std_logic ) RETURN std_logic IS
BEGIN
return to_stdlogic(to_integer(l) / to_integer(r));
END "/";
FUNCTION "REM" ( l : std_logic; r : std_logic ) RETURN std_logic IS
BEGIN
return to_stdlogic(to_integer(l) REM to_integer(r));
END "REM";
------- Arithmatic operations between std_logic and integer
-- caveat, functions below return integer
FUNCTION "+" ( l : std_logic; r : integer ) RETURN integer IS
BEGIN
return to_integer(l) + r;
END "+";
-------------------------------------------------------
FUNCTION "-" ( l : std_logic; r : integer ) RETURN integer IS
BEGIN
return to_integer(l) - r;
END "-";
-------------------------------------------------------
FUNCTION "*" ( l : std_logic; r : integer ) RETURN integer IS
BEGIN
return to_integer(l) * r;
END "*";
-------------------------------------------------------
FUNCTION "/" ( l : std_logic; r : integer ) RETURN integer IS
BEGIN
return to_integer(l) / r;
END "/";
-------------------------------------------------------
FUNCTION "REM" ( l : std_logic; r : integer ) RETURN integer IS
BEGIN
return to_integer(l) REM r;
END "REM";
-------------------------------------------------------
-------------------------------------------------------
FUNCTION "+" ( l : integer; r : std_logic ) RETURN integer IS
begin
return l + to_integer(r);
END "+";
-------------------------------------------------------
FUNCTION "-" ( l : integer; r : std_logic ) RETURN integer IS
begin
return l - to_integer(r);
END "-";
-------------------------------------------------------
FUNCTION "*" ( l : integer; r : std_logic ) RETURN integer IS
begin
return l * to_integer(r);
END "*";
-------------------------------------------------------
FUNCTION "/" ( l : integer; r : std_logic ) RETURN integer IS
begin
return l / to_integer(r);
END "/";
-------------------------------------------------------
FUNCTION "REM" ( l : integer; r : std_logic ) RETURN integer IS
begin
return l REM to_integer(r);
END "REM";
-------------------------------------------------------
FUNCTION "+" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN to_integer(l + SIGNED(r));
END "+";
------------------------------------------------------------------
FUNCTION "-" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN to_integer(l - SIGNED(r));
END "-";
------------------------------------------------------------------
FUNCTION "*" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN to_integer(l * SIGNED(r));
END "*";
------------------------------------------------------------------
FUNCTION "/" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN to_integer(l / SIGNED(r));
END "/";
------------------------------------------------------------------
FUNCTION "REM" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN to_integer(l REM SIGNED(r));
END "REM";
------------------------------------------------------------------
FUNCTION "and" ( l : std_logic; r : integer ) RETURN std_logic IS
BEGIN
RETURN l and to_stdlogic(r);
END "and";
------------------------------------------------------------------
FUNCTION "nand" ( l : std_logic; r : integer ) RETURN std_logic IS
BEGIN
RETURN l nand to_stdlogic(r);
END "nand";
------------------------------------------------------------------
FUNCTION "or" ( l : std_logic; r : integer ) RETURN std_logic IS
BEGIN
RETURN l or to_stdlogic(r);
END "or";
------------------------------------------------------------------
FUNCTION "nor" ( l : std_logic; r : integer ) RETURN std_logic IS
BEGIN
RETURN l nor to_stdlogic(r);
END "nor";
------------------------------------------------------------------
FUNCTION "xor" ( l : std_logic; r : integer ) RETURN std_logic IS
BEGIN
RETURN l xor to_stdlogic(r);
END "xor";
------------------------------------------------------------------
FUNCTION "&" ( l : std_logic; r : integer ) RETURN std_logic_vector IS
BEGIN
RETURN l & to_stdlogic(r);
END "&";
------------------------------------------------------------------
FUNCTION "xnor" ( l : std_logic; r : integer ) RETURN std_logic IS
BEGIN
RETURN not(l xor to_stdlogic(r));
END "xnor";
------------------------------------------------------------------
FUNCTION "and" ( l : integer; r : std_logic ) RETURN integer IS
VARIABLE tmp : integer := 0;
BEGIN
RETURN l and to_integer(r);
END "and";
------------------------------------------------------------------
FUNCTION "nand" ( l : integer; r : std_logic ) RETURN integer IS
VARIABLE tmp : integer := 0;
BEGIN
RETURN l nand to_integer(r);
END "nand";
------------------------------------------------------------------
FUNCTION "or" ( l : integer; r : std_logic ) RETURN integer IS
VARIABLE tmp : integer := 0;
BEGIN
RETURN l or to_integer(r);
END "or";
------------------------------------------------------------------
FUNCTION "nor" ( l : integer; r : std_logic ) RETURN integer IS
VARIABLE tmp : integer := 0;
BEGIN
RETURN l nor to_integer(r);
END "nor";
------------------------------------------------------------------
FUNCTION "xor" ( l : integer; r : std_logic ) RETURN integer IS
VARIABLE tmp : integer := 0;
BEGIN
RETURN l xor to_integer(r);
END "xor";
------------------------------------------------------------------
FUNCTION "&" ( l : integer; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogic(l) & r;
END "&";
------------------------------------------------------------------
FUNCTION "xnor" ( l : integer; r : std_logic ) RETURN integer IS
VARIABLE tmp : integer := 0;
BEGIN
RETURN l xnor to_integer(r);
END "xnor";
------------------------------------------------------------------
FUNCTION "and" ( l : std_logic ; r : boolean ) RETURN std_logic IS
BEGIN
RETURN l AND to_stdlogic(r);
END "and";
------------------------------------------------------------------
FUNCTION "nand" ( l : std_logic ; r : boolean ) RETURN std_logic IS
BEGIN
RETURN l NAND to_stdlogic(r);
END "nand";
------------------------------------------------------------------
FUNCTION "or" ( l : std_logic ; r : boolean ) RETURN std_logic IS
BEGIN
RETURN l OR to_stdlogic(r);
END "or";
------------------------------------------------------------------
FUNCTION "nor" ( l : std_logic ; r : boolean ) RETURN std_logic IS
BEGIN
RETURN l NOR to_stdlogic(r);
END "nor";
------------------------------------------------------------------
FUNCTION "xor" ( l : std_logic ; r : boolean ) RETURN std_logic IS
BEGIN
RETURN l XOR to_stdlogic(r);
END "xor";
------------------------------------------------------------------
FUNCTION "&" ( l : std_logic; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN l & to_stdlogic(r);
END "&";
------------------------------------------------------------------
FUNCTION "xnor" ( l : std_logic ; r : boolean ) RETURN std_logic IS
BEGIN
RETURN NOT(l XOR to_stdlogic(r));
END "xnor";
------------------------------------------------------------------
FUNCTION "and" ( l : boolean ; r : std_logic ) RETURN boolean IS
VARIABLE tmp : std_logic := 'U';
BEGIN
tmp := to_stdlogic(l) AND r;
RETURN to_boolean(tmp);
END "and";
------------------------------------------------------------------
FUNCTION "nand" ( l : boolean ; r : std_logic ) RETURN boolean IS
VARIABLE tmp : std_logic := 'U';
BEGIN
tmp := to_stdlogic(l) NAND r;
RETURN to_boolean(tmp);
END "nand";
------------------------------------------------------------------
FUNCTION "or" ( l : boolean ; r : std_logic ) RETURN boolean IS
VARIABLE tmp : std_logic := 'U';
BEGIN
tmp := to_stdlogic(l) OR r;
RETURN to_boolean(tmp);
END "or";
------------------------------------------------------------------
FUNCTION "nor" ( l : boolean ; r : std_logic ) RETURN boolean IS
VARIABLE tmp : std_logic := 'U';
BEGIN
tmp := to_stdlogic(l) NOR r;
RETURN to_boolean(tmp);
END "nor";
------------------------------------------------------------------
FUNCTION "xor" ( l : boolean ; r : std_logic ) RETURN boolean IS
VARIABLE tmp : std_logic := 'U';
BEGIN
tmp := to_stdlogic(l) XOR r;
RETURN to_boolean(tmp);
END "xor";
------------------------------------------------------------------
FUNCTION "&" ( l : boolean ; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogic(l) & r;
END "&";
------------------------------------------------------------------
FUNCTION "xnor" ( l : boolean ; r : std_logic ) RETURN boolean IS
VARIABLE tmp : std_logic := 'U';
BEGIN
tmp := NOT(to_stdlogic(l) XOR r);
RETURN to_boolean(tmp);
END "xnor";
------------------------------------------------------------------
FUNCTION "and" ( l : integer; r : boolean ) RETURN integer IS
BEGIN
RETURN l and to_integer(r);
END "and";
------------------------------------------------------------------
FUNCTION "nand" ( l : integer; r : boolean ) RETURN integer IS
BEGIN
RETURN l nand to_integer(r);
END "nand";
------------------------------------------------------------------
FUNCTION "or" ( l : integer; r : boolean ) RETURN integer IS
BEGIN
RETURN l or to_integer(r);
END "or";
------------------------------------------------------------------
FUNCTION "nor" ( l : integer; r : boolean ) RETURN integer IS
BEGIN
RETURN l nor to_integer(r);
END "nor";
------------------------------------------------------------------
FUNCTION "xor" ( l : integer; r : boolean ) RETURN integer IS
BEGIN
RETURN l xor to_integer(r);
END "xor";
------------------------------------------------------------------
FUNCTION "&" ( l : integer; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogic(l) & to_stdlogic(r);
END "&";
------------------------------------------------------------------
FUNCTION "xnor" ( l : integer; r : boolean ) RETURN integer IS
BEGIN
RETURN l xnor to_integer(r);
END "xnor";
------------------------------------------------------------------
FUNCTION "and" ( l : boolean; r : integer ) RETURN boolean IS
BEGIN
RETURN l AND to_boolean(r);
END "and";
------------------------------------------------------------------
FUNCTION "nand" ( l : boolean; r : integer ) RETURN boolean IS
BEGIN
RETURN l NAND to_boolean(r);
END "nand";
------------------------------------------------------------------
FUNCTION "or" ( l : boolean; r : integer ) RETURN boolean IS
BEGIN
RETURN l or to_boolean(r);
END "or";
------------------------------------------------------------------
FUNCTION "nor" ( l : boolean; r : integer ) RETURN boolean IS
BEGIN
RETURN l nor to_boolean(r);
END "nor";
------------------------------------------------------------------
FUNCTION "xor" ( l : boolean; r : integer ) RETURN boolean IS
BEGIN
RETURN l xor to_boolean(r);
END "xor";
------------------------------------------------------------------
FUNCTION "&" ( l : boolean; r : integer ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogic(l) & to_stdlogic(r);
END "&";
------------------------------------------------------------------
FUNCTION "xnor" ( l : boolean; r : integer ) RETURN boolean IS
BEGIN
RETURN l xnor to_boolean(r);
END "xnor";
------------------------------------------------------------------
-- Overloaded function for text output
FUNCTION to_bitvector ( a : bit ) RETURN bit_vector IS
VARIABLE s : bit_vector ( 1 TO 1 );
BEGIN
s(1) := a;
RETURN s;
END to_bitvector;
------------------------------------------------------------------
FUNCTION to_bitvector ( a : std_ulogic ) RETURN bit_vector IS
VARIABLE s : bit_vector ( 1 TO 1 );
BEGIN
s(1) := to_bit(a);
RETURN s;
END to_bitvector;
------------------------------------------------------------------
FUNCTION to_bitvector ( a : integer ) RETURN bit_vector IS
VARIABLE s : bit_vector ( 31 DOWNTO 0 );
BEGIN
s := to_bitvector(STD_LOGIC_VECTOR(to_signed(a, 32)));
RETURN s;
END to_bitvector;
------------------------------------------------------------------
FUNCTION to_stdlogicvector(l : integer; size : natural; dir : direction := little_endian) RETURN std_logic_vector IS
BEGIN
IF dir = little_endian THEN
RETURN STD_LOGIC_VECTOR(to_signed(l,size));
ELSE
RETURN STD_LOGIC_VECTOR(to_signed(l,size) ROL size); -- rotate left by size times
END IF;
END to_stdlogicvector;
------------------------------------------------------------------
FUNCTION to_stdlogicvector(l : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN l;
END to_stdlogicvector;
------------------------------------------------------------------
FUNCTION to_stdlogicvector(l : std_logic_vector; size : natural; dir : direction := little_endian )
RETURN std_logic_vector IS
VARIABLE tmp1 : UNSIGNED(l'length-1 downto 0);
VARIABLE tmp2 : UNSIGNED(size-1 downto 0);
BEGIN
IF dir = little_endian THEN
RETURN STD_LOGIC_VECTOR(resize(UNSIGNED(l),size));
ELSE
-- using function ROTATE_LEFT to make it both 87 and 93 compliant
-- first get eqiv. in descending range
-- second resize
-- finally, rotate and return
tmp1 := ROTATE_LEFT(UNSIGNED(l),l'length);
tmp2 := resize(UNSIGNED(tmp1),size);
RETURN STD_LOGIC_VECTOR(ROTATE_LEFT(UNSIGNED(tmp2),size));
END IF;
END to_stdlogicvector;
------------------------------------------------------------------
FUNCTION to_stdlogicvector(l : std_logic; size : natural) RETURN std_logic_vector IS
VARIABLE tmp : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp(0) := l;
RETURN tmp;
END to_stdlogicvector;
------------------------------------------------------------------
FUNCTION to_stdlogicvector(l : boolean; size : natural) RETURN std_logic_vector IS
VARIABLE tmp : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp(0) := to_stdlogic(l);
RETURN tmp;
END to_stdlogicvector;
------------------------------------------------------------------
FUNCTION to_integer(l : integer) RETURN integer IS
BEGIN
RETURN l;
END to_integer;
------------------------------------------------------------------
FUNCTION to_integer(l : std_logic) RETURN integer IS
BEGIN
IF ( l = '0') THEN
RETURN 0;
ELSIF (l = '1') THEN
RETURN 1;
ELSE
ASSERT FALSE REPORT("Std_logic values other than '0' and '1' cannot be converted to integer type")
SEVERITY WARNING;
RETURN 0;
END IF;
END to_integer;
------------------------------------------------------------------
FUNCTION to_integer(l : boolean) RETURN integer IS
BEGIN
IF ( l = TRUE) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END to_integer;
------------------------------------------------------------------
FUNCTION to_stdlogic(l : integer) RETURN std_logic IS
VARIABLE ret_val : std_logic := '0';
BEGIN
IF l = 0 THEN
ret_val := '0';
ELSIF l = 1 THEN
ret_val := '1';
ELSE
ASSERT FALSE REPORT("Integers other than 0 and 1 cannot be converted to std_logic type")
SEVERITY WARNING;
END IF;
RETURN ret_val;
END to_stdlogic;
------------------------------------------------------------------
FUNCTION to_stdlogic(l : Boolean) RETURN std_logic IS
VARIABLE ret_val : std_logic := '0';
BEGIN
IF l = FALSE THEN
ret_val := '0';
ELSE
ret_val := '1';
END IF;
RETURN ret_val;
END to_stdlogic;
------------------------------------------------------------------
FUNCTION to_stdlogic(l : std_logic) RETURN std_logic IS
BEGIN
RETURN l;
END to_stdlogic;
------------------------------------------------------------------
FUNCTION to_stdlogic(l : std_logic_vector) RETURN std_logic IS
BEGIN
RETURN l(l'LOW);
END to_stdlogic;
------------------------------------------------------------------
FUNCTION to_integer(l : std_logic_vector; dir : direction := little_endian) RETURN integer IS
BEGIN
IF dir = little_endian THEN
-- RETURN to_integer(SIGNED(l));
RETURN to_integer(UNSIGNED(l));
ELSE
-- RETURN to_integer(SIGNED(l) ROR l'LENGTH);
RETURN to_integer(UNSIGNED(l) ROR l'LENGTH);
END IF;
END to_integer;
------------------------------------------------------------------
FUNCTION v2v_to_integer(l : std_logic_vector; dir : direction := little_endian) RETURN integer IS
BEGIN
IF dir = little_endian THEN
-- RETURN to_integer(SIGNED(l));
RETURN to_integer(UNSIGNED(l));
ELSE
--NOTE, since ROR is not available in 87, we will use ROTATE_RIGHT
RETURN to_integer(ROTATE_RIGHT(UNSIGNED(l) , l'LENGTH));
-- RETURN to_integer(UNSIGNED(l) ROR l'LENGTH);
END IF;
END v2v_to_integer;
------------------------------------------------------------------
FUNCTION v2v_to_integer(l : integer) RETURN integer IS
BEGIN
RETURN l;
END v2v_to_integer;
------------------------------------------------------------------
FUNCTION v2v_to_integer(l : std_logic) RETURN integer IS
BEGIN
IF ( l = '0') THEN
RETURN 0;
ELSIF (l = '1') THEN
RETURN 1;
ELSE
ASSERT FALSE REPORT("Std_logic values other than '0' and '1' cannot be converted to integer type")
SEVERITY WARNING;
RETURN 0;
END IF;
END v2v_to_integer;
------------------------------------------------------------------
FUNCTION v2v_to_integer(l : boolean) RETURN integer IS
BEGIN
IF ( l = TRUE) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END v2v_to_integer;
------------------------------------------------------------------
--pragma synthesis_off
------------------------------------------------------------------
FUNCTION to_real(l : integer) RETURN real IS
BEGIN
RETURN REAL(l);
END to_real;
------------------------------------------------------------------
FUNCTION to_real(l : real) RETURN real IS
BEGIN
RETURN l;
END to_real;
--pragma synthesis_on
------------------------------------------------------------------
FUNCTION to_boolean(l : std_logic) RETURN boolean IS
BEGIN
IF ( l = '0' ) THEN
RETURN FALSE;
ELSIF (l = '1') THEN
RETURN TRUE;
ELSE
ASSERT FALSE REPORT("Std_logic values other than '0' and '1' cannot be converted to boolean type")
SEVERITY WARNING;
RETURN FALSE;
END IF;
END to_boolean;
------------------------------------------------------------------
FUNCTION to_boolean(l : std_logic_vector) RETURN boolean IS
VARIABLE tmp : std_logic_vector(l'RANGE);
BEGIN
tmp := (OTHERS=>'1');
if to_integer(l AND tmp) /= 0 THEN
RETURN TRUE;
END IF;
RETURN FALSE;
END to_boolean;
------------------------------------------------------------------
FUNCTION to_boolean(l : boolean) RETURN boolean IS
BEGIN
IF ( l) THEN
RETURN TRUE;
END IF;
RETURN FALSE;
END to_boolean;
------------------------------------------------------------------
FUNCTION to_boolean(l : integer) RETURN boolean IS
BEGIN
IF ( l = 0 ) THEN
RETURN FALSE;
ELSE
RETURN TRUE;
END IF;
END to_boolean;
------------------------------------------------------------------
FUNCTION "sll" ( l : std_logic_vector; r : integer) RETURN std_logic_vector IS
VARIABLE v : std_logic_vector(l'RANGE) := (others=>'0');
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "srl"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i) := l(i+r);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i) := l(i-r);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "sll" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector IS
VARIABLE v : std_ulogic_vector(l'RANGE) := (others=>'0');
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "srl"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i) := l(i+r);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i) := l(i-r);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "srl" ( l : std_logic_vector; r : integer) RETURN std_logic_vector IS
VARIABLE v : std_logic_vector(l'RANGE) := (others=>'0');
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "sll"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i+r) := l(i);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i-r) := l(i);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "srl" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector IS
VARIABLE v : std_ulogic_vector(l'RANGE) := (others=>'0');
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "sll"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i+r) := l(i);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i-r) := l(i);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "sla" ( l : std_logic_vector; r : integer) RETURN std_logic_vector IS
VARIABLE v : std_logic_vector(l'RANGE) := (others=>l(l'RIGHT));
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "sra"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i) := l(i+r);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i) := l(i-r);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "sla" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector IS
VARIABLE v : std_ulogic_vector(l'RANGE) := (others=>l(l'RIGHT));
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "sra"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i) := l(i+r);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i) := l(i-r);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "sra" ( l : std_logic_vector; r : integer) RETURN std_logic_vector IS
VARIABLE v : std_logic_vector(l'RANGE) := (others=>l(l'RIGHT));
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "sla"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i+r) := l(i);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i-r) := l(i);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "sra" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector IS
VARIABLE v : std_ulogic_vector(l'RANGE) := (others=>l(l'RIGHT));
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "sla"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i+r) := l(i);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i-r) := l(i);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "rol" ( l : std_logic_vector; r : integer) RETURN std_logic_vector IS
VARIABLE v : std_logic_vector(0 TO l'LENGTH*2-1);
VARIABLE v1 : std_logic_vector(l'RANGE);
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "ror"(l,-r);
ELSE
v(0 TO l'LENGTH-1) := l;
v(l'LENGTH TO v'LENGTH-1) := l;
v1 := v(r TO r+l'LENGTH-1);
RETURN v1;
END IF;
END;
FUNCTION "rol" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector IS
VARIABLE v : std_ulogic_vector(0 TO l'LENGTH*2-1);
VARIABLE v1 : std_ulogic_vector(l'RANGE);
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "ror"(l,-r);
ELSE
v(0 TO l'LENGTH-1) := l;
v(l'LENGTH TO v'LENGTH-1) := l;
v1 := v(r TO r+l'LENGTH-1);
RETURN v1;
END IF;
END;
FUNCTION "ror" ( l : std_logic_vector; r : integer) RETURN std_logic_vector IS
VARIABLE v : std_logic_vector(0 TO l'LENGTH*2-1);
VARIABLE v1 : std_logic_vector(l'RANGE);
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "rol"(l,-r);
ELSE
v(0 TO l'LENGTH-1) := l;
v(l'LENGTH TO v'LENGTH-1) := l;
v1 := v(l'LENGTH-r TO v'LENGTH-r-1);
RETURN v1;
END IF;
END;
FUNCTION "ror" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector IS
VARIABLE v : std_ulogic_vector(0 TO l'LENGTH*2-1);
VARIABLE v1 : std_ulogic_vector(l'RANGE);
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "rol"(l,-r);
ELSE
v(0 TO l'LENGTH-1) := l;
v(l'LENGTH TO v'LENGTH-1) := l;
v1 := v(l'LENGTH-r TO v'LENGTH-r-1);
RETURN v1;
END IF;
END;
FUNCTION to_stdlogicvector(hex : STRING) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(4 * hex'LENGTH DOWNTO 1);
BEGIN
-- Note: The hex parameter can have a range with hex'LOW > 1.
-- For these cases, variable index i in assignments in the FOR loop is normalized
-- to 1 by subtracting hex'LOW ** sas 2/13/96 **
FOR i in hex'RANGE LOOP
CASE hex(i) IS
WHEN '0' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"0";
WHEN '1' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"1";
WHEN '2' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"2";
WHEN '3' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"3";
WHEN '4' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"4";
WHEN '5' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"5";
WHEN '6' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"6";
WHEN '7' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"7";
WHEN '8' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"8";
WHEN '9' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"9";
WHEN 'A' | 'a' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"A";
WHEN 'B' | 'b' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"B";
WHEN 'C' | 'c' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"C";
WHEN 'D' | 'd' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"D";
WHEN 'E' | 'e' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"E";
WHEN 'F' | 'f' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"F";
WHEN 'X' | 'x' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := "XXXX";
WHEN 'Z' | 'z' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := "ZZZZ";
WHEN OTHERS =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := "XXXX";
END CASE;
END LOOP;
RETURN result;
END to_stdlogicvector;
end FUNCTIONS;
|
gpl-2.0
|
87ebdf8634335fb4326bcd59cf86c164
| 0.530123 | 3.403444 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/tech/dware/simprims/DWpackages.vhd
| 4 | 4,075 |
package DWpackages is
end;
-- pragma translate_off
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library grlib;
use grlib.stdlib.all;
entity DW_mult_pipe is
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1; -- '0': non-stallable; '1': stallable
rst_mode : natural range 0 to 2 := 1; -- '0': none; '1': async; '2': sync
op_iso_mode : natural range 0 to 4 := 0); -- '0': apply Power Compiler user setting; '1': noop; '2': and; '3': or; '4' preferred style...'and'
port (
clk : in std_logic; -- register clock
rst_n : in std_logic; -- register reset
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end ;
architecture simple of DW_mult_pipe is
subtype resw is std_logic_vector(A_width+B_width-1 downto 0);
type pipet is array (num_stages-1 downto 1) of resw;
signal p_i : pipet;
signal prod : resw;
begin
comb : process(A, B, TC)
begin
if notx(A) and notx(B) and notx(tc) then
if TC = '1' then
prod <= signed(A) * signed(B);
else
prod <= unsigned(A) * unsigned(B);
end if;
else
prod <= (others => 'X');
end if;
end process;
w2 : if num_stages = 2 generate
reg : process(clk)
begin
if rising_edge(clk) then
if (stall_mode = 0) or (en = '1') then
p_i(1) <= prod;
end if;
end if;
end process;
end generate;
w3 : if num_stages > 2 generate
reg : process(clk)
begin
if rising_edge(clk) then
if (stall_mode = 0) or (en = '1') then
p_i <= p_i(num_stages-2 downto 1) & prod;
end if;
end if;
end process;
end generate;
product <= p_i(num_stages-1);
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library grlib;
use grlib.stdlib.all;
entity DW02_mult is
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end DW02_mult;
architecture behav of DW02_mult is
begin
comb : process(A, B, TC)
begin
if notx(A) and notx(B) and notx(TC) then
if TC = '1' then
product <= signed(A) * signed(B);
else
product <= unsigned(A) * unsigned(B);
end if;
else
product <= (others => 'X');
end if;
end process;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library grlib;
use grlib.stdlib.all;
entity DW02_mult_2_stage is
generic( A_width: POSITIVE;
B_width: POSITIVE);
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end;
architecture behav of DW02_mult_2_stage is
signal P_i : std_logic_vector(A_width+B_width-1 downto 0);
begin
comb : process(A, B, TC)
begin
if notx(A) and notx(B) then
if TC = '1' then
P_i <= signed(A) * signed(B);
else
P_i <= unsigned(A) * unsigned(B);
end if;
else
P_i <= (others => 'X');
end if;
end process;
reg : process(CLK)
begin
if rising_edge(CLK) then
PRODUCT <= P_i;
end if;
end process;
end;
-- pragma translate_on
|
gpl-2.0
|
cc6cfc78e95e0eaab56fc6dda9eb3ac1
| 0.568098 | 3.16874 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/ddr/ahb2mig_7series_pkg.vhd
| 1 | 32,542 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: ah2mig_7series_pkg
-- File: ah2mig_7series_pkg.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler
-- Description: Components, types and functions for AHB2MIG 7-Series controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.config_types.all;
use grlib.config.all;
library gaisler;
use gaisler.all;
package ahb2mig_7series_pkg is
-------------------------------------------------------------------------------
-- AHB2MIG configuration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AHB2MIG interface type declarations and constant
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AHB2MIG Subprograms
-------------------------------------------------------------------------------
function nbrmaxmigcmds (
datawidth : integer)
return integer;
function nbrmigcmds (
hwrite : std_logic;
hsize : std_logic_vector;
htrans : std_logic_vector;
step : unsigned;
datawidth : integer)
return integer;
function nbrmigcmds16 (
hwrite : std_logic;
hsize : std_logic_vector;
htrans : std_logic_vector;
step : unsigned;
datawidth : integer)
return integer;
function reversebyte (
data : std_logic_vector)
return std_logic_vector;
function reversebytemig (
data : std_logic_vector)
return std_logic_vector;
function ahbselectdatanoreplicastep (
haddr : std_logic_vector(7 downto 2);
hsize : std_logic_vector(2 downto 0)
)
return unsigned;
-- Added in order to make it working for 16-bit memory (only with 32-bit bus)
function ahbselectdatanoreplicastep16 (
haddr : std_logic_vector(7 downto 2);
hsize : std_logic_vector(2 downto 0)
)
return unsigned;
function ahbselectdatanoreplicaoutput (
haddr : std_logic_vector(7 downto 0);
counter : unsigned(31 downto 0);
hsize : std_logic_vector(2 downto 0);
rdbuffer : unsigned;
wr_count : unsigned;
replica : boolean)
return std_logic_vector;
-- Added in order to make it working for 16-bit memory (only with 32-bit bus)
function ahbselectdatanoreplicaoutput16 (
haddr : std_logic_vector(7 downto 0);
counter : unsigned(31 downto 0);
hsize : std_logic_vector(2 downto 0);
rdbuffer : unsigned;
wr_count : unsigned;
replica : boolean)
return std_logic_vector;
function ahbselectdatanoreplicamask (
haddr : std_logic_vector(6 downto 0);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector;
function ahbselectdatanoreplica (hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 0); hsize : std_logic_vector(2 downto 0))
return std_logic_vector;
function ahbdrivedatanoreplica (hdata : std_logic_vector) return std_logic_vector;
-------------------------------------------------------------------------------
-- AHB2MIG Components
-------------------------------------------------------------------------------
end;
package body ahb2mig_7series_pkg is
-- Number of Max MIG commands
function nbrmaxmigcmds(
datawidth : integer)
return integer is
variable ret : integer;
begin
case datawidth is
when 128 =>
ret:= 4;
when 64 =>
ret := 2;
when others =>
ret := 2;
end case;
return ret;
end function nbrmaxmigcmds;
-- Number of MIG commands
function nbrmigcmds(
hwrite : std_logic;
hsize : std_logic_vector;
htrans : std_logic_vector;
step : unsigned;
datawidth : integer)
return integer is
variable ret : integer;
begin
if (hwrite = '0') then
case datawidth is
when 128 =>
if (hsize = HSIZE_4WORD) then
ret:= 4;
elsif (hsize = HSIZE_DWORD) then
ret := 2;
elsif (hsize = HSIZE_WORD) then
ret := 1;
else
ret := 1;
end if;
when 64 =>
if (hsize = HSIZE_DWORD) then
ret := 2;
elsif (hsize = HSIZE_WORD) then
ret := 2;
else
ret := 1;
end if;
-- 32
when others =>
if (hsize = HSIZE_WORD) then
ret := 2;
else
ret := 1;
end if;
end case;
if (htrans /= HTRANS_SEQ) then
ret := 1;
end if;
else
ret := to_integer(shift_right(step,4)) + 1;
end if;
return ret;
end function nbrmigcmds;
function nbrmigcmds16(
hwrite : std_logic;
hsize : std_logic_vector;
htrans : std_logic_vector;
step : unsigned;
datawidth : integer)
return integer is
variable ret : integer;
begin
if (hwrite = '0') then
if (hsize = HSIZE_WORD) then
ret := 2;
else
ret := 1;
end if;
if (htrans /= HTRANS_SEQ) then
ret := 1;
end if;
else
ret := to_integer(shift_right(step,2)) + 1;
end if;
return ret;
end function nbrmigcmds16;
-- Reverses byte order.
function reversebyte(
data : std_logic_vector)
return std_logic_vector is
variable rdata: std_logic_vector(data'length-1 downto 0);
begin
for i in 0 to (data'length/8-1) loop
rdata(i*8+8-1 downto i*8) := data(data'length-i*8-1 downto data'length-i*8-8);
end loop;
return rdata;
end function reversebyte;
-- Reverses byte order.
function reversebytemig(
data : std_logic_vector)
return std_logic_vector is
variable rdata: std_logic_vector(data'length-1 downto 0);
begin
for i in 0 to (data'length/8-1) loop
rdata(i*8+8-1 downto i*8) := data(data'left-i*8 downto data'left-i*8-7);
end loop;
return rdata;
end function reversebytemig;
-- Takes in AHB data vector 'hdata' and returns valid data on the full
-- data vector output based on 'haddr' and 'hsize' inputs together with
-- GRLIB AHB bus width. The function works down to word granularity.
function ahbselectdatanoreplica (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 0);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
variable ret : std_logic_vector(AHBDW-1 downto 0);
begin -- ahbselectdatanoreplica
ret := (others => '0');
case hsize is
when HSIZE_4WORD =>
ret(AHBDW-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto 0));
when HSIZE_DWORD =>
if AHBDW = 128 then
case haddr(3) is
when '0' => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto AHBDW/2));
when others => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW/2-1 downto 0));
end case;
elsif AHBDW = 64 then
ret(AHBDW-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto 0));
end if;
when HSIZE_WORD =>
if AHBDW = 128 then
case haddr(3 downto 2) is
when "00" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
elsif AHBDW = 64 then
case haddr(2) is
when '0' => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto AHBDW/2));
when others => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW/2-1 downto 0));
end case;
elsif AHBDW = 32 then
ret(AHBDW-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto 0));
end if;
when HSIZE_HWORD =>
if AHBDW = 128 then
case haddr(3 downto 1) is
when "000" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := reversebytemig(hdata(8*(AHBDW/8)-1 downto 7*(AHBDW/8)));
when "001" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := reversebytemig(hdata(7*(AHBDW/8)-1 downto 6*(AHBDW/8)));
when "010" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := reversebytemig(hdata(6*(AHBDW/8)-1 downto 5*(AHBDW/8)));
when "011" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := reversebytemig(hdata(5*(AHBDW/8)-1 downto 4*(AHBDW/8)));
when "100" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := reversebytemig(hdata(4*(AHBDW/8)-1 downto 3*(AHBDW/8)));
when "101" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := reversebytemig(hdata(3*(AHBDW/8)-1 downto 2*(AHBDW/8)));
when "110" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := reversebytemig(hdata(2*(AHBDW/8)-1 downto 1*(AHBDW/8)));
when others => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := reversebytemig(hdata(1*(AHBDW/8)-1 downto 0*(AHBDW/8)));
end case;
elsif AHBDW = 64 then
case haddr(2 downto 1) is
when "00" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)) := reversebytemig(hdata(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)) := reversebytemig(hdata(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
elsif AHBDW = 32 then
case haddr(1) is
when '0' => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto AHBDW/2));
when others => ret(AHBDW-1 downto AHBDW/2) := reversebytemig(hdata(AHBDW/2-1 downto 0));
end case;
end if;
-- HSIZE_BYTE
when others =>
if AHBDW = 128 then
case haddr(3 downto 0) is
when "0000" => ret( 1*(AHBDW/16)-1 downto 0*(AHBDW/16)) := hdata(16*(AHBDW/16)-1 downto 15*(AHBDW/16));
when "0001" => ret( 2*(AHBDW/16)-1 downto 1*(AHBDW/16)) := hdata(15*(AHBDW/16)-1 downto 14*(AHBDW/16));
when "0010" => ret( 3*(AHBDW/16)-1 downto 2*(AHBDW/16)) := hdata(14*(AHBDW/16)-1 downto 13*(AHBDW/16));
when "0011" => ret( 4*(AHBDW/16)-1 downto 3*(AHBDW/16)) := hdata(13*(AHBDW/16)-1 downto 12*(AHBDW/16));
when "0100" => ret( 1*(AHBDW/16)-1 downto 0*(AHBDW/16)) := hdata(12*(AHBDW/16)-1 downto 11*(AHBDW/16));
when "0101" => ret( 2*(AHBDW/16)-1 downto 1*(AHBDW/16)) := hdata(11*(AHBDW/16)-1 downto 10*(AHBDW/16));
when "0110" => ret( 3*(AHBDW/16)-1 downto 2*(AHBDW/16)) := hdata(10*(AHBDW/16)-1 downto 9*(AHBDW/16));
when "0111" => ret( 4*(AHBDW/16)-1 downto 3*(AHBDW/16)) := hdata( 9*(AHBDW/16)-1 downto 8*(AHBDW/16));
when "1000" => ret( 1*(AHBDW/16)-1 downto 0*(AHBDW/16)) := hdata( 8*(AHBDW/16)-1 downto 7*(AHBDW/16));
when "1001" => ret( 2*(AHBDW/16)-1 downto 1*(AHBDW/16)) := hdata( 7*(AHBDW/16)-1 downto 6*(AHBDW/16));
when "1010" => ret( 3*(AHBDW/16)-1 downto 2*(AHBDW/16)) := hdata( 6*(AHBDW/16)-1 downto 5*(AHBDW/16));
when "1011" => ret( 4*(AHBDW/16)-1 downto 3*(AHBDW/16)) := hdata( 5*(AHBDW/16)-1 downto 4*(AHBDW/16));
when "1100" => ret( 1*(AHBDW/16)-1 downto 0*(AHBDW/16)) := hdata( 4*(AHBDW/16)-1 downto 3*(AHBDW/16));
when "1101" => ret( 2*(AHBDW/16)-1 downto 1*(AHBDW/16)) := hdata( 3*(AHBDW/16)-1 downto 2*(AHBDW/16));
when "1110" => ret( 3*(AHBDW/16)-1 downto 2*(AHBDW/16)) := hdata( 2*(AHBDW/16)-1 downto 1*(AHBDW/16));
when others => ret( 4*(AHBDW/16)-1 downto 3*(AHBDW/16)) := hdata( 1*(AHBDW/16)-1 downto 0*(AHBDW/16));
end case;
elsif AHBDW = 64 then
case haddr(2 downto 0) is
when "000" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := hdata(8*(AHBDW/8)-1 downto 7*(AHBDW/8));
when "001" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := hdata(7*(AHBDW/8)-1 downto 6*(AHBDW/8));
when "010" => ret(3*(AHBDW/8)-1 downto 2*(AHBDW/8)) := hdata(6*(AHBDW/8)-1 downto 5*(AHBDW/8));
when "011" => ret(4*(AHBDW/8)-1 downto 3*(AHBDW/8)) := hdata(5*(AHBDW/8)-1 downto 4*(AHBDW/8));
when "100" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := hdata(4*(AHBDW/8)-1 downto 3*(AHBDW/8));
when "101" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := hdata(3*(AHBDW/8)-1 downto 2*(AHBDW/8));
when "110" => ret(3*(AHBDW/8)-1 downto 2*(AHBDW/8)) := hdata(2*(AHBDW/8)-1 downto 1*(AHBDW/8));
when others => ret(4*(AHBDW/8)-1 downto 3*(AHBDW/8)) := hdata(1*(AHBDW/8)-1 downto 0*(AHBDW/8));
end case;
elsif AHBDW = 32 then
case haddr(1 downto 0) is
when "00" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := hdata(4*(AHBDW/4)-1 downto 3*(AHBDW/4));
when "01" => ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)) := hdata(3*(AHBDW/4)-1 downto 2*(AHBDW/4));
when "10" => ret(3*(AHBDW/4)-1 downto 2*(AHBDW/4)) := hdata(2*(AHBDW/4)-1 downto 1*(AHBDW/4));
when others => ret(4*(AHBDW/4)-1 downto 3*(AHBDW/4)) := hdata(1*(AHBDW/4)-1 downto 0*(AHBDW/4));
end case;
end if;
end case;
return ret;
end ahbselectdatanoreplica;
function ahbselectdatanoreplicastep (
haddr : std_logic_vector(7 downto 2);
hsize : std_logic_vector(2 downto 0))
return unsigned is
variable ret : unsigned(31 downto 0);
begin -- ahbselectdatanoreplicastep
ret := (others => '0');
case AHBDW is
when 128 =>
if (hsize = HSIZE_4WORD) then
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
elsif (hsize = HSIZE_DWORD) then
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
else
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
end if;
when 64 =>
if (hsize = HSIZE_DWORD) then
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
else
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
end if;
-- 32
when others =>
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
end case;
return ret;
end ahbselectdatanoreplicastep;
function ahbselectdatanoreplicastep16 (
haddr : std_logic_vector(7 downto 2);
hsize : std_logic_vector(2 downto 0))
return unsigned is
variable ret : unsigned(31 downto 0);
begin -- ahbselectdatanoreplicastep
ret := resize(unsigned(haddr(3 downto 2)),ret'length);
return ret;
end ahbselectdatanoreplicastep16;
function ahbselectdatanoreplicamask (
haddr : std_logic_vector(6 downto 0);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
variable ret : std_logic_vector(AHBDW/4-1 downto 0);
variable ret128 : std_logic_vector(128/4-1 downto 0);
begin -- ahbselectdatanoreplicamask
ret := (others => '0');
ret128 := (others => '0');
case hsize is
when HSIZE_4WORD =>
ret(AHBDW/8-1 downto 0) := (others => '1');
when HSIZE_DWORD =>
if AHBDW = 128 then
case haddr(3) is
when '0' => ret(AHBDW/8/2-1 downto 0) := (others => '1');
when others => ret(AHBDW/8/2-1 downto 0) := (others => '1');
end case;
else
ret(AHBDW/8-1 downto 0) := (others => '1');
end if;
when HSIZE_WORD =>
if AHBDW = 128 then
case haddr(3 downto 2) is
when "00" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when "01" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when "10" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when others => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
end case;
elsif AHBDW = 64 then
case haddr(2) is
when '0' => ret(AHBDW/8/2-1 downto 0) := (others => '1');
when others => ret(AHBDW/8/2-1 downto 0) := (others => '1');
end case;
elsif AHBDW = 32 then
ret(AHBDW/8-1 downto 0) := (others => '1');
end if;
when HSIZE_HWORD =>
if AHBDW = 128 then
case haddr(3 downto 1) is
when "000" => ret128(1*(128/8/8)-1 downto 0*(128/8/8)) := (others => '1');
when "001" => ret128(2*(128/8/8)-1 downto 1*(128/8/8)) := (others => '1');
when "010" => ret128(1*(128/8/8)-1 downto 0*(128/8/8)) := (others => '1');
when "011" => ret128(2*(128/8/8)-1 downto 1*(128/8/8)) := (others => '1');
when "100" => ret128(1*(128/8/8)-1 downto 0*(128/8/8)) := (others => '1');
when "101" => ret128(2*(128/8/8)-1 downto 1*(128/8/8)) := (others => '1');
when "110" => ret128(1*(128/8/8)-1 downto 0*(128/8/8)) := (others => '1');
when others => ret128(2*(128/8/8)-1 downto 1*(128/8/8)) := (others => '1');
end case;
ret := std_logic_vector(resize(unsigned(ret128),ret'length));
elsif AHBDW = 64 then
case haddr(2 downto 1) is
when "00" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when "01" => ret(2*(AHBDW/8/4)-1 downto 1*(AHBDW/8/4)) := (others => '1');
when "10" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when others => ret(2*(AHBDW/8/4)-1 downto 1*(AHBDW/8/4)) := (others => '1');
end case;
elsif AHBDW = 32 then
case haddr(1) is
when '0' => ret(AHBDW/8/2-1 downto 0) := (others => '1');
when others => ret(AHBDW/8-1 downto AHBDW/8/2) := (others => '1');
end case;
end if;
-- HSIZE_BYTE
when others =>
if AHBDW = 128 then
case haddr(3 downto 0) is
when "0000" => ret( 0) := '1';
when "0001" => ret( 1) := '1';
when "0010" => ret( 2) := '1';
when "0011" => ret( 3) := '1';
when "0100" => ret( 0) := '1';
when "0101" => ret( 1) := '1';
when "0110" => ret( 2) := '1';
when "0111" => ret( 3) := '1';
when "1000" => ret( 0) := '1';
when "1001" => ret( 1) := '1';
when "1010" => ret( 2) := '1';
when "1011" => ret( 3) := '1';
when "1100" => ret( 0) := '1';
when "1101" => ret( 1) := '1';
when "1110" => ret( 2) := '1';
when others => ret( 3) := '1';
end case;
elsif AHBDW = 64 then
case haddr(2 downto 0) is
when "000" => ret(0) := '1';
when "001" => ret(1) := '1';
when "010" => ret(2) := '1';
when "011" => ret(3) := '1';
when "100" => ret(0) := '1';
when "101" => ret(1) := '1';
when "110" => ret(2) := '1';
when others => ret(3) := '1';
end case;
elsif AHBDW = 32 then
case haddr(1 downto 0) is
when "00" => ret(0) := '1';
when "01" => ret(1) := '1';
when "10" => ret(2) := '1';
when others => ret(3) := '1';
end case;
end if;
end case;
return ret;
end ahbselectdatanoreplicamask;
function ahbselectdatanoreplicaoutput (
haddr : std_logic_vector(7 downto 0);
counter : unsigned(31 downto 0);
hsize : std_logic_vector(2 downto 0);
rdbuffer : unsigned;
wr_count : unsigned;
replica : boolean)
return std_logic_vector is
variable ret : std_logic_vector(AHBDW-1 downto 0);
variable retrep : std_logic_vector(AHBDW-1 downto 0);
variable rdbuffer_int : unsigned(AHBDW-1 downto 0);
variable hdata : std_logic_vector(AHBDW-1 downto 0);
variable offset : unsigned(31 downto 0);
variable steps : unsigned(31 downto 0);
variable stepsint : natural;
variable hstart_offset : unsigned(31 downto 0);
variable byteOffset : unsigned(31 downto 0);
variable rdbufferByte : unsigned(AHBDW-1 downto 0);
variable hdataByte : std_logic_vector(AHBDW-1 downto 0);
begin -- ahbselectdatanoreplicaoutput
ret := (others => '0');
--hstart_offset := (others => '0');
--synopsys synthesis_off
--Print("INFO: HADDR " & tost(haddr));
--Print("INFO: hsize " & tost(hsize));
--synopsys synthesis_on
--byteOffset := shift_left( resize(unsigned(haddr(5 downto 0)),byteOffset'length) ,3);
--rdbufferByte := resize(shift_right(rdbuffer,to_integer(byteOffset)),rdbufferByte'length);
--hdataByte := std_logic_vector(rdbufferByte(AHBDW-1 downto 0));
--Print("INFO: **> byteOffset " & tost(to_integer(byteOffset)));
--Print("INFO: **> hdataByte " & tost(hdataByte));
case hsize is
when HSIZE_4WORD =>
offset := resize((unsigned(haddr(5 downto 4))&"0000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"0000000"),steps'length) + offset;
hstart_offset := (others => '0');
when HSIZE_DWORD =>
if AHBDW = 128 then
offset := resize((unsigned(haddr(5 downto 4))&"0000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"000000"),steps'length) + offset;
hstart_offset := shift_left( resize(unsigned(haddr(3 downto 3)),hstart_offset'length) ,5);
elsif AHBDW = 64 then
offset := resize((unsigned(haddr(5 downto 3))&"000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"000000"),steps'length) + offset;
hstart_offset := (others => '0');
end if;
when others =>
if AHBDW = 128 then
offset := resize((unsigned(haddr(5 downto 4))&"0000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"00000"),steps'length) + offset;
hstart_offset := shift_left( resize(unsigned(haddr(3 downto 2)),hstart_offset'length) ,5);
elsif AHBDW = 64 then
offset := resize((unsigned(haddr(5 downto 3))&"000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"00000"),steps'length) + offset;
hstart_offset := shift_left( resize(unsigned(haddr(2 downto 2)),hstart_offset'length) ,5);
elsif AHBDW = 32 then
offset := resize((unsigned(haddr(5 downto 2))&"00000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"00000"),steps'length) + offset;
hstart_offset := (others => '0');
end if;
end case;
--synopsys synthesis_off
--Print("INFO: wr_count " & tost(to_integer(wr_count)));
--Print("INFO: offset " & tost(to_integer(offset)));
--Print("INFO: steps " & tost(to_integer(steps)));
--Print("INFO: hstart_offset " & tost(to_integer(hstart_offset)));
--synopsys synthesis_on
stepsint := to_integer(steps) + to_integer(hstart_offset);
--synopsys synthesis_off
--Print("INFO: ------> stepsint" & tost(stepsint));
--synopsys synthesis_on
rdbuffer_int := resize(shift_right(rdbuffer,stepsint),rdbuffer_int'length);
hdata := std_logic_vector(rdbuffer_int(AHBDW-1 downto 0));
--synopsys synthesis_off
--Print("INFO: rdbuffer_int " & tost( std_logic_vector(rdbuffer(511 downto 0))));
--Print("INFO: rdbuffer_int " & tost( std_logic_vector(rdbuffer(1023 downto 512))));
--Print("INFO: hdata " & tost(hdata));
--synopsys synthesis_on
ret(AHBDW-1 downto 0) := reversebyte(hdata);
--synopsys synthesis_off
--Print("INFO: ret " & tost(ret));
--synopsys synthesis_on
case hsize is
when HSIZE_4WORD =>
offset := resize(unsigned(haddr) + unsigned(counter&"0000" - hstart_offset),offset'length);
when HSIZE_DWORD =>
offset := resize(unsigned(haddr) + unsigned(counter&"000" - hstart_offset),offset'length);
when others =>
offset := resize(unsigned(haddr) + unsigned(counter&"00" - hstart_offset),offset'length);
end case;
if (replica = true) then
case hsize is
when HSIZE_4WORD =>
retrep := ahbdrivedata(ret(AHBDW-1 downto 0));
when HSIZE_DWORD =>
if AHBDW = 128 then
if offset(3) = '0' then retrep := ahbdrivedata(ret(AHBDW-1 downto AHBDW/2));
else retrep := ahbdrivedata(ret(AHBDW/2-1 downto 0)); end if;
else
retrep := ahbdrivedata(ret(AHBDW-1 downto 0));
end if;
when HSIZE_WORD =>
if AHBDW = 128 then
case offset(3 downto 2) is
when "00" => retrep := ahbdrivedata(ret(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => retrep := ahbdrivedata(ret(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => retrep := ahbdrivedata(ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => retrep := ahbdrivedata(ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
elsif AHBDW = 64 then
if offset(2) = '0' then retrep := ahbdrivedata(ret(AHBDW-1 downto AHBDW/2));
else retrep := ahbdrivedata(ret(AHBDW/2-1 downto 0)); end if;
if (wr_count > 0) then
retrep := ahbdrivedata(ret(AHBDW-1 downto AHBDW/2));
end if;
retrep := ahbdrivedata(ret(AHBDW-1 downto AHBDW/2));
else
retrep := ahbdrivedata(ret(AHBDW-1 downto 0));
end if;
when HSIZE_HWORD =>
if AHBDW = 128 then
case offset(3 downto 1) is
when "000" => retrep := ahbdrivedata(ret(8*(AHBDW/8)-1 downto 7*(AHBDW/8)));
when "001" => retrep := ahbdrivedata(ret(7*(AHBDW/8)-1 downto 6*(AHBDW/8)));
when "010" => retrep := ahbdrivedata(ret(6*(AHBDW/8)-1 downto 5*(AHBDW/8)));
when "011" => retrep := ahbdrivedata(ret(5*(AHBDW/8)-1 downto 4*(AHBDW/8)));
when "100" => retrep := ahbdrivedata(ret(4*(AHBDW/8)-1 downto 3*(AHBDW/8)));
when "101" => retrep := ahbdrivedata(ret(3*(AHBDW/8)-1 downto 2*(AHBDW/8)));
when "110" => retrep := ahbdrivedata(ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)));
when others => retrep := ahbdrivedata(ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)));
end case;
elsif AHBDW = 64 then
case offset(1) is
when '0' => retrep := ahbdrivedata(ret(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when others => retrep := ahbdrivedata(ret(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
-- when "10" => retrep := ahbdrivedata(ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
-- when others => retrep := ahbdrivedata(ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
else
if offset(1) = '0' then retrep := ahbdrivedata(ret(AHBDW-1 downto AHBDW/2));
else retrep := ahbdrivedata(ret(AHBDW/2-1 downto 0)); end if;
end if;
-- HSIZE_BYTE
when others =>
if AHBDW = 128 then
case offset(2 downto 0) is
when "000" => retrep := ahbdrivedata(ret(16*(AHBDW/16)-1 downto 15*(AHBDW/16)));
when "001" => retrep := ahbdrivedata(ret(15*(AHBDW/16)-1 downto 14*(AHBDW/16)));
when "010" => retrep := ahbdrivedata(ret(14*(AHBDW/16)-1 downto 13*(AHBDW/16)));
when "011" => retrep := ahbdrivedata(ret(13*(AHBDW/16)-1 downto 12*(AHBDW/16)));
when "100" => retrep := ahbdrivedata(ret(12*(AHBDW/16)-1 downto 11*(AHBDW/16)));
when "101" => retrep := ahbdrivedata(ret(11*(AHBDW/16)-1 downto 10*(AHBDW/16)));
when "110" => retrep := ahbdrivedata(ret(10*(AHBDW/16)-1 downto 9*(AHBDW/16)));
when others => retrep := ahbdrivedata(ret( 9*(AHBDW/16)-1 downto 8*(AHBDW/16)));
end case;
elsif AHBDW = 64 then
case offset(1 downto 0) is
when "00" => retrep := ahbdrivedata(ret(8*(AHBDW/8)-1 downto 7*(AHBDW/8)));
when "01" => retrep := ahbdrivedata(ret(7*(AHBDW/8)-1 downto 6*(AHBDW/8)));
when "10" => retrep := ahbdrivedata(ret(6*(AHBDW/8)-1 downto 5*(AHBDW/8)));
when others => retrep := ahbdrivedata(ret(5*(AHBDW/8)-1 downto 4*(AHBDW/8)));
end case;
else
case offset(1 downto 0) is
when "00" => retrep := ahbdrivedata(ret(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => retrep := ahbdrivedata(ret(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => retrep := ahbdrivedata(ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => retrep := ahbdrivedata(ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
end if;
end case;
--synopsys synthesis_off
-- Print("INFO: retrep " & tost(retrep));
--synopsys synthesis_on
--ret := ahbdrivedatamig(retrep);
ret :=retrep;
end if;
return ret;
end ahbselectdatanoreplicaoutput;
function ahbselectdatanoreplicaoutput16 (
haddr : std_logic_vector(7 downto 0);
counter : unsigned(31 downto 0);
hsize : std_logic_vector(2 downto 0);
rdbuffer : unsigned;
wr_count : unsigned;
replica : boolean)
return std_logic_vector is
variable ret : std_logic_vector(AHBDW-1 downto 0);
variable retrep : std_logic_vector(AHBDW-1 downto 0);
variable rdbuffer_int : unsigned(AHBDW-1 downto 0);
variable hdata : std_logic_vector(AHBDW-1 downto 0);
variable offset : unsigned(31 downto 0);
variable steps : unsigned(31 downto 0);
variable stepsint : natural;
variable hstart_offset : unsigned(31 downto 0);
variable byteOffset : unsigned(31 downto 0);
variable rdbufferByte : unsigned(AHBDW-1 downto 0);
variable hdataByte : std_logic_vector(AHBDW-1 downto 0);
begin -- ahbselectdatanoreplicaoutput16
ret := (others => '0');
offset := resize((unsigned(haddr(3 downto 2))&"00000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"00000"),steps'length) + offset;
hstart_offset := (others => '0');
stepsint := to_integer(steps) + to_integer(hstart_offset);
rdbuffer_int := resize(shift_right(rdbuffer,stepsint),rdbuffer_int'length);
hdata := std_logic_vector(rdbuffer_int(AHBDW-1 downto 0));
ret(AHBDW-1 downto 0) := reversebyte(hdata);
offset := resize(unsigned(haddr) + unsigned(counter&"00" - hstart_offset),offset'length);
return ret;
end ahbselectdatanoreplicaoutput16;
-- purpose: extends 'hdata' to suite AHB data width. If the input vector's
-- length exceeds AHBDW the low part is returned.
function ahbdrivedatanoreplica (
hdata : std_logic_vector)
return std_logic_vector is
variable data : std_logic_vector(AHBDW-1 downto 0);
begin -- ahbdrivedatanoreplica
if AHBDW < hdata'length then
data := hdata(AHBDW+hdata'low-1 downto hdata'low);
else
data := (others => '0');
data(hdata'length-1 downto 0) := hdata;
end if;
return data;
end ahbdrivedatanoreplica;
end;
|
gpl-2.0
|
e66506b6687fde3f644586d35c883b0b
| 0.56152 | 3.591436 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep2s60-sdr/config.vhd
| 1 | 5,745 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FFFF#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
5806df3924ef538ee98a75a17b6a1eb3
| 0.645779 | 3.661568 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep2sgx90-av/testbench.vhd
| 1 | 13,550 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 21; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 4 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal dsuen, dsutx, dsurx, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal debugout : std_logic_vector(31 downto 0);
-- External Adress/data bus, flash+ssram
signal fs_addr : std_logic_vector(24 downto 0);
signal fs_data : std_logic_vector(31 downto 0);
signal io_cen : std_logic;
signal flash_cen : std_ulogic;
signal flash_oen : std_ulogic;
signal flash_wen : std_ulogic;
signal ssram_cen : std_logic;
signal ssram_wen : std_logic;
signal ssram_bw : std_logic_vector (0 to 3);
signal ssram_oen : std_ulogic;
signal ssram_clk : std_ulogic;
signal ssram_adscn : std_ulogic;
signal ssram_adspn : std_ulogic;
signal ssram_advn : std_ulogic;
signal datazz : std_logic_vector(3 downto 0);
signal flash_addr : std_logic_vector(romdepth downto 0);
-- muxed data bus
signal prd : std_logic_vector(31 downto 0);
signal ssd : std_logic_vector(31 downto 0);
-- ddr memory
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_odt : std_logic_vector(1 downto 0);
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (7 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_dqsn : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_rdqs : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (13 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq, ddr_dq2 : std_logic_vector (63 downto 0); -- ddr data
signal phy_gtx_clk : std_logic;
signal phy_mii_data : std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal ft245_data : std_logic_vector (7 downto 0);
signal ft245_rdn : std_logic;
signal ft245_wr : std_logic;
signal ft245_rxfn : std_logic;
signal ft245_txen : std_logic;
signal ft245_pwrenn : std_logic;
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
component sram32 is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1Kx32)
echk : integer := 0; -- Generate EDAC checksum
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"); -- File to read from
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(31 downto 0);
lb : in std_logic;
ub : in std_logic;
ce : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end component;
begin
-- clock and reset
-- 100 MHz
clk <= not clk after 5 ns;
-- ddr_clkin <= not clk after ct * 1 ns;
rst <= dsurst;
rxd1 <= '1';
-- ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech,
ncpu, disas, dbguart, pclow )
port map (
resetn => rst,
clk => clk,
errorn => error,
fs_addr => fs_addr,
fs_data => fs_data,
io_cen => io_cen,
flash_cen => flash_cen,
flash_oen => flash_oen,
flash_wen => flash_wen,
ssram_cen => ssram_cen,
ssram_wen => ssram_wen,
ssram_bw => ssram_bw,
ssram_oen => ssram_oen,
ssram_clk => ssram_clk,
ssram_adscn => ssram_adscn,
ssram_adspn => ssram_adspn,
ssram_advn => ssram_advn,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_odt => ddr_odt,
ddr_web => ddr_web, -- ddr write enable
ddr_rasb => ddr_rasb, -- ddr ras
ddr_casb => ddr_casb, -- ddr cas
ddr_dm => ddr_dm, -- ddr dm
ddr_dqs => ddr_dqs, -- ddr dqs
ddr_ad => ddr_ad, -- ddr address
ddr_ba => ddr_ba, -- ddr bank address
ddr_dq => ddr_dq, -- ddr data
phy_gtx_clk => phy_gtx_clk,
phy_mii_data => phy_mii_data,
phy_tx_clk => phy_tx_clk,
phy_rx_clk => phy_rx_clk,
phy_rx_data => phy_rx_data,
phy_dv => phy_dv,
phy_rx_er => phy_rx_er,
phy_col => phy_col,
phy_crs => phy_crs,
phy_tx_data => phy_tx_data,
phy_tx_en => phy_tx_en,
phy_tx_er => phy_tx_er,
phy_mii_clk => phy_mii_clk,
dsuact => dsuact,
rxd1 => rxd1,
txd1 => txd1,
gpio => gpio,
ft245_data => ft245_data,
ft245_rdn => ft245_rdn,
ft245_wr => ft245_wr,
ft245_rxfn => ft245_rxfn,
ft245_txen => ft245_txen,
ft245_pwrenn => ft245_pwrenn
);
datazz <= "HHHH";
ssram0 : cy7c1380d generic map (fname => sramfile)
port map(
ioDq(35 downto 32) => datazz, ioDq(31 downto 0) => fs_data,
iAddr => fs_addr(19 downto 1), iMode => gnd,
inGW => vcc, inBWE => ssram_wen, inADV => ssram_advn,
inADSP => ssram_adspn, inADSC => ssram_adscn,
iClk => ssram_clk,
inBwa => ssram_bw(3), inBwb => ssram_bw(2),
inBwc => ssram_bw(1), inBwd => ssram_bw(0),
inOE => ssram_oen, inCE1 => ssram_cen,
iCE2 => vcc, inCE3 => gnd, iZz => gnd);
-- 16 bit prom
flash_addr <= '0'&fs_addr(romdepth-1 downto 0);
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (a => flash_addr(romdepth-1 downto 0), d => fs_data(31 downto 16), lb => '0', ub => '0',
ce => flash_cen, we => flash_wen, oe => flash_oen);
-- prd(23 downto 0) <= (others => '0');
-- data mux
-- fs_data <= ssd when ssram_oen='0' and ssram_cen='0' else
-- prd when flash_oen='0' and flash_cen='0' else
-- (others => 'Z');
-- data <= buskeep(data), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, fs_addr(20 downto 1), fs_data,
io_cen, flash_oen, flash_wen, open);
error <= 'H'; -- ERROR pull-up
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 2.5)
port map(a => ddr_dq, b => ddr_dq2);
--DDR2
ddr2mem0: ddr2ram
generic map (
width => 64, abits => 14, babits => 2,
colbits => 10, implbanks => 1, fname => sdramfile
)
port map (
ck => ddr_clk(0), ckn => ddr_clkb(0), cke => ddr_cke(0), csn => ddr_csb(0), odt => ddr_odt(0),
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web, dm => ddr_dm, ba => ddr_ba, a => ddr_ad,
dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn
);
-- ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
ddr_dqsn <= (others => 'U');
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
sd <= buskeep(sd), (others => 'H') after 250 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
gpl-2.0
|
81360fb44bfc6f4be5cd3c8509c1c229
| 0.568561 | 3.073259 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/spi/spi2ahb.vhd
| 1 | 2,979 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahb
-- File: spi2ahb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- See spi2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.conv_std_logic_vector;
library gaisler;
use gaisler.spi.all;
entity spi2ahb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end entity spi2ahb;
architecture rtl of spi2ahb is
signal spi2ahbi : spi2ahb_in_type;
begin
bridge : spi2ahbx
generic map (
hindex => hindex,
oepol => oepol,
filter => filter,
cpol => cpol,
cpha => cpha)
port map (
rstn => rstn,
clk => clk,
ahbi => ahbi,
ahbo => ahbo,
spii => spii,
spio => spio,
spi2ahbi => spi2ahbi,
spi2ahbo => open);
spi2ahbi.en <= '1';
spi2ahbi.haddr <= conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
spi2ahbi.hmask <= conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
end architecture rtl;
|
gpl-2.0
|
8fd0d4a53c495ed6be03a6d28d6834bd
| 0.569319 | 3.889034 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-terasic-de0-nano/testbench.vhd
| 1 | 6,560 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2012 Aeroflex Gaisler
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
romdepth : integer := 22 -- rom address depth (flash 4 MB)
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec";
constant sdramfile : string := "ram.srec";
signal clock_50 : std_logic := '0';
signal led : std_logic_vector(7 downto 0);
signal key : std_logic_vector(1 downto 0);
signal sw : std_logic_vector(3 downto 0);
signal dram_ba : std_logic_vector(1 downto 0);
signal dram_dqm : std_logic_vector(1 downto 0);
signal dram_ras_n : std_ulogic;
signal dram_cas_n : std_ulogic;
signal dram_cke : std_ulogic;
signal dram_clk : std_ulogic;
signal dram_we_n : std_ulogic;
signal dram_cs_n : std_ulogic;
signal dram_dq : std_logic_vector(15 downto 0);
signal dram_addr : std_logic_vector(12 downto 0);
signal epcs_data0 : std_logic;
signal epcs_dclk : std_logic;
signal epcs_ncso : std_logic;
signal epcs_asdo : std_logic;
signal i2c_sclk : std_logic;
signal i2c_sdat : std_logic;
signal g_sensor_cs_n : std_ulogic;
signal g_sensor_int : std_ulogic;
signal adc_cs_n : std_ulogic;
signal adc_saddr : std_ulogic;
signal adc_sclk : std_ulogic;
signal adc_sdat : std_ulogic;
signal gpio_2 : std_logic_vector(12 downto 0);
signal gpio_2_in : std_logic_vector(2 downto 0);
signal gpio_1_in : std_logic_vector(1 downto 0);
signal gpio_1 : std_logic_vector(33 downto 0);
signal gpio_0_in : std_logic_vector(1 downto 0);
signal gpio_0 : std_logic_vector(33 downto 0);
begin
clock_50 <= not clock_50 after 10 ns; --50 MHz clk
key(0) <= '0', '1' after 300 ns;
key(1) <= '1'; -- DSU break, disabled
sw <= (others => 'H');
gpio_0 <= (others => 'H');
gpio_0_in <= (others => 'H');
gpio_1 <= (others => 'H');
gpio_1_in <= (others => 'H');
gpio_2 <= (others => 'H');
gpio_2_in <= (others => 'H');
led(5 downto 0) <= (others => 'H');
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (
clock_50 => clock_50,
led => led,
key => key,
sw => sw,
dram_ba => dram_ba,
dram_dqm => dram_dqm,
dram_ras_n => dram_ras_n,
dram_cas_n => dram_cas_n,
dram_cke => dram_cke,
dram_clk => dram_clk,
dram_we_n => dram_we_n,
dram_cs_n => dram_cs_n,
dram_dq => dram_dq,
dram_addr => dram_addr,
epcs_data0 => epcs_data0,
epcs_dclk => epcs_dclk,
epcs_ncso => epcs_ncso,
epcs_asdo => epcs_asdo,
i2c_sclk => i2c_sclk,
i2c_sdat => i2c_sdat,
g_sensor_cs_n => g_sensor_cs_n,
g_sensor_int => g_sensor_int,
adc_cs_n => adc_cs_n,
adc_saddr => adc_saddr,
adc_sclk => adc_sclk,
adc_sdat => adc_sdat,
gpio_2 => gpio_2,
gpio_2_in => gpio_2_in,
gpio_1_in => gpio_1_in,
gpio_1 => gpio_1,
gpio_0_in => gpio_0_in,
gpio_0 => gpio_0);
sd1 : if (CFG_SDCTRL /= 0) generate
u1: entity work.mt48lc16m16a2 generic map (addr_bits => 13, col_bits => 8, index => 1024, fname => sdramfile)
PORT MAP(
Dq => dram_dq, Addr => dram_addr, Ba => dram_ba, Clk => dram_clk,
Cke => dram_cke, Cs_n => dram_cs_n, Ras_n => dram_ras_n,
Cas_n => dram_cas_n, We_n => dram_we_n, Dqm => dram_dqm);
end generate;
dram_dq <= buskeep(dram_dq) after 5 ns;
spif : if CFG_SPIMCTRL /= 0 generate
spi0: spi_flash
generic map (
ftype => 4,
debug => 0,
fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
memoffset => CFG_SPIMCTRL_OFFSET)
port map (
sck => epcs_dclk,
di => epcs_asdo,
do => epcs_data0,
csn => epcs_ncso,
sd_cmd_timeout => open,
sd_data_timeout => open);
end generate;
iuerr : process
begin
wait for 2500 ns;
if to_x01(led(6)) = '1' then wait on led(6); end if;
assert (to_x01(led(6)) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
|
gpl-2.0
|
97fc1f5d2b085da407266a91361dc7fa
| 0.539634 | 3.532579 | false | false | false | false |
joaocarlos/udlx-verilog
|
fpga/syn/clk_10mhz.vhd
| 1 | 14,771 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: clk_10mhz.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 173 11/01/2011 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY clk_10mhz IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END clk_10mhz;
ARCHITECTURE SYN OF clk_10mhz IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 5,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=clk_10mhz",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_10mhz.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_10mhz.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_10mhz.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_10mhz.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_10mhz.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_10mhz.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_10mhz_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
lgpl-3.0
|
fd92e762e8b1c8a67fe133299ba70806
| 0.700088 | 3.361629 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-terasic-de2-115/config.vhd
| 1 | 6,970 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#0d0007#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 1;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 1;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 1;
constant CFG_SPICTRL_FT : integer := 0;
-- SPI to AHB bridge
constant CFG_SPI2AHB : integer := 0;
constant CFG_SPI2AHB_APB : integer := 0;
constant CFG_SPI2AHB_ADDRH : integer := 16#0#;
constant CFG_SPI2AHB_ADDRL : integer := 16#0#;
constant CFG_SPI2AHB_MASKH : integer := 16#0#;
constant CFG_SPI2AHB_MASKL : integer := 16#0#;
constant CFG_SPI2AHB_RESEN : integer := 0;
constant CFG_SPI2AHB_FILTER : integer := 2;
constant CFG_SPI2AHB_CPOL : integer := 0;
constant CFG_SPI2AHB_CPHA : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
faa1d0f85416aac0e589436fbdd6d777
| 0.648494 | 3.578029 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica04_OsciladorEnable/div.vhd
| 1 | 1,723 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity div is
port(
clkdiv: in std_logic;
indiv: in std_logic_vector(3 downto 0);
outdiv: inout std_logic);
end div;
architecture adiv of div is
signal sdiv: std_logic_vector(20 downto 0);
begin
pdiv: process (clkdiv)
begin
if (clkdiv'event and clkdiv = '1') then
--sdiv <= sdiv + 1;
case indiv is
when "0000" =>
if (sdiv > "100000000000000000000") then
outdiv <= not(outdiv);
sdiv <= "000000000000000000000";
else
sdiv <= sdiv + 1;
end if;
when "0001" =>
if (sdiv > "01000000000000000000") then
outdiv <= not(outdiv);
sdiv <= "000000000000000000000";
else
sdiv <= sdiv + 1;
end if;
when "0011" =>
if (sdiv > "00100000000000000000") then
outdiv <= not(outdiv);
sdiv <= "000000000000000000000";
else
sdiv <= sdiv + 1;
end if;
when "0111" =>
if (sdiv > "00010000000000000000") then
outdiv <= not(outdiv);
sdiv <= "000000000000000000000";
else
sdiv <= sdiv + 1;
end if;
when "1111" =>
if (sdiv > "00001000000000000000") then
outdiv <= not(outdiv);
sdiv <= "000000000000000000000";
else
sdiv <= sdiv + 1;
end if;
when "1110" =>
if (sdiv > "00000100000000000000") then
outdiv <= not(outdiv);
sdiv <= "000000000000000000000";
else
sdiv <= sdiv + 1;
end if;
when others => null;
end case;
end if;
end process pdiv;
end adiv;
|
apache-2.0
|
c72a55736ad056dd17f8bcb2e2009b1e
| 0.534533 | 4.131894 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702/leon3_zc702_stub_sim.vhd
| 2 | 9,621 |
-------------------------------------------------------------------------------
-- leon3_zc702_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity leon3_zc702_stub is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
S_AXI_GP0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_arready : out STD_LOGIC;
S_AXI_GP0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arvalid : in STD_LOGIC;
S_AXI_GP0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_awready : out STD_LOGIC;
S_AXI_GP0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awvalid : in STD_LOGIC;
S_AXI_GP0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_bready : in STD_LOGIC;
S_AXI_GP0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_bvalid : out STD_LOGIC;
S_AXI_GP0_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_rlast : out STD_LOGIC;
S_AXI_GP0_rready : in STD_LOGIC;
S_AXI_GP0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_rvalid : out STD_LOGIC;
S_AXI_GP0_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_wid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_wlast : in STD_LOGIC;
S_AXI_GP0_wready : out STD_LOGIC;
S_AXI_GP0_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_wvalid : in STD_LOGIC
);
end leon3_zc702_stub;
architecture STRUCTURE of leon3_zc702_stub is
signal clk : std_logic := '0';
signal clk0 : std_logic := '0';
signal clk1 : std_logic := '0';
signal rst : std_logic := '0';
type memstatetype is (idle, read1, read2, read3, write1, write2, write3);
type blane is array (0 to 2**18-1) of natural;
type memtype is array (0 to 3) of blane;
constant abits : integer := 20;
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**abits)-1)) of BYTE;
type regtype is record
memstate : memstatetype;
addr : integer;
arlen : integer;
mem : memtype;
rcnt : integer;
end record;
signal S_AXI_GP0_rvalid_i : std_logic;
signal r, rin : regtype;
begin
clk0 <= not clk0 after 6.0 ns; -- 83.33 MHz
clk1 <= not clk1 after 2.5 ns; -- 200 MHz
rst <= '1' after 1 us;
S_AXI_GP0_rvalid <= S_AXI_GP0_rvalid_i;
FCLK_CLK0 <= clk0;
clk <= clk0;
FCLK_CLK1 <= clk1;
-- FCLK_CLK2 <= clk2;
-- FCLK_CLK3 <= clk3;
FCLK_RESET0_N <= rst;
mem0 : process(clk)
variable MEMA : MEM;
variable L1 : line;
variable FIRST : boolean := true;
variable ADR : std_logic_vector(19 downto 0);
variable BUF : std_logic_vector(31 downto 0);
variable CH : character;
variable ai : integer := 0;
variable len : integer := 0;
file TCF : text open read_mode is "ram.srec";
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable memstate : memstatetype;
variable addr : integer;
-- variable len : integer;
-- variable mem : memtype;
variable rcnt : integer;
begin
if FIRST then
-- if clear = 1 then MEMA := (others => X"00"); end if;
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
when others => next;
end case;
hread(L1, recdata);
recaddr(31 downto abits) := (others => '0');
ai := conv_integer(recaddr);
for i in 0 to 15 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
if ai = 0 then
ai := 1;
end if;
end if;
end if;
end if;
end loop;
FIRST := false;
elsif rising_edge(clk) then
case memstate is
when idle =>
S_AXI_GP0_arready <= '0'; S_AXI_GP0_rvalid_i <= '0'; S_AXI_GP0_rlast <= '0';
S_AXI_GP0_awready <= '0'; S_AXI_GP0_wready <= '0'; S_AXI_GP0_bvalid <= '0';
if S_AXI_GP0_arvalid = '1' then
memstate := read1; S_AXI_GP0_arready <= '1';
elsif S_AXI_GP0_awvalid = '1' then
memstate := write1; S_AXI_GP0_awready <= '1';
end if;
when read1 =>
addr:= conv_integer(S_AXI_GP0_araddr(19 downto 0));
len := conv_integer(S_AXI_GP0_arlen);
S_AXI_GP0_arready <= '0'; memstate := read2; rcnt := 23;
when read2 =>
if rcnt /= 0 then rcnt := rcnt - 1;
else
S_AXI_GP0_rvalid_i <= '1';
if len = 0 then S_AXI_GP0_rlast <= '1'; end if;
if (S_AXI_GP0_rready and S_AXI_GP0_rvalid_i) = '1' then
if len = 0 then
S_AXI_GP0_rlast <= '0'; S_AXI_GP0_rvalid_i <= '0';
memstate := idle;
else
addr := addr + 4; len := len - 1;
if len = 0 then S_AXI_GP0_rlast <= '1'; end if;
end if;
end if;
for i in 0 to 3 loop
S_AXI_GP0_rdata(i*8+7 downto i*8) <= MEMA(addr+3-i);
end loop;
end if;
when write1 =>
addr:= conv_integer(S_AXI_GP0_awaddr(19 downto 0));
len := conv_integer(S_AXI_GP0_awlen);
S_AXI_GP0_awready <= '0'; memstate := write2; rcnt := 0;
when write2 =>
if rcnt /= 0 then rcnt := rcnt - 1;
else
memstate := write3;
S_AXI_GP0_wready <= '1';
end if;
when write3 =>
if S_AXI_GP0_wvalid = '1' then
for i in 0 to 3 loop
if S_AXI_GP0_wstrb(i) = '1' then
MEMA(addr+3-i) := S_AXI_GP0_wdata(i*8+7 downto i*8);
end if;
end loop;
if (len = 0) or (S_AXI_GP0_wlast = '1') then
memstate := idle; S_AXI_GP0_wready <= '0'; S_AXI_GP0_bvalid <= '1';
else
addr := addr + 1; len := len - 1;
end if;
end if;
when others =>
end case;
end if;
end process;
S_AXI_GP0_bid <= (others => '0');
S_AXI_GP0_bresp <= (others => '0');
S_AXI_GP0_rresp <= (others => '0');
S_AXI_GP0_rid <= (others => '0');
DDR_addr <= (others => '0');
DDR_ba <= (others => '0');
DDR_cas_n <= '0';
DDR_ck_n <= '0';
DDR_ck_p <= '0';
DDR_cke <= '0';
DDR_cs_n <= '0';
DDR_dm <= (others => '0');
DDR_dq <= (others => '0');
DDR_dqs_n <= (others => '0');
DDR_dqs_p <= (others => '0');
DDR_odt <= '0';
DDR_ras_n <= '0';
DDR_reset_n <= '0';
DDR_we_n <= '0';
FIXED_IO_ddr_vrn <= '0';
FIXED_IO_ddr_vrp <= '0';
FIXED_IO_mio <= (others => '0');
FIXED_IO_ps_clk <= '0';
FIXED_IO_ps_porb <= '0';
FIXED_IO_ps_srstb <= '0';
end architecture STRUCTURE;
|
gpl-2.0
|
0e6697b1be4866e3b1ea4c2b267b1bef
| 0.52136 | 3.129798 | false | false | false | false |
aortiz49/MIPS-Processor
|
Testbenches/add32_tb.vhd
| 1 | 1,632 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity add32_tb is
end add32_tb;
architecture TB of add32_tb is
component add32
port(
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
cin : in std_logic;
cout : out std_logic;
sum : out std_logic_vector(31 downto 0)
);
end component;
signal in1 : std_logic_vector(31 downto 0);
signal in0 : std_logic_vector(31 downto 0);
signal sum : std_logic_vector(31 downto 0);
signal cin : std_logic;
signal cout : std_logic;
begin -- TB
UUT: entity work.add32
port map(
in1 => in1,
in0 => in0,
cin => cin,
cout => cout,
sum => sum
);
process
begin
-- test two positive numbers
cin <= '0';
in1 <= conv_std_logic_vector(1234, in1'length);
in0 <= conv_std_logic_vector(4321, in0'length);
wait for 20 ns;
-- test 2 negatve nums
in1 <= conv_std_logic_vector(-500, in1'length);
in0 <= conv_std_logic_vector(-250, in0'length);
wait for 20 ns;
--test one + and one -
in1 <= conv_std_logic_vector(2048, in1'length);
in0 <= conv_std_logic_vector(-1000, in0'length);
wait for 20 ns;
-- oth unsigned
in1 <= conv_std_logic_vector(5000, in1'length);
in0 <= conv_std_logic_vector(1000, in0'length);
wait for 20 ns;
-- oth FFFF
in1 <= x"FFFFFFFF";
in0 <= x"FFFFFFFF";
wait for 20 ns;
--oth are 0
in1 <= x"00000000";
in0 <= x"00000000";
wait for 20 ns;
-- oth are 80 80
in1 <= x"80000000";
in0 <= x"80000000";
wait for 20 ns;
wait;
end process;
end TB;
|
mit
|
fa8a298df1c842e48ea782060c75fa28
| 0.618873 | 2.636511 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/div00.vhd
| 1 | 1,659 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity div00 is
port(
clkdiv: in std_logic ;
indiv: in std_logic_vector ( 3 downto 0 );
outdiv: inout std_logic );
end;
architecture div0 of div00 is
signal sdiv: std_logic_vector(11 downto 0);
begin
pdiv: process (clkdiv)
begin
if (clkdiv'event and clkdiv = '1') then
case indiv is
when "0000" =>
if (sdiv > "000001000000") then
outdiv <= not(outdiv);
sdiv <= (others => '0');
else
sdiv <= sdiv + 1;
end if;
when "0001" =>
if (sdiv > "000010000000") then
outdiv <= not(outdiv);
sdiv <= (others => '0');
else
sdiv <= sdiv + 1;
end if;
when "0011" =>
if (sdiv > "000100000000") then
outdiv <= not(outdiv);
sdiv <= (others => '0');
else
sdiv <= sdiv + 1;
end if;
when "0111" =>
if (sdiv > "001000000000") then
outdiv <= not(outdiv);
sdiv <= (others => '0');
else
sdiv <= sdiv + 1;
end if;
when "1111" =>
if (sdiv > "010000000000") then
outdiv <= not(outdiv);
sdiv <= (others => '0');
else
sdiv <= sdiv + 1;
end if;
when "1110" =>
if (sdiv > "100000000000") then
outdiv <= not(outdiv);
sdiv <= (others => '0');
else
sdiv <= sdiv + 1;
end if;
when others => null;
end case;
end if;
end process pdiv;
end div0;
|
apache-2.0
|
0fe1c1c3835e933fd562b06606b4070b
| 0.470163 | 3.779043 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/grlib/modgen/leaves.vhd
| 6 | 682,913 |
-----------------------------------------------------------------------------
-- File: leaves.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: A set of multipliers generated from the Arithmetic Module
-- Generator at Norwegian University of Science and Technology.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package blocks is
component FLIPFLOP
port (
DIN, CLK: in std_logic;
DOUT: out std_logic
);
end component;
component DBLCADDER_32_32
port(OPA: in std_logic_vector(0 to 31);
OPB: in std_logic_vector(0 to 31);
CIN: in std_logic;
PHI: in std_logic;
SUM: out std_logic_vector(0 to 31);
COUT: out std_logic);
end component;
component FULL_ADDER
port
(
DATA_A, DATA_B, DATA_C: in std_logic;
SAVE, CARRY: out std_logic
);
end component;
component HALF_ADDER
port
(
DATA_A, DATA_B: in std_logic;
SAVE, CARRY: out std_logic
);
end component;
component R_GATE
port
(
INA, INB, INC: in std_logic;
PPBIT: out std_logic
);
end component;
component DECODER
port
(
INA, INB, INC: in std_logic;
TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic
);
end component;
component PP_LOW
port
(
ONEPOS, ONENEG, TWONEG: in std_logic;
INA, INB: in std_logic;
PPBIT: out std_logic
);
end component;
component PP_MIDDLE
port
(
ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
INA, INB, INC, IND: in std_logic;
PPBIT: out std_logic
);
end component;
component PP_HIGH
port
(
ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
INA, INB: in std_logic;
PPBIT: out std_logic
);
end component;
component BLOCK0
port
(
A,B,PHI: in std_logic;
POUT,GOUT: out std_logic
);
end component;
component INVBLOCK
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK1
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK1A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component BLOCK2
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end component;
component BLOCK2A
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end component;
component PRESTAGE_32
port
(
A: in std_logic_vector(0 to 31);
B: in std_logic_vector(0 to 31);
CIN: in std_logic;
PHI: in std_logic;
POUT: out std_logic_vector(0 to 31);
GOUT: out std_logic_vector(0 to 32)
);
end component;
component XXOR1
port
(
A,B,GIN,PHI:in std_logic;
SUM:out std_logic
);
end component;
component XXOR2
port
(
A,B,GIN,PHI:in std_logic;
SUM:out std_logic
);
end component;
component DBLCTREE_32
port
(
PIN:in std_logic_vector(0 to 31);
GIN:in std_logic_vector(0 to 32);
PHI:in std_logic;
GOUT:out std_logic_vector(0 to 32);
POUT:out std_logic_vector(0 to 0)
);
end component;
component XORSTAGE_32
port
(
A: in std_logic_vector(0 to 31);
B: in std_logic_vector(0 to 31);
PBIT: in std_logic;
PHI: in std_logic;
CARRY: in std_logic_vector(0 to 32);
SUM: out std_logic_vector(0 to 31);
COUT: out std_logic
);
end component;
component DBLC_0_32
port
(
PIN: in std_logic_vector(0 to 31);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 30);
GOUT: out std_logic_vector(0 to 32)
);
end component;
component DBLC_1_32
port
(
PIN: in std_logic_vector(0 to 30);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 28);
GOUT: out std_logic_vector(0 to 32)
);
end component;
component DBLC_2_32
port
(
PIN: in std_logic_vector(0 to 28);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 24);
GOUT: out std_logic_vector(0 to 32)
);
end component;
component DBLC_3_32
port
(
PIN: in std_logic_vector(0 to 24);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 16);
GOUT: out std_logic_vector(0 to 32)
);
end component;
component DBLC_4_32
port
(
PIN: in std_logic_vector(0 to 16);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 0);
GOUT: out std_logic_vector(0 to 32)
);
end component;
component PRESTAGE_64
port
(
A: in std_logic_vector(0 to 63);
B: in std_logic_vector(0 to 63);
CIN: in std_logic;
PHI: in std_logic;
POUT: out std_logic_vector(0 to 63);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLCTREE_64
port
(
PIN:in std_logic_vector(0 to 63);
GIN:in std_logic_vector(0 to 64);
PHI:in std_logic;
GOUT:out std_logic_vector(0 to 64);
POUT:out std_logic_vector(0 to 0)
);
end component;
component XORSTAGE_64
port
(
A: in std_logic_vector(0 to 63);
B: in std_logic_vector(0 to 63);
PBIT: in std_logic;
PHI: in std_logic;
CARRY: in std_logic_vector(0 to 64);
SUM: out std_logic_vector(0 to 63);
COUT: out std_logic
);
end component;
component DBLC_0_64
port
(
PIN: in std_logic_vector(0 to 63);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 62);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLC_1_64
port
(
PIN: in std_logic_vector(0 to 62);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 60);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLC_2_64
port
(
PIN: in std_logic_vector(0 to 60);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 56);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLC_3_64
port
(
PIN: in std_logic_vector(0 to 56);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 48);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLC_4_64
port
(
PIN: in std_logic_vector(0 to 48);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 32);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLC_5_64
port
(
PIN: in std_logic_vector(0 to 32);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 0);
GOUT: out std_logic_vector(0 to 64)
);
end component;
component DBLC_0_128
port
(
PIN: in std_logic_vector(0 to 127);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 126);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLC_1_128
port
(
PIN: in std_logic_vector(0 to 126);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 124);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLC_2_128
port
(
PIN: in std_logic_vector(0 to 124);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 120);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLC_3_128
port
(
PIN: in std_logic_vector(0 to 120);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 112);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLC_4_128
port
(
PIN: in std_logic_vector(0 to 112);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 96);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLC_5_128
port
(
PIN: in std_logic_vector(0 to 96);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 64);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLC_6_128
port
(
PIN: in std_logic_vector(0 to 64);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 0);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component PRESTAGE_128
port
(
A: in std_logic_vector(0 to 127);
B: in std_logic_vector(0 to 127);
CIN: in std_logic;
PHI: in std_logic;
POUT: out std_logic_vector(0 to 127);
GOUT: out std_logic_vector(0 to 128)
);
end component;
component DBLCTREE_128
port
(
PIN:in std_logic_vector(0 to 127);
GIN:in std_logic_vector(0 to 128);
PHI:in std_logic;
GOUT:out std_logic_vector(0 to 128);
POUT:out std_logic_vector(0 to 0)
);
end component;
component XORSTAGE_128
port
(
A: in std_logic_vector(0 to 127);
B: in std_logic_vector(0 to 127);
PBIT: in std_logic;
PHI: in std_logic;
CARRY: in std_logic_vector(0 to 128);
SUM: out std_logic_vector(0 to 127);
COUT: out std_logic
);
end component;
component BOOTHCODER_18_18
port
(
OPA: in std_logic_vector(0 to 17);
OPB: in std_logic_vector(0 to 17);
SUMMAND: out std_logic_vector(0 to 188)
);
end component;
component WALLACE_18_18
port
(
SUMMAND: in std_logic_vector(0 to 188);
CARRY: out std_logic_vector(0 to 33);
SUM: out std_logic_vector(0 to 34)
);
end component;
component DBLCADDER_64_64
port
(
OPA:in std_logic_vector(0 to 63);
OPB:in std_logic_vector(0 to 63);
CIN:in std_logic;
PHI:in std_logic;
SUM:out std_logic_vector(0 to 63);
COUT:out std_logic
);
end component;
component BOOTHCODER_34_10
port
(
OPA: in std_logic_vector(0 to 33);
OPB: in std_logic_vector(0 to 9);
SUMMAND: out std_logic_vector(0 to 184)
);
end component;
component WALLACE_34_10
port
(
SUMMAND: in std_logic_vector(0 to 184);
CARRY: out std_logic_vector(0 to 41);
SUM: out std_logic_vector(0 to 42)
);
end component;
component BOOTHCODER_34_18
port
(
OPA: in std_logic_vector(0 to 33);
OPB: in std_logic_vector(0 to 17);
SUMMAND: out std_logic_vector(0 to 332)
);
end component;
component WALLACE_34_18
port
(
SUMMAND: in std_logic_vector(0 to 332);
CARRY: out std_logic_vector(0 to 49);
SUM: out std_logic_vector(0 to 50)
);
end component;
component BOOTHCODER_34_34
port
(
OPA: in std_logic_vector(0 to 33);
OPB: in std_logic_vector(0 to 33);
SUMMAND: out std_logic_vector(0 to 628)
);
end component;
component WALLACE_34_34
port
(
SUMMAND: in std_logic_vector(0 to 628);
CARRY: out std_logic_vector(0 to 65);
SUM: out std_logic_vector(0 to 66)
);
end component;
component DBLCADDER_128_128
port
(
OPA:in std_logic_vector(0 to 127);
OPB:in std_logic_vector(0 to 127);
CIN:in std_logic;
PHI:in std_logic;
SUM:out std_logic_vector(0 to 127);
COUT:out std_logic
);
end component;
component MULTIPLIER_18_18
generic (mulpipe : integer := 0);
port(MULTIPLICAND: in std_logic_vector(0 to 17);
MULTIPLIER: in std_logic_vector(0 to 17);
PHI: in std_ulogic;
holdn: in std_ulogic;
RESULT: out std_logic_vector(0 to 63));
end component;
component MULTIPLIER_34_10
port(MULTIPLICAND: in std_logic_vector(0 to 33);
MULTIPLIER: in std_logic_vector(0 to 9);
PHI: in std_logic;
RESULT: out std_logic_vector(0 to 63));
end component;
component MULTIPLIER_34_18
port(MULTIPLICAND: in std_logic_vector(0 to 33);
MULTIPLIER: in std_logic_vector(0 to 17);
PHI: in std_logic;
RESULT: out std_logic_vector(0 to 63));
end component;
component MULTIPLIER_34_34
generic (mulpipe : integer := 0);
port(MULTIPLICAND: in std_logic_vector(0 to 33);
MULTIPLIER: in std_logic_vector(0 to 33);
PHI: in std_logic;
holdn: in std_ulogic;
RESULT: out std_logic_vector(0 to 127));
end component;
end;
------------------------------------------------------------
-- START: Entities used within the Modified Booth Recoding
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity FLIPFLOP is
port
(
DIN: in std_logic;
CLK: in std_logic;
DOUT: out std_logic
);
end FLIPFLOP;
architecture FLIPFLOP of FLIPFLOP is
begin
process(CLK)
begin
if(CLK='1')and(CLK'event)then
DOUT <= DIN;
end if;
end process;
end FLIPFLOP;
library ieee;
use ieee.std_logic_1164.all;
entity PP_LOW is
port
(
ONEPOS, ONENEG, TWONEG: in std_logic;
INA, INB: in std_logic;
PPBIT: out std_logic
);
end PP_LOW;
architecture PP_LOW of PP_LOW is
begin
PPBIT <= (ONEPOS and INA) or (ONENEG and INB) or TWONEG;
end PP_LOW;
library ieee;
use ieee.std_logic_1164.all;
entity PP_MIDDLE is
port
(
ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
INA, INB, INC, IND: in std_logic;
PPBIT: out std_logic
);
end PP_MIDDLE;
architecture PP_MIDDLE of PP_MIDDLE is
begin
PPBIT <= not((not(INA and TWOPOS)) and (not(INB and TWONEG)) and (not(INC and ONEPOS)) and (not(IND and ONENEG)));
end PP_MIDDLE;
library ieee;
use ieee.std_logic_1164.all;
entity PP_HIGH is
port
(
ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
INA, INB: in std_logic;
PPBIT: out std_logic
);
end PP_HIGH;
architecture PP_HIGH of PP_HIGH is
begin
PPBIT <= not ((INA and ONEPOS) or (INB and ONENEG) or (INA and TWOPOS) or (INB and TWONEG));
end PP_HIGH;
library ieee;
use ieee.std_logic_1164.all;
entity R_GATE is
port
(
INA, INB, INC: in std_logic;
PPBIT: out std_logic
);
end R_GATE;
architecture R_GATE of R_GATE is
begin
PPBIT <= (not(INA and INB)) and INC;
end R_GATE;
library ieee;
use ieee.std_logic_1164.all;
entity DECODER is
port
(
INA, INB, INC: in std_logic;
TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic
);
end DECODER;
architecture DECODER of DECODER is
begin
TWOPOS <= not(not(INA and INB and (not INC)));
TWONEG <= not(not((not INA) and (not INB) and INC));
ONEPOS <= ((not INA) and INB and (not INC)) or ((not INC) and (not INB) and INA);
ONENEG <= (INA and (not INB) and INC) or (INC and INB and (not INA));
end DECODER;
library ieee;
use ieee.std_logic_1164.all;
entity FULL_ADDER is
port
(
DATA_A, DATA_B, DATA_C: in std_logic;
SAVE, CARRY: out std_logic
);
end FULL_ADDER;
architecture FULL_ADDER of FULL_ADDER is
signal TMP: std_logic;
begin
TMP <= DATA_A xor DATA_B;
SAVE <= TMP xor DATA_C;
CARRY <= not((not (TMP and DATA_C)) and (not (DATA_A and DATA_B)));
end FULL_ADDER;
library ieee;
use ieee.std_logic_1164.all;
entity HALF_ADDER is
port
(
DATA_A, DATA_B: in std_logic;
SAVE, CARRY: out std_logic
);
end HALF_ADDER;
architecture HALF_ADDER of HALF_ADDER is
begin
SAVE <= DATA_A xor DATA_B;
CARRY <= DATA_A and DATA_B;
end HALF_ADDER;
library ieee;
use ieee.std_logic_1164.all;
entity INVBLOCK is
port
(
GIN,PHI:in std_logic;
GOUT:out std_logic
);
end INVBLOCK;
architecture INVBLOCK_regular of INVBLOCK is
begin
GOUT <= not GIN;
end INVBLOCK_regular;
library ieee;
use ieee.std_logic_1164.all;
entity XXOR1 is
port
(
A,B,GIN,PHI:in std_logic;
SUM:out std_logic
);
end XXOR1;
architecture XXOR_regular of XXOR1 is
begin
SUM <= (not (A xor B)) xor GIN;
end XXOR_regular;
library ieee;
use ieee.std_logic_1164.all;
entity BLOCK0 is
port
(
A,B,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end BLOCK0;
architecture BLOCK0_regular of BLOCK0 is
begin
POUT <= not(A or B);
GOUT <= not(A and B);
end BLOCK0_regular;
library ieee;
use ieee.std_logic_1164.all;
entity BLOCK1 is
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end BLOCK1;
architecture BLOCK1_regular of BLOCK1 is
begin
POUT <= not(PIN1 or PIN2);
GOUT <= not(GIN2 and (PIN2 or GIN1));
end BLOCK1_regular;
library ieee;
use ieee.std_logic_1164.all;
entity BLOCK2 is
port
(
PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
POUT,GOUT:out std_logic
);
end BLOCK2;
architecture BLOCK2_regular of BLOCK2 is
begin
POUT <= not(PIN1 and PIN2);
GOUT <= not(GIN2 or (PIN2 and GIN1));
end BLOCK2_regular;
library ieee;
use ieee.std_logic_1164.all;
entity BLOCK1A is
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end BLOCK1A;
architecture BLOCK1A_regular of BLOCK1A is
begin
GOUT <= not(GIN2 and (PIN2 or GIN1));
end BLOCK1A_regular;
library ieee;
use ieee.std_logic_1164.all;
entity BLOCK2A is
port
(
PIN2,GIN1,GIN2,PHI:in std_logic;
GOUT:out std_logic
);
end BLOCK2A;
architecture BLOCK2A_regular of BLOCK2A is
begin
GOUT <= not(GIN2 or (PIN2 and GIN1));
end BLOCK2A_regular;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity PRESTAGE_64 is
port
(
A: in std_logic_vector(0 to 63);
B: in std_logic_vector(0 to 63);
CIN: in std_logic;
PHI: in std_logic;
POUT: out std_logic_vector(0 to 63);
GOUT: out std_logic_vector(0 to 64)
);
end PRESTAGE_64;
architecture PRESTAGE of PRESTAGE_64 is
begin -- PRESTAGE
U1:for I in 0 to 63 generate
U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1));
end generate U1;
U2: INVBLOCK port map(CIN,PHI,GOUT(0));
end PRESTAGE;
-- The DBLC-tree: Level 0
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_0_64 is
port
(
PIN: in std_logic_vector(0 to 63);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 62);
GOUT: out std_logic_vector(0 to 64)
);
end DBLC_0_64;
architecture DBLC_0 of DBLC_0_64 is
begin -- Architecture DBLC_0
U1: for I in 0 to 0 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 1 to 1 generate
U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 2 to 64 generate
U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I));
end generate U3;
end DBLC_0;
-- The DBLC-tree: Level 1
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_1_64 is
port
(
PIN: in std_logic_vector(0 to 62);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 60);
GOUT: out std_logic_vector(0 to 64)
);
end DBLC_1_64;
architecture DBLC_1 of DBLC_1_64 is
begin -- Architecture DBLC_1
U1: for I in 0 to 1 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 2 to 3 generate
U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 4 to 64 generate
U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I));
end generate U3;
end DBLC_1;
-- The DBLC-tree: Level 2
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_2_64 is
port
(
PIN: in std_logic_vector(0 to 60);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 56);
GOUT: out std_logic_vector(0 to 64)
);
end DBLC_2_64;
architecture DBLC_2 of DBLC_2_64 is
begin -- Architecture DBLC_2
U1: for I in 0 to 3 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 4 to 7 generate
U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 8 to 64 generate
U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I));
end generate U3;
end DBLC_2;
-- The DBLC-tree: Level 3
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_3_64 is
port
(
PIN: in std_logic_vector(0 to 56);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 48);
GOUT: out std_logic_vector(0 to 64)
);
end DBLC_3_64;
architecture DBLC_3 of DBLC_3_64 is
begin -- Architecture DBLC_3
U1: for I in 0 to 7 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 8 to 15 generate
U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 16 to 64 generate
U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I));
end generate U3;
end DBLC_3;
-- The DBLC-tree: Level 4
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_4_64 is
port
(
PIN: in std_logic_vector(0 to 48);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 32);
GOUT: out std_logic_vector(0 to 64)
);
end DBLC_4_64;
architecture DBLC_4 of DBLC_4_64 is
begin -- Architecture DBLC_4
U1: for I in 0 to 15 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 16 to 31 generate
U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 32 to 64 generate
U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I));
end generate U3;
end DBLC_4;
-- The DBLC-tree: Level 5
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_5_64 is
port
(
PIN: in std_logic_vector(0 to 32);
GIN: in std_logic_vector(0 to 64);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 0);
GOUT: out std_logic_vector(0 to 64)
);
end DBLC_5_64;
architecture DBLC_5 of DBLC_5_64 is
begin -- Architecture DBLC_5
U1: for I in 0 to 31 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 32 to 63 generate
U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 64 to 64 generate
U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I));
end generate U3;
end DBLC_5;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity XORSTAGE_64 is
port
(
A: in std_logic_vector(0 to 63);
B: in std_logic_vector(0 to 63);
PBIT, PHI: in std_logic;
CARRY: in std_logic_vector(0 to 64);
SUM: out std_logic_vector(0 to 63);
COUT: out std_logic
);
end XORSTAGE_64;
architecture XORSTAGE of XORSTAGE_64 is
begin -- XORSTAGE
U2:for I in 0 to 63 generate
U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I));
end generate U2;
U1: BLOCK1A port map(PBIT,CARRY(0),CARRY(64),PHI,COUT);
end XORSTAGE;
-- The DBLC-tree: All levels encapsulated
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLCTREE_64 is
port
(
PIN:in std_logic_vector(0 to 63);
GIN:in std_logic_vector(0 to 64);
PHI:in std_logic;
GOUT:out std_logic_vector(0 to 64);
POUT:out std_logic_vector(0 to 0)
);
end DBLCTREE_64;
architecture DBLCTREE of DBLCTREE_64 is
signal INTPROP_0: std_logic_vector(0 to 62);
signal INTGEN_0: std_logic_vector(0 to 64);
signal INTPROP_1: std_logic_vector(0 to 60);
signal INTGEN_1: std_logic_vector(0 to 64);
signal INTPROP_2: std_logic_vector(0 to 56);
signal INTGEN_2: std_logic_vector(0 to 64);
signal INTPROP_3: std_logic_vector(0 to 48);
signal INTGEN_3: std_logic_vector(0 to 64);
signal INTPROP_4: std_logic_vector(0 to 32);
signal INTGEN_4: std_logic_vector(0 to 64);
begin -- Architecture DBLCTREE
U_0: DBLC_0_64 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0);
U_1: DBLC_1_64 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1);
U_2: DBLC_2_64 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2);
U_3: DBLC_3_64 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3);
U_4: DBLC_4_64 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4);
U_5: DBLC_5_64 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>POUT,GOUT=>GOUT);
end DBLCTREE;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLCADDER_64_64 is
port
(
OPA:in std_logic_vector(0 to 63);
OPB:in std_logic_vector(0 to 63);
CIN:in std_logic;
PHI:in std_logic;
SUM:out std_logic_vector(0 to 63);
COUT:out std_logic
);
end DBLCADDER_64_64;
architecture DBLCADDER of DBLCADDER_64_64 is
signal INTPROP: std_logic_vector(0 to 63);
signal INTGEN: std_logic_vector(0 to 64);
signal PBIT:std_logic_vector(0 to 0);
signal CARRY: std_logic_vector(0 to 64);
begin -- Architecture DBLCADDER
U1: PRESTAGE_64 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN);
U2: DBLCTREE_64 port map(INTPROP,INTGEN,PHI,CARRY,PBIT);
U3: XORSTAGE_64 port map(OPA(0 to 63),OPB(0 to 63),PBIT(0),PHI,CARRY(0 to 64),SUM,COUT);
end DBLCADDER;
------------------------------------------------------------
-- END: Architectures used with the DBLC adder
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity XXOR2 is
port
(
A,B,GIN,PHI:in std_logic;
SUM:out std_logic
);
end XXOR2;
architecture XXOR_true of XXOR2 is
begin
SUM <= (A xor B) xor GIN;
end XXOR_true;
--
-- Modgen adder created Fri Aug 16 14:47:23 2002
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_0_32 is
port
(
PIN: in std_logic_vector(0 to 31);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 30);
GOUT: out std_logic_vector(0 to 32)
);
end DBLC_0_32;
architecture DBLC_0 of DBLC_0_32 is
begin -- Architecture DBLC_0
U1: for I in 0 to 0 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 1 to 1 generate
U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 2 to 32 generate
U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I));
end generate U3;
end DBLC_0;
-- The DBLC-tree: Level 1
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_1_32 is
port
(
PIN: in std_logic_vector(0 to 30);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 28);
GOUT: out std_logic_vector(0 to 32)
);
end DBLC_1_32;
architecture DBLC_1 of DBLC_1_32 is
begin -- Architecture DBLC_1
U1: for I in 0 to 1 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 2 to 3 generate
U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 4 to 32 generate
U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I));
end generate U3;
end DBLC_1;
-- The DBLC-tree: Level 2
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_2_32 is
port
(
PIN: in std_logic_vector(0 to 28);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 24);
GOUT: out std_logic_vector(0 to 32)
);
end DBLC_2_32;
architecture DBLC_2 of DBLC_2_32 is
begin -- Architecture DBLC_2
U1: for I in 0 to 3 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 4 to 7 generate
U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 8 to 32 generate
U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I));
end generate U3;
end DBLC_2;
-- The DBLC-tree: Level 3
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_3_32 is
port
(
PIN: in std_logic_vector(0 to 24);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 16);
GOUT: out std_logic_vector(0 to 32)
);
end DBLC_3_32;
architecture DBLC_3 of DBLC_3_32 is
begin -- Architecture DBLC_3
U1: for I in 0 to 7 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 8 to 15 generate
U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 16 to 32 generate
U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I));
end generate U3;
end DBLC_3;
-- The DBLC-tree: Level 4
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_4_32 is
port
(
PIN: in std_logic_vector(0 to 16);
GIN: in std_logic_vector(0 to 32);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 0);
GOUT: out std_logic_vector(0 to 32)
);
end DBLC_4_32;
architecture DBLC_4 of DBLC_4_32 is
begin -- Architecture DBLC_4
GOUT(0 to 15) <= GIN(0 to 15);
U2: for I in 16 to 31 generate
U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 32 to 32 generate
U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I));
end generate U3;
end DBLC_4;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity XORSTAGE_32 is
port
(
A: in std_logic_vector(0 to 31);
B: in std_logic_vector(0 to 31);
PBIT, PHI: in std_logic;
CARRY: in std_logic_vector(0 to 32);
SUM: out std_logic_vector(0 to 31);
COUT: out std_logic
);
end XORSTAGE_32;
architecture XORSTAGE of XORSTAGE_32 is
begin -- XORSTAGE
U2:for I in 0 to 15 generate
U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I));
end generate U2;
U3:for I in 16 to 31 generate
U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I));
end generate U3;
U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(32),PHI,COUT);
end XORSTAGE;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity PRESTAGE_32 is
port
(
A: in std_logic_vector(0 to 31);
B: in std_logic_vector(0 to 31);
CIN: in std_logic;
PHI: in std_logic;
POUT: out std_logic_vector(0 to 31);
GOUT: out std_logic_vector(0 to 32)
);
end PRESTAGE_32;
architecture PRESTAGE of PRESTAGE_32 is
begin -- PRESTAGE
U1:for I in 0 to 31 generate
U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1));
end generate U1;
U2: INVBLOCK port map(CIN,PHI,GOUT(0));
end PRESTAGE;
-- The DBLC-tree: All levels encapsulated
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLCTREE_32 is
port
(
PIN:in std_logic_vector(0 to 31);
GIN:in std_logic_vector(0 to 32);
PHI:in std_logic;
GOUT:out std_logic_vector(0 to 32);
POUT:out std_logic_vector(0 to 0)
);
end DBLCTREE_32;
architecture DBLCTREE of DBLCTREE_32 is
signal INTPROP_0: std_logic_vector(0 to 30);
signal INTGEN_0: std_logic_vector(0 to 32);
signal INTPROP_1: std_logic_vector(0 to 28);
signal INTGEN_1: std_logic_vector(0 to 32);
signal INTPROP_2: std_logic_vector(0 to 24);
signal INTGEN_2: std_logic_vector(0 to 32);
signal INTPROP_3: std_logic_vector(0 to 16);
signal INTGEN_3: std_logic_vector(0 to 32);
begin -- Architecture DBLCTREE
U_0: DBLC_0_32 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0);
U_1: DBLC_1_32 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1);
U_2: DBLC_2_32 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2);
U_3: DBLC_3_32 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3);
U_4: DBLC_4_32 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>POUT,GOUT=>GOUT);
end DBLCTREE;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLCADDER_32_32 is
port
(
OPA:in std_logic_vector(0 to 31);
OPB:in std_logic_vector(0 to 31);
CIN:in std_logic;
PHI:in std_logic;
SUM:out std_logic_vector(0 to 31);
COUT:out std_logic
);
end DBLCADDER_32_32;
architecture DBLCADDER of DBLCADDER_32_32 is
signal INTPROP: std_logic_vector(0 to 31);
signal INTGEN: std_logic_vector(0 to 32);
signal PBIT:std_logic_vector(0 to 0);
signal CARRY: std_logic_vector(0 to 32);
begin -- Architecture DBLCADDER
U1: PRESTAGE_32 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN);
U2: DBLCTREE_32 port map(INTPROP,INTGEN,PHI,CARRY,PBIT);
U3: XORSTAGE_32 port map(OPA(0 to 31),OPB(0 to 31),PBIT(0),PHI,CARRY(0 to 32),SUM,COUT);
end DBLCADDER;
------------------------------------------------------------
-- END: Architectures used with the DBLC adder
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity PRESTAGE_128 is
port
(
A: in std_logic_vector(0 to 127);
B: in std_logic_vector(0 to 127);
CIN: in std_logic;
PHI: in std_logic;
POUT: out std_logic_vector(0 to 127);
GOUT: out std_logic_vector(0 to 128)
);
end PRESTAGE_128;
architecture PRESTAGE of PRESTAGE_128 is
begin -- PRESTAGE
U1:for I in 0 to 127 generate
U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1));
end generate U1;
U2: INVBLOCK port map(CIN,PHI,GOUT(0));
end PRESTAGE;
-- The DBLC-tree: Level 0
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_0_128 is
port
(
PIN: in std_logic_vector(0 to 127);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 126);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_0_128;
architecture DBLC_0 of DBLC_0_128 is
begin -- Architecture DBLC_0
U1: for I in 0 to 0 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 1 to 1 generate
U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 2 to 128 generate
U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I));
end generate U3;
end DBLC_0;
-- The DBLC-tree: Level 1
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_1_128 is
port
(
PIN: in std_logic_vector(0 to 126);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 124);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_1_128;
architecture DBLC_1 of DBLC_1_128 is
begin -- Architecture DBLC_1
U1: for I in 0 to 1 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 2 to 3 generate
U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 4 to 128 generate
U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I));
end generate U3;
end DBLC_1;
-- The DBLC-tree: Level 2
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_2_128 is
port
(
PIN: in std_logic_vector(0 to 124);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 120);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_2_128;
architecture DBLC_2 of DBLC_2_128 is
begin -- Architecture DBLC_2
U1: for I in 0 to 3 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 4 to 7 generate
U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 8 to 128 generate
U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I));
end generate U3;
end DBLC_2;
-- The DBLC-tree: Level 3
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_3_128 is
port
(
PIN: in std_logic_vector(0 to 120);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 112);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_3_128;
architecture DBLC_3 of DBLC_3_128 is
begin -- Architecture DBLC_3
U1: for I in 0 to 7 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 8 to 15 generate
U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 16 to 128 generate
U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I));
end generate U3;
end DBLC_3;
-- The DBLC-tree: Level 4
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_4_128 is
port
(
PIN: in std_logic_vector(0 to 112);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 96);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_4_128;
architecture DBLC_4 of DBLC_4_128 is
begin -- Architecture DBLC_4
U1: for I in 0 to 15 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 16 to 31 generate
U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 32 to 128 generate
U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I));
end generate U3;
end DBLC_4;
-- The DBLC-tree: Level 5
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_5_128 is
port
(
PIN: in std_logic_vector(0 to 96);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 64);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_5_128;
architecture DBLC_5 of DBLC_5_128 is
begin -- Architecture DBLC_5
U1: for I in 0 to 31 generate
U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 32 to 63 generate
U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 64 to 128 generate
U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I));
end generate U3;
end DBLC_5;
-- The DBLC-tree: Level 6
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_6_128 is
port
(
PIN: in std_logic_vector(0 to 64);
GIN: in std_logic_vector(0 to 128);
PHI: in std_logic;
POUT: out std_logic_vector(0 to 0);
GOUT: out std_logic_vector(0 to 128)
);
end DBLC_6_128;
architecture DBLC_6 of DBLC_6_128 is
begin -- Architecture DBLC_6
GOUT(0 to 63) <= GIN(0 to 63);
U2: for I in 64 to 127 generate
U21: BLOCK1A port map(PIN(I-64),GIN(I-64),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 128 to 128 generate
U31: BLOCK1 port map(PIN(I-128),PIN(I-64),GIN(I-64),GIN(I),PHI,POUT(I-128),GOUT(I));
end generate U3;
end DBLC_6;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity XORSTAGE_128 is
port
(
A: in std_logic_vector(0 to 127);
B: in std_logic_vector(0 to 127);
PBIT, PHI: in std_logic;
CARRY: in std_logic_vector(0 to 128);
SUM: out std_logic_vector(0 to 127);
COUT: out std_logic
);
end XORSTAGE_128;
architecture XORSTAGE of XORSTAGE_128 is
begin -- XORSTAGE
U2:for I in 0 to 63 generate
U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I));
end generate U2;
U3:for I in 64 to 127 generate
U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I));
end generate U3;
U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(128),PHI,COUT);
end XORSTAGE;
-- The DBLC-tree: All levels encapsulated
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLCTREE_128 is
port
(
PIN:in std_logic_vector(0 to 127);
GIN:in std_logic_vector(0 to 128);
PHI:in std_logic;
GOUT:out std_logic_vector(0 to 128);
POUT:out std_logic_vector(0 to 0)
);
end DBLCTREE_128;
architecture DBLCTREE of DBLCTREE_128 is
signal INTPROP_0: std_logic_vector(0 to 126);
signal INTGEN_0: std_logic_vector(0 to 128);
signal INTPROP_1: std_logic_vector(0 to 124);
signal INTGEN_1: std_logic_vector(0 to 128);
signal INTPROP_2: std_logic_vector(0 to 120);
signal INTGEN_2: std_logic_vector(0 to 128);
signal INTPROP_3: std_logic_vector(0 to 112);
signal INTGEN_3: std_logic_vector(0 to 128);
signal INTPROP_4: std_logic_vector(0 to 96);
signal INTGEN_4: std_logic_vector(0 to 128);
signal INTPROP_5: std_logic_vector(0 to 64);
signal INTGEN_5: std_logic_vector(0 to 128);
begin -- Architecture DBLCTREE
U_0: DBLC_0_128 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0);
U_1: DBLC_1_128 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1);
U_2: DBLC_2_128 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2);
U_3: DBLC_3_128 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3);
U_4: DBLC_4_128 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4);
U_5: DBLC_5_128 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>INTPROP_5,GOUT=>INTGEN_5);
U_6: DBLC_6_128 port map(PIN=>INTPROP_5,GIN=>INTGEN_5,PHI=>PHI,POUT=>POUT,GOUT=>GOUT);
end DBLCTREE;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLCADDER_128_128 is
port
(
OPA:in std_logic_vector(0 to 127);
OPB:in std_logic_vector(0 to 127);
CIN:in std_logic;
PHI:in std_logic;
SUM:out std_logic_vector(0 to 127);
COUT:out std_logic
);
end DBLCADDER_128_128;
architecture DBLCADDER of DBLCADDER_128_128 is
signal INTPROP: std_logic_vector(0 to 127);
signal INTGEN: std_logic_vector(0 to 128);
signal PBIT:std_logic_vector(0 to 0);
signal CARRY: std_logic_vector(0 to 128);
begin -- Architecture DBLCADDER
U1: PRESTAGE_128 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN);
U2: DBLCTREE_128 port map(INTPROP,INTGEN,PHI,CARRY,PBIT);
U3: XORSTAGE_128 port map(OPA(0 to 127),OPB(0 to 127),PBIT(0),PHI,CARRY(0 to 128),SUM,COUT);
end DBLCADDER;
--
-- Modified Booth algorithm architecture
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity BOOTHCODER_18_18 is
port
(
OPA: in std_logic_vector(0 to 17);
OPB: in std_logic_vector(0 to 17);
SUMMAND: out std_logic_vector(0 to 188)
);
end BOOTHCODER_18_18;
------------------------------------------------------------
-- END: Entities used within the Modified Booth Recoding
------------------------------------------------------------
architecture BOOTHCODER of BOOTHCODER_18_18 is
-- Components used in the architecture
-- Internal signal in Booth structure
signal INV_MULTIPLICAND: std_logic_vector(0 to 17);
signal INT_MULTIPLIER: std_logic_vector(0 to 35);
signal LOGIC_ONE, LOGIC_ZERO: std_logic;
begin
LOGIC_ONE <= '1';
LOGIC_ZERO <= '0';
-- Begin decoder block 1
DEC_0:DECODER -- Decoder of multiplier operand
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3)
);
-- End decoder block 1
-- Begin partial product 1
INV_MULTIPLICAND(0) <= NOT OPA(0);
PPL_0:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(0)
);
RGATE_0:R_GATE
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
PPBIT => SUMMAND(1)
);
INV_MULTIPLICAND(1) <= NOT OPA(1);
PPM_0:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(2)
);
INV_MULTIPLICAND(2) <= NOT OPA(2);
PPM_1:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(3)
);
INV_MULTIPLICAND(3) <= NOT OPA(3);
PPM_2:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(6)
);
INV_MULTIPLICAND(4) <= NOT OPA(4);
PPM_3:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(8)
);
INV_MULTIPLICAND(5) <= NOT OPA(5);
PPM_4:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(12)
);
INV_MULTIPLICAND(6) <= NOT OPA(6);
PPM_5:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(15)
);
INV_MULTIPLICAND(7) <= NOT OPA(7);
PPM_6:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(20)
);
INV_MULTIPLICAND(8) <= NOT OPA(8);
PPM_7:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(24)
);
INV_MULTIPLICAND(9) <= NOT OPA(9);
PPM_8:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(30)
);
INV_MULTIPLICAND(10) <= NOT OPA(10);
PPM_9:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(35)
);
INV_MULTIPLICAND(11) <= NOT OPA(11);
PPM_10:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(42)
);
INV_MULTIPLICAND(12) <= NOT OPA(12);
PPM_11:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(48)
);
INV_MULTIPLICAND(13) <= NOT OPA(13);
PPM_12:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(56)
);
INV_MULTIPLICAND(14) <= NOT OPA(14);
PPM_13:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(63)
);
INV_MULTIPLICAND(15) <= NOT OPA(15);
PPM_14:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(72)
);
INV_MULTIPLICAND(16) <= NOT OPA(16);
PPM_15:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(80)
);
INV_MULTIPLICAND(17) <= NOT OPA(17);
PPM_16:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(90)
);
PPH_0:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(99)
);
SUMMAND(100) <= '1';
-- Begin partial product 1
-- Begin decoder block 2
DEC_1:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7)
);
-- End decoder block 2
-- Begin partial product 2
PPL_1:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(4)
);
RGATE_1:R_GATE
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
PPBIT => SUMMAND(5)
);
PPM_17:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(7)
);
PPM_18:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(9)
);
PPM_19:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(13)
);
PPM_20:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(16)
);
PPM_21:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(21)
);
PPM_22:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(25)
);
PPM_23:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(31)
);
PPM_24:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(36)
);
PPM_25:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(43)
);
PPM_26:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(49)
);
PPM_27:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(57)
);
PPM_28:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(64)
);
PPM_29:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(73)
);
PPM_30:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(81)
);
PPM_31:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(91)
);
PPM_32:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(101)
);
PPM_33:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(109)
);
SUMMAND(110) <= LOGIC_ONE;
PPH_1:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(118)
);
-- Begin partial product 2
-- Begin decoder block 3
DEC_2:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11)
);
-- End decoder block 3
-- Begin partial product 3
PPL_2:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(10)
);
RGATE_2:R_GATE
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
PPBIT => SUMMAND(11)
);
PPM_34:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(14)
);
PPM_35:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(17)
);
PPM_36:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(22)
);
PPM_37:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(26)
);
PPM_38:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(32)
);
PPM_39:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(37)
);
PPM_40:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(44)
);
PPM_41:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(50)
);
PPM_42:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(58)
);
PPM_43:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(65)
);
PPM_44:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(74)
);
PPM_45:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(82)
);
PPM_46:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(92)
);
PPM_47:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(102)
);
PPM_48:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(111)
);
PPM_49:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(119)
);
PPM_50:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(126)
);
SUMMAND(127) <= LOGIC_ONE;
PPH_2:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(134)
);
-- Begin partial product 3
-- Begin decoder block 4
DEC_3:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15)
);
-- End decoder block 4
-- Begin partial product 4
PPL_3:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(18)
);
RGATE_3:R_GATE
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
PPBIT => SUMMAND(19)
);
PPM_51:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(23)
);
PPM_52:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(27)
);
PPM_53:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(33)
);
PPM_54:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(38)
);
PPM_55:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(45)
);
PPM_56:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(51)
);
PPM_57:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(59)
);
PPM_58:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(66)
);
PPM_59:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(75)
);
PPM_60:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(83)
);
PPM_61:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(93)
);
PPM_62:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(103)
);
PPM_63:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(112)
);
PPM_64:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(120)
);
PPM_65:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(128)
);
PPM_66:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(135)
);
PPM_67:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(141)
);
SUMMAND(142) <= LOGIC_ONE;
PPH_3:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(148)
);
-- Begin partial product 4
-- Begin decoder block 5
DEC_4:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19)
);
-- End decoder block 5
-- Begin partial product 5
PPL_4:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(28)
);
RGATE_4:R_GATE
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
PPBIT => SUMMAND(29)
);
PPM_68:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(34)
);
PPM_69:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(39)
);
PPM_70:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(46)
);
PPM_71:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(52)
);
PPM_72:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(60)
);
PPM_73:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(67)
);
PPM_74:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(76)
);
PPM_75:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(84)
);
PPM_76:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(94)
);
PPM_77:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(104)
);
PPM_78:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(113)
);
PPM_79:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(121)
);
PPM_80:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(129)
);
PPM_81:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(136)
);
PPM_82:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(143)
);
PPM_83:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(149)
);
PPM_84:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(154)
);
SUMMAND(155) <= LOGIC_ONE;
PPH_4:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(160)
);
-- Begin partial product 5
-- Begin decoder block 6
DEC_5:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(9),INB => OPB(10),INC => OPB(11),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23)
);
-- End decoder block 6
-- Begin partial product 6
PPL_5:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(40)
);
RGATE_5:R_GATE
port map
(
INA => OPB(9),INB => OPB(10),INC => OPB(11),
PPBIT => SUMMAND(41)
);
PPM_85:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(47)
);
PPM_86:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(53)
);
PPM_87:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(61)
);
PPM_88:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(68)
);
PPM_89:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(77)
);
PPM_90:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(85)
);
PPM_91:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(95)
);
PPM_92:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(105)
);
PPM_93:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(114)
);
PPM_94:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(122)
);
PPM_95:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(130)
);
PPM_96:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(137)
);
PPM_97:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(144)
);
PPM_98:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(150)
);
PPM_99:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(156)
);
PPM_100:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(161)
);
PPM_101:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(165)
);
SUMMAND(166) <= LOGIC_ONE;
PPH_5:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(170)
);
-- Begin partial product 6
-- Begin decoder block 7
DEC_6:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(11),INB => OPB(12),INC => OPB(13),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27)
);
-- End decoder block 7
-- Begin partial product 7
PPL_6:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(54)
);
RGATE_6:R_GATE
port map
(
INA => OPB(11),INB => OPB(12),INC => OPB(13),
PPBIT => SUMMAND(55)
);
PPM_102:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(62)
);
PPM_103:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(69)
);
PPM_104:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(78)
);
PPM_105:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(86)
);
PPM_106:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(96)
);
PPM_107:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(106)
);
PPM_108:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(115)
);
PPM_109:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(123)
);
PPM_110:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(131)
);
PPM_111:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(138)
);
PPM_112:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(145)
);
PPM_113:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(151)
);
PPM_114:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(157)
);
PPM_115:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(162)
);
PPM_116:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(167)
);
PPM_117:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(171)
);
PPM_118:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(174)
);
SUMMAND(175) <= LOGIC_ONE;
PPH_6:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(178)
);
-- Begin partial product 7
-- Begin decoder block 8
DEC_7:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(13),INB => OPB(14),INC => OPB(15),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31)
);
-- End decoder block 8
-- Begin partial product 8
PPL_7:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(70)
);
RGATE_7:R_GATE
port map
(
INA => OPB(13),INB => OPB(14),INC => OPB(15),
PPBIT => SUMMAND(71)
);
PPM_119:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(79)
);
PPM_120:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(87)
);
PPM_121:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(97)
);
PPM_122:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(107)
);
PPM_123:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(116)
);
PPM_124:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(124)
);
PPM_125:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(132)
);
PPM_126:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(139)
);
PPM_127:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(146)
);
PPM_128:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(152)
);
PPM_129:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(158)
);
PPM_130:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(163)
);
PPM_131:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(168)
);
PPM_132:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(172)
);
PPM_133:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(176)
);
PPM_134:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(179)
);
PPM_135:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(181)
);
SUMMAND(182) <= LOGIC_ONE;
PPH_7:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(184)
);
-- Begin partial product 8
-- Begin decoder block 9
DEC_8:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(15),INB => OPB(16),INC => OPB(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35)
);
-- End decoder block 9
-- Begin partial product 9
PPL_8:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(88)
);
RGATE_8:R_GATE
port map
(
INA => OPB(15),INB => OPB(16),INC => OPB(17),
PPBIT => SUMMAND(89)
);
PPM_136:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(98)
);
PPM_137:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(108)
);
PPM_138:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(117)
);
PPM_139:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(125)
);
PPM_140:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(133)
);
PPM_141:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(140)
);
PPM_142:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(147)
);
PPM_143:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(153)
);
PPM_144:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(159)
);
PPM_145:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(164)
);
PPM_146:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(169)
);
PPM_147:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(173)
);
PPM_148:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(177)
);
PPM_149:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(180)
);
PPM_150:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(183)
);
PPM_151:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(185)
);
PPM_152:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(186)
);
SUMMAND(187) <= LOGIC_ONE;
PPH_8:PP_HIGH
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(188)
);
-- Begin partial product 9
end BOOTHCODER;
------------------------------------------------------------
-- END: Architectures used with the Modified Booth recoding
------------------------------------------------------------
--
-- Wallace tree architecture
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity WALLACE_18_18 is
port
(
SUMMAND: in std_logic_vector(0 to 188);
CARRY: out std_logic_vector(0 to 33);
SUM: out std_logic_vector(0 to 34)
);
end WALLACE_18_18;
------------------------------------------------------------
-- END: Entities within the Wallace-tree
------------------------------------------------------------
architecture WALLACE of WALLACE_18_18 is
-- Components used in the netlist
-- Signals used inside the wallace trees
signal INT_CARRY: std_logic_vector(0 to 114);
signal INT_SUM: std_logic_vector(0 to 158);
begin -- netlist
-- Begin WT-branch 1
---- Begin HA stage
HA_0:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(0), DATA_B => SUMMAND(1),
SAVE => SUM(0), CARRY => CARRY(0)
);
---- End HA stage
-- End WT-branch 1
-- Begin WT-branch 2
---- Begin NO stage
SUM(1) <= SUMMAND(2); -- At Level 1
CARRY(1) <= '0';
---- End NO stage
-- End WT-branch 2
-- Begin WT-branch 3
---- Begin FA stage
FA_0:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5),
SAVE => SUM(2), CARRY => CARRY(2)
);
---- End FA stage
-- End WT-branch 3
-- Begin WT-branch 4
---- Begin HA stage
HA_1:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(6), DATA_B => SUMMAND(7),
SAVE => SUM(3), CARRY => CARRY(3)
);
---- End HA stage
-- End WT-branch 4
-- Begin WT-branch 5
---- Begin FA stage
FA_1:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10),
SAVE => INT_SUM(0), CARRY => INT_CARRY(0)
);
---- End FA stage
---- Begin NO stage
INT_SUM(1) <= SUMMAND(11); -- At Level 1
---- End NO stage
---- Begin HA stage
HA_2:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(0), DATA_B => INT_SUM(1),
SAVE => SUM(4), CARRY => CARRY(4)
);
---- End HA stage
-- End WT-branch 5
-- Begin WT-branch 6
---- Begin FA stage
FA_2:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14),
SAVE => INT_SUM(2), CARRY => INT_CARRY(1)
);
---- End FA stage
---- Begin HA stage
HA_3:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0),
SAVE => SUM(5), CARRY => CARRY(5)
);
---- End HA stage
-- End WT-branch 6
-- Begin WT-branch 7
---- Begin FA stage
FA_3:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17),
SAVE => INT_SUM(3), CARRY => INT_CARRY(2)
);
---- End FA stage
---- Begin HA stage
HA_4:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(18), DATA_B => SUMMAND(19),
SAVE => INT_SUM(4), CARRY => INT_CARRY(3)
);
---- End HA stage
---- Begin FA stage
FA_4:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1),
SAVE => SUM(6), CARRY => CARRY(6)
);
---- End FA stage
-- End WT-branch 7
-- Begin WT-branch 8
---- Begin FA stage
FA_5:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22),
SAVE => INT_SUM(5), CARRY => INT_CARRY(4)
);
---- End FA stage
---- Begin NO stage
INT_SUM(6) <= SUMMAND(23); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_6:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2),
SAVE => INT_SUM(7), CARRY => INT_CARRY(5)
);
---- End FA stage
---- Begin NO stage
INT_SUM(8) <= INT_CARRY(3); -- At Level 2
---- End NO stage
---- Begin HA stage
HA_5:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(7), DATA_B => INT_SUM(8),
SAVE => SUM(7), CARRY => CARRY(7)
);
---- End HA stage
-- End WT-branch 8
-- Begin WT-branch 9
---- Begin FA stage
FA_7:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26),
SAVE => INT_SUM(9), CARRY => INT_CARRY(6)
);
---- End FA stage
---- Begin FA stage
FA_8:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29),
SAVE => INT_SUM(10), CARRY => INT_CARRY(7)
);
---- End FA stage
---- Begin FA stage
FA_9:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4),
SAVE => INT_SUM(11), CARRY => INT_CARRY(8)
);
---- End FA stage
---- Begin HA stage
HA_6:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5),
SAVE => SUM(8), CARRY => CARRY(8)
);
---- End HA stage
-- End WT-branch 9
-- Begin WT-branch 10
---- Begin FA stage
FA_10:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32),
SAVE => INT_SUM(12), CARRY => INT_CARRY(9)
);
---- End FA stage
---- Begin HA stage
HA_7:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(33), DATA_B => SUMMAND(34),
SAVE => INT_SUM(13), CARRY => INT_CARRY(10)
);
---- End HA stage
---- Begin FA stage
FA_11:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6),
SAVE => INT_SUM(14), CARRY => INT_CARRY(11)
);
---- End FA stage
---- Begin NO stage
INT_SUM(15) <= INT_CARRY(7); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_12:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8),
SAVE => SUM(9), CARRY => CARRY(9)
);
---- End FA stage
-- End WT-branch 10
-- Begin WT-branch 11
---- Begin FA stage
FA_13:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37),
SAVE => INT_SUM(16), CARRY => INT_CARRY(12)
);
---- End FA stage
---- Begin FA stage
FA_14:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40),
SAVE => INT_SUM(17), CARRY => INT_CARRY(13)
);
---- End FA stage
---- Begin NO stage
INT_SUM(18) <= SUMMAND(41); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_15:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18),
SAVE => INT_SUM(19), CARRY => INT_CARRY(14)
);
---- End FA stage
---- Begin HA stage
HA_8:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10),
SAVE => INT_SUM(20), CARRY => INT_CARRY(15)
);
---- End HA stage
---- Begin FA stage
FA_16:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11),
SAVE => SUM(10), CARRY => CARRY(10)
);
---- End FA stage
-- End WT-branch 11
-- Begin WT-branch 12
---- Begin FA stage
FA_17:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44),
SAVE => INT_SUM(21), CARRY => INT_CARRY(16)
);
---- End FA stage
---- Begin FA stage
FA_18:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47),
SAVE => INT_SUM(22), CARRY => INT_CARRY(17)
);
---- End FA stage
---- Begin FA stage
FA_19:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12),
SAVE => INT_SUM(23), CARRY => INT_CARRY(18)
);
---- End FA stage
---- Begin NO stage
INT_SUM(24) <= INT_CARRY(13); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_20:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14),
SAVE => INT_SUM(25), CARRY => INT_CARRY(19)
);
---- End FA stage
---- Begin NO stage
INT_SUM(26) <= INT_CARRY(15); -- At Level 3
---- End NO stage
---- Begin HA stage
HA_9:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(25), DATA_B => INT_SUM(26),
SAVE => SUM(11), CARRY => CARRY(11)
);
---- End HA stage
-- End WT-branch 12
-- Begin WT-branch 13
---- Begin FA stage
FA_21:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50),
SAVE => INT_SUM(27), CARRY => INT_CARRY(20)
);
---- End FA stage
---- Begin FA stage
FA_22:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53),
SAVE => INT_SUM(28), CARRY => INT_CARRY(21)
);
---- End FA stage
---- Begin NO stage
INT_SUM(29) <= SUMMAND(54); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(30) <= SUMMAND(55); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_23:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29),
SAVE => INT_SUM(31), CARRY => INT_CARRY(22)
);
---- End FA stage
---- Begin FA stage
FA_24:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17),
SAVE => INT_SUM(32), CARRY => INT_CARRY(23)
);
---- End FA stage
---- Begin FA stage
FA_25:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18),
SAVE => INT_SUM(33), CARRY => INT_CARRY(24)
);
---- End FA stage
---- Begin HA stage
HA_10:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19),
SAVE => SUM(12), CARRY => CARRY(12)
);
---- End HA stage
-- End WT-branch 13
-- Begin WT-branch 14
---- Begin FA stage
FA_26:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58),
SAVE => INT_SUM(34), CARRY => INT_CARRY(25)
);
---- End FA stage
---- Begin FA stage
FA_27:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61),
SAVE => INT_SUM(35), CARRY => INT_CARRY(26)
);
---- End FA stage
---- Begin NO stage
INT_SUM(36) <= SUMMAND(62); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_28:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36),
SAVE => INT_SUM(37), CARRY => INT_CARRY(27)
);
---- End FA stage
---- Begin HA stage
HA_11:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21),
SAVE => INT_SUM(38), CARRY => INT_CARRY(28)
);
---- End HA stage
---- Begin FA stage
FA_29:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22),
SAVE => INT_SUM(39), CARRY => INT_CARRY(29)
);
---- End FA stage
---- Begin NO stage
INT_SUM(40) <= INT_CARRY(23); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_30:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24),
SAVE => SUM(13), CARRY => CARRY(13)
);
---- End FA stage
-- End WT-branch 14
-- Begin WT-branch 15
---- Begin FA stage
FA_31:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65),
SAVE => INT_SUM(41), CARRY => INT_CARRY(30)
);
---- End FA stage
---- Begin FA stage
FA_32:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68),
SAVE => INT_SUM(42), CARRY => INT_CARRY(31)
);
---- End FA stage
---- Begin FA stage
FA_33:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71),
SAVE => INT_SUM(43), CARRY => INT_CARRY(32)
);
---- End FA stage
---- Begin FA stage
FA_34:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43),
SAVE => INT_SUM(44), CARRY => INT_CARRY(33)
);
---- End FA stage
---- Begin HA stage
HA_12:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26),
SAVE => INT_SUM(45), CARRY => INT_CARRY(34)
);
---- End HA stage
---- Begin FA stage
FA_35:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27),
SAVE => INT_SUM(46), CARRY => INT_CARRY(35)
);
---- End FA stage
---- Begin NO stage
INT_SUM(47) <= INT_CARRY(28); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_36:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29),
SAVE => SUM(14), CARRY => CARRY(14)
);
---- End FA stage
-- End WT-branch 15
-- Begin WT-branch 16
---- Begin FA stage
FA_37:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74),
SAVE => INT_SUM(48), CARRY => INT_CARRY(36)
);
---- End FA stage
---- Begin FA stage
FA_38:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77),
SAVE => INT_SUM(49), CARRY => INT_CARRY(37)
);
---- End FA stage
---- Begin HA stage
HA_13:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(78), DATA_B => SUMMAND(79),
SAVE => INT_SUM(50), CARRY => INT_CARRY(38)
);
---- End HA stage
---- Begin FA stage
FA_39:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50),
SAVE => INT_SUM(51), CARRY => INT_CARRY(39)
);
---- End FA stage
---- Begin FA stage
FA_40:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32),
SAVE => INT_SUM(52), CARRY => INT_CARRY(40)
);
---- End FA stage
---- Begin FA stage
FA_41:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33),
SAVE => INT_SUM(53), CARRY => INT_CARRY(41)
);
---- End FA stage
---- Begin NO stage
INT_SUM(54) <= INT_CARRY(34); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_42:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35),
SAVE => SUM(15), CARRY => CARRY(15)
);
---- End FA stage
-- End WT-branch 16
-- Begin WT-branch 17
---- Begin FA stage
FA_43:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82),
SAVE => INT_SUM(55), CARRY => INT_CARRY(42)
);
---- End FA stage
---- Begin FA stage
FA_44:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85),
SAVE => INT_SUM(56), CARRY => INT_CARRY(43)
);
---- End FA stage
---- Begin FA stage
FA_45:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88),
SAVE => INT_SUM(57), CARRY => INT_CARRY(44)
);
---- End FA stage
---- Begin NO stage
INT_SUM(58) <= SUMMAND(89); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_46:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57),
SAVE => INT_SUM(59), CARRY => INT_CARRY(45)
);
---- End FA stage
---- Begin FA stage
FA_47:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37),
SAVE => INT_SUM(60), CARRY => INT_CARRY(46)
);
---- End FA stage
---- Begin NO stage
INT_SUM(61) <= INT_CARRY(38); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_48:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61),
SAVE => INT_SUM(62), CARRY => INT_CARRY(47)
);
---- End FA stage
---- Begin HA stage
HA_14:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40),
SAVE => INT_SUM(63), CARRY => INT_CARRY(48)
);
---- End HA stage
---- Begin FA stage
FA_49:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41),
SAVE => SUM(16), CARRY => CARRY(16)
);
---- End FA stage
-- End WT-branch 17
-- Begin WT-branch 18
---- Begin FA stage
FA_50:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92),
SAVE => INT_SUM(64), CARRY => INT_CARRY(49)
);
---- End FA stage
---- Begin FA stage
FA_51:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95),
SAVE => INT_SUM(65), CARRY => INT_CARRY(50)
);
---- End FA stage
---- Begin FA stage
FA_52:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98),
SAVE => INT_SUM(66), CARRY => INT_CARRY(51)
);
---- End FA stage
---- Begin FA stage
FA_53:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66),
SAVE => INT_SUM(67), CARRY => INT_CARRY(52)
);
---- End FA stage
---- Begin FA stage
FA_54:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44),
SAVE => INT_SUM(68), CARRY => INT_CARRY(53)
);
---- End FA stage
---- Begin FA stage
FA_55:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45),
SAVE => INT_SUM(69), CARRY => INT_CARRY(54)
);
---- End FA stage
---- Begin NO stage
INT_SUM(70) <= INT_CARRY(46); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_56:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47),
SAVE => INT_SUM(71), CARRY => INT_CARRY(55)
);
---- End FA stage
---- Begin NO stage
INT_SUM(72) <= INT_CARRY(48); -- At Level 4
---- End NO stage
---- Begin HA stage
HA_15:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(71), DATA_B => INT_SUM(72),
SAVE => SUM(17), CARRY => CARRY(17)
);
---- End HA stage
-- End WT-branch 18
-- Begin WT-branch 19
---- Begin FA stage
FA_57:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101),
SAVE => INT_SUM(73), CARRY => INT_CARRY(56)
);
---- End FA stage
---- Begin FA stage
FA_58:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104),
SAVE => INT_SUM(74), CARRY => INT_CARRY(57)
);
---- End FA stage
---- Begin FA stage
FA_59:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107),
SAVE => INT_SUM(75), CARRY => INT_CARRY(58)
);
---- End FA stage
---- Begin NO stage
INT_SUM(76) <= SUMMAND(108); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_60:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75),
SAVE => INT_SUM(77), CARRY => INT_CARRY(59)
);
---- End FA stage
---- Begin FA stage
FA_61:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(76), DATA_B => INT_CARRY(49), DATA_C => INT_CARRY(50),
SAVE => INT_SUM(78), CARRY => INT_CARRY(60)
);
---- End FA stage
---- Begin NO stage
INT_SUM(79) <= INT_CARRY(51); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_62:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(77), DATA_B => INT_SUM(78), DATA_C => INT_SUM(79),
SAVE => INT_SUM(80), CARRY => INT_CARRY(61)
);
---- End FA stage
---- Begin NO stage
INT_SUM(81) <= INT_CARRY(52); -- At Level 3
---- End NO stage
---- Begin NO stage
INT_SUM(82) <= INT_CARRY(53); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_63:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(80), DATA_B => INT_SUM(81), DATA_C => INT_SUM(82),
SAVE => INT_SUM(83), CARRY => INT_CARRY(62)
);
---- End FA stage
---- Begin NO stage
INT_SUM(84) <= INT_CARRY(54); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_64:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(83), DATA_B => INT_SUM(84), DATA_C => INT_CARRY(55),
SAVE => SUM(18), CARRY => CARRY(18)
);
---- End FA stage
-- End WT-branch 19
-- Begin WT-branch 20
---- Begin FA stage
FA_65:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(109), DATA_B => SUMMAND(110), DATA_C => SUMMAND(111),
SAVE => INT_SUM(85), CARRY => INT_CARRY(63)
);
---- End FA stage
---- Begin FA stage
FA_66:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(112), DATA_B => SUMMAND(113), DATA_C => SUMMAND(114),
SAVE => INT_SUM(86), CARRY => INT_CARRY(64)
);
---- End FA stage
---- Begin FA stage
FA_67:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(115), DATA_B => SUMMAND(116), DATA_C => SUMMAND(117),
SAVE => INT_SUM(87), CARRY => INT_CARRY(65)
);
---- End FA stage
---- Begin FA stage
FA_68:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(56), DATA_B => INT_CARRY(57), DATA_C => INT_CARRY(58),
SAVE => INT_SUM(88), CARRY => INT_CARRY(66)
);
---- End FA stage
---- Begin FA stage
FA_69:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(85), DATA_B => INT_SUM(86), DATA_C => INT_SUM(87),
SAVE => INT_SUM(89), CARRY => INT_CARRY(67)
);
---- End FA stage
---- Begin FA stage
FA_70:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(88), DATA_B => INT_CARRY(59), DATA_C => INT_CARRY(60),
SAVE => INT_SUM(90), CARRY => INT_CARRY(68)
);
---- End FA stage
---- Begin FA stage
FA_71:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_CARRY(61),
SAVE => INT_SUM(91), CARRY => INT_CARRY(69)
);
---- End FA stage
---- Begin HA stage
HA_16:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(91), DATA_B => INT_CARRY(62),
SAVE => SUM(19), CARRY => CARRY(19)
);
---- End HA stage
-- End WT-branch 20
-- Begin WT-branch 21
---- Begin FA stage
FA_72:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(118), DATA_B => SUMMAND(119), DATA_C => SUMMAND(120),
SAVE => INT_SUM(92), CARRY => INT_CARRY(70)
);
---- End FA stage
---- Begin FA stage
FA_73:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(121), DATA_B => SUMMAND(122), DATA_C => SUMMAND(123),
SAVE => INT_SUM(93), CARRY => INT_CARRY(71)
);
---- End FA stage
---- Begin NO stage
INT_SUM(94) <= SUMMAND(124); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(95) <= SUMMAND(125); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_74:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_SUM(94),
SAVE => INT_SUM(96), CARRY => INT_CARRY(72)
);
---- End FA stage
---- Begin NO stage
INT_SUM(97) <= INT_SUM(95); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_75:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_CARRY(63),
SAVE => INT_SUM(98), CARRY => INT_CARRY(73)
);
---- End FA stage
---- Begin FA stage
FA_76:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(64), DATA_B => INT_CARRY(65), DATA_C => INT_CARRY(66),
SAVE => INT_SUM(99), CARRY => INT_CARRY(74)
);
---- End FA stage
---- Begin FA stage
FA_77:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(98), DATA_B => INT_SUM(99), DATA_C => INT_CARRY(67),
SAVE => INT_SUM(100), CARRY => INT_CARRY(75)
);
---- End FA stage
---- Begin NO stage
INT_SUM(101) <= INT_CARRY(68); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_78:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(69),
SAVE => SUM(20), CARRY => CARRY(20)
);
---- End FA stage
-- End WT-branch 21
-- Begin WT-branch 22
---- Begin FA stage
FA_79:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128),
SAVE => INT_SUM(102), CARRY => INT_CARRY(76)
);
---- End FA stage
---- Begin FA stage
FA_80:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131),
SAVE => INT_SUM(103), CARRY => INT_CARRY(77)
);
---- End FA stage
---- Begin FA stage
FA_81:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => INT_CARRY(70),
SAVE => INT_SUM(104), CARRY => INT_CARRY(78)
);
---- End FA stage
---- Begin NO stage
INT_SUM(105) <= INT_CARRY(71); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_82:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_SUM(104),
SAVE => INT_SUM(106), CARRY => INT_CARRY(79)
);
---- End FA stage
---- Begin HA stage
HA_17:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(105), DATA_B => INT_CARRY(72),
SAVE => INT_SUM(107), CARRY => INT_CARRY(80)
);
---- End HA stage
---- Begin FA stage
FA_83:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(106), DATA_B => INT_SUM(107), DATA_C => INT_CARRY(73),
SAVE => INT_SUM(108), CARRY => INT_CARRY(81)
);
---- End FA stage
---- Begin NO stage
INT_SUM(109) <= INT_CARRY(74); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_84:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(75),
SAVE => SUM(21), CARRY => CARRY(21)
);
---- End FA stage
-- End WT-branch 22
-- Begin WT-branch 23
---- Begin FA stage
FA_85:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(134), DATA_B => SUMMAND(135), DATA_C => SUMMAND(136),
SAVE => INT_SUM(110), CARRY => INT_CARRY(82)
);
---- End FA stage
---- Begin FA stage
FA_86:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(137), DATA_B => SUMMAND(138), DATA_C => SUMMAND(139),
SAVE => INT_SUM(111), CARRY => INT_CARRY(83)
);
---- End FA stage
---- Begin NO stage
INT_SUM(112) <= SUMMAND(140); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_87:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_SUM(112),
SAVE => INT_SUM(113), CARRY => INT_CARRY(84)
);
---- End FA stage
---- Begin FA stage
FA_88:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(76), DATA_B => INT_CARRY(77), DATA_C => INT_CARRY(78),
SAVE => INT_SUM(114), CARRY => INT_CARRY(85)
);
---- End FA stage
---- Begin FA stage
FA_89:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(113), DATA_B => INT_SUM(114), DATA_C => INT_CARRY(79),
SAVE => INT_SUM(115), CARRY => INT_CARRY(86)
);
---- End FA stage
---- Begin NO stage
INT_SUM(116) <= INT_CARRY(80); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_90:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(115), DATA_B => INT_SUM(116), DATA_C => INT_CARRY(81),
SAVE => SUM(22), CARRY => CARRY(22)
);
---- End FA stage
-- End WT-branch 23
-- Begin WT-branch 24
---- Begin FA stage
FA_91:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(141), DATA_B => SUMMAND(142), DATA_C => SUMMAND(143),
SAVE => INT_SUM(117), CARRY => INT_CARRY(87)
);
---- End FA stage
---- Begin FA stage
FA_92:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(144), DATA_B => SUMMAND(145), DATA_C => SUMMAND(146),
SAVE => INT_SUM(118), CARRY => INT_CARRY(88)
);
---- End FA stage
---- Begin NO stage
INT_SUM(119) <= SUMMAND(147); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_93:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(117), DATA_B => INT_SUM(118), DATA_C => INT_SUM(119),
SAVE => INT_SUM(120), CARRY => INT_CARRY(89)
);
---- End FA stage
---- Begin HA stage
HA_18:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(82), DATA_B => INT_CARRY(83),
SAVE => INT_SUM(121), CARRY => INT_CARRY(90)
);
---- End HA stage
---- Begin FA stage
FA_94:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(120), DATA_B => INT_SUM(121), DATA_C => INT_CARRY(84),
SAVE => INT_SUM(122), CARRY => INT_CARRY(91)
);
---- End FA stage
---- Begin NO stage
INT_SUM(123) <= INT_CARRY(85); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_95:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(86),
SAVE => SUM(23), CARRY => CARRY(23)
);
---- End FA stage
-- End WT-branch 24
-- Begin WT-branch 25
---- Begin FA stage
FA_96:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(148), DATA_B => SUMMAND(149), DATA_C => SUMMAND(150),
SAVE => INT_SUM(124), CARRY => INT_CARRY(92)
);
---- End FA stage
---- Begin FA stage
FA_97:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(151), DATA_B => SUMMAND(152), DATA_C => SUMMAND(153),
SAVE => INT_SUM(125), CARRY => INT_CARRY(93)
);
---- End FA stage
---- Begin FA stage
FA_98:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(87),
SAVE => INT_SUM(126), CARRY => INT_CARRY(94)
);
---- End FA stage
---- Begin NO stage
INT_SUM(127) <= INT_CARRY(88); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_99:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(126), DATA_B => INT_SUM(127), DATA_C => INT_CARRY(89),
SAVE => INT_SUM(128), CARRY => INT_CARRY(95)
);
---- End FA stage
---- Begin NO stage
INT_SUM(129) <= INT_CARRY(90); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_100:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(128), DATA_B => INT_SUM(129), DATA_C => INT_CARRY(91),
SAVE => SUM(24), CARRY => CARRY(24)
);
---- End FA stage
-- End WT-branch 25
-- Begin WT-branch 26
---- Begin FA stage
FA_101:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(154), DATA_B => SUMMAND(155), DATA_C => SUMMAND(156),
SAVE => INT_SUM(130), CARRY => INT_CARRY(96)
);
---- End FA stage
---- Begin FA stage
FA_102:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(157), DATA_B => SUMMAND(158), DATA_C => SUMMAND(159),
SAVE => INT_SUM(131), CARRY => INT_CARRY(97)
);
---- End FA stage
---- Begin FA stage
FA_103:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(130), DATA_B => INT_SUM(131), DATA_C => INT_CARRY(92),
SAVE => INT_SUM(132), CARRY => INT_CARRY(98)
);
---- End FA stage
---- Begin NO stage
INT_SUM(133) <= INT_CARRY(93); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_104:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(94),
SAVE => INT_SUM(134), CARRY => INT_CARRY(99)
);
---- End FA stage
---- Begin HA stage
HA_19:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(134), DATA_B => INT_CARRY(95),
SAVE => SUM(25), CARRY => CARRY(25)
);
---- End HA stage
-- End WT-branch 26
-- Begin WT-branch 27
---- Begin FA stage
FA_105:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(160), DATA_B => SUMMAND(161), DATA_C => SUMMAND(162),
SAVE => INT_SUM(135), CARRY => INT_CARRY(100)
);
---- End FA stage
---- Begin HA stage
HA_20:HALF_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(163), DATA_B => SUMMAND(164),
SAVE => INT_SUM(136), CARRY => INT_CARRY(101)
);
---- End HA stage
---- Begin FA stage
FA_106:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(135), DATA_B => INT_SUM(136), DATA_C => INT_CARRY(96),
SAVE => INT_SUM(137), CARRY => INT_CARRY(102)
);
---- End FA stage
---- Begin NO stage
INT_SUM(138) <= INT_CARRY(97); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_107:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(137), DATA_B => INT_SUM(138), DATA_C => INT_CARRY(98),
SAVE => INT_SUM(139), CARRY => INT_CARRY(103)
);
---- End FA stage
---- Begin HA stage
HA_21:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(139), DATA_B => INT_CARRY(99),
SAVE => SUM(26), CARRY => CARRY(26)
);
---- End HA stage
-- End WT-branch 27
-- Begin WT-branch 28
---- Begin FA stage
FA_108:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167),
SAVE => INT_SUM(140), CARRY => INT_CARRY(104)
);
---- End FA stage
---- Begin HA stage
HA_22:HALF_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(168), DATA_B => SUMMAND(169),
SAVE => INT_SUM(141), CARRY => INT_CARRY(105)
);
---- End HA stage
---- Begin FA stage
FA_109:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(100),
SAVE => INT_SUM(142), CARRY => INT_CARRY(106)
);
---- End FA stage
---- Begin NO stage
INT_SUM(143) <= INT_CARRY(101); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_110:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_CARRY(102),
SAVE => INT_SUM(144), CARRY => INT_CARRY(107)
);
---- End FA stage
---- Begin HA stage
HA_23:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(144), DATA_B => INT_CARRY(103),
SAVE => SUM(27), CARRY => CARRY(27)
);
---- End HA stage
-- End WT-branch 28
-- Begin WT-branch 29
---- Begin FA stage
FA_111:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(170), DATA_B => SUMMAND(171), DATA_C => SUMMAND(172),
SAVE => INT_SUM(145), CARRY => INT_CARRY(108)
);
---- End FA stage
---- Begin FA stage
FA_112:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(173), DATA_B => INT_CARRY(104), DATA_C => INT_CARRY(105),
SAVE => INT_SUM(146), CARRY => INT_CARRY(109)
);
---- End FA stage
---- Begin FA stage
FA_113:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_CARRY(106),
SAVE => INT_SUM(147), CARRY => INT_CARRY(110)
);
---- End FA stage
---- Begin HA stage
HA_24:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(147), DATA_B => INT_CARRY(107),
SAVE => SUM(28), CARRY => CARRY(28)
);
---- End HA stage
-- End WT-branch 29
-- Begin WT-branch 30
---- Begin FA stage
FA_114:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176),
SAVE => INT_SUM(148), CARRY => INT_CARRY(111)
);
---- End FA stage
---- Begin NO stage
INT_SUM(149) <= SUMMAND(177); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_115:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(148), DATA_B => INT_SUM(149), DATA_C => INT_CARRY(108),
SAVE => INT_SUM(150), CARRY => INT_CARRY(112)
);
---- End FA stage
---- Begin NO stage
INT_SUM(151) <= INT_CARRY(109); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_116:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(110),
SAVE => SUM(29), CARRY => CARRY(29)
);
---- End FA stage
-- End WT-branch 30
-- Begin WT-branch 31
---- Begin FA stage
FA_117:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(178), DATA_B => SUMMAND(179), DATA_C => SUMMAND(180),
SAVE => INT_SUM(152), CARRY => INT_CARRY(113)
);
---- End FA stage
---- Begin NO stage
INT_SUM(153) <= INT_SUM(152); -- At Level 4
---- End NO stage
---- Begin NO stage
INT_SUM(154) <= INT_CARRY(111); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_118:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(153), DATA_B => INT_SUM(154), DATA_C => INT_CARRY(112),
SAVE => SUM(30), CARRY => CARRY(30)
);
---- End FA stage
-- End WT-branch 31
-- Begin WT-branch 32
---- Begin FA stage
FA_119:FULL_ADDER -- At Level 4
port map
(
DATA_A => SUMMAND(181), DATA_B => SUMMAND(182), DATA_C => SUMMAND(183),
SAVE => INT_SUM(155), CARRY => INT_CARRY(114)
);
---- End FA stage
---- Begin NO stage
INT_SUM(156) <= INT_CARRY(113); -- At Level 4
---- End NO stage
---- Begin HA stage
HA_25:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(155), DATA_B => INT_SUM(156),
SAVE => SUM(31), CARRY => CARRY(31)
);
---- End HA stage
-- End WT-branch 32
-- Begin WT-branch 33
---- Begin NO stage
INT_SUM(157) <= SUMMAND(184); -- At Level 4
---- End NO stage
---- Begin NO stage
INT_SUM(158) <= SUMMAND(185); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_120:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(157), DATA_B => INT_SUM(158), DATA_C => INT_CARRY(114),
SAVE => SUM(32), CARRY => CARRY(32)
);
---- End FA stage
-- End WT-branch 33
-- Begin WT-branch 34
---- Begin HA stage
HA_26:HALF_ADDER -- At Level 5
port map
(
DATA_A => SUMMAND(186), DATA_B => SUMMAND(187),
SAVE => SUM(33), CARRY => CARRY(33)
);
---- End HA stage
-- End WT-branch 34
-- Begin WT-branch 35
---- Begin NO stage
SUM(34) <= SUMMAND(188); -- At Level 5
---- End NO stage
-- End WT-branch 35
end WALLACE;
------------------------------------------------------------
-- END: Architectures used with the Wallace-tree
------------------------------------------------------------
------------------------------------------------------------
-- START: Architectures used with the multiplier
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity MULTIPLIER_18_18 is
generic (mulpipe : integer := 0);
port
(
MULTIPLICAND: in std_logic_vector(0 to 17);
MULTIPLIER: in std_logic_vector(0 to 17);
PHI: in std_ulogic;
holdn: in std_ulogic;
RESULT: out std_logic_vector(0 to 63)
);
end MULTIPLIER_18_18;
architecture MULTIPLIER of MULTIPLIER_18_18 is
signal PPBIT:std_logic_vector(0 to 188);
signal INT_CARRY: std_logic_vector(0 to 64);
signal INT_CARRYR: std_logic_vector(0 to 64);
signal INT_SUM: std_logic_vector(0 to 63);
signal INT_SUMR: std_logic_vector(0 to 63);
signal LOGIC_ZERO: std_logic;
begin -- Architecture
LOGIC_ZERO <= '0';
B:BOOTHCODER_18_18
port map
(
OPA(0 to 17) => MULTIPLICAND(0 to 17),
OPB(0 to 17) => MULTIPLIER(0 to 17),
SUMMAND(0 to 188) => PPBIT(0 to 188)
);
W:WALLACE_18_18
port map
(
SUMMAND(0 to 188) => PPBIT(0 to 188),
CARRY(0 to 33) => INT_CARRY(1 to 34),
SUM(0 to 34) => INT_SUM(0 to 34)
);
INT_CARRY(0) <= LOGIC_ZERO;
INT_CARRY(35) <= LOGIC_ZERO;
INT_CARRY(36) <= LOGIC_ZERO;
INT_CARRY(37) <= LOGIC_ZERO;
INT_CARRY(38) <= LOGIC_ZERO;
INT_CARRY(39) <= LOGIC_ZERO;
INT_CARRY(40) <= LOGIC_ZERO;
INT_CARRY(41) <= LOGIC_ZERO;
INT_CARRY(42) <= LOGIC_ZERO;
INT_CARRY(43) <= LOGIC_ZERO;
INT_CARRY(44) <= LOGIC_ZERO;
INT_CARRY(45) <= LOGIC_ZERO;
INT_CARRY(46) <= LOGIC_ZERO;
INT_CARRY(47) <= LOGIC_ZERO;
INT_CARRY(48) <= LOGIC_ZERO;
INT_CARRY(49) <= LOGIC_ZERO;
INT_CARRY(50) <= LOGIC_ZERO;
INT_CARRY(51) <= LOGIC_ZERO;
INT_CARRY(52) <= LOGIC_ZERO;
INT_CARRY(53) <= LOGIC_ZERO;
INT_CARRY(54) <= LOGIC_ZERO;
INT_CARRY(55) <= LOGIC_ZERO;
INT_CARRY(56) <= LOGIC_ZERO;
INT_CARRY(57) <= LOGIC_ZERO;
INT_CARRY(58) <= LOGIC_ZERO;
INT_CARRY(59) <= LOGIC_ZERO;
INT_CARRY(60) <= LOGIC_ZERO;
INT_CARRY(61) <= LOGIC_ZERO;
INT_CARRY(62) <= LOGIC_ZERO;
INT_CARRY(63) <= LOGIC_ZERO;
INT_SUM(35) <= LOGIC_ZERO;
INT_SUM(36) <= LOGIC_ZERO;
INT_SUM(37) <= LOGIC_ZERO;
INT_SUM(38) <= LOGIC_ZERO;
INT_SUM(39) <= LOGIC_ZERO;
INT_SUM(40) <= LOGIC_ZERO;
INT_SUM(41) <= LOGIC_ZERO;
INT_SUM(42) <= LOGIC_ZERO;
INT_SUM(43) <= LOGIC_ZERO;
INT_SUM(44) <= LOGIC_ZERO;
INT_SUM(45) <= LOGIC_ZERO;
INT_SUM(46) <= LOGIC_ZERO;
INT_SUM(47) <= LOGIC_ZERO;
INT_SUM(48) <= LOGIC_ZERO;
INT_SUM(49) <= LOGIC_ZERO;
INT_SUM(50) <= LOGIC_ZERO;
INT_SUM(51) <= LOGIC_ZERO;
INT_SUM(52) <= LOGIC_ZERO;
INT_SUM(53) <= LOGIC_ZERO;
INT_SUM(54) <= LOGIC_ZERO;
INT_SUM(55) <= LOGIC_ZERO;
INT_SUM(56) <= LOGIC_ZERO;
INT_SUM(57) <= LOGIC_ZERO;
INT_SUM(58) <= LOGIC_ZERO;
INT_SUM(59) <= LOGIC_ZERO;
INT_SUM(60) <= LOGIC_ZERO;
INT_SUM(61) <= LOGIC_ZERO;
INT_SUM(62) <= LOGIC_ZERO;
INT_SUM(63) <= LOGIC_ZERO;
INT_SUMR(35 to 63) <= INT_SUM(35 to 63);
INT_CARRYR(35 to 63) <= INT_CARRY(35 to 63);
INT_CARRYR(0) <= INT_CARRY(0);
reg : if MULPIPE /= 0 generate
process (PHI) begin
if rising_edge(PHI ) then
if (holdn = '1') then
INT_SUMR(0 to 34) <= INT_SUM(0 to 34);
INT_CARRYR(1 to 34) <= INT_CARRY(1 to 34);
end if;
end if;
end process;
end generate;
noreg : if MULPIPE = 0 generate
INT_SUMR(0 to 34) <= INT_SUM(0 to 34);
INT_CARRYR(1 to 34) <= INT_CARRY(1 to 34);
end generate;
D:DBLCADDER_64_64
port map
(
OPA(0 to 63) => INT_SUMR(0 to 63),
OPB(0 to 63) => INT_CARRYR(0 to 63),
CIN => LOGIC_ZERO,
PHI => PHI ,
SUM(0 to 63) => RESULT(0 to 63)
);
end MULTIPLIER;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity BOOTHCODER_34_10 is
port
(
OPA: in std_logic_vector(0 to 33);
OPB: in std_logic_vector(0 to 9);
SUMMAND: out std_logic_vector(0 to 184)
);
end BOOTHCODER_34_10;
architecture BOOTHCODER of BOOTHCODER_34_10 is
-- Internal signal in Booth structure
signal INV_MULTIPLICAND: std_logic_vector(0 to 33);
signal INT_MULTIPLIER: std_logic_vector(0 to 19);
signal LOGIC_ONE, LOGIC_ZERO: std_logic;
begin
LOGIC_ONE <= '1';
LOGIC_ZERO <= '0';
-- Begin decoder block 1
DEC_0:DECODER -- Decoder of multiplier operand
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3)
);
-- End decoder block 1
-- Begin partial product 1
INV_MULTIPLICAND(0) <= NOT OPA(0);
PPL_0:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(0)
);
RGATE_0:R_GATE
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
PPBIT => SUMMAND(1)
);
INV_MULTIPLICAND(1) <= NOT OPA(1);
PPM_0:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(2)
);
INV_MULTIPLICAND(2) <= NOT OPA(2);
PPM_1:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(3)
);
INV_MULTIPLICAND(3) <= NOT OPA(3);
PPM_2:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(6)
);
INV_MULTIPLICAND(4) <= NOT OPA(4);
PPM_3:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(8)
);
INV_MULTIPLICAND(5) <= NOT OPA(5);
PPM_4:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(12)
);
INV_MULTIPLICAND(6) <= NOT OPA(6);
PPM_5:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(15)
);
INV_MULTIPLICAND(7) <= NOT OPA(7);
PPM_6:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(20)
);
INV_MULTIPLICAND(8) <= NOT OPA(8);
PPM_7:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(24)
);
INV_MULTIPLICAND(9) <= NOT OPA(9);
PPM_8:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(30)
);
INV_MULTIPLICAND(10) <= NOT OPA(10);
PPM_9:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(35)
);
INV_MULTIPLICAND(11) <= NOT OPA(11);
PPM_10:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(40)
);
INV_MULTIPLICAND(12) <= NOT OPA(12);
PPM_11:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(45)
);
INV_MULTIPLICAND(13) <= NOT OPA(13);
PPM_12:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(50)
);
INV_MULTIPLICAND(14) <= NOT OPA(14);
PPM_13:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(55)
);
INV_MULTIPLICAND(15) <= NOT OPA(15);
PPM_14:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(60)
);
INV_MULTIPLICAND(16) <= NOT OPA(16);
PPM_15:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(65)
);
INV_MULTIPLICAND(17) <= NOT OPA(17);
PPM_16:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(70)
);
INV_MULTIPLICAND(18) <= NOT OPA(18);
PPM_17:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(75)
);
INV_MULTIPLICAND(19) <= NOT OPA(19);
PPM_18:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(80)
);
INV_MULTIPLICAND(20) <= NOT OPA(20);
PPM_19:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(85)
);
INV_MULTIPLICAND(21) <= NOT OPA(21);
PPM_20:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(90)
);
INV_MULTIPLICAND(22) <= NOT OPA(22);
PPM_21:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(95)
);
INV_MULTIPLICAND(23) <= NOT OPA(23);
PPM_22:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(100)
);
INV_MULTIPLICAND(24) <= NOT OPA(24);
PPM_23:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(105)
);
INV_MULTIPLICAND(25) <= NOT OPA(25);
PPM_24:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(110)
);
INV_MULTIPLICAND(26) <= NOT OPA(26);
PPM_25:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(115)
);
INV_MULTIPLICAND(27) <= NOT OPA(27);
PPM_26:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(120)
);
INV_MULTIPLICAND(28) <= NOT OPA(28);
PPM_27:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(125)
);
INV_MULTIPLICAND(29) <= NOT OPA(29);
PPM_28:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(130)
);
INV_MULTIPLICAND(30) <= NOT OPA(30);
PPM_29:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(135)
);
INV_MULTIPLICAND(31) <= NOT OPA(31);
PPM_30:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(140)
);
INV_MULTIPLICAND(32) <= NOT OPA(32);
PPM_31:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(145)
);
INV_MULTIPLICAND(33) <= NOT OPA(33);
PPM_32:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(150)
);
PPH_0:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(155)
);
SUMMAND(156) <= '1';
-- Begin partial product 1
-- Begin decoder block 2
DEC_1:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7)
);
-- End decoder block 2
-- Begin partial product 2
PPL_1:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(4)
);
RGATE_1:R_GATE
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
PPBIT => SUMMAND(5)
);
PPM_33:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(7)
);
PPM_34:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(9)
);
PPM_35:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(13)
);
PPM_36:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(16)
);
PPM_37:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(21)
);
PPM_38:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(25)
);
PPM_39:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(31)
);
PPM_40:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(36)
);
PPM_41:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(41)
);
PPM_42:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(46)
);
PPM_43:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(51)
);
PPM_44:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(56)
);
PPM_45:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(61)
);
PPM_46:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(66)
);
PPM_47:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(71)
);
PPM_48:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(76)
);
PPM_49:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(81)
);
PPM_50:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(86)
);
PPM_51:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(91)
);
PPM_52:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(96)
);
PPM_53:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(101)
);
PPM_54:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(106)
);
PPM_55:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(111)
);
PPM_56:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(116)
);
PPM_57:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(121)
);
PPM_58:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(126)
);
PPM_59:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(131)
);
PPM_60:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(136)
);
PPM_61:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(141)
);
PPM_62:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(146)
);
PPM_63:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(151)
);
PPM_64:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(157)
);
PPM_65:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(161)
);
SUMMAND(162) <= LOGIC_ONE;
PPH_1:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(166)
);
-- Begin partial product 2
-- Begin decoder block 3
DEC_2:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11)
);
-- End decoder block 3
-- Begin partial product 3
PPL_2:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(10)
);
RGATE_2:R_GATE
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
PPBIT => SUMMAND(11)
);
PPM_66:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(14)
);
PPM_67:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(17)
);
PPM_68:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(22)
);
PPM_69:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(26)
);
PPM_70:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(32)
);
PPM_71:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(37)
);
PPM_72:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(42)
);
PPM_73:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(47)
);
PPM_74:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(52)
);
PPM_75:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(57)
);
PPM_76:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(62)
);
PPM_77:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(67)
);
PPM_78:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(72)
);
PPM_79:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(77)
);
PPM_80:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(82)
);
PPM_81:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(87)
);
PPM_82:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(92)
);
PPM_83:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(97)
);
PPM_84:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(102)
);
PPM_85:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(107)
);
PPM_86:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(112)
);
PPM_87:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(117)
);
PPM_88:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(122)
);
PPM_89:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(127)
);
PPM_90:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(132)
);
PPM_91:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(137)
);
PPM_92:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(142)
);
PPM_93:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(147)
);
PPM_94:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(152)
);
PPM_95:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(158)
);
PPM_96:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(163)
);
PPM_97:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(167)
);
PPM_98:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(170)
);
SUMMAND(171) <= LOGIC_ONE;
PPH_2:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(174)
);
-- Begin partial product 3
-- Begin decoder block 4
DEC_3:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15)
);
-- End decoder block 4
-- Begin partial product 4
PPL_3:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(18)
);
RGATE_3:R_GATE
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
PPBIT => SUMMAND(19)
);
PPM_99:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(23)
);
PPM_100:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(27)
);
PPM_101:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(33)
);
PPM_102:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(38)
);
PPM_103:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(43)
);
PPM_104:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(48)
);
PPM_105:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(53)
);
PPM_106:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(58)
);
PPM_107:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(63)
);
PPM_108:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(68)
);
PPM_109:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(73)
);
PPM_110:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(78)
);
PPM_111:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(83)
);
PPM_112:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(88)
);
PPM_113:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(93)
);
PPM_114:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(98)
);
PPM_115:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(103)
);
PPM_116:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(108)
);
PPM_117:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(113)
);
PPM_118:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(118)
);
PPM_119:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(123)
);
PPM_120:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(128)
);
PPM_121:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(133)
);
PPM_122:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(138)
);
PPM_123:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(143)
);
PPM_124:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(148)
);
PPM_125:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(153)
);
PPM_126:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(159)
);
PPM_127:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(164)
);
PPM_128:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(168)
);
PPM_129:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(172)
);
PPM_130:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(175)
);
PPM_131:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(177)
);
SUMMAND(178) <= LOGIC_ONE;
PPH_3:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(180)
);
-- Begin partial product 4
-- Begin decoder block 5
DEC_4:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19)
);
-- End decoder block 5
-- Begin partial product 5
PPL_4:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(28)
);
RGATE_4:R_GATE
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
PPBIT => SUMMAND(29)
);
PPM_132:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(34)
);
PPM_133:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(39)
);
PPM_134:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(44)
);
PPM_135:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(49)
);
PPM_136:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(54)
);
PPM_137:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(59)
);
PPM_138:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(64)
);
PPM_139:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(69)
);
PPM_140:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(74)
);
PPM_141:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(79)
);
PPM_142:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(84)
);
PPM_143:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(89)
);
PPM_144:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(94)
);
PPM_145:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(99)
);
PPM_146:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(104)
);
PPM_147:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(109)
);
PPM_148:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(114)
);
PPM_149:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(119)
);
PPM_150:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(124)
);
PPM_151:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(129)
);
PPM_152:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(134)
);
PPM_153:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(139)
);
PPM_154:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(144)
);
PPM_155:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(149)
);
PPM_156:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(154)
);
PPM_157:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(160)
);
PPM_158:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(165)
);
PPM_159:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(169)
);
PPM_160:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(173)
);
PPM_161:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(176)
);
PPM_162:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(179)
);
PPM_163:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(181)
);
PPM_164:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(182)
);
SUMMAND(183) <= LOGIC_ONE;
PPH_4:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(184)
);
-- Begin partial product 5
end BOOTHCODER;
------------------------------------------------------------
-- END: Architectures used with the Modified Booth recoding
------------------------------------------------------------
------------------------------------------------------------
-- START: Architectures used with the Wallace-tree
------------------------------------------------------------
--
-- Wallace tree architecture
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity WALLACE_34_10 is
port
(
SUMMAND: in std_logic_vector(0 to 184);
CARRY: out std_logic_vector(0 to 41);
SUM: out std_logic_vector(0 to 42)
);
end WALLACE_34_10;
architecture WALLACE of WALLACE_34_10 is
signal INT_CARRY: std_logic_vector(0 to 95);
signal INT_SUM: std_logic_vector(0 to 133);
begin -- netlist
-- Begin WT-branch 1
---- Begin HA stage
HA_0:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(0), DATA_B => SUMMAND(1),
SAVE => SUM(0), CARRY => CARRY(0)
);
---- End HA stage
-- End WT-branch 1
-- Begin WT-branch 2
---- Begin NO stage
SUM(1) <= SUMMAND(2); -- At Level 1
CARRY(1) <= '0';
---- End NO stage
-- End WT-branch 2
-- Begin WT-branch 3
---- Begin FA stage
FA_0:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5),
SAVE => SUM(2), CARRY => CARRY(2)
);
---- End FA stage
-- End WT-branch 3
-- Begin WT-branch 4
---- Begin HA stage
HA_1:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(6), DATA_B => SUMMAND(7),
SAVE => SUM(3), CARRY => CARRY(3)
);
---- End HA stage
-- End WT-branch 4
-- Begin WT-branch 5
---- Begin FA stage
FA_1:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10),
SAVE => INT_SUM(0), CARRY => INT_CARRY(0)
);
---- End FA stage
---- Begin NO stage
INT_SUM(1) <= SUMMAND(11); -- At Level 1
---- End NO stage
---- Begin HA stage
HA_2:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(0), DATA_B => INT_SUM(1),
SAVE => SUM(4), CARRY => CARRY(4)
);
---- End HA stage
-- End WT-branch 5
-- Begin WT-branch 6
---- Begin FA stage
FA_2:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14),
SAVE => INT_SUM(2), CARRY => INT_CARRY(1)
);
---- End FA stage
---- Begin HA stage
HA_3:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0),
SAVE => SUM(5), CARRY => CARRY(5)
);
---- End HA stage
-- End WT-branch 6
-- Begin WT-branch 7
---- Begin FA stage
FA_3:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17),
SAVE => INT_SUM(3), CARRY => INT_CARRY(2)
);
---- End FA stage
---- Begin HA stage
HA_4:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(18), DATA_B => SUMMAND(19),
SAVE => INT_SUM(4), CARRY => INT_CARRY(3)
);
---- End HA stage
---- Begin FA stage
FA_4:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1),
SAVE => SUM(6), CARRY => CARRY(6)
);
---- End FA stage
-- End WT-branch 7
-- Begin WT-branch 8
---- Begin FA stage
FA_5:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22),
SAVE => INT_SUM(5), CARRY => INT_CARRY(4)
);
---- End FA stage
---- Begin NO stage
INT_SUM(6) <= SUMMAND(23); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_6:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2),
SAVE => INT_SUM(7), CARRY => INT_CARRY(5)
);
---- End FA stage
---- Begin NO stage
INT_SUM(8) <= INT_CARRY(3); -- At Level 2
---- End NO stage
---- Begin HA stage
HA_5:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(7), DATA_B => INT_SUM(8),
SAVE => SUM(7), CARRY => CARRY(7)
);
---- End HA stage
-- End WT-branch 8
-- Begin WT-branch 9
---- Begin FA stage
FA_7:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26),
SAVE => INT_SUM(9), CARRY => INT_CARRY(6)
);
---- End FA stage
---- Begin FA stage
FA_8:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29),
SAVE => INT_SUM(10), CARRY => INT_CARRY(7)
);
---- End FA stage
---- Begin FA stage
FA_9:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4),
SAVE => INT_SUM(11), CARRY => INT_CARRY(8)
);
---- End FA stage
---- Begin HA stage
HA_6:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5),
SAVE => SUM(8), CARRY => CARRY(8)
);
---- End HA stage
-- End WT-branch 9
-- Begin WT-branch 10
---- Begin FA stage
FA_10:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32),
SAVE => INT_SUM(12), CARRY => INT_CARRY(9)
);
---- End FA stage
---- Begin HA stage
HA_7:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(33), DATA_B => SUMMAND(34),
SAVE => INT_SUM(13), CARRY => INT_CARRY(10)
);
---- End HA stage
---- Begin FA stage
FA_11:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6),
SAVE => INT_SUM(14), CARRY => INT_CARRY(11)
);
---- End FA stage
---- Begin NO stage
INT_SUM(15) <= INT_CARRY(7); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_12:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8),
SAVE => SUM(9), CARRY => CARRY(9)
);
---- End FA stage
-- End WT-branch 10
-- Begin WT-branch 11
---- Begin FA stage
FA_13:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37),
SAVE => INT_SUM(16), CARRY => INT_CARRY(12)
);
---- End FA stage
---- Begin HA stage
HA_8:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(38), DATA_B => SUMMAND(39),
SAVE => INT_SUM(17), CARRY => INT_CARRY(13)
);
---- End HA stage
---- Begin FA stage
FA_14:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_CARRY(9),
SAVE => INT_SUM(18), CARRY => INT_CARRY(14)
);
---- End FA stage
---- Begin NO stage
INT_SUM(19) <= INT_CARRY(10); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_15:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(18), DATA_B => INT_SUM(19), DATA_C => INT_CARRY(11),
SAVE => SUM(10), CARRY => CARRY(10)
);
---- End FA stage
-- End WT-branch 11
-- Begin WT-branch 12
---- Begin FA stage
FA_16:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(40), DATA_B => SUMMAND(41), DATA_C => SUMMAND(42),
SAVE => INT_SUM(20), CARRY => INT_CARRY(15)
);
---- End FA stage
---- Begin HA stage
HA_9:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(43), DATA_B => SUMMAND(44),
SAVE => INT_SUM(21), CARRY => INT_CARRY(16)
);
---- End HA stage
---- Begin FA stage
FA_17:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(20), DATA_B => INT_SUM(21), DATA_C => INT_CARRY(12),
SAVE => INT_SUM(22), CARRY => INT_CARRY(17)
);
---- End FA stage
---- Begin NO stage
INT_SUM(23) <= INT_CARRY(13); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_18:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(22), DATA_B => INT_SUM(23), DATA_C => INT_CARRY(14),
SAVE => SUM(11), CARRY => CARRY(11)
);
---- End FA stage
-- End WT-branch 12
-- Begin WT-branch 13
---- Begin FA stage
FA_19:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47),
SAVE => INT_SUM(24), CARRY => INT_CARRY(18)
);
---- End FA stage
---- Begin HA stage
HA_10:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(48), DATA_B => SUMMAND(49),
SAVE => INT_SUM(25), CARRY => INT_CARRY(19)
);
---- End HA stage
---- Begin FA stage
FA_20:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(24), DATA_B => INT_SUM(25), DATA_C => INT_CARRY(15),
SAVE => INT_SUM(26), CARRY => INT_CARRY(20)
);
---- End FA stage
---- Begin NO stage
INT_SUM(27) <= INT_CARRY(16); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_21:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(26), DATA_B => INT_SUM(27), DATA_C => INT_CARRY(17),
SAVE => SUM(12), CARRY => CARRY(12)
);
---- End FA stage
-- End WT-branch 13
-- Begin WT-branch 14
---- Begin FA stage
FA_22:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(50), DATA_B => SUMMAND(51), DATA_C => SUMMAND(52),
SAVE => INT_SUM(28), CARRY => INT_CARRY(21)
);
---- End FA stage
---- Begin HA stage
HA_11:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(53), DATA_B => SUMMAND(54),
SAVE => INT_SUM(29), CARRY => INT_CARRY(22)
);
---- End HA stage
---- Begin FA stage
FA_23:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(28), DATA_B => INT_SUM(29), DATA_C => INT_CARRY(18),
SAVE => INT_SUM(30), CARRY => INT_CARRY(23)
);
---- End FA stage
---- Begin NO stage
INT_SUM(31) <= INT_CARRY(19); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_24:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(30), DATA_B => INT_SUM(31), DATA_C => INT_CARRY(20),
SAVE => SUM(13), CARRY => CARRY(13)
);
---- End FA stage
-- End WT-branch 14
-- Begin WT-branch 15
---- Begin FA stage
FA_25:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(55), DATA_B => SUMMAND(56), DATA_C => SUMMAND(57),
SAVE => INT_SUM(32), CARRY => INT_CARRY(24)
);
---- End FA stage
---- Begin HA stage
HA_12:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(58), DATA_B => SUMMAND(59),
SAVE => INT_SUM(33), CARRY => INT_CARRY(25)
);
---- End HA stage
---- Begin FA stage
FA_26:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(32), DATA_B => INT_SUM(33), DATA_C => INT_CARRY(21),
SAVE => INT_SUM(34), CARRY => INT_CARRY(26)
);
---- End FA stage
---- Begin NO stage
INT_SUM(35) <= INT_CARRY(22); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_27:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_CARRY(23),
SAVE => SUM(14), CARRY => CARRY(14)
);
---- End FA stage
-- End WT-branch 15
-- Begin WT-branch 16
---- Begin FA stage
FA_28:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(60), DATA_B => SUMMAND(61), DATA_C => SUMMAND(62),
SAVE => INT_SUM(36), CARRY => INT_CARRY(27)
);
---- End FA stage
---- Begin HA stage
HA_13:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(63), DATA_B => SUMMAND(64),
SAVE => INT_SUM(37), CARRY => INT_CARRY(28)
);
---- End HA stage
---- Begin FA stage
FA_29:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(36), DATA_B => INT_SUM(37), DATA_C => INT_CARRY(24),
SAVE => INT_SUM(38), CARRY => INT_CARRY(29)
);
---- End FA stage
---- Begin NO stage
INT_SUM(39) <= INT_CARRY(25); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_30:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(38), DATA_B => INT_SUM(39), DATA_C => INT_CARRY(26),
SAVE => SUM(15), CARRY => CARRY(15)
);
---- End FA stage
-- End WT-branch 16
-- Begin WT-branch 17
---- Begin FA stage
FA_31:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(65), DATA_B => SUMMAND(66), DATA_C => SUMMAND(67),
SAVE => INT_SUM(40), CARRY => INT_CARRY(30)
);
---- End FA stage
---- Begin HA stage
HA_14:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(68), DATA_B => SUMMAND(69),
SAVE => INT_SUM(41), CARRY => INT_CARRY(31)
);
---- End HA stage
---- Begin FA stage
FA_32:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(40), DATA_B => INT_SUM(41), DATA_C => INT_CARRY(27),
SAVE => INT_SUM(42), CARRY => INT_CARRY(32)
);
---- End FA stage
---- Begin NO stage
INT_SUM(43) <= INT_CARRY(28); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_33:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(42), DATA_B => INT_SUM(43), DATA_C => INT_CARRY(29),
SAVE => SUM(16), CARRY => CARRY(16)
);
---- End FA stage
-- End WT-branch 17
-- Begin WT-branch 18
---- Begin FA stage
FA_34:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(70), DATA_B => SUMMAND(71), DATA_C => SUMMAND(72),
SAVE => INT_SUM(44), CARRY => INT_CARRY(33)
);
---- End FA stage
---- Begin HA stage
HA_15:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(73), DATA_B => SUMMAND(74),
SAVE => INT_SUM(45), CARRY => INT_CARRY(34)
);
---- End HA stage
---- Begin FA stage
FA_35:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(30),
SAVE => INT_SUM(46), CARRY => INT_CARRY(35)
);
---- End FA stage
---- Begin NO stage
INT_SUM(47) <= INT_CARRY(31); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_36:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(32),
SAVE => SUM(17), CARRY => CARRY(17)
);
---- End FA stage
-- End WT-branch 18
-- Begin WT-branch 19
---- Begin FA stage
FA_37:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77),
SAVE => INT_SUM(48), CARRY => INT_CARRY(36)
);
---- End FA stage
---- Begin HA stage
HA_16:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(78), DATA_B => SUMMAND(79),
SAVE => INT_SUM(49), CARRY => INT_CARRY(37)
);
---- End HA stage
---- Begin FA stage
FA_38:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_CARRY(33),
SAVE => INT_SUM(50), CARRY => INT_CARRY(38)
);
---- End FA stage
---- Begin NO stage
INT_SUM(51) <= INT_CARRY(34); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_39:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(50), DATA_B => INT_SUM(51), DATA_C => INT_CARRY(35),
SAVE => SUM(18), CARRY => CARRY(18)
);
---- End FA stage
-- End WT-branch 19
-- Begin WT-branch 20
---- Begin FA stage
FA_40:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82),
SAVE => INT_SUM(52), CARRY => INT_CARRY(39)
);
---- End FA stage
---- Begin HA stage
HA_17:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(83), DATA_B => SUMMAND(84),
SAVE => INT_SUM(53), CARRY => INT_CARRY(40)
);
---- End HA stage
---- Begin FA stage
FA_41:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(52), DATA_B => INT_SUM(53), DATA_C => INT_CARRY(36),
SAVE => INT_SUM(54), CARRY => INT_CARRY(41)
);
---- End FA stage
---- Begin NO stage
INT_SUM(55) <= INT_CARRY(37); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_42:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(54), DATA_B => INT_SUM(55), DATA_C => INT_CARRY(38),
SAVE => SUM(19), CARRY => CARRY(19)
);
---- End FA stage
-- End WT-branch 20
-- Begin WT-branch 21
---- Begin FA stage
FA_43:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(85), DATA_B => SUMMAND(86), DATA_C => SUMMAND(87),
SAVE => INT_SUM(56), CARRY => INT_CARRY(42)
);
---- End FA stage
---- Begin HA stage
HA_18:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(88), DATA_B => SUMMAND(89),
SAVE => INT_SUM(57), CARRY => INT_CARRY(43)
);
---- End HA stage
---- Begin FA stage
FA_44:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(56), DATA_B => INT_SUM(57), DATA_C => INT_CARRY(39),
SAVE => INT_SUM(58), CARRY => INT_CARRY(44)
);
---- End FA stage
---- Begin NO stage
INT_SUM(59) <= INT_CARRY(40); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_45:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(58), DATA_B => INT_SUM(59), DATA_C => INT_CARRY(41),
SAVE => SUM(20), CARRY => CARRY(20)
);
---- End FA stage
-- End WT-branch 21
-- Begin WT-branch 22
---- Begin FA stage
FA_46:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92),
SAVE => INT_SUM(60), CARRY => INT_CARRY(45)
);
---- End FA stage
---- Begin HA stage
HA_19:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(93), DATA_B => SUMMAND(94),
SAVE => INT_SUM(61), CARRY => INT_CARRY(46)
);
---- End HA stage
---- Begin FA stage
FA_47:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(60), DATA_B => INT_SUM(61), DATA_C => INT_CARRY(42),
SAVE => INT_SUM(62), CARRY => INT_CARRY(47)
);
---- End FA stage
---- Begin NO stage
INT_SUM(63) <= INT_CARRY(43); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_48:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(44),
SAVE => SUM(21), CARRY => CARRY(21)
);
---- End FA stage
-- End WT-branch 22
-- Begin WT-branch 23
---- Begin FA stage
FA_49:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(95), DATA_B => SUMMAND(96), DATA_C => SUMMAND(97),
SAVE => INT_SUM(64), CARRY => INT_CARRY(48)
);
---- End FA stage
---- Begin HA stage
HA_20:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(98), DATA_B => SUMMAND(99),
SAVE => INT_SUM(65), CARRY => INT_CARRY(49)
);
---- End HA stage
---- Begin FA stage
FA_50:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_CARRY(45),
SAVE => INT_SUM(66), CARRY => INT_CARRY(50)
);
---- End FA stage
---- Begin NO stage
INT_SUM(67) <= INT_CARRY(46); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_51:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(66), DATA_B => INT_SUM(67), DATA_C => INT_CARRY(47),
SAVE => SUM(22), CARRY => CARRY(22)
);
---- End FA stage
-- End WT-branch 23
-- Begin WT-branch 24
---- Begin FA stage
FA_52:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(100), DATA_B => SUMMAND(101), DATA_C => SUMMAND(102),
SAVE => INT_SUM(68), CARRY => INT_CARRY(51)
);
---- End FA stage
---- Begin HA stage
HA_21:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(103), DATA_B => SUMMAND(104),
SAVE => INT_SUM(69), CARRY => INT_CARRY(52)
);
---- End HA stage
---- Begin FA stage
FA_53:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(68), DATA_B => INT_SUM(69), DATA_C => INT_CARRY(48),
SAVE => INT_SUM(70), CARRY => INT_CARRY(53)
);
---- End FA stage
---- Begin NO stage
INT_SUM(71) <= INT_CARRY(49); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_54:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(70), DATA_B => INT_SUM(71), DATA_C => INT_CARRY(50),
SAVE => SUM(23), CARRY => CARRY(23)
);
---- End FA stage
-- End WT-branch 24
-- Begin WT-branch 25
---- Begin FA stage
FA_55:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107),
SAVE => INT_SUM(72), CARRY => INT_CARRY(54)
);
---- End FA stage
---- Begin HA stage
HA_22:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(108), DATA_B => SUMMAND(109),
SAVE => INT_SUM(73), CARRY => INT_CARRY(55)
);
---- End HA stage
---- Begin FA stage
FA_56:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(72), DATA_B => INT_SUM(73), DATA_C => INT_CARRY(51),
SAVE => INT_SUM(74), CARRY => INT_CARRY(56)
);
---- End FA stage
---- Begin NO stage
INT_SUM(75) <= INT_CARRY(52); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_57:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(74), DATA_B => INT_SUM(75), DATA_C => INT_CARRY(53),
SAVE => SUM(24), CARRY => CARRY(24)
);
---- End FA stage
-- End WT-branch 25
-- Begin WT-branch 26
---- Begin FA stage
FA_58:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(110), DATA_B => SUMMAND(111), DATA_C => SUMMAND(112),
SAVE => INT_SUM(76), CARRY => INT_CARRY(57)
);
---- End FA stage
---- Begin HA stage
HA_23:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(113), DATA_B => SUMMAND(114),
SAVE => INT_SUM(77), CARRY => INT_CARRY(58)
);
---- End HA stage
---- Begin FA stage
FA_59:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(54),
SAVE => INT_SUM(78), CARRY => INT_CARRY(59)
);
---- End FA stage
---- Begin NO stage
INT_SUM(79) <= INT_CARRY(55); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_60:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_CARRY(56),
SAVE => SUM(25), CARRY => CARRY(25)
);
---- End FA stage
-- End WT-branch 26
-- Begin WT-branch 27
---- Begin FA stage
FA_61:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(115), DATA_B => SUMMAND(116), DATA_C => SUMMAND(117),
SAVE => INT_SUM(80), CARRY => INT_CARRY(60)
);
---- End FA stage
---- Begin HA stage
HA_24:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(118), DATA_B => SUMMAND(119),
SAVE => INT_SUM(81), CARRY => INT_CARRY(61)
);
---- End HA stage
---- Begin FA stage
FA_62:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(80), DATA_B => INT_SUM(81), DATA_C => INT_CARRY(57),
SAVE => INT_SUM(82), CARRY => INT_CARRY(62)
);
---- End FA stage
---- Begin NO stage
INT_SUM(83) <= INT_CARRY(58); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_63:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(82), DATA_B => INT_SUM(83), DATA_C => INT_CARRY(59),
SAVE => SUM(26), CARRY => CARRY(26)
);
---- End FA stage
-- End WT-branch 27
-- Begin WT-branch 28
---- Begin FA stage
FA_64:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122),
SAVE => INT_SUM(84), CARRY => INT_CARRY(63)
);
---- End FA stage
---- Begin HA stage
HA_25:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(123), DATA_B => SUMMAND(124),
SAVE => INT_SUM(85), CARRY => INT_CARRY(64)
);
---- End HA stage
---- Begin FA stage
FA_65:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(84), DATA_B => INT_SUM(85), DATA_C => INT_CARRY(60),
SAVE => INT_SUM(86), CARRY => INT_CARRY(65)
);
---- End FA stage
---- Begin NO stage
INT_SUM(87) <= INT_CARRY(61); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_66:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(86), DATA_B => INT_SUM(87), DATA_C => INT_CARRY(62),
SAVE => SUM(27), CARRY => CARRY(27)
);
---- End FA stage
-- End WT-branch 28
-- Begin WT-branch 29
---- Begin FA stage
FA_67:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(125), DATA_B => SUMMAND(126), DATA_C => SUMMAND(127),
SAVE => INT_SUM(88), CARRY => INT_CARRY(66)
);
---- End FA stage
---- Begin HA stage
HA_26:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(128), DATA_B => SUMMAND(129),
SAVE => INT_SUM(89), CARRY => INT_CARRY(67)
);
---- End HA stage
---- Begin FA stage
FA_68:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(88), DATA_B => INT_SUM(89), DATA_C => INT_CARRY(63),
SAVE => INT_SUM(90), CARRY => INT_CARRY(68)
);
---- End FA stage
---- Begin NO stage
INT_SUM(91) <= INT_CARRY(64); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_69:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(90), DATA_B => INT_SUM(91), DATA_C => INT_CARRY(65),
SAVE => SUM(28), CARRY => CARRY(28)
);
---- End FA stage
-- End WT-branch 29
-- Begin WT-branch 30
---- Begin FA stage
FA_70:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(130), DATA_B => SUMMAND(131), DATA_C => SUMMAND(132),
SAVE => INT_SUM(92), CARRY => INT_CARRY(69)
);
---- End FA stage
---- Begin HA stage
HA_27:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(133), DATA_B => SUMMAND(134),
SAVE => INT_SUM(93), CARRY => INT_CARRY(70)
);
---- End HA stage
---- Begin FA stage
FA_71:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(66),
SAVE => INT_SUM(94), CARRY => INT_CARRY(71)
);
---- End FA stage
---- Begin NO stage
INT_SUM(95) <= INT_CARRY(67); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_72:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(68),
SAVE => SUM(29), CARRY => CARRY(29)
);
---- End FA stage
-- End WT-branch 30
-- Begin WT-branch 31
---- Begin FA stage
FA_73:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137),
SAVE => INT_SUM(96), CARRY => INT_CARRY(72)
);
---- End FA stage
---- Begin HA stage
HA_28:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(138), DATA_B => SUMMAND(139),
SAVE => INT_SUM(97), CARRY => INT_CARRY(73)
);
---- End HA stage
---- Begin FA stage
FA_74:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_CARRY(69),
SAVE => INT_SUM(98), CARRY => INT_CARRY(74)
);
---- End FA stage
---- Begin NO stage
INT_SUM(99) <= INT_CARRY(70); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_75:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(98), DATA_B => INT_SUM(99), DATA_C => INT_CARRY(71),
SAVE => SUM(30), CARRY => CARRY(30)
);
---- End FA stage
-- End WT-branch 31
-- Begin WT-branch 32
---- Begin FA stage
FA_76:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(140), DATA_B => SUMMAND(141), DATA_C => SUMMAND(142),
SAVE => INT_SUM(100), CARRY => INT_CARRY(75)
);
---- End FA stage
---- Begin HA stage
HA_29:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(143), DATA_B => SUMMAND(144),
SAVE => INT_SUM(101), CARRY => INT_CARRY(76)
);
---- End HA stage
---- Begin FA stage
FA_77:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(72),
SAVE => INT_SUM(102), CARRY => INT_CARRY(77)
);
---- End FA stage
---- Begin NO stage
INT_SUM(103) <= INT_CARRY(73); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_78:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_CARRY(74),
SAVE => SUM(31), CARRY => CARRY(31)
);
---- End FA stage
-- End WT-branch 32
-- Begin WT-branch 33
---- Begin FA stage
FA_79:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(145), DATA_B => SUMMAND(146), DATA_C => SUMMAND(147),
SAVE => INT_SUM(104), CARRY => INT_CARRY(78)
);
---- End FA stage
---- Begin HA stage
HA_30:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(148), DATA_B => SUMMAND(149),
SAVE => INT_SUM(105), CARRY => INT_CARRY(79)
);
---- End HA stage
---- Begin FA stage
FA_80:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(104), DATA_B => INT_SUM(105), DATA_C => INT_CARRY(75),
SAVE => INT_SUM(106), CARRY => INT_CARRY(80)
);
---- End FA stage
---- Begin NO stage
INT_SUM(107) <= INT_CARRY(76); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_81:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(106), DATA_B => INT_SUM(107), DATA_C => INT_CARRY(77),
SAVE => SUM(32), CARRY => CARRY(32)
);
---- End FA stage
-- End WT-branch 33
-- Begin WT-branch 34
---- Begin FA stage
FA_82:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(150), DATA_B => SUMMAND(151), DATA_C => SUMMAND(152),
SAVE => INT_SUM(108), CARRY => INT_CARRY(81)
);
---- End FA stage
---- Begin HA stage
HA_31:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(153), DATA_B => SUMMAND(154),
SAVE => INT_SUM(109), CARRY => INT_CARRY(82)
);
---- End HA stage
---- Begin FA stage
FA_83:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(78),
SAVE => INT_SUM(110), CARRY => INT_CARRY(83)
);
---- End FA stage
---- Begin NO stage
INT_SUM(111) <= INT_CARRY(79); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_84:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(80),
SAVE => SUM(33), CARRY => CARRY(33)
);
---- End FA stage
-- End WT-branch 34
-- Begin WT-branch 35
---- Begin FA stage
FA_85:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(155), DATA_B => SUMMAND(156), DATA_C => SUMMAND(157),
SAVE => INT_SUM(112), CARRY => INT_CARRY(84)
);
---- End FA stage
---- Begin FA stage
FA_86:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(158), DATA_B => SUMMAND(159), DATA_C => SUMMAND(160),
SAVE => INT_SUM(113), CARRY => INT_CARRY(85)
);
---- End FA stage
---- Begin FA stage
FA_87:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(112), DATA_B => INT_SUM(113), DATA_C => INT_CARRY(81),
SAVE => INT_SUM(114), CARRY => INT_CARRY(86)
);
---- End FA stage
---- Begin NO stage
INT_SUM(115) <= INT_CARRY(82); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_88:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(114), DATA_B => INT_SUM(115), DATA_C => INT_CARRY(83),
SAVE => SUM(34), CARRY => CARRY(34)
);
---- End FA stage
-- End WT-branch 35
-- Begin WT-branch 36
---- Begin FA stage
FA_89:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(161), DATA_B => SUMMAND(162), DATA_C => SUMMAND(163),
SAVE => INT_SUM(116), CARRY => INT_CARRY(87)
);
---- End FA stage
---- Begin HA stage
HA_32:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(164), DATA_B => SUMMAND(165),
SAVE => INT_SUM(117), CARRY => INT_CARRY(88)
);
---- End HA stage
---- Begin FA stage
FA_90:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(116), DATA_B => INT_SUM(117), DATA_C => INT_CARRY(84),
SAVE => INT_SUM(118), CARRY => INT_CARRY(89)
);
---- End FA stage
---- Begin NO stage
INT_SUM(119) <= INT_CARRY(85); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_91:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(118), DATA_B => INT_SUM(119), DATA_C => INT_CARRY(86),
SAVE => SUM(35), CARRY => CARRY(35)
);
---- End FA stage
-- End WT-branch 36
-- Begin WT-branch 37
---- Begin FA stage
FA_92:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(166), DATA_B => SUMMAND(167), DATA_C => SUMMAND(168),
SAVE => INT_SUM(120), CARRY => INT_CARRY(90)
);
---- End FA stage
---- Begin NO stage
INT_SUM(121) <= SUMMAND(169); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_93:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(120), DATA_B => INT_SUM(121), DATA_C => INT_CARRY(87),
SAVE => INT_SUM(122), CARRY => INT_CARRY(91)
);
---- End FA stage
---- Begin NO stage
INT_SUM(123) <= INT_CARRY(88); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_94:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(89),
SAVE => SUM(36), CARRY => CARRY(36)
);
---- End FA stage
-- End WT-branch 37
-- Begin WT-branch 38
---- Begin FA stage
FA_95:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(170), DATA_B => SUMMAND(171), DATA_C => SUMMAND(172),
SAVE => INT_SUM(124), CARRY => INT_CARRY(92)
);
---- End FA stage
---- Begin NO stage
INT_SUM(125) <= SUMMAND(173); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_96:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(90),
SAVE => INT_SUM(126), CARRY => INT_CARRY(93)
);
---- End FA stage
---- Begin HA stage
HA_33:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(126), DATA_B => INT_CARRY(91),
SAVE => SUM(37), CARRY => CARRY(37)
);
---- End HA stage
-- End WT-branch 38
-- Begin WT-branch 39
---- Begin FA stage
FA_97:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176),
SAVE => INT_SUM(127), CARRY => INT_CARRY(94)
);
---- End FA stage
---- Begin NO stage
INT_SUM(128) <= INT_SUM(127); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(129) <= INT_CARRY(92); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_98:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(128), DATA_B => INT_SUM(129), DATA_C => INT_CARRY(93),
SAVE => SUM(38), CARRY => CARRY(38)
);
---- End FA stage
-- End WT-branch 39
-- Begin WT-branch 40
---- Begin FA stage
FA_99:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179),
SAVE => INT_SUM(130), CARRY => INT_CARRY(95)
);
---- End FA stage
---- Begin NO stage
INT_SUM(131) <= INT_CARRY(94); -- At Level 2
---- End NO stage
---- Begin HA stage
HA_34:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(130), DATA_B => INT_SUM(131),
SAVE => SUM(39), CARRY => CARRY(39)
);
---- End HA stage
-- End WT-branch 40
-- Begin WT-branch 41
---- Begin NO stage
INT_SUM(132) <= SUMMAND(180); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(133) <= SUMMAND(181); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_100:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(95),
SAVE => SUM(40), CARRY => CARRY(40)
);
---- End FA stage
-- End WT-branch 41
-- Begin WT-branch 42
---- Begin HA stage
HA_35:HALF_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(182), DATA_B => SUMMAND(183),
SAVE => SUM(41), CARRY => CARRY(41)
);
---- End HA stage
-- End WT-branch 42
-- Begin WT-branch 43
---- Begin NO stage
SUM(42) <= SUMMAND(184); -- At Level 3
---- End NO stage
-- End WT-branch 43
end WALLACE;
------------------------------------------------------------
-- END: Architectures used with the Wallace-tree
------------------------------------------------------------
------------------------------------------------------------
-- START: Architectures used with the multiplier
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity MULTIPLIER_34_10 is
port
(
MULTIPLICAND: in std_logic_vector(0 to 33);
MULTIPLIER: in std_logic_vector(0 to 9);
PHI: in std_logic;
RESULT: out std_logic_vector(0 to 63)
);
end MULTIPLIER_34_10;
------------------------------------------------------------
-- End: Multiplier Entitiy
architecture MULTIPLIER of MULTIPLIER_34_10 is
signal PPBIT:std_logic_vector(0 to 184);
signal INT_CARRY: std_logic_vector(0 to 64);
signal INT_SUM: std_logic_vector(0 to 63);
signal LOGIC_ZERO: std_logic;
begin -- Architecture
LOGIC_ZERO <= '0';
B:BOOTHCODER_34_10
port map
(
OPA(0 to 33) => MULTIPLICAND(0 to 33),
OPB(0 to 9) => MULTIPLIER(0 to 9),
SUMMAND(0 to 184) => PPBIT(0 to 184)
);
W:WALLACE_34_10
port map
(
SUMMAND(0 to 184) => PPBIT(0 to 184),
CARRY(0 to 41) => INT_CARRY(1 to 42),
SUM(0 to 42) => INT_SUM(0 to 42)
);
INT_CARRY(0) <= LOGIC_ZERO;
INT_CARRY(43) <= LOGIC_ZERO;
INT_CARRY(44) <= LOGIC_ZERO;
INT_CARRY(45) <= LOGIC_ZERO;
INT_CARRY(46) <= LOGIC_ZERO;
INT_CARRY(47) <= LOGIC_ZERO;
INT_CARRY(48) <= LOGIC_ZERO;
INT_CARRY(49) <= LOGIC_ZERO;
INT_CARRY(50) <= LOGIC_ZERO;
INT_CARRY(51) <= LOGIC_ZERO;
INT_CARRY(52) <= LOGIC_ZERO;
INT_CARRY(53) <= LOGIC_ZERO;
INT_CARRY(54) <= LOGIC_ZERO;
INT_CARRY(55) <= LOGIC_ZERO;
INT_CARRY(56) <= LOGIC_ZERO;
INT_CARRY(57) <= LOGIC_ZERO;
INT_CARRY(58) <= LOGIC_ZERO;
INT_CARRY(59) <= LOGIC_ZERO;
INT_CARRY(60) <= LOGIC_ZERO;
INT_CARRY(61) <= LOGIC_ZERO;
INT_CARRY(62) <= LOGIC_ZERO;
INT_CARRY(63) <= LOGIC_ZERO;
INT_SUM(43) <= LOGIC_ZERO;
INT_SUM(44) <= LOGIC_ZERO;
INT_SUM(45) <= LOGIC_ZERO;
INT_SUM(46) <= LOGIC_ZERO;
INT_SUM(47) <= LOGIC_ZERO;
INT_SUM(48) <= LOGIC_ZERO;
INT_SUM(49) <= LOGIC_ZERO;
INT_SUM(50) <= LOGIC_ZERO;
INT_SUM(51) <= LOGIC_ZERO;
INT_SUM(52) <= LOGIC_ZERO;
INT_SUM(53) <= LOGIC_ZERO;
INT_SUM(54) <= LOGIC_ZERO;
INT_SUM(55) <= LOGIC_ZERO;
INT_SUM(56) <= LOGIC_ZERO;
INT_SUM(57) <= LOGIC_ZERO;
INT_SUM(58) <= LOGIC_ZERO;
INT_SUM(59) <= LOGIC_ZERO;
INT_SUM(60) <= LOGIC_ZERO;
INT_SUM(61) <= LOGIC_ZERO;
INT_SUM(62) <= LOGIC_ZERO;
INT_SUM(63) <= LOGIC_ZERO;
D:DBLCADDER_64_64
port map
(
OPA(0 to 63) => INT_SUM(0 to 63),
OPB(0 to 63) => INT_CARRY(0 to 63),
CIN => LOGIC_ZERO,
PHI => PHI,
SUM(0 to 63) => RESULT(0 to 63)
);
end MULTIPLIER;
------------------------------------------------------------
-- END: Architectures used with the multiplier
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity MUL_33_9 is
port(X: in std_logic_vector(32 downto 0);
Y: in std_logic_vector(8 downto 0);
P: out std_logic_vector(41 downto 0));
end MUL_33_9;
library ieee;
use ieee.std_logic_1164.all;
architecture A of MUL_33_9 is
signal A: std_logic_vector(0 to 33);
signal B: std_logic_vector(0 to 9);
signal Q: std_logic_vector(0 to 63);
signal CLK: std_logic;
begin
U1: MULTIPLIER_34_10 port map(A,B,CLK,Q);
-- std_logic_vector reversals to incorporate decreasing vectors
A(0) <= X(0);
A(1) <= X(1);
A(2) <= X(2);
A(3) <= X(3);
A(4) <= X(4);
A(5) <= X(5);
A(6) <= X(6);
A(7) <= X(7);
A(8) <= X(8);
A(9) <= X(9);
A(10) <= X(10);
A(11) <= X(11);
A(12) <= X(12);
A(13) <= X(13);
A(14) <= X(14);
A(15) <= X(15);
A(16) <= X(16);
A(17) <= X(17);
A(18) <= X(18);
A(19) <= X(19);
A(20) <= X(20);
A(21) <= X(21);
A(22) <= X(22);
A(23) <= X(23);
A(24) <= X(24);
A(25) <= X(25);
A(26) <= X(26);
A(27) <= X(27);
A(28) <= X(28);
A(29) <= X(29);
A(30) <= X(30);
A(31) <= X(31);
A(32) <= X(32);
A(33) <= X(32);
B(0) <= Y(0);
B(1) <= Y(1);
B(2) <= Y(2);
B(3) <= Y(3);
B(4) <= Y(4);
B(5) <= Y(5);
B(6) <= Y(6);
B(7) <= Y(7);
B(8) <= Y(8);
B(9) <= Y(8);
P(0) <= Q(0);
P(1) <= Q(1);
P(2) <= Q(2);
P(3) <= Q(3);
P(4) <= Q(4);
P(5) <= Q(5);
P(6) <= Q(6);
P(7) <= Q(7);
P(8) <= Q(8);
P(9) <= Q(9);
P(10) <= Q(10);
P(11) <= Q(11);
P(12) <= Q(12);
P(13) <= Q(13);
P(14) <= Q(14);
P(15) <= Q(15);
P(16) <= Q(16);
P(17) <= Q(17);
P(18) <= Q(18);
P(19) <= Q(19);
P(20) <= Q(20);
P(21) <= Q(21);
P(22) <= Q(22);
P(23) <= Q(23);
P(24) <= Q(24);
P(25) <= Q(25);
P(26) <= Q(26);
P(27) <= Q(27);
P(28) <= Q(28);
P(29) <= Q(29);
P(30) <= Q(30);
P(31) <= Q(31);
P(32) <= Q(32);
P(33) <= Q(33);
P(34) <= Q(34);
P(35) <= Q(35);
P(36) <= Q(36);
P(37) <= Q(37);
P(38) <= Q(38);
P(39) <= Q(39);
P(40) <= Q(40);
P(41) <= Q(41);
end A;
------------------------------------------------------------
-- START: Entities within the Wallace-tree
------------------------------------------------------------
--
-- Modified Booth algorithm architecture
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity BOOTHCODER_34_18 is
port
(
OPA: in std_logic_vector(0 to 33);
OPB: in std_logic_vector(0 to 17);
SUMMAND: out std_logic_vector(0 to 332)
);
end BOOTHCODER_34_18;
architecture BOOTHCODER of BOOTHCODER_34_18 is
-- Internal signal in Booth structure
signal INV_MULTIPLICAND: std_logic_vector(0 to 33);
signal INT_MULTIPLIER: std_logic_vector(0 to 35);
signal LOGIC_ONE, LOGIC_ZERO: std_logic;
begin
LOGIC_ONE <= '1';
LOGIC_ZERO <= '0';
-- Begin decoder block 1
DEC_0:DECODER -- Decoder of multiplier operand
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3)
);
-- End decoder block 1
-- Begin partial product 1
INV_MULTIPLICAND(0) <= NOT OPA(0);
PPL_0:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(0)
);
RGATE_0:R_GATE
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
PPBIT => SUMMAND(1)
);
INV_MULTIPLICAND(1) <= NOT OPA(1);
PPM_0:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(2)
);
INV_MULTIPLICAND(2) <= NOT OPA(2);
PPM_1:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(3)
);
INV_MULTIPLICAND(3) <= NOT OPA(3);
PPM_2:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(6)
);
INV_MULTIPLICAND(4) <= NOT OPA(4);
PPM_3:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(8)
);
INV_MULTIPLICAND(5) <= NOT OPA(5);
PPM_4:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(12)
);
INV_MULTIPLICAND(6) <= NOT OPA(6);
PPM_5:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(15)
);
INV_MULTIPLICAND(7) <= NOT OPA(7);
PPM_6:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(20)
);
INV_MULTIPLICAND(8) <= NOT OPA(8);
PPM_7:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(24)
);
INV_MULTIPLICAND(9) <= NOT OPA(9);
PPM_8:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(30)
);
INV_MULTIPLICAND(10) <= NOT OPA(10);
PPM_9:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(35)
);
INV_MULTIPLICAND(11) <= NOT OPA(11);
PPM_10:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(42)
);
INV_MULTIPLICAND(12) <= NOT OPA(12);
PPM_11:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(48)
);
INV_MULTIPLICAND(13) <= NOT OPA(13);
PPM_12:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(56)
);
INV_MULTIPLICAND(14) <= NOT OPA(14);
PPM_13:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(63)
);
INV_MULTIPLICAND(15) <= NOT OPA(15);
PPM_14:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(72)
);
INV_MULTIPLICAND(16) <= NOT OPA(16);
PPM_15:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(80)
);
INV_MULTIPLICAND(17) <= NOT OPA(17);
PPM_16:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(90)
);
INV_MULTIPLICAND(18) <= NOT OPA(18);
PPM_17:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(99)
);
INV_MULTIPLICAND(19) <= NOT OPA(19);
PPM_18:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(108)
);
INV_MULTIPLICAND(20) <= NOT OPA(20);
PPM_19:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(117)
);
INV_MULTIPLICAND(21) <= NOT OPA(21);
PPM_20:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(126)
);
INV_MULTIPLICAND(22) <= NOT OPA(22);
PPM_21:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(135)
);
INV_MULTIPLICAND(23) <= NOT OPA(23);
PPM_22:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(144)
);
INV_MULTIPLICAND(24) <= NOT OPA(24);
PPM_23:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(153)
);
INV_MULTIPLICAND(25) <= NOT OPA(25);
PPM_24:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(162)
);
INV_MULTIPLICAND(26) <= NOT OPA(26);
PPM_25:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(171)
);
INV_MULTIPLICAND(27) <= NOT OPA(27);
PPM_26:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(180)
);
INV_MULTIPLICAND(28) <= NOT OPA(28);
PPM_27:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(189)
);
INV_MULTIPLICAND(29) <= NOT OPA(29);
PPM_28:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(198)
);
INV_MULTIPLICAND(30) <= NOT OPA(30);
PPM_29:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(207)
);
INV_MULTIPLICAND(31) <= NOT OPA(31);
PPM_30:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(216)
);
INV_MULTIPLICAND(32) <= NOT OPA(32);
PPM_31:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(225)
);
INV_MULTIPLICAND(33) <= NOT OPA(33);
PPM_32:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(234)
);
PPH_0:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(243)
);
SUMMAND(244) <= '1';
-- Begin partial product 1
-- Begin decoder block 2
DEC_1:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7)
);
-- End decoder block 2
-- Begin partial product 2
PPL_1:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(4)
);
RGATE_1:R_GATE
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
PPBIT => SUMMAND(5)
);
PPM_33:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(7)
);
PPM_34:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(9)
);
PPM_35:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(13)
);
PPM_36:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(16)
);
PPM_37:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(21)
);
PPM_38:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(25)
);
PPM_39:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(31)
);
PPM_40:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(36)
);
PPM_41:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(43)
);
PPM_42:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(49)
);
PPM_43:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(57)
);
PPM_44:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(64)
);
PPM_45:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(73)
);
PPM_46:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(81)
);
PPM_47:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(91)
);
PPM_48:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(100)
);
PPM_49:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(109)
);
PPM_50:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(118)
);
PPM_51:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(127)
);
PPM_52:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(136)
);
PPM_53:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(145)
);
PPM_54:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(154)
);
PPM_55:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(163)
);
PPM_56:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(172)
);
PPM_57:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(181)
);
PPM_58:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(190)
);
PPM_59:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(199)
);
PPM_60:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(208)
);
PPM_61:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(217)
);
PPM_62:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(226)
);
PPM_63:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(235)
);
PPM_64:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(245)
);
PPM_65:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(253)
);
SUMMAND(254) <= LOGIC_ONE;
PPH_1:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(262)
);
-- Begin partial product 2
-- Begin decoder block 3
DEC_2:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11)
);
-- End decoder block 3
-- Begin partial product 3
PPL_2:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(10)
);
RGATE_2:R_GATE
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
PPBIT => SUMMAND(11)
);
PPM_66:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(14)
);
PPM_67:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(17)
);
PPM_68:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(22)
);
PPM_69:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(26)
);
PPM_70:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(32)
);
PPM_71:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(37)
);
PPM_72:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(44)
);
PPM_73:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(50)
);
PPM_74:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(58)
);
PPM_75:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(65)
);
PPM_76:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(74)
);
PPM_77:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(82)
);
PPM_78:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(92)
);
PPM_79:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(101)
);
PPM_80:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(110)
);
PPM_81:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(119)
);
PPM_82:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(128)
);
PPM_83:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(137)
);
PPM_84:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(146)
);
PPM_85:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(155)
);
PPM_86:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(164)
);
PPM_87:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(173)
);
PPM_88:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(182)
);
PPM_89:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(191)
);
PPM_90:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(200)
);
PPM_91:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(209)
);
PPM_92:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(218)
);
PPM_93:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(227)
);
PPM_94:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(236)
);
PPM_95:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(246)
);
PPM_96:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(255)
);
PPM_97:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(263)
);
PPM_98:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(270)
);
SUMMAND(271) <= LOGIC_ONE;
PPH_2:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(278)
);
-- Begin partial product 3
-- Begin decoder block 4
DEC_3:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15)
);
-- End decoder block 4
-- Begin partial product 4
PPL_3:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(18)
);
RGATE_3:R_GATE
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
PPBIT => SUMMAND(19)
);
PPM_99:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(23)
);
PPM_100:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(27)
);
PPM_101:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(33)
);
PPM_102:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(38)
);
PPM_103:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(45)
);
PPM_104:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(51)
);
PPM_105:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(59)
);
PPM_106:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(66)
);
PPM_107:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(75)
);
PPM_108:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(83)
);
PPM_109:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(93)
);
PPM_110:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(102)
);
PPM_111:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(111)
);
PPM_112:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(120)
);
PPM_113:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(129)
);
PPM_114:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(138)
);
PPM_115:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(147)
);
PPM_116:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(156)
);
PPM_117:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(165)
);
PPM_118:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(174)
);
PPM_119:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(183)
);
PPM_120:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(192)
);
PPM_121:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(201)
);
PPM_122:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(210)
);
PPM_123:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(219)
);
PPM_124:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(228)
);
PPM_125:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(237)
);
PPM_126:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(247)
);
PPM_127:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(256)
);
PPM_128:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(264)
);
PPM_129:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(272)
);
PPM_130:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(279)
);
PPM_131:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(285)
);
SUMMAND(286) <= LOGIC_ONE;
PPH_3:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(292)
);
-- Begin partial product 4
-- Begin decoder block 5
DEC_4:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19)
);
-- End decoder block 5
-- Begin partial product 5
PPL_4:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(28)
);
RGATE_4:R_GATE
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
PPBIT => SUMMAND(29)
);
PPM_132:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(34)
);
PPM_133:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(39)
);
PPM_134:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(46)
);
PPM_135:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(52)
);
PPM_136:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(60)
);
PPM_137:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(67)
);
PPM_138:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(76)
);
PPM_139:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(84)
);
PPM_140:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(94)
);
PPM_141:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(103)
);
PPM_142:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(112)
);
PPM_143:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(121)
);
PPM_144:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(130)
);
PPM_145:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(139)
);
PPM_146:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(148)
);
PPM_147:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(157)
);
PPM_148:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(166)
);
PPM_149:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(175)
);
PPM_150:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(184)
);
PPM_151:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(193)
);
PPM_152:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(202)
);
PPM_153:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(211)
);
PPM_154:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(220)
);
PPM_155:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(229)
);
PPM_156:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(238)
);
PPM_157:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(248)
);
PPM_158:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(257)
);
PPM_159:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(265)
);
PPM_160:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(273)
);
PPM_161:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(280)
);
PPM_162:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(287)
);
PPM_163:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(293)
);
PPM_164:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(298)
);
SUMMAND(299) <= LOGIC_ONE;
PPH_4:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(304)
);
-- Begin partial product 5
-- Begin decoder block 6
DEC_5:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(9),INB => OPB(10),INC => OPB(11),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23)
);
-- End decoder block 6
-- Begin partial product 6
PPL_5:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(40)
);
RGATE_5:R_GATE
port map
(
INA => OPB(9),INB => OPB(10),INC => OPB(11),
PPBIT => SUMMAND(41)
);
PPM_165:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(47)
);
PPM_166:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(53)
);
PPM_167:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(61)
);
PPM_168:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(68)
);
PPM_169:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(77)
);
PPM_170:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(85)
);
PPM_171:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(95)
);
PPM_172:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(104)
);
PPM_173:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(113)
);
PPM_174:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(122)
);
PPM_175:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(131)
);
PPM_176:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(140)
);
PPM_177:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(149)
);
PPM_178:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(158)
);
PPM_179:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(167)
);
PPM_180:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(176)
);
PPM_181:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(185)
);
PPM_182:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(194)
);
PPM_183:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(203)
);
PPM_184:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(212)
);
PPM_185:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(221)
);
PPM_186:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(230)
);
PPM_187:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(239)
);
PPM_188:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(249)
);
PPM_189:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(258)
);
PPM_190:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(266)
);
PPM_191:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(274)
);
PPM_192:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(281)
);
PPM_193:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(288)
);
PPM_194:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(294)
);
PPM_195:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(300)
);
PPM_196:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(305)
);
PPM_197:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(309)
);
SUMMAND(310) <= LOGIC_ONE;
PPH_5:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(314)
);
-- Begin partial product 6
-- Begin decoder block 7
DEC_6:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(11),INB => OPB(12),INC => OPB(13),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27)
);
-- End decoder block 7
-- Begin partial product 7
PPL_6:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(54)
);
RGATE_6:R_GATE
port map
(
INA => OPB(11),INB => OPB(12),INC => OPB(13),
PPBIT => SUMMAND(55)
);
PPM_198:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(62)
);
PPM_199:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(69)
);
PPM_200:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(78)
);
PPM_201:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(86)
);
PPM_202:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(96)
);
PPM_203:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(105)
);
PPM_204:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(114)
);
PPM_205:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(123)
);
PPM_206:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(132)
);
PPM_207:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(141)
);
PPM_208:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(150)
);
PPM_209:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(159)
);
PPM_210:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(168)
);
PPM_211:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(177)
);
PPM_212:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(186)
);
PPM_213:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(195)
);
PPM_214:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(204)
);
PPM_215:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(213)
);
PPM_216:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(222)
);
PPM_217:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(231)
);
PPM_218:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(240)
);
PPM_219:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(250)
);
PPM_220:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(259)
);
PPM_221:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(267)
);
PPM_222:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(275)
);
PPM_223:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(282)
);
PPM_224:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(289)
);
PPM_225:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(295)
);
PPM_226:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(301)
);
PPM_227:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(306)
);
PPM_228:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(311)
);
PPM_229:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(315)
);
PPM_230:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(318)
);
SUMMAND(319) <= LOGIC_ONE;
PPH_6:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(322)
);
-- Begin partial product 7
-- Begin decoder block 8
DEC_7:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(13),INB => OPB(14),INC => OPB(15),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31)
);
-- End decoder block 8
-- Begin partial product 8
PPL_7:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(70)
);
RGATE_7:R_GATE
port map
(
INA => OPB(13),INB => OPB(14),INC => OPB(15),
PPBIT => SUMMAND(71)
);
PPM_231:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(79)
);
PPM_232:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(87)
);
PPM_233:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(97)
);
PPM_234:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(106)
);
PPM_235:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(115)
);
PPM_236:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(124)
);
PPM_237:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(133)
);
PPM_238:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(142)
);
PPM_239:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(151)
);
PPM_240:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(160)
);
PPM_241:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(169)
);
PPM_242:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(178)
);
PPM_243:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(187)
);
PPM_244:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(196)
);
PPM_245:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(205)
);
PPM_246:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(214)
);
PPM_247:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(223)
);
PPM_248:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(232)
);
PPM_249:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(241)
);
PPM_250:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(251)
);
PPM_251:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(260)
);
PPM_252:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(268)
);
PPM_253:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(276)
);
PPM_254:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(283)
);
PPM_255:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(290)
);
PPM_256:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(296)
);
PPM_257:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(302)
);
PPM_258:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(307)
);
PPM_259:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(312)
);
PPM_260:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(316)
);
PPM_261:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(320)
);
PPM_262:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(323)
);
PPM_263:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(325)
);
SUMMAND(326) <= LOGIC_ONE;
PPH_7:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(328)
);
-- Begin partial product 8
-- Begin decoder block 9
DEC_8:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(15),INB => OPB(16),INC => OPB(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35)
);
-- End decoder block 9
-- Begin partial product 9
PPL_8:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(88)
);
RGATE_8:R_GATE
port map
(
INA => OPB(15),INB => OPB(16),INC => OPB(17),
PPBIT => SUMMAND(89)
);
PPM_264:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(98)
);
PPM_265:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(107)
);
PPM_266:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(116)
);
PPM_267:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(125)
);
PPM_268:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(134)
);
PPM_269:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(143)
);
PPM_270:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(152)
);
PPM_271:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(161)
);
PPM_272:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(170)
);
PPM_273:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(179)
);
PPM_274:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(188)
);
PPM_275:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(197)
);
PPM_276:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(206)
);
PPM_277:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(215)
);
PPM_278:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(224)
);
PPM_279:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(233)
);
PPM_280:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(242)
);
PPM_281:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(252)
);
PPM_282:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(261)
);
PPM_283:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(269)
);
PPM_284:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(277)
);
PPM_285:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(284)
);
PPM_286:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(291)
);
PPM_287:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(297)
);
PPM_288:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(303)
);
PPM_289:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(308)
);
PPM_290:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(313)
);
PPM_291:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(317)
);
PPM_292:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(321)
);
PPM_293:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(324)
);
PPM_294:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(327)
);
PPM_295:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(329)
);
PPM_296:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(330)
);
SUMMAND(331) <= LOGIC_ONE;
PPH_8:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(332)
);
-- Begin partial product 9
end BOOTHCODER;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity WALLACE_34_18 is
port
(
SUMMAND: in std_logic_vector(0 to 332);
CARRY: out std_logic_vector(0 to 49);
SUM: out std_logic_vector(0 to 50)
);
end WALLACE_34_18;
architecture WALLACE of WALLACE_34_18 is
-- Signals used inside the wallace trees
signal INT_CARRY: std_logic_vector(0 to 226);
signal INT_SUM: std_logic_vector(0 to 286);
begin -- netlist
-- Begin WT-branch 1
---- Begin HA stage
HA_0:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(0), DATA_B => SUMMAND(1),
SAVE => SUM(0), CARRY => CARRY(0)
);
---- End HA stage
-- End WT-branch 1
-- Begin WT-branch 2
---- Begin NO stage
SUM(1) <= SUMMAND(2); -- At Level 1
CARRY(1) <= '0';
---- End NO stage
-- End WT-branch 2
-- Begin WT-branch 3
---- Begin FA stage
FA_0:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5),
SAVE => SUM(2), CARRY => CARRY(2)
);
---- End FA stage
-- End WT-branch 3
-- Begin WT-branch 4
---- Begin HA stage
HA_1:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(6), DATA_B => SUMMAND(7),
SAVE => SUM(3), CARRY => CARRY(3)
);
---- End HA stage
-- End WT-branch 4
-- Begin WT-branch 5
---- Begin FA stage
FA_1:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10),
SAVE => INT_SUM(0), CARRY => INT_CARRY(0)
);
---- End FA stage
---- Begin NO stage
INT_SUM(1) <= SUMMAND(11); -- At Level 1
---- End NO stage
---- Begin HA stage
HA_2:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(0), DATA_B => INT_SUM(1),
SAVE => SUM(4), CARRY => CARRY(4)
);
---- End HA stage
-- End WT-branch 5
-- Begin WT-branch 6
---- Begin FA stage
FA_2:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14),
SAVE => INT_SUM(2), CARRY => INT_CARRY(1)
);
---- End FA stage
---- Begin HA stage
HA_3:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0),
SAVE => SUM(5), CARRY => CARRY(5)
);
---- End HA stage
-- End WT-branch 6
-- Begin WT-branch 7
---- Begin FA stage
FA_3:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17),
SAVE => INT_SUM(3), CARRY => INT_CARRY(2)
);
---- End FA stage
---- Begin HA stage
HA_4:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(18), DATA_B => SUMMAND(19),
SAVE => INT_SUM(4), CARRY => INT_CARRY(3)
);
---- End HA stage
---- Begin FA stage
FA_4:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1),
SAVE => SUM(6), CARRY => CARRY(6)
);
---- End FA stage
-- End WT-branch 7
-- Begin WT-branch 8
---- Begin FA stage
FA_5:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22),
SAVE => INT_SUM(5), CARRY => INT_CARRY(4)
);
---- End FA stage
---- Begin NO stage
INT_SUM(6) <= SUMMAND(23); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_6:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2),
SAVE => INT_SUM(7), CARRY => INT_CARRY(5)
);
---- End FA stage
---- Begin NO stage
INT_SUM(8) <= INT_CARRY(3); -- At Level 2
---- End NO stage
---- Begin HA stage
HA_5:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(7), DATA_B => INT_SUM(8),
SAVE => SUM(7), CARRY => CARRY(7)
);
---- End HA stage
-- End WT-branch 8
-- Begin WT-branch 9
---- Begin FA stage
FA_7:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26),
SAVE => INT_SUM(9), CARRY => INT_CARRY(6)
);
---- End FA stage
---- Begin FA stage
FA_8:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29),
SAVE => INT_SUM(10), CARRY => INT_CARRY(7)
);
---- End FA stage
---- Begin FA stage
FA_9:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4),
SAVE => INT_SUM(11), CARRY => INT_CARRY(8)
);
---- End FA stage
---- Begin HA stage
HA_6:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5),
SAVE => SUM(8), CARRY => CARRY(8)
);
---- End HA stage
-- End WT-branch 9
-- Begin WT-branch 10
---- Begin FA stage
FA_10:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32),
SAVE => INT_SUM(12), CARRY => INT_CARRY(9)
);
---- End FA stage
---- Begin HA stage
HA_7:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(33), DATA_B => SUMMAND(34),
SAVE => INT_SUM(13), CARRY => INT_CARRY(10)
);
---- End HA stage
---- Begin FA stage
FA_11:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6),
SAVE => INT_SUM(14), CARRY => INT_CARRY(11)
);
---- End FA stage
---- Begin NO stage
INT_SUM(15) <= INT_CARRY(7); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_12:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8),
SAVE => SUM(9), CARRY => CARRY(9)
);
---- End FA stage
-- End WT-branch 10
-- Begin WT-branch 11
---- Begin FA stage
FA_13:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37),
SAVE => INT_SUM(16), CARRY => INT_CARRY(12)
);
---- End FA stage
---- Begin FA stage
FA_14:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40),
SAVE => INT_SUM(17), CARRY => INT_CARRY(13)
);
---- End FA stage
---- Begin NO stage
INT_SUM(18) <= SUMMAND(41); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_15:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18),
SAVE => INT_SUM(19), CARRY => INT_CARRY(14)
);
---- End FA stage
---- Begin HA stage
HA_8:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10),
SAVE => INT_SUM(20), CARRY => INT_CARRY(15)
);
---- End HA stage
---- Begin FA stage
FA_16:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11),
SAVE => SUM(10), CARRY => CARRY(10)
);
---- End FA stage
-- End WT-branch 11
-- Begin WT-branch 12
---- Begin FA stage
FA_17:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44),
SAVE => INT_SUM(21), CARRY => INT_CARRY(16)
);
---- End FA stage
---- Begin FA stage
FA_18:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47),
SAVE => INT_SUM(22), CARRY => INT_CARRY(17)
);
---- End FA stage
---- Begin FA stage
FA_19:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12),
SAVE => INT_SUM(23), CARRY => INT_CARRY(18)
);
---- End FA stage
---- Begin NO stage
INT_SUM(24) <= INT_CARRY(13); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_20:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14),
SAVE => INT_SUM(25), CARRY => INT_CARRY(19)
);
---- End FA stage
---- Begin NO stage
INT_SUM(26) <= INT_CARRY(15); -- At Level 3
---- End NO stage
---- Begin HA stage
HA_9:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(25), DATA_B => INT_SUM(26),
SAVE => SUM(11), CARRY => CARRY(11)
);
---- End HA stage
-- End WT-branch 12
-- Begin WT-branch 13
---- Begin FA stage
FA_21:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50),
SAVE => INT_SUM(27), CARRY => INT_CARRY(20)
);
---- End FA stage
---- Begin FA stage
FA_22:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53),
SAVE => INT_SUM(28), CARRY => INT_CARRY(21)
);
---- End FA stage
---- Begin NO stage
INT_SUM(29) <= SUMMAND(54); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(30) <= SUMMAND(55); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_23:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29),
SAVE => INT_SUM(31), CARRY => INT_CARRY(22)
);
---- End FA stage
---- Begin FA stage
FA_24:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17),
SAVE => INT_SUM(32), CARRY => INT_CARRY(23)
);
---- End FA stage
---- Begin FA stage
FA_25:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18),
SAVE => INT_SUM(33), CARRY => INT_CARRY(24)
);
---- End FA stage
---- Begin HA stage
HA_10:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19),
SAVE => SUM(12), CARRY => CARRY(12)
);
---- End HA stage
-- End WT-branch 13
-- Begin WT-branch 14
---- Begin FA stage
FA_26:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58),
SAVE => INT_SUM(34), CARRY => INT_CARRY(25)
);
---- End FA stage
---- Begin FA stage
FA_27:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61),
SAVE => INT_SUM(35), CARRY => INT_CARRY(26)
);
---- End FA stage
---- Begin NO stage
INT_SUM(36) <= SUMMAND(62); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_28:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36),
SAVE => INT_SUM(37), CARRY => INT_CARRY(27)
);
---- End FA stage
---- Begin HA stage
HA_11:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21),
SAVE => INT_SUM(38), CARRY => INT_CARRY(28)
);
---- End HA stage
---- Begin FA stage
FA_29:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22),
SAVE => INT_SUM(39), CARRY => INT_CARRY(29)
);
---- End FA stage
---- Begin NO stage
INT_SUM(40) <= INT_CARRY(23); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_30:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24),
SAVE => SUM(13), CARRY => CARRY(13)
);
---- End FA stage
-- End WT-branch 14
-- Begin WT-branch 15
---- Begin FA stage
FA_31:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65),
SAVE => INT_SUM(41), CARRY => INT_CARRY(30)
);
---- End FA stage
---- Begin FA stage
FA_32:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68),
SAVE => INT_SUM(42), CARRY => INT_CARRY(31)
);
---- End FA stage
---- Begin FA stage
FA_33:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71),
SAVE => INT_SUM(43), CARRY => INT_CARRY(32)
);
---- End FA stage
---- Begin FA stage
FA_34:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43),
SAVE => INT_SUM(44), CARRY => INT_CARRY(33)
);
---- End FA stage
---- Begin HA stage
HA_12:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26),
SAVE => INT_SUM(45), CARRY => INT_CARRY(34)
);
---- End HA stage
---- Begin FA stage
FA_35:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27),
SAVE => INT_SUM(46), CARRY => INT_CARRY(35)
);
---- End FA stage
---- Begin NO stage
INT_SUM(47) <= INT_CARRY(28); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_36:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29),
SAVE => SUM(14), CARRY => CARRY(14)
);
---- End FA stage
-- End WT-branch 15
-- Begin WT-branch 16
---- Begin FA stage
FA_37:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74),
SAVE => INT_SUM(48), CARRY => INT_CARRY(36)
);
---- End FA stage
---- Begin FA stage
FA_38:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77),
SAVE => INT_SUM(49), CARRY => INT_CARRY(37)
);
---- End FA stage
---- Begin HA stage
HA_13:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(78), DATA_B => SUMMAND(79),
SAVE => INT_SUM(50), CARRY => INT_CARRY(38)
);
---- End HA stage
---- Begin FA stage
FA_39:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50),
SAVE => INT_SUM(51), CARRY => INT_CARRY(39)
);
---- End FA stage
---- Begin FA stage
FA_40:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32),
SAVE => INT_SUM(52), CARRY => INT_CARRY(40)
);
---- End FA stage
---- Begin FA stage
FA_41:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33),
SAVE => INT_SUM(53), CARRY => INT_CARRY(41)
);
---- End FA stage
---- Begin NO stage
INT_SUM(54) <= INT_CARRY(34); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_42:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35),
SAVE => SUM(15), CARRY => CARRY(15)
);
---- End FA stage
-- End WT-branch 16
-- Begin WT-branch 17
---- Begin FA stage
FA_43:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82),
SAVE => INT_SUM(55), CARRY => INT_CARRY(42)
);
---- End FA stage
---- Begin FA stage
FA_44:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85),
SAVE => INT_SUM(56), CARRY => INT_CARRY(43)
);
---- End FA stage
---- Begin FA stage
FA_45:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88),
SAVE => INT_SUM(57), CARRY => INT_CARRY(44)
);
---- End FA stage
---- Begin NO stage
INT_SUM(58) <= SUMMAND(89); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_46:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57),
SAVE => INT_SUM(59), CARRY => INT_CARRY(45)
);
---- End FA stage
---- Begin FA stage
FA_47:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37),
SAVE => INT_SUM(60), CARRY => INT_CARRY(46)
);
---- End FA stage
---- Begin NO stage
INT_SUM(61) <= INT_CARRY(38); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_48:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61),
SAVE => INT_SUM(62), CARRY => INT_CARRY(47)
);
---- End FA stage
---- Begin HA stage
HA_14:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40),
SAVE => INT_SUM(63), CARRY => INT_CARRY(48)
);
---- End HA stage
---- Begin FA stage
FA_49:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41),
SAVE => SUM(16), CARRY => CARRY(16)
);
---- End FA stage
-- End WT-branch 17
-- Begin WT-branch 18
---- Begin FA stage
FA_50:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92),
SAVE => INT_SUM(64), CARRY => INT_CARRY(49)
);
---- End FA stage
---- Begin FA stage
FA_51:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95),
SAVE => INT_SUM(65), CARRY => INT_CARRY(50)
);
---- End FA stage
---- Begin FA stage
FA_52:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98),
SAVE => INT_SUM(66), CARRY => INT_CARRY(51)
);
---- End FA stage
---- Begin FA stage
FA_53:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66),
SAVE => INT_SUM(67), CARRY => INT_CARRY(52)
);
---- End FA stage
---- Begin FA stage
FA_54:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44),
SAVE => INT_SUM(68), CARRY => INT_CARRY(53)
);
---- End FA stage
---- Begin FA stage
FA_55:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45),
SAVE => INT_SUM(69), CARRY => INT_CARRY(54)
);
---- End FA stage
---- Begin NO stage
INT_SUM(70) <= INT_CARRY(46); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_56:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47),
SAVE => INT_SUM(71), CARRY => INT_CARRY(55)
);
---- End FA stage
---- Begin NO stage
INT_SUM(72) <= INT_CARRY(48); -- At Level 4
---- End NO stage
---- Begin HA stage
HA_15:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(71), DATA_B => INT_SUM(72),
SAVE => SUM(17), CARRY => CARRY(17)
);
---- End HA stage
-- End WT-branch 18
-- Begin WT-branch 19
---- Begin FA stage
FA_57:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101),
SAVE => INT_SUM(73), CARRY => INT_CARRY(56)
);
---- End FA stage
---- Begin FA stage
FA_58:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104),
SAVE => INT_SUM(74), CARRY => INT_CARRY(57)
);
---- End FA stage
---- Begin FA stage
FA_59:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107),
SAVE => INT_SUM(75), CARRY => INT_CARRY(58)
);
---- End FA stage
---- Begin FA stage
FA_60:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75),
SAVE => INT_SUM(76), CARRY => INT_CARRY(59)
);
---- End FA stage
---- Begin FA stage
FA_61:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(49), DATA_B => INT_CARRY(50), DATA_C => INT_CARRY(51),
SAVE => INT_SUM(77), CARRY => INT_CARRY(60)
);
---- End FA stage
---- Begin FA stage
FA_62:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(52),
SAVE => INT_SUM(78), CARRY => INT_CARRY(61)
);
---- End FA stage
---- Begin NO stage
INT_SUM(79) <= INT_CARRY(53); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_63:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_CARRY(54),
SAVE => INT_SUM(80), CARRY => INT_CARRY(62)
);
---- End FA stage
---- Begin HA stage
HA_16:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(80), DATA_B => INT_CARRY(55),
SAVE => SUM(18), CARRY => CARRY(18)
);
---- End HA stage
-- End WT-branch 19
-- Begin WT-branch 20
---- Begin FA stage
FA_64:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(108), DATA_B => SUMMAND(109), DATA_C => SUMMAND(110),
SAVE => INT_SUM(81), CARRY => INT_CARRY(63)
);
---- End FA stage
---- Begin FA stage
FA_65:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(111), DATA_B => SUMMAND(112), DATA_C => SUMMAND(113),
SAVE => INT_SUM(82), CARRY => INT_CARRY(64)
);
---- End FA stage
---- Begin FA stage
FA_66:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(114), DATA_B => SUMMAND(115), DATA_C => SUMMAND(116),
SAVE => INT_SUM(83), CARRY => INT_CARRY(65)
);
---- End FA stage
---- Begin FA stage
FA_67:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(81), DATA_B => INT_SUM(82), DATA_C => INT_SUM(83),
SAVE => INT_SUM(84), CARRY => INT_CARRY(66)
);
---- End FA stage
---- Begin FA stage
FA_68:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(56), DATA_B => INT_CARRY(57), DATA_C => INT_CARRY(58),
SAVE => INT_SUM(85), CARRY => INT_CARRY(67)
);
---- End FA stage
---- Begin FA stage
FA_69:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(84), DATA_B => INT_SUM(85), DATA_C => INT_CARRY(59),
SAVE => INT_SUM(86), CARRY => INT_CARRY(68)
);
---- End FA stage
---- Begin NO stage
INT_SUM(87) <= INT_CARRY(60); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_70:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(86), DATA_B => INT_SUM(87), DATA_C => INT_CARRY(61),
SAVE => INT_SUM(88), CARRY => INT_CARRY(69)
);
---- End FA stage
---- Begin HA stage
HA_17:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(88), DATA_B => INT_CARRY(62),
SAVE => SUM(19), CARRY => CARRY(19)
);
---- End HA stage
-- End WT-branch 20
-- Begin WT-branch 21
---- Begin FA stage
FA_71:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(117), DATA_B => SUMMAND(118), DATA_C => SUMMAND(119),
SAVE => INT_SUM(89), CARRY => INT_CARRY(70)
);
---- End FA stage
---- Begin FA stage
FA_72:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122),
SAVE => INT_SUM(90), CARRY => INT_CARRY(71)
);
---- End FA stage
---- Begin FA stage
FA_73:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), DATA_C => SUMMAND(125),
SAVE => INT_SUM(91), CARRY => INT_CARRY(72)
);
---- End FA stage
---- Begin FA stage
FA_74:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_SUM(91),
SAVE => INT_SUM(92), CARRY => INT_CARRY(73)
);
---- End FA stage
---- Begin FA stage
FA_75:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(63), DATA_B => INT_CARRY(64), DATA_C => INT_CARRY(65),
SAVE => INT_SUM(93), CARRY => INT_CARRY(74)
);
---- End FA stage
---- Begin FA stage
FA_76:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(66),
SAVE => INT_SUM(94), CARRY => INT_CARRY(75)
);
---- End FA stage
---- Begin NO stage
INT_SUM(95) <= INT_CARRY(67); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_77:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(68),
SAVE => INT_SUM(96), CARRY => INT_CARRY(76)
);
---- End FA stage
---- Begin HA stage
HA_18:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(96), DATA_B => INT_CARRY(69),
SAVE => SUM(20), CARRY => CARRY(20)
);
---- End HA stage
-- End WT-branch 21
-- Begin WT-branch 22
---- Begin FA stage
FA_78:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128),
SAVE => INT_SUM(97), CARRY => INT_CARRY(77)
);
---- End FA stage
---- Begin FA stage
FA_79:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131),
SAVE => INT_SUM(98), CARRY => INT_CARRY(78)
);
---- End FA stage
---- Begin FA stage
FA_80:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => SUMMAND(134),
SAVE => INT_SUM(99), CARRY => INT_CARRY(79)
);
---- End FA stage
---- Begin FA stage
FA_81:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(97), DATA_B => INT_SUM(98), DATA_C => INT_SUM(99),
SAVE => INT_SUM(100), CARRY => INT_CARRY(80)
);
---- End FA stage
---- Begin FA stage
FA_82:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(70), DATA_B => INT_CARRY(71), DATA_C => INT_CARRY(72),
SAVE => INT_SUM(101), CARRY => INT_CARRY(81)
);
---- End FA stage
---- Begin FA stage
FA_83:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_CARRY(73),
SAVE => INT_SUM(102), CARRY => INT_CARRY(82)
);
---- End FA stage
---- Begin NO stage
INT_SUM(103) <= INT_CARRY(74); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_84:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(102), DATA_B => INT_SUM(103), DATA_C => INT_CARRY(75),
SAVE => INT_SUM(104), CARRY => INT_CARRY(83)
);
---- End FA stage
---- Begin HA stage
HA_19:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(104), DATA_B => INT_CARRY(76),
SAVE => SUM(21), CARRY => CARRY(21)
);
---- End HA stage
-- End WT-branch 22
-- Begin WT-branch 23
---- Begin FA stage
FA_85:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137),
SAVE => INT_SUM(105), CARRY => INT_CARRY(84)
);
---- End FA stage
---- Begin FA stage
FA_86:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), DATA_C => SUMMAND(140),
SAVE => INT_SUM(106), CARRY => INT_CARRY(85)
);
---- End FA stage
---- Begin FA stage
FA_87:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(141), DATA_B => SUMMAND(142), DATA_C => SUMMAND(143),
SAVE => INT_SUM(107), CARRY => INT_CARRY(86)
);
---- End FA stage
---- Begin FA stage
FA_88:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(105), DATA_B => INT_SUM(106), DATA_C => INT_SUM(107),
SAVE => INT_SUM(108), CARRY => INT_CARRY(87)
);
---- End FA stage
---- Begin FA stage
FA_89:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(77), DATA_B => INT_CARRY(78), DATA_C => INT_CARRY(79),
SAVE => INT_SUM(109), CARRY => INT_CARRY(88)
);
---- End FA stage
---- Begin FA stage
FA_90:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(108), DATA_B => INT_SUM(109), DATA_C => INT_CARRY(80),
SAVE => INT_SUM(110), CARRY => INT_CARRY(89)
);
---- End FA stage
---- Begin NO stage
INT_SUM(111) <= INT_CARRY(81); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_91:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(82),
SAVE => INT_SUM(112), CARRY => INT_CARRY(90)
);
---- End FA stage
---- Begin HA stage
HA_20:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(112), DATA_B => INT_CARRY(83),
SAVE => SUM(22), CARRY => CARRY(22)
);
---- End HA stage
-- End WT-branch 23
-- Begin WT-branch 24
---- Begin FA stage
FA_92:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(144), DATA_B => SUMMAND(145), DATA_C => SUMMAND(146),
SAVE => INT_SUM(113), CARRY => INT_CARRY(91)
);
---- End FA stage
---- Begin FA stage
FA_93:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(147), DATA_B => SUMMAND(148), DATA_C => SUMMAND(149),
SAVE => INT_SUM(114), CARRY => INT_CARRY(92)
);
---- End FA stage
---- Begin FA stage
FA_94:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(150), DATA_B => SUMMAND(151), DATA_C => SUMMAND(152),
SAVE => INT_SUM(115), CARRY => INT_CARRY(93)
);
---- End FA stage
---- Begin FA stage
FA_95:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(113), DATA_B => INT_SUM(114), DATA_C => INT_SUM(115),
SAVE => INT_SUM(116), CARRY => INT_CARRY(94)
);
---- End FA stage
---- Begin FA stage
FA_96:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(84), DATA_B => INT_CARRY(85), DATA_C => INT_CARRY(86),
SAVE => INT_SUM(117), CARRY => INT_CARRY(95)
);
---- End FA stage
---- Begin FA stage
FA_97:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(116), DATA_B => INT_SUM(117), DATA_C => INT_CARRY(87),
SAVE => INT_SUM(118), CARRY => INT_CARRY(96)
);
---- End FA stage
---- Begin NO stage
INT_SUM(119) <= INT_CARRY(88); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_98:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(118), DATA_B => INT_SUM(119), DATA_C => INT_CARRY(89),
SAVE => INT_SUM(120), CARRY => INT_CARRY(97)
);
---- End FA stage
---- Begin HA stage
HA_21:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(120), DATA_B => INT_CARRY(90),
SAVE => SUM(23), CARRY => CARRY(23)
);
---- End HA stage
-- End WT-branch 24
-- Begin WT-branch 25
---- Begin FA stage
FA_99:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(153), DATA_B => SUMMAND(154), DATA_C => SUMMAND(155),
SAVE => INT_SUM(121), CARRY => INT_CARRY(98)
);
---- End FA stage
---- Begin FA stage
FA_100:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(156), DATA_B => SUMMAND(157), DATA_C => SUMMAND(158),
SAVE => INT_SUM(122), CARRY => INT_CARRY(99)
);
---- End FA stage
---- Begin FA stage
FA_101:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(159), DATA_B => SUMMAND(160), DATA_C => SUMMAND(161),
SAVE => INT_SUM(123), CARRY => INT_CARRY(100)
);
---- End FA stage
---- Begin FA stage
FA_102:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(121), DATA_B => INT_SUM(122), DATA_C => INT_SUM(123),
SAVE => INT_SUM(124), CARRY => INT_CARRY(101)
);
---- End FA stage
---- Begin FA stage
FA_103:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(91), DATA_B => INT_CARRY(92), DATA_C => INT_CARRY(93),
SAVE => INT_SUM(125), CARRY => INT_CARRY(102)
);
---- End FA stage
---- Begin FA stage
FA_104:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_CARRY(94),
SAVE => INT_SUM(126), CARRY => INT_CARRY(103)
);
---- End FA stage
---- Begin NO stage
INT_SUM(127) <= INT_CARRY(95); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_105:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(126), DATA_B => INT_SUM(127), DATA_C => INT_CARRY(96),
SAVE => INT_SUM(128), CARRY => INT_CARRY(104)
);
---- End FA stage
---- Begin HA stage
HA_22:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(128), DATA_B => INT_CARRY(97),
SAVE => SUM(24), CARRY => CARRY(24)
);
---- End HA stage
-- End WT-branch 25
-- Begin WT-branch 26
---- Begin FA stage
FA_106:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(162), DATA_B => SUMMAND(163), DATA_C => SUMMAND(164),
SAVE => INT_SUM(129), CARRY => INT_CARRY(105)
);
---- End FA stage
---- Begin FA stage
FA_107:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167),
SAVE => INT_SUM(130), CARRY => INT_CARRY(106)
);
---- End FA stage
---- Begin FA stage
FA_108:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), DATA_C => SUMMAND(170),
SAVE => INT_SUM(131), CARRY => INT_CARRY(107)
);
---- End FA stage
---- Begin FA stage
FA_109:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(129), DATA_B => INT_SUM(130), DATA_C => INT_SUM(131),
SAVE => INT_SUM(132), CARRY => INT_CARRY(108)
);
---- End FA stage
---- Begin FA stage
FA_110:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(98), DATA_B => INT_CARRY(99), DATA_C => INT_CARRY(100),
SAVE => INT_SUM(133), CARRY => INT_CARRY(109)
);
---- End FA stage
---- Begin FA stage
FA_111:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(132), DATA_B => INT_SUM(133), DATA_C => INT_CARRY(101),
SAVE => INT_SUM(134), CARRY => INT_CARRY(110)
);
---- End FA stage
---- Begin NO stage
INT_SUM(135) <= INT_CARRY(102); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_112:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(134), DATA_B => INT_SUM(135), DATA_C => INT_CARRY(103),
SAVE => INT_SUM(136), CARRY => INT_CARRY(111)
);
---- End FA stage
---- Begin HA stage
HA_23:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(136), DATA_B => INT_CARRY(104),
SAVE => SUM(25), CARRY => CARRY(25)
);
---- End HA stage
-- End WT-branch 26
-- Begin WT-branch 27
---- Begin FA stage
FA_113:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(171), DATA_B => SUMMAND(172), DATA_C => SUMMAND(173),
SAVE => INT_SUM(137), CARRY => INT_CARRY(112)
);
---- End FA stage
---- Begin FA stage
FA_114:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176),
SAVE => INT_SUM(138), CARRY => INT_CARRY(113)
);
---- End FA stage
---- Begin FA stage
FA_115:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179),
SAVE => INT_SUM(139), CARRY => INT_CARRY(114)
);
---- End FA stage
---- Begin FA stage
FA_116:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(137), DATA_B => INT_SUM(138), DATA_C => INT_SUM(139),
SAVE => INT_SUM(140), CARRY => INT_CARRY(115)
);
---- End FA stage
---- Begin FA stage
FA_117:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(105), DATA_B => INT_CARRY(106), DATA_C => INT_CARRY(107),
SAVE => INT_SUM(141), CARRY => INT_CARRY(116)
);
---- End FA stage
---- Begin FA stage
FA_118:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(108),
SAVE => INT_SUM(142), CARRY => INT_CARRY(117)
);
---- End FA stage
---- Begin NO stage
INT_SUM(143) <= INT_CARRY(109); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_119:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_CARRY(110),
SAVE => INT_SUM(144), CARRY => INT_CARRY(118)
);
---- End FA stage
---- Begin HA stage
HA_24:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(144), DATA_B => INT_CARRY(111),
SAVE => SUM(26), CARRY => CARRY(26)
);
---- End HA stage
-- End WT-branch 27
-- Begin WT-branch 28
---- Begin FA stage
FA_120:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(180), DATA_B => SUMMAND(181), DATA_C => SUMMAND(182),
SAVE => INT_SUM(145), CARRY => INT_CARRY(119)
);
---- End FA stage
---- Begin FA stage
FA_121:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(183), DATA_B => SUMMAND(184), DATA_C => SUMMAND(185),
SAVE => INT_SUM(146), CARRY => INT_CARRY(120)
);
---- End FA stage
---- Begin FA stage
FA_122:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(186), DATA_B => SUMMAND(187), DATA_C => SUMMAND(188),
SAVE => INT_SUM(147), CARRY => INT_CARRY(121)
);
---- End FA stage
---- Begin FA stage
FA_123:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_SUM(147),
SAVE => INT_SUM(148), CARRY => INT_CARRY(122)
);
---- End FA stage
---- Begin FA stage
FA_124:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(112), DATA_B => INT_CARRY(113), DATA_C => INT_CARRY(114),
SAVE => INT_SUM(149), CARRY => INT_CARRY(123)
);
---- End FA stage
---- Begin FA stage
FA_125:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(148), DATA_B => INT_SUM(149), DATA_C => INT_CARRY(115),
SAVE => INT_SUM(150), CARRY => INT_CARRY(124)
);
---- End FA stage
---- Begin NO stage
INT_SUM(151) <= INT_CARRY(116); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_126:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(117),
SAVE => INT_SUM(152), CARRY => INT_CARRY(125)
);
---- End FA stage
---- Begin HA stage
HA_25:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(152), DATA_B => INT_CARRY(118),
SAVE => SUM(27), CARRY => CARRY(27)
);
---- End HA stage
-- End WT-branch 28
-- Begin WT-branch 29
---- Begin FA stage
FA_127:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(189), DATA_B => SUMMAND(190), DATA_C => SUMMAND(191),
SAVE => INT_SUM(153), CARRY => INT_CARRY(126)
);
---- End FA stage
---- Begin FA stage
FA_128:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(192), DATA_B => SUMMAND(193), DATA_C => SUMMAND(194),
SAVE => INT_SUM(154), CARRY => INT_CARRY(127)
);
---- End FA stage
---- Begin FA stage
FA_129:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(195), DATA_B => SUMMAND(196), DATA_C => SUMMAND(197),
SAVE => INT_SUM(155), CARRY => INT_CARRY(128)
);
---- End FA stage
---- Begin FA stage
FA_130:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(153), DATA_B => INT_SUM(154), DATA_C => INT_SUM(155),
SAVE => INT_SUM(156), CARRY => INT_CARRY(129)
);
---- End FA stage
---- Begin FA stage
FA_131:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(119), DATA_B => INT_CARRY(120), DATA_C => INT_CARRY(121),
SAVE => INT_SUM(157), CARRY => INT_CARRY(130)
);
---- End FA stage
---- Begin FA stage
FA_132:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(156), DATA_B => INT_SUM(157), DATA_C => INT_CARRY(122),
SAVE => INT_SUM(158), CARRY => INT_CARRY(131)
);
---- End FA stage
---- Begin NO stage
INT_SUM(159) <= INT_CARRY(123); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_133:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(158), DATA_B => INT_SUM(159), DATA_C => INT_CARRY(124),
SAVE => INT_SUM(160), CARRY => INT_CARRY(132)
);
---- End FA stage
---- Begin HA stage
HA_26:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(160), DATA_B => INT_CARRY(125),
SAVE => SUM(28), CARRY => CARRY(28)
);
---- End HA stage
-- End WT-branch 29
-- Begin WT-branch 30
---- Begin FA stage
FA_134:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(198), DATA_B => SUMMAND(199), DATA_C => SUMMAND(200),
SAVE => INT_SUM(161), CARRY => INT_CARRY(133)
);
---- End FA stage
---- Begin FA stage
FA_135:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(201), DATA_B => SUMMAND(202), DATA_C => SUMMAND(203),
SAVE => INT_SUM(162), CARRY => INT_CARRY(134)
);
---- End FA stage
---- Begin FA stage
FA_136:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(204), DATA_B => SUMMAND(205), DATA_C => SUMMAND(206),
SAVE => INT_SUM(163), CARRY => INT_CARRY(135)
);
---- End FA stage
---- Begin FA stage
FA_137:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(161), DATA_B => INT_SUM(162), DATA_C => INT_SUM(163),
SAVE => INT_SUM(164), CARRY => INT_CARRY(136)
);
---- End FA stage
---- Begin FA stage
FA_138:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(126), DATA_B => INT_CARRY(127), DATA_C => INT_CARRY(128),
SAVE => INT_SUM(165), CARRY => INT_CARRY(137)
);
---- End FA stage
---- Begin FA stage
FA_139:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(164), DATA_B => INT_SUM(165), DATA_C => INT_CARRY(129),
SAVE => INT_SUM(166), CARRY => INT_CARRY(138)
);
---- End FA stage
---- Begin NO stage
INT_SUM(167) <= INT_CARRY(130); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_140:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(166), DATA_B => INT_SUM(167), DATA_C => INT_CARRY(131),
SAVE => INT_SUM(168), CARRY => INT_CARRY(139)
);
---- End FA stage
---- Begin HA stage
HA_27:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(168), DATA_B => INT_CARRY(132),
SAVE => SUM(29), CARRY => CARRY(29)
);
---- End HA stage
-- End WT-branch 30
-- Begin WT-branch 31
---- Begin FA stage
FA_141:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(207), DATA_B => SUMMAND(208), DATA_C => SUMMAND(209),
SAVE => INT_SUM(169), CARRY => INT_CARRY(140)
);
---- End FA stage
---- Begin FA stage
FA_142:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(210), DATA_B => SUMMAND(211), DATA_C => SUMMAND(212),
SAVE => INT_SUM(170), CARRY => INT_CARRY(141)
);
---- End FA stage
---- Begin FA stage
FA_143:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(213), DATA_B => SUMMAND(214), DATA_C => SUMMAND(215),
SAVE => INT_SUM(171), CARRY => INT_CARRY(142)
);
---- End FA stage
---- Begin FA stage
FA_144:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(169), DATA_B => INT_SUM(170), DATA_C => INT_SUM(171),
SAVE => INT_SUM(172), CARRY => INT_CARRY(143)
);
---- End FA stage
---- Begin FA stage
FA_145:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(133), DATA_B => INT_CARRY(134), DATA_C => INT_CARRY(135),
SAVE => INT_SUM(173), CARRY => INT_CARRY(144)
);
---- End FA stage
---- Begin FA stage
FA_146:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(172), DATA_B => INT_SUM(173), DATA_C => INT_CARRY(136),
SAVE => INT_SUM(174), CARRY => INT_CARRY(145)
);
---- End FA stage
---- Begin NO stage
INT_SUM(175) <= INT_CARRY(137); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_147:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(174), DATA_B => INT_SUM(175), DATA_C => INT_CARRY(138),
SAVE => INT_SUM(176), CARRY => INT_CARRY(146)
);
---- End FA stage
---- Begin HA stage
HA_28:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(176), DATA_B => INT_CARRY(139),
SAVE => SUM(30), CARRY => CARRY(30)
);
---- End HA stage
-- End WT-branch 31
-- Begin WT-branch 32
---- Begin FA stage
FA_148:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(216), DATA_B => SUMMAND(217), DATA_C => SUMMAND(218),
SAVE => INT_SUM(177), CARRY => INT_CARRY(147)
);
---- End FA stage
---- Begin FA stage
FA_149:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(219), DATA_B => SUMMAND(220), DATA_C => SUMMAND(221),
SAVE => INT_SUM(178), CARRY => INT_CARRY(148)
);
---- End FA stage
---- Begin FA stage
FA_150:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(222), DATA_B => SUMMAND(223), DATA_C => SUMMAND(224),
SAVE => INT_SUM(179), CARRY => INT_CARRY(149)
);
---- End FA stage
---- Begin FA stage
FA_151:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(177), DATA_B => INT_SUM(178), DATA_C => INT_SUM(179),
SAVE => INT_SUM(180), CARRY => INT_CARRY(150)
);
---- End FA stage
---- Begin FA stage
FA_152:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(140), DATA_B => INT_CARRY(141), DATA_C => INT_CARRY(142),
SAVE => INT_SUM(181), CARRY => INT_CARRY(151)
);
---- End FA stage
---- Begin FA stage
FA_153:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(180), DATA_B => INT_SUM(181), DATA_C => INT_CARRY(143),
SAVE => INT_SUM(182), CARRY => INT_CARRY(152)
);
---- End FA stage
---- Begin NO stage
INT_SUM(183) <= INT_CARRY(144); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_154:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(182), DATA_B => INT_SUM(183), DATA_C => INT_CARRY(145),
SAVE => INT_SUM(184), CARRY => INT_CARRY(153)
);
---- End FA stage
---- Begin HA stage
HA_29:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(184), DATA_B => INT_CARRY(146),
SAVE => SUM(31), CARRY => CARRY(31)
);
---- End HA stage
-- End WT-branch 32
-- Begin WT-branch 33
---- Begin FA stage
FA_155:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(225), DATA_B => SUMMAND(226), DATA_C => SUMMAND(227),
SAVE => INT_SUM(185), CARRY => INT_CARRY(154)
);
---- End FA stage
---- Begin FA stage
FA_156:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(228), DATA_B => SUMMAND(229), DATA_C => SUMMAND(230),
SAVE => INT_SUM(186), CARRY => INT_CARRY(155)
);
---- End FA stage
---- Begin FA stage
FA_157:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(231), DATA_B => SUMMAND(232), DATA_C => SUMMAND(233),
SAVE => INT_SUM(187), CARRY => INT_CARRY(156)
);
---- End FA stage
---- Begin FA stage
FA_158:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(185), DATA_B => INT_SUM(186), DATA_C => INT_SUM(187),
SAVE => INT_SUM(188), CARRY => INT_CARRY(157)
);
---- End FA stage
---- Begin FA stage
FA_159:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(147), DATA_B => INT_CARRY(148), DATA_C => INT_CARRY(149),
SAVE => INT_SUM(189), CARRY => INT_CARRY(158)
);
---- End FA stage
---- Begin FA stage
FA_160:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(188), DATA_B => INT_SUM(189), DATA_C => INT_CARRY(150),
SAVE => INT_SUM(190), CARRY => INT_CARRY(159)
);
---- End FA stage
---- Begin NO stage
INT_SUM(191) <= INT_CARRY(151); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_161:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(190), DATA_B => INT_SUM(191), DATA_C => INT_CARRY(152),
SAVE => INT_SUM(192), CARRY => INT_CARRY(160)
);
---- End FA stage
---- Begin HA stage
HA_30:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(192), DATA_B => INT_CARRY(153),
SAVE => SUM(32), CARRY => CARRY(32)
);
---- End HA stage
-- End WT-branch 33
-- Begin WT-branch 34
---- Begin FA stage
FA_162:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(234), DATA_B => SUMMAND(235), DATA_C => SUMMAND(236),
SAVE => INT_SUM(193), CARRY => INT_CARRY(161)
);
---- End FA stage
---- Begin FA stage
FA_163:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(237), DATA_B => SUMMAND(238), DATA_C => SUMMAND(239),
SAVE => INT_SUM(194), CARRY => INT_CARRY(162)
);
---- End FA stage
---- Begin FA stage
FA_164:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(240), DATA_B => SUMMAND(241), DATA_C => SUMMAND(242),
SAVE => INT_SUM(195), CARRY => INT_CARRY(163)
);
---- End FA stage
---- Begin FA stage
FA_165:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(193), DATA_B => INT_SUM(194), DATA_C => INT_SUM(195),
SAVE => INT_SUM(196), CARRY => INT_CARRY(164)
);
---- End FA stage
---- Begin FA stage
FA_166:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(154), DATA_B => INT_CARRY(155), DATA_C => INT_CARRY(156),
SAVE => INT_SUM(197), CARRY => INT_CARRY(165)
);
---- End FA stage
---- Begin FA stage
FA_167:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(196), DATA_B => INT_SUM(197), DATA_C => INT_CARRY(157),
SAVE => INT_SUM(198), CARRY => INT_CARRY(166)
);
---- End FA stage
---- Begin NO stage
INT_SUM(199) <= INT_CARRY(158); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_168:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(198), DATA_B => INT_SUM(199), DATA_C => INT_CARRY(159),
SAVE => INT_SUM(200), CARRY => INT_CARRY(167)
);
---- End FA stage
---- Begin HA stage
HA_31:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(200), DATA_B => INT_CARRY(160),
SAVE => SUM(33), CARRY => CARRY(33)
);
---- End HA stage
-- End WT-branch 34
-- Begin WT-branch 35
---- Begin FA stage
FA_169:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(243), DATA_B => SUMMAND(244), DATA_C => SUMMAND(245),
SAVE => INT_SUM(201), CARRY => INT_CARRY(168)
);
---- End FA stage
---- Begin FA stage
FA_170:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(246), DATA_B => SUMMAND(247), DATA_C => SUMMAND(248),
SAVE => INT_SUM(202), CARRY => INT_CARRY(169)
);
---- End FA stage
---- Begin FA stage
FA_171:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(249), DATA_B => SUMMAND(250), DATA_C => SUMMAND(251),
SAVE => INT_SUM(203), CARRY => INT_CARRY(170)
);
---- End FA stage
---- Begin NO stage
INT_SUM(204) <= SUMMAND(252); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_172:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(201), DATA_B => INT_SUM(202), DATA_C => INT_SUM(203),
SAVE => INT_SUM(205), CARRY => INT_CARRY(171)
);
---- End FA stage
---- Begin FA stage
FA_173:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(204), DATA_B => INT_CARRY(161), DATA_C => INT_CARRY(162),
SAVE => INT_SUM(206), CARRY => INT_CARRY(172)
);
---- End FA stage
---- Begin NO stage
INT_SUM(207) <= INT_CARRY(163); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_174:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(205), DATA_B => INT_SUM(206), DATA_C => INT_SUM(207),
SAVE => INT_SUM(208), CARRY => INT_CARRY(173)
);
---- End FA stage
---- Begin NO stage
INT_SUM(209) <= INT_CARRY(164); -- At Level 3
---- End NO stage
---- Begin NO stage
INT_SUM(210) <= INT_CARRY(165); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_175:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(208), DATA_B => INT_SUM(209), DATA_C => INT_SUM(210),
SAVE => INT_SUM(211), CARRY => INT_CARRY(174)
);
---- End FA stage
---- Begin NO stage
INT_SUM(212) <= INT_CARRY(166); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_176:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(211), DATA_B => INT_SUM(212), DATA_C => INT_CARRY(167),
SAVE => SUM(34), CARRY => CARRY(34)
);
---- End FA stage
-- End WT-branch 35
-- Begin WT-branch 36
---- Begin FA stage
FA_177:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(253), DATA_B => SUMMAND(254), DATA_C => SUMMAND(255),
SAVE => INT_SUM(213), CARRY => INT_CARRY(175)
);
---- End FA stage
---- Begin FA stage
FA_178:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(256), DATA_B => SUMMAND(257), DATA_C => SUMMAND(258),
SAVE => INT_SUM(214), CARRY => INT_CARRY(176)
);
---- End FA stage
---- Begin FA stage
FA_179:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(259), DATA_B => SUMMAND(260), DATA_C => SUMMAND(261),
SAVE => INT_SUM(215), CARRY => INT_CARRY(177)
);
---- End FA stage
---- Begin FA stage
FA_180:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(168), DATA_B => INT_CARRY(169), DATA_C => INT_CARRY(170),
SAVE => INT_SUM(216), CARRY => INT_CARRY(178)
);
---- End FA stage
---- Begin FA stage
FA_181:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(213), DATA_B => INT_SUM(214), DATA_C => INT_SUM(215),
SAVE => INT_SUM(217), CARRY => INT_CARRY(179)
);
---- End FA stage
---- Begin FA stage
FA_182:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(216), DATA_B => INT_CARRY(171), DATA_C => INT_CARRY(172),
SAVE => INT_SUM(218), CARRY => INT_CARRY(180)
);
---- End FA stage
---- Begin FA stage
FA_183:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(217), DATA_B => INT_SUM(218), DATA_C => INT_CARRY(173),
SAVE => INT_SUM(219), CARRY => INT_CARRY(181)
);
---- End FA stage
---- Begin HA stage
HA_32:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(219), DATA_B => INT_CARRY(174),
SAVE => SUM(35), CARRY => CARRY(35)
);
---- End HA stage
-- End WT-branch 36
-- Begin WT-branch 37
---- Begin FA stage
FA_184:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(262), DATA_B => SUMMAND(263), DATA_C => SUMMAND(264),
SAVE => INT_SUM(220), CARRY => INT_CARRY(182)
);
---- End FA stage
---- Begin FA stage
FA_185:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(265), DATA_B => SUMMAND(266), DATA_C => SUMMAND(267),
SAVE => INT_SUM(221), CARRY => INT_CARRY(183)
);
---- End FA stage
---- Begin NO stage
INT_SUM(222) <= SUMMAND(268); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(223) <= SUMMAND(269); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_186:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(220), DATA_B => INT_SUM(221), DATA_C => INT_SUM(222),
SAVE => INT_SUM(224), CARRY => INT_CARRY(184)
);
---- End FA stage
---- Begin NO stage
INT_SUM(225) <= INT_SUM(223); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_187:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(224), DATA_B => INT_SUM(225), DATA_C => INT_CARRY(175),
SAVE => INT_SUM(226), CARRY => INT_CARRY(185)
);
---- End FA stage
---- Begin FA stage
FA_188:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(176), DATA_B => INT_CARRY(177), DATA_C => INT_CARRY(178),
SAVE => INT_SUM(227), CARRY => INT_CARRY(186)
);
---- End FA stage
---- Begin FA stage
FA_189:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(226), DATA_B => INT_SUM(227), DATA_C => INT_CARRY(179),
SAVE => INT_SUM(228), CARRY => INT_CARRY(187)
);
---- End FA stage
---- Begin NO stage
INT_SUM(229) <= INT_CARRY(180); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_190:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(228), DATA_B => INT_SUM(229), DATA_C => INT_CARRY(181),
SAVE => SUM(36), CARRY => CARRY(36)
);
---- End FA stage
-- End WT-branch 37
-- Begin WT-branch 38
---- Begin FA stage
FA_191:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(270), DATA_B => SUMMAND(271), DATA_C => SUMMAND(272),
SAVE => INT_SUM(230), CARRY => INT_CARRY(188)
);
---- End FA stage
---- Begin FA stage
FA_192:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(273), DATA_B => SUMMAND(274), DATA_C => SUMMAND(275),
SAVE => INT_SUM(231), CARRY => INT_CARRY(189)
);
---- End FA stage
---- Begin FA stage
FA_193:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(276), DATA_B => SUMMAND(277), DATA_C => INT_CARRY(182),
SAVE => INT_SUM(232), CARRY => INT_CARRY(190)
);
---- End FA stage
---- Begin NO stage
INT_SUM(233) <= INT_CARRY(183); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_194:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(230), DATA_B => INT_SUM(231), DATA_C => INT_SUM(232),
SAVE => INT_SUM(234), CARRY => INT_CARRY(191)
);
---- End FA stage
---- Begin HA stage
HA_33:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(233), DATA_B => INT_CARRY(184),
SAVE => INT_SUM(235), CARRY => INT_CARRY(192)
);
---- End HA stage
---- Begin FA stage
FA_195:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(234), DATA_B => INT_SUM(235), DATA_C => INT_CARRY(185),
SAVE => INT_SUM(236), CARRY => INT_CARRY(193)
);
---- End FA stage
---- Begin NO stage
INT_SUM(237) <= INT_CARRY(186); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_196:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(236), DATA_B => INT_SUM(237), DATA_C => INT_CARRY(187),
SAVE => SUM(37), CARRY => CARRY(37)
);
---- End FA stage
-- End WT-branch 38
-- Begin WT-branch 39
---- Begin FA stage
FA_197:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(278), DATA_B => SUMMAND(279), DATA_C => SUMMAND(280),
SAVE => INT_SUM(238), CARRY => INT_CARRY(194)
);
---- End FA stage
---- Begin FA stage
FA_198:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(281), DATA_B => SUMMAND(282), DATA_C => SUMMAND(283),
SAVE => INT_SUM(239), CARRY => INT_CARRY(195)
);
---- End FA stage
---- Begin NO stage
INT_SUM(240) <= SUMMAND(284); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_199:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(238), DATA_B => INT_SUM(239), DATA_C => INT_SUM(240),
SAVE => INT_SUM(241), CARRY => INT_CARRY(196)
);
---- End FA stage
---- Begin FA stage
FA_200:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(188), DATA_B => INT_CARRY(189), DATA_C => INT_CARRY(190),
SAVE => INT_SUM(242), CARRY => INT_CARRY(197)
);
---- End FA stage
---- Begin FA stage
FA_201:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(241), DATA_B => INT_SUM(242), DATA_C => INT_CARRY(191),
SAVE => INT_SUM(243), CARRY => INT_CARRY(198)
);
---- End FA stage
---- Begin NO stage
INT_SUM(244) <= INT_CARRY(192); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_202:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(243), DATA_B => INT_SUM(244), DATA_C => INT_CARRY(193),
SAVE => SUM(38), CARRY => CARRY(38)
);
---- End FA stage
-- End WT-branch 39
-- Begin WT-branch 40
---- Begin FA stage
FA_203:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(285), DATA_B => SUMMAND(286), DATA_C => SUMMAND(287),
SAVE => INT_SUM(245), CARRY => INT_CARRY(199)
);
---- End FA stage
---- Begin FA stage
FA_204:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(288), DATA_B => SUMMAND(289), DATA_C => SUMMAND(290),
SAVE => INT_SUM(246), CARRY => INT_CARRY(200)
);
---- End FA stage
---- Begin NO stage
INT_SUM(247) <= SUMMAND(291); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_205:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(245), DATA_B => INT_SUM(246), DATA_C => INT_SUM(247),
SAVE => INT_SUM(248), CARRY => INT_CARRY(201)
);
---- End FA stage
---- Begin HA stage
HA_34:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(194), DATA_B => INT_CARRY(195),
SAVE => INT_SUM(249), CARRY => INT_CARRY(202)
);
---- End HA stage
---- Begin FA stage
FA_206:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(248), DATA_B => INT_SUM(249), DATA_C => INT_CARRY(196),
SAVE => INT_SUM(250), CARRY => INT_CARRY(203)
);
---- End FA stage
---- Begin NO stage
INT_SUM(251) <= INT_CARRY(197); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_207:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(250), DATA_B => INT_SUM(251), DATA_C => INT_CARRY(198),
SAVE => SUM(39), CARRY => CARRY(39)
);
---- End FA stage
-- End WT-branch 40
-- Begin WT-branch 41
---- Begin FA stage
FA_208:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(292), DATA_B => SUMMAND(293), DATA_C => SUMMAND(294),
SAVE => INT_SUM(252), CARRY => INT_CARRY(204)
);
---- End FA stage
---- Begin FA stage
FA_209:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(295), DATA_B => SUMMAND(296), DATA_C => SUMMAND(297),
SAVE => INT_SUM(253), CARRY => INT_CARRY(205)
);
---- End FA stage
---- Begin FA stage
FA_210:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(252), DATA_B => INT_SUM(253), DATA_C => INT_CARRY(199),
SAVE => INT_SUM(254), CARRY => INT_CARRY(206)
);
---- End FA stage
---- Begin NO stage
INT_SUM(255) <= INT_CARRY(200); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_211:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(254), DATA_B => INT_SUM(255), DATA_C => INT_CARRY(201),
SAVE => INT_SUM(256), CARRY => INT_CARRY(207)
);
---- End FA stage
---- Begin NO stage
INT_SUM(257) <= INT_CARRY(202); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_212:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(256), DATA_B => INT_SUM(257), DATA_C => INT_CARRY(203),
SAVE => SUM(40), CARRY => CARRY(40)
);
---- End FA stage
-- End WT-branch 41
-- Begin WT-branch 42
---- Begin FA stage
FA_213:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(298), DATA_B => SUMMAND(299), DATA_C => SUMMAND(300),
SAVE => INT_SUM(258), CARRY => INT_CARRY(208)
);
---- End FA stage
---- Begin FA stage
FA_214:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(301), DATA_B => SUMMAND(302), DATA_C => SUMMAND(303),
SAVE => INT_SUM(259), CARRY => INT_CARRY(209)
);
---- End FA stage
---- Begin FA stage
FA_215:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(258), DATA_B => INT_SUM(259), DATA_C => INT_CARRY(204),
SAVE => INT_SUM(260), CARRY => INT_CARRY(210)
);
---- End FA stage
---- Begin NO stage
INT_SUM(261) <= INT_CARRY(205); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_216:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(260), DATA_B => INT_SUM(261), DATA_C => INT_CARRY(206),
SAVE => INT_SUM(262), CARRY => INT_CARRY(211)
);
---- End FA stage
---- Begin HA stage
HA_35:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(262), DATA_B => INT_CARRY(207),
SAVE => SUM(41), CARRY => CARRY(41)
);
---- End HA stage
-- End WT-branch 42
-- Begin WT-branch 43
---- Begin FA stage
FA_217:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(304), DATA_B => SUMMAND(305), DATA_C => SUMMAND(306),
SAVE => INT_SUM(263), CARRY => INT_CARRY(212)
);
---- End FA stage
---- Begin HA stage
HA_36:HALF_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(307), DATA_B => SUMMAND(308),
SAVE => INT_SUM(264), CARRY => INT_CARRY(213)
);
---- End HA stage
---- Begin FA stage
FA_218:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(263), DATA_B => INT_SUM(264), DATA_C => INT_CARRY(208),
SAVE => INT_SUM(265), CARRY => INT_CARRY(214)
);
---- End FA stage
---- Begin NO stage
INT_SUM(266) <= INT_CARRY(209); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_219:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(265), DATA_B => INT_SUM(266), DATA_C => INT_CARRY(210),
SAVE => INT_SUM(267), CARRY => INT_CARRY(215)
);
---- End FA stage
---- Begin HA stage
HA_37:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(267), DATA_B => INT_CARRY(211),
SAVE => SUM(42), CARRY => CARRY(42)
);
---- End HA stage
-- End WT-branch 43
-- Begin WT-branch 44
---- Begin FA stage
FA_220:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(309), DATA_B => SUMMAND(310), DATA_C => SUMMAND(311),
SAVE => INT_SUM(268), CARRY => INT_CARRY(216)
);
---- End FA stage
---- Begin HA stage
HA_38:HALF_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(312), DATA_B => SUMMAND(313),
SAVE => INT_SUM(269), CARRY => INT_CARRY(217)
);
---- End HA stage
---- Begin FA stage
FA_221:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(268), DATA_B => INT_SUM(269), DATA_C => INT_CARRY(212),
SAVE => INT_SUM(270), CARRY => INT_CARRY(218)
);
---- End FA stage
---- Begin NO stage
INT_SUM(271) <= INT_CARRY(213); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_222:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(270), DATA_B => INT_SUM(271), DATA_C => INT_CARRY(214),
SAVE => INT_SUM(272), CARRY => INT_CARRY(219)
);
---- End FA stage
---- Begin HA stage
HA_39:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(272), DATA_B => INT_CARRY(215),
SAVE => SUM(43), CARRY => CARRY(43)
);
---- End HA stage
-- End WT-branch 44
-- Begin WT-branch 45
---- Begin FA stage
FA_223:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(314), DATA_B => SUMMAND(315), DATA_C => SUMMAND(316),
SAVE => INT_SUM(273), CARRY => INT_CARRY(220)
);
---- End FA stage
---- Begin FA stage
FA_224:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(317), DATA_B => INT_CARRY(216), DATA_C => INT_CARRY(217),
SAVE => INT_SUM(274), CARRY => INT_CARRY(221)
);
---- End FA stage
---- Begin FA stage
FA_225:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(273), DATA_B => INT_SUM(274), DATA_C => INT_CARRY(218),
SAVE => INT_SUM(275), CARRY => INT_CARRY(222)
);
---- End FA stage
---- Begin HA stage
HA_40:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(275), DATA_B => INT_CARRY(219),
SAVE => SUM(44), CARRY => CARRY(44)
);
---- End HA stage
-- End WT-branch 45
-- Begin WT-branch 46
---- Begin FA stage
FA_226:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(318), DATA_B => SUMMAND(319), DATA_C => SUMMAND(320),
SAVE => INT_SUM(276), CARRY => INT_CARRY(223)
);
---- End FA stage
---- Begin NO stage
INT_SUM(277) <= SUMMAND(321); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_227:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(276), DATA_B => INT_SUM(277), DATA_C => INT_CARRY(220),
SAVE => INT_SUM(278), CARRY => INT_CARRY(224)
);
---- End FA stage
---- Begin NO stage
INT_SUM(279) <= INT_CARRY(221); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_228:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(278), DATA_B => INT_SUM(279), DATA_C => INT_CARRY(222),
SAVE => SUM(45), CARRY => CARRY(45)
);
---- End FA stage
-- End WT-branch 46
-- Begin WT-branch 47
---- Begin FA stage
FA_229:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(322), DATA_B => SUMMAND(323), DATA_C => SUMMAND(324),
SAVE => INT_SUM(280), CARRY => INT_CARRY(225)
);
---- End FA stage
---- Begin NO stage
INT_SUM(281) <= INT_SUM(280); -- At Level 4
---- End NO stage
---- Begin NO stage
INT_SUM(282) <= INT_CARRY(223); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_230:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(281), DATA_B => INT_SUM(282), DATA_C => INT_CARRY(224),
SAVE => SUM(46), CARRY => CARRY(46)
);
---- End FA stage
-- End WT-branch 47
-- Begin WT-branch 48
---- Begin FA stage
FA_231:FULL_ADDER -- At Level 4
port map
(
DATA_A => SUMMAND(325), DATA_B => SUMMAND(326), DATA_C => SUMMAND(327),
SAVE => INT_SUM(283), CARRY => INT_CARRY(226)
);
---- End FA stage
---- Begin NO stage
INT_SUM(284) <= INT_CARRY(225); -- At Level 4
---- End NO stage
---- Begin HA stage
HA_41:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(283), DATA_B => INT_SUM(284),
SAVE => SUM(47), CARRY => CARRY(47)
);
---- End HA stage
-- End WT-branch 48
-- Begin WT-branch 49
---- Begin NO stage
INT_SUM(285) <= SUMMAND(328); -- At Level 4
---- End NO stage
---- Begin NO stage
INT_SUM(286) <= SUMMAND(329); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_232:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(285), DATA_B => INT_SUM(286), DATA_C => INT_CARRY(226),
SAVE => SUM(48), CARRY => CARRY(48)
);
---- End FA stage
-- End WT-branch 49
-- Begin WT-branch 50
---- Begin HA stage
HA_42:HALF_ADDER -- At Level 5
port map
(
DATA_A => SUMMAND(330), DATA_B => SUMMAND(331),
SAVE => SUM(49), CARRY => CARRY(49)
);
---- End HA stage
-- End WT-branch 50
-- Begin WT-branch 51
---- Begin NO stage
SUM(50) <= SUMMAND(332); -- At Level 5
---- End NO stage
-- End WT-branch 51
end WALLACE;
------------------------------------------------------------
-- END: Architectures used with the Wallace-tree
------------------------------------------------------------
------------------------------------------------------------
-- START: Architectures used with the multiplier
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity MULTIPLIER_34_18 is
port
(
MULTIPLICAND: in std_logic_vector(0 to 33);
MULTIPLIER: in std_logic_vector(0 to 17);
PHI: in std_logic;
RESULT: out std_logic_vector(0 to 63)
);
end MULTIPLIER_34_18;
------------------------------------------------------------
-- End: Multiplier Entitiy
architecture MULTIPLIER of MULTIPLIER_34_18 is
signal PPBIT:std_logic_vector(0 to 332);
signal INT_CARRY: std_logic_vector(0 to 64);
signal INT_SUM: std_logic_vector(0 to 63);
signal LOGIC_ZERO: std_logic;
begin -- Architecture
LOGIC_ZERO <= '0';
B:BOOTHCODER_34_18
port map
(
OPA(0 to 33) => MULTIPLICAND(0 to 33),
OPB(0 to 17) => MULTIPLIER(0 to 17),
SUMMAND(0 to 332) => PPBIT(0 to 332)
);
W:WALLACE_34_18
port map
(
SUMMAND(0 to 332) => PPBIT(0 to 332),
CARRY(0 to 49) => INT_CARRY(1 to 50),
SUM(0 to 50) => INT_SUM(0 to 50)
);
INT_CARRY(0) <= LOGIC_ZERO;
INT_CARRY(51) <= LOGIC_ZERO;
INT_CARRY(52) <= LOGIC_ZERO;
INT_CARRY(53) <= LOGIC_ZERO;
INT_CARRY(54) <= LOGIC_ZERO;
INT_CARRY(55) <= LOGIC_ZERO;
INT_CARRY(56) <= LOGIC_ZERO;
INT_CARRY(57) <= LOGIC_ZERO;
INT_CARRY(58) <= LOGIC_ZERO;
INT_CARRY(59) <= LOGIC_ZERO;
INT_CARRY(60) <= LOGIC_ZERO;
INT_CARRY(61) <= LOGIC_ZERO;
INT_CARRY(62) <= LOGIC_ZERO;
INT_CARRY(63) <= LOGIC_ZERO;
INT_SUM(51) <= LOGIC_ZERO;
INT_SUM(52) <= LOGIC_ZERO;
INT_SUM(53) <= LOGIC_ZERO;
INT_SUM(54) <= LOGIC_ZERO;
INT_SUM(55) <= LOGIC_ZERO;
INT_SUM(56) <= LOGIC_ZERO;
INT_SUM(57) <= LOGIC_ZERO;
INT_SUM(58) <= LOGIC_ZERO;
INT_SUM(59) <= LOGIC_ZERO;
INT_SUM(60) <= LOGIC_ZERO;
INT_SUM(61) <= LOGIC_ZERO;
INT_SUM(62) <= LOGIC_ZERO;
INT_SUM(63) <= LOGIC_ZERO;
D:DBLCADDER_64_64
port map
(
OPA(0 to 63) => INT_SUM(0 to 63),
OPB(0 to 63) => INT_CARRY(0 to 63),
CIN => LOGIC_ZERO,
PHI => PHI,
SUM(0 to 63) => RESULT(0 to 63)
);
end MULTIPLIER;
------------------------------------------------------------
-- END: Architectures used with the multiplier
------------------------------------------------------------
--
-- Modgen multiplier created Fri Aug 16 16:29:15 2002
--
------------------------------------------------------------
-- START: Multiplier Entitiy
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- START: Top entity
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity MUL_33_17 is
port(X: in std_logic_vector(32 downto 0);
Y: in std_logic_vector(16 downto 0);
P: out std_logic_vector(49 downto 0));
end MUL_33_17;
library ieee;
use ieee.std_logic_1164.all;
architecture A of MUL_33_17 is
signal A: std_logic_vector(0 to 33);
signal B: std_logic_vector(0 to 17);
signal Q: std_logic_vector(0 to 63);
signal CLK: std_logic;
begin
U1: MULTIPLIER_34_18 port map(A,B,CLK,Q);
-- std_logic_vector reversals to incorporate decreasing vectors
A(0) <= X(0);
A(1) <= X(1);
A(2) <= X(2);
A(3) <= X(3);
A(4) <= X(4);
A(5) <= X(5);
A(6) <= X(6);
A(7) <= X(7);
A(8) <= X(8);
A(9) <= X(9);
A(10) <= X(10);
A(11) <= X(11);
A(12) <= X(12);
A(13) <= X(13);
A(14) <= X(14);
A(15) <= X(15);
A(16) <= X(16);
A(17) <= X(17);
A(18) <= X(18);
A(19) <= X(19);
A(20) <= X(20);
A(21) <= X(21);
A(22) <= X(22);
A(23) <= X(23);
A(24) <= X(24);
A(25) <= X(25);
A(26) <= X(26);
A(27) <= X(27);
A(28) <= X(28);
A(29) <= X(29);
A(30) <= X(30);
A(31) <= X(31);
A(32) <= X(32);
A(33) <= X(32);
B(0) <= Y(0);
B(1) <= Y(1);
B(2) <= Y(2);
B(3) <= Y(3);
B(4) <= Y(4);
B(5) <= Y(5);
B(6) <= Y(6);
B(7) <= Y(7);
B(8) <= Y(8);
B(9) <= Y(9);
B(10) <= Y(10);
B(11) <= Y(11);
B(12) <= Y(12);
B(13) <= Y(13);
B(14) <= Y(14);
B(15) <= Y(15);
B(16) <= Y(16);
B(17) <= Y(16);
P(0) <= Q(0);
P(1) <= Q(1);
P(2) <= Q(2);
P(3) <= Q(3);
P(4) <= Q(4);
P(5) <= Q(5);
P(6) <= Q(6);
P(7) <= Q(7);
P(8) <= Q(8);
P(9) <= Q(9);
P(10) <= Q(10);
P(11) <= Q(11);
P(12) <= Q(12);
P(13) <= Q(13);
P(14) <= Q(14);
P(15) <= Q(15);
P(16) <= Q(16);
P(17) <= Q(17);
P(18) <= Q(18);
P(19) <= Q(19);
P(20) <= Q(20);
P(21) <= Q(21);
P(22) <= Q(22);
P(23) <= Q(23);
P(24) <= Q(24);
P(25) <= Q(25);
P(26) <= Q(26);
P(27) <= Q(27);
P(28) <= Q(28);
P(29) <= Q(29);
P(30) <= Q(30);
P(31) <= Q(31);
P(32) <= Q(32);
P(33) <= Q(33);
P(34) <= Q(34);
P(35) <= Q(35);
P(36) <= Q(36);
P(37) <= Q(37);
P(38) <= Q(38);
P(39) <= Q(39);
P(40) <= Q(40);
P(41) <= Q(41);
P(42) <= Q(42);
P(43) <= Q(43);
P(44) <= Q(44);
P(45) <= Q(45);
P(46) <= Q(46);
P(47) <= Q(47);
P(48) <= Q(48);
P(49) <= Q(49);
end A;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity BOOTHCODER_34_34 is
port
(
OPA: in std_logic_vector(0 to 33);
OPB: in std_logic_vector(0 to 33);
SUMMAND: out std_logic_vector(0 to 628)
);
end BOOTHCODER_34_34;
architecture BOOTHCODER of BOOTHCODER_34_34 is
-- Internal signal in Booth structure
signal INV_MULTIPLICAND: std_logic_vector(0 to 33);
signal INT_MULTIPLIER: std_logic_vector(0 to 67);
signal LOGIC_ONE, LOGIC_ZERO: std_logic;
begin
LOGIC_ONE <= '1';
LOGIC_ZERO <= '0';
-- Begin decoder block 1
DEC_0:DECODER -- Decoder of multiplier operand
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3)
);
-- End decoder block 1
-- Begin partial product 1
INV_MULTIPLICAND(0) <= NOT OPA(0);
PPL_0:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(0)
);
RGATE_0:R_GATE
port map
(
INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
PPBIT => SUMMAND(1)
);
INV_MULTIPLICAND(1) <= NOT OPA(1);
PPM_0:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(2)
);
INV_MULTIPLICAND(2) <= NOT OPA(2);
PPM_1:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(3)
);
INV_MULTIPLICAND(3) <= NOT OPA(3);
PPM_2:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(6)
);
INV_MULTIPLICAND(4) <= NOT OPA(4);
PPM_3:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(8)
);
INV_MULTIPLICAND(5) <= NOT OPA(5);
PPM_4:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(12)
);
INV_MULTIPLICAND(6) <= NOT OPA(6);
PPM_5:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(15)
);
INV_MULTIPLICAND(7) <= NOT OPA(7);
PPM_6:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(20)
);
INV_MULTIPLICAND(8) <= NOT OPA(8);
PPM_7:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(24)
);
INV_MULTIPLICAND(9) <= NOT OPA(9);
PPM_8:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(30)
);
INV_MULTIPLICAND(10) <= NOT OPA(10);
PPM_9:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(35)
);
INV_MULTIPLICAND(11) <= NOT OPA(11);
PPM_10:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(42)
);
INV_MULTIPLICAND(12) <= NOT OPA(12);
PPM_11:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(48)
);
INV_MULTIPLICAND(13) <= NOT OPA(13);
PPM_12:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(56)
);
INV_MULTIPLICAND(14) <= NOT OPA(14);
PPM_13:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(63)
);
INV_MULTIPLICAND(15) <= NOT OPA(15);
PPM_14:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(72)
);
INV_MULTIPLICAND(16) <= NOT OPA(16);
PPM_15:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(80)
);
INV_MULTIPLICAND(17) <= NOT OPA(17);
PPM_16:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(90)
);
INV_MULTIPLICAND(18) <= NOT OPA(18);
PPM_17:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(99)
);
INV_MULTIPLICAND(19) <= NOT OPA(19);
PPM_18:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(110)
);
INV_MULTIPLICAND(20) <= NOT OPA(20);
PPM_19:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(120)
);
INV_MULTIPLICAND(21) <= NOT OPA(21);
PPM_20:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(132)
);
INV_MULTIPLICAND(22) <= NOT OPA(22);
PPM_21:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(143)
);
INV_MULTIPLICAND(23) <= NOT OPA(23);
PPM_22:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(156)
);
INV_MULTIPLICAND(24) <= NOT OPA(24);
PPM_23:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(168)
);
INV_MULTIPLICAND(25) <= NOT OPA(25);
PPM_24:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(182)
);
INV_MULTIPLICAND(26) <= NOT OPA(26);
PPM_25:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(195)
);
INV_MULTIPLICAND(27) <= NOT OPA(27);
PPM_26:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(210)
);
INV_MULTIPLICAND(28) <= NOT OPA(28);
PPM_27:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(224)
);
INV_MULTIPLICAND(29) <= NOT OPA(29);
PPM_28:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(240)
);
INV_MULTIPLICAND(30) <= NOT OPA(30);
PPM_29:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(255)
);
INV_MULTIPLICAND(31) <= NOT OPA(31);
PPM_30:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(272)
);
INV_MULTIPLICAND(32) <= NOT OPA(32);
PPM_31:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(288)
);
INV_MULTIPLICAND(33) <= NOT OPA(33);
PPM_32:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(306)
);
PPH_0:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
PPBIT => SUMMAND(323)
);
SUMMAND(324) <= '1';
-- Begin partial product 1
-- Begin decoder block 2
DEC_1:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7)
);
-- End decoder block 2
-- Begin partial product 2
PPL_1:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(4)
);
RGATE_1:R_GATE
port map
(
INA => OPB(1),INB => OPB(2),INC => OPB(3),
PPBIT => SUMMAND(5)
);
PPM_33:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(7)
);
PPM_34:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(9)
);
PPM_35:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(13)
);
PPM_36:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(16)
);
PPM_37:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(21)
);
PPM_38:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(25)
);
PPM_39:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(31)
);
PPM_40:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(36)
);
PPM_41:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(43)
);
PPM_42:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(49)
);
PPM_43:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(57)
);
PPM_44:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(64)
);
PPM_45:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(73)
);
PPM_46:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(81)
);
PPM_47:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(91)
);
PPM_48:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(100)
);
PPM_49:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(111)
);
PPM_50:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(121)
);
PPM_51:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(133)
);
PPM_52:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(144)
);
PPM_53:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(157)
);
PPM_54:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(169)
);
PPM_55:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(183)
);
PPM_56:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(196)
);
PPM_57:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(211)
);
PPM_58:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(225)
);
PPM_59:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(241)
);
PPM_60:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(256)
);
PPM_61:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(273)
);
PPM_62:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(289)
);
PPM_63:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(307)
);
PPM_64:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(325)
);
PPM_65:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(341)
);
SUMMAND(342) <= LOGIC_ONE;
PPH_1:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
PPBIT => SUMMAND(358)
);
-- Begin partial product 2
-- Begin decoder block 3
DEC_2:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11)
);
-- End decoder block 3
-- Begin partial product 3
PPL_2:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(10)
);
RGATE_2:R_GATE
port map
(
INA => OPB(3),INB => OPB(4),INC => OPB(5),
PPBIT => SUMMAND(11)
);
PPM_66:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(14)
);
PPM_67:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(17)
);
PPM_68:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(22)
);
PPM_69:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(26)
);
PPM_70:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(32)
);
PPM_71:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(37)
);
PPM_72:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(44)
);
PPM_73:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(50)
);
PPM_74:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(58)
);
PPM_75:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(65)
);
PPM_76:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(74)
);
PPM_77:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(82)
);
PPM_78:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(92)
);
PPM_79:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(101)
);
PPM_80:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(112)
);
PPM_81:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(122)
);
PPM_82:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(134)
);
PPM_83:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(145)
);
PPM_84:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(158)
);
PPM_85:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(170)
);
PPM_86:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(184)
);
PPM_87:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(197)
);
PPM_88:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(212)
);
PPM_89:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(226)
);
PPM_90:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(242)
);
PPM_91:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(257)
);
PPM_92:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(274)
);
PPM_93:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(290)
);
PPM_94:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(308)
);
PPM_95:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(326)
);
PPM_96:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(343)
);
PPM_97:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(359)
);
PPM_98:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(374)
);
SUMMAND(375) <= LOGIC_ONE;
PPH_2:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(8),TWONEG => INT_MULTIPLIER(9),ONEPOS => INT_MULTIPLIER(10),ONENEG => INT_MULTIPLIER(11),
PPBIT => SUMMAND(390)
);
-- Begin partial product 3
-- Begin decoder block 4
DEC_3:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15)
);
-- End decoder block 4
-- Begin partial product 4
PPL_3:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(18)
);
RGATE_3:R_GATE
port map
(
INA => OPB(5),INB => OPB(6),INC => OPB(7),
PPBIT => SUMMAND(19)
);
PPM_99:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(23)
);
PPM_100:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(27)
);
PPM_101:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(33)
);
PPM_102:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(38)
);
PPM_103:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(45)
);
PPM_104:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(51)
);
PPM_105:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(59)
);
PPM_106:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(66)
);
PPM_107:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(75)
);
PPM_108:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(83)
);
PPM_109:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(93)
);
PPM_110:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(102)
);
PPM_111:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(113)
);
PPM_112:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(123)
);
PPM_113:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(135)
);
PPM_114:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(146)
);
PPM_115:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(159)
);
PPM_116:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(171)
);
PPM_117:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(185)
);
PPM_118:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(198)
);
PPM_119:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(213)
);
PPM_120:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(227)
);
PPM_121:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(243)
);
PPM_122:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(258)
);
PPM_123:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(275)
);
PPM_124:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(291)
);
PPM_125:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(309)
);
PPM_126:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(327)
);
PPM_127:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(344)
);
PPM_128:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(360)
);
PPM_129:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(376)
);
PPM_130:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(391)
);
PPM_131:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(405)
);
SUMMAND(406) <= LOGIC_ONE;
PPH_3:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(12),TWONEG => INT_MULTIPLIER(13),ONEPOS => INT_MULTIPLIER(14),ONENEG => INT_MULTIPLIER(15),
PPBIT => SUMMAND(420)
);
-- Begin partial product 4
-- Begin decoder block 5
DEC_4:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19)
);
-- End decoder block 5
-- Begin partial product 5
PPL_4:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(28)
);
RGATE_4:R_GATE
port map
(
INA => OPB(7),INB => OPB(8),INC => OPB(9),
PPBIT => SUMMAND(29)
);
PPM_132:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(34)
);
PPM_133:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(39)
);
PPM_134:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(46)
);
PPM_135:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(52)
);
PPM_136:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(60)
);
PPM_137:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(67)
);
PPM_138:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(76)
);
PPM_139:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(84)
);
PPM_140:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(94)
);
PPM_141:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(103)
);
PPM_142:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(114)
);
PPM_143:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(124)
);
PPM_144:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(136)
);
PPM_145:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(147)
);
PPM_146:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(160)
);
PPM_147:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(172)
);
PPM_148:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(186)
);
PPM_149:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(199)
);
PPM_150:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(214)
);
PPM_151:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(228)
);
PPM_152:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(244)
);
PPM_153:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(259)
);
PPM_154:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(276)
);
PPM_155:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(292)
);
PPM_156:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(310)
);
PPM_157:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(328)
);
PPM_158:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(345)
);
PPM_159:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(361)
);
PPM_160:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(377)
);
PPM_161:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(392)
);
PPM_162:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(407)
);
PPM_163:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(421)
);
PPM_164:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(434)
);
SUMMAND(435) <= LOGIC_ONE;
PPH_4:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(16),TWONEG => INT_MULTIPLIER(17),ONEPOS => INT_MULTIPLIER(18),ONENEG => INT_MULTIPLIER(19),
PPBIT => SUMMAND(448)
);
-- Begin partial product 5
-- Begin decoder block 6
DEC_5:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(9),INB => OPB(10),INC => OPB(11),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23)
);
-- End decoder block 6
-- Begin partial product 6
PPL_5:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(40)
);
RGATE_5:R_GATE
port map
(
INA => OPB(9),INB => OPB(10),INC => OPB(11),
PPBIT => SUMMAND(41)
);
PPM_165:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(47)
);
PPM_166:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(53)
);
PPM_167:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(61)
);
PPM_168:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(68)
);
PPM_169:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(77)
);
PPM_170:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(85)
);
PPM_171:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(95)
);
PPM_172:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(104)
);
PPM_173:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(115)
);
PPM_174:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(125)
);
PPM_175:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(137)
);
PPM_176:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(148)
);
PPM_177:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(161)
);
PPM_178:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(173)
);
PPM_179:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(187)
);
PPM_180:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(200)
);
PPM_181:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(215)
);
PPM_182:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(229)
);
PPM_183:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(245)
);
PPM_184:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(260)
);
PPM_185:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(277)
);
PPM_186:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(293)
);
PPM_187:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(311)
);
PPM_188:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(329)
);
PPM_189:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(346)
);
PPM_190:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(362)
);
PPM_191:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(378)
);
PPM_192:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(393)
);
PPM_193:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(408)
);
PPM_194:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(422)
);
PPM_195:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(436)
);
PPM_196:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(449)
);
PPM_197:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(461)
);
SUMMAND(462) <= LOGIC_ONE;
PPH_5:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(20),TWONEG => INT_MULTIPLIER(21),ONEPOS => INT_MULTIPLIER(22),ONENEG => INT_MULTIPLIER(23),
PPBIT => SUMMAND(474)
);
-- Begin partial product 6
-- Begin decoder block 7
DEC_6:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(11),INB => OPB(12),INC => OPB(13),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27)
);
-- End decoder block 7
-- Begin partial product 7
PPL_6:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(54)
);
RGATE_6:R_GATE
port map
(
INA => OPB(11),INB => OPB(12),INC => OPB(13),
PPBIT => SUMMAND(55)
);
PPM_198:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(62)
);
PPM_199:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(69)
);
PPM_200:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(78)
);
PPM_201:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(86)
);
PPM_202:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(96)
);
PPM_203:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(105)
);
PPM_204:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(116)
);
PPM_205:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(126)
);
PPM_206:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(138)
);
PPM_207:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(149)
);
PPM_208:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(162)
);
PPM_209:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(174)
);
PPM_210:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(188)
);
PPM_211:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(201)
);
PPM_212:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(216)
);
PPM_213:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(230)
);
PPM_214:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(246)
);
PPM_215:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(261)
);
PPM_216:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(278)
);
PPM_217:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(294)
);
PPM_218:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(312)
);
PPM_219:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(330)
);
PPM_220:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(347)
);
PPM_221:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(363)
);
PPM_222:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(379)
);
PPM_223:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(394)
);
PPM_224:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(409)
);
PPM_225:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(423)
);
PPM_226:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(437)
);
PPM_227:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(450)
);
PPM_228:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(463)
);
PPM_229:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(475)
);
PPM_230:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(486)
);
SUMMAND(487) <= LOGIC_ONE;
PPH_6:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(24),TWONEG => INT_MULTIPLIER(25),ONEPOS => INT_MULTIPLIER(26),ONENEG => INT_MULTIPLIER(27),
PPBIT => SUMMAND(498)
);
-- Begin partial product 7
-- Begin decoder block 8
DEC_7:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(13),INB => OPB(14),INC => OPB(15),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31)
);
-- End decoder block 8
-- Begin partial product 8
PPL_7:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(70)
);
RGATE_7:R_GATE
port map
(
INA => OPB(13),INB => OPB(14),INC => OPB(15),
PPBIT => SUMMAND(71)
);
PPM_231:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(79)
);
PPM_232:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(87)
);
PPM_233:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(97)
);
PPM_234:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(106)
);
PPM_235:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(117)
);
PPM_236:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(127)
);
PPM_237:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(139)
);
PPM_238:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(150)
);
PPM_239:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(163)
);
PPM_240:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(175)
);
PPM_241:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(189)
);
PPM_242:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(202)
);
PPM_243:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(217)
);
PPM_244:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(231)
);
PPM_245:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(247)
);
PPM_246:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(262)
);
PPM_247:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(279)
);
PPM_248:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(295)
);
PPM_249:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(313)
);
PPM_250:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(331)
);
PPM_251:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(348)
);
PPM_252:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(364)
);
PPM_253:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(380)
);
PPM_254:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(395)
);
PPM_255:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(410)
);
PPM_256:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(424)
);
PPM_257:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(438)
);
PPM_258:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(451)
);
PPM_259:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(464)
);
PPM_260:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(476)
);
PPM_261:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(488)
);
PPM_262:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(499)
);
PPM_263:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(509)
);
SUMMAND(510) <= LOGIC_ONE;
PPH_7:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(28),TWONEG => INT_MULTIPLIER(29),ONEPOS => INT_MULTIPLIER(30),ONENEG => INT_MULTIPLIER(31),
PPBIT => SUMMAND(520)
);
-- Begin partial product 8
-- Begin decoder block 9
DEC_8:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(15),INB => OPB(16),INC => OPB(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35)
);
-- End decoder block 9
-- Begin partial product 9
PPL_8:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(88)
);
RGATE_8:R_GATE
port map
(
INA => OPB(15),INB => OPB(16),INC => OPB(17),
PPBIT => SUMMAND(89)
);
PPM_264:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(98)
);
PPM_265:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(107)
);
PPM_266:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(118)
);
PPM_267:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(128)
);
PPM_268:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(140)
);
PPM_269:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(151)
);
PPM_270:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(164)
);
PPM_271:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(176)
);
PPM_272:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(190)
);
PPM_273:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(203)
);
PPM_274:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(218)
);
PPM_275:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(232)
);
PPM_276:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(248)
);
PPM_277:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(263)
);
PPM_278:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(280)
);
PPM_279:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(296)
);
PPM_280:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(314)
);
PPM_281:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(332)
);
PPM_282:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(349)
);
PPM_283:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(365)
);
PPM_284:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(381)
);
PPM_285:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(396)
);
PPM_286:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(411)
);
PPM_287:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(425)
);
PPM_288:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(439)
);
PPM_289:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(452)
);
PPM_290:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(465)
);
PPM_291:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(477)
);
PPM_292:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(489)
);
PPM_293:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(500)
);
PPM_294:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(511)
);
PPM_295:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(521)
);
PPM_296:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(530)
);
SUMMAND(531) <= LOGIC_ONE;
PPH_8:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(32),TWONEG => INT_MULTIPLIER(33),ONEPOS => INT_MULTIPLIER(34),ONENEG => INT_MULTIPLIER(35),
PPBIT => SUMMAND(540)
);
-- Begin partial product 9
-- Begin decoder block 10
DEC_9:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(17),INB => OPB(18),INC => OPB(19),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39)
);
-- End decoder block 10
-- Begin partial product 10
PPL_9:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(108)
);
RGATE_9:R_GATE
port map
(
INA => OPB(17),INB => OPB(18),INC => OPB(19),
PPBIT => SUMMAND(109)
);
PPM_297:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(119)
);
PPM_298:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(129)
);
PPM_299:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(141)
);
PPM_300:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(152)
);
PPM_301:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(165)
);
PPM_302:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(177)
);
PPM_303:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(191)
);
PPM_304:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(204)
);
PPM_305:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(219)
);
PPM_306:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(233)
);
PPM_307:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(249)
);
PPM_308:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(264)
);
PPM_309:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(281)
);
PPM_310:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(297)
);
PPM_311:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(315)
);
PPM_312:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(333)
);
PPM_313:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(350)
);
PPM_314:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(366)
);
PPM_315:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(382)
);
PPM_316:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(397)
);
PPM_317:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(412)
);
PPM_318:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(426)
);
PPM_319:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(440)
);
PPM_320:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(453)
);
PPM_321:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(466)
);
PPM_322:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(478)
);
PPM_323:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(490)
);
PPM_324:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(501)
);
PPM_325:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(512)
);
PPM_326:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(522)
);
PPM_327:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(532)
);
PPM_328:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(541)
);
PPM_329:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(549)
);
SUMMAND(550) <= LOGIC_ONE;
PPH_9:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(36),TWONEG => INT_MULTIPLIER(37),ONEPOS => INT_MULTIPLIER(38),ONENEG => INT_MULTIPLIER(39),
PPBIT => SUMMAND(558)
);
-- Begin partial product 10
-- Begin decoder block 11
DEC_10:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(19),INB => OPB(20),INC => OPB(21),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43)
);
-- End decoder block 11
-- Begin partial product 11
PPL_10:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(130)
);
RGATE_10:R_GATE
port map
(
INA => OPB(19),INB => OPB(20),INC => OPB(21),
PPBIT => SUMMAND(131)
);
PPM_330:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(142)
);
PPM_331:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(153)
);
PPM_332:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(166)
);
PPM_333:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(178)
);
PPM_334:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(192)
);
PPM_335:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(205)
);
PPM_336:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(220)
);
PPM_337:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(234)
);
PPM_338:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(250)
);
PPM_339:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(265)
);
PPM_340:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(282)
);
PPM_341:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(298)
);
PPM_342:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(316)
);
PPM_343:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(334)
);
PPM_344:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(351)
);
PPM_345:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(367)
);
PPM_346:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(383)
);
PPM_347:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(398)
);
PPM_348:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(413)
);
PPM_349:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(427)
);
PPM_350:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(441)
);
PPM_351:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(454)
);
PPM_352:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(467)
);
PPM_353:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(479)
);
PPM_354:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(491)
);
PPM_355:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(502)
);
PPM_356:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(513)
);
PPM_357:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(523)
);
PPM_358:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(533)
);
PPM_359:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(542)
);
PPM_360:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(551)
);
PPM_361:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(559)
);
PPM_362:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(566)
);
SUMMAND(567) <= LOGIC_ONE;
PPH_10:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(40),TWONEG => INT_MULTIPLIER(41),ONEPOS => INT_MULTIPLIER(42),ONENEG => INT_MULTIPLIER(43),
PPBIT => SUMMAND(574)
);
-- Begin partial product 11
-- Begin decoder block 12
DEC_11:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(21),INB => OPB(22),INC => OPB(23),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47)
);
-- End decoder block 12
-- Begin partial product 12
PPL_11:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(154)
);
RGATE_11:R_GATE
port map
(
INA => OPB(21),INB => OPB(22),INC => OPB(23),
PPBIT => SUMMAND(155)
);
PPM_363:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(167)
);
PPM_364:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(179)
);
PPM_365:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(193)
);
PPM_366:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(206)
);
PPM_367:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(221)
);
PPM_368:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(235)
);
PPM_369:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(251)
);
PPM_370:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(266)
);
PPM_371:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(283)
);
PPM_372:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(299)
);
PPM_373:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(317)
);
PPM_374:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(335)
);
PPM_375:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(352)
);
PPM_376:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(368)
);
PPM_377:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(384)
);
PPM_378:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(399)
);
PPM_379:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(414)
);
PPM_380:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(428)
);
PPM_381:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(442)
);
PPM_382:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(455)
);
PPM_383:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(468)
);
PPM_384:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(480)
);
PPM_385:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(492)
);
PPM_386:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(503)
);
PPM_387:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(514)
);
PPM_388:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(524)
);
PPM_389:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(534)
);
PPM_390:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(543)
);
PPM_391:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(552)
);
PPM_392:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(560)
);
PPM_393:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(568)
);
PPM_394:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(575)
);
PPM_395:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(581)
);
SUMMAND(582) <= LOGIC_ONE;
PPH_11:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(44),TWONEG => INT_MULTIPLIER(45),ONEPOS => INT_MULTIPLIER(46),ONENEG => INT_MULTIPLIER(47),
PPBIT => SUMMAND(588)
);
-- Begin partial product 12
-- Begin decoder block 13
DEC_12:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(23),INB => OPB(24),INC => OPB(25),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51)
);
-- End decoder block 13
-- Begin partial product 13
PPL_12:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(180)
);
RGATE_12:R_GATE
port map
(
INA => OPB(23),INB => OPB(24),INC => OPB(25),
PPBIT => SUMMAND(181)
);
PPM_396:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(194)
);
PPM_397:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(207)
);
PPM_398:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(222)
);
PPM_399:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(236)
);
PPM_400:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(252)
);
PPM_401:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(267)
);
PPM_402:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(284)
);
PPM_403:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(300)
);
PPM_404:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(318)
);
PPM_405:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(336)
);
PPM_406:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(353)
);
PPM_407:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(369)
);
PPM_408:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(385)
);
PPM_409:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(400)
);
PPM_410:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(415)
);
PPM_411:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(429)
);
PPM_412:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(443)
);
PPM_413:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(456)
);
PPM_414:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(469)
);
PPM_415:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(481)
);
PPM_416:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(493)
);
PPM_417:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(504)
);
PPM_418:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(515)
);
PPM_419:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(525)
);
PPM_420:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(535)
);
PPM_421:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(544)
);
PPM_422:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(553)
);
PPM_423:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(561)
);
PPM_424:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(569)
);
PPM_425:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(576)
);
PPM_426:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(583)
);
PPM_427:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(589)
);
PPM_428:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(594)
);
SUMMAND(595) <= LOGIC_ONE;
PPH_12:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(48),TWONEG => INT_MULTIPLIER(49),ONEPOS => INT_MULTIPLIER(50),ONENEG => INT_MULTIPLIER(51),
PPBIT => SUMMAND(600)
);
-- Begin partial product 13
-- Begin decoder block 14
DEC_13:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(25),INB => OPB(26),INC => OPB(27),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55)
);
-- End decoder block 14
-- Begin partial product 14
PPL_13:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(208)
);
RGATE_13:R_GATE
port map
(
INA => OPB(25),INB => OPB(26),INC => OPB(27),
PPBIT => SUMMAND(209)
);
PPM_429:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(223)
);
PPM_430:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(237)
);
PPM_431:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(253)
);
PPM_432:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(268)
);
PPM_433:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(285)
);
PPM_434:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(301)
);
PPM_435:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(319)
);
PPM_436:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(337)
);
PPM_437:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(354)
);
PPM_438:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(370)
);
PPM_439:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(386)
);
PPM_440:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(401)
);
PPM_441:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(416)
);
PPM_442:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(430)
);
PPM_443:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(444)
);
PPM_444:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(457)
);
PPM_445:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(470)
);
PPM_446:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(482)
);
PPM_447:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(494)
);
PPM_448:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(505)
);
PPM_449:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(516)
);
PPM_450:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(526)
);
PPM_451:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(536)
);
PPM_452:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(545)
);
PPM_453:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(554)
);
PPM_454:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(562)
);
PPM_455:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(570)
);
PPM_456:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(577)
);
PPM_457:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(584)
);
PPM_458:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(590)
);
PPM_459:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(596)
);
PPM_460:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(601)
);
PPM_461:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(605)
);
SUMMAND(606) <= LOGIC_ONE;
PPH_13:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(52),TWONEG => INT_MULTIPLIER(53),ONEPOS => INT_MULTIPLIER(54),ONENEG => INT_MULTIPLIER(55),
PPBIT => SUMMAND(610)
);
-- Begin partial product 14
-- Begin decoder block 15
DEC_14:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(27),INB => OPB(28),INC => OPB(29),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59)
);
-- End decoder block 15
-- Begin partial product 15
PPL_14:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(238)
);
RGATE_14:R_GATE
port map
(
INA => OPB(27),INB => OPB(28),INC => OPB(29),
PPBIT => SUMMAND(239)
);
PPM_462:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(254)
);
PPM_463:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(269)
);
PPM_464:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(286)
);
PPM_465:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(302)
);
PPM_466:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(320)
);
PPM_467:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(338)
);
PPM_468:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(355)
);
PPM_469:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(371)
);
PPM_470:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(387)
);
PPM_471:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(402)
);
PPM_472:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(417)
);
PPM_473:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(431)
);
PPM_474:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(445)
);
PPM_475:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(458)
);
PPM_476:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(471)
);
PPM_477:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(483)
);
PPM_478:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(495)
);
PPM_479:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(506)
);
PPM_480:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(517)
);
PPM_481:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(527)
);
PPM_482:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(537)
);
PPM_483:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(546)
);
PPM_484:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(555)
);
PPM_485:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(563)
);
PPM_486:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(571)
);
PPM_487:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(578)
);
PPM_488:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(585)
);
PPM_489:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(591)
);
PPM_490:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(597)
);
PPM_491:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(602)
);
PPM_492:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(607)
);
PPM_493:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(611)
);
PPM_494:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(614)
);
SUMMAND(615) <= LOGIC_ONE;
PPH_14:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(56),TWONEG => INT_MULTIPLIER(57),ONEPOS => INT_MULTIPLIER(58),ONENEG => INT_MULTIPLIER(59),
PPBIT => SUMMAND(618)
);
-- Begin partial product 15
-- Begin decoder block 16
DEC_15:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(29),INB => OPB(30),INC => OPB(31),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63)
);
-- End decoder block 16
-- Begin partial product 16
PPL_15:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(270)
);
RGATE_15:R_GATE
port map
(
INA => OPB(29),INB => OPB(30),INC => OPB(31),
PPBIT => SUMMAND(271)
);
PPM_495:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(287)
);
PPM_496:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(303)
);
PPM_497:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(321)
);
PPM_498:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(339)
);
PPM_499:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(356)
);
PPM_500:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(372)
);
PPM_501:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(388)
);
PPM_502:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(403)
);
PPM_503:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(418)
);
PPM_504:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(432)
);
PPM_505:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(446)
);
PPM_506:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(459)
);
PPM_507:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(472)
);
PPM_508:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(484)
);
PPM_509:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(496)
);
PPM_510:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(507)
);
PPM_511:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(518)
);
PPM_512:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(528)
);
PPM_513:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(538)
);
PPM_514:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(547)
);
PPM_515:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(556)
);
PPM_516:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(564)
);
PPM_517:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(572)
);
PPM_518:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(579)
);
PPM_519:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(586)
);
PPM_520:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(592)
);
PPM_521:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(598)
);
PPM_522:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(603)
);
PPM_523:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(608)
);
PPM_524:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(612)
);
PPM_525:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(616)
);
PPM_526:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(619)
);
PPM_527:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(621)
);
SUMMAND(622) <= LOGIC_ONE;
PPH_15:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(60),TWONEG => INT_MULTIPLIER(61),ONEPOS => INT_MULTIPLIER(62),ONENEG => INT_MULTIPLIER(63),
PPBIT => SUMMAND(624)
);
-- Begin partial product 16
-- Begin decoder block 17
DEC_16:DECODER -- Decoder of multiplier operand
port map
(
INA => OPB(31),INB => OPB(32),INC => OPB(33),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67)
);
-- End decoder block 17
-- Begin partial product 17
PPL_16:PP_LOW
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(304)
);
RGATE_16:R_GATE
port map
(
INA => OPB(31),INB => OPB(32),INC => OPB(33),
PPBIT => SUMMAND(305)
);
PPM_528:PP_MIDDLE
port map
(
INA => OPA(0),INB => INV_MULTIPLICAND(0),
INC => OPA(1),IND => INV_MULTIPLICAND(1),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(322)
);
PPM_529:PP_MIDDLE
port map
(
INA => OPA(1),INB => INV_MULTIPLICAND(1),
INC => OPA(2),IND => INV_MULTIPLICAND(2),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(340)
);
PPM_530:PP_MIDDLE
port map
(
INA => OPA(2),INB => INV_MULTIPLICAND(2),
INC => OPA(3),IND => INV_MULTIPLICAND(3),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(357)
);
PPM_531:PP_MIDDLE
port map
(
INA => OPA(3),INB => INV_MULTIPLICAND(3),
INC => OPA(4),IND => INV_MULTIPLICAND(4),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(373)
);
PPM_532:PP_MIDDLE
port map
(
INA => OPA(4),INB => INV_MULTIPLICAND(4),
INC => OPA(5),IND => INV_MULTIPLICAND(5),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(389)
);
PPM_533:PP_MIDDLE
port map
(
INA => OPA(5),INB => INV_MULTIPLICAND(5),
INC => OPA(6),IND => INV_MULTIPLICAND(6),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(404)
);
PPM_534:PP_MIDDLE
port map
(
INA => OPA(6),INB => INV_MULTIPLICAND(6),
INC => OPA(7),IND => INV_MULTIPLICAND(7),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(419)
);
PPM_535:PP_MIDDLE
port map
(
INA => OPA(7),INB => INV_MULTIPLICAND(7),
INC => OPA(8),IND => INV_MULTIPLICAND(8),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(433)
);
PPM_536:PP_MIDDLE
port map
(
INA => OPA(8),INB => INV_MULTIPLICAND(8),
INC => OPA(9),IND => INV_MULTIPLICAND(9),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(447)
);
PPM_537:PP_MIDDLE
port map
(
INA => OPA(9),INB => INV_MULTIPLICAND(9),
INC => OPA(10),IND => INV_MULTIPLICAND(10),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(460)
);
PPM_538:PP_MIDDLE
port map
(
INA => OPA(10),INB => INV_MULTIPLICAND(10),
INC => OPA(11),IND => INV_MULTIPLICAND(11),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(473)
);
PPM_539:PP_MIDDLE
port map
(
INA => OPA(11),INB => INV_MULTIPLICAND(11),
INC => OPA(12),IND => INV_MULTIPLICAND(12),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(485)
);
PPM_540:PP_MIDDLE
port map
(
INA => OPA(12),INB => INV_MULTIPLICAND(12),
INC => OPA(13),IND => INV_MULTIPLICAND(13),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(497)
);
PPM_541:PP_MIDDLE
port map
(
INA => OPA(13),INB => INV_MULTIPLICAND(13),
INC => OPA(14),IND => INV_MULTIPLICAND(14),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(508)
);
PPM_542:PP_MIDDLE
port map
(
INA => OPA(14),INB => INV_MULTIPLICAND(14),
INC => OPA(15),IND => INV_MULTIPLICAND(15),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(519)
);
PPM_543:PP_MIDDLE
port map
(
INA => OPA(15),INB => INV_MULTIPLICAND(15),
INC => OPA(16),IND => INV_MULTIPLICAND(16),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(529)
);
PPM_544:PP_MIDDLE
port map
(
INA => OPA(16),INB => INV_MULTIPLICAND(16),
INC => OPA(17),IND => INV_MULTIPLICAND(17),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(539)
);
PPM_545:PP_MIDDLE
port map
(
INA => OPA(17),INB => INV_MULTIPLICAND(17),
INC => OPA(18),IND => INV_MULTIPLICAND(18),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(548)
);
PPM_546:PP_MIDDLE
port map
(
INA => OPA(18),INB => INV_MULTIPLICAND(18),
INC => OPA(19),IND => INV_MULTIPLICAND(19),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(557)
);
PPM_547:PP_MIDDLE
port map
(
INA => OPA(19),INB => INV_MULTIPLICAND(19),
INC => OPA(20),IND => INV_MULTIPLICAND(20),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(565)
);
PPM_548:PP_MIDDLE
port map
(
INA => OPA(20),INB => INV_MULTIPLICAND(20),
INC => OPA(21),IND => INV_MULTIPLICAND(21),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(573)
);
PPM_549:PP_MIDDLE
port map
(
INA => OPA(21),INB => INV_MULTIPLICAND(21),
INC => OPA(22),IND => INV_MULTIPLICAND(22),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(580)
);
PPM_550:PP_MIDDLE
port map
(
INA => OPA(22),INB => INV_MULTIPLICAND(22),
INC => OPA(23),IND => INV_MULTIPLICAND(23),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(587)
);
PPM_551:PP_MIDDLE
port map
(
INA => OPA(23),INB => INV_MULTIPLICAND(23),
INC => OPA(24),IND => INV_MULTIPLICAND(24),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(593)
);
PPM_552:PP_MIDDLE
port map
(
INA => OPA(24),INB => INV_MULTIPLICAND(24),
INC => OPA(25),IND => INV_MULTIPLICAND(25),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(599)
);
PPM_553:PP_MIDDLE
port map
(
INA => OPA(25),INB => INV_MULTIPLICAND(25),
INC => OPA(26),IND => INV_MULTIPLICAND(26),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(604)
);
PPM_554:PP_MIDDLE
port map
(
INA => OPA(26),INB => INV_MULTIPLICAND(26),
INC => OPA(27),IND => INV_MULTIPLICAND(27),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(609)
);
PPM_555:PP_MIDDLE
port map
(
INA => OPA(27),INB => INV_MULTIPLICAND(27),
INC => OPA(28),IND => INV_MULTIPLICAND(28),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(613)
);
PPM_556:PP_MIDDLE
port map
(
INA => OPA(28),INB => INV_MULTIPLICAND(28),
INC => OPA(29),IND => INV_MULTIPLICAND(29),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(617)
);
PPM_557:PP_MIDDLE
port map
(
INA => OPA(29),INB => INV_MULTIPLICAND(29),
INC => OPA(30),IND => INV_MULTIPLICAND(30),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(620)
);
PPM_558:PP_MIDDLE
port map
(
INA => OPA(30),INB => INV_MULTIPLICAND(30),
INC => OPA(31),IND => INV_MULTIPLICAND(31),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(623)
);
PPM_559:PP_MIDDLE
port map
(
INA => OPA(31),INB => INV_MULTIPLICAND(31),
INC => OPA(32),IND => INV_MULTIPLICAND(32),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(625)
);
PPM_560:PP_MIDDLE
port map
(
INA => OPA(32),INB => INV_MULTIPLICAND(32),
INC => OPA(33),IND => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(626)
);
SUMMAND(627) <= LOGIC_ONE;
PPH_16:PP_HIGH
port map
(
INA => OPA(33),INB => INV_MULTIPLICAND(33),
TWOPOS => INT_MULTIPLIER(64),TWONEG => INT_MULTIPLIER(65),ONEPOS => INT_MULTIPLIER(66),ONENEG => INT_MULTIPLIER(67),
PPBIT => SUMMAND(628)
);
-- Begin partial product 17
end BOOTHCODER;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity WALLACE_34_34 is
port
(
SUMMAND: in std_logic_vector(0 to 628);
CARRY: out std_logic_vector(0 to 65);
SUM: out std_logic_vector(0 to 66)
);
end WALLACE_34_34;
architecture WALLACE of WALLACE_34_34 is
-- Signals used inside the wallace trees
signal INT_CARRY: std_logic_vector(0 to 486);
signal INT_SUM: std_logic_vector(0 to 620);
begin -- netlist
-- Begin WT-branch 1
---- Begin HA stage
HA_0:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(0), DATA_B => SUMMAND(1),
SAVE => SUM(0), CARRY => CARRY(0)
);
---- End HA stage
-- End WT-branch 1
-- Begin WT-branch 2
---- Begin NO stage
SUM(1) <= SUMMAND(2); -- At Level 1
CARRY(1) <= '0';
---- End NO stage
-- End WT-branch 2
-- Begin WT-branch 3
---- Begin FA stage
FA_0:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(3), DATA_B => SUMMAND(4), DATA_C => SUMMAND(5),
SAVE => SUM(2), CARRY => CARRY(2)
);
---- End FA stage
-- End WT-branch 3
-- Begin WT-branch 4
---- Begin HA stage
HA_1:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(6), DATA_B => SUMMAND(7),
SAVE => SUM(3), CARRY => CARRY(3)
);
---- End HA stage
-- End WT-branch 4
-- Begin WT-branch 5
---- Begin FA stage
FA_1:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(8), DATA_B => SUMMAND(9), DATA_C => SUMMAND(10),
SAVE => INT_SUM(0), CARRY => INT_CARRY(0)
);
---- End FA stage
---- Begin NO stage
INT_SUM(1) <= SUMMAND(11); -- At Level 1
---- End NO stage
---- Begin HA stage
HA_2:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(0), DATA_B => INT_SUM(1),
SAVE => SUM(4), CARRY => CARRY(4)
);
---- End HA stage
-- End WT-branch 5
-- Begin WT-branch 6
---- Begin FA stage
FA_2:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(12), DATA_B => SUMMAND(13), DATA_C => SUMMAND(14),
SAVE => INT_SUM(2), CARRY => INT_CARRY(1)
);
---- End FA stage
---- Begin HA stage
HA_3:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(2), DATA_B => INT_CARRY(0),
SAVE => SUM(5), CARRY => CARRY(5)
);
---- End HA stage
-- End WT-branch 6
-- Begin WT-branch 7
---- Begin FA stage
FA_3:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(15), DATA_B => SUMMAND(16), DATA_C => SUMMAND(17),
SAVE => INT_SUM(3), CARRY => INT_CARRY(2)
);
---- End FA stage
---- Begin HA stage
HA_4:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(18), DATA_B => SUMMAND(19),
SAVE => INT_SUM(4), CARRY => INT_CARRY(3)
);
---- End HA stage
---- Begin FA stage
FA_4:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(3), DATA_B => INT_SUM(4), DATA_C => INT_CARRY(1),
SAVE => SUM(6), CARRY => CARRY(6)
);
---- End FA stage
-- End WT-branch 7
-- Begin WT-branch 8
---- Begin FA stage
FA_5:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(20), DATA_B => SUMMAND(21), DATA_C => SUMMAND(22),
SAVE => INT_SUM(5), CARRY => INT_CARRY(4)
);
---- End FA stage
---- Begin NO stage
INT_SUM(6) <= SUMMAND(23); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_6:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(5), DATA_B => INT_SUM(6), DATA_C => INT_CARRY(2),
SAVE => INT_SUM(7), CARRY => INT_CARRY(5)
);
---- End FA stage
---- Begin NO stage
INT_SUM(8) <= INT_CARRY(3); -- At Level 2
---- End NO stage
---- Begin HA stage
HA_5:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(7), DATA_B => INT_SUM(8),
SAVE => SUM(7), CARRY => CARRY(7)
);
---- End HA stage
-- End WT-branch 8
-- Begin WT-branch 9
---- Begin FA stage
FA_7:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(24), DATA_B => SUMMAND(25), DATA_C => SUMMAND(26),
SAVE => INT_SUM(9), CARRY => INT_CARRY(6)
);
---- End FA stage
---- Begin FA stage
FA_8:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(27), DATA_B => SUMMAND(28), DATA_C => SUMMAND(29),
SAVE => INT_SUM(10), CARRY => INT_CARRY(7)
);
---- End FA stage
---- Begin FA stage
FA_9:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(9), DATA_B => INT_SUM(10), DATA_C => INT_CARRY(4),
SAVE => INT_SUM(11), CARRY => INT_CARRY(8)
);
---- End FA stage
---- Begin HA stage
HA_6:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(11), DATA_B => INT_CARRY(5),
SAVE => SUM(8), CARRY => CARRY(8)
);
---- End HA stage
-- End WT-branch 9
-- Begin WT-branch 10
---- Begin FA stage
FA_10:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(30), DATA_B => SUMMAND(31), DATA_C => SUMMAND(32),
SAVE => INT_SUM(12), CARRY => INT_CARRY(9)
);
---- End FA stage
---- Begin HA stage
HA_7:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(33), DATA_B => SUMMAND(34),
SAVE => INT_SUM(13), CARRY => INT_CARRY(10)
);
---- End HA stage
---- Begin FA stage
FA_11:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(12), DATA_B => INT_SUM(13), DATA_C => INT_CARRY(6),
SAVE => INT_SUM(14), CARRY => INT_CARRY(11)
);
---- End FA stage
---- Begin NO stage
INT_SUM(15) <= INT_CARRY(7); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_12:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(14), DATA_B => INT_SUM(15), DATA_C => INT_CARRY(8),
SAVE => SUM(9), CARRY => CARRY(9)
);
---- End FA stage
-- End WT-branch 10
-- Begin WT-branch 11
---- Begin FA stage
FA_13:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(35), DATA_B => SUMMAND(36), DATA_C => SUMMAND(37),
SAVE => INT_SUM(16), CARRY => INT_CARRY(12)
);
---- End FA stage
---- Begin FA stage
FA_14:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(38), DATA_B => SUMMAND(39), DATA_C => SUMMAND(40),
SAVE => INT_SUM(17), CARRY => INT_CARRY(13)
);
---- End FA stage
---- Begin NO stage
INT_SUM(18) <= SUMMAND(41); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_15:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(16), DATA_B => INT_SUM(17), DATA_C => INT_SUM(18),
SAVE => INT_SUM(19), CARRY => INT_CARRY(14)
);
---- End FA stage
---- Begin HA stage
HA_8:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(9), DATA_B => INT_CARRY(10),
SAVE => INT_SUM(20), CARRY => INT_CARRY(15)
);
---- End HA stage
---- Begin FA stage
FA_16:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(19), DATA_B => INT_SUM(20), DATA_C => INT_CARRY(11),
SAVE => SUM(10), CARRY => CARRY(10)
);
---- End FA stage
-- End WT-branch 11
-- Begin WT-branch 12
---- Begin FA stage
FA_17:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(42), DATA_B => SUMMAND(43), DATA_C => SUMMAND(44),
SAVE => INT_SUM(21), CARRY => INT_CARRY(16)
);
---- End FA stage
---- Begin FA stage
FA_18:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(45), DATA_B => SUMMAND(46), DATA_C => SUMMAND(47),
SAVE => INT_SUM(22), CARRY => INT_CARRY(17)
);
---- End FA stage
---- Begin FA stage
FA_19:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(21), DATA_B => INT_SUM(22), DATA_C => INT_CARRY(12),
SAVE => INT_SUM(23), CARRY => INT_CARRY(18)
);
---- End FA stage
---- Begin NO stage
INT_SUM(24) <= INT_CARRY(13); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_20:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(23), DATA_B => INT_SUM(24), DATA_C => INT_CARRY(14),
SAVE => INT_SUM(25), CARRY => INT_CARRY(19)
);
---- End FA stage
---- Begin NO stage
INT_SUM(26) <= INT_CARRY(15); -- At Level 3
---- End NO stage
---- Begin HA stage
HA_9:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(25), DATA_B => INT_SUM(26),
SAVE => SUM(11), CARRY => CARRY(11)
);
---- End HA stage
-- End WT-branch 12
-- Begin WT-branch 13
---- Begin FA stage
FA_21:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(48), DATA_B => SUMMAND(49), DATA_C => SUMMAND(50),
SAVE => INT_SUM(27), CARRY => INT_CARRY(20)
);
---- End FA stage
---- Begin FA stage
FA_22:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(51), DATA_B => SUMMAND(52), DATA_C => SUMMAND(53),
SAVE => INT_SUM(28), CARRY => INT_CARRY(21)
);
---- End FA stage
---- Begin NO stage
INT_SUM(29) <= SUMMAND(54); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(30) <= SUMMAND(55); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_23:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(27), DATA_B => INT_SUM(28), DATA_C => INT_SUM(29),
SAVE => INT_SUM(31), CARRY => INT_CARRY(22)
);
---- End FA stage
---- Begin FA stage
FA_24:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(30), DATA_B => INT_CARRY(16), DATA_C => INT_CARRY(17),
SAVE => INT_SUM(32), CARRY => INT_CARRY(23)
);
---- End FA stage
---- Begin FA stage
FA_25:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(31), DATA_B => INT_SUM(32), DATA_C => INT_CARRY(18),
SAVE => INT_SUM(33), CARRY => INT_CARRY(24)
);
---- End FA stage
---- Begin HA stage
HA_10:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(33), DATA_B => INT_CARRY(19),
SAVE => SUM(12), CARRY => CARRY(12)
);
---- End HA stage
-- End WT-branch 13
-- Begin WT-branch 14
---- Begin FA stage
FA_26:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(56), DATA_B => SUMMAND(57), DATA_C => SUMMAND(58),
SAVE => INT_SUM(34), CARRY => INT_CARRY(25)
);
---- End FA stage
---- Begin FA stage
FA_27:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(59), DATA_B => SUMMAND(60), DATA_C => SUMMAND(61),
SAVE => INT_SUM(35), CARRY => INT_CARRY(26)
);
---- End FA stage
---- Begin NO stage
INT_SUM(36) <= SUMMAND(62); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_28:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(34), DATA_B => INT_SUM(35), DATA_C => INT_SUM(36),
SAVE => INT_SUM(37), CARRY => INT_CARRY(27)
);
---- End FA stage
---- Begin HA stage
HA_11:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(20), DATA_B => INT_CARRY(21),
SAVE => INT_SUM(38), CARRY => INT_CARRY(28)
);
---- End HA stage
---- Begin FA stage
FA_29:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(37), DATA_B => INT_SUM(38), DATA_C => INT_CARRY(22),
SAVE => INT_SUM(39), CARRY => INT_CARRY(29)
);
---- End FA stage
---- Begin NO stage
INT_SUM(40) <= INT_CARRY(23); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_30:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(39), DATA_B => INT_SUM(40), DATA_C => INT_CARRY(24),
SAVE => SUM(13), CARRY => CARRY(13)
);
---- End FA stage
-- End WT-branch 14
-- Begin WT-branch 15
---- Begin FA stage
FA_31:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(63), DATA_B => SUMMAND(64), DATA_C => SUMMAND(65),
SAVE => INT_SUM(41), CARRY => INT_CARRY(30)
);
---- End FA stage
---- Begin FA stage
FA_32:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(66), DATA_B => SUMMAND(67), DATA_C => SUMMAND(68),
SAVE => INT_SUM(42), CARRY => INT_CARRY(31)
);
---- End FA stage
---- Begin FA stage
FA_33:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(69), DATA_B => SUMMAND(70), DATA_C => SUMMAND(71),
SAVE => INT_SUM(43), CARRY => INT_CARRY(32)
);
---- End FA stage
---- Begin FA stage
FA_34:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(41), DATA_B => INT_SUM(42), DATA_C => INT_SUM(43),
SAVE => INT_SUM(44), CARRY => INT_CARRY(33)
);
---- End FA stage
---- Begin HA stage
HA_12:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(25), DATA_B => INT_CARRY(26),
SAVE => INT_SUM(45), CARRY => INT_CARRY(34)
);
---- End HA stage
---- Begin FA stage
FA_35:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(44), DATA_B => INT_SUM(45), DATA_C => INT_CARRY(27),
SAVE => INT_SUM(46), CARRY => INT_CARRY(35)
);
---- End FA stage
---- Begin NO stage
INT_SUM(47) <= INT_CARRY(28); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_36:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(46), DATA_B => INT_SUM(47), DATA_C => INT_CARRY(29),
SAVE => SUM(14), CARRY => CARRY(14)
);
---- End FA stage
-- End WT-branch 15
-- Begin WT-branch 16
---- Begin FA stage
FA_37:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(72), DATA_B => SUMMAND(73), DATA_C => SUMMAND(74),
SAVE => INT_SUM(48), CARRY => INT_CARRY(36)
);
---- End FA stage
---- Begin FA stage
FA_38:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(75), DATA_B => SUMMAND(76), DATA_C => SUMMAND(77),
SAVE => INT_SUM(49), CARRY => INT_CARRY(37)
);
---- End FA stage
---- Begin HA stage
HA_13:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(78), DATA_B => SUMMAND(79),
SAVE => INT_SUM(50), CARRY => INT_CARRY(38)
);
---- End HA stage
---- Begin FA stage
FA_39:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(48), DATA_B => INT_SUM(49), DATA_C => INT_SUM(50),
SAVE => INT_SUM(51), CARRY => INT_CARRY(39)
);
---- End FA stage
---- Begin FA stage
FA_40:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(30), DATA_B => INT_CARRY(31), DATA_C => INT_CARRY(32),
SAVE => INT_SUM(52), CARRY => INT_CARRY(40)
);
---- End FA stage
---- Begin FA stage
FA_41:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(51), DATA_B => INT_SUM(52), DATA_C => INT_CARRY(33),
SAVE => INT_SUM(53), CARRY => INT_CARRY(41)
);
---- End FA stage
---- Begin NO stage
INT_SUM(54) <= INT_CARRY(34); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_42:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(53), DATA_B => INT_SUM(54), DATA_C => INT_CARRY(35),
SAVE => SUM(15), CARRY => CARRY(15)
);
---- End FA stage
-- End WT-branch 16
-- Begin WT-branch 17
---- Begin FA stage
FA_43:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(80), DATA_B => SUMMAND(81), DATA_C => SUMMAND(82),
SAVE => INT_SUM(55), CARRY => INT_CARRY(42)
);
---- End FA stage
---- Begin FA stage
FA_44:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(83), DATA_B => SUMMAND(84), DATA_C => SUMMAND(85),
SAVE => INT_SUM(56), CARRY => INT_CARRY(43)
);
---- End FA stage
---- Begin FA stage
FA_45:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(86), DATA_B => SUMMAND(87), DATA_C => SUMMAND(88),
SAVE => INT_SUM(57), CARRY => INT_CARRY(44)
);
---- End FA stage
---- Begin NO stage
INT_SUM(58) <= SUMMAND(89); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_46:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(55), DATA_B => INT_SUM(56), DATA_C => INT_SUM(57),
SAVE => INT_SUM(59), CARRY => INT_CARRY(45)
);
---- End FA stage
---- Begin FA stage
FA_47:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(58), DATA_B => INT_CARRY(36), DATA_C => INT_CARRY(37),
SAVE => INT_SUM(60), CARRY => INT_CARRY(46)
);
---- End FA stage
---- Begin NO stage
INT_SUM(61) <= INT_CARRY(38); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_48:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(59), DATA_B => INT_SUM(60), DATA_C => INT_SUM(61),
SAVE => INT_SUM(62), CARRY => INT_CARRY(47)
);
---- End FA stage
---- Begin HA stage
HA_14:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(39), DATA_B => INT_CARRY(40),
SAVE => INT_SUM(63), CARRY => INT_CARRY(48)
);
---- End HA stage
---- Begin FA stage
FA_49:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(62), DATA_B => INT_SUM(63), DATA_C => INT_CARRY(41),
SAVE => SUM(16), CARRY => CARRY(16)
);
---- End FA stage
-- End WT-branch 17
-- Begin WT-branch 18
---- Begin FA stage
FA_50:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(90), DATA_B => SUMMAND(91), DATA_C => SUMMAND(92),
SAVE => INT_SUM(64), CARRY => INT_CARRY(49)
);
---- End FA stage
---- Begin FA stage
FA_51:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(93), DATA_B => SUMMAND(94), DATA_C => SUMMAND(95),
SAVE => INT_SUM(65), CARRY => INT_CARRY(50)
);
---- End FA stage
---- Begin FA stage
FA_52:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(96), DATA_B => SUMMAND(97), DATA_C => SUMMAND(98),
SAVE => INT_SUM(66), CARRY => INT_CARRY(51)
);
---- End FA stage
---- Begin FA stage
FA_53:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(64), DATA_B => INT_SUM(65), DATA_C => INT_SUM(66),
SAVE => INT_SUM(67), CARRY => INT_CARRY(52)
);
---- End FA stage
---- Begin FA stage
FA_54:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(42), DATA_B => INT_CARRY(43), DATA_C => INT_CARRY(44),
SAVE => INT_SUM(68), CARRY => INT_CARRY(53)
);
---- End FA stage
---- Begin FA stage
FA_55:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(67), DATA_B => INT_SUM(68), DATA_C => INT_CARRY(45),
SAVE => INT_SUM(69), CARRY => INT_CARRY(54)
);
---- End FA stage
---- Begin NO stage
INT_SUM(70) <= INT_CARRY(46); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_56:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(69), DATA_B => INT_SUM(70), DATA_C => INT_CARRY(47),
SAVE => INT_SUM(71), CARRY => INT_CARRY(55)
);
---- End FA stage
---- Begin NO stage
INT_SUM(72) <= INT_CARRY(48); -- At Level 4
---- End NO stage
---- Begin HA stage
HA_15:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(71), DATA_B => INT_SUM(72),
SAVE => SUM(17), CARRY => CARRY(17)
);
---- End HA stage
-- End WT-branch 18
-- Begin WT-branch 19
---- Begin FA stage
FA_57:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(99), DATA_B => SUMMAND(100), DATA_C => SUMMAND(101),
SAVE => INT_SUM(73), CARRY => INT_CARRY(56)
);
---- End FA stage
---- Begin FA stage
FA_58:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(102), DATA_B => SUMMAND(103), DATA_C => SUMMAND(104),
SAVE => INT_SUM(74), CARRY => INT_CARRY(57)
);
---- End FA stage
---- Begin FA stage
FA_59:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(105), DATA_B => SUMMAND(106), DATA_C => SUMMAND(107),
SAVE => INT_SUM(75), CARRY => INT_CARRY(58)
);
---- End FA stage
---- Begin NO stage
INT_SUM(76) <= SUMMAND(108); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(77) <= SUMMAND(109); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_60:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(73), DATA_B => INT_SUM(74), DATA_C => INT_SUM(75),
SAVE => INT_SUM(78), CARRY => INT_CARRY(59)
);
---- End FA stage
---- Begin FA stage
FA_61:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(76), DATA_B => INT_SUM(77), DATA_C => INT_CARRY(49),
SAVE => INT_SUM(79), CARRY => INT_CARRY(60)
);
---- End FA stage
---- Begin NO stage
INT_SUM(80) <= INT_CARRY(50); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(81) <= INT_CARRY(51); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_62:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(78), DATA_B => INT_SUM(79), DATA_C => INT_SUM(80),
SAVE => INT_SUM(82), CARRY => INT_CARRY(61)
);
---- End FA stage
---- Begin FA stage
FA_63:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(81), DATA_B => INT_CARRY(52), DATA_C => INT_CARRY(53),
SAVE => INT_SUM(83), CARRY => INT_CARRY(62)
);
---- End FA stage
---- Begin FA stage
FA_64:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(82), DATA_B => INT_SUM(83), DATA_C => INT_CARRY(54),
SAVE => INT_SUM(84), CARRY => INT_CARRY(63)
);
---- End FA stage
---- Begin HA stage
HA_16:HALF_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(84), DATA_B => INT_CARRY(55),
SAVE => SUM(18), CARRY => CARRY(18)
);
---- End HA stage
-- End WT-branch 19
-- Begin WT-branch 20
---- Begin FA stage
FA_65:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(110), DATA_B => SUMMAND(111), DATA_C => SUMMAND(112),
SAVE => INT_SUM(85), CARRY => INT_CARRY(64)
);
---- End FA stage
---- Begin FA stage
FA_66:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(113), DATA_B => SUMMAND(114), DATA_C => SUMMAND(115),
SAVE => INT_SUM(86), CARRY => INT_CARRY(65)
);
---- End FA stage
---- Begin FA stage
FA_67:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(116), DATA_B => SUMMAND(117), DATA_C => SUMMAND(118),
SAVE => INT_SUM(87), CARRY => INT_CARRY(66)
);
---- End FA stage
---- Begin NO stage
INT_SUM(88) <= SUMMAND(119); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_68:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(85), DATA_B => INT_SUM(86), DATA_C => INT_SUM(87),
SAVE => INT_SUM(89), CARRY => INT_CARRY(67)
);
---- End FA stage
---- Begin FA stage
FA_69:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(88), DATA_B => INT_CARRY(56), DATA_C => INT_CARRY(57),
SAVE => INT_SUM(90), CARRY => INT_CARRY(68)
);
---- End FA stage
---- Begin NO stage
INT_SUM(91) <= INT_CARRY(58); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_70:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(89), DATA_B => INT_SUM(90), DATA_C => INT_SUM(91),
SAVE => INT_SUM(92), CARRY => INT_CARRY(69)
);
---- End FA stage
---- Begin HA stage
HA_17:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(59), DATA_B => INT_CARRY(60),
SAVE => INT_SUM(93), CARRY => INT_CARRY(70)
);
---- End HA stage
---- Begin FA stage
FA_71:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(92), DATA_B => INT_SUM(93), DATA_C => INT_CARRY(61),
SAVE => INT_SUM(94), CARRY => INT_CARRY(71)
);
---- End FA stage
---- Begin NO stage
INT_SUM(95) <= INT_CARRY(62); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_72:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(94), DATA_B => INT_SUM(95), DATA_C => INT_CARRY(63),
SAVE => SUM(19), CARRY => CARRY(19)
);
---- End FA stage
-- End WT-branch 20
-- Begin WT-branch 21
---- Begin FA stage
FA_73:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(120), DATA_B => SUMMAND(121), DATA_C => SUMMAND(122),
SAVE => INT_SUM(96), CARRY => INT_CARRY(72)
);
---- End FA stage
---- Begin FA stage
FA_74:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(123), DATA_B => SUMMAND(124), DATA_C => SUMMAND(125),
SAVE => INT_SUM(97), CARRY => INT_CARRY(73)
);
---- End FA stage
---- Begin FA stage
FA_75:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(126), DATA_B => SUMMAND(127), DATA_C => SUMMAND(128),
SAVE => INT_SUM(98), CARRY => INT_CARRY(74)
);
---- End FA stage
---- Begin FA stage
FA_76:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(129), DATA_B => SUMMAND(130), DATA_C => SUMMAND(131),
SAVE => INT_SUM(99), CARRY => INT_CARRY(75)
);
---- End FA stage
---- Begin FA stage
FA_77:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(96), DATA_B => INT_SUM(97), DATA_C => INT_SUM(98),
SAVE => INT_SUM(100), CARRY => INT_CARRY(76)
);
---- End FA stage
---- Begin FA stage
FA_78:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(99), DATA_B => INT_CARRY(64), DATA_C => INT_CARRY(65),
SAVE => INT_SUM(101), CARRY => INT_CARRY(77)
);
---- End FA stage
---- Begin NO stage
INT_SUM(102) <= INT_CARRY(66); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_79:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(100), DATA_B => INT_SUM(101), DATA_C => INT_SUM(102),
SAVE => INT_SUM(103), CARRY => INT_CARRY(78)
);
---- End FA stage
---- Begin HA stage
HA_18:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(67), DATA_B => INT_CARRY(68),
SAVE => INT_SUM(104), CARRY => INT_CARRY(79)
);
---- End HA stage
---- Begin FA stage
FA_80:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(103), DATA_B => INT_SUM(104), DATA_C => INT_CARRY(69),
SAVE => INT_SUM(105), CARRY => INT_CARRY(80)
);
---- End FA stage
---- Begin NO stage
INT_SUM(106) <= INT_CARRY(70); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_81:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(105), DATA_B => INT_SUM(106), DATA_C => INT_CARRY(71),
SAVE => SUM(20), CARRY => CARRY(20)
);
---- End FA stage
-- End WT-branch 21
-- Begin WT-branch 22
---- Begin FA stage
FA_82:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(132), DATA_B => SUMMAND(133), DATA_C => SUMMAND(134),
SAVE => INT_SUM(107), CARRY => INT_CARRY(81)
);
---- End FA stage
---- Begin FA stage
FA_83:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(135), DATA_B => SUMMAND(136), DATA_C => SUMMAND(137),
SAVE => INT_SUM(108), CARRY => INT_CARRY(82)
);
---- End FA stage
---- Begin FA stage
FA_84:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(138), DATA_B => SUMMAND(139), DATA_C => SUMMAND(140),
SAVE => INT_SUM(109), CARRY => INT_CARRY(83)
);
---- End FA stage
---- Begin NO stage
INT_SUM(110) <= SUMMAND(141); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(111) <= SUMMAND(142); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_85:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(107), DATA_B => INT_SUM(108), DATA_C => INT_SUM(109),
SAVE => INT_SUM(112), CARRY => INT_CARRY(84)
);
---- End FA stage
---- Begin FA stage
FA_86:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(110), DATA_B => INT_SUM(111), DATA_C => INT_CARRY(72),
SAVE => INT_SUM(113), CARRY => INT_CARRY(85)
);
---- End FA stage
---- Begin FA stage
FA_87:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(73), DATA_B => INT_CARRY(74), DATA_C => INT_CARRY(75),
SAVE => INT_SUM(114), CARRY => INT_CARRY(86)
);
---- End FA stage
---- Begin FA stage
FA_88:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(112), DATA_B => INT_SUM(113), DATA_C => INT_SUM(114),
SAVE => INT_SUM(115), CARRY => INT_CARRY(87)
);
---- End FA stage
---- Begin HA stage
HA_19:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(76), DATA_B => INT_CARRY(77),
SAVE => INT_SUM(116), CARRY => INT_CARRY(88)
);
---- End HA stage
---- Begin FA stage
FA_89:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(115), DATA_B => INT_SUM(116), DATA_C => INT_CARRY(78),
SAVE => INT_SUM(117), CARRY => INT_CARRY(89)
);
---- End FA stage
---- Begin NO stage
INT_SUM(118) <= INT_CARRY(79); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_90:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(117), DATA_B => INT_SUM(118), DATA_C => INT_CARRY(80),
SAVE => SUM(21), CARRY => CARRY(21)
);
---- End FA stage
-- End WT-branch 22
-- Begin WT-branch 23
---- Begin FA stage
FA_91:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(143), DATA_B => SUMMAND(144), DATA_C => SUMMAND(145),
SAVE => INT_SUM(119), CARRY => INT_CARRY(90)
);
---- End FA stage
---- Begin FA stage
FA_92:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(146), DATA_B => SUMMAND(147), DATA_C => SUMMAND(148),
SAVE => INT_SUM(120), CARRY => INT_CARRY(91)
);
---- End FA stage
---- Begin FA stage
FA_93:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(149), DATA_B => SUMMAND(150), DATA_C => SUMMAND(151),
SAVE => INT_SUM(121), CARRY => INT_CARRY(92)
);
---- End FA stage
---- Begin FA stage
FA_94:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(152), DATA_B => SUMMAND(153), DATA_C => SUMMAND(154),
SAVE => INT_SUM(122), CARRY => INT_CARRY(93)
);
---- End FA stage
---- Begin NO stage
INT_SUM(123) <= SUMMAND(155); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_95:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(119), DATA_B => INT_SUM(120), DATA_C => INT_SUM(121),
SAVE => INT_SUM(124), CARRY => INT_CARRY(94)
);
---- End FA stage
---- Begin FA stage
FA_96:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(122), DATA_B => INT_SUM(123), DATA_C => INT_CARRY(81),
SAVE => INT_SUM(125), CARRY => INT_CARRY(95)
);
---- End FA stage
---- Begin HA stage
HA_20:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(82), DATA_B => INT_CARRY(83),
SAVE => INT_SUM(126), CARRY => INT_CARRY(96)
);
---- End HA stage
---- Begin FA stage
FA_97:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(124), DATA_B => INT_SUM(125), DATA_C => INT_SUM(126),
SAVE => INT_SUM(127), CARRY => INT_CARRY(97)
);
---- End FA stage
---- Begin FA stage
FA_98:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(84), DATA_B => INT_CARRY(85), DATA_C => INT_CARRY(86),
SAVE => INT_SUM(128), CARRY => INT_CARRY(98)
);
---- End FA stage
---- Begin FA stage
FA_99:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(127), DATA_B => INT_SUM(128), DATA_C => INT_CARRY(87),
SAVE => INT_SUM(129), CARRY => INT_CARRY(99)
);
---- End FA stage
---- Begin NO stage
INT_SUM(130) <= INT_CARRY(88); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_100:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(129), DATA_B => INT_SUM(130), DATA_C => INT_CARRY(89),
SAVE => SUM(22), CARRY => CARRY(22)
);
---- End FA stage
-- End WT-branch 23
-- Begin WT-branch 24
---- Begin FA stage
FA_101:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(156), DATA_B => SUMMAND(157), DATA_C => SUMMAND(158),
SAVE => INT_SUM(131), CARRY => INT_CARRY(100)
);
---- End FA stage
---- Begin FA stage
FA_102:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(159), DATA_B => SUMMAND(160), DATA_C => SUMMAND(161),
SAVE => INT_SUM(132), CARRY => INT_CARRY(101)
);
---- End FA stage
---- Begin FA stage
FA_103:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(162), DATA_B => SUMMAND(163), DATA_C => SUMMAND(164),
SAVE => INT_SUM(133), CARRY => INT_CARRY(102)
);
---- End FA stage
---- Begin FA stage
FA_104:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(165), DATA_B => SUMMAND(166), DATA_C => SUMMAND(167),
SAVE => INT_SUM(134), CARRY => INT_CARRY(103)
);
---- End FA stage
---- Begin FA stage
FA_105:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(131), DATA_B => INT_SUM(132), DATA_C => INT_SUM(133),
SAVE => INT_SUM(135), CARRY => INT_CARRY(104)
);
---- End FA stage
---- Begin FA stage
FA_106:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(134), DATA_B => INT_CARRY(90), DATA_C => INT_CARRY(91),
SAVE => INT_SUM(136), CARRY => INT_CARRY(105)
);
---- End FA stage
---- Begin HA stage
HA_21:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(92), DATA_B => INT_CARRY(93),
SAVE => INT_SUM(137), CARRY => INT_CARRY(106)
);
---- End HA stage
---- Begin FA stage
FA_107:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(135), DATA_B => INT_SUM(136), DATA_C => INT_SUM(137),
SAVE => INT_SUM(138), CARRY => INT_CARRY(107)
);
---- End FA stage
---- Begin FA stage
FA_108:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(94), DATA_B => INT_CARRY(95), DATA_C => INT_CARRY(96),
SAVE => INT_SUM(139), CARRY => INT_CARRY(108)
);
---- End FA stage
---- Begin FA stage
FA_109:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(138), DATA_B => INT_SUM(139), DATA_C => INT_CARRY(97),
SAVE => INT_SUM(140), CARRY => INT_CARRY(109)
);
---- End FA stage
---- Begin NO stage
INT_SUM(141) <= INT_CARRY(98); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_110:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(140), DATA_B => INT_SUM(141), DATA_C => INT_CARRY(99),
SAVE => SUM(23), CARRY => CARRY(23)
);
---- End FA stage
-- End WT-branch 24
-- Begin WT-branch 25
---- Begin FA stage
FA_111:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(168), DATA_B => SUMMAND(169), DATA_C => SUMMAND(170),
SAVE => INT_SUM(142), CARRY => INT_CARRY(110)
);
---- End FA stage
---- Begin FA stage
FA_112:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(171), DATA_B => SUMMAND(172), DATA_C => SUMMAND(173),
SAVE => INT_SUM(143), CARRY => INT_CARRY(111)
);
---- End FA stage
---- Begin FA stage
FA_113:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(174), DATA_B => SUMMAND(175), DATA_C => SUMMAND(176),
SAVE => INT_SUM(144), CARRY => INT_CARRY(112)
);
---- End FA stage
---- Begin FA stage
FA_114:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(177), DATA_B => SUMMAND(178), DATA_C => SUMMAND(179),
SAVE => INT_SUM(145), CARRY => INT_CARRY(113)
);
---- End FA stage
---- Begin HA stage
HA_22:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(180), DATA_B => SUMMAND(181),
SAVE => INT_SUM(146), CARRY => INT_CARRY(114)
);
---- End HA stage
---- Begin FA stage
FA_115:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(142), DATA_B => INT_SUM(143), DATA_C => INT_SUM(144),
SAVE => INT_SUM(147), CARRY => INT_CARRY(115)
);
---- End FA stage
---- Begin FA stage
FA_116:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(145), DATA_B => INT_SUM(146), DATA_C => INT_CARRY(100),
SAVE => INT_SUM(148), CARRY => INT_CARRY(116)
);
---- End FA stage
---- Begin FA stage
FA_117:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(101), DATA_B => INT_CARRY(102), DATA_C => INT_CARRY(103),
SAVE => INT_SUM(149), CARRY => INT_CARRY(117)
);
---- End FA stage
---- Begin FA stage
FA_118:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(147), DATA_B => INT_SUM(148), DATA_C => INT_SUM(149),
SAVE => INT_SUM(150), CARRY => INT_CARRY(118)
);
---- End FA stage
---- Begin FA stage
FA_119:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(104), DATA_B => INT_CARRY(105), DATA_C => INT_CARRY(106),
SAVE => INT_SUM(151), CARRY => INT_CARRY(119)
);
---- End FA stage
---- Begin FA stage
FA_120:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(150), DATA_B => INT_SUM(151), DATA_C => INT_CARRY(107),
SAVE => INT_SUM(152), CARRY => INT_CARRY(120)
);
---- End FA stage
---- Begin NO stage
INT_SUM(153) <= INT_CARRY(108); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_121:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(152), DATA_B => INT_SUM(153), DATA_C => INT_CARRY(109),
SAVE => SUM(24), CARRY => CARRY(24)
);
---- End FA stage
-- End WT-branch 25
-- Begin WT-branch 26
---- Begin FA stage
FA_122:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(182), DATA_B => SUMMAND(183), DATA_C => SUMMAND(184),
SAVE => INT_SUM(154), CARRY => INT_CARRY(121)
);
---- End FA stage
---- Begin FA stage
FA_123:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(185), DATA_B => SUMMAND(186), DATA_C => SUMMAND(187),
SAVE => INT_SUM(155), CARRY => INT_CARRY(122)
);
---- End FA stage
---- Begin FA stage
FA_124:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(188), DATA_B => SUMMAND(189), DATA_C => SUMMAND(190),
SAVE => INT_SUM(156), CARRY => INT_CARRY(123)
);
---- End FA stage
---- Begin FA stage
FA_125:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(191), DATA_B => SUMMAND(192), DATA_C => SUMMAND(193),
SAVE => INT_SUM(157), CARRY => INT_CARRY(124)
);
---- End FA stage
---- Begin NO stage
INT_SUM(158) <= SUMMAND(194); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_126:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(154), DATA_B => INT_SUM(155), DATA_C => INT_SUM(156),
SAVE => INT_SUM(159), CARRY => INT_CARRY(125)
);
---- End FA stage
---- Begin FA stage
FA_127:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(157), DATA_B => INT_SUM(158), DATA_C => INT_CARRY(110),
SAVE => INT_SUM(160), CARRY => INT_CARRY(126)
);
---- End FA stage
---- Begin FA stage
FA_128:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(111), DATA_B => INT_CARRY(112), DATA_C => INT_CARRY(113),
SAVE => INT_SUM(161), CARRY => INT_CARRY(127)
);
---- End FA stage
---- Begin NO stage
INT_SUM(162) <= INT_CARRY(114); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_129:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(159), DATA_B => INT_SUM(160), DATA_C => INT_SUM(161),
SAVE => INT_SUM(163), CARRY => INT_CARRY(128)
);
---- End FA stage
---- Begin FA stage
FA_130:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(162), DATA_B => INT_CARRY(115), DATA_C => INT_CARRY(116),
SAVE => INT_SUM(164), CARRY => INT_CARRY(129)
);
---- End FA stage
---- Begin NO stage
INT_SUM(165) <= INT_CARRY(117); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_131:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(163), DATA_B => INT_SUM(164), DATA_C => INT_SUM(165),
SAVE => INT_SUM(166), CARRY => INT_CARRY(130)
);
---- End FA stage
---- Begin HA stage
HA_23:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(118), DATA_B => INT_CARRY(119),
SAVE => INT_SUM(167), CARRY => INT_CARRY(131)
);
---- End HA stage
---- Begin FA stage
FA_132:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(166), DATA_B => INT_SUM(167), DATA_C => INT_CARRY(120),
SAVE => SUM(25), CARRY => CARRY(25)
);
---- End FA stage
-- End WT-branch 26
-- Begin WT-branch 27
---- Begin FA stage
FA_133:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(195), DATA_B => SUMMAND(196), DATA_C => SUMMAND(197),
SAVE => INT_SUM(168), CARRY => INT_CARRY(132)
);
---- End FA stage
---- Begin FA stage
FA_134:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(198), DATA_B => SUMMAND(199), DATA_C => SUMMAND(200),
SAVE => INT_SUM(169), CARRY => INT_CARRY(133)
);
---- End FA stage
---- Begin FA stage
FA_135:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(201), DATA_B => SUMMAND(202), DATA_C => SUMMAND(203),
SAVE => INT_SUM(170), CARRY => INT_CARRY(134)
);
---- End FA stage
---- Begin FA stage
FA_136:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(204), DATA_B => SUMMAND(205), DATA_C => SUMMAND(206),
SAVE => INT_SUM(171), CARRY => INT_CARRY(135)
);
---- End FA stage
---- Begin FA stage
FA_137:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(207), DATA_B => SUMMAND(208), DATA_C => SUMMAND(209),
SAVE => INT_SUM(172), CARRY => INT_CARRY(136)
);
---- End FA stage
---- Begin FA stage
FA_138:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(168), DATA_B => INT_SUM(169), DATA_C => INT_SUM(170),
SAVE => INT_SUM(173), CARRY => INT_CARRY(137)
);
---- End FA stage
---- Begin FA stage
FA_139:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(171), DATA_B => INT_SUM(172), DATA_C => INT_CARRY(121),
SAVE => INT_SUM(174), CARRY => INT_CARRY(138)
);
---- End FA stage
---- Begin FA stage
FA_140:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(122), DATA_B => INT_CARRY(123), DATA_C => INT_CARRY(124),
SAVE => INT_SUM(175), CARRY => INT_CARRY(139)
);
---- End FA stage
---- Begin FA stage
FA_141:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(173), DATA_B => INT_SUM(174), DATA_C => INT_SUM(175),
SAVE => INT_SUM(176), CARRY => INT_CARRY(140)
);
---- End FA stage
---- Begin FA stage
FA_142:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(125), DATA_B => INT_CARRY(126), DATA_C => INT_CARRY(127),
SAVE => INT_SUM(177), CARRY => INT_CARRY(141)
);
---- End FA stage
---- Begin FA stage
FA_143:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(176), DATA_B => INT_SUM(177), DATA_C => INT_CARRY(128),
SAVE => INT_SUM(178), CARRY => INT_CARRY(142)
);
---- End FA stage
---- Begin NO stage
INT_SUM(179) <= INT_CARRY(129); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_144:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(178), DATA_B => INT_SUM(179), DATA_C => INT_CARRY(130),
SAVE => INT_SUM(180), CARRY => INT_CARRY(143)
);
---- End FA stage
---- Begin NO stage
INT_SUM(181) <= INT_CARRY(131); -- At Level 5
---- End NO stage
---- Begin HA stage
HA_24:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(180), DATA_B => INT_SUM(181),
SAVE => SUM(26), CARRY => CARRY(26)
);
---- End HA stage
-- End WT-branch 27
-- Begin WT-branch 28
---- Begin FA stage
FA_145:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(210), DATA_B => SUMMAND(211), DATA_C => SUMMAND(212),
SAVE => INT_SUM(182), CARRY => INT_CARRY(144)
);
---- End FA stage
---- Begin FA stage
FA_146:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(213), DATA_B => SUMMAND(214), DATA_C => SUMMAND(215),
SAVE => INT_SUM(183), CARRY => INT_CARRY(145)
);
---- End FA stage
---- Begin FA stage
FA_147:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(216), DATA_B => SUMMAND(217), DATA_C => SUMMAND(218),
SAVE => INT_SUM(184), CARRY => INT_CARRY(146)
);
---- End FA stage
---- Begin FA stage
FA_148:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(219), DATA_B => SUMMAND(220), DATA_C => SUMMAND(221),
SAVE => INT_SUM(185), CARRY => INT_CARRY(147)
);
---- End FA stage
---- Begin HA stage
HA_25:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(222), DATA_B => SUMMAND(223),
SAVE => INT_SUM(186), CARRY => INT_CARRY(148)
);
---- End HA stage
---- Begin FA stage
FA_149:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(182), DATA_B => INT_SUM(183), DATA_C => INT_SUM(184),
SAVE => INT_SUM(187), CARRY => INT_CARRY(149)
);
---- End FA stage
---- Begin FA stage
FA_150:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(185), DATA_B => INT_SUM(186), DATA_C => INT_CARRY(132),
SAVE => INT_SUM(188), CARRY => INT_CARRY(150)
);
---- End FA stage
---- Begin FA stage
FA_151:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(133), DATA_B => INT_CARRY(134), DATA_C => INT_CARRY(135),
SAVE => INT_SUM(189), CARRY => INT_CARRY(151)
);
---- End FA stage
---- Begin NO stage
INT_SUM(190) <= INT_CARRY(136); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_152:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(187), DATA_B => INT_SUM(188), DATA_C => INT_SUM(189),
SAVE => INT_SUM(191), CARRY => INT_CARRY(152)
);
---- End FA stage
---- Begin FA stage
FA_153:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(190), DATA_B => INT_CARRY(137), DATA_C => INT_CARRY(138),
SAVE => INT_SUM(192), CARRY => INT_CARRY(153)
);
---- End FA stage
---- Begin NO stage
INT_SUM(193) <= INT_CARRY(139); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_154:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(191), DATA_B => INT_SUM(192), DATA_C => INT_SUM(193),
SAVE => INT_SUM(194), CARRY => INT_CARRY(154)
);
---- End FA stage
---- Begin NO stage
INT_SUM(195) <= INT_CARRY(140); -- At Level 4
---- End NO stage
---- Begin NO stage
INT_SUM(196) <= INT_CARRY(141); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_155:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(194), DATA_B => INT_SUM(195), DATA_C => INT_SUM(196),
SAVE => INT_SUM(197), CARRY => INT_CARRY(155)
);
---- End FA stage
---- Begin NO stage
INT_SUM(198) <= INT_CARRY(142); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_156:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(197), DATA_B => INT_SUM(198), DATA_C => INT_CARRY(143),
SAVE => SUM(27), CARRY => CARRY(27)
);
---- End FA stage
-- End WT-branch 28
-- Begin WT-branch 29
---- Begin FA stage
FA_157:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(224), DATA_B => SUMMAND(225), DATA_C => SUMMAND(226),
SAVE => INT_SUM(199), CARRY => INT_CARRY(156)
);
---- End FA stage
---- Begin FA stage
FA_158:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(227), DATA_B => SUMMAND(228), DATA_C => SUMMAND(229),
SAVE => INT_SUM(200), CARRY => INT_CARRY(157)
);
---- End FA stage
---- Begin FA stage
FA_159:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(230), DATA_B => SUMMAND(231), DATA_C => SUMMAND(232),
SAVE => INT_SUM(201), CARRY => INT_CARRY(158)
);
---- End FA stage
---- Begin FA stage
FA_160:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(233), DATA_B => SUMMAND(234), DATA_C => SUMMAND(235),
SAVE => INT_SUM(202), CARRY => INT_CARRY(159)
);
---- End FA stage
---- Begin FA stage
FA_161:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(236), DATA_B => SUMMAND(237), DATA_C => SUMMAND(238),
SAVE => INT_SUM(203), CARRY => INT_CARRY(160)
);
---- End FA stage
---- Begin NO stage
INT_SUM(204) <= SUMMAND(239); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_162:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(199), DATA_B => INT_SUM(200), DATA_C => INT_SUM(201),
SAVE => INT_SUM(205), CARRY => INT_CARRY(161)
);
---- End FA stage
---- Begin FA stage
FA_163:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(202), DATA_B => INT_SUM(203), DATA_C => INT_SUM(204),
SAVE => INT_SUM(206), CARRY => INT_CARRY(162)
);
---- End FA stage
---- Begin FA stage
FA_164:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(144), DATA_B => INT_CARRY(145), DATA_C => INT_CARRY(146),
SAVE => INT_SUM(207), CARRY => INT_CARRY(163)
);
---- End FA stage
---- Begin NO stage
INT_SUM(208) <= INT_CARRY(147); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(209) <= INT_CARRY(148); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_165:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(205), DATA_B => INT_SUM(206), DATA_C => INT_SUM(207),
SAVE => INT_SUM(210), CARRY => INT_CARRY(164)
);
---- End FA stage
---- Begin FA stage
FA_166:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(208), DATA_B => INT_SUM(209), DATA_C => INT_CARRY(149),
SAVE => INT_SUM(211), CARRY => INT_CARRY(165)
);
---- End FA stage
---- Begin NO stage
INT_SUM(212) <= INT_CARRY(150); -- At Level 3
---- End NO stage
---- Begin NO stage
INT_SUM(213) <= INT_CARRY(151); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_167:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(210), DATA_B => INT_SUM(211), DATA_C => INT_SUM(212),
SAVE => INT_SUM(214), CARRY => INT_CARRY(166)
);
---- End FA stage
---- Begin FA stage
FA_168:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(213), DATA_B => INT_CARRY(152), DATA_C => INT_CARRY(153),
SAVE => INT_SUM(215), CARRY => INT_CARRY(167)
);
---- End FA stage
---- Begin FA stage
FA_169:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(214), DATA_B => INT_SUM(215), DATA_C => INT_CARRY(154),
SAVE => INT_SUM(216), CARRY => INT_CARRY(168)
);
---- End FA stage
---- Begin HA stage
HA_26:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(216), DATA_B => INT_CARRY(155),
SAVE => SUM(28), CARRY => CARRY(28)
);
---- End HA stage
-- End WT-branch 29
-- Begin WT-branch 30
---- Begin FA stage
FA_170:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(240), DATA_B => SUMMAND(241), DATA_C => SUMMAND(242),
SAVE => INT_SUM(217), CARRY => INT_CARRY(169)
);
---- End FA stage
---- Begin FA stage
FA_171:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(243), DATA_B => SUMMAND(244), DATA_C => SUMMAND(245),
SAVE => INT_SUM(218), CARRY => INT_CARRY(170)
);
---- End FA stage
---- Begin FA stage
FA_172:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(246), DATA_B => SUMMAND(247), DATA_C => SUMMAND(248),
SAVE => INT_SUM(219), CARRY => INT_CARRY(171)
);
---- End FA stage
---- Begin FA stage
FA_173:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(249), DATA_B => SUMMAND(250), DATA_C => SUMMAND(251),
SAVE => INT_SUM(220), CARRY => INT_CARRY(172)
);
---- End FA stage
---- Begin FA stage
FA_174:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(252), DATA_B => SUMMAND(253), DATA_C => SUMMAND(254),
SAVE => INT_SUM(221), CARRY => INT_CARRY(173)
);
---- End FA stage
---- Begin FA stage
FA_175:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(217), DATA_B => INT_SUM(218), DATA_C => INT_SUM(219),
SAVE => INT_SUM(222), CARRY => INT_CARRY(174)
);
---- End FA stage
---- Begin FA stage
FA_176:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(220), DATA_B => INT_SUM(221), DATA_C => INT_CARRY(156),
SAVE => INT_SUM(223), CARRY => INT_CARRY(175)
);
---- End FA stage
---- Begin FA stage
FA_177:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(157), DATA_B => INT_CARRY(158), DATA_C => INT_CARRY(159),
SAVE => INT_SUM(224), CARRY => INT_CARRY(176)
);
---- End FA stage
---- Begin NO stage
INT_SUM(225) <= INT_CARRY(160); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_178:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(222), DATA_B => INT_SUM(223), DATA_C => INT_SUM(224),
SAVE => INT_SUM(226), CARRY => INT_CARRY(177)
);
---- End FA stage
---- Begin FA stage
FA_179:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(225), DATA_B => INT_CARRY(161), DATA_C => INT_CARRY(162),
SAVE => INT_SUM(227), CARRY => INT_CARRY(178)
);
---- End FA stage
---- Begin NO stage
INT_SUM(228) <= INT_CARRY(163); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_180:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(226), DATA_B => INT_SUM(227), DATA_C => INT_SUM(228),
SAVE => INT_SUM(229), CARRY => INT_CARRY(179)
);
---- End FA stage
---- Begin HA stage
HA_27:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(164), DATA_B => INT_CARRY(165),
SAVE => INT_SUM(230), CARRY => INT_CARRY(180)
);
---- End HA stage
---- Begin FA stage
FA_181:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(229), DATA_B => INT_SUM(230), DATA_C => INT_CARRY(166),
SAVE => INT_SUM(231), CARRY => INT_CARRY(181)
);
---- End FA stage
---- Begin NO stage
INT_SUM(232) <= INT_CARRY(167); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_182:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(231), DATA_B => INT_SUM(232), DATA_C => INT_CARRY(168),
SAVE => SUM(29), CARRY => CARRY(29)
);
---- End FA stage
-- End WT-branch 30
-- Begin WT-branch 31
---- Begin FA stage
FA_183:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(255), DATA_B => SUMMAND(256), DATA_C => SUMMAND(257),
SAVE => INT_SUM(233), CARRY => INT_CARRY(182)
);
---- End FA stage
---- Begin FA stage
FA_184:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(258), DATA_B => SUMMAND(259), DATA_C => SUMMAND(260),
SAVE => INT_SUM(234), CARRY => INT_CARRY(183)
);
---- End FA stage
---- Begin FA stage
FA_185:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(261), DATA_B => SUMMAND(262), DATA_C => SUMMAND(263),
SAVE => INT_SUM(235), CARRY => INT_CARRY(184)
);
---- End FA stage
---- Begin FA stage
FA_186:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(264), DATA_B => SUMMAND(265), DATA_C => SUMMAND(266),
SAVE => INT_SUM(236), CARRY => INT_CARRY(185)
);
---- End FA stage
---- Begin FA stage
FA_187:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(267), DATA_B => SUMMAND(268), DATA_C => SUMMAND(269),
SAVE => INT_SUM(237), CARRY => INT_CARRY(186)
);
---- End FA stage
---- Begin NO stage
INT_SUM(238) <= SUMMAND(270); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(239) <= SUMMAND(271); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_188:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(233), DATA_B => INT_SUM(234), DATA_C => INT_SUM(235),
SAVE => INT_SUM(240), CARRY => INT_CARRY(187)
);
---- End FA stage
---- Begin FA stage
FA_189:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(236), DATA_B => INT_SUM(237), DATA_C => INT_SUM(238),
SAVE => INT_SUM(241), CARRY => INT_CARRY(188)
);
---- End FA stage
---- Begin FA stage
FA_190:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(239), DATA_B => INT_CARRY(169), DATA_C => INT_CARRY(170),
SAVE => INT_SUM(242), CARRY => INT_CARRY(189)
);
---- End FA stage
---- Begin FA stage
FA_191:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(171), DATA_B => INT_CARRY(172), DATA_C => INT_CARRY(173),
SAVE => INT_SUM(243), CARRY => INT_CARRY(190)
);
---- End FA stage
---- Begin FA stage
FA_192:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(240), DATA_B => INT_SUM(241), DATA_C => INT_SUM(242),
SAVE => INT_SUM(244), CARRY => INT_CARRY(191)
);
---- End FA stage
---- Begin FA stage
FA_193:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(243), DATA_B => INT_CARRY(174), DATA_C => INT_CARRY(175),
SAVE => INT_SUM(245), CARRY => INT_CARRY(192)
);
---- End FA stage
---- Begin NO stage
INT_SUM(246) <= INT_CARRY(176); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_194:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(244), DATA_B => INT_SUM(245), DATA_C => INT_SUM(246),
SAVE => INT_SUM(247), CARRY => INT_CARRY(193)
);
---- End FA stage
---- Begin HA stage
HA_28:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(177), DATA_B => INT_CARRY(178),
SAVE => INT_SUM(248), CARRY => INT_CARRY(194)
);
---- End HA stage
---- Begin FA stage
FA_195:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(247), DATA_B => INT_SUM(248), DATA_C => INT_CARRY(179),
SAVE => INT_SUM(249), CARRY => INT_CARRY(195)
);
---- End FA stage
---- Begin NO stage
INT_SUM(250) <= INT_CARRY(180); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_196:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(249), DATA_B => INT_SUM(250), DATA_C => INT_CARRY(181),
SAVE => SUM(30), CARRY => CARRY(30)
);
---- End FA stage
-- End WT-branch 31
-- Begin WT-branch 32
---- Begin FA stage
FA_197:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(272), DATA_B => SUMMAND(273), DATA_C => SUMMAND(274),
SAVE => INT_SUM(251), CARRY => INT_CARRY(196)
);
---- End FA stage
---- Begin FA stage
FA_198:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(275), DATA_B => SUMMAND(276), DATA_C => SUMMAND(277),
SAVE => INT_SUM(252), CARRY => INT_CARRY(197)
);
---- End FA stage
---- Begin FA stage
FA_199:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(278), DATA_B => SUMMAND(279), DATA_C => SUMMAND(280),
SAVE => INT_SUM(253), CARRY => INT_CARRY(198)
);
---- End FA stage
---- Begin FA stage
FA_200:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(281), DATA_B => SUMMAND(282), DATA_C => SUMMAND(283),
SAVE => INT_SUM(254), CARRY => INT_CARRY(199)
);
---- End FA stage
---- Begin FA stage
FA_201:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(284), DATA_B => SUMMAND(285), DATA_C => SUMMAND(286),
SAVE => INT_SUM(255), CARRY => INT_CARRY(200)
);
---- End FA stage
---- Begin NO stage
INT_SUM(256) <= SUMMAND(287); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_202:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(251), DATA_B => INT_SUM(252), DATA_C => INT_SUM(253),
SAVE => INT_SUM(257), CARRY => INT_CARRY(201)
);
---- End FA stage
---- Begin FA stage
FA_203:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(254), DATA_B => INT_SUM(255), DATA_C => INT_SUM(256),
SAVE => INT_SUM(258), CARRY => INT_CARRY(202)
);
---- End FA stage
---- Begin FA stage
FA_204:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(182), DATA_B => INT_CARRY(183), DATA_C => INT_CARRY(184),
SAVE => INT_SUM(259), CARRY => INT_CARRY(203)
);
---- End FA stage
---- Begin NO stage
INT_SUM(260) <= INT_CARRY(185); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(261) <= INT_CARRY(186); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_205:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(257), DATA_B => INT_SUM(258), DATA_C => INT_SUM(259),
SAVE => INT_SUM(262), CARRY => INT_CARRY(204)
);
---- End FA stage
---- Begin FA stage
FA_206:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(260), DATA_B => INT_SUM(261), DATA_C => INT_CARRY(187),
SAVE => INT_SUM(263), CARRY => INT_CARRY(205)
);
---- End FA stage
---- Begin FA stage
FA_207:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(188), DATA_B => INT_CARRY(189), DATA_C => INT_CARRY(190),
SAVE => INT_SUM(264), CARRY => INT_CARRY(206)
);
---- End FA stage
---- Begin FA stage
FA_208:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(262), DATA_B => INT_SUM(263), DATA_C => INT_SUM(264),
SAVE => INT_SUM(265), CARRY => INT_CARRY(207)
);
---- End FA stage
---- Begin HA stage
HA_29:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(191), DATA_B => INT_CARRY(192),
SAVE => INT_SUM(266), CARRY => INT_CARRY(208)
);
---- End HA stage
---- Begin FA stage
FA_209:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(265), DATA_B => INT_SUM(266), DATA_C => INT_CARRY(193),
SAVE => INT_SUM(267), CARRY => INT_CARRY(209)
);
---- End FA stage
---- Begin NO stage
INT_SUM(268) <= INT_CARRY(194); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_210:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(267), DATA_B => INT_SUM(268), DATA_C => INT_CARRY(195),
SAVE => SUM(31), CARRY => CARRY(31)
);
---- End FA stage
-- End WT-branch 32
-- Begin WT-branch 33
---- Begin FA stage
FA_211:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(288), DATA_B => SUMMAND(289), DATA_C => SUMMAND(290),
SAVE => INT_SUM(269), CARRY => INT_CARRY(210)
);
---- End FA stage
---- Begin FA stage
FA_212:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(291), DATA_B => SUMMAND(292), DATA_C => SUMMAND(293),
SAVE => INT_SUM(270), CARRY => INT_CARRY(211)
);
---- End FA stage
---- Begin FA stage
FA_213:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(294), DATA_B => SUMMAND(295), DATA_C => SUMMAND(296),
SAVE => INT_SUM(271), CARRY => INT_CARRY(212)
);
---- End FA stage
---- Begin FA stage
FA_214:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(297), DATA_B => SUMMAND(298), DATA_C => SUMMAND(299),
SAVE => INT_SUM(272), CARRY => INT_CARRY(213)
);
---- End FA stage
---- Begin FA stage
FA_215:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(300), DATA_B => SUMMAND(301), DATA_C => SUMMAND(302),
SAVE => INT_SUM(273), CARRY => INT_CARRY(214)
);
---- End FA stage
---- Begin FA stage
FA_216:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(303), DATA_B => SUMMAND(304), DATA_C => SUMMAND(305),
SAVE => INT_SUM(274), CARRY => INT_CARRY(215)
);
---- End FA stage
---- Begin FA stage
FA_217:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(269), DATA_B => INT_SUM(270), DATA_C => INT_SUM(271),
SAVE => INT_SUM(275), CARRY => INT_CARRY(216)
);
---- End FA stage
---- Begin FA stage
FA_218:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(272), DATA_B => INT_SUM(273), DATA_C => INT_SUM(274),
SAVE => INT_SUM(276), CARRY => INT_CARRY(217)
);
---- End FA stage
---- Begin FA stage
FA_219:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(196), DATA_B => INT_CARRY(197), DATA_C => INT_CARRY(198),
SAVE => INT_SUM(277), CARRY => INT_CARRY(218)
);
---- End FA stage
---- Begin HA stage
HA_30:HALF_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(199), DATA_B => INT_CARRY(200),
SAVE => INT_SUM(278), CARRY => INT_CARRY(219)
);
---- End HA stage
---- Begin FA stage
FA_220:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(275), DATA_B => INT_SUM(276), DATA_C => INT_SUM(277),
SAVE => INT_SUM(279), CARRY => INT_CARRY(220)
);
---- End FA stage
---- Begin FA stage
FA_221:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(278), DATA_B => INT_CARRY(201), DATA_C => INT_CARRY(202),
SAVE => INT_SUM(280), CARRY => INT_CARRY(221)
);
---- End FA stage
---- Begin NO stage
INT_SUM(281) <= INT_CARRY(203); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_222:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(279), DATA_B => INT_SUM(280), DATA_C => INT_SUM(281),
SAVE => INT_SUM(282), CARRY => INT_CARRY(222)
);
---- End FA stage
---- Begin FA stage
FA_223:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(204), DATA_B => INT_CARRY(205), DATA_C => INT_CARRY(206),
SAVE => INT_SUM(283), CARRY => INT_CARRY(223)
);
---- End FA stage
---- Begin FA stage
FA_224:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(282), DATA_B => INT_SUM(283), DATA_C => INT_CARRY(207),
SAVE => INT_SUM(284), CARRY => INT_CARRY(224)
);
---- End FA stage
---- Begin NO stage
INT_SUM(285) <= INT_CARRY(208); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_225:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(284), DATA_B => INT_SUM(285), DATA_C => INT_CARRY(209),
SAVE => SUM(32), CARRY => CARRY(32)
);
---- End FA stage
-- End WT-branch 33
-- Begin WT-branch 34
---- Begin FA stage
FA_226:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(306), DATA_B => SUMMAND(307), DATA_C => SUMMAND(308),
SAVE => INT_SUM(286), CARRY => INT_CARRY(225)
);
---- End FA stage
---- Begin FA stage
FA_227:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(309), DATA_B => SUMMAND(310), DATA_C => SUMMAND(311),
SAVE => INT_SUM(287), CARRY => INT_CARRY(226)
);
---- End FA stage
---- Begin FA stage
FA_228:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(312), DATA_B => SUMMAND(313), DATA_C => SUMMAND(314),
SAVE => INT_SUM(288), CARRY => INT_CARRY(227)
);
---- End FA stage
---- Begin FA stage
FA_229:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(315), DATA_B => SUMMAND(316), DATA_C => SUMMAND(317),
SAVE => INT_SUM(289), CARRY => INT_CARRY(228)
);
---- End FA stage
---- Begin FA stage
FA_230:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(318), DATA_B => SUMMAND(319), DATA_C => SUMMAND(320),
SAVE => INT_SUM(290), CARRY => INT_CARRY(229)
);
---- End FA stage
---- Begin NO stage
INT_SUM(291) <= SUMMAND(321); -- At Level 1
---- End NO stage
---- Begin NO stage
INT_SUM(292) <= SUMMAND(322); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_231:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(286), DATA_B => INT_SUM(287), DATA_C => INT_SUM(288),
SAVE => INT_SUM(293), CARRY => INT_CARRY(230)
);
---- End FA stage
---- Begin FA stage
FA_232:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(289), DATA_B => INT_SUM(290), DATA_C => INT_SUM(291),
SAVE => INT_SUM(294), CARRY => INT_CARRY(231)
);
---- End FA stage
---- Begin FA stage
FA_233:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(292), DATA_B => INT_CARRY(210), DATA_C => INT_CARRY(211),
SAVE => INT_SUM(295), CARRY => INT_CARRY(232)
);
---- End FA stage
---- Begin FA stage
FA_234:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(212), DATA_B => INT_CARRY(213), DATA_C => INT_CARRY(214),
SAVE => INT_SUM(296), CARRY => INT_CARRY(233)
);
---- End FA stage
---- Begin NO stage
INT_SUM(297) <= INT_CARRY(215); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_235:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(293), DATA_B => INT_SUM(294), DATA_C => INT_SUM(295),
SAVE => INT_SUM(298), CARRY => INT_CARRY(234)
);
---- End FA stage
---- Begin FA stage
FA_236:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(296), DATA_B => INT_SUM(297), DATA_C => INT_CARRY(216),
SAVE => INT_SUM(299), CARRY => INT_CARRY(235)
);
---- End FA stage
---- Begin FA stage
FA_237:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(217), DATA_B => INT_CARRY(218), DATA_C => INT_CARRY(219),
SAVE => INT_SUM(300), CARRY => INT_CARRY(236)
);
---- End FA stage
---- Begin FA stage
FA_238:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(298), DATA_B => INT_SUM(299), DATA_C => INT_SUM(300),
SAVE => INT_SUM(301), CARRY => INT_CARRY(237)
);
---- End FA stage
---- Begin HA stage
HA_31:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(220), DATA_B => INT_CARRY(221),
SAVE => INT_SUM(302), CARRY => INT_CARRY(238)
);
---- End HA stage
---- Begin FA stage
FA_239:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(301), DATA_B => INT_SUM(302), DATA_C => INT_CARRY(222),
SAVE => INT_SUM(303), CARRY => INT_CARRY(239)
);
---- End FA stage
---- Begin NO stage
INT_SUM(304) <= INT_CARRY(223); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_240:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(303), DATA_B => INT_SUM(304), DATA_C => INT_CARRY(224),
SAVE => SUM(33), CARRY => CARRY(33)
);
---- End FA stage
-- End WT-branch 34
-- Begin WT-branch 35
---- Begin FA stage
FA_241:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(323), DATA_B => SUMMAND(324), DATA_C => SUMMAND(325),
SAVE => INT_SUM(305), CARRY => INT_CARRY(240)
);
---- End FA stage
---- Begin FA stage
FA_242:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(326), DATA_B => SUMMAND(327), DATA_C => SUMMAND(328),
SAVE => INT_SUM(306), CARRY => INT_CARRY(241)
);
---- End FA stage
---- Begin FA stage
FA_243:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(329), DATA_B => SUMMAND(330), DATA_C => SUMMAND(331),
SAVE => INT_SUM(307), CARRY => INT_CARRY(242)
);
---- End FA stage
---- Begin FA stage
FA_244:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(332), DATA_B => SUMMAND(333), DATA_C => SUMMAND(334),
SAVE => INT_SUM(308), CARRY => INT_CARRY(243)
);
---- End FA stage
---- Begin FA stage
FA_245:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(335), DATA_B => SUMMAND(336), DATA_C => SUMMAND(337),
SAVE => INT_SUM(309), CARRY => INT_CARRY(244)
);
---- End FA stage
---- Begin FA stage
FA_246:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(338), DATA_B => SUMMAND(339), DATA_C => SUMMAND(340),
SAVE => INT_SUM(310), CARRY => INT_CARRY(245)
);
---- End FA stage
---- Begin FA stage
FA_247:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(305), DATA_B => INT_SUM(306), DATA_C => INT_SUM(307),
SAVE => INT_SUM(311), CARRY => INT_CARRY(246)
);
---- End FA stage
---- Begin FA stage
FA_248:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(308), DATA_B => INT_SUM(309), DATA_C => INT_SUM(310),
SAVE => INT_SUM(312), CARRY => INT_CARRY(247)
);
---- End FA stage
---- Begin FA stage
FA_249:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(225), DATA_B => INT_CARRY(226), DATA_C => INT_CARRY(227),
SAVE => INT_SUM(313), CARRY => INT_CARRY(248)
);
---- End FA stage
---- Begin NO stage
INT_SUM(314) <= INT_CARRY(228); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(315) <= INT_CARRY(229); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_250:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(311), DATA_B => INT_SUM(312), DATA_C => INT_SUM(313),
SAVE => INT_SUM(316), CARRY => INT_CARRY(249)
);
---- End FA stage
---- Begin FA stage
FA_251:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(314), DATA_B => INT_SUM(315), DATA_C => INT_CARRY(230),
SAVE => INT_SUM(317), CARRY => INT_CARRY(250)
);
---- End FA stage
---- Begin FA stage
FA_252:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(231), DATA_B => INT_CARRY(232), DATA_C => INT_CARRY(233),
SAVE => INT_SUM(318), CARRY => INT_CARRY(251)
);
---- End FA stage
---- Begin FA stage
FA_253:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(316), DATA_B => INT_SUM(317), DATA_C => INT_SUM(318),
SAVE => INT_SUM(319), CARRY => INT_CARRY(252)
);
---- End FA stage
---- Begin FA stage
FA_254:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(234), DATA_B => INT_CARRY(235), DATA_C => INT_CARRY(236),
SAVE => INT_SUM(320), CARRY => INT_CARRY(253)
);
---- End FA stage
---- Begin FA stage
FA_255:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(319), DATA_B => INT_SUM(320), DATA_C => INT_CARRY(237),
SAVE => INT_SUM(321), CARRY => INT_CARRY(254)
);
---- End FA stage
---- Begin NO stage
INT_SUM(322) <= INT_CARRY(238); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_256:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(321), DATA_B => INT_SUM(322), DATA_C => INT_CARRY(239),
SAVE => SUM(34), CARRY => CARRY(34)
);
---- End FA stage
-- End WT-branch 35
-- Begin WT-branch 36
---- Begin FA stage
FA_257:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(341), DATA_B => SUMMAND(342), DATA_C => SUMMAND(343),
SAVE => INT_SUM(323), CARRY => INT_CARRY(255)
);
---- End FA stage
---- Begin FA stage
FA_258:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(344), DATA_B => SUMMAND(345), DATA_C => SUMMAND(346),
SAVE => INT_SUM(324), CARRY => INT_CARRY(256)
);
---- End FA stage
---- Begin FA stage
FA_259:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(347), DATA_B => SUMMAND(348), DATA_C => SUMMAND(349),
SAVE => INT_SUM(325), CARRY => INT_CARRY(257)
);
---- End FA stage
---- Begin FA stage
FA_260:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(350), DATA_B => SUMMAND(351), DATA_C => SUMMAND(352),
SAVE => INT_SUM(326), CARRY => INT_CARRY(258)
);
---- End FA stage
---- Begin FA stage
FA_261:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(353), DATA_B => SUMMAND(354), DATA_C => SUMMAND(355),
SAVE => INT_SUM(327), CARRY => INT_CARRY(259)
);
---- End FA stage
---- Begin HA stage
HA_32:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(356), DATA_B => SUMMAND(357),
SAVE => INT_SUM(328), CARRY => INT_CARRY(260)
);
---- End HA stage
---- Begin FA stage
FA_262:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(323), DATA_B => INT_SUM(324), DATA_C => INT_SUM(325),
SAVE => INT_SUM(329), CARRY => INT_CARRY(261)
);
---- End FA stage
---- Begin FA stage
FA_263:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(326), DATA_B => INT_SUM(327), DATA_C => INT_SUM(328),
SAVE => INT_SUM(330), CARRY => INT_CARRY(262)
);
---- End FA stage
---- Begin FA stage
FA_264:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(240), DATA_B => INT_CARRY(241), DATA_C => INT_CARRY(242),
SAVE => INT_SUM(331), CARRY => INT_CARRY(263)
);
---- End FA stage
---- Begin FA stage
FA_265:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(243), DATA_B => INT_CARRY(244), DATA_C => INT_CARRY(245),
SAVE => INT_SUM(332), CARRY => INT_CARRY(264)
);
---- End FA stage
---- Begin FA stage
FA_266:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(329), DATA_B => INT_SUM(330), DATA_C => INT_SUM(331),
SAVE => INT_SUM(333), CARRY => INT_CARRY(265)
);
---- End FA stage
---- Begin FA stage
FA_267:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(332), DATA_B => INT_CARRY(246), DATA_C => INT_CARRY(247),
SAVE => INT_SUM(334), CARRY => INT_CARRY(266)
);
---- End FA stage
---- Begin NO stage
INT_SUM(335) <= INT_CARRY(248); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_268:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(333), DATA_B => INT_SUM(334), DATA_C => INT_SUM(335),
SAVE => INT_SUM(336), CARRY => INT_CARRY(267)
);
---- End FA stage
---- Begin FA stage
FA_269:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(249), DATA_B => INT_CARRY(250), DATA_C => INT_CARRY(251),
SAVE => INT_SUM(337), CARRY => INT_CARRY(268)
);
---- End FA stage
---- Begin FA stage
FA_270:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(336), DATA_B => INT_SUM(337), DATA_C => INT_CARRY(252),
SAVE => INT_SUM(338), CARRY => INT_CARRY(269)
);
---- End FA stage
---- Begin NO stage
INT_SUM(339) <= INT_CARRY(253); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_271:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(338), DATA_B => INT_SUM(339), DATA_C => INT_CARRY(254),
SAVE => SUM(35), CARRY => CARRY(35)
);
---- End FA stage
-- End WT-branch 36
-- Begin WT-branch 37
---- Begin FA stage
FA_272:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(358), DATA_B => SUMMAND(359), DATA_C => SUMMAND(360),
SAVE => INT_SUM(340), CARRY => INT_CARRY(270)
);
---- End FA stage
---- Begin FA stage
FA_273:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(361), DATA_B => SUMMAND(362), DATA_C => SUMMAND(363),
SAVE => INT_SUM(341), CARRY => INT_CARRY(271)
);
---- End FA stage
---- Begin FA stage
FA_274:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(364), DATA_B => SUMMAND(365), DATA_C => SUMMAND(366),
SAVE => INT_SUM(342), CARRY => INT_CARRY(272)
);
---- End FA stage
---- Begin FA stage
FA_275:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(367), DATA_B => SUMMAND(368), DATA_C => SUMMAND(369),
SAVE => INT_SUM(343), CARRY => INT_CARRY(273)
);
---- End FA stage
---- Begin FA stage
FA_276:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(370), DATA_B => SUMMAND(371), DATA_C => SUMMAND(372),
SAVE => INT_SUM(344), CARRY => INT_CARRY(274)
);
---- End FA stage
---- Begin NO stage
INT_SUM(345) <= SUMMAND(373); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_277:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(340), DATA_B => INT_SUM(341), DATA_C => INT_SUM(342),
SAVE => INT_SUM(346), CARRY => INT_CARRY(275)
);
---- End FA stage
---- Begin FA stage
FA_278:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(343), DATA_B => INT_SUM(344), DATA_C => INT_SUM(345),
SAVE => INT_SUM(347), CARRY => INT_CARRY(276)
);
---- End FA stage
---- Begin FA stage
FA_279:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(255), DATA_B => INT_CARRY(256), DATA_C => INT_CARRY(257),
SAVE => INT_SUM(348), CARRY => INT_CARRY(277)
);
---- End FA stage
---- Begin FA stage
FA_280:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(258), DATA_B => INT_CARRY(259), DATA_C => INT_CARRY(260),
SAVE => INT_SUM(349), CARRY => INT_CARRY(278)
);
---- End FA stage
---- Begin FA stage
FA_281:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(346), DATA_B => INT_SUM(347), DATA_C => INT_SUM(348),
SAVE => INT_SUM(350), CARRY => INT_CARRY(279)
);
---- End FA stage
---- Begin FA stage
FA_282:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(349), DATA_B => INT_CARRY(261), DATA_C => INT_CARRY(262),
SAVE => INT_SUM(351), CARRY => INT_CARRY(280)
);
---- End FA stage
---- Begin NO stage
INT_SUM(352) <= INT_CARRY(263); -- At Level 3
---- End NO stage
---- Begin NO stage
INT_SUM(353) <= INT_CARRY(264); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_283:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(350), DATA_B => INT_SUM(351), DATA_C => INT_SUM(352),
SAVE => INT_SUM(354), CARRY => INT_CARRY(281)
);
---- End FA stage
---- Begin FA stage
FA_284:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(353), DATA_B => INT_CARRY(265), DATA_C => INT_CARRY(266),
SAVE => INT_SUM(355), CARRY => INT_CARRY(282)
);
---- End FA stage
---- Begin FA stage
FA_285:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(354), DATA_B => INT_SUM(355), DATA_C => INT_CARRY(267),
SAVE => INT_SUM(356), CARRY => INT_CARRY(283)
);
---- End FA stage
---- Begin NO stage
INT_SUM(357) <= INT_CARRY(268); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_286:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(356), DATA_B => INT_SUM(357), DATA_C => INT_CARRY(269),
SAVE => SUM(36), CARRY => CARRY(36)
);
---- End FA stage
-- End WT-branch 37
-- Begin WT-branch 38
---- Begin FA stage
FA_287:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(374), DATA_B => SUMMAND(375), DATA_C => SUMMAND(376),
SAVE => INT_SUM(358), CARRY => INT_CARRY(284)
);
---- End FA stage
---- Begin FA stage
FA_288:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(377), DATA_B => SUMMAND(378), DATA_C => SUMMAND(379),
SAVE => INT_SUM(359), CARRY => INT_CARRY(285)
);
---- End FA stage
---- Begin FA stage
FA_289:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(380), DATA_B => SUMMAND(381), DATA_C => SUMMAND(382),
SAVE => INT_SUM(360), CARRY => INT_CARRY(286)
);
---- End FA stage
---- Begin FA stage
FA_290:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(383), DATA_B => SUMMAND(384), DATA_C => SUMMAND(385),
SAVE => INT_SUM(361), CARRY => INT_CARRY(287)
);
---- End FA stage
---- Begin FA stage
FA_291:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(386), DATA_B => SUMMAND(387), DATA_C => SUMMAND(388),
SAVE => INT_SUM(362), CARRY => INT_CARRY(288)
);
---- End FA stage
---- Begin NO stage
INT_SUM(363) <= SUMMAND(389); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_292:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(358), DATA_B => INT_SUM(359), DATA_C => INT_SUM(360),
SAVE => INT_SUM(364), CARRY => INT_CARRY(289)
);
---- End FA stage
---- Begin FA stage
FA_293:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(361), DATA_B => INT_SUM(362), DATA_C => INT_SUM(363),
SAVE => INT_SUM(365), CARRY => INT_CARRY(290)
);
---- End FA stage
---- Begin FA stage
FA_294:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(270), DATA_B => INT_CARRY(271), DATA_C => INT_CARRY(272),
SAVE => INT_SUM(366), CARRY => INT_CARRY(291)
);
---- End FA stage
---- Begin NO stage
INT_SUM(367) <= INT_CARRY(273); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(368) <= INT_CARRY(274); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_295:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(364), DATA_B => INT_SUM(365), DATA_C => INT_SUM(366),
SAVE => INT_SUM(369), CARRY => INT_CARRY(292)
);
---- End FA stage
---- Begin FA stage
FA_296:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(367), DATA_B => INT_SUM(368), DATA_C => INT_CARRY(275),
SAVE => INT_SUM(370), CARRY => INT_CARRY(293)
);
---- End FA stage
---- Begin FA stage
FA_297:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(276), DATA_B => INT_CARRY(277), DATA_C => INT_CARRY(278),
SAVE => INT_SUM(371), CARRY => INT_CARRY(294)
);
---- End FA stage
---- Begin FA stage
FA_298:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(369), DATA_B => INT_SUM(370), DATA_C => INT_SUM(371),
SAVE => INT_SUM(372), CARRY => INT_CARRY(295)
);
---- End FA stage
---- Begin HA stage
HA_33:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(279), DATA_B => INT_CARRY(280),
SAVE => INT_SUM(373), CARRY => INT_CARRY(296)
);
---- End HA stage
---- Begin FA stage
FA_299:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(372), DATA_B => INT_SUM(373), DATA_C => INT_CARRY(281),
SAVE => INT_SUM(374), CARRY => INT_CARRY(297)
);
---- End FA stage
---- Begin NO stage
INT_SUM(375) <= INT_CARRY(282); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_300:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(374), DATA_B => INT_SUM(375), DATA_C => INT_CARRY(283),
SAVE => SUM(37), CARRY => CARRY(37)
);
---- End FA stage
-- End WT-branch 38
-- Begin WT-branch 39
---- Begin FA stage
FA_301:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(390), DATA_B => SUMMAND(391), DATA_C => SUMMAND(392),
SAVE => INT_SUM(376), CARRY => INT_CARRY(298)
);
---- End FA stage
---- Begin FA stage
FA_302:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(393), DATA_B => SUMMAND(394), DATA_C => SUMMAND(395),
SAVE => INT_SUM(377), CARRY => INT_CARRY(299)
);
---- End FA stage
---- Begin FA stage
FA_303:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(396), DATA_B => SUMMAND(397), DATA_C => SUMMAND(398),
SAVE => INT_SUM(378), CARRY => INT_CARRY(300)
);
---- End FA stage
---- Begin FA stage
FA_304:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(399), DATA_B => SUMMAND(400), DATA_C => SUMMAND(401),
SAVE => INT_SUM(379), CARRY => INT_CARRY(301)
);
---- End FA stage
---- Begin FA stage
FA_305:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(402), DATA_B => SUMMAND(403), DATA_C => SUMMAND(404),
SAVE => INT_SUM(380), CARRY => INT_CARRY(302)
);
---- End FA stage
---- Begin FA stage
FA_306:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(376), DATA_B => INT_SUM(377), DATA_C => INT_SUM(378),
SAVE => INT_SUM(381), CARRY => INT_CARRY(303)
);
---- End FA stage
---- Begin FA stage
FA_307:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(379), DATA_B => INT_SUM(380), DATA_C => INT_CARRY(284),
SAVE => INT_SUM(382), CARRY => INT_CARRY(304)
);
---- End FA stage
---- Begin FA stage
FA_308:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(285), DATA_B => INT_CARRY(286), DATA_C => INT_CARRY(287),
SAVE => INT_SUM(383), CARRY => INT_CARRY(305)
);
---- End FA stage
---- Begin NO stage
INT_SUM(384) <= INT_CARRY(288); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_309:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(381), DATA_B => INT_SUM(382), DATA_C => INT_SUM(383),
SAVE => INT_SUM(385), CARRY => INT_CARRY(306)
);
---- End FA stage
---- Begin FA stage
FA_310:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(384), DATA_B => INT_CARRY(289), DATA_C => INT_CARRY(290),
SAVE => INT_SUM(386), CARRY => INT_CARRY(307)
);
---- End FA stage
---- Begin NO stage
INT_SUM(387) <= INT_CARRY(291); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_311:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(385), DATA_B => INT_SUM(386), DATA_C => INT_SUM(387),
SAVE => INT_SUM(388), CARRY => INT_CARRY(308)
);
---- End FA stage
---- Begin FA stage
FA_312:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(292), DATA_B => INT_CARRY(293), DATA_C => INT_CARRY(294),
SAVE => INT_SUM(389), CARRY => INT_CARRY(309)
);
---- End FA stage
---- Begin FA stage
FA_313:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(388), DATA_B => INT_SUM(389), DATA_C => INT_CARRY(295),
SAVE => INT_SUM(390), CARRY => INT_CARRY(310)
);
---- End FA stage
---- Begin NO stage
INT_SUM(391) <= INT_CARRY(296); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_314:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(390), DATA_B => INT_SUM(391), DATA_C => INT_CARRY(297),
SAVE => SUM(38), CARRY => CARRY(38)
);
---- End FA stage
-- End WT-branch 39
-- Begin WT-branch 40
---- Begin FA stage
FA_315:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(405), DATA_B => SUMMAND(406), DATA_C => SUMMAND(407),
SAVE => INT_SUM(392), CARRY => INT_CARRY(311)
);
---- End FA stage
---- Begin FA stage
FA_316:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(408), DATA_B => SUMMAND(409), DATA_C => SUMMAND(410),
SAVE => INT_SUM(393), CARRY => INT_CARRY(312)
);
---- End FA stage
---- Begin FA stage
FA_317:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(411), DATA_B => SUMMAND(412), DATA_C => SUMMAND(413),
SAVE => INT_SUM(394), CARRY => INT_CARRY(313)
);
---- End FA stage
---- Begin FA stage
FA_318:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(414), DATA_B => SUMMAND(415), DATA_C => SUMMAND(416),
SAVE => INT_SUM(395), CARRY => INT_CARRY(314)
);
---- End FA stage
---- Begin FA stage
FA_319:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(417), DATA_B => SUMMAND(418), DATA_C => SUMMAND(419),
SAVE => INT_SUM(396), CARRY => INT_CARRY(315)
);
---- End FA stage
---- Begin FA stage
FA_320:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(392), DATA_B => INT_SUM(393), DATA_C => INT_SUM(394),
SAVE => INT_SUM(397), CARRY => INT_CARRY(316)
);
---- End FA stage
---- Begin FA stage
FA_321:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(395), DATA_B => INT_SUM(396), DATA_C => INT_CARRY(298),
SAVE => INT_SUM(398), CARRY => INT_CARRY(317)
);
---- End FA stage
---- Begin FA stage
FA_322:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(299), DATA_B => INT_CARRY(300), DATA_C => INT_CARRY(301),
SAVE => INT_SUM(399), CARRY => INT_CARRY(318)
);
---- End FA stage
---- Begin NO stage
INT_SUM(400) <= INT_CARRY(302); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_323:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(397), DATA_B => INT_SUM(398), DATA_C => INT_SUM(399),
SAVE => INT_SUM(401), CARRY => INT_CARRY(319)
);
---- End FA stage
---- Begin FA stage
FA_324:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(400), DATA_B => INT_CARRY(303), DATA_C => INT_CARRY(304),
SAVE => INT_SUM(402), CARRY => INT_CARRY(320)
);
---- End FA stage
---- Begin NO stage
INT_SUM(403) <= INT_CARRY(305); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_325:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(401), DATA_B => INT_SUM(402), DATA_C => INT_SUM(403),
SAVE => INT_SUM(404), CARRY => INT_CARRY(321)
);
---- End FA stage
---- Begin HA stage
HA_34:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(306), DATA_B => INT_CARRY(307),
SAVE => INT_SUM(405), CARRY => INT_CARRY(322)
);
---- End HA stage
---- Begin FA stage
FA_326:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(404), DATA_B => INT_SUM(405), DATA_C => INT_CARRY(308),
SAVE => INT_SUM(406), CARRY => INT_CARRY(323)
);
---- End FA stage
---- Begin NO stage
INT_SUM(407) <= INT_CARRY(309); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_327:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(406), DATA_B => INT_SUM(407), DATA_C => INT_CARRY(310),
SAVE => SUM(39), CARRY => CARRY(39)
);
---- End FA stage
-- End WT-branch 40
-- Begin WT-branch 41
---- Begin FA stage
FA_328:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(420), DATA_B => SUMMAND(421), DATA_C => SUMMAND(422),
SAVE => INT_SUM(408), CARRY => INT_CARRY(324)
);
---- End FA stage
---- Begin FA stage
FA_329:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(423), DATA_B => SUMMAND(424), DATA_C => SUMMAND(425),
SAVE => INT_SUM(409), CARRY => INT_CARRY(325)
);
---- End FA stage
---- Begin FA stage
FA_330:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(426), DATA_B => SUMMAND(427), DATA_C => SUMMAND(428),
SAVE => INT_SUM(410), CARRY => INT_CARRY(326)
);
---- End FA stage
---- Begin FA stage
FA_331:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(429), DATA_B => SUMMAND(430), DATA_C => SUMMAND(431),
SAVE => INT_SUM(411), CARRY => INT_CARRY(327)
);
---- End FA stage
---- Begin HA stage
HA_35:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(432), DATA_B => SUMMAND(433),
SAVE => INT_SUM(412), CARRY => INT_CARRY(328)
);
---- End HA stage
---- Begin FA stage
FA_332:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(408), DATA_B => INT_SUM(409), DATA_C => INT_SUM(410),
SAVE => INT_SUM(413), CARRY => INT_CARRY(329)
);
---- End FA stage
---- Begin FA stage
FA_333:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(411), DATA_B => INT_SUM(412), DATA_C => INT_CARRY(311),
SAVE => INT_SUM(414), CARRY => INT_CARRY(330)
);
---- End FA stage
---- Begin FA stage
FA_334:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(312), DATA_B => INT_CARRY(313), DATA_C => INT_CARRY(314),
SAVE => INT_SUM(415), CARRY => INT_CARRY(331)
);
---- End FA stage
---- Begin NO stage
INT_SUM(416) <= INT_CARRY(315); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_335:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(413), DATA_B => INT_SUM(414), DATA_C => INT_SUM(415),
SAVE => INT_SUM(417), CARRY => INT_CARRY(332)
);
---- End FA stage
---- Begin FA stage
FA_336:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(416), DATA_B => INT_CARRY(316), DATA_C => INT_CARRY(317),
SAVE => INT_SUM(418), CARRY => INT_CARRY(333)
);
---- End FA stage
---- Begin NO stage
INT_SUM(419) <= INT_CARRY(318); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_337:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(417), DATA_B => INT_SUM(418), DATA_C => INT_SUM(419),
SAVE => INT_SUM(420), CARRY => INT_CARRY(334)
);
---- End FA stage
---- Begin HA stage
HA_36:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(319), DATA_B => INT_CARRY(320),
SAVE => INT_SUM(421), CARRY => INT_CARRY(335)
);
---- End HA stage
---- Begin FA stage
FA_338:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(420), DATA_B => INT_SUM(421), DATA_C => INT_CARRY(321),
SAVE => INT_SUM(422), CARRY => INT_CARRY(336)
);
---- End FA stage
---- Begin NO stage
INT_SUM(423) <= INT_CARRY(322); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_339:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(422), DATA_B => INT_SUM(423), DATA_C => INT_CARRY(323),
SAVE => SUM(40), CARRY => CARRY(40)
);
---- End FA stage
-- End WT-branch 41
-- Begin WT-branch 42
---- Begin FA stage
FA_340:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(434), DATA_B => SUMMAND(435), DATA_C => SUMMAND(436),
SAVE => INT_SUM(424), CARRY => INT_CARRY(337)
);
---- End FA stage
---- Begin FA stage
FA_341:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(437), DATA_B => SUMMAND(438), DATA_C => SUMMAND(439),
SAVE => INT_SUM(425), CARRY => INT_CARRY(338)
);
---- End FA stage
---- Begin FA stage
FA_342:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(440), DATA_B => SUMMAND(441), DATA_C => SUMMAND(442),
SAVE => INT_SUM(426), CARRY => INT_CARRY(339)
);
---- End FA stage
---- Begin FA stage
FA_343:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(443), DATA_B => SUMMAND(444), DATA_C => SUMMAND(445),
SAVE => INT_SUM(427), CARRY => INT_CARRY(340)
);
---- End FA stage
---- Begin HA stage
HA_37:HALF_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(446), DATA_B => SUMMAND(447),
SAVE => INT_SUM(428), CARRY => INT_CARRY(341)
);
---- End HA stage
---- Begin FA stage
FA_344:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(424), DATA_B => INT_SUM(425), DATA_C => INT_SUM(426),
SAVE => INT_SUM(429), CARRY => INT_CARRY(342)
);
---- End FA stage
---- Begin FA stage
FA_345:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(427), DATA_B => INT_SUM(428), DATA_C => INT_CARRY(324),
SAVE => INT_SUM(430), CARRY => INT_CARRY(343)
);
---- End FA stage
---- Begin FA stage
FA_346:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(325), DATA_B => INT_CARRY(326), DATA_C => INT_CARRY(327),
SAVE => INT_SUM(431), CARRY => INT_CARRY(344)
);
---- End FA stage
---- Begin NO stage
INT_SUM(432) <= INT_CARRY(328); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_347:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(429), DATA_B => INT_SUM(430), DATA_C => INT_SUM(431),
SAVE => INT_SUM(433), CARRY => INT_CARRY(345)
);
---- End FA stage
---- Begin FA stage
FA_348:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(432), DATA_B => INT_CARRY(329), DATA_C => INT_CARRY(330),
SAVE => INT_SUM(434), CARRY => INT_CARRY(346)
);
---- End FA stage
---- Begin NO stage
INT_SUM(435) <= INT_CARRY(331); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_349:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(433), DATA_B => INT_SUM(434), DATA_C => INT_SUM(435),
SAVE => INT_SUM(436), CARRY => INT_CARRY(347)
);
---- End FA stage
---- Begin HA stage
HA_38:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(332), DATA_B => INT_CARRY(333),
SAVE => INT_SUM(437), CARRY => INT_CARRY(348)
);
---- End HA stage
---- Begin FA stage
FA_350:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(436), DATA_B => INT_SUM(437), DATA_C => INT_CARRY(334),
SAVE => INT_SUM(438), CARRY => INT_CARRY(349)
);
---- End FA stage
---- Begin NO stage
INT_SUM(439) <= INT_CARRY(335); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_351:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(438), DATA_B => INT_SUM(439), DATA_C => INT_CARRY(336),
SAVE => SUM(41), CARRY => CARRY(41)
);
---- End FA stage
-- End WT-branch 42
-- Begin WT-branch 43
---- Begin FA stage
FA_352:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(448), DATA_B => SUMMAND(449), DATA_C => SUMMAND(450),
SAVE => INT_SUM(440), CARRY => INT_CARRY(350)
);
---- End FA stage
---- Begin FA stage
FA_353:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(451), DATA_B => SUMMAND(452), DATA_C => SUMMAND(453),
SAVE => INT_SUM(441), CARRY => INT_CARRY(351)
);
---- End FA stage
---- Begin FA stage
FA_354:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(454), DATA_B => SUMMAND(455), DATA_C => SUMMAND(456),
SAVE => INT_SUM(442), CARRY => INT_CARRY(352)
);
---- End FA stage
---- Begin FA stage
FA_355:FULL_ADDER -- At Level 1
port map
(
DATA_A => SUMMAND(457), DATA_B => SUMMAND(458), DATA_C => SUMMAND(459),
SAVE => INT_SUM(443), CARRY => INT_CARRY(353)
);
---- End FA stage
---- Begin NO stage
INT_SUM(444) <= SUMMAND(460); -- At Level 1
---- End NO stage
---- Begin FA stage
FA_356:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(440), DATA_B => INT_SUM(441), DATA_C => INT_SUM(442),
SAVE => INT_SUM(445), CARRY => INT_CARRY(354)
);
---- End FA stage
---- Begin FA stage
FA_357:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_SUM(443), DATA_B => INT_SUM(444), DATA_C => INT_CARRY(337),
SAVE => INT_SUM(446), CARRY => INT_CARRY(355)
);
---- End FA stage
---- Begin FA stage
FA_358:FULL_ADDER -- At Level 2
port map
(
DATA_A => INT_CARRY(338), DATA_B => INT_CARRY(339), DATA_C => INT_CARRY(340),
SAVE => INT_SUM(447), CARRY => INT_CARRY(356)
);
---- End FA stage
---- Begin NO stage
INT_SUM(448) <= INT_CARRY(341); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_359:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(445), DATA_B => INT_SUM(446), DATA_C => INT_SUM(447),
SAVE => INT_SUM(449), CARRY => INT_CARRY(357)
);
---- End FA stage
---- Begin FA stage
FA_360:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(448), DATA_B => INT_CARRY(342), DATA_C => INT_CARRY(343),
SAVE => INT_SUM(450), CARRY => INT_CARRY(358)
);
---- End FA stage
---- Begin NO stage
INT_SUM(451) <= INT_CARRY(344); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_361:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(449), DATA_B => INT_SUM(450), DATA_C => INT_SUM(451),
SAVE => INT_SUM(452), CARRY => INT_CARRY(359)
);
---- End FA stage
---- Begin HA stage
HA_39:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(345), DATA_B => INT_CARRY(346),
SAVE => INT_SUM(453), CARRY => INT_CARRY(360)
);
---- End HA stage
---- Begin FA stage
FA_362:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(452), DATA_B => INT_SUM(453), DATA_C => INT_CARRY(347),
SAVE => INT_SUM(454), CARRY => INT_CARRY(361)
);
---- End FA stage
---- Begin NO stage
INT_SUM(455) <= INT_CARRY(348); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_363:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(454), DATA_B => INT_SUM(455), DATA_C => INT_CARRY(349),
SAVE => SUM(42), CARRY => CARRY(42)
);
---- End FA stage
-- End WT-branch 43
-- Begin WT-branch 44
---- Begin FA stage
FA_364:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(461), DATA_B => SUMMAND(462), DATA_C => SUMMAND(463),
SAVE => INT_SUM(456), CARRY => INT_CARRY(362)
);
---- End FA stage
---- Begin FA stage
FA_365:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(464), DATA_B => SUMMAND(465), DATA_C => SUMMAND(466),
SAVE => INT_SUM(457), CARRY => INT_CARRY(363)
);
---- End FA stage
---- Begin FA stage
FA_366:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(467), DATA_B => SUMMAND(468), DATA_C => SUMMAND(469),
SAVE => INT_SUM(458), CARRY => INT_CARRY(364)
);
---- End FA stage
---- Begin FA stage
FA_367:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(470), DATA_B => SUMMAND(471), DATA_C => SUMMAND(472),
SAVE => INT_SUM(459), CARRY => INT_CARRY(365)
);
---- End FA stage
---- Begin FA stage
FA_368:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(473), DATA_B => INT_CARRY(350), DATA_C => INT_CARRY(351),
SAVE => INT_SUM(460), CARRY => INT_CARRY(366)
);
---- End FA stage
---- Begin NO stage
INT_SUM(461) <= INT_CARRY(352); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(462) <= INT_CARRY(353); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_369:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(456), DATA_B => INT_SUM(457), DATA_C => INT_SUM(458),
SAVE => INT_SUM(463), CARRY => INT_CARRY(367)
);
---- End FA stage
---- Begin FA stage
FA_370:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(459), DATA_B => INT_SUM(460), DATA_C => INT_SUM(461),
SAVE => INT_SUM(464), CARRY => INT_CARRY(368)
);
---- End FA stage
---- Begin FA stage
FA_371:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(462), DATA_B => INT_CARRY(354), DATA_C => INT_CARRY(355),
SAVE => INT_SUM(465), CARRY => INT_CARRY(369)
);
---- End FA stage
---- Begin NO stage
INT_SUM(466) <= INT_CARRY(356); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_372:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(463), DATA_B => INT_SUM(464), DATA_C => INT_SUM(465),
SAVE => INT_SUM(467), CARRY => INT_CARRY(370)
);
---- End FA stage
---- Begin FA stage
FA_373:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(466), DATA_B => INT_CARRY(357), DATA_C => INT_CARRY(358),
SAVE => INT_SUM(468), CARRY => INT_CARRY(371)
);
---- End FA stage
---- Begin FA stage
FA_374:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(467), DATA_B => INT_SUM(468), DATA_C => INT_CARRY(359),
SAVE => INT_SUM(469), CARRY => INT_CARRY(372)
);
---- End FA stage
---- Begin NO stage
INT_SUM(470) <= INT_CARRY(360); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_375:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(469), DATA_B => INT_SUM(470), DATA_C => INT_CARRY(361),
SAVE => SUM(43), CARRY => CARRY(43)
);
---- End FA stage
-- End WT-branch 44
-- Begin WT-branch 45
---- Begin FA stage
FA_376:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(474), DATA_B => SUMMAND(475), DATA_C => SUMMAND(476),
SAVE => INT_SUM(471), CARRY => INT_CARRY(373)
);
---- End FA stage
---- Begin FA stage
FA_377:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(477), DATA_B => SUMMAND(478), DATA_C => SUMMAND(479),
SAVE => INT_SUM(472), CARRY => INT_CARRY(374)
);
---- End FA stage
---- Begin FA stage
FA_378:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(480), DATA_B => SUMMAND(481), DATA_C => SUMMAND(482),
SAVE => INT_SUM(473), CARRY => INT_CARRY(375)
);
---- End FA stage
---- Begin FA stage
FA_379:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(483), DATA_B => SUMMAND(484), DATA_C => SUMMAND(485),
SAVE => INT_SUM(474), CARRY => INT_CARRY(376)
);
---- End FA stage
---- Begin FA stage
FA_380:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(471), DATA_B => INT_SUM(472), DATA_C => INT_SUM(473),
SAVE => INT_SUM(475), CARRY => INT_CARRY(377)
);
---- End FA stage
---- Begin FA stage
FA_381:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(474), DATA_B => INT_CARRY(362), DATA_C => INT_CARRY(363),
SAVE => INT_SUM(476), CARRY => INT_CARRY(378)
);
---- End FA stage
---- Begin FA stage
FA_382:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(364), DATA_B => INT_CARRY(365), DATA_C => INT_CARRY(366),
SAVE => INT_SUM(477), CARRY => INT_CARRY(379)
);
---- End FA stage
---- Begin FA stage
FA_383:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(475), DATA_B => INT_SUM(476), DATA_C => INT_SUM(477),
SAVE => INT_SUM(478), CARRY => INT_CARRY(380)
);
---- End FA stage
---- Begin FA stage
FA_384:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(367), DATA_B => INT_CARRY(368), DATA_C => INT_CARRY(369),
SAVE => INT_SUM(479), CARRY => INT_CARRY(381)
);
---- End FA stage
---- Begin FA stage
FA_385:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(478), DATA_B => INT_SUM(479), DATA_C => INT_CARRY(370),
SAVE => INT_SUM(480), CARRY => INT_CARRY(382)
);
---- End FA stage
---- Begin NO stage
INT_SUM(481) <= INT_CARRY(371); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_386:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(480), DATA_B => INT_SUM(481), DATA_C => INT_CARRY(372),
SAVE => SUM(44), CARRY => CARRY(44)
);
---- End FA stage
-- End WT-branch 45
-- Begin WT-branch 46
---- Begin FA stage
FA_387:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(486), DATA_B => SUMMAND(487), DATA_C => SUMMAND(488),
SAVE => INT_SUM(482), CARRY => INT_CARRY(383)
);
---- End FA stage
---- Begin FA stage
FA_388:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(489), DATA_B => SUMMAND(490), DATA_C => SUMMAND(491),
SAVE => INT_SUM(483), CARRY => INT_CARRY(384)
);
---- End FA stage
---- Begin FA stage
FA_389:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(492), DATA_B => SUMMAND(493), DATA_C => SUMMAND(494),
SAVE => INT_SUM(484), CARRY => INT_CARRY(385)
);
---- End FA stage
---- Begin FA stage
FA_390:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(495), DATA_B => SUMMAND(496), DATA_C => SUMMAND(497),
SAVE => INT_SUM(485), CARRY => INT_CARRY(386)
);
---- End FA stage
---- Begin FA stage
FA_391:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(482), DATA_B => INT_SUM(483), DATA_C => INT_SUM(484),
SAVE => INT_SUM(486), CARRY => INT_CARRY(387)
);
---- End FA stage
---- Begin FA stage
FA_392:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(485), DATA_B => INT_CARRY(373), DATA_C => INT_CARRY(374),
SAVE => INT_SUM(487), CARRY => INT_CARRY(388)
);
---- End FA stage
---- Begin HA stage
HA_40:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(375), DATA_B => INT_CARRY(376),
SAVE => INT_SUM(488), CARRY => INT_CARRY(389)
);
---- End HA stage
---- Begin FA stage
FA_393:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(486), DATA_B => INT_SUM(487), DATA_C => INT_SUM(488),
SAVE => INT_SUM(489), CARRY => INT_CARRY(390)
);
---- End FA stage
---- Begin FA stage
FA_394:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(377), DATA_B => INT_CARRY(378), DATA_C => INT_CARRY(379),
SAVE => INT_SUM(490), CARRY => INT_CARRY(391)
);
---- End FA stage
---- Begin FA stage
FA_395:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(489), DATA_B => INT_SUM(490), DATA_C => INT_CARRY(380),
SAVE => INT_SUM(491), CARRY => INT_CARRY(392)
);
---- End FA stage
---- Begin NO stage
INT_SUM(492) <= INT_CARRY(381); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_396:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(491), DATA_B => INT_SUM(492), DATA_C => INT_CARRY(382),
SAVE => SUM(45), CARRY => CARRY(45)
);
---- End FA stage
-- End WT-branch 46
-- Begin WT-branch 47
---- Begin FA stage
FA_397:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(498), DATA_B => SUMMAND(499), DATA_C => SUMMAND(500),
SAVE => INT_SUM(493), CARRY => INT_CARRY(393)
);
---- End FA stage
---- Begin FA stage
FA_398:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(501), DATA_B => SUMMAND(502), DATA_C => SUMMAND(503),
SAVE => INT_SUM(494), CARRY => INT_CARRY(394)
);
---- End FA stage
---- Begin FA stage
FA_399:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(504), DATA_B => SUMMAND(505), DATA_C => SUMMAND(506),
SAVE => INT_SUM(495), CARRY => INT_CARRY(395)
);
---- End FA stage
---- Begin NO stage
INT_SUM(496) <= SUMMAND(507); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(497) <= SUMMAND(508); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_400:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(493), DATA_B => INT_SUM(494), DATA_C => INT_SUM(495),
SAVE => INT_SUM(498), CARRY => INT_CARRY(396)
);
---- End FA stage
---- Begin FA stage
FA_401:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(496), DATA_B => INT_SUM(497), DATA_C => INT_CARRY(383),
SAVE => INT_SUM(499), CARRY => INT_CARRY(397)
);
---- End FA stage
---- Begin FA stage
FA_402:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(384), DATA_B => INT_CARRY(385), DATA_C => INT_CARRY(386),
SAVE => INT_SUM(500), CARRY => INT_CARRY(398)
);
---- End FA stage
---- Begin FA stage
FA_403:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(498), DATA_B => INT_SUM(499), DATA_C => INT_SUM(500),
SAVE => INT_SUM(501), CARRY => INT_CARRY(399)
);
---- End FA stage
---- Begin FA stage
FA_404:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(387), DATA_B => INT_CARRY(388), DATA_C => INT_CARRY(389),
SAVE => INT_SUM(502), CARRY => INT_CARRY(400)
);
---- End FA stage
---- Begin FA stage
FA_405:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(501), DATA_B => INT_SUM(502), DATA_C => INT_CARRY(390),
SAVE => INT_SUM(503), CARRY => INT_CARRY(401)
);
---- End FA stage
---- Begin NO stage
INT_SUM(504) <= INT_CARRY(391); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_406:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(503), DATA_B => INT_SUM(504), DATA_C => INT_CARRY(392),
SAVE => SUM(46), CARRY => CARRY(46)
);
---- End FA stage
-- End WT-branch 47
-- Begin WT-branch 48
---- Begin FA stage
FA_407:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(509), DATA_B => SUMMAND(510), DATA_C => SUMMAND(511),
SAVE => INT_SUM(505), CARRY => INT_CARRY(402)
);
---- End FA stage
---- Begin FA stage
FA_408:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(512), DATA_B => SUMMAND(513), DATA_C => SUMMAND(514),
SAVE => INT_SUM(506), CARRY => INT_CARRY(403)
);
---- End FA stage
---- Begin FA stage
FA_409:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(515), DATA_B => SUMMAND(516), DATA_C => SUMMAND(517),
SAVE => INT_SUM(507), CARRY => INT_CARRY(404)
);
---- End FA stage
---- Begin HA stage
HA_41:HALF_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(518), DATA_B => SUMMAND(519),
SAVE => INT_SUM(508), CARRY => INT_CARRY(405)
);
---- End HA stage
---- Begin FA stage
FA_410:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(505), DATA_B => INT_SUM(506), DATA_C => INT_SUM(507),
SAVE => INT_SUM(509), CARRY => INT_CARRY(406)
);
---- End FA stage
---- Begin FA stage
FA_411:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(508), DATA_B => INT_CARRY(393), DATA_C => INT_CARRY(394),
SAVE => INT_SUM(510), CARRY => INT_CARRY(407)
);
---- End FA stage
---- Begin NO stage
INT_SUM(511) <= INT_CARRY(395); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_412:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(509), DATA_B => INT_SUM(510), DATA_C => INT_SUM(511),
SAVE => INT_SUM(512), CARRY => INT_CARRY(408)
);
---- End FA stage
---- Begin FA stage
FA_413:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(396), DATA_B => INT_CARRY(397), DATA_C => INT_CARRY(398),
SAVE => INT_SUM(513), CARRY => INT_CARRY(409)
);
---- End FA stage
---- Begin FA stage
FA_414:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(512), DATA_B => INT_SUM(513), DATA_C => INT_CARRY(399),
SAVE => INT_SUM(514), CARRY => INT_CARRY(410)
);
---- End FA stage
---- Begin NO stage
INT_SUM(515) <= INT_CARRY(400); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_415:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(514), DATA_B => INT_SUM(515), DATA_C => INT_CARRY(401),
SAVE => SUM(47), CARRY => CARRY(47)
);
---- End FA stage
-- End WT-branch 48
-- Begin WT-branch 49
---- Begin FA stage
FA_416:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(520), DATA_B => SUMMAND(521), DATA_C => SUMMAND(522),
SAVE => INT_SUM(516), CARRY => INT_CARRY(411)
);
---- End FA stage
---- Begin FA stage
FA_417:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(523), DATA_B => SUMMAND(524), DATA_C => SUMMAND(525),
SAVE => INT_SUM(517), CARRY => INT_CARRY(412)
);
---- End FA stage
---- Begin FA stage
FA_418:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(526), DATA_B => SUMMAND(527), DATA_C => SUMMAND(528),
SAVE => INT_SUM(518), CARRY => INT_CARRY(413)
);
---- End FA stage
---- Begin NO stage
INT_SUM(519) <= SUMMAND(529); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_419:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(516), DATA_B => INT_SUM(517), DATA_C => INT_SUM(518),
SAVE => INT_SUM(520), CARRY => INT_CARRY(414)
);
---- End FA stage
---- Begin FA stage
FA_420:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(519), DATA_B => INT_CARRY(402), DATA_C => INT_CARRY(403),
SAVE => INT_SUM(521), CARRY => INT_CARRY(415)
);
---- End FA stage
---- Begin NO stage
INT_SUM(522) <= INT_CARRY(404); -- At Level 3
---- End NO stage
---- Begin NO stage
INT_SUM(523) <= INT_CARRY(405); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_421:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(520), DATA_B => INT_SUM(521), DATA_C => INT_SUM(522),
SAVE => INT_SUM(524), CARRY => INT_CARRY(416)
);
---- End FA stage
---- Begin FA stage
FA_422:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(523), DATA_B => INT_CARRY(406), DATA_C => INT_CARRY(407),
SAVE => INT_SUM(525), CARRY => INT_CARRY(417)
);
---- End FA stage
---- Begin FA stage
FA_423:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(524), DATA_B => INT_SUM(525), DATA_C => INT_CARRY(408),
SAVE => INT_SUM(526), CARRY => INT_CARRY(418)
);
---- End FA stage
---- Begin NO stage
INT_SUM(527) <= INT_CARRY(409); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_424:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(526), DATA_B => INT_SUM(527), DATA_C => INT_CARRY(410),
SAVE => SUM(48), CARRY => CARRY(48)
);
---- End FA stage
-- End WT-branch 49
-- Begin WT-branch 50
---- Begin FA stage
FA_425:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(530), DATA_B => SUMMAND(531), DATA_C => SUMMAND(532),
SAVE => INT_SUM(528), CARRY => INT_CARRY(419)
);
---- End FA stage
---- Begin FA stage
FA_426:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(533), DATA_B => SUMMAND(534), DATA_C => SUMMAND(535),
SAVE => INT_SUM(529), CARRY => INT_CARRY(420)
);
---- End FA stage
---- Begin FA stage
FA_427:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(536), DATA_B => SUMMAND(537), DATA_C => SUMMAND(538),
SAVE => INT_SUM(530), CARRY => INT_CARRY(421)
);
---- End FA stage
---- Begin NO stage
INT_SUM(531) <= SUMMAND(539); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_428:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(528), DATA_B => INT_SUM(529), DATA_C => INT_SUM(530),
SAVE => INT_SUM(532), CARRY => INT_CARRY(422)
);
---- End FA stage
---- Begin FA stage
FA_429:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(531), DATA_B => INT_CARRY(411), DATA_C => INT_CARRY(412),
SAVE => INT_SUM(533), CARRY => INT_CARRY(423)
);
---- End FA stage
---- Begin NO stage
INT_SUM(534) <= INT_CARRY(413); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_430:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(532), DATA_B => INT_SUM(533), DATA_C => INT_SUM(534),
SAVE => INT_SUM(535), CARRY => INT_CARRY(424)
);
---- End FA stage
---- Begin HA stage
HA_42:HALF_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(414), DATA_B => INT_CARRY(415),
SAVE => INT_SUM(536), CARRY => INT_CARRY(425)
);
---- End HA stage
---- Begin FA stage
FA_431:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(535), DATA_B => INT_SUM(536), DATA_C => INT_CARRY(416),
SAVE => INT_SUM(537), CARRY => INT_CARRY(426)
);
---- End FA stage
---- Begin NO stage
INT_SUM(538) <= INT_CARRY(417); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_432:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(537), DATA_B => INT_SUM(538), DATA_C => INT_CARRY(418),
SAVE => SUM(49), CARRY => CARRY(49)
);
---- End FA stage
-- End WT-branch 50
-- Begin WT-branch 51
---- Begin FA stage
FA_433:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(540), DATA_B => SUMMAND(541), DATA_C => SUMMAND(542),
SAVE => INT_SUM(539), CARRY => INT_CARRY(427)
);
---- End FA stage
---- Begin FA stage
FA_434:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(543), DATA_B => SUMMAND(544), DATA_C => SUMMAND(545),
SAVE => INT_SUM(540), CARRY => INT_CARRY(428)
);
---- End FA stage
---- Begin FA stage
FA_435:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(546), DATA_B => SUMMAND(547), DATA_C => SUMMAND(548),
SAVE => INT_SUM(541), CARRY => INT_CARRY(429)
);
---- End FA stage
---- Begin FA stage
FA_436:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(539), DATA_B => INT_SUM(540), DATA_C => INT_SUM(541),
SAVE => INT_SUM(542), CARRY => INT_CARRY(430)
);
---- End FA stage
---- Begin FA stage
FA_437:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(419), DATA_B => INT_CARRY(420), DATA_C => INT_CARRY(421),
SAVE => INT_SUM(543), CARRY => INT_CARRY(431)
);
---- End FA stage
---- Begin FA stage
FA_438:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(542), DATA_B => INT_SUM(543), DATA_C => INT_CARRY(422),
SAVE => INT_SUM(544), CARRY => INT_CARRY(432)
);
---- End FA stage
---- Begin NO stage
INT_SUM(545) <= INT_CARRY(423); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_439:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(544), DATA_B => INT_SUM(545), DATA_C => INT_CARRY(424),
SAVE => INT_SUM(546), CARRY => INT_CARRY(433)
);
---- End FA stage
---- Begin NO stage
INT_SUM(547) <= INT_CARRY(425); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_440:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(546), DATA_B => INT_SUM(547), DATA_C => INT_CARRY(426),
SAVE => SUM(50), CARRY => CARRY(50)
);
---- End FA stage
-- End WT-branch 51
-- Begin WT-branch 52
---- Begin FA stage
FA_441:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(549), DATA_B => SUMMAND(550), DATA_C => SUMMAND(551),
SAVE => INT_SUM(548), CARRY => INT_CARRY(434)
);
---- End FA stage
---- Begin FA stage
FA_442:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(552), DATA_B => SUMMAND(553), DATA_C => SUMMAND(554),
SAVE => INT_SUM(549), CARRY => INT_CARRY(435)
);
---- End FA stage
---- Begin FA stage
FA_443:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(555), DATA_B => SUMMAND(556), DATA_C => SUMMAND(557),
SAVE => INT_SUM(550), CARRY => INT_CARRY(436)
);
---- End FA stage
---- Begin FA stage
FA_444:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(548), DATA_B => INT_SUM(549), DATA_C => INT_SUM(550),
SAVE => INT_SUM(551), CARRY => INT_CARRY(437)
);
---- End FA stage
---- Begin FA stage
FA_445:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(427), DATA_B => INT_CARRY(428), DATA_C => INT_CARRY(429),
SAVE => INT_SUM(552), CARRY => INT_CARRY(438)
);
---- End FA stage
---- Begin FA stage
FA_446:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(551), DATA_B => INT_SUM(552), DATA_C => INT_CARRY(430),
SAVE => INT_SUM(553), CARRY => INT_CARRY(439)
);
---- End FA stage
---- Begin NO stage
INT_SUM(554) <= INT_CARRY(431); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_447:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(553), DATA_B => INT_SUM(554), DATA_C => INT_CARRY(432),
SAVE => INT_SUM(555), CARRY => INT_CARRY(440)
);
---- End FA stage
---- Begin HA stage
HA_43:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(555), DATA_B => INT_CARRY(433),
SAVE => SUM(51), CARRY => CARRY(51)
);
---- End HA stage
-- End WT-branch 52
-- Begin WT-branch 53
---- Begin FA stage
FA_448:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(558), DATA_B => SUMMAND(559), DATA_C => SUMMAND(560),
SAVE => INT_SUM(556), CARRY => INT_CARRY(441)
);
---- End FA stage
---- Begin FA stage
FA_449:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(561), DATA_B => SUMMAND(562), DATA_C => SUMMAND(563),
SAVE => INT_SUM(557), CARRY => INT_CARRY(442)
);
---- End FA stage
---- Begin FA stage
FA_450:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(564), DATA_B => SUMMAND(565), DATA_C => INT_CARRY(434),
SAVE => INT_SUM(558), CARRY => INT_CARRY(443)
);
---- End FA stage
---- Begin HA stage
HA_44:HALF_ADDER -- At Level 3
port map
(
DATA_A => INT_CARRY(435), DATA_B => INT_CARRY(436),
SAVE => INT_SUM(559), CARRY => INT_CARRY(444)
);
---- End HA stage
---- Begin FA stage
FA_451:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(556), DATA_B => INT_SUM(557), DATA_C => INT_SUM(558),
SAVE => INT_SUM(560), CARRY => INT_CARRY(445)
);
---- End FA stage
---- Begin FA stage
FA_452:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(559), DATA_B => INT_CARRY(437), DATA_C => INT_CARRY(438),
SAVE => INT_SUM(561), CARRY => INT_CARRY(446)
);
---- End FA stage
---- Begin FA stage
FA_453:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(560), DATA_B => INT_SUM(561), DATA_C => INT_CARRY(439),
SAVE => INT_SUM(562), CARRY => INT_CARRY(447)
);
---- End FA stage
---- Begin HA stage
HA_45:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(562), DATA_B => INT_CARRY(440),
SAVE => SUM(52), CARRY => CARRY(52)
);
---- End HA stage
-- End WT-branch 53
-- Begin WT-branch 54
---- Begin FA stage
FA_454:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(566), DATA_B => SUMMAND(567), DATA_C => SUMMAND(568),
SAVE => INT_SUM(563), CARRY => INT_CARRY(448)
);
---- End FA stage
---- Begin FA stage
FA_455:FULL_ADDER -- At Level 2
port map
(
DATA_A => SUMMAND(569), DATA_B => SUMMAND(570), DATA_C => SUMMAND(571),
SAVE => INT_SUM(564), CARRY => INT_CARRY(449)
);
---- End FA stage
---- Begin NO stage
INT_SUM(565) <= SUMMAND(572); -- At Level 2
---- End NO stage
---- Begin NO stage
INT_SUM(566) <= SUMMAND(573); -- At Level 2
---- End NO stage
---- Begin FA stage
FA_456:FULL_ADDER -- At Level 3
port map
(
DATA_A => INT_SUM(563), DATA_B => INT_SUM(564), DATA_C => INT_SUM(565),
SAVE => INT_SUM(567), CARRY => INT_CARRY(450)
);
---- End FA stage
---- Begin NO stage
INT_SUM(568) <= INT_SUM(566); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_457:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(567), DATA_B => INT_SUM(568), DATA_C => INT_CARRY(441),
SAVE => INT_SUM(569), CARRY => INT_CARRY(451)
);
---- End FA stage
---- Begin FA stage
FA_458:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(442), DATA_B => INT_CARRY(443), DATA_C => INT_CARRY(444),
SAVE => INT_SUM(570), CARRY => INT_CARRY(452)
);
---- End FA stage
---- Begin FA stage
FA_459:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(569), DATA_B => INT_SUM(570), DATA_C => INT_CARRY(445),
SAVE => INT_SUM(571), CARRY => INT_CARRY(453)
);
---- End FA stage
---- Begin NO stage
INT_SUM(572) <= INT_CARRY(446); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_460:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(571), DATA_B => INT_SUM(572), DATA_C => INT_CARRY(447),
SAVE => SUM(53), CARRY => CARRY(53)
);
---- End FA stage
-- End WT-branch 54
-- Begin WT-branch 55
---- Begin FA stage
FA_461:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(574), DATA_B => SUMMAND(575), DATA_C => SUMMAND(576),
SAVE => INT_SUM(573), CARRY => INT_CARRY(454)
);
---- End FA stage
---- Begin FA stage
FA_462:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(577), DATA_B => SUMMAND(578), DATA_C => SUMMAND(579),
SAVE => INT_SUM(574), CARRY => INT_CARRY(455)
);
---- End FA stage
---- Begin FA stage
FA_463:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(580), DATA_B => INT_CARRY(448), DATA_C => INT_CARRY(449),
SAVE => INT_SUM(575), CARRY => INT_CARRY(456)
);
---- End FA stage
---- Begin FA stage
FA_464:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(573), DATA_B => INT_SUM(574), DATA_C => INT_SUM(575),
SAVE => INT_SUM(576), CARRY => INT_CARRY(457)
);
---- End FA stage
---- Begin NO stage
INT_SUM(577) <= INT_CARRY(450); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_465:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(576), DATA_B => INT_SUM(577), DATA_C => INT_CARRY(451),
SAVE => INT_SUM(578), CARRY => INT_CARRY(458)
);
---- End FA stage
---- Begin NO stage
INT_SUM(579) <= INT_CARRY(452); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_466:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(578), DATA_B => INT_SUM(579), DATA_C => INT_CARRY(453),
SAVE => SUM(54), CARRY => CARRY(54)
);
---- End FA stage
-- End WT-branch 55
-- Begin WT-branch 56
---- Begin FA stage
FA_467:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(581), DATA_B => SUMMAND(582), DATA_C => SUMMAND(583),
SAVE => INT_SUM(580), CARRY => INT_CARRY(459)
);
---- End FA stage
---- Begin FA stage
FA_468:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(584), DATA_B => SUMMAND(585), DATA_C => SUMMAND(586),
SAVE => INT_SUM(581), CARRY => INT_CARRY(460)
);
---- End FA stage
---- Begin NO stage
INT_SUM(582) <= SUMMAND(587); -- At Level 3
---- End NO stage
---- Begin FA stage
FA_469:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(580), DATA_B => INT_SUM(581), DATA_C => INT_SUM(582),
SAVE => INT_SUM(583), CARRY => INT_CARRY(461)
);
---- End FA stage
---- Begin FA stage
FA_470:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_CARRY(454), DATA_B => INT_CARRY(455), DATA_C => INT_CARRY(456),
SAVE => INT_SUM(584), CARRY => INT_CARRY(462)
);
---- End FA stage
---- Begin FA stage
FA_471:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(583), DATA_B => INT_SUM(584), DATA_C => INT_CARRY(457),
SAVE => INT_SUM(585), CARRY => INT_CARRY(463)
);
---- End FA stage
---- Begin HA stage
HA_46:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(585), DATA_B => INT_CARRY(458),
SAVE => SUM(55), CARRY => CARRY(55)
);
---- End HA stage
-- End WT-branch 56
-- Begin WT-branch 57
---- Begin FA stage
FA_472:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(588), DATA_B => SUMMAND(589), DATA_C => SUMMAND(590),
SAVE => INT_SUM(586), CARRY => INT_CARRY(464)
);
---- End FA stage
---- Begin FA stage
FA_473:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(591), DATA_B => SUMMAND(592), DATA_C => SUMMAND(593),
SAVE => INT_SUM(587), CARRY => INT_CARRY(465)
);
---- End FA stage
---- Begin FA stage
FA_474:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(586), DATA_B => INT_SUM(587), DATA_C => INT_CARRY(459),
SAVE => INT_SUM(588), CARRY => INT_CARRY(466)
);
---- End FA stage
---- Begin NO stage
INT_SUM(589) <= INT_CARRY(460); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_475:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(588), DATA_B => INT_SUM(589), DATA_C => INT_CARRY(461),
SAVE => INT_SUM(590), CARRY => INT_CARRY(467)
);
---- End FA stage
---- Begin NO stage
INT_SUM(591) <= INT_CARRY(462); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_476:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(590), DATA_B => INT_SUM(591), DATA_C => INT_CARRY(463),
SAVE => SUM(56), CARRY => CARRY(56)
);
---- End FA stage
-- End WT-branch 57
-- Begin WT-branch 58
---- Begin FA stage
FA_477:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(594), DATA_B => SUMMAND(595), DATA_C => SUMMAND(596),
SAVE => INT_SUM(592), CARRY => INT_CARRY(468)
);
---- End FA stage
---- Begin FA stage
FA_478:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(597), DATA_B => SUMMAND(598), DATA_C => SUMMAND(599),
SAVE => INT_SUM(593), CARRY => INT_CARRY(469)
);
---- End FA stage
---- Begin FA stage
FA_479:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(592), DATA_B => INT_SUM(593), DATA_C => INT_CARRY(464),
SAVE => INT_SUM(594), CARRY => INT_CARRY(470)
);
---- End FA stage
---- Begin NO stage
INT_SUM(595) <= INT_CARRY(465); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_480:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(594), DATA_B => INT_SUM(595), DATA_C => INT_CARRY(466),
SAVE => INT_SUM(596), CARRY => INT_CARRY(471)
);
---- End FA stage
---- Begin HA stage
HA_47:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(596), DATA_B => INT_CARRY(467),
SAVE => SUM(57), CARRY => CARRY(57)
);
---- End HA stage
-- End WT-branch 58
-- Begin WT-branch 59
---- Begin FA stage
FA_481:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(600), DATA_B => SUMMAND(601), DATA_C => SUMMAND(602),
SAVE => INT_SUM(597), CARRY => INT_CARRY(472)
);
---- End FA stage
---- Begin HA stage
HA_48:HALF_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(603), DATA_B => SUMMAND(604),
SAVE => INT_SUM(598), CARRY => INT_CARRY(473)
);
---- End HA stage
---- Begin FA stage
FA_482:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(597), DATA_B => INT_SUM(598), DATA_C => INT_CARRY(468),
SAVE => INT_SUM(599), CARRY => INT_CARRY(474)
);
---- End FA stage
---- Begin NO stage
INT_SUM(600) <= INT_CARRY(469); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_483:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(599), DATA_B => INT_SUM(600), DATA_C => INT_CARRY(470),
SAVE => INT_SUM(601), CARRY => INT_CARRY(475)
);
---- End FA stage
---- Begin HA stage
HA_49:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(601), DATA_B => INT_CARRY(471),
SAVE => SUM(58), CARRY => CARRY(58)
);
---- End HA stage
-- End WT-branch 59
-- Begin WT-branch 60
---- Begin FA stage
FA_484:FULL_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(605), DATA_B => SUMMAND(606), DATA_C => SUMMAND(607),
SAVE => INT_SUM(602), CARRY => INT_CARRY(476)
);
---- End FA stage
---- Begin HA stage
HA_50:HALF_ADDER -- At Level 3
port map
(
DATA_A => SUMMAND(608), DATA_B => SUMMAND(609),
SAVE => INT_SUM(603), CARRY => INT_CARRY(477)
);
---- End HA stage
---- Begin FA stage
FA_485:FULL_ADDER -- At Level 4
port map
(
DATA_A => INT_SUM(602), DATA_B => INT_SUM(603), DATA_C => INT_CARRY(472),
SAVE => INT_SUM(604), CARRY => INT_CARRY(478)
);
---- End FA stage
---- Begin NO stage
INT_SUM(605) <= INT_CARRY(473); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_486:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(604), DATA_B => INT_SUM(605), DATA_C => INT_CARRY(474),
SAVE => INT_SUM(606), CARRY => INT_CARRY(479)
);
---- End FA stage
---- Begin HA stage
HA_51:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(606), DATA_B => INT_CARRY(475),
SAVE => SUM(59), CARRY => CARRY(59)
);
---- End HA stage
-- End WT-branch 60
-- Begin WT-branch 61
---- Begin FA stage
FA_487:FULL_ADDER -- At Level 4
port map
(
DATA_A => SUMMAND(610), DATA_B => SUMMAND(611), DATA_C => SUMMAND(612),
SAVE => INT_SUM(607), CARRY => INT_CARRY(480)
);
---- End FA stage
---- Begin FA stage
FA_488:FULL_ADDER -- At Level 4
port map
(
DATA_A => SUMMAND(613), DATA_B => INT_CARRY(476), DATA_C => INT_CARRY(477),
SAVE => INT_SUM(608), CARRY => INT_CARRY(481)
);
---- End FA stage
---- Begin FA stage
FA_489:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(607), DATA_B => INT_SUM(608), DATA_C => INT_CARRY(478),
SAVE => INT_SUM(609), CARRY => INT_CARRY(482)
);
---- End FA stage
---- Begin HA stage
HA_52:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(609), DATA_B => INT_CARRY(479),
SAVE => SUM(60), CARRY => CARRY(60)
);
---- End HA stage
-- End WT-branch 61
-- Begin WT-branch 62
---- Begin FA stage
FA_490:FULL_ADDER -- At Level 4
port map
(
DATA_A => SUMMAND(614), DATA_B => SUMMAND(615), DATA_C => SUMMAND(616),
SAVE => INT_SUM(610), CARRY => INT_CARRY(483)
);
---- End FA stage
---- Begin NO stage
INT_SUM(611) <= SUMMAND(617); -- At Level 4
---- End NO stage
---- Begin FA stage
FA_491:FULL_ADDER -- At Level 5
port map
(
DATA_A => INT_SUM(610), DATA_B => INT_SUM(611), DATA_C => INT_CARRY(480),
SAVE => INT_SUM(612), CARRY => INT_CARRY(484)
);
---- End FA stage
---- Begin NO stage
INT_SUM(613) <= INT_CARRY(481); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_492:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(612), DATA_B => INT_SUM(613), DATA_C => INT_CARRY(482),
SAVE => SUM(61), CARRY => CARRY(61)
);
---- End FA stage
-- End WT-branch 62
-- Begin WT-branch 63
---- Begin FA stage
FA_493:FULL_ADDER -- At Level 4
port map
(
DATA_A => SUMMAND(618), DATA_B => SUMMAND(619), DATA_C => SUMMAND(620),
SAVE => INT_SUM(614), CARRY => INT_CARRY(485)
);
---- End FA stage
---- Begin NO stage
INT_SUM(615) <= INT_SUM(614); -- At Level 5
---- End NO stage
---- Begin NO stage
INT_SUM(616) <= INT_CARRY(483); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_494:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(615), DATA_B => INT_SUM(616), DATA_C => INT_CARRY(484),
SAVE => SUM(62), CARRY => CARRY(62)
);
---- End FA stage
-- End WT-branch 63
-- Begin WT-branch 64
---- Begin FA stage
FA_495:FULL_ADDER -- At Level 5
port map
(
DATA_A => SUMMAND(621), DATA_B => SUMMAND(622), DATA_C => SUMMAND(623),
SAVE => INT_SUM(617), CARRY => INT_CARRY(486)
);
---- End FA stage
---- Begin NO stage
INT_SUM(618) <= INT_CARRY(485); -- At Level 5
---- End NO stage
---- Begin HA stage
HA_53:HALF_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(617), DATA_B => INT_SUM(618),
SAVE => SUM(63), CARRY => CARRY(63)
);
---- End HA stage
-- End WT-branch 64
-- Begin WT-branch 65
---- Begin NO stage
INT_SUM(619) <= SUMMAND(624); -- At Level 5
---- End NO stage
---- Begin NO stage
INT_SUM(620) <= SUMMAND(625); -- At Level 5
---- End NO stage
---- Begin FA stage
FA_496:FULL_ADDER -- At Level 6
port map
(
DATA_A => INT_SUM(619), DATA_B => INT_SUM(620), DATA_C => INT_CARRY(486),
SAVE => SUM(64), CARRY => CARRY(64)
);
---- End FA stage
-- End WT-branch 65
-- Begin WT-branch 66
---- Begin HA stage
HA_54:HALF_ADDER -- At Level 6
port map
(
DATA_A => SUMMAND(626), DATA_B => SUMMAND(627),
SAVE => SUM(65), CARRY => CARRY(65)
);
---- End HA stage
-- End WT-branch 66
-- Begin WT-branch 67
---- Begin NO stage
SUM(66) <= SUMMAND(628); -- At Level 6
---- End NO stage
-- End WT-branch 67
end WALLACE;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity MULTIPLIER_34_34 is
generic (mulpipe : integer := 0);
port
(
MULTIPLICAND: in std_logic_vector(0 to 33);
MULTIPLIER: in std_logic_vector(0 to 33);
PHI: in std_logic;
holdn: in std_logic;
RESULT: out std_logic_vector(0 to 127)
);
end MULTIPLIER_34_34;
architecture MULTIPLIER of MULTIPLIER_34_34 is
signal PPBIT:std_logic_vector(0 to 628);
signal INT_CARRY: std_logic_vector(0 to 128);
signal INT_SUM: std_logic_vector(0 to 127);
signal LOGIC_ZERO: std_logic;
signal INT_CARRYR: std_logic_vector(0 to 128);
signal INT_SUMR: std_logic_vector(0 to 127);
begin -- Architecture
LOGIC_ZERO <= '0';
B:BOOTHCODER_34_34
port map
(
OPA(0 to 33) => MULTIPLICAND(0 to 33),
OPB(0 to 33) => MULTIPLIER(0 to 33),
SUMMAND(0 to 628) => PPBIT(0 to 628)
);
W:WALLACE_34_34
port map
(
SUMMAND(0 to 628) => PPBIT(0 to 628),
CARRY(0 to 65) => INT_CARRY(1 to 66),
SUM(0 to 66) => INT_SUM(0 to 66)
);
INT_CARRY(0) <= LOGIC_ZERO;
INT_CARRY(67) <= LOGIC_ZERO;
INT_CARRY(68) <= LOGIC_ZERO;
INT_CARRY(69) <= LOGIC_ZERO;
INT_CARRY(70) <= LOGIC_ZERO;
INT_CARRY(71) <= LOGIC_ZERO;
INT_CARRY(72) <= LOGIC_ZERO;
INT_CARRY(73) <= LOGIC_ZERO;
INT_CARRY(74) <= LOGIC_ZERO;
INT_CARRY(75) <= LOGIC_ZERO;
INT_CARRY(76) <= LOGIC_ZERO;
INT_CARRY(77) <= LOGIC_ZERO;
INT_CARRY(78) <= LOGIC_ZERO;
INT_CARRY(79) <= LOGIC_ZERO;
INT_CARRY(80) <= LOGIC_ZERO;
INT_CARRY(81) <= LOGIC_ZERO;
INT_CARRY(82) <= LOGIC_ZERO;
INT_CARRY(83) <= LOGIC_ZERO;
INT_CARRY(84) <= LOGIC_ZERO;
INT_CARRY(85) <= LOGIC_ZERO;
INT_CARRY(86) <= LOGIC_ZERO;
INT_CARRY(87) <= LOGIC_ZERO;
INT_CARRY(88) <= LOGIC_ZERO;
INT_CARRY(89) <= LOGIC_ZERO;
INT_CARRY(90) <= LOGIC_ZERO;
INT_CARRY(91) <= LOGIC_ZERO;
INT_CARRY(92) <= LOGIC_ZERO;
INT_CARRY(93) <= LOGIC_ZERO;
INT_CARRY(94) <= LOGIC_ZERO;
INT_CARRY(95) <= LOGIC_ZERO;
INT_CARRY(96) <= LOGIC_ZERO;
INT_CARRY(97) <= LOGIC_ZERO;
INT_CARRY(98) <= LOGIC_ZERO;
INT_CARRY(99) <= LOGIC_ZERO;
INT_CARRY(100) <= LOGIC_ZERO;
INT_CARRY(101) <= LOGIC_ZERO;
INT_CARRY(102) <= LOGIC_ZERO;
INT_CARRY(103) <= LOGIC_ZERO;
INT_CARRY(104) <= LOGIC_ZERO;
INT_CARRY(105) <= LOGIC_ZERO;
INT_CARRY(106) <= LOGIC_ZERO;
INT_CARRY(107) <= LOGIC_ZERO;
INT_CARRY(108) <= LOGIC_ZERO;
INT_CARRY(109) <= LOGIC_ZERO;
INT_CARRY(110) <= LOGIC_ZERO;
INT_CARRY(111) <= LOGIC_ZERO;
INT_CARRY(112) <= LOGIC_ZERO;
INT_CARRY(113) <= LOGIC_ZERO;
INT_CARRY(114) <= LOGIC_ZERO;
INT_CARRY(115) <= LOGIC_ZERO;
INT_CARRY(116) <= LOGIC_ZERO;
INT_CARRY(117) <= LOGIC_ZERO;
INT_CARRY(118) <= LOGIC_ZERO;
INT_CARRY(119) <= LOGIC_ZERO;
INT_CARRY(120) <= LOGIC_ZERO;
INT_CARRY(121) <= LOGIC_ZERO;
INT_CARRY(122) <= LOGIC_ZERO;
INT_CARRY(123) <= LOGIC_ZERO;
INT_CARRY(124) <= LOGIC_ZERO;
INT_CARRY(125) <= LOGIC_ZERO;
INT_CARRY(126) <= LOGIC_ZERO;
INT_CARRY(127) <= LOGIC_ZERO;
INT_SUM(67) <= LOGIC_ZERO;
INT_SUM(68) <= LOGIC_ZERO;
INT_SUM(69) <= LOGIC_ZERO;
INT_SUM(70) <= LOGIC_ZERO;
INT_SUM(71) <= LOGIC_ZERO;
INT_SUM(72) <= LOGIC_ZERO;
INT_SUM(73) <= LOGIC_ZERO;
INT_SUM(74) <= LOGIC_ZERO;
INT_SUM(75) <= LOGIC_ZERO;
INT_SUM(76) <= LOGIC_ZERO;
INT_SUM(77) <= LOGIC_ZERO;
INT_SUM(78) <= LOGIC_ZERO;
INT_SUM(79) <= LOGIC_ZERO;
INT_SUM(80) <= LOGIC_ZERO;
INT_SUM(81) <= LOGIC_ZERO;
INT_SUM(82) <= LOGIC_ZERO;
INT_SUM(83) <= LOGIC_ZERO;
INT_SUM(84) <= LOGIC_ZERO;
INT_SUM(85) <= LOGIC_ZERO;
INT_SUM(86) <= LOGIC_ZERO;
INT_SUM(87) <= LOGIC_ZERO;
INT_SUM(88) <= LOGIC_ZERO;
INT_SUM(89) <= LOGIC_ZERO;
INT_SUM(90) <= LOGIC_ZERO;
INT_SUM(91) <= LOGIC_ZERO;
INT_SUM(92) <= LOGIC_ZERO;
INT_SUM(93) <= LOGIC_ZERO;
INT_SUM(94) <= LOGIC_ZERO;
INT_SUM(95) <= LOGIC_ZERO;
INT_SUM(96) <= LOGIC_ZERO;
INT_SUM(97) <= LOGIC_ZERO;
INT_SUM(98) <= LOGIC_ZERO;
INT_SUM(99) <= LOGIC_ZERO;
INT_SUM(100) <= LOGIC_ZERO;
INT_SUM(101) <= LOGIC_ZERO;
INT_SUM(102) <= LOGIC_ZERO;
INT_SUM(103) <= LOGIC_ZERO;
INT_SUM(104) <= LOGIC_ZERO;
INT_SUM(105) <= LOGIC_ZERO;
INT_SUM(106) <= LOGIC_ZERO;
INT_SUM(107) <= LOGIC_ZERO;
INT_SUM(108) <= LOGIC_ZERO;
INT_SUM(109) <= LOGIC_ZERO;
INT_SUM(110) <= LOGIC_ZERO;
INT_SUM(111) <= LOGIC_ZERO;
INT_SUM(112) <= LOGIC_ZERO;
INT_SUM(113) <= LOGIC_ZERO;
INT_SUM(114) <= LOGIC_ZERO;
INT_SUM(115) <= LOGIC_ZERO;
INT_SUM(116) <= LOGIC_ZERO;
INT_SUM(117) <= LOGIC_ZERO;
INT_SUM(118) <= LOGIC_ZERO;
INT_SUM(119) <= LOGIC_ZERO;
INT_SUM(120) <= LOGIC_ZERO;
INT_SUM(121) <= LOGIC_ZERO;
INT_SUM(122) <= LOGIC_ZERO;
INT_SUM(123) <= LOGIC_ZERO;
INT_SUM(124) <= LOGIC_ZERO;
INT_SUM(125) <= LOGIC_ZERO;
INT_SUM(126) <= LOGIC_ZERO;
INT_SUM(127) <= LOGIC_ZERO;
INT_SUMR(67 to 127) <= INT_SUM(67 to 127);
INT_CARRYR(67 to 127) <= INT_CARRY(67 to 127);
INT_CARRYR(0) <= INT_CARRY(0);
reg : if MULPIPE /= 0 generate
process (PHI) begin
if rising_edge(PHI ) then
if (holdn = '1') then
INT_SUMR(0 to 66) <= INT_SUM(0 to 66);
INT_CARRYR(1 to 66) <= INT_CARRY(1 to 66);
end if;
end if;
end process;
end generate;
noreg : if MULPIPE = 0 generate
INT_SUMR(0 to 66) <= INT_SUM(0 to 66);
INT_CARRYR(1 to 66) <= INT_CARRY(1 to 66);
end generate;
D:DBLCADDER_128_128
port map
(
OPA(0 to 127) => INT_SUMR(0 to 127),
OPB(0 to 127) => INT_CARRYR(0 to 127),
CIN => LOGIC_ZERO,
PHI => PHI,
SUM(0 to 127) => RESULT(0 to 127)
);
end MULTIPLIER;
------------------------------------------------------------
-- END: Architectures used with the multiplier
------------------------------------------------------------
--
-- Modgen multiplier created Fri Aug 16 16:35:11 2002
--
------------------------------------------------------------
-- START: Multiplier Entitiy
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- START: Top entity
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity MUL_33_33 is
generic (mulpipe : integer := 0);
port(clk : in std_ulogic;
holdn: in std_ulogic;
X: in std_logic_vector(32 downto 0);
Y: in std_logic_vector(32 downto 0);
P: out std_logic_vector(65 downto 0));
end MUL_33_33;
architecture A of MUL_33_33 is
signal A: std_logic_vector(0 to 33);
signal B: std_logic_vector(0 to 33);
signal Q: std_logic_vector(0 to 127);
begin
U1: MULTIPLIER_34_34 generic map (mulpipe) port map(A,B,CLK, holdn ,Q);
-- std_logic_vector reversals to incorporate decreasing vectors
A(0) <= X(0);
A(1) <= X(1);
A(2) <= X(2);
A(3) <= X(3);
A(4) <= X(4);
A(5) <= X(5);
A(6) <= X(6);
A(7) <= X(7);
A(8) <= X(8);
A(9) <= X(9);
A(10) <= X(10);
A(11) <= X(11);
A(12) <= X(12);
A(13) <= X(13);
A(14) <= X(14);
A(15) <= X(15);
A(16) <= X(16);
A(17) <= X(17);
A(18) <= X(18);
A(19) <= X(19);
A(20) <= X(20);
A(21) <= X(21);
A(22) <= X(22);
A(23) <= X(23);
A(24) <= X(24);
A(25) <= X(25);
A(26) <= X(26);
A(27) <= X(27);
A(28) <= X(28);
A(29) <= X(29);
A(30) <= X(30);
A(31) <= X(31);
A(32) <= X(32);
A(33) <= X(32);
B(0) <= Y(0);
B(1) <= Y(1);
B(2) <= Y(2);
B(3) <= Y(3);
B(4) <= Y(4);
B(5) <= Y(5);
B(6) <= Y(6);
B(7) <= Y(7);
B(8) <= Y(8);
B(9) <= Y(9);
B(10) <= Y(10);
B(11) <= Y(11);
B(12) <= Y(12);
B(13) <= Y(13);
B(14) <= Y(14);
B(15) <= Y(15);
B(16) <= Y(16);
B(17) <= Y(17);
B(18) <= Y(18);
B(19) <= Y(19);
B(20) <= Y(20);
B(21) <= Y(21);
B(22) <= Y(22);
B(23) <= Y(23);
B(24) <= Y(24);
B(25) <= Y(25);
B(26) <= Y(26);
B(27) <= Y(27);
B(28) <= Y(28);
B(29) <= Y(29);
B(30) <= Y(30);
B(31) <= Y(31);
B(32) <= Y(32);
B(33) <= Y(32);
P(0) <= Q(0);
P(1) <= Q(1);
P(2) <= Q(2);
P(3) <= Q(3);
P(4) <= Q(4);
P(5) <= Q(5);
P(6) <= Q(6);
P(7) <= Q(7);
P(8) <= Q(8);
P(9) <= Q(9);
P(10) <= Q(10);
P(11) <= Q(11);
P(12) <= Q(12);
P(13) <= Q(13);
P(14) <= Q(14);
P(15) <= Q(15);
P(16) <= Q(16);
P(17) <= Q(17);
P(18) <= Q(18);
P(19) <= Q(19);
P(20) <= Q(20);
P(21) <= Q(21);
P(22) <= Q(22);
P(23) <= Q(23);
P(24) <= Q(24);
P(25) <= Q(25);
P(26) <= Q(26);
P(27) <= Q(27);
P(28) <= Q(28);
P(29) <= Q(29);
P(30) <= Q(30);
P(31) <= Q(31);
P(32) <= Q(32);
P(33) <= Q(33);
P(34) <= Q(34);
P(35) <= Q(35);
P(36) <= Q(36);
P(37) <= Q(37);
P(38) <= Q(38);
P(39) <= Q(39);
P(40) <= Q(40);
P(41) <= Q(41);
P(42) <= Q(42);
P(43) <= Q(43);
P(44) <= Q(44);
P(45) <= Q(45);
P(46) <= Q(46);
P(47) <= Q(47);
P(48) <= Q(48);
P(49) <= Q(49);
P(50) <= Q(50);
P(51) <= Q(51);
P(52) <= Q(52);
P(53) <= Q(53);
P(54) <= Q(54);
P(55) <= Q(55);
P(56) <= Q(56);
P(57) <= Q(57);
P(58) <= Q(58);
P(59) <= Q(59);
P(60) <= Q(60);
P(61) <= Q(61);
P(62) <= Q(62);
P(63) <= Q(63);
P(64) <= Q(64);
P(65) <= Q(65);
end A;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity ADD32 is
port(X: in std_logic_vector(31 downto 0);
Y: in std_logic_vector(31 downto 0);
CI: in std_logic;
S: out std_logic_vector(31 downto 0);
CO: out std_logic);
end ADD32;
architecture A of ADD32 is
signal A,B,Q: std_logic_vector(0 to 31);
signal CLK: std_logic;
begin
U1: DBLCADDER_32_32 port map(A,B,CI,CLK,Q,CO);
-- std_logic_vector reversals to incorporate decreasing vectors
A(0) <= X(0);
B(0) <= Y(0);
A(1) <= X(1);
B(1) <= Y(1);
A(2) <= X(2);
B(2) <= Y(2);
A(3) <= X(3);
B(3) <= Y(3);
A(4) <= X(4);
B(4) <= Y(4);
A(5) <= X(5);
B(5) <= Y(5);
A(6) <= X(6);
B(6) <= Y(6);
A(7) <= X(7);
B(7) <= Y(7);
A(8) <= X(8);
B(8) <= Y(8);
A(9) <= X(9);
B(9) <= Y(9);
A(10) <= X(10);
B(10) <= Y(10);
A(11) <= X(11);
B(11) <= Y(11);
A(12) <= X(12);
B(12) <= Y(12);
A(13) <= X(13);
B(13) <= Y(13);
A(14) <= X(14);
B(14) <= Y(14);
A(15) <= X(15);
B(15) <= Y(15);
A(16) <= X(16);
B(16) <= Y(16);
A(17) <= X(17);
B(17) <= Y(17);
A(18) <= X(18);
B(18) <= Y(18);
A(19) <= X(19);
B(19) <= Y(19);
A(20) <= X(20);
B(20) <= Y(20);
A(21) <= X(21);
B(21) <= Y(21);
A(22) <= X(22);
B(22) <= Y(22);
A(23) <= X(23);
B(23) <= Y(23);
A(24) <= X(24);
B(24) <= Y(24);
A(25) <= X(25);
B(25) <= Y(25);
A(26) <= X(26);
B(26) <= Y(26);
A(27) <= X(27);
B(27) <= Y(27);
A(28) <= X(28);
B(28) <= Y(28);
A(29) <= X(29);
B(29) <= Y(29);
A(30) <= X(30);
B(30) <= Y(30);
A(31) <= X(31);
B(31) <= Y(31);
S(0) <= Q(0);
S(1) <= Q(1);
S(2) <= Q(2);
S(3) <= Q(3);
S(4) <= Q(4);
S(5) <= Q(5);
S(6) <= Q(6);
S(7) <= Q(7);
S(8) <= Q(8);
S(9) <= Q(9);
S(10) <= Q(10);
S(11) <= Q(11);
S(12) <= Q(12);
S(13) <= Q(13);
S(14) <= Q(14);
S(15) <= Q(15);
S(16) <= Q(16);
S(17) <= Q(17);
S(18) <= Q(18);
S(19) <= Q(19);
S(20) <= Q(20);
S(21) <= Q(21);
S(22) <= Q(22);
S(23) <= Q(23);
S(24) <= Q(24);
S(25) <= Q(25);
S(26) <= Q(26);
S(27) <= Q(27);
S(28) <= Q(28);
S(29) <= Q(29);
S(30) <= Q(30);
S(31) <= Q(31);
end A;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity MUL_17_17 is
generic (mulpipe : integer := 0);
port(clk : in std_ulogic;
holdn: in std_ulogic;
X: in std_logic_vector(16 downto 0);
Y: in std_logic_vector(16 downto 0);
P: out std_logic_vector(33 downto 0));
end MUL_17_17;
architecture A of MUL_17_17 is
signal A: std_logic_vector(0 to 17);
signal B: std_logic_vector(0 to 17);
signal Q: std_logic_vector(0 to 63);
begin
U1: MULTIPLIER_18_18 generic map (mulpipe) port map(A,B,CLK, holdn, Q);
-- std_logic_vector reversals to incorporate decreasing vectors
A(0) <= X(0);
A(1) <= X(1);
A(2) <= X(2);
A(3) <= X(3);
A(4) <= X(4);
A(5) <= X(5);
A(6) <= X(6);
A(7) <= X(7);
A(8) <= X(8);
A(9) <= X(9);
A(10) <= X(10);
A(11) <= X(11);
A(12) <= X(12);
A(13) <= X(13);
A(14) <= X(14);
A(15) <= X(15);
A(16) <= X(16);
A(17) <= X(16);
B(0) <= Y(0);
B(1) <= Y(1);
B(2) <= Y(2);
B(3) <= Y(3);
B(4) <= Y(4);
B(5) <= Y(5);
B(6) <= Y(6);
B(7) <= Y(7);
B(8) <= Y(8);
B(9) <= Y(9);
B(10) <= Y(10);
B(11) <= Y(11);
B(12) <= Y(12);
B(13) <= Y(13);
B(14) <= Y(14);
B(15) <= Y(15);
B(16) <= Y(16);
B(17) <= Y(16);
P(0) <= Q(0);
P(1) <= Q(1);
P(2) <= Q(2);
P(3) <= Q(3);
P(4) <= Q(4);
P(5) <= Q(5);
P(6) <= Q(6);
P(7) <= Q(7);
P(8) <= Q(8);
P(9) <= Q(9);
P(10) <= Q(10);
P(11) <= Q(11);
P(12) <= Q(12);
P(13) <= Q(13);
P(14) <= Q(14);
P(15) <= Q(15);
P(16) <= Q(16);
P(17) <= Q(17);
P(18) <= Q(18);
P(19) <= Q(19);
P(20) <= Q(20);
P(21) <= Q(21);
P(22) <= Q(22);
P(23) <= Q(23);
P(24) <= Q(24);
P(25) <= Q(25);
P(26) <= Q(26);
P(27) <= Q(27);
P(28) <= Q(28);
P(29) <= Q(29);
P(30) <= Q(30);
P(31) <= Q(31);
P(32) <= Q(32);
P(33) <= Q(33);
end A;
|
gpl-2.0
|
ad83c071f7bf56ac0a9a04a2fc28f0c7
| 0.620772 | 2.766757 | false | false | false | false |
rhexsel/cmips
|
cMIPS/altera/tb_cMIPS.vhd
| 1 | 50,996 |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- testbench for classicalMIPS
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
library altera;
use altera.altera_syn_attributes.all;
entity tb_cMIPS is
port
(
-- {ALTERA_IO_BEGIN} DO NOT REMOVE THIS LINE!
clock_50mhz : in std_logic;
clock1_50mhz : in std_logic;
clock2_50mhz : in std_logic;
clock3_50mhz : in std_logic;
gpio0_clkin : in std_logic_vector(1 downto 0);
gpio0_clkout : in std_logic_vector(1 downto 0);
gpio0_d : in std_logic_vector(31 downto 0);
gpio1_clkin : in std_logic_vector(1 downto 0);
gpio1_clkout : in std_logic_vector(1 downto 0);
gpio1_d : in std_logic_vector(31 downto 0);
i2c_overtempn : in std_logic;
i2c_scl : in std_logic;
i2c_sda : in std_logic;
key : in std_logic_vector(11 downto 0);
lcd_backlight : out std_logic;
lcd_d : inout std_logic_vector(7 downto 0);
lcd_en : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic;
ledm_c : in std_logic_vector(4 downto 0);
ledm_r : in std_logic_vector(7 downto 0);
led_r : out std_logic;
led_g : out std_logic;
led_b : out std_logic;
proto_a : in std_logic_vector(7 downto 0);
proto_b : in std_logic_vector(7 downto 0);
sw : in std_logic_vector(3 downto 0);
disp1 : out std_logic_vector (7 downto 0);
disp0 : out std_logic_vector (7 downto 0);
dac_sclk : in std_logic;
dac_din : in std_logic;
dac_clr : in std_logic;
dac_csn : in std_logic;
adc_ub : in std_logic;
adc_sel : in std_logic;
adc_sd : in std_logic;
adc_sclk : in std_logic;
adc_refsel : in std_logic;
adc_dout2 : in std_logic;
adc_dout1 : in std_logic;
adc_csn : in std_logic;
adc_cnvst : in std_logic;
vga_b : in std_logic_vector(3 downto 0);
vga_g : in std_logic_vector(3 downto 0);
vga_r : in std_logic_vector(3 downto 0);
vga_hs : in std_logic;
vga_vs : in std_logic;
uart_cts : in std_logic;
uart_rts : out std_logic;
uart_rxd : in std_logic;
uart_txd : out std_logic;
usb_d : in std_logic_vector(7 downto 0);
usb_powerenn : in std_logic;
usb_rd : in std_logic;
usb_rxfn : in std_logic;
usb_txen : in std_logic;
usb_wr : in std_logic;
sma_clkin : in std_logic;
sma_clkin1 : in std_logic;
sma_clkout : in std_logic;
sd_cdn : in std_logic; -- card plugged in (not connected)
sd_clk : out std_logic; -- serial clk
sd_cmd : in std_logic; -- mosi_i sd_d(3)=cs
sd_d : out std_logic_vector(3 downto 0); -- sd_d(0)=miso_o
eth_col : in std_logic;
eth_crs : in std_logic;
eth_mdc : in std_logic;
eth_mdio : in std_logic;
eth_rstn : in std_logic;
eth_rxc : in std_logic;
eth_rxd : in std_logic_vector(3 downto 0);
eth_rxdv : in std_logic;
eth_rxer : in std_logic;
eth_txc : in std_logic;
eth_txd : in std_logic_vector(3 downto 0);
eth_txen : in std_logic;
eth_txer : in std_logic;
sdram_a : in std_logic_vector(12 downto 0);
sdram_ba : in std_logic_vector(1 downto 0);
sdram_cke : in std_logic;
sdram_clk : in std_logic;
sdram_csn : in std_logic;
sdram_d : in std_logic_vector(15 downto 0);
sdram_ldqm : in std_logic;
sdram_rasn : in std_logic;
sdram_udqm : in std_logic;
sdram_wen : in std_logic;
sdram_casn : in std_logic
-- flash_data0 : in std_logic;
-- flash_dclk : in std_logic;
-- flash_cs0n : out std_logic;
-- flash_asdo : out std_logic
-- {ALTERA_IO_END} DO NOT REMOVE THIS LINE!
);
-- {ALTERA_ATTRIBUTE_BEGIN} DO NOT REMOVE THIS LINE!
-- {ALTERA_ATTRIBUTE_END} DO NOT REMOVE THIS LINE!
end tb_cMIPS;
architecture ppl_type of tb_cMIPS is
-- {ALTERA_COMPONENTS_BEGIN} DO NOT REMOVE THIS LINE!
-- {ALTERA_COMPONENTS_END} DO NOT REMOVE THIS LINE!
component FFD is
port(clk, rst, set, D : in std_logic; Q : out std_logic);
end component FFD;
component SDcard is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic_vector; -- a03, a02
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
sdc_cs : out std_logic; -- SDcard chip-select
sdc_clk : out std_logic; -- SDcard serial clock
sdc_mosi_o : out std_logic; -- SDcard serial data out (to card)
sdc_mosi_i : in std_logic; -- SDcard serial data inp (fro card)
irq : out std_logic); -- interrupt request (not yet used)
end component SDCard;
component LCD_display is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic; -- 0=constrol, 1=data
data_inp : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
LCD_DATA : inout std_logic_vector(7 downto 0); -- bidirectional bus
LCD_RS : out std_logic; -- LCD register select 0=ctrl, 1=data
LCD_RW : out std_logic; -- LCD read=1, 0=write
LCD_EN : out std_logic; -- LCD enable=1
LCD_BLON : out std_logic);
end component LCD_display;
component to_7seg is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector;
display0 : out std_logic_vector;
display1 : out std_logic_vector;
red : out std_logic;
green : out std_logic;
blue : out std_logic);
end component to_7seg;
component read_keys is
generic (DEB_CYCLES : natural);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
data : out reg32;
kbd : in std_logic_vector (11 downto 0);
sw : in std_logic_vector (3 downto 0));
end component read_keys;
component to_stdout is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector);
end component to_stdout;
component from_stdin is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : out std_logic_vector);
end component from_stdin;
component print_data is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector);
end component print_data;
component write_data_file is
generic (OUTPUT_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data : in std_logic_vector;
byte_sel : in std_logic_vector;
dump_ram : out std_logic);
end component write_data_file;
component read_data_file is
generic (INPUT_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector;
byte_sel: in std_logic_vector);
end component read_data_file;
component do_interrupt is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
irq : out std_logic);
end component do_interrupt;
component simple_uart is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
txdat : out std_logic;
rxdat : in std_logic;
rts : out std_logic;
cts : in std_logic;
irq : out std_logic;
bit_rt : out std_logic_vector);-- communication speed - TB only
end component simple_uart;
component FPU is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector);
end component FPU;
component remota is
generic(OUTPUT_FILE_NAME : string; INPUT_FILE_NAME : string);
port(rst, clk : in std_logic;
start : in std_logic;
inpDat : in std_logic; -- serial input
outDat : out std_logic; -- serial output
bit_rt : in std_logic_vector);
end component remota;
component sys_stats is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector;
cnt_dc_ref : in integer;
cnt_dc_rd_hit : in integer;
cnt_dc_wr_hit : in integer;
cnt_dc_flush : in integer;
cnt_ic_ref : in integer;
cnt_ic_hit : in integer);
end component sys_stats;
component ram_addr_decode is
port (rst : in std_logic;
cpu_d_aVal : in std_logic;
addr : in std_logic_vector;
aVal : out std_logic;
dev_select : out std_logic_vector);
end component ram_addr_decode;
component sdram_addr_decode is
port (rst : in std_logic;
cpu_d_aVal : in std_logic;
addr : in std_logic_vector;
aVal : out std_logic;
dev_select : out std_logic_vector);
end component sdram_addr_decode;
component io_addr_decode is
port (rst : in std_logic;
clk : in std_logic;
cpu_d_aVal : in std_logic;
addr : in std_logic_vector;
dev_select : out std_logic_vector;
print_sel : out std_logic;
stdout_sel : out std_logic;
stdin_sel : out std_logic;
read_sel : out std_logic;
write_sel : out std_logic;
counter_sel : out std_logic;
FPU_sel : out std_logic;
uart_sel : out std_logic;
sstats_sel : out std_logic;
dsp7seg_sel : out std_logic;
keybd_sel : out std_logic;
lcd_sel : out std_logic;
sdc_sel : out std_logic;
not_waiting : in std_logic);
end component io_addr_decode;
component busError_addr_decode is
port (rst : in std_logic;
cpu_d_aVal : in std_logic;
addr : in reg32;
d_busError : out std_logic); -- decoded address not in range (act=0)
end component busError_addr_decode;
component inst_addr_decode is
port (rst : in std_logic;
cpu_i_aVal : in std_logic;
addr : in std_logic_vector;
aVal : out std_logic;
i_busError : out std_logic);
end component inst_addr_decode;
component ROM is
generic (LOAD_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
strobe : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector);
end component ROM;
component RAM is
generic (LOAD_FILE_NAME : string; DUMP_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
strobe : in std_logic;
addr : in std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
byte_sel : in std_logic_vector;
dump_ram : in std_logic);
end component RAM;
component SDRAM_controller is
port (rst : in std_logic; -- FPGA reset (=0)
clk : in std_logic; -- CPU clock
clk2x : in std_logic; -- 100MHz clock
sel : in std_logic; -- host side chip select (=0)
rdy : out std_logic; -- tell CPU to wait (=0)
wr : in std_logic; -- host side write enable (=0)
bsel : in reg4; -- byte select
haddr : in reg26; -- host side address
hDinp : in reg32; -- host side data input
hDout : out reg32; -- host side data output
cke : out std_logic; -- ram side clock enable
scs : out std_logic; -- ram side chip select
ras : out std_logic; -- ram side RAS
cas : out std_logic; -- ram side CAS
we : out std_logic; -- ram side write enable
dqm0 : out std_logic; -- ram side byte0 output enable
dqm1 : out std_logic; -- ram side byte0 output enable
ba0 : out std_logic; -- ram side bank select 0
ba1 : out std_logic; -- ram side bank select 1
saddr : out reg12; -- ram side address
sdata : inout reg16); -- ram side data
end component SDRAM_controller;
component I_CACHE is
port (rst : in std_logic;
clk4x : in std_logic;
ic_reset : out std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_addr : in std_logic_vector;
cpu_data : out std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_addr : out std_logic_vector;
mem_data : in std_logic_vector;
ref_cnt : out integer;
hit_cnt : out integer);
end component I_CACHE;
component I_CACHE_fpga is
port (rst : in std_logic;
clk4x : in std_logic;
ic_reset : out std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_addr : in std_logic_vector;
cpu_data : out std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_addr : out std_logic_vector;
mem_data : in std_logic_vector;
ref_cnt : out integer;
hit_cnt : out integer);
end component I_CACHE_fpga;
component D_CACHE is
port (rst : in std_logic;
clk4x : in std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_wr : in std_logic;
cpu_addr : in std_logic_vector;
cpu_data_inp : in std_logic_vector;
cpu_data_out : out std_logic_vector;
cpu_xfer : in std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_wr : out std_logic;
mem_addr : out std_logic_vector;
mem_data_inp : in std_logic_vector;
mem_data_out : out std_logic_vector;
mem_xfer : out std_logic_vector;
ref_cnt : out integer;
rd_hit_cnt : out integer;
wr_hit_cnt : out integer;
flush_cnt : out integer);
end component D_CACHE;
component core is
port (rst : in std_logic;
clk : in std_logic;
phi1 : in std_logic;
phi2 : in std_logic;
phi3 : in std_logic;
i_aVal : out std_logic;
i_wait : in std_logic;
i_addr : out std_logic_vector;
instr : in std_logic_vector;
d_aVal : out std_logic;
d_wait : in std_logic;
d_addr : out std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
wr : out std_logic;
b_sel : out std_logic_vector;
nmi : in std_logic;
irq : in std_logic_vector;
i_busErr : in std_logic;
d_busErr : in std_logic);
end component core;
component mf_altpll port (
inclk0 : IN STD_LOGIC;
c0 : OUT STD_LOGIC;
c1 : OUT STD_LOGIC;
c2 : OUT STD_LOGIC;
c3 : OUT STD_LOGIC;
c4 : OUT STD_LOGIC;
locked : OUT STD_LOGIC);
end component mf_altpll;
component mf_altpll_io port (
areset : IN STD_LOGIC;
inclk0 : IN STD_LOGIC;
c0 : OUT STD_LOGIC;
c1 : OUT STD_LOGIC;
c2 : OUT STD_LOGIC);
end component mf_altpll_io;
component mf_altclkctrl port (
inclk : IN STD_LOGIC;
outclk : OUT STD_LOGIC);
end component mf_altclkctrl;
-- use fake / behavioral
for U_I_CACHE : I_cache use entity work.I_cache(fake);
-- use simulation / rtl
for U_ROM : ROM use entity work.ROM(rtl);
-- use simulation / rtl
for U_RAM : RAM use entity work.RAM(rtl);
-- use fake / behavioral
for U_D_CACHE : D_cache use entity work.D_cache(fake);
-- use fake / rtl
for U_FPU: FPU use entity work.FPU(fake);
-- use fake / simple
for U_SDRAMc : SDRAM_controller
use entity work.SDRAM_controller(fake);
signal clk,clkin,clk_locked,clk_50mhz : std_logic;
signal clk2x, clk4x,clk4x0,clk4x180 : std_logic;
signal phi0,phi1,phi2,phi3,phi0in,phi1in,phi2in,phi3in : std_logic;
signal cpu_i_aVal, cpu_i_wait, wr, cpu_d_aVal, cpu_d_wait : std_logic;
signal rst, ic_reset, cpu_reset : std_logic;
signal a_reset, a_rst0,a_rst1,a_rst2,a_rst3,a_rst4,a_rst5,a_rst6,a_rst7,a_rst8,a_rst9, a_rstA, a_rstB, a_rst :std_logic;
signal nmi, i_busError, d_busError : std_logic;
signal irq : reg6;
signal inst_aVal, inst_wait, rom_rdy : std_logic := '1';
signal data_aVal, data_wait, ram_rdy, mem_wr : std_logic;
signal sdram_aVal, sdram_wait, sdram_wr : std_logic;
signal cpu_xfer, mem_xfer : reg4;
signal dev_select, dev_select_ram, dev_select_io, dev_select_sdram : reg4;
signal io_print_sel : std_logic := '1';
signal io_stdout_sel : std_logic := '1';
signal io_stdin_sel : std_logic := '1';
signal io_write_sel : std_logic := '1';
signal io_read_sel : std_logic := '1';
signal io_counter_sel : std_logic := '1';
signal io_uart_sel : std_logic := '1';
signal io_sstats_sel : std_logic := '1';
signal io_7seg_sel : std_logic := '1';
signal io_keys_sel : std_logic := '1';
signal io_fpu_sel, io_fpu_wait : std_logic := '1';
signal io_lcd_sel, io_lcd_wait : std_logic := '1';
signal io_sdc_sel, io_sdc_wait : std_logic := '1';
signal d_cache_d_out, stdin_d_out, read_d_out, counter_d_out : reg32;
signal fpu_d_out, uart_d_out, sstats_d_out, keybd_d_out : reg32;
signal lcd_d_out, sdc_d_out, sdram_d_out : reg32;
signal hDinp, hDout: reg32;
signal sdcke,sdscs,sdras,sdcas,sdwe,sddqm0,sddqm1,sdba0,sdba1 : std_logic;
signal sdaddr : reg12;
signal sddata : reg16;
signal counter_irq : std_logic;
signal io_wait, not_waiting : std_logic;
signal i_addr,d_addr,p_addr : reg32;
signal datrom, datram_inp,datram_out, cpu_instr : reg32;
signal cpu_data_inp, cpu_data_out, cpu_data : reg32;
signal mem_i_sel, mem_d_sel: std_logic;
signal mem_i_addr, mem_addr, mem_d_addr: reg32;
signal cnt_i_ref,cnt_i_hit : integer;
signal cnt_d_ref,cnt_d_rd_hit,cnt_d_wr_hit,cnt_d_flush : integer;
signal dump_ram : std_logic;
signal uart_irq, start_remota, uart_inp, uart_out, u_rts, u_cts : std_logic;
signal bit_rt : reg3;
signal sdc_mosi_i, sdc_miso_o : std_logic;
begin -- TB
-- {ALTERA_INSTANTIATION_BEGIN} DO NOT REMOVE THIS LINE!
-- {ALTERA_INSTANTIATION_END} DO NOT REMOVE THIS LINE!
pll : mf_altpll port map (inclk0 => clock_50mhz, locked => clk_locked,
c0 => phi0in, c1 => phi1in, c2 => phi2in, c3 => phi3in, c4 => clkin);
-- pll_io : mf_altpll_io port map (areset => rst, inclk0 => clock_50mhz,
-- c0 => clk2x, c1 => clk4x0, c2 => clk4x180);
clk2x <= '0';
clk4x0 <= '0';
clk4x180 <= '0';
mf_altclkctrl_inst_clk : mf_altclkctrl port map (
inclk => clkin, outclk => clk);
mf_altclkctrl_inst_clk4x : mf_altclkctrl port map (
inclk => clk4x180, outclk => clk4x);
mf_altclkctrl_inst_phi0 : mf_altclkctrl port map (
inclk => phi0in, outclk => phi0);
mf_altclkctrl_inst_phi1 : mf_altclkctrl port map (
inclk => phi1in, outclk => phi1);
mf_altclkctrl_inst_phi2 : mf_altclkctrl port map (
inclk => phi2in, outclk => phi2);
mf_altclkctrl_inst_phi3 : mf_altclkctrl port map (
inclk => phi3in, outclk => phi3);
-- synchronize external asynchronous reset = sw(3) at lower left
a_reset <= not(sw(3));
U_SYNC_RESET0: FFD port map (clock_50mhz, a_reset, '1', '1', a_rst0);
U_SYNC_RESET1: FFD port map (clock_50mhz, '1', '1', a_rst0, a_rst1);
U_SYNC_RESET2: FFD port map (clock_50mhz, '1', '1', a_rst1, a_rst2);
-- pulse extender and debounce filter
U_SYNC_RESET3: FFD port map (clock_50mhz, '1','1', a_rst2, a_rst3);
U_SYNC_RESET4: FFD port map (clock_50mhz, '1','1', a_rst3, a_rst4);
U_SYNC_RESET5: FFD port map (clock_50mhz, '1','1', a_rst4, a_rst5);
U_SYNC_RESET6: FFD port map (clock_50mhz, '1','1', a_rst5, a_rst6);
U_SYNC_RESET7: FFD port map (clock_50mhz, '1','1', a_rst6, a_rst7);
a_rst8 <= (a_rst7 or a_rst2) and clk_locked;
-- synchronize reset
U_SYNC_RESET8: FFD port map (clk, '1','1', a_rst8, a_rst9);
U_SYNC_RESET9: FFD port map (clk, '1','1', a_rst9, rst);
-- synchronize cache-resets and external reset to reset the processor
a_rstA <= rst and ic_reset;
U_SYNC_RESETa: FFD port map (clk, rst, '1', a_rstA, a_rstB);
U_SYNC_RESETb: FFD port map (clk, rst, '1', a_rstB, cpu_reset);
cpu_i_wait <= inst_wait;
cpu_d_wait <= data_wait and io_wait; -- and sdram_wait;
io_wait <= io_lcd_wait; -- and io_fpu_wait;
not_waiting <= (inst_wait and data_wait); -- for I/O references
-- irq <= b"000000"; -- NO interrupt requests
-- Count=Compare at IRQ7, UART at IRQ6, extCounter at IRQ5
-- C=C U E 0 0 0 sw1 sw0
irq <= '0' & uart_irq & counter_irq & b"000"; -- uart+counter interrupts
-- irq <= b"00" & counter_irq & b"000"; -- counter interrupts
nmi <= '0'; -- input port to TB
U_CORE: core
port map (cpu_reset, clk, phi1,phi2,phi3,
cpu_i_aVal, cpu_i_wait, i_addr, cpu_instr,
cpu_d_aVal, cpu_d_wait, d_addr, cpu_data_inp, cpu_data,
wr, cpu_xfer, nmi, irq, i_busError, d_busError);
U_INST_ADDR_DEC: inst_addr_decode
port map (rst, cpu_i_aVal, i_addr, inst_aVal, i_busError);
-- U_I_CACHE: i_cache_fpga -- or FPGA implementation
U_I_CACHE: i_cache
port map (rst, clk4x, ic_reset,
inst_aVal, inst_wait, i_addr, cpu_instr,
mem_i_sel, rom_rdy, mem_i_addr, datrom, cnt_i_ref,cnt_i_hit);
U_ROM: ROM generic map ("prog.bin")
port map (rst, clk, mem_i_sel,rom_rdy, phi3, mem_i_addr,datrom);
U_DATA_BUS_ERROR_DEC: busError_addr_decode
port map (rst, cpu_d_aVal, d_addr, d_busError);
-- d_busError <= '1'; -- only while testing the SDRAM
U_IO_ADDR_DEC: io_addr_decode
port map (rst, phi0, cpu_d_aVal, d_addr, dev_select_io,
io_print_sel, io_stdout_sel, io_stdin_sel,io_read_sel,
io_write_sel, io_counter_sel, io_fpu_sel, io_uart_sel,
io_sstats_sel, io_7seg_sel, io_keys_sel, io_lcd_sel,
io_sdc_sel, not_waiting);
U_DATA_ADDR_DEC: ram_addr_decode
port map (rst, cpu_d_aVal, d_addr,data_aVal, dev_select_ram);
U_SDRAM_ADDR_DEC: sdram_addr_decode
port map (rst, cpu_d_aVal, d_addr,sdram_aVal, dev_select_sdram);
dev_select <= dev_select_io or dev_select_ram; -- or dev_select_sdram;
with dev_select select
cpu_data_inp <= d_cache_d_out when b"0001",
-- stdin_d_out when b"0100",
-- read_d_out when b"0101",
counter_d_out when b"0111",
fpu_d_out when b"1000",
uart_d_out when b"1001",
-- sstats_d_out when b"1010",
keybd_d_out when b"1100",
lcd_d_out when b"1101",
sdc_d_out when b"1110",
-- sdram_d_out when b"1110",
(others => 'X') when others;
U_D_CACHE: d_cache
port map (rst, clk4x,
data_aVal, data_wait, wr,
d_addr, cpu_data, d_cache_d_out, cpu_xfer,
mem_d_sel, ram_rdy, mem_wr,
mem_addr, datram_inp, datram_out, mem_xfer,
cnt_d_ref, cnt_d_rd_hit, cnt_d_wr_hit, cnt_d_flush);
U_RAM: RAM generic map ("data.bin", "dump.data")
port map (rst, clk, mem_d_sel, ram_rdy, mem_wr, phi2,
mem_addr, datram_out, datram_inp, mem_xfer, dump_ram);
dump_ram <= '0';
hDinp <= (others => 'X');
U_SDRAMc: SDRAM_controller port map
(rst, clk, clk2x, sdram_aVal, sdram_wait, wr,
cpu_xfer, d_addr(25 downto 0), hDinp,hDout,
sdcke,sdscs,sdras,sdcas,sdwe,sddqm0,sddqm1,sdba0,sdba1,sdaddr,sddata);
sdcke <= '1';
-- U_to_stdout: to_stdout
-- port map (rst,clk, io_stdout_sel, wr, cpu_data);
-- U_from_stdin: from_stdin
-- port map (rst,clk, io_stdin_sel, wr, stdin_d_out);
-- U_read_inp: read_data_file generic map ("input.data")
-- port map (rst,clk, io_read_sel, wr, d_addr, read_d_out, cpu_xfer);
-- U_write_out: write_data_file generic map ("output.data")
-- port map (rst,clk, io_write_sel, wr, d_addr,cpu_data,cpu_xfer,dump_ram);
-- U_print_data: print_data
-- port map (rst,clk, io_print_sel, wr, cpu_data);
U_interrupt_counter: do_interrupt -- external counter+interrupt
port map (rst,clk, io_counter_sel, wr, cpu_data,
counter_d_out, counter_irq);
U_to_7seg: to_7seg
port map (rst,clk,io_7seg_sel, wr, cpu_data, disp0, disp1,
led_r, led_g, led_b);
U_read_keys: read_keys
generic map (17500) -- debouncing interval, in clock cycles
port map (rst,clk, io_keys_sel, keybd_d_out, key, sw);
U_LCD_display: LCD_display
port map (rst, clk, io_lcd_sel, io_lcd_wait,
wr, d_addr(2), cpu_data, lcd_d_out,
lcd_d, lcd_rs, lcd_rw, lcd_en, lcd_backlight);
U_simple_uart: simple_uart
port map (rst,clk, io_uart_sel, wr, d_addr(2), cpu_data, uart_d_out,
uart_txd, uart_rxd, uart_rts, uart_cts, uart_irq, bit_rt);
-- to test in loopback mode, uncoment next line & replace 2nd line for above
-- uart_out, uart_inp, u_rts, u_cts, uart_irq, bit_rt);
-- uart_inp <= uart_out; -- looping back;
-- u_cts <= u_rts;
-- U_uart_remota: remota generic map ("serial.out","serial.inp")
-- port map (rst, clk, start_remota, txdat, rxdat, bit_rt);
U_sdcard: SDcard
port map (rst, clk, io_sdc_sel, io_sdc_wait,
wr, d_addr(3 downto 2), cpu_data, sdc_d_out,
sd_d(3), sd_clk, sdc_miso_o, sdc_mosi_i, open);
-- sd_clk <= sdc_clk; -- serial clock to SD card
-- sd_d(3) <= sdc_cs; -- chip-select (active low)
sd_d(0) <= sdc_miso_o; -- data outputo to SD card
sdc_mosi_i <= sd_cmd; -- data input form SD card
U_FPU: FPU
port map (rst,clk, io_FPU_sel, io_FPU_wait, wr, d_addr(5 downto 2),
cpu_data, fpu_d_out);
-- U_sys_stats: sys_stats -- CPU reads system counters
-- port map (cpu_reset,clk, io_sstats_sel, wr, d_addr, sstats_d_out,
-- cnt_d_ref,cnt_d_rd_hit,cnt_d_wr_hit,cnt_d_flush,
-- cnt_i_ref,cnt_i_hit);
-- U_clock: process -- simulate external clock
-- begin
-- clock_50mhz <= '1';
-- wait for CLOCK_PER / 2;
-- clock_50mhz <= '0';
-- wait for CLOCK_PER / 2;
-- end process; -- -------------------------------------------------------
-- simulate reset switch bounces
-- a_reset <= '1', '0' after 5 ns, '1' after 8 ns, '0' after 12 ns, '1' after 14 ns, '0' after 18 ns, '1' after 25 ns;
end architecture ppl_type;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- instruction address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity inst_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_i_aVal : in std_logic; -- CPU instr addr valid (act=0)
addr : in reg32; -- CPU address
aVal : out std_logic; -- decoded address in range (act=0)
i_busError : out std_logic); -- decoded address not in range (act=0)
end entity inst_addr_decode;
architecture behavioral of inst_addr_decode is
signal in_range : boolean;
begin
in_range <= (addr(HI_SEL_BITS downto LO_SEL_BITS)
=
x_INST_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS));
aVal <= '0' when ( cpu_i_aVal = '0' and in_range ) else
'1';
i_busError <= '0' when ( cpu_i_aVal = '0' and not(in_range) ) else
'1';
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- RAM address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity ram_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
aVal : out std_logic; -- data address (act=0)
dev_select : out reg4); -- select input to CPU
constant LO_ADDR : integer := log2_ceil(DATA_BASE_ADDR);
constant HI_ADDR : integer := log2_ceil(DATA_BASE_ADDR + DATA_MEM_SZ - 1);
constant in_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '1');
constant ng_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '0');
constant oth : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'1');
constant ng_o : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'0');
end entity ram_addr_decode;
architecture behavioral of ram_addr_decode is
-- constant LO_ADDR : natural := log2_ceil(DATA_BASE_ADDR);
-- constant HI_ADDR : natural := log2_ceil(DATA_BASE_ADDR + DATA_MEM_SZ - 1);
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
constant a_hi : std_logic_vector(31 downto HI_ADDR+1) := (others=>'0');
constant a_lo : std_logic_vector(LO_ADDR-1 downto 0) := (others=>'0');
constant a_bits : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'1');
constant a_mask : std_logic_vector := a_hi & a_bits & a_lo;
constant LO_RAM : natural := 0;
constant HI_RAM : natural := log2_ceil(DATA_MEM_SZ-1);
constant r_hi : std_logic_vector(31 downto HI_RAM+1) := (others=>'1');
constant r_lo : std_logic_vector(HI_RAM downto LO_RAM) := (others=>'0');
constant r_mask : std_logic_vector := r_hi & r_lo;
signal in_range : boolean;
begin
-- in_range <= ( ((addr(HI_ADDR downto LO_ADDR) and in_r) /= ng_r) and
-- ((addr(HI_SEL_BITS downto HI_ADDR+1) and oth) = ng_o) );
in_range <= ( addr(HI_SEL_BITS downto LO_SEL_BITS)
=
x_DATA_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS) );
aVal <= '0' when (cpu_d_aVal = '0' and in_range) else '1';
dev_select <= b"0001" when (cpu_d_aVal = '0' and in_range) else b"0000";
assert TRUE -- cpu_d_aVal = '1'
report LF & "e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" LO_AD " & integer'image(LO_ADDR) &
" HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask)
severity NOTE;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- busError address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity busError_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
d_busError : out std_logic); -- decoded address not in range (act=0)
end entity busError_addr_decode;
architecture behavioral of busError_addr_decode is
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
-- I/O constants
constant IO_RANGE : integer := IO_ADDR_RANGE * IO_MAX_NUM_DEVS;
constant LO_DEV : natural := 0;
constant HI_DEV : natural := log2_ceil(IO_RANGE);
constant IO_LO_ADDR : integer := log2_ceil(IO_BASE_ADDR);
constant IO_HI_ADDR : integer := log2_ceil(IO_BASE_ADDR + IO_RANGE - 1);
constant iin_r:std_logic_vector(IO_HI_ADDR downto IO_LO_ADDR) := (others=>'1');
constant ing_r:std_logic_vector(IO_HI_ADDR downto IO_LO_ADDR) := (others=>'0');
constant ioth:std_logic_vector(HI_SEL_BITS downto IO_HI_ADDR+1):=(others=>'1');
constant ing_o:std_logic_vector(HI_SEL_BITS downto IO_HI_ADDR+1):=(others=>'0');
constant x_hi : std_logic_vector(31 downto HI_DEV) := (others=>'1');
constant x_lo : std_logic_vector(HI_DEV-1 downto 0) := (others=>'0');
constant x_mask : std_logic_vector := x_hi & x_lo; -- 1..10..0
-- RAM constants
constant LO_ADDR : natural := log2_ceil(DATA_BASE_ADDR);
constant HI_ADDR : natural := log2_ceil(DATA_BASE_ADDR + DATA_MEM_SZ - 1);
constant a_hi : std_logic_vector(31 downto HI_ADDR+1) := (others=>'0');
constant a_lo : std_logic_vector(LO_ADDR-1 downto 0) := (others=>'0');
constant a_bits : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'1');
constant a_mask : std_logic_vector := a_hi & a_bits & a_lo; -- 0..0110..0
constant LO_RAM : natural := 0;
constant HI_RAM : natural := log2_ceil(DATA_MEM_SZ-1);
constant r_hi : std_logic_vector(31 downto HI_RAM+1) := (others=>'1');
constant r_lo : std_logic_vector(HI_RAM downto LO_RAM) := (others=>'0');
constant r_mask : std_logic_vector := r_hi & r_lo; -- 1..10..0
constant in_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '1');
constant ng_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '0');
constant oth : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'1');
constant ng_o : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'0');
signal in_range, io_in_range : boolean;
begin
-- in_range <= ( ((addr and a_mask) = x_DATA_BASE_ADDR) and
-- ((addr and r_mask) = x_DATA_BASE_ADDR) );
-- io_in_range <= ( ((addr and x_mask) = x_IO_BASE_ADDR) );
in_range <= ( addr(HI_SEL_BITS downto LO_SEL_BITS)
=
x_DATA_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS) );
io_in_range <= (addr(HI_SEL_BITS downto LO_SEL_BITS)
=
x_IO_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS));
-- in_range <= ((addr(HI_ADDR downto LO_ADDR) and in_r) /= ng_r) and
-- ((addr(HI_SEL_BITS downto HI_ADDR+1) and oth) = ng_o);
-- io_in_range <= ((addr(IO_HI_ADDR downto IO_LO_ADDR) and iin_r)/=ing_r)and
-- ((addr(HI_SEL_BITS downto IO_HI_ADDR+1) and ioth) = ing_o);
-- d_busError <= '0' when ( (cpu_d_aVal = '0') and
-- (not(in_range) and not(io_in_range)) ) else '1';
d_busError <= '0' when ( (cpu_d_aVal = '0') and
(not(in_range) and not(io_in_range)) ) else '1';
assert TRUE -- cpu_d_aVal = '1'
report LF &
" e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" LO_AD " & integer'image(LO_ADDR) &
" HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask)
severity NOTE;
assert TRUE -- cpu_d_aVal = '1' and io_busError
report LF &
" e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" x_hi " & SLV2STR(x_hi) &
" x_lo " & SLV2STR(x_lo) &
" x_mask " & SLV32HEX(x_mask) & LF &
" LO_DEV " & integer'image(LO_DEV) &
" HI_DEV " & integer'image(HI_DEV)
severity NOTE;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- I/O address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity io_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
clk : in std_logic; -- clk sparates back-to-back refs
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
dev_select : out reg4; -- select input to CPU
print_sel : out std_logic; -- std_out (integer) (act=0)
stdout_sel : out std_logic; -- std_out (character) (act=0)
stdin_sel : out std_logic; -- std_inp (character) (act=0)
read_sel : out std_logic; -- file read (act=0)
write_sel : out std_logic; -- file write (act=0)
counter_sel : out std_logic; -- interrupt counter (act=0)
FPU_sel : out std_logic; -- floating point unit (act=0)
UART_sel : out std_logic; -- floating point unit (act=0)
SSTATS_sel : out std_logic; -- system statistics (act=0)
dsp7seg_sel : out std_logic; -- 7 segments display (act=0)
keybd_sel : out std_logic; -- telephone keyboard (act=0)
lcd_sel : out std_logic; -- LCD 2x16 char display (act=0)
sdc_sel : out std_logic; -- SDcard reader/writer (act=0)
not_waiting : in std_logic); -- no other device is waiting
end entity io_addr_decode;
architecture behavioral of io_addr_decode is
constant LO_SEL_ADDR : integer := log2_ceil(IO_ADDR_RANGE);
constant IO_RANGE : integer := IO_ADDR_RANGE * IO_MAX_NUM_DEVS;
constant LO_ADDR : integer := log2_ceil(IO_BASE_ADDR);
constant HI_ADDR : integer := log2_ceil(IO_BASE_ADDR + IO_RANGE - 1);
constant in_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '1');
constant ng_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '0');
constant oth : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'1');
constant ng_o : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'0');
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
-- I/O constants
constant LO_DEV : natural := 0;
constant HI_DEV : natural := log2_ceil(IO_RANGE-1);
constant x_hi : std_logic_vector(31 downto HI_DEV) := (others=>'1');
constant x_lo : std_logic_vector(HI_DEV-1 downto 0) := (others=>'0');
constant x_mask : std_logic_vector := x_hi & x_lo; -- 1..10..0
signal in_range : boolean;
signal aVal : std_logic;
signal dev : integer; -- DEBUGGING only
begin
-- in_range <= ((addr and x_mask) = x_IO_BASE_ADDR);
-- in_range <= ((addr(HI_ADDR downto LO_ADDR) and in_r) /= ng_r) and
-- ((addr(HI_SEL_BITS downto HI_ADDR+1) and oth) = ng_o);
in_range <= (addr(HI_SEL_BITS downto LO_SEL_BITS)
=
x_IO_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS));
-- in_range <= ( ((addr(HI_ADDR downto LO_ADDR) and in_r) /= ng_r) and
-- ((addr(HI_SEL_BITS downto HI_ADDR+1) and oth) = ng_o) );
-- dev <= to_integer(signed(addr(HI_SEL_ADDR downto LO_SEL_ADDR)));
dev <= to_integer(signed(addr(IO_ADDR_BITS downto LO_SEL_ADDR)));
aVal <= '0' when ( cpu_d_aVal = '0' and not_waiting = '1' and
in_range ) else '1';
U_decode: process(aVal, addr, dev)
variable dev_sel : reg4;
constant is_noise : integer := 0;
constant is_print : integer := 2;
constant is_stdout : integer := 3;
constant is_stdin : integer := 4;
constant is_read : integer := 5;
constant is_write : integer := 6;
constant is_count : integer := 7;
constant is_FPU : integer := 8;
constant is_UART : integer := 9;
constant is_SSTATS : integer := 10;
constant is_dsp7seg : integer := 11;
constant is_keybd : integer := 12;
constant is_lcd : integer := 13;
constant is_sdc : integer := 14;
begin
print_sel <= '1';
stdout_sel <= '1';
stdin_sel <= '1';
read_sel <= '1';
write_sel <= '1';
counter_sel <= '1';
FPU_sel <= '1';
UART_sel <= '1';
SSTATS_sel <= '1';
dsp7seg_sel <= '1';
keybd_sel <= '1';
lcd_sel <= '1';
sdc_sel <= '1';
case dev is -- to_integer(signed(addr(HI_ADDR downto LO_ADDR))) is
when 0 => dev_sel := std_logic_vector(to_signed(is_print, 4));
print_sel <= aVal;
when 1 => dev_sel := std_logic_vector(to_signed(is_stdout, 4));
stdout_sel <= aVal;
when 2 => dev_sel := std_logic_vector(to_signed(is_stdin, 4));
stdin_sel <= aVal;
when 3 => dev_sel := std_logic_vector(to_signed(is_read, 4));
read_sel <= aVal;
when 4 => dev_sel := std_logic_vector(to_signed(is_write, 4));
write_sel <= aVal;
when 5 => dev_sel := std_logic_vector(to_signed(is_count, 4));
counter_sel <= aVal;
when 6 => dev_sel := std_logic_vector(to_signed(is_FPU, 4));
FPU_sel <= aVal;
when 7 => dev_sel := std_logic_vector(to_signed(is_UART, 4));
UART_sel <= aVal;
when 8 => dev_sel := std_logic_vector(to_signed(is_SSTATS, 4));
SSTATS_sel <= aVal;
when 9 => dev_sel := std_logic_vector(to_signed(is_dsp7seg, 4));
dsp7seg_sel <= aVal;
when 10 => dev_sel := std_logic_vector(to_signed(is_keybd, 4));
keybd_sel <= aVal;
when 11 => dev_sel := std_logic_vector(to_signed(is_lcd, 4));
lcd_sel <= aVal;
when 12 => dev_sel := std_logic_vector(to_signed(is_sdc, 4));
sdc_sel <= aVal;
when others => dev_sel := std_logic_vector(to_signed(is_noise, 4));
end case;
assert TRUE report "IO_addr "& SLV32HEX(addr); -- DEBUG
if aVal = '0' then
dev_select <= dev_sel;
else
dev_select <= std_logic_vector(to_signed(is_noise, 4));
end if;
end process U_decode;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- SDRAM address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity sdram_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
aVal : out std_logic; -- data address (act=0)
dev_select : out reg4); -- select input to CPU
constant LO_ADDR : integer := log2_ceil(SDRAM_BASE_ADDR);
constant HI_ADDR : integer := log2_ceil(SDRAM_BASE_ADDR + SDRAM_MEM_SZ - 1);
constant in_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '1');
constant ng_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '0');
constant oth : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'1');
constant ng_o : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'0');
end entity sdram_addr_decode;
architecture behavioral of sdram_addr_decode is
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
constant a_hi : std_logic_vector(31 downto HI_ADDR+1) := (others=>'0');
constant a_lo : std_logic_vector(LO_ADDR-1 downto 0) := (others=>'0');
constant a_bits : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'1');
constant a_mask : std_logic_vector := a_hi & a_bits & a_lo;
constant LO_RAM : natural := 0;
constant HI_RAM : natural := log2_ceil(SDRAM_MEM_SZ-1);
constant r_hi : std_logic_vector(31 downto HI_RAM+1) := (others=>'1');
constant r_lo : std_logic_vector(HI_RAM downto LO_RAM) := (others=>'0');
constant r_mask : std_logic_vector := r_hi & r_lo;
signal in_range : boolean;
constant SDRAM_ADDR_BOTTOM : natural :=
to_integer(signed(x_SDRAM_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)));
constant SDRAM_ADDR_RANGE : natural :=
(to_integer(signed(x_SDRAM_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)))
+
to_integer(signed(x_SDRAM_MEM_SZ(HI_SEL_BITS downto LO_SEL_BITS))));
constant SDRAM_ADDR_TOP : natural := SDRAM_ADDR_BOTTOM + SDRAM_ADDR_RANGE;
begin
-- this is ONLY acceptable for simulations;
-- computing these differences is TOO expensive for synthesis
in_range <= ( (to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
>=
SDRAM_ADDR_BOTTOM)
and
(to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
<
SDRAM_ADDR_TOP)
);
aVal <= '0' when (cpu_d_aVal = '0' and in_range) else '1';
dev_select <= b"1110" when (cpu_d_aVal = '0' and in_range) else b"0000";
assert TRUE -- cpu_d_aVal = '1'
report "e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" LO_AD " & integer'image(LO_ADDR) &
" HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask)
severity NOTE;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
use work.all;
configuration CFG_TB of TB_CMIPS is
for ppl_type
end for;
end configuration CFG_TB;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
gpl-3.0
|
c7d02b23854b55d7d338086486a93567
| 0.525806 | 3.262282 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/ddr/ddrpkg.vhd
| 1 | 36,380 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: ddrpkg
-- File: ddrpkg.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Components and types for DDR SDRAM controllers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
package ddrpkg is
type ddrctrl_in_type is record
-- Data signals
data : std_logic_vector (127 downto 0);-- data in
cb : std_logic_vector(63 downto 0); -- checkbits in
-- Bus/timing control signals
datavalid : std_logic; -- Data-valid signal (DDR2,LPDDR2,LPDDR3)
writereq : std_logic; -- Write-data request (LPDDR2,LPDDR3)
-- Calibration and configuration
regrdata : std_logic_vector(63 downto 0); -- PHY-specific reg in (DDR2)
end record;
constant ddrctrl_in_none : ddrctrl_in_type :=
((others => '0'), (others => '0'), '0', '0', (others => '0'));
type ddrctrl_out_type is record
-- Control signals to memory
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en (DDR1,DDR2,LPDDR1)
rasn : std_ulogic; -- row addr stb (DDR1,DDR2,LPDDR1)
casn : std_ulogic; -- col addr stb (DDR1,DDR2,LPDDR1)
address : std_logic_vector(14 downto 0); -- address out (DDR1,DDR2,LPDDR1)
ba : std_logic_vector (2 downto 0); -- bank address (DDR1,DDR2,LPDDR1)
odt : std_logic_vector(1 downto 0); -- On Die Termination (DDR2,LPDDR3)
ca : std_logic_vector(19 downto 0); -- Ctrl/Addr bus (LPDDR2,LPDDR3)
-- Data signals
data : std_logic_vector(127 downto 0); -- data out
dqm : std_logic_vector(15 downto 0); -- data i/o mask
cb : std_logic_vector(63 downto 0); -- checkbits
cbdqm : std_logic_vector(7 downto 0); -- checkbits data mask
-- Bus/timing control signals
bdrive : std_ulogic; -- bus drive (DDR1,DDR2,LPDDR1)
qdrive : std_ulogic; -- bus drive (DDR1,DDR2,LPDDR1)
nbdrive : std_ulogic; -- bdrive 1 cycle early (DDR2)
sdck : std_logic_vector(2 downto 0); -- Clock enable (DDR1,LPDDR1,LPDDR2,LPDDR3)
moben : std_logic; -- Mobile DDR mode (DDR1/LPDDR1)
oct : std_logic; -- On Chip Termination (DDR2)
dqs_gate : std_logic; -- DQS gate control (DDR2)
read_pend : std_logic_vector(7 downto 0); -- Read pending within 7...0
-- cycles (not including phy
-- delays) (DDR2,LPDDR2,LPDDR3)
wrpend : std_logic_vector(7 downto 0); -- Write pending (LPDDR2,LPDDR3)
boot : std_ulogic; -- Boot clock selection (LPDDR2,LPDDR3)
-- Calibration and configuration
cal_en : std_logic_vector(7 downto 0); -- enable delay calibration (DDR2)
cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay (DDR2)
cal_pll : std_logic_vector(1 downto 0); -- (enable,inc/dec) pll phase (DDR2)
cal_rst : std_logic; -- calibration reset (DDR2)
conf : std_logic_vector(63 downto 0); -- Conf. interface (DDR1,LPDDR1)
cbcal_en : std_logic_vector(3 downto 0); -- CB enable delay calib (DDR2)
cbcal_inc : std_logic_vector(3 downto 0); -- CB inc/dec delay (DDR2)
regwdata : std_logic_vector(63 downto 0); -- Reg Write data (DDR2)
regwrite : std_logic_vector(1 downto 0); -- Reg write strobe (DDR2)
-- Status outputs to front-end
ce : std_ulogic; -- Error corrected
end record;
constant ddrctrl_out_none : ddrctrl_out_type :=
((others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'),
(others => '0'), (others => '0'), '0', '0', '0', (others => '0'),
'0', '0', '0', (others => '0'), (others => '0'), '0', (others => '0'),
(others => '0'), (others => '0'), '0', (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'), '0' );
-----------------------------------------------------------------------------
-- DDR2SPA types and components
-----------------------------------------------------------------------------
-- DDR2 controller without PHY
component ddr2spax is
generic (
memtech : integer := 0;
phytech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
TRFC : integer := 130;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0;
octen : integer := 0;
dqsgating : integer := 0;
nosync : integer := 0;
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
dqsse : integer range 0 to 1 := 0; -- single ended DQS
ddr_syncrst: integer range 0 to 1 := 0;
ahbbits : integer := ahbdw;
ft : integer range 0 to 1 := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
hwidthen : integer range 0 to 1 := 0;
rstdel : integer := 200;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
ahb_rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
hwidth : in std_ulogic
);
end component;
-- DDR2 controller with PHY
component ddr2spa
generic (
fabtech : integer := 0;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
TRFC : integer := 130;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50;
readdly : integer := 1;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1 : integer := 0;
cbdelayb2 : integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0;
octen : integer := 0;
dqsgating : integer := 0;
nosync : integer := 0;
eightbanks : integer := 0;
dqsse : integer range 0 to 1 := 0;
burstlen : integer range 4 to 128 := 8;
ahbbits : integer := ahbdw;
ft : integer range 0 to 1 := 0;
ftbits : integer := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
nclk : integer range 1 to 3 := 3;
scantest : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clkref200 : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((ddrbits+ftbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((ddrbits+ftbits)/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector ((ddrbits+ftbits)/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits+ftbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
ce : out std_logic
);
end component;
-- DDR2 PHY with just data or checkbits+data on same bus, including pads
component ddr2phy_wrap_cbd is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2 ;
clk_div : integer := 2;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1 : integer := 0;
cbdelayb2 : integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0;
rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
ctrl2en : integer := 0;
resync : integer := 0;
custombits : integer := 8;
extraio : integer := 0;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (extraio+(dbits+padbits+chkbits)/8-1 downto 0);-- ddr dqs
ddr_dqsn : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
-- DDR2 PHY with just data or checkbits+data on same bus, not including pads
component ddr2phy_wrap_cbd_wo_pads is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2 ;
clk_div : integer := 2;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1: integer := 0;
cbdelayb2: integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0;
rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
resync : integer := 0;
custombits : integer := 8;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
-- DDR2 PHY with separate checkbit and data buses, including pads
component ddr2phy_wrap
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2;
clk_div : integer := 2;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1 : integer := 0;
cbdelayb2 : integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
cben : integer := 0;
chkbits : integer := 8;
ctrl2en : integer := 0;
resync : integer := 0;
custombits : integer := 8;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
ddr_cbdm : out std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdqs : inout std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdqsn : inout std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdq : inout std_logic_vector(chkbits-1 downto 0);
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
-----------------------------------------------------------------------------
-- DDRSPA types and components
-----------------------------------------------------------------------------
-- DDR/LPDDR controller, without PHY
component ddr1spax is
generic (
memtech : integer := 0;
phytech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
nosync : integer := 0;
ddr_syncrst: integer range 0 to 1 := 0;
ahbbits : integer := ahbdw;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
regoutput : integer := 0;
ft : integer := 0;
ddr400 : integer := 1;
rstdel : integer := 200;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
ahb_rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type
);
end component;
-- DDR/LPDDR controller with PHY
component ddrspa
generic (
fabtech : integer := 0;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
regoutput : integer range 0 to 1 := 0;
ddr400 : integer := 1;
scantest : integer := 0;
phyiconf : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits-1 downto 0) -- ddr data
);
end component;
-- DDR/LPDDR PHY, including pads
component ddrphy_wrap
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
clk_mul : integer := 2;
clk_div : integer := 2;
rskew : integer := 0;
mobile : integer := 0;
scantest : integer := 0;
phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic;
clkread : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0);-- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
-- DDR/LPDDR PHY with data and checkbits on same bus, including pads
component ddrphy_wrap_cbd is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
chkbits : integer := 0;
padbits : integer := 0;
clk_mul : integer := 2;
clk_div : integer := 2;
rskew : integer := 0;
mobile : integer := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
scantest : integer := 0;
phyiconf : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkread : out std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
-- DDR/LPDDR PHY with data and checkbits on same bus, without pads
component ddrphy_wrap_cbd_wo_pads is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2;
clk_div : integer := 2;
rskew : integer := 0;
mobile : integer := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
component lpddr2phy_wrap_cbd_wo_pads is
generic (
tech : integer := virtex2;
dbits : integer := 16;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
padbits : integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic; -- input clock
clkin2 : in std_ulogic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkout2 : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0); -- ddr cmd/addr
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0);
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
-----------------------------------------------------------------------------
-- Other components using DDRxSPA sub-components
-----------------------------------------------------------------------------
type ddravl_slv_in_type is record
burstbegin : std_ulogic;
addr : std_logic_vector(31 downto 0);
wdata : std_logic_vector(256 downto 0);
be : std_logic_vector(32 downto 0);
read_req : std_ulogic;
write_req : std_ulogic;
size : std_logic_vector(3 downto 0);
end record;
type ddravl_slv_out_type is record
ready : std_ulogic;
rdata_valid : std_ulogic;
rdata : std_logic_vector(256 downto 0);
end record;
constant ddravl_slv_in_none: ddravl_slv_in_type :=
('0',(others => '0'),(others => '0'),(others => '0'),'0','0',(others => '0'));
component ahb2avl_async is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
avldbits : integer := 32;
avlabits : integer := 20
);
port (
rst_ahb : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
rst_avl : in std_ulogic;
clk_avl : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type
);
end component;
end package;
|
gpl-2.0
|
3f958d315eaa5e861d42a7cc67b8d277
| 0.495217 | 3.807829 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-avnet-xc2v1500/ahbrom.vhd
| 3 | 8,186 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 464;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03002040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"83480000";
when 16#0002D# => romdata <= X"8330600C";
when 16#0002E# => romdata <= X"80886001";
when 16#0002F# => romdata <= X"02800019";
when 16#00030# => romdata <= X"01000000";
when 16#00031# => romdata <= X"07000000";
when 16#00032# => romdata <= X"8610E118";
when 16#00033# => romdata <= X"C108C000";
when 16#00034# => romdata <= X"C118C000";
when 16#00035# => romdata <= X"C518C000";
when 16#00036# => romdata <= X"C918C000";
when 16#00037# => romdata <= X"CD18E008";
when 16#00038# => romdata <= X"D118C000";
when 16#00039# => romdata <= X"D518C000";
when 16#0003A# => romdata <= X"D918C000";
when 16#0003B# => romdata <= X"DD18C000";
when 16#0003C# => romdata <= X"E118C000";
when 16#0003D# => romdata <= X"E518C000";
when 16#0003E# => romdata <= X"E918C000";
when 16#0003F# => romdata <= X"ED18C000";
when 16#00040# => romdata <= X"F118C000";
when 16#00041# => romdata <= X"F518C000";
when 16#00042# => romdata <= X"F918C000";
when 16#00043# => romdata <= X"10800005";
when 16#00044# => romdata <= X"FD18C000";
when 16#00045# => romdata <= X"01000000";
when 16#00046# => romdata <= X"00000000";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"87444000";
when 16#00049# => romdata <= X"8730E01C";
when 16#0004A# => romdata <= X"8688E00F";
when 16#0004B# => romdata <= X"12800015";
when 16#0004C# => romdata <= X"03200000";
when 16#0004D# => romdata <= X"05040E00";
when 16#0004E# => romdata <= X"8410A2FF";
when 16#0004F# => romdata <= X"C4204000";
when 16#00050# => romdata <= X"0539AE1B";
when 16#00051# => romdata <= X"8410A265";
when 16#00052# => romdata <= X"C4206004";
when 16#00053# => romdata <= X"050003FC";
when 16#00054# => romdata <= X"C4206008";
when 16#00055# => romdata <= X"82103860";
when 16#00056# => romdata <= X"C4004000";
when 16#00057# => romdata <= X"8530A00C";
when 16#00058# => romdata <= X"03000004";
when 16#00059# => romdata <= X"82106009";
when 16#0005A# => romdata <= X"80A04002";
when 16#0005B# => romdata <= X"12800005";
when 16#0005C# => romdata <= X"03200000";
when 16#0005D# => romdata <= X"0539A81B";
when 16#0005E# => romdata <= X"8410A265";
when 16#0005F# => romdata <= X"C4204000";
when 16#00060# => romdata <= X"05000008";
when 16#00061# => romdata <= X"82100000";
when 16#00062# => romdata <= X"80A0E000";
when 16#00063# => romdata <= X"02800005";
when 16#00064# => romdata <= X"01000000";
when 16#00065# => romdata <= X"82004002";
when 16#00066# => romdata <= X"10BFFFFC";
when 16#00067# => romdata <= X"8620E001";
when 16#00068# => romdata <= X"3D1003FF";
when 16#00069# => romdata <= X"BC17A3E0";
when 16#0006A# => romdata <= X"BC278001";
when 16#0006B# => romdata <= X"9C27A060";
when 16#0006C# => romdata <= X"03100000";
when 16#0006D# => romdata <= X"81C04000";
when 16#0006E# => romdata <= X"01000000";
when 16#0006F# => romdata <= X"01000000";
when 16#00070# => romdata <= X"00000000";
when 16#00071# => romdata <= X"00000000";
when 16#00072# => romdata <= X"00000000";
when 16#00073# => romdata <= X"00000000";
when 16#00074# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
gpl-2.0
|
bab2dfca78794977bbc366e7dc35913d
| 0.585634 | 3.29284 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/inferred/memory_inferred.vhd
| 1 | 12,179 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: memory_inferred.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Behavioural memory generators
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic
);
end;
architecture behavioral of generic_syncram is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra : std_logic_vector((abits -1) downto 0);
begin
main : process(clk)
begin
if rising_edge(clk) then
if write = '1' then
memarr(conv_integer(address)) <= datain;
end if;
ra <= address;
end if;
end process;
dataout <= memarr(conv_integer(ra));
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram_reg is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic
);
end;
architecture behavioral of generic_syncram_reg is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra : std_logic_vector((abits -1) downto 0);
attribute syn_ramstyle : string;
attribute syn_ramstyle of memarr : signal is "registers";
begin
main : process(clk)
begin
if rising_edge(clk) then
if write = '1' then
memarr(conv_integer(address)) <= datain;
end if;
ra <= address;
end if;
end process;
dataout <= memarr(conv_integer(ra));
end;
-- synchronous 2-port ram, common clock
LIBRARY ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram_2p is
generic (
abits : integer := 8;
dbits : integer := 32;
sepclk: integer := 0
);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of generic_syncram_2p is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
signal rfd : dregtype;
begin
wp : process(wclk)
begin
if rising_edge(wclk) then
if wren = '1' then rfd(conv_integer(wraddress)) <= data; end if;
end if;
end process;
oneclk : if sepclk = 0 generate
rp : process(wclk) begin
if rising_edge(wclk) then q <= rfd(conv_integer(rdaddress)); end if;
end process;
end generate;
twoclk : if sepclk = 1 generate
rp : process(rclk) begin
if rising_edge(rclk) then q <= rfd(conv_integer(rdaddress)); end if;
end process;
end generate;
end;
-- synchronous 2-port ram, common clock, flip-flops
LIBRARY ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram_2p_reg is
generic (
abits : integer := 8;
dbits : integer := 32;
sepclk: integer := 0
);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of generic_syncram_2p_reg is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
signal rfd : dregtype;
signal wa, ra : std_logic_vector (abits -1 downto 0);
attribute syn_ramstyle : string;
attribute syn_ramstyle of rfd : signal is "registers";
begin
wp : process(wclk)
begin
if rising_edge(wclk) then
if wren = '1' then rfd(conv_integer(wraddress)) <= data; end if;
end if;
end process;
oneclk : if sepclk = 0 generate
rp : process(wclk) begin
if rising_edge(wclk) then ra <= rdaddress; end if;
end process;
end generate;
twoclk : if sepclk = 1 generate
rp : process(rclk) begin
if rising_edge(rclk) then ra <= rdaddress; end if;
end process;
end generate;
q <= rfd(conv_integer(ra));
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_regfile_3p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32;
wrfst : integer := 0; numregs : integer := 40; delout: integer := 0);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
pre1 : out std_ulogic;
pre2 : out std_ulogic;
prdata1 : out std_logic_vector((dbits -1) downto 0);
prdata2 : out std_logic_vector((dbits -1) downto 0)
);
end;
architecture rtl of generic_regfile_3p is
type mem is array(0 to numregs-1)
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra1, ra2, wa : std_logic_vector((abits -1) downto 0);
signal din : std_logic_vector((dbits -1) downto 0);
signal wr : std_ulogic;
signal re1d,re1dd,re2d,re2dd: std_ulogic;
signal rdata1i,rdata2i,rdata1d,rdata2d: std_logic_vector(dbits-1 downto 0);
begin
main : process(wclk)
begin
if rising_edge(wclk) then
din <= wdata; wr <= we;
if (we = '1')
-- pragma translate_off
and (conv_integer(waddr) < numregs)
-- pragma translate_on
then wa <= waddr; end if;
if (re1 = '1')
-- pragma translate_off
and (conv_integer(raddr1) < numregs)
-- pragma translate_on
then ra1 <= raddr1; end if;
if (re2 = '1')
-- pragma translate_off
and (conv_integer(raddr2) < numregs)
-- pragma translate_on
then ra2 <= raddr2; end if;
if wr = '1' then
memarr(conv_integer(wa)) <= din;
end if;
end if;
end process;
rdata1i <= din when (wr = '1') and (wa = ra1) and (wrfst = 1)
else memarr(conv_integer(ra1));
rdata2i <= din when (wr = '1') and (wa = ra2) and (wrfst = 1)
else memarr(conv_integer(ra2));
rdata1 <= rdata1i;
rdata2 <= rdata2i;
delgen: if delout /= 0 generate
p: process(wclk)
begin
if rising_edge(wclk) then
re1d <= re1;
re2d <= re2;
re1dd <= re1d;
re2dd <= re2d;
rdata1d <= rdata1i;
rdata2d <= rdata2i;
end if;
end process;
end generate;
ndelgen: if delout=0 generate
re1d <= '0'; re2d <= '0';
re1dd <= '0'; re2dd <= '0';
rdata1d <= (others => '0');
rdata2d <= (others => '0');
end generate;
pre1 <= re1dd;
pre2 <= re2dd;
prdata1 <= rdata1d;
prdata2 <= rdata2d;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_regfile_4p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32;
wrfst : integer := 0; numregs : integer := 40; g0addr: integer := 0;
delout : integer := 0);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
raddr3 : in std_logic_vector((abits -1) downto 0);
re3 : in std_ulogic;
rdata3 : out std_logic_vector((dbits -1) downto 0);
pre1 : out std_ulogic;
pre2 : out std_ulogic;
pre3 : out std_ulogic;
prdata1 : out std_logic_vector((dbits -1) downto 0);
prdata2 : out std_logic_vector((dbits -1) downto 0);
prdata3 : out std_logic_vector((dbits -1) downto 0)
);
end;
architecture rtl of generic_regfile_4p is
type mem is array(0 to numregs-1)
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra1, ra2, ra3, wa : std_logic_vector((abits -1) downto 0);
signal din : std_logic_vector((dbits -1) downto 0);
signal wr : std_ulogic;
signal re1d,re1dd,re2d,re2dd,re3d,re3dd: std_ulogic;
signal rdata1i,rdata2i,rdata3i,rdata1d,rdata2d,rdata3d: std_logic_vector(dbits-1 downto 0);
begin
main : process(wclk)
begin
if rising_edge(wclk) then
din <= wdata; wr <= we;
if (we = '1')
-- pragma translate_off
and (conv_integer(waddr) < numregs)
-- pragma translate_on
then wa <= waddr; end if;
if (re1 = '1')
-- pragma translate_off
and (conv_integer(raddr1) < numregs)
-- pragma translate_on
then ra1 <= raddr1; end if;
if (re2 = '1')
-- pragma translate_off
and (conv_integer(raddr2) < numregs)
-- pragma translate_on
then ra2 <= raddr2; end if;
if (re3 = '1')
-- pragma translate_off
and (conv_integer(raddr3) < numregs)
-- pragma translate_on
then ra3 <= raddr3; end if;
if wr = '1' then
memarr(conv_integer(wa)) <= din;
end if;
if g0addr > 0 and g0addr < numregs then
memarr(g0addr) <= (others => '0');
end if;
end if;
end process;
rdata1i <= din when (wr = '1') and (wa = ra1) and (wrfst = 1)
else memarr(conv_integer(ra1));
rdata2i <= din when (wr = '1') and (wa = ra2) and (wrfst = 1)
else memarr(conv_integer(ra2));
rdata3i <= din when (wr = '1') and (wa = ra3) and (wrfst = 1)
else memarr(conv_integer(ra3));
rdata1 <= rdata1i;
rdata2 <= rdata2i;
rdata3 <= rdata3i;
delgen: if delout /= 0 generate
p: process(wclk)
begin
if rising_edge(wclk) then
re1d <= re1;
re2d <= re2;
re3d <= re3;
re1dd <= re1d;
re2dd <= re2d;
re3dd <= re3d;
rdata1d <= rdata1i;
rdata2d <= rdata2i;
rdata3d <= rdata3i;
end if;
end process;
end generate;
ndelgen: if delout=0 generate
re1d <= '0'; re2d <= '0'; re3d <= '0';
re1dd <= '0'; re2dd <= '0'; re3dd <= '0';
rdata1d <= (others => '0');
rdata2d <= (others => '0');
rdata3d <= (others => '0');
end generate;
pre1 <= re1dd;
pre2 <= re2dd;
pre3 <= re3dd;
prdata1 <= rdata1d;
prdata2 <= rdata2d;
prdata3 <= rdata3d;
end;
|
gpl-2.0
|
1c8a47c48bf4f403320ab33138894f17
| 0.60785 | 3.221106 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/can/can_rd.vhd
| 1 | 6,744 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_rd is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
dmap : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(1 downto 0);
can_txo : out std_logic_vector(1 downto 0)
);
end;
architecture rtl of can_rd is
constant ncores : integer := 1;
constant sepirq : integer := 0;
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
muxsel : std_logic;
writemux : std_logic;
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal addr : std_logic_vector(7 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
signal can_lrxi, can_ltxo : std_logic;
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
variable vmuxreg : std_logic;
variable hwdata : std_logic_vector(31 downto 0);
begin
v := r;
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1));
vmuxreg := not r.haddr(7) and r.haddr(6);
--v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
-- and not r.ws(0) and not r.herr;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr and not vmuxreg;
v.writemux := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and vmuxreg;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := hwdata(31 downto 24);
when "01" => v.hwdata := hwdata(23 downto 16);
when "10" => v.hwdata := hwdata(15 downto 8);
when others => v.hwdata := hwdata(7 downto 0);
end case;
--dataout := data_out(0);
if r.haddr(7 downto 6) = "01" then
dataout := (others => r.muxsel);
if r.writemux = '1' then
v.muxsel := r.hwdata(0);
end if;
else
dataout := data_out(0);
end if;
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= ahbdrivedata(dataout);
ahbso.hresp <= hresp; rin <= v;
end process;
-- Double mapping of registers [byte (offset 0), word (offset 0x80)]
dmap0 : if dmap = 0 generate
addr <= r.haddr(7 downto 0);
end generate;
dmap1 : if dmap = 1 generate
addr <= "000"&r.haddr(6 downto 2) when r.haddr(7) = '1' else
r.haddr(7 downto 0);
end generate;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cmod : can_mod generic map (memtech, syncrst)
--port map (reset, clk, r.hsel, r.hwrite2, r.haddr(7 downto 0), r.hwdata,
port map (reset, clk, r.hsel, r.hwrite2, addr, r.hwdata,
data_out(0), irqo(0), can_lrxi, can_ltxo, ahbsi.testen);
cmux : canmux port map (r.muxsel, can_lrxi, can_ltxo, can_rxi, can_txo);
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, revision " & tost(REVISION) &
", irq " & tost(irq));
-- pragma translate_on
end;
|
gpl-2.0
|
8d4692b3770c130cfa2756aada3f23bc
| 0.595196 | 3.412955 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-gr-xc6s/testbench.vhd
| 1 | 12,972 |
----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(24 downto 0);
signal data : std_logic_vector(31 downto 24);
signal pio : std_logic_vector(17 downto 0);
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal wdogn,wdogn_local : std_logic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal ctsn1, rtsn1 : std_ulogic;
signal ctsn2, rtsn2 : std_ulogic;
signal erx_dv, erx_dv_d, etx_en: std_logic:='0';
signal erxd, erxd_d, etxd: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal emdint : std_ulogic;
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic := '0';
signal ps2clk : std_logic_vector(1 downto 0);
signal ps2data : std_logic_vector(1 downto 0);
signal clk2 : std_ulogic := '0';
signal clk125 : std_ulogic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic := '0';
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_dq2 : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(9 downto 0); -- I/O port
signal led : std_logic_vector(3 downto 0); -- I/O port
signal erx_er : std_logic := '0';
signal erx_col : std_logic := '0';
signal erx_crs : std_logic := '1';
signal etx_er : std_logic := '0';
constant lresp : boolean := false;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk125 <= not clk125 after 10 ns;
--erx_clk <= not erx_clk after 4 ns;
clk2 <= '0'; --not clk2 after 5 ns;
rst <= dsurst and wdogn_local;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
ps2clk <= "HH"; ps2data <= "HH";
pio(4) <= pio(5); pio(1) <= pio(2); pio <= (others => 'H');
wdogn <= 'H';
wdogn_local <= 'H';
switch(7) <= '1';
switch(8) <= '0';
emdio <= 'H';
spw_rxdp <= spw_txdp; spw_rxdn <= spw_txdn;
spw_rxsp <= spw_txsp; spw_rxsn <= spw_txsn;
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, clk2, clk125, wdogn, address(24 downto 0), data,
oen, writen, romsn,
ddr_clk, ddr_clkb, ddr_cke, ddr_odt, ddr_we, ddr_ras, ddr_csb ,ddr_cas, ddr_dm,
ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_rzq, ddr_zio,
txd1, rxd1, ctsn1, rtsn1, txd2, rxd2, ctsn2, rtsn2, pio, genio,
switch, led, erx_clk, emdio, erxd(3 downto 0)'delayed(1 ns), erx_dv'delayed(1 ns), emdint,
etx_clk, etxd(3 downto 0), etx_en, emdc,
ps2clk, ps2data, iic_scl, iic_sda, ddc_scl, ddc_sda,
dvi_iic_scl, dvi_iic_sda,
tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
spw_clk, spw_rxdp, spw_rxdn,
spw_rxsp, spw_rxsn, spw_txdp, spw_txdn, spw_txsp, spw_txsn,
spi_sel_n, spi_clk, spi_mosi
);
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
writen, oen);
ddr2mem : if (CFG_MIG_DDR2 = 1) generate
u1: ddr2ram
generic map (width => 16, abits => 13, babits => 3,
colbits => 10, rowbits => 13, implbanks => 1,
fname => sdramfile, lddelay => (340 us),
speedbin => 1)
port map (ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb,
odt => ddr_odt, rasn => ddr_ras, casn => ddr_cas, wen => ddr_we,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad,
dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn);
end generate;
ps2devs: for i in 0 to 1 generate
ps2_device(ps2clk(i), ps2data(i));
end generate ps2devs;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map(
address => 1,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
rmii => 0,
rgmii => 1
)
port map(rst, emdio, open, erx_clk, erxd_d, erx_dv_d,
erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, clk125);
end generate;
rcxclkp : process(erx_clk) is
begin
erxd <= erxd_d;
erx_dv <= erx_dv_d;
end process;
--wdognp : process
-- begin
-- wdogn_local <= 'H';
-- if wdogn = '0' then
-- wdogn_local <= '0';
-- wait for 1 ms;
-- end if;
-- wait for 20 ns;
-- end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 201 us;
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
iuerr : process
begin
wait until dsurst = '1';
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
|
gpl-2.0
|
44e76ca83158fd25d8c5bdf835ff92d8
| 0.567916 | 2.992388 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/greth/greth.vhd
| 1 | 12,439 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth
-- File: greth.vhd
-- Author: Marko Isomaki
-- Description: Ethernet Media Access Controller with Ethernet Debug
-- Communication Link
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
use gaisler.ethernet_mac.all;
library eth;
use eth.ethcomp.all;
entity greth is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1518;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end entity;
architecture rtl of greth is
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
constant fabits : integer := log2(fifosize);
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits : integer := log2(edclbufsz) + 8;
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, revision, 0),
others => zero32);
constant ehconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_EDCLMST, 0, REVISION, 0),
others => zero32);
signal irq : std_ulogic;
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(10 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(10 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(10 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(10 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
signal lmdio_oe : std_ulogic;
-- Fix for wider bus
signal hwdata : std_logic_vector(31 downto 0);
signal hrdata : std_logic_vector(31 downto 0);
begin
ethc0: grethc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => 0,
ramdebug => ramdebug,
mdiohold => mdiohold,
maxsize => maxsize,
gmiimode => gmiimode
)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => ahbmi.hgrant(hindex),
hready => ahbmi.hready,
hresp => ahbmi.hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => ahbmo.hbusreq,
hlock => ahbmo.hlock,
htrans => ahbmo.htrans,
haddr => ahbmo.haddr,
hwrite => ahbmo.hwrite,
hsize => ahbmo.hsize,
hburst => ahbmo.hburst,
hprot => ahbmo.hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ahbmi.hgrant(hindex),
ehready => ahbmi.hready,
ehresp => ahbmi.hresp,
ehrdata => hrdata,
--edcl ahb mst out
ehbusreq => open,
ehlock => open,
ehtrans => open,
ehaddr => open,
ehwrite => open,
ehsize => open,
ehburst => open,
ehprot => open,
ehwdata => open,
--apb slv in
psel => apbi.psel(pindex),
penable => apbi.penable,
paddr => apbi.paddr,
pwrite => apbi.pwrite,
pwdata => apbi.pwdata,
--apb slv out
prdata => apbo.prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
rmii_clk => ethi.rmii_clk,
tx_clk => ethi.tx_clk,
tx_dv => ethi.tx_dv,
rx_clk => ethi.rx_clk,
rxd => ethi.rxd(3 downto 0),
rx_dv => ethi.rx_dv,
rx_er => ethi.rx_er,
rx_col => ethi.rx_col,
rx_crs => ethi.rx_crs,
rx_en => ethi.rx_en,
mdio_i => ethi.mdio_i,
phyrstaddr => ethi.phyrstaddr,
mdint => ethi.mdint,
--ethernet output signals
reset => etho.reset,
txd => etho.txd(3 downto 0),
tx_en => etho.tx_en,
tx_er => etho.tx_er,
mdc => etho.mdc,
mdio_o => etho.mdio_o,
mdio_oe => lmdio_oe,
--scantest
testrst => ahbmi.testrst,
testen => ahbmi.testen,
testoen => ahbmi.testoen,
edcladdr => ethi.edcladdr,
edclsepahb => ethi.edclsepahb,
edcldisable => ethi.edcldisable,
speed => etho.speed);
etho.txd(7 downto 4) <= "0000";
etho.mdio_oe <= ahbmi.testoen when (scanen = 1) and (ahbmi.testen = '1')
else lmdio_oe;
etho.gbit <= '0';
etho.tx_clk <= '0'; -- driven in rgmii component
irqdrv : process(irq)
begin
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= irq;
end process;
hrdata <= ahbreadword(ahbmi.hrdata);
ahbmo.hwdata <= ahbdrivedata(hwdata);
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
ahbmo.hirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
-- pragma translate_off
bootmsg : report_version
generic map (
"greth" & tost(hindex) & ": 10/100 Mbit Ethernet MAC rev " & tost(REVISION)
& tost(hindex) & ", EDCL " & tost(edcl) & ", buffer " &
tost(edclbufsz) & " kbyte " & tost(txfifosize) & " txfifo," &
" irq " & tost(pirq)
);
-- pragma translate_on
end architecture;
|
gpl-2.0
|
e0ef1b2f452ac3fff585caed23abbc0c
| 0.521585 | 4.165774 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/work/debug/cpu_disas.vhd
| 1 | 4,256 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cpu_disas
-- File: cpu_disas.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Module for disassembly
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use std.textio.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity cpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic);
end;
architecture behav of cpu_disas is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1') and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (conv_integer(index), pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1', false);
end if;
end process;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use std.textio.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity gaisler_cpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic);
end;
architecture behav of gaisler_cpu_disas is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1') and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (conv_integer(index), pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1', false);
end if;
end process;
-- pragma translate_on
end;
|
gpl-2.0
|
d9b115c261935b18b91d03165ac5b676
| 0.609727 | 3.457352 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/virtex5/serdes_unisim.vhd
| 1 | 74,616 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: serdes_unisim
-- File: serdes_unisim.vhd
-- Author: Andrea Gianarro - Cobham Gaisler AB
-- Description: Xilinx Virtex 5 GTP and GTX-based SGMII Gigabit Ethernet Serdes
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library unisim;
--use unisim.BUFG;
use unisim.vcomponents.all;
-- pragma translate_off
-- pragma translate_on
entity serdes_unisim is
generic (
transtech : integer
);
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
rx_in_p : in std_logic; -- SER IN
rx_in_n : in std_logic; -- SER IN
rx_out : out std_logic_vector(9 downto 0); -- PAR OUT
rx_clk : out std_logic;
rx_rstn : out std_logic;
rx_pll_clk : out std_logic;
rx_pll_rstn : out std_logic;
tx_pll_clk : out std_logic;
tx_pll_rstn : out std_logic;
tx_in : in std_logic_vector(9 downto 0) ; -- PAR IN
tx_out_p : out std_logic; -- SER OUT
tx_out_n : out std_logic; -- SER OUT
bitslip : in std_logic
);
end entity;
architecture rtl of serdes_unisim is
constant SIMULATION_P : integer := 1;
component BUFG
port ( O : out std_logic;
I : in std_logic );
end component;
-- signal rx_clk_int, rx_pll_clk_int, tx_pll_clk_int, rst_int, pll_areset_int, rx_locked_int, rx_rstn_int_0, tx_locked_int : std_logic;
-- signal rx_cda_reset_int, bitslip_int, rx_in_int, rx_rst_int, rx_divfwdclk_int, tx_out_int : std_logic_vector(0 downto 0) ;
-- signal rx_clk_rstn_int, rx_pll_rstn_int, tx_pll_rstn_int, rx_cda_reset_int_0 : std_logic;
-- signal rx_out_int, tx_in_int : std_logic_vector(9 downto 0) ;
signal ref_clk_int, ref_clk_lock_int, ref_clk_rstn_int, ref_clk_rst_int : std_logic;
signal ref_clk_buf_int, rx_usrclk_int, rx_usrclk2_int, tx_usrclk_int, tx_usrclk2_int : std_logic;
signal ref_clk_buf_rstn_int, rx_usrclk2_rstn_int, tx_usrclk2_rstn_int, tx_rst_int, rx_rst_int : std_logic;
signal rx_rec_clk_int, rx_rec_clk_buf_int : std_logic;
signal tx_out_clk_int, tx_out_clk_rstn_int, rst_done_int : std_logic;
signal tx_usrclk_lock_int, rx_usrclk_lock_int : std_logic;
signal rx_rec_clk0_int, rst_done0_int, rx_in0_n, rx_in0_p, tx_out0_n, tx_out0_p : std_logic;
signal rx_rec_clk1_int, rst_done1_int, rx_in1_n, rx_in1_p, tx_out1_n, tx_out1_p : std_logic;
signal r0, r1, r2 : std_logic_vector(4 downto 0);
signal clkdv_i, clk0_i, clkfb_i, reset_to_dcm : std_logic;
signal count_to_dcm_reset : std_logic_vector(1 downto 0);
signal clkfbout_i, clkout0_i, clkout1_i, pll_lk_out, pll_locked_out_r, time_elapsed : std_logic;
signal lock_wait_counter : std_logic_vector(15 downto 0);
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
-- RX Datapath signals
signal rxdata0_i : std_logic_vector(31 downto 0);
signal rxchariscomma0_float_i : std_logic;
signal rxcharisk0_float_i : std_logic;
signal rxdisperr0_float_i : std_logic;
signal rxnotintable0_float_i : std_logic;
signal rxrundisp0_float_i : std_logic;
signal rxdata0_out_i : std_logic_vector(9 downto 0);
signal rxcharisk0_i : std_logic_vector(3 downto 0);
signal rxdisperr0_i : std_logic_vector(3 downto 0);
-- TX Datapath signals
signal txdata0_i : std_logic_vector(31 downto 0);
signal txdata0_in_i : std_logic_vector(9 downto 0);
signal txchardispmode0_i : std_logic_vector(3 downto 0);
signal txchardispval0_i : std_logic_vector(3 downto 0);
signal txkerr0_float_i : std_logic;
signal txrundisp0_float_i : std_logic;
-- Electrical idle reset logic signals
signal rxelecidle0_i : std_logic;
signal rxelecidlereset0_i : std_logic;
-- RX Datapath signals
signal rxdata1_i : std_logic_vector(31 downto 0);
signal rxchariscomma1_float_i : std_logic;
signal rxcharisk1_float_i : std_logic;
signal rxdisperr1_float_i : std_logic;
signal rxnotintable1_float_i : std_logic;
signal rxrundisp1_float_i : std_logic;
signal rxdata1_out_i : std_logic_vector(9 downto 0);
signal rxcharisk1_i : std_logic_vector(3 downto 0);
signal rxdisperr1_i : std_logic_vector(3 downto 0);
-- TX Datapath signals
signal txdata1_i : std_logic_vector(31 downto 0);
signal txdata1_in_i : std_logic_vector(9 downto 0);
signal txchardispmode1_i : std_logic_vector(3 downto 0);
signal txchardispval1_i : std_logic_vector(3 downto 0);
signal txkerr1_float_i : std_logic;
signal txrundisp1_float_i : std_logic;
-- Electrical idle reset logic signals
signal rxelecidle1_i : std_logic;
signal resetdone1_i : std_logic;
signal rxelecidlereset1_i : std_logic;
-- Shared Electrical Idle Reset signal
signal rxenelecidleresetb_i : std_logic;
signal txelecidle_r : std_logic;
signal txelecidle0_r : std_logic;
signal txelecidle1_r : std_logic;
signal txpowerdown0_r : std_logic_vector(1 downto 0);
signal rxpowerdown0_r : std_logic_vector(1 downto 0);
signal txpowerdown1_r : std_logic_vector(1 downto 0);
signal rxpowerdown1_r : std_logic_vector(1 downto 0);
begin
-- output clocks
rx_clk <= rx_usrclk2_int;
rx_pll_clk <= ref_clk_buf_int;
tx_pll_clk <= tx_usrclk2_int;
-- output synchronized resets
rx_rstn <= rx_usrclk2_rstn_int;
rx_pll_rstn <= ref_clk_buf_rstn_int;
tx_pll_rstn <= tx_usrclk2_rstn_int;
ref_clk_rst_int <= not ref_clk_lock_int;
-- reset synchronizers
rst0 : process (ref_clk_buf_int, ref_clk_rst_int) begin
if rising_edge(ref_clk_buf_int) then
r0 <= r0(3 downto 0) & rst_done_int;
ref_clk_buf_rstn_int <= r0(4) and r0(3) and r0(2);
end if;
if (ref_clk_rst_int = '1') then r0 <= "00000"; ref_clk_buf_rstn_int <= '0'; end if;
end process;
rst1 : process (rx_usrclk2_int, rx_rst_int) begin
if rising_edge(rx_usrclk2_int) then
r1 <= r1(3 downto 0) & rst_done_int;
rx_usrclk2_rstn_int <= r1(4) and r1(3) and r1(2);
end if;
if (rx_rst_int = '1') then r1 <= "00000"; rx_usrclk2_rstn_int <= '0'; end if;
end process;
rst2 : process (tx_usrclk2_int, tx_rst_int) begin
if rising_edge(tx_usrclk2_int) then
r2 <= r2(3 downto 0) & rst_done_int;
tx_usrclk2_rstn_int <= r2(4) and r2(3) and r2(2);
end if;
if (tx_rst_int = '1') then r2 <= "00000"; tx_usrclk2_rstn_int <= '0'; end if;
end process;
-- Transceiver channel selection
ch0: if transtech = GTP0 or transtech = GTX0 generate
rx_rec_clk_int <= rx_rec_clk0_int;
rst_done_int <= rst_done0_int;
rx_in0_n <= rx_in_n;
rx_in0_p <= rx_in_p;
tx_out_n <= tx_out0_n;
tx_out_p <= tx_out0_p;
inv_tx: for i in 0 to 9 generate
txdata0_in_i(i) <= tx_in(9-i);
rx_out(i) <= rxdata0_out_i(9-i);
end generate ;
end generate;
ch1: if transtech = GTP1 or transtech = GTX1 generate
rx_rec_clk_int <= rx_rec_clk1_int;
rst_done_int <= rst_done1_int;
rx_in1_n <= rx_in_n;
rx_in1_p <= rx_in_p;
tx_out_n <= tx_out1_n;
tx_out_p <= tx_out1_p;
inv_tx: for i in 0 to 9 generate
txdata1_in_i(i) <= tx_in(9-i);
rx_out(i) <= rxdata1_out_i(9-i);
end generate ;
end generate;
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
------------------- GTP Datapath byte mapping -----------------
--The GTP deserializes the rightmost parallel bit (LSb) first
--The GTP serializes the rightmost parallel bit (LSb) first
--The GTP deserializes the rightmost parallel bit (LSb) first
--The GTP serializes the rightmost parallel bit (LSb) first
------------- GTP0 rxdata_out_i Assignments for 10 bit datapath -------
rxdata0_out_i <= (rxdisperr0_i(0) & rxcharisk0_i(0) & rxdata0_i(7 downto 0));
------------- GTP0 txdata_i Assignments for 10 bit datapath -------
txdata0_i <= (tied_to_ground_vec_i(23 downto 0) & txdata0_in_i(7 downto 0));
txchardispval0_i <= (tied_to_ground_vec_i(2 downto 0) & txdata0_in_i(8));
txchardispmode0_i <= (tied_to_ground_vec_i(2 downto 0) & txdata0_in_i(9));
------------- GTP1 rxdata_out_i Assignments for 10 bit datapath -------
rxdata1_out_i <= (rxdisperr1_i(0) & rxcharisk1_i(0) & rxdata1_i(7 downto 0));
------------- GTP1 txdata_i Assignments for 10 bit datapath -------
txdata1_i <= (tied_to_ground_vec_i(23 downto 0) & txdata1_in_i(7 downto 0));
txchardispval1_i <= (tied_to_ground_vec_i(2 downto 0) & txdata1_in_i(8));
txchardispmode1_i <= (tied_to_ground_vec_i(2 downto 0) & txdata1_in_i(9));
---- Clock buffers
ref_clk_buf0 : BUFG
port map
(
I => ref_clk_int,
O => ref_clk_buf_int
);
rx_rec_clk_buf0 : BUFG
port map
(
I => rx_rec_clk_int,
O => rx_rec_clk_buf_int
);
---- GTP_DUAL instantiation
inst_gtp0: if (transtech = GTP0) or (transtech = GTP1) generate
-- no need for extra clocks on GTP transtech
tx_usrclk_int <= ref_clk_buf_int;
tx_usrclk2_int <= ref_clk_buf_int;
tx_rst_int <= not ref_clk_lock_int;
rx_usrclk_int <= rx_rec_clk_buf_int;
rx_usrclk2_int <= rx_rec_clk_buf_int;
rx_rst_int <= not ref_clk_lock_int;
gtp_dual_i:GTP_DUAL
generic map (
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS0 => TRUE,
SIM_RECEIVER_DETECT_PASS1 => TRUE,
SIM_MODE => "FAST",
SIM_GTPRESET_SPEEDUP => 0,
SIM_PLL_PERDIV2 => x"190",
--___________________________ Shared Attributes ________________________
-------------------------- Tile and PLL Attributes ---------------------
CLK25_DIVIDER => 5,
CLKINDC_B => TRUE,
OOB_CLK_DIVIDER => 4,
OVERSAMPLE_MODE => FALSE,
PLL_DIVSEL_FB => 2,
PLL_DIVSEL_REF => 1,
PLL_TXDIVSEL_COMM_OUT => 2,
TX_SYNC_FILTERB => 1,
--____________________ Transmit Interface Attributes ___________________
------------------- TX Buffering and Phase Alignment -------------------
TX_BUFFER_USE_0 => FALSE,
TX_XCLK_SEL_0 => "TXUSR",
TXRX_INVERT_0 => "00100",
TX_BUFFER_USE_1 => FALSE,
TX_XCLK_SEL_1 => "TXUSR",
TXRX_INVERT_1 => "00100",
--------------------- TX Serial Line Rate settings ---------------------
PLL_TXDIVSEL_OUT_0 => 1,
PLL_TXDIVSEL_OUT_1 => 1,
--------------------- TX Driver and OOB signalling --------------------
TX_DIFF_BOOST_0 => TRUE,
TX_DIFF_BOOST_1 => TRUE,
------------------ TX Pipe Control for PCI Express/SATA ---------------
COM_BURST_VAL_0 => "1111",
COM_BURST_VAL_1 => "1111",
--_______________________ Receive Interface Attributes ________________
------------ RX Driver,OOB signalling,Coupling and Eq,CDR -------------
AC_CAP_DIS_0 => TRUE,
OOBDETECT_THRESHOLD_0 => "001",
PMA_CDR_SCAN_0 => x"6c07640",
PMA_RX_CFG_0 => x"09f0088",
RCV_TERM_GND_0 => FALSE,
RCV_TERM_MID_0 => FALSE,
RCV_TERM_VTTRX_0 => FALSE,
TERMINATION_IMP_0 => 50,
AC_CAP_DIS_1 => TRUE,
OOBDETECT_THRESHOLD_1 => "001",
PMA_CDR_SCAN_1 => x"6c07640",
PMA_RX_CFG_1 => x"09f0088",
RCV_TERM_GND_1 => FALSE,
RCV_TERM_MID_1 => FALSE,
RCV_TERM_VTTRX_1 => FALSE,
TERMINATION_IMP_1 => 50,
PCS_COM_CFG => x"1680a0e",
TERMINATION_CTRL => "10100",
TERMINATION_OVRD => FALSE,
--------------------- RX Serial Line Rate Attributes ------------------
PLL_RXDIVSEL_OUT_0 => 2,
PLL_SATA_0 => FALSE,
PLL_RXDIVSEL_OUT_1 => 2,
PLL_SATA_1 => FALSE,
----------------------- PRBS Detection Attributes ---------------------
PRBS_ERR_THRESHOLD_0 => x"00000001",
PRBS_ERR_THRESHOLD_1 => x"00000001",
---------------- Comma Detection and Alignment Attributes -------------
ALIGN_COMMA_WORD_0 => 1,
COMMA_10B_ENABLE_0 => "1111111111",
COMMA_DOUBLE_0 => FALSE,
DEC_MCOMMA_DETECT_0 => FALSE,
DEC_PCOMMA_DETECT_0 => FALSE,
DEC_VALID_COMMA_ONLY_0 => FALSE,
MCOMMA_10B_VALUE_0 => "1010000011",
MCOMMA_DETECT_0 => FALSE,
PCOMMA_10B_VALUE_0 => "0101111100",
PCOMMA_DETECT_0 => FALSE,
RX_SLIDE_MODE_0 => "PCS",
ALIGN_COMMA_WORD_1 => 1,
COMMA_10B_ENABLE_1 => "1111111111",
COMMA_DOUBLE_1 => FALSE,
DEC_MCOMMA_DETECT_1 => FALSE,
DEC_PCOMMA_DETECT_1 => FALSE,
DEC_VALID_COMMA_ONLY_1 => FALSE,
MCOMMA_10B_VALUE_1 => "1010000011",
MCOMMA_DETECT_1 => FALSE,
PCOMMA_10B_VALUE_1 => "0101111100",
PCOMMA_DETECT_1 => FALSE,
RX_SLIDE_MODE_1 => "PCS",
------------------ RX Loss-of-sync State Machine Attributes -----------
RX_LOSS_OF_SYNC_FSM_0 => FALSE,
RX_LOS_INVALID_INCR_0 => 8,
RX_LOS_THRESHOLD_0 => 128,
RX_LOSS_OF_SYNC_FSM_1 => FALSE,
RX_LOS_INVALID_INCR_1 => 8,
RX_LOS_THRESHOLD_1 => 128,
-------------- RX Elastic Buffer and Phase alignment Attributes -------
RX_BUFFER_USE_0 => FALSE,
RX_XCLK_SEL_0 => "RXUSR",
RX_BUFFER_USE_1 => FALSE,
RX_XCLK_SEL_1 => "RXUSR",
------------------------ Clock Correction Attributes ------------------
CLK_CORRECT_USE_0 => FALSE,
CLK_COR_ADJ_LEN_0 => 1,
CLK_COR_DET_LEN_0 => 1,
CLK_COR_INSERT_IDLE_FLAG_0 => FALSE,
CLK_COR_KEEP_IDLE_0 => FALSE,
CLK_COR_MAX_LAT_0 => 18,
CLK_COR_MIN_LAT_0 => 16,
CLK_COR_PRECEDENCE_0 => TRUE,
CLK_COR_REPEAT_WAIT_0 => 0,
CLK_COR_SEQ_1_1_0 => "0000000000",
CLK_COR_SEQ_1_2_0 => "0000000000",
CLK_COR_SEQ_1_3_0 => "0000000000",
CLK_COR_SEQ_1_4_0 => "0000000000",
CLK_COR_SEQ_1_ENABLE_0 => "0000",
CLK_COR_SEQ_2_1_0 => "0000000000",
CLK_COR_SEQ_2_2_0 => "0000000000",
CLK_COR_SEQ_2_3_0 => "0000000000",
CLK_COR_SEQ_2_4_0 => "0000000000",
CLK_COR_SEQ_2_ENABLE_0 => "0000",
CLK_COR_SEQ_2_USE_0 => FALSE,
RX_DECODE_SEQ_MATCH_0 => FALSE,
CLK_CORRECT_USE_1 => FALSE,
CLK_COR_ADJ_LEN_1 => 1,
CLK_COR_DET_LEN_1 => 1,
CLK_COR_INSERT_IDLE_FLAG_1 => FALSE,
CLK_COR_KEEP_IDLE_1 => FALSE,
CLK_COR_MAX_LAT_1 => 18,
CLK_COR_MIN_LAT_1 => 16,
CLK_COR_PRECEDENCE_1 => TRUE,
CLK_COR_REPEAT_WAIT_1 => 0,
CLK_COR_SEQ_1_1_1 => "0000000000",
CLK_COR_SEQ_1_2_1 => "0000000000",
CLK_COR_SEQ_1_3_1 => "0000000000",
CLK_COR_SEQ_1_4_1 => "0000000000",
CLK_COR_SEQ_1_ENABLE_1 => "0000",
CLK_COR_SEQ_2_1_1 => "0000000000",
CLK_COR_SEQ_2_2_1 => "0000000000",
CLK_COR_SEQ_2_3_1 => "0000000000",
CLK_COR_SEQ_2_4_1 => "0000000000",
CLK_COR_SEQ_2_ENABLE_1 => "0000",
CLK_COR_SEQ_2_USE_1 => FALSE,
RX_DECODE_SEQ_MATCH_1 => FALSE,
------------------------ Channel Bonding Attributes -------------------
CHAN_BOND_1_MAX_SKEW_0 => 1,
CHAN_BOND_2_MAX_SKEW_0 => 1,
CHAN_BOND_LEVEL_0 => 0,
CHAN_BOND_MODE_0 => "OFF",
CHAN_BOND_SEQ_1_1_0 => "0000000000",
CHAN_BOND_SEQ_1_2_0 => "0000000000",
CHAN_BOND_SEQ_1_3_0 => "0000000000",
CHAN_BOND_SEQ_1_4_0 => "0000000000",
CHAN_BOND_SEQ_1_ENABLE_0 => "0001",
CHAN_BOND_SEQ_2_1_0 => "0000000000",
CHAN_BOND_SEQ_2_2_0 => "0000000000",
CHAN_BOND_SEQ_2_3_0 => "0000000000",
CHAN_BOND_SEQ_2_4_0 => "0000000000",
CHAN_BOND_SEQ_2_ENABLE_0 => "0000",
CHAN_BOND_SEQ_2_USE_0 => FALSE,
CHAN_BOND_SEQ_LEN_0 => 1,
PCI_EXPRESS_MODE_0 => FALSE,
CHAN_BOND_1_MAX_SKEW_1 => 1,
CHAN_BOND_2_MAX_SKEW_1 => 1,
CHAN_BOND_LEVEL_1 => 0,
CHAN_BOND_MODE_1 => "OFF",
CHAN_BOND_SEQ_1_1_1 => "0000000000",
CHAN_BOND_SEQ_1_2_1 => "0000000000",
CHAN_BOND_SEQ_1_3_1 => "0000000000",
CHAN_BOND_SEQ_1_4_1 => "0000000000",
CHAN_BOND_SEQ_1_ENABLE_1 => "0001",
CHAN_BOND_SEQ_2_1_1 => "0000000000",
CHAN_BOND_SEQ_2_2_1 => "0000000000",
CHAN_BOND_SEQ_2_3_1 => "0000000000",
CHAN_BOND_SEQ_2_4_1 => "0000000000",
CHAN_BOND_SEQ_2_ENABLE_1 => "0000",
CHAN_BOND_SEQ_2_USE_1 => FALSE,
CHAN_BOND_SEQ_LEN_1 => 1,
PCI_EXPRESS_MODE_1 => FALSE,
------------------ RX Attributes for PCI Express/SATA ---------------
RX_STATUS_FMT_0 => "PCIE",
SATA_BURST_VAL_0 => "100",
SATA_IDLE_VAL_0 => "100",
SATA_MAX_BURST_0 => 9,
SATA_MAX_INIT_0 => 27,
SATA_MAX_WAKE_0 => 9,
SATA_MIN_BURST_0 => 5,
SATA_MIN_INIT_0 => 15,
SATA_MIN_WAKE_0 => 5,
TRANS_TIME_FROM_P2_0 => x"003c",
TRANS_TIME_NON_P2_0 => x"0019",
TRANS_TIME_TO_P2_0 => x"0064",
RX_STATUS_FMT_1 => "PCIE",
SATA_BURST_VAL_1 => "100",
SATA_IDLE_VAL_1 => "100",
SATA_MAX_BURST_1 => 9,
SATA_MAX_INIT_1 => 27,
SATA_MAX_WAKE_1 => 9,
SATA_MIN_BURST_1 => 5,
SATA_MIN_INIT_1 => 15,
SATA_MIN_WAKE_1 => 5,
TRANS_TIME_FROM_P2_1 => x"003c",
TRANS_TIME_NON_P2_1 => x"0019",
TRANS_TIME_TO_P2_1 => x"0064"
)
port map (
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0 => tied_to_ground_vec_i(2 downto 0),
LOOPBACK1 => tied_to_ground_vec_i(2 downto 0),
RXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
RXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA0 => open,
RXCHARISCOMMA1 => open,
RXCHARISK0 => rxcharisk0_i(1 downto 0),
RXCHARISK1 => rxcharisk1_i(1 downto 0),
RXDEC8B10BUSE0 => tied_to_ground_i,
RXDEC8B10BUSE1 => tied_to_ground_i,
RXDISPERR0 => rxdisperr0_i(1 downto 0),
RXDISPERR1 => rxdisperr1_i(1 downto 0),
RXNOTINTABLE0 => open,
RXNOTINTABLE1 => open,
RXRUNDISP0 => open,
RXRUNDISP1 => open,
------------------- Receive Ports - Channel Bonding Ports ------------------
RXCHANBONDSEQ0 => open,
RXCHANBONDSEQ1 => open,
RXCHBONDI0 => tied_to_ground_vec_i(2 downto 0),
RXCHBONDI1 => tied_to_ground_vec_i(2 downto 0),
RXCHBONDO0 => open,
RXCHBONDO1 => open,
RXENCHANSYNC0 => tied_to_ground_i,
RXENCHANSYNC1 => tied_to_ground_i,
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT0 => open,
RXCLKCORCNT1 => open,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0 => open,
RXBYTEISALIGNED1 => open,
RXBYTEREALIGN0 => open,
RXBYTEREALIGN1 => open,
RXCOMMADET0 => open,
RXCOMMADET1 => open,
RXCOMMADETUSE0 => tied_to_vcc_i,
RXCOMMADETUSE1 => tied_to_vcc_i,
RXENMCOMMAALIGN0 => tied_to_ground_i,
RXENMCOMMAALIGN1 => tied_to_ground_i,
RXENPCOMMAALIGN0 => tied_to_ground_i,
RXENPCOMMAALIGN1 => tied_to_ground_i,
RXSLIDE0 => bitslip,
RXSLIDE1 => bitslip,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET0 => tied_to_ground_i,
PRBSCNTRESET1 => tied_to_ground_i,
RXENPRBSTST0 => tied_to_ground_vec_i(1 downto 0),
RXENPRBSTST1 => tied_to_ground_vec_i(1 downto 0),
RXPRBSERR0 => open,
RXPRBSERR1 => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0 => rxdata0_i(15 downto 0),
RXDATA1 => rxdata1_i(15 downto 0),
RXDATAWIDTH0 => tied_to_ground_i,
RXDATAWIDTH1 => tied_to_ground_i,
RXRECCLK0 => rx_rec_clk0_int,
RXRECCLK1 => rx_rec_clk1_int,
RXRESET0 => rx_rst_int,
RXRESET1 => rx_rst_int,
RXUSRCLK0 => rx_usrclk_int,
RXUSRCLK1 => rx_usrclk_int,
RXUSRCLK20 => rx_usrclk2_int,
RXUSRCLK21 => rx_usrclk2_int,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET0 => tied_to_ground_i,
RXCDRRESET1 => tied_to_ground_i,
RXELECIDLE0 => rxelecidle0_i,
RXELECIDLE1 => rxelecidle1_i,
RXELECIDLERESET0 => tied_to_ground_i,
RXELECIDLERESET1 => tied_to_ground_i,
RXENEQB0 => tied_to_vcc_i,
RXENEQB1 => tied_to_vcc_i,
RXEQMIX0 => tied_to_ground_vec_i(1 downto 0),
RXEQMIX1 => tied_to_ground_vec_i(1 downto 0),
RXEQPOLE0 => tied_to_ground_vec_i(3 downto 0),
RXEQPOLE1 => tied_to_ground_vec_i(3 downto 0),
RXN0 => rx_in0_n,
RXN1 => rx_in1_n,
RXP0 => rx_in0_p,
RXP1 => rx_in1_p,
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
RXBUFRESET0 => tied_to_ground_i,
RXBUFRESET1 => tied_to_ground_i,
RXBUFSTATUS0 => open,
RXBUFSTATUS1 => open,
RXCHANISALIGNED0 => open,
RXCHANISALIGNED1 => open,
RXCHANREALIGN0 => open,
RXCHANREALIGN1 => open,
RXPMASETPHASE0 => tied_to_ground_i,
RXPMASETPHASE1 => tied_to_ground_i,
RXSTATUS0 => open,
RXSTATUS1 => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0 => open,
RXLOSSOFSYNC1 => open,
---------------------- Receive Ports - RX Oversampling ---------------------
RXENSAMPLEALIGN0 => tied_to_ground_i,
RXENSAMPLEALIGN1 => tied_to_ground_i,
RXOVERSAMPLEERR0 => open,
RXOVERSAMPLEERR1 => open,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0 => open,
PHYSTATUS1 => open,
RXVALID0 => open,
RXVALID1 => open,
----------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY0 => tied_to_ground_i,
RXPOLARITY1 => tied_to_ground_i,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => tied_to_ground_vec_i(6 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DO => open,
DRDY => open,
DWE => tied_to_ground_i,
--------------------- Shared Ports - Tile and PLL Ports --------------------
CLKIN => clk_125,
GTPRESET => rst_125,
GTPTEST => tied_to_ground_vec_i(3 downto 0),
INTDATAWIDTH => tied_to_vcc_i,
PLLLKDET => ref_clk_lock_int,
PLLLKDETEN => tied_to_vcc_i,
PLLPOWERDOWN => tied_to_ground_i,
REFCLKOUT => ref_clk_int,
REFCLKPWRDNB => tied_to_vcc_i,
RESETDONE0 => rst_done0_int,
RESETDONE1 => rst_done1_int,
RXENELECIDLERESETB => tied_to_vcc_i,
TXENPMAPHASEALIGN => tied_to_ground_i,
TXPMASETPHASE => tied_to_ground_i,
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXBYPASS8B10B0 => tied_to_ground_vec_i(1 downto 0),
TXBYPASS8B10B1 => tied_to_ground_vec_i(1 downto 0),
TXCHARDISPMODE0 => txchardispmode0_i(1 downto 0),
TXCHARDISPMODE1 => txchardispmode1_i(1 downto 0),
TXCHARDISPVAL0 => txchardispval0_i(1 downto 0),
TXCHARDISPVAL1 => txchardispval1_i(1 downto 0),
TXCHARISK0 => tied_to_ground_vec_i(1 downto 0),
TXCHARISK1 => tied_to_ground_vec_i(1 downto 0),
TXENC8B10BUSE0 => tied_to_ground_i,
TXENC8B10BUSE1 => tied_to_ground_i,
TXKERR0 => open,
TXKERR1 => open,
TXRUNDISP0 => open,
TXRUNDISP1 => open,
------------- Transmit Ports - TX Buffering and Phase Alignment ------------
TXBUFSTATUS0 => open,
TXBUFSTATUS1 => open,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0 => txdata0_i(15 downto 0),
TXDATA1 => txdata1_i(15 downto 0),
TXDATAWIDTH0 => tied_to_ground_i,
TXDATAWIDTH1 => tied_to_ground_i,
TXOUTCLK0 => open,
TXOUTCLK1 => open,
TXRESET0 => tx_rst_int,
TXRESET1 => tx_rst_int,
TXUSRCLK0 => tx_usrclk_int,
TXUSRCLK1 => tx_usrclk_int,
TXUSRCLK20 => tx_usrclk2_int,
TXUSRCLK21 => tx_usrclk2_int,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXBUFDIFFCTRL0 => "000",
TXBUFDIFFCTRL1 => "000",
TXDIFFCTRL0 => "000",
TXDIFFCTRL1 => "000",
TXINHIBIT0 => tied_to_ground_i,
TXINHIBIT1 => tied_to_ground_i,
TXN0 => tx_out0_n,
TXN1 => tx_out1_n,
TXP0 => tx_out0_p,
TXP1 => tx_out1_p,
TXPREEMPHASIS0 => "000",
TXPREEMPHASIS1 => "000",
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST0 => tied_to_ground_vec_i(1 downto 0),
TXENPRBSTST1 => tied_to_ground_vec_i(1 downto 0),
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY0 => tied_to_ground_i,
TXPOLARITY1 => tied_to_ground_i,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0 => tied_to_ground_i,
TXDETECTRX1 => tied_to_ground_i,
TXELECIDLE0 => tied_to_ground_i,
TXELECIDLE1 => tied_to_ground_i,
--------------------- Transmit Ports - TX Ports for SATA -------------------
TXCOMSTART0 => tied_to_ground_i,
TXCOMSTART1 => tied_to_ground_i,
TXCOMTYPE0 => tied_to_ground_i,
TXCOMTYPE1 => tied_to_ground_i
);
end generate;
---- GTX_DUAL instantiation
inst_gtx0: if (transtech = GTX0) or (transtech = GTX1) generate
-- refclkout_dcm0: MGT_USRCLK_SOURCE
-- generic map
-- (
-- FREQUENCY_MODE => "LOW",
-- PERFORMANCE_MODE => "MAX_SPEED"
-- )
-- port map
-- (
-- DIV1_OUT => tx_usrclk2_int,
-- DIV2_OUT => tx_usrclk_int,
-- DCM_LOCKED_OUT => tx_usrclk_lock_int,
-- CLK_IN => ref_clk_buf_int,
-- DCM_RESET_IN => ref_clk_rst_int
-- );
-- Logic to apply DCM reset for 3 CLKIN cycles
process(ref_clk_buf_int, ref_clk_rst_int)
begin
if(ref_clk_rst_int='1') then
count_to_dcm_reset <= "00";
elsif(ref_clk_buf_int'event and ref_clk_buf_int='1') then
if(count_to_dcm_reset<"11") then
count_to_dcm_reset <= count_to_dcm_reset + '1';
else
count_to_dcm_reset <= count_to_dcm_reset;
end if;
end if;
end process;
reset_to_dcm <= '1' when (count_to_dcm_reset <"11") else
'0';
-- Instantiate a DCM module to divide the reference clock.
clock_divider_i : DCM_BASE
generic map
(
CLKDV_DIVIDE => 2.0,
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DCM_PERFORMANCE_MODE => "MAX_SPEED"
)
port map
(
CLK0 => clk0_i,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLKDV => clkdv_i,
CLKFX => open,
CLKFX180 => open,
LOCKED => tx_usrclk_lock_int,
CLKFB => clkfb_i,
CLKIN => ref_clk_buf_int,
RST => reset_to_dcm
);
dcm_1x_bufg_i : BUFG
port map
(
I => clk0_i,
O => clkfb_i
);
tx_usrclk2_int <= clkfb_i;
dcm_div2_bufg_i : BUFG
port map
(
I => clkdv_i,
O => tx_usrclk_int
);
pll_adv_i : PLL_ADV
generic map
(
CLKFBOUT_MULT => 18,
DIVCLK_DIVIDE => 1,
CLKFBOUT_PHASE => 0.0,
CLKIN1_PERIOD => 16.0,
CLKIN2_PERIOD => 10.0, -- Not used
CLKOUT0_DIVIDE => 18,
CLKOUT0_PHASE => 0.0,
CLKOUT1_DIVIDE => 9,
CLKOUT1_PHASE => 0.0,
CLKOUT2_DIVIDE => 1,
CLKOUT2_PHASE => 0.0,
CLKOUT3_DIVIDE => 1,
CLKOUT3_PHASE => 0.0
)
port map
(
CLKIN1 => rx_rec_clk_buf_int,
CLKIN2 => tied_to_ground_i,
CLKINSEL => tied_to_vcc_i,
CLKFBIN => clkfbout_i,
CLKOUT0 => clkout0_i,
CLKOUT1 => clkout1_i,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKFBOUT => clkfbout_i,
CLKFBDCM => open,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
DO => open,
DRDY => open,
DADDR => tied_to_ground_vec_i(4 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DWE => tied_to_ground_i,
REL => tied_to_ground_i,
LOCKED => pll_lk_out,
RST => ref_clk_rst_int
);
clkout0_bufg_i : BUFG
port map
(
O => rx_usrclk_int,
I => clkout0_i
);
clkout1_bufg_i : BUFG
port map
(
O => rx_usrclk2_int,
I => clkout1_i
);
--lockwait_count : if SIMULATION_P = 1 generate
--
-- -- lock not valid until 100us after PLL is released from reset
-- process(rx_rec_clk_buf_int, ref_clk_rst_int)
-- begin
-- if (ref_clk_rst_int = '1') then
-- lock_wait_counter <= "0000000000000000";
-- pll_locked_out_r <= '0';
-- time_elapsed <= '0';
-- elsif (rx_rec_clk_buf_int'event and rx_rec_clk_buf_int = '1') then
-- if (lock_wait_counter = "0001100001101010" or (time_elapsed = '1')) then
-- pll_locked_out_r <= pll_lk_out;
-- time_elapsed <= '1';
-- else
-- lock_wait_counter <= lock_wait_counter + 1;
-- end if;
-- end if;
-- end process;
--
-- rx_usrclk_lock_int <= pll_locked_out_r;
--
-- end generate lockwait_count; -- end SIMULATION_P=1 generate section
--
-- no_lockwait_count : if SIMULATION_P = 0 generate
rx_usrclk_lock_int <= pll_lk_out;
--end generate no_lockwait_count; -- End generate for SIMULATION_P
-- rxrecclk_pll1_i : MGT_USRCLK_SOURCE_PLL
-- generic map
-- (
-- MULT => 18,
-- DIVIDE => 1,
-- CLK_PERIOD => 16.0,
-- OUT0_DIVIDE => 18,
-- OUT1_DIVIDE => 9,
-- OUT2_DIVIDE => 1,
-- OUT3_DIVIDE => 1,
-- SIMULATION_P => 1,
-- LOCK_WAIT_COUNT => "0001100001101010"
-- )
-- port map
-- (
-- CLK0_OUT => rx_usrclk_int,
-- CLK1_OUT => rx_usrclk2_int,
-- CLK2_OUT => open,
-- CLK3_OUT => open,
-- CLK_IN => rx_rec_clk_buf_int,
-- PLL_LOCKED_OUT => rx_usrclk_lock_int,
-- PLL_RESET_IN => ref_clk_rst_int
-- );
tx_rst_int <= not tx_usrclk_lock_int;
rx_rst_int <= not rx_usrclk_lock_int;
gtx_dual_i: GTX_DUAL
generic map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS_0 => TRUE,
SIM_RECEIVER_DETECT_PASS_1 => TRUE,
SIM_MODE => "FAST",
SIM_GTXRESET_SPEEDUP => 0,
SIM_PLL_PERDIV2 => x"0c8",
--___________________________ Shared Attributes ________________________
-------------------------- Tile and PLL Attributes ---------------------
CLK25_DIVIDER => 5,
CLKINDC_B => TRUE,
CLKRCV_TRST => TRUE,
OOB_CLK_DIVIDER => 4,
OVERSAMPLE_MODE => FALSE,
PLL_COM_CFG => x"21680a",
PLL_CP_CFG => x"00",
PLL_DIVSEL_FB => 4,
PLL_DIVSEL_REF => 1,
PLL_FB_DCCEN => FALSE,
PLL_LKDET_CFG => "101",
PLL_TDCC_CFG => "000",
PMA_COM_CFG => x"000000000000000000",
--____________________ Transmit Interface Attributes ___________________
------------------- TX Buffering and Phase Alignment -------------------
TX_BUFFER_USE_0 => FALSE,
TX_XCLK_SEL_0 => "TXUSR",
TXRX_INVERT_0 => "111",
TX_BUFFER_USE_1 => FALSE,
TX_XCLK_SEL_1 => "TXUSR",
TXRX_INVERT_1 => "111",
--------------------- TX Gearbox Settings -----------------------------
GEARBOX_ENDEC_0 => "000",
TXGEARBOX_USE_0 => FALSE,
GEARBOX_ENDEC_1 => "000",
TXGEARBOX_USE_1 => FALSE,
--------------------- TX Serial Line Rate settings ---------------------
PLL_TXDIVSEL_OUT_0 => 4,
PLL_TXDIVSEL_OUT_1 => 4,
--------------------- TX Driver and OOB signalling --------------------
CM_TRIM_0 => "10",
PMA_TX_CFG_0 => x"80082",
TX_DETECT_RX_CFG_0 => x"1832",
TX_IDLE_DELAY_0 => "010",
CM_TRIM_1 => "10",
PMA_TX_CFG_1 => x"80082",
TX_DETECT_RX_CFG_1 => x"1832",
TX_IDLE_DELAY_1 => "010",
------------------ TX Pipe Control for PCI Express/SATA ---------------
COM_BURST_VAL_0 => "1111",
COM_BURST_VAL_1 => "1111",
--_______________________ Receive Interface Attributes ________________
------------ RX Driver,OOB signalling,Coupling and Eq,CDR -------------
AC_CAP_DIS_0 => TRUE,
OOBDETECT_THRESHOLD_0 => "111",
PMA_CDR_SCAN_0 => x"6404035",
PMA_RX_CFG_0 => x"0f44088",
RCV_TERM_GND_0 => FALSE,
RCV_TERM_VTTRX_0 => FALSE,
TERMINATION_IMP_0 => 50,
AC_CAP_DIS_1 => TRUE,
OOBDETECT_THRESHOLD_1 => "111",
PMA_CDR_SCAN_1 => x"6404035",
PMA_RX_CFG_1 => x"0f44088",
RCV_TERM_GND_1 => FALSE,
RCV_TERM_VTTRX_1 => FALSE,
TERMINATION_IMP_1 => 50,
TERMINATION_CTRL => "10100",
TERMINATION_OVRD => FALSE,
---------------- RX Decision Feedback Equalizer(DFE) ----------------
DFE_CFG_0 => "1001111011",
DFE_CFG_1 => "1001111011",
DFE_CAL_TIME => "00110",
--------------------- RX Serial Line Rate Attributes ------------------
PLL_RXDIVSEL_OUT_0 => 4,
PLL_SATA_0 => FALSE,
PLL_RXDIVSEL_OUT_1 => 4,
PLL_SATA_1 => FALSE,
----------------------- PRBS Detection Attributes ---------------------
PRBS_ERR_THRESHOLD_0 => x"00000001",
PRBS_ERR_THRESHOLD_1 => x"00000001",
---------------- Comma Detection and Alignment Attributes -------------
ALIGN_COMMA_WORD_0 => 1,
COMMA_10B_ENABLE_0 => "0001111111",
COMMA_DOUBLE_0 => FALSE,
DEC_MCOMMA_DETECT_0 => FALSE,
DEC_PCOMMA_DETECT_0 => FALSE,
DEC_VALID_COMMA_ONLY_0 => FALSE,
MCOMMA_10B_VALUE_0 => "1010000011",
MCOMMA_DETECT_0 => FALSE,
PCOMMA_10B_VALUE_0 => "0101111100",
PCOMMA_DETECT_0 => FALSE,
RX_SLIDE_MODE_0 => "PCS",
ALIGN_COMMA_WORD_1 => 1,
COMMA_10B_ENABLE_1 => "0001111111",
COMMA_DOUBLE_1 => FALSE,
DEC_MCOMMA_DETECT_1 => FALSE,
DEC_PCOMMA_DETECT_1 => FALSE,
DEC_VALID_COMMA_ONLY_1 => FALSE,
MCOMMA_10B_VALUE_1 => "1010000011",
MCOMMA_DETECT_1 => FALSE,
PCOMMA_10B_VALUE_1 => "0101111100",
PCOMMA_DETECT_1 => FALSE,
RX_SLIDE_MODE_1 => "PCS",
------------------ RX Loss-of-sync State Machine Attributes -----------
RX_LOSS_OF_SYNC_FSM_0 => FALSE,
RX_LOS_INVALID_INCR_0 => 8,
RX_LOS_THRESHOLD_0 => 128,
RX_LOSS_OF_SYNC_FSM_1 => FALSE,
RX_LOS_INVALID_INCR_1 => 8,
RX_LOS_THRESHOLD_1 => 128,
--------------------- RX Gearbox Settings -----------------------------
RXGEARBOX_USE_0 => FALSE,
RXGEARBOX_USE_1 => FALSE,
-------------- RX Elastic Buffer and Phase alignment Attributes -------
PMA_RXSYNC_CFG_0 => x"00",
RX_BUFFER_USE_0 => FALSE,
RX_XCLK_SEL_0 => "RXUSR",
PMA_RXSYNC_CFG_1 => x"00",
RX_BUFFER_USE_1 => FALSE,
RX_XCLK_SEL_1 => "RXUSR",
------------------------ Clock Correction Attributes ------------------
CLK_CORRECT_USE_0 => FALSE,
CLK_COR_ADJ_LEN_0 => 2,
CLK_COR_DET_LEN_0 => 2,
CLK_COR_INSERT_IDLE_FLAG_0 => FALSE,
CLK_COR_KEEP_IDLE_0 => FALSE,
CLK_COR_MAX_LAT_0 => 20,
CLK_COR_MIN_LAT_0 => 16,
CLK_COR_PRECEDENCE_0 => TRUE,
CLK_COR_REPEAT_WAIT_0 => 0,
CLK_COR_SEQ_1_1_0 => "0000000000",
CLK_COR_SEQ_1_2_0 => "0000000000",
CLK_COR_SEQ_1_3_0 => "0000000000",
CLK_COR_SEQ_1_4_0 => "0000000000",
CLK_COR_SEQ_1_ENABLE_0 => "0000",
CLK_COR_SEQ_2_1_0 => "0000000000",
CLK_COR_SEQ_2_2_0 => "0000000000",
CLK_COR_SEQ_2_3_0 => "0000000000",
CLK_COR_SEQ_2_4_0 => "0000000000",
CLK_COR_SEQ_2_ENABLE_0 => "0000",
CLK_COR_SEQ_2_USE_0 => FALSE,
RX_DECODE_SEQ_MATCH_0 => FALSE,
CLK_CORRECT_USE_1 => FALSE,
CLK_COR_ADJ_LEN_1 => 2,
CLK_COR_DET_LEN_1 => 2,
CLK_COR_INSERT_IDLE_FLAG_1 => FALSE,
CLK_COR_KEEP_IDLE_1 => FALSE,
CLK_COR_MAX_LAT_1 => 20,
CLK_COR_MIN_LAT_1 => 16,
CLK_COR_PRECEDENCE_1 => TRUE,
CLK_COR_REPEAT_WAIT_1 => 0,
CLK_COR_SEQ_1_1_1 => "0000000000",
CLK_COR_SEQ_1_2_1 => "0000000000",
CLK_COR_SEQ_1_3_1 => "0000000000",
CLK_COR_SEQ_1_4_1 => "0000000000",
CLK_COR_SEQ_1_ENABLE_1 => "0000",
CLK_COR_SEQ_2_1_1 => "0000000000",
CLK_COR_SEQ_2_2_1 => "0000000000",
CLK_COR_SEQ_2_3_1 => "0000000000",
CLK_COR_SEQ_2_4_1 => "0000000000",
CLK_COR_SEQ_2_ENABLE_1 => "0000",
CLK_COR_SEQ_2_USE_1 => FALSE,
RX_DECODE_SEQ_MATCH_1 => FALSE,
------------------------ Channel Bonding Attributes -------------------
CB2_INH_CC_PERIOD_0 => 8,
CHAN_BOND_1_MAX_SKEW_0 => 1,
CHAN_BOND_2_MAX_SKEW_0 => 1,
CHAN_BOND_KEEP_ALIGN_0 => FALSE,
CHAN_BOND_LEVEL_0 => 0,
CHAN_BOND_MODE_0 => "OFF",
CHAN_BOND_SEQ_1_1_0 => "0000000000",
CHAN_BOND_SEQ_1_2_0 => "0000000000",
CHAN_BOND_SEQ_1_3_0 => "0000000000",
CHAN_BOND_SEQ_1_4_0 => "0000000000",
CHAN_BOND_SEQ_1_ENABLE_0 => "0000",
CHAN_BOND_SEQ_2_1_0 => "0000000000",
CHAN_BOND_SEQ_2_2_0 => "0000000000",
CHAN_BOND_SEQ_2_3_0 => "0000000000",
CHAN_BOND_SEQ_2_4_0 => "0000000000",
CHAN_BOND_SEQ_2_ENABLE_0 => "0000",
CHAN_BOND_SEQ_2_USE_0 => FALSE,
CHAN_BOND_SEQ_LEN_0 => 1,
PCI_EXPRESS_MODE_0 => FALSE,
CB2_INH_CC_PERIOD_1 => 8,
CHAN_BOND_1_MAX_SKEW_1 => 1,
CHAN_BOND_2_MAX_SKEW_1 => 1,
CHAN_BOND_KEEP_ALIGN_1 => FALSE,
CHAN_BOND_LEVEL_1 => 0,
CHAN_BOND_MODE_1 => "OFF",
CHAN_BOND_SEQ_1_1_1 => "0000000000",
CHAN_BOND_SEQ_1_2_1 => "0000000000",
CHAN_BOND_SEQ_1_3_1 => "0000000000",
CHAN_BOND_SEQ_1_4_1 => "0000000000",
CHAN_BOND_SEQ_1_ENABLE_1 => "0000",
CHAN_BOND_SEQ_2_1_1 => "0000000000",
CHAN_BOND_SEQ_2_2_1 => "0000000000",
CHAN_BOND_SEQ_2_3_1 => "0000000000",
CHAN_BOND_SEQ_2_4_1 => "0000000000",
CHAN_BOND_SEQ_2_ENABLE_1 => "0000",
CHAN_BOND_SEQ_2_USE_1 => FALSE,
CHAN_BOND_SEQ_LEN_1 => 1,
PCI_EXPRESS_MODE_1 => FALSE,
-------- RX Attributes to Control Reset after Electrical Idle ------
RX_EN_IDLE_HOLD_DFE_0 => TRUE,
RX_EN_IDLE_RESET_BUF_0 => TRUE,
RX_IDLE_HI_CNT_0 => "1000",
RX_IDLE_LO_CNT_0 => "0000",
RX_EN_IDLE_HOLD_DFE_1 => TRUE,
RX_EN_IDLE_RESET_BUF_1 => TRUE,
RX_IDLE_HI_CNT_1 => "1000",
RX_IDLE_LO_CNT_1 => "0000",
CDR_PH_ADJ_TIME => "01010",
RX_EN_IDLE_RESET_FR => TRUE,
RX_EN_IDLE_HOLD_CDR => FALSE,
RX_EN_IDLE_RESET_PH => TRUE,
------------------ RX Attributes for PCI Express/SATA ---------------
RX_STATUS_FMT_0 => "PCIE",
SATA_BURST_VAL_0 => "100",
SATA_IDLE_VAL_0 => "100",
SATA_MAX_BURST_0 => 9,
SATA_MAX_INIT_0 => 27,
SATA_MAX_WAKE_0 => 9,
SATA_MIN_BURST_0 => 5,
SATA_MIN_INIT_0 => 15,
SATA_MIN_WAKE_0 => 5,
TRANS_TIME_FROM_P2_0 => x"003c",
TRANS_TIME_NON_P2_0 => x"0019",
TRANS_TIME_TO_P2_0 => x"0064",
RX_STATUS_FMT_1 => "PCIE",
SATA_BURST_VAL_1 => "100",
SATA_IDLE_VAL_1 => "100",
SATA_MAX_BURST_1 => 9,
SATA_MAX_INIT_1 => 27,
SATA_MAX_WAKE_1 => 9,
SATA_MIN_BURST_1 => 5,
SATA_MIN_INIT_1 => 15,
SATA_MIN_WAKE_1 => 5,
TRANS_TIME_FROM_P2_1 => x"003c",
TRANS_TIME_NON_P2_1 => x"0019",
TRANS_TIME_TO_P2_1 => x"0064"
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0 => tied_to_ground_vec_i(2 downto 0),
LOOPBACK1 => tied_to_ground_vec_i(2 downto 0),
RXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
RXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
-------------- Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
RXDATAVALID0 => open,
RXDATAVALID1 => open,
RXGEARBOXSLIP0 => tied_to_ground_i,
RXGEARBOXSLIP1 => tied_to_ground_i,
RXHEADER0 => open,
RXHEADER1 => open,
RXHEADERVALID0 => open,
RXHEADERVALID1 => open,
RXSTARTOFSEQ0 => open,
RXSTARTOFSEQ1 => open,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA0 => open,
RXCHARISCOMMA1 => open,
RXCHARISK0 => rxcharisk0_i,
RXCHARISK1 => rxcharisk1_i,
RXDEC8B10BUSE0 => tied_to_ground_i,
RXDEC8B10BUSE1 => tied_to_ground_i,
RXDISPERR0 => rxdisperr0_i,
RXDISPERR1 => rxdisperr1_i,
RXNOTINTABLE0 => open,
RXNOTINTABLE1 => open,
RXRUNDISP0 => open,
RXRUNDISP1 => open,
------------------- Receive Ports - Channel Bonding Ports ------------------
RXCHANBONDSEQ0 => open,
RXCHANBONDSEQ1 => open,
RXCHBONDI0 => tied_to_ground_vec_i(3 downto 0),
RXCHBONDI1 => tied_to_ground_vec_i(3 downto 0),
RXCHBONDO0 => open,
RXCHBONDO1 => open,
RXENCHANSYNC0 => tied_to_ground_i,
RXENCHANSYNC1 => tied_to_ground_i,
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT0 => open,
RXCLKCORCNT1 => open,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0 => open,
RXBYTEISALIGNED1 => open,
RXBYTEREALIGN0 => open,
RXBYTEREALIGN1 => open,
RXCOMMADET0 => open,
RXCOMMADET1 => open,
RXCOMMADETUSE0 => tied_to_vcc_i,
RXCOMMADETUSE1 => tied_to_vcc_i,
RXENMCOMMAALIGN0 => tied_to_ground_i,
RXENMCOMMAALIGN1 => tied_to_ground_i,
RXENPCOMMAALIGN0 => tied_to_ground_i,
RXENPCOMMAALIGN1 => tied_to_ground_i,
RXSLIDE0 => bitslip,
RXSLIDE1 => bitslip,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET0 => tied_to_ground_i,
PRBSCNTRESET1 => tied_to_ground_i,
RXENPRBSTST0 => tied_to_ground_vec_i(1 downto 0),
RXENPRBSTST1 => tied_to_ground_vec_i(1 downto 0),
RXPRBSERR0 => open,
RXPRBSERR1 => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0 => rxdata0_i,
RXDATA1 => rxdata1_i,
RXDATAWIDTH0 => "00",
RXDATAWIDTH1 => "00",
RXRECCLK0 => rx_rec_clk0_int,
RXRECCLK1 => rx_rec_clk1_int,
RXRESET0 => rx_rst_int,
RXRESET1 => rx_rst_int,
RXUSRCLK0 => rx_usrclk_int,
RXUSRCLK1 => rx_usrclk_int,
RXUSRCLK20 => rx_usrclk2_int,
RXUSRCLK21 => rx_usrclk2_int,
------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
DFECLKDLYADJ0 => tied_to_ground_vec_i(5 downto 0),
DFECLKDLYADJ1 => tied_to_ground_vec_i(5 downto 0),
DFECLKDLYADJMONITOR0 => open,
DFECLKDLYADJMONITOR1 => open,
DFEEYEDACMONITOR0 => open,
DFEEYEDACMONITOR1 => open,
DFESENSCAL0 => open,
DFESENSCAL1 => open,
DFETAP10 => tied_to_ground_vec_i(4 downto 0),
DFETAP11 => tied_to_ground_vec_i(4 downto 0),
DFETAP1MONITOR0 => open,
DFETAP1MONITOR1 => open,
DFETAP20 => tied_to_ground_vec_i(4 downto 0),
DFETAP21 => tied_to_ground_vec_i(4 downto 0),
DFETAP2MONITOR0 => open,
DFETAP2MONITOR1 => open,
DFETAP30 => tied_to_ground_vec_i(3 downto 0),
DFETAP31 => tied_to_ground_vec_i(3 downto 0),
DFETAP3MONITOR0 => open,
DFETAP3MONITOR1 => open,
DFETAP40 => tied_to_ground_vec_i(3 downto 0),
DFETAP41 => tied_to_ground_vec_i(3 downto 0),
DFETAP4MONITOR0 => open,
DFETAP4MONITOR1 => open,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET0 => tied_to_ground_i,
RXCDRRESET1 => tied_to_ground_i,
RXELECIDLE0 => open,
RXELECIDLE1 => open,
RXENEQB0 => tied_to_ground_i,
RXENEQB1 => tied_to_ground_i,
RXEQMIX0 => "11",
RXEQMIX1 => "11",
RXEQPOLE0 => "0000",
RXEQPOLE1 => "0000",
RXN0 => rx_in0_n,
RXN1 => rx_in1_n,
RXP0 => rx_in0_p,
RXP1 => rx_in1_p,
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
RXBUFRESET0 => tied_to_ground_i,
RXBUFRESET1 => tied_to_ground_i,
RXBUFSTATUS0 => open,
RXBUFSTATUS1 => open,
RXCHANISALIGNED0 => open,
RXCHANISALIGNED1 => open,
RXCHANREALIGN0 => open,
RXCHANREALIGN1 => open,
RXENPMAPHASEALIGN0 => tied_to_ground_i,
RXENPMAPHASEALIGN1 => tied_to_ground_i,
RXPMASETPHASE0 => tied_to_ground_i,
RXPMASETPHASE1 => tied_to_ground_i,
RXSTATUS0 => open,
RXSTATUS1 => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0 => open,
RXLOSSOFSYNC1 => open,
---------------------- Receive Ports - RX Oversampling ---------------------
RXENSAMPLEALIGN0 => tied_to_ground_i,
RXENSAMPLEALIGN1 => tied_to_ground_i,
RXOVERSAMPLEERR0 => open,
RXOVERSAMPLEERR1 => open,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0 => open,
PHYSTATUS1 => open,
RXVALID0 => open,
RXVALID1 => open,
----------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY0 => tied_to_ground_i,
RXPOLARITY1 => tied_to_ground_i,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => tied_to_ground_vec_i(6 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DO => open,
DRDY => open,
DWE => tied_to_ground_i,
--------------------- Shared Ports - Tile and PLL Ports --------------------
CLKIN => clk_125,
GTXRESET => rst_125,
GTXTEST => "10000000000000",
INTDATAWIDTH => tied_to_vcc_i,
PLLLKDET => ref_clk_lock_int,
PLLLKDETEN => tied_to_vcc_i,
PLLPOWERDOWN => tied_to_ground_i,
REFCLKOUT => ref_clk_int,
REFCLKPWRDNB => tied_to_vcc_i,
RESETDONE0 => rst_done0_int,
RESETDONE1 => rst_done1_int,
-------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
TXGEARBOXREADY0 => open,
TXGEARBOXREADY1 => open,
TXHEADER0 => tied_to_ground_vec_i(2 downto 0),
TXHEADER1 => tied_to_ground_vec_i(2 downto 0),
TXSEQUENCE0 => tied_to_ground_vec_i(6 downto 0),
TXSEQUENCE1 => tied_to_ground_vec_i(6 downto 0),
TXSTARTSEQ0 => tied_to_ground_i,
TXSTARTSEQ1 => tied_to_ground_i,
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXBYPASS8B10B0 => tied_to_ground_vec_i(3 downto 0),
TXBYPASS8B10B1 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE0 => txchardispmode0_i,
TXCHARDISPMODE1 => txchardispmode1_i,
TXCHARDISPVAL0 => txchardispval0_i,
TXCHARDISPVAL1 => txchardispval1_i,
TXCHARISK0 => tied_to_ground_vec_i(3 downto 0),
TXCHARISK1 => tied_to_ground_vec_i(3 downto 0),
TXENC8B10BUSE0 => tied_to_ground_i,
TXENC8B10BUSE1 => tied_to_ground_i,
TXKERR0 => open,
TXKERR1 => open,
TXRUNDISP0 => open,
TXRUNDISP1 => open,
------------- Transmit Ports - TX Buffering and Phase Alignment ------------
TXBUFSTATUS0 => open,
TXBUFSTATUS1 => open,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0 => txdata0_i,
TXDATA1 => txdata1_i,
TXDATAWIDTH0 => "00",
TXDATAWIDTH1 => "00",
TXOUTCLK0 => open,
TXOUTCLK1 => open,
TXRESET0 => tx_rst_int,
TXRESET1 => tx_rst_int,
TXUSRCLK0 => tx_usrclk_int,
TXUSRCLK1 => tx_usrclk_int,
TXUSRCLK20 => tx_usrclk2_int,
TXUSRCLK21 => tx_usrclk2_int,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXBUFDIFFCTRL0 => "101",
TXBUFDIFFCTRL1 => "101",
TXDIFFCTRL0 => "000",
TXDIFFCTRL1 => "000",
TXINHIBIT0 => tied_to_ground_i,
TXINHIBIT1 => tied_to_ground_i,
TXN0 => tx_out0_n,
TXN1 => tx_out1_n,
TXP0 => tx_out0_p,
TXP1 => tx_out1_p,
TXPREEMPHASIS0 => "0000",
TXPREEMPHASIS1 => "0000",
-------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
TXENPMAPHASEALIGN0 => tied_to_ground_i,
TXENPMAPHASEALIGN1 => tied_to_ground_i,
TXPMASETPHASE0 => tied_to_ground_i,
TXPMASETPHASE1 => tied_to_ground_i,
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST0 => tied_to_ground_vec_i(1 downto 0),
TXENPRBSTST1 => tied_to_ground_vec_i(1 downto 0),
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY0 => tied_to_ground_i,
TXPOLARITY1 => tied_to_ground_i,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0 => tied_to_ground_i,
TXDETECTRX1 => tied_to_ground_i,
TXELECIDLE0 => tied_to_ground_i,
TXELECIDLE1 => tied_to_ground_i,
--------------------- Transmit Ports - TX Ports for SATA -------------------
TXCOMSTART0 => tied_to_ground_i,
TXCOMSTART1 => tied_to_ground_i,
TXCOMTYPE0 => tied_to_ground_i,
TXCOMTYPE1 => tied_to_ground_i
);
end generate;
end architecture ;
|
gpl-2.0
|
476577d44f442aa0a136fe48d2e1e13c
| 0.376501 | 4.269871 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/ec/memory_ec.vhd
| 1 | 92,635 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_ec_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Lattice XP/EC/ECP RAM blocks
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S1_S1 is
port (
DataInA: in std_logic_vector(0 downto 0);
DataInB: in std_logic_vector(0 downto 0);
AddressA: in std_logic_vector(12 downto 0);
AddressB: in std_logic_vector(12 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(0 downto 0);
QB: out std_logic_vector(0 downto 0));
end;
architecture Structure of EC_RAMB8_S1_S1 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 1)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>gnd, DIA1=>gnd, DIA2=>gnd,
DIA3=>gnd, DIA4=>gnd, DIA5=>gnd,
DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
DIA9=>gnd, DIA10=>gnd, DIA11=>DataInA(0),
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>AddressA(0), ADA1=>AddressA(1), ADA2=>AddressA(2),
ADA3=>AddressA(3), ADA4=>AddressA(4), ADA5=>AddressA(5),
ADA6=>AddressA(6), ADA7=>AddressA(7), ADA8=>AddressA(8),
ADA9=>AddressA(9), ADA10=>AddressA(10), ADA11=>AddressA(11),
ADA12=>AddressA(12), DIB0=>gnd, DIB1=>gnd,
DIB2=>gnd, DIB3=>gnd, DIB4=>gnd,
DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
DIB11=>DataInB(0), DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>AddressB(0), ADB1=>AddressB(1),
ADB2=>AddressB(2), ADB3=>AddressB(3), ADB4=>AddressB(4),
ADB5=>AddressB(5), ADB6=>AddressB(6), ADB7=>AddressB(7),
ADB8=>AddressB(8), ADB9=>AddressB(9), ADB10=>AddressB(10),
ADB11=>AddressB(11), ADB12=>AddressB(12), DOA0=>QA(0),
DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(0), DOB1=>open, DOB2=>open,
DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S2_S2 is
port (
DataInA: in std_logic_vector(1 downto 0);
DataInB: in std_logic_vector(1 downto 0);
AddressA: in std_logic_vector(11 downto 0);
AddressB: in std_logic_vector(11 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(1 downto 0);
QB: out std_logic_vector(1 downto 0));
end;
architecture Structure of EC_RAMB8_S2_S2 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 2, DATA_WIDTH_A=> 2)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>gnd, DIA1=>DataInA(0), DIA2=>gnd,
DIA3=>gnd, DIA4=>gnd, DIA5=>gnd,
DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
DIA9=>gnd, DIA10=>gnd, DIA11=>DataInA(1),
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>vcc, ADA1=>AddressA(0), ADA2=>AddressA(1),
ADA3=>AddressA(2), ADA4=>AddressA(3), ADA5=>AddressA(4),
ADA6=>AddressA(6), ADA7=>AddressA(6), ADA8=>AddressA(7),
ADA9=>AddressA(8), ADA10=>AddressA(9), ADA11=>AddressA(10),
ADA12=>AddressA(11), DIB0=>gnd, DIB1=>DataInB(0),
DIB2=>gnd, DIB3=>gnd, DIB4=>gnd,
DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
DIB11=>DataInB(1), DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>vcc, ADB1=>AddressB(0),
ADB2=>AddressB(1), ADB3=>AddressB(2), ADB4=>AddressB(3),
ADB5=>AddressB(4), ADB6=>AddressB(5), ADB7=>AddressB(6),
ADB8=>AddressB(7), ADB9=>AddressB(8), ADB10=>AddressB(9),
ADB11=>AddressB(10), ADB12=>AddressB(11), DOA0=>QA(1),
DOA1=>QA(0), DOA2=>open, DOA3=>open, DOA4=>open,
DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(1), DOB1=>QB(0), DOB2=>open,
DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S4_S4 is
port (
DataInA: in std_logic_vector(3 downto 0);
DataInB: in std_logic_vector(3 downto 0);
AddressA: in std_logic_vector(10 downto 0);
AddressB: in std_logic_vector(10 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(3 downto 0);
QB: out std_logic_vector(3 downto 0));
end;
architecture Structure of EC_RAMB8_S4_S4 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 4, DATA_WIDTH_A=> 4)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
DIA3=>DataInA(3), DIA4=>gnd, DIA5=>gnd,
DIA6=>gnd, DIA7=>gnd, DIA8=>gnd,
DIA9=>gnd, DIA10=>gnd, DIA11=>gnd,
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>vcc, ADA1=>vcc, ADA2=>AddressA(0),
ADA3=>AddressA(1), ADA4=>AddressA(2), ADA5=>AddressA(3),
ADA6=>AddressA(4), ADA7=>AddressA(5), ADA8=>AddressA(6),
ADA9=>AddressA(7), ADA10=>AddressA(8), ADA11=>AddressA(9),
ADA12=>AddressA(10), DIB0=>DataInB(0), DIB1=>DataInB(1),
DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>gnd,
DIB5=>gnd, DIB6=>gnd, DIB7=>gnd,
DIB8=>gnd, DIB9=>gnd, DIB10=>gnd,
DIB11=>gnd, DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>vcc, ADB1=>vcc,
ADB2=>AddressB(0), ADB3=>AddressB(1), ADB4=>AddressB(2),
ADB5=>AddressB(3), ADB6=>AddressB(4), ADB7=>AddressB(5),
ADB8=>AddressB(6), ADB9=>AddressB(7), ADB10=>AddressB(8),
ADB11=>AddressB(9), ADB12=>AddressB(10), DOA0=>QA(0),
DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>open,
DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
DOB3=>QB(3), DOB4=>open, DOB5=>open, DOB6=>open,
DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S9_S9 is
port (
DataInA: in std_logic_vector(8 downto 0);
DataInB: in std_logic_vector(8 downto 0);
AddressA: in std_logic_vector(9 downto 0);
AddressB: in std_logic_vector(9 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(8 downto 0);
QB: out std_logic_vector(8 downto 0));
end;
architecture Structure of EC_RAMB8_S9_S9 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
DIA9=>gnd, DIA10=>gnd, DIA11=>gnd,
DIA12=>gnd, DIA13=>gnd, DIA14=>gnd,
DIA15=>gnd, DIA16=>gnd, DIA17=>gnd,
ADA0=>vcc, ADA1=>vcc, ADA2=>gnd,
ADA3=>AddressA(0), ADA4=>AddressA(1), ADA5=>AddressA(2),
ADA6=>AddressA(3), ADA7=>AddressA(4), ADA8=>AddressA(5),
ADA9=>AddressA(6), ADA10=>AddressA(7), ADA11=>AddressA(8),
ADA12=>AddressA(9), DIB0=>DataInB(0), DIB1=>DataInB(1),
DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>DataInB(4),
DIB5=>DataInB(5), DIB6=>DataInB(6), DIB7=>DataInB(7),
DIB8=>DataInB(8), DIB9=>gnd, DIB10=>gnd,
DIB11=>gnd, DIB12=>gnd, DIB13=>gnd,
DIB14=>gnd, DIB15=>gnd, DIB16=>gnd,
DIB17=>gnd, ADB0=>vcc, ADB1=>vcc,
ADB2=>gnd, ADB3=>AddressB(0), ADB4=>AddressB(1),
ADB5=>AddressB(2), ADB6=>AddressB(3), ADB7=>AddressB(4),
ADB8=>AddressB(5), ADB9=>AddressB(6), ADB10=>AddressB(7),
ADB11=>AddressB(8), ADB12=>AddressB(9), DOA0=>QA(0),
DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4),
DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8),
DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
DOA17=>open, DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6),
DOB7=>QB(7), DOB8=>QB(8), DOB9=>open, DOB10=>open,
DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S18_S18 is
port (
DataInA: in std_logic_vector(17 downto 0);
DataInB: in std_logic_vector(17 downto 0);
AddressA: in std_logic_vector(8 downto 0);
AddressB: in std_logic_vector(8 downto 0);
ClockA: in std_logic;
ClockB: in std_logic;
ClockEnA: in std_logic;
ClockEnB: in std_logic;
WrA: in std_logic;
WrB: in std_logic;
QA: out std_logic_vector(17 downto 0);
QB: out std_logic_vector(17 downto 0));
end;
architecture Structure of EC_RAMB8_S18_S18 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL",
GSR=>"DISABLED", RESETMODE=>"ASYNC", REGMODE_B=>"NOREG",
REGMODE_A=>"NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
port map (CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=>gnd,
CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB0=>gnd,
CSB1=>gnd, CSB2=>gnd, RSTB=>gnd,
DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11),
DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14),
DIA15=>DataInA(15), DIA16=>DataInA(16), DIA17=>DataInA(17),
ADA0=>vcc, ADA1=>vcc, ADA2=>gnd,
ADA3=>gnd, ADA4=>AddressA(0), ADA5=>AddressA(1),
ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4),
ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7),
ADA12=>AddressA(8), DIB0=>DataInB(0), DIB1=>DataInB(1),
DIB2=>DataInB(2), DIB3=>DataInB(3), DIB4=>DataInB(4),
DIB5=>DataInB(5), DIB6=>DataInB(6), DIB7=>DataInB(7),
DIB8=>DataInB(8), DIB9=>DataInB(9), DIB10=>DataInB(10),
DIB11=>DataInB(11), DIB12=>DataInB(12), DIB13=>DataInB(13),
DIB14=>DataInB(14), DIB15=>DataInB(15), DIB16=>DataInB(16),
DIB17=>DataInB(17), ADB0=>vcc, ADB1=>vcc,
ADB2=>gnd, ADB3=>gnd, ADB4=>AddressB(0),
ADB5=>AddressB(1), ADB6=>AddressB(2), ADB7=>AddressB(3),
ADB8=>AddressB(4), ADB9=>AddressB(5), ADB10=>AddressB(6),
ADB11=>AddressB(7), ADB12=>AddressB(8), DOA0=>QA(0),
DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4),
DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8),
DOA9=>QA(9), DOA10=>QA(10), DOA11=>QA(11), DOA12=>QA(12),
DOA13=>QA(13), DOA14=>QA(14), DOA15=>QA(15), DOA16=>QA(16),
DOA17=>QA(17), DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6),
DOB7=>QB(7), DOB8=>QB(8), DOB9=>QB(9), DOB10=>QB(10),
DOB11=>QB(11), DOB12=>QB(12), DOB13=>QB(13), DOB14=>QB(14),
DOB15=>QB(15), DOB16=>QB(16), DOB17=>QB(17));
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S1 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (12 downto 0);
data : in std_logic_vector (0 downto 0);
q : out std_logic_vector (0 downto 0));
end;
architecture behav of EC_RAMB8_S1 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 1)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>gnd,
DI1=>gnd, DI2=>gnd, DI3=>gnd, DI4=>gnd,
DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
DI9=>gnd, DI10=>gnd, DI11=>Data(0),
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>Address(0), AD1=>Address(1), AD2=>Address(2),
AD3=>Address(3), AD4=>Address(4), AD5=>Address(5),
AD6=>Address(6), AD7=>Address(7), AD8=>Address(8),
AD9=>Address(9), AD10=>Address(10), AD11=>Address(11),
AD12=>Address(12), DO0=>Q(0), DO1=>open, DO2=>open, DO3=>open,
DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S2 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (11 downto 0);
data : in std_logic_vector (1 downto 0);
q : out std_logic_vector (1 downto 0));
end;
architecture behav of EC_RAMB8_S2 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 2)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>gnd,
DI1=>Data(0), DI2=>gnd, DI3=>gnd, DI4=>gnd,
DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
DI9=>gnd, DI10=>gnd, DI11=>Data(1),
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>gnd, AD1=>Address(0), AD2=>Address(1),
AD3=>Address(2), AD4=>Address(3), AD5=>Address(4),
AD6=>Address(5), AD7=>Address(6), AD8=>Address(7),
AD9=>Address(8), AD10=>Address(9), AD11=>Address(10),
AD12=>Address(11), DO0=>Q(1), DO1=>Q(0), DO2=>open, DO3=>open,
DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S4 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (10 downto 0);
data : in std_logic_vector (3 downto 0);
q : out std_logic_vector (3 downto 0));
end;
architecture behav of EC_RAMB8_S4 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 4)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>gnd,
DI5=>gnd, DI6=>gnd, DI7=>gnd, DI8=>gnd,
DI9=>gnd, DI10=>gnd, DI11=>gnd,
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>gnd, AD1=>gnd, AD2=>Address(0),
AD3=>Address(1), AD4=>Address(2), AD5=>Address(3),
AD6=>Address(4), AD7=>Address(5), AD8=>Address(6),
AD9=>Address(7), AD10=>Address(8), AD11=>Address(9),
AD12=>Address(10), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S9 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (9 downto 0);
data : in std_logic_vector (8 downto 0);
q : out std_logic_vector (8 downto 0));
end;
architecture behav of EC_RAMB8_S9 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 9)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>Data(4),
DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), DI8=>Data(8),
DI9=>gnd, DI10=>gnd, DI11=>gnd,
DI12=>gnd, DI13=>gnd, DI14=>gnd,
DI15=>gnd, DI16=>gnd, DI17=>gnd,
AD0=>gnd, AD1=>gnd, AD2=>gnd,
AD3=>Address(0), AD4=>Address(1), AD5=>Address(2),
AD6=>Address(3), AD7=>Address(4), AD8=>Address(5),
AD9=>Address(6), AD10=>Address(7), AD11=>Address(8),
AD12=>Address(9), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8),
DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
DO14=>open, DO15=>open, DO16=>open, DO17=>open);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.sp8ka;
-- pragma translate_on
entity EC_RAMB8_S18 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (8 downto 0);
data : in std_logic_vector (17 downto 0);
q : out std_logic_vector (17 downto 0));
end;
architecture behav of EC_RAMB8_S18 is
COMPONENT sp8ka
GENERIC(
DATA_WIDTH : in Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: SP8KA
generic map (CSDECODE=>"000", GSR=>"DISABLED",
WRITEMODE=>"WRITETHROUGH", RESETMODE=>"ASYNC",
REGMODE=>"NOREG", DATA_WIDTH=> 18)
port map (CE=>En, CLK=>Clk, WE=>WE, CS0=>gnd,
CS1=>gnd, CS2=>gnd, RST=>gnd, DI0=>Data(0),
DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>Data(4),
DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), DI8=>Data(8),
DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
AD0=>gnd, AD1=>gnd, AD2=>gnd,
AD3=>gnd, AD4=>Address(0), AD5=>Address(1),
AD6=>Address(2), AD7=>Address(3), AD8=>Address(4),
AD9=>Address(5), AD10=>Address(6), AD11=>Address(7),
AD12=>Address(8), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8),
DO9=>Q(9), DO10=>Q(10), DO11=>Q(11), DO12=>Q(12), DO13=>Q(13),
DO14=>Q(14), DO15=>Q(15), DO16=>Q(16), DO17=>Q(17));
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.dp8ka;
-- pragma translate_on
entity EC_RAMB8_S36 is
port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (7 downto 0);
data : in std_logic_vector (35 downto 0);
q : out std_logic_vector (35 downto 0));
end;
architecture behav of EC_RAMB8_S36 is
COMPONENT dp8ka
GENERIC(
DATA_WIDTH_A : in Integer := 18;
DATA_WIDTH_B : in Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
END COMPONENT;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
u0: DP8KA
generic map (CSDECODE_B=>"000", CSDECODE_A=>"000",
WRITEMODE_B=>"NORMAL", WRITEMODE_A=>"NORMAL", GSR=>"DISABLED",
RESETMODE=>"ASYNC", REGMODE_B=>"NOREG", REGMODE_A=>"NOREG",
DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
port map (CEA => en, CLKA => clk, WEA => we, CSA0 => gnd,
CSA1=>gnd, CSA2=>gnd, RSTA=> gnd, CEB=> en,
CLKB=> clk, WEB=> we, CSB0=>gnd, CSB1=>gnd,
CSB2=>gnd, RSTB=>gnd, DIA0=>Data(0), DIA1=>Data(1),
DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5),
DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9),
DIA10=>Data(10), DIA11=>Data(11), DIA12=>Data(12),
DIA13=>Data(13), DIA14=>Data(14), DIA15=>Data(15),
DIA16=>Data(16), DIA17=>Data(17), ADA0=>vcc,
ADA1=>vcc, ADA2=>vcc, ADA3=>vcc,
ADA4=>Address(0), ADA5=>Address(1), ADA6=>Address(2),
ADA7=>Address(3), ADA8=>Address(4), ADA9=>Address(5),
ADA10=>Address(6), ADA11=>Address(7), ADA12=>gnd,
DIB0=>Data(18), DIB1=>Data(19), DIB2=>Data(20),
DIB3=>Data(21), DIB4=>Data(22), DIB5=>Data(23),
DIB6=>Data(24), DIB7=>Data(25), DIB8=>Data(26),
DIB9=>Data(27), DIB10=>Data(28), DIB11=>Data(29),
DIB12=>Data(30), DIB13=>Data(31), DIB14=>Data(32),
DIB15=>Data(33), DIB16=>Data(34), DIB17=>Data(35),
ADB0=>vcc, ADB1=>vcc, ADB2=>gnd,
ADB3=>gnd, ADB4=>Address(0), ADB5=>Address(1),
ADB6=>Address(2), ADB7=>Address(3), ADB8=>Address(4),
ADB9=>Address(5), ADB10=>Address(6), ADB11=>Address(7),
ADB12=>vcc, DOA0=>Q(0), DOA1=>Q(1), DOA2=>Q(2),
DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6), DOA7=>Q(7),
DOA8=>Q(8), DOA9=>Q(9), DOA10=>Q(10), DOA11=>Q(11),
DOA12=>Q(12), DOA13=>Q(13), DOA14=>Q(14), DOA15=>Q(15),
DOA16=>Q(16), DOA17=>Q(17), DOB0=>Q(18), DOB1=>Q(19),
DOB2=>Q(20), DOB3=>Q(21), DOB4=>Q(22), DOB5=>Q(23),
DOB6=>Q(24), DOB7=>Q(25), DOB8=>Q(26), DOB9=>Q(27),
DOB10=>Q(28), DOB11=>Q(29), DOB12=>Q(30), DOB13=>Q(31),
DOB14=>Q(32), DOB15=>Q(33), DOB16=>Q(34), DOB17=>Q(35));
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity ec_syncram is
generic (abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of ec_syncram is
component EC_RAMB8_S1 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (12 downto 0);
data : in std_logic_vector (0 downto 0);
q : out std_logic_vector (0 downto 0));
end component;
component EC_RAMB8_S2 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (11 downto 0);
data : in std_logic_vector (1 downto 0);
q : out std_logic_vector (1 downto 0));
end component;
component EC_RAMB8_S4 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (10 downto 0);
data : in std_logic_vector (3 downto 0);
q : out std_logic_vector (3 downto 0));
end component;
component EC_RAMB8_S9 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (9 downto 0);
data : in std_logic_vector (8 downto 0);
q : out std_logic_vector (8 downto 0));
end component;
component EC_RAMB8_S18 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (8 downto 0);
data : in std_logic_vector (17 downto 0);
q : out std_logic_vector (17 downto 0));
end component;
component EC_RAMB8_S36 port (
clk, en, we : in std_ulogic;
address : in std_logic_vector (7 downto 0);
data : in std_logic_vector (35 downto 0);
q : out std_logic_vector (35 downto 0));
end component;
constant DMAX : integer := dbits+36;
constant AMAX : integer := 13;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(DMAX downto 0);
signal xa, ya : std_logic_vector(AMAX downto 0);
begin
gnd <= '0'; dataout <= do(dbits-1 downto 0); di(dbits-1 downto 0) <= datain;
di(DMAX downto dbits) <= (others => '0'); xa(abits-1 downto 0) <= address;
xa(AMAX downto abits) <= (others => '0'); ya(abits-1 downto 0) <= address;
ya(AMAX downto abits) <= (others => '1');
a8 : if (abits <= 8) generate
x : for i in 0 to ((dbits-1)/36) generate
r : EC_RAMB8_S36 port map ( clk, enable, write, xa(7 downto 0),
di((i+1)*36-1 downto i*36), do((i+1)*36-1 downto i*36));
end generate;
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to ((dbits-1)/18) generate
r : EC_RAMB8_S18 port map ( clk, enable, write, xa(8 downto 0),
di((i+1)*18-1 downto i*18), do((i+1)*18-1 downto i*18));
end generate;
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to ((dbits-1)/9) generate
r : EC_RAMB8_S9 port map ( clk, enable, write, xa(9 downto 0),
di((i+1)*9-1 downto i*9), do((i+1)*9-1 downto i*9));
end generate;
end generate;
a11 : if (abits = 11) generate
x : for i in 0 to ((dbits-1)/4) generate
r : EC_RAMB8_S4 port map ( clk, enable, write, xa(10 downto 0),
di((i+1)*4-1 downto i*4), do((i+1)*4-1 downto i*4));
end generate;
end generate;
a12 : if (abits = 12) generate
x : for i in 0 to ((dbits-1)/2) generate
r : EC_RAMB8_S2 port map ( clk, enable, write, xa(11 downto 0),
di((i+1)*2-1 downto i*2), do((i+1)*2-1 downto i*2));
end generate;
end generate;
a13 : if (abits = 13) generate
x : for i in 0 to ((dbits-1)/1) generate
r : EC_RAMB8_S1 port map ( clk, enable, write, xa(12 downto 0),
di((i+1)*1-1 downto i*1), do((i+1)*1-1 downto i*1));
end generate;
end generate;
-- pragma translate_off
unsup : if (abits > 13) generate
x : process
begin
assert false
report "Lattice EC syncram mapper: unsupported memory configuration!"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity ec_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of ec_syncram_dp is
component EC_RAMB8_S1_S1 is port (
DataInA, DataInB: in std_logic_vector(0 downto 0);
AddressA, AddressB: in std_logic_vector(12 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(0 downto 0));
end component;
component EC_RAMB8_S2_S2 is port (
DataInA, DataInB: in std_logic_vector(1 downto 0);
AddressA, AddressB: in std_logic_vector(11 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(1 downto 0));
end component;
component EC_RAMB8_S4_S4 is port (
DataInA, DataInB: in std_logic_vector(3 downto 0);
AddressA, AddressB: in std_logic_vector(10 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(3 downto 0));
end component;
component EC_RAMB8_S9_S9 is port (
DataInA, DataInB: in std_logic_vector(8 downto 0);
AddressA, AddressB: in std_logic_vector(9 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(8 downto 0));
end component;
component EC_RAMB8_S18_S18 is port (
DataInA, DataInB: in std_logic_vector(17 downto 0);
AddressA, AddressB: in std_logic_vector(8 downto 0);
ClockA, ClockB: in std_logic;
ClockEnA, ClockEnB: in std_logic;
WrA, WrB: in std_logic;
QA, QB: out std_logic_vector(17 downto 0));
end component;
constant DMAX : integer := dbits+18;
constant AMAX : integer := 13;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(DMAX downto 0);
signal addr1, addr2 : std_logic_vector(AMAX downto 0);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(DMAX downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(DMAX downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(AMAX downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(AMAX downto abits) <= (others => '0');
a9 : if abits <= 9 generate
x : for i in 0 to ((dbits-1)/18) generate
r0 : EC_RAMB8_S18_S18 port map (
di1((i+1)*18-1 downto i*18), di2((i+1)*18-1 downto i*18),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*18-1 downto i*18), do2((i+1)*18-1 downto i*18));
end generate;
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/9) generate
r0 : EC_RAMB8_S9_S9 port map (
di1((i+1)*9-1 downto i*9), di2((i+1)*9-1 downto i*9),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*9-1 downto i*9), do2((i+1)*9-1 downto i*9));
end generate;
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : EC_RAMB8_S4_S4 port map (
di1((i+1)*4-1 downto i*4), di2((i+1)*4-1 downto i*4),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*4-1 downto i*4), do2((i+1)*4-1 downto i*4));
end generate;
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : EC_RAMB8_S2_S2 port map (
di1((i+1)*2-1 downto i*2), di2((i+1)*2-1 downto i*2),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*2-1 downto i*2), do2((i+1)*2-1 downto i*2));
end generate;
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : EC_RAMB8_S1_S1 port map (
di1((i+1)*1-1 downto i*1), di2((i+1)*1-1 downto i*1),
addr1(12 downto 0), addr2(12 downto 0), clk1, clk2,
enable1, enable2, write1, write2,
do1((i+1)*1-1 downto i*1), do2((i+1)*1-1 downto i*1));
end generate;
end generate;
-- pragma translate_off
unsup : if (abits > 13) generate
x : process
begin
assert false
report "Lattice EC syncram_dp: unsupported memory configuration!"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
|
gpl-2.0
|
7097c814c64eaaa8feed1911d268029a
| 0.666238 | 4.282511 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/spi/spictrlx.vhd
| 1 | 73,541 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spictrlx
-- File: spictrlx.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Auto mode: J. Andersson, J. Ekergarn - Aeroflex Gaisler AB
-- Contact: [email protected]
--
-- Description: SPI controller with an interface compatible with MPC83xx SPI.
-- Relies on APB's wait state between back-to-back transfers.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.spi.all;
entity spictrlx is
generic (
rev : integer := 0; -- Core revision
fdepth : integer range 1 to 7 := 1; -- FIFO depth is 2^fdepth
slvselen : integer range 0 to 1 := 0; -- Slave select register enable
slvselsz : integer range 1 to 32 := 1; -- Number of slave select signals
oepol : integer range 0 to 1 := 0; -- Output enable polarity
odmode : integer range 0 to 1 := 0; -- Support open drain mode, only
-- set if pads are i/o or od pads.
automode : integer range 0 to 1 := 0; -- Enable automated transfer mode
acntbits : integer range 1 to 32 := 32; -- # Bits in am period counter
aslvsel : integer range 0 to 1 := 0; -- Automatic slave select
twen : integer range 0 to 1 := 1; -- Enable three wire mode
maxwlen : integer range 0 to 15 := 0; -- Maximum word length;
syncram : integer range 0 to 1 := 1; -- Use SYNCRAM for buffers
memtech : integer range 0 to NTECH := 0; -- Memory technology
ft : integer range 0 to 2 := 0; -- Fault-Tolerance
scantest : integer range 0 to 1 := 0; -- Scan test support
syncrst : integer range 0 to 1 := 0; -- Use only sync reset
automask0 : integer := 0; -- Mask 0 for automated transfers
automask1 : integer := 0; -- Mask 1 for automated transfers
automask2 : integer := 0; -- Mask 2 for automated transfers
automask3 : integer := 0; -- Mask 3 for automated transfers
ignore : integer range 0 to 1 := 0 -- Ignore samples
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spii_ignore : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0)
);
attribute sync_set_reset of rstn : signal is "true";
end entity spictrlx;
architecture rtl of spictrlx is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant OEPOL_LEVEL : std_ulogic := conv_std_logic(oepol = 1);
constant OUTPUT : std_ulogic := OEPOL_LEVEL; -- Enable outputs
constant INPUT : std_ulogic := not OEPOL_LEVEL; -- Tri-state outputs
constant FIFO_DEPTH : integer := 2**fdepth;
constant SLVSEL_EN : integer := slvselen;
constant SLVSEL_SZ : integer := slvselsz;
constant ASEL_EN : integer := aslvsel * slvselen;
constant AM_EN : integer := automode;
constant AM_CNT_BITS : integer := acntbits;
constant OD_EN : integer := odmode;
constant TW_EN : integer := twen;
constant MAX_WLEN : integer := maxwlen;
constant AM_MSK1_EN : boolean := AM_EN = 1 and FIFO_DEPTH > 32;
constant AM_MSK2_EN : boolean := AM_EN = 1 and FIFO_DEPTH > 64;
constant AM_MSK3_EN : boolean := AM_EN = 1 and FIFO_DEPTH > 96;
constant FIFO_BITS : integer := fdepth;
constant APBBITS : integer := 6+3*AM_EN;
constant APBH : integer := 2+APBBITS-1;
constant CAP_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(0, APBBITS);
constant MODE_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(8, APBBITS);
constant EVENT_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(9, APBBITS);
constant MASK_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(10, APBBITS);
constant COM_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(11, APBBITS);
constant TD_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(12, APBBITS);
constant RD_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(13, APBBITS);
constant SLVSEL_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(14, APBBITS);
constant ASEL_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(15, APBBITS);
constant AMCFG_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(16, APBBITS);
constant AMPER_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(17, APBBITS);
constant AMMSK0_ADDR : std_logic_vector(10 downto 2) := "000010100"; -- 0x050
constant AMMSK1_ADDR : std_logic_vector(10 downto 2) := "000010101"; -- 0x054
constant AMMSK2_ADDR : std_logic_vector(10 downto 2) := "000010110"; -- 0x058
constant AMMSK3_ADDR : std_logic_vector(10 downto 2) := "000010111"; -- 0x05C
constant AMTX_ADDR : std_logic_vector(10 downto 2) := "010000000"; -- 0x200
constant AMRX_ADDR : std_logic_vector(10 downto 2) := "100000000"; -- 0x40
constant SPICTRLCAPREG : std_logic_vector(31 downto 0) :=
conv_std_logic_vector(SLVSEL_SZ, 8) & conv_std_logic_vector(MAX_WLEN, 4) &
conv_std_logic_vector(TW_EN, 1) & conv_std_logic_vector(AM_EN, 1) &
conv_std_logic_vector(ASEL_EN, 1) & conv_std_logic_vector(SLVSEL_EN, 1) &
conv_std_logic_vector(FIFO_DEPTH, 8) & conv_std_logic(syncram = 1) &
conv_std_logic_vector(ft, 2) & conv_std_logic_vector(rev, 5);
-- Returns an integer containing the maximum characted length - 1 as
-- restricted by the maxwlen VHDL generic.
function wlen return integer is
begin -- maxwlen
if MAX_WLEN = 0 then return 31; end if;
return MAX_WLEN;
end wlen;
constant PROG_AM_MASK : boolean :=
AM_EN = 1 and automask0 = 0 and (automask1 = 0 or FIFO_DEPTH <= 32) and
(automask2 = 0 or FIFO_DEPTH <= 64) and (automask3 = 0 or FIFO_DEPTH <= 96);
constant AM_MASK : std_logic_vector(127 downto 0) :=
conv_std_logic_vector_signed(automask3,32) &
conv_std_logic_vector_signed(automask2,32) &
conv_std_logic_vector_signed(automask1,32) &
conv_std_logic_vector_signed(automask0,32);
function check_discont_am_mask return boolean is
variable foundzero : boolean;
begin
if AM_EN = 0 then
return false;
elsif PROG_AM_MASK then
return true;
else
foundzero := false;
for i in 0 to FIFO_DEPTH-1 loop
if AM_MASK(i) = '0' then
foundzero := true;
else
if foundzero then
return true;
end if;
end if;
end loop;
return false;
end if;
end function;
constant DISCONT_AM_MASK : boolean := check_discont_am_mask;
function check_am_mask_end return integer is
variable ret : integer;
begin
ret := 0;
for i in 0 to FIFO_DEPTH-1 loop
if AM_MASK(i) = '1' then
ret := i;
end if;
end loop;
return ret;
end function;
constant AM_MASK_END : integer := check_am_mask_end;
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type spi_mode_rec is record -- SPI Mode register
amen : std_ulogic;
loopb : std_ulogic; -- loopback mode
cpol : std_ulogic; -- clock polarity
cpha : std_ulogic; -- clock phase
div16 : std_ulogic; -- Divide by 16
rev : std_ulogic; -- Reverse data mode
ms : std_ulogic; -- Master/slave
en : std_ulogic; -- Enable SPI
len : std_logic_vector(3 downto 0); -- Bits per character
pm : std_logic_vector(3 downto 0); -- Prescale modulus
tw : std_ulogic; -- 3-wire mode
asel : std_ulogic; -- Automatic slave select
fact : std_ulogic; -- PM multiplication factor
od : std_ulogic; -- Open drain mode
cg : std_logic_vector(4 downto 0); -- Clock gap
aseldel : std_logic_vector(1 downto 0); -- Asel delay
tac : std_ulogic;
tto : std_ulogic; -- Three-wire mode word order
igsel : std_ulogic; -- Ignore spisel input
cite : std_ulogic; -- Require SCK = CPOL for TIP end
end record;
type spi_em_rec is record -- SPI Event and Mask registers
tip : std_ulogic; -- Transfer in progress/Clock generated
lt : std_ulogic; -- last character transmitted
ov : std_ulogic; -- slave/master overrun
un : std_ulogic; -- slave/master underrun
mme : std_ulogic; -- Multiple-master error
ne : std_ulogic; -- Not empty
nf : std_ulogic; -- Not full
at : std_ulogic; -- Automated transfer
end record;
type spi_fifo is array (0 to (1-syncram)*(FIFO_DEPTH-1)) of std_logic_vector(wlen downto 0);
type spi_amcfg_rec is record -- AM config register
seq : std_ulogic; -- Data must always be read out of receive queue
strict : std_ulogic; -- Strict period
ovtb : std_ulogic; -- Perform transfer on OV
ovdb : std_ulogic; -- Skip data on OV
act : std_ulogic; -- Start immediately
eact : std_ulogic; -- Activate on external event
erpt : std_ulogic; -- Repeat on external event, not on period done
lock : std_ulogic; -- Lock receive registers when reading data
ecgc : std_ulogic; -- External clock gap control
end record;
type spi_am_rec is record -- Automode state
-- Register interface
cfg : spi_amcfg_rec; -- AM config register
per : std_logic_vector((AM_CNT_BITS-1)*AM_EN downto 0); -- AM period
--
active : std_ulogic; -- Auto mode active
lock : std_ulogic;
cnt : unsigned((AM_CNT_BITS-1)*AM_EN downto 0);
--
skipdata : std_ulogic;
rxfull : std_ulogic; -- AM RX FIFO is filled
rxfifo : spi_fifo; -- Receive data FIFO
txfifo : spi_fifo; -- Transmit data FIFO
rfreecnt : integer range 0 to FIFO_DEPTH; -- free rx fifo slots
mask : std_logic_vector(FIFO_DEPTH-1 downto 0);
mask_shdw : std_logic_vector(FIFO_DEPTH-1 downto 0);
unread : std_logic_vector(FIFO_DEPTH-1 downto 0);
at : std_ulogic;
--
rxread : std_ulogic;
txwrite : std_ulogic;
txread : std_ulogic;
apbaddr : std_logic_vector(FIFO_BITS-1 downto 0);
rxsel : std_ulogic;
end record;
-- Two stage synchronizers on each input coming from off-chip
type spi_in_local_type is record
miso : std_ulogic;
mosi : std_ulogic;
sck : std_ulogic;
spisel : std_ulogic;
end record;
type spi_in_array is array (1 downto 0) of spi_in_local_type;
-- Local spi out type without ssn
type spi_out_local_type is record
miso : std_ulogic;
misooen : std_ulogic;
mosi : std_ulogic;
mosioen : std_ulogic;
sck : std_ulogic;
sckoen : std_ulogic;
enable : std_ulogic;
astart : std_ulogic;
aready : std_ulogic;
end record;
-- Yet another subset of out type to make it easier for certain tools to
-- place registers near pads.
type spi_out_local_lb_type is record
mosi : std_ulogic;
sck : std_ulogic;
end record;
type spi_reg_type is record
-- SPI registers
mode : spi_mode_rec; -- Mode register
event : spi_em_rec; -- Event register
mask : spi_em_rec; -- Mask register
lst : std_ulogic; -- Only field on command register
td : std_logic_vector(31 downto 0); -- Transmit register
rd : std_logic_vector(31 downto 0); -- Receive register
slvsel : std_logic_vector((SLVSEL_SZ-1) downto 0); -- Slave select register
aslvsel : std_logic_vector((SLVSEL_SZ-1) downto 0); -- Automatic slave select
--
uf : std_ulogic; -- Slave in underflow condition
ov : std_ulogic; -- Receive overflow condition
td_occ : std_ulogic; -- Transmit register occupied
rd_free : std_ulogic; -- Receive register free (empty)
txfifo : spi_fifo; -- Transmit data FIFO
rxfifo : spi_fifo; -- Receive data FIFO
rxd : std_logic_vector(wlen downto 0); -- Receive shift register
txd : std_logic_vector(wlen downto 0); -- Transmit shift register
txdupd : std_ulogic; -- Update txd
txdbyp : std_ulogic; -- txd update bypass
toggle : std_ulogic; -- SCK has toggled
samp : std_ulogic; -- Sample
chng : std_ulogic; -- Change
psck : std_ulogic; -- Previous value of SC
twdir : std_ulogic; -- Direction in 3-wire mode
syncsamp : std_logic_vector(1 downto 0); -- Sample synchronized input
incrdli : std_ulogic;
rxdone : std_ulogic;
rxdone2 : std_ulogic;
running : std_ulogic;
ov2 : std_ulogic;
-- counters
tfreecnt : integer range 0 to FIFO_DEPTH; -- free td fifo slots
rfreecnt : integer range 0 to FIFO_DEPTH; -- free td fifo slots
tdfi : std_logic_vector(fdepth-1 downto 0); -- First tx queue element
rdfi : std_logic_vector(fdepth-1 downto 0); -- First rx queue element
tdli : std_logic_vector(fdepth-1 downto 0); -- Last tx queue element
rdli : std_logic_vector(fdepth-1 downto 0); -- Last rx queue element
rbitcnt : std_logic_vector(log2(wlen+1)-1 downto 0); -- Current receive bit
tbitcnt : std_logic_vector(log2(wlen+1)-1 downto 0); -- Current transmit bit
divcnt : unsigned(9 downto 0); -- Clock scaler
cgcnt : unsigned(5 downto 0); -- Clock gap counter
cgcntblock: std_ulogic;
aselcnt : unsigned(1 downto 0); -- ASEL delay
cgasel : std_ulogic; -- ASEL when entering CG
--
irq : std_ulogic;
--
-- Automode
am : spi_am_rec;
-- Sync registers for inputs
spii : spi_in_array;
-- Output
spio : spi_out_local_type;
spiolb : spi_out_local_lb_type;
--
astart : std_ulogic;
cstart : std_ulogic;
txdupd2 : std_ulogic;
twdir2 : std_ulogic;
end record;
-----------------------------------------------------------------------------
-- Sub programs
-----------------------------------------------------------------------------
-- Returns a vector containing the character length - 1 in bits as selected
-- by the Mode field LEN.
function spilen (
len : std_logic_vector(3 downto 0))
return std_logic_vector is
begin -- spilen
if len = zero32(3 downto 0) then
return "11111";
else
return "0" & len;
end if;
end spilen;
-- Write clear
procedure wc (
reg_o : out std_ulogic;
reg_i : in std_ulogic;
b : in std_ulogic) is
begin
reg_o := reg_i and not b;
end procedure wc;
-- Reverses string. After this function has been called the first bit
-- to send is always at position 0.
function reverse(
data : std_logic_vector)
return std_logic_vector is
variable rdata: std_logic_vector(data'reverse_range);
begin
for i in data'range loop
rdata(i) := data(i);
end loop;
return rdata;
end function reverse;
-- Performs a HWORD swap if len /= 0
function condhwordswap (
data : std_logic_vector(31 downto 0);
len : std_logic_vector(4 downto 0))
return std_logic_vector is
variable rdata : std_logic_vector(31 downto 0);
begin -- condhwordswap
if len = one32(4 downto 0) then
rdata := data;
else
rdata := data(15 downto 0) & data(31 downto 16);
end if;
return rdata;
end condhwordswap;
-- Zeroes out unused part of receive vector.
function select_data (
data : std_logic_vector(wlen downto 0);
len : std_logic_vector(4 downto 0))
return std_logic_vector is
variable rdata : std_logic_vector(31 downto 0) := (others => '0');
variable length : integer range 0 to 31 := conv_integer(len);
variable sdata : std_logic_vector(31 downto 0) := (others => '0');
begin -- select_data
-- Quartus can not handle variable ranges
-- rdata(conv_integer(len) downto 0) := data(conv_integer(len) downto 0);
sdata := (others => '0'); sdata(wlen downto 0) := data;
case length is
when 15 => rdata(15 downto 0) := sdata(15 downto 0);
when 14 => rdata(14 downto 0) := sdata(14 downto 0);
when 13 => rdata(13 downto 0) := sdata(13 downto 0);
when 12 => rdata(12 downto 0) := sdata(12 downto 0);
when 11 => rdata(11 downto 0) := sdata(11 downto 0);
when 10 => rdata(10 downto 0) := sdata(10 downto 0);
when 9 => rdata(9 downto 0) := sdata(9 downto 0);
when 8 => rdata(8 downto 0) := sdata(8 downto 0);
when 7 => rdata(7 downto 0) := sdata(7 downto 0);
when 6 => rdata(6 downto 0) := sdata(6 downto 0);
when 5 => rdata(5 downto 0) := sdata(5 downto 0);
when 4 => rdata(4 downto 0) := sdata(4 downto 0);
when 3 => rdata(3 downto 0) := sdata(3 downto 0);
when others => rdata := sdata;
end case;
return rdata;
end select_data;
-- purpose: Returns true when a slave is selected and the clock starts
function slv_start (
spisel : std_ulogic;
cpol : std_ulogic;
sck : std_ulogic;
fsck_chg : std_ulogic)
return boolean is
begin -- slv_start
if spisel = '0' then -- Slave is selected
if fsck_chg = '1' then -- The clock has changed
return (cpol xor sck) = '1'; -- The clock is not idle
end if;
end if;
return false;
end slv_start;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
function spictrl_resval return spi_reg_type is
variable v : spi_reg_type;
begin
v.mode := ('0','0','0','0','0','0','0','0',"0000","0000",
'0','0','0','0',"00000","00", '0', '0', '0', '0');
v.event := ('0', '0', '0', '0', '0', '0', '0', '0');
v.mask := ('0', '0', '0', '0', '0', '0', '0', '0');
v.lst := '0';
v.td := (others => '0');
v.rd := (others => '0');
v.slvsel := (others => '1');
v.aslvsel := (others => '0');
v.uf := '0';
v.ov := '0';
v.td_occ := '0';
v.rd_free := '1';
for i in 0 to (1-syncram)*(FIFO_DEPTH-1) loop
v.txfifo(i) := (others => '0');
v.rxfifo(i) := (others => '0');
end loop;
v.rxd := (others => '0');
v.txd := (others => '0'); v.txd(0) := '1';
v.txdupd := '0';
v.txdbyp := '0';
v.toggle := '0';
v.samp := '1';
v.chng := '0';
v.psck := '0';
v.twdir := INPUT;
v.syncsamp := (others => '0');
v.incrdli := '0';
v.rxdone := '0';
v.rxdone2 := '0';
v.running := '0';
v.ov2 := '0';
v.tfreecnt := FIFO_DEPTH;
v.rfreecnt := FIFO_DEPTH;
v.tdfi := (others => '0');
v.rdfi := (others => '0');
v.tdli := (others => '0');
v.rdli := (others => '0');
v.rbitcnt := (others => '0');
v.tbitcnt := (others => '0');
v.divcnt := (others => '0');
v.cgcnt := (others => '0');
v.cgcntblock := '0';
v.aselcnt := (others => '0');
v.cgasel := '0';
v.irq := '0';
v.am.cfg := ('0', '0', '0', '0', '0', '0', '0', '0', '0');
v.am.per := (others => '0');
v.am.active := '0';
v.am.lock := '0';
v.am.cnt := (others => '0');
v.am.skipdata := '0';
v.am.rxfull := '0';
for i in 0 to (1-syncram)*(FIFO_DEPTH-1) loop
v.am.rxfifo := (others => (others => '0'));
v.am.txfifo := (others => (others => '0'));
end loop;
v.am.rfreecnt := 0;
v.am.mask := (others => '0');
v.am.mask_shdw := (others => '1');
v.am.unread := (others => '0');
v.am.at := '0';
v.am.rxread := '0';
v.am.txwrite := '0';
v.am.txread := '0';
v.am.apbaddr := (others => '0');
v.am.rxsel := '0';
for i in 1 downto 0 loop
v.spii(i).miso := '1';
v.spii(i).mosi := '1';
v.spii(i).sck := '0';
v.spii(i).spisel := '1';
end loop;
v.spio.miso := '1';
v.spio.misooen := INPUT;
v.spio.mosi := '1';
v.spio.mosioen := INPUT;
v.spio.sck := '0';
v.spio.sckoen := INPUT;
v.spio.enable := '0';
v.spio.astart := '0';
v.spio.aready := '0';
v.spiolb.mosi := '1';
v.spiolb.sck := '1';
v.astart := '0';
v.cstart := '0';
v.txdupd2 := '0';
v.twdir2 := '0';
return v;
end spictrl_resval;
constant RES : spi_reg_type := spictrl_resval;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal r, rin : spi_reg_type;
type fifo_data_vector_array is array (automode downto 0) of std_logic_vector(wlen downto 0);
type fifo_addr_vector_array is array (automode downto 0) of std_logic_vector(fdepth-1 downto 0);
signal rx_di, rx_do, tx_di, tx_do : fifo_data_vector_array;
signal rx_ra, rx_wa, tx_ra, tx_wa : fifo_addr_vector_array;
signal rx_read, tx_read, rx_write, tx_write : std_logic_vector(automode downto 0);
signal arstn : std_ulogic;
begin
arstn <= apbi_testrst when (scantest = 1) and (apbi_testen = '1') else rstn;
-- SPI controller, register interface and related logic
comb: process (r, rstn, apbi_psel, apbi_penable, apbi_paddr, apbi_pwrite,
apbi_pwdata, apbi_testen, apbi_testrst, apbi_scanen,
apbi_testoen, spii_miso, spii_mosi, spii_sck, spii_spisel,
spii_astart, rx_do, tx_do, spii_cstart, spii_ignore)
variable v : spi_reg_type;
variable apbaddr : std_logic_vector(APBH downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable len : std_logic_vector(4 downto 0);
variable indata : std_ulogic;
variable change : std_ulogic;
variable update : std_ulogic;
variable sample : std_ulogic;
variable reload : std_ulogic;
variable cgasel : std_ulogic;
variable txshift : std_ulogic;
-- automode
variable rstop1 : std_ulogic;
variable rstop2 : std_ulogic;
variable rstop3 : std_ulogic;
variable tstop1 : std_ulogic;
variable tstop2 : std_ulogic;
variable tstop3 : std_ulogic;
variable astart : std_ulogic;
-- fifos
variable rx_rd : std_ulogic;
variable tx_rd : std_ulogic;
variable rx_wr : std_ulogic;
variable tx_wr : std_ulogic;
--
variable fsck : std_ulogic;
variable fsck_chg : std_ulogic;
--
variable spisel : std_ulogic;
--
variable rntxd : std_logic_vector(0 to 31);
variable ntxd : std_logic_vector(wlen downto 0);
variable amask : std_logic_vector(FIFO_DEPTH-1 downto 0);
variable aloop : integer;
begin -- process comb
v := r; v.irq := '0';
apbaddr := apbi_paddr(APBH downto 2); apbout := (others => '0');
len := spilen(r.mode.len); v.toggle := '0'; v.txdupd := '0';
v.syncsamp := r.syncsamp(0) & '0'; update := '0'; v.rxdone := '0';
indata := '0'; sample := '0'; change := '0'; reload := '0';
v.spio.astart := '0'; cgasel := '0'; v.ov2 := r.ov; txshift := '0';
fsck := '0'; fsck_chg := '0'; v.txdbyp := '0';
spisel := r.spii(1).spisel or r.mode.igsel;
ntxd := r.td(wlen downto 0); rntxd := reverse(r.td);
if r.mode.rev = '1' then ntxd := rntxd(31-wlen to 31); end if;
v.spio.aready := '0';
if AM_EN = 1 then
v.txdupd2 := '0';
v.cstart := '0';
if TW_EN = 1 then
v.twdir2 := r.twdir;
end if;
end if;
if PROG_AM_MASK then
amask := r.am.mask;
aloop := FIFO_DEPTH-1;
else
amask := AM_MASK(FIFO_DEPTH-1 downto 0);
aloop := AM_MASK_END;
end if;
rx_rd := '0'; tx_rd := '0'; rx_wr := '0'; tx_wr := '0';
rstop1 := '0'; rstop2 := '0'; rstop3 := '0';
tstop1 := '0'; tstop2 := '0'; tstop3 := '0';
astart := '0'; v.am.txwrite := '0'; v.am.txwrite := '0'; v.am.rxread := '0';
if AM_EN = 1 then
v.am.at := r.event.at;
v.astart := spii_astart;
if r.event.at = '0' then
astart := spii_astart and (not r.astart);
if PROG_AM_MASK then
v.am.mask := r.am.mask_shdw;
end if;
end if;
if spii_cstart = '1' then v.cstart := '1'; end if;
end if;
if (apbi_psel and apbi_penable and (not apbi_pwrite)) = '1' then
if apbaddr = CAP_ADDR then
apbout := SPICTRLCAPREG;
elsif apbaddr = MODE_ADDR then
apbout := r.mode.amen & r.mode.loopb & r.mode.cpol & r.mode.cpha &
r.mode.div16 & r.mode.rev & r.mode.ms & r.mode.en &
r.mode.len & r.mode.pm & r.mode.tw & r.mode.asel &
r.mode.fact & r.mode.od & r.mode.cg & r.mode.aseldel &
r.mode.tac & r.mode.tto & r.mode.igsel & r.mode.cite &
zero32(0);
elsif apbaddr = EVENT_ADDR then
apbout := r.event.tip & zero32(30 downto 16) & r.event.at &
r.event.lt & zero32(13) & r.event.ov & r.event.un &
r.event.mme & r.event.ne & r.event.nf & zero32(7 downto 0);
elsif apbaddr = MASK_ADDR then
apbout := r.mask.tip & zero32(30 downto 16) & r.mask.at &
r.mask.lt & zero32(13) & r.mask.ov & r.mask.un &
r.mask.mme & r.mask.ne & r.mask.nf & zero32(7 downto 0);
elsif apbaddr = RD_ADDR then
apbout := condhwordswap(r.rd, len);
if AM_EN = 0 or r.mode.amen = '0' then
v.rd_free := '1';
end if;
elsif apbaddr = SLVSEL_ADDR then
if SLVSEL_EN /= 0 then apbout((SLVSEL_SZ-1) downto 0) := r.slvsel;
else null; end if;
elsif apbaddr = ASEL_ADDR then
if ASEL_EN /= 0 then
apbout((SLVSEL_SZ-1) downto 0) := r.aslvsel;
else null; end if;
end if;
end if;
-- write registers
if (apbi_psel and apbi_penable and apbi_pwrite) = '1' then
if apbaddr = MODE_ADDR then
if AM_EN = 1 then v.mode.amen := apbi_pwdata(31); end if;
v.mode.loopb := apbi_pwdata(30);
v.mode.cpol := apbi_pwdata(29);
v.mode.cpha := apbi_pwdata(28);
v.mode.div16 := apbi_pwdata(27);
v.mode.rev := apbi_pwdata(26);
v.mode.ms := apbi_pwdata(25);
v.mode.en := apbi_pwdata(24);
v.mode.len := apbi_pwdata(23 downto 20);
v.mode.pm := apbi_pwdata(19 downto 16);
if TW_EN = 1 then v.mode.tw := apbi_pwdata(15); end if;
if ASEL_EN = 1 then v.mode.asel := apbi_pwdata(14); end if;
v.mode.fact := apbi_pwdata(13);
if OD_EN = 1 then v.mode.od := apbi_pwdata(12); end if;
v.mode.cg := apbi_pwdata(11 downto 7);
if ASEL_EN = 1 then
v.mode.aseldel := apbi_pwdata(6 downto 5);
v.mode.tac := apbi_pwdata(4);
end if;
if TW_EN = 1 then v.mode.tto := apbi_pwdata(3); end if;
v.mode.igsel := apbi_pwdata(2);
v.mode.cite := apbi_pwdata(1);
elsif apbaddr = EVENT_ADDR then
wc(v.event.lt, r.event.lt, apbi_pwdata(14));
wc(v.event.ov, r.event.ov, apbi_pwdata(12));
wc(v.event.un, r.event.un, apbi_pwdata(11));
wc(v.event.mme, r.event.mme, apbi_pwdata(10));
elsif apbaddr = MASK_ADDR then
v.mask.tip := apbi_pwdata(31);
if AM_EN = 1 then
v.mask.at := apbi_pwdata(15);
end if;
v.mask.lt := apbi_pwdata(14);
v.mask.ov := apbi_pwdata(12);
v.mask.un := apbi_pwdata(11);
v.mask.mme := apbi_pwdata(10);
v.mask.ne := apbi_pwdata(9);
v.mask.nf := apbi_pwdata(8);
elsif apbaddr = COM_ADDR then
v.lst := apbi_pwdata(22);
elsif apbaddr = TD_ADDR then
-- The write is lost if the transmit register is written when
-- the not full bit is zero.
if r.event.nf = '1' then
v.td := apbi_pwdata;
if AM_EN = 0 or r.mode.amen = '0' then
v.td_occ := '1';
end if;
end if;
elsif apbaddr = SLVSEL_ADDR then
if SLVSEL_EN /= 0 then v.slvsel := apbi_pwdata((SLVSEL_SZ-1) downto 0);
else null; end if;
elsif apbaddr = ASEL_ADDR then
if ASEL_EN /= 0 then
v.aslvsel := apbi_pwdata((SLVSEL_SZ-1) downto 0);
else null; end if;
end if;
end if;
-- Automode register interface
if AM_EN /= 0 then
if apbi_psel = '1' then
v.am.apbaddr := apbaddr(FIFO_BITS+1 downto 2);
if syncram /= 0 then
-- Check if tx queue will be read
if apbaddr(10 downto 9) = AMTX_ADDR(10 downto 9) then
v.am.txread := apbi_pwrite and not r.am.txread;
end if;
if apbaddr(10 downto 9) = AMRX_ADDR(10 downto 9) then
v.am.rxread := not r.am.rxread;
end if;
end if;
end if;
if (apbi_psel and apbi_penable) = '1' then
if apbaddr = AMCFG_ADDR then
apbout := zero32(31 downto 9) & r.am.cfg.ecgc & r.am.cfg.lock &
r.am.cfg.erpt & r.am.cfg.seq & r.am.cfg.strict &
r.am.cfg.ovtb & r.am.cfg.ovdb & r.am.active &
r.am.cfg.eact;
if apbi_pwrite = '1' then
v.am.cfg.ecgc := apbi_pwdata(8);
v.am.cfg.lock := apbi_pwdata(7);
v.am.cfg.erpt := apbi_pwdata(6);
v.am.cfg.seq := apbi_pwdata(5);
v.am.cfg.strict := apbi_pwdata(4);
v.am.cfg.ovtb := apbi_pwdata(3);
v.am.cfg.ovdb := apbi_pwdata(2);
v.am.cfg.act := apbi_pwdata(1);
v.spio.astart := apbi_pwdata(1);
v.am.cfg.eact := apbi_pwdata(0);
end if;
elsif apbaddr = AMPER_ADDR then
apbout((AM_CNT_BITS-1)*AM_EN downto 0) := r.am.per;
if apbi_pwrite = '1' then
v.am.per := apbi_pwdata((AM_CNT_BITS-1)*AM_EN downto 0);
end if;
elsif apbaddr = AMMSK0_ADDR then
if FIFO_DEPTH > 32 then
apbout := amask(31 downto 0);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(31 downto 0) := apbi_pwdata;
end if;
end if;
else
apbout(FIFO_DEPTH-1 downto 0) := amask(FIFO_DEPTH-1 downto 0);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 0) := apbi_pwdata(FIFO_DEPTH-1 downto 0);
end if;
end if;
end if;
elsif apbaddr = AMMSK1_ADDR then
if AM_MSK1_EN then
if FIFO_DEPTH > 64 then
apbout := amask(63 downto 32);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(63 downto 32) := apbi_pwdata;
end if;
end if;
else
apbout(FIFO_DEPTH-33 downto 0) := amask(FIFO_DEPTH-1 downto 32);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 32) := apbi_pwdata(FIFO_DEPTH-33 downto 0);
end if;
end if;
end if;
else
null;
end if;
elsif apbaddr = AMMSK2_ADDR then
if AM_MSK2_EN then
if FIFO_DEPTH > 96 then
apbout := amask(95 downto 64);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(95 downto 64) := apbi_pwdata;
end if;
end if;
else
apbout(FIFO_DEPTH-65 downto 0) := amask(FIFO_DEPTH-1 downto 64);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 64) := apbi_pwdata(FIFO_DEPTH-65 downto 0);
end if;
end if;
end if;
else
null;
end if;
elsif apbaddr = AMMSK3_ADDR then
if AM_MSK3_EN then
apbout(FIFO_DEPTH-97 downto 0) := amask(FIFO_DEPTH-1 downto 96);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 96) := apbi_pwdata(FIFO_DEPTH-97 downto 0);
end if;
end if;
else
null;
end if;
elsif apbaddr(10 downto 9) = AMTX_ADDR(10 downto 9) then
if conv_integer(apbaddr(8 downto 2)) < FIFO_DEPTH then
if syncram = 0 then
apbout(wlen downto 0) :=
r.am.txfifo(conv_integer(apbaddr(FIFO_BITS+1 downto 2)));
else
apbout(wlen downto 0) := tx_do(automode);
end if;
if apbi_pwrite = '1' then
v.am.txwrite := '1';
v.td := apbi_pwdata;
end if;
end if;
elsif apbaddr(10 downto 9) = AMRX_ADDR(10 downto 9) then
if conv_integer(apbaddr(8 downto 2)) < FIFO_DEPTH then
if syncram = 0 then
if r.mode.rev = '0' then
apbout := condhwordswap(reverse(select_data(r.rxfifo(conv_integer(r.am.apbaddr)), len)), len);
else
apbout := condhwordswap(select_data(r.rxfifo(conv_integer(r.am.apbaddr)), len), len);
end if;
else
if r.mode.rev = '0' then
apbout := condhwordswap(reverse(select_data(rx_do(conv_integer(not r.am.rxsel)), len)), len);
else
apbout := condhwordswap(select_data(rx_do(conv_integer(not r.am.rxsel)), len), len);
end if;
end if;
if r.am.unread(conv_integer(r.am.apbaddr)) = '1' then
v.rd_free := '1';
v.am.unread(conv_integer(r.am.apbaddr)) := '0';
v.am.lock := r.am.cfg.lock;
end if;
end if;
end if;
end if;
end if;
-- Handle transmit FIFO
if r.td_occ = '1' and r.tfreecnt /= 0 then
if syncram = 0 then
v.txfifo(conv_integer(r.tdli)) := ntxd;
else
tx_wr := '1';
end if;
v.tdli := r.tdli + 1;
v.tfreecnt := r.tfreecnt - 1;
v.td_occ := '0';
if r.tfreecnt = FIFO_DEPTH then
v.txdbyp := r.running and r.mode.ms and r.txdupd;
v.txdupd := not r.uf;
tx_rd := '1';
end if;
end if;
-- AM transmit FIFO handling when core is not implemented with SYNCRAM
if syncram = 0 and AM_EN /= 0 and r.am.txwrite = '1' then
if r.mode.rev = '0' then
v.am.txfifo(conv_integer(r.am.apbaddr)) := r.td(wlen downto 0);
else
v.am.txfifo(conv_integer(r.am.apbaddr)) := reverse(r.td)(31-wlen to 31);
end if;
end if;
-- Update receive register and FIFO
if r.rd_free = '1' and r.rfreecnt /= FIFO_DEPTH then
if syncram = 0 then
if r.mode.rev = '0' then
v.rd := reverse(select_data(r.rxfifo(conv_integer(r.rdfi)), len));
else
v.rd := select_data(r.rxfifo(conv_integer(r.rdfi)), len);
end if;
else
if r.mode.rev = '0' then
v.rd := reverse(select_data(rx_do(0), len));
else
v.rd := select_data(rx_do(0), len);
end if;
end if;
if not ((ignore > 0) and (spii_ignore = '1')) then
v.rdfi := r.rdfi + 1;
v.rfreecnt := r.rfreecnt + 1;
v.rd_free := '0';
end if;
end if;
if v.rd_free = '1' and r.rfreecnt /= FIFO_DEPTH then rx_rd := '1'; end if;
if r.mode.en = '1' then -- Core is enabled
-- Not full detection
if r.tfreecnt /= 0 or r.td_occ /= '1' then
v.event.nf := '1';
if (r.mask.nf and not r.event.nf) = '1' then
v.irq := '1';
end if;
else
v.event.nf := '0';
end if;
-- Not empty detection
if ((AM_EN = 0 or r.mode.amen = '0') and (r.rfreecnt /= FIFO_DEPTH or r.rd_free /= '1')) or
(AM_EN = 1 and r.mode.amen = '1' and r.am.unread /= zero128(FIFO_DEPTH-1 downto 0)) then
v.event.ne := '1';
if (r.mask.ne and not r.event.ne) = '1' then
v.irq := '1';
end if;
else
v.event.ne := '0';
if AM_EN = 1 then v.am.lock := '0'; end if;
end if;
end if;
---------------------------------------------------------------------------
-- Automated periodic transfer control
---------------------------------------------------------------------------
if AM_EN = 1 and r.mode.amen = '1' then
if r.am.active = '0' then
-- Activation either from register write or external event.
v.am.active := r.spio.astart or (astart and r.am.cfg.eact);
v.am.cfg.act := v.am.active;
v.am.rfreecnt := 0;
for i in 0 to aloop loop
if amask(i) = '1' then
v.am.rfreecnt := v.am.rfreecnt+1;
end if;
end loop;
v.am.skipdata := '0'; v.am.rxfull := '0';
v.am.cnt := unsigned(r.am.per);
v.event.at := v.am.active;
v.tdfi := (others => '0');
-- Check mask to see which word in the FIFO to start with.
for i in 0 to aloop loop
if amask(i) = '1' then
if tstop1 = '0' then
v.tdfi := conv_std_logic_vector(i, r.tdfi'length);
end if;
tstop1 := '1';
end if;
end loop;
if v.am.active = '1' then
v.txdupd2 := '1'; tx_rd := '1';
v.tfreecnt := FIFO_DEPTH;
for i in 0 to aloop loop
if amask(i) = '1' then
v.tfreecnt := v.tfreecnt-1;
end if;
end loop;
end if;
v.rdli := (others => '0');
for i in 0 to aloop loop
if rstop1 = '0' then
if amask(i) = '0' then
v.rdli := v.rdli + 1;
else
rstop1 := '1';
end if;
end if;
end loop;
v.cstart := v.am.active;
else
-- Receive fifo handling
if r.am.rxfull = '1' then -- AM RX fifo is filled
-- Move to receive queue if the queue is empty or if there is no
-- requirement on sequential transfers and the queue is not locked.
if (r.event.ne and (v.am.lock or r.am.cfg.seq)) = '0' then
-- Queue is empty
if syncram = 0 then
v.rxfifo := r.am.rxfifo;
else
v.am.rxsel := not r.am.rxsel;
end if;
v.rdfi := (others => '0');
v.rfreecnt := r.am.rfreecnt;
v.rd_free := '0';
v.am.rxfull := '0';
for i in 0 to aloop loop
if amask(i) = '1' then
v.am.unread(i) := '1';
end if;
end loop;
end if;
if r.event.tip = '0' and r.am.at = '1' then
v.event.at := '0';
end if;
if (r.mask.at and r.event.at) = '1' then
v.irq := '1';
end if;
end if;
if r.am.cfg.act = '0' then v.am.active := r.running; end if;
v.am.cfg.eact := '0';
if (r.am.cnt = 0 and r.am.cfg.erpt = '0') or (astart = '1' and r.am.cfg.erpt = '1') then
-- Only allowed to start new transfer if previous transfer(s) is finished
if r.event.tip = '0' then
if (not v.am.rxfull or r.am.cfg.strict) = '1' then
v.am.cnt := unsigned(r.am.per);
end if;
if (not v.am.rxfull or (r.am.cfg.strict and not r.am.cfg.ovtb)) = '1' then
-- Start transfer. Initialize indexes and fifo counter
v.txdupd2 := '1'; tx_rd := '1';
v.am.cnt := unsigned(r.am.per);
v.rdli := (others => '0');
for i in 0 to aloop loop
if rstop2 = '0' then
if amask(i) = '0' then
v.rdli := v.rdli + 1;
else
rstop2 := '1';
end if;
end if;
end loop;
v.tfreecnt := FIFO_DEPTH;
v.am.rfreecnt := 0;
for i in 0 to aloop loop
if amask(i) = '1' then
v.am.rfreecnt := v.am.rfreecnt+1;
v.tfreecnt := v.tfreecnt-1;
end if;
end loop;
v.tdfi := (others => '0');
-- Check mask to see which word in the FIFO to start with.
for i in 0 to aloop loop
if amask(i) = '1' then
if tstop2 = '0' then
v.tdfi := conv_std_logic_vector(i, r.tdfi'length);
end if;
tstop2 := '1';
end if;
end loop;
-- Skip incoming data if receive FIFO is full and OVDB is '1'.
v.am.skipdata := v.am.rxfull and r.am.cfg.ovdb;
if v.am.skipdata = '0' then
-- Clear AM receive fifo if we will overwrite it.
v.am.rfreecnt := FIFO_DEPTH;
for i in 0 to aloop loop
if amask(i) = '0' then
v.am.rfreecnt := v.am.rfreecnt-1;
end if;
end loop;
v.am.rxfull := '0';
end if;
v.event.at := '1';
v.cstart := astart and r.am.cfg.erpt;
end if;
end if;
else
v.am.cnt := r.am.cnt - 1;
end if;
end if;
end if;
---------------------------------------------------------------------------
-- SCK filtering, only used in slave mode
---------------------------------------------------------------------------
fsck := r.psck;
if (r.mode.en and not r.mode.ms) = '1' then
if (r.spii(1).sck xor r.psck) = '0' then
reload := '1';
else
-- Detected SCK change
if r.divcnt = 0 then
v.psck := r.spii(1).sck;
fsck := r.spii(1).sck;
fsck_chg := '1';
reload := '1';
else
v.divcnt := r.divcnt - 1;
end if;
end if;
elsif r.mode.en = '1' then
v.psck := r.spii(1).sck;
end if;
---------------------------------------------------------------------------
-- SPI bus control
---------------------------------------------------------------------------
if (r.mode.en and not r.running) = '1' and (r.mode.ms = '0' or r.divcnt = 0) then
if r.mode.ms = '1' then
if r.divcnt = 0 then
v.spio.sck := r.mode.cpol;
end if;
v.spio.misooen := INPUT;
if TW_EN = 0 or r.mode.tw = '0' then
if OD_EN = 0 or r.mode.od = '0' then
v.spio.mosioen := OUTPUT;
end if;
else
v.spio.mosioen := INPUT;
end if;
v.spio.sckoen := OUTPUT;
if TW_EN = 1 then v.twdir := OUTPUT xor r.mode.tto; end if;
else
if (spisel or r.mode.tw) = '0' then
v.spio.misooen := OUTPUT;
else
v.spio.misooen := INPUT;
end if;
if (not spisel and r.mode.tw and r.mode.tto) = '0' then
v.spio.mosioen := INPUT;
else
v.spio.mosioen := OUTPUT;
end if;
v.spio.sckoen := INPUT;
if TW_EN = 1 then v.twdir := INPUT xor r.mode.tto; end if;
end if;
if ((((AM_EN = 0 or r.mode.amen = '0') or
(AM_EN = 1 and r.mode.amen = '1' and r.am.active = '1')) and
r.mode.ms = '1' and r.tfreecnt /= FIFO_DEPTH and r.txdupd = '0' and (AM_EN = 0 or r.txdupd2 = '0')) or
slv_start(spisel, r.mode.cpol, fsck, fsck_chg)) then
-- Slave underrun detection
if r.tfreecnt = FIFO_DEPTH then
v.uf := '1';
if (r.mask.un and not v.event.un) = '1' then
v.irq := '1';
end if;
v.event.un := '1';
end if;
v.running := '1';
if r.mode.ms = '1' then
if TW_EN = 0 or r.mode.tw = '0' then
v.spio.mosioen := OUTPUT;
else
v.spio.mosioen := OUTPUT xor r.mode.tto;
end if;
change := not r.mode.cpha;
-- Insert cycles when cpha = '0' to ensure proper setup
-- time for first MOSI value in master mode.
reload := not r.mode.cpha;
end if;
end if;
v.cgcnt := (others => '0');
v.rbitcnt := (others => '0'); v.tbitcnt := (others => '0');
if r.mode.ms = '0' then
update := not (r.mode.cpha or (fsck xor r.mode.cpol));
if r.mode.cpha = '0' then
-- Prepare first bit
v.tbitcnt := (others => '0'); v.tbitcnt(0) := '1';
if v.running = '1' and (TW_EN = 0 or r.mode.tw = '0' or r.twdir = OUTPUT) then
txshift := '1';
end if;
end if;
end if;
-- samp and chng should not be changed on b2b
if spisel /= '0' then
v.samp := not r.mode.cpha;
v.chng := r.mode.cpha;
v.psck := r.mode.cpol;
end if;
end if;
if AM_EN = 0 or r.mode.amen = '0' or r.am.cfg.ecgc = '0' then
v.cgcntblock := '0';
else
if r.cstart = '1' then
v.cgcntblock := '0';
end if;
end if;
---------------------------------------------------------------------------
-- Clock generation, only in master mode
---------------------------------------------------------------------------
if r.mode.ms = '1' and (r.running = '1' or r.divcnt /= 0) then
-- The frequency of the SPI clock relative to the system clock is
-- determined by the fact, div16 and pm register fields.
--
-- With fact = 0 the fields have the same meaning as in the MPC83xx
-- register interface. The clock is divided by 4*([PM]+1) and if div16
-- is set the clock is divided by 16*(4*([PM]+1)).
--
-- With fact = 1 the core's register i/f is no longer compatible with
-- the MPC83xx register interface. The clock is divided by 2*([PM]+1) and
-- if div16 is set the clock is divided by 16*(2*([PM]+1)).
--
-- The generated clock's duty cycle is always 50%.
if r.divcnt = 0 then
if ASEL_EN = 0 or r.aselcnt = 0 then
-- Toggle SCK unless we are in a clock gap
if (r.cgcnt = 0 and (AM_EN = 0 or r.cgcntblock = '0')) or
r.spiolb.sck /= r.mode.cpol then
v.spio.sck := not r.spiolb.sck;
v.toggle := r.running;
end if;
if r.cgcnt /= 0 and (AM_EN = 0 or r.cgcntblock = '0') then
v.cgcnt := r.cgcnt - 1;
if ASEL_EN /= 0 and r.cgcnt = 1 then
cgasel := r.mode.tac;
end if;
end if;
elsif ASEL_EN = 1 then
v.aselcnt := r.aselcnt - 1;
end if;
reload := '1';
else
v.divcnt := r.divcnt - 1;
end if;
elsif r.mode.ms = '1' then
v.divcnt := (others => '0');
end if;
if reload = '1' then
-- Reload clock scale counter
v.divcnt(4 downto 0) := unsigned('0' & r.mode.pm) + 1;
if (not r.mode.fact and r.mode.ms) = '1' then
if r.mode.div16 = '1' then
v.divcnt := shift_left(v.divcnt, 5) - 1;
else
v.divcnt := shift_left(v.divcnt, 1) - 1;
end if;
else
if (r.mode.div16 and r.mode.ms) = '1' then
v.divcnt := shift_left(v.divcnt, 4) - 1;
else
v.divcnt(9 downto 4) := (others => '0');
v.divcnt(3 downto 0) := unsigned(r.mode.pm);
end if;
end if;
end if;
---------------------------------------------------------------------------
-- Handle master operation.
---------------------------------------------------------------------------
if r.mode.ms = '1' then
-- Sample data
if r.toggle = '1' then
v.samp := not r.samp;
sample := r.samp;
end if;
-- Change data on the clock flank...
if v.toggle = '1' then
v.chng := not r.chng;
change := r.chng;
end if;
-- Detect multiple-master errors (mode-fault)
if spisel = '0' then
v.mode.en := '0';
v.mode.ms := '0';
v.event.mme := '1';
if (r.mask.mme and not r.event.mme) = '1' then
v.irq := '1';
end if;
v.running := '0';
v.event.tip := '0';
if AM_EN = 1 then
v.event.at := '0';
end if;
end if;
-- Select input data
if r.mode.loopb = '1' then
indata := r.spiolb.mosi;
elsif TW_EN = 1 and r.mode.tw = '1' then
indata := r.spii(1).mosi;
else
indata := r.spii(1).miso;
end if;
end if;
---------------------------------------------------------------------------
-- Handle slave operation
---------------------------------------------------------------------------
if (r.mode.en and not r.mode.ms) = '1' then
if spisel = '0' then
if fsck_chg = '1' then
sample := r.samp; v.samp := not r.samp;
change := r.chng; v.chng := not r.chng;
end if;
indata := r.spii(1).mosi;
end if;
end if;
---------------------------------------------------------------------------
-- Used in both master and slave operation
---------------------------------------------------------------------------
if sample = '1' then
-- Detect receive overflow
if ((AM_EN = 0 or r.mode.amen = '0' ) and (r.rfreecnt = 0 and r.rd_free = '0')) or
(AM_EN = 1 and r.mode.amen = '1' and r.am.rfreecnt = 0) or
r.ov = '1' then
if TW_EN = 0 or r.mode.tw = '0' or r.twdir = INPUT then
-- Overflow event and IRQ
v.ov := '1';
if r.ov = '0' then
if (r.mask.ov and not r.event.ov) = '1' then
v.irq := '1';
end if;
v.event.ov := '1';
end if;
end if;
sample := '0'; -- Prevent sample below
else
sample := not r.mode.ms or r.mode.loopb;
v.syncsamp(0) := not sample;
end if;
if r.rbitcnt = len(log2(wlen+1)-1 downto 0) then
v.rbitcnt := (others => '0');
if TW_EN = 1 then
v.twdir := r.twdir xor not r.mode.loopb;
end if;
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or
(r.mode.tw = '1' and r.twdir = INPUT)) then
v.incrdli := not r.ov;
end if;
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or
(TW_EN = 1 and r.mode.tw = '1' and
(((r.mode.ms xor r.mode.tto) = '1' and r.twdir = INPUT) or
((r.mode.ms xor r.mode.tto) = '0' and r.twdir = OUTPUT)))) then
if r.mode.cpha = '0' then
v.cgcnt := unsigned(r.mode.cg & '0');
if ASEL_EN /= 0 then v.cgasel := r.mode.tac; end if;
if AM_EN = 1 and r.mode.amen = '1' and r.am.cfg.ecgc = '1' then
v.cgcntblock := '1';
end if;
end if;
v.ov := '0';
if r.tfreecnt = FIFO_DEPTH then
v.running := '0';
-- When running with with SCK freq. at half the system freq. we are
-- past the last edge here and SCK has transitioned from CPOL.
-- Force controller into idle state, only applies to master mode.
if (r.toggle and v.toggle) = '1' then
v.toggle := '0';
v.spio.sck := r.mode.cpol;
v.chng := r.chng;
end if;
end if;
v.uf := '0';
end if;
else
v.rbitcnt := r.rbitcnt + 1;
end if;
end if;
-- Sample data line and put into shift register.
if (r.syncsamp(1) or sample) = '1' then
v.rxd := r.rxd(wlen-1 downto 0) & indata;
if ((r.syncsamp(1) and r.incrdli) or (sample and v.incrdli)) = '1' then
v.rxdone := '1'; v.rxdone2 := '1'; v.incrdli := '0';
end if;
end if;
-- Put data into receive queue
if ((AM_EN = 0 or (r.mode.amen and r.am.skipdata) = '0') and
r.rxdone = '1') then
if AM_EN = 1 and r.am.active = '1'then
if not ((ignore > 0) and (spii_ignore = '1')) then
-- Check mask, maybe we need to skip next word in fifo
v.rdli := r.rdli + 1;
v.am.rfreecnt := v.am.rfreecnt - 1;
if DISCONT_AM_MASK then
for i in 0 to aloop loop
if i > conv_integer(r.rdli) and rstop3 = '0' then
if amask(i) = '0' then
v.rdli := v.rdli + 1;
else
rstop3 := '1';
end if;
end if;
end loop;
end if;
end if;
else
v.rdli := r.rdli + 1;
v.rfreecnt := v.rfreecnt - 1;
rx_rd := v.rd_free;
end if;
if syncram = 0 then
if AM_EN = 1 and r.am.active = '1' then
v.am.rxfifo(conv_integer(r.rdli)) := r.rxd;
else
v.rxfifo(conv_integer(r.rdli)) := r.rxd;
end if;
else
rx_wr := '1';
end if;
if r.running = '0' then
if AM_EN = 1 then v.am.rxfull := r.am.active; end if;
end if;
end if;
if AM_EN = 1 and r.mode.amen = '1' then
if TW_EN = 0 or r.mode.tw = '0' or r.mode.tto = '0' then
if r.rxdone = '1' then
v.spio.aready := '1';
end if;
else
if r.twdir = '1' and r.twdir2 = '0' then
v.spio.aready := '1';
end if;
end if;
end if;
-- Special case to put data in receive queue for automatic
-- transfer while in three wire mode with tto = 1
if AM_EN = 1 and TW_EN = 1 and r.mode.amen = '1' and
r.mode.tw = '1' and r.running = '0' and r.rxdone2 = '1' and
r.mode.tto = '1' and r.twdir = INPUT and r.mode.ms = '1' then
v.am.rxfull := r.am.active;
end if;
-- Advance transmit queue
if change = '1' then
if TW_EN = 1 and r.mode.tw = '1' then
v.spio.mosioen := r.twdir;
end if;
if r.tbitcnt = len(log2(wlen+1)-1 downto 0) then
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or
(TW_EN = 1 and r.mode.tw = '1' and
(((r.mode.ms xor r.mode.tto) = '1' and r.twdir = INPUT) or
((r.mode.ms xor r.mode.tto) = '0' and r.twdir = OUTPUT)))) then
if r.mode.cpha = '1' then
v.cgcnt := unsigned(r.mode.cg & '0');
if ASEL_EN /= 0 then v.cgasel := r.mode.tac; end if;
if AM_EN = 1 and r.mode.amen = '1' and r.am.cfg.ecgc = '1' then
v.cgcntblock := '1';
end if;
end if;
end if;
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or r.twdir = OUTPUT) then
if r.uf = '0' then
if not ((ignore > 0) and (spii_ignore = '1')) then
v.tfreecnt := v.tfreecnt + 1;
end if;
end if;
v.txdupd := '1'; tx_rd := '1';
end if;
v.tbitcnt := (others => '0');
else
v.tbitcnt := r.tbitcnt + 1;
end if;
if v.uf = '0' and (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or r.twdir = OUTPUT) then
txshift := v.running;
end if;
end if;
if txshift = '1' then
v.txd := '1' & r.txd(wlen downto 1);
end if;
if AM_EN = 1 then
if r.txdupd2 = '1' then
tx_rd := '1';
v.txdupd := '1';
end if;
end if;
if r.txdupd = '1' then
tx_rd := '1';
if r.txdbyp = '0' then
if syncram = 0 then
if AM_EN = 1 and r.mode.amen = '1' then
v.txd := r.am.txfifo(conv_integer(r.tdfi));
else
v.txd := r.txfifo(conv_integer(r.tdfi));
end if;
else
-- The first FIFO is always used when using syncrams, even in AM mode
v.txd := tx_do(0);
end if;
end if;
-- Data written to TD, bypass
if v.txdbyp = '1' then
v.txd := ntxd;
end if;
if r.tfreecnt /= FIFO_DEPTH then
if AM_EN = 0 or r.mode.amen = '0' then
v.tdfi := v.tdfi + 1;
else
-- Check mask, might need to skip next word
if not (((ignore > 0) and (spii_ignore = '1'))) then
if DISCONT_AM_MASK then
for i in 0 to aloop loop
if tstop3 = '0' and i > conv_integer(v.tdfi) then
if amask(i) = '0' then
v.tdfi := v.tdfi + 1;
else
tstop3 := '1';
end if;
end if;
end loop;
end if;
v.tdfi := v.tdfi + 1;
end if;
end if;
elsif v.txdbyp = '0' then
-- Bus idle value
v.txd(0) := '1';
end if;
end if;
-- Transmit bit
if (change or update) = '1' then
if v.uf = '0' then
v.spio.miso := r.txd(0);
v.spio.mosi := r.txd(0);
if OD_EN = 1 and r.mode.od = '1' then
if (r.mode.ms or r.mode.tw) = '1' then
v.spio.mosioen := r.txd(0) xor OUTPUT;
else
v.spio.misooen := r.txd(0) xor OUTPUT;
end if;
end if;
else
v.spio.miso := '1';
v.spio.mosi := '1';
if OD_EN = 1 and r.mode.od = '1' then
v.spio.misooen := INPUT;
v.spio.mosioen := INPUT;
end if;
end if;
end if;
-- Transfer in progress interrupt generation
if (not r.running and (r.ov2 or (r.rxdone2 or (not r.mode.ms and r.mode.tw)))) = '1' then
if r.mode.ms = '0' or r.mode.cite = '0' or r.divcnt = 0 then
v.event.tip := '0'; v.rxdone2 := '0';
end if;
end if;
if v.running = '1' then v.event.tip := '1'; end if;
if (v.running and not r.event.tip and r.mask.tip and r.mode.en) = '1' then
v.irq := '1';
end if;
-- LST detection and interrupt generation
if v.running = '0' and v.tfreecnt = FIFO_DEPTH and r.lst = '1' then
v.event.lt := '1'; v.lst := '0';
if (r.mask.lt and not r.event.lt) = '1' then v.irq := '1'; end if;
end if;
---------------------------------------------------------------------------
-- Automatic slave select, only in master mode
---------------------------------------------------------------------------
if ASEL_EN /= 0 then
if (r.mode.ms and r.mode.asel) = '1' then
if ((not r.running and v.running) or -- Transfer start or
(r.event.tip and not v.event.tip) or -- transfer end or
(v.running and (cgasel or -- End or start of CG
(r.cgasel and not (r.spiolb.sck xor r.mode.cpol))))) = '1'
then
v.slvsel := r.aslvsel;
v.aslvsel := r.slvsel;
v.cgasel := '0';
end if;
-- May need to delay start of transfer
if ((not r.running and v.running) or cgasel) = '1' then -- Transfer start
v.aselcnt := unsigned(r.mode.aseldel);
end if;
else
v.cgasel := '0';
v.aselcnt := (others => '0');
end if;
end if;
-- Do not toggle outputs in loopback mode
if (r.mode.loopb = '1' or
(r.mode.tw = '1' and TW_EN = 1 and r.twdir = INPUT)) then
v.spio.mosioen := INPUT; v.spio.misooen := INPUT;
end if;
if r.mode.loopb = '1' then v.spio.sckoen := INPUT; end if;
-- When driving in OD mode, always drive low.
if OD_EN = 1 and (r.mode.od and not r.mode.loopb) = '1' then
v.spio.miso := v.spio.miso and not r.mode.od;
v.spio.mosi := v.spio.mosi and not r.mode.od;
end if;
-- Core is disabled
if ((not RESET_ALL) and rstn = '0') or (r.mode.en = '0') then
v.tfreecnt := FIFO_DEPTH;
v.rfreecnt := FIFO_DEPTH;
v.tdfi := RES.tdfi; v.rdfi := RES.rdfi;
v.tdli := RES.tdli; v.rdli := RES.rdli;
v.rd_free := RES.rd_free;
v.td_occ := RES.td_occ;
v.lst := RES.lst;
v.uf := RES.uf;
v.ov := RES.ov;
v.running := RES.running;
v.event.tip := RES.event.tip;
v.incrdli := RES.incrdli;
if TW_EN = 1 then
v.twdir := RES.twdir;
end if;
v.spio.miso := RES.spio.miso;
v.spio.mosi := RES.spio.mosi;
if syncrst = 1 or (r.mode.en = '0') then
v.spio.misooen := RES.spio.misooen;
v.spio.mosioen := RES.spio.mosioen;
v.spio.sckoen := RES.spio.sckoen;
end if;
if AM_EN = 1 then
v.event.at := RES.event.at;
end if;
-- Need to assign samp, chng and psck here if spisel is low when the
-- core is enabled
v.samp := not r.mode.cpha;
v.chng := r.mode.cpha;
v.psck := r.mode.cpol;
if AM_EN = 1 then
v.am.active := RES.am.active;
v.am.cfg.act := RES.am.cfg.act;
v.am.cfg.eact := RES.am.cfg.eact;
v.am.unread := RES.am.unread;
v.am.rxsel := RES.am.rxsel;
end if;
v.rxdone2 := '0';
v.divcnt := (others => '0');
end if;
-- Chip reset
if (not RESET_ALL) and (rstn = '0') then
v.mode := RES.mode;
v.event.tip := RES.event.tip;
v.event.lt := RES.event.lt;
v.event.ov := RES.event.ov;
v.event.un := RES.event.un;
v.event.mme := RES.event.mme;
v.event.ne := RES.event.ne;
v.event.nf := RES.event.nf;
v.mask := RES.mask;
if AM_EN = 1 then
v.event.at := RES.event.at;
if PROG_AM_MASK then
v.am.mask_shdw := RES.am.mask_shdw;
end if;
v.am.per := RES.am.per;
v.am.cfg := RES.am.cfg;
v.am.rxread := RES.am.rxread;
v.am.txwrite := RES.am.txwrite;
v.am.txread := RES.am.txread;
v.am.apbaddr := RES.am.apbaddr;
v.am.rxsel := RES.am.rxsel;
v.cgcntblock := RES.cgcntblock;
end if;
v.lst := RES.lst;
if syncrst = 1 then
v.slvsel := RES.slvsel;
end if;
v.cgcnt := RES.cgcnt;
v.rbitcnt := RES.rbitcnt; v.tbitcnt := RES.tbitcnt;
v.txd := RES.txd;
end if;
-- Drive unused bit if open drain mode is not supported
if OD_EN = 0 then v.mode.od := '0'; end if;
-- Drive unused bits if automode is not supported
if AM_EN = 0 then
v.mode.amen := '0';
--
v.am.cfg.seq := '0';
v.am.cfg.strict := '0';
v.am.cfg.ovtb := '0';
v.am.cfg.ovdb := '0';
v.am.cfg.act := '0';
v.am.cfg.eact := '0';
v.am.per := (others => '0');
v.am.active := '0';
v.am.lock := '0';
v.am.skipdata := '0';
v.am.rxfull := '0';
v.am.rfreecnt := 0;
v.event.at := '0';
v.am.unread := (others=>'0');
v.am.cfg.erpt := '0';
v.am.cfg.lock := '0';
v.am.cfg.ecgc := '0';
v.am.cnt := (others=>'0');
v.am.rxread := '0';
v.am.txwrite := '0';
v.am.txread := '0';
v.am.apbaddr := (others => '0');
v.am.rxsel := '0';
v.mask.at := '0';
v.cstart := '0';
end if;
if AM_EN = 0 or not PROG_AM_MASK then
v.am.mask := (others=>'0');
v.am.mask_shdw := (others=>'0');
end if;
-- Drive unused bits if automatic slave select is not enabled
if ASEL_EN = 0 then
v.mode.asel := '0';
v.aslvsel := (others => '0');
v.mode.aseldel := (others => '0');
v.mode.tac := '0';
v.aselcnt := (others => '0');
v.cgasel := '0';
end if;
-- Drive unused bits if three-wire mode is not enabled
if TW_EN = 0 then
v.mode.tw := '0';
v.mode.tto := '0';
v.twdir := INPUT;
end if;
if TW_EN = 0 or AM_EN = 0 then
v.twdir2 := INPUT;
end if;
if SLVSEL_EN = 0 then
v.slvsel := (others => '1');
end if;
-- Propagate core enable bit
v.spio.enable := r.mode.en;
-- Synchronize inputs coming from off-chip
v.spii(0) := (spii_miso, spii_mosi, spii_sck, spii_spisel);
v.spii(1) := r.spii(0);
-- Outputs to RAMs
if syncram = 0 then
rx_di <= (others => (others => '0'));
tx_di <= (others => (others => '0'));
rx_ra <= (others => (others => '0'));
rx_wa <= (others => (others => '0'));
tx_ra <= (others => (others => '0'));
tx_wa <= (others => (others => '0'));
rx_read <= (others => '0'); rx_write <= (others => '0');
tx_read <= (others => '0'); tx_write <= (others => '0');
else
-- TX RAM(s) write
-- TX RAM(s) are either written from TX register or AM TX area
for i in 0 to automode loop
tx_di(i) <= ntxd;
end loop;
for i in 0 to automode loop
tx_wa(i) <= r.tdli;
end loop;
tx_write(0) <= tx_wr;
if AM_EN /= 0 then
-- Auto mode present
-- Write from AM register interface writes both RAMs
-- Write from TXD register writes RAM 0
tx_write(automode) <= r.am.txwrite;
tx_write(0) <= tx_wr or r.am.txwrite;
if r.am.txwrite = '1' then
for i in 0 to automode loop
tx_wa(i) <= r.am.apbaddr;
end loop;
end if;
end if;
-- TX RAM(s) read
-- First RAM is read by bit shift logic
tx_read(0) <= tx_rd;
tx_ra(0) <= r.tdfi;
if AM_EN /= 0 then
-- Second RAM is read from register interface
tx_read(automode) <= v.am.txread or r.am.txread;
tx_ra(automode) <= v.am.apbaddr;
end if;
-- RX RAM(s) write
-- RX RAM(s) is always written from receive shift register
for i in 0 to automode loop
rx_di(i) <= r.rxd;
rx_wa(i) <= r.rdli;
end loop;
rx_write(0) <= rx_wr;
if AM_EN /= 0 then
rx_write(automode) <= '0';
end if;
if AM_EN /= 0 and r.mode.amen = '1' then
-- AM active
-- Handle writes from bit shift logic
if r.am.rxsel = '0' then
rx_write(0) <= rx_wr;
rx_write(automode) <= '0';
else
rx_write(0) <= '0';
rx_write(automode) <= rx_wr;
end if;
end if;
-- RX RAM(s) are read via register interface
for i in 0 to automode loop
rx_ra(i) <= r.rdfi;
rx_read(i) <= rx_rd;
end loop;
if AM_EN /= 0 and r.mode.amen = '1' then
if r.am.rxsel = '0' then
rx_read(0) <= '0';
rx_read(automode) <= v.am.rxread;
if v.am.rxread = '1' then
rx_ra(automode) <= v.am.apbaddr;
end if;
else
rx_read(0) <= v.am.rxread;
rx_read(automode) <= '0';
if v.am.rxread = '1' then
rx_ra(0) <= v.am.apbaddr;
end if;
end if;
end if;
if scantest = 1 and (apbi_scanen and apbi_testen) = '1' then
rx_read <= (others => '0'); rx_write <= (others => '0');
tx_read <= (others => '0'); tx_write <= (others => '0');
end if;
end if;
v.spiolb.mosi := v.spio.mosi;
v.spiolb.sck := v.spio.sck;
-- Update registers
rin <= v;
-- Update outputs
apbo_prdata <= apbout;
apbo_pirq <= r.irq;
slvsel <= r.slvsel;
spio_miso <= r.spio.miso;
spio_misooen <= r.spio.misooen;
spio_mosi <= r.spio.mosi;
spio_mosioen <= r.spio.mosioen;
spio_sck <= r.spio.sck;
spio_sckoen <= r.spio.sckoen;
spio_enable <= r.spio.enable;
spio_astart <= r.spio.astart;
spio_aready <= r.spio.aready;
if scantest = 1 and apbi_testen = '1' then
spio_misooen <= apbi_testoen;
spio_mosioen <= apbi_testoen;
spio_sckoen <= apbi_testoen;
end if;
end process comb;
-- FIFOs
fiforams : if syncram /= 0 generate
fifoloop : for i in 0 to automode generate
noft : if ft = 0 generate
rxfifo : syncram_2p
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1)
port map (
rclk => clk,
renable => rx_read(i),
raddress => rx_ra(i),
dataout => rx_do(i),
wclk => clk,
write => rx_write(i),
waddress => rx_wa(i),
datain => rx_di(i));
-- testin => testin);
txfifo : syncram_2p
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1)
port map (
rclk => clk,
renable => tx_read(i),
raddress => tx_ra(i),
dataout => tx_do(i),
wclk => clk,
write => tx_write(i),
waddress => tx_wa(i),
datain => tx_di(i));
-- testin => testin);
end generate noft;
ftfifos : if ft /= 0 generate
ftrxfifo : syncram_2pft
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1,
ft => ft)
port map (
rclk => clk,
renable => rx_read(i),
raddress => rx_ra(i),
dataout => rx_do(i),
wclk => clk,
write => rx_write(i),
waddress => rx_wa(i),
datain => rx_di(i),
error => open);
-- testin => testin);
fttxfifo : syncram_2pft
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1,
ft => ft)
port map (
rclk => clk,
renable => tx_read(i),
raddress => tx_ra(i),
dataout => tx_do(i),
wclk => clk,
write => tx_write(i),
waddress => tx_wa(i),
datain => tx_di(i),
error => open);
-- testin => testin);
end generate ftfifos;
end generate fifoloop;
end generate fiforams;
nofiforams : if syncram = 0 generate
rx_do <= (others => (others => '0'));
tx_do <= (others => (others => '0'));
end generate;
-- Registers
reg: process (clk, arstn)
begin -- process reg
if rising_edge(clk) then
r <= rin;
if rstn = '0' then
r.spio.sck <= RES.spio.sck;
r.rbitcnt <= RES.rbitcnt; r.tbitcnt <= RES.tbitcnt;
if RESET_ALL then
r <= RES;
-- Do not use synchronous reset for sync. registers
r.spii <= rin.spii;
end if;
end if;
end if;
if syncrst = 0 and arstn = '0' then
r.spio.misooen <= RES.spio.misooen;
r.spio.mosioen <= RES.spio.mosioen;
r.spio.sckoen <= RES.spio.sckoen;
if SLVSEL_EN /= 0 then
r.slvsel <= RES.slvsel;
end if;
end if;
end process reg;
end architecture rtl;
|
gpl-2.0
|
2721b841deb4d416b18c19fbb15af12c
| 0.50191 | 3.416221 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/uc00.vhd
| 1 | 2,121 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity uc00 is
port(
clkuc: in std_logic ;
inFlaguc: in std_logic ;
inFlaguc2: in std_logic ;
enable: in std_logic ;
inuc: in std_logic_vector ( 7 downto 0 );
outuc: out std_logic_vector ( 7 downto 0 );
outFlaguc: out std_logic );
end;
architecture uc0 of uc00 is
begin
puc: process(clkuc, enable, inuc)
begin
if(clkuc = '1' and enable = '1') then
outFlaguc <= '1';
outuc <= inuc;
else
outFlaguc <= '0';
outuc <= (others => '0');
end if;
end process puc;
--puc: process(clkuc, inFlaguc, enable)
-- begin
-- if (clkuc'event and clkuc = '1') then
-- if (inFlaguc = '0' and inFlaguc2 = '0') then
-- if (enable = '1') then
-- outuc <= inuc;
-- outFlaguc <= '1';
-- else
-- outuc <= (others => 'Z');
-- outFlaguc <= 'Z';
-- end if;
-- elsif (inFlaguc = '0' and inFlaguc2 = '1') then
-- if (enable = '1') then
-- outuc <= (others => 'Z');
-- outFlaguc <= 'Z';
-- else
-- outuc <= (others => 'Z');
-- outFlaguc <= 'Z';
-- end if;
-- elsif (inFlaguc = '1' and inFlaguc2 = '0') then
-- if (enable = '1') then
-- outuc <= inuc;
-- outFlaguc <= '1';
-- else
-- outuc <= (others => 'Z');
-- outFlaguc <= 'Z';
-- end if;
-- elsif (inFlaguc = '1' and inFlaguc2 = '1') then
-- if (enable = '1') then
-- outuc <= (others => 'Z');
-- outFlaguc <= 'Z';
-- else
-- outuc <= (others => 'Z');
-- outFlaguc <= 'Z';
-- end if;
-- end if;
-- end if;
-- end process puc;
end uc0;
|
apache-2.0
|
11fa323fc2dd26c9e24c3f5cfaa250d8
| 0.404055 | 3.619454 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/micron/sdram/components.vhd
| 1 | 13,878 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Package: components
-- File: components.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Component declaration of Micron SDRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package components is
component mt48lc16m16a2
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec" -- File to read from
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
end component;
component mt46v16m16
GENERIC ( -- Timing for -75Z CL2
tCK : TIME := 7.500 ns;
tCH : TIME := 3.375 ns; -- 0.45*tCK
tCL : TIME := 3.375 ns; -- 0.45*tCK
tDH : TIME := 0.500 ns;
tDS : TIME := 0.500 ns;
tIH : TIME := 0.900 ns;
tIS : TIME := 0.900 ns;
tMRD : TIME := 15.000 ns;
tRAS : TIME := 40.000 ns;
tRAP : TIME := 20.000 ns;
tRC : TIME := 65.000 ns;
tRFC : TIME := 75.000 ns;
tRCD : TIME := 20.000 ns;
tRP : TIME := 20.000 ns;
tRRD : TIME := 15.000 ns;
tWR : TIME := 15.000 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
cols_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec"; -- File to read from
bbits : INTEGER := 16;
fdelay : INTEGER := 0;
chktiming : boolean := true
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END component;
component ftmt48lc16m16a2
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec"; -- File to read from
err : INTEGER := 0
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
end component;
component ddr2 is
generic(
DM_BITS : integer := 2;
ADDR_BITS : integer := 13;
ROW_BITS : integer := 13;
COL_BITS : integer := 9;
DQ_BITS : integer := 16;
DQS_BITS : integer := 2;
TRRD : integer := 10000;
TFAW : integer := 50000;
DEBUG : integer := 0
);
port (
ck : in std_ulogic;
ck_n : in std_ulogic;
cke : in std_ulogic;
cs_n : in std_ulogic;
ras_n : in std_ulogic;
cas_n : in std_ulogic;
we_n : in std_ulogic;
dm_rdqs : inout std_logic_vector(DQS_BITS-1 downto 0);
ba : in std_logic_vector(1 downto 0);
addr : in std_logic_vector(ADDR_BITS-1 downto 0);
dq : inout std_logic_vector(DQ_BITS-1 downto 0);
dqs : inout std_logic_vector(DQS_BITS-1 downto 0);
dqs_n : inout std_logic_vector(DQS_BITS-1 downto 0);
rdqs_n : out std_logic_vector(DQS_BITS-1 downto 0);
odt : in std_ulogic
);
end component;
component mobile_ddr
--GENERIC ( -- Timing for -75Z CL2
-- tCK : TIME := 7.500 ns;
-- tCH : TIME := 3.375 ns; -- 0.45*tCK
-- tCL : TIME := 3.375 ns; -- 0.45*tCK
-- tDH : TIME := 0.500 ns;
-- tDS : TIME := 0.500 ns;
-- tIH : TIME := 0.900 ns;
-- tIS : TIME := 0.900 ns;
-- tMRD : TIME := 15.000 ns;
-- tRAS : TIME := 40.000 ns;
-- tRAP : TIME := 20.000 ns;
-- tRC : TIME := 65.000 ns;
-- tRFC : TIME := 75.000 ns;
-- tRCD : TIME := 20.000 ns;
-- tRP : TIME := 20.000 ns;
-- tRRD : TIME := 15.000 ns;
-- tWR : TIME := 15.000 ns;
-- addr_bits : INTEGER := 13;
-- data_bits : INTEGER := 16;
-- cols_bits : INTEGER := 9;
-- index : INTEGER := 0;
-- fname : string := "ram.srec"; -- File to read from
-- bbits : INTEGER := 32
--);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => 'Z');
----Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => 'Z');
----Dqs : INOUT STD_LOGIC_VECTOR (data_bits/8 - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
----Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
----Dm : IN STD_LOGIC_VECTOR (data_bits/8 - 1 DOWNTO 0)
);
END component;
component mobile_ddr_fe
generic (addr_swap : integer := 0);
port (
Dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
BEaddr: out std_logic_vector (24 downto 0);
BEwr : out std_logic_vector(1 downto 0);
BEdin : out std_logic_vector(15 downto 0);
BEdout: in std_logic_vector(15 downto 0);
BEclear: out std_logic;
BEclrpart: out std_logic;
BEsynco: out std_logic;
BEsynci: in std_logic
);
end component;
component mobile_ddr_febe
generic (
dbits: integer := 32;
rampad: integer := 0;
fname: string := "dummy";
autoload: integer := 1;
rstmode: integer := 0;
rstdatah: integer := 16#DEAD#;
rstdatal: integer := 16#BEEF#;
addr_swap : integer := 0;
offset_addr : std_logic_vector(31 downto 0) := x"00000000";
swap_halfw : integer := 0
);
port (
Dq : INOUT STD_LOGIC_VECTOR (dbits-1 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (dbits/8-1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (dbits/8-1 DOWNTO 0)
);
end component;
component mobile_ddr2_fe
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ca : in std_logic_vector( 9 downto 0);
dm : in std_logic_vector( 1 downto 0);
dq : inout std_logic_vector(15 downto 0) := (OTHERS => 'Z');
dqs : inout std_logic_vector( 1 downto 0) := (OTHERS => 'Z');
dqs_n : inout std_logic_vector( 1 downto 0) := (OTHERS => 'Z');
BEaddr : out std_logic_vector(27 downto 0);
BEwr_h : out std_logic_vector( 1 downto 0);
BEwr_l : out std_logic_vector( 1 downto 0);
BEdin_h : out std_logic_vector(15 downto 0);
BEdin_l : out std_logic_vector(15 downto 0);
BEdout_h: in std_logic_vector(15 downto 0);
BEdout_l: in std_logic_vector(15 downto 0);
BEclear : out std_logic;
BEreload: out std_logic;
BEsynco : out std_logic;
BEsynci : in std_logic
);
end component;
component mobile_ddr2_febe
generic (
dbits: integer := 32;
rampad: integer := 0;
fname: string := "dummy";
autoload: integer := 1;
rstmode: integer := 0;
rstdatah: integer := 16#DEAD#;
rstdatal: integer := 16#BEEF#
);
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ca : in std_logic_vector( 9 downto 0);
dm : in std_logic_vector(dbits/8-1 downto 0);
dq : inout std_logic_vector( dbits-1 downto 0) := (OTHERS => 'Z');
dqs : inout std_logic_vector(dbits/8-1 downto 0) := (OTHERS => 'Z');
dqs_n : inout std_logic_vector(dbits/8-1 downto 0) := (OTHERS => 'Z')
);
end component;
component mobile_sdr
--GENERIC (
-- DEBUG : INTEGER := 1;
-- addr_bits : INTEGER := 13;
-- data_bits : INTEGER := 16
--);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
end component;
end;
-- pragma translate_on
|
gpl-2.0
|
e1c7d37877e46c879d59f31a13cf2466
| 0.453596 | 3.320096 | false | false | false | false |
lunod/lt24_ctrl
|
rtl/lt24ctrl.vhd
| 1 | 5,713 |
---------------------------------------------------------------------------
-- This file is part of lt24ctrl, a video controler IP core for Terrasic
-- LT24 LCD display
-- Copyright (C) 2017 Ludovic Noury <[email protected]>
--
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
---------------------------------------------------------------------------
-- Remarks :
-- * LT24 is a 320x240 LCD screen but the integrated controller considers
-- a 240x320 display with x=0 and y=0 the pixel on the top left when the
-- screen is held vertically with PCB text "terasic LT24" on the right
-- side.
-- Hence the choice to provide an interface with y=320 lines of x=240
-- pixels.
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
---------------------------------------------------------------------------
entity lt24ctrl is
generic(system_frequency: real := 50_000_000.0;
tmin_cycles : natural := 1);
port (
clk : in std_logic;
resetn : in std_logic;
x : out std_logic_vector(7 downto 0); -- 0 .. 239 => 8 bits
y : out std_logic_vector(8 downto 0); -- 0 .. 319 => 9 bits
c : in std_logic_vector(15 downto 0); -- couleurs 16 bits
lt24_reset_n: out std_logic;
lt24_cs_n : out std_logic;
lt24_rs : out std_logic;
lt24_rd_n : out std_logic;
lt24_wr_n : out std_logic;
lt24_d : out std_logic_vector(15 downto 0);
lt24_lcd_on : out std_logic);
end entity lt24ctrl;
---------------------------------------------------------------------------
architecture inst of lt24ctrl is
signal rom_addr : std_logic_vector(6 downto 0);
signal rom_data : std_logic_vector(16 downto 0);
signal clr_cptdelay, tick_1ms, tick_10ms,
tick_120ms, tick_tmin : std_logic;
signal clr_init_rom_addr, inc_init_rom_addr,
end_init_rom : std_logic;
signal clr_cptpix, inc_cptpix, end_cptpix : std_logic;
signal lt24_reset_n_noreg, lt24_cs_n_noreg,
lt24_rs_noreg, lt24_rd_n_noreg,
lt24_wr_n_noreg, lt24_lcd_on_noreg : std_logic;
signal lt24_d_noreg : std_logic_vector(lt24_d'range);
begin
rom: entity work.rom_init_lt24
port map(
clk => clk,
addr => rom_addr,
q => rom_data);
cpt_timming: entity work.cpt_delay
generic map(system_frequency => system_frequency,
tmin_cycles => tmin_cycles)
port map(clk => clk,
resetn => resetn,
clr_cptdelay => clr_cptdelay,
tick_1ms => tick_1ms,
tick_10ms => tick_10ms,
tick_120ms => tick_120ms,
tick_tmin => tick_tmin);
cpt_address: entity work.cpt_addr_rom
port map(clk => clk,
resetn => resetn,
clr_init_rom_addr => clr_init_rom_addr,
inc_init_rom_addr => inc_init_rom_addr,
end_init_rom => end_init_rom,
address => rom_addr);
cpt_pixels: entity work.cpt_pix
port map(clk => clk,
resetn => resetn,
clr_cptpix => clr_cptpix,
inc_cptpix => inc_cptpix,
end_cptpix => end_cptpix,
x => x,
y => y);
fsm: entity work.lt24_fsm
port map(clk => clk,
resetn => resetn,
tick_1ms => tick_1ms,
tick_10ms => tick_10ms,
tick_120ms => tick_120ms,
tick_tmin => tick_tmin,
clr_cptdelay => clr_cptdelay,
clr_init_rom_addr => clr_init_rom_addr,
inc_init_rom_addr => inc_init_rom_addr,
end_init_rom => end_init_rom,
init_rom_data => rom_data,
clr_cptpix => clr_cptpix,
inc_cptpix => inc_cptpix,
end_cptpix => end_cptpix,
color => c,
lt24_reset_n => lt24_reset_n_noreg,
lt24_lcd_on => lt24_lcd_on_noreg,
lt24_cs_n => lt24_cs_n_noreg,
lt24_rs => lt24_rs_noreg,
lt24_rd_n => lt24_rd_n_noreg,
lt24_wr_n => lt24_wr_n_noreg,
lt24_d => lt24_d_noreg);
-- Register outputs to relax timming delays and have clean/glitchless
-- outputs from the FPGA to LT24
sync_out:process(clk)
begin
if rising_edge(clk) then
lt24_reset_n <= lt24_reset_n_noreg;
lt24_cs_n <= lt24_cs_n_noreg;
lt24_rs <= lt24_rs_noreg;
lt24_rd_n <= lt24_rd_n_noreg;
lt24_wr_n <= lt24_wr_n_noreg;
lt24_d <= lt24_d_noreg;
lt24_lcd_on <= lt24_lcd_on_noreg;
end if;
end process;
end architecture inst;
---------------------------------------------------------------------------
|
lgpl-3.0
|
1117a1b16a7f1779b5b23f4a97ef5097
| 0.498512 | 3.763505 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/cycloneiii/alt/apll.vhd
| 4 | 8,874 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY apll IS
generic (
freq : integer := 200;
mult : integer := 8;
div : integer := 5;
rskew : integer := 0
);
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
phasestep : IN STD_LOGIC := '0';
phaseupdown : IN STD_LOGIC := '0';
scanclk : IN STD_LOGIC := '1';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC ;
phasedone : OUT STD_LOGIC
);
END apll;
ARCHITECTURE SYN OF apll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC ;
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire10_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire10 : STD_LOGIC_VECTOR (0 DOWNTO 0);
signal phasecounter_reg : std_logic_vector(2 downto 0);
attribute syn_keep : boolean;
attribute syn_keep of phasecounter_reg : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of phasecounter_reg : signal is true;
constant period : integer := 1000000/freq;
function set_phase(freq : in integer) return string is
variable s : string(1 to 4) := "0000";
variable f,r : integer;
begin
f := freq;
while f /= 0 loop
r := f mod 10;
case r is
when 0 => s := "0" & s(1 to 3);
when 1 => s := "1" & s(1 to 3);
when 2 => s := "2" & s(1 to 3);
when 3 => s := "3" & s(1 to 3);
when 4 => s := "4" & s(1 to 3);
when 5 => s := "5" & s(1 to 3);
when 6 => s := "6" & s(1 to 3);
when 7 => s := "7" & s(1 to 3);
when 8 => s := "8" & s(1 to 3);
when 9 => s := "9" & s(1 to 3);
when others =>
end case;
f := f / 10;
end loop;
return s;
end function;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 21) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769"), -- 120 & 130 MHz
("1786", "3571", "5357"), ("1667", "3333", "5000"), -- 140 & 150 MHz
("1563", "3125", "4688"), ("1471", "2941", "4412"), -- 160 & 170 MHz
("1389", "2778", "4167"), ("1316", "2632", "3947"), -- 180 & 190 MHz
("1250", "2500", "3750"), ("1190", "2381", "3571")); -- 200 & 210 MHz
--constant pshift_90 : string := phasearr((freq*mult)/(10*div))(1);
constant pshift_90 : string := set_phase(100000/((4*freq*mult)/(10*div)));
--constant pshift_180 : string := phasearr((freq*mult)/(10*div))(2);
constant pshift_180 : string := set_phase(100000/((2*freq*mult)/(10*div)));
--constant pshift_270 : string := phasearr((freq*mult)/(10*div))(3);
constant pshift_270 : string := set_phase(300000/((4*freq*mult)/(10*div)));
constant pshift_rclk : string := set_phase(rskew);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
clk4_divide_by : NATURAL;
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL;
width_phasecounterselect : NATURAL
);
PORT (
phasestep : IN STD_LOGIC ;
phaseupdown : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
phasecounterselect : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
locked : OUT STD_LOGIC ;
phasedone : OUT STD_LOGIC ;
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
scanclk : IN STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire10_bv(0 DOWNTO 0) <= "0";
sub_wire10 <= To_stdlogicvector(sub_wire10_bv);
sub_wire5 <= sub_wire0(4);
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
c3 <= sub_wire4;
c4 <= sub_wire5;
locked <= sub_wire6;
--phasedone <= sub_wire7;
sub_wire8 <= inclk0;
sub_wire9 <= sub_wire10(0 DOWNTO 0) & sub_wire8;
-- quartus bug, cant be constant
process(scanclk)
begin
if rising_edge(scanclk) then
phasecounter_reg <= "110"; --phasecounter;
end if;
end process;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => div,--1,
clk0_duty_cycle => 50,
clk0_multiply_by => mult,--1,
clk0_phase_shift => "0",
clk1_divide_by => div,--1,
clk1_duty_cycle => 50,
clk1_multiply_by => mult,--1,
clk1_phase_shift => pshift_90,--"2500",
clk2_divide_by => div,--1,
clk2_duty_cycle => 50,
clk2_multiply_by => mult,--1,
clk2_phase_shift => pshift_180,--"5000",
clk3_divide_by => div,--1,
clk3_duty_cycle => 50,
clk3_multiply_by => mult,--1,
clk3_phase_shift => pshift_270,--"7500",
clk4_divide_by => div,--1,
clk4_duty_cycle => 50,
clk4_multiply_by => mult,--1,
clk4_phase_shift => pshift_rclk,--"0",
compensate_clock => "CLK0",
inclk0_input_frequency => period,--10000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=apll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "Fast",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_USED",
port_phasedone => "PORT_USED",
port_phasestep => "PORT_USED",
port_phaseupdown => "PORT_USED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_USED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_USED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5,
width_phasecounterselect => 3
)
PORT MAP (
phasestep => phasestep,
phaseupdown => phaseupdown,
inclk => sub_wire9,
phasecounterselect => phasecounter_reg,
areset => areset,
scanclk => scanclk,
clk => sub_wire0,
locked => sub_wire6,
phasedone => phasedone
);
END SYN;
|
gpl-2.0
|
e74f61a704d2c568dfd88c676285ea72
| 0.610097 | 2.748219 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/eth/core/greth_rx.vhd
| 1 | 11,677 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_rx
-- File: greth_rx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet receiver
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
attribute sync_set_reset of rst : signal is "true";
end entity;
architecture rtl of greth_rx is
-- constant maxsize : integer := 1518;
constant maxsizerx : unsigned(15 downto 0) :=
to_unsigned(maxsize + 18, 16);
constant minsize : integer := 64;
--receiver types
type rx_state_type is (idle, wait_sfd, data1, data2, errorst, report_status,
wait_report, check_crc, discard_packet);
type rx_reg_type is record
er : std_ulogic;
en : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rxdp : std_logic_vector(3 downto 0);
crc : std_logic_vector(31 downto 0);
sync_start : std_ulogic;
gotframe : std_ulogic;
start : std_ulogic;
write : std_ulogic;
done : std_ulogic;
odd_nibble : std_ulogic;
lentype : std_logic_vector(15 downto 0);
ltfound : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
data : std_logic_vector(31 downto 0);
dataout : std_logic_vector(31 downto 0);
rx_state : rx_state_type;
status : std_logic_vector(3 downto 0);
write_ack : std_logic_vector(nsync-1 downto 0);
done_ack : std_logic_vector(nsync downto 0);
rxen : std_logic_vector(1 downto 0);
got4b : std_ulogic;
mcasthash : std_logic_vector(5 downto 0);
hashlock : std_ulogic;
--rmii
enold : std_ulogic;
act : std_ulogic;
dv : std_ulogic;
cnt : std_logic_vector(3 downto 0);
rxd2 : std_logic_vector(1 downto 0);
speed : std_logic_vector(1 downto 0);
zero : std_ulogic;
end record;
--receiver signals
signal r, rin : rx_reg_type;
signal rxrst : std_ulogic;
signal vcc : std_ulogic;
-- attribute sync_set_reset : string;
attribute sync_set_reset of rxrst : signal is "true";
begin
vcc <= '1';
rx_rst : eth_rstgen
port map(rst, clk, vcc, rxrst, open);
rx : process(rxrst, r, rxi) is
variable v : rx_reg_type;
variable index : integer range 0 to 3;
variable crc_en : std_ulogic;
variable write_req : std_ulogic;
variable write_ack : std_ulogic;
variable done_ack : std_ulogic;
variable er : std_ulogic;
variable dv : std_ulogic;
variable act : std_ulogic;
variable rxd : std_logic_vector(3 downto 0);
begin
v := r; v.rxd := rxi.rxd(3 downto 0);
if rmii = 0 then
v.en := rxi.rx_dv;
else
v.en := rxi.rx_crs;
end if;
v.er := rxi.rx_er; write_req := '0'; crc_en := '0';
index := conv_integer(r.byte_count(1 downto 0));
--synchronization
v.rxen(1) := r.rxen(0); v.rxen(0) := rxi.enable;
v.write_ack(0) := rxi.writeack;
v.done_ack(0) := rxi.doneack;
if nsync = 2 then
v.write_ack(1) := r.write_ack(0);
v.done_ack(1) := r.done_ack(0);
end if;
write_ack := not (r.write xor r.write_ack(nsync-1));
done_ack := not (r.done xor r.done_ack(nsync-1));
--rmii/mii
if rmii = 0 then
er := r.er; dv := r.en; act := r.en; rxd := r.rxd;
else
--sync
v.speed(1) := r.speed(0); v.speed(0) := rxi.speed;
rxd := r.rxd(1 downto 0) & r.rxd2;
if r.cnt = "0000" then
v.cnt := "1001";
else
v.cnt := r.cnt - 1;
end if;
if v.cnt = "0000" then
v.zero := '1';
else
v.zero := '0';
end if;
act := r.act; er := '0';
if r.speed(1) = '0' then
if r.zero = '1' then
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
if r.dv = '0' then
v.rxd2 := r.rxd(1 downto 0);
end if;
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
else
dv := '0';
end if;
else
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
v.rxd2 := r.rxd(1 downto 0);
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
end if;
end if;
if (r.en and not r.act) = '1' then
if (rxd = "0101") and (r.speed(1) or
(not r.speed(1) and r.zero)) = '1' then
v.act := '1'; v.dv := '0'; v.rxdp := rxd;
end if;
end if;
if (dv = '1') then
v.rxdp := rxd;
end if;
if multicast = 1 then
if (r.byte_count(2 downto 0) = "110") and (r.hashlock = '0') then
v.mcasthash := r.crc(5 downto 0); v.hashlock := '1';
end if;
end if;
--fsm
case r.rx_state is
when idle =>
v.gotframe := '0'; v.status := (others => '0'); v.got4b := '0';
v.byte_count := (others => '0'); v.odd_nibble := '0';
v.ltfound := '0';
if multicast = 1 then
v.hashlock := '0';
end if;
if (dv and r.rxen(1)) = '1' then
if (rxd = "1101") and (r.rxdp = "0101") then
v.rx_state := data1; v.sync_start := not r.sync_start;
end if;
v.start := '0'; v.crc := (others => '1');
if er = '1' then v.status(2) := '1'; end if;
elsif dv = '1' then
v.rx_state := discard_packet;
end if;
when discard_packet =>
if act = '0' then v.rx_state := idle; end if;
when data1 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data2;
case index is
when 0 => v.data(27 downto 24) := rxd;
when 1 => v.data(19 downto 16) := rxd;
when 2 => v.data(11 downto 8) := rxd;
when 3 => v.data(3 downto 0) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if (r.byte_count(1 downto 0) = "00" and (r.start and act and dv) = '1') then
write_req := '1';
end if;
if er = '1' then v.status(2) := '1'; end if;
if conv_integer(r.byte_count) > maxsizerx then
v.rx_state := errorst; v.status(1) := '1';
v.byte_count := r.byte_count - 4;
end if;
v.got4b := v.byte_count(2) or r.got4b;
when data2 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data1;
v.byte_count := r.byte_count + 1; v.start := '1';
case index is
when 0 => v.data(31 downto 28) := rxd;
when 1 => v.data(23 downto 20) := rxd;
when 2 => v.data(15 downto 12) := rxd;
when 3 => v.data(7 downto 4) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if er = '1' then v.status(2) := '1'; end if;
v.got4b := v.byte_count(2) or r.got4b;
when check_crc =>
if r.crc /= X"C704DD7B" then
if r.odd_nibble = '1' then v.status(0) := '1';
else v.status(2) := '1'; end if;
end if;
if write_ack = '1' then
if r.got4b = '1' then
v.byte_count := r.byte_count - 4;
else
v.byte_count := (others => '0');
end if;
v.rx_state := report_status;
if conv_integer(r.byte_count) < minsize then
v.rx_state := wait_report; v.done := not r.done;
end if;
end if;
when errorst =>
if act = '0' then
v.rx_state := wait_report; v.done := not r.done;
v.gotframe := '1';
end if;
when report_status =>
v.done := not r.done; v.rx_state := wait_report;
v.gotframe := '1';
when wait_report =>
if done_ack = '1' then
if act = '1' then
v.rx_state := discard_packet;
else
v.rx_state := idle;
end if;
end if;
when others => null;
end case;
--write to fifo
if write_req = '1' then
if (r.status(3) or not write_ack) = '1' then
v.status(3) := '1';
else
v.dataout := r.data; v.write := not r.write;
end if;
if (r.byte_count(4 downto 2) = "100") and (r.ltfound = '0') then
v.lentype := r.data(31 downto 16) + 14; v.ltfound := '1';
end if;
end if;
if write_ack = '1' then
if rxi.writeok = '0' then v.status(3) := '1'; end if;
end if;
--crc generation
if crc_en = '1' then
v.crc := calccrc(rxd, r.crc);
end if;
if rxrst = '0' then
v.rx_state := idle; v.write := '0'; v.done := '0'; v.sync_start := '0';
v.done_ack := (others => '0');
v.gotframe := '0'; v.write_ack := (others => '0');
v.dv := '0'; v.cnt := (others => '0'); v.zero := '0';
v.byte_count := (others => '0'); v.lentype := (others => '0');
v.status := (others => '0'); v.got4b := '0'; v.odd_nibble := '0';
v.ltfound := '0';
if multicast = 1 then
v.hashlock := '0';
end if;
end if;
if rmii = 0 then
v.cnt := (others => '0'); v.zero := '0';
end if;
rin <= v;
rxo.dataout <= r.dataout;
rxo.start <= r.sync_start;
rxo.done <= r.done;
rxo.write <= r.write;
rxo.status <= r.status;
rxo.gotframe <= r.gotframe;
rxo.byte_count <= r.byte_count;
rxo.lentype <= r.lentype;
rxo.mcasthash <= r.mcasthash;
end process;
gmiimode0 : if gmiimode = 0 generate
rxregs0 : process(clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end generate;
gmiimode1 : if gmiimode = 1 generate
rxregs1 : process(clk) is
begin
if rising_edge(clk) then
if (rxi.rx_en = '1' or rxrst = '0') then r <= rin; end if;
end if;
end process;
end generate;
end architecture;
|
gpl-2.0
|
0a8f335d36adc451f753b07da7746fcf
| 0.501841 | 3.249026 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/leon3/leon3.vhd
| 1 | 41,323 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: leon3
-- File: leon3.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: LEON3 types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package leon3 is
constant LEON3_VERSION : integer := 3;
type l3_irq_in_type is record
irl : std_logic_vector(3 downto 0);
rst : std_ulogic;
run : std_ulogic;
rstvec : std_logic_vector(31 downto 12);
iact : std_ulogic;
index : std_logic_vector(3 downto 0);
hrdrst : std_ulogic;
end record;
type l3_irq_out_type is record
intack : std_ulogic;
irl : std_logic_vector(3 downto 0);
pwd : std_ulogic;
fpen : std_ulogic;
idle : std_ulogic;
end record;
type l3_debug_in_type is record
dsuen : std_ulogic; -- DSU enable
denable : std_ulogic; -- diagnostic register access enable
dbreak : std_ulogic; -- debug break-in
step : std_ulogic; -- single step
halt : std_ulogic; -- halt processor
reset : std_ulogic; -- reset processor
dwrite : std_ulogic; -- read/write
daddr : std_logic_vector(23 downto 2); -- diagnostic address
ddata : std_logic_vector(31 downto 0); -- diagnostic data
btrapa : std_ulogic; -- break on IU trap
btrape : std_ulogic; -- break on IU trap
berror : std_ulogic; -- break on IU error mode
bwatch : std_ulogic; -- break on IU watchpoint
bsoft : std_ulogic; -- break on software breakpoint (TA 1)
tenable : std_ulogic;
timer : std_logic_vector(30 downto 0); --
end record;
constant dbgi_none : l3_debug_in_type := ('0', '0', '0', '0', '0',
'0', '0', (others => '0'), (others => '0'), '0', '0', '0', '0', '0', '0', (others => '0'));
constant l3_dbgi_none : l3_debug_in_type := dbgi_none;
type l3_cstat_type is record
cmiss : std_ulogic; -- cache miss
tmiss : std_ulogic; -- TLB miss
chold : std_ulogic; -- cache hold
mhold : std_ulogic; -- cache mmu hold
end record;
constant cstat_none : l3_cstat_type := ('0', '0', '0', '0');
type l3_debug_out_type is record
data : std_logic_vector(31 downto 0);
crdy : std_ulogic;
dsu : std_ulogic;
dsumode : std_ulogic;
error : std_ulogic;
halt : std_ulogic;
pwd : std_ulogic;
idle : std_ulogic;
ipend : std_ulogic;
icnt : std_ulogic;
fcnt : std_ulogic;
optype : std_logic_vector(5 downto 0); -- instruction type
bpmiss : std_ulogic; -- branch predict miss
istat : l3_cstat_type;
dstat : l3_cstat_type;
wbhold : std_ulogic; -- write buffer hold
su : std_ulogic; -- supervisor state
end record;
type l3_debug_in_vector is array (natural range <>) of l3_debug_in_type;
type l3_debug_out_vector is array (natural range <>) of l3_debug_out_type;
constant dbgo_none : l3_debug_out_type := (X"00000000", '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', "000000", '0', cstat_none, cstat_none, '0', '0');
constant l3_dbgo_none : l3_debug_out_type := dbgo_none;
type tracebuf_in_type is record
addr : std_logic_vector(11 downto 0);
data : std_logic_vector(255 downto 0);
enable : std_logic;
write : std_logic_vector(7 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(255 downto 0);
end record;
type tracebuf_2p_in_type is record
renable : std_logic;
raddr : std_logic_vector(11 downto 0);
write : std_logic_vector(7 downto 0);
waddr : std_logic_vector(11 downto 0);
data : std_logic_vector(255 downto 0);
end record;
type tracebuf_2p_out_type is record
data : std_logic_vector(255 downto 0);
end record;
component tbufmem
generic ( tech : integer := 0; tbuf : integer := 0; dwidth : integer := 32; testen: integer := 0);
port (
clk : in std_ulogic;
di : in tracebuf_in_type;
do : out tracebuf_out_type;
testin: in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end component;
component tbufmem_2p is
generic (
tech : integer := 0;
tbuf : integer := 0; -- trace buf size in kB (0 - no trace buffer)
dwidth : integer := 64; -- AHB data width
testen : integer := 0
);
port (
clk : in std_ulogic;
di : in tracebuf_2p_in_type;
do : out tracebuf_2p_out_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end component;
constant tracebuf_out_type_none : tracebuf_out_type :=
(data => (others => '0'));
constant tracebuf_in_type_none : tracebuf_in_type := (
addr => (others => '0'),
data => (others => '0'),
enable => '0',
write => (others => '0')
);
constant tracebuf_2p_out_type_none : tracebuf_2p_out_type :=
(data => (others => '0'));
constant tracebuf_2p_in_type_none : tracebuf_2p_in_type := (
renable => '0',
raddr => (others => '0'),
write => (others => '0'),
waddr => (others => '0'),
data => (others => '0')
);
component leon3s
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type
);
end component;
component leon3cg
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic
);
end component;
component leon3ft
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0; -- cacheability table
netlist : integer := 0; -- use netlist
scantest : integer := 0; -- enable scan test support
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic
);
end component;
type grfpu_in_type is record
start : std_logic;
nonstd : std_logic;
flop : std_logic_vector(8 downto 0);
op1 : std_logic_vector(63 downto 0);
op2 : std_logic_vector(63 downto 0);
opid : std_logic_vector(7 downto 0);
flush : std_logic;
flushid : std_logic_vector(5 downto 0);
rndmode : std_logic_vector(1 downto 0);
req : std_logic_vector(2 downto 0);
end record;
constant grfpu_in_none : grfpu_in_type :=
('0', '0', (others => '0'), (others => '0'), (others => '0'),
(others => '0'), '0', (others => '0'), (others => '0'),
(others => '0'));
type grfpu_out_type is record
res : std_logic_vector(63 downto 0);
exc : std_logic_vector(5 downto 0);
allow : std_logic_vector(2 downto 0);
rdy : std_logic;
cc : std_logic_vector(1 downto 0);
idout : std_logic_vector(7 downto 0);
end record;
constant grfpu_out_none : grfpu_out_type :=
((others => '0'), (others => '0'), (others => '0'),
'0', (others => '0'), (others => '0'));
type grfpu_out_vector_type is array (integer range 0 to 7) of grfpu_out_type;
type grfpu_in_vector_type is array (integer range 0 to 7) of grfpu_in_type;
component grfpushwx
generic (mul : integer := 0;
nshare : integer range 0 to 8 := 0;
tech : integer;
arb : integer range 0 to 2 := 1);
port(
clk : in std_logic;
reset : in std_logic;
fpvi : in grfpu_in_vector_type;
fpvo : out grfpu_out_vector_type
);
end component;
component leon3sh
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
component leon3s2x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
clk2x : integer := 1;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
gclk2 : in std_ulogic;
clk2 : in std_ulogic; -- snoop clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
clken : in std_ulogic
);
end component;
component leon3ft2x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
clk2x : integer := 1;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end component;
type dsu_in_type is record
enable : std_ulogic;
break : std_ulogic;
end record;
subtype dsu_astat_type is amba_stat_type;
constant dsu_astat_none : dsu_astat_type := amba_stat_none;
type dsu_out_type is record
active : std_ulogic;
tstop : std_ulogic;
pwd : std_logic_vector(15 downto 0);
astat : dsu_astat_type;
end record;
constant dsu_out_none : dsu_out_type :=
(active => '0', tstop => '0', pwd => (others => '0'),
astat => dsu_astat_none);
component dsu3
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end component;
component dsu3_2x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
end component;
component dsu3x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
clk2x : integer range 0 to 1 := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
end component;
component dsu3_mb
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end component;
type l3stat_src_array is array (15 downto 0) of std_logic_vector(3 downto 0);
type l3stat_in_type is record
event : std_logic_vector(15 downto 0);
esource : l3stat_src_array;
sel : std_logic_vector(15 downto 0);
req : std_logic_vector(15 downto 0);
latcnt : std_ulogic;
timer : std_logic_vector(31 downto 0);
end record;
constant l3stat_in_none : l3stat_in_type :=
(event => (others => '0'),
esource => (others => (others => '0')),
sel => (others => '0'),
req => (others => '0'),
latcnt => '0',
timer => (others => '0'));
component l3stat
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncnt : integer := 2;
ncpu : integer := 1;
nmax : integer := 0;
lahben : integer := 0;
dsuen : integer := 0;
nextev : integer range 0 to 16 := 0;
apb2en : integer := 0;
pindex2 : integer := 0;
paddr2 : integer := 0;
pmask2 : integer := 16#fff#;
astaten : integer := 0;
selreq : integer := 0;
clatch : integer := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbsi : in ahb_slv_in_type;
dbgo : in l3_debug_out_vector(0 to NCPU-1);
dsuo : in dsu_out_type := dsu_out_none;
stati : in l3stat_in_type := l3stat_in_none;
apb2i : in apb_slv_in_type := apb_slv_in_none;
apb2o : out apb_slv_out_type;
astat : in amba_stat_type := amba_stat_none);
end component;
type irq_in_vector is array (Natural range <> ) of l3_irq_in_type;
type irq_out_vector is array (Natural range <> ) of l3_irq_out_type;
component irqmp
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
irqmap : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1)
);
end component;
component irqmp2x
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
clkfact : integer := 2;
irqmap : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
hclken : in std_ulogic
);
end component;
component irqamp
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
nctrl : integer range 1 to 16 := 1;
tstamp : integer range 0 to 16 := 0;
wdogen : integer range 0 to 1 := 0;
nwdog : integer range 1 to 16 := 1;
dynrstaddr : integer range 0 to 1 := 0;
rstaddr : integer range 0 to 16#fffff# := 0;
extrun : integer range 0 to 1 := 0;
irqmap : integer := 0;
exttimer : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
wdog : in std_logic_vector(nwdog-1 downto 0) := (others => '0');
cpurun : in std_logic_vector(ncpu-1 downto 0) := (others => '0');
timer : in std_logic_vector(31 downto 0) := (others => '0')
);
end component;
component irqamp2x
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
nctrl : integer range 1 to 16 := 1;
tstamp : integer range 0 to 16 := 0;
wdogen : integer range 0 to 1 := 0;
nwdog : integer range 1 to 16 := 1;
dynrstaddr : integer range 0 to 1 := 0;
rstaddr : integer range 0 to 16#fffff# := 0;
extrun : integer range 0 to 1 := 0;
clkfact : integer := 2;
irqmap : integer := 0;
exttimer : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
wdog : in std_logic_vector(nwdog-1 downto 0) := (others => '0');
cpurun : in std_logic_vector(ncpu-1 downto 0) := (others => '0');
hclken : in std_ulogic;
timer : in std_logic_vector(31 downto 0) := (others => '0')
);
end component;
component leon3ftsh
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- free-running clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic; -- gated clock
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
component leon3x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
clk2x : integer := 1;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end component;
-- disassembly dummy module
component cpu_disasx
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result : in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end component;
end;
|
gpl-2.0
|
9b09efc6d05e4a2a0c6aa5d8b13bdfb3
| 0.525567 | 3.417383 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/misc/grgpreg.vhd
| 1 | 4,704 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grgpreg
-- File: grgpreg.vhd
-- Author: Kristoffer Glembo - Aeroflex Gaisler
-- Description: General purpose register
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity grgpreg is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
nbits : integer range 1 to 64 := 16;
rstval : integer := 0;
rstval2 : integer := 0;
extrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gprego : out std_logic_vector(nbits-1 downto 0);
resval : in std_logic_vector(nbits-1 downto 0) := (others => '0')
);
end;
architecture rtl of grgpreg is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_GPREG, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type registers is record
reg : std_logic_vector(nbits-1 downto 0);
end record;
signal r, rin : registers;
begin
comb : process(rst, r, apbi, resval)
variable readdata : std_logic_vector(31 downto 0);
variable v : registers;
begin
v := r;
-- read register
readdata := (others => '0');
case apbi.paddr(4 downto 2) is
when "000" =>
if nbits > 32 then
readdata := r.reg(31 downto 0);
else
readdata(nbits-1 downto 0) := r.reg;
end if;
when "001" =>
if nbits > 32 then
readdata(nbits-33 downto 0) := r.reg(nbits-1 downto 32);
end if;
when others =>
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
if nbits > 32 then
v.reg(31 downto 0) := apbi.pwdata;
else
v.reg := apbi.pwdata(nbits-1 downto 0);
end if;
when "001" =>
if nbits > 32 then
v.reg(nbits-1 downto 32) := apbi.pwdata(nbits-33 downto 0);
end if;
when others =>
end case;
end if;
if rst = '0' then
if extrst = 0 then
v.reg := conv_std_logic_vector(rstval, nbits);
if nbits > 32 then
v.reg(nbits-1 downto 32) := conv_std_logic_vector(rstval2, nbits-32);
end if;
else
v.reg := resval;
end if;
end if;
rin <= v;
apbo.prdata <= readdata; -- drive apb read bus
end process;
gprego <= r.reg;
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("grgpreg" & tost(pindex) &
": " & tost(nbits) & "-bit GPREG Unit rev " & tost(REVISION));
-- pragma translate_on
end;
|
gpl-2.0
|
69f2d6a9edb4021ce7bb4ff82fd61b7c
| 0.526361 | 4.055172 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-atlys/vga_clkgen.vhd
| 3 | 2,676 |
------------------------------------------------------------------------------
-- Clock generator for VGA/TMDS video output.
-- Modified by Joris van Rantwijk to support Digilent Atlys board.
--
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2012, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library unisim;
use unisim.vcomponents.BUFGMUX;
use unisim.vcomponents.PLL_BASE;
entity vga_clkgen is
port (
resetn : in std_logic;
clk100 : in std_logic;
sel : in std_logic_vector(1 downto 0);
vgaclk : out std_logic;
fastclk : out std_logic
);
end;
architecture struct of vga_clkgen is
signal s_resetp : std_logic;
signal s_clkfb : std_logic;
signal s_clk25 : std_logic;
signal s_clk40 : std_logic;
signal s_clk125 : std_logic;
signal s_clk200 : std_logic;
begin
s_resetp <= not resetn;
-- Generate VGA pixel clock and 5x fast clock.
vgapll: PLL_BASE
generic map (
CLKFBOUT_MULT => 10,
DIVCLK_DIVIDE => 1,
CLKOUT0_DIVIDE => 40,
CLKOUT1_DIVIDE => 25,
CLKOUT2_DIVIDE => 8,
CLKOUT3_DIVIDE => 5,
CLKIN_PERIOD => 10.0,
CLK_FEEDBACK => "CLKFBOUT" )
port map (
CLKIN => clk100,
CLKFBIN => s_clkfb,
CLKFBOUT => s_clkfb,
CLKOUT0 => s_clk25,
CLKOUT1 => s_clk40,
CLKOUT2 => s_clk125,
CLKOUT3 => s_clk200,
RST => s_resetp );
-- Choose between 25 Mhz and 40 MHz for pixel clock.
bufg0 : BUFGMUX
port map ( I0 => s_clk25, I1 => s_clk40, S => sel(0), O => vgaclk );
-- Choose between 125 MHz and 200 MHz for TMDS output clock.
bufg1 : BUFGMUX
port map ( I0 => s_clk125, I1 => s_clk200, S => sel(0), O => fastclk );
end architecture;
|
gpl-2.0
|
85f614f3ac5c17258b62988d28e562f7
| 0.620703 | 3.670782 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/unisim/mul_unisim.vhd
| 4 | 947,856 |
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity virtex4_mul_61x61 is
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end virtex4_mul_61x61;
architecture beh of virtex4_mul_61x61 is
signal R1IN_3_2_1 : std_logic_vector(33 downto 17);
signal R1IN_3_2 : std_logic_vector(16 downto 0);
signal R1IN_2_2_1 : std_logic_vector(33 downto 17);
signal R1IN_2_2 : std_logic_vector(16 downto 0);
signal R1IN_4_4_2 : std_logic_vector(26 downto 0);
signal R1IN_ADD_1 : std_logic_vector(31 downto 0);
signal R1IN_4 : std_logic_vector(52 downto 17);
signal R1IN_4_3_1 : std_logic_vector(33 downto 17);
signal R1IN_4_3 : std_logic_vector(16 downto 0);
signal R1IN_4_2 : std_logic_vector(16 downto 0);
signal R1IN_4_2_1 : std_logic_vector(33 downto 17);
signal R1IN_4_2F : std_logic_vector(43 downto 1);
signal R1IN_4_3F : std_logic_vector(43 downto 0);
signal R1IN_1FF : std_logic_vector(33 downto 18);
signal R1IN_4FF : std_logic_vector(16 downto 0);
signal R1IN_2_2F : std_logic_vector(43 downto 1);
signal R1IN_4_4_ADD_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_4_4_ADD_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_2_2_ADD_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_2_2_ADD_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_3_2_ADD_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_3_2_ADD_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_4_2_ADD_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_4_2_ADD_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_4_3_ADD_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_4_3_ADD_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_4_4_2_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_2_2_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_3_2_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_4_2_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_4_3_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_2_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_3_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_3_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_4_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_4_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_4_4_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_4_4_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_4_4_4_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_4_4_4_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_4_4_2_0 : std_logic_vector(26 downto 0);
signal R1IN_2_2_0 : std_logic_vector(16 downto 0);
signal R1IN_2_2_1_0 : std_logic_vector(33 downto 17);
signal R1IN_3_2_0 : std_logic_vector(16 downto 0);
signal R1IN_3_2_1_0 : std_logic_vector(33 downto 17);
signal R1IN_4_2_0 : std_logic_vector(16 downto 0);
signal R1IN_4_2_1_0 : std_logic_vector(33 downto 17);
signal R1IN_4_3_0 : std_logic_vector(16 downto 0);
signal R1IN_4_3_1_0 : std_logic_vector(33 downto 17);
signal B_0 : std_logic_vector(16 downto 0);
signal R1IN_4_4 : std_logic_vector(53 downto 17);
signal R1IN_2F_RETO : std_logic_vector(16 downto 0);
signal R1IN_3F : std_logic_vector(16 downto 0);
signal R1IN_3F_RETO : std_logic_vector(16 downto 0);
signal R1IN_2_RETO : std_logic_vector(60 downto 17);
signal R1IN_3_1F_RETO : std_logic_vector(33 downto 17);
signal R1IN_3 : std_logic_vector(60 downto 17);
signal R1IN_4_1F_RETO : std_logic_vector(33 downto 17);
signal R1IN_4_ADD_1_RETO : std_logic_vector(44 downto 1);
signal R1IN_4_4F : std_logic_vector(16 downto 0);
signal R1IN_4_4F_RETO : std_logic_vector(16 downto 0);
signal R1IN_4_4_ADD_1F_RETO : std_logic_vector(27 downto 0);
signal R1IN_3_1F : std_logic_vector(33 downto 17);
signal R1IN_3_1F_RETO_0 : std_logic_vector(17 to 17);
signal R1IN_3_2F : std_logic_vector(43 downto 1);
signal R1IN_3_2F_RETO : std_logic_vector(43 downto 1);
signal R1IN_4_4_ADD_1F : std_logic_vector(27 downto 0);
signal R1IN_4_4_ADD_1F_RETO_0 : std_logic_vector(0 to 0);
signal R1IN_4_4_1F : std_logic_vector(33 downto 18);
signal R1IN_4_4_1F_RETO : std_logic_vector(33 downto 18);
signal R1IN_4_4_4F_RETO : std_logic_vector(19 downto 0);
signal R1IN_4_4_4_P : std_logic_vector(47 downto 20);
signal R1IN_4_1_P : std_logic_vector(47 downto 34);
signal R1IN_2_1F_RETO : std_logic_vector(33 downto 17);
signal R1IN_2_2F_RETO : std_logic_vector(43 downto 1);
signal R1IN_4_3F_RETO : std_logic_vector(43 downto 0);
signal R1IN_4_2F_RETO : std_logic_vector(43 downto 1);
signal R1IN_2_1_P : std_logic_vector(47 downto 34);
signal NN_1 : std_logic ;
signal NN_2 : std_logic ;
signal R1IN_4_ADD_1 : std_logic ;
signal R1IN_ADD_2 : std_logic ;
signal R1IN_2_ADD_1 : std_logic ;
signal UC : std_logic ;
signal UC_0 : std_logic ;
signal UC_1 : std_logic ;
signal UC_2 : std_logic ;
signal UC_3 : std_logic ;
signal UC_4 : std_logic ;
signal UC_5 : std_logic ;
signal UC_6 : std_logic ;
signal UC_7 : std_logic ;
signal UC_8 : std_logic ;
signal UC_9 : std_logic ;
signal UC_10 : std_logic ;
signal UC_11 : std_logic ;
signal UC_12 : std_logic ;
signal UC_13 : std_logic ;
signal UC_14 : std_logic ;
signal UC_15 : std_logic ;
signal UC_16 : std_logic ;
signal UC_17 : std_logic ;
signal UC_18 : std_logic ;
signal UC_19 : std_logic ;
signal UC_20 : std_logic ;
signal UC_21 : std_logic ;
signal UC_22 : std_logic ;
signal UC_23 : std_logic ;
signal UC_24 : std_logic ;
signal UC_25 : std_logic ;
signal UC_26 : std_logic ;
signal UC_27 : std_logic ;
signal UC_28 : std_logic ;
signal UC_29 : std_logic ;
signal UC_30 : std_logic ;
signal UC_31 : std_logic ;
signal UC_32 : std_logic ;
signal UC_33 : std_logic ;
signal UC_34 : std_logic ;
signal UC_35 : std_logic ;
signal UC_36 : std_logic ;
signal UC_37 : std_logic ;
signal UC_38 : std_logic ;
signal UC_39 : std_logic ;
signal UC_40 : std_logic ;
signal UC_41 : std_logic ;
signal UC_42 : std_logic ;
signal UC_43 : std_logic ;
signal UC_44 : std_logic ;
signal UC_45 : std_logic ;
signal UC_46 : std_logic ;
signal UC_47 : std_logic ;
signal UC_48 : std_logic ;
signal UC_49 : std_logic ;
signal UC_50 : std_logic ;
signal UC_51 : std_logic ;
signal UC_52 : std_logic ;
signal UC_53 : std_logic ;
signal UC_54 : std_logic ;
signal UC_55 : std_logic ;
signal UC_56 : std_logic ;
signal UC_57 : std_logic ;
signal UC_58 : std_logic ;
signal UC_59 : std_logic ;
signal UC_60 : std_logic ;
signal UC_61 : std_logic ;
signal UC_62 : std_logic ;
signal UC_63 : std_logic ;
signal UC_64 : std_logic ;
signal UC_65 : std_logic ;
signal UC_66 : std_logic ;
signal UC_67 : std_logic ;
signal UC_68 : std_logic ;
signal UC_69 : std_logic ;
signal UC_70 : std_logic ;
signal UC_71 : std_logic ;
signal UC_72 : std_logic ;
signal UC_73 : std_logic ;
signal UC_74 : std_logic ;
signal UC_75 : std_logic ;
signal UC_76 : std_logic ;
signal UC_77 : std_logic ;
signal UC_78 : std_logic ;
signal UC_79 : std_logic ;
signal UC_80 : std_logic ;
signal UC_81 : std_logic ;
signal UC_82 : std_logic ;
signal UC_83 : std_logic ;
signal UC_84 : std_logic ;
signal UC_85 : std_logic ;
signal UC_86 : std_logic ;
signal UC_87 : std_logic ;
signal UC_88 : std_logic ;
signal UC_89 : std_logic ;
signal UC_90 : std_logic ;
signal UC_91 : std_logic ;
signal UC_92 : std_logic ;
signal UC_93 : std_logic ;
signal UC_94 : std_logic ;
signal UC_95 : std_logic ;
signal UC_96 : std_logic ;
signal UC_97 : std_logic ;
signal UC_98 : std_logic ;
signal UC_99 : std_logic ;
signal UC_100 : std_logic ;
signal UC_101 : std_logic ;
signal UC_102 : std_logic ;
signal UC_103 : std_logic ;
signal UC_104 : std_logic ;
signal UC_105 : std_logic ;
signal UC_106 : std_logic ;
signal UC_107 : std_logic ;
signal UC_108 : std_logic ;
signal UC_109 : std_logic ;
signal UC_110 : std_logic ;
signal UC_111 : std_logic ;
signal UC_112 : std_logic ;
signal UC_113 : std_logic ;
signal UC_114 : std_logic ;
signal UC_115 : std_logic ;
signal UC_116 : std_logic ;
signal UC_117 : std_logic ;
signal UC_118 : std_logic ;
signal UC_119 : std_logic ;
signal UC_120 : std_logic ;
signal UC_121 : std_logic ;
signal UC_122 : std_logic ;
signal UC_123 : std_logic ;
signal UC_124 : std_logic ;
signal UC_125 : std_logic ;
signal UC_126 : std_logic ;
signal UC_127 : std_logic ;
signal UC_128 : std_logic ;
signal UC_129 : std_logic ;
signal UC_130 : std_logic ;
signal UC_131 : std_logic ;
signal UC_132 : std_logic ;
signal UC_133 : std_logic ;
signal UC_134 : std_logic ;
signal UC_135 : std_logic ;
signal UC_136 : std_logic ;
signal UC_137 : std_logic ;
signal UC_138 : std_logic ;
signal UC_139 : std_logic ;
signal UC_140 : std_logic ;
signal UC_141 : std_logic ;
signal UC_142 : std_logic ;
signal UC_143 : std_logic ;
signal UC_144 : std_logic ;
signal UC_145 : std_logic ;
signal UC_146 : std_logic ;
signal UC_147 : std_logic ;
signal UC_148 : std_logic ;
signal UC_149 : std_logic ;
signal UC_150 : std_logic ;
signal UC_151 : std_logic ;
signal UC_152 : std_logic ;
signal UC_153 : std_logic ;
signal UC_154 : std_logic ;
signal UC_155 : std_logic ;
signal UC_156 : std_logic ;
signal UC_157 : std_logic ;
signal UC_158 : std_logic ;
signal UC_159 : std_logic ;
signal UC_160 : std_logic ;
signal UC_161 : std_logic ;
signal UC_162 : std_logic ;
signal UC_163 : std_logic ;
signal UC_164 : std_logic ;
signal UC_165 : std_logic ;
signal UC_166 : std_logic ;
signal UC_167 : std_logic ;
signal UC_168 : std_logic ;
signal UC_169 : std_logic ;
signal UC_170 : std_logic ;
signal UC_171 : std_logic ;
signal UC_172 : std_logic ;
signal UC_173 : std_logic ;
signal UC_174 : std_logic ;
signal UC_175 : std_logic ;
signal UC_176 : std_logic ;
signal UC_177 : std_logic ;
signal UC_178 : std_logic ;
signal UC_179 : std_logic ;
signal UC_180 : std_logic ;
signal UC_181 : std_logic ;
signal UC_182 : std_logic ;
signal UC_183 : std_logic ;
signal UC_184 : std_logic ;
signal UC_185 : std_logic ;
signal UC_186 : std_logic ;
signal UC_187 : std_logic ;
signal UC_188 : std_logic ;
signal UC_189 : std_logic ;
signal UC_190 : std_logic ;
signal UC_191 : std_logic ;
signal UC_192 : std_logic ;
signal UC_193 : std_logic ;
signal UC_208 : std_logic ;
signal UC_209 : std_logic ;
signal UC_210 : std_logic ;
signal UC_211 : std_logic ;
signal UC_212 : std_logic ;
signal UC_213 : std_logic ;
signal UC_214 : std_logic ;
signal UC_215 : std_logic ;
signal UC_216 : std_logic ;
signal UC_217 : std_logic ;
signal UC_218 : std_logic ;
signal UC_219 : std_logic ;
signal UC_220 : std_logic ;
signal UC_221 : std_logic ;
signal UC_236 : std_logic ;
signal UC_237 : std_logic ;
signal UC_238 : std_logic ;
signal UC_239 : std_logic ;
signal UC_240 : std_logic ;
signal UC_241 : std_logic ;
signal UC_242 : std_logic ;
signal UC_243 : std_logic ;
signal UC_244 : std_logic ;
signal UC_245 : std_logic ;
signal UC_246 : std_logic ;
signal UC_247 : std_logic ;
signal UC_248 : std_logic ;
signal UC_249 : std_logic ;
signal UC_103_0 : std_logic ;
signal UC_104_0 : std_logic ;
signal UC_105_0 : std_logic ;
signal UC_106_0 : std_logic ;
signal UC_107_0 : std_logic ;
signal UC_108_0 : std_logic ;
signal UC_109_0 : std_logic ;
signal UC_110_0 : std_logic ;
signal UC_111_0 : std_logic ;
signal UC_112_0 : std_logic ;
signal UC_113_0 : std_logic ;
signal UC_114_0 : std_logic ;
signal UC_115_0 : std_logic ;
signal UC_116_0 : std_logic ;
signal UC_117_0 : std_logic ;
signal UC_118_0 : std_logic ;
signal UC_119_0 : std_logic ;
signal UC_120_0 : std_logic ;
signal UC_121_0 : std_logic ;
signal UC_122_0 : std_logic ;
signal UC_123_0 : std_logic ;
signal UC_124_0 : std_logic ;
signal UC_125_0 : std_logic ;
signal UC_126_0 : std_logic ;
signal UC_127_0 : std_logic ;
signal UC_128_0 : std_logic ;
signal UC_129_0 : std_logic ;
signal UC_130_0 : std_logic ;
signal UC_131_0 : std_logic ;
signal UC_132_0 : std_logic ;
signal UC_133_0 : std_logic ;
signal UC_134_0 : std_logic ;
signal UC_135_0 : std_logic ;
signal UC_136_0 : std_logic ;
signal UC_137_0 : std_logic ;
signal UC_138_0 : std_logic ;
signal UC_139_0 : std_logic ;
signal UC_140_0 : std_logic ;
signal UC_141_0 : std_logic ;
signal UC_142_0 : std_logic ;
signal UC_143_0 : std_logic ;
signal UC_144_0 : std_logic ;
signal UC_145_0 : std_logic ;
signal UC_146_0 : std_logic ;
signal UC_147_0 : std_logic ;
signal UC_148_0 : std_logic ;
signal UC_149_0 : std_logic ;
signal UC_150_0 : std_logic ;
signal UC_151_0 : std_logic ;
signal UC_152_0 : std_logic ;
signal UC_153_0 : std_logic ;
signal UC_154_0 : std_logic ;
signal UC_155_0 : std_logic ;
signal UC_156_0 : std_logic ;
signal UC_157_0 : std_logic ;
signal UC_158_0 : std_logic ;
signal UC_159_0 : std_logic ;
signal UC_160_0 : std_logic ;
signal UC_161_0 : std_logic ;
signal UC_162_0 : std_logic ;
signal UC_163_0 : std_logic ;
signal UC_164_0 : std_logic ;
signal UC_165_0 : std_logic ;
signal UC_166_0 : std_logic ;
signal UC_167_0 : std_logic ;
signal UC_168_0 : std_logic ;
signal UC_169_0 : std_logic ;
signal UC_170_0 : std_logic ;
signal UC_171_0 : std_logic ;
signal UC_172_0 : std_logic ;
signal UC_173_0 : std_logic ;
signal UC_174_0 : std_logic ;
signal UC_175_0 : std_logic ;
signal UC_176_0 : std_logic ;
signal UC_177_0 : std_logic ;
signal UC_178_0 : std_logic ;
signal UC_179_0 : std_logic ;
signal GND_0 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_0 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_1 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_1 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_2 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_2 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_3 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_3 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_4 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_4 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_5 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_5 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_6 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_6 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_7 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_7 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_8 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_8 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_9 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_9 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_10 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_10 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_11 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_11 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_12 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_12 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_13 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_13 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_14 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_14 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_15 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_15 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_16 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_16 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_17 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_17 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_18 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_18 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_19 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_19 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_20 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_20 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_21 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_21 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_22 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_22 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_23 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_23 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_24 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_24 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_25 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_25 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_26 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_26 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_27 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_27 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_28 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_28 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_29 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_29 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_30 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_30 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_31 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_31 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_32 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_32 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_33 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_33 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_34 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_34 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_35 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_0 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_1 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_1 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_2 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_2 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_3 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_3 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_4 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_4 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_5 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_5 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_6 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_6 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_7 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_7 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_8 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_8 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_9 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_9 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_10 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_10 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_11 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_11 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_12 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_12 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_13 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_13 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_14 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_14 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_15 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_15 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_16 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_16 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_17 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_17 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_18 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_18 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_19 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_19 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_20 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_20 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_21 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_21 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_22 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_22 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_23 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_23 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_24 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_24 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_25 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_25 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_26 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_26 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_27 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_27 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_28 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_28 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_29 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_29 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_30 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_30 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_31 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_31 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_32 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_32 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_33 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_33 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_34 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_0 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_1 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_1 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_2 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_2 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_3 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_3 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_4 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_4 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_5 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_5 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_6 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_6 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_7 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_7 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_8 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_8 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_9 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_9 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_10 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_10 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_11 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_11 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_12 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_12 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_13 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_13 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_14 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_14 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_15 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_15 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_16 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_16 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_17 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_17 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_18 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_18 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_19 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_19 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_20 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_20 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_21 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_21 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_22 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_22 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_23 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_23 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_24 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_24 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_25 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_25 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_26 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_26 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_27 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_27 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_28 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_28 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_29 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_29 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_30 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_30 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_31 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_31 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_32 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_32 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_33 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_33 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_34 : std_logic ;
signal R1IN_ADD_1_0_CRY_0 : std_logic ;
signal R1IN_ADD_1_0_AXB_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_1 : std_logic ;
signal R1IN_ADD_1_0_AXB_2 : std_logic ;
signal R1IN_ADD_1_0_CRY_2 : std_logic ;
signal R1IN_ADD_1_0_AXB_3 : std_logic ;
signal R1IN_ADD_1_0_CRY_3 : std_logic ;
signal R1IN_ADD_1_0_AXB_4 : std_logic ;
signal R1IN_ADD_1_0_CRY_4 : std_logic ;
signal R1IN_ADD_1_0_AXB_5 : std_logic ;
signal R1IN_ADD_1_0_CRY_5 : std_logic ;
signal R1IN_ADD_1_0_AXB_6 : std_logic ;
signal R1IN_ADD_1_0_CRY_6 : std_logic ;
signal R1IN_ADD_1_0_AXB_7 : std_logic ;
signal R1IN_ADD_1_0_CRY_7 : std_logic ;
signal R1IN_ADD_1_0_AXB_8 : std_logic ;
signal R1IN_ADD_1_0_CRY_8 : std_logic ;
signal R1IN_ADD_1_0_AXB_9 : std_logic ;
signal R1IN_ADD_1_0_CRY_9 : std_logic ;
signal R1IN_ADD_1_0_AXB_10 : std_logic ;
signal R1IN_ADD_1_0_CRY_10 : std_logic ;
signal R1IN_ADD_1_0_AXB_11 : std_logic ;
signal R1IN_ADD_1_0_CRY_11 : std_logic ;
signal R1IN_ADD_1_0_AXB_12 : std_logic ;
signal R1IN_ADD_1_0_CRY_12 : std_logic ;
signal R1IN_ADD_1_0_AXB_13 : std_logic ;
signal R1IN_ADD_1_0_CRY_13 : std_logic ;
signal R1IN_ADD_1_0_AXB_14 : std_logic ;
signal R1IN_ADD_1_0_CRY_14 : std_logic ;
signal R1IN_ADD_1_0_AXB_15 : std_logic ;
signal R1IN_ADD_1_0_CRY_15 : std_logic ;
signal R1IN_ADD_1_0_AXB_16 : std_logic ;
signal R1IN_ADD_1_0_CRY_16 : std_logic ;
signal R1IN_ADD_1_0_AXB_17 : std_logic ;
signal R1IN_ADD_1_0_CRY_17 : std_logic ;
signal R1IN_ADD_1_0_AXB_18 : std_logic ;
signal R1IN_ADD_1_0_CRY_18 : std_logic ;
signal R1IN_ADD_1_0_AXB_19 : std_logic ;
signal R1IN_ADD_1_0_CRY_19 : std_logic ;
signal R1IN_ADD_1_0_AXB_20 : std_logic ;
signal R1IN_ADD_1_0_CRY_20 : std_logic ;
signal R1IN_ADD_1_0_AXB_21 : std_logic ;
signal R1IN_ADD_1_0_CRY_21 : std_logic ;
signal R1IN_ADD_1_0_AXB_22 : std_logic ;
signal R1IN_ADD_1_0_CRY_22 : std_logic ;
signal R1IN_ADD_1_0_AXB_23 : std_logic ;
signal R1IN_ADD_1_0_CRY_23 : std_logic ;
signal R1IN_ADD_1_0_AXB_24 : std_logic ;
signal R1IN_ADD_1_0_CRY_24 : std_logic ;
signal R1IN_ADD_1_0_AXB_25 : std_logic ;
signal R1IN_ADD_1_0_CRY_25 : std_logic ;
signal R1IN_ADD_1_0_AXB_26 : std_logic ;
signal R1IN_ADD_1_0_CRY_26 : std_logic ;
signal R1IN_ADD_1_0_AXB_27 : std_logic ;
signal R1IN_ADD_1_0_CRY_27 : std_logic ;
signal R1IN_ADD_1_0_AXB_28 : std_logic ;
signal R1IN_ADD_1_0_CRY_28 : std_logic ;
signal R1IN_ADD_1_0_AXB_29 : std_logic ;
signal R1IN_ADD_1_0_CRY_29 : std_logic ;
signal R1IN_ADD_1_0_AXB_30 : std_logic ;
signal R1IN_ADD_1_0_CRY_30 : std_logic ;
signal R1IN_ADD_1_0_AXB_31 : std_logic ;
signal R1IN_ADD_1_1_CRY_0 : std_logic ;
signal R1IN_ADD_1_1_AXB_1 : std_logic ;
signal R1IN_ADD_1_1_CRY_1 : std_logic ;
signal R1IN_ADD_1_1_AXB_2 : std_logic ;
signal R1IN_ADD_1_1_CRY_2 : std_logic ;
signal R1IN_ADD_1_1_AXB_3 : std_logic ;
signal R1IN_ADD_1_1_CRY_3 : std_logic ;
signal R1IN_ADD_1_1_AXB_4 : std_logic ;
signal R1IN_ADD_1_1_CRY_4 : std_logic ;
signal R1IN_ADD_1_1_AXB_5 : std_logic ;
signal R1IN_ADD_1_1_CRY_5 : std_logic ;
signal R1IN_ADD_1_1_AXB_6 : std_logic ;
signal R1IN_ADD_1_1_CRY_6 : std_logic ;
signal R1IN_ADD_1_1_AXB_7 : std_logic ;
signal R1IN_ADD_1_1_CRY_7 : std_logic ;
signal R1IN_ADD_1_1_AXB_8 : std_logic ;
signal R1IN_ADD_1_1_CRY_8 : std_logic ;
signal R1IN_ADD_1_1_AXB_9 : std_logic ;
signal R1IN_ADD_1_1_CRY_9 : std_logic ;
signal R1IN_ADD_1_1_AXB_10 : std_logic ;
signal R1IN_ADD_1_1_CRY_10 : std_logic ;
signal R1IN_ADD_1_1_AXB_11 : std_logic ;
signal R1IN_ADD_1_1_CRY_11 : std_logic ;
signal R1IN_ADD_1_1_AXB_12 : std_logic ;
signal R1IN_ADD_1_1_CRY_12 : std_logic ;
signal R1IN_ADD_1_1_AXB_13 : std_logic ;
signal R1IN_ADD_1_1_CRY_13 : std_logic ;
signal R1IN_ADD_1_1_AXB_14 : std_logic ;
signal R1IN_ADD_1_1_CRY_14 : std_logic ;
signal R1IN_ADD_1_1_AXB_15 : std_logic ;
signal R1IN_ADD_1_1_CRY_15 : std_logic ;
signal R1IN_ADD_1_1_AXB_16 : std_logic ;
signal R1IN_ADD_1_1_CRY_16 : std_logic ;
signal R1IN_ADD_1_1_AXB_17 : std_logic ;
signal R1IN_ADD_1_1_CRY_17 : std_logic ;
signal R1IN_ADD_1_1_AXB_18 : std_logic ;
signal R1IN_ADD_1_1_CRY_18 : std_logic ;
signal R1IN_ADD_1_1_AXB_19 : std_logic ;
signal R1IN_ADD_1_1_CRY_19 : std_logic ;
signal R1IN_ADD_1_1_AXB_20 : std_logic ;
signal R1IN_ADD_1_1_CRY_20 : std_logic ;
signal R1IN_ADD_1_1_AXB_21 : std_logic ;
signal R1IN_ADD_1_1_CRY_21 : std_logic ;
signal R1IN_ADD_1_1_AXB_22 : std_logic ;
signal R1IN_ADD_1_1_CRY_22 : std_logic ;
signal R1IN_ADD_1_1_AXB_23 : std_logic ;
signal R1IN_ADD_1_1_CRY_23 : std_logic ;
signal R1IN_ADD_1_1_AXB_24 : std_logic ;
signal R1IN_ADD_1_1_CRY_24 : std_logic ;
signal R1IN_ADD_1_1_AXB_25 : std_logic ;
signal R1IN_ADD_1_1_CRY_25 : std_logic ;
signal R1IN_ADD_1_1_AXB_26 : std_logic ;
signal R1IN_ADD_1_1_CRY_26 : std_logic ;
signal R1IN_ADD_1_1_AXB_27 : std_logic ;
signal R1IN_ADD_1_1_CRY_27 : std_logic ;
signal R1IN_ADD_1_1_AXB_28 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_0 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_1 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_1 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_2 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_2 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_3 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_3 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_4 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_4 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_5 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_5 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_6 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_6 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_7 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_7 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_8 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_8 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_9 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_9 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_10 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_10 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_11 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_11 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_12 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_12 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_13 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_13 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_14 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_14 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_15 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_15 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_16 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_16 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_17 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_17 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_18 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_18 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_19 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_19 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_20 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_20 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_21 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_21 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_22 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_22 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_23 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_23 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_24 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_24 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_25 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_25 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_26 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_26 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_27 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_27 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_28 : std_logic ;
signal R1IN_3_ADD_1_CRY_0 : std_logic ;
signal R1IN_3_ADD_1_AXB_1 : std_logic ;
signal R1IN_3_ADD_1_CRY_1 : std_logic ;
signal R1IN_3_ADD_1_AXB_2 : std_logic ;
signal R1IN_3_ADD_1_CRY_2 : std_logic ;
signal R1IN_3_ADD_1_AXB_3 : std_logic ;
signal R1IN_3_ADD_1_CRY_3 : std_logic ;
signal R1IN_3_ADD_1_AXB_4 : std_logic ;
signal R1IN_3_ADD_1_CRY_4 : std_logic ;
signal R1IN_3_ADD_1_AXB_5 : std_logic ;
signal R1IN_3_ADD_1_CRY_5 : std_logic ;
signal R1IN_3_ADD_1_AXB_6 : std_logic ;
signal R1IN_3_ADD_1_CRY_6 : std_logic ;
signal R1IN_3_ADD_1_AXB_7 : std_logic ;
signal R1IN_3_ADD_1_CRY_7 : std_logic ;
signal R1IN_3_ADD_1_AXB_8 : std_logic ;
signal R1IN_3_ADD_1_CRY_8 : std_logic ;
signal R1IN_3_ADD_1_AXB_9 : std_logic ;
signal R1IN_3_ADD_1_CRY_9 : std_logic ;
signal R1IN_3_ADD_1_AXB_10 : std_logic ;
signal R1IN_3_ADD_1_CRY_10 : std_logic ;
signal R1IN_3_ADD_1_AXB_11 : std_logic ;
signal R1IN_3_ADD_1_CRY_11 : std_logic ;
signal R1IN_3_ADD_1_AXB_12 : std_logic ;
signal R1IN_3_ADD_1_CRY_12 : std_logic ;
signal R1IN_3_ADD_1_AXB_13 : std_logic ;
signal R1IN_3_ADD_1_CRY_13 : std_logic ;
signal R1IN_3_ADD_1_AXB_14 : std_logic ;
signal R1IN_3_ADD_1_CRY_14 : std_logic ;
signal R1IN_3_ADD_1_AXB_15 : std_logic ;
signal R1IN_3_ADD_1_CRY_15 : std_logic ;
signal R1IN_3_ADD_1_AXB_16 : std_logic ;
signal R1IN_3_ADD_1_CRY_16 : std_logic ;
signal R1IN_3_ADD_1_AXB_17 : std_logic ;
signal R1IN_3_ADD_1_CRY_17 : std_logic ;
signal R1IN_3_ADD_1_AXB_18 : std_logic ;
signal R1IN_3_ADD_1_CRY_18 : std_logic ;
signal R1IN_3_ADD_1_AXB_19 : std_logic ;
signal R1IN_3_ADD_1_CRY_19 : std_logic ;
signal R1IN_3_ADD_1_AXB_20 : std_logic ;
signal R1IN_3_ADD_1_CRY_20 : std_logic ;
signal R1IN_3_ADD_1_AXB_21 : std_logic ;
signal R1IN_3_ADD_1_CRY_21 : std_logic ;
signal R1IN_3_ADD_1_AXB_22 : std_logic ;
signal R1IN_3_ADD_1_CRY_22 : std_logic ;
signal R1IN_3_ADD_1_AXB_23 : std_logic ;
signal R1IN_3_ADD_1_CRY_23 : std_logic ;
signal R1IN_3_ADD_1_AXB_24 : std_logic ;
signal R1IN_3_ADD_1_CRY_24 : std_logic ;
signal R1IN_3_ADD_1_AXB_25 : std_logic ;
signal R1IN_3_ADD_1_CRY_25 : std_logic ;
signal R1IN_3_ADD_1_AXB_26 : std_logic ;
signal R1IN_3_ADD_1_CRY_26 : std_logic ;
signal R1IN_3_ADD_1_AXB_27 : std_logic ;
signal R1IN_3_ADD_1_CRY_27 : std_logic ;
signal R1IN_3_ADD_1_AXB_28 : std_logic ;
signal R1IN_3_ADD_1_CRY_28 : std_logic ;
signal R1IN_3_ADD_1_AXB_29 : std_logic ;
signal R1IN_3_ADD_1_CRY_29 : std_logic ;
signal R1IN_3_ADD_1_AXB_30 : std_logic ;
signal R1IN_3_ADD_1_CRY_30 : std_logic ;
signal R1IN_3_ADD_1_AXB_31 : std_logic ;
signal R1IN_3_ADD_1_CRY_31 : std_logic ;
signal R1IN_3_ADD_1_AXB_32 : std_logic ;
signal R1IN_3_ADD_1_CRY_32 : std_logic ;
signal R1IN_3_ADD_1_AXB_33 : std_logic ;
signal R1IN_3_ADD_1_CRY_33 : std_logic ;
signal R1IN_3_ADD_1_AXB_34 : std_logic ;
signal R1IN_3_ADD_1_CRY_34 : std_logic ;
signal R1IN_3_ADD_1_AXB_35 : std_logic ;
signal R1IN_3_ADD_1_CRY_35 : std_logic ;
signal R1IN_3_ADD_1_AXB_36 : std_logic ;
signal R1IN_3_ADD_1_CRY_36 : std_logic ;
signal R1IN_3_ADD_1_AXB_37 : std_logic ;
signal R1IN_3_ADD_1_CRY_37 : std_logic ;
signal R1IN_3_ADD_1_AXB_38 : std_logic ;
signal R1IN_3_ADD_1_CRY_38 : std_logic ;
signal R1IN_3_ADD_1_AXB_39 : std_logic ;
signal R1IN_3_ADD_1_CRY_39 : std_logic ;
signal R1IN_3_ADD_1_AXB_40 : std_logic ;
signal R1IN_3_ADD_1_CRY_40 : std_logic ;
signal R1IN_3_ADD_1_AXB_41 : std_logic ;
signal R1IN_3_ADD_1_CRY_41 : std_logic ;
signal R1IN_3_ADD_1_AXB_42 : std_logic ;
signal R1IN_3_ADD_1_CRY_42 : std_logic ;
signal R1IN_3_ADD_1_AXB_43 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_0 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_1 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_1 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_2 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_2 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_3 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_3 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_4 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_4 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_5 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_5 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_6 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_6 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_7 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_7 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_8 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_8 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_9 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_9 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_10 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_10 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_11 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_11 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_12 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_12 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_13 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_13 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_14 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_14 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_15 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_15 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_16 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_16 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_17 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_17 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_18 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_18 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_19 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_19 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_20 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_20 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_21 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_21 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_22 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_22 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_23 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_23 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_24 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_24 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_25 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_25 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_26 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_26 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_27 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_27 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_28 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_28 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_29 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_29 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_30 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_30 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_31 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_31 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_32 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_32 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_33 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_33 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_34 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_34 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_35 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_35 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_36 : std_logic ;
signal NN_3 : std_logic ;
signal R1IN_ADD_2_CRY_0 : std_logic ;
signal R1IN_ADD_2_AXB_1 : std_logic ;
signal R1IN_ADD_2_CRY_1 : std_logic ;
signal R1IN_ADD_2_AXB_2 : std_logic ;
signal R1IN_ADD_2_CRY_2 : std_logic ;
signal R1IN_ADD_2_AXB_3 : std_logic ;
signal R1IN_ADD_2_CRY_3 : std_logic ;
signal R1IN_ADD_2_AXB_4 : std_logic ;
signal R1IN_ADD_2_CRY_4 : std_logic ;
signal R1IN_ADD_2_AXB_5 : std_logic ;
signal R1IN_ADD_2_CRY_5 : std_logic ;
signal R1IN_ADD_2_AXB_6 : std_logic ;
signal R1IN_ADD_2_CRY_6 : std_logic ;
signal R1IN_ADD_2_AXB_7 : std_logic ;
signal R1IN_ADD_2_CRY_7 : std_logic ;
signal R1IN_ADD_2_AXB_8 : std_logic ;
signal R1IN_ADD_2_CRY_8 : std_logic ;
signal R1IN_ADD_2_AXB_9 : std_logic ;
signal R1IN_ADD_2_CRY_9 : std_logic ;
signal R1IN_ADD_2_AXB_10 : std_logic ;
signal R1IN_ADD_2_CRY_10 : std_logic ;
signal R1IN_ADD_2_AXB_11 : std_logic ;
signal R1IN_ADD_2_CRY_11 : std_logic ;
signal R1IN_ADD_2_AXB_12 : std_logic ;
signal R1IN_ADD_2_CRY_12 : std_logic ;
signal R1IN_ADD_2_AXB_13 : std_logic ;
signal R1IN_ADD_2_CRY_13 : std_logic ;
signal R1IN_ADD_2_AXB_14 : std_logic ;
signal R1IN_ADD_2_CRY_14 : std_logic ;
signal R1IN_ADD_2_AXB_15 : std_logic ;
signal R1IN_ADD_2_CRY_15 : std_logic ;
signal R1IN_ADD_2_AXB_16 : std_logic ;
signal R1IN_ADD_2_CRY_16 : std_logic ;
signal R1IN_ADD_2_AXB_17 : std_logic ;
signal R1IN_ADD_2_CRY_17 : std_logic ;
signal R1IN_ADD_2_AXB_18 : std_logic ;
signal R1IN_ADD_2_CRY_18 : std_logic ;
signal R1IN_ADD_2_AXB_19 : std_logic ;
signal R1IN_ADD_2_CRY_19 : std_logic ;
signal R1IN_ADD_2_AXB_20 : std_logic ;
signal R1IN_ADD_2_CRY_20 : std_logic ;
signal R1IN_ADD_2_AXB_21 : std_logic ;
signal R1IN_ADD_2_CRY_21 : std_logic ;
signal R1IN_ADD_2_AXB_22 : std_logic ;
signal R1IN_ADD_2_CRY_22 : std_logic ;
signal R1IN_ADD_2_AXB_23 : std_logic ;
signal R1IN_ADD_2_CRY_23 : std_logic ;
signal R1IN_ADD_2_AXB_24 : std_logic ;
signal R1IN_ADD_2_CRY_24 : std_logic ;
signal R1IN_ADD_2_AXB_25 : std_logic ;
signal R1IN_ADD_2_CRY_25 : std_logic ;
signal R1IN_ADD_2_AXB_26 : std_logic ;
signal R1IN_ADD_2_CRY_26 : std_logic ;
signal R1IN_ADD_2_AXB_27 : std_logic ;
signal R1IN_ADD_2_CRY_27 : std_logic ;
signal R1IN_ADD_2_AXB_28 : std_logic ;
signal R1IN_ADD_2_CRY_28 : std_logic ;
signal R1IN_ADD_2_AXB_29 : std_logic ;
signal R1IN_ADD_2_CRY_29 : std_logic ;
signal R1IN_ADD_2_AXB_30 : std_logic ;
signal R1IN_ADD_2_CRY_30 : std_logic ;
signal R1IN_ADD_2_AXB_31 : std_logic ;
signal R1IN_ADD_2_CRY_31 : std_logic ;
signal R1IN_ADD_2_AXB_32 : std_logic ;
signal R1IN_ADD_2_CRY_32 : std_logic ;
signal R1IN_ADD_2_AXB_33 : std_logic ;
signal R1IN_ADD_2_CRY_33 : std_logic ;
signal R1IN_ADD_2_AXB_34 : std_logic ;
signal R1IN_ADD_2_CRY_34 : std_logic ;
signal R1IN_ADD_2_AXB_35 : std_logic ;
signal R1IN_ADD_2_CRY_35 : std_logic ;
signal R1IN_ADD_2_AXB_36 : std_logic ;
signal R1IN_ADD_2_CRY_36 : std_logic ;
signal R1IN_ADD_2_AXB_37 : std_logic ;
signal R1IN_ADD_2_CRY_37 : std_logic ;
signal R1IN_ADD_2_AXB_38 : std_logic ;
signal R1IN_ADD_2_CRY_38 : std_logic ;
signal R1IN_ADD_2_AXB_39 : std_logic ;
signal R1IN_ADD_2_CRY_39 : std_logic ;
signal R1IN_ADD_2_AXB_40 : std_logic ;
signal R1IN_ADD_2_CRY_40 : std_logic ;
signal R1IN_ADD_2_AXB_41 : std_logic ;
signal R1IN_ADD_2_CRY_41 : std_logic ;
signal R1IN_ADD_2_AXB_42 : std_logic ;
signal R1IN_ADD_2_CRY_42 : std_logic ;
signal R1IN_ADD_2_AXB_43 : std_logic ;
signal R1IN_ADD_2_CRY_43 : std_logic ;
signal R1IN_ADD_2_AXB_44 : std_logic ;
signal R1IN_ADD_2_CRY_44 : std_logic ;
signal R1IN_ADD_2_AXB_45 : std_logic ;
signal R1IN_ADD_2_CRY_45 : std_logic ;
signal R1IN_ADD_2_AXB_46 : std_logic ;
signal R1IN_ADD_2_CRY_46 : std_logic ;
signal R1IN_ADD_2_AXB_47 : std_logic ;
signal R1IN_ADD_2_CRY_47 : std_logic ;
signal R1IN_ADD_2_AXB_48 : std_logic ;
signal R1IN_ADD_2_CRY_48 : std_logic ;
signal R1IN_ADD_2_AXB_49 : std_logic ;
signal R1IN_ADD_2_CRY_49 : std_logic ;
signal R1IN_ADD_2_AXB_50 : std_logic ;
signal R1IN_ADD_2_CRY_50 : std_logic ;
signal R1IN_ADD_2_AXB_51 : std_logic ;
signal R1IN_ADD_2_CRY_51 : std_logic ;
signal R1IN_ADD_2_AXB_52 : std_logic ;
signal R1IN_ADD_2_CRY_52 : std_logic ;
signal R1IN_ADD_2_AXB_53 : std_logic ;
signal R1IN_ADD_2_CRY_53 : std_logic ;
signal R1IN_ADD_2_AXB_54 : std_logic ;
signal R1IN_ADD_2_CRY_54 : std_logic ;
signal R1IN_ADD_2_AXB_55 : std_logic ;
signal R1IN_ADD_2_CRY_55 : std_logic ;
signal R1IN_ADD_2_AXB_56 : std_logic ;
signal R1IN_ADD_2_CRY_56 : std_logic ;
signal R1IN_ADD_2_AXB_57 : std_logic ;
signal R1IN_ADD_2_CRY_57 : std_logic ;
signal R1IN_ADD_2_AXB_58 : std_logic ;
signal R1IN_ADD_2_CRY_58 : std_logic ;
signal R1IN_ADD_2_AXB_59 : std_logic ;
signal R1IN_ADD_2_CRY_59 : std_logic ;
signal R1IN_ADD_2_AXB_60 : std_logic ;
signal R1IN_ADD_2_CRY_60 : std_logic ;
signal R1IN_ADD_2_AXB_61 : std_logic ;
signal R1IN_ADD_2_CRY_61 : std_logic ;
signal R1IN_ADD_2_AXB_62 : std_logic ;
signal R1IN_ADD_2_CRY_62 : std_logic ;
signal R1IN_ADD_2_AXB_63 : std_logic ;
signal R1IN_ADD_2_CRY_63 : std_logic ;
signal R1IN_ADD_2_AXB_64 : std_logic ;
signal R1IN_ADD_2_CRY_64 : std_logic ;
signal R1IN_ADD_2_AXB_65 : std_logic ;
signal R1IN_ADD_2_CRY_65 : std_logic ;
signal R1IN_ADD_2_AXB_66 : std_logic ;
signal R1IN_ADD_2_CRY_66 : std_logic ;
signal R1IN_ADD_2_AXB_67 : std_logic ;
signal R1IN_ADD_2_CRY_67 : std_logic ;
signal R1IN_ADD_2_AXB_68 : std_logic ;
signal R1IN_ADD_2_CRY_68 : std_logic ;
signal R1IN_ADD_2_AXB_69 : std_logic ;
signal R1IN_ADD_2_CRY_69 : std_logic ;
signal R1IN_ADD_2_AXB_70 : std_logic ;
signal R1IN_ADD_2_CRY_70 : std_logic ;
signal R1IN_ADD_2_AXB_71 : std_logic ;
signal R1IN_ADD_2_CRY_71 : std_logic ;
signal R1IN_ADD_2_AXB_72 : std_logic ;
signal R1IN_ADD_2_CRY_72 : std_logic ;
signal R1IN_ADD_2_AXB_73 : std_logic ;
signal R1IN_ADD_2_CRY_73 : std_logic ;
signal R1IN_ADD_2_AXB_74 : std_logic ;
signal R1IN_ADD_2_CRY_74 : std_logic ;
signal R1IN_ADD_2_AXB_75 : std_logic ;
signal R1IN_ADD_2_CRY_75 : std_logic ;
signal R1IN_ADD_2_AXB_76 : std_logic ;
signal R1IN_ADD_2_CRY_76 : std_logic ;
signal R1IN_ADD_2_AXB_77 : std_logic ;
signal R1IN_ADD_2_CRY_77 : std_logic ;
signal R1IN_ADD_2_AXB_78 : std_logic ;
signal R1IN_ADD_2_CRY_78 : std_logic ;
signal R1IN_ADD_2_AXB_79 : std_logic ;
signal R1IN_ADD_2_CRY_79 : std_logic ;
signal R1IN_ADD_2_AXB_80 : std_logic ;
signal R1IN_ADD_2_CRY_80 : std_logic ;
signal R1IN_ADD_2_AXB_81 : std_logic ;
signal R1IN_ADD_2_CRY_81 : std_logic ;
signal R1IN_ADD_2_AXB_82 : std_logic ;
signal R1IN_ADD_2_CRY_82 : std_logic ;
signal R1IN_ADD_2_AXB_83 : std_logic ;
signal R1IN_ADD_2_CRY_83 : std_logic ;
signal R1IN_ADD_2_AXB_84 : std_logic ;
signal R1IN_ADD_2_CRY_84 : std_logic ;
signal R1IN_ADD_2_AXB_85 : std_logic ;
signal R1IN_ADD_2_CRY_85 : std_logic ;
signal R1IN_ADD_2_AXB_86 : std_logic ;
signal R1IN_ADD_2_CRY_86 : std_logic ;
signal R1IN_ADD_2_AXB_87 : std_logic ;
signal R1IN_ADD_2_CRY_87 : std_logic ;
signal R1IN_ADD_2_AXB_88 : std_logic ;
signal R1IN_ADD_2_CRY_88 : std_logic ;
signal R1IN_ADD_2_AXB_89 : std_logic ;
signal R1IN_ADD_2_CRY_89 : std_logic ;
signal R1IN_ADD_2_AXB_90 : std_logic ;
signal R1IN_ADD_2_CRY_90 : std_logic ;
signal R1IN_ADD_2_AXB_91 : std_logic ;
signal R1IN_ADD_2_CRY_91 : std_logic ;
signal R1IN_ADD_2_AXB_92 : std_logic ;
signal R1IN_ADD_2_CRY_92 : std_logic ;
signal R1IN_ADD_2_AXB_93 : std_logic ;
signal R1IN_ADD_2_CRY_93 : std_logic ;
signal R1IN_ADD_2_AXB_94 : std_logic ;
signal R1IN_ADD_2_CRY_94 : std_logic ;
signal R1IN_ADD_2_AXB_95 : std_logic ;
signal R1IN_ADD_2_CRY_95 : std_logic ;
signal R1IN_ADD_2_AXB_96 : std_logic ;
signal R1IN_ADD_2_CRY_96 : std_logic ;
signal R1IN_ADD_2_AXB_97 : std_logic ;
signal R1IN_ADD_2_CRY_97 : std_logic ;
signal R1IN_ADD_2_AXB_98 : std_logic ;
signal R1IN_ADD_2_CRY_98 : std_logic ;
signal R1IN_ADD_2_AXB_99 : std_logic ;
signal R1IN_ADD_2_CRY_99 : std_logic ;
signal R1IN_ADD_2_AXB_100 : std_logic ;
signal R1IN_ADD_2_CRY_100 : std_logic ;
signal R1IN_ADD_2_AXB_101 : std_logic ;
signal R1IN_ADD_2_CRY_101 : std_logic ;
signal R1IN_ADD_2_AXB_102 : std_logic ;
signal R1IN_ADD_2_CRY_102 : std_logic ;
signal R1IN_ADD_2_AXB_103 : std_logic ;
signal R1IN_ADD_2_CRY_103 : std_logic ;
signal R1IN_ADD_2_AXB_104 : std_logic ;
signal N_1433 : std_logic ;
signal N_1592 : std_logic ;
signal N_4634 : std_logic ;
signal N_1431 : std_logic ;
signal N_1591 : std_logic ;
signal N_4635 : std_logic ;
signal N_1429 : std_logic ;
signal N_1590 : std_logic ;
signal N_4636 : std_logic ;
signal N_1427 : std_logic ;
signal N_1589 : std_logic ;
signal N_4637 : std_logic ;
signal N_1425 : std_logic ;
signal N_1588 : std_logic ;
signal N_4638 : std_logic ;
signal N_1423 : std_logic ;
signal N_1587 : std_logic ;
signal N_4639 : std_logic ;
signal N_1421 : std_logic ;
signal N_1586 : std_logic ;
signal N_4640 : std_logic ;
signal N_1419 : std_logic ;
signal N_1585 : std_logic ;
signal N_4641 : std_logic ;
signal N_1511 : std_logic ;
signal N_1556 : std_logic ;
signal N_4642 : std_logic ;
signal N_1417 : std_logic ;
signal N_1584 : std_logic ;
signal N_4643 : std_logic ;
signal N_1509 : std_logic ;
signal N_1555 : std_logic ;
signal N_4644 : std_logic ;
signal N_1415 : std_logic ;
signal N_1583 : std_logic ;
signal N_4645 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_28 : std_logic ;
signal R1IN_ADD_1_1_CRY_28 : std_logic ;
signal N_4646 : std_logic ;
signal N_1507 : std_logic ;
signal N_1554 : std_logic ;
signal N_4647 : std_logic ;
signal N_1413 : std_logic ;
signal N_1582 : std_logic ;
signal N_4648 : std_logic ;
signal N_1505 : std_logic ;
signal N_1553 : std_logic ;
signal N_4649 : std_logic ;
signal N_1411 : std_logic ;
signal N_1581 : std_logic ;
signal N_4650 : std_logic ;
signal N_1503 : std_logic ;
signal N_1552 : std_logic ;
signal N_4651 : std_logic ;
signal N_1409 : std_logic ;
signal N_1580 : std_logic ;
signal N_4652 : std_logic ;
signal N_1501 : std_logic ;
signal N_1551 : std_logic ;
signal N_4653 : std_logic ;
signal N_1407 : std_logic ;
signal N_1579 : std_logic ;
signal N_4654 : std_logic ;
signal N_1499 : std_logic ;
signal N_1550 : std_logic ;
signal N_4655 : std_logic ;
signal N_1405 : std_logic ;
signal N_1578 : std_logic ;
signal N_4656 : std_logic ;
signal N_1497 : std_logic ;
signal N_1549 : std_logic ;
signal N_4657 : std_logic ;
signal N_1403 : std_logic ;
signal N_1577 : std_logic ;
signal N_4658 : std_logic ;
signal N_1495 : std_logic ;
signal N_1548 : std_logic ;
signal N_4659 : std_logic ;
signal N_1401 : std_logic ;
signal N_1576 : std_logic ;
signal N_4660 : std_logic ;
signal N_1493 : std_logic ;
signal N_1547 : std_logic ;
signal N_4661 : std_logic ;
signal N_1399 : std_logic ;
signal N_1575 : std_logic ;
signal N_4662 : std_logic ;
signal N_1491 : std_logic ;
signal N_1546 : std_logic ;
signal N_4663 : std_logic ;
signal N_1397 : std_logic ;
signal N_1574 : std_logic ;
signal N_4664 : std_logic ;
signal N_1489 : std_logic ;
signal N_1545 : std_logic ;
signal N_4665 : std_logic ;
signal N_1395 : std_logic ;
signal N_1573 : std_logic ;
signal N_4666 : std_logic ;
signal N_1487 : std_logic ;
signal N_1544 : std_logic ;
signal N_4667 : std_logic ;
signal N_1393 : std_logic ;
signal N_1572 : std_logic ;
signal N_4668 : std_logic ;
signal N_1485 : std_logic ;
signal N_1543 : std_logic ;
signal N_4669 : std_logic ;
signal N_1391 : std_logic ;
signal N_1571 : std_logic ;
signal N_4670 : std_logic ;
signal N_1483 : std_logic ;
signal N_1542 : std_logic ;
signal N_4671 : std_logic ;
signal N_1389 : std_logic ;
signal N_1570 : std_logic ;
signal N_4672 : std_logic ;
signal N_1481 : std_logic ;
signal N_1541 : std_logic ;
signal N_4673 : std_logic ;
signal N_1387 : std_logic ;
signal N_1569 : std_logic ;
signal N_4674 : std_logic ;
signal N_1479 : std_logic ;
signal N_1540 : std_logic ;
signal N_4675 : std_logic ;
signal N_1385 : std_logic ;
signal N_1568 : std_logic ;
signal N_4676 : std_logic ;
signal N_1477 : std_logic ;
signal N_1539 : std_logic ;
signal N_4677 : std_logic ;
signal N_1383 : std_logic ;
signal N_1567 : std_logic ;
signal N_4678 : std_logic ;
signal N_1475 : std_logic ;
signal N_1538 : std_logic ;
signal N_4679 : std_logic ;
signal N_1381 : std_logic ;
signal N_1566 : std_logic ;
signal N_4680 : std_logic ;
signal N_1473 : std_logic ;
signal N_1537 : std_logic ;
signal N_4681 : std_logic ;
signal N_1379 : std_logic ;
signal N_1565 : std_logic ;
signal N_4682 : std_logic ;
signal N_1471 : std_logic ;
signal N_1536 : std_logic ;
signal N_4683 : std_logic ;
signal N_1469 : std_logic ;
signal N_1535 : std_logic ;
signal N_4684 : std_logic ;
signal N_1467 : std_logic ;
signal N_1534 : std_logic ;
signal N_4685 : std_logic ;
signal N_1465 : std_logic ;
signal N_1533 : std_logic ;
signal N_4686 : std_logic ;
signal N_1463 : std_logic ;
signal N_1532 : std_logic ;
signal N_4687 : std_logic ;
signal N_1461 : std_logic ;
signal N_1531 : std_logic ;
signal N_4688 : std_logic ;
signal N_1459 : std_logic ;
signal N_1530 : std_logic ;
signal N_4689 : std_logic ;
signal R1IN_ADD_1_0_CRY_31 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_0 : std_logic ;
signal R1IN_ADD_1_1_AXB_0 : std_logic ;
signal N_4690 : std_logic ;
signal N_1457 : std_logic ;
signal N_1529 : std_logic ;
signal N_4691 : std_logic ;
signal N_1455 : std_logic ;
signal N_1528 : std_logic ;
signal N_4692 : std_logic ;
signal N_1453 : std_logic ;
signal N_1527 : std_logic ;
signal N_4693 : std_logic ;
signal N_1451 : std_logic ;
signal N_1526 : std_logic ;
signal N_4694 : std_logic ;
signal N_1449 : std_logic ;
signal N_1525 : std_logic ;
signal N_4695 : std_logic ;
signal N_1447 : std_logic ;
signal N_1524 : std_logic ;
signal N_4696 : std_logic ;
signal N_1445 : std_logic ;
signal N_1523 : std_logic ;
signal N_4697 : std_logic ;
signal N_4698 : std_logic ;
signal N_4699 : std_logic ;
signal N_4700 : std_logic ;
signal N_4701 : std_logic ;
signal N_4702 : std_logic ;
signal N_4703 : std_logic ;
signal N_4704 : std_logic ;
signal N_4705 : std_logic ;
signal N_4706 : std_logic ;
signal N_4707 : std_logic ;
signal N_4708 : std_logic ;
signal N_4709 : std_logic ;
signal N_4710 : std_logic ;
signal N_4711 : std_logic ;
signal N_4712 : std_logic ;
signal N_4713 : std_logic ;
signal N_4714 : std_logic ;
signal N_4715 : std_logic ;
signal N_4716 : std_logic ;
signal N_4717 : std_logic ;
signal N_4718 : std_logic ;
signal N_4719 : std_logic ;
signal N_4720 : std_logic ;
signal N_4721 : std_logic ;
signal N_4722 : std_logic ;
signal N_4723 : std_logic ;
signal N_4724 : std_logic ;
signal N_4725 : std_logic ;
signal N_4726 : std_logic ;
signal N_4727 : std_logic ;
signal N_4728 : std_logic ;
signal N_4729 : std_logic ;
signal N_4730 : std_logic ;
signal N_4731 : std_logic ;
signal N_4732 : std_logic ;
signal N_4733 : std_logic ;
signal N_4734 : std_logic ;
signal N_4735 : std_logic ;
signal N_4736 : std_logic ;
signal N_4737 : std_logic ;
signal N_4738 : std_logic ;
signal N_4739 : std_logic ;
signal N_4740 : std_logic ;
signal N_4741 : std_logic ;
signal N_4742 : std_logic ;
signal N_4743 : std_logic ;
signal N_4744 : std_logic ;
signal N_4745 : std_logic ;
signal N_4746 : std_logic ;
signal N_4747 : std_logic ;
signal N_4748 : std_logic ;
signal N_4749 : std_logic ;
signal N_4750 : std_logic ;
signal N_4751 : std_logic ;
signal N_4752 : std_logic ;
signal N_4753 : std_logic ;
signal N_4754 : std_logic ;
signal N_4755 : std_logic ;
signal N_4756 : std_logic ;
signal N_4757 : std_logic ;
signal N_4758 : std_logic ;
signal R1IN_3_ADD_1_RETO : std_logic ;
signal N_4759 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_0 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_0 : std_logic ;
signal N_4760 : std_logic ;
signal N_4761 : std_logic ;
signal N_4762 : std_logic ;
signal N_4763 : std_logic ;
signal N_4764 : std_logic ;
signal N_4765 : std_logic ;
signal N_4766 : std_logic ;
signal N_4767 : std_logic ;
signal N_4768 : std_logic ;
signal N_4769 : std_logic ;
signal N_4770 : std_logic ;
signal N_4771 : std_logic ;
signal N_4772 : std_logic ;
signal N_4773 : std_logic ;
signal N_4774 : std_logic ;
signal N_4775 : std_logic ;
signal N_4776 : std_logic ;
signal N_4777 : std_logic ;
signal N_4778 : std_logic ;
signal N_4779 : std_logic ;
signal N_4780 : std_logic ;
signal N_4781 : std_logic ;
signal N_4782 : std_logic ;
signal N_4783 : std_logic ;
signal N_4784 : std_logic ;
signal N_4785 : std_logic ;
signal N_4786 : std_logic ;
signal N_4787 : std_logic ;
signal N_4788 : std_logic ;
signal N_4789 : std_logic ;
signal N_4790 : std_logic ;
signal N_4791 : std_logic ;
signal N_4792 : std_logic ;
signal N_4793 : std_logic ;
signal N_4794 : std_logic ;
signal N_4795 : std_logic ;
signal N_4796 : std_logic ;
signal N_4797 : std_logic ;
signal N_4798 : std_logic ;
signal N_4799 : std_logic ;
signal N_4800 : std_logic ;
signal N_4801 : std_logic ;
signal N_4802 : std_logic ;
signal N_4803 : std_logic ;
signal N_4804 : std_logic ;
signal N_4805 : std_logic ;
signal N_4806 : std_logic ;
signal N_4807 : std_logic ;
signal N_4808 : std_logic ;
signal N_4809 : std_logic ;
signal N_4810 : std_logic ;
signal N_4811 : std_logic ;
signal N_4812 : std_logic ;
signal N_4813 : std_logic ;
signal N_4814 : std_logic ;
signal N_4815 : std_logic ;
signal N_4816 : std_logic ;
signal N_4817 : std_logic ;
signal N_4818 : std_logic ;
signal N_4819 : std_logic ;
signal N_4820 : std_logic ;
signal N_4821 : std_logic ;
signal N_4822 : std_logic ;
signal N_4823 : std_logic ;
signal N_4824 : std_logic ;
signal N_4825 : std_logic ;
signal N_4826 : std_logic ;
signal N_4827 : std_logic ;
signal N_4828 : std_logic ;
signal N_4829 : std_logic ;
signal N_4830 : std_logic ;
signal R1IN_4_ADD_2_0_RETO : std_logic ;
signal R1IN_4_4_ADD_2_RETO : std_logic ;
signal N_4831 : std_logic ;
signal N_4880 : std_logic ;
signal N_4881 : std_logic ;
signal N_4882 : std_logic ;
signal N_4883 : std_logic ;
signal N_4884 : std_logic ;
signal N_4885 : std_logic ;
signal N_4886 : std_logic ;
signal N_4887 : std_logic ;
signal N_4888 : std_logic ;
signal N_4889 : std_logic ;
signal N_4890 : std_logic ;
signal N_4891 : std_logic ;
signal N_4892 : std_logic ;
signal N_4893 : std_logic ;
signal N_4894 : std_logic ;
signal N_4895 : std_logic ;
signal N_4896 : std_logic ;
signal N_4897 : std_logic ;
signal N_4898 : std_logic ;
signal N_4899 : std_logic ;
signal N_4900 : std_logic ;
signal N_4901 : std_logic ;
signal N_4902 : std_logic ;
signal N_4903 : std_logic ;
signal N_4904 : std_logic ;
signal N_4905 : std_logic ;
signal N_4906 : std_logic ;
signal N_4907 : std_logic ;
signal N_4908 : std_logic ;
signal N_4909 : std_logic ;
signal N_4910 : std_logic ;
signal N_4911 : std_logic ;
signal N_4912 : std_logic ;
signal N_4913 : std_logic ;
signal N_4914 : std_logic ;
signal N_4915 : std_logic ;
signal N_4916 : std_logic ;
signal N_4917 : std_logic ;
signal N_4918 : std_logic ;
signal N_4919 : std_logic ;
signal N_4920 : std_logic ;
signal N_4921 : std_logic ;
signal N_4922 : std_logic ;
signal N_4923 : std_logic ;
signal N_4924 : std_logic ;
signal N_4925 : std_logic ;
signal N_4926 : std_logic ;
signal N_4927 : std_logic ;
signal N_4928 : std_logic ;
signal N_4929 : std_logic ;
signal N_4930 : std_logic ;
signal N_4931 : std_logic ;
signal N_4932 : std_logic ;
signal N_4933 : std_logic ;
signal N_4934 : std_logic ;
signal N_4935 : std_logic ;
signal N_4936 : std_logic ;
signal N_4937 : std_logic ;
signal N_4938 : std_logic ;
signal N_4939 : std_logic ;
signal N_4940 : std_logic ;
signal N_4941 : std_logic ;
signal N_4942 : std_logic ;
signal N_4943 : std_logic ;
signal N_4944 : std_logic ;
signal N_4945 : std_logic ;
signal N_4946 : std_logic ;
signal N_4947 : std_logic ;
signal N_4948 : std_logic ;
signal N_4949 : std_logic ;
signal N_4950 : std_logic ;
signal N_4951 : std_logic ;
signal N_4952 : std_logic ;
signal N_4953 : std_logic ;
signal N_4954 : std_logic ;
signal N_4955 : std_logic ;
signal N_4956 : std_logic ;
signal N_4957 : std_logic ;
signal N_4958 : std_logic ;
signal N_4959 : std_logic ;
signal N_4960 : std_logic ;
signal N_4961 : std_logic ;
signal N_4962 : std_logic ;
signal N_4963 : std_logic ;
signal N_4964 : std_logic ;
signal N_4965 : std_logic ;
signal N_4966 : std_logic ;
signal N_4967 : std_logic ;
signal N_4968 : std_logic ;
signal N_4969 : std_logic ;
signal N_4970 : std_logic ;
signal N_4971 : std_logic ;
signal N_4972 : std_logic ;
signal N_4973 : std_logic ;
signal N_4974 : std_logic ;
signal N_4975 : std_logic ;
signal N_4976 : std_logic ;
signal N_4977 : std_logic ;
signal N_4978 : std_logic ;
signal N_4979 : std_logic ;
signal N_4980 : std_logic ;
signal N_4981 : std_logic ;
signal N_4982 : std_logic ;
signal N_4983 : std_logic ;
signal N_4984 : std_logic ;
signal N_4985 : std_logic ;
signal N_4986 : std_logic ;
signal N_4987 : std_logic ;
signal N_4988 : std_logic ;
signal N_4989 : std_logic ;
signal N_4990 : std_logic ;
signal N_4991 : std_logic ;
signal N_4992 : std_logic ;
signal N_4993 : std_logic ;
signal N_4994 : std_logic ;
signal N_4995 : std_logic ;
signal N_4996 : std_logic ;
signal N_4997 : std_logic ;
signal N_4998 : std_logic ;
signal N_4999 : std_logic ;
signal N_5000 : std_logic ;
signal N_5001 : std_logic ;
signal N_5002 : std_logic ;
signal N_5003 : std_logic ;
signal N_5004 : std_logic ;
signal N_5005 : std_logic ;
signal N_5006 : std_logic ;
signal N_5007 : std_logic ;
signal N_5008 : std_logic ;
signal R1IN_4_ADD_2_1_RETO : std_logic ;
signal N_5009 : std_logic ;
signal N_5010 : std_logic ;
signal N_5011 : std_logic ;
signal N_5012 : std_logic ;
signal N_5013 : std_logic ;
signal N_5014 : std_logic ;
signal N_5015 : std_logic ;
signal N_5016 : std_logic ;
signal N_5017 : std_logic ;
signal N_5018 : std_logic ;
signal N_5019 : std_logic ;
signal N_5020 : std_logic ;
signal N_5021 : std_logic ;
signal N_5022 : std_logic ;
signal N_5023 : std_logic ;
signal N_5024 : std_logic ;
signal N_5025 : std_logic ;
signal N_5026 : std_logic ;
signal N_5027 : std_logic ;
signal N_5028 : std_logic ;
signal N_5029 : std_logic ;
signal N_5030 : std_logic ;
signal N_5031 : std_logic ;
signal N_5032 : std_logic ;
signal N_5033 : std_logic ;
signal N_5034 : std_logic ;
signal N_5035 : std_logic ;
signal N_5036 : std_logic ;
signal N_5037 : std_logic ;
signal N_5038 : std_logic ;
signal N_5039 : std_logic ;
signal N_5040 : std_logic ;
signal N_5041 : std_logic ;
signal N_5042 : std_logic ;
signal N_5043 : std_logic ;
signal N_5044 : std_logic ;
signal N_5045 : std_logic ;
signal N_5046 : std_logic ;
signal N_5047 : std_logic ;
signal N_5048 : std_logic ;
signal N_5049 : std_logic ;
signal N_5050 : std_logic ;
signal N_5051 : std_logic ;
signal N_5052 : std_logic ;
signal N_5053 : std_logic ;
signal N_5054 : std_logic ;
signal N_5055 : std_logic ;
signal N_5056 : std_logic ;
signal N_5057 : std_logic ;
signal N_5058 : std_logic ;
signal N_5059 : std_logic ;
signal N_5060 : std_logic ;
signal N_5061 : std_logic ;
signal N_5062 : std_logic ;
signal N_5063 : std_logic ;
signal N_5064 : std_logic ;
signal N_5065 : std_logic ;
signal N_5066 : std_logic ;
signal N_5067 : std_logic ;
signal N_5068 : std_logic ;
signal N_5069 : std_logic ;
signal N_5070 : std_logic ;
signal N_5071 : std_logic ;
signal N_5072 : std_logic ;
signal N_5073 : std_logic ;
signal N_5074 : std_logic ;
signal N_5075 : std_logic ;
signal N_5076 : std_logic ;
signal N_5077 : std_logic ;
signal N_5078 : std_logic ;
signal N_5079 : std_logic ;
signal N_5080 : std_logic ;
signal N_5081 : std_logic ;
signal R1IN_3_ADD_1 : std_logic ;
signal R1IN_3_ADD_1_RETO_0 : std_logic ;
signal N_5082 : std_logic ;
signal N_5083 : std_logic ;
signal N_5084 : std_logic ;
signal N_5085 : std_logic ;
signal N_5086 : std_logic ;
signal N_5087 : std_logic ;
signal N_5088 : std_logic ;
signal N_5089 : std_logic ;
signal N_5090 : std_logic ;
signal N_5091 : std_logic ;
signal N_5092 : std_logic ;
signal N_5093 : std_logic ;
signal N_5094 : std_logic ;
signal N_5095 : std_logic ;
signal N_5096 : std_logic ;
signal N_5097 : std_logic ;
signal N_5098 : std_logic ;
signal N_5099 : std_logic ;
signal N_5100 : std_logic ;
signal N_5101 : std_logic ;
signal N_5102 : std_logic ;
signal N_5103 : std_logic ;
signal N_5104 : std_logic ;
signal N_5105 : std_logic ;
signal N_5106 : std_logic ;
signal N_5107 : std_logic ;
signal N_5108 : std_logic ;
signal N_5109 : std_logic ;
signal N_5110 : std_logic ;
signal N_5111 : std_logic ;
signal N_5112 : std_logic ;
signal N_5113 : std_logic ;
signal N_5114 : std_logic ;
signal N_5115 : std_logic ;
signal N_5116 : std_logic ;
signal N_5117 : std_logic ;
signal N_5118 : std_logic ;
signal N_5119 : std_logic ;
signal N_5120 : std_logic ;
signal N_5121 : std_logic ;
signal N_5122 : std_logic ;
signal N_5123 : std_logic ;
signal N_5124 : std_logic ;
signal N_5125 : std_logic ;
signal N_5126 : std_logic ;
signal N_5127 : std_logic ;
signal N_5128 : std_logic ;
signal N_5129 : std_logic ;
signal N_5130 : std_logic ;
signal N_5131 : std_logic ;
signal N_5132 : std_logic ;
signal N_5133 : std_logic ;
signal N_5134 : std_logic ;
signal N_5135 : std_logic ;
signal N_5136 : std_logic ;
signal N_5137 : std_logic ;
signal N_5138 : std_logic ;
signal N_5139 : std_logic ;
signal N_5140 : std_logic ;
signal N_5141 : std_logic ;
signal N_5142 : std_logic ;
signal N_5143 : std_logic ;
signal N_5144 : std_logic ;
signal N_5145 : std_logic ;
signal N_5146 : std_logic ;
signal N_5147 : std_logic ;
signal N_5148 : std_logic ;
signal N_5149 : std_logic ;
signal N_5150 : std_logic ;
signal N_5151 : std_logic ;
signal N_5152 : std_logic ;
signal R1IN_4_4_ADD_2 : std_logic ;
signal R1IN_4_4_ADD_2_RETO_0 : std_logic ;
signal N_5153 : std_logic ;
signal R1IN_2_ADD_1_AXB_1 : std_logic ;
signal R1IN_2_ADD_1_CRY_0 : std_logic ;
signal R1IN_2_ADD_1_AXB_2 : std_logic ;
signal R1IN_2_ADD_1_CRY_1 : std_logic ;
signal R1IN_2_ADD_1_AXB_3 : std_logic ;
signal R1IN_2_ADD_1_CRY_2 : std_logic ;
signal R1IN_2_ADD_1_AXB_4 : std_logic ;
signal R1IN_2_ADD_1_CRY_3 : std_logic ;
signal R1IN_2_ADD_1_AXB_5 : std_logic ;
signal R1IN_2_ADD_1_CRY_4 : std_logic ;
signal R1IN_2_ADD_1_AXB_6 : std_logic ;
signal R1IN_2_ADD_1_CRY_5 : std_logic ;
signal R1IN_2_ADD_1_AXB_7 : std_logic ;
signal R1IN_2_ADD_1_CRY_6 : std_logic ;
signal R1IN_2_ADD_1_AXB_8 : std_logic ;
signal R1IN_2_ADD_1_CRY_7 : std_logic ;
signal R1IN_2_ADD_1_AXB_9 : std_logic ;
signal R1IN_2_ADD_1_CRY_8 : std_logic ;
signal R1IN_2_ADD_1_AXB_10 : std_logic ;
signal R1IN_2_ADD_1_CRY_9 : std_logic ;
signal R1IN_2_ADD_1_AXB_11 : std_logic ;
signal R1IN_2_ADD_1_CRY_10 : std_logic ;
signal R1IN_2_ADD_1_AXB_12 : std_logic ;
signal R1IN_2_ADD_1_CRY_11 : std_logic ;
signal R1IN_2_ADD_1_AXB_13 : std_logic ;
signal R1IN_2_ADD_1_CRY_12 : std_logic ;
signal R1IN_2_ADD_1_AXB_14 : std_logic ;
signal R1IN_2_ADD_1_CRY_13 : std_logic ;
signal R1IN_2_ADD_1_AXB_15 : std_logic ;
signal R1IN_2_ADD_1_CRY_14 : std_logic ;
signal R1IN_2_ADD_1_AXB_16 : std_logic ;
signal R1IN_2_ADD_1_CRY_15 : std_logic ;
signal R1IN_2_ADD_1_AXB_17 : std_logic ;
signal R1IN_2_ADD_1_CRY_16 : std_logic ;
signal R1IN_2_ADD_1_AXB_18 : std_logic ;
signal R1IN_2_ADD_1_CRY_17 : std_logic ;
signal R1IN_2_ADD_1_AXB_19 : std_logic ;
signal R1IN_2_ADD_1_CRY_18 : std_logic ;
signal R1IN_2_ADD_1_AXB_20 : std_logic ;
signal R1IN_2_ADD_1_CRY_19 : std_logic ;
signal R1IN_2_ADD_1_AXB_21 : std_logic ;
signal R1IN_2_ADD_1_CRY_20 : std_logic ;
signal R1IN_2_ADD_1_AXB_22 : std_logic ;
signal R1IN_2_ADD_1_CRY_21 : std_logic ;
signal R1IN_2_ADD_1_AXB_23 : std_logic ;
signal R1IN_2_ADD_1_CRY_22 : std_logic ;
signal R1IN_2_ADD_1_AXB_24 : std_logic ;
signal R1IN_2_ADD_1_CRY_23 : std_logic ;
signal R1IN_2_ADD_1_AXB_25 : std_logic ;
signal R1IN_2_ADD_1_CRY_24 : std_logic ;
signal R1IN_2_ADD_1_AXB_26 : std_logic ;
signal R1IN_2_ADD_1_CRY_25 : std_logic ;
signal R1IN_2_ADD_1_AXB_27 : std_logic ;
signal R1IN_2_ADD_1_CRY_26 : std_logic ;
signal R1IN_2_ADD_1_AXB_28 : std_logic ;
signal R1IN_2_ADD_1_CRY_27 : std_logic ;
signal R1IN_2_ADD_1_AXB_29 : std_logic ;
signal R1IN_2_ADD_1_CRY_28 : std_logic ;
signal R1IN_2_ADD_1_AXB_30 : std_logic ;
signal R1IN_2_ADD_1_CRY_29 : std_logic ;
signal R1IN_2_ADD_1_AXB_31 : std_logic ;
signal R1IN_2_ADD_1_CRY_30 : std_logic ;
signal R1IN_2_ADD_1_AXB_32 : std_logic ;
signal R1IN_2_ADD_1_CRY_31 : std_logic ;
signal R1IN_2_ADD_1_AXB_33 : std_logic ;
signal R1IN_2_ADD_1_CRY_32 : std_logic ;
signal R1IN_2_ADD_1_AXB_34 : std_logic ;
signal R1IN_2_ADD_1_CRY_33 : std_logic ;
signal R1IN_2_ADD_1_AXB_35 : std_logic ;
signal R1IN_2_ADD_1_CRY_34 : std_logic ;
signal R1IN_2_ADD_1_AXB_36 : std_logic ;
signal R1IN_2_ADD_1_CRY_35 : std_logic ;
signal R1IN_2_ADD_1_AXB_37 : std_logic ;
signal R1IN_2_ADD_1_CRY_36 : std_logic ;
signal R1IN_2_ADD_1_AXB_38 : std_logic ;
signal R1IN_2_ADD_1_CRY_37 : std_logic ;
signal R1IN_2_ADD_1_AXB_39 : std_logic ;
signal R1IN_2_ADD_1_CRY_38 : std_logic ;
signal R1IN_2_ADD_1_AXB_40 : std_logic ;
signal R1IN_2_ADD_1_CRY_39 : std_logic ;
signal R1IN_2_ADD_1_AXB_41 : std_logic ;
signal R1IN_2_ADD_1_CRY_40 : std_logic ;
signal R1IN_2_ADD_1_AXB_42 : std_logic ;
signal R1IN_2_ADD_1_CRY_41 : std_logic ;
signal R1IN_2_ADD_1_CRY_42 : std_logic ;
signal R1IN_2_ADD_1_AXB_43 : std_logic ;
signal N_1 : std_logic ;
signal N_2 : std_logic ;
signal N_3 : std_logic ;
signal N_4 : std_logic ;
signal N_5 : std_logic ;
signal N_6 : std_logic ;
signal N_7 : std_logic ;
signal N_8 : std_logic ;
signal N_9 : std_logic ;
signal N_10 : std_logic ;
signal N_11 : std_logic ;
signal N_12 : std_logic ;
signal N_13 : std_logic ;
signal N_14 : std_logic ;
signal N_15 : std_logic ;
signal N_16 : std_logic ;
signal N_17 : std_logic ;
signal N_18 : std_logic ;
signal N_19 : std_logic ;
signal N_20 : std_logic ;
signal N_21 : std_logic ;
signal N_22 : std_logic ;
signal N_23 : std_logic ;
signal N_24 : std_logic ;
signal N_25 : std_logic ;
signal N_26 : std_logic ;
signal N_27 : std_logic ;
signal N_28 : std_logic ;
signal N_29 : std_logic ;
signal N_30 : std_logic ;
signal N_31 : std_logic ;
signal N_32 : std_logic ;
signal N_33 : std_logic ;
signal N_34 : std_logic ;
signal N_35 : std_logic ;
signal N_36 : std_logic ;
signal N_37 : std_logic ;
signal N_38 : std_logic ;
signal N_39 : std_logic ;
signal N_40 : std_logic ;
signal N_41 : std_logic ;
signal N_42 : std_logic ;
signal N_43 : std_logic ;
signal N_44 : std_logic ;
signal N_45 : std_logic ;
signal N_46 : std_logic ;
signal N_47 : std_logic ;
signal N_48 : std_logic ;
signal N_49 : std_logic ;
signal N_50 : std_logic ;
signal N_51 : std_logic ;
signal N_52 : std_logic ;
signal N_53 : std_logic ;
signal N_54 : std_logic ;
signal N_55 : std_logic ;
signal N_56 : std_logic ;
signal N_57 : std_logic ;
signal N_58 : std_logic ;
signal N_59 : std_logic ;
signal N_60 : std_logic ;
signal N_61 : std_logic ;
signal N_62 : std_logic ;
signal N_63 : std_logic ;
signal N_64 : std_logic ;
signal N_65 : std_logic ;
signal N_66 : std_logic ;
signal N_67 : std_logic ;
signal N_68 : std_logic ;
signal N_69 : std_logic ;
signal N_70 : std_logic ;
signal N_71 : std_logic ;
signal N_72 : std_logic ;
signal R1IN_2_ADD_1_RETO : std_logic ;
signal N_73 : std_logic ;
signal R1IN_4_ADD_1_AXB_1 : std_logic ;
signal R1IN_4_ADD_1_CRY_0 : std_logic ;
signal R1IN_4_ADD_1_AXB_2 : std_logic ;
signal R1IN_4_ADD_1_CRY_1 : std_logic ;
signal R1IN_4_ADD_1_AXB_3 : std_logic ;
signal R1IN_4_ADD_1_CRY_2 : std_logic ;
signal R1IN_4_ADD_1_AXB_4 : std_logic ;
signal R1IN_4_ADD_1_CRY_3 : std_logic ;
signal R1IN_4_ADD_1_AXB_5 : std_logic ;
signal R1IN_4_ADD_1_CRY_4 : std_logic ;
signal R1IN_4_ADD_1_AXB_6 : std_logic ;
signal R1IN_4_ADD_1_CRY_5 : std_logic ;
signal R1IN_4_ADD_1_AXB_7 : std_logic ;
signal R1IN_4_ADD_1_CRY_6 : std_logic ;
signal R1IN_4_ADD_1_AXB_8 : std_logic ;
signal R1IN_4_ADD_1_CRY_7 : std_logic ;
signal R1IN_4_ADD_1_AXB_9 : std_logic ;
signal R1IN_4_ADD_1_CRY_8 : std_logic ;
signal R1IN_4_ADD_1_AXB_10 : std_logic ;
signal R1IN_4_ADD_1_CRY_9 : std_logic ;
signal R1IN_4_ADD_1_AXB_11 : std_logic ;
signal R1IN_4_ADD_1_CRY_10 : std_logic ;
signal R1IN_4_ADD_1_AXB_12 : std_logic ;
signal R1IN_4_ADD_1_CRY_11 : std_logic ;
signal R1IN_4_ADD_1_AXB_13 : std_logic ;
signal R1IN_4_ADD_1_CRY_12 : std_logic ;
signal R1IN_4_ADD_1_AXB_14 : std_logic ;
signal R1IN_4_ADD_1_CRY_13 : std_logic ;
signal R1IN_4_ADD_1_AXB_15 : std_logic ;
signal R1IN_4_ADD_1_CRY_14 : std_logic ;
signal R1IN_4_ADD_1_AXB_16 : std_logic ;
signal R1IN_4_ADD_1_CRY_15 : std_logic ;
signal R1IN_4_ADD_1_AXB_17 : std_logic ;
signal R1IN_4_ADD_1_CRY_16 : std_logic ;
signal R1IN_4_ADD_1_AXB_18 : std_logic ;
signal R1IN_4_ADD_1_CRY_17 : std_logic ;
signal R1IN_4_ADD_1_AXB_19 : std_logic ;
signal R1IN_4_ADD_1_CRY_18 : std_logic ;
signal R1IN_4_ADD_1_AXB_20 : std_logic ;
signal R1IN_4_ADD_1_CRY_19 : std_logic ;
signal R1IN_4_ADD_1_AXB_21 : std_logic ;
signal R1IN_4_ADD_1_CRY_20 : std_logic ;
signal R1IN_4_ADD_1_AXB_22 : std_logic ;
signal R1IN_4_ADD_1_CRY_21 : std_logic ;
signal R1IN_4_ADD_1_AXB_23 : std_logic ;
signal R1IN_4_ADD_1_CRY_22 : std_logic ;
signal R1IN_4_ADD_1_AXB_24 : std_logic ;
signal R1IN_4_ADD_1_CRY_23 : std_logic ;
signal R1IN_4_ADD_1_AXB_25 : std_logic ;
signal R1IN_4_ADD_1_CRY_24 : std_logic ;
signal R1IN_4_ADD_1_AXB_26 : std_logic ;
signal R1IN_4_ADD_1_CRY_25 : std_logic ;
signal R1IN_4_ADD_1_AXB_27 : std_logic ;
signal R1IN_4_ADD_1_CRY_26 : std_logic ;
signal R1IN_4_ADD_1_AXB_28 : std_logic ;
signal R1IN_4_ADD_1_CRY_27 : std_logic ;
signal R1IN_4_ADD_1_AXB_29 : std_logic ;
signal R1IN_4_ADD_1_CRY_28 : std_logic ;
signal R1IN_4_ADD_1_AXB_30 : std_logic ;
signal R1IN_4_ADD_1_CRY_29 : std_logic ;
signal R1IN_4_ADD_1_AXB_31 : std_logic ;
signal R1IN_4_ADD_1_CRY_30 : std_logic ;
signal R1IN_4_ADD_1_AXB_32 : std_logic ;
signal R1IN_4_ADD_1_CRY_31 : std_logic ;
signal R1IN_4_ADD_1_AXB_33 : std_logic ;
signal R1IN_4_ADD_1_CRY_32 : std_logic ;
signal R1IN_4_ADD_1_AXB_34 : std_logic ;
signal R1IN_4_ADD_1_CRY_33 : std_logic ;
signal R1IN_4_ADD_1_AXB_35 : std_logic ;
signal R1IN_4_ADD_1_CRY_34 : std_logic ;
signal R1IN_4_ADD_1_AXB_36 : std_logic ;
signal R1IN_4_ADD_1_CRY_35 : std_logic ;
signal R1IN_4_ADD_1_AXB_37 : std_logic ;
signal R1IN_4_ADD_1_CRY_36 : std_logic ;
signal R1IN_4_ADD_1_AXB_38 : std_logic ;
signal R1IN_4_ADD_1_CRY_37 : std_logic ;
signal R1IN_4_ADD_1_AXB_39 : std_logic ;
signal R1IN_4_ADD_1_CRY_38 : std_logic ;
signal R1IN_4_ADD_1_AXB_40 : std_logic ;
signal R1IN_4_ADD_1_CRY_39 : std_logic ;
signal R1IN_4_ADD_1_AXB_41 : std_logic ;
signal R1IN_4_ADD_1_CRY_40 : std_logic ;
signal R1IN_4_ADD_1_AXB_42 : std_logic ;
signal R1IN_4_ADD_1_CRY_41 : std_logic ;
signal R1IN_4_ADD_1_CRY_42 : std_logic ;
signal R1IN_4_ADD_1_AXB_43 : std_logic ;
signal N_1_0 : std_logic ;
signal N_2_0 : std_logic ;
signal N_3_0 : std_logic ;
signal N_4_0 : std_logic ;
signal N_5_0 : std_logic ;
signal N_6_0 : std_logic ;
signal N_7_0 : std_logic ;
signal N_8_0 : std_logic ;
signal N_9_0 : std_logic ;
signal N_10_0 : std_logic ;
signal N_11_0 : std_logic ;
signal N_12_0 : std_logic ;
signal N_13_0 : std_logic ;
signal N_14_0 : std_logic ;
signal N_15_0 : std_logic ;
signal N_16_0 : std_logic ;
signal N_17_0 : std_logic ;
signal N_18_0 : std_logic ;
signal N_19_0 : std_logic ;
signal N_20_0 : std_logic ;
signal N_21_0 : std_logic ;
signal N_22_0 : std_logic ;
signal N_23_0 : std_logic ;
signal N_24_0 : std_logic ;
signal N_25_0 : std_logic ;
signal N_26_0 : std_logic ;
signal N_27_0 : std_logic ;
signal N_28_0 : std_logic ;
signal N_29_0 : std_logic ;
signal N_30_0 : std_logic ;
signal N_31_0 : std_logic ;
signal N_32_0 : std_logic ;
signal N_33_0 : std_logic ;
signal N_34_0 : std_logic ;
signal N_35_0 : std_logic ;
signal N_36_0 : std_logic ;
signal N_37_0 : std_logic ;
signal N_38_0 : std_logic ;
signal N_39_0 : std_logic ;
signal N_40_0 : std_logic ;
signal N_41_0 : std_logic ;
signal N_42_0 : std_logic ;
signal N_43_0 : std_logic ;
signal N_44_0 : std_logic ;
signal N_45_0 : std_logic ;
signal N_46_0 : std_logic ;
signal N_47_0 : std_logic ;
signal N_48_0 : std_logic ;
signal N_49_0 : std_logic ;
signal N_50_0 : std_logic ;
signal N_51_0 : std_logic ;
signal N_52_0 : std_logic ;
signal N_53_0 : std_logic ;
signal NN_4 : std_logic ;
signal N_54_0 : std_logic ;
begin
R1IN_4_ADD_2_1_AXB_1_Z4370: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(20),
I1 => R1IN_4_ADD_1_RETO(37),
O => R1IN_4_ADD_2_1_AXB_1);
R1IN_4_ADD_2_1_AXB_2_Z4371: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(21),
I1 => R1IN_4_ADD_1_RETO(38),
O => R1IN_4_ADD_2_1_AXB_2);
R1IN_4_ADD_2_1_AXB_3_Z4372: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(22),
I1 => R1IN_4_ADD_1_RETO(39),
O => R1IN_4_ADD_2_1_AXB_3);
R1IN_4_ADD_2_1_AXB_4_Z4373: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(23),
I1 => R1IN_4_ADD_1_RETO(40),
O => R1IN_4_ADD_2_1_AXB_4);
R1IN_4_ADD_2_1_AXB_5_Z4374: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(24),
I1 => R1IN_4_ADD_1_RETO(41),
O => R1IN_4_ADD_2_1_AXB_5);
R1IN_4_ADD_2_1_AXB_6_Z4375: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(25),
I1 => R1IN_4_ADD_1_RETO(42),
O => R1IN_4_ADD_2_1_AXB_6);
R1IN_4_ADD_2_1_AXB_7_Z4376: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(26),
I1 => R1IN_4_ADD_1_RETO(43),
O => R1IN_4_ADD_2_1_AXB_7);
R1IN_4_ADD_2_1_AXB_8_Z4377: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(27),
I1 => R1IN_4_ADD_1_RETO(44),
O => R1IN_4_ADD_2_1_AXB_8);
R1IN_4_ADD_2_1_AXB_9_Z4378: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(28),
O => R1IN_4_ADD_2_1_AXB_9);
R1IN_4_ADD_2_1_AXB_10_Z4379: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(29),
O => R1IN_4_ADD_2_1_AXB_10);
R1IN_4_ADD_2_1_AXB_11_Z4380: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(30),
O => R1IN_4_ADD_2_1_AXB_11);
R1IN_4_ADD_2_1_AXB_12_Z4381: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(31),
O => R1IN_4_ADD_2_1_AXB_12);
R1IN_4_ADD_2_1_AXB_13_Z4382: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(32),
O => R1IN_4_ADD_2_1_AXB_13);
R1IN_4_ADD_2_1_AXB_14_Z4383: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(33),
O => R1IN_4_ADD_2_1_AXB_14);
R1IN_4_ADD_2_1_AXB_15_Z4384: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(34),
O => R1IN_4_ADD_2_1_AXB_15);
R1IN_4_ADD_2_1_AXB_16_Z4385: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(35),
O => R1IN_4_ADD_2_1_AXB_16);
R1IN_4_ADD_2_1_AXB_17_Z4386: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(36),
O => R1IN_4_ADD_2_1_AXB_17);
R1IN_4_ADD_2_1_AXB_18_Z4387: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(37),
O => R1IN_4_ADD_2_1_AXB_18);
R1IN_4_ADD_2_1_AXB_19_Z4388: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(38),
O => R1IN_4_ADD_2_1_AXB_19);
R1IN_4_ADD_2_1_AXB_20_Z4389: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(39),
O => R1IN_4_ADD_2_1_AXB_20);
R1IN_4_ADD_2_1_AXB_21_Z4390: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(40),
O => R1IN_4_ADD_2_1_AXB_21);
R1IN_4_ADD_2_1_AXB_22_Z4391: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(41),
O => R1IN_4_ADD_2_1_AXB_22);
R1IN_4_ADD_2_1_AXB_23_Z4392: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(42),
O => R1IN_4_ADD_2_1_AXB_23);
R1IN_4_ADD_2_1_AXB_24_Z4393: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(43),
O => R1IN_4_ADD_2_1_AXB_24);
R1IN_4_ADD_2_1_AXB_25_Z4394: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(44),
O => R1IN_4_ADD_2_1_AXB_25);
R1IN_4_ADD_2_1_AXB_26_Z4395: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(45),
O => R1IN_4_ADD_2_1_AXB_26);
R1IN_4_ADD_2_1_AXB_27_Z4396: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(46),
O => R1IN_4_ADD_2_1_AXB_27);
R1IN_4_ADD_2_1_AXB_28_Z4397: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(47),
O => R1IN_4_ADD_2_1_AXB_28);
R1IN_4_ADD_2_1_AXB_29_Z4398: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(48),
O => R1IN_4_ADD_2_1_AXB_29);
R1IN_4_ADD_2_1_AXB_30_Z4399: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(49),
O => R1IN_4_ADD_2_1_AXB_30);
R1IN_4_ADD_2_1_AXB_31_Z4400: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(50),
O => R1IN_4_ADD_2_1_AXB_31);
R1IN_4_ADD_2_1_AXB_32_Z4401: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(51),
O => R1IN_4_ADD_2_1_AXB_32);
R1IN_4_ADD_2_1_AXB_33_Z4402: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(52),
O => R1IN_4_ADD_2_1_AXB_33);
R1IN_4_ADD_2_1_0_AXB_1_Z4403: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(20),
I1 => R1IN_4_ADD_1_RETO(37),
O => R1IN_4_ADD_2_1_0_AXB_1);
R1IN_4_ADD_2_1_0_AXB_2_Z4404: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(21),
I1 => R1IN_4_ADD_1_RETO(38),
O => R1IN_4_ADD_2_1_0_AXB_2);
R1IN_4_ADD_2_1_0_AXB_3_Z4405: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(22),
I1 => R1IN_4_ADD_1_RETO(39),
O => R1IN_4_ADD_2_1_0_AXB_3);
R1IN_4_ADD_2_1_0_AXB_4_Z4406: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(23),
I1 => R1IN_4_ADD_1_RETO(40),
O => R1IN_4_ADD_2_1_0_AXB_4);
R1IN_4_ADD_2_1_0_AXB_5_Z4407: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(24),
I1 => R1IN_4_ADD_1_RETO(41),
O => R1IN_4_ADD_2_1_0_AXB_5);
R1IN_4_ADD_2_1_0_AXB_6_Z4408: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(25),
I1 => R1IN_4_ADD_1_RETO(42),
O => R1IN_4_ADD_2_1_0_AXB_6);
R1IN_4_ADD_2_1_0_AXB_7_Z4409: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(26),
I1 => R1IN_4_ADD_1_RETO(43),
O => R1IN_4_ADD_2_1_0_AXB_7);
R1IN_4_ADD_2_1_0_AXB_8_Z4410: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(27),
I1 => R1IN_4_ADD_1_RETO(44),
O => R1IN_4_ADD_2_1_0_AXB_8);
R1IN_4_ADD_2_1_0_AXB_9_Z4411: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(28),
O => R1IN_4_ADD_2_1_0_AXB_9);
R1IN_4_ADD_2_1_0_AXB_10_Z4412: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(29),
O => R1IN_4_ADD_2_1_0_AXB_10);
R1IN_4_ADD_2_1_0_AXB_11_Z4413: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(30),
O => R1IN_4_ADD_2_1_0_AXB_11);
R1IN_4_ADD_2_1_0_AXB_12_Z4414: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(31),
O => R1IN_4_ADD_2_1_0_AXB_12);
R1IN_4_ADD_2_1_0_AXB_13_Z4415: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(32),
O => R1IN_4_ADD_2_1_0_AXB_13);
R1IN_4_ADD_2_1_0_AXB_14_Z4416: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(33),
O => R1IN_4_ADD_2_1_0_AXB_14);
R1IN_4_ADD_2_1_0_AXB_15_Z4417: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(34),
O => R1IN_4_ADD_2_1_0_AXB_15);
R1IN_4_ADD_2_1_0_AXB_16_Z4418: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(35),
O => R1IN_4_ADD_2_1_0_AXB_16);
R1IN_4_ADD_2_1_0_AXB_17_Z4419: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(36),
O => R1IN_4_ADD_2_1_0_AXB_17);
R1IN_4_ADD_2_1_0_AXB_18_Z4420: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(37),
O => R1IN_4_ADD_2_1_0_AXB_18);
R1IN_4_ADD_2_1_0_AXB_19_Z4421: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(38),
O => R1IN_4_ADD_2_1_0_AXB_19);
R1IN_4_ADD_2_1_0_AXB_20_Z4422: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(39),
O => R1IN_4_ADD_2_1_0_AXB_20);
R1IN_4_ADD_2_1_0_AXB_21_Z4423: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(40),
O => R1IN_4_ADD_2_1_0_AXB_21);
R1IN_4_ADD_2_1_0_AXB_22_Z4424: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(41),
O => R1IN_4_ADD_2_1_0_AXB_22);
R1IN_4_ADD_2_1_0_AXB_23_Z4425: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(42),
O => R1IN_4_ADD_2_1_0_AXB_23);
R1IN_4_ADD_2_1_0_AXB_24_Z4426: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(43),
O => R1IN_4_ADD_2_1_0_AXB_24);
R1IN_4_ADD_2_1_0_AXB_25_Z4427: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(44),
O => R1IN_4_ADD_2_1_0_AXB_25);
R1IN_4_ADD_2_1_0_AXB_26_Z4428: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(45),
O => R1IN_4_ADD_2_1_0_AXB_26);
R1IN_4_ADD_2_1_0_AXB_27_Z4429: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(46),
O => R1IN_4_ADD_2_1_0_AXB_27);
R1IN_4_ADD_2_1_0_AXB_28_Z4430: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(47),
O => R1IN_4_ADD_2_1_0_AXB_28);
R1IN_4_ADD_2_1_0_AXB_29_Z4431: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(48),
O => R1IN_4_ADD_2_1_0_AXB_29);
R1IN_4_ADD_2_1_0_AXB_30_Z4432: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(49),
O => R1IN_4_ADD_2_1_0_AXB_30);
R1IN_4_ADD_2_1_0_AXB_31_Z4433: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(50),
O => R1IN_4_ADD_2_1_0_AXB_31);
R1IN_4_ADD_2_1_0_AXB_32_Z4434: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(51),
O => R1IN_4_ADD_2_1_0_AXB_32);
R1IN_4_ADD_2_1_0_AXB_33_Z4435: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(52),
O => R1IN_4_ADD_2_1_0_AXB_33);
R1IN_ADD_1_1_AXB_1_Z4436: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(33),
I1 => R1IN_3(33),
O => R1IN_ADD_1_1_AXB_1);
R1IN_ADD_1_1_AXB_2_Z4437: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(34),
I1 => R1IN_3(34),
O => R1IN_ADD_1_1_AXB_2);
R1IN_ADD_1_1_AXB_3_Z4438: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(35),
I1 => R1IN_3(35),
O => R1IN_ADD_1_1_AXB_3);
R1IN_ADD_1_1_AXB_4_Z4439: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(36),
I1 => R1IN_3(36),
O => R1IN_ADD_1_1_AXB_4);
R1IN_ADD_1_1_AXB_5_Z4440: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(37),
I1 => R1IN_3(37),
O => R1IN_ADD_1_1_AXB_5);
R1IN_ADD_1_1_AXB_6_Z4441: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(38),
I1 => R1IN_3(38),
O => R1IN_ADD_1_1_AXB_6);
R1IN_ADD_1_1_AXB_7_Z4442: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(39),
I1 => R1IN_3(39),
O => R1IN_ADD_1_1_AXB_7);
R1IN_ADD_1_1_AXB_8_Z4443: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(40),
I1 => R1IN_3(40),
O => R1IN_ADD_1_1_AXB_8);
R1IN_ADD_1_1_AXB_9_Z4444: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(41),
I1 => R1IN_3(41),
O => R1IN_ADD_1_1_AXB_9);
R1IN_ADD_1_1_AXB_10_Z4445: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(42),
I1 => R1IN_3(42),
O => R1IN_ADD_1_1_AXB_10);
R1IN_ADD_1_1_AXB_11_Z4446: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(43),
I1 => R1IN_3(43),
O => R1IN_ADD_1_1_AXB_11);
R1IN_ADD_1_1_AXB_12_Z4447: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(44),
I1 => R1IN_3(44),
O => R1IN_ADD_1_1_AXB_12);
R1IN_ADD_1_1_AXB_13_Z4448: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(45),
I1 => R1IN_3(45),
O => R1IN_ADD_1_1_AXB_13);
R1IN_ADD_1_1_AXB_14_Z4449: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(46),
I1 => R1IN_3(46),
O => R1IN_ADD_1_1_AXB_14);
R1IN_ADD_1_1_AXB_15_Z4450: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(47),
I1 => R1IN_3(47),
O => R1IN_ADD_1_1_AXB_15);
R1IN_ADD_1_1_AXB_16_Z4451: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(48),
I1 => R1IN_3(48),
O => R1IN_ADD_1_1_AXB_16);
R1IN_ADD_1_1_AXB_17_Z4452: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(49),
I1 => R1IN_3(49),
O => R1IN_ADD_1_1_AXB_17);
R1IN_ADD_1_1_AXB_18_Z4453: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(50),
I1 => R1IN_3(50),
O => R1IN_ADD_1_1_AXB_18);
R1IN_ADD_1_1_AXB_19_Z4454: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(51),
I1 => R1IN_3(51),
O => R1IN_ADD_1_1_AXB_19);
R1IN_ADD_1_1_AXB_20_Z4455: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(52),
I1 => R1IN_3(52),
O => R1IN_ADD_1_1_AXB_20);
R1IN_ADD_1_1_AXB_21_Z4456: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(53),
I1 => R1IN_3(53),
O => R1IN_ADD_1_1_AXB_21);
R1IN_ADD_1_1_AXB_22_Z4457: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(54),
I1 => R1IN_3(54),
O => R1IN_ADD_1_1_AXB_22);
R1IN_ADD_1_1_AXB_23_Z4458: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(55),
I1 => R1IN_3(55),
O => R1IN_ADD_1_1_AXB_23);
R1IN_ADD_1_1_AXB_24_Z4459: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(56),
I1 => R1IN_3(56),
O => R1IN_ADD_1_1_AXB_24);
R1IN_ADD_1_1_AXB_25_Z4460: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(57),
I1 => R1IN_3(57),
O => R1IN_ADD_1_1_AXB_25);
R1IN_ADD_1_1_AXB_26_Z4461: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(58),
I1 => R1IN_3(58),
O => R1IN_ADD_1_1_AXB_26);
R1IN_ADD_1_1_AXB_27_Z4462: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(59),
I1 => R1IN_3(59),
O => R1IN_ADD_1_1_AXB_27);
R1IN_ADD_1_1_0_AXB_1_Z4463: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(33),
I1 => R1IN_3(33),
O => R1IN_ADD_1_1_0_AXB_1);
R1IN_ADD_1_1_0_AXB_2_Z4464: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(34),
I1 => R1IN_3(34),
O => R1IN_ADD_1_1_0_AXB_2);
R1IN_ADD_1_1_0_AXB_3_Z4465: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(35),
I1 => R1IN_3(35),
O => R1IN_ADD_1_1_0_AXB_3);
R1IN_ADD_1_1_0_AXB_4_Z4466: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(36),
I1 => R1IN_3(36),
O => R1IN_ADD_1_1_0_AXB_4);
R1IN_ADD_1_1_0_AXB_5_Z4467: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(37),
I1 => R1IN_3(37),
O => R1IN_ADD_1_1_0_AXB_5);
R1IN_ADD_1_1_0_AXB_6_Z4468: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(38),
I1 => R1IN_3(38),
O => R1IN_ADD_1_1_0_AXB_6);
R1IN_ADD_1_1_0_AXB_7_Z4469: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(39),
I1 => R1IN_3(39),
O => R1IN_ADD_1_1_0_AXB_7);
R1IN_ADD_1_1_0_AXB_8_Z4470: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(40),
I1 => R1IN_3(40),
O => R1IN_ADD_1_1_0_AXB_8);
R1IN_ADD_1_1_0_AXB_9_Z4471: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(41),
I1 => R1IN_3(41),
O => R1IN_ADD_1_1_0_AXB_9);
R1IN_ADD_1_1_0_AXB_10_Z4472: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(42),
I1 => R1IN_3(42),
O => R1IN_ADD_1_1_0_AXB_10);
R1IN_ADD_1_1_0_AXB_11_Z4473: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(43),
I1 => R1IN_3(43),
O => R1IN_ADD_1_1_0_AXB_11);
R1IN_ADD_1_1_0_AXB_12_Z4474: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(44),
I1 => R1IN_3(44),
O => R1IN_ADD_1_1_0_AXB_12);
R1IN_ADD_1_1_0_AXB_13_Z4475: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(45),
I1 => R1IN_3(45),
O => R1IN_ADD_1_1_0_AXB_13);
R1IN_ADD_1_1_0_AXB_14_Z4476: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(46),
I1 => R1IN_3(46),
O => R1IN_ADD_1_1_0_AXB_14);
R1IN_ADD_1_1_0_AXB_15_Z4477: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(47),
I1 => R1IN_3(47),
O => R1IN_ADD_1_1_0_AXB_15);
R1IN_ADD_1_1_0_AXB_16_Z4478: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(48),
I1 => R1IN_3(48),
O => R1IN_ADD_1_1_0_AXB_16);
R1IN_ADD_1_1_0_AXB_17_Z4479: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(49),
I1 => R1IN_3(49),
O => R1IN_ADD_1_1_0_AXB_17);
R1IN_ADD_1_1_0_AXB_18_Z4480: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(50),
I1 => R1IN_3(50),
O => R1IN_ADD_1_1_0_AXB_18);
R1IN_ADD_1_1_0_AXB_19_Z4481: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(51),
I1 => R1IN_3(51),
O => R1IN_ADD_1_1_0_AXB_19);
R1IN_ADD_1_1_0_AXB_20_Z4482: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(52),
I1 => R1IN_3(52),
O => R1IN_ADD_1_1_0_AXB_20);
R1IN_ADD_1_1_0_AXB_21_Z4483: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(53),
I1 => R1IN_3(53),
O => R1IN_ADD_1_1_0_AXB_21);
R1IN_ADD_1_1_0_AXB_22_Z4484: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(54),
I1 => R1IN_3(54),
O => R1IN_ADD_1_1_0_AXB_22);
R1IN_ADD_1_1_0_AXB_23_Z4485: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(55),
I1 => R1IN_3(55),
O => R1IN_ADD_1_1_0_AXB_23);
R1IN_ADD_1_1_0_AXB_24_Z4486: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(56),
I1 => R1IN_3(56),
O => R1IN_ADD_1_1_0_AXB_24);
R1IN_ADD_1_1_0_AXB_25_Z4487: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(57),
I1 => R1IN_3(57),
O => R1IN_ADD_1_1_0_AXB_25);
R1IN_ADD_1_1_0_AXB_26_Z4488: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(58),
I1 => R1IN_3(58),
O => R1IN_ADD_1_1_0_AXB_26);
R1IN_ADD_1_1_0_AXB_27_Z4489: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(59),
I1 => R1IN_3(59),
O => R1IN_ADD_1_1_0_AXB_27);
R1IN_ADD_1_1_0_AXB_28_Z4490: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(60),
I1 => R1IN_3(60),
O => R1IN_ADD_1_1_0_AXB_28);
R1IN_3_ADD_1_AXB_1_Z4491: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F_RETO(18),
I1 => R1IN_3_2F_RETO(1),
O => R1IN_3_ADD_1_AXB_1);
R1IN_3_ADD_1_AXB_2_Z4492: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F_RETO(19),
I1 => R1IN_3_2F_RETO(2),
O => R1IN_3_ADD_1_AXB_2);
R1IN_3_ADD_1_AXB_3_Z4493: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F_RETO(20),
I1 => R1IN_3_2F_RETO(3),
O => R1IN_3_ADD_1_AXB_3);
R1IN_3_ADD_1_AXB_4_Z4494: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F_RETO(21),
I1 => R1IN_3_2F_RETO(4),
O => R1IN_3_ADD_1_AXB_4);
R1IN_3_ADD_1_AXB_5_Z4495: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F_RETO(22),
I1 => R1IN_3_2F_RETO(5),
O => R1IN_3_ADD_1_AXB_5);
R1IN_3_ADD_1_AXB_6_Z4496: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F_RETO(23),
I1 => R1IN_3_2F_RETO(6),
O => R1IN_3_ADD_1_AXB_6);
R1IN_3_ADD_1_AXB_7_Z4497: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F_RETO(24),
I1 => R1IN_3_2F_RETO(7),
O => R1IN_3_ADD_1_AXB_7);
R1IN_3_ADD_1_AXB_8_Z4498: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F_RETO(25),
I1 => R1IN_3_2F_RETO(8),
O => R1IN_3_ADD_1_AXB_8);
R1IN_3_ADD_1_AXB_9_Z4499: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F_RETO(26),
I1 => R1IN_3_2F_RETO(9),
O => R1IN_3_ADD_1_AXB_9);
R1IN_3_ADD_1_AXB_10_Z4500: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F_RETO(27),
I1 => R1IN_3_2F_RETO(10),
O => R1IN_3_ADD_1_AXB_10);
R1IN_3_ADD_1_AXB_11_Z4501: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F_RETO(28),
I1 => R1IN_3_2F_RETO(11),
O => R1IN_3_ADD_1_AXB_11);
R1IN_3_ADD_1_AXB_12_Z4502: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F_RETO(29),
I1 => R1IN_3_2F_RETO(12),
O => R1IN_3_ADD_1_AXB_12);
R1IN_3_ADD_1_AXB_13_Z4503: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F_RETO(30),
I1 => R1IN_3_2F_RETO(13),
O => R1IN_3_ADD_1_AXB_13);
R1IN_3_ADD_1_AXB_14_Z4504: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F_RETO(31),
I1 => R1IN_3_2F_RETO(14),
O => R1IN_3_ADD_1_AXB_14);
R1IN_3_ADD_1_AXB_15_Z4505: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F_RETO(32),
I1 => R1IN_3_2F_RETO(15),
O => R1IN_3_ADD_1_AXB_15);
R1IN_3_ADD_1_AXB_16_Z4506: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F_RETO(33),
I1 => R1IN_3_2F_RETO(16),
O => R1IN_3_ADD_1_AXB_16);
R1IN_3_ADD_1_AXB_17_Z4507: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(17),
O => R1IN_3_ADD_1_AXB_17);
R1IN_3_ADD_1_AXB_18_Z4508: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(18),
O => R1IN_3_ADD_1_AXB_18);
R1IN_3_ADD_1_AXB_19_Z4509: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(19),
O => R1IN_3_ADD_1_AXB_19);
R1IN_3_ADD_1_AXB_20_Z4510: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(20),
O => R1IN_3_ADD_1_AXB_20);
R1IN_3_ADD_1_AXB_21_Z4511: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(21),
O => R1IN_3_ADD_1_AXB_21);
R1IN_3_ADD_1_AXB_22_Z4512: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(22),
O => R1IN_3_ADD_1_AXB_22);
R1IN_3_ADD_1_AXB_23_Z4513: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(23),
O => R1IN_3_ADD_1_AXB_23);
R1IN_3_ADD_1_AXB_24_Z4514: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(24),
O => R1IN_3_ADD_1_AXB_24);
R1IN_3_ADD_1_AXB_25_Z4515: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(25),
O => R1IN_3_ADD_1_AXB_25);
R1IN_3_ADD_1_AXB_26_Z4516: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(26),
O => R1IN_3_ADD_1_AXB_26);
R1IN_3_ADD_1_AXB_27_Z4517: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(27),
O => R1IN_3_ADD_1_AXB_27);
R1IN_3_ADD_1_AXB_28_Z4518: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(28),
O => R1IN_3_ADD_1_AXB_28);
R1IN_3_ADD_1_AXB_29_Z4519: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(29),
O => R1IN_3_ADD_1_AXB_29);
R1IN_3_ADD_1_AXB_30_Z4520: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(30),
O => R1IN_3_ADD_1_AXB_30);
R1IN_3_ADD_1_AXB_31_Z4521: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(31),
O => R1IN_3_ADD_1_AXB_31);
R1IN_3_ADD_1_AXB_32_Z4522: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(32),
O => R1IN_3_ADD_1_AXB_32);
R1IN_3_ADD_1_AXB_33_Z4523: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(33),
O => R1IN_3_ADD_1_AXB_33);
R1IN_3_ADD_1_AXB_34_Z4524: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(34),
O => R1IN_3_ADD_1_AXB_34);
R1IN_3_ADD_1_AXB_35_Z4525: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(35),
O => R1IN_3_ADD_1_AXB_35);
R1IN_3_ADD_1_AXB_36_Z4526: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(36),
O => R1IN_3_ADD_1_AXB_36);
R1IN_3_ADD_1_AXB_37_Z4527: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(37),
O => R1IN_3_ADD_1_AXB_37);
R1IN_3_ADD_1_AXB_38_Z4528: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(38),
O => R1IN_3_ADD_1_AXB_38);
R1IN_3_ADD_1_AXB_39_Z4529: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(39),
O => R1IN_3_ADD_1_AXB_39);
R1IN_3_ADD_1_AXB_40_Z4530: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(40),
O => R1IN_3_ADD_1_AXB_40);
R1IN_3_ADD_1_AXB_41_Z4531: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(41),
O => R1IN_3_ADD_1_AXB_41);
R1IN_3_ADD_1_AXB_42_Z4532: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(42),
O => R1IN_3_ADD_1_AXB_42);
R1IN_4_4_ADD_2_AXB_0: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_ADD_1F_RETO_0(0),
I1 => R1IN_4_4_ADD_2_RETO_0,
O => R1IN_4_4(17));
R1IN_4_4_ADD_2_AXB_1_Z4534: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F_RETO(18),
I1 => R1IN_4_4_ADD_1F_RETO(1),
O => R1IN_4_4_ADD_2_AXB_1);
R1IN_4_4_ADD_2_AXB_2_Z4535: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F_RETO(19),
I1 => R1IN_4_4_ADD_1F_RETO(2),
O => R1IN_4_4_ADD_2_AXB_2);
R1IN_4_4_ADD_2_AXB_3_Z4536: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F_RETO(20),
I1 => R1IN_4_4_ADD_1F_RETO(3),
O => R1IN_4_4_ADD_2_AXB_3);
R1IN_4_4_ADD_2_AXB_4_Z4537: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F_RETO(21),
I1 => R1IN_4_4_ADD_1F_RETO(4),
O => R1IN_4_4_ADD_2_AXB_4);
R1IN_4_4_ADD_2_AXB_5_Z4538: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F_RETO(22),
I1 => R1IN_4_4_ADD_1F_RETO(5),
O => R1IN_4_4_ADD_2_AXB_5);
R1IN_4_4_ADD_2_AXB_6_Z4539: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F_RETO(23),
I1 => R1IN_4_4_ADD_1F_RETO(6),
O => R1IN_4_4_ADD_2_AXB_6);
R1IN_4_4_ADD_2_AXB_7_Z4540: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F_RETO(24),
I1 => R1IN_4_4_ADD_1F_RETO(7),
O => R1IN_4_4_ADD_2_AXB_7);
R1IN_4_4_ADD_2_AXB_8_Z4541: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F_RETO(25),
I1 => R1IN_4_4_ADD_1F_RETO(8),
O => R1IN_4_4_ADD_2_AXB_8);
R1IN_4_4_ADD_2_AXB_9_Z4542: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F_RETO(26),
I1 => R1IN_4_4_ADD_1F_RETO(9),
O => R1IN_4_4_ADD_2_AXB_9);
R1IN_4_4_ADD_2_AXB_10_Z4543: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F_RETO(27),
I1 => R1IN_4_4_ADD_1F_RETO(10),
O => R1IN_4_4_ADD_2_AXB_10);
R1IN_4_4_ADD_2_AXB_11_Z4544: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F_RETO(28),
I1 => R1IN_4_4_ADD_1F_RETO(11),
O => R1IN_4_4_ADD_2_AXB_11);
R1IN_4_4_ADD_2_AXB_12_Z4545: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F_RETO(29),
I1 => R1IN_4_4_ADD_1F_RETO(12),
O => R1IN_4_4_ADD_2_AXB_12);
R1IN_4_4_ADD_2_AXB_13_Z4546: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F_RETO(30),
I1 => R1IN_4_4_ADD_1F_RETO(13),
O => R1IN_4_4_ADD_2_AXB_13);
R1IN_4_4_ADD_2_AXB_14_Z4547: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F_RETO(31),
I1 => R1IN_4_4_ADD_1F_RETO(14),
O => R1IN_4_4_ADD_2_AXB_14);
R1IN_4_4_ADD_2_AXB_15_Z4548: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F_RETO(32),
I1 => R1IN_4_4_ADD_1F_RETO(15),
O => R1IN_4_4_ADD_2_AXB_15);
R1IN_4_4_ADD_2_AXB_16_Z4549: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F_RETO(33),
I1 => R1IN_4_4_ADD_1F_RETO(16),
O => R1IN_4_4_ADD_2_AXB_16);
R1IN_4_4_ADD_2_AXB_17_Z4550: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F_RETO(0),
I1 => R1IN_4_4_ADD_1F_RETO(17),
O => R1IN_4_4_ADD_2_AXB_17);
R1IN_4_4_ADD_2_AXB_18_Z4551: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F_RETO(1),
I1 => R1IN_4_4_ADD_1F_RETO(18),
O => R1IN_4_4_ADD_2_AXB_18);
R1IN_4_4_ADD_2_AXB_19_Z4552: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F_RETO(2),
I1 => R1IN_4_4_ADD_1F_RETO(19),
O => R1IN_4_4_ADD_2_AXB_19);
R1IN_4_4_ADD_2_AXB_20_Z4553: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F_RETO(3),
I1 => R1IN_4_4_ADD_1F_RETO(20),
O => R1IN_4_4_ADD_2_AXB_20);
R1IN_4_4_ADD_2_AXB_21_Z4554: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F_RETO(4),
I1 => R1IN_4_4_ADD_1F_RETO(21),
O => R1IN_4_4_ADD_2_AXB_21);
R1IN_4_4_ADD_2_AXB_22_Z4555: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F_RETO(5),
I1 => R1IN_4_4_ADD_1F_RETO(22),
O => R1IN_4_4_ADD_2_AXB_22);
R1IN_4_4_ADD_2_AXB_23_Z4556: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F_RETO(6),
I1 => R1IN_4_4_ADD_1F_RETO(23),
O => R1IN_4_4_ADD_2_AXB_23);
R1IN_4_4_ADD_2_AXB_24_Z4557: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F_RETO(7),
I1 => R1IN_4_4_ADD_1F_RETO(24),
O => R1IN_4_4_ADD_2_AXB_24);
R1IN_4_4_ADD_2_AXB_25_Z4558: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F_RETO(8),
I1 => R1IN_4_4_ADD_1F_RETO(25),
O => R1IN_4_4_ADD_2_AXB_25);
R1IN_4_4_ADD_2_AXB_26_Z4559: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F_RETO(9),
I1 => R1IN_4_4_ADD_1F_RETO(26),
O => R1IN_4_4_ADD_2_AXB_26);
R1IN_4_4_ADD_2_AXB_27_Z4560: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F_RETO(10),
I1 => R1IN_4_4_ADD_1F_RETO(27),
O => R1IN_4_4_ADD_2_AXB_27);
R1IN_4_4_ADD_2_AXB_28_Z4561: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4_4F_RETO(11),
O => R1IN_4_4_ADD_2_AXB_28);
R1IN_4_4_ADD_2_AXB_29_Z4562: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4_4F_RETO(12),
O => R1IN_4_4_ADD_2_AXB_29);
R1IN_4_4_ADD_2_AXB_30_Z4563: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4_4F_RETO(13),
O => R1IN_4_4_ADD_2_AXB_30);
R1IN_4_4_ADD_2_AXB_31_Z4564: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4_4F_RETO(14),
O => R1IN_4_4_ADD_2_AXB_31);
R1IN_4_4_ADD_2_AXB_32_Z4565: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4_4F_RETO(15),
O => R1IN_4_4_ADD_2_AXB_32);
R1IN_4_4_ADD_2_AXB_33_Z4566: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4_4F_RETO(16),
O => R1IN_4_4_ADD_2_AXB_33);
R1IN_4_4_ADD_2_AXB_34_Z4567: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4_4F_RETO(17),
O => R1IN_4_4_ADD_2_AXB_34);
R1IN_4_4_ADD_2_AXB_35_Z4568: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4_4F_RETO(18),
O => R1IN_4_4_ADD_2_AXB_35);
R1IN_ADD_2_AXB_1_Z4569: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(18),
I1 => R1IN_ADD_1(1),
O => R1IN_ADD_2_AXB_1);
R1IN_ADD_2_AXB_2_Z4570: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(19),
I1 => R1IN_ADD_1(2),
O => R1IN_ADD_2_AXB_2);
R1IN_ADD_2_AXB_3_Z4571: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(20),
I1 => R1IN_ADD_1(3),
O => R1IN_ADD_2_AXB_3);
R1IN_ADD_2_AXB_4_Z4572: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(21),
I1 => R1IN_ADD_1(4),
O => R1IN_ADD_2_AXB_4);
R1IN_ADD_2_AXB_5_Z4573: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(22),
I1 => R1IN_ADD_1(5),
O => R1IN_ADD_2_AXB_5);
R1IN_ADD_2_AXB_6_Z4574: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(23),
I1 => R1IN_ADD_1(6),
O => R1IN_ADD_2_AXB_6);
R1IN_ADD_2_AXB_7_Z4575: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(24),
I1 => R1IN_ADD_1(7),
O => R1IN_ADD_2_AXB_7);
R1IN_ADD_2_AXB_8_Z4576: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(25),
I1 => R1IN_ADD_1(8),
O => R1IN_ADD_2_AXB_8);
R1IN_ADD_2_AXB_9_Z4577: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(26),
I1 => R1IN_ADD_1(9),
O => R1IN_ADD_2_AXB_9);
R1IN_ADD_2_AXB_10_Z4578: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(27),
I1 => R1IN_ADD_1(10),
O => R1IN_ADD_2_AXB_10);
R1IN_ADD_2_AXB_11_Z4579: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(28),
I1 => R1IN_ADD_1(11),
O => R1IN_ADD_2_AXB_11);
R1IN_ADD_2_AXB_12_Z4580: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(29),
I1 => R1IN_ADD_1(12),
O => R1IN_ADD_2_AXB_12);
R1IN_ADD_2_AXB_13_Z4581: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(30),
I1 => R1IN_ADD_1(13),
O => R1IN_ADD_2_AXB_13);
R1IN_ADD_2_AXB_14_Z4582: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(31),
I1 => R1IN_ADD_1(14),
O => R1IN_ADD_2_AXB_14);
R1IN_ADD_2_AXB_15_Z4583: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(32),
I1 => R1IN_ADD_1(15),
O => R1IN_ADD_2_AXB_15);
R1IN_ADD_2_AXB_16_Z4584: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(33),
I1 => R1IN_ADD_1(16),
O => R1IN_ADD_2_AXB_16);
R1IN_ADD_2_AXB_17_Z4585: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(0),
I1 => R1IN_ADD_1(17),
O => R1IN_ADD_2_AXB_17);
R1IN_ADD_2_AXB_18_Z4586: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(1),
I1 => R1IN_ADD_1(18),
O => R1IN_ADD_2_AXB_18);
R1IN_ADD_2_AXB_19_Z4587: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(2),
I1 => R1IN_ADD_1(19),
O => R1IN_ADD_2_AXB_19);
R1IN_ADD_2_AXB_20_Z4588: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(3),
I1 => R1IN_ADD_1(20),
O => R1IN_ADD_2_AXB_20);
R1IN_ADD_2_AXB_21_Z4589: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(4),
I1 => R1IN_ADD_1(21),
O => R1IN_ADD_2_AXB_21);
R1IN_ADD_2_AXB_22_Z4590: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(5),
I1 => R1IN_ADD_1(22),
O => R1IN_ADD_2_AXB_22);
R1IN_ADD_2_AXB_23_Z4591: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(6),
I1 => R1IN_ADD_1(23),
O => R1IN_ADD_2_AXB_23);
R1IN_ADD_2_AXB_24_Z4592: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(7),
I1 => R1IN_ADD_1(24),
O => R1IN_ADD_2_AXB_24);
R1IN_ADD_2_AXB_25_Z4593: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(8),
I1 => R1IN_ADD_1(25),
O => R1IN_ADD_2_AXB_25);
R1IN_ADD_2_AXB_26_Z4594: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(9),
I1 => R1IN_ADD_1(26),
O => R1IN_ADD_2_AXB_26);
R1IN_ADD_2_AXB_27_Z4595: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(10),
I1 => R1IN_ADD_1(27),
O => R1IN_ADD_2_AXB_27);
R1IN_ADD_2_AXB_28_Z4596: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(11),
I1 => R1IN_ADD_1(28),
O => R1IN_ADD_2_AXB_28);
R1IN_ADD_2_AXB_29_Z4597: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(12),
I1 => R1IN_ADD_1(29),
O => R1IN_ADD_2_AXB_29);
R1IN_ADD_2_AXB_30_Z4598: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(13),
I1 => R1IN_ADD_1(30),
O => R1IN_ADD_2_AXB_30);
R1IN_ADD_2_AXB_31_Z4599: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(14),
I1 => R1IN_ADD_1(31),
O => R1IN_ADD_2_AXB_31);
R1IN_ADD_2_AXB_32_Z4600: LUT4
generic map(
INIT => X"95A6"
)
port map (
I0 => R1IN_4FF(15),
I1 => R1IN_ADD_1_0_CRY_31,
I2 => R1IN_ADD_1_1_0_AXB_0,
I3 => R1IN_ADD_1_1_AXB_0,
O => R1IN_ADD_2_AXB_32);
R1IN_ADD_2_AXB_33_Z4601: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1379,
I1 => N_1565,
I2 => R1IN_4FF(16),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_33);
R1IN_ADD_2_AXB_34_Z4602: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1381,
I1 => N_1566,
I2 => R1IN_4(17),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_34);
R1IN_ADD_2_AXB_35_Z4603: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1383,
I1 => N_1567,
I2 => R1IN_4(18),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_35);
R1IN_ADD_2_AXB_36_Z4604: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1385,
I1 => N_1568,
I2 => R1IN_4(19),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_36);
R1IN_ADD_2_AXB_37_Z4605: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1387,
I1 => N_1569,
I2 => R1IN_4(20),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_37);
R1IN_ADD_2_AXB_38_Z4606: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1389,
I1 => N_1570,
I2 => R1IN_4(21),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_38);
R1IN_ADD_2_AXB_39_Z4607: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1391,
I1 => N_1571,
I2 => R1IN_4(22),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_39);
R1IN_ADD_2_AXB_40_Z4608: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1393,
I1 => N_1572,
I2 => R1IN_4(23),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_40);
R1IN_ADD_2_AXB_41_Z4609: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1395,
I1 => N_1573,
I2 => R1IN_4(24),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_41);
R1IN_ADD_2_AXB_42_Z4610: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1397,
I1 => N_1574,
I2 => R1IN_4(25),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_42);
R1IN_ADD_2_AXB_43_Z4611: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1399,
I1 => N_1575,
I2 => R1IN_4(26),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_43);
R1IN_ADD_2_AXB_44_Z4612: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1401,
I1 => N_1576,
I2 => R1IN_4(27),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_44);
R1IN_ADD_2_AXB_45_Z4613: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1403,
I1 => N_1577,
I2 => R1IN_4(28),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_45);
R1IN_ADD_2_AXB_46_Z4614: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1405,
I1 => N_1578,
I2 => R1IN_4(29),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_46);
R1IN_ADD_2_AXB_47_Z4615: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1407,
I1 => N_1579,
I2 => R1IN_4(30),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_47);
R1IN_ADD_2_AXB_48_Z4616: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1409,
I1 => N_1580,
I2 => R1IN_4(31),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_48);
R1IN_ADD_2_AXB_49_Z4617: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1411,
I1 => N_1581,
I2 => R1IN_4(32),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_49);
R1IN_ADD_2_AXB_50_Z4618: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1413,
I1 => N_1582,
I2 => R1IN_4(33),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_50);
R1IN_ADD_2_AXB_51_Z4619: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1415,
I1 => N_1583,
I2 => R1IN_4(34),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_51);
R1IN_ADD_2_AXB_52_Z4620: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1417,
I1 => N_1584,
I2 => R1IN_4(35),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_52);
R1IN_ADD_2_AXB_53_Z4621: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1419,
I1 => N_1585,
I2 => R1IN_4(36),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_53);
R1IN_ADD_2_AXB_54_Z4622: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1421,
I1 => N_1586,
I2 => R1IN_4(37),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_54);
R1IN_ADD_2_AXB_55_Z4623: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1423,
I1 => N_1587,
I2 => R1IN_4(38),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_55);
R1IN_ADD_2_AXB_56_Z4624: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1425,
I1 => N_1588,
I2 => R1IN_4(39),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_56);
R1IN_ADD_2_AXB_57_Z4625: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1427,
I1 => N_1589,
I2 => R1IN_4(40),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_57);
R1IN_ADD_2_AXB_58_Z4626: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1429,
I1 => N_1590,
I2 => R1IN_4(41),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_58);
R1IN_ADD_2_AXB_59_Z4627: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1431,
I1 => N_1591,
I2 => R1IN_4(42),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_59);
R1IN_ADD_2_AXB_60_Z4628: LUT4
generic map(
INIT => X"3C5A"
)
port map (
I0 => N_1433,
I1 => N_1592,
I2 => R1IN_4(43),
I3 => R1IN_ADD_1_0_CRY_31,
O => R1IN_ADD_2_AXB_60);
R1IN_ADD_2_AXB_61_Z4629: LUT4
generic map(
INIT => X"596A"
)
port map (
I0 => R1IN_4(44),
I1 => R1IN_ADD_1_0_CRY_31,
I2 => R1IN_ADD_1_1_0_CRY_28,
I3 => R1IN_ADD_1_1_CRY_28,
O => R1IN_ADD_2_AXB_61);
R1IN_ADD_2_AXB_62_Z4630: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4(45),
O => R1IN_ADD_2_AXB_62);
R1IN_ADD_2_AXB_63_Z4631: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4(46),
O => R1IN_ADD_2_AXB_63);
R1IN_ADD_2_AXB_64_Z4632: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4(47),
O => R1IN_ADD_2_AXB_64);
R1IN_ADD_2_AXB_65_Z4633: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4(48),
O => R1IN_ADD_2_AXB_65);
R1IN_ADD_2_AXB_66_Z4634: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4(49),
O => R1IN_ADD_2_AXB_66);
R1IN_ADD_2_AXB_67_Z4635: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4(50),
O => R1IN_ADD_2_AXB_67);
R1IN_ADD_2_AXB_68_Z4636: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4(51),
O => R1IN_ADD_2_AXB_68);
R1IN_ADD_2_AXB_69_Z4637: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4(52),
O => R1IN_ADD_2_AXB_69);
R1IN_ADD_2_AXB_70_Z4638: LUT3
generic map(
INIT => X"72"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35,
I1 => R1IN_4_ADD_2_1_0_AXB_0,
I2 => R1IN_4_ADD_2_1_AXB_0,
O => R1IN_ADD_2_AXB_70);
R1IN_ADD_2_AXB_71_Z4639: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1445,
I1 => N_1523,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_71);
R1IN_ADD_2_AXB_72_Z4640: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1447,
I1 => N_1524,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_72);
R1IN_ADD_2_AXB_73_Z4641: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1449,
I1 => N_1525,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_73);
R1IN_ADD_2_AXB_74_Z4642: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1451,
I1 => N_1526,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_74);
R1IN_ADD_2_AXB_75_Z4643: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1453,
I1 => N_1527,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_75);
R1IN_ADD_2_AXB_76_Z4644: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1455,
I1 => N_1528,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_76);
R1IN_ADD_2_AXB_77_Z4645: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1457,
I1 => N_1529,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_77);
R1IN_ADD_2_AXB_78_Z4646: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1459,
I1 => N_1530,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_78);
R1IN_ADD_2_AXB_79_Z4647: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1461,
I1 => N_1531,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_79);
R1IN_ADD_2_AXB_80_Z4648: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1463,
I1 => N_1532,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_80);
R1IN_ADD_2_AXB_81_Z4649: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1465,
I1 => N_1533,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_81);
R1IN_ADD_2_AXB_82_Z4650: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1467,
I1 => N_1534,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_82);
R1IN_ADD_2_AXB_83_Z4651: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1469,
I1 => N_1535,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_83);
R1IN_ADD_2_AXB_84_Z4652: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1471,
I1 => N_1536,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_84);
R1IN_ADD_2_AXB_85_Z4653: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1473,
I1 => N_1537,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_85);
R1IN_ADD_2_AXB_86_Z4654: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1475,
I1 => N_1538,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_86);
R1IN_ADD_2_AXB_87_Z4655: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1477,
I1 => N_1539,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_87);
R1IN_ADD_2_AXB_88_Z4656: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1479,
I1 => N_1540,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_88);
R1IN_ADD_2_AXB_89_Z4657: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1481,
I1 => N_1541,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_89);
R1IN_ADD_2_AXB_90_Z4658: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1483,
I1 => N_1542,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_90);
R1IN_ADD_2_AXB_91_Z4659: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1485,
I1 => N_1543,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_91);
R1IN_ADD_2_AXB_92_Z4660: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1487,
I1 => N_1544,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_92);
R1IN_ADD_2_AXB_93_Z4661: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1489,
I1 => N_1545,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_93);
R1IN_ADD_2_AXB_94_Z4662: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1491,
I1 => N_1546,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_94);
R1IN_ADD_2_AXB_95_Z4663: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1493,
I1 => N_1547,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_95);
R1IN_ADD_2_AXB_96_Z4664: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1495,
I1 => N_1548,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_96);
R1IN_ADD_2_AXB_97_Z4665: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1497,
I1 => N_1549,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_97);
R1IN_ADD_2_AXB_98_Z4666: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1499,
I1 => N_1550,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_98);
R1IN_ADD_2_AXB_99_Z4667: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1501,
I1 => N_1551,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_99);
R1IN_ADD_2_AXB_100_Z4668: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1503,
I1 => N_1552,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_100);
R1IN_ADD_2_AXB_101_Z4669: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1505,
I1 => N_1553,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_101);
R1IN_ADD_2_AXB_102_Z4670: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1507,
I1 => N_1554,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_102);
R1IN_ADD_2_AXB_103_Z4671: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1509,
I1 => N_1555,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_103);
R1IN_2_ADD_1_AXB_1_Z4672: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F_RETO(18),
I1 => R1IN_2_2F_RETO(1),
O => R1IN_2_ADD_1_AXB_1);
R1IN_2_ADD_1_AXB_2_Z4673: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F_RETO(19),
I1 => R1IN_2_2F_RETO(2),
O => R1IN_2_ADD_1_AXB_2);
R1IN_2_ADD_1_AXB_3_Z4674: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F_RETO(20),
I1 => R1IN_2_2F_RETO(3),
O => R1IN_2_ADD_1_AXB_3);
R1IN_2_ADD_1_AXB_4_Z4675: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F_RETO(21),
I1 => R1IN_2_2F_RETO(4),
O => R1IN_2_ADD_1_AXB_4);
R1IN_2_ADD_1_AXB_5_Z4676: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F_RETO(22),
I1 => R1IN_2_2F_RETO(5),
O => R1IN_2_ADD_1_AXB_5);
R1IN_2_ADD_1_AXB_6_Z4677: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F_RETO(23),
I1 => R1IN_2_2F_RETO(6),
O => R1IN_2_ADD_1_AXB_6);
R1IN_2_ADD_1_AXB_7_Z4678: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F_RETO(24),
I1 => R1IN_2_2F_RETO(7),
O => R1IN_2_ADD_1_AXB_7);
R1IN_2_ADD_1_AXB_8_Z4679: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F_RETO(25),
I1 => R1IN_2_2F_RETO(8),
O => R1IN_2_ADD_1_AXB_8);
R1IN_2_ADD_1_AXB_9_Z4680: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F_RETO(26),
I1 => R1IN_2_2F_RETO(9),
O => R1IN_2_ADD_1_AXB_9);
R1IN_2_ADD_1_AXB_10_Z4681: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F_RETO(27),
I1 => R1IN_2_2F_RETO(10),
O => R1IN_2_ADD_1_AXB_10);
R1IN_2_ADD_1_AXB_11_Z4682: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F_RETO(28),
I1 => R1IN_2_2F_RETO(11),
O => R1IN_2_ADD_1_AXB_11);
R1IN_2_ADD_1_AXB_12_Z4683: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F_RETO(29),
I1 => R1IN_2_2F_RETO(12),
O => R1IN_2_ADD_1_AXB_12);
R1IN_2_ADD_1_AXB_13_Z4684: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F_RETO(30),
I1 => R1IN_2_2F_RETO(13),
O => R1IN_2_ADD_1_AXB_13);
R1IN_2_ADD_1_AXB_14_Z4685: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F_RETO(31),
I1 => R1IN_2_2F_RETO(14),
O => R1IN_2_ADD_1_AXB_14);
R1IN_2_ADD_1_AXB_15_Z4686: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F_RETO(32),
I1 => R1IN_2_2F_RETO(15),
O => R1IN_2_ADD_1_AXB_15);
R1IN_2_ADD_1_AXB_16_Z4687: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F_RETO(33),
I1 => R1IN_2_2F_RETO(16),
O => R1IN_2_ADD_1_AXB_16);
R1IN_2_ADD_1_AXB_17_Z4688: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(17),
O => R1IN_2_ADD_1_AXB_17);
R1IN_2_ADD_1_AXB_18_Z4689: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(18),
O => R1IN_2_ADD_1_AXB_18);
R1IN_2_ADD_1_AXB_19_Z4690: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(19),
O => R1IN_2_ADD_1_AXB_19);
R1IN_2_ADD_1_AXB_20_Z4691: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(20),
O => R1IN_2_ADD_1_AXB_20);
R1IN_2_ADD_1_AXB_21_Z4692: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(21),
O => R1IN_2_ADD_1_AXB_21);
R1IN_2_ADD_1_AXB_22_Z4693: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(22),
O => R1IN_2_ADD_1_AXB_22);
R1IN_2_ADD_1_AXB_23_Z4694: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(23),
O => R1IN_2_ADD_1_AXB_23);
R1IN_2_ADD_1_AXB_24_Z4695: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(24),
O => R1IN_2_ADD_1_AXB_24);
R1IN_2_ADD_1_AXB_25_Z4696: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(25),
O => R1IN_2_ADD_1_AXB_25);
R1IN_2_ADD_1_AXB_26_Z4697: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(26),
O => R1IN_2_ADD_1_AXB_26);
R1IN_2_ADD_1_AXB_27_Z4698: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(27),
O => R1IN_2_ADD_1_AXB_27);
R1IN_2_ADD_1_AXB_28_Z4699: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(28),
O => R1IN_2_ADD_1_AXB_28);
R1IN_2_ADD_1_AXB_29_Z4700: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(29),
O => R1IN_2_ADD_1_AXB_29);
R1IN_2_ADD_1_AXB_30_Z4701: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(30),
O => R1IN_2_ADD_1_AXB_30);
R1IN_2_ADD_1_AXB_31_Z4702: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(31),
O => R1IN_2_ADD_1_AXB_31);
R1IN_2_ADD_1_AXB_32_Z4703: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(32),
O => R1IN_2_ADD_1_AXB_32);
R1IN_2_ADD_1_AXB_33_Z4704: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(33),
O => R1IN_2_ADD_1_AXB_33);
R1IN_2_ADD_1_AXB_34_Z4705: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(34),
O => R1IN_2_ADD_1_AXB_34);
R1IN_2_ADD_1_AXB_35_Z4706: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(35),
O => R1IN_2_ADD_1_AXB_35);
R1IN_2_ADD_1_AXB_36_Z4707: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(36),
O => R1IN_2_ADD_1_AXB_36);
R1IN_2_ADD_1_AXB_37_Z4708: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(37),
O => R1IN_2_ADD_1_AXB_37);
R1IN_2_ADD_1_AXB_38_Z4709: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(38),
O => R1IN_2_ADD_1_AXB_38);
R1IN_2_ADD_1_AXB_39_Z4710: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(39),
O => R1IN_2_ADD_1_AXB_39);
R1IN_2_ADD_1_AXB_40_Z4711: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(40),
O => R1IN_2_ADD_1_AXB_40);
R1IN_2_ADD_1_AXB_41_Z4712: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(41),
O => R1IN_2_ADD_1_AXB_41);
R1IN_2_ADD_1_AXB_42_Z4713: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(42),
O => R1IN_2_ADD_1_AXB_42);
R1IN_4_ADD_1_AXB_1_Z4714: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(1),
I1 => R1IN_4_3F_RETO(1),
O => R1IN_4_ADD_1_AXB_1);
R1IN_4_ADD_1_AXB_2_Z4715: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(2),
I1 => R1IN_4_3F_RETO(2),
O => R1IN_4_ADD_1_AXB_2);
R1IN_4_ADD_1_AXB_3_Z4716: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(3),
I1 => R1IN_4_3F_RETO(3),
O => R1IN_4_ADD_1_AXB_3);
R1IN_4_ADD_1_AXB_4_Z4717: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(4),
I1 => R1IN_4_3F_RETO(4),
O => R1IN_4_ADD_1_AXB_4);
R1IN_4_ADD_1_AXB_5_Z4718: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(5),
I1 => R1IN_4_3F_RETO(5),
O => R1IN_4_ADD_1_AXB_5);
R1IN_4_ADD_1_AXB_6_Z4719: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(6),
I1 => R1IN_4_3F_RETO(6),
O => R1IN_4_ADD_1_AXB_6);
R1IN_4_ADD_1_AXB_7_Z4720: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(7),
I1 => R1IN_4_3F_RETO(7),
O => R1IN_4_ADD_1_AXB_7);
R1IN_4_ADD_1_AXB_8_Z4721: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(8),
I1 => R1IN_4_3F_RETO(8),
O => R1IN_4_ADD_1_AXB_8);
R1IN_4_ADD_1_AXB_9_Z4722: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(9),
I1 => R1IN_4_3F_RETO(9),
O => R1IN_4_ADD_1_AXB_9);
R1IN_4_ADD_1_AXB_10_Z4723: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(10),
I1 => R1IN_4_3F_RETO(10),
O => R1IN_4_ADD_1_AXB_10);
R1IN_4_ADD_1_AXB_11_Z4724: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(11),
I1 => R1IN_4_3F_RETO(11),
O => R1IN_4_ADD_1_AXB_11);
R1IN_4_ADD_1_AXB_12_Z4725: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(12),
I1 => R1IN_4_3F_RETO(12),
O => R1IN_4_ADD_1_AXB_12);
R1IN_4_ADD_1_AXB_13_Z4726: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(13),
I1 => R1IN_4_3F_RETO(13),
O => R1IN_4_ADD_1_AXB_13);
R1IN_4_ADD_1_AXB_14_Z4727: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(14),
I1 => R1IN_4_3F_RETO(14),
O => R1IN_4_ADD_1_AXB_14);
R1IN_4_ADD_1_AXB_15_Z4728: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(15),
I1 => R1IN_4_3F_RETO(15),
O => R1IN_4_ADD_1_AXB_15);
R1IN_4_ADD_1_AXB_16_Z4729: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(16),
I1 => R1IN_4_3F_RETO(16),
O => R1IN_4_ADD_1_AXB_16);
R1IN_4_ADD_1_AXB_17_Z4730: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(17),
I1 => R1IN_4_3F_RETO(17),
O => R1IN_4_ADD_1_AXB_17);
R1IN_4_ADD_1_AXB_18_Z4731: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(18),
I1 => R1IN_4_3F_RETO(18),
O => R1IN_4_ADD_1_AXB_18);
R1IN_4_ADD_1_AXB_19_Z4732: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(19),
I1 => R1IN_4_3F_RETO(19),
O => R1IN_4_ADD_1_AXB_19);
R1IN_4_ADD_1_AXB_20_Z4733: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(20),
I1 => R1IN_4_3F_RETO(20),
O => R1IN_4_ADD_1_AXB_20);
R1IN_4_ADD_1_AXB_21_Z4734: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(21),
I1 => R1IN_4_3F_RETO(21),
O => R1IN_4_ADD_1_AXB_21);
R1IN_4_ADD_1_AXB_22_Z4735: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(22),
I1 => R1IN_4_3F_RETO(22),
O => R1IN_4_ADD_1_AXB_22);
R1IN_4_ADD_1_AXB_23_Z4736: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(23),
I1 => R1IN_4_3F_RETO(23),
O => R1IN_4_ADD_1_AXB_23);
R1IN_4_ADD_1_AXB_24_Z4737: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(24),
I1 => R1IN_4_3F_RETO(24),
O => R1IN_4_ADD_1_AXB_24);
R1IN_4_ADD_1_AXB_25_Z4738: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(25),
I1 => R1IN_4_3F_RETO(25),
O => R1IN_4_ADD_1_AXB_25);
R1IN_4_ADD_1_AXB_26_Z4739: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(26),
I1 => R1IN_4_3F_RETO(26),
O => R1IN_4_ADD_1_AXB_26);
R1IN_4_ADD_1_AXB_27_Z4740: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(27),
I1 => R1IN_4_3F_RETO(27),
O => R1IN_4_ADD_1_AXB_27);
R1IN_4_ADD_1_AXB_28_Z4741: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(28),
I1 => R1IN_4_3F_RETO(28),
O => R1IN_4_ADD_1_AXB_28);
R1IN_4_ADD_1_AXB_29_Z4742: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(29),
I1 => R1IN_4_3F_RETO(29),
O => R1IN_4_ADD_1_AXB_29);
R1IN_4_ADD_1_AXB_30_Z4743: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(30),
I1 => R1IN_4_3F_RETO(30),
O => R1IN_4_ADD_1_AXB_30);
R1IN_4_ADD_1_AXB_31_Z4744: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(31),
I1 => R1IN_4_3F_RETO(31),
O => R1IN_4_ADD_1_AXB_31);
R1IN_4_ADD_1_AXB_32_Z4745: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(32),
I1 => R1IN_4_3F_RETO(32),
O => R1IN_4_ADD_1_AXB_32);
R1IN_4_ADD_1_AXB_33_Z4746: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(33),
I1 => R1IN_4_3F_RETO(33),
O => R1IN_4_ADD_1_AXB_33);
R1IN_4_ADD_1_AXB_34_Z4747: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(34),
I1 => R1IN_4_3F_RETO(34),
O => R1IN_4_ADD_1_AXB_34);
R1IN_4_ADD_1_AXB_35_Z4748: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(35),
I1 => R1IN_4_3F_RETO(35),
O => R1IN_4_ADD_1_AXB_35);
R1IN_4_ADD_1_AXB_36_Z4749: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(36),
I1 => R1IN_4_3F_RETO(36),
O => R1IN_4_ADD_1_AXB_36);
R1IN_4_ADD_1_AXB_37_Z4750: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(37),
I1 => R1IN_4_3F_RETO(37),
O => R1IN_4_ADD_1_AXB_37);
R1IN_4_ADD_1_AXB_38_Z4751: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(38),
I1 => R1IN_4_3F_RETO(38),
O => R1IN_4_ADD_1_AXB_38);
R1IN_4_ADD_1_AXB_39_Z4752: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(39),
I1 => R1IN_4_3F_RETO(39),
O => R1IN_4_ADD_1_AXB_39);
R1IN_4_ADD_1_AXB_40_Z4753: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(40),
I1 => R1IN_4_3F_RETO(40),
O => R1IN_4_ADD_1_AXB_40);
R1IN_4_ADD_1_AXB_41_Z4754: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(41),
I1 => R1IN_4_3F_RETO(41),
O => R1IN_4_ADD_1_AXB_41);
R1IN_4_ADD_1_AXB_42_Z4755: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(42),
I1 => R1IN_4_3F_RETO(42),
O => R1IN_4_ADD_1_AXB_42);
R1IN_4_ADD_1_AXB_43_Z4756: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F_RETO(43),
I1 => R1IN_4_3F_RETO(43),
O => R1IN_4_ADD_1_AXB_43);
R1IN_ADD_1_1_AXB_28_Z4757: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(60),
I1 => R1IN_3(60),
O => R1IN_ADD_1_1_AXB_28);
R1_PIPE_34: FDE port map (
Q => R1IN_4_ADD_1,
D => R1IN_4_2(0),
C => CLK,
CE => EN);
R1_PIPE_283: FDE port map (
Q => R1IN_4_2F(1),
D => R1IN_4_2(1),
C => CLK,
CE => EN);
R1_PIPE_284: FDE port map (
Q => R1IN_4_2F(2),
D => R1IN_4_2(2),
C => CLK,
CE => EN);
R1_PIPE_285: FDE port map (
Q => R1IN_4_2F(3),
D => R1IN_4_2(3),
C => CLK,
CE => EN);
R1_PIPE_286: FDE port map (
Q => R1IN_4_2F(4),
D => R1IN_4_2(4),
C => CLK,
CE => EN);
R1_PIPE_287: FDE port map (
Q => R1IN_4_2F(5),
D => R1IN_4_2(5),
C => CLK,
CE => EN);
R1_PIPE_288: FDE port map (
Q => R1IN_4_2F(6),
D => R1IN_4_2(6),
C => CLK,
CE => EN);
R1_PIPE_289: FDE port map (
Q => R1IN_4_2F(7),
D => R1IN_4_2(7),
C => CLK,
CE => EN);
R1_PIPE_290: FDE port map (
Q => R1IN_4_2F(8),
D => R1IN_4_2(8),
C => CLK,
CE => EN);
R1_PIPE_291: FDE port map (
Q => R1IN_4_2F(9),
D => R1IN_4_2(9),
C => CLK,
CE => EN);
R1_PIPE_292: FDE port map (
Q => R1IN_4_2F(10),
D => R1IN_4_2(10),
C => CLK,
CE => EN);
R1_PIPE_293: FDE port map (
Q => R1IN_4_2F(11),
D => R1IN_4_2(11),
C => CLK,
CE => EN);
R1_PIPE_294: FDE port map (
Q => R1IN_4_2F(12),
D => R1IN_4_2(12),
C => CLK,
CE => EN);
R1_PIPE_295: FDE port map (
Q => R1IN_4_2F(13),
D => R1IN_4_2(13),
C => CLK,
CE => EN);
R1_PIPE_296: FDE port map (
Q => R1IN_4_2F(14),
D => R1IN_4_2(14),
C => CLK,
CE => EN);
R1_PIPE_297: FDE port map (
Q => R1IN_4_2F(15),
D => R1IN_4_2(15),
C => CLK,
CE => EN);
R1_PIPE_298: FDE port map (
Q => R1IN_4_2F(16),
D => R1IN_4_2(16),
C => CLK,
CE => EN);
R1_PIPE_326: FDE port map (
Q => R1IN_4_3F(0),
D => R1IN_4_3(0),
C => CLK,
CE => EN);
R1_PIPE_327: FDE port map (
Q => R1IN_4_3F(1),
D => R1IN_4_3(1),
C => CLK,
CE => EN);
R1_PIPE_328: FDE port map (
Q => R1IN_4_3F(2),
D => R1IN_4_3(2),
C => CLK,
CE => EN);
R1_PIPE_329: FDE port map (
Q => R1IN_4_3F(3),
D => R1IN_4_3(3),
C => CLK,
CE => EN);
R1_PIPE_330: FDE port map (
Q => R1IN_4_3F(4),
D => R1IN_4_3(4),
C => CLK,
CE => EN);
R1_PIPE_331: FDE port map (
Q => R1IN_4_3F(5),
D => R1IN_4_3(5),
C => CLK,
CE => EN);
R1_PIPE_332: FDE port map (
Q => R1IN_4_3F(6),
D => R1IN_4_3(6),
C => CLK,
CE => EN);
R1_PIPE_333: FDE port map (
Q => R1IN_4_3F(7),
D => R1IN_4_3(7),
C => CLK,
CE => EN);
R1_PIPE_334: FDE port map (
Q => R1IN_4_3F(8),
D => R1IN_4_3(8),
C => CLK,
CE => EN);
R1_PIPE_335: FDE port map (
Q => R1IN_4_3F(9),
D => R1IN_4_3(9),
C => CLK,
CE => EN);
R1_PIPE_336: FDE port map (
Q => R1IN_4_3F(10),
D => R1IN_4_3(10),
C => CLK,
CE => EN);
R1_PIPE_337: FDE port map (
Q => R1IN_4_3F(11),
D => R1IN_4_3(11),
C => CLK,
CE => EN);
R1_PIPE_338: FDE port map (
Q => R1IN_4_3F(12),
D => R1IN_4_3(12),
C => CLK,
CE => EN);
R1_PIPE_339: FDE port map (
Q => R1IN_4_3F(13),
D => R1IN_4_3(13),
C => CLK,
CE => EN);
R1_PIPE_340: FDE port map (
Q => R1IN_4_3F(14),
D => R1IN_4_3(14),
C => CLK,
CE => EN);
R1_PIPE_341: FDE port map (
Q => R1IN_4_3F(15),
D => R1IN_4_3(15),
C => CLK,
CE => EN);
R1_PIPE_342: FDE port map (
Q => R1IN_4_3F(16),
D => R1IN_4_3(16),
C => CLK,
CE => EN);
R1_PIPE_105: FDE port map (
Q => R1IN_2_ADD_1,
D => R1IN_2_2(0),
C => CLK,
CE => EN);
R1_PIPE_589: FDE port map (
Q => R1IN_2_2F(1),
D => R1IN_2_2(1),
C => CLK,
CE => EN);
R1_PIPE_590: FDE port map (
Q => R1IN_2_2F(2),
D => R1IN_2_2(2),
C => CLK,
CE => EN);
R1_PIPE_591: FDE port map (
Q => R1IN_2_2F(3),
D => R1IN_2_2(3),
C => CLK,
CE => EN);
R1_PIPE_592: FDE port map (
Q => R1IN_2_2F(4),
D => R1IN_2_2(4),
C => CLK,
CE => EN);
R1_PIPE_593: FDE port map (
Q => R1IN_2_2F(5),
D => R1IN_2_2(5),
C => CLK,
CE => EN);
R1_PIPE_594: FDE port map (
Q => R1IN_2_2F(6),
D => R1IN_2_2(6),
C => CLK,
CE => EN);
R1_PIPE_595: FDE port map (
Q => R1IN_2_2F(7),
D => R1IN_2_2(7),
C => CLK,
CE => EN);
R1_PIPE_596: FDE port map (
Q => R1IN_2_2F(8),
D => R1IN_2_2(8),
C => CLK,
CE => EN);
R1_PIPE_597: FDE port map (
Q => R1IN_2_2F(9),
D => R1IN_2_2(9),
C => CLK,
CE => EN);
R1_PIPE_598: FDE port map (
Q => R1IN_2_2F(10),
D => R1IN_2_2(10),
C => CLK,
CE => EN);
R1_PIPE_599: FDE port map (
Q => R1IN_2_2F(11),
D => R1IN_2_2(11),
C => CLK,
CE => EN);
R1_PIPE_600: FDE port map (
Q => R1IN_2_2F(12),
D => R1IN_2_2(12),
C => CLK,
CE => EN);
R1_PIPE_601: FDE port map (
Q => R1IN_2_2F(13),
D => R1IN_2_2(13),
C => CLK,
CE => EN);
R1_PIPE_602: FDE port map (
Q => R1IN_2_2F(14),
D => R1IN_2_2(14),
C => CLK,
CE => EN);
R1_PIPE_603: FDE port map (
Q => R1IN_2_2F(15),
D => R1IN_2_2(15),
C => CLK,
CE => EN);
R1_PIPE_604: FDE port map (
Q => R1IN_2_2F(16),
D => R1IN_2_2(16),
C => CLK,
CE => EN);
R1_PIPE_484: FDE port map (
Q => R1IN_3_ADD_1,
D => R1IN_3_2(0),
C => CLK,
CE => EN);
R1_PIPE_649: FDE port map (
Q => R1IN_3_2F(1),
D => R1IN_3_2(1),
C => CLK,
CE => EN);
R1_PIPE_650: FDE port map (
Q => R1IN_3_2F(2),
D => R1IN_3_2(2),
C => CLK,
CE => EN);
R1_PIPE_651: FDE port map (
Q => R1IN_3_2F(3),
D => R1IN_3_2(3),
C => CLK,
CE => EN);
R1_PIPE_652: FDE port map (
Q => R1IN_3_2F(4),
D => R1IN_3_2(4),
C => CLK,
CE => EN);
R1_PIPE_653: FDE port map (
Q => R1IN_3_2F(5),
D => R1IN_3_2(5),
C => CLK,
CE => EN);
R1_PIPE_654: FDE port map (
Q => R1IN_3_2F(6),
D => R1IN_3_2(6),
C => CLK,
CE => EN);
R1_PIPE_655: FDE port map (
Q => R1IN_3_2F(7),
D => R1IN_3_2(7),
C => CLK,
CE => EN);
R1_PIPE_656: FDE port map (
Q => R1IN_3_2F(8),
D => R1IN_3_2(8),
C => CLK,
CE => EN);
R1_PIPE_657: FDE port map (
Q => R1IN_3_2F(9),
D => R1IN_3_2(9),
C => CLK,
CE => EN);
R1_PIPE_658: FDE port map (
Q => R1IN_3_2F(10),
D => R1IN_3_2(10),
C => CLK,
CE => EN);
R1_PIPE_659: FDE port map (
Q => R1IN_3_2F(11),
D => R1IN_3_2(11),
C => CLK,
CE => EN);
R1_PIPE_660: FDE port map (
Q => R1IN_3_2F(12),
D => R1IN_3_2(12),
C => CLK,
CE => EN);
R1_PIPE_661: FDE port map (
Q => R1IN_3_2F(13),
D => R1IN_3_2(13),
C => CLK,
CE => EN);
R1_PIPE_662: FDE port map (
Q => R1IN_3_2F(14),
D => R1IN_3_2(14),
C => CLK,
CE => EN);
R1_PIPE_663: FDE port map (
Q => R1IN_3_2F(15),
D => R1IN_3_2(15),
C => CLK,
CE => EN);
R1_PIPE_664: FDE port map (
Q => R1IN_3_2F(16),
D => R1IN_3_2(16),
C => CLK,
CE => EN);
R2_PIPE_136_RET_1: FDE port map (
Q => R1IN_3F_RETO(0),
D => R1IN_3F(0),
C => CLK,
CE => EN);
R2_PIPE_136_RET_3: FDE port map (
Q => R1IN_3F_RETO(1),
D => R1IN_3F(1),
C => CLK,
CE => EN);
R2_PIPE_136_RET_5: FDE port map (
Q => R1IN_3F_RETO(2),
D => R1IN_3F(2),
C => CLK,
CE => EN);
R2_PIPE_136_RET_7: FDE port map (
Q => R1IN_3F_RETO(3),
D => R1IN_3F(3),
C => CLK,
CE => EN);
R2_PIPE_136_RET_9: FDE port map (
Q => R1IN_3F_RETO(4),
D => R1IN_3F(4),
C => CLK,
CE => EN);
R2_PIPE_136_RET_11: FDE port map (
Q => R1IN_3F_RETO(5),
D => R1IN_3F(5),
C => CLK,
CE => EN);
R2_PIPE_136_RET_13: FDE port map (
Q => R1IN_3F_RETO(6),
D => R1IN_3F(6),
C => CLK,
CE => EN);
R2_PIPE_136_RET_15: FDE port map (
Q => R1IN_3F_RETO(7),
D => R1IN_3F(7),
C => CLK,
CE => EN);
R2_PIPE_136_RET_17: FDE port map (
Q => R1IN_3F_RETO(8),
D => R1IN_3F(8),
C => CLK,
CE => EN);
R2_PIPE_136_RET_19: FDE port map (
Q => R1IN_3F_RETO(9),
D => R1IN_3F(9),
C => CLK,
CE => EN);
R2_PIPE_136_RET_21: FDE port map (
Q => R1IN_3F_RETO(10),
D => R1IN_3F(10),
C => CLK,
CE => EN);
R2_PIPE_136_RET_23: FDE port map (
Q => R1IN_3F_RETO(11),
D => R1IN_3F(11),
C => CLK,
CE => EN);
R2_PIPE_136_RET_25: FDE port map (
Q => R1IN_3F_RETO(12),
D => R1IN_3F(12),
C => CLK,
CE => EN);
R2_PIPE_136_RET_27: FDE port map (
Q => R1IN_3F_RETO(13),
D => R1IN_3F(13),
C => CLK,
CE => EN);
R2_PIPE_136_RET_29: FDE port map (
Q => R1IN_3F_RETO(14),
D => R1IN_3F(14),
C => CLK,
CE => EN);
R2_PIPE_136_RET_31: FDE port map (
Q => R1IN_3F_RETO(15),
D => R1IN_3F(15),
C => CLK,
CE => EN);
R2_PIPE_136_RET_33: FDE port map (
Q => R1IN_3F_RETO(16),
D => R1IN_3F(16),
C => CLK,
CE => EN);
R2_PIPE_136_RET_35: FDE port map (
Q => R1IN_3_1F_RETO(17),
D => R1IN_3_1F(17),
C => CLK,
CE => EN);
R2_PIPE_136_RET_36: FDE port map (
Q => R1IN_3_ADD_1_RETO,
D => R1IN_3_ADD_1,
C => CLK,
CE => EN);
R2_PIPE_69_RET_34: FDE port map (
Q => R1IN_4_4F_RETO(0),
D => R1IN_4_4F(0),
C => CLK,
CE => EN);
R2_PIPE_69_RET_36: FDE port map (
Q => R1IN_4_4F_RETO(1),
D => R1IN_4_4F(1),
C => CLK,
CE => EN);
R2_PIPE_69_RET_38: FDE port map (
Q => R1IN_4_4F_RETO(2),
D => R1IN_4_4F(2),
C => CLK,
CE => EN);
R2_PIPE_69_RET_40: FDE port map (
Q => R1IN_4_4F_RETO(3),
D => R1IN_4_4F(3),
C => CLK,
CE => EN);
R2_PIPE_69_RET_42: FDE port map (
Q => R1IN_4_4F_RETO(4),
D => R1IN_4_4F(4),
C => CLK,
CE => EN);
R2_PIPE_69_RET_44: FDE port map (
Q => R1IN_4_4F_RETO(5),
D => R1IN_4_4F(5),
C => CLK,
CE => EN);
R2_PIPE_69_RET_46: FDE port map (
Q => R1IN_4_4F_RETO(6),
D => R1IN_4_4F(6),
C => CLK,
CE => EN);
R2_PIPE_69_RET_48: FDE port map (
Q => R1IN_4_4F_RETO(7),
D => R1IN_4_4F(7),
C => CLK,
CE => EN);
R2_PIPE_69_RET_50: FDE port map (
Q => R1IN_4_4F_RETO(8),
D => R1IN_4_4F(8),
C => CLK,
CE => EN);
R2_PIPE_69_RET_52: FDE port map (
Q => R1IN_4_4F_RETO(9),
D => R1IN_4_4F(9),
C => CLK,
CE => EN);
R2_PIPE_69_RET_54: FDE port map (
Q => R1IN_4_4F_RETO(10),
D => R1IN_4_4F(10),
C => CLK,
CE => EN);
R2_PIPE_69_RET_56: FDE port map (
Q => R1IN_4_4F_RETO(11),
D => R1IN_4_4F(11),
C => CLK,
CE => EN);
R2_PIPE_69_RET_58: FDE port map (
Q => R1IN_4_4F_RETO(12),
D => R1IN_4_4F(12),
C => CLK,
CE => EN);
R2_PIPE_69_RET_60: FDE port map (
Q => R1IN_4_4F_RETO(13),
D => R1IN_4_4F(13),
C => CLK,
CE => EN);
R2_PIPE_69_RET_62: FDE port map (
Q => R1IN_4_4F_RETO(14),
D => R1IN_4_4F(14),
C => CLK,
CE => EN);
R2_PIPE_69_RET_64: FDE port map (
Q => R1IN_4_4F_RETO(15),
D => R1IN_4_4F(15),
C => CLK,
CE => EN);
R2_PIPE_69_RET_66: FDE port map (
Q => R1IN_4_4F_RETO(16),
D => R1IN_4_4F(16),
C => CLK,
CE => EN);
R2_PIPE_69_RET_68: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(0),
D => R1IN_4_4_ADD_1F(0),
C => CLK,
CE => EN);
R2_PIPE_69_RET_69: FDE port map (
Q => R1IN_4_4_ADD_2_RETO,
D => R1IN_4_4_ADD_2,
C => CLK,
CE => EN);
R2_PIPE_165_RET_119: FDE port map (
Q => R1IN_3_1F_RETO_0(17),
D => R1IN_3_1F(17),
C => CLK,
CE => EN);
R2_PIPE_165_RET_120: FDE port map (
Q => R1IN_3_ADD_1_RETO_0,
D => R1IN_3_ADD_1,
C => CLK,
CE => EN);
R2_PIPE_165_RET_121: FDE port map (
Q => R1IN_3_1F_RETO(18),
D => R1IN_3_1F(18),
C => CLK,
CE => EN);
R2_PIPE_165_RET_122: FDE port map (
Q => R1IN_3_2F_RETO(1),
D => R1IN_3_2F(1),
C => CLK,
CE => EN);
R2_PIPE_165_RET_123: FDE port map (
Q => R1IN_3_1F_RETO(19),
D => R1IN_3_1F(19),
C => CLK,
CE => EN);
R2_PIPE_165_RET_124: FDE port map (
Q => R1IN_3_2F_RETO(2),
D => R1IN_3_2F(2),
C => CLK,
CE => EN);
R2_PIPE_165_RET_125: FDE port map (
Q => R1IN_3_1F_RETO(20),
D => R1IN_3_1F(20),
C => CLK,
CE => EN);
R2_PIPE_165_RET_126: FDE port map (
Q => R1IN_3_2F_RETO(3),
D => R1IN_3_2F(3),
C => CLK,
CE => EN);
R2_PIPE_165_RET_127: FDE port map (
Q => R1IN_3_1F_RETO(21),
D => R1IN_3_1F(21),
C => CLK,
CE => EN);
R2_PIPE_165_RET_128: FDE port map (
Q => R1IN_3_2F_RETO(4),
D => R1IN_3_2F(4),
C => CLK,
CE => EN);
R2_PIPE_165_RET_129: FDE port map (
Q => R1IN_3_1F_RETO(22),
D => R1IN_3_1F(22),
C => CLK,
CE => EN);
R2_PIPE_165_RET_130: FDE port map (
Q => R1IN_3_2F_RETO(5),
D => R1IN_3_2F(5),
C => CLK,
CE => EN);
R2_PIPE_165_RET_131: FDE port map (
Q => R1IN_3_1F_RETO(23),
D => R1IN_3_1F(23),
C => CLK,
CE => EN);
R2_PIPE_165_RET_132: FDE port map (
Q => R1IN_3_2F_RETO(6),
D => R1IN_3_2F(6),
C => CLK,
CE => EN);
R2_PIPE_165_RET_133: FDE port map (
Q => R1IN_3_1F_RETO(24),
D => R1IN_3_1F(24),
C => CLK,
CE => EN);
R2_PIPE_165_RET_134: FDE port map (
Q => R1IN_3_2F_RETO(7),
D => R1IN_3_2F(7),
C => CLK,
CE => EN);
R2_PIPE_165_RET_135: FDE port map (
Q => R1IN_3_1F_RETO(25),
D => R1IN_3_1F(25),
C => CLK,
CE => EN);
R2_PIPE_165_RET_136: FDE port map (
Q => R1IN_3_2F_RETO(8),
D => R1IN_3_2F(8),
C => CLK,
CE => EN);
R2_PIPE_165_RET_137: FDE port map (
Q => R1IN_3_1F_RETO(26),
D => R1IN_3_1F(26),
C => CLK,
CE => EN);
R2_PIPE_165_RET_138: FDE port map (
Q => R1IN_3_2F_RETO(9),
D => R1IN_3_2F(9),
C => CLK,
CE => EN);
R2_PIPE_165_RET_139: FDE port map (
Q => R1IN_3_1F_RETO(27),
D => R1IN_3_1F(27),
C => CLK,
CE => EN);
R2_PIPE_165_RET_140: FDE port map (
Q => R1IN_3_2F_RETO(10),
D => R1IN_3_2F(10),
C => CLK,
CE => EN);
R2_PIPE_165_RET_141: FDE port map (
Q => R1IN_3_1F_RETO(28),
D => R1IN_3_1F(28),
C => CLK,
CE => EN);
R2_PIPE_165_RET_142: FDE port map (
Q => R1IN_3_2F_RETO(11),
D => R1IN_3_2F(11),
C => CLK,
CE => EN);
R2_PIPE_165_RET_143: FDE port map (
Q => R1IN_3_1F_RETO(29),
D => R1IN_3_1F(29),
C => CLK,
CE => EN);
R2_PIPE_165_RET_144: FDE port map (
Q => R1IN_3_2F_RETO(12),
D => R1IN_3_2F(12),
C => CLK,
CE => EN);
R2_PIPE_165_RET_145: FDE port map (
Q => R1IN_3_1F_RETO(30),
D => R1IN_3_1F(30),
C => CLK,
CE => EN);
R2_PIPE_165_RET_146: FDE port map (
Q => R1IN_3_2F_RETO(13),
D => R1IN_3_2F(13),
C => CLK,
CE => EN);
R2_PIPE_165_RET_147: FDE port map (
Q => R1IN_3_1F_RETO(31),
D => R1IN_3_1F(31),
C => CLK,
CE => EN);
R2_PIPE_165_RET_148: FDE port map (
Q => R1IN_3_2F_RETO(14),
D => R1IN_3_2F(14),
C => CLK,
CE => EN);
R2_PIPE_165_RET_149: FDE port map (
Q => R1IN_3_1F_RETO(32),
D => R1IN_3_1F(32),
C => CLK,
CE => EN);
R2_PIPE_165_RET_150: FDE port map (
Q => R1IN_3_2F_RETO(15),
D => R1IN_3_2F(15),
C => CLK,
CE => EN);
R2_PIPE_165_RET_151: FDE port map (
Q => R1IN_3_1F_RETO(33),
D => R1IN_3_1F(33),
C => CLK,
CE => EN);
R2_PIPE_165_RET_152: FDE port map (
Q => R1IN_3_2F_RETO(16),
D => R1IN_3_2F(16),
C => CLK,
CE => EN);
R2_PIPE_165_RET_153: FDE port map (
Q => R1IN_3_2F_RETO(17),
D => R1IN_3_2F(17),
C => CLK,
CE => EN);
R2_PIPE_165_RET_154: FDE port map (
Q => R1IN_3_2F_RETO(18),
D => R1IN_3_2F(18),
C => CLK,
CE => EN);
R2_PIPE_165_RET_155: FDE port map (
Q => R1IN_3_2F_RETO(19),
D => R1IN_3_2F(19),
C => CLK,
CE => EN);
R2_PIPE_165_RET_156: FDE port map (
Q => R1IN_3_2F_RETO(20),
D => R1IN_3_2F(20),
C => CLK,
CE => EN);
R2_PIPE_165_RET_157: FDE port map (
Q => R1IN_3_2F_RETO(21),
D => R1IN_3_2F(21),
C => CLK,
CE => EN);
R2_PIPE_165_RET_158: FDE port map (
Q => R1IN_3_2F_RETO(22),
D => R1IN_3_2F(22),
C => CLK,
CE => EN);
R2_PIPE_165_RET_159: FDE port map (
Q => R1IN_3_2F_RETO(23),
D => R1IN_3_2F(23),
C => CLK,
CE => EN);
R2_PIPE_165_RET_160: FDE port map (
Q => R1IN_3_2F_RETO(24),
D => R1IN_3_2F(24),
C => CLK,
CE => EN);
R2_PIPE_165_RET_161: FDE port map (
Q => R1IN_3_2F_RETO(25),
D => R1IN_3_2F(25),
C => CLK,
CE => EN);
R2_PIPE_165_RET_162: FDE port map (
Q => R1IN_3_2F_RETO(26),
D => R1IN_3_2F(26),
C => CLK,
CE => EN);
R2_PIPE_165_RET_163: FDE port map (
Q => R1IN_3_2F_RETO(27),
D => R1IN_3_2F(27),
C => CLK,
CE => EN);
R2_PIPE_165_RET_164: FDE port map (
Q => R1IN_3_2F_RETO(28),
D => R1IN_3_2F(28),
C => CLK,
CE => EN);
R2_PIPE_165_RET_165: FDE port map (
Q => R1IN_3_2F_RETO(29),
D => R1IN_3_2F(29),
C => CLK,
CE => EN);
R2_PIPE_165_RET_166: FDE port map (
Q => R1IN_3_2F_RETO(30),
D => R1IN_3_2F(30),
C => CLK,
CE => EN);
R2_PIPE_165_RET_167: FDE port map (
Q => R1IN_3_2F_RETO(31),
D => R1IN_3_2F(31),
C => CLK,
CE => EN);
R2_PIPE_165_RET_168: FDE port map (
Q => R1IN_3_2F_RETO(32),
D => R1IN_3_2F(32),
C => CLK,
CE => EN);
R2_PIPE_165_RET_169: FDE port map (
Q => R1IN_3_2F_RETO(33),
D => R1IN_3_2F(33),
C => CLK,
CE => EN);
R2_PIPE_165_RET_170: FDE port map (
Q => R1IN_3_2F_RETO(34),
D => R1IN_3_2F(34),
C => CLK,
CE => EN);
R2_PIPE_165_RET_171: FDE port map (
Q => R1IN_3_2F_RETO(35),
D => R1IN_3_2F(35),
C => CLK,
CE => EN);
R2_PIPE_165_RET_172: FDE port map (
Q => R1IN_3_2F_RETO(36),
D => R1IN_3_2F(36),
C => CLK,
CE => EN);
R2_PIPE_165_RET_173: FDE port map (
Q => R1IN_3_2F_RETO(37),
D => R1IN_3_2F(37),
C => CLK,
CE => EN);
R2_PIPE_165_RET_174: FDE port map (
Q => R1IN_3_2F_RETO(38),
D => R1IN_3_2F(38),
C => CLK,
CE => EN);
R2_PIPE_165_RET_175: FDE port map (
Q => R1IN_3_2F_RETO(39),
D => R1IN_3_2F(39),
C => CLK,
CE => EN);
R2_PIPE_165_RET_176: FDE port map (
Q => R1IN_3_2F_RETO(40),
D => R1IN_3_2F(40),
C => CLK,
CE => EN);
R2_PIPE_165_RET_177: FDE port map (
Q => R1IN_3_2F_RETO(41),
D => R1IN_3_2F(41),
C => CLK,
CE => EN);
R2_PIPE_165_RET_178: FDE port map (
Q => R1IN_3_2F_RETO(42),
D => R1IN_3_2F(42),
C => CLK,
CE => EN);
R2_PIPE_165_RET_179: FDE port map (
Q => R1IN_3_2F_RETO(43),
D => R1IN_3_2F(43),
C => CLK,
CE => EN);
R2_PIPE_104_RET_91: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO_0(0),
D => R1IN_4_4_ADD_1F(0),
C => CLK,
CE => EN);
R2_PIPE_104_RET_92: FDE port map (
Q => R1IN_4_4_ADD_2_RETO_0,
D => R1IN_4_4_ADD_2,
C => CLK,
CE => EN);
R2_PIPE_104_RET_93: FDE port map (
Q => R1IN_4_4_1F_RETO(18),
D => R1IN_4_4_1F(18),
C => CLK,
CE => EN);
R2_PIPE_104_RET_94: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(1),
D => R1IN_4_4_ADD_1F(1),
C => CLK,
CE => EN);
R2_PIPE_104_RET_95: FDE port map (
Q => R1IN_4_4_1F_RETO(19),
D => R1IN_4_4_1F(19),
C => CLK,
CE => EN);
R2_PIPE_104_RET_96: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(2),
D => R1IN_4_4_ADD_1F(2),
C => CLK,
CE => EN);
R2_PIPE_104_RET_97: FDE port map (
Q => R1IN_4_4_1F_RETO(20),
D => R1IN_4_4_1F(20),
C => CLK,
CE => EN);
R2_PIPE_104_RET_98: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(3),
D => R1IN_4_4_ADD_1F(3),
C => CLK,
CE => EN);
R2_PIPE_104_RET_99: FDE port map (
Q => R1IN_4_4_1F_RETO(21),
D => R1IN_4_4_1F(21),
C => CLK,
CE => EN);
R2_PIPE_104_RET_100: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(4),
D => R1IN_4_4_ADD_1F(4),
C => CLK,
CE => EN);
R2_PIPE_104_RET_101: FDE port map (
Q => R1IN_4_4_1F_RETO(22),
D => R1IN_4_4_1F(22),
C => CLK,
CE => EN);
R2_PIPE_104_RET_102: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(5),
D => R1IN_4_4_ADD_1F(5),
C => CLK,
CE => EN);
R2_PIPE_104_RET_103: FDE port map (
Q => R1IN_4_4_1F_RETO(23),
D => R1IN_4_4_1F(23),
C => CLK,
CE => EN);
R2_PIPE_104_RET_104: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(6),
D => R1IN_4_4_ADD_1F(6),
C => CLK,
CE => EN);
R2_PIPE_104_RET_105: FDE port map (
Q => R1IN_4_4_1F_RETO(24),
D => R1IN_4_4_1F(24),
C => CLK,
CE => EN);
R2_PIPE_104_RET_106: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(7),
D => R1IN_4_4_ADD_1F(7),
C => CLK,
CE => EN);
R2_PIPE_104_RET_107: FDE port map (
Q => R1IN_4_4_1F_RETO(25),
D => R1IN_4_4_1F(25),
C => CLK,
CE => EN);
R2_PIPE_104_RET_108: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(8),
D => R1IN_4_4_ADD_1F(8),
C => CLK,
CE => EN);
R2_PIPE_104_RET_109: FDE port map (
Q => R1IN_4_4_1F_RETO(26),
D => R1IN_4_4_1F(26),
C => CLK,
CE => EN);
R2_PIPE_104_RET_110: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(9),
D => R1IN_4_4_ADD_1F(9),
C => CLK,
CE => EN);
R2_PIPE_104_RET_111: FDE port map (
Q => R1IN_4_4_1F_RETO(27),
D => R1IN_4_4_1F(27),
C => CLK,
CE => EN);
R2_PIPE_104_RET_112: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(10),
D => R1IN_4_4_ADD_1F(10),
C => CLK,
CE => EN);
R2_PIPE_104_RET_113: FDE port map (
Q => R1IN_4_4_1F_RETO(28),
D => R1IN_4_4_1F(28),
C => CLK,
CE => EN);
R2_PIPE_104_RET_114: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(11),
D => R1IN_4_4_ADD_1F(11),
C => CLK,
CE => EN);
R2_PIPE_104_RET_115: FDE port map (
Q => R1IN_4_4_1F_RETO(29),
D => R1IN_4_4_1F(29),
C => CLK,
CE => EN);
R2_PIPE_104_RET_116: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(12),
D => R1IN_4_4_ADD_1F(12),
C => CLK,
CE => EN);
R2_PIPE_104_RET_117: FDE port map (
Q => R1IN_4_4_1F_RETO(30),
D => R1IN_4_4_1F(30),
C => CLK,
CE => EN);
R2_PIPE_104_RET_118: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(13),
D => R1IN_4_4_ADD_1F(13),
C => CLK,
CE => EN);
R2_PIPE_104_RET_119: FDE port map (
Q => R1IN_4_4_1F_RETO(31),
D => R1IN_4_4_1F(31),
C => CLK,
CE => EN);
R2_PIPE_104_RET_120: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(14),
D => R1IN_4_4_ADD_1F(14),
C => CLK,
CE => EN);
R2_PIPE_104_RET_121: FDE port map (
Q => R1IN_4_4_1F_RETO(32),
D => R1IN_4_4_1F(32),
C => CLK,
CE => EN);
R2_PIPE_104_RET_122: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(15),
D => R1IN_4_4_ADD_1F(15),
C => CLK,
CE => EN);
R2_PIPE_104_RET_123: FDE port map (
Q => R1IN_4_4_1F_RETO(33),
D => R1IN_4_4_1F(33),
C => CLK,
CE => EN);
R2_PIPE_104_RET_124: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(16),
D => R1IN_4_4_ADD_1F(16),
C => CLK,
CE => EN);
R2_PIPE_104_RET_126: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(17),
D => R1IN_4_4_ADD_1F(17),
C => CLK,
CE => EN);
R2_PIPE_104_RET_128: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(18),
D => R1IN_4_4_ADD_1F(18),
C => CLK,
CE => EN);
R2_PIPE_104_RET_130: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(19),
D => R1IN_4_4_ADD_1F(19),
C => CLK,
CE => EN);
R2_PIPE_104_RET_132: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(20),
D => R1IN_4_4_ADD_1F(20),
C => CLK,
CE => EN);
R2_PIPE_104_RET_134: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(21),
D => R1IN_4_4_ADD_1F(21),
C => CLK,
CE => EN);
R2_PIPE_104_RET_136: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(22),
D => R1IN_4_4_ADD_1F(22),
C => CLK,
CE => EN);
R2_PIPE_104_RET_138: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(23),
D => R1IN_4_4_ADD_1F(23),
C => CLK,
CE => EN);
R2_PIPE_104_RET_140: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(24),
D => R1IN_4_4_ADD_1F(24),
C => CLK,
CE => EN);
R2_PIPE_104_RET_142: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(25),
D => R1IN_4_4_ADD_1F(25),
C => CLK,
CE => EN);
R2_PIPE_104_RET_144: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(26),
D => R1IN_4_4_ADD_1F(26),
C => CLK,
CE => EN);
R2_PIPE_104_RET_146: FDE port map (
Q => R1IN_4_4_ADD_1F_RETO(27),
D => R1IN_4_4_ADD_1F(27),
C => CLK,
CE => EN);
R2_PIPE_165_RET_60: FDE port map (
Q => R1IN_2_ADD_1_RETO,
D => R1IN_2_ADD_1,
C => CLK,
CE => EN);
R2_PIPE_165_RET_181: FDE port map (
Q => R1IN_2_2F_RETO(1),
D => R1IN_2_2F(1),
C => CLK,
CE => EN);
R2_PIPE_165_RET_183: FDE port map (
Q => R1IN_2_2F_RETO(2),
D => R1IN_2_2F(2),
C => CLK,
CE => EN);
R2_PIPE_165_RET_185: FDE port map (
Q => R1IN_2_2F_RETO(3),
D => R1IN_2_2F(3),
C => CLK,
CE => EN);
R2_PIPE_165_RET_187: FDE port map (
Q => R1IN_2_2F_RETO(4),
D => R1IN_2_2F(4),
C => CLK,
CE => EN);
R2_PIPE_165_RET_189: FDE port map (
Q => R1IN_2_2F_RETO(5),
D => R1IN_2_2F(5),
C => CLK,
CE => EN);
R2_PIPE_165_RET_191: FDE port map (
Q => R1IN_2_2F_RETO(6),
D => R1IN_2_2F(6),
C => CLK,
CE => EN);
R2_PIPE_165_RET_193: FDE port map (
Q => R1IN_2_2F_RETO(7),
D => R1IN_2_2F(7),
C => CLK,
CE => EN);
R2_PIPE_165_RET_195: FDE port map (
Q => R1IN_2_2F_RETO(8),
D => R1IN_2_2F(8),
C => CLK,
CE => EN);
R2_PIPE_165_RET_197: FDE port map (
Q => R1IN_2_2F_RETO(9),
D => R1IN_2_2F(9),
C => CLK,
CE => EN);
R2_PIPE_165_RET_199: FDE port map (
Q => R1IN_2_2F_RETO(10),
D => R1IN_2_2F(10),
C => CLK,
CE => EN);
R2_PIPE_165_RET_201: FDE port map (
Q => R1IN_2_2F_RETO(11),
D => R1IN_2_2F(11),
C => CLK,
CE => EN);
R2_PIPE_165_RET_203: FDE port map (
Q => R1IN_2_2F_RETO(12),
D => R1IN_2_2F(12),
C => CLK,
CE => EN);
R2_PIPE_165_RET_205: FDE port map (
Q => R1IN_2_2F_RETO(13),
D => R1IN_2_2F(13),
C => CLK,
CE => EN);
R2_PIPE_165_RET_207: FDE port map (
Q => R1IN_2_2F_RETO(14),
D => R1IN_2_2F(14),
C => CLK,
CE => EN);
R2_PIPE_165_RET_209: FDE port map (
Q => R1IN_2_2F_RETO(15),
D => R1IN_2_2F(15),
C => CLK,
CE => EN);
R2_PIPE_165_RET_211: FDE port map (
Q => R1IN_2_2F_RETO(16),
D => R1IN_2_2F(16),
C => CLK,
CE => EN);
R2_PIPE_165_RET_212: FDE port map (
Q => R1IN_2_2F_RETO(17),
D => R1IN_2_2F(17),
C => CLK,
CE => EN);
R2_PIPE_165_RET_213: FDE port map (
Q => R1IN_2_2F_RETO(18),
D => R1IN_2_2F(18),
C => CLK,
CE => EN);
R2_PIPE_165_RET_214: FDE port map (
Q => R1IN_2_2F_RETO(19),
D => R1IN_2_2F(19),
C => CLK,
CE => EN);
R2_PIPE_165_RET_215: FDE port map (
Q => R1IN_2_2F_RETO(20),
D => R1IN_2_2F(20),
C => CLK,
CE => EN);
R2_PIPE_165_RET_216: FDE port map (
Q => R1IN_2_2F_RETO(21),
D => R1IN_2_2F(21),
C => CLK,
CE => EN);
R2_PIPE_165_RET_217: FDE port map (
Q => R1IN_2_2F_RETO(22),
D => R1IN_2_2F(22),
C => CLK,
CE => EN);
R2_PIPE_165_RET_218: FDE port map (
Q => R1IN_2_2F_RETO(23),
D => R1IN_2_2F(23),
C => CLK,
CE => EN);
R2_PIPE_165_RET_219: FDE port map (
Q => R1IN_2_2F_RETO(24),
D => R1IN_2_2F(24),
C => CLK,
CE => EN);
R2_PIPE_165_RET_220: FDE port map (
Q => R1IN_2_2F_RETO(25),
D => R1IN_2_2F(25),
C => CLK,
CE => EN);
R2_PIPE_165_RET_221: FDE port map (
Q => R1IN_2_2F_RETO(26),
D => R1IN_2_2F(26),
C => CLK,
CE => EN);
R2_PIPE_165_RET_222: FDE port map (
Q => R1IN_2_2F_RETO(27),
D => R1IN_2_2F(27),
C => CLK,
CE => EN);
R2_PIPE_165_RET_223: FDE port map (
Q => R1IN_2_2F_RETO(28),
D => R1IN_2_2F(28),
C => CLK,
CE => EN);
R2_PIPE_165_RET_224: FDE port map (
Q => R1IN_2_2F_RETO(29),
D => R1IN_2_2F(29),
C => CLK,
CE => EN);
R2_PIPE_165_RET_225: FDE port map (
Q => R1IN_2_2F_RETO(30),
D => R1IN_2_2F(30),
C => CLK,
CE => EN);
R2_PIPE_165_RET_226: FDE port map (
Q => R1IN_2_2F_RETO(31),
D => R1IN_2_2F(31),
C => CLK,
CE => EN);
R2_PIPE_165_RET_227: FDE port map (
Q => R1IN_2_2F_RETO(32),
D => R1IN_2_2F(32),
C => CLK,
CE => EN);
R2_PIPE_165_RET_228: FDE port map (
Q => R1IN_2_2F_RETO(33),
D => R1IN_2_2F(33),
C => CLK,
CE => EN);
R2_PIPE_165_RET_229: FDE port map (
Q => R1IN_2_2F_RETO(34),
D => R1IN_2_2F(34),
C => CLK,
CE => EN);
R2_PIPE_165_RET_230: FDE port map (
Q => R1IN_2_2F_RETO(35),
D => R1IN_2_2F(35),
C => CLK,
CE => EN);
R2_PIPE_165_RET_231: FDE port map (
Q => R1IN_2_2F_RETO(36),
D => R1IN_2_2F(36),
C => CLK,
CE => EN);
R2_PIPE_165_RET_232: FDE port map (
Q => R1IN_2_2F_RETO(37),
D => R1IN_2_2F(37),
C => CLK,
CE => EN);
R2_PIPE_165_RET_233: FDE port map (
Q => R1IN_2_2F_RETO(38),
D => R1IN_2_2F(38),
C => CLK,
CE => EN);
R2_PIPE_165_RET_234: FDE port map (
Q => R1IN_2_2F_RETO(39),
D => R1IN_2_2F(39),
C => CLK,
CE => EN);
R2_PIPE_165_RET_235: FDE port map (
Q => R1IN_2_2F_RETO(40),
D => R1IN_2_2F(40),
C => CLK,
CE => EN);
R2_PIPE_165_RET_236: FDE port map (
Q => R1IN_2_2F_RETO(41),
D => R1IN_2_2F(41),
C => CLK,
CE => EN);
R2_PIPE_165_RET_237: FDE port map (
Q => R1IN_2_2F_RETO(42),
D => R1IN_2_2F(42),
C => CLK,
CE => EN);
R2_PIPE_165_RET_238: FDE port map (
Q => R1IN_2_2F_RETO(43),
D => R1IN_2_2F(43),
C => CLK,
CE => EN);
R2_PIPE_104_RET_0: FDE port map (
Q => R1IN_4_3F_RETO(0),
D => R1IN_4_3F(0),
C => CLK,
CE => EN);
R2_PIPE_104_RET_62: FDE port map (
Q => NN_4,
D => R1IN_4_ADD_1,
C => CLK,
CE => EN);
R2_PIPE_104_RET_125: FDE port map (
Q => R1IN_4_2F_RETO(1),
D => R1IN_4_2F(1),
C => CLK,
CE => EN);
R2_PIPE_104_RET_127: FDE port map (
Q => R1IN_4_3F_RETO(1),
D => R1IN_4_3F(1),
C => CLK,
CE => EN);
R2_PIPE_104_RET_147: FDE port map (
Q => R1IN_4_2F_RETO(2),
D => R1IN_4_2F(2),
C => CLK,
CE => EN);
R2_PIPE_104_RET_148: FDE port map (
Q => R1IN_4_3F_RETO(2),
D => R1IN_4_3F(2),
C => CLK,
CE => EN);
R2_PIPE_104_RET_149: FDE port map (
Q => R1IN_4_2F_RETO(3),
D => R1IN_4_2F(3),
C => CLK,
CE => EN);
R2_PIPE_104_RET_150: FDE port map (
Q => R1IN_4_3F_RETO(3),
D => R1IN_4_3F(3),
C => CLK,
CE => EN);
R2_PIPE_104_RET_151: FDE port map (
Q => R1IN_4_2F_RETO(4),
D => R1IN_4_2F(4),
C => CLK,
CE => EN);
R2_PIPE_104_RET_152: FDE port map (
Q => R1IN_4_3F_RETO(4),
D => R1IN_4_3F(4),
C => CLK,
CE => EN);
R2_PIPE_104_RET_153: FDE port map (
Q => R1IN_4_2F_RETO(5),
D => R1IN_4_2F(5),
C => CLK,
CE => EN);
R2_PIPE_104_RET_154: FDE port map (
Q => R1IN_4_3F_RETO(5),
D => R1IN_4_3F(5),
C => CLK,
CE => EN);
R2_PIPE_104_RET_155: FDE port map (
Q => R1IN_4_2F_RETO(6),
D => R1IN_4_2F(6),
C => CLK,
CE => EN);
R2_PIPE_104_RET_156: FDE port map (
Q => R1IN_4_3F_RETO(6),
D => R1IN_4_3F(6),
C => CLK,
CE => EN);
R2_PIPE_104_RET_157: FDE port map (
Q => R1IN_4_2F_RETO(7),
D => R1IN_4_2F(7),
C => CLK,
CE => EN);
R2_PIPE_104_RET_158: FDE port map (
Q => R1IN_4_3F_RETO(7),
D => R1IN_4_3F(7),
C => CLK,
CE => EN);
R2_PIPE_104_RET_159: FDE port map (
Q => R1IN_4_2F_RETO(8),
D => R1IN_4_2F(8),
C => CLK,
CE => EN);
R2_PIPE_104_RET_160: FDE port map (
Q => R1IN_4_3F_RETO(8),
D => R1IN_4_3F(8),
C => CLK,
CE => EN);
R2_PIPE_104_RET_161: FDE port map (
Q => R1IN_4_2F_RETO(9),
D => R1IN_4_2F(9),
C => CLK,
CE => EN);
R2_PIPE_104_RET_162: FDE port map (
Q => R1IN_4_3F_RETO(9),
D => R1IN_4_3F(9),
C => CLK,
CE => EN);
R2_PIPE_104_RET_163: FDE port map (
Q => R1IN_4_2F_RETO(10),
D => R1IN_4_2F(10),
C => CLK,
CE => EN);
R2_PIPE_104_RET_164: FDE port map (
Q => R1IN_4_3F_RETO(10),
D => R1IN_4_3F(10),
C => CLK,
CE => EN);
R2_PIPE_104_RET_165: FDE port map (
Q => R1IN_4_2F_RETO(11),
D => R1IN_4_2F(11),
C => CLK,
CE => EN);
R2_PIPE_104_RET_166: FDE port map (
Q => R1IN_4_3F_RETO(11),
D => R1IN_4_3F(11),
C => CLK,
CE => EN);
R2_PIPE_104_RET_167: FDE port map (
Q => R1IN_4_2F_RETO(12),
D => R1IN_4_2F(12),
C => CLK,
CE => EN);
R2_PIPE_104_RET_168: FDE port map (
Q => R1IN_4_3F_RETO(12),
D => R1IN_4_3F(12),
C => CLK,
CE => EN);
R2_PIPE_104_RET_169: FDE port map (
Q => R1IN_4_2F_RETO(13),
D => R1IN_4_2F(13),
C => CLK,
CE => EN);
R2_PIPE_104_RET_170: FDE port map (
Q => R1IN_4_3F_RETO(13),
D => R1IN_4_3F(13),
C => CLK,
CE => EN);
R2_PIPE_104_RET_171: FDE port map (
Q => R1IN_4_2F_RETO(14),
D => R1IN_4_2F(14),
C => CLK,
CE => EN);
R2_PIPE_104_RET_172: FDE port map (
Q => R1IN_4_3F_RETO(14),
D => R1IN_4_3F(14),
C => CLK,
CE => EN);
R2_PIPE_104_RET_173: FDE port map (
Q => R1IN_4_2F_RETO(15),
D => R1IN_4_2F(15),
C => CLK,
CE => EN);
R2_PIPE_104_RET_174: FDE port map (
Q => R1IN_4_3F_RETO(15),
D => R1IN_4_3F(15),
C => CLK,
CE => EN);
R2_PIPE_104_RET_175: FDE port map (
Q => R1IN_4_2F_RETO(16),
D => R1IN_4_2F(16),
C => CLK,
CE => EN);
R2_PIPE_104_RET_176: FDE port map (
Q => R1IN_4_3F_RETO(16),
D => R1IN_4_3F(16),
C => CLK,
CE => EN);
R2_PIPE_104_RET_177: FDE port map (
Q => R1IN_4_2F_RETO(17),
D => R1IN_4_2F(17),
C => CLK,
CE => EN);
R2_PIPE_104_RET_178: FDE port map (
Q => R1IN_4_3F_RETO(17),
D => R1IN_4_3F(17),
C => CLK,
CE => EN);
R2_PIPE_104_RET_179: FDE port map (
Q => R1IN_4_2F_RETO(18),
D => R1IN_4_2F(18),
C => CLK,
CE => EN);
R2_PIPE_104_RET_180: FDE port map (
Q => R1IN_4_3F_RETO(18),
D => R1IN_4_3F(18),
C => CLK,
CE => EN);
R2_PIPE_104_RET_181: FDE port map (
Q => R1IN_4_2F_RETO(19),
D => R1IN_4_2F(19),
C => CLK,
CE => EN);
R2_PIPE_104_RET_182: FDE port map (
Q => R1IN_4_3F_RETO(19),
D => R1IN_4_3F(19),
C => CLK,
CE => EN);
R2_PIPE_104_RET_183: FDE port map (
Q => R1IN_4_2F_RETO(20),
D => R1IN_4_2F(20),
C => CLK,
CE => EN);
R2_PIPE_104_RET_184: FDE port map (
Q => R1IN_4_3F_RETO(20),
D => R1IN_4_3F(20),
C => CLK,
CE => EN);
R2_PIPE_104_RET_185: FDE port map (
Q => R1IN_4_2F_RETO(21),
D => R1IN_4_2F(21),
C => CLK,
CE => EN);
R2_PIPE_104_RET_186: FDE port map (
Q => R1IN_4_3F_RETO(21),
D => R1IN_4_3F(21),
C => CLK,
CE => EN);
R2_PIPE_104_RET_187: FDE port map (
Q => R1IN_4_2F_RETO(22),
D => R1IN_4_2F(22),
C => CLK,
CE => EN);
R2_PIPE_104_RET_188: FDE port map (
Q => R1IN_4_3F_RETO(22),
D => R1IN_4_3F(22),
C => CLK,
CE => EN);
R2_PIPE_104_RET_189: FDE port map (
Q => R1IN_4_2F_RETO(23),
D => R1IN_4_2F(23),
C => CLK,
CE => EN);
R2_PIPE_104_RET_190: FDE port map (
Q => R1IN_4_3F_RETO(23),
D => R1IN_4_3F(23),
C => CLK,
CE => EN);
R2_PIPE_104_RET_191: FDE port map (
Q => R1IN_4_2F_RETO(24),
D => R1IN_4_2F(24),
C => CLK,
CE => EN);
R2_PIPE_104_RET_192: FDE port map (
Q => R1IN_4_3F_RETO(24),
D => R1IN_4_3F(24),
C => CLK,
CE => EN);
R2_PIPE_104_RET_193: FDE port map (
Q => R1IN_4_2F_RETO(25),
D => R1IN_4_2F(25),
C => CLK,
CE => EN);
R2_PIPE_104_RET_194: FDE port map (
Q => R1IN_4_3F_RETO(25),
D => R1IN_4_3F(25),
C => CLK,
CE => EN);
R2_PIPE_104_RET_195: FDE port map (
Q => R1IN_4_2F_RETO(26),
D => R1IN_4_2F(26),
C => CLK,
CE => EN);
R2_PIPE_104_RET_196: FDE port map (
Q => R1IN_4_3F_RETO(26),
D => R1IN_4_3F(26),
C => CLK,
CE => EN);
R2_PIPE_104_RET_197: FDE port map (
Q => R1IN_4_2F_RETO(27),
D => R1IN_4_2F(27),
C => CLK,
CE => EN);
R2_PIPE_104_RET_198: FDE port map (
Q => R1IN_4_3F_RETO(27),
D => R1IN_4_3F(27),
C => CLK,
CE => EN);
R2_PIPE_104_RET_199: FDE port map (
Q => R1IN_4_2F_RETO(28),
D => R1IN_4_2F(28),
C => CLK,
CE => EN);
R2_PIPE_104_RET_200: FDE port map (
Q => R1IN_4_3F_RETO(28),
D => R1IN_4_3F(28),
C => CLK,
CE => EN);
R2_PIPE_104_RET_201: FDE port map (
Q => R1IN_4_2F_RETO(29),
D => R1IN_4_2F(29),
C => CLK,
CE => EN);
R2_PIPE_104_RET_202: FDE port map (
Q => R1IN_4_3F_RETO(29),
D => R1IN_4_3F(29),
C => CLK,
CE => EN);
R2_PIPE_104_RET_203: FDE port map (
Q => R1IN_4_2F_RETO(30),
D => R1IN_4_2F(30),
C => CLK,
CE => EN);
R2_PIPE_104_RET_204: FDE port map (
Q => R1IN_4_3F_RETO(30),
D => R1IN_4_3F(30),
C => CLK,
CE => EN);
R2_PIPE_104_RET_205: FDE port map (
Q => R1IN_4_2F_RETO(31),
D => R1IN_4_2F(31),
C => CLK,
CE => EN);
R2_PIPE_104_RET_206: FDE port map (
Q => R1IN_4_3F_RETO(31),
D => R1IN_4_3F(31),
C => CLK,
CE => EN);
R2_PIPE_104_RET_207: FDE port map (
Q => R1IN_4_2F_RETO(32),
D => R1IN_4_2F(32),
C => CLK,
CE => EN);
R2_PIPE_104_RET_208: FDE port map (
Q => R1IN_4_3F_RETO(32),
D => R1IN_4_3F(32),
C => CLK,
CE => EN);
R2_PIPE_104_RET_209: FDE port map (
Q => R1IN_4_2F_RETO(33),
D => R1IN_4_2F(33),
C => CLK,
CE => EN);
R2_PIPE_104_RET_210: FDE port map (
Q => R1IN_4_3F_RETO(33),
D => R1IN_4_3F(33),
C => CLK,
CE => EN);
R2_PIPE_104_RET_211: FDE port map (
Q => R1IN_4_2F_RETO(34),
D => R1IN_4_2F(34),
C => CLK,
CE => EN);
R2_PIPE_104_RET_212: FDE port map (
Q => R1IN_4_3F_RETO(34),
D => R1IN_4_3F(34),
C => CLK,
CE => EN);
R2_PIPE_104_RET_213: FDE port map (
Q => R1IN_4_2F_RETO(35),
D => R1IN_4_2F(35),
C => CLK,
CE => EN);
R2_PIPE_104_RET_214: FDE port map (
Q => R1IN_4_3F_RETO(35),
D => R1IN_4_3F(35),
C => CLK,
CE => EN);
R2_PIPE_104_RET_215: FDE port map (
Q => R1IN_4_2F_RETO(36),
D => R1IN_4_2F(36),
C => CLK,
CE => EN);
R2_PIPE_104_RET_216: FDE port map (
Q => R1IN_4_3F_RETO(36),
D => R1IN_4_3F(36),
C => CLK,
CE => EN);
R2_PIPE_104_RET_217: FDE port map (
Q => R1IN_4_2F_RETO(37),
D => R1IN_4_2F(37),
C => CLK,
CE => EN);
R2_PIPE_104_RET_218: FDE port map (
Q => R1IN_4_3F_RETO(37),
D => R1IN_4_3F(37),
C => CLK,
CE => EN);
R2_PIPE_104_RET_219: FDE port map (
Q => R1IN_4_2F_RETO(38),
D => R1IN_4_2F(38),
C => CLK,
CE => EN);
R2_PIPE_104_RET_220: FDE port map (
Q => R1IN_4_3F_RETO(38),
D => R1IN_4_3F(38),
C => CLK,
CE => EN);
R2_PIPE_104_RET_221: FDE port map (
Q => R1IN_4_2F_RETO(39),
D => R1IN_4_2F(39),
C => CLK,
CE => EN);
R2_PIPE_104_RET_222: FDE port map (
Q => R1IN_4_3F_RETO(39),
D => R1IN_4_3F(39),
C => CLK,
CE => EN);
R2_PIPE_104_RET_223: FDE port map (
Q => R1IN_4_2F_RETO(40),
D => R1IN_4_2F(40),
C => CLK,
CE => EN);
R2_PIPE_104_RET_224: FDE port map (
Q => R1IN_4_3F_RETO(40),
D => R1IN_4_3F(40),
C => CLK,
CE => EN);
R2_PIPE_104_RET_225: FDE port map (
Q => R1IN_4_2F_RETO(41),
D => R1IN_4_2F(41),
C => CLK,
CE => EN);
R2_PIPE_104_RET_226: FDE port map (
Q => R1IN_4_3F_RETO(41),
D => R1IN_4_3F(41),
C => CLK,
CE => EN);
R2_PIPE_104_RET_227: FDE port map (
Q => R1IN_4_2F_RETO(42),
D => R1IN_4_2F(42),
C => CLK,
CE => EN);
R2_PIPE_104_RET_228: FDE port map (
Q => R1IN_4_3F_RETO(42),
D => R1IN_4_3F(42),
C => CLK,
CE => EN);
R2_PIPE_104_RET_229: FDE port map (
Q => R1IN_4_2F_RETO(43),
D => R1IN_4_2F(43),
C => CLK,
CE => EN);
R2_PIPE_104_RET_230: FDE port map (
Q => R1IN_4_3F_RETO(43),
D => R1IN_4_3F(43),
C => CLK,
CE => EN);
R1IN_ADD_1_1_CRY_28_Z5102: MUXCY port map (
DI => R1IN_3(60),
CI => R1IN_ADD_1_1_CRY_27,
S => R1IN_ADD_1_1_AXB_28,
O => R1IN_ADD_1_1_CRY_28);
R1IN_ADD_2_AXB_104_Z5103: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => N_1511,
I1 => N_1556,
I2 => R1IN_4_ADD_2_0_CRY_35,
O => R1IN_ADD_2_AXB_104);
R1IN_4_ADD_1_S_43: XORCY port map (
LI => R1IN_4_ADD_1_AXB_43,
CI => R1IN_4_ADD_1_CRY_42,
O => R1IN_4_ADD_1_RETO(43));
R1IN_4_ADD_1_CRY_43: MUXCY port map (
DI => R1IN_4_2F_RETO(43),
CI => R1IN_4_ADD_1_CRY_42,
S => R1IN_4_ADD_1_AXB_43,
O => R1IN_4_ADD_1_RETO(44));
R1IN_4_ADD_1_CRY_42_Z5160: MUXCY_L port map (
DI => R1IN_4_2F_RETO(42),
CI => R1IN_4_ADD_1_CRY_41,
S => R1IN_4_ADD_1_AXB_42,
LO => R1IN_4_ADD_1_CRY_42);
R1IN_4_ADD_1_CRY_41_Z5161: MUXCY_L port map (
DI => R1IN_4_2F_RETO(41),
CI => R1IN_4_ADD_1_CRY_40,
S => R1IN_4_ADD_1_AXB_41,
LO => R1IN_4_ADD_1_CRY_41);
R1IN_4_ADD_1_S_42: XORCY port map (
LI => R1IN_4_ADD_1_AXB_42,
CI => R1IN_4_ADD_1_CRY_41,
O => R1IN_4_ADD_1_RETO(42));
R1IN_4_ADD_1_CRY_40_Z5163: MUXCY_L port map (
DI => R1IN_4_2F_RETO(40),
CI => R1IN_4_ADD_1_CRY_39,
S => R1IN_4_ADD_1_AXB_40,
LO => R1IN_4_ADD_1_CRY_40);
R1IN_4_ADD_1_S_41: XORCY port map (
LI => R1IN_4_ADD_1_AXB_41,
CI => R1IN_4_ADD_1_CRY_40,
O => R1IN_4_ADD_1_RETO(41));
R1IN_4_ADD_1_CRY_39_Z5165: MUXCY_L port map (
DI => R1IN_4_2F_RETO(39),
CI => R1IN_4_ADD_1_CRY_38,
S => R1IN_4_ADD_1_AXB_39,
LO => R1IN_4_ADD_1_CRY_39);
R1IN_4_ADD_1_S_40: XORCY port map (
LI => R1IN_4_ADD_1_AXB_40,
CI => R1IN_4_ADD_1_CRY_39,
O => R1IN_4_ADD_1_RETO(40));
R1IN_4_ADD_1_CRY_38_Z5167: MUXCY_L port map (
DI => R1IN_4_2F_RETO(38),
CI => R1IN_4_ADD_1_CRY_37,
S => R1IN_4_ADD_1_AXB_38,
LO => R1IN_4_ADD_1_CRY_38);
R1IN_4_ADD_1_S_39: XORCY port map (
LI => R1IN_4_ADD_1_AXB_39,
CI => R1IN_4_ADD_1_CRY_38,
O => R1IN_4_ADD_1_RETO(39));
R1IN_4_ADD_1_CRY_37_Z5169: MUXCY_L port map (
DI => R1IN_4_2F_RETO(37),
CI => R1IN_4_ADD_1_CRY_36,
S => R1IN_4_ADD_1_AXB_37,
LO => R1IN_4_ADD_1_CRY_37);
R1IN_4_ADD_1_S_38: XORCY port map (
LI => R1IN_4_ADD_1_AXB_38,
CI => R1IN_4_ADD_1_CRY_37,
O => R1IN_4_ADD_1_RETO(38));
R1IN_4_ADD_1_CRY_36_Z5171: MUXCY_L port map (
DI => R1IN_4_2F_RETO(36),
CI => R1IN_4_ADD_1_CRY_35,
S => R1IN_4_ADD_1_AXB_36,
LO => R1IN_4_ADD_1_CRY_36);
R1IN_4_ADD_1_S_37: XORCY port map (
LI => R1IN_4_ADD_1_AXB_37,
CI => R1IN_4_ADD_1_CRY_36,
O => R1IN_4_ADD_1_RETO(37));
R1IN_4_ADD_1_CRY_35_Z5173: MUXCY_L port map (
DI => R1IN_4_2F_RETO(35),
CI => R1IN_4_ADD_1_CRY_34,
S => R1IN_4_ADD_1_AXB_35,
LO => R1IN_4_ADD_1_CRY_35);
R1IN_4_ADD_1_S_36: XORCY port map (
LI => R1IN_4_ADD_1_AXB_36,
CI => R1IN_4_ADD_1_CRY_35,
O => R1IN_4_ADD_2_1_RETO);
R1IN_4_ADD_1_CRY_34_Z5175: MUXCY_L port map (
DI => R1IN_4_2F_RETO(34),
CI => R1IN_4_ADD_1_CRY_33,
S => R1IN_4_ADD_1_AXB_34,
LO => R1IN_4_ADD_1_CRY_34);
R1IN_4_ADD_1_S_35: XORCY port map (
LI => R1IN_4_ADD_1_AXB_35,
CI => R1IN_4_ADD_1_CRY_34,
O => R1IN_4_ADD_1_RETO(35));
R1IN_4_ADD_1_CRY_33_Z5177: MUXCY_L port map (
DI => R1IN_4_2F_RETO(33),
CI => R1IN_4_ADD_1_CRY_32,
S => R1IN_4_ADD_1_AXB_33,
LO => R1IN_4_ADD_1_CRY_33);
R1IN_4_ADD_1_S_34: XORCY port map (
LI => R1IN_4_ADD_1_AXB_34,
CI => R1IN_4_ADD_1_CRY_33,
O => R1IN_4_ADD_1_RETO(34));
R1IN_4_ADD_1_CRY_32_Z5179: MUXCY_L port map (
DI => R1IN_4_2F_RETO(32),
CI => R1IN_4_ADD_1_CRY_31,
S => R1IN_4_ADD_1_AXB_32,
LO => R1IN_4_ADD_1_CRY_32);
R1IN_4_ADD_1_S_33: XORCY port map (
LI => R1IN_4_ADD_1_AXB_33,
CI => R1IN_4_ADD_1_CRY_32,
O => R1IN_4_ADD_1_RETO(33));
R1IN_4_ADD_1_CRY_31_Z5181: MUXCY_L port map (
DI => R1IN_4_2F_RETO(31),
CI => R1IN_4_ADD_1_CRY_30,
S => R1IN_4_ADD_1_AXB_31,
LO => R1IN_4_ADD_1_CRY_31);
R1IN_4_ADD_1_S_32: XORCY port map (
LI => R1IN_4_ADD_1_AXB_32,
CI => R1IN_4_ADD_1_CRY_31,
O => R1IN_4_ADD_1_RETO(32));
R1IN_4_ADD_1_CRY_30_Z5183: MUXCY_L port map (
DI => R1IN_4_2F_RETO(30),
CI => R1IN_4_ADD_1_CRY_29,
S => R1IN_4_ADD_1_AXB_30,
LO => R1IN_4_ADD_1_CRY_30);
R1IN_4_ADD_1_S_31: XORCY port map (
LI => R1IN_4_ADD_1_AXB_31,
CI => R1IN_4_ADD_1_CRY_30,
O => R1IN_4_ADD_1_RETO(31));
R1IN_4_ADD_1_CRY_29_Z5185: MUXCY_L port map (
DI => R1IN_4_2F_RETO(29),
CI => R1IN_4_ADD_1_CRY_28,
S => R1IN_4_ADD_1_AXB_29,
LO => R1IN_4_ADD_1_CRY_29);
R1IN_4_ADD_1_S_30: XORCY port map (
LI => R1IN_4_ADD_1_AXB_30,
CI => R1IN_4_ADD_1_CRY_29,
O => R1IN_4_ADD_1_RETO(30));
R1IN_4_ADD_1_CRY_28_Z5187: MUXCY_L port map (
DI => R1IN_4_2F_RETO(28),
CI => R1IN_4_ADD_1_CRY_27,
S => R1IN_4_ADD_1_AXB_28,
LO => R1IN_4_ADD_1_CRY_28);
R1IN_4_ADD_1_S_29: XORCY port map (
LI => R1IN_4_ADD_1_AXB_29,
CI => R1IN_4_ADD_1_CRY_28,
O => R1IN_4_ADD_1_RETO(29));
R1IN_4_ADD_1_CRY_27_Z5189: MUXCY_L port map (
DI => R1IN_4_2F_RETO(27),
CI => R1IN_4_ADD_1_CRY_26,
S => R1IN_4_ADD_1_AXB_27,
LO => R1IN_4_ADD_1_CRY_27);
R1IN_4_ADD_1_S_28: XORCY port map (
LI => R1IN_4_ADD_1_AXB_28,
CI => R1IN_4_ADD_1_CRY_27,
O => R1IN_4_ADD_1_RETO(28));
R1IN_4_ADD_1_CRY_26_Z5191: MUXCY_L port map (
DI => R1IN_4_2F_RETO(26),
CI => R1IN_4_ADD_1_CRY_25,
S => R1IN_4_ADD_1_AXB_26,
LO => R1IN_4_ADD_1_CRY_26);
R1IN_4_ADD_1_S_27: XORCY port map (
LI => R1IN_4_ADD_1_AXB_27,
CI => R1IN_4_ADD_1_CRY_26,
O => R1IN_4_ADD_1_RETO(27));
R1IN_4_ADD_1_CRY_25_Z5193: MUXCY_L port map (
DI => R1IN_4_2F_RETO(25),
CI => R1IN_4_ADD_1_CRY_24,
S => R1IN_4_ADD_1_AXB_25,
LO => R1IN_4_ADD_1_CRY_25);
R1IN_4_ADD_1_S_26: XORCY port map (
LI => R1IN_4_ADD_1_AXB_26,
CI => R1IN_4_ADD_1_CRY_25,
O => R1IN_4_ADD_1_RETO(26));
R1IN_4_ADD_1_CRY_24_Z5195: MUXCY_L port map (
DI => R1IN_4_2F_RETO(24),
CI => R1IN_4_ADD_1_CRY_23,
S => R1IN_4_ADD_1_AXB_24,
LO => R1IN_4_ADD_1_CRY_24);
R1IN_4_ADD_1_S_25: XORCY port map (
LI => R1IN_4_ADD_1_AXB_25,
CI => R1IN_4_ADD_1_CRY_24,
O => R1IN_4_ADD_1_RETO(25));
R1IN_4_ADD_1_CRY_23_Z5197: MUXCY_L port map (
DI => R1IN_4_2F_RETO(23),
CI => R1IN_4_ADD_1_CRY_22,
S => R1IN_4_ADD_1_AXB_23,
LO => R1IN_4_ADD_1_CRY_23);
R1IN_4_ADD_1_S_24: XORCY port map (
LI => R1IN_4_ADD_1_AXB_24,
CI => R1IN_4_ADD_1_CRY_23,
O => R1IN_4_ADD_1_RETO(24));
R1IN_4_ADD_1_CRY_22_Z5199: MUXCY_L port map (
DI => R1IN_4_2F_RETO(22),
CI => R1IN_4_ADD_1_CRY_21,
S => R1IN_4_ADD_1_AXB_22,
LO => R1IN_4_ADD_1_CRY_22);
R1IN_4_ADD_1_S_23: XORCY port map (
LI => R1IN_4_ADD_1_AXB_23,
CI => R1IN_4_ADD_1_CRY_22,
O => R1IN_4_ADD_1_RETO(23));
R1IN_4_ADD_1_CRY_21_Z5201: MUXCY_L port map (
DI => R1IN_4_2F_RETO(21),
CI => R1IN_4_ADD_1_CRY_20,
S => R1IN_4_ADD_1_AXB_21,
LO => R1IN_4_ADD_1_CRY_21);
R1IN_4_ADD_1_S_22: XORCY port map (
LI => R1IN_4_ADD_1_AXB_22,
CI => R1IN_4_ADD_1_CRY_21,
O => R1IN_4_ADD_1_RETO(22));
R1IN_4_ADD_1_CRY_20_Z5203: MUXCY_L port map (
DI => R1IN_4_2F_RETO(20),
CI => R1IN_4_ADD_1_CRY_19,
S => R1IN_4_ADD_1_AXB_20,
LO => R1IN_4_ADD_1_CRY_20);
R1IN_4_ADD_1_S_21: XORCY port map (
LI => R1IN_4_ADD_1_AXB_21,
CI => R1IN_4_ADD_1_CRY_20,
O => R1IN_4_ADD_1_RETO(21));
R1IN_4_ADD_1_CRY_19_Z5205: MUXCY_L port map (
DI => R1IN_4_2F_RETO(19),
CI => R1IN_4_ADD_1_CRY_18,
S => R1IN_4_ADD_1_AXB_19,
LO => R1IN_4_ADD_1_CRY_19);
R1IN_4_ADD_1_S_20: XORCY port map (
LI => R1IN_4_ADD_1_AXB_20,
CI => R1IN_4_ADD_1_CRY_19,
O => R1IN_4_ADD_1_RETO(20));
R1IN_4_ADD_1_CRY_18_Z5207: MUXCY_L port map (
DI => R1IN_4_2F_RETO(18),
CI => R1IN_4_ADD_1_CRY_17,
S => R1IN_4_ADD_1_AXB_18,
LO => R1IN_4_ADD_1_CRY_18);
R1IN_4_ADD_1_S_19: XORCY port map (
LI => R1IN_4_ADD_1_AXB_19,
CI => R1IN_4_ADD_1_CRY_18,
O => R1IN_4_ADD_1_RETO(19));
R1IN_4_ADD_1_CRY_17_Z5209: MUXCY_L port map (
DI => R1IN_4_2F_RETO(17),
CI => R1IN_4_ADD_1_CRY_16,
S => R1IN_4_ADD_1_AXB_17,
LO => R1IN_4_ADD_1_CRY_17);
R1IN_4_ADD_1_S_18: XORCY port map (
LI => R1IN_4_ADD_1_AXB_18,
CI => R1IN_4_ADD_1_CRY_17,
O => R1IN_4_ADD_1_RETO(18));
R1IN_4_ADD_1_CRY_16_Z5211: MUXCY_L port map (
DI => R1IN_4_2F_RETO(16),
CI => R1IN_4_ADD_1_CRY_15,
S => R1IN_4_ADD_1_AXB_16,
LO => R1IN_4_ADD_1_CRY_16);
R1IN_4_ADD_1_S_17: XORCY port map (
LI => R1IN_4_ADD_1_AXB_17,
CI => R1IN_4_ADD_1_CRY_16,
O => R1IN_4_ADD_1_RETO(17));
R1IN_4_ADD_1_CRY_15_Z5213: MUXCY_L port map (
DI => R1IN_4_2F_RETO(15),
CI => R1IN_4_ADD_1_CRY_14,
S => R1IN_4_ADD_1_AXB_15,
LO => R1IN_4_ADD_1_CRY_15);
R1IN_4_ADD_1_S_16: XORCY port map (
LI => R1IN_4_ADD_1_AXB_16,
CI => R1IN_4_ADD_1_CRY_15,
O => R1IN_4_ADD_1_RETO(16));
R1IN_4_ADD_1_CRY_14_Z5215: MUXCY_L port map (
DI => R1IN_4_2F_RETO(14),
CI => R1IN_4_ADD_1_CRY_13,
S => R1IN_4_ADD_1_AXB_14,
LO => R1IN_4_ADD_1_CRY_14);
R1IN_4_ADD_1_S_15: XORCY port map (
LI => R1IN_4_ADD_1_AXB_15,
CI => R1IN_4_ADD_1_CRY_14,
O => R1IN_4_ADD_1_RETO(15));
R1IN_4_ADD_1_CRY_13_Z5217: MUXCY_L port map (
DI => R1IN_4_2F_RETO(13),
CI => R1IN_4_ADD_1_CRY_12,
S => R1IN_4_ADD_1_AXB_13,
LO => R1IN_4_ADD_1_CRY_13);
R1IN_4_ADD_1_S_14: XORCY port map (
LI => R1IN_4_ADD_1_AXB_14,
CI => R1IN_4_ADD_1_CRY_13,
O => R1IN_4_ADD_1_RETO(14));
R1IN_4_ADD_1_CRY_12_Z5219: MUXCY_L port map (
DI => R1IN_4_2F_RETO(12),
CI => R1IN_4_ADD_1_CRY_11,
S => R1IN_4_ADD_1_AXB_12,
LO => R1IN_4_ADD_1_CRY_12);
R1IN_4_ADD_1_S_13: XORCY port map (
LI => R1IN_4_ADD_1_AXB_13,
CI => R1IN_4_ADD_1_CRY_12,
O => R1IN_4_ADD_1_RETO(13));
R1IN_4_ADD_1_CRY_11_Z5221: MUXCY_L port map (
DI => R1IN_4_2F_RETO(11),
CI => R1IN_4_ADD_1_CRY_10,
S => R1IN_4_ADD_1_AXB_11,
LO => R1IN_4_ADD_1_CRY_11);
R1IN_4_ADD_1_S_12: XORCY port map (
LI => R1IN_4_ADD_1_AXB_12,
CI => R1IN_4_ADD_1_CRY_11,
O => R1IN_4_ADD_1_RETO(12));
R1IN_4_ADD_1_CRY_10_Z5223: MUXCY_L port map (
DI => R1IN_4_2F_RETO(10),
CI => R1IN_4_ADD_1_CRY_9,
S => R1IN_4_ADD_1_AXB_10,
LO => R1IN_4_ADD_1_CRY_10);
R1IN_4_ADD_1_S_11: XORCY port map (
LI => R1IN_4_ADD_1_AXB_11,
CI => R1IN_4_ADD_1_CRY_10,
O => R1IN_4_ADD_1_RETO(11));
R1IN_4_ADD_1_CRY_9_Z5225: MUXCY_L port map (
DI => R1IN_4_2F_RETO(9),
CI => R1IN_4_ADD_1_CRY_8,
S => R1IN_4_ADD_1_AXB_9,
LO => R1IN_4_ADD_1_CRY_9);
R1IN_4_ADD_1_S_10: XORCY port map (
LI => R1IN_4_ADD_1_AXB_10,
CI => R1IN_4_ADD_1_CRY_9,
O => R1IN_4_ADD_1_RETO(10));
R1IN_4_ADD_1_CRY_8_Z5227: MUXCY_L port map (
DI => R1IN_4_2F_RETO(8),
CI => R1IN_4_ADD_1_CRY_7,
S => R1IN_4_ADD_1_AXB_8,
LO => R1IN_4_ADD_1_CRY_8);
R1IN_4_ADD_1_S_9: XORCY port map (
LI => R1IN_4_ADD_1_AXB_9,
CI => R1IN_4_ADD_1_CRY_8,
O => R1IN_4_ADD_1_RETO(9));
R1IN_4_ADD_1_CRY_7_Z5229: MUXCY_L port map (
DI => R1IN_4_2F_RETO(7),
CI => R1IN_4_ADD_1_CRY_6,
S => R1IN_4_ADD_1_AXB_7,
LO => R1IN_4_ADD_1_CRY_7);
R1IN_4_ADD_1_S_8: XORCY port map (
LI => R1IN_4_ADD_1_AXB_8,
CI => R1IN_4_ADD_1_CRY_7,
O => R1IN_4_ADD_1_RETO(8));
R1IN_4_ADD_1_CRY_6_Z5231: MUXCY_L port map (
DI => R1IN_4_2F_RETO(6),
CI => R1IN_4_ADD_1_CRY_5,
S => R1IN_4_ADD_1_AXB_6,
LO => R1IN_4_ADD_1_CRY_6);
R1IN_4_ADD_1_S_7: XORCY port map (
LI => R1IN_4_ADD_1_AXB_7,
CI => R1IN_4_ADD_1_CRY_6,
O => R1IN_4_ADD_1_RETO(7));
R1IN_4_ADD_1_CRY_5_Z5233: MUXCY_L port map (
DI => R1IN_4_2F_RETO(5),
CI => R1IN_4_ADD_1_CRY_4,
S => R1IN_4_ADD_1_AXB_5,
LO => R1IN_4_ADD_1_CRY_5);
R1IN_4_ADD_1_S_6: XORCY port map (
LI => R1IN_4_ADD_1_AXB_6,
CI => R1IN_4_ADD_1_CRY_5,
O => R1IN_4_ADD_1_RETO(6));
R1IN_4_ADD_1_CRY_4_Z5235: MUXCY_L port map (
DI => R1IN_4_2F_RETO(4),
CI => R1IN_4_ADD_1_CRY_3,
S => R1IN_4_ADD_1_AXB_4,
LO => R1IN_4_ADD_1_CRY_4);
R1IN_4_ADD_1_S_5: XORCY port map (
LI => R1IN_4_ADD_1_AXB_5,
CI => R1IN_4_ADD_1_CRY_4,
O => R1IN_4_ADD_1_RETO(5));
R1IN_4_ADD_1_CRY_3_Z5237: MUXCY_L port map (
DI => R1IN_4_2F_RETO(3),
CI => R1IN_4_ADD_1_CRY_2,
S => R1IN_4_ADD_1_AXB_3,
LO => R1IN_4_ADD_1_CRY_3);
R1IN_4_ADD_1_S_4: XORCY port map (
LI => R1IN_4_ADD_1_AXB_4,
CI => R1IN_4_ADD_1_CRY_3,
O => R1IN_4_ADD_1_RETO(4));
R1IN_4_ADD_1_CRY_2_Z5239: MUXCY_L port map (
DI => R1IN_4_2F_RETO(2),
CI => R1IN_4_ADD_1_CRY_1,
S => R1IN_4_ADD_1_AXB_2,
LO => R1IN_4_ADD_1_CRY_2);
R1IN_4_ADD_1_S_3: XORCY port map (
LI => R1IN_4_ADD_1_AXB_3,
CI => R1IN_4_ADD_1_CRY_2,
O => R1IN_4_ADD_1_RETO(3));
R1IN_4_ADD_1_CRY_1_Z5241: MUXCY_L port map (
DI => R1IN_4_2F_RETO(1),
CI => R1IN_4_ADD_1_CRY_0,
S => R1IN_4_ADD_1_AXB_1,
LO => R1IN_4_ADD_1_CRY_1);
R1IN_4_ADD_1_S_2: XORCY port map (
LI => R1IN_4_ADD_1_AXB_2,
CI => R1IN_4_ADD_1_CRY_1,
O => R1IN_4_ADD_1_RETO(2));
R1IN_4_ADD_1_CRY_0_Z5243: MUXCY_L port map (
DI => NN_4,
CI => NN_1,
S => R1IN_4_ADD_2_0_RETO,
LO => R1IN_4_ADD_1_CRY_0);
R1IN_4_ADD_1_S_1: XORCY port map (
LI => R1IN_4_ADD_1_AXB_1,
CI => R1IN_4_ADD_1_CRY_0,
O => R1IN_4_ADD_1_RETO(1));
R1IN_4_ADD_1_AXB_0: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_3F_RETO(0),
I1 => NN_4,
O => R1IN_4_ADD_2_0_RETO);
R1IN_2_ADD_1_S_43: XORCY port map (
LI => R1IN_2_ADD_1_AXB_43,
CI => R1IN_2_ADD_1_CRY_42,
O => R1IN_2_RETO(60));
R1IN_2_ADD_1_AXB_43_Z5320: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F_RETO(43),
O => R1IN_2_ADD_1_AXB_43);
R1IN_2_ADD_1_CRY_42_Z5321: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_41,
S => R1IN_2_ADD_1_AXB_42,
LO => R1IN_2_ADD_1_CRY_42);
R1IN_2_ADD_1_CRY_41_Z5322: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_40,
S => R1IN_2_ADD_1_AXB_41,
LO => R1IN_2_ADD_1_CRY_41);
R1IN_2_ADD_1_S_42: XORCY port map (
LI => R1IN_2_ADD_1_AXB_42,
CI => R1IN_2_ADD_1_CRY_41,
O => R1IN_2_RETO(59));
R1IN_2_ADD_1_CRY_40_Z5324: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_39,
S => R1IN_2_ADD_1_AXB_40,
LO => R1IN_2_ADD_1_CRY_40);
R1IN_2_ADD_1_S_41: XORCY port map (
LI => R1IN_2_ADD_1_AXB_41,
CI => R1IN_2_ADD_1_CRY_40,
O => R1IN_2_RETO(58));
R1IN_2_ADD_1_CRY_39_Z5326: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_38,
S => R1IN_2_ADD_1_AXB_39,
LO => R1IN_2_ADD_1_CRY_39);
R1IN_2_ADD_1_S_40: XORCY port map (
LI => R1IN_2_ADD_1_AXB_40,
CI => R1IN_2_ADD_1_CRY_39,
O => R1IN_2_RETO(57));
R1IN_2_ADD_1_CRY_38_Z5328: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_37,
S => R1IN_2_ADD_1_AXB_38,
LO => R1IN_2_ADD_1_CRY_38);
R1IN_2_ADD_1_S_39: XORCY port map (
LI => R1IN_2_ADD_1_AXB_39,
CI => R1IN_2_ADD_1_CRY_38,
O => R1IN_2_RETO(56));
R1IN_2_ADD_1_CRY_37_Z5330: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_36,
S => R1IN_2_ADD_1_AXB_37,
LO => R1IN_2_ADD_1_CRY_37);
R1IN_2_ADD_1_S_38: XORCY port map (
LI => R1IN_2_ADD_1_AXB_38,
CI => R1IN_2_ADD_1_CRY_37,
O => R1IN_2_RETO(55));
R1IN_2_ADD_1_CRY_36_Z5332: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_35,
S => R1IN_2_ADD_1_AXB_36,
LO => R1IN_2_ADD_1_CRY_36);
R1IN_2_ADD_1_S_37: XORCY port map (
LI => R1IN_2_ADD_1_AXB_37,
CI => R1IN_2_ADD_1_CRY_36,
O => R1IN_2_RETO(54));
R1IN_2_ADD_1_CRY_35_Z5334: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_34,
S => R1IN_2_ADD_1_AXB_35,
LO => R1IN_2_ADD_1_CRY_35);
R1IN_2_ADD_1_S_36: XORCY port map (
LI => R1IN_2_ADD_1_AXB_36,
CI => R1IN_2_ADD_1_CRY_35,
O => R1IN_2_RETO(53));
R1IN_2_ADD_1_CRY_34_Z5336: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_33,
S => R1IN_2_ADD_1_AXB_34,
LO => R1IN_2_ADD_1_CRY_34);
R1IN_2_ADD_1_S_35: XORCY port map (
LI => R1IN_2_ADD_1_AXB_35,
CI => R1IN_2_ADD_1_CRY_34,
O => R1IN_2_RETO(52));
R1IN_2_ADD_1_CRY_33_Z5338: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_32,
S => R1IN_2_ADD_1_AXB_33,
LO => R1IN_2_ADD_1_CRY_33);
R1IN_2_ADD_1_S_34: XORCY port map (
LI => R1IN_2_ADD_1_AXB_34,
CI => R1IN_2_ADD_1_CRY_33,
O => R1IN_2_RETO(51));
R1IN_2_ADD_1_CRY_32_Z5340: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_31,
S => R1IN_2_ADD_1_AXB_32,
LO => R1IN_2_ADD_1_CRY_32);
R1IN_2_ADD_1_S_33: XORCY port map (
LI => R1IN_2_ADD_1_AXB_33,
CI => R1IN_2_ADD_1_CRY_32,
O => R1IN_2_RETO(50));
R1IN_2_ADD_1_CRY_31_Z5342: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_30,
S => R1IN_2_ADD_1_AXB_31,
LO => R1IN_2_ADD_1_CRY_31);
R1IN_2_ADD_1_S_32: XORCY port map (
LI => R1IN_2_ADD_1_AXB_32,
CI => R1IN_2_ADD_1_CRY_31,
O => R1IN_2_RETO(49));
R1IN_2_ADD_1_CRY_30_Z5344: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_29,
S => R1IN_2_ADD_1_AXB_30,
LO => R1IN_2_ADD_1_CRY_30);
R1IN_2_ADD_1_S_31: XORCY port map (
LI => R1IN_2_ADD_1_AXB_31,
CI => R1IN_2_ADD_1_CRY_30,
O => R1IN_2_RETO(48));
R1IN_2_ADD_1_CRY_29_Z5346: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_28,
S => R1IN_2_ADD_1_AXB_29,
LO => R1IN_2_ADD_1_CRY_29);
R1IN_2_ADD_1_S_30: XORCY port map (
LI => R1IN_2_ADD_1_AXB_30,
CI => R1IN_2_ADD_1_CRY_29,
O => R1IN_2_RETO(47));
R1IN_2_ADD_1_CRY_28_Z5348: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_27,
S => R1IN_2_ADD_1_AXB_28,
LO => R1IN_2_ADD_1_CRY_28);
R1IN_2_ADD_1_S_29: XORCY port map (
LI => R1IN_2_ADD_1_AXB_29,
CI => R1IN_2_ADD_1_CRY_28,
O => R1IN_2_RETO(46));
R1IN_2_ADD_1_CRY_27_Z5350: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_26,
S => R1IN_2_ADD_1_AXB_27,
LO => R1IN_2_ADD_1_CRY_27);
R1IN_2_ADD_1_S_28: XORCY port map (
LI => R1IN_2_ADD_1_AXB_28,
CI => R1IN_2_ADD_1_CRY_27,
O => R1IN_2_RETO(45));
R1IN_2_ADD_1_CRY_26_Z5352: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_25,
S => R1IN_2_ADD_1_AXB_26,
LO => R1IN_2_ADD_1_CRY_26);
R1IN_2_ADD_1_S_27: XORCY port map (
LI => R1IN_2_ADD_1_AXB_27,
CI => R1IN_2_ADD_1_CRY_26,
O => R1IN_2_RETO(44));
R1IN_2_ADD_1_CRY_25_Z5354: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_24,
S => R1IN_2_ADD_1_AXB_25,
LO => R1IN_2_ADD_1_CRY_25);
R1IN_2_ADD_1_S_26: XORCY port map (
LI => R1IN_2_ADD_1_AXB_26,
CI => R1IN_2_ADD_1_CRY_25,
O => R1IN_2_RETO(43));
R1IN_2_ADD_1_CRY_24_Z5356: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_23,
S => R1IN_2_ADD_1_AXB_24,
LO => R1IN_2_ADD_1_CRY_24);
R1IN_2_ADD_1_S_25: XORCY port map (
LI => R1IN_2_ADD_1_AXB_25,
CI => R1IN_2_ADD_1_CRY_24,
O => R1IN_2_RETO(42));
R1IN_2_ADD_1_CRY_23_Z5358: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_22,
S => R1IN_2_ADD_1_AXB_23,
LO => R1IN_2_ADD_1_CRY_23);
R1IN_2_ADD_1_S_24: XORCY port map (
LI => R1IN_2_ADD_1_AXB_24,
CI => R1IN_2_ADD_1_CRY_23,
O => R1IN_2_RETO(41));
R1IN_2_ADD_1_CRY_22_Z5360: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_21,
S => R1IN_2_ADD_1_AXB_22,
LO => R1IN_2_ADD_1_CRY_22);
R1IN_2_ADD_1_S_23: XORCY port map (
LI => R1IN_2_ADD_1_AXB_23,
CI => R1IN_2_ADD_1_CRY_22,
O => R1IN_2_RETO(40));
R1IN_2_ADD_1_CRY_21_Z5362: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_20,
S => R1IN_2_ADD_1_AXB_21,
LO => R1IN_2_ADD_1_CRY_21);
R1IN_2_ADD_1_S_22: XORCY port map (
LI => R1IN_2_ADD_1_AXB_22,
CI => R1IN_2_ADD_1_CRY_21,
O => R1IN_2_RETO(39));
R1IN_2_ADD_1_CRY_20_Z5364: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_19,
S => R1IN_2_ADD_1_AXB_20,
LO => R1IN_2_ADD_1_CRY_20);
R1IN_2_ADD_1_S_21: XORCY port map (
LI => R1IN_2_ADD_1_AXB_21,
CI => R1IN_2_ADD_1_CRY_20,
O => R1IN_2_RETO(38));
R1IN_2_ADD_1_CRY_19_Z5366: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_18,
S => R1IN_2_ADD_1_AXB_19,
LO => R1IN_2_ADD_1_CRY_19);
R1IN_2_ADD_1_S_20: XORCY port map (
LI => R1IN_2_ADD_1_AXB_20,
CI => R1IN_2_ADD_1_CRY_19,
O => R1IN_2_RETO(37));
R1IN_2_ADD_1_CRY_18_Z5368: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_17,
S => R1IN_2_ADD_1_AXB_18,
LO => R1IN_2_ADD_1_CRY_18);
R1IN_2_ADD_1_S_19: XORCY port map (
LI => R1IN_2_ADD_1_AXB_19,
CI => R1IN_2_ADD_1_CRY_18,
O => R1IN_2_RETO(36));
R1IN_2_ADD_1_CRY_17_Z5370: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_16,
S => R1IN_2_ADD_1_AXB_17,
LO => R1IN_2_ADD_1_CRY_17);
R1IN_2_ADD_1_S_18: XORCY port map (
LI => R1IN_2_ADD_1_AXB_18,
CI => R1IN_2_ADD_1_CRY_17,
O => R1IN_2_RETO(35));
R1IN_2_ADD_1_CRY_16_Z5372: MUXCY_L port map (
DI => R1IN_2_2F_RETO(16),
CI => R1IN_2_ADD_1_CRY_15,
S => R1IN_2_ADD_1_AXB_16,
LO => R1IN_2_ADD_1_CRY_16);
R1IN_2_ADD_1_S_17: XORCY port map (
LI => R1IN_2_ADD_1_AXB_17,
CI => R1IN_2_ADD_1_CRY_16,
O => R1IN_2_RETO(34));
R1IN_2_ADD_1_CRY_15_Z5374: MUXCY_L port map (
DI => R1IN_2_2F_RETO(15),
CI => R1IN_2_ADD_1_CRY_14,
S => R1IN_2_ADD_1_AXB_15,
LO => R1IN_2_ADD_1_CRY_15);
R1IN_2_ADD_1_S_16: XORCY port map (
LI => R1IN_2_ADD_1_AXB_16,
CI => R1IN_2_ADD_1_CRY_15,
O => R1IN_2_RETO(33));
R1IN_2_ADD_1_CRY_14_Z5376: MUXCY_L port map (
DI => R1IN_2_2F_RETO(14),
CI => R1IN_2_ADD_1_CRY_13,
S => R1IN_2_ADD_1_AXB_14,
LO => R1IN_2_ADD_1_CRY_14);
R1IN_2_ADD_1_S_15: XORCY port map (
LI => R1IN_2_ADD_1_AXB_15,
CI => R1IN_2_ADD_1_CRY_14,
O => R1IN_2_RETO(32));
R1IN_2_ADD_1_CRY_13_Z5378: MUXCY_L port map (
DI => R1IN_2_2F_RETO(13),
CI => R1IN_2_ADD_1_CRY_12,
S => R1IN_2_ADD_1_AXB_13,
LO => R1IN_2_ADD_1_CRY_13);
R1IN_2_ADD_1_S_14: XORCY port map (
LI => R1IN_2_ADD_1_AXB_14,
CI => R1IN_2_ADD_1_CRY_13,
O => R1IN_2_RETO(31));
R1IN_2_ADD_1_CRY_12_Z5380: MUXCY_L port map (
DI => R1IN_2_2F_RETO(12),
CI => R1IN_2_ADD_1_CRY_11,
S => R1IN_2_ADD_1_AXB_12,
LO => R1IN_2_ADD_1_CRY_12);
R1IN_2_ADD_1_S_13: XORCY port map (
LI => R1IN_2_ADD_1_AXB_13,
CI => R1IN_2_ADD_1_CRY_12,
O => R1IN_2_RETO(30));
R1IN_2_ADD_1_CRY_11_Z5382: MUXCY_L port map (
DI => R1IN_2_2F_RETO(11),
CI => R1IN_2_ADD_1_CRY_10,
S => R1IN_2_ADD_1_AXB_11,
LO => R1IN_2_ADD_1_CRY_11);
R1IN_2_ADD_1_S_12: XORCY port map (
LI => R1IN_2_ADD_1_AXB_12,
CI => R1IN_2_ADD_1_CRY_11,
O => R1IN_2_RETO(29));
R1IN_2_ADD_1_CRY_10_Z5384: MUXCY_L port map (
DI => R1IN_2_2F_RETO(10),
CI => R1IN_2_ADD_1_CRY_9,
S => R1IN_2_ADD_1_AXB_10,
LO => R1IN_2_ADD_1_CRY_10);
R1IN_2_ADD_1_S_11: XORCY port map (
LI => R1IN_2_ADD_1_AXB_11,
CI => R1IN_2_ADD_1_CRY_10,
O => R1IN_2_RETO(28));
R1IN_2_ADD_1_CRY_9_Z5386: MUXCY_L port map (
DI => R1IN_2_2F_RETO(9),
CI => R1IN_2_ADD_1_CRY_8,
S => R1IN_2_ADD_1_AXB_9,
LO => R1IN_2_ADD_1_CRY_9);
R1IN_2_ADD_1_S_10: XORCY port map (
LI => R1IN_2_ADD_1_AXB_10,
CI => R1IN_2_ADD_1_CRY_9,
O => R1IN_2_RETO(27));
R1IN_2_ADD_1_CRY_8_Z5388: MUXCY_L port map (
DI => R1IN_2_2F_RETO(8),
CI => R1IN_2_ADD_1_CRY_7,
S => R1IN_2_ADD_1_AXB_8,
LO => R1IN_2_ADD_1_CRY_8);
R1IN_2_ADD_1_S_9: XORCY port map (
LI => R1IN_2_ADD_1_AXB_9,
CI => R1IN_2_ADD_1_CRY_8,
O => R1IN_2_RETO(26));
R1IN_2_ADD_1_CRY_7_Z5390: MUXCY_L port map (
DI => R1IN_2_2F_RETO(7),
CI => R1IN_2_ADD_1_CRY_6,
S => R1IN_2_ADD_1_AXB_7,
LO => R1IN_2_ADD_1_CRY_7);
R1IN_2_ADD_1_S_8: XORCY port map (
LI => R1IN_2_ADD_1_AXB_8,
CI => R1IN_2_ADD_1_CRY_7,
O => R1IN_2_RETO(25));
R1IN_2_ADD_1_CRY_6_Z5392: MUXCY_L port map (
DI => R1IN_2_2F_RETO(6),
CI => R1IN_2_ADD_1_CRY_5,
S => R1IN_2_ADD_1_AXB_6,
LO => R1IN_2_ADD_1_CRY_6);
R1IN_2_ADD_1_S_7: XORCY port map (
LI => R1IN_2_ADD_1_AXB_7,
CI => R1IN_2_ADD_1_CRY_6,
O => R1IN_2_RETO(24));
R1IN_2_ADD_1_CRY_5_Z5394: MUXCY_L port map (
DI => R1IN_2_2F_RETO(5),
CI => R1IN_2_ADD_1_CRY_4,
S => R1IN_2_ADD_1_AXB_5,
LO => R1IN_2_ADD_1_CRY_5);
R1IN_2_ADD_1_S_6: XORCY port map (
LI => R1IN_2_ADD_1_AXB_6,
CI => R1IN_2_ADD_1_CRY_5,
O => R1IN_2_RETO(23));
R1IN_2_ADD_1_CRY_4_Z5396: MUXCY_L port map (
DI => R1IN_2_2F_RETO(4),
CI => R1IN_2_ADD_1_CRY_3,
S => R1IN_2_ADD_1_AXB_4,
LO => R1IN_2_ADD_1_CRY_4);
R1IN_2_ADD_1_S_5: XORCY port map (
LI => R1IN_2_ADD_1_AXB_5,
CI => R1IN_2_ADD_1_CRY_4,
O => R1IN_2_RETO(22));
R1IN_2_ADD_1_CRY_3_Z5398: MUXCY_L port map (
DI => R1IN_2_2F_RETO(3),
CI => R1IN_2_ADD_1_CRY_2,
S => R1IN_2_ADD_1_AXB_3,
LO => R1IN_2_ADD_1_CRY_3);
R1IN_2_ADD_1_S_4: XORCY port map (
LI => R1IN_2_ADD_1_AXB_4,
CI => R1IN_2_ADD_1_CRY_3,
O => R1IN_2_RETO(21));
R1IN_2_ADD_1_CRY_2_Z5400: MUXCY_L port map (
DI => R1IN_2_2F_RETO(2),
CI => R1IN_2_ADD_1_CRY_1,
S => R1IN_2_ADD_1_AXB_2,
LO => R1IN_2_ADD_1_CRY_2);
R1IN_2_ADD_1_S_3: XORCY port map (
LI => R1IN_2_ADD_1_AXB_3,
CI => R1IN_2_ADD_1_CRY_2,
O => R1IN_2_RETO(20));
R1IN_2_ADD_1_CRY_1_Z5402: MUXCY_L port map (
DI => R1IN_2_2F_RETO(1),
CI => R1IN_2_ADD_1_CRY_0,
S => R1IN_2_ADD_1_AXB_1,
LO => R1IN_2_ADD_1_CRY_1);
R1IN_2_ADD_1_S_2: XORCY port map (
LI => R1IN_2_ADD_1_AXB_2,
CI => R1IN_2_ADD_1_CRY_1,
O => R1IN_2_RETO(19));
R1IN_2_ADD_1_CRY_0_Z5404: MUXCY_L port map (
DI => R1IN_2_ADD_1_RETO,
CI => NN_1,
S => R1IN_2_RETO(17),
LO => R1IN_2_ADD_1_CRY_0);
R1IN_2_ADD_1_S_1: XORCY port map (
LI => R1IN_2_ADD_1_AXB_1,
CI => R1IN_2_ADD_1_CRY_0,
O => R1IN_2_RETO(18));
R1IN_2_ADD_1_AXB_0: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F_RETO(17),
I1 => R1IN_2_ADD_1_RETO,
O => R1IN_2_RETO(17));
R1IN_4_ADD_2_0_AXB_1_Z5879: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F_RETO(18),
I1 => R1IN_4_ADD_1_RETO(1),
LO => R1IN_4_ADD_2_0_AXB_1);
R1IN_4_ADD_2_0_AXB_2_Z5880: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F_RETO(19),
I1 => R1IN_4_ADD_1_RETO(2),
LO => R1IN_4_ADD_2_0_AXB_2);
R1IN_4_ADD_2_0_AXB_3_Z5881: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F_RETO(20),
I1 => R1IN_4_ADD_1_RETO(3),
LO => R1IN_4_ADD_2_0_AXB_3);
R1IN_4_ADD_2_0_AXB_4_Z5882: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F_RETO(21),
I1 => R1IN_4_ADD_1_RETO(4),
LO => R1IN_4_ADD_2_0_AXB_4);
R1IN_4_ADD_2_0_AXB_5_Z5883: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F_RETO(22),
I1 => R1IN_4_ADD_1_RETO(5),
LO => R1IN_4_ADD_2_0_AXB_5);
R1IN_4_ADD_2_0_AXB_6_Z5884: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F_RETO(23),
I1 => R1IN_4_ADD_1_RETO(6),
LO => R1IN_4_ADD_2_0_AXB_6);
R1IN_4_ADD_2_0_AXB_7_Z5885: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F_RETO(24),
I1 => R1IN_4_ADD_1_RETO(7),
LO => R1IN_4_ADD_2_0_AXB_7);
R1IN_4_ADD_2_0_AXB_8_Z5886: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F_RETO(25),
I1 => R1IN_4_ADD_1_RETO(8),
LO => R1IN_4_ADD_2_0_AXB_8);
R1IN_4_ADD_2_0_AXB_9_Z5887: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F_RETO(26),
I1 => R1IN_4_ADD_1_RETO(9),
LO => R1IN_4_ADD_2_0_AXB_9);
R1IN_4_ADD_2_0_AXB_10_Z5888: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F_RETO(27),
I1 => R1IN_4_ADD_1_RETO(10),
LO => R1IN_4_ADD_2_0_AXB_10);
R1IN_4_ADD_2_0_AXB_11_Z5889: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F_RETO(28),
I1 => R1IN_4_ADD_1_RETO(11),
LO => R1IN_4_ADD_2_0_AXB_11);
R1IN_4_ADD_2_0_AXB_12_Z5890: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F_RETO(29),
I1 => R1IN_4_ADD_1_RETO(12),
LO => R1IN_4_ADD_2_0_AXB_12);
R1IN_4_ADD_2_0_AXB_13_Z5891: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F_RETO(30),
I1 => R1IN_4_ADD_1_RETO(13),
LO => R1IN_4_ADD_2_0_AXB_13);
R1IN_4_ADD_2_0_AXB_14_Z5892: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F_RETO(31),
I1 => R1IN_4_ADD_1_RETO(14),
LO => R1IN_4_ADD_2_0_AXB_14);
R1IN_4_ADD_2_0_AXB_15_Z5893: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F_RETO(32),
I1 => R1IN_4_ADD_1_RETO(15),
LO => R1IN_4_ADD_2_0_AXB_15);
R1IN_4_ADD_2_0_AXB_16_Z5894: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F_RETO(33),
I1 => R1IN_4_ADD_1_RETO(16),
LO => R1IN_4_ADD_2_0_AXB_16);
R1IN_4_ADD_2_0_AXB_17_Z5895: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F_RETO(0),
I1 => R1IN_4_ADD_1_RETO(17),
LO => R1IN_4_ADD_2_0_AXB_17);
R1IN_4_ADD_2_0_AXB_18_Z5896: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F_RETO(1),
I1 => R1IN_4_ADD_1_RETO(18),
LO => R1IN_4_ADD_2_0_AXB_18);
R1IN_4_ADD_2_0_AXB_19_Z5897: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F_RETO(2),
I1 => R1IN_4_ADD_1_RETO(19),
LO => R1IN_4_ADD_2_0_AXB_19);
R1IN_4_ADD_2_0_AXB_20_Z5898: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F_RETO(3),
I1 => R1IN_4_ADD_1_RETO(20),
LO => R1IN_4_ADD_2_0_AXB_20);
R1IN_4_ADD_2_0_AXB_21_Z5899: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F_RETO(4),
I1 => R1IN_4_ADD_1_RETO(21),
LO => R1IN_4_ADD_2_0_AXB_21);
R1IN_4_ADD_2_0_AXB_22_Z5900: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F_RETO(5),
I1 => R1IN_4_ADD_1_RETO(22),
LO => R1IN_4_ADD_2_0_AXB_22);
R1IN_4_ADD_2_0_AXB_23_Z5901: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F_RETO(6),
I1 => R1IN_4_ADD_1_RETO(23),
LO => R1IN_4_ADD_2_0_AXB_23);
R1IN_4_ADD_2_0_AXB_24_Z5902: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F_RETO(7),
I1 => R1IN_4_ADD_1_RETO(24),
LO => R1IN_4_ADD_2_0_AXB_24);
R1IN_4_ADD_2_0_AXB_25_Z5903: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F_RETO(8),
I1 => R1IN_4_ADD_1_RETO(25),
LO => R1IN_4_ADD_2_0_AXB_25);
R1IN_4_ADD_2_0_AXB_26_Z5904: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F_RETO(9),
I1 => R1IN_4_ADD_1_RETO(26),
LO => R1IN_4_ADD_2_0_AXB_26);
R1IN_4_ADD_2_0_AXB_27_Z5905: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F_RETO(10),
I1 => R1IN_4_ADD_1_RETO(27),
LO => R1IN_4_ADD_2_0_AXB_27);
R1IN_4_ADD_2_0_AXB_28_Z5906: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F_RETO(11),
I1 => R1IN_4_ADD_1_RETO(28),
LO => R1IN_4_ADD_2_0_AXB_28);
R1IN_4_ADD_2_0_AXB_29_Z5907: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F_RETO(12),
I1 => R1IN_4_ADD_1_RETO(29),
LO => R1IN_4_ADD_2_0_AXB_29);
R1IN_4_ADD_2_0_AXB_30_Z5908: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F_RETO(13),
I1 => R1IN_4_ADD_1_RETO(30),
LO => R1IN_4_ADD_2_0_AXB_30);
R1IN_4_ADD_2_0_AXB_31_Z5909: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F_RETO(14),
I1 => R1IN_4_ADD_1_RETO(31),
LO => R1IN_4_ADD_2_0_AXB_31);
R1IN_4_ADD_2_0_AXB_32_Z5910: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F_RETO(15),
I1 => R1IN_4_ADD_1_RETO(32),
LO => R1IN_4_ADD_2_0_AXB_32);
R1IN_4_ADD_2_0_AXB_33_Z5911: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F_RETO(16),
I1 => R1IN_4_ADD_1_RETO(33),
LO => R1IN_4_ADD_2_0_AXB_33);
R1IN_4_ADD_2_0_AXB_34_Z5912: LUT3_L
generic map(
INIT => X"96"
)
port map (
I0 => R1IN_4_4_ADD_1F_RETO(0),
I1 => R1IN_4_4_ADD_2_RETO,
I2 => R1IN_4_ADD_1_RETO(34),
LO => R1IN_4_ADD_2_0_AXB_34);
R1IN_4_ADD_2_0_AXB_35_Z5913: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(18),
I1 => R1IN_4_ADD_1_RETO(35),
LO => R1IN_4_ADD_2_0_AXB_35);
R1IN_ADD_1_0_AXB_1_Z5914: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F_RETO(1),
I1 => R1IN_3F_RETO(1),
LO => R1IN_ADD_1_0_AXB_1);
R1IN_ADD_1_0_AXB_2_Z5915: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F_RETO(2),
I1 => R1IN_3F_RETO(2),
LO => R1IN_ADD_1_0_AXB_2);
R1IN_ADD_1_0_AXB_3_Z5916: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F_RETO(3),
I1 => R1IN_3F_RETO(3),
LO => R1IN_ADD_1_0_AXB_3);
R1IN_ADD_1_0_AXB_4_Z5917: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F_RETO(4),
I1 => R1IN_3F_RETO(4),
LO => R1IN_ADD_1_0_AXB_4);
R1IN_ADD_1_0_AXB_5_Z5918: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F_RETO(5),
I1 => R1IN_3F_RETO(5),
LO => R1IN_ADD_1_0_AXB_5);
R1IN_ADD_1_0_AXB_6_Z5919: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F_RETO(6),
I1 => R1IN_3F_RETO(6),
LO => R1IN_ADD_1_0_AXB_6);
R1IN_ADD_1_0_AXB_7_Z5920: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F_RETO(7),
I1 => R1IN_3F_RETO(7),
LO => R1IN_ADD_1_0_AXB_7);
R1IN_ADD_1_0_AXB_8_Z5921: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F_RETO(8),
I1 => R1IN_3F_RETO(8),
LO => R1IN_ADD_1_0_AXB_8);
R1IN_ADD_1_0_AXB_9_Z5922: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F_RETO(9),
I1 => R1IN_3F_RETO(9),
LO => R1IN_ADD_1_0_AXB_9);
R1IN_ADD_1_0_AXB_10_Z5923: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F_RETO(10),
I1 => R1IN_3F_RETO(10),
LO => R1IN_ADD_1_0_AXB_10);
R1IN_ADD_1_0_AXB_11_Z5924: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F_RETO(11),
I1 => R1IN_3F_RETO(11),
LO => R1IN_ADD_1_0_AXB_11);
R1IN_ADD_1_0_AXB_12_Z5925: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F_RETO(12),
I1 => R1IN_3F_RETO(12),
LO => R1IN_ADD_1_0_AXB_12);
R1IN_ADD_1_0_AXB_13_Z5926: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F_RETO(13),
I1 => R1IN_3F_RETO(13),
LO => R1IN_ADD_1_0_AXB_13);
R1IN_ADD_1_0_AXB_14_Z5927: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F_RETO(14),
I1 => R1IN_3F_RETO(14),
LO => R1IN_ADD_1_0_AXB_14);
R1IN_ADD_1_0_AXB_15_Z5928: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F_RETO(15),
I1 => R1IN_3F_RETO(15),
LO => R1IN_ADD_1_0_AXB_15);
R1IN_ADD_1_0_AXB_16_Z5929: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F_RETO(16),
I1 => R1IN_3F_RETO(16),
LO => R1IN_ADD_1_0_AXB_16);
R1IN_ADD_1_0_AXB_17_Z5930: LUT3_L
generic map(
INIT => X"96"
)
port map (
I0 => R1IN_2_RETO(17),
I1 => R1IN_3_1F_RETO(17),
I2 => R1IN_3_ADD_1_RETO,
LO => R1IN_ADD_1_0_AXB_17);
R1IN_ADD_1_0_AXB_18_Z5931: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(18),
I1 => R1IN_3(18),
LO => R1IN_ADD_1_0_AXB_18);
R1IN_ADD_1_0_AXB_19_Z5932: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(19),
I1 => R1IN_3(19),
LO => R1IN_ADD_1_0_AXB_19);
R1IN_ADD_1_0_AXB_20_Z5933: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(20),
I1 => R1IN_3(20),
LO => R1IN_ADD_1_0_AXB_20);
R1IN_ADD_1_0_AXB_21_Z5934: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(21),
I1 => R1IN_3(21),
LO => R1IN_ADD_1_0_AXB_21);
R1IN_ADD_1_0_AXB_22_Z5935: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(22),
I1 => R1IN_3(22),
LO => R1IN_ADD_1_0_AXB_22);
R1IN_ADD_1_0_AXB_23_Z5936: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(23),
I1 => R1IN_3(23),
LO => R1IN_ADD_1_0_AXB_23);
R1IN_ADD_1_0_AXB_24_Z5937: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(24),
I1 => R1IN_3(24),
LO => R1IN_ADD_1_0_AXB_24);
R1IN_ADD_1_0_AXB_25_Z5938: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(25),
I1 => R1IN_3(25),
LO => R1IN_ADD_1_0_AXB_25);
R1IN_ADD_1_0_AXB_26_Z5939: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(26),
I1 => R1IN_3(26),
LO => R1IN_ADD_1_0_AXB_26);
R1IN_ADD_1_0_AXB_27_Z5940: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(27),
I1 => R1IN_3(27),
LO => R1IN_ADD_1_0_AXB_27);
R1IN_ADD_1_0_AXB_28_Z5941: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(28),
I1 => R1IN_3(28),
LO => R1IN_ADD_1_0_AXB_28);
R1IN_ADD_1_0_AXB_29_Z5942: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(29),
I1 => R1IN_3(29),
LO => R1IN_ADD_1_0_AXB_29);
R1IN_ADD_1_0_AXB_30_Z5943: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(30),
I1 => R1IN_3(30),
LO => R1IN_ADD_1_0_AXB_30);
R1IN_ADD_1_0_AXB_31_Z5944: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(31),
I1 => R1IN_3(31),
LO => R1IN_ADD_1_0_AXB_31);
R1IN_ADD_2_AXB_0: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_ADD_1(0),
I1 => R1IN_ADD_2,
O => NN_3);
R1IN_4_4_ADD_2_AXB_36_Z5946: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4_4F_RETO(19),
O => R1IN_4_4_ADD_2_AXB_36);
R1IN_3_ADD_1_AXB_43_Z5947: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F_RETO(43),
O => R1IN_3_ADD_1_AXB_43);
R1IN_3_ADD_1_AXB_0: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F_RETO_0(17),
I1 => R1IN_3_ADD_1_RETO_0,
O => R1IN_3(17));
R1IN_ADD_1_1_0_AXB_0_Z5949: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(32),
I1 => R1IN_3(32),
O => R1IN_ADD_1_1_0_AXB_0);
R1IN_ADD_1_1_AXB_0_Z5950: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_RETO(32),
I1 => R1IN_3(32),
O => R1IN_ADD_1_1_AXB_0);
R1IN_ADD_1_0_AXB_0: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F_RETO(0),
I1 => R1IN_3F_RETO(0),
O => R1IN_ADD_1(0));
R1IN_4_ADD_2_1_0_AXB_34_Z5952: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(53),
O => R1IN_4_ADD_2_1_0_AXB_34);
R1IN_4_ADD_2_1_0_AXB_0_Z5953: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(19),
I1 => R1IN_4_ADD_2_1_RETO,
O => R1IN_4_ADD_2_1_0_AXB_0);
R1IN_4_ADD_2_1_AXB_34_Z5954: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(53),
O => R1IN_4_ADD_2_1_AXB_34);
R1IN_4_ADD_2_1_AXB_0_Z5955: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(19),
I1 => R1IN_4_ADD_2_1_RETO,
O => R1IN_4_ADD_2_1_AXB_0);
R1IN_4_ADD_2_0_AXB_0: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F_RETO(17),
I1 => R1IN_4_ADD_2_0_RETO,
O => R1IN_4(17));
R1IN_ADD_2_S_104: XORCY port map (
LI => R1IN_ADD_2_AXB_104,
CI => R1IN_ADD_2_CRY_103,
O => PRODUCT(121));
R1IN_ADD_2_S_103: XORCY port map (
LI => R1IN_ADD_2_AXB_103,
CI => R1IN_ADD_2_CRY_102,
O => PRODUCT(120));
R1IN_ADD_2_CRY_103_Z5959: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_102,
S => R1IN_ADD_2_AXB_103,
LO => R1IN_ADD_2_CRY_103);
R1IN_ADD_2_S_102: XORCY port map (
LI => R1IN_ADD_2_AXB_102,
CI => R1IN_ADD_2_CRY_101,
O => PRODUCT(119));
R1IN_ADD_2_CRY_102_Z5961: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_101,
S => R1IN_ADD_2_AXB_102,
LO => R1IN_ADD_2_CRY_102);
R1IN_ADD_2_S_101: XORCY port map (
LI => R1IN_ADD_2_AXB_101,
CI => R1IN_ADD_2_CRY_100,
O => PRODUCT(118));
R1IN_ADD_2_CRY_101_Z5963: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_100,
S => R1IN_ADD_2_AXB_101,
LO => R1IN_ADD_2_CRY_101);
R1IN_ADD_2_S_100: XORCY port map (
LI => R1IN_ADD_2_AXB_100,
CI => R1IN_ADD_2_CRY_99,
O => PRODUCT(117));
R1IN_ADD_2_CRY_100_Z5965: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_99,
S => R1IN_ADD_2_AXB_100,
LO => R1IN_ADD_2_CRY_100);
R1IN_ADD_2_S_99: XORCY port map (
LI => R1IN_ADD_2_AXB_99,
CI => R1IN_ADD_2_CRY_98,
O => PRODUCT(116));
R1IN_ADD_2_CRY_99_Z5967: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_98,
S => R1IN_ADD_2_AXB_99,
LO => R1IN_ADD_2_CRY_99);
R1IN_ADD_2_S_98: XORCY port map (
LI => R1IN_ADD_2_AXB_98,
CI => R1IN_ADD_2_CRY_97,
O => PRODUCT(115));
R1IN_ADD_2_CRY_98_Z5969: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_97,
S => R1IN_ADD_2_AXB_98,
LO => R1IN_ADD_2_CRY_98);
R1IN_ADD_2_S_97: XORCY port map (
LI => R1IN_ADD_2_AXB_97,
CI => R1IN_ADD_2_CRY_96,
O => PRODUCT(114));
R1IN_ADD_2_CRY_97_Z5971: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_96,
S => R1IN_ADD_2_AXB_97,
LO => R1IN_ADD_2_CRY_97);
R1IN_ADD_2_S_96: XORCY port map (
LI => R1IN_ADD_2_AXB_96,
CI => R1IN_ADD_2_CRY_95,
O => PRODUCT(113));
R1IN_ADD_2_CRY_96_Z5973: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_95,
S => R1IN_ADD_2_AXB_96,
LO => R1IN_ADD_2_CRY_96);
R1IN_ADD_2_S_95: XORCY port map (
LI => R1IN_ADD_2_AXB_95,
CI => R1IN_ADD_2_CRY_94,
O => PRODUCT(112));
R1IN_ADD_2_CRY_95_Z5975: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_94,
S => R1IN_ADD_2_AXB_95,
LO => R1IN_ADD_2_CRY_95);
R1IN_ADD_2_S_94: XORCY port map (
LI => R1IN_ADD_2_AXB_94,
CI => R1IN_ADD_2_CRY_93,
O => PRODUCT(111));
R1IN_ADD_2_CRY_94_Z5977: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_93,
S => R1IN_ADD_2_AXB_94,
LO => R1IN_ADD_2_CRY_94);
R1IN_ADD_2_S_93: XORCY port map (
LI => R1IN_ADD_2_AXB_93,
CI => R1IN_ADD_2_CRY_92,
O => PRODUCT(110));
R1IN_ADD_2_CRY_93_Z5979: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_92,
S => R1IN_ADD_2_AXB_93,
LO => R1IN_ADD_2_CRY_93);
R1IN_ADD_2_S_92: XORCY port map (
LI => R1IN_ADD_2_AXB_92,
CI => R1IN_ADD_2_CRY_91,
O => PRODUCT(109));
R1IN_ADD_2_CRY_92_Z5981: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_91,
S => R1IN_ADD_2_AXB_92,
LO => R1IN_ADD_2_CRY_92);
R1IN_ADD_2_S_91: XORCY port map (
LI => R1IN_ADD_2_AXB_91,
CI => R1IN_ADD_2_CRY_90,
O => PRODUCT(108));
R1IN_ADD_2_CRY_91_Z5983: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_90,
S => R1IN_ADD_2_AXB_91,
LO => R1IN_ADD_2_CRY_91);
R1IN_ADD_2_S_90: XORCY port map (
LI => R1IN_ADD_2_AXB_90,
CI => R1IN_ADD_2_CRY_89,
O => PRODUCT(107));
R1IN_ADD_2_CRY_90_Z5985: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_89,
S => R1IN_ADD_2_AXB_90,
LO => R1IN_ADD_2_CRY_90);
R1IN_ADD_2_S_89: XORCY port map (
LI => R1IN_ADD_2_AXB_89,
CI => R1IN_ADD_2_CRY_88,
O => PRODUCT(106));
R1IN_ADD_2_CRY_89_Z5987: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_88,
S => R1IN_ADD_2_AXB_89,
LO => R1IN_ADD_2_CRY_89);
R1IN_ADD_2_S_88: XORCY port map (
LI => R1IN_ADD_2_AXB_88,
CI => R1IN_ADD_2_CRY_87,
O => PRODUCT(105));
R1IN_ADD_2_CRY_88_Z5989: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_87,
S => R1IN_ADD_2_AXB_88,
LO => R1IN_ADD_2_CRY_88);
R1IN_ADD_2_S_87: XORCY port map (
LI => R1IN_ADD_2_AXB_87,
CI => R1IN_ADD_2_CRY_86,
O => PRODUCT(104));
R1IN_ADD_2_CRY_87_Z5991: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_86,
S => R1IN_ADD_2_AXB_87,
LO => R1IN_ADD_2_CRY_87);
R1IN_ADD_2_S_86: XORCY port map (
LI => R1IN_ADD_2_AXB_86,
CI => R1IN_ADD_2_CRY_85,
O => PRODUCT(103));
R1IN_ADD_2_CRY_86_Z5993: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_85,
S => R1IN_ADD_2_AXB_86,
LO => R1IN_ADD_2_CRY_86);
R1IN_ADD_2_S_85: XORCY port map (
LI => R1IN_ADD_2_AXB_85,
CI => R1IN_ADD_2_CRY_84,
O => PRODUCT(102));
R1IN_ADD_2_CRY_85_Z5995: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_84,
S => R1IN_ADD_2_AXB_85,
LO => R1IN_ADD_2_CRY_85);
R1IN_ADD_2_S_84: XORCY port map (
LI => R1IN_ADD_2_AXB_84,
CI => R1IN_ADD_2_CRY_83,
O => PRODUCT(101));
R1IN_ADD_2_CRY_84_Z5997: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_83,
S => R1IN_ADD_2_AXB_84,
LO => R1IN_ADD_2_CRY_84);
R1IN_ADD_2_S_83: XORCY port map (
LI => R1IN_ADD_2_AXB_83,
CI => R1IN_ADD_2_CRY_82,
O => PRODUCT(100));
R1IN_ADD_2_CRY_83_Z5999: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_82,
S => R1IN_ADD_2_AXB_83,
LO => R1IN_ADD_2_CRY_83);
R1IN_ADD_2_S_82: XORCY port map (
LI => R1IN_ADD_2_AXB_82,
CI => R1IN_ADD_2_CRY_81,
O => PRODUCT(99));
R1IN_ADD_2_CRY_82_Z6001: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_81,
S => R1IN_ADD_2_AXB_82,
LO => R1IN_ADD_2_CRY_82);
R1IN_ADD_2_S_81: XORCY port map (
LI => R1IN_ADD_2_AXB_81,
CI => R1IN_ADD_2_CRY_80,
O => PRODUCT(98));
R1IN_ADD_2_CRY_81_Z6003: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_80,
S => R1IN_ADD_2_AXB_81,
LO => R1IN_ADD_2_CRY_81);
R1IN_ADD_2_S_80: XORCY port map (
LI => R1IN_ADD_2_AXB_80,
CI => R1IN_ADD_2_CRY_79,
O => PRODUCT(97));
R1IN_ADD_2_CRY_80_Z6005: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_79,
S => R1IN_ADD_2_AXB_80,
LO => R1IN_ADD_2_CRY_80);
R1IN_ADD_2_S_79: XORCY port map (
LI => R1IN_ADD_2_AXB_79,
CI => R1IN_ADD_2_CRY_78,
O => PRODUCT(96));
R1IN_ADD_2_CRY_79_Z6007: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_78,
S => R1IN_ADD_2_AXB_79,
LO => R1IN_ADD_2_CRY_79);
R1IN_ADD_2_S_78: XORCY port map (
LI => R1IN_ADD_2_AXB_78,
CI => R1IN_ADD_2_CRY_77,
O => PRODUCT(95));
R1IN_ADD_2_CRY_78_Z6009: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_77,
S => R1IN_ADD_2_AXB_78,
LO => R1IN_ADD_2_CRY_78);
R1IN_ADD_2_S_77: XORCY port map (
LI => R1IN_ADD_2_AXB_77,
CI => R1IN_ADD_2_CRY_76,
O => PRODUCT(94));
R1IN_ADD_2_CRY_77_Z6011: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_76,
S => R1IN_ADD_2_AXB_77,
LO => R1IN_ADD_2_CRY_77);
R1IN_ADD_2_S_76: XORCY port map (
LI => R1IN_ADD_2_AXB_76,
CI => R1IN_ADD_2_CRY_75,
O => PRODUCT(93));
R1IN_ADD_2_CRY_76_Z6013: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_75,
S => R1IN_ADD_2_AXB_76,
LO => R1IN_ADD_2_CRY_76);
R1IN_ADD_2_S_75: XORCY port map (
LI => R1IN_ADD_2_AXB_75,
CI => R1IN_ADD_2_CRY_74,
O => PRODUCT(92));
R1IN_ADD_2_CRY_75_Z6015: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_74,
S => R1IN_ADD_2_AXB_75,
LO => R1IN_ADD_2_CRY_75);
R1IN_ADD_2_S_74: XORCY port map (
LI => R1IN_ADD_2_AXB_74,
CI => R1IN_ADD_2_CRY_73,
O => PRODUCT(91));
R1IN_ADD_2_CRY_74_Z6017: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_73,
S => R1IN_ADD_2_AXB_74,
LO => R1IN_ADD_2_CRY_74);
R1IN_ADD_2_S_73: XORCY port map (
LI => R1IN_ADD_2_AXB_73,
CI => R1IN_ADD_2_CRY_72,
O => PRODUCT(90));
R1IN_ADD_2_CRY_73_Z6019: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_72,
S => R1IN_ADD_2_AXB_73,
LO => R1IN_ADD_2_CRY_73);
R1IN_ADD_2_S_72: XORCY port map (
LI => R1IN_ADD_2_AXB_72,
CI => R1IN_ADD_2_CRY_71,
O => PRODUCT(89));
R1IN_ADD_2_CRY_72_Z6021: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_71,
S => R1IN_ADD_2_AXB_72,
LO => R1IN_ADD_2_CRY_72);
R1IN_ADD_2_S_71: XORCY port map (
LI => R1IN_ADD_2_AXB_71,
CI => R1IN_ADD_2_CRY_70,
O => PRODUCT(88));
R1IN_ADD_2_CRY_71_Z6023: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_70,
S => R1IN_ADD_2_AXB_71,
LO => R1IN_ADD_2_CRY_71);
R1IN_ADD_2_S_70: XORCY port map (
LI => R1IN_ADD_2_AXB_70,
CI => R1IN_ADD_2_CRY_69,
O => PRODUCT(87));
R1IN_ADD_2_CRY_70_Z6025: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_69,
S => R1IN_ADD_2_AXB_70,
LO => R1IN_ADD_2_CRY_70);
R1IN_ADD_2_S_69: XORCY port map (
LI => R1IN_ADD_2_AXB_69,
CI => R1IN_ADD_2_CRY_68,
O => PRODUCT(86));
R1IN_ADD_2_CRY_69_Z6027: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_68,
S => R1IN_ADD_2_AXB_69,
LO => R1IN_ADD_2_CRY_69);
R1IN_ADD_2_S_68: XORCY port map (
LI => R1IN_ADD_2_AXB_68,
CI => R1IN_ADD_2_CRY_67,
O => PRODUCT(85));
R1IN_ADD_2_CRY_68_Z6029: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_67,
S => R1IN_ADD_2_AXB_68,
LO => R1IN_ADD_2_CRY_68);
R1IN_ADD_2_S_67: XORCY port map (
LI => R1IN_ADD_2_AXB_67,
CI => R1IN_ADD_2_CRY_66,
O => PRODUCT(84));
R1IN_ADD_2_CRY_67_Z6031: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_66,
S => R1IN_ADD_2_AXB_67,
LO => R1IN_ADD_2_CRY_67);
R1IN_ADD_2_S_66: XORCY port map (
LI => R1IN_ADD_2_AXB_66,
CI => R1IN_ADD_2_CRY_65,
O => PRODUCT(83));
R1IN_ADD_2_CRY_66_Z6033: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_65,
S => R1IN_ADD_2_AXB_66,
LO => R1IN_ADD_2_CRY_66);
R1IN_ADD_2_S_65: XORCY port map (
LI => R1IN_ADD_2_AXB_65,
CI => R1IN_ADD_2_CRY_64,
O => PRODUCT(82));
R1IN_ADD_2_CRY_65_Z6035: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_64,
S => R1IN_ADD_2_AXB_65,
LO => R1IN_ADD_2_CRY_65);
R1IN_ADD_2_S_64: XORCY port map (
LI => R1IN_ADD_2_AXB_64,
CI => R1IN_ADD_2_CRY_63,
O => PRODUCT(81));
R1IN_ADD_2_CRY_64_Z6037: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_63,
S => R1IN_ADD_2_AXB_64,
LO => R1IN_ADD_2_CRY_64);
R1IN_ADD_2_S_63: XORCY port map (
LI => R1IN_ADD_2_AXB_63,
CI => R1IN_ADD_2_CRY_62,
O => PRODUCT(80));
R1IN_ADD_2_CRY_63_Z6039: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_62,
S => R1IN_ADD_2_AXB_63,
LO => R1IN_ADD_2_CRY_63);
R1IN_ADD_2_S_62: XORCY port map (
LI => R1IN_ADD_2_AXB_62,
CI => R1IN_ADD_2_CRY_61,
O => PRODUCT(79));
R1IN_ADD_2_CRY_62_Z6041: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_CRY_61,
S => R1IN_ADD_2_AXB_62,
LO => R1IN_ADD_2_CRY_62);
R1IN_ADD_2_S_61: XORCY port map (
LI => R1IN_ADD_2_AXB_61,
CI => R1IN_ADD_2_CRY_60,
O => PRODUCT(78));
R1IN_ADD_2_CRY_61_Z6043: MUXCY_L port map (
DI => R1IN_4(44),
CI => R1IN_ADD_2_CRY_60,
S => R1IN_ADD_2_AXB_61,
LO => R1IN_ADD_2_CRY_61);
R1IN_ADD_2_S_60: XORCY port map (
LI => R1IN_ADD_2_AXB_60,
CI => R1IN_ADD_2_CRY_59,
O => PRODUCT(77));
R1IN_ADD_2_CRY_60_Z6045: MUXCY_L port map (
DI => R1IN_4(43),
CI => R1IN_ADD_2_CRY_59,
S => R1IN_ADD_2_AXB_60,
LO => R1IN_ADD_2_CRY_60);
R1IN_ADD_2_S_59: XORCY port map (
LI => R1IN_ADD_2_AXB_59,
CI => R1IN_ADD_2_CRY_58,
O => PRODUCT(76));
R1IN_ADD_2_CRY_59_Z6047: MUXCY_L port map (
DI => R1IN_4(42),
CI => R1IN_ADD_2_CRY_58,
S => R1IN_ADD_2_AXB_59,
LO => R1IN_ADD_2_CRY_59);
R1IN_ADD_2_S_58: XORCY port map (
LI => R1IN_ADD_2_AXB_58,
CI => R1IN_ADD_2_CRY_57,
O => PRODUCT(75));
R1IN_ADD_2_CRY_58_Z6049: MUXCY_L port map (
DI => R1IN_4(41),
CI => R1IN_ADD_2_CRY_57,
S => R1IN_ADD_2_AXB_58,
LO => R1IN_ADD_2_CRY_58);
R1IN_ADD_2_S_57: XORCY port map (
LI => R1IN_ADD_2_AXB_57,
CI => R1IN_ADD_2_CRY_56,
O => PRODUCT(74));
R1IN_ADD_2_CRY_57_Z6051: MUXCY_L port map (
DI => R1IN_4(40),
CI => R1IN_ADD_2_CRY_56,
S => R1IN_ADD_2_AXB_57,
LO => R1IN_ADD_2_CRY_57);
R1IN_ADD_2_S_56: XORCY port map (
LI => R1IN_ADD_2_AXB_56,
CI => R1IN_ADD_2_CRY_55,
O => PRODUCT(73));
R1IN_ADD_2_CRY_56_Z6053: MUXCY_L port map (
DI => R1IN_4(39),
CI => R1IN_ADD_2_CRY_55,
S => R1IN_ADD_2_AXB_56,
LO => R1IN_ADD_2_CRY_56);
R1IN_ADD_2_S_55: XORCY port map (
LI => R1IN_ADD_2_AXB_55,
CI => R1IN_ADD_2_CRY_54,
O => PRODUCT(72));
R1IN_ADD_2_CRY_55_Z6055: MUXCY_L port map (
DI => R1IN_4(38),
CI => R1IN_ADD_2_CRY_54,
S => R1IN_ADD_2_AXB_55,
LO => R1IN_ADD_2_CRY_55);
R1IN_ADD_2_S_54: XORCY port map (
LI => R1IN_ADD_2_AXB_54,
CI => R1IN_ADD_2_CRY_53,
O => PRODUCT(71));
R1IN_ADD_2_CRY_54_Z6057: MUXCY_L port map (
DI => R1IN_4(37),
CI => R1IN_ADD_2_CRY_53,
S => R1IN_ADD_2_AXB_54,
LO => R1IN_ADD_2_CRY_54);
R1IN_ADD_2_S_53: XORCY port map (
LI => R1IN_ADD_2_AXB_53,
CI => R1IN_ADD_2_CRY_52,
O => PRODUCT(70));
R1IN_ADD_2_CRY_53_Z6059: MUXCY_L port map (
DI => R1IN_4(36),
CI => R1IN_ADD_2_CRY_52,
S => R1IN_ADD_2_AXB_53,
LO => R1IN_ADD_2_CRY_53);
R1IN_ADD_2_S_52: XORCY port map (
LI => R1IN_ADD_2_AXB_52,
CI => R1IN_ADD_2_CRY_51,
O => PRODUCT(69));
R1IN_ADD_2_CRY_52_Z6061: MUXCY_L port map (
DI => R1IN_4(35),
CI => R1IN_ADD_2_CRY_51,
S => R1IN_ADD_2_AXB_52,
LO => R1IN_ADD_2_CRY_52);
R1IN_ADD_2_S_51: XORCY port map (
LI => R1IN_ADD_2_AXB_51,
CI => R1IN_ADD_2_CRY_50,
O => PRODUCT(68));
R1IN_ADD_2_CRY_51_Z6063: MUXCY_L port map (
DI => R1IN_4(34),
CI => R1IN_ADD_2_CRY_50,
S => R1IN_ADD_2_AXB_51,
LO => R1IN_ADD_2_CRY_51);
R1IN_ADD_2_S_50: XORCY port map (
LI => R1IN_ADD_2_AXB_50,
CI => R1IN_ADD_2_CRY_49,
O => PRODUCT(67));
R1IN_ADD_2_CRY_50_Z6065: MUXCY_L port map (
DI => R1IN_4(33),
CI => R1IN_ADD_2_CRY_49,
S => R1IN_ADD_2_AXB_50,
LO => R1IN_ADD_2_CRY_50);
R1IN_ADD_2_S_49: XORCY port map (
LI => R1IN_ADD_2_AXB_49,
CI => R1IN_ADD_2_CRY_48,
O => PRODUCT(66));
R1IN_ADD_2_CRY_49_Z6067: MUXCY_L port map (
DI => R1IN_4(32),
CI => R1IN_ADD_2_CRY_48,
S => R1IN_ADD_2_AXB_49,
LO => R1IN_ADD_2_CRY_49);
R1IN_ADD_2_S_48: XORCY port map (
LI => R1IN_ADD_2_AXB_48,
CI => R1IN_ADD_2_CRY_47,
O => PRODUCT(65));
R1IN_ADD_2_CRY_48_Z6069: MUXCY_L port map (
DI => R1IN_4(31),
CI => R1IN_ADD_2_CRY_47,
S => R1IN_ADD_2_AXB_48,
LO => R1IN_ADD_2_CRY_48);
R1IN_ADD_2_S_47: XORCY port map (
LI => R1IN_ADD_2_AXB_47,
CI => R1IN_ADD_2_CRY_46,
O => PRODUCT(64));
R1IN_ADD_2_CRY_47_Z6071: MUXCY_L port map (
DI => R1IN_4(30),
CI => R1IN_ADD_2_CRY_46,
S => R1IN_ADD_2_AXB_47,
LO => R1IN_ADD_2_CRY_47);
R1IN_ADD_2_S_46: XORCY port map (
LI => R1IN_ADD_2_AXB_46,
CI => R1IN_ADD_2_CRY_45,
O => PRODUCT(63));
R1IN_ADD_2_CRY_46_Z6073: MUXCY_L port map (
DI => R1IN_4(29),
CI => R1IN_ADD_2_CRY_45,
S => R1IN_ADD_2_AXB_46,
LO => R1IN_ADD_2_CRY_46);
R1IN_ADD_2_S_45: XORCY port map (
LI => R1IN_ADD_2_AXB_45,
CI => R1IN_ADD_2_CRY_44,
O => PRODUCT(62));
R1IN_ADD_2_CRY_45_Z6075: MUXCY_L port map (
DI => R1IN_4(28),
CI => R1IN_ADD_2_CRY_44,
S => R1IN_ADD_2_AXB_45,
LO => R1IN_ADD_2_CRY_45);
R1IN_ADD_2_S_44: XORCY port map (
LI => R1IN_ADD_2_AXB_44,
CI => R1IN_ADD_2_CRY_43,
O => PRODUCT(61));
R1IN_ADD_2_CRY_44_Z6077: MUXCY_L port map (
DI => R1IN_4(27),
CI => R1IN_ADD_2_CRY_43,
S => R1IN_ADD_2_AXB_44,
LO => R1IN_ADD_2_CRY_44);
R1IN_ADD_2_S_43: XORCY port map (
LI => R1IN_ADD_2_AXB_43,
CI => R1IN_ADD_2_CRY_42,
O => PRODUCT(60));
R1IN_ADD_2_CRY_43_Z6079: MUXCY_L port map (
DI => R1IN_4(26),
CI => R1IN_ADD_2_CRY_42,
S => R1IN_ADD_2_AXB_43,
LO => R1IN_ADD_2_CRY_43);
R1IN_ADD_2_S_42: XORCY port map (
LI => R1IN_ADD_2_AXB_42,
CI => R1IN_ADD_2_CRY_41,
O => PRODUCT(59));
R1IN_ADD_2_CRY_42_Z6081: MUXCY_L port map (
DI => R1IN_4(25),
CI => R1IN_ADD_2_CRY_41,
S => R1IN_ADD_2_AXB_42,
LO => R1IN_ADD_2_CRY_42);
R1IN_ADD_2_S_41: XORCY port map (
LI => R1IN_ADD_2_AXB_41,
CI => R1IN_ADD_2_CRY_40,
O => PRODUCT(58));
R1IN_ADD_2_CRY_41_Z6083: MUXCY_L port map (
DI => R1IN_4(24),
CI => R1IN_ADD_2_CRY_40,
S => R1IN_ADD_2_AXB_41,
LO => R1IN_ADD_2_CRY_41);
R1IN_ADD_2_S_40: XORCY port map (
LI => R1IN_ADD_2_AXB_40,
CI => R1IN_ADD_2_CRY_39,
O => PRODUCT(57));
R1IN_ADD_2_CRY_40_Z6085: MUXCY_L port map (
DI => R1IN_4(23),
CI => R1IN_ADD_2_CRY_39,
S => R1IN_ADD_2_AXB_40,
LO => R1IN_ADD_2_CRY_40);
R1IN_ADD_2_S_39: XORCY port map (
LI => R1IN_ADD_2_AXB_39,
CI => R1IN_ADD_2_CRY_38,
O => PRODUCT(56));
R1IN_ADD_2_CRY_39_Z6087: MUXCY_L port map (
DI => R1IN_4(22),
CI => R1IN_ADD_2_CRY_38,
S => R1IN_ADD_2_AXB_39,
LO => R1IN_ADD_2_CRY_39);
R1IN_ADD_2_S_38: XORCY port map (
LI => R1IN_ADD_2_AXB_38,
CI => R1IN_ADD_2_CRY_37,
O => PRODUCT(55));
R1IN_ADD_2_CRY_38_Z6089: MUXCY_L port map (
DI => R1IN_4(21),
CI => R1IN_ADD_2_CRY_37,
S => R1IN_ADD_2_AXB_38,
LO => R1IN_ADD_2_CRY_38);
R1IN_ADD_2_S_37: XORCY port map (
LI => R1IN_ADD_2_AXB_37,
CI => R1IN_ADD_2_CRY_36,
O => PRODUCT(54));
R1IN_ADD_2_CRY_37_Z6091: MUXCY_L port map (
DI => R1IN_4(20),
CI => R1IN_ADD_2_CRY_36,
S => R1IN_ADD_2_AXB_37,
LO => R1IN_ADD_2_CRY_37);
R1IN_ADD_2_S_36: XORCY port map (
LI => R1IN_ADD_2_AXB_36,
CI => R1IN_ADD_2_CRY_35,
O => PRODUCT(53));
R1IN_ADD_2_CRY_36_Z6093: MUXCY_L port map (
DI => R1IN_4(19),
CI => R1IN_ADD_2_CRY_35,
S => R1IN_ADD_2_AXB_36,
LO => R1IN_ADD_2_CRY_36);
R1IN_ADD_2_S_35: XORCY port map (
LI => R1IN_ADD_2_AXB_35,
CI => R1IN_ADD_2_CRY_34,
O => PRODUCT(52));
R1IN_ADD_2_CRY_35_Z6095: MUXCY_L port map (
DI => R1IN_4(18),
CI => R1IN_ADD_2_CRY_34,
S => R1IN_ADD_2_AXB_35,
LO => R1IN_ADD_2_CRY_35);
R1IN_ADD_2_S_34: XORCY port map (
LI => R1IN_ADD_2_AXB_34,
CI => R1IN_ADD_2_CRY_33,
O => PRODUCT(51));
R1IN_ADD_2_CRY_34_Z6097: MUXCY_L port map (
DI => R1IN_4(17),
CI => R1IN_ADD_2_CRY_33,
S => R1IN_ADD_2_AXB_34,
LO => R1IN_ADD_2_CRY_34);
R1IN_ADD_2_S_33: XORCY port map (
LI => R1IN_ADD_2_AXB_33,
CI => R1IN_ADD_2_CRY_32,
O => PRODUCT(50));
R1IN_ADD_2_CRY_33_Z6099: MUXCY_L port map (
DI => R1IN_4FF(16),
CI => R1IN_ADD_2_CRY_32,
S => R1IN_ADD_2_AXB_33,
LO => R1IN_ADD_2_CRY_33);
R1IN_ADD_2_S_32: XORCY port map (
LI => R1IN_ADD_2_AXB_32,
CI => R1IN_ADD_2_CRY_31,
O => PRODUCT(49));
R1IN_ADD_2_CRY_32_Z6101: MUXCY_L port map (
DI => R1IN_4FF(15),
CI => R1IN_ADD_2_CRY_31,
S => R1IN_ADD_2_AXB_32,
LO => R1IN_ADD_2_CRY_32);
R1IN_ADD_2_S_31: XORCY port map (
LI => R1IN_ADD_2_AXB_31,
CI => R1IN_ADD_2_CRY_30,
O => PRODUCT(48));
R1IN_ADD_2_CRY_31_Z6103: MUXCY_L port map (
DI => R1IN_4FF(14),
CI => R1IN_ADD_2_CRY_30,
S => R1IN_ADD_2_AXB_31,
LO => R1IN_ADD_2_CRY_31);
R1IN_ADD_2_S_30: XORCY port map (
LI => R1IN_ADD_2_AXB_30,
CI => R1IN_ADD_2_CRY_29,
O => PRODUCT(47));
R1IN_ADD_2_CRY_30_Z6105: MUXCY_L port map (
DI => R1IN_4FF(13),
CI => R1IN_ADD_2_CRY_29,
S => R1IN_ADD_2_AXB_30,
LO => R1IN_ADD_2_CRY_30);
R1IN_ADD_2_S_29: XORCY port map (
LI => R1IN_ADD_2_AXB_29,
CI => R1IN_ADD_2_CRY_28,
O => PRODUCT(46));
R1IN_ADD_2_CRY_29_Z6107: MUXCY_L port map (
DI => R1IN_4FF(12),
CI => R1IN_ADD_2_CRY_28,
S => R1IN_ADD_2_AXB_29,
LO => R1IN_ADD_2_CRY_29);
R1IN_ADD_2_S_28: XORCY port map (
LI => R1IN_ADD_2_AXB_28,
CI => R1IN_ADD_2_CRY_27,
O => PRODUCT(45));
R1IN_ADD_2_CRY_28_Z6109: MUXCY_L port map (
DI => R1IN_4FF(11),
CI => R1IN_ADD_2_CRY_27,
S => R1IN_ADD_2_AXB_28,
LO => R1IN_ADD_2_CRY_28);
R1IN_ADD_2_S_27: XORCY port map (
LI => R1IN_ADD_2_AXB_27,
CI => R1IN_ADD_2_CRY_26,
O => PRODUCT(44));
R1IN_ADD_2_CRY_27_Z6111: MUXCY_L port map (
DI => R1IN_4FF(10),
CI => R1IN_ADD_2_CRY_26,
S => R1IN_ADD_2_AXB_27,
LO => R1IN_ADD_2_CRY_27);
R1IN_ADD_2_S_26: XORCY port map (
LI => R1IN_ADD_2_AXB_26,
CI => R1IN_ADD_2_CRY_25,
O => PRODUCT(43));
R1IN_ADD_2_CRY_26_Z6113: MUXCY_L port map (
DI => R1IN_4FF(9),
CI => R1IN_ADD_2_CRY_25,
S => R1IN_ADD_2_AXB_26,
LO => R1IN_ADD_2_CRY_26);
R1IN_ADD_2_S_25: XORCY port map (
LI => R1IN_ADD_2_AXB_25,
CI => R1IN_ADD_2_CRY_24,
O => PRODUCT(42));
R1IN_ADD_2_CRY_25_Z6115: MUXCY_L port map (
DI => R1IN_4FF(8),
CI => R1IN_ADD_2_CRY_24,
S => R1IN_ADD_2_AXB_25,
LO => R1IN_ADD_2_CRY_25);
R1IN_ADD_2_S_24: XORCY port map (
LI => R1IN_ADD_2_AXB_24,
CI => R1IN_ADD_2_CRY_23,
O => PRODUCT(41));
R1IN_ADD_2_CRY_24_Z6117: MUXCY_L port map (
DI => R1IN_4FF(7),
CI => R1IN_ADD_2_CRY_23,
S => R1IN_ADD_2_AXB_24,
LO => R1IN_ADD_2_CRY_24);
R1IN_ADD_2_S_23: XORCY port map (
LI => R1IN_ADD_2_AXB_23,
CI => R1IN_ADD_2_CRY_22,
O => PRODUCT(40));
R1IN_ADD_2_CRY_23_Z6119: MUXCY_L port map (
DI => R1IN_4FF(6),
CI => R1IN_ADD_2_CRY_22,
S => R1IN_ADD_2_AXB_23,
LO => R1IN_ADD_2_CRY_23);
R1IN_ADD_2_S_22: XORCY port map (
LI => R1IN_ADD_2_AXB_22,
CI => R1IN_ADD_2_CRY_21,
O => PRODUCT(39));
R1IN_ADD_2_CRY_22_Z6121: MUXCY_L port map (
DI => R1IN_4FF(5),
CI => R1IN_ADD_2_CRY_21,
S => R1IN_ADD_2_AXB_22,
LO => R1IN_ADD_2_CRY_22);
R1IN_ADD_2_S_21: XORCY port map (
LI => R1IN_ADD_2_AXB_21,
CI => R1IN_ADD_2_CRY_20,
O => PRODUCT(38));
R1IN_ADD_2_CRY_21_Z6123: MUXCY_L port map (
DI => R1IN_4FF(4),
CI => R1IN_ADD_2_CRY_20,
S => R1IN_ADD_2_AXB_21,
LO => R1IN_ADD_2_CRY_21);
R1IN_ADD_2_S_20: XORCY port map (
LI => R1IN_ADD_2_AXB_20,
CI => R1IN_ADD_2_CRY_19,
O => PRODUCT(37));
R1IN_ADD_2_CRY_20_Z6125: MUXCY_L port map (
DI => R1IN_4FF(3),
CI => R1IN_ADD_2_CRY_19,
S => R1IN_ADD_2_AXB_20,
LO => R1IN_ADD_2_CRY_20);
R1IN_ADD_2_S_19: XORCY port map (
LI => R1IN_ADD_2_AXB_19,
CI => R1IN_ADD_2_CRY_18,
O => PRODUCT(36));
R1IN_ADD_2_CRY_19_Z6127: MUXCY_L port map (
DI => R1IN_4FF(2),
CI => R1IN_ADD_2_CRY_18,
S => R1IN_ADD_2_AXB_19,
LO => R1IN_ADD_2_CRY_19);
R1IN_ADD_2_S_18: XORCY port map (
LI => R1IN_ADD_2_AXB_18,
CI => R1IN_ADD_2_CRY_17,
O => PRODUCT(35));
R1IN_ADD_2_CRY_18_Z6129: MUXCY_L port map (
DI => R1IN_4FF(1),
CI => R1IN_ADD_2_CRY_17,
S => R1IN_ADD_2_AXB_18,
LO => R1IN_ADD_2_CRY_18);
R1IN_ADD_2_S_17: XORCY port map (
LI => R1IN_ADD_2_AXB_17,
CI => R1IN_ADD_2_CRY_16,
O => PRODUCT(34));
R1IN_ADD_2_CRY_17_Z6131: MUXCY_L port map (
DI => R1IN_4FF(0),
CI => R1IN_ADD_2_CRY_16,
S => R1IN_ADD_2_AXB_17,
LO => R1IN_ADD_2_CRY_17);
R1IN_ADD_2_S_16: XORCY port map (
LI => R1IN_ADD_2_AXB_16,
CI => R1IN_ADD_2_CRY_15,
O => PRODUCT(33));
R1IN_ADD_2_CRY_16_Z6133: MUXCY_L port map (
DI => R1IN_1FF(33),
CI => R1IN_ADD_2_CRY_15,
S => R1IN_ADD_2_AXB_16,
LO => R1IN_ADD_2_CRY_16);
R1IN_ADD_2_S_15: XORCY port map (
LI => R1IN_ADD_2_AXB_15,
CI => R1IN_ADD_2_CRY_14,
O => PRODUCT(32));
R1IN_ADD_2_CRY_15_Z6135: MUXCY_L port map (
DI => R1IN_1FF(32),
CI => R1IN_ADD_2_CRY_14,
S => R1IN_ADD_2_AXB_15,
LO => R1IN_ADD_2_CRY_15);
R1IN_ADD_2_S_14: XORCY port map (
LI => R1IN_ADD_2_AXB_14,
CI => R1IN_ADD_2_CRY_13,
O => PRODUCT(31));
R1IN_ADD_2_CRY_14_Z6137: MUXCY_L port map (
DI => R1IN_1FF(31),
CI => R1IN_ADD_2_CRY_13,
S => R1IN_ADD_2_AXB_14,
LO => R1IN_ADD_2_CRY_14);
R1IN_ADD_2_S_13: XORCY port map (
LI => R1IN_ADD_2_AXB_13,
CI => R1IN_ADD_2_CRY_12,
O => PRODUCT(30));
R1IN_ADD_2_CRY_13_Z6139: MUXCY_L port map (
DI => R1IN_1FF(30),
CI => R1IN_ADD_2_CRY_12,
S => R1IN_ADD_2_AXB_13,
LO => R1IN_ADD_2_CRY_13);
R1IN_ADD_2_S_12: XORCY port map (
LI => R1IN_ADD_2_AXB_12,
CI => R1IN_ADD_2_CRY_11,
O => PRODUCT(29));
R1IN_ADD_2_CRY_12_Z6141: MUXCY_L port map (
DI => R1IN_1FF(29),
CI => R1IN_ADD_2_CRY_11,
S => R1IN_ADD_2_AXB_12,
LO => R1IN_ADD_2_CRY_12);
R1IN_ADD_2_S_11: XORCY port map (
LI => R1IN_ADD_2_AXB_11,
CI => R1IN_ADD_2_CRY_10,
O => PRODUCT(28));
R1IN_ADD_2_CRY_11_Z6143: MUXCY_L port map (
DI => R1IN_1FF(28),
CI => R1IN_ADD_2_CRY_10,
S => R1IN_ADD_2_AXB_11,
LO => R1IN_ADD_2_CRY_11);
R1IN_ADD_2_S_10: XORCY port map (
LI => R1IN_ADD_2_AXB_10,
CI => R1IN_ADD_2_CRY_9,
O => PRODUCT(27));
R1IN_ADD_2_CRY_10_Z6145: MUXCY_L port map (
DI => R1IN_1FF(27),
CI => R1IN_ADD_2_CRY_9,
S => R1IN_ADD_2_AXB_10,
LO => R1IN_ADD_2_CRY_10);
R1IN_ADD_2_S_9: XORCY port map (
LI => R1IN_ADD_2_AXB_9,
CI => R1IN_ADD_2_CRY_8,
O => PRODUCT(26));
R1IN_ADD_2_CRY_9_Z6147: MUXCY_L port map (
DI => R1IN_1FF(26),
CI => R1IN_ADD_2_CRY_8,
S => R1IN_ADD_2_AXB_9,
LO => R1IN_ADD_2_CRY_9);
R1IN_ADD_2_S_8: XORCY port map (
LI => R1IN_ADD_2_AXB_8,
CI => R1IN_ADD_2_CRY_7,
O => PRODUCT(25));
R1IN_ADD_2_CRY_8_Z6149: MUXCY_L port map (
DI => R1IN_1FF(25),
CI => R1IN_ADD_2_CRY_7,
S => R1IN_ADD_2_AXB_8,
LO => R1IN_ADD_2_CRY_8);
R1IN_ADD_2_S_7: XORCY port map (
LI => R1IN_ADD_2_AXB_7,
CI => R1IN_ADD_2_CRY_6,
O => PRODUCT(24));
R1IN_ADD_2_CRY_7_Z6151: MUXCY_L port map (
DI => R1IN_1FF(24),
CI => R1IN_ADD_2_CRY_6,
S => R1IN_ADD_2_AXB_7,
LO => R1IN_ADD_2_CRY_7);
R1IN_ADD_2_S_6: XORCY port map (
LI => R1IN_ADD_2_AXB_6,
CI => R1IN_ADD_2_CRY_5,
O => PRODUCT(23));
R1IN_ADD_2_CRY_6_Z6153: MUXCY_L port map (
DI => R1IN_1FF(23),
CI => R1IN_ADD_2_CRY_5,
S => R1IN_ADD_2_AXB_6,
LO => R1IN_ADD_2_CRY_6);
R1IN_ADD_2_S_5: XORCY port map (
LI => R1IN_ADD_2_AXB_5,
CI => R1IN_ADD_2_CRY_4,
O => PRODUCT(22));
R1IN_ADD_2_CRY_5_Z6155: MUXCY_L port map (
DI => R1IN_1FF(22),
CI => R1IN_ADD_2_CRY_4,
S => R1IN_ADD_2_AXB_5,
LO => R1IN_ADD_2_CRY_5);
R1IN_ADD_2_S_4: XORCY port map (
LI => R1IN_ADD_2_AXB_4,
CI => R1IN_ADD_2_CRY_3,
O => PRODUCT(21));
R1IN_ADD_2_CRY_4_Z6157: MUXCY_L port map (
DI => R1IN_1FF(21),
CI => R1IN_ADD_2_CRY_3,
S => R1IN_ADD_2_AXB_4,
LO => R1IN_ADD_2_CRY_4);
R1IN_ADD_2_S_3: XORCY port map (
LI => R1IN_ADD_2_AXB_3,
CI => R1IN_ADD_2_CRY_2,
O => PRODUCT(20));
R1IN_ADD_2_CRY_3_Z6159: MUXCY_L port map (
DI => R1IN_1FF(20),
CI => R1IN_ADD_2_CRY_2,
S => R1IN_ADD_2_AXB_3,
LO => R1IN_ADD_2_CRY_3);
R1IN_ADD_2_S_2: XORCY port map (
LI => R1IN_ADD_2_AXB_2,
CI => R1IN_ADD_2_CRY_1,
O => PRODUCT(19));
R1IN_ADD_2_CRY_2_Z6161: MUXCY_L port map (
DI => R1IN_1FF(19),
CI => R1IN_ADD_2_CRY_1,
S => R1IN_ADD_2_AXB_2,
LO => R1IN_ADD_2_CRY_2);
R1IN_ADD_2_S_1: XORCY port map (
LI => R1IN_ADD_2_AXB_1,
CI => R1IN_ADD_2_CRY_0,
O => PRODUCT(18));
R1IN_ADD_2_CRY_1_Z6163: MUXCY_L port map (
DI => R1IN_1FF(18),
CI => R1IN_ADD_2_CRY_0,
S => R1IN_ADD_2_AXB_1,
LO => R1IN_ADD_2_CRY_1);
R1IN_ADD_2_CRY_0_Z6164: MUXCY_L port map (
DI => R1IN_ADD_2,
CI => NN_1,
S => NN_3,
LO => R1IN_ADD_2_CRY_0);
R1IN_4_4_ADD_2_S_36: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_36,
CI => R1IN_4_4_ADD_2_CRY_35,
O => R1IN_4_4(53));
R1IN_4_4_ADD_2_S_35: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_35,
CI => R1IN_4_4_ADD_2_CRY_34,
O => R1IN_4_4(52));
R1IN_4_4_ADD_2_CRY_35_Z6167: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_4_ADD_2_CRY_34,
S => R1IN_4_4_ADD_2_AXB_35,
LO => R1IN_4_4_ADD_2_CRY_35);
R1IN_4_4_ADD_2_S_34: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_34,
CI => R1IN_4_4_ADD_2_CRY_33,
O => R1IN_4_4(51));
R1IN_4_4_ADD_2_CRY_34_Z6169: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_4_ADD_2_CRY_33,
S => R1IN_4_4_ADD_2_AXB_34,
LO => R1IN_4_4_ADD_2_CRY_34);
R1IN_4_4_ADD_2_S_33: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_33,
CI => R1IN_4_4_ADD_2_CRY_32,
O => R1IN_4_4(50));
R1IN_4_4_ADD_2_CRY_33_Z6171: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_4_ADD_2_CRY_32,
S => R1IN_4_4_ADD_2_AXB_33,
LO => R1IN_4_4_ADD_2_CRY_33);
R1IN_4_4_ADD_2_S_32: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_32,
CI => R1IN_4_4_ADD_2_CRY_31,
O => R1IN_4_4(49));
R1IN_4_4_ADD_2_CRY_32_Z6173: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_4_ADD_2_CRY_31,
S => R1IN_4_4_ADD_2_AXB_32,
LO => R1IN_4_4_ADD_2_CRY_32);
R1IN_4_4_ADD_2_S_31: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_31,
CI => R1IN_4_4_ADD_2_CRY_30,
O => R1IN_4_4(48));
R1IN_4_4_ADD_2_CRY_31_Z6175: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_4_ADD_2_CRY_30,
S => R1IN_4_4_ADD_2_AXB_31,
LO => R1IN_4_4_ADD_2_CRY_31);
R1IN_4_4_ADD_2_S_30: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_30,
CI => R1IN_4_4_ADD_2_CRY_29,
O => R1IN_4_4(47));
R1IN_4_4_ADD_2_CRY_30_Z6177: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_4_ADD_2_CRY_29,
S => R1IN_4_4_ADD_2_AXB_30,
LO => R1IN_4_4_ADD_2_CRY_30);
R1IN_4_4_ADD_2_S_29: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_29,
CI => R1IN_4_4_ADD_2_CRY_28,
O => R1IN_4_4(46));
R1IN_4_4_ADD_2_CRY_29_Z6179: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_4_ADD_2_CRY_28,
S => R1IN_4_4_ADD_2_AXB_29,
LO => R1IN_4_4_ADD_2_CRY_29);
R1IN_4_4_ADD_2_S_28: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_28,
CI => R1IN_4_4_ADD_2_CRY_27,
O => R1IN_4_4(45));
R1IN_4_4_ADD_2_CRY_28_Z6181: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_4_ADD_2_CRY_27,
S => R1IN_4_4_ADD_2_AXB_28,
LO => R1IN_4_4_ADD_2_CRY_28);
R1IN_4_4_ADD_2_S_27: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_27,
CI => R1IN_4_4_ADD_2_CRY_26,
O => R1IN_4_4(44));
R1IN_4_4_ADD_2_CRY_27_Z6183: MUXCY_L port map (
DI => R1IN_4_4_4F_RETO(10),
CI => R1IN_4_4_ADD_2_CRY_26,
S => R1IN_4_4_ADD_2_AXB_27,
LO => R1IN_4_4_ADD_2_CRY_27);
R1IN_4_4_ADD_2_S_26: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_26,
CI => R1IN_4_4_ADD_2_CRY_25,
O => R1IN_4_4(43));
R1IN_4_4_ADD_2_CRY_26_Z6185: MUXCY_L port map (
DI => R1IN_4_4_4F_RETO(9),
CI => R1IN_4_4_ADD_2_CRY_25,
S => R1IN_4_4_ADD_2_AXB_26,
LO => R1IN_4_4_ADD_2_CRY_26);
R1IN_4_4_ADD_2_S_25: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_25,
CI => R1IN_4_4_ADD_2_CRY_24,
O => R1IN_4_4(42));
R1IN_4_4_ADD_2_CRY_25_Z6187: MUXCY_L port map (
DI => R1IN_4_4_4F_RETO(8),
CI => R1IN_4_4_ADD_2_CRY_24,
S => R1IN_4_4_ADD_2_AXB_25,
LO => R1IN_4_4_ADD_2_CRY_25);
R1IN_4_4_ADD_2_S_24: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_24,
CI => R1IN_4_4_ADD_2_CRY_23,
O => R1IN_4_4(41));
R1IN_4_4_ADD_2_CRY_24_Z6189: MUXCY_L port map (
DI => R1IN_4_4_4F_RETO(7),
CI => R1IN_4_4_ADD_2_CRY_23,
S => R1IN_4_4_ADD_2_AXB_24,
LO => R1IN_4_4_ADD_2_CRY_24);
R1IN_4_4_ADD_2_S_23: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_23,
CI => R1IN_4_4_ADD_2_CRY_22,
O => R1IN_4_4(40));
R1IN_4_4_ADD_2_CRY_23_Z6191: MUXCY_L port map (
DI => R1IN_4_4_4F_RETO(6),
CI => R1IN_4_4_ADD_2_CRY_22,
S => R1IN_4_4_ADD_2_AXB_23,
LO => R1IN_4_4_ADD_2_CRY_23);
R1IN_4_4_ADD_2_S_22: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_22,
CI => R1IN_4_4_ADD_2_CRY_21,
O => R1IN_4_4(39));
R1IN_4_4_ADD_2_CRY_22_Z6193: MUXCY_L port map (
DI => R1IN_4_4_4F_RETO(5),
CI => R1IN_4_4_ADD_2_CRY_21,
S => R1IN_4_4_ADD_2_AXB_22,
LO => R1IN_4_4_ADD_2_CRY_22);
R1IN_4_4_ADD_2_S_21: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_21,
CI => R1IN_4_4_ADD_2_CRY_20,
O => R1IN_4_4(38));
R1IN_4_4_ADD_2_CRY_21_Z6195: MUXCY_L port map (
DI => R1IN_4_4_4F_RETO(4),
CI => R1IN_4_4_ADD_2_CRY_20,
S => R1IN_4_4_ADD_2_AXB_21,
LO => R1IN_4_4_ADD_2_CRY_21);
R1IN_4_4_ADD_2_S_20: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_20,
CI => R1IN_4_4_ADD_2_CRY_19,
O => R1IN_4_4(37));
R1IN_4_4_ADD_2_CRY_20_Z6197: MUXCY_L port map (
DI => R1IN_4_4_4F_RETO(3),
CI => R1IN_4_4_ADD_2_CRY_19,
S => R1IN_4_4_ADD_2_AXB_20,
LO => R1IN_4_4_ADD_2_CRY_20);
R1IN_4_4_ADD_2_S_19: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_19,
CI => R1IN_4_4_ADD_2_CRY_18,
O => R1IN_4_4(36));
R1IN_4_4_ADD_2_CRY_19_Z6199: MUXCY_L port map (
DI => R1IN_4_4_4F_RETO(2),
CI => R1IN_4_4_ADD_2_CRY_18,
S => R1IN_4_4_ADD_2_AXB_19,
LO => R1IN_4_4_ADD_2_CRY_19);
R1IN_4_4_ADD_2_S_18: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_18,
CI => R1IN_4_4_ADD_2_CRY_17,
O => R1IN_4_4(35));
R1IN_4_4_ADD_2_CRY_18_Z6201: MUXCY_L port map (
DI => R1IN_4_4_4F_RETO(1),
CI => R1IN_4_4_ADD_2_CRY_17,
S => R1IN_4_4_ADD_2_AXB_18,
LO => R1IN_4_4_ADD_2_CRY_18);
R1IN_4_4_ADD_2_S_17: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_17,
CI => R1IN_4_4_ADD_2_CRY_16,
O => R1IN_4_4(34));
R1IN_4_4_ADD_2_CRY_17_Z6203: MUXCY_L port map (
DI => R1IN_4_4_4F_RETO(0),
CI => R1IN_4_4_ADD_2_CRY_16,
S => R1IN_4_4_ADD_2_AXB_17,
LO => R1IN_4_4_ADD_2_CRY_17);
R1IN_4_4_ADD_2_S_16: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_16,
CI => R1IN_4_4_ADD_2_CRY_15,
O => R1IN_4_4(33));
R1IN_4_4_ADD_2_CRY_16_Z6205: MUXCY_L port map (
DI => R1IN_4_4_1F_RETO(33),
CI => R1IN_4_4_ADD_2_CRY_15,
S => R1IN_4_4_ADD_2_AXB_16,
LO => R1IN_4_4_ADD_2_CRY_16);
R1IN_4_4_ADD_2_S_15: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_15,
CI => R1IN_4_4_ADD_2_CRY_14,
O => R1IN_4_4(32));
R1IN_4_4_ADD_2_CRY_15_Z6207: MUXCY_L port map (
DI => R1IN_4_4_1F_RETO(32),
CI => R1IN_4_4_ADD_2_CRY_14,
S => R1IN_4_4_ADD_2_AXB_15,
LO => R1IN_4_4_ADD_2_CRY_15);
R1IN_4_4_ADD_2_S_14: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_14,
CI => R1IN_4_4_ADD_2_CRY_13,
O => R1IN_4_4(31));
R1IN_4_4_ADD_2_CRY_14_Z6209: MUXCY_L port map (
DI => R1IN_4_4_1F_RETO(31),
CI => R1IN_4_4_ADD_2_CRY_13,
S => R1IN_4_4_ADD_2_AXB_14,
LO => R1IN_4_4_ADD_2_CRY_14);
R1IN_4_4_ADD_2_S_13: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_13,
CI => R1IN_4_4_ADD_2_CRY_12,
O => R1IN_4_4(30));
R1IN_4_4_ADD_2_CRY_13_Z6211: MUXCY_L port map (
DI => R1IN_4_4_1F_RETO(30),
CI => R1IN_4_4_ADD_2_CRY_12,
S => R1IN_4_4_ADD_2_AXB_13,
LO => R1IN_4_4_ADD_2_CRY_13);
R1IN_4_4_ADD_2_S_12: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_12,
CI => R1IN_4_4_ADD_2_CRY_11,
O => R1IN_4_4(29));
R1IN_4_4_ADD_2_CRY_12_Z6213: MUXCY_L port map (
DI => R1IN_4_4_1F_RETO(29),
CI => R1IN_4_4_ADD_2_CRY_11,
S => R1IN_4_4_ADD_2_AXB_12,
LO => R1IN_4_4_ADD_2_CRY_12);
R1IN_4_4_ADD_2_S_11: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_11,
CI => R1IN_4_4_ADD_2_CRY_10,
O => R1IN_4_4(28));
R1IN_4_4_ADD_2_CRY_11_Z6215: MUXCY_L port map (
DI => R1IN_4_4_1F_RETO(28),
CI => R1IN_4_4_ADD_2_CRY_10,
S => R1IN_4_4_ADD_2_AXB_11,
LO => R1IN_4_4_ADD_2_CRY_11);
R1IN_4_4_ADD_2_S_10: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_10,
CI => R1IN_4_4_ADD_2_CRY_9,
O => R1IN_4_4(27));
R1IN_4_4_ADD_2_CRY_10_Z6217: MUXCY_L port map (
DI => R1IN_4_4_1F_RETO(27),
CI => R1IN_4_4_ADD_2_CRY_9,
S => R1IN_4_4_ADD_2_AXB_10,
LO => R1IN_4_4_ADD_2_CRY_10);
R1IN_4_4_ADD_2_S_9: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_9,
CI => R1IN_4_4_ADD_2_CRY_8,
O => R1IN_4_4(26));
R1IN_4_4_ADD_2_CRY_9_Z6219: MUXCY_L port map (
DI => R1IN_4_4_1F_RETO(26),
CI => R1IN_4_4_ADD_2_CRY_8,
S => R1IN_4_4_ADD_2_AXB_9,
LO => R1IN_4_4_ADD_2_CRY_9);
R1IN_4_4_ADD_2_S_8: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_8,
CI => R1IN_4_4_ADD_2_CRY_7,
O => R1IN_4_4(25));
R1IN_4_4_ADD_2_CRY_8_Z6221: MUXCY_L port map (
DI => R1IN_4_4_1F_RETO(25),
CI => R1IN_4_4_ADD_2_CRY_7,
S => R1IN_4_4_ADD_2_AXB_8,
LO => R1IN_4_4_ADD_2_CRY_8);
R1IN_4_4_ADD_2_S_7: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_7,
CI => R1IN_4_4_ADD_2_CRY_6,
O => R1IN_4_4(24));
R1IN_4_4_ADD_2_CRY_7_Z6223: MUXCY_L port map (
DI => R1IN_4_4_1F_RETO(24),
CI => R1IN_4_4_ADD_2_CRY_6,
S => R1IN_4_4_ADD_2_AXB_7,
LO => R1IN_4_4_ADD_2_CRY_7);
R1IN_4_4_ADD_2_S_6: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_6,
CI => R1IN_4_4_ADD_2_CRY_5,
O => R1IN_4_4(23));
R1IN_4_4_ADD_2_CRY_6_Z6225: MUXCY_L port map (
DI => R1IN_4_4_1F_RETO(23),
CI => R1IN_4_4_ADD_2_CRY_5,
S => R1IN_4_4_ADD_2_AXB_6,
LO => R1IN_4_4_ADD_2_CRY_6);
R1IN_4_4_ADD_2_S_5: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_5,
CI => R1IN_4_4_ADD_2_CRY_4,
O => R1IN_4_4(22));
R1IN_4_4_ADD_2_CRY_5_Z6227: MUXCY_L port map (
DI => R1IN_4_4_1F_RETO(22),
CI => R1IN_4_4_ADD_2_CRY_4,
S => R1IN_4_4_ADD_2_AXB_5,
LO => R1IN_4_4_ADD_2_CRY_5);
R1IN_4_4_ADD_2_S_4: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_4,
CI => R1IN_4_4_ADD_2_CRY_3,
O => R1IN_4_4(21));
R1IN_4_4_ADD_2_CRY_4_Z6229: MUXCY_L port map (
DI => R1IN_4_4_1F_RETO(21),
CI => R1IN_4_4_ADD_2_CRY_3,
S => R1IN_4_4_ADD_2_AXB_4,
LO => R1IN_4_4_ADD_2_CRY_4);
R1IN_4_4_ADD_2_S_3: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_3,
CI => R1IN_4_4_ADD_2_CRY_2,
O => R1IN_4_4(20));
R1IN_4_4_ADD_2_CRY_3_Z6231: MUXCY_L port map (
DI => R1IN_4_4_1F_RETO(20),
CI => R1IN_4_4_ADD_2_CRY_2,
S => R1IN_4_4_ADD_2_AXB_3,
LO => R1IN_4_4_ADD_2_CRY_3);
R1IN_4_4_ADD_2_S_2: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_2,
CI => R1IN_4_4_ADD_2_CRY_1,
O => R1IN_4_4(19));
R1IN_4_4_ADD_2_CRY_2_Z6233: MUXCY_L port map (
DI => R1IN_4_4_1F_RETO(19),
CI => R1IN_4_4_ADD_2_CRY_1,
S => R1IN_4_4_ADD_2_AXB_2,
LO => R1IN_4_4_ADD_2_CRY_2);
R1IN_4_4_ADD_2_S_1: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_1,
CI => R1IN_4_4_ADD_2_CRY_0,
O => R1IN_4_4(18));
R1IN_4_4_ADD_2_CRY_1_Z6235: MUXCY_L port map (
DI => R1IN_4_4_1F_RETO(18),
CI => R1IN_4_4_ADD_2_CRY_0,
S => R1IN_4_4_ADD_2_AXB_1,
LO => R1IN_4_4_ADD_2_CRY_1);
R1IN_4_4_ADD_2_CRY_0_Z6236: MUXCY_L port map (
DI => R1IN_4_4_ADD_2_RETO_0,
CI => NN_1,
S => R1IN_4_4(17),
LO => R1IN_4_4_ADD_2_CRY_0);
R1IN_3_ADD_1_S_43: XORCY port map (
LI => R1IN_3_ADD_1_AXB_43,
CI => R1IN_3_ADD_1_CRY_42,
O => R1IN_3(60));
R1IN_3_ADD_1_S_42: XORCY port map (
LI => R1IN_3_ADD_1_AXB_42,
CI => R1IN_3_ADD_1_CRY_41,
O => R1IN_3(59));
R1IN_3_ADD_1_CRY_42_Z6239: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_41,
S => R1IN_3_ADD_1_AXB_42,
LO => R1IN_3_ADD_1_CRY_42);
R1IN_3_ADD_1_S_41: XORCY port map (
LI => R1IN_3_ADD_1_AXB_41,
CI => R1IN_3_ADD_1_CRY_40,
O => R1IN_3(58));
R1IN_3_ADD_1_CRY_41_Z6241: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_40,
S => R1IN_3_ADD_1_AXB_41,
LO => R1IN_3_ADD_1_CRY_41);
R1IN_3_ADD_1_S_40: XORCY port map (
LI => R1IN_3_ADD_1_AXB_40,
CI => R1IN_3_ADD_1_CRY_39,
O => R1IN_3(57));
R1IN_3_ADD_1_CRY_40_Z6243: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_39,
S => R1IN_3_ADD_1_AXB_40,
LO => R1IN_3_ADD_1_CRY_40);
R1IN_3_ADD_1_S_39: XORCY port map (
LI => R1IN_3_ADD_1_AXB_39,
CI => R1IN_3_ADD_1_CRY_38,
O => R1IN_3(56));
R1IN_3_ADD_1_CRY_39_Z6245: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_38,
S => R1IN_3_ADD_1_AXB_39,
LO => R1IN_3_ADD_1_CRY_39);
R1IN_3_ADD_1_S_38: XORCY port map (
LI => R1IN_3_ADD_1_AXB_38,
CI => R1IN_3_ADD_1_CRY_37,
O => R1IN_3(55));
R1IN_3_ADD_1_CRY_38_Z6247: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_37,
S => R1IN_3_ADD_1_AXB_38,
LO => R1IN_3_ADD_1_CRY_38);
R1IN_3_ADD_1_S_37: XORCY port map (
LI => R1IN_3_ADD_1_AXB_37,
CI => R1IN_3_ADD_1_CRY_36,
O => R1IN_3(54));
R1IN_3_ADD_1_CRY_37_Z6249: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_36,
S => R1IN_3_ADD_1_AXB_37,
LO => R1IN_3_ADD_1_CRY_37);
R1IN_3_ADD_1_S_36: XORCY port map (
LI => R1IN_3_ADD_1_AXB_36,
CI => R1IN_3_ADD_1_CRY_35,
O => R1IN_3(53));
R1IN_3_ADD_1_CRY_36_Z6251: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_35,
S => R1IN_3_ADD_1_AXB_36,
LO => R1IN_3_ADD_1_CRY_36);
R1IN_3_ADD_1_S_35: XORCY port map (
LI => R1IN_3_ADD_1_AXB_35,
CI => R1IN_3_ADD_1_CRY_34,
O => R1IN_3(52));
R1IN_3_ADD_1_CRY_35_Z6253: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_34,
S => R1IN_3_ADD_1_AXB_35,
LO => R1IN_3_ADD_1_CRY_35);
R1IN_3_ADD_1_S_34: XORCY port map (
LI => R1IN_3_ADD_1_AXB_34,
CI => R1IN_3_ADD_1_CRY_33,
O => R1IN_3(51));
R1IN_3_ADD_1_CRY_34_Z6255: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_33,
S => R1IN_3_ADD_1_AXB_34,
LO => R1IN_3_ADD_1_CRY_34);
R1IN_3_ADD_1_S_33: XORCY port map (
LI => R1IN_3_ADD_1_AXB_33,
CI => R1IN_3_ADD_1_CRY_32,
O => R1IN_3(50));
R1IN_3_ADD_1_CRY_33_Z6257: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_32,
S => R1IN_3_ADD_1_AXB_33,
LO => R1IN_3_ADD_1_CRY_33);
R1IN_3_ADD_1_S_32: XORCY port map (
LI => R1IN_3_ADD_1_AXB_32,
CI => R1IN_3_ADD_1_CRY_31,
O => R1IN_3(49));
R1IN_3_ADD_1_CRY_32_Z6259: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_31,
S => R1IN_3_ADD_1_AXB_32,
LO => R1IN_3_ADD_1_CRY_32);
R1IN_3_ADD_1_S_31: XORCY port map (
LI => R1IN_3_ADD_1_AXB_31,
CI => R1IN_3_ADD_1_CRY_30,
O => R1IN_3(48));
R1IN_3_ADD_1_CRY_31_Z6261: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_30,
S => R1IN_3_ADD_1_AXB_31,
LO => R1IN_3_ADD_1_CRY_31);
R1IN_3_ADD_1_S_30: XORCY port map (
LI => R1IN_3_ADD_1_AXB_30,
CI => R1IN_3_ADD_1_CRY_29,
O => R1IN_3(47));
R1IN_3_ADD_1_CRY_30_Z6263: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_29,
S => R1IN_3_ADD_1_AXB_30,
LO => R1IN_3_ADD_1_CRY_30);
R1IN_3_ADD_1_S_29: XORCY port map (
LI => R1IN_3_ADD_1_AXB_29,
CI => R1IN_3_ADD_1_CRY_28,
O => R1IN_3(46));
R1IN_3_ADD_1_CRY_29_Z6265: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_28,
S => R1IN_3_ADD_1_AXB_29,
LO => R1IN_3_ADD_1_CRY_29);
R1IN_3_ADD_1_S_28: XORCY port map (
LI => R1IN_3_ADD_1_AXB_28,
CI => R1IN_3_ADD_1_CRY_27,
O => R1IN_3(45));
R1IN_3_ADD_1_CRY_28_Z6267: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_27,
S => R1IN_3_ADD_1_AXB_28,
LO => R1IN_3_ADD_1_CRY_28);
R1IN_3_ADD_1_S_27: XORCY port map (
LI => R1IN_3_ADD_1_AXB_27,
CI => R1IN_3_ADD_1_CRY_26,
O => R1IN_3(44));
R1IN_3_ADD_1_CRY_27_Z6269: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_26,
S => R1IN_3_ADD_1_AXB_27,
LO => R1IN_3_ADD_1_CRY_27);
R1IN_3_ADD_1_S_26: XORCY port map (
LI => R1IN_3_ADD_1_AXB_26,
CI => R1IN_3_ADD_1_CRY_25,
O => R1IN_3(43));
R1IN_3_ADD_1_CRY_26_Z6271: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_25,
S => R1IN_3_ADD_1_AXB_26,
LO => R1IN_3_ADD_1_CRY_26);
R1IN_3_ADD_1_S_25: XORCY port map (
LI => R1IN_3_ADD_1_AXB_25,
CI => R1IN_3_ADD_1_CRY_24,
O => R1IN_3(42));
R1IN_3_ADD_1_CRY_25_Z6273: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_24,
S => R1IN_3_ADD_1_AXB_25,
LO => R1IN_3_ADD_1_CRY_25);
R1IN_3_ADD_1_S_24: XORCY port map (
LI => R1IN_3_ADD_1_AXB_24,
CI => R1IN_3_ADD_1_CRY_23,
O => R1IN_3(41));
R1IN_3_ADD_1_CRY_24_Z6275: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_23,
S => R1IN_3_ADD_1_AXB_24,
LO => R1IN_3_ADD_1_CRY_24);
R1IN_3_ADD_1_S_23: XORCY port map (
LI => R1IN_3_ADD_1_AXB_23,
CI => R1IN_3_ADD_1_CRY_22,
O => R1IN_3(40));
R1IN_3_ADD_1_CRY_23_Z6277: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_22,
S => R1IN_3_ADD_1_AXB_23,
LO => R1IN_3_ADD_1_CRY_23);
R1IN_3_ADD_1_S_22: XORCY port map (
LI => R1IN_3_ADD_1_AXB_22,
CI => R1IN_3_ADD_1_CRY_21,
O => R1IN_3(39));
R1IN_3_ADD_1_CRY_22_Z6279: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_21,
S => R1IN_3_ADD_1_AXB_22,
LO => R1IN_3_ADD_1_CRY_22);
R1IN_3_ADD_1_S_21: XORCY port map (
LI => R1IN_3_ADD_1_AXB_21,
CI => R1IN_3_ADD_1_CRY_20,
O => R1IN_3(38));
R1IN_3_ADD_1_CRY_21_Z6281: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_20,
S => R1IN_3_ADD_1_AXB_21,
LO => R1IN_3_ADD_1_CRY_21);
R1IN_3_ADD_1_S_20: XORCY port map (
LI => R1IN_3_ADD_1_AXB_20,
CI => R1IN_3_ADD_1_CRY_19,
O => R1IN_3(37));
R1IN_3_ADD_1_CRY_20_Z6283: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_19,
S => R1IN_3_ADD_1_AXB_20,
LO => R1IN_3_ADD_1_CRY_20);
R1IN_3_ADD_1_S_19: XORCY port map (
LI => R1IN_3_ADD_1_AXB_19,
CI => R1IN_3_ADD_1_CRY_18,
O => R1IN_3(36));
R1IN_3_ADD_1_CRY_19_Z6285: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_18,
S => R1IN_3_ADD_1_AXB_19,
LO => R1IN_3_ADD_1_CRY_19);
R1IN_3_ADD_1_S_18: XORCY port map (
LI => R1IN_3_ADD_1_AXB_18,
CI => R1IN_3_ADD_1_CRY_17,
O => R1IN_3(35));
R1IN_3_ADD_1_CRY_18_Z6287: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_17,
S => R1IN_3_ADD_1_AXB_18,
LO => R1IN_3_ADD_1_CRY_18);
R1IN_3_ADD_1_S_17: XORCY port map (
LI => R1IN_3_ADD_1_AXB_17,
CI => R1IN_3_ADD_1_CRY_16,
O => R1IN_3(34));
R1IN_3_ADD_1_CRY_17_Z6289: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_16,
S => R1IN_3_ADD_1_AXB_17,
LO => R1IN_3_ADD_1_CRY_17);
R1IN_3_ADD_1_S_16: XORCY port map (
LI => R1IN_3_ADD_1_AXB_16,
CI => R1IN_3_ADD_1_CRY_15,
O => R1IN_3(33));
R1IN_3_ADD_1_CRY_16_Z6291: MUXCY_L port map (
DI => R1IN_3_2F_RETO(16),
CI => R1IN_3_ADD_1_CRY_15,
S => R1IN_3_ADD_1_AXB_16,
LO => R1IN_3_ADD_1_CRY_16);
R1IN_3_ADD_1_S_15: XORCY port map (
LI => R1IN_3_ADD_1_AXB_15,
CI => R1IN_3_ADD_1_CRY_14,
O => R1IN_3(32));
R1IN_3_ADD_1_CRY_15_Z6293: MUXCY_L port map (
DI => R1IN_3_2F_RETO(15),
CI => R1IN_3_ADD_1_CRY_14,
S => R1IN_3_ADD_1_AXB_15,
LO => R1IN_3_ADD_1_CRY_15);
R1IN_3_ADD_1_S_14: XORCY port map (
LI => R1IN_3_ADD_1_AXB_14,
CI => R1IN_3_ADD_1_CRY_13,
O => R1IN_3(31));
R1IN_3_ADD_1_CRY_14_Z6295: MUXCY_L port map (
DI => R1IN_3_2F_RETO(14),
CI => R1IN_3_ADD_1_CRY_13,
S => R1IN_3_ADD_1_AXB_14,
LO => R1IN_3_ADD_1_CRY_14);
R1IN_3_ADD_1_S_13: XORCY port map (
LI => R1IN_3_ADD_1_AXB_13,
CI => R1IN_3_ADD_1_CRY_12,
O => R1IN_3(30));
R1IN_3_ADD_1_CRY_13_Z6297: MUXCY_L port map (
DI => R1IN_3_2F_RETO(13),
CI => R1IN_3_ADD_1_CRY_12,
S => R1IN_3_ADD_1_AXB_13,
LO => R1IN_3_ADD_1_CRY_13);
R1IN_3_ADD_1_S_12: XORCY port map (
LI => R1IN_3_ADD_1_AXB_12,
CI => R1IN_3_ADD_1_CRY_11,
O => R1IN_3(29));
R1IN_3_ADD_1_CRY_12_Z6299: MUXCY_L port map (
DI => R1IN_3_2F_RETO(12),
CI => R1IN_3_ADD_1_CRY_11,
S => R1IN_3_ADD_1_AXB_12,
LO => R1IN_3_ADD_1_CRY_12);
R1IN_3_ADD_1_S_11: XORCY port map (
LI => R1IN_3_ADD_1_AXB_11,
CI => R1IN_3_ADD_1_CRY_10,
O => R1IN_3(28));
R1IN_3_ADD_1_CRY_11_Z6301: MUXCY_L port map (
DI => R1IN_3_2F_RETO(11),
CI => R1IN_3_ADD_1_CRY_10,
S => R1IN_3_ADD_1_AXB_11,
LO => R1IN_3_ADD_1_CRY_11);
R1IN_3_ADD_1_S_10: XORCY port map (
LI => R1IN_3_ADD_1_AXB_10,
CI => R1IN_3_ADD_1_CRY_9,
O => R1IN_3(27));
R1IN_3_ADD_1_CRY_10_Z6303: MUXCY_L port map (
DI => R1IN_3_2F_RETO(10),
CI => R1IN_3_ADD_1_CRY_9,
S => R1IN_3_ADD_1_AXB_10,
LO => R1IN_3_ADD_1_CRY_10);
R1IN_3_ADD_1_S_9: XORCY port map (
LI => R1IN_3_ADD_1_AXB_9,
CI => R1IN_3_ADD_1_CRY_8,
O => R1IN_3(26));
R1IN_3_ADD_1_CRY_9_Z6305: MUXCY_L port map (
DI => R1IN_3_2F_RETO(9),
CI => R1IN_3_ADD_1_CRY_8,
S => R1IN_3_ADD_1_AXB_9,
LO => R1IN_3_ADD_1_CRY_9);
R1IN_3_ADD_1_S_8: XORCY port map (
LI => R1IN_3_ADD_1_AXB_8,
CI => R1IN_3_ADD_1_CRY_7,
O => R1IN_3(25));
R1IN_3_ADD_1_CRY_8_Z6307: MUXCY_L port map (
DI => R1IN_3_2F_RETO(8),
CI => R1IN_3_ADD_1_CRY_7,
S => R1IN_3_ADD_1_AXB_8,
LO => R1IN_3_ADD_1_CRY_8);
R1IN_3_ADD_1_S_7: XORCY port map (
LI => R1IN_3_ADD_1_AXB_7,
CI => R1IN_3_ADD_1_CRY_6,
O => R1IN_3(24));
R1IN_3_ADD_1_CRY_7_Z6309: MUXCY_L port map (
DI => R1IN_3_2F_RETO(7),
CI => R1IN_3_ADD_1_CRY_6,
S => R1IN_3_ADD_1_AXB_7,
LO => R1IN_3_ADD_1_CRY_7);
R1IN_3_ADD_1_S_6: XORCY port map (
LI => R1IN_3_ADD_1_AXB_6,
CI => R1IN_3_ADD_1_CRY_5,
O => R1IN_3(23));
R1IN_3_ADD_1_CRY_6_Z6311: MUXCY_L port map (
DI => R1IN_3_2F_RETO(6),
CI => R1IN_3_ADD_1_CRY_5,
S => R1IN_3_ADD_1_AXB_6,
LO => R1IN_3_ADD_1_CRY_6);
R1IN_3_ADD_1_S_5: XORCY port map (
LI => R1IN_3_ADD_1_AXB_5,
CI => R1IN_3_ADD_1_CRY_4,
O => R1IN_3(22));
R1IN_3_ADD_1_CRY_5_Z6313: MUXCY_L port map (
DI => R1IN_3_2F_RETO(5),
CI => R1IN_3_ADD_1_CRY_4,
S => R1IN_3_ADD_1_AXB_5,
LO => R1IN_3_ADD_1_CRY_5);
R1IN_3_ADD_1_S_4: XORCY port map (
LI => R1IN_3_ADD_1_AXB_4,
CI => R1IN_3_ADD_1_CRY_3,
O => R1IN_3(21));
R1IN_3_ADD_1_CRY_4_Z6315: MUXCY_L port map (
DI => R1IN_3_2F_RETO(4),
CI => R1IN_3_ADD_1_CRY_3,
S => R1IN_3_ADD_1_AXB_4,
LO => R1IN_3_ADD_1_CRY_4);
R1IN_3_ADD_1_S_3: XORCY port map (
LI => R1IN_3_ADD_1_AXB_3,
CI => R1IN_3_ADD_1_CRY_2,
O => R1IN_3(20));
R1IN_3_ADD_1_CRY_3_Z6317: MUXCY_L port map (
DI => R1IN_3_2F_RETO(3),
CI => R1IN_3_ADD_1_CRY_2,
S => R1IN_3_ADD_1_AXB_3,
LO => R1IN_3_ADD_1_CRY_3);
R1IN_3_ADD_1_S_2: XORCY port map (
LI => R1IN_3_ADD_1_AXB_2,
CI => R1IN_3_ADD_1_CRY_1,
O => R1IN_3(19));
R1IN_3_ADD_1_CRY_2_Z6319: MUXCY_L port map (
DI => R1IN_3_2F_RETO(2),
CI => R1IN_3_ADD_1_CRY_1,
S => R1IN_3_ADD_1_AXB_2,
LO => R1IN_3_ADD_1_CRY_2);
R1IN_3_ADD_1_S_1: XORCY port map (
LI => R1IN_3_ADD_1_AXB_1,
CI => R1IN_3_ADD_1_CRY_0,
O => R1IN_3(18));
R1IN_3_ADD_1_CRY_1_Z6321: MUXCY_L port map (
DI => R1IN_3_2F_RETO(1),
CI => R1IN_3_ADD_1_CRY_0,
S => R1IN_3_ADD_1_AXB_1,
LO => R1IN_3_ADD_1_CRY_1);
R1IN_3_ADD_1_CRY_0_Z6322: MUXCY_L port map (
DI => R1IN_3_ADD_1_RETO_0,
CI => NN_1,
S => R1IN_3(17),
LO => R1IN_3_ADD_1_CRY_0);
R1IN_ADD_1_1_0_S_28: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_28,
CI => R1IN_ADD_1_1_0_CRY_27,
O => N_1592);
R1IN_ADD_1_1_0_CRY_28_Z6324: MUXCY port map (
DI => R1IN_3(60),
CI => R1IN_ADD_1_1_0_CRY_27,
S => R1IN_ADD_1_1_0_AXB_28,
O => R1IN_ADD_1_1_0_CRY_28);
R1IN_ADD_1_1_0_S_27: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_27,
CI => R1IN_ADD_1_1_0_CRY_26,
O => N_1591);
R1IN_ADD_1_1_0_CRY_27_Z6326: MUXCY_L port map (
DI => R1IN_3(59),
CI => R1IN_ADD_1_1_0_CRY_26,
S => R1IN_ADD_1_1_0_AXB_27,
LO => R1IN_ADD_1_1_0_CRY_27);
R1IN_ADD_1_1_0_S_26: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_26,
CI => R1IN_ADD_1_1_0_CRY_25,
O => N_1590);
R1IN_ADD_1_1_0_CRY_26_Z6328: MUXCY_L port map (
DI => R1IN_3(58),
CI => R1IN_ADD_1_1_0_CRY_25,
S => R1IN_ADD_1_1_0_AXB_26,
LO => R1IN_ADD_1_1_0_CRY_26);
R1IN_ADD_1_1_0_S_25: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_25,
CI => R1IN_ADD_1_1_0_CRY_24,
O => N_1589);
R1IN_ADD_1_1_0_CRY_25_Z6330: MUXCY_L port map (
DI => R1IN_3(57),
CI => R1IN_ADD_1_1_0_CRY_24,
S => R1IN_ADD_1_1_0_AXB_25,
LO => R1IN_ADD_1_1_0_CRY_25);
R1IN_ADD_1_1_0_S_24: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_24,
CI => R1IN_ADD_1_1_0_CRY_23,
O => N_1588);
R1IN_ADD_1_1_0_CRY_24_Z6332: MUXCY_L port map (
DI => R1IN_3(56),
CI => R1IN_ADD_1_1_0_CRY_23,
S => R1IN_ADD_1_1_0_AXB_24,
LO => R1IN_ADD_1_1_0_CRY_24);
R1IN_ADD_1_1_0_S_23: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_23,
CI => R1IN_ADD_1_1_0_CRY_22,
O => N_1587);
R1IN_ADD_1_1_0_CRY_23_Z6334: MUXCY_L port map (
DI => R1IN_3(55),
CI => R1IN_ADD_1_1_0_CRY_22,
S => R1IN_ADD_1_1_0_AXB_23,
LO => R1IN_ADD_1_1_0_CRY_23);
R1IN_ADD_1_1_0_S_22: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_22,
CI => R1IN_ADD_1_1_0_CRY_21,
O => N_1586);
R1IN_ADD_1_1_0_CRY_22_Z6336: MUXCY_L port map (
DI => R1IN_3(54),
CI => R1IN_ADD_1_1_0_CRY_21,
S => R1IN_ADD_1_1_0_AXB_22,
LO => R1IN_ADD_1_1_0_CRY_22);
R1IN_ADD_1_1_0_S_21: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_21,
CI => R1IN_ADD_1_1_0_CRY_20,
O => N_1585);
R1IN_ADD_1_1_0_CRY_21_Z6338: MUXCY_L port map (
DI => R1IN_3(53),
CI => R1IN_ADD_1_1_0_CRY_20,
S => R1IN_ADD_1_1_0_AXB_21,
LO => R1IN_ADD_1_1_0_CRY_21);
R1IN_ADD_1_1_0_S_20: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_20,
CI => R1IN_ADD_1_1_0_CRY_19,
O => N_1584);
R1IN_ADD_1_1_0_CRY_20_Z6340: MUXCY_L port map (
DI => R1IN_3(52),
CI => R1IN_ADD_1_1_0_CRY_19,
S => R1IN_ADD_1_1_0_AXB_20,
LO => R1IN_ADD_1_1_0_CRY_20);
R1IN_ADD_1_1_0_S_19: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_19,
CI => R1IN_ADD_1_1_0_CRY_18,
O => N_1583);
R1IN_ADD_1_1_0_CRY_19_Z6342: MUXCY_L port map (
DI => R1IN_3(51),
CI => R1IN_ADD_1_1_0_CRY_18,
S => R1IN_ADD_1_1_0_AXB_19,
LO => R1IN_ADD_1_1_0_CRY_19);
R1IN_ADD_1_1_0_S_18: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_18,
CI => R1IN_ADD_1_1_0_CRY_17,
O => N_1582);
R1IN_ADD_1_1_0_CRY_18_Z6344: MUXCY_L port map (
DI => R1IN_3(50),
CI => R1IN_ADD_1_1_0_CRY_17,
S => R1IN_ADD_1_1_0_AXB_18,
LO => R1IN_ADD_1_1_0_CRY_18);
R1IN_ADD_1_1_0_S_17: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_17,
CI => R1IN_ADD_1_1_0_CRY_16,
O => N_1581);
R1IN_ADD_1_1_0_CRY_17_Z6346: MUXCY_L port map (
DI => R1IN_3(49),
CI => R1IN_ADD_1_1_0_CRY_16,
S => R1IN_ADD_1_1_0_AXB_17,
LO => R1IN_ADD_1_1_0_CRY_17);
R1IN_ADD_1_1_0_S_16: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_16,
CI => R1IN_ADD_1_1_0_CRY_15,
O => N_1580);
R1IN_ADD_1_1_0_CRY_16_Z6348: MUXCY_L port map (
DI => R1IN_3(48),
CI => R1IN_ADD_1_1_0_CRY_15,
S => R1IN_ADD_1_1_0_AXB_16,
LO => R1IN_ADD_1_1_0_CRY_16);
R1IN_ADD_1_1_0_S_15: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_15,
CI => R1IN_ADD_1_1_0_CRY_14,
O => N_1579);
R1IN_ADD_1_1_0_CRY_15_Z6350: MUXCY_L port map (
DI => R1IN_3(47),
CI => R1IN_ADD_1_1_0_CRY_14,
S => R1IN_ADD_1_1_0_AXB_15,
LO => R1IN_ADD_1_1_0_CRY_15);
R1IN_ADD_1_1_0_S_14: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_14,
CI => R1IN_ADD_1_1_0_CRY_13,
O => N_1578);
R1IN_ADD_1_1_0_CRY_14_Z6352: MUXCY_L port map (
DI => R1IN_3(46),
CI => R1IN_ADD_1_1_0_CRY_13,
S => R1IN_ADD_1_1_0_AXB_14,
LO => R1IN_ADD_1_1_0_CRY_14);
R1IN_ADD_1_1_0_S_13: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_13,
CI => R1IN_ADD_1_1_0_CRY_12,
O => N_1577);
R1IN_ADD_1_1_0_CRY_13_Z6354: MUXCY_L port map (
DI => R1IN_3(45),
CI => R1IN_ADD_1_1_0_CRY_12,
S => R1IN_ADD_1_1_0_AXB_13,
LO => R1IN_ADD_1_1_0_CRY_13);
R1IN_ADD_1_1_0_S_12: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_12,
CI => R1IN_ADD_1_1_0_CRY_11,
O => N_1576);
R1IN_ADD_1_1_0_CRY_12_Z6356: MUXCY_L port map (
DI => R1IN_3(44),
CI => R1IN_ADD_1_1_0_CRY_11,
S => R1IN_ADD_1_1_0_AXB_12,
LO => R1IN_ADD_1_1_0_CRY_12);
R1IN_ADD_1_1_0_S_11: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_11,
CI => R1IN_ADD_1_1_0_CRY_10,
O => N_1575);
R1IN_ADD_1_1_0_CRY_11_Z6358: MUXCY_L port map (
DI => R1IN_3(43),
CI => R1IN_ADD_1_1_0_CRY_10,
S => R1IN_ADD_1_1_0_AXB_11,
LO => R1IN_ADD_1_1_0_CRY_11);
R1IN_ADD_1_1_0_S_10: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_10,
CI => R1IN_ADD_1_1_0_CRY_9,
O => N_1574);
R1IN_ADD_1_1_0_CRY_10_Z6360: MUXCY_L port map (
DI => R1IN_3(42),
CI => R1IN_ADD_1_1_0_CRY_9,
S => R1IN_ADD_1_1_0_AXB_10,
LO => R1IN_ADD_1_1_0_CRY_10);
R1IN_ADD_1_1_0_S_9: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_9,
CI => R1IN_ADD_1_1_0_CRY_8,
O => N_1573);
R1IN_ADD_1_1_0_CRY_9_Z6362: MUXCY_L port map (
DI => R1IN_3(41),
CI => R1IN_ADD_1_1_0_CRY_8,
S => R1IN_ADD_1_1_0_AXB_9,
LO => R1IN_ADD_1_1_0_CRY_9);
R1IN_ADD_1_1_0_S_8: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_8,
CI => R1IN_ADD_1_1_0_CRY_7,
O => N_1572);
R1IN_ADD_1_1_0_CRY_8_Z6364: MUXCY_L port map (
DI => R1IN_3(40),
CI => R1IN_ADD_1_1_0_CRY_7,
S => R1IN_ADD_1_1_0_AXB_8,
LO => R1IN_ADD_1_1_0_CRY_8);
R1IN_ADD_1_1_0_S_7: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_7,
CI => R1IN_ADD_1_1_0_CRY_6,
O => N_1571);
R1IN_ADD_1_1_0_CRY_7_Z6366: MUXCY_L port map (
DI => R1IN_3(39),
CI => R1IN_ADD_1_1_0_CRY_6,
S => R1IN_ADD_1_1_0_AXB_7,
LO => R1IN_ADD_1_1_0_CRY_7);
R1IN_ADD_1_1_0_S_6: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_6,
CI => R1IN_ADD_1_1_0_CRY_5,
O => N_1570);
R1IN_ADD_1_1_0_CRY_6_Z6368: MUXCY_L port map (
DI => R1IN_3(38),
CI => R1IN_ADD_1_1_0_CRY_5,
S => R1IN_ADD_1_1_0_AXB_6,
LO => R1IN_ADD_1_1_0_CRY_6);
R1IN_ADD_1_1_0_S_5: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_5,
CI => R1IN_ADD_1_1_0_CRY_4,
O => N_1569);
R1IN_ADD_1_1_0_CRY_5_Z6370: MUXCY_L port map (
DI => R1IN_3(37),
CI => R1IN_ADD_1_1_0_CRY_4,
S => R1IN_ADD_1_1_0_AXB_5,
LO => R1IN_ADD_1_1_0_CRY_5);
R1IN_ADD_1_1_0_S_4: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_4,
CI => R1IN_ADD_1_1_0_CRY_3,
O => N_1568);
R1IN_ADD_1_1_0_CRY_4_Z6372: MUXCY_L port map (
DI => R1IN_3(36),
CI => R1IN_ADD_1_1_0_CRY_3,
S => R1IN_ADD_1_1_0_AXB_4,
LO => R1IN_ADD_1_1_0_CRY_4);
R1IN_ADD_1_1_0_S_3: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_3,
CI => R1IN_ADD_1_1_0_CRY_2,
O => N_1567);
R1IN_ADD_1_1_0_CRY_3_Z6374: MUXCY_L port map (
DI => R1IN_3(35),
CI => R1IN_ADD_1_1_0_CRY_2,
S => R1IN_ADD_1_1_0_AXB_3,
LO => R1IN_ADD_1_1_0_CRY_3);
R1IN_ADD_1_1_0_S_2: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_2,
CI => R1IN_ADD_1_1_0_CRY_1,
O => N_1566);
R1IN_ADD_1_1_0_CRY_2_Z6376: MUXCY_L port map (
DI => R1IN_3(34),
CI => R1IN_ADD_1_1_0_CRY_1,
S => R1IN_ADD_1_1_0_AXB_2,
LO => R1IN_ADD_1_1_0_CRY_2);
R1IN_ADD_1_1_0_S_1: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_1,
CI => R1IN_ADD_1_1_0_CRY_0,
O => N_1565);
R1IN_ADD_1_1_0_CRY_1_Z6378: MUXCY_L port map (
DI => R1IN_3(33),
CI => R1IN_ADD_1_1_0_CRY_0,
S => R1IN_ADD_1_1_0_AXB_1,
LO => R1IN_ADD_1_1_0_CRY_1);
R1IN_ADD_1_1_0_CRY_0_Z6379: MUXCY_L port map (
DI => R1IN_3(32),
CI => NN_2,
S => R1IN_ADD_1_1_0_AXB_0,
LO => R1IN_ADD_1_1_0_CRY_0);
R1IN_ADD_1_1_S_28: XORCY port map (
LI => R1IN_ADD_1_1_AXB_28,
CI => R1IN_ADD_1_1_CRY_27,
O => N_1433);
R1IN_ADD_1_1_S_27: XORCY port map (
LI => R1IN_ADD_1_1_AXB_27,
CI => R1IN_ADD_1_1_CRY_26,
O => N_1431);
R1IN_ADD_1_1_CRY_27_Z6382: MUXCY_L port map (
DI => R1IN_3(59),
CI => R1IN_ADD_1_1_CRY_26,
S => R1IN_ADD_1_1_AXB_27,
LO => R1IN_ADD_1_1_CRY_27);
R1IN_ADD_1_1_S_26: XORCY port map (
LI => R1IN_ADD_1_1_AXB_26,
CI => R1IN_ADD_1_1_CRY_25,
O => N_1429);
R1IN_ADD_1_1_CRY_26_Z6384: MUXCY_L port map (
DI => R1IN_3(58),
CI => R1IN_ADD_1_1_CRY_25,
S => R1IN_ADD_1_1_AXB_26,
LO => R1IN_ADD_1_1_CRY_26);
R1IN_ADD_1_1_S_25: XORCY port map (
LI => R1IN_ADD_1_1_AXB_25,
CI => R1IN_ADD_1_1_CRY_24,
O => N_1427);
R1IN_ADD_1_1_CRY_25_Z6386: MUXCY_L port map (
DI => R1IN_3(57),
CI => R1IN_ADD_1_1_CRY_24,
S => R1IN_ADD_1_1_AXB_25,
LO => R1IN_ADD_1_1_CRY_25);
R1IN_ADD_1_1_S_24: XORCY port map (
LI => R1IN_ADD_1_1_AXB_24,
CI => R1IN_ADD_1_1_CRY_23,
O => N_1425);
R1IN_ADD_1_1_CRY_24_Z6388: MUXCY_L port map (
DI => R1IN_3(56),
CI => R1IN_ADD_1_1_CRY_23,
S => R1IN_ADD_1_1_AXB_24,
LO => R1IN_ADD_1_1_CRY_24);
R1IN_ADD_1_1_S_23: XORCY port map (
LI => R1IN_ADD_1_1_AXB_23,
CI => R1IN_ADD_1_1_CRY_22,
O => N_1423);
R1IN_ADD_1_1_CRY_23_Z6390: MUXCY_L port map (
DI => R1IN_3(55),
CI => R1IN_ADD_1_1_CRY_22,
S => R1IN_ADD_1_1_AXB_23,
LO => R1IN_ADD_1_1_CRY_23);
R1IN_ADD_1_1_S_22: XORCY port map (
LI => R1IN_ADD_1_1_AXB_22,
CI => R1IN_ADD_1_1_CRY_21,
O => N_1421);
R1IN_ADD_1_1_CRY_22_Z6392: MUXCY_L port map (
DI => R1IN_3(54),
CI => R1IN_ADD_1_1_CRY_21,
S => R1IN_ADD_1_1_AXB_22,
LO => R1IN_ADD_1_1_CRY_22);
R1IN_ADD_1_1_S_21: XORCY port map (
LI => R1IN_ADD_1_1_AXB_21,
CI => R1IN_ADD_1_1_CRY_20,
O => N_1419);
R1IN_ADD_1_1_CRY_21_Z6394: MUXCY_L port map (
DI => R1IN_3(53),
CI => R1IN_ADD_1_1_CRY_20,
S => R1IN_ADD_1_1_AXB_21,
LO => R1IN_ADD_1_1_CRY_21);
R1IN_ADD_1_1_S_20: XORCY port map (
LI => R1IN_ADD_1_1_AXB_20,
CI => R1IN_ADD_1_1_CRY_19,
O => N_1417);
R1IN_ADD_1_1_CRY_20_Z6396: MUXCY_L port map (
DI => R1IN_3(52),
CI => R1IN_ADD_1_1_CRY_19,
S => R1IN_ADD_1_1_AXB_20,
LO => R1IN_ADD_1_1_CRY_20);
R1IN_ADD_1_1_S_19: XORCY port map (
LI => R1IN_ADD_1_1_AXB_19,
CI => R1IN_ADD_1_1_CRY_18,
O => N_1415);
R1IN_ADD_1_1_CRY_19_Z6398: MUXCY_L port map (
DI => R1IN_3(51),
CI => R1IN_ADD_1_1_CRY_18,
S => R1IN_ADD_1_1_AXB_19,
LO => R1IN_ADD_1_1_CRY_19);
R1IN_ADD_1_1_S_18: XORCY port map (
LI => R1IN_ADD_1_1_AXB_18,
CI => R1IN_ADD_1_1_CRY_17,
O => N_1413);
R1IN_ADD_1_1_CRY_18_Z6400: MUXCY_L port map (
DI => R1IN_3(50),
CI => R1IN_ADD_1_1_CRY_17,
S => R1IN_ADD_1_1_AXB_18,
LO => R1IN_ADD_1_1_CRY_18);
R1IN_ADD_1_1_S_17: XORCY port map (
LI => R1IN_ADD_1_1_AXB_17,
CI => R1IN_ADD_1_1_CRY_16,
O => N_1411);
R1IN_ADD_1_1_CRY_17_Z6402: MUXCY_L port map (
DI => R1IN_3(49),
CI => R1IN_ADD_1_1_CRY_16,
S => R1IN_ADD_1_1_AXB_17,
LO => R1IN_ADD_1_1_CRY_17);
R1IN_ADD_1_1_S_16: XORCY port map (
LI => R1IN_ADD_1_1_AXB_16,
CI => R1IN_ADD_1_1_CRY_15,
O => N_1409);
R1IN_ADD_1_1_CRY_16_Z6404: MUXCY_L port map (
DI => R1IN_3(48),
CI => R1IN_ADD_1_1_CRY_15,
S => R1IN_ADD_1_1_AXB_16,
LO => R1IN_ADD_1_1_CRY_16);
R1IN_ADD_1_1_S_15: XORCY port map (
LI => R1IN_ADD_1_1_AXB_15,
CI => R1IN_ADD_1_1_CRY_14,
O => N_1407);
R1IN_ADD_1_1_CRY_15_Z6406: MUXCY_L port map (
DI => R1IN_3(47),
CI => R1IN_ADD_1_1_CRY_14,
S => R1IN_ADD_1_1_AXB_15,
LO => R1IN_ADD_1_1_CRY_15);
R1IN_ADD_1_1_S_14: XORCY port map (
LI => R1IN_ADD_1_1_AXB_14,
CI => R1IN_ADD_1_1_CRY_13,
O => N_1405);
R1IN_ADD_1_1_CRY_14_Z6408: MUXCY_L port map (
DI => R1IN_3(46),
CI => R1IN_ADD_1_1_CRY_13,
S => R1IN_ADD_1_1_AXB_14,
LO => R1IN_ADD_1_1_CRY_14);
R1IN_ADD_1_1_S_13: XORCY port map (
LI => R1IN_ADD_1_1_AXB_13,
CI => R1IN_ADD_1_1_CRY_12,
O => N_1403);
R1IN_ADD_1_1_CRY_13_Z6410: MUXCY_L port map (
DI => R1IN_3(45),
CI => R1IN_ADD_1_1_CRY_12,
S => R1IN_ADD_1_1_AXB_13,
LO => R1IN_ADD_1_1_CRY_13);
R1IN_ADD_1_1_S_12: XORCY port map (
LI => R1IN_ADD_1_1_AXB_12,
CI => R1IN_ADD_1_1_CRY_11,
O => N_1401);
R1IN_ADD_1_1_CRY_12_Z6412: MUXCY_L port map (
DI => R1IN_3(44),
CI => R1IN_ADD_1_1_CRY_11,
S => R1IN_ADD_1_1_AXB_12,
LO => R1IN_ADD_1_1_CRY_12);
R1IN_ADD_1_1_S_11: XORCY port map (
LI => R1IN_ADD_1_1_AXB_11,
CI => R1IN_ADD_1_1_CRY_10,
O => N_1399);
R1IN_ADD_1_1_CRY_11_Z6414: MUXCY_L port map (
DI => R1IN_3(43),
CI => R1IN_ADD_1_1_CRY_10,
S => R1IN_ADD_1_1_AXB_11,
LO => R1IN_ADD_1_1_CRY_11);
R1IN_ADD_1_1_S_10: XORCY port map (
LI => R1IN_ADD_1_1_AXB_10,
CI => R1IN_ADD_1_1_CRY_9,
O => N_1397);
R1IN_ADD_1_1_CRY_10_Z6416: MUXCY_L port map (
DI => R1IN_3(42),
CI => R1IN_ADD_1_1_CRY_9,
S => R1IN_ADD_1_1_AXB_10,
LO => R1IN_ADD_1_1_CRY_10);
R1IN_ADD_1_1_S_9: XORCY port map (
LI => R1IN_ADD_1_1_AXB_9,
CI => R1IN_ADD_1_1_CRY_8,
O => N_1395);
R1IN_ADD_1_1_CRY_9_Z6418: MUXCY_L port map (
DI => R1IN_3(41),
CI => R1IN_ADD_1_1_CRY_8,
S => R1IN_ADD_1_1_AXB_9,
LO => R1IN_ADD_1_1_CRY_9);
R1IN_ADD_1_1_S_8: XORCY port map (
LI => R1IN_ADD_1_1_AXB_8,
CI => R1IN_ADD_1_1_CRY_7,
O => N_1393);
R1IN_ADD_1_1_CRY_8_Z6420: MUXCY_L port map (
DI => R1IN_3(40),
CI => R1IN_ADD_1_1_CRY_7,
S => R1IN_ADD_1_1_AXB_8,
LO => R1IN_ADD_1_1_CRY_8);
R1IN_ADD_1_1_S_7: XORCY port map (
LI => R1IN_ADD_1_1_AXB_7,
CI => R1IN_ADD_1_1_CRY_6,
O => N_1391);
R1IN_ADD_1_1_CRY_7_Z6422: MUXCY_L port map (
DI => R1IN_3(39),
CI => R1IN_ADD_1_1_CRY_6,
S => R1IN_ADD_1_1_AXB_7,
LO => R1IN_ADD_1_1_CRY_7);
R1IN_ADD_1_1_S_6: XORCY port map (
LI => R1IN_ADD_1_1_AXB_6,
CI => R1IN_ADD_1_1_CRY_5,
O => N_1389);
R1IN_ADD_1_1_CRY_6_Z6424: MUXCY_L port map (
DI => R1IN_3(38),
CI => R1IN_ADD_1_1_CRY_5,
S => R1IN_ADD_1_1_AXB_6,
LO => R1IN_ADD_1_1_CRY_6);
R1IN_ADD_1_1_S_5: XORCY port map (
LI => R1IN_ADD_1_1_AXB_5,
CI => R1IN_ADD_1_1_CRY_4,
O => N_1387);
R1IN_ADD_1_1_CRY_5_Z6426: MUXCY_L port map (
DI => R1IN_3(37),
CI => R1IN_ADD_1_1_CRY_4,
S => R1IN_ADD_1_1_AXB_5,
LO => R1IN_ADD_1_1_CRY_5);
R1IN_ADD_1_1_S_4: XORCY port map (
LI => R1IN_ADD_1_1_AXB_4,
CI => R1IN_ADD_1_1_CRY_3,
O => N_1385);
R1IN_ADD_1_1_CRY_4_Z6428: MUXCY_L port map (
DI => R1IN_3(36),
CI => R1IN_ADD_1_1_CRY_3,
S => R1IN_ADD_1_1_AXB_4,
LO => R1IN_ADD_1_1_CRY_4);
R1IN_ADD_1_1_S_3: XORCY port map (
LI => R1IN_ADD_1_1_AXB_3,
CI => R1IN_ADD_1_1_CRY_2,
O => N_1383);
R1IN_ADD_1_1_CRY_3_Z6430: MUXCY_L port map (
DI => R1IN_3(35),
CI => R1IN_ADD_1_1_CRY_2,
S => R1IN_ADD_1_1_AXB_3,
LO => R1IN_ADD_1_1_CRY_3);
R1IN_ADD_1_1_S_2: XORCY port map (
LI => R1IN_ADD_1_1_AXB_2,
CI => R1IN_ADD_1_1_CRY_1,
O => N_1381);
R1IN_ADD_1_1_CRY_2_Z6432: MUXCY_L port map (
DI => R1IN_3(34),
CI => R1IN_ADD_1_1_CRY_1,
S => R1IN_ADD_1_1_AXB_2,
LO => R1IN_ADD_1_1_CRY_2);
R1IN_ADD_1_1_S_1: XORCY port map (
LI => R1IN_ADD_1_1_AXB_1,
CI => R1IN_ADD_1_1_CRY_0,
O => N_1379);
R1IN_ADD_1_1_CRY_1_Z6434: MUXCY_L port map (
DI => R1IN_3(33),
CI => R1IN_ADD_1_1_CRY_0,
S => R1IN_ADD_1_1_AXB_1,
LO => R1IN_ADD_1_1_CRY_1);
R1IN_ADD_1_1_CRY_0_Z6435: MUXCY_L port map (
DI => R1IN_3(32),
CI => NN_1,
S => R1IN_ADD_1_1_AXB_0,
LO => R1IN_ADD_1_1_CRY_0);
R1IN_ADD_1_0_S_31: XORCY port map (
LI => R1IN_ADD_1_0_AXB_31,
CI => R1IN_ADD_1_0_CRY_30,
O => R1IN_ADD_1(31));
R1IN_ADD_1_0_CRY_31_Z6437: MUXCY port map (
DI => R1IN_3(31),
CI => R1IN_ADD_1_0_CRY_30,
S => R1IN_ADD_1_0_AXB_31,
O => R1IN_ADD_1_0_CRY_31);
R1IN_ADD_1_0_S_30: XORCY port map (
LI => R1IN_ADD_1_0_AXB_30,
CI => R1IN_ADD_1_0_CRY_29,
O => R1IN_ADD_1(30));
R1IN_ADD_1_0_CRY_30_Z6439: MUXCY_L port map (
DI => R1IN_3(30),
CI => R1IN_ADD_1_0_CRY_29,
S => R1IN_ADD_1_0_AXB_30,
LO => R1IN_ADD_1_0_CRY_30);
R1IN_ADD_1_0_S_29: XORCY port map (
LI => R1IN_ADD_1_0_AXB_29,
CI => R1IN_ADD_1_0_CRY_28,
O => R1IN_ADD_1(29));
R1IN_ADD_1_0_CRY_29_Z6441: MUXCY_L port map (
DI => R1IN_3(29),
CI => R1IN_ADD_1_0_CRY_28,
S => R1IN_ADD_1_0_AXB_29,
LO => R1IN_ADD_1_0_CRY_29);
R1IN_ADD_1_0_S_28: XORCY port map (
LI => R1IN_ADD_1_0_AXB_28,
CI => R1IN_ADD_1_0_CRY_27,
O => R1IN_ADD_1(28));
R1IN_ADD_1_0_CRY_28_Z6443: MUXCY_L port map (
DI => R1IN_3(28),
CI => R1IN_ADD_1_0_CRY_27,
S => R1IN_ADD_1_0_AXB_28,
LO => R1IN_ADD_1_0_CRY_28);
R1IN_ADD_1_0_S_27: XORCY port map (
LI => R1IN_ADD_1_0_AXB_27,
CI => R1IN_ADD_1_0_CRY_26,
O => R1IN_ADD_1(27));
R1IN_ADD_1_0_CRY_27_Z6445: MUXCY_L port map (
DI => R1IN_3(27),
CI => R1IN_ADD_1_0_CRY_26,
S => R1IN_ADD_1_0_AXB_27,
LO => R1IN_ADD_1_0_CRY_27);
R1IN_ADD_1_0_S_26: XORCY port map (
LI => R1IN_ADD_1_0_AXB_26,
CI => R1IN_ADD_1_0_CRY_25,
O => R1IN_ADD_1(26));
R1IN_ADD_1_0_CRY_26_Z6447: MUXCY_L port map (
DI => R1IN_3(26),
CI => R1IN_ADD_1_0_CRY_25,
S => R1IN_ADD_1_0_AXB_26,
LO => R1IN_ADD_1_0_CRY_26);
R1IN_ADD_1_0_S_25: XORCY port map (
LI => R1IN_ADD_1_0_AXB_25,
CI => R1IN_ADD_1_0_CRY_24,
O => R1IN_ADD_1(25));
R1IN_ADD_1_0_CRY_25_Z6449: MUXCY_L port map (
DI => R1IN_3(25),
CI => R1IN_ADD_1_0_CRY_24,
S => R1IN_ADD_1_0_AXB_25,
LO => R1IN_ADD_1_0_CRY_25);
R1IN_ADD_1_0_S_24: XORCY port map (
LI => R1IN_ADD_1_0_AXB_24,
CI => R1IN_ADD_1_0_CRY_23,
O => R1IN_ADD_1(24));
R1IN_ADD_1_0_CRY_24_Z6451: MUXCY_L port map (
DI => R1IN_3(24),
CI => R1IN_ADD_1_0_CRY_23,
S => R1IN_ADD_1_0_AXB_24,
LO => R1IN_ADD_1_0_CRY_24);
R1IN_ADD_1_0_S_23: XORCY port map (
LI => R1IN_ADD_1_0_AXB_23,
CI => R1IN_ADD_1_0_CRY_22,
O => R1IN_ADD_1(23));
R1IN_ADD_1_0_CRY_23_Z6453: MUXCY_L port map (
DI => R1IN_3(23),
CI => R1IN_ADD_1_0_CRY_22,
S => R1IN_ADD_1_0_AXB_23,
LO => R1IN_ADD_1_0_CRY_23);
R1IN_ADD_1_0_S_22: XORCY port map (
LI => R1IN_ADD_1_0_AXB_22,
CI => R1IN_ADD_1_0_CRY_21,
O => R1IN_ADD_1(22));
R1IN_ADD_1_0_CRY_22_Z6455: MUXCY_L port map (
DI => R1IN_3(22),
CI => R1IN_ADD_1_0_CRY_21,
S => R1IN_ADD_1_0_AXB_22,
LO => R1IN_ADD_1_0_CRY_22);
R1IN_ADD_1_0_S_21: XORCY port map (
LI => R1IN_ADD_1_0_AXB_21,
CI => R1IN_ADD_1_0_CRY_20,
O => R1IN_ADD_1(21));
R1IN_ADD_1_0_CRY_21_Z6457: MUXCY_L port map (
DI => R1IN_3(21),
CI => R1IN_ADD_1_0_CRY_20,
S => R1IN_ADD_1_0_AXB_21,
LO => R1IN_ADD_1_0_CRY_21);
R1IN_ADD_1_0_S_20: XORCY port map (
LI => R1IN_ADD_1_0_AXB_20,
CI => R1IN_ADD_1_0_CRY_19,
O => R1IN_ADD_1(20));
R1IN_ADD_1_0_CRY_20_Z6459: MUXCY_L port map (
DI => R1IN_3(20),
CI => R1IN_ADD_1_0_CRY_19,
S => R1IN_ADD_1_0_AXB_20,
LO => R1IN_ADD_1_0_CRY_20);
R1IN_ADD_1_0_S_19: XORCY port map (
LI => R1IN_ADD_1_0_AXB_19,
CI => R1IN_ADD_1_0_CRY_18,
O => R1IN_ADD_1(19));
R1IN_ADD_1_0_CRY_19_Z6461: MUXCY_L port map (
DI => R1IN_3(19),
CI => R1IN_ADD_1_0_CRY_18,
S => R1IN_ADD_1_0_AXB_19,
LO => R1IN_ADD_1_0_CRY_19);
R1IN_ADD_1_0_S_18: XORCY port map (
LI => R1IN_ADD_1_0_AXB_18,
CI => R1IN_ADD_1_0_CRY_17,
O => R1IN_ADD_1(18));
R1IN_ADD_1_0_CRY_18_Z6463: MUXCY_L port map (
DI => R1IN_3(18),
CI => R1IN_ADD_1_0_CRY_17,
S => R1IN_ADD_1_0_AXB_18,
LO => R1IN_ADD_1_0_CRY_18);
R1IN_ADD_1_0_S_17: XORCY port map (
LI => R1IN_ADD_1_0_AXB_17,
CI => R1IN_ADD_1_0_CRY_16,
O => R1IN_ADD_1(17));
R1IN_ADD_1_0_CRY_17_Z6465: MUXCY_L port map (
DI => R1IN_3(17),
CI => R1IN_ADD_1_0_CRY_16,
S => R1IN_ADD_1_0_AXB_17,
LO => R1IN_ADD_1_0_CRY_17);
R1IN_ADD_1_0_S_16: XORCY port map (
LI => R1IN_ADD_1_0_AXB_16,
CI => R1IN_ADD_1_0_CRY_15,
O => R1IN_ADD_1(16));
R1IN_ADD_1_0_CRY_16_Z6467: MUXCY_L port map (
DI => R1IN_2F_RETO(16),
CI => R1IN_ADD_1_0_CRY_15,
S => R1IN_ADD_1_0_AXB_16,
LO => R1IN_ADD_1_0_CRY_16);
R1IN_ADD_1_0_S_15: XORCY port map (
LI => R1IN_ADD_1_0_AXB_15,
CI => R1IN_ADD_1_0_CRY_14,
O => R1IN_ADD_1(15));
R1IN_ADD_1_0_CRY_15_Z6469: MUXCY_L port map (
DI => R1IN_2F_RETO(15),
CI => R1IN_ADD_1_0_CRY_14,
S => R1IN_ADD_1_0_AXB_15,
LO => R1IN_ADD_1_0_CRY_15);
R1IN_ADD_1_0_S_14: XORCY port map (
LI => R1IN_ADD_1_0_AXB_14,
CI => R1IN_ADD_1_0_CRY_13,
O => R1IN_ADD_1(14));
R1IN_ADD_1_0_CRY_14_Z6471: MUXCY_L port map (
DI => R1IN_2F_RETO(14),
CI => R1IN_ADD_1_0_CRY_13,
S => R1IN_ADD_1_0_AXB_14,
LO => R1IN_ADD_1_0_CRY_14);
R1IN_ADD_1_0_S_13: XORCY port map (
LI => R1IN_ADD_1_0_AXB_13,
CI => R1IN_ADD_1_0_CRY_12,
O => R1IN_ADD_1(13));
R1IN_ADD_1_0_CRY_13_Z6473: MUXCY_L port map (
DI => R1IN_2F_RETO(13),
CI => R1IN_ADD_1_0_CRY_12,
S => R1IN_ADD_1_0_AXB_13,
LO => R1IN_ADD_1_0_CRY_13);
R1IN_ADD_1_0_S_12: XORCY port map (
LI => R1IN_ADD_1_0_AXB_12,
CI => R1IN_ADD_1_0_CRY_11,
O => R1IN_ADD_1(12));
R1IN_ADD_1_0_CRY_12_Z6475: MUXCY_L port map (
DI => R1IN_2F_RETO(12),
CI => R1IN_ADD_1_0_CRY_11,
S => R1IN_ADD_1_0_AXB_12,
LO => R1IN_ADD_1_0_CRY_12);
R1IN_ADD_1_0_S_11: XORCY port map (
LI => R1IN_ADD_1_0_AXB_11,
CI => R1IN_ADD_1_0_CRY_10,
O => R1IN_ADD_1(11));
R1IN_ADD_1_0_CRY_11_Z6477: MUXCY_L port map (
DI => R1IN_2F_RETO(11),
CI => R1IN_ADD_1_0_CRY_10,
S => R1IN_ADD_1_0_AXB_11,
LO => R1IN_ADD_1_0_CRY_11);
R1IN_ADD_1_0_S_10: XORCY port map (
LI => R1IN_ADD_1_0_AXB_10,
CI => R1IN_ADD_1_0_CRY_9,
O => R1IN_ADD_1(10));
R1IN_ADD_1_0_CRY_10_Z6479: MUXCY_L port map (
DI => R1IN_2F_RETO(10),
CI => R1IN_ADD_1_0_CRY_9,
S => R1IN_ADD_1_0_AXB_10,
LO => R1IN_ADD_1_0_CRY_10);
R1IN_ADD_1_0_S_9: XORCY port map (
LI => R1IN_ADD_1_0_AXB_9,
CI => R1IN_ADD_1_0_CRY_8,
O => R1IN_ADD_1(9));
R1IN_ADD_1_0_CRY_9_Z6481: MUXCY_L port map (
DI => R1IN_2F_RETO(9),
CI => R1IN_ADD_1_0_CRY_8,
S => R1IN_ADD_1_0_AXB_9,
LO => R1IN_ADD_1_0_CRY_9);
R1IN_ADD_1_0_S_8: XORCY port map (
LI => R1IN_ADD_1_0_AXB_8,
CI => R1IN_ADD_1_0_CRY_7,
O => R1IN_ADD_1(8));
R1IN_ADD_1_0_CRY_8_Z6483: MUXCY_L port map (
DI => R1IN_2F_RETO(8),
CI => R1IN_ADD_1_0_CRY_7,
S => R1IN_ADD_1_0_AXB_8,
LO => R1IN_ADD_1_0_CRY_8);
R1IN_ADD_1_0_S_7: XORCY port map (
LI => R1IN_ADD_1_0_AXB_7,
CI => R1IN_ADD_1_0_CRY_6,
O => R1IN_ADD_1(7));
R1IN_ADD_1_0_CRY_7_Z6485: MUXCY_L port map (
DI => R1IN_2F_RETO(7),
CI => R1IN_ADD_1_0_CRY_6,
S => R1IN_ADD_1_0_AXB_7,
LO => R1IN_ADD_1_0_CRY_7);
R1IN_ADD_1_0_S_6: XORCY port map (
LI => R1IN_ADD_1_0_AXB_6,
CI => R1IN_ADD_1_0_CRY_5,
O => R1IN_ADD_1(6));
R1IN_ADD_1_0_CRY_6_Z6487: MUXCY_L port map (
DI => R1IN_2F_RETO(6),
CI => R1IN_ADD_1_0_CRY_5,
S => R1IN_ADD_1_0_AXB_6,
LO => R1IN_ADD_1_0_CRY_6);
R1IN_ADD_1_0_S_5: XORCY port map (
LI => R1IN_ADD_1_0_AXB_5,
CI => R1IN_ADD_1_0_CRY_4,
O => R1IN_ADD_1(5));
R1IN_ADD_1_0_CRY_5_Z6489: MUXCY_L port map (
DI => R1IN_2F_RETO(5),
CI => R1IN_ADD_1_0_CRY_4,
S => R1IN_ADD_1_0_AXB_5,
LO => R1IN_ADD_1_0_CRY_5);
R1IN_ADD_1_0_S_4: XORCY port map (
LI => R1IN_ADD_1_0_AXB_4,
CI => R1IN_ADD_1_0_CRY_3,
O => R1IN_ADD_1(4));
R1IN_ADD_1_0_CRY_4_Z6491: MUXCY_L port map (
DI => R1IN_2F_RETO(4),
CI => R1IN_ADD_1_0_CRY_3,
S => R1IN_ADD_1_0_AXB_4,
LO => R1IN_ADD_1_0_CRY_4);
R1IN_ADD_1_0_S_3: XORCY port map (
LI => R1IN_ADD_1_0_AXB_3,
CI => R1IN_ADD_1_0_CRY_2,
O => R1IN_ADD_1(3));
R1IN_ADD_1_0_CRY_3_Z6493: MUXCY_L port map (
DI => R1IN_2F_RETO(3),
CI => R1IN_ADD_1_0_CRY_2,
S => R1IN_ADD_1_0_AXB_3,
LO => R1IN_ADD_1_0_CRY_3);
R1IN_ADD_1_0_S_2: XORCY port map (
LI => R1IN_ADD_1_0_AXB_2,
CI => R1IN_ADD_1_0_CRY_1,
O => R1IN_ADD_1(2));
R1IN_ADD_1_0_CRY_2_Z6495: MUXCY_L port map (
DI => R1IN_2F_RETO(2),
CI => R1IN_ADD_1_0_CRY_1,
S => R1IN_ADD_1_0_AXB_2,
LO => R1IN_ADD_1_0_CRY_2);
R1IN_ADD_1_0_S_1: XORCY port map (
LI => R1IN_ADD_1_0_AXB_1,
CI => R1IN_ADD_1_0_CRY_0,
O => R1IN_ADD_1(1));
R1IN_ADD_1_0_CRY_1_Z6497: MUXCY_L port map (
DI => R1IN_2F_RETO(1),
CI => R1IN_ADD_1_0_CRY_0,
S => R1IN_ADD_1_0_AXB_1,
LO => R1IN_ADD_1_0_CRY_1);
R1IN_ADD_1_0_CRY_0_Z6498: MUXCY_L port map (
DI => R1IN_2F_RETO(0),
CI => NN_1,
S => R1IN_ADD_1(0),
LO => R1IN_ADD_1_0_CRY_0);
R1IN_4_ADD_2_1_0_S_34: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_34,
CI => R1IN_4_ADD_2_1_0_CRY_33,
O => N_1556);
R1IN_4_ADD_2_1_0_S_33: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_33,
CI => R1IN_4_ADD_2_1_0_CRY_32,
O => N_1555);
R1IN_4_ADD_2_1_0_CRY_33_Z6501: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_32,
S => R1IN_4_ADD_2_1_0_AXB_33,
LO => R1IN_4_ADD_2_1_0_CRY_33);
R1IN_4_ADD_2_1_0_S_32: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_32,
CI => R1IN_4_ADD_2_1_0_CRY_31,
O => N_1554);
R1IN_4_ADD_2_1_0_CRY_32_Z6503: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_31,
S => R1IN_4_ADD_2_1_0_AXB_32,
LO => R1IN_4_ADD_2_1_0_CRY_32);
R1IN_4_ADD_2_1_0_S_31: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_31,
CI => R1IN_4_ADD_2_1_0_CRY_30,
O => N_1553);
R1IN_4_ADD_2_1_0_CRY_31_Z6505: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_30,
S => R1IN_4_ADD_2_1_0_AXB_31,
LO => R1IN_4_ADD_2_1_0_CRY_31);
R1IN_4_ADD_2_1_0_S_30: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_30,
CI => R1IN_4_ADD_2_1_0_CRY_29,
O => N_1552);
R1IN_4_ADD_2_1_0_CRY_30_Z6507: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_29,
S => R1IN_4_ADD_2_1_0_AXB_30,
LO => R1IN_4_ADD_2_1_0_CRY_30);
R1IN_4_ADD_2_1_0_S_29: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_29,
CI => R1IN_4_ADD_2_1_0_CRY_28,
O => N_1551);
R1IN_4_ADD_2_1_0_CRY_29_Z6509: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_28,
S => R1IN_4_ADD_2_1_0_AXB_29,
LO => R1IN_4_ADD_2_1_0_CRY_29);
R1IN_4_ADD_2_1_0_S_28: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_28,
CI => R1IN_4_ADD_2_1_0_CRY_27,
O => N_1550);
R1IN_4_ADD_2_1_0_CRY_28_Z6511: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_27,
S => R1IN_4_ADD_2_1_0_AXB_28,
LO => R1IN_4_ADD_2_1_0_CRY_28);
R1IN_4_ADD_2_1_0_S_27: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_27,
CI => R1IN_4_ADD_2_1_0_CRY_26,
O => N_1549);
R1IN_4_ADD_2_1_0_CRY_27_Z6513: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_26,
S => R1IN_4_ADD_2_1_0_AXB_27,
LO => R1IN_4_ADD_2_1_0_CRY_27);
R1IN_4_ADD_2_1_0_S_26: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_26,
CI => R1IN_4_ADD_2_1_0_CRY_25,
O => N_1548);
R1IN_4_ADD_2_1_0_CRY_26_Z6515: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_25,
S => R1IN_4_ADD_2_1_0_AXB_26,
LO => R1IN_4_ADD_2_1_0_CRY_26);
R1IN_4_ADD_2_1_0_S_25: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_25,
CI => R1IN_4_ADD_2_1_0_CRY_24,
O => N_1547);
R1IN_4_ADD_2_1_0_CRY_25_Z6517: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_24,
S => R1IN_4_ADD_2_1_0_AXB_25,
LO => R1IN_4_ADD_2_1_0_CRY_25);
R1IN_4_ADD_2_1_0_S_24: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_24,
CI => R1IN_4_ADD_2_1_0_CRY_23,
O => N_1546);
R1IN_4_ADD_2_1_0_CRY_24_Z6519: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_23,
S => R1IN_4_ADD_2_1_0_AXB_24,
LO => R1IN_4_ADD_2_1_0_CRY_24);
R1IN_4_ADD_2_1_0_S_23: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_23,
CI => R1IN_4_ADD_2_1_0_CRY_22,
O => N_1545);
R1IN_4_ADD_2_1_0_CRY_23_Z6521: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_22,
S => R1IN_4_ADD_2_1_0_AXB_23,
LO => R1IN_4_ADD_2_1_0_CRY_23);
R1IN_4_ADD_2_1_0_S_22: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_22,
CI => R1IN_4_ADD_2_1_0_CRY_21,
O => N_1544);
R1IN_4_ADD_2_1_0_CRY_22_Z6523: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_21,
S => R1IN_4_ADD_2_1_0_AXB_22,
LO => R1IN_4_ADD_2_1_0_CRY_22);
R1IN_4_ADD_2_1_0_S_21: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_21,
CI => R1IN_4_ADD_2_1_0_CRY_20,
O => N_1543);
R1IN_4_ADD_2_1_0_CRY_21_Z6525: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_20,
S => R1IN_4_ADD_2_1_0_AXB_21,
LO => R1IN_4_ADD_2_1_0_CRY_21);
R1IN_4_ADD_2_1_0_S_20: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_20,
CI => R1IN_4_ADD_2_1_0_CRY_19,
O => N_1542);
R1IN_4_ADD_2_1_0_CRY_20_Z6527: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_19,
S => R1IN_4_ADD_2_1_0_AXB_20,
LO => R1IN_4_ADD_2_1_0_CRY_20);
R1IN_4_ADD_2_1_0_S_19: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_19,
CI => R1IN_4_ADD_2_1_0_CRY_18,
O => N_1541);
R1IN_4_ADD_2_1_0_CRY_19_Z6529: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_18,
S => R1IN_4_ADD_2_1_0_AXB_19,
LO => R1IN_4_ADD_2_1_0_CRY_19);
R1IN_4_ADD_2_1_0_S_18: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_18,
CI => R1IN_4_ADD_2_1_0_CRY_17,
O => N_1540);
R1IN_4_ADD_2_1_0_CRY_18_Z6531: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_17,
S => R1IN_4_ADD_2_1_0_AXB_18,
LO => R1IN_4_ADD_2_1_0_CRY_18);
R1IN_4_ADD_2_1_0_S_17: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_17,
CI => R1IN_4_ADD_2_1_0_CRY_16,
O => N_1539);
R1IN_4_ADD_2_1_0_CRY_17_Z6533: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_16,
S => R1IN_4_ADD_2_1_0_AXB_17,
LO => R1IN_4_ADD_2_1_0_CRY_17);
R1IN_4_ADD_2_1_0_S_16: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_16,
CI => R1IN_4_ADD_2_1_0_CRY_15,
O => N_1538);
R1IN_4_ADD_2_1_0_CRY_16_Z6535: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_15,
S => R1IN_4_ADD_2_1_0_AXB_16,
LO => R1IN_4_ADD_2_1_0_CRY_16);
R1IN_4_ADD_2_1_0_S_15: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_15,
CI => R1IN_4_ADD_2_1_0_CRY_14,
O => N_1537);
R1IN_4_ADD_2_1_0_CRY_15_Z6537: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_14,
S => R1IN_4_ADD_2_1_0_AXB_15,
LO => R1IN_4_ADD_2_1_0_CRY_15);
R1IN_4_ADD_2_1_0_S_14: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_14,
CI => R1IN_4_ADD_2_1_0_CRY_13,
O => N_1536);
R1IN_4_ADD_2_1_0_CRY_14_Z6539: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_13,
S => R1IN_4_ADD_2_1_0_AXB_14,
LO => R1IN_4_ADD_2_1_0_CRY_14);
R1IN_4_ADD_2_1_0_S_13: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_13,
CI => R1IN_4_ADD_2_1_0_CRY_12,
O => N_1535);
R1IN_4_ADD_2_1_0_CRY_13_Z6541: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_12,
S => R1IN_4_ADD_2_1_0_AXB_13,
LO => R1IN_4_ADD_2_1_0_CRY_13);
R1IN_4_ADD_2_1_0_S_12: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_12,
CI => R1IN_4_ADD_2_1_0_CRY_11,
O => N_1534);
R1IN_4_ADD_2_1_0_CRY_12_Z6543: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_11,
S => R1IN_4_ADD_2_1_0_AXB_12,
LO => R1IN_4_ADD_2_1_0_CRY_12);
R1IN_4_ADD_2_1_0_S_11: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_11,
CI => R1IN_4_ADD_2_1_0_CRY_10,
O => N_1533);
R1IN_4_ADD_2_1_0_CRY_11_Z6545: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_10,
S => R1IN_4_ADD_2_1_0_AXB_11,
LO => R1IN_4_ADD_2_1_0_CRY_11);
R1IN_4_ADD_2_1_0_S_10: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_10,
CI => R1IN_4_ADD_2_1_0_CRY_9,
O => N_1532);
R1IN_4_ADD_2_1_0_CRY_10_Z6547: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_9,
S => R1IN_4_ADD_2_1_0_AXB_10,
LO => R1IN_4_ADD_2_1_0_CRY_10);
R1IN_4_ADD_2_1_0_S_9: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_9,
CI => R1IN_4_ADD_2_1_0_CRY_8,
O => N_1531);
R1IN_4_ADD_2_1_0_CRY_9_Z6549: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_8,
S => R1IN_4_ADD_2_1_0_AXB_9,
LO => R1IN_4_ADD_2_1_0_CRY_9);
R1IN_4_ADD_2_1_0_S_8: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_8,
CI => R1IN_4_ADD_2_1_0_CRY_7,
O => N_1530);
R1IN_4_ADD_2_1_0_CRY_8_Z6551: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(44),
CI => R1IN_4_ADD_2_1_0_CRY_7,
S => R1IN_4_ADD_2_1_0_AXB_8,
LO => R1IN_4_ADD_2_1_0_CRY_8);
R1IN_4_ADD_2_1_0_S_7: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_7,
CI => R1IN_4_ADD_2_1_0_CRY_6,
O => N_1529);
R1IN_4_ADD_2_1_0_CRY_7_Z6553: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(43),
CI => R1IN_4_ADD_2_1_0_CRY_6,
S => R1IN_4_ADD_2_1_0_AXB_7,
LO => R1IN_4_ADD_2_1_0_CRY_7);
R1IN_4_ADD_2_1_0_S_6: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_6,
CI => R1IN_4_ADD_2_1_0_CRY_5,
O => N_1528);
R1IN_4_ADD_2_1_0_CRY_6_Z6555: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(42),
CI => R1IN_4_ADD_2_1_0_CRY_5,
S => R1IN_4_ADD_2_1_0_AXB_6,
LO => R1IN_4_ADD_2_1_0_CRY_6);
R1IN_4_ADD_2_1_0_S_5: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_5,
CI => R1IN_4_ADD_2_1_0_CRY_4,
O => N_1527);
R1IN_4_ADD_2_1_0_CRY_5_Z6557: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(41),
CI => R1IN_4_ADD_2_1_0_CRY_4,
S => R1IN_4_ADD_2_1_0_AXB_5,
LO => R1IN_4_ADD_2_1_0_CRY_5);
R1IN_4_ADD_2_1_0_S_4: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_4,
CI => R1IN_4_ADD_2_1_0_CRY_3,
O => N_1526);
R1IN_4_ADD_2_1_0_CRY_4_Z6559: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(40),
CI => R1IN_4_ADD_2_1_0_CRY_3,
S => R1IN_4_ADD_2_1_0_AXB_4,
LO => R1IN_4_ADD_2_1_0_CRY_4);
R1IN_4_ADD_2_1_0_S_3: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_3,
CI => R1IN_4_ADD_2_1_0_CRY_2,
O => N_1525);
R1IN_4_ADD_2_1_0_CRY_3_Z6561: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(39),
CI => R1IN_4_ADD_2_1_0_CRY_2,
S => R1IN_4_ADD_2_1_0_AXB_3,
LO => R1IN_4_ADD_2_1_0_CRY_3);
R1IN_4_ADD_2_1_0_S_2: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_2,
CI => R1IN_4_ADD_2_1_0_CRY_1,
O => N_1524);
R1IN_4_ADD_2_1_0_CRY_2_Z6563: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(38),
CI => R1IN_4_ADD_2_1_0_CRY_1,
S => R1IN_4_ADD_2_1_0_AXB_2,
LO => R1IN_4_ADD_2_1_0_CRY_2);
R1IN_4_ADD_2_1_0_S_1: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_1,
CI => R1IN_4_ADD_2_1_0_CRY_0,
O => N_1523);
R1IN_4_ADD_2_1_0_CRY_1_Z6565: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(37),
CI => R1IN_4_ADD_2_1_0_CRY_0,
S => R1IN_4_ADD_2_1_0_AXB_1,
LO => R1IN_4_ADD_2_1_0_CRY_1);
R1IN_4_ADD_2_1_0_CRY_0_Z6566: MUXCY_L port map (
DI => R1IN_4_ADD_2_1_RETO,
CI => NN_2,
S => R1IN_4_ADD_2_1_0_AXB_0,
LO => R1IN_4_ADD_2_1_0_CRY_0);
R1IN_4_ADD_2_1_S_34: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_34,
CI => R1IN_4_ADD_2_1_CRY_33,
O => N_1511);
R1IN_4_ADD_2_1_S_33: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_33,
CI => R1IN_4_ADD_2_1_CRY_32,
O => N_1509);
R1IN_4_ADD_2_1_CRY_33_Z6569: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_32,
S => R1IN_4_ADD_2_1_AXB_33,
LO => R1IN_4_ADD_2_1_CRY_33);
R1IN_4_ADD_2_1_S_32: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_32,
CI => R1IN_4_ADD_2_1_CRY_31,
O => N_1507);
R1IN_4_ADD_2_1_CRY_32_Z6571: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_31,
S => R1IN_4_ADD_2_1_AXB_32,
LO => R1IN_4_ADD_2_1_CRY_32);
R1IN_4_ADD_2_1_S_31: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_31,
CI => R1IN_4_ADD_2_1_CRY_30,
O => N_1505);
R1IN_4_ADD_2_1_CRY_31_Z6573: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_30,
S => R1IN_4_ADD_2_1_AXB_31,
LO => R1IN_4_ADD_2_1_CRY_31);
R1IN_4_ADD_2_1_S_30: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_30,
CI => R1IN_4_ADD_2_1_CRY_29,
O => N_1503);
R1IN_4_ADD_2_1_CRY_30_Z6575: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_29,
S => R1IN_4_ADD_2_1_AXB_30,
LO => R1IN_4_ADD_2_1_CRY_30);
R1IN_4_ADD_2_1_S_29: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_29,
CI => R1IN_4_ADD_2_1_CRY_28,
O => N_1501);
R1IN_4_ADD_2_1_CRY_29_Z6577: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_28,
S => R1IN_4_ADD_2_1_AXB_29,
LO => R1IN_4_ADD_2_1_CRY_29);
R1IN_4_ADD_2_1_S_28: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_28,
CI => R1IN_4_ADD_2_1_CRY_27,
O => N_1499);
R1IN_4_ADD_2_1_CRY_28_Z6579: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_27,
S => R1IN_4_ADD_2_1_AXB_28,
LO => R1IN_4_ADD_2_1_CRY_28);
R1IN_4_ADD_2_1_S_27: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_27,
CI => R1IN_4_ADD_2_1_CRY_26,
O => N_1497);
R1IN_4_ADD_2_1_CRY_27_Z6581: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_26,
S => R1IN_4_ADD_2_1_AXB_27,
LO => R1IN_4_ADD_2_1_CRY_27);
R1IN_4_ADD_2_1_S_26: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_26,
CI => R1IN_4_ADD_2_1_CRY_25,
O => N_1495);
R1IN_4_ADD_2_1_CRY_26_Z6583: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_25,
S => R1IN_4_ADD_2_1_AXB_26,
LO => R1IN_4_ADD_2_1_CRY_26);
R1IN_4_ADD_2_1_S_25: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_25,
CI => R1IN_4_ADD_2_1_CRY_24,
O => N_1493);
R1IN_4_ADD_2_1_CRY_25_Z6585: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_24,
S => R1IN_4_ADD_2_1_AXB_25,
LO => R1IN_4_ADD_2_1_CRY_25);
R1IN_4_ADD_2_1_S_24: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_24,
CI => R1IN_4_ADD_2_1_CRY_23,
O => N_1491);
R1IN_4_ADD_2_1_CRY_24_Z6587: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_23,
S => R1IN_4_ADD_2_1_AXB_24,
LO => R1IN_4_ADD_2_1_CRY_24);
R1IN_4_ADD_2_1_S_23: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_23,
CI => R1IN_4_ADD_2_1_CRY_22,
O => N_1489);
R1IN_4_ADD_2_1_CRY_23_Z6589: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_22,
S => R1IN_4_ADD_2_1_AXB_23,
LO => R1IN_4_ADD_2_1_CRY_23);
R1IN_4_ADD_2_1_S_22: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_22,
CI => R1IN_4_ADD_2_1_CRY_21,
O => N_1487);
R1IN_4_ADD_2_1_CRY_22_Z6591: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_21,
S => R1IN_4_ADD_2_1_AXB_22,
LO => R1IN_4_ADD_2_1_CRY_22);
R1IN_4_ADD_2_1_S_21: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_21,
CI => R1IN_4_ADD_2_1_CRY_20,
O => N_1485);
R1IN_4_ADD_2_1_CRY_21_Z6593: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_20,
S => R1IN_4_ADD_2_1_AXB_21,
LO => R1IN_4_ADD_2_1_CRY_21);
R1IN_4_ADD_2_1_S_20: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_20,
CI => R1IN_4_ADD_2_1_CRY_19,
O => N_1483);
R1IN_4_ADD_2_1_CRY_20_Z6595: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_19,
S => R1IN_4_ADD_2_1_AXB_20,
LO => R1IN_4_ADD_2_1_CRY_20);
R1IN_4_ADD_2_1_S_19: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_19,
CI => R1IN_4_ADD_2_1_CRY_18,
O => N_1481);
R1IN_4_ADD_2_1_CRY_19_Z6597: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_18,
S => R1IN_4_ADD_2_1_AXB_19,
LO => R1IN_4_ADD_2_1_CRY_19);
R1IN_4_ADD_2_1_S_18: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_18,
CI => R1IN_4_ADD_2_1_CRY_17,
O => N_1479);
R1IN_4_ADD_2_1_CRY_18_Z6599: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_17,
S => R1IN_4_ADD_2_1_AXB_18,
LO => R1IN_4_ADD_2_1_CRY_18);
R1IN_4_ADD_2_1_S_17: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_17,
CI => R1IN_4_ADD_2_1_CRY_16,
O => N_1477);
R1IN_4_ADD_2_1_CRY_17_Z6601: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_16,
S => R1IN_4_ADD_2_1_AXB_17,
LO => R1IN_4_ADD_2_1_CRY_17);
R1IN_4_ADD_2_1_S_16: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_16,
CI => R1IN_4_ADD_2_1_CRY_15,
O => N_1475);
R1IN_4_ADD_2_1_CRY_16_Z6603: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_15,
S => R1IN_4_ADD_2_1_AXB_16,
LO => R1IN_4_ADD_2_1_CRY_16);
R1IN_4_ADD_2_1_S_15: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_15,
CI => R1IN_4_ADD_2_1_CRY_14,
O => N_1473);
R1IN_4_ADD_2_1_CRY_15_Z6605: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_14,
S => R1IN_4_ADD_2_1_AXB_15,
LO => R1IN_4_ADD_2_1_CRY_15);
R1IN_4_ADD_2_1_S_14: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_14,
CI => R1IN_4_ADD_2_1_CRY_13,
O => N_1471);
R1IN_4_ADD_2_1_CRY_14_Z6607: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_13,
S => R1IN_4_ADD_2_1_AXB_14,
LO => R1IN_4_ADD_2_1_CRY_14);
R1IN_4_ADD_2_1_S_13: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_13,
CI => R1IN_4_ADD_2_1_CRY_12,
O => N_1469);
R1IN_4_ADD_2_1_CRY_13_Z6609: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_12,
S => R1IN_4_ADD_2_1_AXB_13,
LO => R1IN_4_ADD_2_1_CRY_13);
R1IN_4_ADD_2_1_S_12: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_12,
CI => R1IN_4_ADD_2_1_CRY_11,
O => N_1467);
R1IN_4_ADD_2_1_CRY_12_Z6611: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_11,
S => R1IN_4_ADD_2_1_AXB_12,
LO => R1IN_4_ADD_2_1_CRY_12);
R1IN_4_ADD_2_1_S_11: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_11,
CI => R1IN_4_ADD_2_1_CRY_10,
O => N_1465);
R1IN_4_ADD_2_1_CRY_11_Z6613: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_10,
S => R1IN_4_ADD_2_1_AXB_11,
LO => R1IN_4_ADD_2_1_CRY_11);
R1IN_4_ADD_2_1_S_10: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_10,
CI => R1IN_4_ADD_2_1_CRY_9,
O => N_1463);
R1IN_4_ADD_2_1_CRY_10_Z6615: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_9,
S => R1IN_4_ADD_2_1_AXB_10,
LO => R1IN_4_ADD_2_1_CRY_10);
R1IN_4_ADD_2_1_S_9: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_9,
CI => R1IN_4_ADD_2_1_CRY_8,
O => N_1461);
R1IN_4_ADD_2_1_CRY_9_Z6617: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_8,
S => R1IN_4_ADD_2_1_AXB_9,
LO => R1IN_4_ADD_2_1_CRY_9);
R1IN_4_ADD_2_1_S_8: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_8,
CI => R1IN_4_ADD_2_1_CRY_7,
O => N_1459);
R1IN_4_ADD_2_1_CRY_8_Z6619: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(44),
CI => R1IN_4_ADD_2_1_CRY_7,
S => R1IN_4_ADD_2_1_AXB_8,
LO => R1IN_4_ADD_2_1_CRY_8);
R1IN_4_ADD_2_1_S_7: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_7,
CI => R1IN_4_ADD_2_1_CRY_6,
O => N_1457);
R1IN_4_ADD_2_1_CRY_7_Z6621: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(43),
CI => R1IN_4_ADD_2_1_CRY_6,
S => R1IN_4_ADD_2_1_AXB_7,
LO => R1IN_4_ADD_2_1_CRY_7);
R1IN_4_ADD_2_1_S_6: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_6,
CI => R1IN_4_ADD_2_1_CRY_5,
O => N_1455);
R1IN_4_ADD_2_1_CRY_6_Z6623: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(42),
CI => R1IN_4_ADD_2_1_CRY_5,
S => R1IN_4_ADD_2_1_AXB_6,
LO => R1IN_4_ADD_2_1_CRY_6);
R1IN_4_ADD_2_1_S_5: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_5,
CI => R1IN_4_ADD_2_1_CRY_4,
O => N_1453);
R1IN_4_ADD_2_1_CRY_5_Z6625: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(41),
CI => R1IN_4_ADD_2_1_CRY_4,
S => R1IN_4_ADD_2_1_AXB_5,
LO => R1IN_4_ADD_2_1_CRY_5);
R1IN_4_ADD_2_1_S_4: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_4,
CI => R1IN_4_ADD_2_1_CRY_3,
O => N_1451);
R1IN_4_ADD_2_1_CRY_4_Z6627: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(40),
CI => R1IN_4_ADD_2_1_CRY_3,
S => R1IN_4_ADD_2_1_AXB_4,
LO => R1IN_4_ADD_2_1_CRY_4);
R1IN_4_ADD_2_1_S_3: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_3,
CI => R1IN_4_ADD_2_1_CRY_2,
O => N_1449);
R1IN_4_ADD_2_1_CRY_3_Z6629: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(39),
CI => R1IN_4_ADD_2_1_CRY_2,
S => R1IN_4_ADD_2_1_AXB_3,
LO => R1IN_4_ADD_2_1_CRY_3);
R1IN_4_ADD_2_1_S_2: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_2,
CI => R1IN_4_ADD_2_1_CRY_1,
O => N_1447);
R1IN_4_ADD_2_1_CRY_2_Z6631: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(38),
CI => R1IN_4_ADD_2_1_CRY_1,
S => R1IN_4_ADD_2_1_AXB_2,
LO => R1IN_4_ADD_2_1_CRY_2);
R1IN_4_ADD_2_1_S_1: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_1,
CI => R1IN_4_ADD_2_1_CRY_0,
O => N_1445);
R1IN_4_ADD_2_1_CRY_1_Z6633: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(37),
CI => R1IN_4_ADD_2_1_CRY_0,
S => R1IN_4_ADD_2_1_AXB_1,
LO => R1IN_4_ADD_2_1_CRY_1);
R1IN_4_ADD_2_1_CRY_0_Z6634: MUXCY_L port map (
DI => R1IN_4_ADD_2_1_RETO,
CI => NN_1,
S => R1IN_4_ADD_2_1_AXB_0,
LO => R1IN_4_ADD_2_1_CRY_0);
R1IN_4_ADD_2_0_S_35: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_35,
CI => R1IN_4_ADD_2_0_CRY_34,
O => R1IN_4(52));
R1IN_4_ADD_2_0_CRY_35_Z6636: MUXCY port map (
DI => R1IN_4_ADD_1_RETO(35),
CI => R1IN_4_ADD_2_0_CRY_34,
S => R1IN_4_ADD_2_0_AXB_35,
O => R1IN_4_ADD_2_0_CRY_35);
R1IN_4_ADD_2_0_S_34: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_34,
CI => R1IN_4_ADD_2_0_CRY_33,
O => R1IN_4(51));
R1IN_4_ADD_2_0_CRY_34_Z6638: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(34),
CI => R1IN_4_ADD_2_0_CRY_33,
S => R1IN_4_ADD_2_0_AXB_34,
LO => R1IN_4_ADD_2_0_CRY_34);
R1IN_4_ADD_2_0_S_33: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_33,
CI => R1IN_4_ADD_2_0_CRY_32,
O => R1IN_4(50));
R1IN_4_ADD_2_0_CRY_33_Z6640: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(33),
CI => R1IN_4_ADD_2_0_CRY_32,
S => R1IN_4_ADD_2_0_AXB_33,
LO => R1IN_4_ADD_2_0_CRY_33);
R1IN_4_ADD_2_0_S_32: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_32,
CI => R1IN_4_ADD_2_0_CRY_31,
O => R1IN_4(49));
R1IN_4_ADD_2_0_CRY_32_Z6642: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(32),
CI => R1IN_4_ADD_2_0_CRY_31,
S => R1IN_4_ADD_2_0_AXB_32,
LO => R1IN_4_ADD_2_0_CRY_32);
R1IN_4_ADD_2_0_S_31: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_31,
CI => R1IN_4_ADD_2_0_CRY_30,
O => R1IN_4(48));
R1IN_4_ADD_2_0_CRY_31_Z6644: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(31),
CI => R1IN_4_ADD_2_0_CRY_30,
S => R1IN_4_ADD_2_0_AXB_31,
LO => R1IN_4_ADD_2_0_CRY_31);
R1IN_4_ADD_2_0_S_30: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_30,
CI => R1IN_4_ADD_2_0_CRY_29,
O => R1IN_4(47));
R1IN_4_ADD_2_0_CRY_30_Z6646: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(30),
CI => R1IN_4_ADD_2_0_CRY_29,
S => R1IN_4_ADD_2_0_AXB_30,
LO => R1IN_4_ADD_2_0_CRY_30);
R1IN_4_ADD_2_0_S_29: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_29,
CI => R1IN_4_ADD_2_0_CRY_28,
O => R1IN_4(46));
R1IN_4_ADD_2_0_CRY_29_Z6648: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(29),
CI => R1IN_4_ADD_2_0_CRY_28,
S => R1IN_4_ADD_2_0_AXB_29,
LO => R1IN_4_ADD_2_0_CRY_29);
R1IN_4_ADD_2_0_S_28: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_28,
CI => R1IN_4_ADD_2_0_CRY_27,
O => R1IN_4(45));
R1IN_4_ADD_2_0_CRY_28_Z6650: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(28),
CI => R1IN_4_ADD_2_0_CRY_27,
S => R1IN_4_ADD_2_0_AXB_28,
LO => R1IN_4_ADD_2_0_CRY_28);
R1IN_4_ADD_2_0_S_27: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_27,
CI => R1IN_4_ADD_2_0_CRY_26,
O => R1IN_4(44));
R1IN_4_ADD_2_0_CRY_27_Z6652: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(27),
CI => R1IN_4_ADD_2_0_CRY_26,
S => R1IN_4_ADD_2_0_AXB_27,
LO => R1IN_4_ADD_2_0_CRY_27);
R1IN_4_ADD_2_0_S_26: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_26,
CI => R1IN_4_ADD_2_0_CRY_25,
O => R1IN_4(43));
R1IN_4_ADD_2_0_CRY_26_Z6654: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(26),
CI => R1IN_4_ADD_2_0_CRY_25,
S => R1IN_4_ADD_2_0_AXB_26,
LO => R1IN_4_ADD_2_0_CRY_26);
R1IN_4_ADD_2_0_S_25: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_25,
CI => R1IN_4_ADD_2_0_CRY_24,
O => R1IN_4(42));
R1IN_4_ADD_2_0_CRY_25_Z6656: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(25),
CI => R1IN_4_ADD_2_0_CRY_24,
S => R1IN_4_ADD_2_0_AXB_25,
LO => R1IN_4_ADD_2_0_CRY_25);
R1IN_4_ADD_2_0_S_24: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_24,
CI => R1IN_4_ADD_2_0_CRY_23,
O => R1IN_4(41));
R1IN_4_ADD_2_0_CRY_24_Z6658: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(24),
CI => R1IN_4_ADD_2_0_CRY_23,
S => R1IN_4_ADD_2_0_AXB_24,
LO => R1IN_4_ADD_2_0_CRY_24);
R1IN_4_ADD_2_0_S_23: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_23,
CI => R1IN_4_ADD_2_0_CRY_22,
O => R1IN_4(40));
R1IN_4_ADD_2_0_CRY_23_Z6660: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(23),
CI => R1IN_4_ADD_2_0_CRY_22,
S => R1IN_4_ADD_2_0_AXB_23,
LO => R1IN_4_ADD_2_0_CRY_23);
R1IN_4_ADD_2_0_S_22: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_22,
CI => R1IN_4_ADD_2_0_CRY_21,
O => R1IN_4(39));
R1IN_4_ADD_2_0_CRY_22_Z6662: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(22),
CI => R1IN_4_ADD_2_0_CRY_21,
S => R1IN_4_ADD_2_0_AXB_22,
LO => R1IN_4_ADD_2_0_CRY_22);
R1IN_4_ADD_2_0_S_21: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_21,
CI => R1IN_4_ADD_2_0_CRY_20,
O => R1IN_4(38));
R1IN_4_ADD_2_0_CRY_21_Z6664: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(21),
CI => R1IN_4_ADD_2_0_CRY_20,
S => R1IN_4_ADD_2_0_AXB_21,
LO => R1IN_4_ADD_2_0_CRY_21);
R1IN_4_ADD_2_0_S_20: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_20,
CI => R1IN_4_ADD_2_0_CRY_19,
O => R1IN_4(37));
R1IN_4_ADD_2_0_CRY_20_Z6666: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(20),
CI => R1IN_4_ADD_2_0_CRY_19,
S => R1IN_4_ADD_2_0_AXB_20,
LO => R1IN_4_ADD_2_0_CRY_20);
R1IN_4_ADD_2_0_S_19: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_19,
CI => R1IN_4_ADD_2_0_CRY_18,
O => R1IN_4(36));
R1IN_4_ADD_2_0_CRY_19_Z6668: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(19),
CI => R1IN_4_ADD_2_0_CRY_18,
S => R1IN_4_ADD_2_0_AXB_19,
LO => R1IN_4_ADD_2_0_CRY_19);
R1IN_4_ADD_2_0_S_18: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_18,
CI => R1IN_4_ADD_2_0_CRY_17,
O => R1IN_4(35));
R1IN_4_ADD_2_0_CRY_18_Z6670: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(18),
CI => R1IN_4_ADD_2_0_CRY_17,
S => R1IN_4_ADD_2_0_AXB_18,
LO => R1IN_4_ADD_2_0_CRY_18);
R1IN_4_ADD_2_0_S_17: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_17,
CI => R1IN_4_ADD_2_0_CRY_16,
O => R1IN_4(34));
R1IN_4_ADD_2_0_CRY_17_Z6672: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(17),
CI => R1IN_4_ADD_2_0_CRY_16,
S => R1IN_4_ADD_2_0_AXB_17,
LO => R1IN_4_ADD_2_0_CRY_17);
R1IN_4_ADD_2_0_S_16: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_16,
CI => R1IN_4_ADD_2_0_CRY_15,
O => R1IN_4(33));
R1IN_4_ADD_2_0_CRY_16_Z6674: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(16),
CI => R1IN_4_ADD_2_0_CRY_15,
S => R1IN_4_ADD_2_0_AXB_16,
LO => R1IN_4_ADD_2_0_CRY_16);
R1IN_4_ADD_2_0_S_15: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_15,
CI => R1IN_4_ADD_2_0_CRY_14,
O => R1IN_4(32));
R1IN_4_ADD_2_0_CRY_15_Z6676: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(15),
CI => R1IN_4_ADD_2_0_CRY_14,
S => R1IN_4_ADD_2_0_AXB_15,
LO => R1IN_4_ADD_2_0_CRY_15);
R1IN_4_ADD_2_0_S_14: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_14,
CI => R1IN_4_ADD_2_0_CRY_13,
O => R1IN_4(31));
R1IN_4_ADD_2_0_CRY_14_Z6678: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(14),
CI => R1IN_4_ADD_2_0_CRY_13,
S => R1IN_4_ADD_2_0_AXB_14,
LO => R1IN_4_ADD_2_0_CRY_14);
R1IN_4_ADD_2_0_S_13: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_13,
CI => R1IN_4_ADD_2_0_CRY_12,
O => R1IN_4(30));
R1IN_4_ADD_2_0_CRY_13_Z6680: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(13),
CI => R1IN_4_ADD_2_0_CRY_12,
S => R1IN_4_ADD_2_0_AXB_13,
LO => R1IN_4_ADD_2_0_CRY_13);
R1IN_4_ADD_2_0_S_12: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_12,
CI => R1IN_4_ADD_2_0_CRY_11,
O => R1IN_4(29));
R1IN_4_ADD_2_0_CRY_12_Z6682: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(12),
CI => R1IN_4_ADD_2_0_CRY_11,
S => R1IN_4_ADD_2_0_AXB_12,
LO => R1IN_4_ADD_2_0_CRY_12);
R1IN_4_ADD_2_0_S_11: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_11,
CI => R1IN_4_ADD_2_0_CRY_10,
O => R1IN_4(28));
R1IN_4_ADD_2_0_CRY_11_Z6684: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(11),
CI => R1IN_4_ADD_2_0_CRY_10,
S => R1IN_4_ADD_2_0_AXB_11,
LO => R1IN_4_ADD_2_0_CRY_11);
R1IN_4_ADD_2_0_S_10: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_10,
CI => R1IN_4_ADD_2_0_CRY_9,
O => R1IN_4(27));
R1IN_4_ADD_2_0_CRY_10_Z6686: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(10),
CI => R1IN_4_ADD_2_0_CRY_9,
S => R1IN_4_ADD_2_0_AXB_10,
LO => R1IN_4_ADD_2_0_CRY_10);
R1IN_4_ADD_2_0_S_9: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_9,
CI => R1IN_4_ADD_2_0_CRY_8,
O => R1IN_4(26));
R1IN_4_ADD_2_0_CRY_9_Z6688: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(9),
CI => R1IN_4_ADD_2_0_CRY_8,
S => R1IN_4_ADD_2_0_AXB_9,
LO => R1IN_4_ADD_2_0_CRY_9);
R1IN_4_ADD_2_0_S_8: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_8,
CI => R1IN_4_ADD_2_0_CRY_7,
O => R1IN_4(25));
R1IN_4_ADD_2_0_CRY_8_Z6690: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(8),
CI => R1IN_4_ADD_2_0_CRY_7,
S => R1IN_4_ADD_2_0_AXB_8,
LO => R1IN_4_ADD_2_0_CRY_8);
R1IN_4_ADD_2_0_S_7: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_7,
CI => R1IN_4_ADD_2_0_CRY_6,
O => R1IN_4(24));
R1IN_4_ADD_2_0_CRY_7_Z6692: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(7),
CI => R1IN_4_ADD_2_0_CRY_6,
S => R1IN_4_ADD_2_0_AXB_7,
LO => R1IN_4_ADD_2_0_CRY_7);
R1IN_4_ADD_2_0_S_6: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_6,
CI => R1IN_4_ADD_2_0_CRY_5,
O => R1IN_4(23));
R1IN_4_ADD_2_0_CRY_6_Z6694: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(6),
CI => R1IN_4_ADD_2_0_CRY_5,
S => R1IN_4_ADD_2_0_AXB_6,
LO => R1IN_4_ADD_2_0_CRY_6);
R1IN_4_ADD_2_0_S_5: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_5,
CI => R1IN_4_ADD_2_0_CRY_4,
O => R1IN_4(22));
R1IN_4_ADD_2_0_CRY_5_Z6696: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(5),
CI => R1IN_4_ADD_2_0_CRY_4,
S => R1IN_4_ADD_2_0_AXB_5,
LO => R1IN_4_ADD_2_0_CRY_5);
R1IN_4_ADD_2_0_S_4: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_4,
CI => R1IN_4_ADD_2_0_CRY_3,
O => R1IN_4(21));
R1IN_4_ADD_2_0_CRY_4_Z6698: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(4),
CI => R1IN_4_ADD_2_0_CRY_3,
S => R1IN_4_ADD_2_0_AXB_4,
LO => R1IN_4_ADD_2_0_CRY_4);
R1IN_4_ADD_2_0_S_3: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_3,
CI => R1IN_4_ADD_2_0_CRY_2,
O => R1IN_4(20));
R1IN_4_ADD_2_0_CRY_3_Z6700: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(3),
CI => R1IN_4_ADD_2_0_CRY_2,
S => R1IN_4_ADD_2_0_AXB_3,
LO => R1IN_4_ADD_2_0_CRY_3);
R1IN_4_ADD_2_0_S_2: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_2,
CI => R1IN_4_ADD_2_0_CRY_1,
O => R1IN_4(19));
R1IN_4_ADD_2_0_CRY_2_Z6702: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(2),
CI => R1IN_4_ADD_2_0_CRY_1,
S => R1IN_4_ADD_2_0_AXB_2,
LO => R1IN_4_ADD_2_0_CRY_2);
R1IN_4_ADD_2_0_S_1: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_1,
CI => R1IN_4_ADD_2_0_CRY_0,
O => R1IN_4(18));
R1IN_4_ADD_2_0_CRY_1_Z6704: MUXCY_L port map (
DI => R1IN_4_ADD_1_RETO(1),
CI => R1IN_4_ADD_2_0_CRY_0,
S => R1IN_4_ADD_2_0_AXB_1,
LO => R1IN_4_ADD_2_0_CRY_1);
R1IN_4_ADD_2_0_CRY_0_Z6705: MUXCY_L port map (
DI => R1IN_4_ADD_2_0_RETO,
CI => NN_1,
S => R1IN_4(17),
LO => R1IN_4_ADD_2_0_CRY_0);
R1IN_4_4_4q190w: DSP48
generic map(
AREG => 1,
BREG => 1,
CREG => 0,
PREG => 1,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => A(51),
A(1) => A(52),
A(2) => A(53),
A(3) => A(54),
A(4) => A(55),
A(5) => A(56),
A(6) => A(57),
A(7) => A(58),
A(8) => A(59),
A(9) => A(60),
A(10) => NN_1,
A(11) => NN_1,
A(12) => NN_1,
A(13) => NN_1,
A(14) => NN_1,
A(15) => NN_1,
A(16) => NN_1,
A(17) => NN_1,
B(0) => B(51),
B(1) => B(52),
B(2) => B(53),
B(3) => B(54),
B(4) => B(55),
B(5) => B(56),
B(6) => B(57),
B(7) => B(58),
B(8) => B(59),
B(9) => B(60),
B(10) => NN_1,
B(11) => NN_1,
B(12) => NN_1,
B(13) => NN_1,
B(14) => NN_1,
B(15) => NN_1,
B(16) => NN_1,
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => EN,
CEB => EN,
CEC => NN_1,
CEP => EN,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_4_4_4_BCOUT(0),
BCOUT(1) => R1IN_4_4_4_BCOUT(1),
BCOUT(2) => R1IN_4_4_4_BCOUT(2),
BCOUT(3) => R1IN_4_4_4_BCOUT(3),
BCOUT(4) => R1IN_4_4_4_BCOUT(4),
BCOUT(5) => R1IN_4_4_4_BCOUT(5),
BCOUT(6) => R1IN_4_4_4_BCOUT(6),
BCOUT(7) => R1IN_4_4_4_BCOUT(7),
BCOUT(8) => R1IN_4_4_4_BCOUT(8),
BCOUT(9) => R1IN_4_4_4_BCOUT(9),
BCOUT(10) => R1IN_4_4_4_BCOUT(10),
BCOUT(11) => R1IN_4_4_4_BCOUT(11),
BCOUT(12) => R1IN_4_4_4_BCOUT(12),
BCOUT(13) => R1IN_4_4_4_BCOUT(13),
BCOUT(14) => R1IN_4_4_4_BCOUT(14),
BCOUT(15) => R1IN_4_4_4_BCOUT(15),
BCOUT(16) => R1IN_4_4_4_BCOUT(16),
BCOUT(17) => R1IN_4_4_4_BCOUT(17),
P(0) => R1IN_4_4_4F_RETO(0),
P(1) => R1IN_4_4_4F_RETO(1),
P(2) => R1IN_4_4_4F_RETO(2),
P(3) => R1IN_4_4_4F_RETO(3),
P(4) => R1IN_4_4_4F_RETO(4),
P(5) => R1IN_4_4_4F_RETO(5),
P(6) => R1IN_4_4_4F_RETO(6),
P(7) => R1IN_4_4_4F_RETO(7),
P(8) => R1IN_4_4_4F_RETO(8),
P(9) => R1IN_4_4_4F_RETO(9),
P(10) => R1IN_4_4_4F_RETO(10),
P(11) => R1IN_4_4_4F_RETO(11),
P(12) => R1IN_4_4_4F_RETO(12),
P(13) => R1IN_4_4_4F_RETO(13),
P(14) => R1IN_4_4_4F_RETO(14),
P(15) => R1IN_4_4_4F_RETO(15),
P(16) => R1IN_4_4_4F_RETO(16),
P(17) => R1IN_4_4_4F_RETO(17),
P(18) => R1IN_4_4_4F_RETO(18),
P(19) => R1IN_4_4_4F_RETO(19),
P(20) => R1IN_4_4_4_P(20),
P(21) => R1IN_4_4_4_P(21),
P(22) => R1IN_4_4_4_P(22),
P(23) => R1IN_4_4_4_P(23),
P(24) => R1IN_4_4_4_P(24),
P(25) => R1IN_4_4_4_P(25),
P(26) => R1IN_4_4_4_P(26),
P(27) => R1IN_4_4_4_P(27),
P(28) => R1IN_4_4_4_P(28),
P(29) => R1IN_4_4_4_P(29),
P(30) => R1IN_4_4_4_P(30),
P(31) => R1IN_4_4_4_P(31),
P(32) => R1IN_4_4_4_P(32),
P(33) => R1IN_4_4_4_P(33),
P(34) => R1IN_4_4_4_P(34),
P(35) => R1IN_4_4_4_P(35),
P(36) => R1IN_4_4_4_P(36),
P(37) => R1IN_4_4_4_P(37),
P(38) => R1IN_4_4_4_P(38),
P(39) => R1IN_4_4_4_P(39),
P(40) => R1IN_4_4_4_P(40),
P(41) => R1IN_4_4_4_P(41),
P(42) => R1IN_4_4_4_P(42),
P(43) => R1IN_4_4_4_P(43),
P(44) => R1IN_4_4_4_P(44),
P(45) => R1IN_4_4_4_P(45),
P(46) => R1IN_4_4_4_P(46),
P(47) => R1IN_4_4_4_P(47),
PCOUT(0) => R1IN_4_4_4_PCOUT(0),
PCOUT(1) => R1IN_4_4_4_PCOUT(1),
PCOUT(2) => R1IN_4_4_4_PCOUT(2),
PCOUT(3) => R1IN_4_4_4_PCOUT(3),
PCOUT(4) => R1IN_4_4_4_PCOUT(4),
PCOUT(5) => R1IN_4_4_4_PCOUT(5),
PCOUT(6) => R1IN_4_4_4_PCOUT(6),
PCOUT(7) => R1IN_4_4_4_PCOUT(7),
PCOUT(8) => R1IN_4_4_4_PCOUT(8),
PCOUT(9) => R1IN_4_4_4_PCOUT(9),
PCOUT(10) => R1IN_4_4_4_PCOUT(10),
PCOUT(11) => R1IN_4_4_4_PCOUT(11),
PCOUT(12) => R1IN_4_4_4_PCOUT(12),
PCOUT(13) => R1IN_4_4_4_PCOUT(13),
PCOUT(14) => R1IN_4_4_4_PCOUT(14),
PCOUT(15) => R1IN_4_4_4_PCOUT(15),
PCOUT(16) => R1IN_4_4_4_PCOUT(16),
PCOUT(17) => R1IN_4_4_4_PCOUT(17),
PCOUT(18) => R1IN_4_4_4_PCOUT(18),
PCOUT(19) => R1IN_4_4_4_PCOUT(19),
PCOUT(20) => R1IN_4_4_4_PCOUT(20),
PCOUT(21) => R1IN_4_4_4_PCOUT(21),
PCOUT(22) => R1IN_4_4_4_PCOUT(22),
PCOUT(23) => R1IN_4_4_4_PCOUT(23),
PCOUT(24) => R1IN_4_4_4_PCOUT(24),
PCOUT(25) => R1IN_4_4_4_PCOUT(25),
PCOUT(26) => R1IN_4_4_4_PCOUT(26),
PCOUT(27) => R1IN_4_4_4_PCOUT(27),
PCOUT(28) => R1IN_4_4_4_PCOUT(28),
PCOUT(29) => R1IN_4_4_4_PCOUT(29),
PCOUT(30) => R1IN_4_4_4_PCOUT(30),
PCOUT(31) => R1IN_4_4_4_PCOUT(31),
PCOUT(32) => R1IN_4_4_4_PCOUT(32),
PCOUT(33) => R1IN_4_4_4_PCOUT(33),
PCOUT(34) => R1IN_4_4_4_PCOUT(34),
PCOUT(35) => R1IN_4_4_4_PCOUT(35),
PCOUT(36) => R1IN_4_4_4_PCOUT(36),
PCOUT(37) => R1IN_4_4_4_PCOUT(37),
PCOUT(38) => R1IN_4_4_4_PCOUT(38),
PCOUT(39) => R1IN_4_4_4_PCOUT(39),
PCOUT(40) => R1IN_4_4_4_PCOUT(40),
PCOUT(41) => R1IN_4_4_4_PCOUT(41),
PCOUT(42) => R1IN_4_4_4_PCOUT(42),
PCOUT(43) => R1IN_4_4_4_PCOUT(43),
PCOUT(44) => R1IN_4_4_4_PCOUT(44),
PCOUT(45) => R1IN_4_4_4_PCOUT(45),
PCOUT(46) => R1IN_4_4_4_PCOUT(46),
PCOUT(47) => R1IN_4_4_4_PCOUT(47));
R1IN_4_4_1q330w: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 0,
MREG => 1,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18S"
)
port map (
A(0) => A(34),
A(1) => A(35),
A(2) => A(36),
A(3) => A(37),
A(4) => A(38),
A(5) => A(39),
A(6) => A(40),
A(7) => A(41),
A(8) => A(42),
A(9) => A(43),
A(10) => A(44),
A(11) => A(45),
A(12) => A(46),
A(13) => A(47),
A(14) => A(48),
A(15) => A(49),
A(16) => A(50),
A(17) => NN_1,
B(0) => B(34),
B(1) => B(35),
B(2) => B(36),
B(3) => B(37),
B(4) => B(38),
B(5) => B(39),
B(6) => B(40),
B(7) => B(41),
B(8) => B(42),
B(9) => B(43),
B(10) => B(44),
B(11) => B(45),
B(12) => B(46),
B(13) => B(47),
B(14) => B(48),
B(15) => B(49),
B(16) => B(50),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => NN_1,
CEM => EN,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_4_4_1_BCOUT(0),
BCOUT(1) => R1IN_4_4_1_BCOUT(1),
BCOUT(2) => R1IN_4_4_1_BCOUT(2),
BCOUT(3) => R1IN_4_4_1_BCOUT(3),
BCOUT(4) => R1IN_4_4_1_BCOUT(4),
BCOUT(5) => R1IN_4_4_1_BCOUT(5),
BCOUT(6) => R1IN_4_4_1_BCOUT(6),
BCOUT(7) => R1IN_4_4_1_BCOUT(7),
BCOUT(8) => R1IN_4_4_1_BCOUT(8),
BCOUT(9) => R1IN_4_4_1_BCOUT(9),
BCOUT(10) => R1IN_4_4_1_BCOUT(10),
BCOUT(11) => R1IN_4_4_1_BCOUT(11),
BCOUT(12) => R1IN_4_4_1_BCOUT(12),
BCOUT(13) => R1IN_4_4_1_BCOUT(13),
BCOUT(14) => R1IN_4_4_1_BCOUT(14),
BCOUT(15) => R1IN_4_4_1_BCOUT(15),
BCOUT(16) => R1IN_4_4_1_BCOUT(16),
BCOUT(17) => R1IN_4_4_1_BCOUT(17),
P(0) => R1IN_4_4F(0),
P(1) => R1IN_4_4F(1),
P(2) => R1IN_4_4F(2),
P(3) => R1IN_4_4F(3),
P(4) => R1IN_4_4F(4),
P(5) => R1IN_4_4F(5),
P(6) => R1IN_4_4F(6),
P(7) => R1IN_4_4F(7),
P(8) => R1IN_4_4F(8),
P(9) => R1IN_4_4F(9),
P(10) => R1IN_4_4F(10),
P(11) => R1IN_4_4F(11),
P(12) => R1IN_4_4F(12),
P(13) => R1IN_4_4F(13),
P(14) => R1IN_4_4F(14),
P(15) => R1IN_4_4F(15),
P(16) => R1IN_4_4F(16),
P(17) => R1IN_4_4_ADD_2,
P(18) => R1IN_4_4_1F(18),
P(19) => R1IN_4_4_1F(19),
P(20) => R1IN_4_4_1F(20),
P(21) => R1IN_4_4_1F(21),
P(22) => R1IN_4_4_1F(22),
P(23) => R1IN_4_4_1F(23),
P(24) => R1IN_4_4_1F(24),
P(25) => R1IN_4_4_1F(25),
P(26) => R1IN_4_4_1F(26),
P(27) => R1IN_4_4_1F(27),
P(28) => R1IN_4_4_1F(28),
P(29) => R1IN_4_4_1F(29),
P(30) => R1IN_4_4_1F(30),
P(31) => R1IN_4_4_1F(31),
P(32) => R1IN_4_4_1F(32),
P(33) => R1IN_4_4_1F(33),
P(34) => UC_236,
P(35) => UC_237,
P(36) => UC_238,
P(37) => UC_239,
P(38) => UC_240,
P(39) => UC_241,
P(40) => UC_242,
P(41) => UC_243,
P(42) => UC_244,
P(43) => UC_245,
P(44) => UC_246,
P(45) => UC_247,
P(46) => UC_248,
P(47) => UC_249,
PCOUT(0) => R1IN_4_4_1_PCOUT(0),
PCOUT(1) => R1IN_4_4_1_PCOUT(1),
PCOUT(2) => R1IN_4_4_1_PCOUT(2),
PCOUT(3) => R1IN_4_4_1_PCOUT(3),
PCOUT(4) => R1IN_4_4_1_PCOUT(4),
PCOUT(5) => R1IN_4_4_1_PCOUT(5),
PCOUT(6) => R1IN_4_4_1_PCOUT(6),
PCOUT(7) => R1IN_4_4_1_PCOUT(7),
PCOUT(8) => R1IN_4_4_1_PCOUT(8),
PCOUT(9) => R1IN_4_4_1_PCOUT(9),
PCOUT(10) => R1IN_4_4_1_PCOUT(10),
PCOUT(11) => R1IN_4_4_1_PCOUT(11),
PCOUT(12) => R1IN_4_4_1_PCOUT(12),
PCOUT(13) => R1IN_4_4_1_PCOUT(13),
PCOUT(14) => R1IN_4_4_1_PCOUT(14),
PCOUT(15) => R1IN_4_4_1_PCOUT(15),
PCOUT(16) => R1IN_4_4_1_PCOUT(16),
PCOUT(17) => R1IN_4_4_1_PCOUT(17),
PCOUT(18) => R1IN_4_4_1_PCOUT(18),
PCOUT(19) => R1IN_4_4_1_PCOUT(19),
PCOUT(20) => R1IN_4_4_1_PCOUT(20),
PCOUT(21) => R1IN_4_4_1_PCOUT(21),
PCOUT(22) => R1IN_4_4_1_PCOUT(22),
PCOUT(23) => R1IN_4_4_1_PCOUT(23),
PCOUT(24) => R1IN_4_4_1_PCOUT(24),
PCOUT(25) => R1IN_4_4_1_PCOUT(25),
PCOUT(26) => R1IN_4_4_1_PCOUT(26),
PCOUT(27) => R1IN_4_4_1_PCOUT(27),
PCOUT(28) => R1IN_4_4_1_PCOUT(28),
PCOUT(29) => R1IN_4_4_1_PCOUT(29),
PCOUT(30) => R1IN_4_4_1_PCOUT(30),
PCOUT(31) => R1IN_4_4_1_PCOUT(31),
PCOUT(32) => R1IN_4_4_1_PCOUT(32),
PCOUT(33) => R1IN_4_4_1_PCOUT(33),
PCOUT(34) => R1IN_4_4_1_PCOUT(34),
PCOUT(35) => R1IN_4_4_1_PCOUT(35),
PCOUT(36) => R1IN_4_4_1_PCOUT(36),
PCOUT(37) => R1IN_4_4_1_PCOUT(37),
PCOUT(38) => R1IN_4_4_1_PCOUT(38),
PCOUT(39) => R1IN_4_4_1_PCOUT(39),
PCOUT(40) => R1IN_4_4_1_PCOUT(40),
PCOUT(41) => R1IN_4_4_1_PCOUT(41),
PCOUT(42) => R1IN_4_4_1_PCOUT(42),
PCOUT(43) => R1IN_4_4_1_PCOUT(43),
PCOUT(44) => R1IN_4_4_1_PCOUT(44),
PCOUT(45) => R1IN_4_4_1_PCOUT(45),
PCOUT(46) => R1IN_4_4_1_PCOUT(46),
PCOUT(47) => R1IN_4_4_1_PCOUT(47));
R1IN_4_1q330w: DSP48
generic map(
AREG => 1,
BREG => 1,
CREG => 0,
PREG => 1,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => A(17),
A(1) => A(18),
A(2) => A(19),
A(3) => A(20),
A(4) => A(21),
A(5) => A(22),
A(6) => A(23),
A(7) => A(24),
A(8) => A(25),
A(9) => A(26),
A(10) => A(27),
A(11) => A(28),
A(12) => A(29),
A(13) => A(30),
A(14) => A(31),
A(15) => A(32),
A(16) => A(33),
A(17) => NN_1,
B(0) => B(17),
B(1) => B(18),
B(2) => B(19),
B(3) => B(20),
B(4) => B(21),
B(5) => B(22),
B(6) => B(23),
B(7) => B(24),
B(8) => B(25),
B(9) => B(26),
B(10) => B(27),
B(11) => B(28),
B(12) => B(29),
B(13) => B(30),
B(14) => B(31),
B(15) => B(32),
B(16) => B(33),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => EN,
CEB => EN,
CEC => NN_1,
CEP => EN,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_4_1_BCOUT(0),
BCOUT(1) => R1IN_4_1_BCOUT(1),
BCOUT(2) => R1IN_4_1_BCOUT(2),
BCOUT(3) => R1IN_4_1_BCOUT(3),
BCOUT(4) => R1IN_4_1_BCOUT(4),
BCOUT(5) => R1IN_4_1_BCOUT(5),
BCOUT(6) => R1IN_4_1_BCOUT(6),
BCOUT(7) => R1IN_4_1_BCOUT(7),
BCOUT(8) => R1IN_4_1_BCOUT(8),
BCOUT(9) => R1IN_4_1_BCOUT(9),
BCOUT(10) => R1IN_4_1_BCOUT(10),
BCOUT(11) => R1IN_4_1_BCOUT(11),
BCOUT(12) => R1IN_4_1_BCOUT(12),
BCOUT(13) => R1IN_4_1_BCOUT(13),
BCOUT(14) => R1IN_4_1_BCOUT(14),
BCOUT(15) => R1IN_4_1_BCOUT(15),
BCOUT(16) => R1IN_4_1_BCOUT(16),
BCOUT(17) => R1IN_4_1_BCOUT(17),
P(0) => R1IN_4FF(0),
P(1) => R1IN_4FF(1),
P(2) => R1IN_4FF(2),
P(3) => R1IN_4FF(3),
P(4) => R1IN_4FF(4),
P(5) => R1IN_4FF(5),
P(6) => R1IN_4FF(6),
P(7) => R1IN_4FF(7),
P(8) => R1IN_4FF(8),
P(9) => R1IN_4FF(9),
P(10) => R1IN_4FF(10),
P(11) => R1IN_4FF(11),
P(12) => R1IN_4FF(12),
P(13) => R1IN_4FF(13),
P(14) => R1IN_4FF(14),
P(15) => R1IN_4FF(15),
P(16) => R1IN_4FF(16),
P(17) => R1IN_4_1F_RETO(17),
P(18) => R1IN_4_1F_RETO(18),
P(19) => R1IN_4_1F_RETO(19),
P(20) => R1IN_4_1F_RETO(20),
P(21) => R1IN_4_1F_RETO(21),
P(22) => R1IN_4_1F_RETO(22),
P(23) => R1IN_4_1F_RETO(23),
P(24) => R1IN_4_1F_RETO(24),
P(25) => R1IN_4_1F_RETO(25),
P(26) => R1IN_4_1F_RETO(26),
P(27) => R1IN_4_1F_RETO(27),
P(28) => R1IN_4_1F_RETO(28),
P(29) => R1IN_4_1F_RETO(29),
P(30) => R1IN_4_1F_RETO(30),
P(31) => R1IN_4_1F_RETO(31),
P(32) => R1IN_4_1F_RETO(32),
P(33) => R1IN_4_1F_RETO(33),
P(34) => R1IN_4_1_P(34),
P(35) => R1IN_4_1_P(35),
P(36) => R1IN_4_1_P(36),
P(37) => R1IN_4_1_P(37),
P(38) => R1IN_4_1_P(38),
P(39) => R1IN_4_1_P(39),
P(40) => R1IN_4_1_P(40),
P(41) => R1IN_4_1_P(41),
P(42) => R1IN_4_1_P(42),
P(43) => R1IN_4_1_P(43),
P(44) => R1IN_4_1_P(44),
P(45) => R1IN_4_1_P(45),
P(46) => R1IN_4_1_P(46),
P(47) => R1IN_4_1_P(47),
PCOUT(0) => R1IN_4_1_PCOUT(0),
PCOUT(1) => R1IN_4_1_PCOUT(1),
PCOUT(2) => R1IN_4_1_PCOUT(2),
PCOUT(3) => R1IN_4_1_PCOUT(3),
PCOUT(4) => R1IN_4_1_PCOUT(4),
PCOUT(5) => R1IN_4_1_PCOUT(5),
PCOUT(6) => R1IN_4_1_PCOUT(6),
PCOUT(7) => R1IN_4_1_PCOUT(7),
PCOUT(8) => R1IN_4_1_PCOUT(8),
PCOUT(9) => R1IN_4_1_PCOUT(9),
PCOUT(10) => R1IN_4_1_PCOUT(10),
PCOUT(11) => R1IN_4_1_PCOUT(11),
PCOUT(12) => R1IN_4_1_PCOUT(12),
PCOUT(13) => R1IN_4_1_PCOUT(13),
PCOUT(14) => R1IN_4_1_PCOUT(14),
PCOUT(15) => R1IN_4_1_PCOUT(15),
PCOUT(16) => R1IN_4_1_PCOUT(16),
PCOUT(17) => R1IN_4_1_PCOUT(17),
PCOUT(18) => R1IN_4_1_PCOUT(18),
PCOUT(19) => R1IN_4_1_PCOUT(19),
PCOUT(20) => R1IN_4_1_PCOUT(20),
PCOUT(21) => R1IN_4_1_PCOUT(21),
PCOUT(22) => R1IN_4_1_PCOUT(22),
PCOUT(23) => R1IN_4_1_PCOUT(23),
PCOUT(24) => R1IN_4_1_PCOUT(24),
PCOUT(25) => R1IN_4_1_PCOUT(25),
PCOUT(26) => R1IN_4_1_PCOUT(26),
PCOUT(27) => R1IN_4_1_PCOUT(27),
PCOUT(28) => R1IN_4_1_PCOUT(28),
PCOUT(29) => R1IN_4_1_PCOUT(29),
PCOUT(30) => R1IN_4_1_PCOUT(30),
PCOUT(31) => R1IN_4_1_PCOUT(31),
PCOUT(32) => R1IN_4_1_PCOUT(32),
PCOUT(33) => R1IN_4_1_PCOUT(33),
PCOUT(34) => R1IN_4_1_PCOUT(34),
PCOUT(35) => R1IN_4_1_PCOUT(35),
PCOUT(36) => R1IN_4_1_PCOUT(36),
PCOUT(37) => R1IN_4_1_PCOUT(37),
PCOUT(38) => R1IN_4_1_PCOUT(38),
PCOUT(39) => R1IN_4_1_PCOUT(39),
PCOUT(40) => R1IN_4_1_PCOUT(40),
PCOUT(41) => R1IN_4_1_PCOUT(41),
PCOUT(42) => R1IN_4_1_PCOUT(42),
PCOUT(43) => R1IN_4_1_PCOUT(43),
PCOUT(44) => R1IN_4_1_PCOUT(44),
PCOUT(45) => R1IN_4_1_PCOUT(45),
PCOUT(46) => R1IN_4_1_PCOUT(46),
PCOUT(47) => R1IN_4_1_PCOUT(47));
R1IN_3_1q330w: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 0,
MREG => 1,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18S"
)
port map (
A(0) => B(17),
A(1) => B(18),
A(2) => B(19),
A(3) => B(20),
A(4) => B(21),
A(5) => B(22),
A(6) => B(23),
A(7) => B(24),
A(8) => B(25),
A(9) => B(26),
A(10) => B(27),
A(11) => B(28),
A(12) => B(29),
A(13) => B(30),
A(14) => B(31),
A(15) => B(32),
A(16) => B(33),
A(17) => NN_1,
B(0) => A(0),
B(1) => A(1),
B(2) => A(2),
B(3) => A(3),
B(4) => A(4),
B(5) => A(5),
B(6) => A(6),
B(7) => A(7),
B(8) => A(8),
B(9) => A(9),
B(10) => A(10),
B(11) => A(11),
B(12) => A(12),
B(13) => A(13),
B(14) => A(14),
B(15) => A(15),
B(16) => A(16),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => NN_1,
CEM => EN,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_3_1_BCOUT(0),
BCOUT(1) => R1IN_3_1_BCOUT(1),
BCOUT(2) => R1IN_3_1_BCOUT(2),
BCOUT(3) => R1IN_3_1_BCOUT(3),
BCOUT(4) => R1IN_3_1_BCOUT(4),
BCOUT(5) => R1IN_3_1_BCOUT(5),
BCOUT(6) => R1IN_3_1_BCOUT(6),
BCOUT(7) => R1IN_3_1_BCOUT(7),
BCOUT(8) => R1IN_3_1_BCOUT(8),
BCOUT(9) => R1IN_3_1_BCOUT(9),
BCOUT(10) => R1IN_3_1_BCOUT(10),
BCOUT(11) => R1IN_3_1_BCOUT(11),
BCOUT(12) => R1IN_3_1_BCOUT(12),
BCOUT(13) => R1IN_3_1_BCOUT(13),
BCOUT(14) => R1IN_3_1_BCOUT(14),
BCOUT(15) => R1IN_3_1_BCOUT(15),
BCOUT(16) => R1IN_3_1_BCOUT(16),
BCOUT(17) => R1IN_3_1_BCOUT(17),
P(0) => R1IN_3F(0),
P(1) => R1IN_3F(1),
P(2) => R1IN_3F(2),
P(3) => R1IN_3F(3),
P(4) => R1IN_3F(4),
P(5) => R1IN_3F(5),
P(6) => R1IN_3F(6),
P(7) => R1IN_3F(7),
P(8) => R1IN_3F(8),
P(9) => R1IN_3F(9),
P(10) => R1IN_3F(10),
P(11) => R1IN_3F(11),
P(12) => R1IN_3F(12),
P(13) => R1IN_3F(13),
P(14) => R1IN_3F(14),
P(15) => R1IN_3F(15),
P(16) => R1IN_3F(16),
P(17) => R1IN_3_1F(17),
P(18) => R1IN_3_1F(18),
P(19) => R1IN_3_1F(19),
P(20) => R1IN_3_1F(20),
P(21) => R1IN_3_1F(21),
P(22) => R1IN_3_1F(22),
P(23) => R1IN_3_1F(23),
P(24) => R1IN_3_1F(24),
P(25) => R1IN_3_1F(25),
P(26) => R1IN_3_1F(26),
P(27) => R1IN_3_1F(27),
P(28) => R1IN_3_1F(28),
P(29) => R1IN_3_1F(29),
P(30) => R1IN_3_1F(30),
P(31) => R1IN_3_1F(31),
P(32) => R1IN_3_1F(32),
P(33) => R1IN_3_1F(33),
P(34) => UC_208,
P(35) => UC_209,
P(36) => UC_210,
P(37) => UC_211,
P(38) => UC_212,
P(39) => UC_213,
P(40) => UC_214,
P(41) => UC_215,
P(42) => UC_216,
P(43) => UC_217,
P(44) => UC_218,
P(45) => UC_219,
P(46) => UC_220,
P(47) => UC_221,
PCOUT(0) => R1IN_3_1_PCOUT(0),
PCOUT(1) => R1IN_3_1_PCOUT(1),
PCOUT(2) => R1IN_3_1_PCOUT(2),
PCOUT(3) => R1IN_3_1_PCOUT(3),
PCOUT(4) => R1IN_3_1_PCOUT(4),
PCOUT(5) => R1IN_3_1_PCOUT(5),
PCOUT(6) => R1IN_3_1_PCOUT(6),
PCOUT(7) => R1IN_3_1_PCOUT(7),
PCOUT(8) => R1IN_3_1_PCOUT(8),
PCOUT(9) => R1IN_3_1_PCOUT(9),
PCOUT(10) => R1IN_3_1_PCOUT(10),
PCOUT(11) => R1IN_3_1_PCOUT(11),
PCOUT(12) => R1IN_3_1_PCOUT(12),
PCOUT(13) => R1IN_3_1_PCOUT(13),
PCOUT(14) => R1IN_3_1_PCOUT(14),
PCOUT(15) => R1IN_3_1_PCOUT(15),
PCOUT(16) => R1IN_3_1_PCOUT(16),
PCOUT(17) => R1IN_3_1_PCOUT(17),
PCOUT(18) => R1IN_3_1_PCOUT(18),
PCOUT(19) => R1IN_3_1_PCOUT(19),
PCOUT(20) => R1IN_3_1_PCOUT(20),
PCOUT(21) => R1IN_3_1_PCOUT(21),
PCOUT(22) => R1IN_3_1_PCOUT(22),
PCOUT(23) => R1IN_3_1_PCOUT(23),
PCOUT(24) => R1IN_3_1_PCOUT(24),
PCOUT(25) => R1IN_3_1_PCOUT(25),
PCOUT(26) => R1IN_3_1_PCOUT(26),
PCOUT(27) => R1IN_3_1_PCOUT(27),
PCOUT(28) => R1IN_3_1_PCOUT(28),
PCOUT(29) => R1IN_3_1_PCOUT(29),
PCOUT(30) => R1IN_3_1_PCOUT(30),
PCOUT(31) => R1IN_3_1_PCOUT(31),
PCOUT(32) => R1IN_3_1_PCOUT(32),
PCOUT(33) => R1IN_3_1_PCOUT(33),
PCOUT(34) => R1IN_3_1_PCOUT(34),
PCOUT(35) => R1IN_3_1_PCOUT(35),
PCOUT(36) => R1IN_3_1_PCOUT(36),
PCOUT(37) => R1IN_3_1_PCOUT(37),
PCOUT(38) => R1IN_3_1_PCOUT(38),
PCOUT(39) => R1IN_3_1_PCOUT(39),
PCOUT(40) => R1IN_3_1_PCOUT(40),
PCOUT(41) => R1IN_3_1_PCOUT(41),
PCOUT(42) => R1IN_3_1_PCOUT(42),
PCOUT(43) => R1IN_3_1_PCOUT(43),
PCOUT(44) => R1IN_3_1_PCOUT(44),
PCOUT(45) => R1IN_3_1_PCOUT(45),
PCOUT(46) => R1IN_3_1_PCOUT(46),
PCOUT(47) => R1IN_3_1_PCOUT(47));
R1IN_2_1q330w: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 1,
MREG => 1,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18S"
)
port map (
A(0) => A(17),
A(1) => A(18),
A(2) => A(19),
A(3) => A(20),
A(4) => A(21),
A(5) => A(22),
A(6) => A(23),
A(7) => A(24),
A(8) => A(25),
A(9) => A(26),
A(10) => A(27),
A(11) => A(28),
A(12) => A(29),
A(13) => A(30),
A(14) => A(31),
A(15) => A(32),
A(16) => A(33),
A(17) => NN_1,
B(0) => B(0),
B(1) => B(1),
B(2) => B(2),
B(3) => B(3),
B(4) => B(4),
B(5) => B(5),
B(6) => B(6),
B(7) => B(7),
B(8) => B(8),
B(9) => B(9),
B(10) => B(10),
B(11) => B(11),
B(12) => B(12),
B(13) => B(13),
B(14) => B(14),
B(15) => B(15),
B(16) => B(16),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => EN,
CEM => EN,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => B_0(0),
BCOUT(1) => B_0(1),
BCOUT(2) => B_0(2),
BCOUT(3) => B_0(3),
BCOUT(4) => B_0(4),
BCOUT(5) => B_0(5),
BCOUT(6) => B_0(6),
BCOUT(7) => B_0(7),
BCOUT(8) => B_0(8),
BCOUT(9) => B_0(9),
BCOUT(10) => B_0(10),
BCOUT(11) => B_0(11),
BCOUT(12) => B_0(12),
BCOUT(13) => B_0(13),
BCOUT(14) => B_0(14),
BCOUT(15) => B_0(15),
BCOUT(16) => B_0(16),
BCOUT(17) => GND_0,
P(0) => R1IN_2F_RETO(0),
P(1) => R1IN_2F_RETO(1),
P(2) => R1IN_2F_RETO(2),
P(3) => R1IN_2F_RETO(3),
P(4) => R1IN_2F_RETO(4),
P(5) => R1IN_2F_RETO(5),
P(6) => R1IN_2F_RETO(6),
P(7) => R1IN_2F_RETO(7),
P(8) => R1IN_2F_RETO(8),
P(9) => R1IN_2F_RETO(9),
P(10) => R1IN_2F_RETO(10),
P(11) => R1IN_2F_RETO(11),
P(12) => R1IN_2F_RETO(12),
P(13) => R1IN_2F_RETO(13),
P(14) => R1IN_2F_RETO(14),
P(15) => R1IN_2F_RETO(15),
P(16) => R1IN_2F_RETO(16),
P(17) => R1IN_2_1F_RETO(17),
P(18) => R1IN_2_1F_RETO(18),
P(19) => R1IN_2_1F_RETO(19),
P(20) => R1IN_2_1F_RETO(20),
P(21) => R1IN_2_1F_RETO(21),
P(22) => R1IN_2_1F_RETO(22),
P(23) => R1IN_2_1F_RETO(23),
P(24) => R1IN_2_1F_RETO(24),
P(25) => R1IN_2_1F_RETO(25),
P(26) => R1IN_2_1F_RETO(26),
P(27) => R1IN_2_1F_RETO(27),
P(28) => R1IN_2_1F_RETO(28),
P(29) => R1IN_2_1F_RETO(29),
P(30) => R1IN_2_1F_RETO(30),
P(31) => R1IN_2_1F_RETO(31),
P(32) => R1IN_2_1F_RETO(32),
P(33) => R1IN_2_1F_RETO(33),
P(34) => R1IN_2_1_P(34),
P(35) => R1IN_2_1_P(35),
P(36) => R1IN_2_1_P(36),
P(37) => R1IN_2_1_P(37),
P(38) => R1IN_2_1_P(38),
P(39) => R1IN_2_1_P(39),
P(40) => R1IN_2_1_P(40),
P(41) => R1IN_2_1_P(41),
P(42) => R1IN_2_1_P(42),
P(43) => R1IN_2_1_P(43),
P(44) => R1IN_2_1_P(44),
P(45) => R1IN_2_1_P(45),
P(46) => R1IN_2_1_P(46),
P(47) => R1IN_2_1_P(47),
PCOUT(0) => R1IN_2_1_PCOUT(0),
PCOUT(1) => R1IN_2_1_PCOUT(1),
PCOUT(2) => R1IN_2_1_PCOUT(2),
PCOUT(3) => R1IN_2_1_PCOUT(3),
PCOUT(4) => R1IN_2_1_PCOUT(4),
PCOUT(5) => R1IN_2_1_PCOUT(5),
PCOUT(6) => R1IN_2_1_PCOUT(6),
PCOUT(7) => R1IN_2_1_PCOUT(7),
PCOUT(8) => R1IN_2_1_PCOUT(8),
PCOUT(9) => R1IN_2_1_PCOUT(9),
PCOUT(10) => R1IN_2_1_PCOUT(10),
PCOUT(11) => R1IN_2_1_PCOUT(11),
PCOUT(12) => R1IN_2_1_PCOUT(12),
PCOUT(13) => R1IN_2_1_PCOUT(13),
PCOUT(14) => R1IN_2_1_PCOUT(14),
PCOUT(15) => R1IN_2_1_PCOUT(15),
PCOUT(16) => R1IN_2_1_PCOUT(16),
PCOUT(17) => R1IN_2_1_PCOUT(17),
PCOUT(18) => R1IN_2_1_PCOUT(18),
PCOUT(19) => R1IN_2_1_PCOUT(19),
PCOUT(20) => R1IN_2_1_PCOUT(20),
PCOUT(21) => R1IN_2_1_PCOUT(21),
PCOUT(22) => R1IN_2_1_PCOUT(22),
PCOUT(23) => R1IN_2_1_PCOUT(23),
PCOUT(24) => R1IN_2_1_PCOUT(24),
PCOUT(25) => R1IN_2_1_PCOUT(25),
PCOUT(26) => R1IN_2_1_PCOUT(26),
PCOUT(27) => R1IN_2_1_PCOUT(27),
PCOUT(28) => R1IN_2_1_PCOUT(28),
PCOUT(29) => R1IN_2_1_PCOUT(29),
PCOUT(30) => R1IN_2_1_PCOUT(30),
PCOUT(31) => R1IN_2_1_PCOUT(31),
PCOUT(32) => R1IN_2_1_PCOUT(32),
PCOUT(33) => R1IN_2_1_PCOUT(33),
PCOUT(34) => R1IN_2_1_PCOUT(34),
PCOUT(35) => R1IN_2_1_PCOUT(35),
PCOUT(36) => R1IN_2_1_PCOUT(36),
PCOUT(37) => R1IN_2_1_PCOUT(37),
PCOUT(38) => R1IN_2_1_PCOUT(38),
PCOUT(39) => R1IN_2_1_PCOUT(39),
PCOUT(40) => R1IN_2_1_PCOUT(40),
PCOUT(41) => R1IN_2_1_PCOUT(41),
PCOUT(42) => R1IN_2_1_PCOUT(42),
PCOUT(43) => R1IN_2_1_PCOUT(43),
PCOUT(44) => R1IN_2_1_PCOUT(44),
PCOUT(45) => R1IN_2_1_PCOUT(45),
PCOUT(46) => R1IN_2_1_PCOUT(46),
PCOUT(47) => R1IN_2_1_PCOUT(47));
R1IN_1q330w: DSP48
generic map(
AREG => 1,
BREG => 1,
CREG => 0,
PREG => 1,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "CASCADE",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => A(0),
A(1) => A(1),
A(2) => A(2),
A(3) => A(3),
A(4) => A(4),
A(5) => A(5),
A(6) => A(6),
A(7) => A(7),
A(8) => A(8),
A(9) => A(9),
A(10) => A(10),
A(11) => A(11),
A(12) => A(12),
A(13) => A(13),
A(14) => A(14),
A(15) => A(15),
A(16) => A(16),
A(17) => NN_1,
B(0) => NN_1,
B(1) => NN_1,
B(2) => NN_1,
B(3) => NN_1,
B(4) => NN_1,
B(5) => NN_1,
B(6) => NN_1,
B(7) => NN_1,
B(8) => NN_1,
B(9) => NN_1,
B(10) => NN_1,
B(11) => NN_1,
B(12) => NN_1,
B(13) => NN_1,
B(14) => NN_1,
B(15) => NN_1,
B(16) => NN_1,
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => B_0(0),
BCIN(1) => B_0(1),
BCIN(2) => B_0(2),
BCIN(3) => B_0(3),
BCIN(4) => B_0(4),
BCIN(5) => B_0(5),
BCIN(6) => B_0(6),
BCIN(7) => B_0(7),
BCIN(8) => B_0(8),
BCIN(9) => B_0(9),
BCIN(10) => B_0(10),
BCIN(11) => B_0(11),
BCIN(12) => B_0(12),
BCIN(13) => B_0(13),
BCIN(14) => B_0(14),
BCIN(15) => B_0(15),
BCIN(16) => B_0(16),
BCIN(17) => GND_0,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => EN,
CEB => EN,
CEC => NN_1,
CEP => EN,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_1_BCOUT(0),
BCOUT(1) => R1IN_1_BCOUT(1),
BCOUT(2) => R1IN_1_BCOUT(2),
BCOUT(3) => R1IN_1_BCOUT(3),
BCOUT(4) => R1IN_1_BCOUT(4),
BCOUT(5) => R1IN_1_BCOUT(5),
BCOUT(6) => R1IN_1_BCOUT(6),
BCOUT(7) => R1IN_1_BCOUT(7),
BCOUT(8) => R1IN_1_BCOUT(8),
BCOUT(9) => R1IN_1_BCOUT(9),
BCOUT(10) => R1IN_1_BCOUT(10),
BCOUT(11) => R1IN_1_BCOUT(11),
BCOUT(12) => R1IN_1_BCOUT(12),
BCOUT(13) => R1IN_1_BCOUT(13),
BCOUT(14) => R1IN_1_BCOUT(14),
BCOUT(15) => R1IN_1_BCOUT(15),
BCOUT(16) => R1IN_1_BCOUT(16),
BCOUT(17) => R1IN_1_BCOUT(17),
P(0) => PRODUCT(0),
P(1) => PRODUCT(1),
P(2) => PRODUCT(2),
P(3) => PRODUCT(3),
P(4) => PRODUCT(4),
P(5) => PRODUCT(5),
P(6) => PRODUCT(6),
P(7) => PRODUCT(7),
P(8) => PRODUCT(8),
P(9) => PRODUCT(9),
P(10) => PRODUCT(10),
P(11) => PRODUCT(11),
P(12) => PRODUCT(12),
P(13) => PRODUCT(13),
P(14) => PRODUCT(14),
P(15) => PRODUCT(15),
P(16) => PRODUCT(16),
P(17) => R1IN_ADD_2,
P(18) => R1IN_1FF(18),
P(19) => R1IN_1FF(19),
P(20) => R1IN_1FF(20),
P(21) => R1IN_1FF(21),
P(22) => R1IN_1FF(22),
P(23) => R1IN_1FF(23),
P(24) => R1IN_1FF(24),
P(25) => R1IN_1FF(25),
P(26) => R1IN_1FF(26),
P(27) => R1IN_1FF(27),
P(28) => R1IN_1FF(28),
P(29) => R1IN_1FF(29),
P(30) => R1IN_1FF(30),
P(31) => R1IN_1FF(31),
P(32) => R1IN_1FF(32),
P(33) => R1IN_1FF(33),
P(34) => UC_180,
P(35) => UC_181,
P(36) => UC_182,
P(37) => UC_183,
P(38) => UC_184,
P(39) => UC_185,
P(40) => UC_186,
P(41) => UC_187,
P(42) => UC_188,
P(43) => UC_189,
P(44) => UC_190,
P(45) => UC_191,
P(46) => UC_192,
P(47) => UC_193,
PCOUT(0) => R1IN_1_PCOUT(0),
PCOUT(1) => R1IN_1_PCOUT(1),
PCOUT(2) => R1IN_1_PCOUT(2),
PCOUT(3) => R1IN_1_PCOUT(3),
PCOUT(4) => R1IN_1_PCOUT(4),
PCOUT(5) => R1IN_1_PCOUT(5),
PCOUT(6) => R1IN_1_PCOUT(6),
PCOUT(7) => R1IN_1_PCOUT(7),
PCOUT(8) => R1IN_1_PCOUT(8),
PCOUT(9) => R1IN_1_PCOUT(9),
PCOUT(10) => R1IN_1_PCOUT(10),
PCOUT(11) => R1IN_1_PCOUT(11),
PCOUT(12) => R1IN_1_PCOUT(12),
PCOUT(13) => R1IN_1_PCOUT(13),
PCOUT(14) => R1IN_1_PCOUT(14),
PCOUT(15) => R1IN_1_PCOUT(15),
PCOUT(16) => R1IN_1_PCOUT(16),
PCOUT(17) => R1IN_1_PCOUT(17),
PCOUT(18) => R1IN_1_PCOUT(18),
PCOUT(19) => R1IN_1_PCOUT(19),
PCOUT(20) => R1IN_1_PCOUT(20),
PCOUT(21) => R1IN_1_PCOUT(21),
PCOUT(22) => R1IN_1_PCOUT(22),
PCOUT(23) => R1IN_1_PCOUT(23),
PCOUT(24) => R1IN_1_PCOUT(24),
PCOUT(25) => R1IN_1_PCOUT(25),
PCOUT(26) => R1IN_1_PCOUT(26),
PCOUT(27) => R1IN_1_PCOUT(27),
PCOUT(28) => R1IN_1_PCOUT(28),
PCOUT(29) => R1IN_1_PCOUT(29),
PCOUT(30) => R1IN_1_PCOUT(30),
PCOUT(31) => R1IN_1_PCOUT(31),
PCOUT(32) => R1IN_1_PCOUT(32),
PCOUT(33) => R1IN_1_PCOUT(33),
PCOUT(34) => R1IN_1_PCOUT(34),
PCOUT(35) => R1IN_1_PCOUT(35),
PCOUT(36) => R1IN_1_PCOUT(36),
PCOUT(37) => R1IN_1_PCOUT(37),
PCOUT(38) => R1IN_1_PCOUT(38),
PCOUT(39) => R1IN_1_PCOUT(39),
PCOUT(40) => R1IN_1_PCOUT(40),
PCOUT(41) => R1IN_1_PCOUT(41),
PCOUT(42) => R1IN_1_PCOUT(42),
PCOUT(43) => R1IN_1_PCOUT(43),
PCOUT(44) => R1IN_1_PCOUT(44),
PCOUT(45) => R1IN_1_PCOUT(45),
PCOUT(46) => R1IN_1_PCOUT(46),
PCOUT(47) => R1IN_1_PCOUT(47));
R1IN_4_3_1q330w: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 0,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => B(34),
A(1) => B(35),
A(2) => B(36),
A(3) => B(37),
A(4) => B(38),
A(5) => B(39),
A(6) => B(40),
A(7) => B(41),
A(8) => B(42),
A(9) => B(43),
A(10) => B(44),
A(11) => B(45),
A(12) => B(46),
A(13) => B(47),
A(14) => B(48),
A(15) => B(49),
A(16) => B(50),
A(17) => NN_1,
B(0) => A(17),
B(1) => A(18),
B(2) => A(19),
B(3) => A(20),
B(4) => A(21),
B(5) => A(22),
B(6) => A(23),
B(7) => A(24),
B(8) => A(25),
B(9) => A(26),
B(10) => A(27),
B(11) => A(28),
B(12) => A(29),
B(13) => A(30),
B(14) => A(31),
B(15) => A(32),
B(16) => A(33),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => NN_1,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => NN_1,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_4_3_1_BCOUT(0),
BCOUT(1) => R1IN_4_3_1_BCOUT(1),
BCOUT(2) => R1IN_4_3_1_BCOUT(2),
BCOUT(3) => R1IN_4_3_1_BCOUT(3),
BCOUT(4) => R1IN_4_3_1_BCOUT(4),
BCOUT(5) => R1IN_4_3_1_BCOUT(5),
BCOUT(6) => R1IN_4_3_1_BCOUT(6),
BCOUT(7) => R1IN_4_3_1_BCOUT(7),
BCOUT(8) => R1IN_4_3_1_BCOUT(8),
BCOUT(9) => R1IN_4_3_1_BCOUT(9),
BCOUT(10) => R1IN_4_3_1_BCOUT(10),
BCOUT(11) => R1IN_4_3_1_BCOUT(11),
BCOUT(12) => R1IN_4_3_1_BCOUT(12),
BCOUT(13) => R1IN_4_3_1_BCOUT(13),
BCOUT(14) => R1IN_4_3_1_BCOUT(14),
BCOUT(15) => R1IN_4_3_1_BCOUT(15),
BCOUT(16) => R1IN_4_3_1_BCOUT(16),
BCOUT(17) => R1IN_4_3_1_BCOUT(17),
P(0) => R1IN_4_3(0),
P(1) => R1IN_4_3(1),
P(2) => R1IN_4_3(2),
P(3) => R1IN_4_3(3),
P(4) => R1IN_4_3(4),
P(5) => R1IN_4_3(5),
P(6) => R1IN_4_3(6),
P(7) => R1IN_4_3(7),
P(8) => R1IN_4_3(8),
P(9) => R1IN_4_3(9),
P(10) => R1IN_4_3(10),
P(11) => R1IN_4_3(11),
P(12) => R1IN_4_3(12),
P(13) => R1IN_4_3(13),
P(14) => R1IN_4_3(14),
P(15) => R1IN_4_3(15),
P(16) => R1IN_4_3(16),
P(17) => R1IN_4_3_1(17),
P(18) => R1IN_4_3_1(18),
P(19) => R1IN_4_3_1(19),
P(20) => R1IN_4_3_1(20),
P(21) => R1IN_4_3_1(21),
P(22) => R1IN_4_3_1(22),
P(23) => R1IN_4_3_1(23),
P(24) => R1IN_4_3_1(24),
P(25) => R1IN_4_3_1(25),
P(26) => R1IN_4_3_1(26),
P(27) => R1IN_4_3_1(27),
P(28) => R1IN_4_3_1(28),
P(29) => R1IN_4_3_1(29),
P(30) => R1IN_4_3_1(30),
P(31) => R1IN_4_3_1(31),
P(32) => R1IN_4_3_1(32),
P(33) => R1IN_4_3_1(33),
P(34) => UC_166,
P(35) => UC_167,
P(36) => UC_168,
P(37) => UC_169,
P(38) => UC_170,
P(39) => UC_171,
P(40) => UC_172,
P(41) => UC_173,
P(42) => UC_174,
P(43) => UC_175,
P(44) => UC_176,
P(45) => UC_177,
P(46) => UC_178,
P(47) => UC_179,
PCOUT(0) => R1IN_4_3_0(0),
PCOUT(1) => R1IN_4_3_0(1),
PCOUT(2) => R1IN_4_3_0(2),
PCOUT(3) => R1IN_4_3_0(3),
PCOUT(4) => R1IN_4_3_0(4),
PCOUT(5) => R1IN_4_3_0(5),
PCOUT(6) => R1IN_4_3_0(6),
PCOUT(7) => R1IN_4_3_0(7),
PCOUT(8) => R1IN_4_3_0(8),
PCOUT(9) => R1IN_4_3_0(9),
PCOUT(10) => R1IN_4_3_0(10),
PCOUT(11) => R1IN_4_3_0(11),
PCOUT(12) => R1IN_4_3_0(12),
PCOUT(13) => R1IN_4_3_0(13),
PCOUT(14) => R1IN_4_3_0(14),
PCOUT(15) => R1IN_4_3_0(15),
PCOUT(16) => R1IN_4_3_0(16),
PCOUT(17) => R1IN_4_3_1_0(17),
PCOUT(18) => R1IN_4_3_1_0(18),
PCOUT(19) => R1IN_4_3_1_0(19),
PCOUT(20) => R1IN_4_3_1_0(20),
PCOUT(21) => R1IN_4_3_1_0(21),
PCOUT(22) => R1IN_4_3_1_0(22),
PCOUT(23) => R1IN_4_3_1_0(23),
PCOUT(24) => R1IN_4_3_1_0(24),
PCOUT(25) => R1IN_4_3_1_0(25),
PCOUT(26) => R1IN_4_3_1_0(26),
PCOUT(27) => R1IN_4_3_1_0(27),
PCOUT(28) => R1IN_4_3_1_0(28),
PCOUT(29) => R1IN_4_3_1_0(29),
PCOUT(30) => R1IN_4_3_1_0(30),
PCOUT(31) => R1IN_4_3_1_0(31),
PCOUT(32) => R1IN_4_3_1_0(32),
PCOUT(33) => R1IN_4_3_1_0(33),
PCOUT(34) => UC_166_0,
PCOUT(35) => UC_167_0,
PCOUT(36) => UC_168_0,
PCOUT(37) => UC_169_0,
PCOUT(38) => UC_170_0,
PCOUT(39) => UC_171_0,
PCOUT(40) => UC_172_0,
PCOUT(41) => UC_173_0,
PCOUT(42) => UC_174_0,
PCOUT(43) => UC_175_0,
PCOUT(44) => UC_176_0,
PCOUT(45) => UC_177_0,
PCOUT(46) => UC_178_0,
PCOUT(47) => UC_179_0);
R1IN_4_2_1q330w: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 0,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => A(34),
A(1) => A(35),
A(2) => A(36),
A(3) => A(37),
A(4) => A(38),
A(5) => A(39),
A(6) => A(40),
A(7) => A(41),
A(8) => A(42),
A(9) => A(43),
A(10) => A(44),
A(11) => A(45),
A(12) => A(46),
A(13) => A(47),
A(14) => A(48),
A(15) => A(49),
A(16) => A(50),
A(17) => NN_1,
B(0) => B(17),
B(1) => B(18),
B(2) => B(19),
B(3) => B(20),
B(4) => B(21),
B(5) => B(22),
B(6) => B(23),
B(7) => B(24),
B(8) => B(25),
B(9) => B(26),
B(10) => B(27),
B(11) => B(28),
B(12) => B(29),
B(13) => B(30),
B(14) => B(31),
B(15) => B(32),
B(16) => B(33),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => NN_1,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => NN_1,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_4_2_1_BCOUT(0),
BCOUT(1) => R1IN_4_2_1_BCOUT(1),
BCOUT(2) => R1IN_4_2_1_BCOUT(2),
BCOUT(3) => R1IN_4_2_1_BCOUT(3),
BCOUT(4) => R1IN_4_2_1_BCOUT(4),
BCOUT(5) => R1IN_4_2_1_BCOUT(5),
BCOUT(6) => R1IN_4_2_1_BCOUT(6),
BCOUT(7) => R1IN_4_2_1_BCOUT(7),
BCOUT(8) => R1IN_4_2_1_BCOUT(8),
BCOUT(9) => R1IN_4_2_1_BCOUT(9),
BCOUT(10) => R1IN_4_2_1_BCOUT(10),
BCOUT(11) => R1IN_4_2_1_BCOUT(11),
BCOUT(12) => R1IN_4_2_1_BCOUT(12),
BCOUT(13) => R1IN_4_2_1_BCOUT(13),
BCOUT(14) => R1IN_4_2_1_BCOUT(14),
BCOUT(15) => R1IN_4_2_1_BCOUT(15),
BCOUT(16) => R1IN_4_2_1_BCOUT(16),
BCOUT(17) => R1IN_4_2_1_BCOUT(17),
P(0) => R1IN_4_2(0),
P(1) => R1IN_4_2(1),
P(2) => R1IN_4_2(2),
P(3) => R1IN_4_2(3),
P(4) => R1IN_4_2(4),
P(5) => R1IN_4_2(5),
P(6) => R1IN_4_2(6),
P(7) => R1IN_4_2(7),
P(8) => R1IN_4_2(8),
P(9) => R1IN_4_2(9),
P(10) => R1IN_4_2(10),
P(11) => R1IN_4_2(11),
P(12) => R1IN_4_2(12),
P(13) => R1IN_4_2(13),
P(14) => R1IN_4_2(14),
P(15) => R1IN_4_2(15),
P(16) => R1IN_4_2(16),
P(17) => R1IN_4_2_1(17),
P(18) => R1IN_4_2_1(18),
P(19) => R1IN_4_2_1(19),
P(20) => R1IN_4_2_1(20),
P(21) => R1IN_4_2_1(21),
P(22) => R1IN_4_2_1(22),
P(23) => R1IN_4_2_1(23),
P(24) => R1IN_4_2_1(24),
P(25) => R1IN_4_2_1(25),
P(26) => R1IN_4_2_1(26),
P(27) => R1IN_4_2_1(27),
P(28) => R1IN_4_2_1(28),
P(29) => R1IN_4_2_1(29),
P(30) => R1IN_4_2_1(30),
P(31) => R1IN_4_2_1(31),
P(32) => R1IN_4_2_1(32),
P(33) => R1IN_4_2_1(33),
P(34) => UC_152,
P(35) => UC_153,
P(36) => UC_154,
P(37) => UC_155,
P(38) => UC_156,
P(39) => UC_157,
P(40) => UC_158,
P(41) => UC_159,
P(42) => UC_160,
P(43) => UC_161,
P(44) => UC_162,
P(45) => UC_163,
P(46) => UC_164,
P(47) => UC_165,
PCOUT(0) => R1IN_4_2_0(0),
PCOUT(1) => R1IN_4_2_0(1),
PCOUT(2) => R1IN_4_2_0(2),
PCOUT(3) => R1IN_4_2_0(3),
PCOUT(4) => R1IN_4_2_0(4),
PCOUT(5) => R1IN_4_2_0(5),
PCOUT(6) => R1IN_4_2_0(6),
PCOUT(7) => R1IN_4_2_0(7),
PCOUT(8) => R1IN_4_2_0(8),
PCOUT(9) => R1IN_4_2_0(9),
PCOUT(10) => R1IN_4_2_0(10),
PCOUT(11) => R1IN_4_2_0(11),
PCOUT(12) => R1IN_4_2_0(12),
PCOUT(13) => R1IN_4_2_0(13),
PCOUT(14) => R1IN_4_2_0(14),
PCOUT(15) => R1IN_4_2_0(15),
PCOUT(16) => R1IN_4_2_0(16),
PCOUT(17) => R1IN_4_2_1_0(17),
PCOUT(18) => R1IN_4_2_1_0(18),
PCOUT(19) => R1IN_4_2_1_0(19),
PCOUT(20) => R1IN_4_2_1_0(20),
PCOUT(21) => R1IN_4_2_1_0(21),
PCOUT(22) => R1IN_4_2_1_0(22),
PCOUT(23) => R1IN_4_2_1_0(23),
PCOUT(24) => R1IN_4_2_1_0(24),
PCOUT(25) => R1IN_4_2_1_0(25),
PCOUT(26) => R1IN_4_2_1_0(26),
PCOUT(27) => R1IN_4_2_1_0(27),
PCOUT(28) => R1IN_4_2_1_0(28),
PCOUT(29) => R1IN_4_2_1_0(29),
PCOUT(30) => R1IN_4_2_1_0(30),
PCOUT(31) => R1IN_4_2_1_0(31),
PCOUT(32) => R1IN_4_2_1_0(32),
PCOUT(33) => R1IN_4_2_1_0(33),
PCOUT(34) => UC_152_0,
PCOUT(35) => UC_153_0,
PCOUT(36) => UC_154_0,
PCOUT(37) => UC_155_0,
PCOUT(38) => UC_156_0,
PCOUT(39) => UC_157_0,
PCOUT(40) => UC_158_0,
PCOUT(41) => UC_159_0,
PCOUT(42) => UC_160_0,
PCOUT(43) => UC_161_0,
PCOUT(44) => UC_162_0,
PCOUT(45) => UC_163_0,
PCOUT(46) => UC_164_0,
PCOUT(47) => UC_165_0);
R1IN_3_2_1q330w: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 0,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => B(34),
A(1) => B(35),
A(2) => B(36),
A(3) => B(37),
A(4) => B(38),
A(5) => B(39),
A(6) => B(40),
A(7) => B(41),
A(8) => B(42),
A(9) => B(43),
A(10) => B(44),
A(11) => B(45),
A(12) => B(46),
A(13) => B(47),
A(14) => B(48),
A(15) => B(49),
A(16) => B(50),
A(17) => NN_1,
B(0) => A(0),
B(1) => A(1),
B(2) => A(2),
B(3) => A(3),
B(4) => A(4),
B(5) => A(5),
B(6) => A(6),
B(7) => A(7),
B(8) => A(8),
B(9) => A(9),
B(10) => A(10),
B(11) => A(11),
B(12) => A(12),
B(13) => A(13),
B(14) => A(14),
B(15) => A(15),
B(16) => A(16),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => NN_1,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => NN_1,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_3_2_1_BCOUT(0),
BCOUT(1) => R1IN_3_2_1_BCOUT(1),
BCOUT(2) => R1IN_3_2_1_BCOUT(2),
BCOUT(3) => R1IN_3_2_1_BCOUT(3),
BCOUT(4) => R1IN_3_2_1_BCOUT(4),
BCOUT(5) => R1IN_3_2_1_BCOUT(5),
BCOUT(6) => R1IN_3_2_1_BCOUT(6),
BCOUT(7) => R1IN_3_2_1_BCOUT(7),
BCOUT(8) => R1IN_3_2_1_BCOUT(8),
BCOUT(9) => R1IN_3_2_1_BCOUT(9),
BCOUT(10) => R1IN_3_2_1_BCOUT(10),
BCOUT(11) => R1IN_3_2_1_BCOUT(11),
BCOUT(12) => R1IN_3_2_1_BCOUT(12),
BCOUT(13) => R1IN_3_2_1_BCOUT(13),
BCOUT(14) => R1IN_3_2_1_BCOUT(14),
BCOUT(15) => R1IN_3_2_1_BCOUT(15),
BCOUT(16) => R1IN_3_2_1_BCOUT(16),
BCOUT(17) => R1IN_3_2_1_BCOUT(17),
P(0) => R1IN_3_2(0),
P(1) => R1IN_3_2(1),
P(2) => R1IN_3_2(2),
P(3) => R1IN_3_2(3),
P(4) => R1IN_3_2(4),
P(5) => R1IN_3_2(5),
P(6) => R1IN_3_2(6),
P(7) => R1IN_3_2(7),
P(8) => R1IN_3_2(8),
P(9) => R1IN_3_2(9),
P(10) => R1IN_3_2(10),
P(11) => R1IN_3_2(11),
P(12) => R1IN_3_2(12),
P(13) => R1IN_3_2(13),
P(14) => R1IN_3_2(14),
P(15) => R1IN_3_2(15),
P(16) => R1IN_3_2(16),
P(17) => R1IN_3_2_1(17),
P(18) => R1IN_3_2_1(18),
P(19) => R1IN_3_2_1(19),
P(20) => R1IN_3_2_1(20),
P(21) => R1IN_3_2_1(21),
P(22) => R1IN_3_2_1(22),
P(23) => R1IN_3_2_1(23),
P(24) => R1IN_3_2_1(24),
P(25) => R1IN_3_2_1(25),
P(26) => R1IN_3_2_1(26),
P(27) => R1IN_3_2_1(27),
P(28) => R1IN_3_2_1(28),
P(29) => R1IN_3_2_1(29),
P(30) => R1IN_3_2_1(30),
P(31) => R1IN_3_2_1(31),
P(32) => R1IN_3_2_1(32),
P(33) => R1IN_3_2_1(33),
P(34) => UC_138,
P(35) => UC_139,
P(36) => UC_140,
P(37) => UC_141,
P(38) => UC_142,
P(39) => UC_143,
P(40) => UC_144,
P(41) => UC_145,
P(42) => UC_146,
P(43) => UC_147,
P(44) => UC_148,
P(45) => UC_149,
P(46) => UC_150,
P(47) => UC_151,
PCOUT(0) => R1IN_3_2_0(0),
PCOUT(1) => R1IN_3_2_0(1),
PCOUT(2) => R1IN_3_2_0(2),
PCOUT(3) => R1IN_3_2_0(3),
PCOUT(4) => R1IN_3_2_0(4),
PCOUT(5) => R1IN_3_2_0(5),
PCOUT(6) => R1IN_3_2_0(6),
PCOUT(7) => R1IN_3_2_0(7),
PCOUT(8) => R1IN_3_2_0(8),
PCOUT(9) => R1IN_3_2_0(9),
PCOUT(10) => R1IN_3_2_0(10),
PCOUT(11) => R1IN_3_2_0(11),
PCOUT(12) => R1IN_3_2_0(12),
PCOUT(13) => R1IN_3_2_0(13),
PCOUT(14) => R1IN_3_2_0(14),
PCOUT(15) => R1IN_3_2_0(15),
PCOUT(16) => R1IN_3_2_0(16),
PCOUT(17) => R1IN_3_2_1_0(17),
PCOUT(18) => R1IN_3_2_1_0(18),
PCOUT(19) => R1IN_3_2_1_0(19),
PCOUT(20) => R1IN_3_2_1_0(20),
PCOUT(21) => R1IN_3_2_1_0(21),
PCOUT(22) => R1IN_3_2_1_0(22),
PCOUT(23) => R1IN_3_2_1_0(23),
PCOUT(24) => R1IN_3_2_1_0(24),
PCOUT(25) => R1IN_3_2_1_0(25),
PCOUT(26) => R1IN_3_2_1_0(26),
PCOUT(27) => R1IN_3_2_1_0(27),
PCOUT(28) => R1IN_3_2_1_0(28),
PCOUT(29) => R1IN_3_2_1_0(29),
PCOUT(30) => R1IN_3_2_1_0(30),
PCOUT(31) => R1IN_3_2_1_0(31),
PCOUT(32) => R1IN_3_2_1_0(32),
PCOUT(33) => R1IN_3_2_1_0(33),
PCOUT(34) => UC_138_0,
PCOUT(35) => UC_139_0,
PCOUT(36) => UC_140_0,
PCOUT(37) => UC_141_0,
PCOUT(38) => UC_142_0,
PCOUT(39) => UC_143_0,
PCOUT(40) => UC_144_0,
PCOUT(41) => UC_145_0,
PCOUT(42) => UC_146_0,
PCOUT(43) => UC_147_0,
PCOUT(44) => UC_148_0,
PCOUT(45) => UC_149_0,
PCOUT(46) => UC_150_0,
PCOUT(47) => UC_151_0);
R1IN_2_2_1q330w: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 0,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => A(34),
A(1) => A(35),
A(2) => A(36),
A(3) => A(37),
A(4) => A(38),
A(5) => A(39),
A(6) => A(40),
A(7) => A(41),
A(8) => A(42),
A(9) => A(43),
A(10) => A(44),
A(11) => A(45),
A(12) => A(46),
A(13) => A(47),
A(14) => A(48),
A(15) => A(49),
A(16) => A(50),
A(17) => NN_1,
B(0) => B(0),
B(1) => B(1),
B(2) => B(2),
B(3) => B(3),
B(4) => B(4),
B(5) => B(5),
B(6) => B(6),
B(7) => B(7),
B(8) => B(8),
B(9) => B(9),
B(10) => B(10),
B(11) => B(11),
B(12) => B(12),
B(13) => B(13),
B(14) => B(14),
B(15) => B(15),
B(16) => B(16),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => NN_1,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => NN_1,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_2_2_1_BCOUT(0),
BCOUT(1) => R1IN_2_2_1_BCOUT(1),
BCOUT(2) => R1IN_2_2_1_BCOUT(2),
BCOUT(3) => R1IN_2_2_1_BCOUT(3),
BCOUT(4) => R1IN_2_2_1_BCOUT(4),
BCOUT(5) => R1IN_2_2_1_BCOUT(5),
BCOUT(6) => R1IN_2_2_1_BCOUT(6),
BCOUT(7) => R1IN_2_2_1_BCOUT(7),
BCOUT(8) => R1IN_2_2_1_BCOUT(8),
BCOUT(9) => R1IN_2_2_1_BCOUT(9),
BCOUT(10) => R1IN_2_2_1_BCOUT(10),
BCOUT(11) => R1IN_2_2_1_BCOUT(11),
BCOUT(12) => R1IN_2_2_1_BCOUT(12),
BCOUT(13) => R1IN_2_2_1_BCOUT(13),
BCOUT(14) => R1IN_2_2_1_BCOUT(14),
BCOUT(15) => R1IN_2_2_1_BCOUT(15),
BCOUT(16) => R1IN_2_2_1_BCOUT(16),
BCOUT(17) => R1IN_2_2_1_BCOUT(17),
P(0) => R1IN_2_2(0),
P(1) => R1IN_2_2(1),
P(2) => R1IN_2_2(2),
P(3) => R1IN_2_2(3),
P(4) => R1IN_2_2(4),
P(5) => R1IN_2_2(5),
P(6) => R1IN_2_2(6),
P(7) => R1IN_2_2(7),
P(8) => R1IN_2_2(8),
P(9) => R1IN_2_2(9),
P(10) => R1IN_2_2(10),
P(11) => R1IN_2_2(11),
P(12) => R1IN_2_2(12),
P(13) => R1IN_2_2(13),
P(14) => R1IN_2_2(14),
P(15) => R1IN_2_2(15),
P(16) => R1IN_2_2(16),
P(17) => R1IN_2_2_1(17),
P(18) => R1IN_2_2_1(18),
P(19) => R1IN_2_2_1(19),
P(20) => R1IN_2_2_1(20),
P(21) => R1IN_2_2_1(21),
P(22) => R1IN_2_2_1(22),
P(23) => R1IN_2_2_1(23),
P(24) => R1IN_2_2_1(24),
P(25) => R1IN_2_2_1(25),
P(26) => R1IN_2_2_1(26),
P(27) => R1IN_2_2_1(27),
P(28) => R1IN_2_2_1(28),
P(29) => R1IN_2_2_1(29),
P(30) => R1IN_2_2_1(30),
P(31) => R1IN_2_2_1(31),
P(32) => R1IN_2_2_1(32),
P(33) => R1IN_2_2_1(33),
P(34) => UC_124,
P(35) => UC_125,
P(36) => UC_126,
P(37) => UC_127,
P(38) => UC_128,
P(39) => UC_129,
P(40) => UC_130,
P(41) => UC_131,
P(42) => UC_132,
P(43) => UC_133,
P(44) => UC_134,
P(45) => UC_135,
P(46) => UC_136,
P(47) => UC_137,
PCOUT(0) => R1IN_2_2_0(0),
PCOUT(1) => R1IN_2_2_0(1),
PCOUT(2) => R1IN_2_2_0(2),
PCOUT(3) => R1IN_2_2_0(3),
PCOUT(4) => R1IN_2_2_0(4),
PCOUT(5) => R1IN_2_2_0(5),
PCOUT(6) => R1IN_2_2_0(6),
PCOUT(7) => R1IN_2_2_0(7),
PCOUT(8) => R1IN_2_2_0(8),
PCOUT(9) => R1IN_2_2_0(9),
PCOUT(10) => R1IN_2_2_0(10),
PCOUT(11) => R1IN_2_2_0(11),
PCOUT(12) => R1IN_2_2_0(12),
PCOUT(13) => R1IN_2_2_0(13),
PCOUT(14) => R1IN_2_2_0(14),
PCOUT(15) => R1IN_2_2_0(15),
PCOUT(16) => R1IN_2_2_0(16),
PCOUT(17) => R1IN_2_2_1_0(17),
PCOUT(18) => R1IN_2_2_1_0(18),
PCOUT(19) => R1IN_2_2_1_0(19),
PCOUT(20) => R1IN_2_2_1_0(20),
PCOUT(21) => R1IN_2_2_1_0(21),
PCOUT(22) => R1IN_2_2_1_0(22),
PCOUT(23) => R1IN_2_2_1_0(23),
PCOUT(24) => R1IN_2_2_1_0(24),
PCOUT(25) => R1IN_2_2_1_0(25),
PCOUT(26) => R1IN_2_2_1_0(26),
PCOUT(27) => R1IN_2_2_1_0(27),
PCOUT(28) => R1IN_2_2_1_0(28),
PCOUT(29) => R1IN_2_2_1_0(29),
PCOUT(30) => R1IN_2_2_1_0(30),
PCOUT(31) => R1IN_2_2_1_0(31),
PCOUT(32) => R1IN_2_2_1_0(32),
PCOUT(33) => R1IN_2_2_1_0(33),
PCOUT(34) => UC_124_0,
PCOUT(35) => UC_125_0,
PCOUT(36) => UC_126_0,
PCOUT(37) => UC_127_0,
PCOUT(38) => UC_128_0,
PCOUT(39) => UC_129_0,
PCOUT(40) => UC_130_0,
PCOUT(41) => UC_131_0,
PCOUT(42) => UC_132_0,
PCOUT(43) => UC_133_0,
PCOUT(44) => UC_134_0,
PCOUT(45) => UC_135_0,
PCOUT(46) => UC_136_0,
PCOUT(47) => UC_137_0);
R1IN_4_4_2q260w: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 0,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => A(51),
A(1) => A(52),
A(2) => A(53),
A(3) => A(54),
A(4) => A(55),
A(5) => A(56),
A(6) => A(57),
A(7) => A(58),
A(8) => A(59),
A(9) => A(60),
A(10) => NN_1,
A(11) => NN_1,
A(12) => NN_1,
A(13) => NN_1,
A(14) => NN_1,
A(15) => NN_1,
A(16) => NN_1,
A(17) => NN_1,
B(0) => B(34),
B(1) => B(35),
B(2) => B(36),
B(3) => B(37),
B(4) => B(38),
B(5) => B(39),
B(6) => B(40),
B(7) => B(41),
B(8) => B(42),
B(9) => B(43),
B(10) => B(44),
B(11) => B(45),
B(12) => B(46),
B(13) => B(47),
B(14) => B(48),
B(15) => B(49),
B(16) => B(50),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => NN_1,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => NN_1,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_4_4_2_BCOUT(0),
BCOUT(1) => R1IN_4_4_2_BCOUT(1),
BCOUT(2) => R1IN_4_4_2_BCOUT(2),
BCOUT(3) => R1IN_4_4_2_BCOUT(3),
BCOUT(4) => R1IN_4_4_2_BCOUT(4),
BCOUT(5) => R1IN_4_4_2_BCOUT(5),
BCOUT(6) => R1IN_4_4_2_BCOUT(6),
BCOUT(7) => R1IN_4_4_2_BCOUT(7),
BCOUT(8) => R1IN_4_4_2_BCOUT(8),
BCOUT(9) => R1IN_4_4_2_BCOUT(9),
BCOUT(10) => R1IN_4_4_2_BCOUT(10),
BCOUT(11) => R1IN_4_4_2_BCOUT(11),
BCOUT(12) => R1IN_4_4_2_BCOUT(12),
BCOUT(13) => R1IN_4_4_2_BCOUT(13),
BCOUT(14) => R1IN_4_4_2_BCOUT(14),
BCOUT(15) => R1IN_4_4_2_BCOUT(15),
BCOUT(16) => R1IN_4_4_2_BCOUT(16),
BCOUT(17) => R1IN_4_4_2_BCOUT(17),
P(0) => R1IN_4_4_2(0),
P(1) => R1IN_4_4_2(1),
P(2) => R1IN_4_4_2(2),
P(3) => R1IN_4_4_2(3),
P(4) => R1IN_4_4_2(4),
P(5) => R1IN_4_4_2(5),
P(6) => R1IN_4_4_2(6),
P(7) => R1IN_4_4_2(7),
P(8) => R1IN_4_4_2(8),
P(9) => R1IN_4_4_2(9),
P(10) => R1IN_4_4_2(10),
P(11) => R1IN_4_4_2(11),
P(12) => R1IN_4_4_2(12),
P(13) => R1IN_4_4_2(13),
P(14) => R1IN_4_4_2(14),
P(15) => R1IN_4_4_2(15),
P(16) => R1IN_4_4_2(16),
P(17) => R1IN_4_4_2(17),
P(18) => R1IN_4_4_2(18),
P(19) => R1IN_4_4_2(19),
P(20) => R1IN_4_4_2(20),
P(21) => R1IN_4_4_2(21),
P(22) => R1IN_4_4_2(22),
P(23) => R1IN_4_4_2(23),
P(24) => R1IN_4_4_2(24),
P(25) => R1IN_4_4_2(25),
P(26) => R1IN_4_4_2(26),
P(27) => UC_103,
P(28) => UC_104,
P(29) => UC_105,
P(30) => UC_106,
P(31) => UC_107,
P(32) => UC_108,
P(33) => UC_109,
P(34) => UC_110,
P(35) => UC_111,
P(36) => UC_112,
P(37) => UC_113,
P(38) => UC_114,
P(39) => UC_115,
P(40) => UC_116,
P(41) => UC_117,
P(42) => UC_118,
P(43) => UC_119,
P(44) => UC_120,
P(45) => UC_121,
P(46) => UC_122,
P(47) => UC_123,
PCOUT(0) => R1IN_4_4_2_0(0),
PCOUT(1) => R1IN_4_4_2_0(1),
PCOUT(2) => R1IN_4_4_2_0(2),
PCOUT(3) => R1IN_4_4_2_0(3),
PCOUT(4) => R1IN_4_4_2_0(4),
PCOUT(5) => R1IN_4_4_2_0(5),
PCOUT(6) => R1IN_4_4_2_0(6),
PCOUT(7) => R1IN_4_4_2_0(7),
PCOUT(8) => R1IN_4_4_2_0(8),
PCOUT(9) => R1IN_4_4_2_0(9),
PCOUT(10) => R1IN_4_4_2_0(10),
PCOUT(11) => R1IN_4_4_2_0(11),
PCOUT(12) => R1IN_4_4_2_0(12),
PCOUT(13) => R1IN_4_4_2_0(13),
PCOUT(14) => R1IN_4_4_2_0(14),
PCOUT(15) => R1IN_4_4_2_0(15),
PCOUT(16) => R1IN_4_4_2_0(16),
PCOUT(17) => R1IN_4_4_2_0(17),
PCOUT(18) => R1IN_4_4_2_0(18),
PCOUT(19) => R1IN_4_4_2_0(19),
PCOUT(20) => R1IN_4_4_2_0(20),
PCOUT(21) => R1IN_4_4_2_0(21),
PCOUT(22) => R1IN_4_4_2_0(22),
PCOUT(23) => R1IN_4_4_2_0(23),
PCOUT(24) => R1IN_4_4_2_0(24),
PCOUT(25) => R1IN_4_4_2_0(25),
PCOUT(26) => R1IN_4_4_2_0(26),
PCOUT(27) => UC_103_0,
PCOUT(28) => UC_104_0,
PCOUT(29) => UC_105_0,
PCOUT(30) => UC_106_0,
PCOUT(31) => UC_107_0,
PCOUT(32) => UC_108_0,
PCOUT(33) => UC_109_0,
PCOUT(34) => UC_110_0,
PCOUT(35) => UC_111_0,
PCOUT(36) => UC_112_0,
PCOUT(37) => UC_113_0,
PCOUT(38) => UC_114_0,
PCOUT(39) => UC_115_0,
PCOUT(40) => UC_116_0,
PCOUT(41) => UC_117_0,
PCOUT(42) => UC_118_0,
PCOUT(43) => UC_119_0,
PCOUT(44) => UC_120_0,
PCOUT(45) => UC_121_0,
PCOUT(46) => UC_122_0,
PCOUT(47) => UC_123_0);
R1IN_4_3_ADD_1q260w: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 1,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => B(51),
A(1) => B(52),
A(2) => B(53),
A(3) => B(54),
A(4) => B(55),
A(5) => B(56),
A(6) => B(57),
A(7) => B(58),
A(8) => B(59),
A(9) => B(60),
A(10) => NN_1,
A(11) => NN_1,
A(12) => NN_1,
A(13) => NN_1,
A(14) => NN_1,
A(15) => NN_1,
A(16) => NN_1,
A(17) => NN_1,
B(0) => A(17),
B(1) => A(18),
B(2) => A(19),
B(3) => A(20),
B(4) => A(21),
B(5) => A(22),
B(6) => A(23),
B(7) => A(24),
B(8) => A(25),
B(9) => A(26),
B(10) => A(27),
B(11) => A(28),
B(12) => A(29),
B(13) => A(30),
B(14) => A(31),
B(15) => A(32),
B(16) => A(33),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => R1IN_4_3_0(0),
PCIN(1) => R1IN_4_3_0(1),
PCIN(2) => R1IN_4_3_0(2),
PCIN(3) => R1IN_4_3_0(3),
PCIN(4) => R1IN_4_3_0(4),
PCIN(5) => R1IN_4_3_0(5),
PCIN(6) => R1IN_4_3_0(6),
PCIN(7) => R1IN_4_3_0(7),
PCIN(8) => R1IN_4_3_0(8),
PCIN(9) => R1IN_4_3_0(9),
PCIN(10) => R1IN_4_3_0(10),
PCIN(11) => R1IN_4_3_0(11),
PCIN(12) => R1IN_4_3_0(12),
PCIN(13) => R1IN_4_3_0(13),
PCIN(14) => R1IN_4_3_0(14),
PCIN(15) => R1IN_4_3_0(15),
PCIN(16) => R1IN_4_3_0(16),
PCIN(17) => R1IN_4_3_1_0(17),
PCIN(18) => R1IN_4_3_1_0(18),
PCIN(19) => R1IN_4_3_1_0(19),
PCIN(20) => R1IN_4_3_1_0(20),
PCIN(21) => R1IN_4_3_1_0(21),
PCIN(22) => R1IN_4_3_1_0(22),
PCIN(23) => R1IN_4_3_1_0(23),
PCIN(24) => R1IN_4_3_1_0(24),
PCIN(25) => R1IN_4_3_1_0(25),
PCIN(26) => R1IN_4_3_1_0(26),
PCIN(27) => R1IN_4_3_1_0(27),
PCIN(28) => R1IN_4_3_1_0(28),
PCIN(29) => R1IN_4_3_1_0(29),
PCIN(30) => R1IN_4_3_1_0(30),
PCIN(31) => R1IN_4_3_1_0(31),
PCIN(32) => R1IN_4_3_1_0(32),
PCIN(33) => R1IN_4_3_1_0(33),
PCIN(34) => UC_166_0,
PCIN(35) => UC_167_0,
PCIN(36) => UC_168_0,
PCIN(37) => UC_169_0,
PCIN(38) => UC_170_0,
PCIN(39) => UC_171_0,
PCIN(40) => UC_172_0,
PCIN(41) => UC_173_0,
PCIN(42) => UC_174_0,
PCIN(43) => UC_175_0,
PCIN(44) => UC_176_0,
PCIN(45) => UC_177_0,
PCIN(46) => UC_178_0,
PCIN(47) => UC_179_0,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_2,
OPMODE(5) => NN_1,
OPMODE(6) => NN_2,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => EN,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_4_3_ADD_1_BCOUT(0),
BCOUT(1) => R1IN_4_3_ADD_1_BCOUT(1),
BCOUT(2) => R1IN_4_3_ADD_1_BCOUT(2),
BCOUT(3) => R1IN_4_3_ADD_1_BCOUT(3),
BCOUT(4) => R1IN_4_3_ADD_1_BCOUT(4),
BCOUT(5) => R1IN_4_3_ADD_1_BCOUT(5),
BCOUT(6) => R1IN_4_3_ADD_1_BCOUT(6),
BCOUT(7) => R1IN_4_3_ADD_1_BCOUT(7),
BCOUT(8) => R1IN_4_3_ADD_1_BCOUT(8),
BCOUT(9) => R1IN_4_3_ADD_1_BCOUT(9),
BCOUT(10) => R1IN_4_3_ADD_1_BCOUT(10),
BCOUT(11) => R1IN_4_3_ADD_1_BCOUT(11),
BCOUT(12) => R1IN_4_3_ADD_1_BCOUT(12),
BCOUT(13) => R1IN_4_3_ADD_1_BCOUT(13),
BCOUT(14) => R1IN_4_3_ADD_1_BCOUT(14),
BCOUT(15) => R1IN_4_3_ADD_1_BCOUT(15),
BCOUT(16) => R1IN_4_3_ADD_1_BCOUT(16),
BCOUT(17) => R1IN_4_3_ADD_1_BCOUT(17),
P(0) => R1IN_4_3F(17),
P(1) => R1IN_4_3F(18),
P(2) => R1IN_4_3F(19),
P(3) => R1IN_4_3F(20),
P(4) => R1IN_4_3F(21),
P(5) => R1IN_4_3F(22),
P(6) => R1IN_4_3F(23),
P(7) => R1IN_4_3F(24),
P(8) => R1IN_4_3F(25),
P(9) => R1IN_4_3F(26),
P(10) => R1IN_4_3F(27),
P(11) => R1IN_4_3F(28),
P(12) => R1IN_4_3F(29),
P(13) => R1IN_4_3F(30),
P(14) => R1IN_4_3F(31),
P(15) => R1IN_4_3F(32),
P(16) => R1IN_4_3F(33),
P(17) => R1IN_4_3F(34),
P(18) => R1IN_4_3F(35),
P(19) => R1IN_4_3F(36),
P(20) => R1IN_4_3F(37),
P(21) => R1IN_4_3F(38),
P(22) => R1IN_4_3F(39),
P(23) => R1IN_4_3F(40),
P(24) => R1IN_4_3F(41),
P(25) => R1IN_4_3F(42),
P(26) => R1IN_4_3F(43),
P(27) => UC_82,
P(28) => UC_83,
P(29) => UC_84,
P(30) => UC_85,
P(31) => UC_86,
P(32) => UC_87,
P(33) => UC_88,
P(34) => UC_89,
P(35) => UC_90,
P(36) => UC_91,
P(37) => UC_92,
P(38) => UC_93,
P(39) => UC_94,
P(40) => UC_95,
P(41) => UC_96,
P(42) => UC_97,
P(43) => UC_98,
P(44) => UC_99,
P(45) => UC_100,
P(46) => UC_101,
P(47) => UC_102,
PCOUT(0) => R1IN_4_3_ADD_1_PCOUT(0),
PCOUT(1) => R1IN_4_3_ADD_1_PCOUT(1),
PCOUT(2) => R1IN_4_3_ADD_1_PCOUT(2),
PCOUT(3) => R1IN_4_3_ADD_1_PCOUT(3),
PCOUT(4) => R1IN_4_3_ADD_1_PCOUT(4),
PCOUT(5) => R1IN_4_3_ADD_1_PCOUT(5),
PCOUT(6) => R1IN_4_3_ADD_1_PCOUT(6),
PCOUT(7) => R1IN_4_3_ADD_1_PCOUT(7),
PCOUT(8) => R1IN_4_3_ADD_1_PCOUT(8),
PCOUT(9) => R1IN_4_3_ADD_1_PCOUT(9),
PCOUT(10) => R1IN_4_3_ADD_1_PCOUT(10),
PCOUT(11) => R1IN_4_3_ADD_1_PCOUT(11),
PCOUT(12) => R1IN_4_3_ADD_1_PCOUT(12),
PCOUT(13) => R1IN_4_3_ADD_1_PCOUT(13),
PCOUT(14) => R1IN_4_3_ADD_1_PCOUT(14),
PCOUT(15) => R1IN_4_3_ADD_1_PCOUT(15),
PCOUT(16) => R1IN_4_3_ADD_1_PCOUT(16),
PCOUT(17) => R1IN_4_3_ADD_1_PCOUT(17),
PCOUT(18) => R1IN_4_3_ADD_1_PCOUT(18),
PCOUT(19) => R1IN_4_3_ADD_1_PCOUT(19),
PCOUT(20) => R1IN_4_3_ADD_1_PCOUT(20),
PCOUT(21) => R1IN_4_3_ADD_1_PCOUT(21),
PCOUT(22) => R1IN_4_3_ADD_1_PCOUT(22),
PCOUT(23) => R1IN_4_3_ADD_1_PCOUT(23),
PCOUT(24) => R1IN_4_3_ADD_1_PCOUT(24),
PCOUT(25) => R1IN_4_3_ADD_1_PCOUT(25),
PCOUT(26) => R1IN_4_3_ADD_1_PCOUT(26),
PCOUT(27) => R1IN_4_3_ADD_1_PCOUT(27),
PCOUT(28) => R1IN_4_3_ADD_1_PCOUT(28),
PCOUT(29) => R1IN_4_3_ADD_1_PCOUT(29),
PCOUT(30) => R1IN_4_3_ADD_1_PCOUT(30),
PCOUT(31) => R1IN_4_3_ADD_1_PCOUT(31),
PCOUT(32) => R1IN_4_3_ADD_1_PCOUT(32),
PCOUT(33) => R1IN_4_3_ADD_1_PCOUT(33),
PCOUT(34) => R1IN_4_3_ADD_1_PCOUT(34),
PCOUT(35) => R1IN_4_3_ADD_1_PCOUT(35),
PCOUT(36) => R1IN_4_3_ADD_1_PCOUT(36),
PCOUT(37) => R1IN_4_3_ADD_1_PCOUT(37),
PCOUT(38) => R1IN_4_3_ADD_1_PCOUT(38),
PCOUT(39) => R1IN_4_3_ADD_1_PCOUT(39),
PCOUT(40) => R1IN_4_3_ADD_1_PCOUT(40),
PCOUT(41) => R1IN_4_3_ADD_1_PCOUT(41),
PCOUT(42) => R1IN_4_3_ADD_1_PCOUT(42),
PCOUT(43) => R1IN_4_3_ADD_1_PCOUT(43),
PCOUT(44) => R1IN_4_3_ADD_1_PCOUT(44),
PCOUT(45) => R1IN_4_3_ADD_1_PCOUT(45),
PCOUT(46) => R1IN_4_3_ADD_1_PCOUT(46),
PCOUT(47) => R1IN_4_3_ADD_1_PCOUT(47));
R1IN_4_2_ADD_1q260w: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 1,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => A(51),
A(1) => A(52),
A(2) => A(53),
A(3) => A(54),
A(4) => A(55),
A(5) => A(56),
A(6) => A(57),
A(7) => A(58),
A(8) => A(59),
A(9) => A(60),
A(10) => NN_1,
A(11) => NN_1,
A(12) => NN_1,
A(13) => NN_1,
A(14) => NN_1,
A(15) => NN_1,
A(16) => NN_1,
A(17) => NN_1,
B(0) => B(17),
B(1) => B(18),
B(2) => B(19),
B(3) => B(20),
B(4) => B(21),
B(5) => B(22),
B(6) => B(23),
B(7) => B(24),
B(8) => B(25),
B(9) => B(26),
B(10) => B(27),
B(11) => B(28),
B(12) => B(29),
B(13) => B(30),
B(14) => B(31),
B(15) => B(32),
B(16) => B(33),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => R1IN_4_2_0(0),
PCIN(1) => R1IN_4_2_0(1),
PCIN(2) => R1IN_4_2_0(2),
PCIN(3) => R1IN_4_2_0(3),
PCIN(4) => R1IN_4_2_0(4),
PCIN(5) => R1IN_4_2_0(5),
PCIN(6) => R1IN_4_2_0(6),
PCIN(7) => R1IN_4_2_0(7),
PCIN(8) => R1IN_4_2_0(8),
PCIN(9) => R1IN_4_2_0(9),
PCIN(10) => R1IN_4_2_0(10),
PCIN(11) => R1IN_4_2_0(11),
PCIN(12) => R1IN_4_2_0(12),
PCIN(13) => R1IN_4_2_0(13),
PCIN(14) => R1IN_4_2_0(14),
PCIN(15) => R1IN_4_2_0(15),
PCIN(16) => R1IN_4_2_0(16),
PCIN(17) => R1IN_4_2_1_0(17),
PCIN(18) => R1IN_4_2_1_0(18),
PCIN(19) => R1IN_4_2_1_0(19),
PCIN(20) => R1IN_4_2_1_0(20),
PCIN(21) => R1IN_4_2_1_0(21),
PCIN(22) => R1IN_4_2_1_0(22),
PCIN(23) => R1IN_4_2_1_0(23),
PCIN(24) => R1IN_4_2_1_0(24),
PCIN(25) => R1IN_4_2_1_0(25),
PCIN(26) => R1IN_4_2_1_0(26),
PCIN(27) => R1IN_4_2_1_0(27),
PCIN(28) => R1IN_4_2_1_0(28),
PCIN(29) => R1IN_4_2_1_0(29),
PCIN(30) => R1IN_4_2_1_0(30),
PCIN(31) => R1IN_4_2_1_0(31),
PCIN(32) => R1IN_4_2_1_0(32),
PCIN(33) => R1IN_4_2_1_0(33),
PCIN(34) => UC_152_0,
PCIN(35) => UC_153_0,
PCIN(36) => UC_154_0,
PCIN(37) => UC_155_0,
PCIN(38) => UC_156_0,
PCIN(39) => UC_157_0,
PCIN(40) => UC_158_0,
PCIN(41) => UC_159_0,
PCIN(42) => UC_160_0,
PCIN(43) => UC_161_0,
PCIN(44) => UC_162_0,
PCIN(45) => UC_163_0,
PCIN(46) => UC_164_0,
PCIN(47) => UC_165_0,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_2,
OPMODE(5) => NN_1,
OPMODE(6) => NN_2,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => EN,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_4_2_ADD_1_BCOUT(0),
BCOUT(1) => R1IN_4_2_ADD_1_BCOUT(1),
BCOUT(2) => R1IN_4_2_ADD_1_BCOUT(2),
BCOUT(3) => R1IN_4_2_ADD_1_BCOUT(3),
BCOUT(4) => R1IN_4_2_ADD_1_BCOUT(4),
BCOUT(5) => R1IN_4_2_ADD_1_BCOUT(5),
BCOUT(6) => R1IN_4_2_ADD_1_BCOUT(6),
BCOUT(7) => R1IN_4_2_ADD_1_BCOUT(7),
BCOUT(8) => R1IN_4_2_ADD_1_BCOUT(8),
BCOUT(9) => R1IN_4_2_ADD_1_BCOUT(9),
BCOUT(10) => R1IN_4_2_ADD_1_BCOUT(10),
BCOUT(11) => R1IN_4_2_ADD_1_BCOUT(11),
BCOUT(12) => R1IN_4_2_ADD_1_BCOUT(12),
BCOUT(13) => R1IN_4_2_ADD_1_BCOUT(13),
BCOUT(14) => R1IN_4_2_ADD_1_BCOUT(14),
BCOUT(15) => R1IN_4_2_ADD_1_BCOUT(15),
BCOUT(16) => R1IN_4_2_ADD_1_BCOUT(16),
BCOUT(17) => R1IN_4_2_ADD_1_BCOUT(17),
P(0) => R1IN_4_2F(17),
P(1) => R1IN_4_2F(18),
P(2) => R1IN_4_2F(19),
P(3) => R1IN_4_2F(20),
P(4) => R1IN_4_2F(21),
P(5) => R1IN_4_2F(22),
P(6) => R1IN_4_2F(23),
P(7) => R1IN_4_2F(24),
P(8) => R1IN_4_2F(25),
P(9) => R1IN_4_2F(26),
P(10) => R1IN_4_2F(27),
P(11) => R1IN_4_2F(28),
P(12) => R1IN_4_2F(29),
P(13) => R1IN_4_2F(30),
P(14) => R1IN_4_2F(31),
P(15) => R1IN_4_2F(32),
P(16) => R1IN_4_2F(33),
P(17) => R1IN_4_2F(34),
P(18) => R1IN_4_2F(35),
P(19) => R1IN_4_2F(36),
P(20) => R1IN_4_2F(37),
P(21) => R1IN_4_2F(38),
P(22) => R1IN_4_2F(39),
P(23) => R1IN_4_2F(40),
P(24) => R1IN_4_2F(41),
P(25) => R1IN_4_2F(42),
P(26) => R1IN_4_2F(43),
P(27) => UC_61,
P(28) => UC_62,
P(29) => UC_63,
P(30) => UC_64,
P(31) => UC_65,
P(32) => UC_66,
P(33) => UC_67,
P(34) => UC_68,
P(35) => UC_69,
P(36) => UC_70,
P(37) => UC_71,
P(38) => UC_72,
P(39) => UC_73,
P(40) => UC_74,
P(41) => UC_75,
P(42) => UC_76,
P(43) => UC_77,
P(44) => UC_78,
P(45) => UC_79,
P(46) => UC_80,
P(47) => UC_81,
PCOUT(0) => R1IN_4_2_ADD_1_PCOUT(0),
PCOUT(1) => R1IN_4_2_ADD_1_PCOUT(1),
PCOUT(2) => R1IN_4_2_ADD_1_PCOUT(2),
PCOUT(3) => R1IN_4_2_ADD_1_PCOUT(3),
PCOUT(4) => R1IN_4_2_ADD_1_PCOUT(4),
PCOUT(5) => R1IN_4_2_ADD_1_PCOUT(5),
PCOUT(6) => R1IN_4_2_ADD_1_PCOUT(6),
PCOUT(7) => R1IN_4_2_ADD_1_PCOUT(7),
PCOUT(8) => R1IN_4_2_ADD_1_PCOUT(8),
PCOUT(9) => R1IN_4_2_ADD_1_PCOUT(9),
PCOUT(10) => R1IN_4_2_ADD_1_PCOUT(10),
PCOUT(11) => R1IN_4_2_ADD_1_PCOUT(11),
PCOUT(12) => R1IN_4_2_ADD_1_PCOUT(12),
PCOUT(13) => R1IN_4_2_ADD_1_PCOUT(13),
PCOUT(14) => R1IN_4_2_ADD_1_PCOUT(14),
PCOUT(15) => R1IN_4_2_ADD_1_PCOUT(15),
PCOUT(16) => R1IN_4_2_ADD_1_PCOUT(16),
PCOUT(17) => R1IN_4_2_ADD_1_PCOUT(17),
PCOUT(18) => R1IN_4_2_ADD_1_PCOUT(18),
PCOUT(19) => R1IN_4_2_ADD_1_PCOUT(19),
PCOUT(20) => R1IN_4_2_ADD_1_PCOUT(20),
PCOUT(21) => R1IN_4_2_ADD_1_PCOUT(21),
PCOUT(22) => R1IN_4_2_ADD_1_PCOUT(22),
PCOUT(23) => R1IN_4_2_ADD_1_PCOUT(23),
PCOUT(24) => R1IN_4_2_ADD_1_PCOUT(24),
PCOUT(25) => R1IN_4_2_ADD_1_PCOUT(25),
PCOUT(26) => R1IN_4_2_ADD_1_PCOUT(26),
PCOUT(27) => R1IN_4_2_ADD_1_PCOUT(27),
PCOUT(28) => R1IN_4_2_ADD_1_PCOUT(28),
PCOUT(29) => R1IN_4_2_ADD_1_PCOUT(29),
PCOUT(30) => R1IN_4_2_ADD_1_PCOUT(30),
PCOUT(31) => R1IN_4_2_ADD_1_PCOUT(31),
PCOUT(32) => R1IN_4_2_ADD_1_PCOUT(32),
PCOUT(33) => R1IN_4_2_ADD_1_PCOUT(33),
PCOUT(34) => R1IN_4_2_ADD_1_PCOUT(34),
PCOUT(35) => R1IN_4_2_ADD_1_PCOUT(35),
PCOUT(36) => R1IN_4_2_ADD_1_PCOUT(36),
PCOUT(37) => R1IN_4_2_ADD_1_PCOUT(37),
PCOUT(38) => R1IN_4_2_ADD_1_PCOUT(38),
PCOUT(39) => R1IN_4_2_ADD_1_PCOUT(39),
PCOUT(40) => R1IN_4_2_ADD_1_PCOUT(40),
PCOUT(41) => R1IN_4_2_ADD_1_PCOUT(41),
PCOUT(42) => R1IN_4_2_ADD_1_PCOUT(42),
PCOUT(43) => R1IN_4_2_ADD_1_PCOUT(43),
PCOUT(44) => R1IN_4_2_ADD_1_PCOUT(44),
PCOUT(45) => R1IN_4_2_ADD_1_PCOUT(45),
PCOUT(46) => R1IN_4_2_ADD_1_PCOUT(46),
PCOUT(47) => R1IN_4_2_ADD_1_PCOUT(47));
R1IN_3_2_ADD_1q260w: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 1,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => B(51),
A(1) => B(52),
A(2) => B(53),
A(3) => B(54),
A(4) => B(55),
A(5) => B(56),
A(6) => B(57),
A(7) => B(58),
A(8) => B(59),
A(9) => B(60),
A(10) => NN_1,
A(11) => NN_1,
A(12) => NN_1,
A(13) => NN_1,
A(14) => NN_1,
A(15) => NN_1,
A(16) => NN_1,
A(17) => NN_1,
B(0) => A(0),
B(1) => A(1),
B(2) => A(2),
B(3) => A(3),
B(4) => A(4),
B(5) => A(5),
B(6) => A(6),
B(7) => A(7),
B(8) => A(8),
B(9) => A(9),
B(10) => A(10),
B(11) => A(11),
B(12) => A(12),
B(13) => A(13),
B(14) => A(14),
B(15) => A(15),
B(16) => A(16),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => R1IN_3_2_0(0),
PCIN(1) => R1IN_3_2_0(1),
PCIN(2) => R1IN_3_2_0(2),
PCIN(3) => R1IN_3_2_0(3),
PCIN(4) => R1IN_3_2_0(4),
PCIN(5) => R1IN_3_2_0(5),
PCIN(6) => R1IN_3_2_0(6),
PCIN(7) => R1IN_3_2_0(7),
PCIN(8) => R1IN_3_2_0(8),
PCIN(9) => R1IN_3_2_0(9),
PCIN(10) => R1IN_3_2_0(10),
PCIN(11) => R1IN_3_2_0(11),
PCIN(12) => R1IN_3_2_0(12),
PCIN(13) => R1IN_3_2_0(13),
PCIN(14) => R1IN_3_2_0(14),
PCIN(15) => R1IN_3_2_0(15),
PCIN(16) => R1IN_3_2_0(16),
PCIN(17) => R1IN_3_2_1_0(17),
PCIN(18) => R1IN_3_2_1_0(18),
PCIN(19) => R1IN_3_2_1_0(19),
PCIN(20) => R1IN_3_2_1_0(20),
PCIN(21) => R1IN_3_2_1_0(21),
PCIN(22) => R1IN_3_2_1_0(22),
PCIN(23) => R1IN_3_2_1_0(23),
PCIN(24) => R1IN_3_2_1_0(24),
PCIN(25) => R1IN_3_2_1_0(25),
PCIN(26) => R1IN_3_2_1_0(26),
PCIN(27) => R1IN_3_2_1_0(27),
PCIN(28) => R1IN_3_2_1_0(28),
PCIN(29) => R1IN_3_2_1_0(29),
PCIN(30) => R1IN_3_2_1_0(30),
PCIN(31) => R1IN_3_2_1_0(31),
PCIN(32) => R1IN_3_2_1_0(32),
PCIN(33) => R1IN_3_2_1_0(33),
PCIN(34) => UC_138_0,
PCIN(35) => UC_139_0,
PCIN(36) => UC_140_0,
PCIN(37) => UC_141_0,
PCIN(38) => UC_142_0,
PCIN(39) => UC_143_0,
PCIN(40) => UC_144_0,
PCIN(41) => UC_145_0,
PCIN(42) => UC_146_0,
PCIN(43) => UC_147_0,
PCIN(44) => UC_148_0,
PCIN(45) => UC_149_0,
PCIN(46) => UC_150_0,
PCIN(47) => UC_151_0,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_2,
OPMODE(5) => NN_1,
OPMODE(6) => NN_2,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => EN,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_3_2_ADD_1_BCOUT(0),
BCOUT(1) => R1IN_3_2_ADD_1_BCOUT(1),
BCOUT(2) => R1IN_3_2_ADD_1_BCOUT(2),
BCOUT(3) => R1IN_3_2_ADD_1_BCOUT(3),
BCOUT(4) => R1IN_3_2_ADD_1_BCOUT(4),
BCOUT(5) => R1IN_3_2_ADD_1_BCOUT(5),
BCOUT(6) => R1IN_3_2_ADD_1_BCOUT(6),
BCOUT(7) => R1IN_3_2_ADD_1_BCOUT(7),
BCOUT(8) => R1IN_3_2_ADD_1_BCOUT(8),
BCOUT(9) => R1IN_3_2_ADD_1_BCOUT(9),
BCOUT(10) => R1IN_3_2_ADD_1_BCOUT(10),
BCOUT(11) => R1IN_3_2_ADD_1_BCOUT(11),
BCOUT(12) => R1IN_3_2_ADD_1_BCOUT(12),
BCOUT(13) => R1IN_3_2_ADD_1_BCOUT(13),
BCOUT(14) => R1IN_3_2_ADD_1_BCOUT(14),
BCOUT(15) => R1IN_3_2_ADD_1_BCOUT(15),
BCOUT(16) => R1IN_3_2_ADD_1_BCOUT(16),
BCOUT(17) => R1IN_3_2_ADD_1_BCOUT(17),
P(0) => R1IN_3_2F(17),
P(1) => R1IN_3_2F(18),
P(2) => R1IN_3_2F(19),
P(3) => R1IN_3_2F(20),
P(4) => R1IN_3_2F(21),
P(5) => R1IN_3_2F(22),
P(6) => R1IN_3_2F(23),
P(7) => R1IN_3_2F(24),
P(8) => R1IN_3_2F(25),
P(9) => R1IN_3_2F(26),
P(10) => R1IN_3_2F(27),
P(11) => R1IN_3_2F(28),
P(12) => R1IN_3_2F(29),
P(13) => R1IN_3_2F(30),
P(14) => R1IN_3_2F(31),
P(15) => R1IN_3_2F(32),
P(16) => R1IN_3_2F(33),
P(17) => R1IN_3_2F(34),
P(18) => R1IN_3_2F(35),
P(19) => R1IN_3_2F(36),
P(20) => R1IN_3_2F(37),
P(21) => R1IN_3_2F(38),
P(22) => R1IN_3_2F(39),
P(23) => R1IN_3_2F(40),
P(24) => R1IN_3_2F(41),
P(25) => R1IN_3_2F(42),
P(26) => R1IN_3_2F(43),
P(27) => UC_40,
P(28) => UC_41,
P(29) => UC_42,
P(30) => UC_43,
P(31) => UC_44,
P(32) => UC_45,
P(33) => UC_46,
P(34) => UC_47,
P(35) => UC_48,
P(36) => UC_49,
P(37) => UC_50,
P(38) => UC_51,
P(39) => UC_52,
P(40) => UC_53,
P(41) => UC_54,
P(42) => UC_55,
P(43) => UC_56,
P(44) => UC_57,
P(45) => UC_58,
P(46) => UC_59,
P(47) => UC_60,
PCOUT(0) => R1IN_3_2_ADD_1_PCOUT(0),
PCOUT(1) => R1IN_3_2_ADD_1_PCOUT(1),
PCOUT(2) => R1IN_3_2_ADD_1_PCOUT(2),
PCOUT(3) => R1IN_3_2_ADD_1_PCOUT(3),
PCOUT(4) => R1IN_3_2_ADD_1_PCOUT(4),
PCOUT(5) => R1IN_3_2_ADD_1_PCOUT(5),
PCOUT(6) => R1IN_3_2_ADD_1_PCOUT(6),
PCOUT(7) => R1IN_3_2_ADD_1_PCOUT(7),
PCOUT(8) => R1IN_3_2_ADD_1_PCOUT(8),
PCOUT(9) => R1IN_3_2_ADD_1_PCOUT(9),
PCOUT(10) => R1IN_3_2_ADD_1_PCOUT(10),
PCOUT(11) => R1IN_3_2_ADD_1_PCOUT(11),
PCOUT(12) => R1IN_3_2_ADD_1_PCOUT(12),
PCOUT(13) => R1IN_3_2_ADD_1_PCOUT(13),
PCOUT(14) => R1IN_3_2_ADD_1_PCOUT(14),
PCOUT(15) => R1IN_3_2_ADD_1_PCOUT(15),
PCOUT(16) => R1IN_3_2_ADD_1_PCOUT(16),
PCOUT(17) => R1IN_3_2_ADD_1_PCOUT(17),
PCOUT(18) => R1IN_3_2_ADD_1_PCOUT(18),
PCOUT(19) => R1IN_3_2_ADD_1_PCOUT(19),
PCOUT(20) => R1IN_3_2_ADD_1_PCOUT(20),
PCOUT(21) => R1IN_3_2_ADD_1_PCOUT(21),
PCOUT(22) => R1IN_3_2_ADD_1_PCOUT(22),
PCOUT(23) => R1IN_3_2_ADD_1_PCOUT(23),
PCOUT(24) => R1IN_3_2_ADD_1_PCOUT(24),
PCOUT(25) => R1IN_3_2_ADD_1_PCOUT(25),
PCOUT(26) => R1IN_3_2_ADD_1_PCOUT(26),
PCOUT(27) => R1IN_3_2_ADD_1_PCOUT(27),
PCOUT(28) => R1IN_3_2_ADD_1_PCOUT(28),
PCOUT(29) => R1IN_3_2_ADD_1_PCOUT(29),
PCOUT(30) => R1IN_3_2_ADD_1_PCOUT(30),
PCOUT(31) => R1IN_3_2_ADD_1_PCOUT(31),
PCOUT(32) => R1IN_3_2_ADD_1_PCOUT(32),
PCOUT(33) => R1IN_3_2_ADD_1_PCOUT(33),
PCOUT(34) => R1IN_3_2_ADD_1_PCOUT(34),
PCOUT(35) => R1IN_3_2_ADD_1_PCOUT(35),
PCOUT(36) => R1IN_3_2_ADD_1_PCOUT(36),
PCOUT(37) => R1IN_3_2_ADD_1_PCOUT(37),
PCOUT(38) => R1IN_3_2_ADD_1_PCOUT(38),
PCOUT(39) => R1IN_3_2_ADD_1_PCOUT(39),
PCOUT(40) => R1IN_3_2_ADD_1_PCOUT(40),
PCOUT(41) => R1IN_3_2_ADD_1_PCOUT(41),
PCOUT(42) => R1IN_3_2_ADD_1_PCOUT(42),
PCOUT(43) => R1IN_3_2_ADD_1_PCOUT(43),
PCOUT(44) => R1IN_3_2_ADD_1_PCOUT(44),
PCOUT(45) => R1IN_3_2_ADD_1_PCOUT(45),
PCOUT(46) => R1IN_3_2_ADD_1_PCOUT(46),
PCOUT(47) => R1IN_3_2_ADD_1_PCOUT(47));
R1IN_2_2_ADD_1q260w: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 1,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => A(51),
A(1) => A(52),
A(2) => A(53),
A(3) => A(54),
A(4) => A(55),
A(5) => A(56),
A(6) => A(57),
A(7) => A(58),
A(8) => A(59),
A(9) => A(60),
A(10) => NN_1,
A(11) => NN_1,
A(12) => NN_1,
A(13) => NN_1,
A(14) => NN_1,
A(15) => NN_1,
A(16) => NN_1,
A(17) => NN_1,
B(0) => B(0),
B(1) => B(1),
B(2) => B(2),
B(3) => B(3),
B(4) => B(4),
B(5) => B(5),
B(6) => B(6),
B(7) => B(7),
B(8) => B(8),
B(9) => B(9),
B(10) => B(10),
B(11) => B(11),
B(12) => B(12),
B(13) => B(13),
B(14) => B(14),
B(15) => B(15),
B(16) => B(16),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => R1IN_2_2_0(0),
PCIN(1) => R1IN_2_2_0(1),
PCIN(2) => R1IN_2_2_0(2),
PCIN(3) => R1IN_2_2_0(3),
PCIN(4) => R1IN_2_2_0(4),
PCIN(5) => R1IN_2_2_0(5),
PCIN(6) => R1IN_2_2_0(6),
PCIN(7) => R1IN_2_2_0(7),
PCIN(8) => R1IN_2_2_0(8),
PCIN(9) => R1IN_2_2_0(9),
PCIN(10) => R1IN_2_2_0(10),
PCIN(11) => R1IN_2_2_0(11),
PCIN(12) => R1IN_2_2_0(12),
PCIN(13) => R1IN_2_2_0(13),
PCIN(14) => R1IN_2_2_0(14),
PCIN(15) => R1IN_2_2_0(15),
PCIN(16) => R1IN_2_2_0(16),
PCIN(17) => R1IN_2_2_1_0(17),
PCIN(18) => R1IN_2_2_1_0(18),
PCIN(19) => R1IN_2_2_1_0(19),
PCIN(20) => R1IN_2_2_1_0(20),
PCIN(21) => R1IN_2_2_1_0(21),
PCIN(22) => R1IN_2_2_1_0(22),
PCIN(23) => R1IN_2_2_1_0(23),
PCIN(24) => R1IN_2_2_1_0(24),
PCIN(25) => R1IN_2_2_1_0(25),
PCIN(26) => R1IN_2_2_1_0(26),
PCIN(27) => R1IN_2_2_1_0(27),
PCIN(28) => R1IN_2_2_1_0(28),
PCIN(29) => R1IN_2_2_1_0(29),
PCIN(30) => R1IN_2_2_1_0(30),
PCIN(31) => R1IN_2_2_1_0(31),
PCIN(32) => R1IN_2_2_1_0(32),
PCIN(33) => R1IN_2_2_1_0(33),
PCIN(34) => UC_124_0,
PCIN(35) => UC_125_0,
PCIN(36) => UC_126_0,
PCIN(37) => UC_127_0,
PCIN(38) => UC_128_0,
PCIN(39) => UC_129_0,
PCIN(40) => UC_130_0,
PCIN(41) => UC_131_0,
PCIN(42) => UC_132_0,
PCIN(43) => UC_133_0,
PCIN(44) => UC_134_0,
PCIN(45) => UC_135_0,
PCIN(46) => UC_136_0,
PCIN(47) => UC_137_0,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_2,
OPMODE(5) => NN_1,
OPMODE(6) => NN_2,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => EN,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_2_2_ADD_1_BCOUT(0),
BCOUT(1) => R1IN_2_2_ADD_1_BCOUT(1),
BCOUT(2) => R1IN_2_2_ADD_1_BCOUT(2),
BCOUT(3) => R1IN_2_2_ADD_1_BCOUT(3),
BCOUT(4) => R1IN_2_2_ADD_1_BCOUT(4),
BCOUT(5) => R1IN_2_2_ADD_1_BCOUT(5),
BCOUT(6) => R1IN_2_2_ADD_1_BCOUT(6),
BCOUT(7) => R1IN_2_2_ADD_1_BCOUT(7),
BCOUT(8) => R1IN_2_2_ADD_1_BCOUT(8),
BCOUT(9) => R1IN_2_2_ADD_1_BCOUT(9),
BCOUT(10) => R1IN_2_2_ADD_1_BCOUT(10),
BCOUT(11) => R1IN_2_2_ADD_1_BCOUT(11),
BCOUT(12) => R1IN_2_2_ADD_1_BCOUT(12),
BCOUT(13) => R1IN_2_2_ADD_1_BCOUT(13),
BCOUT(14) => R1IN_2_2_ADD_1_BCOUT(14),
BCOUT(15) => R1IN_2_2_ADD_1_BCOUT(15),
BCOUT(16) => R1IN_2_2_ADD_1_BCOUT(16),
BCOUT(17) => R1IN_2_2_ADD_1_BCOUT(17),
P(0) => R1IN_2_2F(17),
P(1) => R1IN_2_2F(18),
P(2) => R1IN_2_2F(19),
P(3) => R1IN_2_2F(20),
P(4) => R1IN_2_2F(21),
P(5) => R1IN_2_2F(22),
P(6) => R1IN_2_2F(23),
P(7) => R1IN_2_2F(24),
P(8) => R1IN_2_2F(25),
P(9) => R1IN_2_2F(26),
P(10) => R1IN_2_2F(27),
P(11) => R1IN_2_2F(28),
P(12) => R1IN_2_2F(29),
P(13) => R1IN_2_2F(30),
P(14) => R1IN_2_2F(31),
P(15) => R1IN_2_2F(32),
P(16) => R1IN_2_2F(33),
P(17) => R1IN_2_2F(34),
P(18) => R1IN_2_2F(35),
P(19) => R1IN_2_2F(36),
P(20) => R1IN_2_2F(37),
P(21) => R1IN_2_2F(38),
P(22) => R1IN_2_2F(39),
P(23) => R1IN_2_2F(40),
P(24) => R1IN_2_2F(41),
P(25) => R1IN_2_2F(42),
P(26) => R1IN_2_2F(43),
P(27) => UC_19,
P(28) => UC_20,
P(29) => UC_21,
P(30) => UC_22,
P(31) => UC_23,
P(32) => UC_24,
P(33) => UC_25,
P(34) => UC_26,
P(35) => UC_27,
P(36) => UC_28,
P(37) => UC_29,
P(38) => UC_30,
P(39) => UC_31,
P(40) => UC_32,
P(41) => UC_33,
P(42) => UC_34,
P(43) => UC_35,
P(44) => UC_36,
P(45) => UC_37,
P(46) => UC_38,
P(47) => UC_39,
PCOUT(0) => R1IN_2_2_ADD_1_PCOUT(0),
PCOUT(1) => R1IN_2_2_ADD_1_PCOUT(1),
PCOUT(2) => R1IN_2_2_ADD_1_PCOUT(2),
PCOUT(3) => R1IN_2_2_ADD_1_PCOUT(3),
PCOUT(4) => R1IN_2_2_ADD_1_PCOUT(4),
PCOUT(5) => R1IN_2_2_ADD_1_PCOUT(5),
PCOUT(6) => R1IN_2_2_ADD_1_PCOUT(6),
PCOUT(7) => R1IN_2_2_ADD_1_PCOUT(7),
PCOUT(8) => R1IN_2_2_ADD_1_PCOUT(8),
PCOUT(9) => R1IN_2_2_ADD_1_PCOUT(9),
PCOUT(10) => R1IN_2_2_ADD_1_PCOUT(10),
PCOUT(11) => R1IN_2_2_ADD_1_PCOUT(11),
PCOUT(12) => R1IN_2_2_ADD_1_PCOUT(12),
PCOUT(13) => R1IN_2_2_ADD_1_PCOUT(13),
PCOUT(14) => R1IN_2_2_ADD_1_PCOUT(14),
PCOUT(15) => R1IN_2_2_ADD_1_PCOUT(15),
PCOUT(16) => R1IN_2_2_ADD_1_PCOUT(16),
PCOUT(17) => R1IN_2_2_ADD_1_PCOUT(17),
PCOUT(18) => R1IN_2_2_ADD_1_PCOUT(18),
PCOUT(19) => R1IN_2_2_ADD_1_PCOUT(19),
PCOUT(20) => R1IN_2_2_ADD_1_PCOUT(20),
PCOUT(21) => R1IN_2_2_ADD_1_PCOUT(21),
PCOUT(22) => R1IN_2_2_ADD_1_PCOUT(22),
PCOUT(23) => R1IN_2_2_ADD_1_PCOUT(23),
PCOUT(24) => R1IN_2_2_ADD_1_PCOUT(24),
PCOUT(25) => R1IN_2_2_ADD_1_PCOUT(25),
PCOUT(26) => R1IN_2_2_ADD_1_PCOUT(26),
PCOUT(27) => R1IN_2_2_ADD_1_PCOUT(27),
PCOUT(28) => R1IN_2_2_ADD_1_PCOUT(28),
PCOUT(29) => R1IN_2_2_ADD_1_PCOUT(29),
PCOUT(30) => R1IN_2_2_ADD_1_PCOUT(30),
PCOUT(31) => R1IN_2_2_ADD_1_PCOUT(31),
PCOUT(32) => R1IN_2_2_ADD_1_PCOUT(32),
PCOUT(33) => R1IN_2_2_ADD_1_PCOUT(33),
PCOUT(34) => R1IN_2_2_ADD_1_PCOUT(34),
PCOUT(35) => R1IN_2_2_ADD_1_PCOUT(35),
PCOUT(36) => R1IN_2_2_ADD_1_PCOUT(36),
PCOUT(37) => R1IN_2_2_ADD_1_PCOUT(37),
PCOUT(38) => R1IN_2_2_ADD_1_PCOUT(38),
PCOUT(39) => R1IN_2_2_ADD_1_PCOUT(39),
PCOUT(40) => R1IN_2_2_ADD_1_PCOUT(40),
PCOUT(41) => R1IN_2_2_ADD_1_PCOUT(41),
PCOUT(42) => R1IN_2_2_ADD_1_PCOUT(42),
PCOUT(43) => R1IN_2_2_ADD_1_PCOUT(43),
PCOUT(44) => R1IN_2_2_ADD_1_PCOUT(44),
PCOUT(45) => R1IN_2_2_ADD_1_PCOUT(45),
PCOUT(46) => R1IN_2_2_ADD_1_PCOUT(46),
PCOUT(47) => R1IN_2_2_ADD_1_PCOUT(47));
R1IN_4_4_ADD_1q270w: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 1,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => B(51),
A(1) => B(52),
A(2) => B(53),
A(3) => B(54),
A(4) => B(55),
A(5) => B(56),
A(6) => B(57),
A(7) => B(58),
A(8) => B(59),
A(9) => B(60),
A(10) => NN_1,
A(11) => NN_1,
A(12) => NN_1,
A(13) => NN_1,
A(14) => NN_1,
A(15) => NN_1,
A(16) => NN_1,
A(17) => NN_1,
B(0) => A(34),
B(1) => A(35),
B(2) => A(36),
B(3) => A(37),
B(4) => A(38),
B(5) => A(39),
B(6) => A(40),
B(7) => A(41),
B(8) => A(42),
B(9) => A(43),
B(10) => A(44),
B(11) => A(45),
B(12) => A(46),
B(13) => A(47),
B(14) => A(48),
B(15) => A(49),
B(16) => A(50),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => R1IN_4_4_2_0(0),
PCIN(1) => R1IN_4_4_2_0(1),
PCIN(2) => R1IN_4_4_2_0(2),
PCIN(3) => R1IN_4_4_2_0(3),
PCIN(4) => R1IN_4_4_2_0(4),
PCIN(5) => R1IN_4_4_2_0(5),
PCIN(6) => R1IN_4_4_2_0(6),
PCIN(7) => R1IN_4_4_2_0(7),
PCIN(8) => R1IN_4_4_2_0(8),
PCIN(9) => R1IN_4_4_2_0(9),
PCIN(10) => R1IN_4_4_2_0(10),
PCIN(11) => R1IN_4_4_2_0(11),
PCIN(12) => R1IN_4_4_2_0(12),
PCIN(13) => R1IN_4_4_2_0(13),
PCIN(14) => R1IN_4_4_2_0(14),
PCIN(15) => R1IN_4_4_2_0(15),
PCIN(16) => R1IN_4_4_2_0(16),
PCIN(17) => R1IN_4_4_2_0(17),
PCIN(18) => R1IN_4_4_2_0(18),
PCIN(19) => R1IN_4_4_2_0(19),
PCIN(20) => R1IN_4_4_2_0(20),
PCIN(21) => R1IN_4_4_2_0(21),
PCIN(22) => R1IN_4_4_2_0(22),
PCIN(23) => R1IN_4_4_2_0(23),
PCIN(24) => R1IN_4_4_2_0(24),
PCIN(25) => R1IN_4_4_2_0(25),
PCIN(26) => R1IN_4_4_2_0(26),
PCIN(27) => UC_103_0,
PCIN(28) => UC_104_0,
PCIN(29) => UC_105_0,
PCIN(30) => UC_106_0,
PCIN(31) => UC_107_0,
PCIN(32) => UC_108_0,
PCIN(33) => UC_109_0,
PCIN(34) => UC_110_0,
PCIN(35) => UC_111_0,
PCIN(36) => UC_112_0,
PCIN(37) => UC_113_0,
PCIN(38) => UC_114_0,
PCIN(39) => UC_115_0,
PCIN(40) => UC_116_0,
PCIN(41) => UC_117_0,
PCIN(42) => UC_118_0,
PCIN(43) => UC_119_0,
PCIN(44) => UC_120_0,
PCIN(45) => UC_121_0,
PCIN(46) => UC_122_0,
PCIN(47) => UC_123_0,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_2,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => EN,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_4_4_ADD_1_BCOUT(0),
BCOUT(1) => R1IN_4_4_ADD_1_BCOUT(1),
BCOUT(2) => R1IN_4_4_ADD_1_BCOUT(2),
BCOUT(3) => R1IN_4_4_ADD_1_BCOUT(3),
BCOUT(4) => R1IN_4_4_ADD_1_BCOUT(4),
BCOUT(5) => R1IN_4_4_ADD_1_BCOUT(5),
BCOUT(6) => R1IN_4_4_ADD_1_BCOUT(6),
BCOUT(7) => R1IN_4_4_ADD_1_BCOUT(7),
BCOUT(8) => R1IN_4_4_ADD_1_BCOUT(8),
BCOUT(9) => R1IN_4_4_ADD_1_BCOUT(9),
BCOUT(10) => R1IN_4_4_ADD_1_BCOUT(10),
BCOUT(11) => R1IN_4_4_ADD_1_BCOUT(11),
BCOUT(12) => R1IN_4_4_ADD_1_BCOUT(12),
BCOUT(13) => R1IN_4_4_ADD_1_BCOUT(13),
BCOUT(14) => R1IN_4_4_ADD_1_BCOUT(14),
BCOUT(15) => R1IN_4_4_ADD_1_BCOUT(15),
BCOUT(16) => R1IN_4_4_ADD_1_BCOUT(16),
BCOUT(17) => R1IN_4_4_ADD_1_BCOUT(17),
P(0) => R1IN_4_4_ADD_1F(0),
P(1) => R1IN_4_4_ADD_1F(1),
P(2) => R1IN_4_4_ADD_1F(2),
P(3) => R1IN_4_4_ADD_1F(3),
P(4) => R1IN_4_4_ADD_1F(4),
P(5) => R1IN_4_4_ADD_1F(5),
P(6) => R1IN_4_4_ADD_1F(6),
P(7) => R1IN_4_4_ADD_1F(7),
P(8) => R1IN_4_4_ADD_1F(8),
P(9) => R1IN_4_4_ADD_1F(9),
P(10) => R1IN_4_4_ADD_1F(10),
P(11) => R1IN_4_4_ADD_1F(11),
P(12) => R1IN_4_4_ADD_1F(12),
P(13) => R1IN_4_4_ADD_1F(13),
P(14) => R1IN_4_4_ADD_1F(14),
P(15) => R1IN_4_4_ADD_1F(15),
P(16) => R1IN_4_4_ADD_1F(16),
P(17) => R1IN_4_4_ADD_1F(17),
P(18) => R1IN_4_4_ADD_1F(18),
P(19) => R1IN_4_4_ADD_1F(19),
P(20) => R1IN_4_4_ADD_1F(20),
P(21) => R1IN_4_4_ADD_1F(21),
P(22) => R1IN_4_4_ADD_1F(22),
P(23) => R1IN_4_4_ADD_1F(23),
P(24) => R1IN_4_4_ADD_1F(24),
P(25) => R1IN_4_4_ADD_1F(25),
P(26) => R1IN_4_4_ADD_1F(26),
P(27) => R1IN_4_4_ADD_1F(27),
P(28) => UC,
P(29) => UC_0,
P(30) => UC_1,
P(31) => UC_2,
P(32) => UC_3,
P(33) => UC_4,
P(34) => UC_5,
P(35) => UC_6,
P(36) => UC_7,
P(37) => UC_8,
P(38) => UC_9,
P(39) => UC_10,
P(40) => UC_11,
P(41) => UC_12,
P(42) => UC_13,
P(43) => UC_14,
P(44) => UC_15,
P(45) => UC_16,
P(46) => UC_17,
P(47) => UC_18,
PCOUT(0) => R1IN_4_4_ADD_1_PCOUT(0),
PCOUT(1) => R1IN_4_4_ADD_1_PCOUT(1),
PCOUT(2) => R1IN_4_4_ADD_1_PCOUT(2),
PCOUT(3) => R1IN_4_4_ADD_1_PCOUT(3),
PCOUT(4) => R1IN_4_4_ADD_1_PCOUT(4),
PCOUT(5) => R1IN_4_4_ADD_1_PCOUT(5),
PCOUT(6) => R1IN_4_4_ADD_1_PCOUT(6),
PCOUT(7) => R1IN_4_4_ADD_1_PCOUT(7),
PCOUT(8) => R1IN_4_4_ADD_1_PCOUT(8),
PCOUT(9) => R1IN_4_4_ADD_1_PCOUT(9),
PCOUT(10) => R1IN_4_4_ADD_1_PCOUT(10),
PCOUT(11) => R1IN_4_4_ADD_1_PCOUT(11),
PCOUT(12) => R1IN_4_4_ADD_1_PCOUT(12),
PCOUT(13) => R1IN_4_4_ADD_1_PCOUT(13),
PCOUT(14) => R1IN_4_4_ADD_1_PCOUT(14),
PCOUT(15) => R1IN_4_4_ADD_1_PCOUT(15),
PCOUT(16) => R1IN_4_4_ADD_1_PCOUT(16),
PCOUT(17) => R1IN_4_4_ADD_1_PCOUT(17),
PCOUT(18) => R1IN_4_4_ADD_1_PCOUT(18),
PCOUT(19) => R1IN_4_4_ADD_1_PCOUT(19),
PCOUT(20) => R1IN_4_4_ADD_1_PCOUT(20),
PCOUT(21) => R1IN_4_4_ADD_1_PCOUT(21),
PCOUT(22) => R1IN_4_4_ADD_1_PCOUT(22),
PCOUT(23) => R1IN_4_4_ADD_1_PCOUT(23),
PCOUT(24) => R1IN_4_4_ADD_1_PCOUT(24),
PCOUT(25) => R1IN_4_4_ADD_1_PCOUT(25),
PCOUT(26) => R1IN_4_4_ADD_1_PCOUT(26),
PCOUT(27) => R1IN_4_4_ADD_1_PCOUT(27),
PCOUT(28) => R1IN_4_4_ADD_1_PCOUT(28),
PCOUT(29) => R1IN_4_4_ADD_1_PCOUT(29),
PCOUT(30) => R1IN_4_4_ADD_1_PCOUT(30),
PCOUT(31) => R1IN_4_4_ADD_1_PCOUT(31),
PCOUT(32) => R1IN_4_4_ADD_1_PCOUT(32),
PCOUT(33) => R1IN_4_4_ADD_1_PCOUT(33),
PCOUT(34) => R1IN_4_4_ADD_1_PCOUT(34),
PCOUT(35) => R1IN_4_4_ADD_1_PCOUT(35),
PCOUT(36) => R1IN_4_4_ADD_1_PCOUT(36),
PCOUT(37) => R1IN_4_4_ADD_1_PCOUT(37),
PCOUT(38) => R1IN_4_4_ADD_1_PCOUT(38),
PCOUT(39) => R1IN_4_4_ADD_1_PCOUT(39),
PCOUT(40) => R1IN_4_4_ADD_1_PCOUT(40),
PCOUT(41) => R1IN_4_4_ADD_1_PCOUT(41),
PCOUT(42) => R1IN_4_4_ADD_1_PCOUT(42),
PCOUT(43) => R1IN_4_4_ADD_1_PCOUT(43),
PCOUT(44) => R1IN_4_4_ADD_1_PCOUT(44),
PCOUT(45) => R1IN_4_4_ADD_1_PCOUT(45),
PCOUT(46) => R1IN_4_4_ADD_1_PCOUT(46),
PCOUT(47) => R1IN_4_4_ADD_1_PCOUT(47));
II_GND: GND port map (
G => NN_1);
II_VCC: VCC port map (
P => NN_2);
PRODUCT(17) <= NN_3;
end beh;
library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity virtex6_mul_61x61 is
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end virtex6_mul_61x61;
architecture beh of virtex6_mul_61x61 is
signal R1IN_3_2_1 : std_logic_vector(33 downto 17);
signal R1IN_3_2 : std_logic_vector(16 downto 0);
signal R1IN_2_2_1 : std_logic_vector(33 downto 17);
signal R1IN_2_2 : std_logic_vector(16 downto 0);
signal R1IN_4_4_2 : std_logic_vector(26 downto 0);
signal R1IN_3 : std_logic_vector(60 downto 17);
signal R1IN_2 : std_logic_vector(60 downto 17);
signal R1IN_ADD_1 : std_logic_vector(32 downto 0);
signal R1IN_4_4 : std_logic_vector(53 downto 17);
signal R1IN_4 : std_logic_vector(54 downto 17);
signal R1IN_4_3_1 : std_logic_vector(33 downto 17);
signal R1IN_4_3 : std_logic_vector(16 downto 0);
signal R1IN_4_ADD_1 : std_logic_vector(35 downto 1);
signal R1IN_4_2 : std_logic_vector(16 downto 0);
signal R1IN_4_2_1 : std_logic_vector(33 downto 17);
signal R1IN_4F : std_logic_vector(52 downto 0);
signal R1IN_4_1F : std_logic_vector(33 downto 17);
signal R1IN_4_4F : std_logic_vector(16 downto 0);
signal R1IN_4_2F : std_logic_vector(43 downto 1);
signal R1IN_4_3F : std_logic_vector(43 downto 0);
signal R1IN_1FF : std_logic_vector(33 downto 18);
signal R1IN_4FF : std_logic_vector(16 downto 0);
signal R1IN_ADD_1FF : std_logic_vector(32 downto 0);
signal R1IN_4_4_1F : std_logic_vector(33 downto 18);
signal R1IN_4_4_4F : std_logic_vector(19 downto 0);
signal R1IN_4_4_ADD_1F : std_logic_vector(27 downto 0);
signal R1IN_2F : std_logic_vector(16 downto 0);
signal R1IN_3F : std_logic_vector(16 downto 0);
signal R1IN_2_2F : std_logic_vector(43 downto 1);
signal R1IN_2_1F : std_logic_vector(33 downto 17);
signal R1IN_3_2F : std_logic_vector(43 downto 1);
signal R1IN_3_1F : std_logic_vector(33 downto 17);
signal R1IN_4_4_ADD_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_4_4_ADD_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_2_2_ADD_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_3_2_ADD_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_3_2_ADD_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_4_2_ADD_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_4_2_ADD_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_4_3_ADD_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_4_3_ADD_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_2_2_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_3_2_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_4_2_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_4_3_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_2_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_2_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_3_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_3_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_4_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_4_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_4_4_1_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_4_4_1_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_4_4_2_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_4_4_4_BCOUT : std_logic_vector(17 downto 0);
signal R1IN_4_4_4_PCOUT : std_logic_vector(47 downto 0);
signal R1IN_2_2_0 : std_logic_vector(16 downto 0);
signal R1IN_2_2_1_0 : std_logic_vector(33 downto 17);
signal R1IN_3_2_0 : std_logic_vector(16 downto 0);
signal R1IN_3_2_1_0 : std_logic_vector(33 downto 17);
signal R1IN_4_2_0 : std_logic_vector(16 downto 0);
signal R1IN_4_2_1_0 : std_logic_vector(33 downto 17);
signal R1IN_4_3_0 : std_logic_vector(16 downto 0);
signal R1IN_4_3_1_0 : std_logic_vector(33 downto 17);
signal R1IN_4_4_2_0 : std_logic_vector(26 downto 0);
signal B_0 : std_logic_vector(16 downto 0);
signal R1IN_3F_0 : std_logic_vector(16 downto 0);
signal R1IN_3_1F_0 : std_logic_vector(33 downto 17);
signal R1IN_2F_0 : std_logic_vector(16 downto 0);
signal R1IN_2_1F_0 : std_logic_vector(33 downto 17);
signal NN_1 : std_logic ;
signal NN_2 : std_logic ;
signal NN_12 : std_logic ;
signal R1IN_ADD_2_0 : std_logic ;
signal R1IN_4_4_ADD_2 : std_logic ;
signal R1IN_2_ADD_1 : std_logic ;
signal R1IN_3_ADD_1 : std_logic ;
signal UC : std_logic ;
signal UC_0 : std_logic ;
signal UC_1 : std_logic ;
signal UC_2 : std_logic ;
signal UC_3 : std_logic ;
signal UC_4 : std_logic ;
signal UC_5 : std_logic ;
signal UC_6 : std_logic ;
signal UC_7 : std_logic ;
signal UC_8 : std_logic ;
signal UC_9 : std_logic ;
signal UC_10 : std_logic ;
signal UC_11 : std_logic ;
signal UC_12 : std_logic ;
signal UC_13 : std_logic ;
signal UC_14 : std_logic ;
signal UC_15 : std_logic ;
signal UC_16 : std_logic ;
signal UC_17 : std_logic ;
signal UC_18 : std_logic ;
signal UC_19 : std_logic ;
signal UC_20 : std_logic ;
signal UC_21 : std_logic ;
signal UC_22 : std_logic ;
signal UC_23 : std_logic ;
signal UC_24 : std_logic ;
signal UC_25 : std_logic ;
signal UC_26 : std_logic ;
signal UC_27 : std_logic ;
signal UC_28 : std_logic ;
signal UC_29 : std_logic ;
signal UC_30 : std_logic ;
signal UC_31 : std_logic ;
signal UC_32 : std_logic ;
signal UC_33 : std_logic ;
signal UC_34 : std_logic ;
signal UC_35 : std_logic ;
signal UC_36 : std_logic ;
signal UC_37 : std_logic ;
signal UC_38 : std_logic ;
signal UC_39 : std_logic ;
signal UC_40 : std_logic ;
signal UC_41 : std_logic ;
signal UC_42 : std_logic ;
signal UC_43 : std_logic ;
signal UC_44 : std_logic ;
signal UC_45 : std_logic ;
signal UC_46 : std_logic ;
signal UC_47 : std_logic ;
signal UC_48 : std_logic ;
signal UC_49 : std_logic ;
signal UC_50 : std_logic ;
signal UC_51 : std_logic ;
signal UC_52 : std_logic ;
signal UC_53 : std_logic ;
signal UC_54 : std_logic ;
signal UC_55 : std_logic ;
signal UC_56 : std_logic ;
signal UC_57 : std_logic ;
signal UC_58 : std_logic ;
signal UC_59 : std_logic ;
signal UC_60 : std_logic ;
signal UC_61 : std_logic ;
signal UC_62 : std_logic ;
signal UC_63 : std_logic ;
signal UC_64 : std_logic ;
signal UC_65 : std_logic ;
signal UC_66 : std_logic ;
signal UC_67 : std_logic ;
signal UC_68 : std_logic ;
signal UC_69 : std_logic ;
signal UC_70 : std_logic ;
signal UC_71 : std_logic ;
signal UC_72 : std_logic ;
signal UC_73 : std_logic ;
signal UC_74 : std_logic ;
signal UC_75 : std_logic ;
signal UC_76 : std_logic ;
signal UC_77 : std_logic ;
signal UC_78 : std_logic ;
signal UC_79 : std_logic ;
signal UC_80 : std_logic ;
signal UC_81 : std_logic ;
signal UC_82 : std_logic ;
signal UC_83 : std_logic ;
signal UC_84 : std_logic ;
signal UC_85 : std_logic ;
signal UC_86 : std_logic ;
signal UC_87 : std_logic ;
signal UC_88 : std_logic ;
signal UC_89 : std_logic ;
signal UC_90 : std_logic ;
signal UC_91 : std_logic ;
signal UC_92 : std_logic ;
signal UC_93 : std_logic ;
signal UC_94 : std_logic ;
signal UC_95 : std_logic ;
signal UC_96 : std_logic ;
signal UC_97 : std_logic ;
signal UC_98 : std_logic ;
signal UC_99 : std_logic ;
signal UC_100 : std_logic ;
signal UC_101 : std_logic ;
signal UC_102 : std_logic ;
signal UC_103 : std_logic ;
signal UC_104 : std_logic ;
signal UC_105 : std_logic ;
signal UC_106 : std_logic ;
signal UC_107 : std_logic ;
signal UC_108 : std_logic ;
signal UC_109 : std_logic ;
signal UC_110 : std_logic ;
signal UC_111 : std_logic ;
signal UC_112 : std_logic ;
signal UC_113 : std_logic ;
signal UC_114 : std_logic ;
signal UC_115 : std_logic ;
signal UC_116 : std_logic ;
signal UC_117 : std_logic ;
signal UC_118 : std_logic ;
signal UC_119 : std_logic ;
signal UC_120 : std_logic ;
signal UC_121 : std_logic ;
signal UC_122 : std_logic ;
signal UC_123 : std_logic ;
signal UC_124 : std_logic ;
signal UC_125 : std_logic ;
signal UC_126 : std_logic ;
signal UC_127 : std_logic ;
signal UC_128 : std_logic ;
signal UC_129 : std_logic ;
signal UC_130 : std_logic ;
signal UC_131 : std_logic ;
signal UC_132 : std_logic ;
signal UC_133 : std_logic ;
signal UC_134 : std_logic ;
signal UC_135 : std_logic ;
signal UC_136 : std_logic ;
signal UC_137 : std_logic ;
signal UC_138 : std_logic ;
signal UC_139 : std_logic ;
signal UC_140 : std_logic ;
signal UC_141 : std_logic ;
signal UC_142 : std_logic ;
signal UC_143 : std_logic ;
signal UC_144 : std_logic ;
signal UC_145 : std_logic ;
signal UC_146 : std_logic ;
signal UC_147 : std_logic ;
signal UC_148 : std_logic ;
signal UC_149 : std_logic ;
signal UC_150 : std_logic ;
signal UC_151 : std_logic ;
signal UC_152 : std_logic ;
signal UC_153 : std_logic ;
signal UC_154 : std_logic ;
signal UC_155 : std_logic ;
signal UC_156 : std_logic ;
signal UC_157 : std_logic ;
signal UC_158 : std_logic ;
signal UC_159 : std_logic ;
signal UC_160 : std_logic ;
signal UC_161 : std_logic ;
signal UC_162 : std_logic ;
signal UC_163 : std_logic ;
signal UC_164 : std_logic ;
signal UC_165 : std_logic ;
signal UC_166 : std_logic ;
signal UC_167 : std_logic ;
signal UC_168 : std_logic ;
signal UC_169 : std_logic ;
signal UC_170 : std_logic ;
signal UC_171 : std_logic ;
signal UC_172 : std_logic ;
signal UC_201 : std_logic ;
signal UC_202 : std_logic ;
signal UC_203 : std_logic ;
signal UC_204 : std_logic ;
signal UC_205 : std_logic ;
signal UC_206 : std_logic ;
signal UC_207 : std_logic ;
signal UC_208 : std_logic ;
signal UC_209 : std_logic ;
signal UC_210 : std_logic ;
signal UC_211 : std_logic ;
signal UC_212 : std_logic ;
signal UC_213 : std_logic ;
signal UC_214 : std_logic ;
signal UC_215 : std_logic ;
signal UC_216 : std_logic ;
signal UC_217 : std_logic ;
signal UC_218 : std_logic ;
signal UC_219 : std_logic ;
signal UC_220 : std_logic ;
signal UC_221 : std_logic ;
signal UC_222 : std_logic ;
signal UC_223 : std_logic ;
signal UC_224 : std_logic ;
signal UC_225 : std_logic ;
signal UC_226 : std_logic ;
signal UC_227 : std_logic ;
signal UC_228 : std_logic ;
signal UC_229 : std_logic ;
signal UC_230 : std_logic ;
signal UC_231 : std_logic ;
signal UC_232 : std_logic ;
signal UC_233 : std_logic ;
signal UC_234 : std_logic ;
signal UC_235 : std_logic ;
signal UC_236 : std_logic ;
signal UC_237 : std_logic ;
signal UC_238 : std_logic ;
signal UC_239 : std_logic ;
signal UC_240 : std_logic ;
signal UC_241 : std_logic ;
signal UC_242 : std_logic ;
signal UC_243 : std_logic ;
signal UC_244 : std_logic ;
signal UC_245 : std_logic ;
signal UC_246 : std_logic ;
signal UC_247 : std_logic ;
signal UC_248 : std_logic ;
signal UC_249 : std_logic ;
signal UC_250 : std_logic ;
signal UC_251 : std_logic ;
signal UC_252 : std_logic ;
signal UC_253 : std_logic ;
signal UC_254 : std_logic ;
signal UC_255 : std_logic ;
signal UC_256 : std_logic ;
signal UC_257 : std_logic ;
signal UC_258 : std_logic ;
signal UC_259 : std_logic ;
signal UC_260 : std_logic ;
signal UC_261 : std_logic ;
signal UC_262 : std_logic ;
signal UC_263 : std_logic ;
signal UC_264 : std_logic ;
signal UC_265 : std_logic ;
signal UC_266 : std_logic ;
signal UC_267 : std_logic ;
signal UC_268 : std_logic ;
signal UC_269 : std_logic ;
signal UC_270 : std_logic ;
signal UC_271 : std_logic ;
signal UC_272 : std_logic ;
signal UC_273 : std_logic ;
signal UC_274 : std_logic ;
signal UC_275 : std_logic ;
signal UC_276 : std_logic ;
signal UC_277 : std_logic ;
signal UC_103_0 : std_logic ;
signal UC_104_0 : std_logic ;
signal UC_105_0 : std_logic ;
signal UC_106_0 : std_logic ;
signal UC_107_0 : std_logic ;
signal UC_108_0 : std_logic ;
signal UC_109_0 : std_logic ;
signal UC_110_0 : std_logic ;
signal UC_111_0 : std_logic ;
signal UC_112_0 : std_logic ;
signal UC_113_0 : std_logic ;
signal UC_114_0 : std_logic ;
signal UC_115_0 : std_logic ;
signal UC_116_0 : std_logic ;
signal UC_117_0 : std_logic ;
signal UC_118_0 : std_logic ;
signal UC_119_0 : std_logic ;
signal UC_120_0 : std_logic ;
signal UC_121_0 : std_logic ;
signal UC_122_0 : std_logic ;
signal UC_123_0 : std_logic ;
signal UC_124_0 : std_logic ;
signal UC_125_0 : std_logic ;
signal UC_126_0 : std_logic ;
signal UC_127_0 : std_logic ;
signal UC_128_0 : std_logic ;
signal UC_129_0 : std_logic ;
signal UC_130_0 : std_logic ;
signal UC_131_0 : std_logic ;
signal UC_132_0 : std_logic ;
signal UC_133_0 : std_logic ;
signal UC_134_0 : std_logic ;
signal UC_135_0 : std_logic ;
signal UC_136_0 : std_logic ;
signal UC_137_0 : std_logic ;
signal UC_138_0 : std_logic ;
signal UC_139_0 : std_logic ;
signal UC_140_0 : std_logic ;
signal UC_141_0 : std_logic ;
signal UC_142_0 : std_logic ;
signal UC_143_0 : std_logic ;
signal UC_144_0 : std_logic ;
signal UC_145_0 : std_logic ;
signal UC_146_0 : std_logic ;
signal UC_147_0 : std_logic ;
signal UC_148_0 : std_logic ;
signal UC_149_0 : std_logic ;
signal UC_150_0 : std_logic ;
signal UC_151_0 : std_logic ;
signal UC_152_0 : std_logic ;
signal UC_153_0 : std_logic ;
signal UC_154_0 : std_logic ;
signal UC_155_0 : std_logic ;
signal UC_156_0 : std_logic ;
signal UC_157_0 : std_logic ;
signal UC_158_0 : std_logic ;
signal UC_229_0 : std_logic ;
signal UC_230_0 : std_logic ;
signal UC_231_0 : std_logic ;
signal UC_232_0 : std_logic ;
signal UC_233_0 : std_logic ;
signal UC_234_0 : std_logic ;
signal UC_235_0 : std_logic ;
signal UC_236_0 : std_logic ;
signal UC_237_0 : std_logic ;
signal UC_238_0 : std_logic ;
signal UC_239_0 : std_logic ;
signal UC_240_0 : std_logic ;
signal UC_241_0 : std_logic ;
signal UC_242_0 : std_logic ;
signal UC_243_0 : std_logic ;
signal UC_244_0 : std_logic ;
signal UC_245_0 : std_logic ;
signal UC_246_0 : std_logic ;
signal UC_247_0 : std_logic ;
signal UC_248_0 : std_logic ;
signal UC_249_0 : std_logic ;
signal GND_0 : std_logic ;
signal R1IN_ADD_1_1_S_21 : std_logic ;
signal R1IN_ADD_1_1_S_22 : std_logic ;
signal R1IN_ADD_1_1_S_23 : std_logic ;
signal R1IN_ADD_1_1_S_24 : std_logic ;
signal R1IN_ADD_1_1_S_25 : std_logic ;
signal R1IN_ADD_1_1_S_26 : std_logic ;
signal R1IN_ADD_1_1_S_27 : std_logic ;
signal R1IN_ADD_1_1_S_28 : std_logic ;
signal R1IN_ADD_1_1_CRY_28 : std_logic ;
signal R1IN_ADD_2_0_CRY_52 : std_logic ;
signal R1IN_ADD_2_1_S_1 : std_logic ;
signal R1IN_ADD_2_1_S_2 : std_logic ;
signal R1IN_ADD_2_1_S_3 : std_logic ;
signal R1IN_ADD_2_1_S_4 : std_logic ;
signal R1IN_ADD_2_1_S_5 : std_logic ;
signal R1IN_ADD_2_1_S_6 : std_logic ;
signal R1IN_ADD_2_1_S_7 : std_logic ;
signal R1IN_ADD_2_1_S_8 : std_logic ;
signal R1IN_ADD_2_1_S_9 : std_logic ;
signal R1IN_ADD_2_1_S_10 : std_logic ;
signal R1IN_ADD_2_1_S_11 : std_logic ;
signal R1IN_ADD_2_1_S_12 : std_logic ;
signal R1IN_ADD_2_1_S_13 : std_logic ;
signal R1IN_ADD_2_1_S_14 : std_logic ;
signal R1IN_ADD_2_1_S_15 : std_logic ;
signal R1IN_ADD_2_1_S_16 : std_logic ;
signal R1IN_ADD_2_1_S_17 : std_logic ;
signal R1IN_ADD_2_1_S_18 : std_logic ;
signal R1IN_ADD_2_1_S_19 : std_logic ;
signal R1IN_ADD_2_1_S_20 : std_logic ;
signal R1IN_ADD_2_1_S_21 : std_logic ;
signal R1IN_ADD_2_1_S_22 : std_logic ;
signal R1IN_ADD_2_1_S_23 : std_logic ;
signal R1IN_ADD_2_1_S_24 : std_logic ;
signal R1IN_ADD_2_1_S_25 : std_logic ;
signal R1IN_ADD_2_1_S_26 : std_logic ;
signal R1IN_ADD_2_1_S_27 : std_logic ;
signal R1IN_ADD_2_1_S_28 : std_logic ;
signal R1IN_ADD_2_1_S_29 : std_logic ;
signal R1IN_ADD_2_1_S_30 : std_logic ;
signal R1IN_ADD_2_1_S_31 : std_logic ;
signal R1IN_ADD_2_1_S_32 : std_logic ;
signal R1IN_ADD_2_1_S_33 : std_logic ;
signal R1IN_ADD_2_1_S_34 : std_logic ;
signal R1IN_ADD_2_1_S_35 : std_logic ;
signal R1IN_ADD_2_1_S_36 : std_logic ;
signal R1IN_ADD_2_1_S_37 : std_logic ;
signal R1IN_ADD_2_1_S_38 : std_logic ;
signal R1IN_ADD_2_1_S_39 : std_logic ;
signal R1IN_ADD_2_1_S_40 : std_logic ;
signal R1IN_ADD_2_1_S_41 : std_logic ;
signal R1IN_ADD_2_1_S_42 : std_logic ;
signal R1IN_ADD_2_1_S_43 : std_logic ;
signal R1IN_ADD_2_1_S_44 : std_logic ;
signal R1IN_ADD_2_1_S_45 : std_logic ;
signal R1IN_ADD_2_1_S_46 : std_logic ;
signal R1IN_ADD_2_1_S_47 : std_logic ;
signal R1IN_ADD_2_1_S_48 : std_logic ;
signal R1IN_ADD_2_1_S_49 : std_logic ;
signal R1IN_ADD_2_1_S_50 : std_logic ;
signal R1IN_ADD_2_1_S_51 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_0 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_1 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_1 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_2 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_2 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_3 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_3 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_4 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_4 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_5 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_5 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_6 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_6 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_7 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_7 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_8 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_8 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_9 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_9 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_10 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_10 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_11 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_11 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_12 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_12 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_13 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_13 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_14 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_14 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_15 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_15 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_16 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_16 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_17 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_17 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_18 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_18 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_19 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_19 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_20 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_20 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_21 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_21 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_22 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_22 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_23 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_23 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_24 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_24 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_25 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_25 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_26 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_26 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_27 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_27 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_28 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_28 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_29 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_29 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_30 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_30 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_31 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_31 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_32 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_32 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_33 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_33 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_34 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_34 : std_logic ;
signal R1IN_4_ADD_2_0_AXB_35 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_0 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_1 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_1 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_2 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_2 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_3 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_3 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_4 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_4 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_5 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_5 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_6 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_6 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_7 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_7 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_8 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_8 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_9 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_9 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_10 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_10 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_11 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_11 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_12 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_12 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_13 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_13 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_14 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_14 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_15 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_15 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_16 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_16 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_17 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_17 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_18 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_18 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_19 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_19 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_20 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_20 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_21 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_21 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_22 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_22 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_23 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_23 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_24 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_24 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_25 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_25 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_26 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_26 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_27 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_27 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_28 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_28 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_29 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_29 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_30 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_30 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_31 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_31 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_32 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_32 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_33 : std_logic ;
signal R1IN_4_ADD_2_1_CRY_33 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_34 : std_logic ;
signal R1IN_ADD_2_0_CRY_0 : std_logic ;
signal R1IN_ADD_2_0_AXB_1 : std_logic ;
signal R1IN_ADD_2_0_CRY_1 : std_logic ;
signal R1IN_ADD_2_0_AXB_2 : std_logic ;
signal R1IN_ADD_2_0_CRY_2 : std_logic ;
signal R1IN_ADD_2_0_AXB_3 : std_logic ;
signal R1IN_ADD_2_0_CRY_3 : std_logic ;
signal R1IN_ADD_2_0_AXB_4 : std_logic ;
signal R1IN_ADD_2_0_CRY_4 : std_logic ;
signal R1IN_ADD_2_0_AXB_5 : std_logic ;
signal R1IN_ADD_2_0_CRY_5 : std_logic ;
signal R1IN_ADD_2_0_AXB_6 : std_logic ;
signal R1IN_ADD_2_0_CRY_6 : std_logic ;
signal R1IN_ADD_2_0_AXB_7 : std_logic ;
signal R1IN_ADD_2_0_CRY_7 : std_logic ;
signal R1IN_ADD_2_0_AXB_8 : std_logic ;
signal R1IN_ADD_2_0_CRY_8 : std_logic ;
signal R1IN_ADD_2_0_AXB_9 : std_logic ;
signal R1IN_ADD_2_0_CRY_9 : std_logic ;
signal R1IN_ADD_2_0_AXB_10 : std_logic ;
signal R1IN_ADD_2_0_CRY_10 : std_logic ;
signal R1IN_ADD_2_0_AXB_11 : std_logic ;
signal R1IN_ADD_2_0_CRY_11 : std_logic ;
signal R1IN_ADD_2_0_AXB_12 : std_logic ;
signal R1IN_ADD_2_0_CRY_12 : std_logic ;
signal R1IN_ADD_2_0_AXB_13 : std_logic ;
signal R1IN_ADD_2_0_CRY_13 : std_logic ;
signal R1IN_ADD_2_0_AXB_14 : std_logic ;
signal R1IN_ADD_2_0_CRY_14 : std_logic ;
signal R1IN_ADD_2_0_AXB_15 : std_logic ;
signal R1IN_ADD_2_0_CRY_15 : std_logic ;
signal R1IN_ADD_2_0_AXB_16 : std_logic ;
signal R1IN_ADD_2_0_CRY_16 : std_logic ;
signal R1IN_ADD_2_0_AXB_17 : std_logic ;
signal R1IN_ADD_2_0_CRY_17 : std_logic ;
signal R1IN_ADD_2_0_AXB_18 : std_logic ;
signal R1IN_ADD_2_0_CRY_18 : std_logic ;
signal R1IN_ADD_2_0_AXB_19 : std_logic ;
signal R1IN_ADD_2_0_CRY_19 : std_logic ;
signal R1IN_ADD_2_0_AXB_20 : std_logic ;
signal R1IN_ADD_2_0_CRY_20 : std_logic ;
signal R1IN_ADD_2_0_AXB_21 : std_logic ;
signal R1IN_ADD_2_0_CRY_21 : std_logic ;
signal R1IN_ADD_2_0_AXB_22 : std_logic ;
signal R1IN_ADD_2_0_CRY_22 : std_logic ;
signal R1IN_ADD_2_0_AXB_23 : std_logic ;
signal R1IN_ADD_2_0_CRY_23 : std_logic ;
signal R1IN_ADD_2_0_AXB_24 : std_logic ;
signal R1IN_ADD_2_0_CRY_24 : std_logic ;
signal R1IN_ADD_2_0_AXB_25 : std_logic ;
signal R1IN_ADD_2_0_CRY_25 : std_logic ;
signal R1IN_ADD_2_0_AXB_26 : std_logic ;
signal R1IN_ADD_2_0_CRY_26 : std_logic ;
signal R1IN_ADD_2_0_AXB_27 : std_logic ;
signal R1IN_ADD_2_0_CRY_27 : std_logic ;
signal R1IN_ADD_2_0_AXB_28 : std_logic ;
signal R1IN_ADD_2_0_CRY_28 : std_logic ;
signal R1IN_ADD_2_0_AXB_29 : std_logic ;
signal R1IN_ADD_2_0_CRY_29 : std_logic ;
signal R1IN_ADD_2_0_AXB_30 : std_logic ;
signal R1IN_ADD_2_0_CRY_30 : std_logic ;
signal R1IN_ADD_2_0_AXB_31 : std_logic ;
signal R1IN_ADD_2_0_CRY_31 : std_logic ;
signal R1IN_ADD_2_0_AXB_32 : std_logic ;
signal R1IN_ADD_2_0_CRY_32 : std_logic ;
signal R1IN_ADD_2_0_AXB_33 : std_logic ;
signal R1IN_ADD_2_0_CRY_33 : std_logic ;
signal R1IN_ADD_2_0_AXB_34 : std_logic ;
signal R1IN_ADD_2_0_CRY_34 : std_logic ;
signal R1IN_ADD_2_0_AXB_35 : std_logic ;
signal R1IN_ADD_2_0_CRY_35 : std_logic ;
signal R1IN_ADD_2_0_AXB_36 : std_logic ;
signal R1IN_ADD_2_0_CRY_36 : std_logic ;
signal R1IN_ADD_2_0_AXB_37 : std_logic ;
signal R1IN_ADD_2_0_CRY_37 : std_logic ;
signal R1IN_ADD_2_0_AXB_38 : std_logic ;
signal R1IN_ADD_2_0_CRY_38 : std_logic ;
signal R1IN_ADD_2_0_AXB_39 : std_logic ;
signal R1IN_ADD_2_0_CRY_39 : std_logic ;
signal R1IN_ADD_2_0_AXB_40 : std_logic ;
signal R1IN_ADD_2_0_CRY_40 : std_logic ;
signal R1IN_ADD_2_0_AXB_41 : std_logic ;
signal R1IN_ADD_2_0_CRY_41 : std_logic ;
signal R1IN_ADD_2_0_AXB_42 : std_logic ;
signal R1IN_ADD_2_0_CRY_42 : std_logic ;
signal R1IN_ADD_2_0_AXB_43 : std_logic ;
signal R1IN_ADD_2_0_CRY_43 : std_logic ;
signal R1IN_ADD_2_0_AXB_44 : std_logic ;
signal R1IN_ADD_2_0_CRY_44 : std_logic ;
signal R1IN_ADD_2_0_AXB_45 : std_logic ;
signal R1IN_ADD_2_0_CRY_45 : std_logic ;
signal R1IN_ADD_2_0_AXB_46 : std_logic ;
signal R1IN_ADD_2_0_CRY_46 : std_logic ;
signal R1IN_ADD_2_0_AXB_47 : std_logic ;
signal R1IN_ADD_2_0_CRY_47 : std_logic ;
signal R1IN_ADD_2_0_AXB_48 : std_logic ;
signal R1IN_ADD_2_0_CRY_48 : std_logic ;
signal R1IN_ADD_2_0_AXB_49 : std_logic ;
signal R1IN_ADD_2_0_CRY_49 : std_logic ;
signal R1IN_ADD_2_0_AXB_50 : std_logic ;
signal R1IN_ADD_2_0_CRY_50 : std_logic ;
signal R1IN_ADD_2_0_AXB_51 : std_logic ;
signal R1IN_ADD_2_0_CRY_51 : std_logic ;
signal R1IN_ADD_2_0_AXB_52 : std_logic ;
signal R1IN_ADD_2_1_AXB_0 : std_logic ;
signal R1IN_ADD_2_1_CRY_0 : std_logic ;
signal R1IN_ADD_2_1_AXB_1 : std_logic ;
signal R1IN_ADD_2_1_CRY_1 : std_logic ;
signal R1IN_ADD_2_1_AXB_2 : std_logic ;
signal R1IN_ADD_2_1_CRY_2 : std_logic ;
signal R1IN_ADD_2_1_AXB_3 : std_logic ;
signal R1IN_ADD_2_1_CRY_3 : std_logic ;
signal R1IN_ADD_2_1_AXB_4 : std_logic ;
signal R1IN_ADD_2_1_CRY_4 : std_logic ;
signal R1IN_ADD_2_1_AXB_5 : std_logic ;
signal R1IN_ADD_2_1_CRY_5 : std_logic ;
signal R1IN_ADD_2_1_AXB_6 : std_logic ;
signal R1IN_ADD_2_1_CRY_6 : std_logic ;
signal R1IN_ADD_2_1_AXB_7 : std_logic ;
signal R1IN_ADD_2_1_CRY_7 : std_logic ;
signal R1IN_ADD_2_1_AXB_8 : std_logic ;
signal R1IN_ADD_2_1_CRY_8 : std_logic ;
signal R1IN_ADD_2_1_AXB_9 : std_logic ;
signal R1IN_ADD_2_1_CRY_9 : std_logic ;
signal R1IN_ADD_2_1_AXB_10 : std_logic ;
signal R1IN_ADD_2_1_CRY_10 : std_logic ;
signal R1IN_ADD_2_1_AXB_11 : std_logic ;
signal R1IN_ADD_2_1_CRY_11 : std_logic ;
signal R1IN_ADD_2_1_AXB_12 : std_logic ;
signal R1IN_ADD_2_1_CRY_12 : std_logic ;
signal R1IN_ADD_2_1_AXB_13 : std_logic ;
signal R1IN_ADD_2_1_CRY_13 : std_logic ;
signal R1IN_ADD_2_1_AXB_14 : std_logic ;
signal R1IN_ADD_2_1_CRY_14 : std_logic ;
signal R1IN_ADD_2_1_AXB_15 : std_logic ;
signal R1IN_ADD_2_1_CRY_15 : std_logic ;
signal R1IN_ADD_2_1_AXB_16 : std_logic ;
signal R1IN_ADD_2_1_CRY_16 : std_logic ;
signal R1IN_ADD_2_1_AXB_17 : std_logic ;
signal R1IN_ADD_2_1_CRY_17 : std_logic ;
signal R1IN_ADD_2_1_AXB_18 : std_logic ;
signal R1IN_ADD_2_1_CRY_18 : std_logic ;
signal R1IN_ADD_2_1_AXB_19 : std_logic ;
signal R1IN_ADD_2_1_CRY_19 : std_logic ;
signal R1IN_ADD_2_1_AXB_20 : std_logic ;
signal R1IN_ADD_2_1_CRY_20 : std_logic ;
signal R1IN_ADD_2_1_AXB_21 : std_logic ;
signal R1IN_ADD_2_1_CRY_21 : std_logic ;
signal R1IN_ADD_2_1_AXB_22 : std_logic ;
signal R1IN_ADD_2_1_CRY_22 : std_logic ;
signal R1IN_ADD_2_1_AXB_23 : std_logic ;
signal R1IN_ADD_2_1_CRY_23 : std_logic ;
signal R1IN_ADD_2_1_AXB_24 : std_logic ;
signal R1IN_ADD_2_1_CRY_24 : std_logic ;
signal R1IN_ADD_2_1_AXB_25 : std_logic ;
signal R1IN_ADD_2_1_CRY_25 : std_logic ;
signal R1IN_ADD_2_1_AXB_26 : std_logic ;
signal R1IN_ADD_2_1_CRY_26 : std_logic ;
signal R1IN_ADD_2_1_AXB_27 : std_logic ;
signal R1IN_ADD_2_1_CRY_27 : std_logic ;
signal R1IN_ADD_2_1_AXB_28 : std_logic ;
signal R1IN_ADD_2_1_CRY_28 : std_logic ;
signal R1IN_ADD_2_1_AXB_29 : std_logic ;
signal R1IN_ADD_2_1_CRY_29 : std_logic ;
signal R1IN_ADD_2_1_AXB_30 : std_logic ;
signal R1IN_ADD_2_1_CRY_30 : std_logic ;
signal R1IN_ADD_2_1_AXB_31 : std_logic ;
signal R1IN_ADD_2_1_CRY_31 : std_logic ;
signal R1IN_ADD_2_1_AXB_32 : std_logic ;
signal R1IN_ADD_2_1_CRY_32 : std_logic ;
signal R1IN_ADD_2_1_AXB_33 : std_logic ;
signal R1IN_ADD_2_1_CRY_33 : std_logic ;
signal R1IN_ADD_2_1_AXB_34 : std_logic ;
signal R1IN_ADD_2_1_CRY_34 : std_logic ;
signal R1IN_ADD_2_1_AXB_35 : std_logic ;
signal R1IN_ADD_2_1_CRY_35 : std_logic ;
signal R1IN_ADD_2_1_AXB_36 : std_logic ;
signal R1IN_ADD_2_1_CRY_36 : std_logic ;
signal R1IN_ADD_2_1_AXB_37 : std_logic ;
signal R1IN_ADD_2_1_CRY_37 : std_logic ;
signal R1IN_ADD_2_1_AXB_38 : std_logic ;
signal R1IN_ADD_2_1_CRY_38 : std_logic ;
signal R1IN_ADD_2_1_AXB_39 : std_logic ;
signal R1IN_ADD_2_1_CRY_39 : std_logic ;
signal R1IN_ADD_2_1_AXB_40 : std_logic ;
signal R1IN_ADD_2_1_CRY_40 : std_logic ;
signal R1IN_ADD_2_1_AXB_41 : std_logic ;
signal R1IN_ADD_2_1_CRY_41 : std_logic ;
signal R1IN_ADD_2_1_AXB_42 : std_logic ;
signal R1IN_ADD_2_1_CRY_42 : std_logic ;
signal R1IN_ADD_2_1_AXB_43 : std_logic ;
signal R1IN_ADD_2_1_CRY_43 : std_logic ;
signal R1IN_ADD_2_1_AXB_44 : std_logic ;
signal R1IN_ADD_2_1_CRY_44 : std_logic ;
signal R1IN_ADD_2_1_AXB_45 : std_logic ;
signal R1IN_ADD_2_1_CRY_45 : std_logic ;
signal R1IN_ADD_2_1_AXB_46 : std_logic ;
signal R1IN_ADD_2_1_CRY_46 : std_logic ;
signal R1IN_ADD_2_1_AXB_47 : std_logic ;
signal R1IN_ADD_2_1_CRY_47 : std_logic ;
signal R1IN_ADD_2_1_AXB_48 : std_logic ;
signal R1IN_ADD_2_1_CRY_48 : std_logic ;
signal R1IN_ADD_2_1_AXB_49 : std_logic ;
signal R1IN_ADD_2_1_CRY_49 : std_logic ;
signal R1IN_ADD_2_1_AXB_50 : std_logic ;
signal R1IN_ADD_2_1_CRY_50 : std_logic ;
signal R1IN_ADD_2_1_AXB_51 : std_logic ;
signal R1IN_ADD_2_1_0_S_1 : std_logic ;
signal R1IN_ADD_2_1_0_S_2 : std_logic ;
signal R1IN_ADD_2_1_0_S_3 : std_logic ;
signal R1IN_ADD_2_1_0_S_4 : std_logic ;
signal R1IN_ADD_2_1_0_S_5 : std_logic ;
signal R1IN_ADD_2_1_0_S_6 : std_logic ;
signal R1IN_ADD_2_1_0_S_7 : std_logic ;
signal R1IN_ADD_2_1_0_S_8 : std_logic ;
signal R1IN_ADD_2_1_0_S_9 : std_logic ;
signal R1IN_ADD_2_1_0_S_10 : std_logic ;
signal R1IN_ADD_2_1_0_S_11 : std_logic ;
signal R1IN_ADD_2_1_0_S_12 : std_logic ;
signal R1IN_ADD_2_1_0_S_13 : std_logic ;
signal R1IN_ADD_2_1_0_S_14 : std_logic ;
signal R1IN_ADD_2_1_0_S_15 : std_logic ;
signal R1IN_ADD_2_1_0_S_16 : std_logic ;
signal R1IN_ADD_2_1_0_S_17 : std_logic ;
signal R1IN_ADD_2_1_0_S_18 : std_logic ;
signal R1IN_ADD_2_1_0_S_19 : std_logic ;
signal R1IN_ADD_2_1_0_S_20 : std_logic ;
signal R1IN_ADD_2_1_0_S_21 : std_logic ;
signal R1IN_ADD_2_1_0_S_22 : std_logic ;
signal R1IN_ADD_2_1_0_S_23 : std_logic ;
signal R1IN_ADD_2_1_0_S_24 : std_logic ;
signal R1IN_ADD_2_1_0_S_25 : std_logic ;
signal R1IN_ADD_2_1_0_S_26 : std_logic ;
signal R1IN_ADD_2_1_0_S_27 : std_logic ;
signal R1IN_ADD_2_1_0_S_28 : std_logic ;
signal R1IN_ADD_2_1_0_S_29 : std_logic ;
signal R1IN_ADD_2_1_0_S_30 : std_logic ;
signal R1IN_ADD_2_1_0_S_31 : std_logic ;
signal R1IN_ADD_2_1_0_S_32 : std_logic ;
signal R1IN_ADD_2_1_0_S_33 : std_logic ;
signal R1IN_ADD_2_1_0_S_34 : std_logic ;
signal R1IN_ADD_2_1_0_S_35 : std_logic ;
signal R1IN_ADD_2_1_0_S_36 : std_logic ;
signal R1IN_ADD_2_1_0_S_37 : std_logic ;
signal R1IN_ADD_2_1_0_S_38 : std_logic ;
signal R1IN_ADD_2_1_0_S_39 : std_logic ;
signal R1IN_ADD_2_1_0_S_40 : std_logic ;
signal R1IN_ADD_2_1_0_S_41 : std_logic ;
signal R1IN_ADD_2_1_0_S_42 : std_logic ;
signal R1IN_ADD_2_1_0_S_43 : std_logic ;
signal R1IN_ADD_2_1_0_S_44 : std_logic ;
signal R1IN_ADD_2_1_0_S_45 : std_logic ;
signal R1IN_ADD_2_1_0_S_46 : std_logic ;
signal R1IN_ADD_2_1_0_S_47 : std_logic ;
signal R1IN_ADD_2_1_0_S_48 : std_logic ;
signal R1IN_ADD_2_1_0_S_49 : std_logic ;
signal R1IN_ADD_2_1_0_S_50 : std_logic ;
signal R1IN_ADD_2_1_0_S_51 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_0 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_0 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_1 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_1 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_2 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_2 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_3 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_3 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_4 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_4 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_5 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_5 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_6 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_6 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_7 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_7 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_8 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_8 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_9 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_9 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_10 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_10 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_11 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_11 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_12 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_12 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_13 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_13 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_14 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_14 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_15 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_15 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_16 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_16 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_17 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_17 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_18 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_18 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_19 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_19 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_20 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_20 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_21 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_21 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_22 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_22 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_23 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_23 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_24 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_24 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_25 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_25 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_26 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_26 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_27 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_27 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_28 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_28 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_29 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_29 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_30 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_30 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_31 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_31 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_32 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_32 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_33 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_33 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_34 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_34 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_35 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_35 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_36 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_36 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_37 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_37 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_38 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_38 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_39 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_39 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_40 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_40 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_41 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_41 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_42 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_42 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_43 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_43 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_44 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_44 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_45 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_45 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_46 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_46 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_47 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_47 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_48 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_48 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_49 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_49 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_50 : std_logic ;
signal R1IN_ADD_2_1_0_CRY_50 : std_logic ;
signal R1IN_ADD_2_1_0_AXB_51 : std_logic ;
signal R1IN_ADD_1_0_CRY_0 : std_logic ;
signal R1IN_ADD_1_0_AXB_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_1 : std_logic ;
signal R1IN_ADD_1_0_AXB_2 : std_logic ;
signal R1IN_ADD_1_0_CRY_2 : std_logic ;
signal R1IN_ADD_1_0_AXB_3 : std_logic ;
signal R1IN_ADD_1_0_CRY_3 : std_logic ;
signal R1IN_ADD_1_0_AXB_4 : std_logic ;
signal R1IN_ADD_1_0_CRY_4 : std_logic ;
signal R1IN_ADD_1_0_AXB_5 : std_logic ;
signal R1IN_ADD_1_0_CRY_5 : std_logic ;
signal R1IN_ADD_1_0_AXB_6 : std_logic ;
signal R1IN_ADD_1_0_CRY_6 : std_logic ;
signal R1IN_ADD_1_0_AXB_7 : std_logic ;
signal R1IN_ADD_1_0_CRY_7 : std_logic ;
signal R1IN_ADD_1_0_AXB_8 : std_logic ;
signal R1IN_ADD_1_0_CRY_8 : std_logic ;
signal R1IN_ADD_1_0_AXB_9 : std_logic ;
signal R1IN_ADD_1_0_CRY_9 : std_logic ;
signal R1IN_ADD_1_0_AXB_10 : std_logic ;
signal R1IN_ADD_1_0_CRY_10 : std_logic ;
signal R1IN_ADD_1_0_AXB_11 : std_logic ;
signal R1IN_ADD_1_0_CRY_11 : std_logic ;
signal R1IN_ADD_1_0_AXB_12 : std_logic ;
signal R1IN_ADD_1_0_CRY_12 : std_logic ;
signal R1IN_ADD_1_0_AXB_13 : std_logic ;
signal R1IN_ADD_1_0_CRY_13 : std_logic ;
signal R1IN_ADD_1_0_AXB_14 : std_logic ;
signal R1IN_ADD_1_0_CRY_14 : std_logic ;
signal R1IN_ADD_1_0_AXB_15 : std_logic ;
signal R1IN_ADD_1_0_CRY_15 : std_logic ;
signal R1IN_ADD_1_0_AXB_16 : std_logic ;
signal R1IN_ADD_1_0_CRY_16 : std_logic ;
signal R1IN_ADD_1_0_AXB_17 : std_logic ;
signal R1IN_ADD_1_0_CRY_17 : std_logic ;
signal R1IN_ADD_1_0_AXB_18 : std_logic ;
signal R1IN_ADD_1_0_CRY_18 : std_logic ;
signal R1IN_ADD_1_0_AXB_19 : std_logic ;
signal R1IN_ADD_1_0_CRY_19 : std_logic ;
signal R1IN_ADD_1_0_AXB_20 : std_logic ;
signal R1IN_ADD_1_0_CRY_20 : std_logic ;
signal R1IN_ADD_1_0_AXB_21 : std_logic ;
signal R1IN_ADD_1_0_CRY_21 : std_logic ;
signal R1IN_ADD_1_0_AXB_22 : std_logic ;
signal R1IN_ADD_1_0_CRY_22 : std_logic ;
signal R1IN_ADD_1_0_AXB_23 : std_logic ;
signal R1IN_ADD_1_0_CRY_23 : std_logic ;
signal R1IN_ADD_1_0_AXB_24 : std_logic ;
signal R1IN_ADD_1_0_CRY_24 : std_logic ;
signal R1IN_ADD_1_0_AXB_25 : std_logic ;
signal R1IN_ADD_1_0_CRY_25 : std_logic ;
signal R1IN_ADD_1_0_AXB_26 : std_logic ;
signal R1IN_ADD_1_0_CRY_26 : std_logic ;
signal R1IN_ADD_1_0_AXB_27 : std_logic ;
signal R1IN_ADD_1_0_CRY_27 : std_logic ;
signal R1IN_ADD_1_0_AXB_28 : std_logic ;
signal R1IN_ADD_1_0_CRY_28 : std_logic ;
signal R1IN_ADD_1_0_AXB_29 : std_logic ;
signal R1IN_ADD_1_0_CRY_29 : std_logic ;
signal R1IN_ADD_1_0_AXB_30 : std_logic ;
signal R1IN_ADD_1_0_CRY_30 : std_logic ;
signal R1IN_ADD_1_0_AXB_31 : std_logic ;
signal R1IN_ADD_1_1_AXB_0 : std_logic ;
signal R1IN_ADD_1_1_CRY_0 : std_logic ;
signal R1IN_ADD_1_1_AXB_1 : std_logic ;
signal R1IN_ADD_1_1_CRY_1 : std_logic ;
signal R1IN_ADD_1_1_AXB_2 : std_logic ;
signal R1IN_ADD_1_1_CRY_2 : std_logic ;
signal R1IN_ADD_1_1_AXB_3 : std_logic ;
signal R1IN_ADD_1_1_CRY_3 : std_logic ;
signal R1IN_ADD_1_1_AXB_4 : std_logic ;
signal R1IN_ADD_1_1_CRY_4 : std_logic ;
signal R1IN_ADD_1_1_AXB_5 : std_logic ;
signal R1IN_ADD_1_1_CRY_5 : std_logic ;
signal R1IN_ADD_1_1_AXB_6 : std_logic ;
signal R1IN_ADD_1_1_CRY_6 : std_logic ;
signal R1IN_ADD_1_1_AXB_7 : std_logic ;
signal R1IN_ADD_1_1_CRY_7 : std_logic ;
signal R1IN_ADD_1_1_AXB_8 : std_logic ;
signal R1IN_ADD_1_1_CRY_8 : std_logic ;
signal R1IN_ADD_1_1_AXB_9 : std_logic ;
signal R1IN_ADD_1_1_CRY_9 : std_logic ;
signal R1IN_ADD_1_1_AXB_10 : std_logic ;
signal R1IN_ADD_1_1_CRY_10 : std_logic ;
signal R1IN_ADD_1_1_AXB_11 : std_logic ;
signal R1IN_ADD_1_1_CRY_11 : std_logic ;
signal R1IN_ADD_1_1_AXB_12 : std_logic ;
signal R1IN_ADD_1_1_CRY_12 : std_logic ;
signal R1IN_ADD_1_1_AXB_13 : std_logic ;
signal R1IN_ADD_1_1_CRY_13 : std_logic ;
signal R1IN_ADD_1_1_AXB_14 : std_logic ;
signal R1IN_ADD_1_1_CRY_14 : std_logic ;
signal R1IN_ADD_1_1_AXB_15 : std_logic ;
signal R1IN_ADD_1_1_CRY_15 : std_logic ;
signal R1IN_ADD_1_1_AXB_16 : std_logic ;
signal R1IN_ADD_1_1_CRY_16 : std_logic ;
signal R1IN_ADD_1_1_AXB_17 : std_logic ;
signal R1IN_ADD_1_1_CRY_17 : std_logic ;
signal R1IN_ADD_1_1_AXB_18 : std_logic ;
signal R1IN_ADD_1_1_CRY_18 : std_logic ;
signal R1IN_ADD_1_1_AXB_19 : std_logic ;
signal R1IN_ADD_1_1_CRY_19 : std_logic ;
signal R1IN_ADD_1_1_AXB_20 : std_logic ;
signal R1IN_ADD_1_1_CRY_20 : std_logic ;
signal R1IN_ADD_1_1_AXB_21 : std_logic ;
signal R1IN_ADD_1_1_CRY_21 : std_logic ;
signal R1IN_ADD_1_1_AXB_22 : std_logic ;
signal R1IN_ADD_1_1_CRY_22 : std_logic ;
signal R1IN_ADD_1_1_AXB_23 : std_logic ;
signal R1IN_ADD_1_1_CRY_23 : std_logic ;
signal R1IN_ADD_1_1_AXB_24 : std_logic ;
signal R1IN_ADD_1_1_CRY_24 : std_logic ;
signal R1IN_ADD_1_1_AXB_25 : std_logic ;
signal R1IN_ADD_1_1_CRY_25 : std_logic ;
signal R1IN_ADD_1_1_AXB_26 : std_logic ;
signal R1IN_ADD_1_1_CRY_26 : std_logic ;
signal R1IN_ADD_1_1_AXB_27 : std_logic ;
signal R1IN_ADD_1_1_CRY_27 : std_logic ;
signal R1IN_ADD_1_1_AXB_28 : std_logic ;
signal R1IN_ADD_1_1_0_S_21 : std_logic ;
signal R1IN_ADD_1_1_0_S_22 : std_logic ;
signal R1IN_ADD_1_1_0_S_23 : std_logic ;
signal R1IN_ADD_1_1_0_S_24 : std_logic ;
signal R1IN_ADD_1_1_0_S_25 : std_logic ;
signal R1IN_ADD_1_1_0_S_26 : std_logic ;
signal R1IN_ADD_1_1_0_S_27 : std_logic ;
signal R1IN_ADD_1_1_0_S_28 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_28 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_0 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_0 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_1 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_1 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_2 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_2 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_3 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_3 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_4 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_4 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_5 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_5 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_6 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_6 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_7 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_7 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_8 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_8 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_9 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_9 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_10 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_10 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_11 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_11 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_12 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_12 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_13 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_13 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_14 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_14 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_15 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_15 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_16 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_16 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_17 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_17 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_18 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_18 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_19 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_19 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_20 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_20 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_21 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_21 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_22 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_22 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_23 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_23 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_24 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_24 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_25 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_25 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_26 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_26 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_27 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_27 : std_logic ;
signal R1IN_ADD_1_1_0_AXB_28 : std_logic ;
signal R1IN_3_ADD_1_CRY_0 : std_logic ;
signal R1IN_3_ADD_1_AXB_1 : std_logic ;
signal R1IN_3_ADD_1_CRY_1 : std_logic ;
signal R1IN_3_ADD_1_AXB_2 : std_logic ;
signal R1IN_3_ADD_1_CRY_2 : std_logic ;
signal R1IN_3_ADD_1_AXB_3 : std_logic ;
signal R1IN_3_ADD_1_CRY_3 : std_logic ;
signal R1IN_3_ADD_1_AXB_4 : std_logic ;
signal R1IN_3_ADD_1_CRY_4 : std_logic ;
signal R1IN_3_ADD_1_AXB_5 : std_logic ;
signal R1IN_3_ADD_1_CRY_5 : std_logic ;
signal R1IN_3_ADD_1_AXB_6 : std_logic ;
signal R1IN_3_ADD_1_CRY_6 : std_logic ;
signal R1IN_3_ADD_1_AXB_7 : std_logic ;
signal R1IN_3_ADD_1_CRY_7 : std_logic ;
signal R1IN_3_ADD_1_AXB_8 : std_logic ;
signal R1IN_3_ADD_1_CRY_8 : std_logic ;
signal R1IN_3_ADD_1_AXB_9 : std_logic ;
signal R1IN_3_ADD_1_CRY_9 : std_logic ;
signal R1IN_3_ADD_1_AXB_10 : std_logic ;
signal R1IN_3_ADD_1_CRY_10 : std_logic ;
signal R1IN_3_ADD_1_AXB_11 : std_logic ;
signal R1IN_3_ADD_1_CRY_11 : std_logic ;
signal R1IN_3_ADD_1_AXB_12 : std_logic ;
signal R1IN_3_ADD_1_CRY_12 : std_logic ;
signal R1IN_3_ADD_1_AXB_13 : std_logic ;
signal R1IN_3_ADD_1_CRY_13 : std_logic ;
signal R1IN_3_ADD_1_AXB_14 : std_logic ;
signal R1IN_3_ADD_1_CRY_14 : std_logic ;
signal R1IN_3_ADD_1_AXB_15 : std_logic ;
signal R1IN_3_ADD_1_CRY_15 : std_logic ;
signal R1IN_3_ADD_1_AXB_16 : std_logic ;
signal R1IN_3_ADD_1_CRY_16 : std_logic ;
signal R1IN_3_ADD_1_AXB_17 : std_logic ;
signal R1IN_3_ADD_1_CRY_17 : std_logic ;
signal R1IN_3_ADD_1_AXB_18 : std_logic ;
signal R1IN_3_ADD_1_CRY_18 : std_logic ;
signal R1IN_3_ADD_1_AXB_19 : std_logic ;
signal R1IN_3_ADD_1_CRY_19 : std_logic ;
signal R1IN_3_ADD_1_AXB_20 : std_logic ;
signal R1IN_3_ADD_1_CRY_20 : std_logic ;
signal R1IN_3_ADD_1_AXB_21 : std_logic ;
signal R1IN_3_ADD_1_CRY_21 : std_logic ;
signal R1IN_3_ADD_1_AXB_22 : std_logic ;
signal R1IN_3_ADD_1_CRY_22 : std_logic ;
signal R1IN_3_ADD_1_AXB_23 : std_logic ;
signal R1IN_3_ADD_1_CRY_23 : std_logic ;
signal R1IN_3_ADD_1_AXB_24 : std_logic ;
signal R1IN_3_ADD_1_CRY_24 : std_logic ;
signal R1IN_3_ADD_1_AXB_25 : std_logic ;
signal R1IN_3_ADD_1_CRY_25 : std_logic ;
signal R1IN_3_ADD_1_AXB_26 : std_logic ;
signal R1IN_3_ADD_1_CRY_26 : std_logic ;
signal R1IN_3_ADD_1_AXB_27 : std_logic ;
signal R1IN_3_ADD_1_CRY_27 : std_logic ;
signal R1IN_3_ADD_1_AXB_28 : std_logic ;
signal R1IN_3_ADD_1_CRY_28 : std_logic ;
signal R1IN_3_ADD_1_AXB_29 : std_logic ;
signal R1IN_3_ADD_1_CRY_29 : std_logic ;
signal R1IN_3_ADD_1_AXB_30 : std_logic ;
signal R1IN_3_ADD_1_CRY_30 : std_logic ;
signal R1IN_3_ADD_1_AXB_31 : std_logic ;
signal R1IN_3_ADD_1_CRY_31 : std_logic ;
signal R1IN_3_ADD_1_AXB_32 : std_logic ;
signal R1IN_3_ADD_1_CRY_32 : std_logic ;
signal R1IN_3_ADD_1_AXB_33 : std_logic ;
signal R1IN_3_ADD_1_CRY_33 : std_logic ;
signal R1IN_3_ADD_1_AXB_34 : std_logic ;
signal R1IN_3_ADD_1_CRY_34 : std_logic ;
signal R1IN_3_ADD_1_AXB_35 : std_logic ;
signal R1IN_3_ADD_1_CRY_35 : std_logic ;
signal R1IN_3_ADD_1_AXB_36 : std_logic ;
signal R1IN_3_ADD_1_CRY_36 : std_logic ;
signal R1IN_3_ADD_1_AXB_37 : std_logic ;
signal R1IN_3_ADD_1_CRY_37 : std_logic ;
signal R1IN_3_ADD_1_AXB_38 : std_logic ;
signal R1IN_3_ADD_1_CRY_38 : std_logic ;
signal R1IN_3_ADD_1_AXB_39 : std_logic ;
signal R1IN_3_ADD_1_CRY_39 : std_logic ;
signal R1IN_3_ADD_1_AXB_40 : std_logic ;
signal R1IN_3_ADD_1_CRY_40 : std_logic ;
signal R1IN_3_ADD_1_AXB_41 : std_logic ;
signal R1IN_3_ADD_1_CRY_41 : std_logic ;
signal R1IN_3_ADD_1_AXB_42 : std_logic ;
signal R1IN_3_ADD_1_CRY_42 : std_logic ;
signal R1IN_3_ADD_1_AXB_43 : std_logic ;
signal R1IN_2_ADD_1_CRY_0 : std_logic ;
signal R1IN_2_ADD_1_AXB_1 : std_logic ;
signal R1IN_2_ADD_1_CRY_1 : std_logic ;
signal R1IN_2_ADD_1_AXB_2 : std_logic ;
signal R1IN_2_ADD_1_CRY_2 : std_logic ;
signal R1IN_2_ADD_1_AXB_3 : std_logic ;
signal R1IN_2_ADD_1_CRY_3 : std_logic ;
signal R1IN_2_ADD_1_AXB_4 : std_logic ;
signal R1IN_2_ADD_1_CRY_4 : std_logic ;
signal R1IN_2_ADD_1_AXB_5 : std_logic ;
signal R1IN_2_ADD_1_CRY_5 : std_logic ;
signal R1IN_2_ADD_1_AXB_6 : std_logic ;
signal R1IN_2_ADD_1_CRY_6 : std_logic ;
signal R1IN_2_ADD_1_AXB_7 : std_logic ;
signal R1IN_2_ADD_1_CRY_7 : std_logic ;
signal R1IN_2_ADD_1_AXB_8 : std_logic ;
signal R1IN_2_ADD_1_CRY_8 : std_logic ;
signal R1IN_2_ADD_1_AXB_9 : std_logic ;
signal R1IN_2_ADD_1_CRY_9 : std_logic ;
signal R1IN_2_ADD_1_AXB_10 : std_logic ;
signal R1IN_2_ADD_1_CRY_10 : std_logic ;
signal R1IN_2_ADD_1_AXB_11 : std_logic ;
signal R1IN_2_ADD_1_CRY_11 : std_logic ;
signal R1IN_2_ADD_1_AXB_12 : std_logic ;
signal R1IN_2_ADD_1_CRY_12 : std_logic ;
signal R1IN_2_ADD_1_AXB_13 : std_logic ;
signal R1IN_2_ADD_1_CRY_13 : std_logic ;
signal R1IN_2_ADD_1_AXB_14 : std_logic ;
signal R1IN_2_ADD_1_CRY_14 : std_logic ;
signal R1IN_2_ADD_1_AXB_15 : std_logic ;
signal R1IN_2_ADD_1_CRY_15 : std_logic ;
signal R1IN_2_ADD_1_AXB_16 : std_logic ;
signal R1IN_2_ADD_1_CRY_16 : std_logic ;
signal R1IN_2_ADD_1_AXB_17 : std_logic ;
signal R1IN_2_ADD_1_CRY_17 : std_logic ;
signal R1IN_2_ADD_1_AXB_18 : std_logic ;
signal R1IN_2_ADD_1_CRY_18 : std_logic ;
signal R1IN_2_ADD_1_AXB_19 : std_logic ;
signal R1IN_2_ADD_1_CRY_19 : std_logic ;
signal R1IN_2_ADD_1_AXB_20 : std_logic ;
signal R1IN_2_ADD_1_CRY_20 : std_logic ;
signal R1IN_2_ADD_1_AXB_21 : std_logic ;
signal R1IN_2_ADD_1_CRY_21 : std_logic ;
signal R1IN_2_ADD_1_AXB_22 : std_logic ;
signal R1IN_2_ADD_1_CRY_22 : std_logic ;
signal R1IN_2_ADD_1_AXB_23 : std_logic ;
signal R1IN_2_ADD_1_CRY_23 : std_logic ;
signal R1IN_2_ADD_1_AXB_24 : std_logic ;
signal R1IN_2_ADD_1_CRY_24 : std_logic ;
signal R1IN_2_ADD_1_AXB_25 : std_logic ;
signal R1IN_2_ADD_1_CRY_25 : std_logic ;
signal R1IN_2_ADD_1_AXB_26 : std_logic ;
signal R1IN_2_ADD_1_CRY_26 : std_logic ;
signal R1IN_2_ADD_1_AXB_27 : std_logic ;
signal R1IN_2_ADD_1_CRY_27 : std_logic ;
signal R1IN_2_ADD_1_AXB_28 : std_logic ;
signal R1IN_2_ADD_1_CRY_28 : std_logic ;
signal R1IN_2_ADD_1_AXB_29 : std_logic ;
signal R1IN_2_ADD_1_CRY_29 : std_logic ;
signal R1IN_2_ADD_1_AXB_30 : std_logic ;
signal R1IN_2_ADD_1_CRY_30 : std_logic ;
signal R1IN_2_ADD_1_AXB_31 : std_logic ;
signal R1IN_2_ADD_1_CRY_31 : std_logic ;
signal R1IN_2_ADD_1_AXB_32 : std_logic ;
signal R1IN_2_ADD_1_CRY_32 : std_logic ;
signal R1IN_2_ADD_1_AXB_33 : std_logic ;
signal R1IN_2_ADD_1_CRY_33 : std_logic ;
signal R1IN_2_ADD_1_AXB_34 : std_logic ;
signal R1IN_2_ADD_1_CRY_34 : std_logic ;
signal R1IN_2_ADD_1_AXB_35 : std_logic ;
signal R1IN_2_ADD_1_CRY_35 : std_logic ;
signal R1IN_2_ADD_1_AXB_36 : std_logic ;
signal R1IN_2_ADD_1_CRY_36 : std_logic ;
signal R1IN_2_ADD_1_AXB_37 : std_logic ;
signal R1IN_2_ADD_1_CRY_37 : std_logic ;
signal R1IN_2_ADD_1_AXB_38 : std_logic ;
signal R1IN_2_ADD_1_CRY_38 : std_logic ;
signal R1IN_2_ADD_1_AXB_39 : std_logic ;
signal R1IN_2_ADD_1_CRY_39 : std_logic ;
signal R1IN_2_ADD_1_AXB_40 : std_logic ;
signal R1IN_2_ADD_1_CRY_40 : std_logic ;
signal R1IN_2_ADD_1_AXB_41 : std_logic ;
signal R1IN_2_ADD_1_CRY_41 : std_logic ;
signal R1IN_2_ADD_1_AXB_42 : std_logic ;
signal R1IN_2_ADD_1_CRY_42 : std_logic ;
signal R1IN_2_ADD_1_AXB_43 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_0 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_1 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_1 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_2 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_2 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_3 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_3 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_4 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_4 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_5 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_5 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_6 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_6 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_7 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_7 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_8 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_8 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_9 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_9 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_10 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_10 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_11 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_11 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_12 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_12 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_13 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_13 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_14 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_14 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_15 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_15 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_16 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_16 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_17 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_17 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_18 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_18 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_19 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_19 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_20 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_20 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_21 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_21 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_22 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_22 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_23 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_23 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_24 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_24 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_25 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_25 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_26 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_26 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_27 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_27 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_28 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_28 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_29 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_29 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_30 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_30 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_31 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_31 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_32 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_32 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_33 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_33 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_34 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_34 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_35 : std_logic ;
signal R1IN_4_4_ADD_2_CRY_35 : std_logic ;
signal R1IN_4_4_ADD_2_AXB_36 : std_logic ;
signal R1IN_4_ADD_2_0 : std_logic ;
signal R1IN_4_ADD_1_CRY_0 : std_logic ;
signal R1IN_4_ADD_1_AXB_1 : std_logic ;
signal R1IN_4_ADD_1_CRY_1 : std_logic ;
signal R1IN_4_ADD_1_AXB_2 : std_logic ;
signal R1IN_4_ADD_1_CRY_2 : std_logic ;
signal R1IN_4_ADD_1_AXB_3 : std_logic ;
signal R1IN_4_ADD_1_CRY_3 : std_logic ;
signal R1IN_4_ADD_1_AXB_4 : std_logic ;
signal R1IN_4_ADD_1_CRY_4 : std_logic ;
signal R1IN_4_ADD_1_AXB_5 : std_logic ;
signal R1IN_4_ADD_1_CRY_5 : std_logic ;
signal R1IN_4_ADD_1_AXB_6 : std_logic ;
signal R1IN_4_ADD_1_CRY_6 : std_logic ;
signal R1IN_4_ADD_1_AXB_7 : std_logic ;
signal R1IN_4_ADD_1_CRY_7 : std_logic ;
signal R1IN_4_ADD_1_AXB_8 : std_logic ;
signal R1IN_4_ADD_1_CRY_8 : std_logic ;
signal R1IN_4_ADD_1_AXB_9 : std_logic ;
signal R1IN_4_ADD_1_CRY_9 : std_logic ;
signal R1IN_4_ADD_1_AXB_10 : std_logic ;
signal R1IN_4_ADD_1_CRY_10 : std_logic ;
signal R1IN_4_ADD_1_AXB_11 : std_logic ;
signal R1IN_4_ADD_1_CRY_11 : std_logic ;
signal R1IN_4_ADD_1_AXB_12 : std_logic ;
signal R1IN_4_ADD_1_CRY_12 : std_logic ;
signal R1IN_4_ADD_1_AXB_13 : std_logic ;
signal R1IN_4_ADD_1_CRY_13 : std_logic ;
signal R1IN_4_ADD_1_AXB_14 : std_logic ;
signal R1IN_4_ADD_1_CRY_14 : std_logic ;
signal R1IN_4_ADD_1_AXB_15 : std_logic ;
signal R1IN_4_ADD_1_CRY_15 : std_logic ;
signal R1IN_4_ADD_1_AXB_16 : std_logic ;
signal R1IN_4_ADD_1_CRY_16 : std_logic ;
signal R1IN_4_ADD_1_AXB_17 : std_logic ;
signal R1IN_4_ADD_1_CRY_17 : std_logic ;
signal R1IN_4_ADD_1_AXB_18 : std_logic ;
signal R1IN_4_ADD_1_CRY_18 : std_logic ;
signal R1IN_4_ADD_1_AXB_19 : std_logic ;
signal R1IN_4_ADD_1_CRY_19 : std_logic ;
signal R1IN_4_ADD_1_AXB_20 : std_logic ;
signal R1IN_4_ADD_1_CRY_20 : std_logic ;
signal R1IN_4_ADD_1_AXB_21 : std_logic ;
signal R1IN_4_ADD_1_CRY_21 : std_logic ;
signal R1IN_4_ADD_1_AXB_22 : std_logic ;
signal R1IN_4_ADD_1_CRY_22 : std_logic ;
signal R1IN_4_ADD_1_AXB_23 : std_logic ;
signal R1IN_4_ADD_1_CRY_23 : std_logic ;
signal R1IN_4_ADD_1_AXB_24 : std_logic ;
signal R1IN_4_ADD_1_CRY_24 : std_logic ;
signal R1IN_4_ADD_1_AXB_25 : std_logic ;
signal R1IN_4_ADD_1_CRY_25 : std_logic ;
signal R1IN_4_ADD_1_AXB_26 : std_logic ;
signal R1IN_4_ADD_1_CRY_26 : std_logic ;
signal R1IN_4_ADD_1_AXB_27 : std_logic ;
signal R1IN_4_ADD_1_CRY_27 : std_logic ;
signal R1IN_4_ADD_1_AXB_28 : std_logic ;
signal R1IN_4_ADD_1_CRY_28 : std_logic ;
signal R1IN_4_ADD_1_AXB_29 : std_logic ;
signal R1IN_4_ADD_1_CRY_29 : std_logic ;
signal R1IN_4_ADD_1_AXB_30 : std_logic ;
signal R1IN_4_ADD_1_CRY_30 : std_logic ;
signal R1IN_4_ADD_1_AXB_31 : std_logic ;
signal R1IN_4_ADD_1_CRY_31 : std_logic ;
signal R1IN_4_ADD_1_AXB_32 : std_logic ;
signal R1IN_4_ADD_1_CRY_32 : std_logic ;
signal R1IN_4_ADD_1_AXB_33 : std_logic ;
signal R1IN_4_ADD_1_CRY_33 : std_logic ;
signal R1IN_4_ADD_1_AXB_34 : std_logic ;
signal R1IN_4_ADD_1_CRY_34 : std_logic ;
signal R1IN_4_ADD_1_AXB_35 : std_logic ;
signal R1IN_4_ADD_1_CRY_35 : std_logic ;
signal R1IN_4_ADD_1_AXB_36 : std_logic ;
signal R1IN_4_ADD_1_CRY_36 : std_logic ;
signal R1IN_4_ADD_1_AXB_37 : std_logic ;
signal R1IN_4_ADD_1_CRY_37 : std_logic ;
signal R1IN_4_ADD_1_AXB_38 : std_logic ;
signal R1IN_4_ADD_1_CRY_38 : std_logic ;
signal R1IN_4_ADD_1_AXB_39 : std_logic ;
signal R1IN_4_ADD_1_CRY_39 : std_logic ;
signal R1IN_4_ADD_1_AXB_40 : std_logic ;
signal R1IN_4_ADD_1_CRY_40 : std_logic ;
signal R1IN_4_ADD_1_AXB_41 : std_logic ;
signal R1IN_4_ADD_1_CRY_41 : std_logic ;
signal R1IN_4_ADD_1_AXB_42 : std_logic ;
signal R1IN_4_ADD_1_CRY_42 : std_logic ;
signal R1IN_4_ADD_1_AXB_43 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO : std_logic ;
signal N_5444 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_0 : std_logic ;
signal N_5445 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_1 : std_logic ;
signal N_5446 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_2 : std_logic ;
signal N_5447 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_3 : std_logic ;
signal N_5448 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_4 : std_logic ;
signal N_5449 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_5 : std_logic ;
signal N_5450 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_6 : std_logic ;
signal N_5451 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_7 : std_logic ;
signal N_5452 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_8 : std_logic ;
signal N_5453 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_9 : std_logic ;
signal N_5454 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_10 : std_logic ;
signal N_5455 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_11 : std_logic ;
signal N_5456 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_12 : std_logic ;
signal N_5457 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_13 : std_logic ;
signal N_5458 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_14 : std_logic ;
signal N_5459 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_15 : std_logic ;
signal N_5460 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_16 : std_logic ;
signal N_5461 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_17 : std_logic ;
signal N_5462 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_18 : std_logic ;
signal N_5463 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_19 : std_logic ;
signal N_5464 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_20 : std_logic ;
signal N_5465 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_21 : std_logic ;
signal N_5466 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_22 : std_logic ;
signal N_5467 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_23 : std_logic ;
signal N_5468 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_24 : std_logic ;
signal N_5469 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_25 : std_logic ;
signal N_5470 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_26 : std_logic ;
signal N_5471 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_27 : std_logic ;
signal N_5472 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_28 : std_logic ;
signal N_5473 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_29 : std_logic ;
signal N_5474 : std_logic ;
signal N_1577 : std_logic ;
signal R2_PIPE_157_RET : std_logic ;
signal N_1913 : std_logic ;
signal R2_PIPE_157_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO : std_logic ;
signal N_5475 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_30 : std_logic ;
signal N_5476 : std_logic ;
signal N_1575 : std_logic ;
signal R2_PIPE_156_RET : std_logic ;
signal N_1912 : std_logic ;
signal R2_PIPE_156_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_0 : std_logic ;
signal N_5477 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_31 : std_logic ;
signal N_5478 : std_logic ;
signal N_1573 : std_logic ;
signal R2_PIPE_155_RET : std_logic ;
signal N_1911 : std_logic ;
signal R2_PIPE_155_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_1 : std_logic ;
signal N_5479 : std_logic ;
signal N_1571 : std_logic ;
signal R2_PIPE_154_RET : std_logic ;
signal N_1910 : std_logic ;
signal R2_PIPE_154_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_2 : std_logic ;
signal N_5480 : std_logic ;
signal N_1569 : std_logic ;
signal R2_PIPE_153_RET : std_logic ;
signal N_1909 : std_logic ;
signal R2_PIPE_153_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_3 : std_logic ;
signal N_5481 : std_logic ;
signal N_1567 : std_logic ;
signal R2_PIPE_152_RET : std_logic ;
signal N_1908 : std_logic ;
signal R2_PIPE_152_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_4 : std_logic ;
signal N_5482 : std_logic ;
signal N_1565 : std_logic ;
signal R2_PIPE_151_RET : std_logic ;
signal N_1907 : std_logic ;
signal R2_PIPE_151_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_5 : std_logic ;
signal N_5483 : std_logic ;
signal N_1563 : std_logic ;
signal R2_PIPE_150_RET : std_logic ;
signal N_1906 : std_logic ;
signal R2_PIPE_150_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_6 : std_logic ;
signal N_5484 : std_logic ;
signal N_1561 : std_logic ;
signal R2_PIPE_149_RET : std_logic ;
signal N_1905 : std_logic ;
signal R2_PIPE_149_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_7 : std_logic ;
signal N_5485 : std_logic ;
signal N_1559 : std_logic ;
signal R2_PIPE_148_RET : std_logic ;
signal N_1904 : std_logic ;
signal R2_PIPE_148_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_8 : std_logic ;
signal N_5486 : std_logic ;
signal N_1557 : std_logic ;
signal R2_PIPE_147_RET : std_logic ;
signal N_1903 : std_logic ;
signal R2_PIPE_147_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_9 : std_logic ;
signal N_5487 : std_logic ;
signal N_1555 : std_logic ;
signal R2_PIPE_146_RET : std_logic ;
signal N_1902 : std_logic ;
signal R2_PIPE_146_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_10 : std_logic ;
signal N_5488 : std_logic ;
signal N_1553 : std_logic ;
signal R2_PIPE_145_RET : std_logic ;
signal N_1901 : std_logic ;
signal R2_PIPE_145_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_11 : std_logic ;
signal N_5489 : std_logic ;
signal N_1551 : std_logic ;
signal R2_PIPE_144_RET : std_logic ;
signal N_1900 : std_logic ;
signal R2_PIPE_144_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_12 : std_logic ;
signal N_5490 : std_logic ;
signal N_1549 : std_logic ;
signal R2_PIPE_143_RET : std_logic ;
signal N_1899 : std_logic ;
signal R2_PIPE_143_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_13 : std_logic ;
signal N_5491 : std_logic ;
signal N_1547 : std_logic ;
signal R2_PIPE_142_RET : std_logic ;
signal N_1898 : std_logic ;
signal R2_PIPE_142_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_14 : std_logic ;
signal N_5492 : std_logic ;
signal N_1545 : std_logic ;
signal R2_PIPE_141_RET : std_logic ;
signal N_1897 : std_logic ;
signal R2_PIPE_141_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_15 : std_logic ;
signal N_5493 : std_logic ;
signal N_1543 : std_logic ;
signal R2_PIPE_140_RET : std_logic ;
signal N_1896 : std_logic ;
signal R2_PIPE_140_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_16 : std_logic ;
signal N_5494 : std_logic ;
signal N_1541 : std_logic ;
signal R2_PIPE_139_RET : std_logic ;
signal N_1895 : std_logic ;
signal R2_PIPE_139_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_17 : std_logic ;
signal N_5495 : std_logic ;
signal N_1539 : std_logic ;
signal R2_PIPE_138_RET : std_logic ;
signal N_1894 : std_logic ;
signal R2_PIPE_138_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_18 : std_logic ;
signal N_5496 : std_logic ;
signal N_5585 : std_logic ;
signal N_5586 : std_logic ;
signal N_5587 : std_logic ;
signal N_5588 : std_logic ;
signal N_5589 : std_logic ;
signal N_5590 : std_logic ;
signal N_5591 : std_logic ;
signal N_5592 : std_logic ;
signal N_5593 : std_logic ;
signal N_5594 : std_logic ;
signal N_5595 : std_logic ;
signal N_5596 : std_logic ;
signal N_5597 : std_logic ;
signal N_5598 : std_logic ;
signal N_5599 : std_logic ;
signal N_5600 : std_logic ;
signal N_5601 : std_logic ;
signal N_5602 : std_logic ;
signal N_5603 : std_logic ;
signal N_5604 : std_logic ;
signal N_5605 : std_logic ;
signal N_5606 : std_logic ;
signal N_5607 : std_logic ;
signal N_5608 : std_logic ;
signal N_5609 : std_logic ;
signal N_5610 : std_logic ;
signal N_5611 : std_logic ;
signal N_5612 : std_logic ;
signal N_5613 : std_logic ;
signal N_5614 : std_logic ;
signal N_5615 : std_logic ;
signal N_5616 : std_logic ;
signal N_5617 : std_logic ;
signal N_5618 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35 : std_logic ;
signal R1IN_4_ADD_2_0_CRY_35_RETO_32 : std_logic ;
signal N_5619 : std_logic ;
signal UC_187_0 : std_logic ;
signal UC_188_0 : std_logic ;
signal UC_189_0 : std_logic ;
signal UC_190_0 : std_logic ;
signal UC_191_0 : std_logic ;
signal UC_192_0 : std_logic ;
signal UC_193_0 : std_logic ;
signal UC_194_0 : std_logic ;
signal UC_195_0 : std_logic ;
signal UC_196_0 : std_logic ;
signal UC_197_0 : std_logic ;
signal UC_198_0 : std_logic ;
signal UC_199_0 : std_logic ;
signal UC_200_0 : std_logic ;
signal UC_173_0 : std_logic ;
signal UC_174_0 : std_logic ;
signal UC_175_0 : std_logic ;
signal UC_176_0 : std_logic ;
signal UC_177_0 : std_logic ;
signal UC_178_0 : std_logic ;
signal UC_179_0 : std_logic ;
signal UC_180_0 : std_logic ;
signal UC_181_0 : std_logic ;
signal UC_182_0 : std_logic ;
signal UC_183_0 : std_logic ;
signal UC_184_0 : std_logic ;
signal UC_185_0 : std_logic ;
signal UC_186_0 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_1 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_0 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_2 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_1 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_3 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_2 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_4 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_3 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_5 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_4 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_6 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_5 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_7 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_6 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_8 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_7 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_9 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_8 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_10 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_9 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_11 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_10 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_12 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_11 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_13 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_12 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_14 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_13 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_15 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_14 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_16 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_15 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_17 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_16 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_18 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_17 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_19 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_18 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_20 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_19 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_21 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_20 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_22 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_21 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_23 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_22 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_24 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_23 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_25 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_24 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_26 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_25 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_27 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_26 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_28 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_27 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_29 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_28 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_30 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_29 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_31 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_30 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_32 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_31 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_33 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_32 : std_logic ;
signal R1IN_4_ADD_2_1_0_CRY_33 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_34 : std_logic ;
signal N_1 : std_logic ;
signal N_2 : std_logic ;
signal N_3 : std_logic ;
signal N_4 : std_logic ;
signal N_5 : std_logic ;
signal N_6 : std_logic ;
signal N_7 : std_logic ;
signal N_8 : std_logic ;
signal N_9 : std_logic ;
signal N_10 : std_logic ;
signal N_11 : std_logic ;
signal N_12 : std_logic ;
signal N_13 : std_logic ;
signal N_14 : std_logic ;
signal N_15 : std_logic ;
signal N_16 : std_logic ;
signal N_17 : std_logic ;
signal N_18 : std_logic ;
signal N_19 : std_logic ;
signal N_20 : std_logic ;
signal N_21 : std_logic ;
signal N_22 : std_logic ;
signal N_23 : std_logic ;
signal N_24 : std_logic ;
signal N_25 : std_logic ;
signal N_26 : std_logic ;
signal N_27 : std_logic ;
signal N_28 : std_logic ;
signal N_29 : std_logic ;
signal N_30 : std_logic ;
signal N_31 : std_logic ;
signal N_32 : std_logic ;
signal N_33 : std_logic ;
signal N_34 : std_logic ;
signal N_35 : std_logic ;
signal R2_PIPE_165_RET : std_logic ;
signal R2_PIPE_165_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_19 : std_logic ;
signal N_1_0 : std_logic ;
signal R2_PIPE_164_RET : std_logic ;
signal R2_PIPE_164_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_20 : std_logic ;
signal N_1_1 : std_logic ;
signal R2_PIPE_163_RET : std_logic ;
signal R2_PIPE_163_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_21 : std_logic ;
signal N_1_2 : std_logic ;
signal R2_PIPE_162_RET : std_logic ;
signal R2_PIPE_162_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_22 : std_logic ;
signal N_1_3 : std_logic ;
signal R2_PIPE_161_RET : std_logic ;
signal R2_PIPE_161_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_23 : std_logic ;
signal N_1_4 : std_logic ;
signal R2_PIPE_160_RET : std_logic ;
signal R2_PIPE_160_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_24 : std_logic ;
signal N_1_5 : std_logic ;
signal R2_PIPE_159_RET : std_logic ;
signal R2_PIPE_159_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_25 : std_logic ;
signal N_1_6 : std_logic ;
signal R2_PIPE_158_RET : std_logic ;
signal R2_PIPE_158_RET_1 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_26 : std_logic ;
signal N_1_7 : std_logic ;
signal R1IN_ADD_1_0_CRY_31_RETO_27 : std_logic ;
signal R1IN_ADD_1_1_0_CRY_28_RETO : std_logic ;
signal R1IN_ADD_1_1_CRY_28_RETO : std_logic ;
signal N_1_8 : std_logic ;
signal N_6019 : std_logic ;
signal N_6020 : std_logic ;
signal N_6021 : std_logic ;
signal N_6022 : std_logic ;
signal N_6023 : std_logic ;
signal N_6024 : std_logic ;
signal N_6025 : std_logic ;
signal N_6026 : std_logic ;
signal N_6027 : std_logic ;
signal N_6028 : std_logic ;
signal N_6029 : std_logic ;
signal N_6030 : std_logic ;
signal N_6031 : std_logic ;
signal N_6032 : std_logic ;
signal N_6033 : std_logic ;
signal N_6034 : std_logic ;
signal N_6035 : std_logic ;
signal N_6036 : std_logic ;
signal N_6037 : std_logic ;
signal N_6038 : std_logic ;
signal N_6039 : std_logic ;
signal N_6040 : std_logic ;
signal N_6041 : std_logic ;
signal N_6042 : std_logic ;
signal N_6043 : std_logic ;
signal N_6044 : std_logic ;
signal N_6045 : std_logic ;
signal N_6046 : std_logic ;
signal N_6047 : std_logic ;
signal N_6048 : std_logic ;
signal N_6049 : std_logic ;
signal N_6050 : std_logic ;
signal N_6051 : std_logic ;
signal N_6052 : std_logic ;
signal N_6053 : std_logic ;
signal N_6054 : std_logic ;
signal N_6055 : std_logic ;
signal N_6056 : std_logic ;
signal N_6057 : std_logic ;
signal N_6058 : std_logic ;
signal N_6059 : std_logic ;
signal N_6060 : std_logic ;
signal N_6061 : std_logic ;
signal N_1822_RET_0I : std_logic ;
signal R2_PIPE_104_RET_48 : std_logic ;
signal N_1821_RET_0I : std_logic ;
signal R2_PIPE_104_RET_49 : std_logic ;
signal N_1820_RET_0I : std_logic ;
signal R2_PIPE_104_RET_93 : std_logic ;
signal N_1819_RET_0I : std_logic ;
signal R2_PIPE_104_RET_94 : std_logic ;
signal N_1818_RET_0I : std_logic ;
signal R2_PIPE_104_RET_95 : std_logic ;
signal N_1817_RET_0I : std_logic ;
signal R2_PIPE_104_RET_96 : std_logic ;
signal N_1816_RET_0I : std_logic ;
signal R2_PIPE_104_RET_97 : std_logic ;
signal N_1815_RET_0I : std_logic ;
signal R2_PIPE_104_RET_98 : std_logic ;
signal N_1814_RET_0I : std_logic ;
signal R2_PIPE_104_RET_99 : std_logic ;
signal N_1813_RET_0I : std_logic ;
signal R2_PIPE_104_RET_100 : std_logic ;
signal N_1812_RET_0I : std_logic ;
signal R2_PIPE_104_RET_101 : std_logic ;
signal N_1811_RET_0I : std_logic ;
signal R2_PIPE_104_RET_102 : std_logic ;
signal N_1810_RET_0I : std_logic ;
signal R2_PIPE_104_RET_103 : std_logic ;
signal N_1809_RET_0I : std_logic ;
signal R2_PIPE_104_RET_104 : std_logic ;
signal N_1808_RET_0I : std_logic ;
signal R2_PIPE_104_RET_105 : std_logic ;
signal N_1807_RET_0I : std_logic ;
signal R2_PIPE_104_RET_106 : std_logic ;
signal N_1806_RET_0I : std_logic ;
signal R2_PIPE_104_RET_107 : std_logic ;
signal N_1805_RET_0I : std_logic ;
signal R2_PIPE_104_RET_108 : std_logic ;
signal N_1804_RET_0I : std_logic ;
signal R2_PIPE_104_RET_109 : std_logic ;
signal N_1803_RET_0I : std_logic ;
signal R2_PIPE_104_RET_110 : std_logic ;
signal N_1802_RET_0I : std_logic ;
signal R2_PIPE_104_RET_111 : std_logic ;
signal N_1801_RET_0I : std_logic ;
signal R2_PIPE_104_RET_112 : std_logic ;
signal N_1800_RET_0I : std_logic ;
signal R2_PIPE_104_RET_113 : std_logic ;
signal N_1799_RET_0I : std_logic ;
signal R2_PIPE_104_RET_114 : std_logic ;
signal N_1798_RET_0I : std_logic ;
signal R2_PIPE_104_RET_115 : std_logic ;
signal N_1797_RET_0I : std_logic ;
signal R2_PIPE_104_RET_116 : std_logic ;
signal N_1796_RET_0I : std_logic ;
signal R2_PIPE_104_RET_117 : std_logic ;
signal N_1795_RET_0I : std_logic ;
signal R2_PIPE_104_RET_118 : std_logic ;
signal N_1794_RET_0I : std_logic ;
signal R2_PIPE_104_RET_119 : std_logic ;
signal N_1793_RET_0I : std_logic ;
signal R2_PIPE_104_RET_120 : std_logic ;
signal N_1792_RET_0I : std_logic ;
signal R2_PIPE_104_RET_121 : std_logic ;
signal N_1791_RET_0I : std_logic ;
signal R2_PIPE_104_RET_122 : std_logic ;
signal N_1790_RET_0I : std_logic ;
signal R2_PIPE_104_RET_123 : std_logic ;
signal N_1789_RET_0I : std_logic ;
signal R2_PIPE_104_RET_124 : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_0_RET_0I : std_logic ;
signal R1IN_4_ADD_2_1_0_AXB_0_RETO : std_logic ;
signal N_6062 : std_logic ;
signal N_6402 : std_logic ;
signal N_6403 : std_logic ;
signal N_6404 : std_logic ;
signal N_6405 : std_logic ;
signal N_6406 : std_logic ;
signal N_6407 : std_logic ;
signal N_6408 : std_logic ;
signal N_6409 : std_logic ;
signal N_6410 : std_logic ;
signal N_6411 : std_logic ;
signal N_6412 : std_logic ;
signal N_6413 : std_logic ;
signal N_6414 : std_logic ;
signal N_6415 : std_logic ;
signal N_6416 : std_logic ;
signal N_6417 : std_logic ;
signal N_6418 : std_logic ;
signal N_6419 : std_logic ;
signal N_6420 : std_logic ;
signal N_6421 : std_logic ;
signal N_6422 : std_logic ;
signal N_6423 : std_logic ;
signal N_6424 : std_logic ;
signal N_6425 : std_logic ;
signal N_6426 : std_logic ;
signal N_6427 : std_logic ;
signal N_6428 : std_logic ;
signal N_6429 : std_logic ;
signal N_6430 : std_logic ;
signal N_6431 : std_logic ;
signal N_6432 : std_logic ;
signal N_6433 : std_logic ;
signal N_6434 : std_logic ;
signal N_6435 : std_logic ;
signal N_6436 : std_logic ;
signal N_6437 : std_logic ;
signal N_6438 : std_logic ;
signal N_6439 : std_logic ;
signal N_6440 : std_logic ;
signal N_6441 : std_logic ;
signal N_6442 : std_logic ;
signal N_6443 : std_logic ;
signal N_6444 : std_logic ;
signal N_6445 : std_logic ;
signal N_6446 : std_logic ;
signal N_6447 : std_logic ;
signal N_6448 : std_logic ;
signal N_6449 : std_logic ;
signal N_6450 : std_logic ;
signal N_6451 : std_logic ;
signal N_6452 : std_logic ;
signal N_6453 : std_logic ;
signal N_6454 : std_logic ;
signal N_6455 : std_logic ;
signal N_6456 : std_logic ;
signal N_6457 : std_logic ;
signal N_6458 : std_logic ;
signal N_6459 : std_logic ;
signal N_6460 : std_logic ;
signal N_6461 : std_logic ;
signal N_6462 : std_logic ;
signal N_6463 : std_logic ;
signal N_6464 : std_logic ;
signal N_6465 : std_logic ;
signal N_6466 : std_logic ;
signal N_6467 : std_logic ;
signal N_6468 : std_logic ;
signal N_6469 : std_logic ;
signal N_6470 : std_logic ;
signal N_6471 : std_logic ;
signal N_6472 : std_logic ;
signal N_6473 : std_logic ;
signal N_6474 : std_logic ;
signal N_6475 : std_logic ;
signal N_6476 : std_logic ;
signal N_6477 : std_logic ;
signal N_6478 : std_logic ;
signal N_6479 : std_logic ;
signal N_6480 : std_logic ;
signal N_6654 : std_logic ;
signal N_6655 : std_logic ;
signal N_6656 : std_logic ;
signal N_6657 : std_logic ;
signal N_6658 : std_logic ;
signal N_6659 : std_logic ;
signal N_6660 : std_logic ;
signal N_6661 : std_logic ;
signal N_6662 : std_logic ;
signal N_6663 : std_logic ;
signal N_6664 : std_logic ;
signal N_6665 : std_logic ;
signal N_6666 : std_logic ;
signal N_6667 : std_logic ;
signal N_6668 : std_logic ;
signal N_6669 : std_logic ;
signal N_6670 : std_logic ;
signal N_6671 : std_logic ;
signal N_6672 : std_logic ;
signal N_6673 : std_logic ;
signal N_6674 : std_logic ;
signal N_6675 : std_logic ;
signal N_6676 : std_logic ;
signal N_6677 : std_logic ;
signal N_6678 : std_logic ;
signal N_6679 : std_logic ;
signal N_6680 : std_logic ;
signal N_6681 : std_logic ;
signal N_6682 : std_logic ;
signal N_6683 : std_logic ;
signal N_6684 : std_logic ;
signal N_6685 : std_logic ;
signal N_6686 : std_logic ;
signal N_6687 : std_logic ;
signal N_6688 : std_logic ;
signal N_6689 : std_logic ;
signal N_6690 : std_logic ;
signal N_6691 : std_logic ;
signal N_6692 : std_logic ;
signal N_6693 : std_logic ;
signal N_6694 : std_logic ;
signal N_6695 : std_logic ;
signal N_6696 : std_logic ;
signal N_6697 : std_logic ;
signal N_6698 : std_logic ;
signal N_6699 : std_logic ;
signal N_6700 : std_logic ;
signal N_6701 : std_logic ;
signal N_6702 : std_logic ;
signal N_6703 : std_logic ;
signal N_6704 : std_logic ;
signal N_6705 : std_logic ;
signal N_6706 : std_logic ;
signal N_6707 : std_logic ;
signal N_6708 : std_logic ;
signal N_6709 : std_logic ;
signal N_6710 : std_logic ;
signal N_6711 : std_logic ;
signal N_6712 : std_logic ;
signal N_6713 : std_logic ;
signal N_6714 : std_logic ;
signal N_6715 : std_logic ;
signal N_6716 : std_logic ;
signal N_6717 : std_logic ;
signal N_6718 : std_logic ;
signal N_6719 : std_logic ;
signal N_6720 : std_logic ;
signal N_6721 : std_logic ;
signal N_6722 : std_logic ;
signal N_6723 : std_logic ;
signal N_6724 : std_logic ;
signal N_6725 : std_logic ;
signal N_6726 : std_logic ;
signal N_6727 : std_logic ;
signal N_6728 : std_logic ;
signal N_6729 : std_logic ;
signal N_6730 : std_logic ;
signal N_6731 : std_logic ;
signal N_6732 : std_logic ;
signal N_6906 : std_logic ;
signal N_6907 : std_logic ;
signal N_6908 : std_logic ;
signal N_6909 : std_logic ;
signal N_6910 : std_logic ;
signal N_6911 : std_logic ;
signal N_6912 : std_logic ;
signal N_6913 : std_logic ;
signal N_6914 : std_logic ;
signal N_6915 : std_logic ;
signal N_6916 : std_logic ;
signal N_6917 : std_logic ;
signal N_6918 : std_logic ;
signal N_6919 : std_logic ;
signal N_6920 : std_logic ;
signal N_6921 : std_logic ;
signal N_6922 : std_logic ;
signal N_6923 : std_logic ;
signal N_6924 : std_logic ;
signal N_6925 : std_logic ;
signal N_6926 : std_logic ;
signal N_6927 : std_logic ;
signal N_6928 : std_logic ;
signal N_6929 : std_logic ;
signal N_6930 : std_logic ;
signal N_6931 : std_logic ;
signal N_6932 : std_logic ;
signal N_6933 : std_logic ;
signal N_6934 : std_logic ;
signal N_6935 : std_logic ;
signal N_6936 : std_logic ;
signal N_6937 : std_logic ;
signal N_6938 : std_logic ;
signal N_6939 : std_logic ;
signal N_6940 : std_logic ;
signal N_6941 : std_logic ;
signal N_6942 : std_logic ;
signal N_6943 : std_logic ;
signal N_6944 : std_logic ;
signal N_6945 : std_logic ;
signal N_6946 : std_logic ;
signal N_6947 : std_logic ;
signal N_6948 : std_logic ;
signal N_6949 : std_logic ;
signal N_6950 : std_logic ;
signal N_6951 : std_logic ;
signal N_6952 : std_logic ;
signal N_6953 : std_logic ;
signal N_6954 : std_logic ;
signal N_6955 : std_logic ;
signal N_6956 : std_logic ;
signal N_6957 : std_logic ;
signal N_6958 : std_logic ;
signal N_6959 : std_logic ;
signal N_6960 : std_logic ;
signal N_6961 : std_logic ;
signal N_6962 : std_logic ;
signal N_6963 : std_logic ;
signal N_6964 : std_logic ;
signal N_6965 : std_logic ;
signal N_6966 : std_logic ;
signal N_6967 : std_logic ;
signal N_6968 : std_logic ;
signal N_6969 : std_logic ;
signal N_6970 : std_logic ;
signal N_6971 : std_logic ;
signal N_6972 : std_logic ;
signal N_6973 : std_logic ;
signal N_6974 : std_logic ;
signal N_6975 : std_logic ;
signal N_6976 : std_logic ;
signal N_6977 : std_logic ;
signal N_6978 : std_logic ;
signal N_6979 : std_logic ;
signal N_6980 : std_logic ;
signal N_6981 : std_logic ;
signal N_6982 : std_logic ;
signal N_6983 : std_logic ;
signal N_6984 : std_logic ;
signal N_7158 : std_logic ;
signal N_7159 : std_logic ;
signal N_7160 : std_logic ;
signal N_7161 : std_logic ;
signal N_7162 : std_logic ;
signal N_7163 : std_logic ;
signal N_7164 : std_logic ;
signal N_7165 : std_logic ;
signal N_7166 : std_logic ;
signal N_7167 : std_logic ;
signal N_7168 : std_logic ;
signal N_7169 : std_logic ;
signal N_7170 : std_logic ;
signal N_7171 : std_logic ;
signal N_7172 : std_logic ;
signal N_7173 : std_logic ;
signal N_7174 : std_logic ;
signal N_7175 : std_logic ;
signal N_7176 : std_logic ;
signal N_7177 : std_logic ;
signal N_7178 : std_logic ;
signal N_7179 : std_logic ;
signal N_7180 : std_logic ;
signal N_7181 : std_logic ;
signal N_7182 : std_logic ;
signal N_7183 : std_logic ;
signal N_7184 : std_logic ;
signal N_7185 : std_logic ;
signal N_7186 : std_logic ;
signal N_7187 : std_logic ;
signal N_7188 : std_logic ;
signal N_7189 : std_logic ;
signal N_7190 : std_logic ;
signal N_7191 : std_logic ;
signal N_7192 : std_logic ;
signal N_7193 : std_logic ;
signal N_7194 : std_logic ;
signal N_7195 : std_logic ;
signal N_7196 : std_logic ;
signal N_7197 : std_logic ;
signal N_7198 : std_logic ;
signal N_7199 : std_logic ;
signal N_7200 : std_logic ;
signal N_7201 : std_logic ;
signal N_7202 : std_logic ;
signal N_7203 : std_logic ;
signal N_7204 : std_logic ;
signal N_7205 : std_logic ;
signal N_7206 : std_logic ;
signal N_7207 : std_logic ;
signal N_7208 : std_logic ;
signal N_7209 : std_logic ;
signal N_7210 : std_logic ;
signal N_7211 : std_logic ;
signal N_7212 : std_logic ;
signal N_7213 : std_logic ;
signal N_7214 : std_logic ;
signal N_7215 : std_logic ;
signal N_7216 : std_logic ;
signal N_7217 : std_logic ;
signal N_7218 : std_logic ;
signal N_7219 : std_logic ;
signal N_7220 : std_logic ;
signal N_7221 : std_logic ;
signal N_7222 : std_logic ;
signal N_7223 : std_logic ;
signal N_7224 : std_logic ;
signal N_7225 : std_logic ;
signal N_7226 : std_logic ;
signal N_7227 : std_logic ;
signal N_7228 : std_logic ;
signal N_7229 : std_logic ;
signal N_7230 : std_logic ;
signal N_7231 : std_logic ;
signal N_7232 : std_logic ;
signal N_7233 : std_logic ;
signal N_7234 : std_logic ;
signal N_7235 : std_logic ;
signal N_7236 : std_logic ;
signal N_7410 : std_logic ;
signal N_7411 : std_logic ;
signal N_7412 : std_logic ;
signal N_7413 : std_logic ;
signal N_7414 : std_logic ;
signal N_7415 : std_logic ;
signal N_7416 : std_logic ;
signal N_7417 : std_logic ;
signal N_7418 : std_logic ;
signal N_7419 : std_logic ;
signal N_7420 : std_logic ;
signal N_7421 : std_logic ;
signal N_7422 : std_logic ;
signal N_7423 : std_logic ;
signal N_7424 : std_logic ;
signal N_7425 : std_logic ;
signal N_7426 : std_logic ;
signal N_7427 : std_logic ;
signal N_7428 : std_logic ;
signal N_7429 : std_logic ;
signal N_7430 : std_logic ;
signal N_7431 : std_logic ;
signal N_7432 : std_logic ;
signal N_7433 : std_logic ;
signal N_7434 : std_logic ;
signal N_7435 : std_logic ;
signal N_7436 : std_logic ;
signal N_7437 : std_logic ;
signal N_7438 : std_logic ;
signal N_7439 : std_logic ;
signal N_7440 : std_logic ;
signal N_7441 : std_logic ;
signal N_7442 : std_logic ;
signal N_7443 : std_logic ;
signal N_7444 : std_logic ;
signal N_7445 : std_logic ;
signal N_7446 : std_logic ;
signal N_7447 : std_logic ;
signal N_7448 : std_logic ;
signal N_7449 : std_logic ;
signal N_7450 : std_logic ;
signal N_7451 : std_logic ;
signal N_7452 : std_logic ;
signal N_7453 : std_logic ;
signal N_7454 : std_logic ;
signal N_7455 : std_logic ;
signal N_7456 : std_logic ;
signal N_7457 : std_logic ;
signal N_7458 : std_logic ;
signal N_7459 : std_logic ;
signal N_7460 : std_logic ;
signal N_7461 : std_logic ;
signal N_7462 : std_logic ;
signal N_7463 : std_logic ;
signal N_7464 : std_logic ;
signal N_7465 : std_logic ;
signal N_7466 : std_logic ;
signal N_7467 : std_logic ;
signal N_7468 : std_logic ;
signal N_7469 : std_logic ;
signal N_7470 : std_logic ;
signal N_7471 : std_logic ;
signal N_7472 : std_logic ;
signal N_7473 : std_logic ;
signal N_7474 : std_logic ;
signal N_7475 : std_logic ;
signal N_7476 : std_logic ;
signal N_7477 : std_logic ;
signal N_7478 : std_logic ;
signal N_7479 : std_logic ;
signal N_7480 : std_logic ;
signal N_7481 : std_logic ;
signal N_7482 : std_logic ;
signal N_7483 : std_logic ;
signal N_7484 : std_logic ;
signal N_7485 : std_logic ;
signal N_7486 : std_logic ;
signal N_7487 : std_logic ;
signal N_7488 : std_logic ;
signal N_8038 : std_logic ;
signal N_8039 : std_logic ;
signal N_8040 : std_logic ;
signal N_8041 : std_logic ;
signal N_8042 : std_logic ;
signal N_8043 : std_logic ;
signal N_8044 : std_logic ;
signal N_8045 : std_logic ;
signal N_8046 : std_logic ;
signal N_8047 : std_logic ;
signal N_8048 : std_logic ;
signal N_8049 : std_logic ;
signal N_8050 : std_logic ;
signal N_8051 : std_logic ;
signal N_8052 : std_logic ;
signal N_8053 : std_logic ;
signal N_8054 : std_logic ;
signal N_8055 : std_logic ;
signal N_8056 : std_logic ;
signal N_8057 : std_logic ;
signal N_8058 : std_logic ;
signal N_8059 : std_logic ;
signal N_8060 : std_logic ;
signal N_8061 : std_logic ;
signal N_8062 : std_logic ;
signal N_8063 : std_logic ;
signal N_8064 : std_logic ;
signal N_8065 : std_logic ;
signal N_8066 : std_logic ;
signal N_8067 : std_logic ;
signal N_8068 : std_logic ;
signal N_8069 : std_logic ;
signal N_8070 : std_logic ;
signal N_8071 : std_logic ;
signal N_8072 : std_logic ;
signal N_8073 : std_logic ;
signal N_8074 : std_logic ;
signal N_8075 : std_logic ;
signal N_8076 : std_logic ;
signal N_8077 : std_logic ;
signal N_8078 : std_logic ;
signal N_8079 : std_logic ;
signal N_8080 : std_logic ;
signal N_8081 : std_logic ;
signal N_8082 : std_logic ;
signal N_8083 : std_logic ;
signal N_8084 : std_logic ;
signal N_8085 : std_logic ;
signal N_8086 : std_logic ;
signal N_8087 : std_logic ;
signal N_8088 : std_logic ;
signal N_8089 : std_logic ;
signal N_8090 : std_logic ;
signal N_8091 : std_logic ;
signal N_8092 : std_logic ;
signal N_8093 : std_logic ;
signal N_8094 : std_logic ;
signal N_8095 : std_logic ;
signal N_8096 : std_logic ;
signal N_8097 : std_logic ;
signal N_8098 : std_logic ;
signal N_8099 : std_logic ;
signal N_8100 : std_logic ;
signal N_8101 : std_logic ;
signal N_8102 : std_logic ;
signal N_8103 : std_logic ;
signal N_8104 : std_logic ;
signal N_8105 : std_logic ;
signal N_8106 : std_logic ;
signal N_8107 : std_logic ;
signal N_8108 : std_logic ;
signal N_8109 : std_logic ;
signal N_8110 : std_logic ;
signal N_8111 : std_logic ;
signal N_8112 : std_logic ;
signal N_8113 : std_logic ;
signal N_8114 : std_logic ;
signal N_8115 : std_logic ;
signal N_8116 : std_logic ;
signal N_8290 : std_logic ;
signal N_8291 : std_logic ;
signal N_8292 : std_logic ;
signal N_8293 : std_logic ;
signal N_8294 : std_logic ;
signal N_8295 : std_logic ;
signal N_8296 : std_logic ;
signal N_8297 : std_logic ;
signal N_8298 : std_logic ;
signal N_8299 : std_logic ;
signal N_8300 : std_logic ;
signal N_8301 : std_logic ;
signal N_8302 : std_logic ;
signal N_8303 : std_logic ;
signal N_8304 : std_logic ;
signal N_8305 : std_logic ;
signal N_8306 : std_logic ;
signal N_8307 : std_logic ;
signal N_8308 : std_logic ;
signal N_8309 : std_logic ;
signal N_8310 : std_logic ;
signal N_8311 : std_logic ;
signal N_8312 : std_logic ;
signal N_8313 : std_logic ;
signal N_8314 : std_logic ;
signal N_8315 : std_logic ;
signal N_8316 : std_logic ;
signal N_8317 : std_logic ;
signal N_8318 : std_logic ;
signal N_8319 : std_logic ;
signal N_8320 : std_logic ;
signal N_8321 : std_logic ;
signal N_8322 : std_logic ;
signal N_8323 : std_logic ;
signal N_8324 : std_logic ;
signal N_8325 : std_logic ;
signal N_8326 : std_logic ;
signal N_8327 : std_logic ;
signal N_8328 : std_logic ;
signal N_8329 : std_logic ;
signal N_8330 : std_logic ;
signal N_8331 : std_logic ;
signal N_8332 : std_logic ;
signal N_8333 : std_logic ;
signal N_8334 : std_logic ;
signal N_8335 : std_logic ;
signal N_8336 : std_logic ;
signal N_8337 : std_logic ;
signal N_8338 : std_logic ;
signal N_8339 : std_logic ;
signal N_8340 : std_logic ;
signal N_8341 : std_logic ;
signal N_8342 : std_logic ;
signal N_8343 : std_logic ;
signal N_8344 : std_logic ;
signal N_8345 : std_logic ;
signal N_8346 : std_logic ;
signal N_8347 : std_logic ;
signal N_8348 : std_logic ;
signal N_8349 : std_logic ;
signal N_8350 : std_logic ;
signal N_8351 : std_logic ;
signal N_8352 : std_logic ;
signal N_8353 : std_logic ;
signal N_8354 : std_logic ;
signal N_8355 : std_logic ;
signal N_8356 : std_logic ;
signal N_8357 : std_logic ;
signal N_8358 : std_logic ;
signal N_8359 : std_logic ;
signal N_8360 : std_logic ;
signal N_8361 : std_logic ;
signal N_8362 : std_logic ;
signal N_8363 : std_logic ;
signal N_8364 : std_logic ;
signal N_8365 : std_logic ;
signal N_8366 : std_logic ;
signal N_8367 : std_logic ;
signal N_8368 : std_logic ;
signal N_8542 : std_logic ;
signal N_8543 : std_logic ;
signal N_8544 : std_logic ;
signal N_8545 : std_logic ;
signal N_8546 : std_logic ;
signal N_8547 : std_logic ;
signal N_8548 : std_logic ;
signal N_8549 : std_logic ;
signal N_8550 : std_logic ;
signal N_8551 : std_logic ;
signal N_8552 : std_logic ;
signal N_8553 : std_logic ;
signal N_8554 : std_logic ;
signal N_8555 : std_logic ;
signal N_8556 : std_logic ;
signal N_8557 : std_logic ;
signal N_8558 : std_logic ;
signal N_8559 : std_logic ;
signal N_8560 : std_logic ;
signal N_8561 : std_logic ;
signal N_8562 : std_logic ;
signal N_8563 : std_logic ;
signal N_8564 : std_logic ;
signal N_8565 : std_logic ;
signal N_8566 : std_logic ;
signal N_8567 : std_logic ;
signal N_8568 : std_logic ;
signal N_8569 : std_logic ;
signal N_8570 : std_logic ;
signal N_8571 : std_logic ;
signal N_8572 : std_logic ;
signal N_8573 : std_logic ;
signal N_8574 : std_logic ;
signal N_8575 : std_logic ;
signal N_8576 : std_logic ;
signal N_8577 : std_logic ;
signal N_8578 : std_logic ;
signal N_8579 : std_logic ;
signal N_8580 : std_logic ;
signal N_8581 : std_logic ;
signal N_8582 : std_logic ;
signal N_8583 : std_logic ;
signal N_8584 : std_logic ;
signal N_8585 : std_logic ;
signal N_8586 : std_logic ;
signal N_8587 : std_logic ;
signal N_8588 : std_logic ;
signal N_8589 : std_logic ;
signal N_8590 : std_logic ;
signal N_8591 : std_logic ;
signal N_8592 : std_logic ;
signal N_8593 : std_logic ;
signal N_8594 : std_logic ;
signal N_8595 : std_logic ;
signal N_8596 : std_logic ;
signal N_8597 : std_logic ;
signal N_8598 : std_logic ;
signal N_8599 : std_logic ;
signal N_8600 : std_logic ;
signal N_8601 : std_logic ;
signal N_8602 : std_logic ;
signal N_8603 : std_logic ;
signal N_8604 : std_logic ;
signal N_8605 : std_logic ;
signal N_8606 : std_logic ;
signal N_8607 : std_logic ;
signal N_8608 : std_logic ;
signal N_8609 : std_logic ;
signal N_8610 : std_logic ;
signal N_8611 : std_logic ;
signal N_8612 : std_logic ;
signal N_8613 : std_logic ;
signal N_8614 : std_logic ;
signal N_8615 : std_logic ;
signal N_8616 : std_logic ;
signal N_8617 : std_logic ;
signal N_8618 : std_logic ;
signal N_8619 : std_logic ;
signal N_8620 : std_logic ;
signal N_9170 : std_logic ;
signal N_9171 : std_logic ;
signal N_9172 : std_logic ;
signal N_9173 : std_logic ;
signal N_9174 : std_logic ;
signal N_9175 : std_logic ;
signal N_9176 : std_logic ;
signal N_9177 : std_logic ;
signal N_9178 : std_logic ;
signal N_9179 : std_logic ;
signal N_9180 : std_logic ;
signal N_9181 : std_logic ;
signal N_9182 : std_logic ;
signal N_9183 : std_logic ;
signal N_9184 : std_logic ;
signal N_9185 : std_logic ;
signal N_9186 : std_logic ;
signal N_9187 : std_logic ;
signal N_9188 : std_logic ;
signal N_9189 : std_logic ;
signal N_9190 : std_logic ;
signal N_9191 : std_logic ;
signal N_9192 : std_logic ;
signal N_9193 : std_logic ;
signal N_9194 : std_logic ;
signal N_9195 : std_logic ;
signal N_9196 : std_logic ;
signal N_9197 : std_logic ;
signal N_9198 : std_logic ;
signal N_9199 : std_logic ;
signal N_9200 : std_logic ;
signal N_9201 : std_logic ;
signal N_9202 : std_logic ;
signal N_9203 : std_logic ;
signal N_9204 : std_logic ;
signal N_9205 : std_logic ;
signal N_9206 : std_logic ;
signal N_9207 : std_logic ;
signal N_9208 : std_logic ;
signal N_9209 : std_logic ;
signal N_9210 : std_logic ;
signal N_9211 : std_logic ;
signal N_9212 : std_logic ;
signal N_9213 : std_logic ;
signal N_9214 : std_logic ;
signal N_9215 : std_logic ;
signal N_9216 : std_logic ;
signal N_9217 : std_logic ;
signal N_9218 : std_logic ;
signal N_9219 : std_logic ;
signal N_9220 : std_logic ;
signal N_9221 : std_logic ;
signal N_9222 : std_logic ;
signal N_9223 : std_logic ;
signal N_9224 : std_logic ;
signal N_9225 : std_logic ;
signal N_9226 : std_logic ;
signal N_9227 : std_logic ;
signal N_9228 : std_logic ;
signal N_9229 : std_logic ;
signal N_9230 : std_logic ;
signal N_9231 : std_logic ;
signal N_9232 : std_logic ;
signal N_9233 : std_logic ;
signal N_9234 : std_logic ;
signal N_9235 : std_logic ;
signal N_9236 : std_logic ;
signal N_9237 : std_logic ;
signal N_9238 : std_logic ;
signal N_9239 : std_logic ;
signal N_9240 : std_logic ;
signal N_9241 : std_logic ;
signal N_9242 : std_logic ;
signal N_9243 : std_logic ;
signal N_9244 : std_logic ;
signal N_9245 : std_logic ;
signal N_9246 : std_logic ;
signal N_9247 : std_logic ;
signal N_9248 : std_logic ;
signal N_9422 : std_logic ;
signal N_9423 : std_logic ;
signal N_9424 : std_logic ;
signal N_9425 : std_logic ;
signal N_9426 : std_logic ;
signal N_9427 : std_logic ;
signal N_9428 : std_logic ;
signal N_9429 : std_logic ;
signal N_9430 : std_logic ;
signal N_9431 : std_logic ;
signal N_9432 : std_logic ;
signal N_9433 : std_logic ;
signal N_9434 : std_logic ;
signal N_9435 : std_logic ;
signal N_9436 : std_logic ;
signal N_9437 : std_logic ;
signal N_9438 : std_logic ;
signal N_9439 : std_logic ;
signal N_9440 : std_logic ;
signal N_9441 : std_logic ;
signal N_9442 : std_logic ;
signal N_9443 : std_logic ;
signal N_9444 : std_logic ;
signal N_9445 : std_logic ;
signal N_9446 : std_logic ;
signal N_9447 : std_logic ;
signal N_9448 : std_logic ;
signal N_9449 : std_logic ;
signal N_9450 : std_logic ;
signal N_9451 : std_logic ;
signal N_9452 : std_logic ;
signal N_9453 : std_logic ;
signal N_9454 : std_logic ;
signal N_9455 : std_logic ;
signal N_9456 : std_logic ;
signal N_9457 : std_logic ;
signal N_9458 : std_logic ;
signal N_9459 : std_logic ;
signal N_9460 : std_logic ;
signal N_9461 : std_logic ;
signal N_9462 : std_logic ;
signal N_9463 : std_logic ;
signal N_9464 : std_logic ;
signal N_9465 : std_logic ;
signal N_9466 : std_logic ;
signal N_9467 : std_logic ;
signal N_9468 : std_logic ;
signal N_9469 : std_logic ;
signal N_9470 : std_logic ;
signal N_9471 : std_logic ;
signal N_9472 : std_logic ;
signal N_9473 : std_logic ;
signal N_9474 : std_logic ;
signal N_9475 : std_logic ;
signal N_9476 : std_logic ;
signal N_9477 : std_logic ;
signal N_9478 : std_logic ;
signal N_9479 : std_logic ;
signal N_9480 : std_logic ;
signal N_9481 : std_logic ;
signal N_9482 : std_logic ;
signal N_9483 : std_logic ;
signal N_9484 : std_logic ;
signal N_9485 : std_logic ;
signal N_9486 : std_logic ;
signal N_9487 : std_logic ;
signal N_9488 : std_logic ;
signal N_9489 : std_logic ;
signal N_9490 : std_logic ;
signal N_9491 : std_logic ;
signal N_9492 : std_logic ;
signal N_9493 : std_logic ;
signal N_9494 : std_logic ;
signal N_9495 : std_logic ;
signal N_9496 : std_logic ;
signal N_9497 : std_logic ;
signal N_9498 : std_logic ;
signal N_9499 : std_logic ;
signal N_9500 : std_logic ;
signal N_9674 : std_logic ;
signal N_9675 : std_logic ;
signal N_9676 : std_logic ;
signal N_9677 : std_logic ;
signal N_9678 : std_logic ;
signal N_9679 : std_logic ;
signal N_9680 : std_logic ;
signal N_9681 : std_logic ;
signal N_9682 : std_logic ;
signal N_9683 : std_logic ;
signal N_9684 : std_logic ;
signal N_9685 : std_logic ;
signal N_9686 : std_logic ;
signal N_9687 : std_logic ;
signal N_9688 : std_logic ;
signal N_9689 : std_logic ;
signal N_9690 : std_logic ;
signal N_9691 : std_logic ;
signal N_9692 : std_logic ;
signal N_9693 : std_logic ;
signal N_9694 : std_logic ;
signal N_9695 : std_logic ;
signal N_9696 : std_logic ;
signal N_9697 : std_logic ;
signal N_9698 : std_logic ;
signal N_9699 : std_logic ;
signal N_9700 : std_logic ;
signal N_9701 : std_logic ;
signal N_9702 : std_logic ;
signal N_9703 : std_logic ;
signal N_9704 : std_logic ;
signal N_9705 : std_logic ;
signal N_9706 : std_logic ;
signal N_9707 : std_logic ;
signal N_9708 : std_logic ;
signal N_9709 : std_logic ;
signal N_9710 : std_logic ;
signal N_9711 : std_logic ;
signal N_9712 : std_logic ;
signal N_9713 : std_logic ;
signal N_9714 : std_logic ;
signal N_9715 : std_logic ;
signal N_9716 : std_logic ;
signal N_9717 : std_logic ;
signal N_9718 : std_logic ;
signal N_9719 : std_logic ;
signal N_9720 : std_logic ;
signal N_9721 : std_logic ;
signal N_9722 : std_logic ;
signal N_9723 : std_logic ;
signal N_9724 : std_logic ;
signal N_9725 : std_logic ;
signal N_9726 : std_logic ;
signal N_9727 : std_logic ;
signal N_9728 : std_logic ;
signal N_9729 : std_logic ;
signal N_9730 : std_logic ;
signal N_9731 : std_logic ;
signal N_9732 : std_logic ;
signal N_9733 : std_logic ;
signal N_9734 : std_logic ;
signal N_9735 : std_logic ;
signal N_9736 : std_logic ;
signal N_9737 : std_logic ;
signal N_9738 : std_logic ;
signal N_9739 : std_logic ;
signal N_9740 : std_logic ;
signal N_9741 : std_logic ;
signal N_9742 : std_logic ;
signal N_9743 : std_logic ;
signal N_9744 : std_logic ;
signal N_9745 : std_logic ;
signal N_9746 : std_logic ;
signal N_9747 : std_logic ;
signal N_9748 : std_logic ;
signal N_9749 : std_logic ;
signal N_9750 : std_logic ;
signal N_9751 : std_logic ;
signal N_9752 : std_logic ;
signal N_10302 : std_logic ;
signal N_10303 : std_logic ;
signal N_10304 : std_logic ;
signal N_10305 : std_logic ;
signal N_10306 : std_logic ;
signal N_10307 : std_logic ;
signal N_10308 : std_logic ;
signal N_10309 : std_logic ;
signal N_10310 : std_logic ;
signal N_10311 : std_logic ;
signal N_10312 : std_logic ;
signal N_10313 : std_logic ;
signal N_10314 : std_logic ;
signal N_10315 : std_logic ;
signal N_10316 : std_logic ;
signal N_10317 : std_logic ;
signal N_10318 : std_logic ;
signal N_10319 : std_logic ;
signal N_10320 : std_logic ;
signal N_10321 : std_logic ;
signal N_10322 : std_logic ;
signal N_10323 : std_logic ;
signal N_10324 : std_logic ;
signal N_10325 : std_logic ;
signal N_10326 : std_logic ;
signal N_10327 : std_logic ;
signal N_10328 : std_logic ;
signal N_10329 : std_logic ;
signal N_10330 : std_logic ;
signal N_10331 : std_logic ;
signal N_10332 : std_logic ;
signal N_10333 : std_logic ;
signal N_10334 : std_logic ;
signal N_10335 : std_logic ;
signal N_10336 : std_logic ;
signal N_10337 : std_logic ;
signal N_10338 : std_logic ;
signal N_10339 : std_logic ;
signal N_10340 : std_logic ;
signal N_10341 : std_logic ;
signal N_10342 : std_logic ;
signal N_10343 : std_logic ;
signal N_10344 : std_logic ;
signal N_10345 : std_logic ;
signal N_10346 : std_logic ;
signal N_10347 : std_logic ;
signal N_10348 : std_logic ;
signal N_10349 : std_logic ;
signal N_10350 : std_logic ;
signal N_10351 : std_logic ;
signal N_10352 : std_logic ;
signal N_10353 : std_logic ;
signal N_10354 : std_logic ;
signal N_10355 : std_logic ;
signal N_10356 : std_logic ;
signal N_10357 : std_logic ;
signal N_10358 : std_logic ;
signal N_10359 : std_logic ;
signal N_10360 : std_logic ;
signal N_10361 : std_logic ;
signal N_10362 : std_logic ;
signal N_10363 : std_logic ;
signal N_10364 : std_logic ;
signal N_10365 : std_logic ;
signal N_10366 : std_logic ;
signal N_10367 : std_logic ;
signal N_10368 : std_logic ;
signal N_10369 : std_logic ;
signal N_10370 : std_logic ;
signal N_10371 : std_logic ;
signal N_10372 : std_logic ;
signal N_10373 : std_logic ;
signal N_10374 : std_logic ;
signal N_10375 : std_logic ;
signal N_10376 : std_logic ;
signal N_10377 : std_logic ;
signal N_10378 : std_logic ;
signal N_10379 : std_logic ;
signal N_10380 : std_logic ;
signal N_10554 : std_logic ;
signal N_10555 : std_logic ;
signal N_10556 : std_logic ;
signal N_10557 : std_logic ;
signal N_10558 : std_logic ;
signal N_10559 : std_logic ;
signal N_10560 : std_logic ;
signal N_10561 : std_logic ;
signal N_10562 : std_logic ;
signal N_10563 : std_logic ;
signal N_10564 : std_logic ;
signal N_10565 : std_logic ;
signal N_10566 : std_logic ;
signal N_10567 : std_logic ;
signal N_10568 : std_logic ;
signal N_10569 : std_logic ;
signal N_10570 : std_logic ;
signal N_10571 : std_logic ;
signal N_10572 : std_logic ;
signal N_10573 : std_logic ;
signal N_10574 : std_logic ;
signal N_10575 : std_logic ;
signal N_10576 : std_logic ;
signal N_10577 : std_logic ;
signal N_10578 : std_logic ;
signal N_10579 : std_logic ;
signal N_10580 : std_logic ;
signal N_10581 : std_logic ;
signal N_10582 : std_logic ;
signal N_10583 : std_logic ;
signal N_10584 : std_logic ;
signal N_10585 : std_logic ;
signal N_10586 : std_logic ;
signal N_10587 : std_logic ;
signal N_10588 : std_logic ;
signal N_10589 : std_logic ;
signal N_10590 : std_logic ;
signal N_10591 : std_logic ;
signal N_10592 : std_logic ;
signal N_10593 : std_logic ;
signal N_10594 : std_logic ;
signal N_10595 : std_logic ;
signal N_10596 : std_logic ;
signal N_10597 : std_logic ;
signal N_10598 : std_logic ;
signal N_10599 : std_logic ;
signal N_10600 : std_logic ;
signal N_10601 : std_logic ;
signal N_10602 : std_logic ;
signal N_10603 : std_logic ;
signal N_10604 : std_logic ;
signal N_10605 : std_logic ;
signal N_10606 : std_logic ;
signal N_10607 : std_logic ;
signal N_10608 : std_logic ;
signal N_10609 : std_logic ;
signal N_10610 : std_logic ;
signal N_10611 : std_logic ;
signal N_10612 : std_logic ;
signal N_10613 : std_logic ;
signal N_10614 : std_logic ;
signal N_10615 : std_logic ;
signal N_10616 : std_logic ;
signal N_10617 : std_logic ;
signal N_10618 : std_logic ;
signal N_10619 : std_logic ;
signal N_10620 : std_logic ;
signal N_10621 : std_logic ;
signal N_10622 : std_logic ;
signal N_10623 : std_logic ;
signal N_10624 : std_logic ;
signal N_10625 : std_logic ;
signal N_10626 : std_logic ;
signal N_10627 : std_logic ;
signal N_10628 : std_logic ;
signal N_10629 : std_logic ;
signal N_10630 : std_logic ;
signal N_10631 : std_logic ;
signal R1IN_4_ADD_2_1 : std_logic ;
signal NN_3 : std_logic ;
signal NN_4 : std_logic ;
signal NN_5 : std_logic ;
signal NN_6 : std_logic ;
signal NN_7 : std_logic ;
signal NN_8 : std_logic ;
signal NN_9 : std_logic ;
signal NN_10 : std_logic ;
signal N_10632 : std_logic ;
signal N_10806 : std_logic ;
signal N_10807 : std_logic ;
signal N_10808 : std_logic ;
signal N_10809 : std_logic ;
signal N_10810 : std_logic ;
signal N_10811 : std_logic ;
signal N_10812 : std_logic ;
signal N_10813 : std_logic ;
signal N_10814 : std_logic ;
signal N_10815 : std_logic ;
signal N_10816 : std_logic ;
signal N_10817 : std_logic ;
signal N_10818 : std_logic ;
signal N_10819 : std_logic ;
signal N_10820 : std_logic ;
signal N_10821 : std_logic ;
signal N_10822 : std_logic ;
signal N_10823 : std_logic ;
signal N_10824 : std_logic ;
signal N_10825 : std_logic ;
signal N_10826 : std_logic ;
signal N_10827 : std_logic ;
signal N_10828 : std_logic ;
signal N_10829 : std_logic ;
signal N_10830 : std_logic ;
signal N_10831 : std_logic ;
signal N_10832 : std_logic ;
signal N_10833 : std_logic ;
signal N_10834 : std_logic ;
signal N_10835 : std_logic ;
signal N_10836 : std_logic ;
signal N_10837 : std_logic ;
signal N_10838 : std_logic ;
signal N_10839 : std_logic ;
signal N_10840 : std_logic ;
signal N_10841 : std_logic ;
signal N_10842 : std_logic ;
signal N_10843 : std_logic ;
signal N_10844 : std_logic ;
signal N_10845 : std_logic ;
signal N_10846 : std_logic ;
signal N_10847 : std_logic ;
signal N_10848 : std_logic ;
signal N_1781_RETI : std_logic ;
signal R2_PIPE_104_RET_1027 : std_logic ;
signal N_1779_RETI : std_logic ;
signal R2_PIPE_104_RET_1028 : std_logic ;
signal N_1777_RETI : std_logic ;
signal R2_PIPE_104_RET_1029 : std_logic ;
signal N_1775_RETI : std_logic ;
signal R2_PIPE_104_RET_1030 : std_logic ;
signal N_1773_RETI : std_logic ;
signal R2_PIPE_104_RET_1031 : std_logic ;
signal N_1771_RETI : std_logic ;
signal R2_PIPE_104_RET_1032 : std_logic ;
signal N_1769_RETI : std_logic ;
signal R2_PIPE_104_RET_1033 : std_logic ;
signal N_1767_RETI : std_logic ;
signal R2_PIPE_104_RET_1034 : std_logic ;
signal N_1765_RETI : std_logic ;
signal R2_PIPE_104_RET_1035 : std_logic ;
signal N_1763_RETI : std_logic ;
signal R2_PIPE_104_RET_1036 : std_logic ;
signal N_1761_RETI : std_logic ;
signal R2_PIPE_104_RET_1037 : std_logic ;
signal N_1759_RETI : std_logic ;
signal R2_PIPE_104_RET_1038 : std_logic ;
signal N_1757_RETI : std_logic ;
signal R2_PIPE_104_RET_1039 : std_logic ;
signal N_1755_RETI : std_logic ;
signal R2_PIPE_104_RET_1040 : std_logic ;
signal N_1753_RETI : std_logic ;
signal R2_PIPE_104_RET_1041 : std_logic ;
signal N_1751_RETI : std_logic ;
signal R2_PIPE_104_RET_1042 : std_logic ;
signal N_1749_RETI : std_logic ;
signal R2_PIPE_104_RET_1043 : std_logic ;
signal N_1747_RETI : std_logic ;
signal R2_PIPE_104_RET_1044 : std_logic ;
signal N_1745_RETI : std_logic ;
signal R2_PIPE_104_RET_1045 : std_logic ;
signal N_1743_RETI : std_logic ;
signal R2_PIPE_104_RET_1046 : std_logic ;
signal N_1741_RETI : std_logic ;
signal R2_PIPE_104_RET_1047 : std_logic ;
signal N_1739_RETI : std_logic ;
signal R2_PIPE_104_RET_1048 : std_logic ;
signal N_1737_RETI : std_logic ;
signal R2_PIPE_104_RET_1049 : std_logic ;
signal N_1735_RETI : std_logic ;
signal R2_PIPE_104_RET_1050 : std_logic ;
signal N_1733_RETI : std_logic ;
signal R2_PIPE_104_RET_1051 : std_logic ;
signal N_1731_RETI : std_logic ;
signal R2_PIPE_104_RET_1052 : std_logic ;
signal N_1729_RETI : std_logic ;
signal R2_PIPE_104_RET_1053 : std_logic ;
signal N_1727_RETI : std_logic ;
signal R2_PIPE_104_RET_1054 : std_logic ;
signal N_1725_RETI : std_logic ;
signal R2_PIPE_104_RET_1055 : std_logic ;
signal N_1723_RETI : std_logic ;
signal R2_PIPE_104_RET_1056 : std_logic ;
signal N_1721_RETI : std_logic ;
signal R2_PIPE_104_RET_1057 : std_logic ;
signal N_1719_RETI : std_logic ;
signal R2_PIPE_104_RET_1058 : std_logic ;
signal N_1717_RETI : std_logic ;
signal R2_PIPE_104_RET_1059 : std_logic ;
signal N_1715_RETI : std_logic ;
signal R2_PIPE_104_RET_1060 : std_logic ;
signal R1IN_4_ADD_2_1_AXB_0_RETI : std_logic ;
signal R1IN_4_ADD_2_1_AXB_0 : std_logic ;
signal N_10849 : std_logic ;
signal NN_11 : std_logic ;
component DSP48
generic (
AREG : integer := 0;
BREG : integer := 0;
CREG : integer := 0;
PREG : integer := 0;
MREG : integer := 0;
SUBTRACTREG : integer := 0;
OPMODEREG : integer := 0;
CARRYINSELREG : integer := 0;
CARRYINREG : integer := 0;
B_INPUT : string := "DIRECT";
LEGACY_MODE : string := "MULT18X18S"
);
port(
A : in std_logic_vector(17 downto 0);
B : in std_logic_vector(17 downto 0);
C : in std_logic_vector(47 downto 0);
BCIN : in std_logic_vector(17 downto 0);
PCIN : in std_logic_vector(47 downto 0);
OPMODE : in std_logic_vector(6 downto 0);
SUBTRACT : in std_logic;
CARRYIN : in std_logic;
CARRYINSEL : in std_logic_vector(1 downto 0);
CLK : in std_logic;
CEA : in std_logic;
CEB : in std_logic;
CEC : in std_logic;
CEP : in std_logic;
CEM : in std_logic;
CECARRYIN : in std_logic;
CECTRL : in std_logic;
CECINSUB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
RSTC : in std_logic;
RSTP : in std_logic;
RSTM : in std_logic;
RSTCTRL : in std_logic;
RSTCARRYIN : in std_logic;
BCOUT : out std_logic_vector(17 downto 0);
P : out std_logic_vector(47 downto 0);
PCOUT : out std_logic_vector(47 downto 0) );
end component;
begin
R1IN_ADD_2_0_AXB_1_Z5286: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(18),
I1 => R1IN_ADD_1FF(1),
O => R1IN_ADD_2_0_AXB_1);
R1IN_ADD_2_0_AXB_2_Z5287: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(19),
I1 => R1IN_ADD_1FF(2),
O => R1IN_ADD_2_0_AXB_2);
R1IN_ADD_2_0_AXB_3_Z5288: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(20),
I1 => R1IN_ADD_1FF(3),
O => R1IN_ADD_2_0_AXB_3);
R1IN_ADD_2_0_AXB_4_Z5289: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(21),
I1 => R1IN_ADD_1FF(4),
O => R1IN_ADD_2_0_AXB_4);
R1IN_ADD_2_0_AXB_5_Z5290: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(22),
I1 => R1IN_ADD_1FF(5),
O => R1IN_ADD_2_0_AXB_5);
R1IN_ADD_2_0_AXB_6_Z5291: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(23),
I1 => R1IN_ADD_1FF(6),
O => R1IN_ADD_2_0_AXB_6);
R1IN_ADD_2_0_AXB_7_Z5292: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(24),
I1 => R1IN_ADD_1FF(7),
O => R1IN_ADD_2_0_AXB_7);
R1IN_ADD_2_0_AXB_8_Z5293: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(25),
I1 => R1IN_ADD_1FF(8),
O => R1IN_ADD_2_0_AXB_8);
R1IN_ADD_2_0_AXB_9_Z5294: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(26),
I1 => R1IN_ADD_1FF(9),
O => R1IN_ADD_2_0_AXB_9);
R1IN_ADD_2_0_AXB_10_Z5295: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(27),
I1 => R1IN_ADD_1FF(10),
O => R1IN_ADD_2_0_AXB_10);
R1IN_ADD_2_0_AXB_11_Z5296: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(28),
I1 => R1IN_ADD_1FF(11),
O => R1IN_ADD_2_0_AXB_11);
R1IN_ADD_2_0_AXB_12_Z5297: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(29),
I1 => R1IN_ADD_1FF(12),
O => R1IN_ADD_2_0_AXB_12);
R1IN_ADD_2_0_AXB_13_Z5298: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(30),
I1 => R1IN_ADD_1FF(13),
O => R1IN_ADD_2_0_AXB_13);
R1IN_ADD_2_0_AXB_14_Z5299: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(31),
I1 => R1IN_ADD_1FF(14),
O => R1IN_ADD_2_0_AXB_14);
R1IN_ADD_2_0_AXB_15_Z5300: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(32),
I1 => R1IN_ADD_1FF(15),
O => R1IN_ADD_2_0_AXB_15);
R1IN_ADD_2_0_AXB_16_Z5301: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_1FF(33),
I1 => R1IN_ADD_1FF(16),
O => R1IN_ADD_2_0_AXB_16);
R1IN_ADD_2_0_AXB_17_Z5302: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(0),
I1 => R1IN_ADD_1FF(17),
O => R1IN_ADD_2_0_AXB_17);
R1IN_ADD_2_0_AXB_18_Z5303: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(1),
I1 => R1IN_ADD_1FF(18),
O => R1IN_ADD_2_0_AXB_18);
R1IN_ADD_2_0_AXB_19_Z5304: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(2),
I1 => R1IN_ADD_1FF(19),
O => R1IN_ADD_2_0_AXB_19);
R1IN_ADD_2_0_AXB_20_Z5305: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(3),
I1 => R1IN_ADD_1FF(20),
O => R1IN_ADD_2_0_AXB_20);
R1IN_ADD_2_0_AXB_21_Z5306: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(4),
I1 => R1IN_ADD_1FF(21),
O => R1IN_ADD_2_0_AXB_21);
R1IN_ADD_2_0_AXB_22_Z5307: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(5),
I1 => R1IN_ADD_1FF(22),
O => R1IN_ADD_2_0_AXB_22);
R1IN_ADD_2_0_AXB_23_Z5308: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(6),
I1 => R1IN_ADD_1FF(23),
O => R1IN_ADD_2_0_AXB_23);
R1IN_ADD_2_0_AXB_24_Z5309: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(7),
I1 => R1IN_ADD_1FF(24),
O => R1IN_ADD_2_0_AXB_24);
R1IN_ADD_2_0_AXB_25_Z5310: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(8),
I1 => R1IN_ADD_1FF(25),
O => R1IN_ADD_2_0_AXB_25);
R1IN_ADD_2_0_AXB_26_Z5311: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(9),
I1 => R1IN_ADD_1FF(26),
O => R1IN_ADD_2_0_AXB_26);
R1IN_ADD_2_0_AXB_27_Z5312: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(10),
I1 => R1IN_ADD_1FF(27),
O => R1IN_ADD_2_0_AXB_27);
R1IN_ADD_2_0_AXB_28_Z5313: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(11),
I1 => R1IN_ADD_1FF(28),
O => R1IN_ADD_2_0_AXB_28);
R1IN_ADD_2_0_AXB_29_Z5314: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(12),
I1 => R1IN_ADD_1FF(29),
O => R1IN_ADD_2_0_AXB_29);
R1IN_ADD_2_0_AXB_30_Z5315: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(13),
I1 => R1IN_ADD_1FF(30),
O => R1IN_ADD_2_0_AXB_30);
R1IN_ADD_2_0_AXB_31_Z5316: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(14),
I1 => R1IN_ADD_1FF(31),
O => R1IN_ADD_2_0_AXB_31);
R1IN_ADD_2_0_AXB_32_Z5317: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4FF(15),
I1 => R1IN_ADD_1FF(32),
O => R1IN_ADD_2_0_AXB_32);
R1IN_ADD_2_0_AXB_33_Z5318: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4FF(16),
I1 => R1IN_ADD_1_0_CRY_31_RETO_18,
I2 => R2_PIPE_138_RET,
I3 => R2_PIPE_138_RET_1,
O => R1IN_ADD_2_0_AXB_33);
R1IN_ADD_2_0_AXB_34_Z5319: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(17),
I1 => R1IN_ADD_1_0_CRY_31_RETO_17,
I2 => R2_PIPE_139_RET,
I3 => R2_PIPE_139_RET_1,
O => R1IN_ADD_2_0_AXB_34);
R1IN_ADD_2_0_AXB_35_Z5320: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(18),
I1 => R1IN_ADD_1_0_CRY_31_RETO_16,
I2 => R2_PIPE_140_RET,
I3 => R2_PIPE_140_RET_1,
O => R1IN_ADD_2_0_AXB_35);
R1IN_ADD_2_0_AXB_36_Z5321: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(19),
I1 => R1IN_ADD_1_0_CRY_31_RETO_15,
I2 => R2_PIPE_141_RET,
I3 => R2_PIPE_141_RET_1,
O => R1IN_ADD_2_0_AXB_36);
R1IN_ADD_2_0_AXB_37_Z5322: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(20),
I1 => R1IN_ADD_1_0_CRY_31_RETO_14,
I2 => R2_PIPE_142_RET,
I3 => R2_PIPE_142_RET_1,
O => R1IN_ADD_2_0_AXB_37);
R1IN_ADD_2_0_AXB_38_Z5323: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(21),
I1 => R1IN_ADD_1_0_CRY_31_RETO_13,
I2 => R2_PIPE_143_RET,
I3 => R2_PIPE_143_RET_1,
O => R1IN_ADD_2_0_AXB_38);
R1IN_ADD_2_0_AXB_39_Z5324: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(22),
I1 => R1IN_ADD_1_0_CRY_31_RETO_12,
I2 => R2_PIPE_144_RET,
I3 => R2_PIPE_144_RET_1,
O => R1IN_ADD_2_0_AXB_39);
R1IN_ADD_2_0_AXB_40_Z5325: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(23),
I1 => R1IN_ADD_1_0_CRY_31_RETO_11,
I2 => R2_PIPE_145_RET,
I3 => R2_PIPE_145_RET_1,
O => R1IN_ADD_2_0_AXB_40);
R1IN_ADD_2_0_AXB_41_Z5326: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(24),
I1 => R1IN_ADD_1_0_CRY_31_RETO_10,
I2 => R2_PIPE_146_RET,
I3 => R2_PIPE_146_RET_1,
O => R1IN_ADD_2_0_AXB_41);
R1IN_ADD_2_0_AXB_42_Z5327: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(25),
I1 => R1IN_ADD_1_0_CRY_31_RETO_9,
I2 => R2_PIPE_147_RET,
I3 => R2_PIPE_147_RET_1,
O => R1IN_ADD_2_0_AXB_42);
R1IN_ADD_2_0_AXB_43_Z5328: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(26),
I1 => R1IN_ADD_1_0_CRY_31_RETO_8,
I2 => R2_PIPE_148_RET,
I3 => R2_PIPE_148_RET_1,
O => R1IN_ADD_2_0_AXB_43);
R1IN_ADD_2_0_AXB_44_Z5329: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(27),
I1 => R1IN_ADD_1_0_CRY_31_RETO_7,
I2 => R2_PIPE_149_RET,
I3 => R2_PIPE_149_RET_1,
O => R1IN_ADD_2_0_AXB_44);
R1IN_ADD_2_0_AXB_45_Z5330: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(28),
I1 => R1IN_ADD_1_0_CRY_31_RETO_6,
I2 => R2_PIPE_150_RET,
I3 => R2_PIPE_150_RET_1,
O => R1IN_ADD_2_0_AXB_45);
R1IN_ADD_2_0_AXB_46_Z5331: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(29),
I1 => R1IN_ADD_1_0_CRY_31_RETO_5,
I2 => R2_PIPE_151_RET,
I3 => R2_PIPE_151_RET_1,
O => R1IN_ADD_2_0_AXB_46);
R1IN_ADD_2_0_AXB_47_Z5332: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(30),
I1 => R1IN_ADD_1_0_CRY_31_RETO_4,
I2 => R2_PIPE_152_RET,
I3 => R2_PIPE_152_RET_1,
O => R1IN_ADD_2_0_AXB_47);
R1IN_ADD_2_0_AXB_48_Z5333: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(31),
I1 => R1IN_ADD_1_0_CRY_31_RETO_3,
I2 => R2_PIPE_153_RET,
I3 => R2_PIPE_153_RET_1,
O => R1IN_ADD_2_0_AXB_48);
R1IN_ADD_2_0_AXB_49_Z5334: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(32),
I1 => R1IN_ADD_1_0_CRY_31_RETO_2,
I2 => R2_PIPE_154_RET,
I3 => R2_PIPE_154_RET_1,
O => R1IN_ADD_2_0_AXB_49);
R1IN_ADD_2_0_AXB_50_Z5335: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(33),
I1 => R1IN_ADD_1_0_CRY_31_RETO_1,
I2 => R2_PIPE_155_RET,
I3 => R2_PIPE_155_RET_1,
O => R1IN_ADD_2_0_AXB_50);
R1IN_ADD_2_0_AXB_51_Z5336: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(34),
I1 => R1IN_ADD_1_0_CRY_31_RETO_0,
I2 => R2_PIPE_156_RET,
I3 => R2_PIPE_156_RET_1,
O => R1IN_ADD_2_0_AXB_51);
R1IN_ADD_2_0_AXB_52_Z5337: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(35),
I1 => R1IN_ADD_1_0_CRY_31_RETO,
I2 => R2_PIPE_157_RET,
I3 => R2_PIPE_157_RET_1,
O => R1IN_ADD_2_0_AXB_52);
R1IN_ADD_2_1_AXB_1_Z5338: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(37),
I1 => R1IN_ADD_1_0_CRY_31_RETO_25,
I2 => R2_PIPE_159_RET,
I3 => R2_PIPE_159_RET_1,
O => R1IN_ADD_2_1_AXB_1);
R1IN_ADD_2_1_AXB_2_Z5339: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(38),
I1 => R1IN_ADD_1_0_CRY_31_RETO_24,
I2 => R2_PIPE_160_RET,
I3 => R2_PIPE_160_RET_1,
O => R1IN_ADD_2_1_AXB_2);
R1IN_ADD_2_1_AXB_3_Z5340: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(39),
I1 => R1IN_ADD_1_0_CRY_31_RETO_23,
I2 => R2_PIPE_161_RET,
I3 => R2_PIPE_161_RET_1,
O => R1IN_ADD_2_1_AXB_3);
R1IN_ADD_2_1_AXB_4_Z5341: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(40),
I1 => R1IN_ADD_1_0_CRY_31_RETO_22,
I2 => R2_PIPE_162_RET,
I3 => R2_PIPE_162_RET_1,
O => R1IN_ADD_2_1_AXB_4);
R1IN_ADD_2_1_AXB_5_Z5342: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(41),
I1 => R1IN_ADD_1_0_CRY_31_RETO_21,
I2 => R2_PIPE_163_RET,
I3 => R2_PIPE_163_RET_1,
O => R1IN_ADD_2_1_AXB_5);
R1IN_ADD_2_1_AXB_6_Z5343: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(42),
I1 => R1IN_ADD_1_0_CRY_31_RETO_20,
I2 => R2_PIPE_164_RET,
I3 => R2_PIPE_164_RET_1,
O => R1IN_ADD_2_1_AXB_6);
R1IN_ADD_2_1_AXB_7_Z5344: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(43),
I1 => R1IN_ADD_1_0_CRY_31_RETO_19,
I2 => R2_PIPE_165_RET,
I3 => R2_PIPE_165_RET_1,
O => R1IN_ADD_2_1_AXB_7);
R1IN_ADD_2_1_AXB_8_Z5345: LUT4
generic map(
INIT => X"596A"
)
port map (
I0 => R1IN_4F(44),
I1 => R1IN_ADD_1_0_CRY_31_RETO_27,
I2 => R1IN_ADD_1_1_0_CRY_28_RETO,
I3 => R1IN_ADD_1_1_CRY_28_RETO,
O => R1IN_ADD_2_1_AXB_8);
R1IN_ADD_2_1_AXB_9_Z5346: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4F(45),
O => R1IN_ADD_2_1_AXB_9);
R1IN_ADD_2_1_AXB_10_Z5347: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4F(46),
O => R1IN_ADD_2_1_AXB_10);
R1IN_ADD_2_1_AXB_11_Z5348: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4F(47),
O => R1IN_ADD_2_1_AXB_11);
R1IN_ADD_2_1_AXB_12_Z5349: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4F(48),
O => R1IN_ADD_2_1_AXB_12);
R1IN_ADD_2_1_AXB_13_Z5350: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4F(49),
O => R1IN_ADD_2_1_AXB_13);
R1IN_ADD_2_1_AXB_14_Z5351: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4F(50),
O => R1IN_ADD_2_1_AXB_14);
R1IN_ADD_2_1_AXB_15_Z5352: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4F(51),
O => R1IN_ADD_2_1_AXB_15);
R1IN_ADD_2_1_AXB_16_Z5353: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4F(52),
O => R1IN_ADD_2_1_AXB_16);
R1IN_ADD_2_1_AXB_17_Z5354: LUT3
generic map(
INIT => X"72"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_32,
I1 => R1IN_4_ADD_2_1_0_AXB_0_RETO,
I2 => R1IN_4_ADD_2_1_AXB_0,
O => R1IN_ADD_2_1_AXB_17);
R1IN_ADD_2_1_AXB_18_Z5355: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4(54),
O => R1IN_ADD_2_1_AXB_18);
R1IN_ADD_2_1_AXB_19_Z5356: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_31,
I1 => R2_PIPE_104_RET_123,
I2 => R2_PIPE_104_RET_1059,
O => R1IN_ADD_2_1_AXB_19);
R1IN_ADD_2_1_AXB_20_Z5357: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_30,
I1 => R2_PIPE_104_RET_122,
I2 => R2_PIPE_104_RET_1058,
O => R1IN_ADD_2_1_AXB_20);
R1IN_ADD_2_1_AXB_21_Z5358: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_29,
I1 => R2_PIPE_104_RET_121,
I2 => R2_PIPE_104_RET_1057,
O => R1IN_ADD_2_1_AXB_21);
R1IN_ADD_2_1_AXB_22_Z5359: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_28,
I1 => R2_PIPE_104_RET_120,
I2 => R2_PIPE_104_RET_1056,
O => R1IN_ADD_2_1_AXB_22);
R1IN_ADD_2_1_AXB_23_Z5360: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_27,
I1 => R2_PIPE_104_RET_119,
I2 => R2_PIPE_104_RET_1055,
O => R1IN_ADD_2_1_AXB_23);
R1IN_ADD_2_1_AXB_24_Z5361: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_26,
I1 => R2_PIPE_104_RET_118,
I2 => R2_PIPE_104_RET_1054,
O => R1IN_ADD_2_1_AXB_24);
R1IN_ADD_2_1_AXB_25_Z5362: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_25,
I1 => R2_PIPE_104_RET_117,
I2 => R2_PIPE_104_RET_1053,
O => R1IN_ADD_2_1_AXB_25);
R1IN_ADD_2_1_AXB_26_Z5363: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_24,
I1 => R2_PIPE_104_RET_116,
I2 => R2_PIPE_104_RET_1052,
O => R1IN_ADD_2_1_AXB_26);
R1IN_ADD_2_1_AXB_27_Z5364: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_23,
I1 => R2_PIPE_104_RET_115,
I2 => R2_PIPE_104_RET_1051,
O => R1IN_ADD_2_1_AXB_27);
R1IN_ADD_2_1_AXB_28_Z5365: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_22,
I1 => R2_PIPE_104_RET_114,
I2 => R2_PIPE_104_RET_1050,
O => R1IN_ADD_2_1_AXB_28);
R1IN_ADD_2_1_AXB_29_Z5366: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_21,
I1 => R2_PIPE_104_RET_113,
I2 => R2_PIPE_104_RET_1049,
O => R1IN_ADD_2_1_AXB_29);
R1IN_ADD_2_1_AXB_30_Z5367: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_20,
I1 => R2_PIPE_104_RET_112,
I2 => R2_PIPE_104_RET_1048,
O => R1IN_ADD_2_1_AXB_30);
R1IN_ADD_2_1_AXB_31_Z5368: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_19,
I1 => R2_PIPE_104_RET_111,
I2 => R2_PIPE_104_RET_1047,
O => R1IN_ADD_2_1_AXB_31);
R1IN_ADD_2_1_AXB_32_Z5369: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_18,
I1 => R2_PIPE_104_RET_110,
I2 => R2_PIPE_104_RET_1046,
O => R1IN_ADD_2_1_AXB_32);
R1IN_ADD_2_1_AXB_33_Z5370: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_17,
I1 => R2_PIPE_104_RET_109,
I2 => R2_PIPE_104_RET_1045,
O => R1IN_ADD_2_1_AXB_33);
R1IN_ADD_2_1_AXB_34_Z5371: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_16,
I1 => R2_PIPE_104_RET_108,
I2 => R2_PIPE_104_RET_1044,
O => R1IN_ADD_2_1_AXB_34);
R1IN_ADD_2_1_AXB_35_Z5372: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_15,
I1 => R2_PIPE_104_RET_107,
I2 => R2_PIPE_104_RET_1043,
O => R1IN_ADD_2_1_AXB_35);
R1IN_ADD_2_1_AXB_36_Z5373: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_14,
I1 => R2_PIPE_104_RET_106,
I2 => R2_PIPE_104_RET_1042,
O => R1IN_ADD_2_1_AXB_36);
R1IN_ADD_2_1_AXB_37_Z5374: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_13,
I1 => R2_PIPE_104_RET_105,
I2 => R2_PIPE_104_RET_1041,
O => R1IN_ADD_2_1_AXB_37);
R1IN_ADD_2_1_AXB_38_Z5375: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_12,
I1 => R2_PIPE_104_RET_104,
I2 => R2_PIPE_104_RET_1040,
O => R1IN_ADD_2_1_AXB_38);
R1IN_ADD_2_1_AXB_39_Z5376: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_11,
I1 => R2_PIPE_104_RET_103,
I2 => R2_PIPE_104_RET_1039,
O => R1IN_ADD_2_1_AXB_39);
R1IN_ADD_2_1_AXB_40_Z5377: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_10,
I1 => R2_PIPE_104_RET_102,
I2 => R2_PIPE_104_RET_1038,
O => R1IN_ADD_2_1_AXB_40);
R1IN_ADD_2_1_AXB_41_Z5378: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_9,
I1 => R2_PIPE_104_RET_101,
I2 => R2_PIPE_104_RET_1037,
O => R1IN_ADD_2_1_AXB_41);
R1IN_ADD_2_1_AXB_42_Z5379: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_8,
I1 => R2_PIPE_104_RET_100,
I2 => R2_PIPE_104_RET_1036,
O => R1IN_ADD_2_1_AXB_42);
R1IN_ADD_2_1_AXB_43_Z5380: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_7,
I1 => R2_PIPE_104_RET_99,
I2 => R2_PIPE_104_RET_1035,
O => R1IN_ADD_2_1_AXB_43);
R1IN_ADD_2_1_AXB_44_Z5381: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_6,
I1 => R2_PIPE_104_RET_98,
I2 => R2_PIPE_104_RET_1034,
O => R1IN_ADD_2_1_AXB_44);
R1IN_ADD_2_1_AXB_45_Z5382: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_5,
I1 => R2_PIPE_104_RET_97,
I2 => R2_PIPE_104_RET_1033,
O => R1IN_ADD_2_1_AXB_45);
R1IN_ADD_2_1_AXB_46_Z5383: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_4,
I1 => R2_PIPE_104_RET_96,
I2 => R2_PIPE_104_RET_1032,
O => R1IN_ADD_2_1_AXB_46);
R1IN_ADD_2_1_AXB_47_Z5384: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_3,
I1 => R2_PIPE_104_RET_95,
I2 => R2_PIPE_104_RET_1031,
O => R1IN_ADD_2_1_AXB_47);
R1IN_ADD_2_1_AXB_48_Z5385: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_2,
I1 => R2_PIPE_104_RET_94,
I2 => R2_PIPE_104_RET_1030,
O => R1IN_ADD_2_1_AXB_48);
R1IN_ADD_2_1_AXB_49_Z5386: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_1,
I1 => R2_PIPE_104_RET_93,
I2 => R2_PIPE_104_RET_1029,
O => R1IN_ADD_2_1_AXB_49);
R1IN_ADD_2_1_AXB_50_Z5387: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_0,
I1 => R2_PIPE_104_RET_49,
I2 => R2_PIPE_104_RET_1028,
O => R1IN_ADD_2_1_AXB_50);
R1IN_ADD_2_1_0_AXB_1_Z5388: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(37),
I1 => R1IN_ADD_1_0_CRY_31_RETO_25,
I2 => R2_PIPE_159_RET,
I3 => R2_PIPE_159_RET_1,
O => R1IN_ADD_2_1_0_AXB_1);
R1IN_ADD_2_1_0_AXB_2_Z5389: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(38),
I1 => R1IN_ADD_1_0_CRY_31_RETO_24,
I2 => R2_PIPE_160_RET,
I3 => R2_PIPE_160_RET_1,
O => R1IN_ADD_2_1_0_AXB_2);
R1IN_ADD_2_1_0_AXB_3_Z5390: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(39),
I1 => R1IN_ADD_1_0_CRY_31_RETO_23,
I2 => R2_PIPE_161_RET,
I3 => R2_PIPE_161_RET_1,
O => R1IN_ADD_2_1_0_AXB_3);
R1IN_ADD_2_1_0_AXB_4_Z5391: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(40),
I1 => R1IN_ADD_1_0_CRY_31_RETO_22,
I2 => R2_PIPE_162_RET,
I3 => R2_PIPE_162_RET_1,
O => R1IN_ADD_2_1_0_AXB_4);
R1IN_ADD_2_1_0_AXB_5_Z5392: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(41),
I1 => R1IN_ADD_1_0_CRY_31_RETO_21,
I2 => R2_PIPE_163_RET,
I3 => R2_PIPE_163_RET_1,
O => R1IN_ADD_2_1_0_AXB_5);
R1IN_ADD_2_1_0_AXB_6_Z5393: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(42),
I1 => R1IN_ADD_1_0_CRY_31_RETO_20,
I2 => R2_PIPE_164_RET,
I3 => R2_PIPE_164_RET_1,
O => R1IN_ADD_2_1_0_AXB_6);
R1IN_ADD_2_1_0_AXB_7_Z5394: LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => R1IN_4F(43),
I1 => R1IN_ADD_1_0_CRY_31_RETO_19,
I2 => R2_PIPE_165_RET,
I3 => R2_PIPE_165_RET_1,
O => R1IN_ADD_2_1_0_AXB_7);
R1IN_ADD_2_1_0_AXB_8_Z5395: LUT4
generic map(
INIT => X"596A"
)
port map (
I0 => R1IN_4F(44),
I1 => R1IN_ADD_1_0_CRY_31_RETO_27,
I2 => R1IN_ADD_1_1_0_CRY_28_RETO,
I3 => R1IN_ADD_1_1_CRY_28_RETO,
O => R1IN_ADD_2_1_0_AXB_8);
R1IN_ADD_2_1_0_AXB_9_Z5396: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4F(45),
O => R1IN_ADD_2_1_0_AXB_9);
R1IN_ADD_2_1_0_AXB_10_Z5397: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4F(46),
O => R1IN_ADD_2_1_0_AXB_10);
R1IN_ADD_2_1_0_AXB_11_Z5398: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4F(47),
O => R1IN_ADD_2_1_0_AXB_11);
R1IN_ADD_2_1_0_AXB_12_Z5399: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4F(48),
O => R1IN_ADD_2_1_0_AXB_12);
R1IN_ADD_2_1_0_AXB_13_Z5400: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4F(49),
O => R1IN_ADD_2_1_0_AXB_13);
R1IN_ADD_2_1_0_AXB_14_Z5401: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4F(50),
O => R1IN_ADD_2_1_0_AXB_14);
R1IN_ADD_2_1_0_AXB_15_Z5402: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4F(51),
O => R1IN_ADD_2_1_0_AXB_15);
R1IN_ADD_2_1_0_AXB_16_Z5403: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4F(52),
O => R1IN_ADD_2_1_0_AXB_16);
R1IN_ADD_2_1_0_AXB_17_Z5404: LUT3
generic map(
INIT => X"72"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_32,
I1 => R1IN_4_ADD_2_1_0_AXB_0_RETO,
I2 => R1IN_4_ADD_2_1_AXB_0,
O => R1IN_ADD_2_1_0_AXB_17);
R1IN_ADD_2_1_0_AXB_18_Z5405: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4(54),
O => R1IN_ADD_2_1_0_AXB_18);
R1IN_ADD_2_1_0_AXB_19_Z5406: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_31,
I1 => R2_PIPE_104_RET_123,
I2 => R2_PIPE_104_RET_1059,
O => R1IN_ADD_2_1_0_AXB_19);
R1IN_ADD_2_1_0_AXB_20_Z5407: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_30,
I1 => R2_PIPE_104_RET_122,
I2 => R2_PIPE_104_RET_1058,
O => R1IN_ADD_2_1_0_AXB_20);
R1IN_ADD_2_1_0_AXB_21_Z5408: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_29,
I1 => R2_PIPE_104_RET_121,
I2 => R2_PIPE_104_RET_1057,
O => R1IN_ADD_2_1_0_AXB_21);
R1IN_ADD_2_1_0_AXB_22_Z5409: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_28,
I1 => R2_PIPE_104_RET_120,
I2 => R2_PIPE_104_RET_1056,
O => R1IN_ADD_2_1_0_AXB_22);
R1IN_ADD_2_1_0_AXB_23_Z5410: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_27,
I1 => R2_PIPE_104_RET_119,
I2 => R2_PIPE_104_RET_1055,
O => R1IN_ADD_2_1_0_AXB_23);
R1IN_ADD_2_1_0_AXB_24_Z5411: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_26,
I1 => R2_PIPE_104_RET_118,
I2 => R2_PIPE_104_RET_1054,
O => R1IN_ADD_2_1_0_AXB_24);
R1IN_ADD_2_1_0_AXB_25_Z5412: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_25,
I1 => R2_PIPE_104_RET_117,
I2 => R2_PIPE_104_RET_1053,
O => R1IN_ADD_2_1_0_AXB_25);
R1IN_ADD_2_1_0_AXB_26_Z5413: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_24,
I1 => R2_PIPE_104_RET_116,
I2 => R2_PIPE_104_RET_1052,
O => R1IN_ADD_2_1_0_AXB_26);
R1IN_ADD_2_1_0_AXB_27_Z5414: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_23,
I1 => R2_PIPE_104_RET_115,
I2 => R2_PIPE_104_RET_1051,
O => R1IN_ADD_2_1_0_AXB_27);
R1IN_ADD_2_1_0_AXB_28_Z5415: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_22,
I1 => R2_PIPE_104_RET_114,
I2 => R2_PIPE_104_RET_1050,
O => R1IN_ADD_2_1_0_AXB_28);
R1IN_ADD_2_1_0_AXB_29_Z5416: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_21,
I1 => R2_PIPE_104_RET_113,
I2 => R2_PIPE_104_RET_1049,
O => R1IN_ADD_2_1_0_AXB_29);
R1IN_ADD_2_1_0_AXB_30_Z5417: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_20,
I1 => R2_PIPE_104_RET_112,
I2 => R2_PIPE_104_RET_1048,
O => R1IN_ADD_2_1_0_AXB_30);
R1IN_ADD_2_1_0_AXB_31_Z5418: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_19,
I1 => R2_PIPE_104_RET_111,
I2 => R2_PIPE_104_RET_1047,
O => R1IN_ADD_2_1_0_AXB_31);
R1IN_ADD_2_1_0_AXB_32_Z5419: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_18,
I1 => R2_PIPE_104_RET_110,
I2 => R2_PIPE_104_RET_1046,
O => R1IN_ADD_2_1_0_AXB_32);
R1IN_ADD_2_1_0_AXB_33_Z5420: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_17,
I1 => R2_PIPE_104_RET_109,
I2 => R2_PIPE_104_RET_1045,
O => R1IN_ADD_2_1_0_AXB_33);
R1IN_ADD_2_1_0_AXB_34_Z5421: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_16,
I1 => R2_PIPE_104_RET_108,
I2 => R2_PIPE_104_RET_1044,
O => R1IN_ADD_2_1_0_AXB_34);
R1IN_ADD_2_1_0_AXB_35_Z5422: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_15,
I1 => R2_PIPE_104_RET_107,
I2 => R2_PIPE_104_RET_1043,
O => R1IN_ADD_2_1_0_AXB_35);
R1IN_ADD_2_1_0_AXB_36_Z5423: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_14,
I1 => R2_PIPE_104_RET_106,
I2 => R2_PIPE_104_RET_1042,
O => R1IN_ADD_2_1_0_AXB_36);
R1IN_ADD_2_1_0_AXB_37_Z5424: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_13,
I1 => R2_PIPE_104_RET_105,
I2 => R2_PIPE_104_RET_1041,
O => R1IN_ADD_2_1_0_AXB_37);
R1IN_ADD_2_1_0_AXB_38_Z5425: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_12,
I1 => R2_PIPE_104_RET_104,
I2 => R2_PIPE_104_RET_1040,
O => R1IN_ADD_2_1_0_AXB_38);
R1IN_ADD_2_1_0_AXB_39_Z5426: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_11,
I1 => R2_PIPE_104_RET_103,
I2 => R2_PIPE_104_RET_1039,
O => R1IN_ADD_2_1_0_AXB_39);
R1IN_ADD_2_1_0_AXB_40_Z5427: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_10,
I1 => R2_PIPE_104_RET_102,
I2 => R2_PIPE_104_RET_1038,
O => R1IN_ADD_2_1_0_AXB_40);
R1IN_ADD_2_1_0_AXB_41_Z5428: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_9,
I1 => R2_PIPE_104_RET_101,
I2 => R2_PIPE_104_RET_1037,
O => R1IN_ADD_2_1_0_AXB_41);
R1IN_ADD_2_1_0_AXB_42_Z5429: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_8,
I1 => R2_PIPE_104_RET_100,
I2 => R2_PIPE_104_RET_1036,
O => R1IN_ADD_2_1_0_AXB_42);
R1IN_ADD_2_1_0_AXB_43_Z5430: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_7,
I1 => R2_PIPE_104_RET_99,
I2 => R2_PIPE_104_RET_1035,
O => R1IN_ADD_2_1_0_AXB_43);
R1IN_ADD_2_1_0_AXB_44_Z5431: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_6,
I1 => R2_PIPE_104_RET_98,
I2 => R2_PIPE_104_RET_1034,
O => R1IN_ADD_2_1_0_AXB_44);
R1IN_ADD_2_1_0_AXB_45_Z5432: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_5,
I1 => R2_PIPE_104_RET_97,
I2 => R2_PIPE_104_RET_1033,
O => R1IN_ADD_2_1_0_AXB_45);
R1IN_ADD_2_1_0_AXB_46_Z5433: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_4,
I1 => R2_PIPE_104_RET_96,
I2 => R2_PIPE_104_RET_1032,
O => R1IN_ADD_2_1_0_AXB_46);
R1IN_ADD_2_1_0_AXB_47_Z5434: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_3,
I1 => R2_PIPE_104_RET_95,
I2 => R2_PIPE_104_RET_1031,
O => R1IN_ADD_2_1_0_AXB_47);
R1IN_ADD_2_1_0_AXB_48_Z5435: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_2,
I1 => R2_PIPE_104_RET_94,
I2 => R2_PIPE_104_RET_1030,
O => R1IN_ADD_2_1_0_AXB_48);
R1IN_ADD_2_1_0_AXB_49_Z5436: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_1,
I1 => R2_PIPE_104_RET_93,
I2 => R2_PIPE_104_RET_1029,
O => R1IN_ADD_2_1_0_AXB_49);
R1IN_ADD_2_1_0_AXB_50_Z5437: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO_0,
I1 => R2_PIPE_104_RET_49,
I2 => R2_PIPE_104_RET_1028,
O => R1IN_ADD_2_1_0_AXB_50);
R1IN_3_ADD_1_AXB_1_Z5438: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F(18),
I1 => R1IN_3_2F(1),
O => R1IN_3_ADD_1_AXB_1);
R1IN_3_ADD_1_AXB_2_Z5439: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F(19),
I1 => R1IN_3_2F(2),
O => R1IN_3_ADD_1_AXB_2);
R1IN_3_ADD_1_AXB_3_Z5440: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F(20),
I1 => R1IN_3_2F(3),
O => R1IN_3_ADD_1_AXB_3);
R1IN_3_ADD_1_AXB_4_Z5441: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F(21),
I1 => R1IN_3_2F(4),
O => R1IN_3_ADD_1_AXB_4);
R1IN_3_ADD_1_AXB_5_Z5442: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F(22),
I1 => R1IN_3_2F(5),
O => R1IN_3_ADD_1_AXB_5);
R1IN_3_ADD_1_AXB_6_Z5443: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F(23),
I1 => R1IN_3_2F(6),
O => R1IN_3_ADD_1_AXB_6);
R1IN_3_ADD_1_AXB_7_Z5444: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F(24),
I1 => R1IN_3_2F(7),
O => R1IN_3_ADD_1_AXB_7);
R1IN_3_ADD_1_AXB_8_Z5445: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F(25),
I1 => R1IN_3_2F(8),
O => R1IN_3_ADD_1_AXB_8);
R1IN_3_ADD_1_AXB_9_Z5446: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F(26),
I1 => R1IN_3_2F(9),
O => R1IN_3_ADD_1_AXB_9);
R1IN_3_ADD_1_AXB_10_Z5447: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F(27),
I1 => R1IN_3_2F(10),
O => R1IN_3_ADD_1_AXB_10);
R1IN_3_ADD_1_AXB_11_Z5448: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F(28),
I1 => R1IN_3_2F(11),
O => R1IN_3_ADD_1_AXB_11);
R1IN_3_ADD_1_AXB_12_Z5449: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F(29),
I1 => R1IN_3_2F(12),
O => R1IN_3_ADD_1_AXB_12);
R1IN_3_ADD_1_AXB_13_Z5450: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F(30),
I1 => R1IN_3_2F(13),
O => R1IN_3_ADD_1_AXB_13);
R1IN_3_ADD_1_AXB_14_Z5451: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F(31),
I1 => R1IN_3_2F(14),
O => R1IN_3_ADD_1_AXB_14);
R1IN_3_ADD_1_AXB_15_Z5452: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F(32),
I1 => R1IN_3_2F(15),
O => R1IN_3_ADD_1_AXB_15);
R1IN_3_ADD_1_AXB_16_Z5453: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F(33),
I1 => R1IN_3_2F(16),
O => R1IN_3_ADD_1_AXB_16);
R1IN_3_ADD_1_AXB_17_Z5454: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(17),
O => R1IN_3_ADD_1_AXB_17);
R1IN_3_ADD_1_AXB_18_Z5455: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(18),
O => R1IN_3_ADD_1_AXB_18);
R1IN_3_ADD_1_AXB_19_Z5456: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(19),
O => R1IN_3_ADD_1_AXB_19);
R1IN_3_ADD_1_AXB_20_Z5457: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(20),
O => R1IN_3_ADD_1_AXB_20);
R1IN_3_ADD_1_AXB_21_Z5458: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(21),
O => R1IN_3_ADD_1_AXB_21);
R1IN_3_ADD_1_AXB_22_Z5459: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(22),
O => R1IN_3_ADD_1_AXB_22);
R1IN_3_ADD_1_AXB_23_Z5460: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(23),
O => R1IN_3_ADD_1_AXB_23);
R1IN_3_ADD_1_AXB_24_Z5461: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(24),
O => R1IN_3_ADD_1_AXB_24);
R1IN_3_ADD_1_AXB_25_Z5462: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(25),
O => R1IN_3_ADD_1_AXB_25);
R1IN_3_ADD_1_AXB_26_Z5463: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(26),
O => R1IN_3_ADD_1_AXB_26);
R1IN_3_ADD_1_AXB_27_Z5464: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(27),
O => R1IN_3_ADD_1_AXB_27);
R1IN_3_ADD_1_AXB_28_Z5465: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(28),
O => R1IN_3_ADD_1_AXB_28);
R1IN_3_ADD_1_AXB_29_Z5466: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(29),
O => R1IN_3_ADD_1_AXB_29);
R1IN_3_ADD_1_AXB_30_Z5467: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(30),
O => R1IN_3_ADD_1_AXB_30);
R1IN_3_ADD_1_AXB_31_Z5468: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(31),
O => R1IN_3_ADD_1_AXB_31);
R1IN_3_ADD_1_AXB_32_Z5469: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(32),
O => R1IN_3_ADD_1_AXB_32);
R1IN_3_ADD_1_AXB_33_Z5470: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(33),
O => R1IN_3_ADD_1_AXB_33);
R1IN_3_ADD_1_AXB_34_Z5471: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(34),
O => R1IN_3_ADD_1_AXB_34);
R1IN_3_ADD_1_AXB_35_Z5472: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(35),
O => R1IN_3_ADD_1_AXB_35);
R1IN_3_ADD_1_AXB_36_Z5473: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(36),
O => R1IN_3_ADD_1_AXB_36);
R1IN_3_ADD_1_AXB_37_Z5474: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(37),
O => R1IN_3_ADD_1_AXB_37);
R1IN_3_ADD_1_AXB_38_Z5475: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(38),
O => R1IN_3_ADD_1_AXB_38);
R1IN_3_ADD_1_AXB_39_Z5476: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(39),
O => R1IN_3_ADD_1_AXB_39);
R1IN_3_ADD_1_AXB_40_Z5477: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(40),
O => R1IN_3_ADD_1_AXB_40);
R1IN_3_ADD_1_AXB_41_Z5478: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(41),
O => R1IN_3_ADD_1_AXB_41);
R1IN_3_ADD_1_AXB_42_Z5479: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(42),
O => R1IN_3_ADD_1_AXB_42);
R1IN_2_ADD_1_AXB_0: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F(17),
I1 => R1IN_2_ADD_1,
O => R1IN_2(17));
R1IN_2_ADD_1_AXB_1_Z5481: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F(18),
I1 => R1IN_2_2F(1),
O => R1IN_2_ADD_1_AXB_1);
R1IN_2_ADD_1_AXB_2_Z5482: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F(19),
I1 => R1IN_2_2F(2),
O => R1IN_2_ADD_1_AXB_2);
R1IN_2_ADD_1_AXB_3_Z5483: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F(20),
I1 => R1IN_2_2F(3),
O => R1IN_2_ADD_1_AXB_3);
R1IN_2_ADD_1_AXB_4_Z5484: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F(21),
I1 => R1IN_2_2F(4),
O => R1IN_2_ADD_1_AXB_4);
R1IN_2_ADD_1_AXB_5_Z5485: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F(22),
I1 => R1IN_2_2F(5),
O => R1IN_2_ADD_1_AXB_5);
R1IN_2_ADD_1_AXB_6_Z5486: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F(23),
I1 => R1IN_2_2F(6),
O => R1IN_2_ADD_1_AXB_6);
R1IN_2_ADD_1_AXB_7_Z5487: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F(24),
I1 => R1IN_2_2F(7),
O => R1IN_2_ADD_1_AXB_7);
R1IN_2_ADD_1_AXB_8_Z5488: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F(25),
I1 => R1IN_2_2F(8),
O => R1IN_2_ADD_1_AXB_8);
R1IN_2_ADD_1_AXB_9_Z5489: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F(26),
I1 => R1IN_2_2F(9),
O => R1IN_2_ADD_1_AXB_9);
R1IN_2_ADD_1_AXB_10_Z5490: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F(27),
I1 => R1IN_2_2F(10),
O => R1IN_2_ADD_1_AXB_10);
R1IN_2_ADD_1_AXB_11_Z5491: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F(28),
I1 => R1IN_2_2F(11),
O => R1IN_2_ADD_1_AXB_11);
R1IN_2_ADD_1_AXB_12_Z5492: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F(29),
I1 => R1IN_2_2F(12),
O => R1IN_2_ADD_1_AXB_12);
R1IN_2_ADD_1_AXB_13_Z5493: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F(30),
I1 => R1IN_2_2F(13),
O => R1IN_2_ADD_1_AXB_13);
R1IN_2_ADD_1_AXB_14_Z5494: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F(31),
I1 => R1IN_2_2F(14),
O => R1IN_2_ADD_1_AXB_14);
R1IN_2_ADD_1_AXB_15_Z5495: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F(32),
I1 => R1IN_2_2F(15),
O => R1IN_2_ADD_1_AXB_15);
R1IN_2_ADD_1_AXB_16_Z5496: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2_1F(33),
I1 => R1IN_2_2F(16),
O => R1IN_2_ADD_1_AXB_16);
R1IN_2_ADD_1_AXB_17_Z5497: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(17),
O => R1IN_2_ADD_1_AXB_17);
R1IN_2_ADD_1_AXB_18_Z5498: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(18),
O => R1IN_2_ADD_1_AXB_18);
R1IN_2_ADD_1_AXB_19_Z5499: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(19),
O => R1IN_2_ADD_1_AXB_19);
R1IN_2_ADD_1_AXB_20_Z5500: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(20),
O => R1IN_2_ADD_1_AXB_20);
R1IN_2_ADD_1_AXB_21_Z5501: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(21),
O => R1IN_2_ADD_1_AXB_21);
R1IN_2_ADD_1_AXB_22_Z5502: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(22),
O => R1IN_2_ADD_1_AXB_22);
R1IN_2_ADD_1_AXB_23_Z5503: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(23),
O => R1IN_2_ADD_1_AXB_23);
R1IN_2_ADD_1_AXB_24_Z5504: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(24),
O => R1IN_2_ADD_1_AXB_24);
R1IN_2_ADD_1_AXB_25_Z5505: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(25),
O => R1IN_2_ADD_1_AXB_25);
R1IN_2_ADD_1_AXB_26_Z5506: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(26),
O => R1IN_2_ADD_1_AXB_26);
R1IN_2_ADD_1_AXB_27_Z5507: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(27),
O => R1IN_2_ADD_1_AXB_27);
R1IN_2_ADD_1_AXB_28_Z5508: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(28),
O => R1IN_2_ADD_1_AXB_28);
R1IN_2_ADD_1_AXB_29_Z5509: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(29),
O => R1IN_2_ADD_1_AXB_29);
R1IN_2_ADD_1_AXB_30_Z5510: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(30),
O => R1IN_2_ADD_1_AXB_30);
R1IN_2_ADD_1_AXB_31_Z5511: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(31),
O => R1IN_2_ADD_1_AXB_31);
R1IN_2_ADD_1_AXB_32_Z5512: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(32),
O => R1IN_2_ADD_1_AXB_32);
R1IN_2_ADD_1_AXB_33_Z5513: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(33),
O => R1IN_2_ADD_1_AXB_33);
R1IN_2_ADD_1_AXB_34_Z5514: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(34),
O => R1IN_2_ADD_1_AXB_34);
R1IN_2_ADD_1_AXB_35_Z5515: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(35),
O => R1IN_2_ADD_1_AXB_35);
R1IN_2_ADD_1_AXB_36_Z5516: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(36),
O => R1IN_2_ADD_1_AXB_36);
R1IN_2_ADD_1_AXB_37_Z5517: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(37),
O => R1IN_2_ADD_1_AXB_37);
R1IN_2_ADD_1_AXB_38_Z5518: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(38),
O => R1IN_2_ADD_1_AXB_38);
R1IN_2_ADD_1_AXB_39_Z5519: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(39),
O => R1IN_2_ADD_1_AXB_39);
R1IN_2_ADD_1_AXB_40_Z5520: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(40),
O => R1IN_2_ADD_1_AXB_40);
R1IN_2_ADD_1_AXB_41_Z5521: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(41),
O => R1IN_2_ADD_1_AXB_41);
R1IN_2_ADD_1_AXB_42_Z5522: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(42),
O => R1IN_2_ADD_1_AXB_42);
R1IN_4_4_ADD_2_AXB_1_Z5523: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F(18),
I1 => R1IN_4_4_ADD_1F(1),
O => R1IN_4_4_ADD_2_AXB_1);
R1IN_4_4_ADD_2_AXB_2_Z5524: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F(19),
I1 => R1IN_4_4_ADD_1F(2),
O => R1IN_4_4_ADD_2_AXB_2);
R1IN_4_4_ADD_2_AXB_3_Z5525: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F(20),
I1 => R1IN_4_4_ADD_1F(3),
O => R1IN_4_4_ADD_2_AXB_3);
R1IN_4_4_ADD_2_AXB_4_Z5526: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F(21),
I1 => R1IN_4_4_ADD_1F(4),
O => R1IN_4_4_ADD_2_AXB_4);
R1IN_4_4_ADD_2_AXB_5_Z5527: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F(22),
I1 => R1IN_4_4_ADD_1F(5),
O => R1IN_4_4_ADD_2_AXB_5);
R1IN_4_4_ADD_2_AXB_6_Z5528: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F(23),
I1 => R1IN_4_4_ADD_1F(6),
O => R1IN_4_4_ADD_2_AXB_6);
R1IN_4_4_ADD_2_AXB_7_Z5529: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F(24),
I1 => R1IN_4_4_ADD_1F(7),
O => R1IN_4_4_ADD_2_AXB_7);
R1IN_4_4_ADD_2_AXB_8_Z5530: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F(25),
I1 => R1IN_4_4_ADD_1F(8),
O => R1IN_4_4_ADD_2_AXB_8);
R1IN_4_4_ADD_2_AXB_9_Z5531: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F(26),
I1 => R1IN_4_4_ADD_1F(9),
O => R1IN_4_4_ADD_2_AXB_9);
R1IN_4_4_ADD_2_AXB_10_Z5532: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F(27),
I1 => R1IN_4_4_ADD_1F(10),
O => R1IN_4_4_ADD_2_AXB_10);
R1IN_4_4_ADD_2_AXB_11_Z5533: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F(28),
I1 => R1IN_4_4_ADD_1F(11),
O => R1IN_4_4_ADD_2_AXB_11);
R1IN_4_4_ADD_2_AXB_12_Z5534: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F(29),
I1 => R1IN_4_4_ADD_1F(12),
O => R1IN_4_4_ADD_2_AXB_12);
R1IN_4_4_ADD_2_AXB_13_Z5535: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F(30),
I1 => R1IN_4_4_ADD_1F(13),
O => R1IN_4_4_ADD_2_AXB_13);
R1IN_4_4_ADD_2_AXB_14_Z5536: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F(31),
I1 => R1IN_4_4_ADD_1F(14),
O => R1IN_4_4_ADD_2_AXB_14);
R1IN_4_4_ADD_2_AXB_15_Z5537: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F(32),
I1 => R1IN_4_4_ADD_1F(15),
O => R1IN_4_4_ADD_2_AXB_15);
R1IN_4_4_ADD_2_AXB_16_Z5538: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_1F(33),
I1 => R1IN_4_4_ADD_1F(16),
O => R1IN_4_4_ADD_2_AXB_16);
R1IN_4_4_ADD_2_AXB_17_Z5539: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F(0),
I1 => R1IN_4_4_ADD_1F(17),
O => R1IN_4_4_ADD_2_AXB_17);
R1IN_4_4_ADD_2_AXB_18_Z5540: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F(1),
I1 => R1IN_4_4_ADD_1F(18),
O => R1IN_4_4_ADD_2_AXB_18);
R1IN_4_4_ADD_2_AXB_19_Z5541: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F(2),
I1 => R1IN_4_4_ADD_1F(19),
O => R1IN_4_4_ADD_2_AXB_19);
R1IN_4_4_ADD_2_AXB_20_Z5542: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F(3),
I1 => R1IN_4_4_ADD_1F(20),
O => R1IN_4_4_ADD_2_AXB_20);
R1IN_4_4_ADD_2_AXB_21_Z5543: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F(4),
I1 => R1IN_4_4_ADD_1F(21),
O => R1IN_4_4_ADD_2_AXB_21);
R1IN_4_4_ADD_2_AXB_22_Z5544: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F(5),
I1 => R1IN_4_4_ADD_1F(22),
O => R1IN_4_4_ADD_2_AXB_22);
R1IN_4_4_ADD_2_AXB_23_Z5545: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F(6),
I1 => R1IN_4_4_ADD_1F(23),
O => R1IN_4_4_ADD_2_AXB_23);
R1IN_4_4_ADD_2_AXB_24_Z5546: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F(7),
I1 => R1IN_4_4_ADD_1F(24),
O => R1IN_4_4_ADD_2_AXB_24);
R1IN_4_4_ADD_2_AXB_25_Z5547: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F(8),
I1 => R1IN_4_4_ADD_1F(25),
O => R1IN_4_4_ADD_2_AXB_25);
R1IN_4_4_ADD_2_AXB_26_Z5548: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F(9),
I1 => R1IN_4_4_ADD_1F(26),
O => R1IN_4_4_ADD_2_AXB_26);
R1IN_4_4_ADD_2_AXB_27_Z5549: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_4F(10),
I1 => R1IN_4_4_ADD_1F(27),
O => R1IN_4_4_ADD_2_AXB_27);
R1IN_4_4_ADD_2_AXB_28_Z5550: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4_4F(11),
O => R1IN_4_4_ADD_2_AXB_28);
R1IN_4_4_ADD_2_AXB_29_Z5551: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4_4F(12),
O => R1IN_4_4_ADD_2_AXB_29);
R1IN_4_4_ADD_2_AXB_30_Z5552: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4_4F(13),
O => R1IN_4_4_ADD_2_AXB_30);
R1IN_4_4_ADD_2_AXB_31_Z5553: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4_4F(14),
O => R1IN_4_4_ADD_2_AXB_31);
R1IN_4_4_ADD_2_AXB_32_Z5554: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4_4F(15),
O => R1IN_4_4_ADD_2_AXB_32);
R1IN_4_4_ADD_2_AXB_33_Z5555: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4_4F(16),
O => R1IN_4_4_ADD_2_AXB_33);
R1IN_4_4_ADD_2_AXB_34_Z5556: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4_4F(17),
O => R1IN_4_4_ADD_2_AXB_34);
R1IN_4_4_ADD_2_AXB_35_Z5557: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4_4F(18),
O => R1IN_4_4_ADD_2_AXB_35);
R1IN_4_ADD_1_AXB_1_Z5558: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(1),
I1 => R1IN_4_3F(1),
O => R1IN_4_ADD_1_AXB_1);
R1IN_4_ADD_1_AXB_2_Z5559: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(2),
I1 => R1IN_4_3F(2),
O => R1IN_4_ADD_1_AXB_2);
R1IN_4_ADD_1_AXB_3_Z5560: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(3),
I1 => R1IN_4_3F(3),
O => R1IN_4_ADD_1_AXB_3);
R1IN_4_ADD_1_AXB_4_Z5561: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(4),
I1 => R1IN_4_3F(4),
O => R1IN_4_ADD_1_AXB_4);
R1IN_4_ADD_1_AXB_5_Z5562: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(5),
I1 => R1IN_4_3F(5),
O => R1IN_4_ADD_1_AXB_5);
R1IN_4_ADD_1_AXB_6_Z5563: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(6),
I1 => R1IN_4_3F(6),
O => R1IN_4_ADD_1_AXB_6);
R1IN_4_ADD_1_AXB_7_Z5564: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(7),
I1 => R1IN_4_3F(7),
O => R1IN_4_ADD_1_AXB_7);
R1IN_4_ADD_1_AXB_8_Z5565: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(8),
I1 => R1IN_4_3F(8),
O => R1IN_4_ADD_1_AXB_8);
R1IN_4_ADD_1_AXB_9_Z5566: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(9),
I1 => R1IN_4_3F(9),
O => R1IN_4_ADD_1_AXB_9);
R1IN_4_ADD_1_AXB_10_Z5567: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(10),
I1 => R1IN_4_3F(10),
O => R1IN_4_ADD_1_AXB_10);
R1IN_4_ADD_1_AXB_11_Z5568: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(11),
I1 => R1IN_4_3F(11),
O => R1IN_4_ADD_1_AXB_11);
R1IN_4_ADD_1_AXB_12_Z5569: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(12),
I1 => R1IN_4_3F(12),
O => R1IN_4_ADD_1_AXB_12);
R1IN_4_ADD_1_AXB_13_Z5570: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(13),
I1 => R1IN_4_3F(13),
O => R1IN_4_ADD_1_AXB_13);
R1IN_4_ADD_1_AXB_14_Z5571: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(14),
I1 => R1IN_4_3F(14),
O => R1IN_4_ADD_1_AXB_14);
R1IN_4_ADD_1_AXB_15_Z5572: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(15),
I1 => R1IN_4_3F(15),
O => R1IN_4_ADD_1_AXB_15);
R1IN_4_ADD_1_AXB_16_Z5573: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(16),
I1 => R1IN_4_3F(16),
O => R1IN_4_ADD_1_AXB_16);
R1IN_4_ADD_1_AXB_17_Z5574: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(17),
I1 => R1IN_4_3F(17),
O => R1IN_4_ADD_1_AXB_17);
R1IN_4_ADD_1_AXB_18_Z5575: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(18),
I1 => R1IN_4_3F(18),
O => R1IN_4_ADD_1_AXB_18);
R1IN_4_ADD_1_AXB_19_Z5576: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(19),
I1 => R1IN_4_3F(19),
O => R1IN_4_ADD_1_AXB_19);
R1IN_4_ADD_1_AXB_20_Z5577: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(20),
I1 => R1IN_4_3F(20),
O => R1IN_4_ADD_1_AXB_20);
R1IN_4_ADD_1_AXB_21_Z5578: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(21),
I1 => R1IN_4_3F(21),
O => R1IN_4_ADD_1_AXB_21);
R1IN_4_ADD_1_AXB_22_Z5579: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(22),
I1 => R1IN_4_3F(22),
O => R1IN_4_ADD_1_AXB_22);
R1IN_4_ADD_1_AXB_23_Z5580: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(23),
I1 => R1IN_4_3F(23),
O => R1IN_4_ADD_1_AXB_23);
R1IN_4_ADD_1_AXB_24_Z5581: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(24),
I1 => R1IN_4_3F(24),
O => R1IN_4_ADD_1_AXB_24);
R1IN_4_ADD_1_AXB_25_Z5582: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(25),
I1 => R1IN_4_3F(25),
O => R1IN_4_ADD_1_AXB_25);
R1IN_4_ADD_1_AXB_26_Z5583: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(26),
I1 => R1IN_4_3F(26),
O => R1IN_4_ADD_1_AXB_26);
R1IN_4_ADD_1_AXB_27_Z5584: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(27),
I1 => R1IN_4_3F(27),
O => R1IN_4_ADD_1_AXB_27);
R1IN_4_ADD_1_AXB_28_Z5585: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(28),
I1 => R1IN_4_3F(28),
O => R1IN_4_ADD_1_AXB_28);
R1IN_4_ADD_1_AXB_29_Z5586: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(29),
I1 => R1IN_4_3F(29),
O => R1IN_4_ADD_1_AXB_29);
R1IN_4_ADD_1_AXB_30_Z5587: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(30),
I1 => R1IN_4_3F(30),
O => R1IN_4_ADD_1_AXB_30);
R1IN_4_ADD_1_AXB_31_Z5588: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(31),
I1 => R1IN_4_3F(31),
O => R1IN_4_ADD_1_AXB_31);
R1IN_4_ADD_1_AXB_32_Z5589: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(32),
I1 => R1IN_4_3F(32),
O => R1IN_4_ADD_1_AXB_32);
R1IN_4_ADD_1_AXB_33_Z5590: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(33),
I1 => R1IN_4_3F(33),
O => R1IN_4_ADD_1_AXB_33);
R1IN_4_ADD_1_AXB_34_Z5591: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(34),
I1 => R1IN_4_3F(34),
O => R1IN_4_ADD_1_AXB_34);
R1IN_4_ADD_1_AXB_35_Z5592: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(35),
I1 => R1IN_4_3F(35),
O => R1IN_4_ADD_1_AXB_35);
R1IN_4_ADD_1_AXB_36_Z5593: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(36),
I1 => R1IN_4_3F(36),
O => R1IN_4_ADD_1_AXB_36);
R1IN_4_ADD_1_AXB_37_Z5594: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(37),
I1 => R1IN_4_3F(37),
O => R1IN_4_ADD_1_AXB_37);
R1IN_4_ADD_1_AXB_38_Z5595: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(38),
I1 => R1IN_4_3F(38),
O => R1IN_4_ADD_1_AXB_38);
R1IN_4_ADD_1_AXB_39_Z5596: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(39),
I1 => R1IN_4_3F(39),
O => R1IN_4_ADD_1_AXB_39);
R1IN_4_ADD_1_AXB_40_Z5597: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(40),
I1 => R1IN_4_3F(40),
O => R1IN_4_ADD_1_AXB_40);
R1IN_4_ADD_1_AXB_41_Z5598: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(41),
I1 => R1IN_4_3F(41),
O => R1IN_4_ADD_1_AXB_41);
R1IN_4_ADD_1_AXB_42_Z5599: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(42),
I1 => R1IN_4_3F(42),
O => R1IN_4_ADD_1_AXB_42);
R1IN_4_ADD_1_AXB_43_Z5600: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_2F(43),
I1 => R1IN_4_3F(43),
O => R1IN_4_ADD_1_AXB_43);
R1_PIPE_34: FDE port map (
Q => NN_12,
D => R1IN_4_2(0),
C => CLK,
CE => EN);
R1_PIPE_283: FDE port map (
Q => R1IN_4_2F(1),
D => R1IN_4_2(1),
C => CLK,
CE => EN);
R1_PIPE_284: FDE port map (
Q => R1IN_4_2F(2),
D => R1IN_4_2(2),
C => CLK,
CE => EN);
R1_PIPE_285: FDE port map (
Q => R1IN_4_2F(3),
D => R1IN_4_2(3),
C => CLK,
CE => EN);
R1_PIPE_286: FDE port map (
Q => R1IN_4_2F(4),
D => R1IN_4_2(4),
C => CLK,
CE => EN);
R1_PIPE_287: FDE port map (
Q => R1IN_4_2F(5),
D => R1IN_4_2(5),
C => CLK,
CE => EN);
R1_PIPE_288: FDE port map (
Q => R1IN_4_2F(6),
D => R1IN_4_2(6),
C => CLK,
CE => EN);
R1_PIPE_289: FDE port map (
Q => R1IN_4_2F(7),
D => R1IN_4_2(7),
C => CLK,
CE => EN);
R1_PIPE_290: FDE port map (
Q => R1IN_4_2F(8),
D => R1IN_4_2(8),
C => CLK,
CE => EN);
R1_PIPE_291: FDE port map (
Q => R1IN_4_2F(9),
D => R1IN_4_2(9),
C => CLK,
CE => EN);
R1_PIPE_292: FDE port map (
Q => R1IN_4_2F(10),
D => R1IN_4_2(10),
C => CLK,
CE => EN);
R1_PIPE_293: FDE port map (
Q => R1IN_4_2F(11),
D => R1IN_4_2(11),
C => CLK,
CE => EN);
R1_PIPE_294: FDE port map (
Q => R1IN_4_2F(12),
D => R1IN_4_2(12),
C => CLK,
CE => EN);
R1_PIPE_295: FDE port map (
Q => R1IN_4_2F(13),
D => R1IN_4_2(13),
C => CLK,
CE => EN);
R1_PIPE_296: FDE port map (
Q => R1IN_4_2F(14),
D => R1IN_4_2(14),
C => CLK,
CE => EN);
R1_PIPE_297: FDE port map (
Q => R1IN_4_2F(15),
D => R1IN_4_2(15),
C => CLK,
CE => EN);
R1_PIPE_298: FDE port map (
Q => R1IN_4_2F(16),
D => R1IN_4_2(16),
C => CLK,
CE => EN);
R1_PIPE_326: FDE port map (
Q => R1IN_4_3F(0),
D => R1IN_4_3(0),
C => CLK,
CE => EN);
R1_PIPE_327: FDE port map (
Q => R1IN_4_3F(1),
D => R1IN_4_3(1),
C => CLK,
CE => EN);
R1_PIPE_328: FDE port map (
Q => R1IN_4_3F(2),
D => R1IN_4_3(2),
C => CLK,
CE => EN);
R1_PIPE_329: FDE port map (
Q => R1IN_4_3F(3),
D => R1IN_4_3(3),
C => CLK,
CE => EN);
R1_PIPE_330: FDE port map (
Q => R1IN_4_3F(4),
D => R1IN_4_3(4),
C => CLK,
CE => EN);
R1_PIPE_331: FDE port map (
Q => R1IN_4_3F(5),
D => R1IN_4_3(5),
C => CLK,
CE => EN);
R1_PIPE_332: FDE port map (
Q => R1IN_4_3F(6),
D => R1IN_4_3(6),
C => CLK,
CE => EN);
R1_PIPE_333: FDE port map (
Q => R1IN_4_3F(7),
D => R1IN_4_3(7),
C => CLK,
CE => EN);
R1_PIPE_334: FDE port map (
Q => R1IN_4_3F(8),
D => R1IN_4_3(8),
C => CLK,
CE => EN);
R1_PIPE_335: FDE port map (
Q => R1IN_4_3F(9),
D => R1IN_4_3(9),
C => CLK,
CE => EN);
R1_PIPE_336: FDE port map (
Q => R1IN_4_3F(10),
D => R1IN_4_3(10),
C => CLK,
CE => EN);
R1_PIPE_337: FDE port map (
Q => R1IN_4_3F(11),
D => R1IN_4_3(11),
C => CLK,
CE => EN);
R1_PIPE_338: FDE port map (
Q => R1IN_4_3F(12),
D => R1IN_4_3(12),
C => CLK,
CE => EN);
R1_PIPE_339: FDE port map (
Q => R1IN_4_3F(13),
D => R1IN_4_3(13),
C => CLK,
CE => EN);
R1_PIPE_340: FDE port map (
Q => R1IN_4_3F(14),
D => R1IN_4_3(14),
C => CLK,
CE => EN);
R1_PIPE_341: FDE port map (
Q => R1IN_4_3F(15),
D => R1IN_4_3(15),
C => CLK,
CE => EN);
R1_PIPE_342: FDE port map (
Q => R1IN_4_3F(16),
D => R1IN_4_3(16),
C => CLK,
CE => EN);
R2_PIPE_17: FDE port map (
Q => R1IN_4FF(0),
D => R1IN_4F(0),
C => CLK,
CE => EN);
R2_PIPE_18: FDE port map (
Q => R1IN_4FF(1),
D => R1IN_4F(1),
C => CLK,
CE => EN);
R2_PIPE_19: FDE port map (
Q => R1IN_4FF(2),
D => R1IN_4F(2),
C => CLK,
CE => EN);
R2_PIPE_20: FDE port map (
Q => R1IN_4FF(3),
D => R1IN_4F(3),
C => CLK,
CE => EN);
R2_PIPE_21: FDE port map (
Q => R1IN_4FF(4),
D => R1IN_4F(4),
C => CLK,
CE => EN);
R2_PIPE_22: FDE port map (
Q => R1IN_4FF(5),
D => R1IN_4F(5),
C => CLK,
CE => EN);
R2_PIPE_23: FDE port map (
Q => R1IN_4FF(6),
D => R1IN_4F(6),
C => CLK,
CE => EN);
R2_PIPE_24: FDE port map (
Q => R1IN_4FF(7),
D => R1IN_4F(7),
C => CLK,
CE => EN);
R2_PIPE_25: FDE port map (
Q => R1IN_4FF(8),
D => R1IN_4F(8),
C => CLK,
CE => EN);
R2_PIPE_26: FDE port map (
Q => R1IN_4FF(9),
D => R1IN_4F(9),
C => CLK,
CE => EN);
R2_PIPE_27: FDE port map (
Q => R1IN_4FF(10),
D => R1IN_4F(10),
C => CLK,
CE => EN);
R2_PIPE_28: FDE port map (
Q => R1IN_4FF(11),
D => R1IN_4F(11),
C => CLK,
CE => EN);
R2_PIPE_29: FDE port map (
Q => R1IN_4FF(12),
D => R1IN_4F(12),
C => CLK,
CE => EN);
R2_PIPE_30: FDE port map (
Q => R1IN_4FF(13),
D => R1IN_4F(13),
C => CLK,
CE => EN);
R2_PIPE_31: FDE port map (
Q => R1IN_4FF(14),
D => R1IN_4F(14),
C => CLK,
CE => EN);
R2_PIPE_32: FDE port map (
Q => R1IN_4FF(15),
D => R1IN_4F(15),
C => CLK,
CE => EN);
R2_PIPE_33: FDE port map (
Q => R1IN_4FF(16),
D => R1IN_4F(16),
C => CLK,
CE => EN);
R2_PIPE_34: FDE port map (
Q => R1IN_4F(17),
D => R1IN_4(17),
C => CLK,
CE => EN);
R2_PIPE_35: FDE port map (
Q => R1IN_4F(18),
D => R1IN_4(18),
C => CLK,
CE => EN);
R2_PIPE_36: FDE port map (
Q => R1IN_4F(19),
D => R1IN_4(19),
C => CLK,
CE => EN);
R2_PIPE_37: FDE port map (
Q => R1IN_4F(20),
D => R1IN_4(20),
C => CLK,
CE => EN);
R2_PIPE_38: FDE port map (
Q => R1IN_4F(21),
D => R1IN_4(21),
C => CLK,
CE => EN);
R2_PIPE_39: FDE port map (
Q => R1IN_4F(22),
D => R1IN_4(22),
C => CLK,
CE => EN);
R2_PIPE_40: FDE port map (
Q => R1IN_4F(23),
D => R1IN_4(23),
C => CLK,
CE => EN);
R2_PIPE_41: FDE port map (
Q => R1IN_4F(24),
D => R1IN_4(24),
C => CLK,
CE => EN);
R2_PIPE_42: FDE port map (
Q => R1IN_4F(25),
D => R1IN_4(25),
C => CLK,
CE => EN);
R2_PIPE_43: FDE port map (
Q => R1IN_4F(26),
D => R1IN_4(26),
C => CLK,
CE => EN);
R2_PIPE_44: FDE port map (
Q => R1IN_4F(27),
D => R1IN_4(27),
C => CLK,
CE => EN);
R2_PIPE_45: FDE port map (
Q => R1IN_4F(28),
D => R1IN_4(28),
C => CLK,
CE => EN);
R2_PIPE_46: FDE port map (
Q => R1IN_4F(29),
D => R1IN_4(29),
C => CLK,
CE => EN);
R2_PIPE_47: FDE port map (
Q => R1IN_4F(30),
D => R1IN_4(30),
C => CLK,
CE => EN);
R2_PIPE_48: FDE port map (
Q => R1IN_4F(31),
D => R1IN_4(31),
C => CLK,
CE => EN);
R2_PIPE_49: FDE port map (
Q => R1IN_4F(32),
D => R1IN_4(32),
C => CLK,
CE => EN);
R2_PIPE_50: FDE port map (
Q => R1IN_4F(33),
D => R1IN_4(33),
C => CLK,
CE => EN);
R2_PIPE_51: FDE port map (
Q => R1IN_4F(34),
D => R1IN_4(34),
C => CLK,
CE => EN);
R2_PIPE_52: FDE port map (
Q => R1IN_4F(35),
D => R1IN_4(35),
C => CLK,
CE => EN);
R2_PIPE_53: FDE port map (
Q => R1IN_4F(36),
D => R1IN_4(36),
C => CLK,
CE => EN);
R2_PIPE_54: FDE port map (
Q => R1IN_4F(37),
D => R1IN_4(37),
C => CLK,
CE => EN);
R2_PIPE_55: FDE port map (
Q => R1IN_4F(38),
D => R1IN_4(38),
C => CLK,
CE => EN);
R2_PIPE_56: FDE port map (
Q => R1IN_4F(39),
D => R1IN_4(39),
C => CLK,
CE => EN);
R2_PIPE_57: FDE port map (
Q => R1IN_4F(40),
D => R1IN_4(40),
C => CLK,
CE => EN);
R2_PIPE_58: FDE port map (
Q => R1IN_4F(41),
D => R1IN_4(41),
C => CLK,
CE => EN);
R2_PIPE_59: FDE port map (
Q => R1IN_4F(42),
D => R1IN_4(42),
C => CLK,
CE => EN);
R2_PIPE_60: FDE port map (
Q => R1IN_4F(43),
D => R1IN_4(43),
C => CLK,
CE => EN);
R2_PIPE_61: FDE port map (
Q => R1IN_4F(44),
D => R1IN_4(44),
C => CLK,
CE => EN);
R2_PIPE_62: FDE port map (
Q => R1IN_4F(45),
D => R1IN_4(45),
C => CLK,
CE => EN);
R2_PIPE_63: FDE port map (
Q => R1IN_4F(46),
D => R1IN_4(46),
C => CLK,
CE => EN);
R2_PIPE_64: FDE port map (
Q => R1IN_4F(47),
D => R1IN_4(47),
C => CLK,
CE => EN);
R2_PIPE_65: FDE port map (
Q => R1IN_4F(48),
D => R1IN_4(48),
C => CLK,
CE => EN);
R2_PIPE_66: FDE port map (
Q => R1IN_4F(49),
D => R1IN_4(49),
C => CLK,
CE => EN);
R2_PIPE_67: FDE port map (
Q => R1IN_4F(50),
D => R1IN_4(50),
C => CLK,
CE => EN);
R2_PIPE_68: FDE port map (
Q => R1IN_4F(51),
D => R1IN_4(51),
C => CLK,
CE => EN);
R2_PIPE_69: FDE port map (
Q => R1IN_4F(52),
D => R1IN_4(52),
C => CLK,
CE => EN);
R2_PIPE_105: FDE port map (
Q => R1IN_ADD_1FF(0),
D => R1IN_ADD_1(0),
C => CLK,
CE => EN);
R2_PIPE_106: FDE port map (
Q => R1IN_ADD_1FF(1),
D => R1IN_ADD_1(1),
C => CLK,
CE => EN);
R2_PIPE_107: FDE port map (
Q => R1IN_ADD_1FF(2),
D => R1IN_ADD_1(2),
C => CLK,
CE => EN);
R2_PIPE_108: FDE port map (
Q => R1IN_ADD_1FF(3),
D => R1IN_ADD_1(3),
C => CLK,
CE => EN);
R2_PIPE_109: FDE port map (
Q => R1IN_ADD_1FF(4),
D => R1IN_ADD_1(4),
C => CLK,
CE => EN);
R2_PIPE_110: FDE port map (
Q => R1IN_ADD_1FF(5),
D => R1IN_ADD_1(5),
C => CLK,
CE => EN);
R2_PIPE_111: FDE port map (
Q => R1IN_ADD_1FF(6),
D => R1IN_ADD_1(6),
C => CLK,
CE => EN);
R2_PIPE_112: FDE port map (
Q => R1IN_ADD_1FF(7),
D => R1IN_ADD_1(7),
C => CLK,
CE => EN);
R2_PIPE_113: FDE port map (
Q => R1IN_ADD_1FF(8),
D => R1IN_ADD_1(8),
C => CLK,
CE => EN);
R2_PIPE_114: FDE port map (
Q => R1IN_ADD_1FF(9),
D => R1IN_ADD_1(9),
C => CLK,
CE => EN);
R2_PIPE_115: FDE port map (
Q => R1IN_ADD_1FF(10),
D => R1IN_ADD_1(10),
C => CLK,
CE => EN);
R2_PIPE_116: FDE port map (
Q => R1IN_ADD_1FF(11),
D => R1IN_ADD_1(11),
C => CLK,
CE => EN);
R2_PIPE_117: FDE port map (
Q => R1IN_ADD_1FF(12),
D => R1IN_ADD_1(12),
C => CLK,
CE => EN);
R2_PIPE_118: FDE port map (
Q => R1IN_ADD_1FF(13),
D => R1IN_ADD_1(13),
C => CLK,
CE => EN);
R2_PIPE_119: FDE port map (
Q => R1IN_ADD_1FF(14),
D => R1IN_ADD_1(14),
C => CLK,
CE => EN);
R2_PIPE_120: FDE port map (
Q => R1IN_ADD_1FF(15),
D => R1IN_ADD_1(15),
C => CLK,
CE => EN);
R2_PIPE_121: FDE port map (
Q => R1IN_ADD_1FF(16),
D => R1IN_ADD_1(16),
C => CLK,
CE => EN);
R2_PIPE_122: FDE port map (
Q => R1IN_ADD_1FF(17),
D => R1IN_ADD_1(17),
C => CLK,
CE => EN);
R2_PIPE_123: FDE port map (
Q => R1IN_ADD_1FF(18),
D => R1IN_ADD_1(18),
C => CLK,
CE => EN);
R2_PIPE_124: FDE port map (
Q => R1IN_ADD_1FF(19),
D => R1IN_ADD_1(19),
C => CLK,
CE => EN);
R2_PIPE_125: FDE port map (
Q => R1IN_ADD_1FF(20),
D => R1IN_ADD_1(20),
C => CLK,
CE => EN);
R2_PIPE_126: FDE port map (
Q => R1IN_ADD_1FF(21),
D => R1IN_ADD_1(21),
C => CLK,
CE => EN);
R2_PIPE_127: FDE port map (
Q => R1IN_ADD_1FF(22),
D => R1IN_ADD_1(22),
C => CLK,
CE => EN);
R2_PIPE_128: FDE port map (
Q => R1IN_ADD_1FF(23),
D => R1IN_ADD_1(23),
C => CLK,
CE => EN);
R2_PIPE_129: FDE port map (
Q => R1IN_ADD_1FF(24),
D => R1IN_ADD_1(24),
C => CLK,
CE => EN);
R2_PIPE_130: FDE port map (
Q => R1IN_ADD_1FF(25),
D => R1IN_ADD_1(25),
C => CLK,
CE => EN);
R2_PIPE_131: FDE port map (
Q => R1IN_ADD_1FF(26),
D => R1IN_ADD_1(26),
C => CLK,
CE => EN);
R2_PIPE_132: FDE port map (
Q => R1IN_ADD_1FF(27),
D => R1IN_ADD_1(27),
C => CLK,
CE => EN);
R2_PIPE_133: FDE port map (
Q => R1IN_ADD_1FF(28),
D => R1IN_ADD_1(28),
C => CLK,
CE => EN);
R2_PIPE_134: FDE port map (
Q => R1IN_ADD_1FF(29),
D => R1IN_ADD_1(29),
C => CLK,
CE => EN);
R2_PIPE_135: FDE port map (
Q => R1IN_ADD_1FF(30),
D => R1IN_ADD_1(30),
C => CLK,
CE => EN);
R2_PIPE_136: FDE port map (
Q => R1IN_ADD_1FF(31),
D => R1IN_ADD_1(31),
C => CLK,
CE => EN);
R2_PIPE_137: FDE port map (
Q => R1IN_ADD_1FF(32),
D => R1IN_ADD_1(32),
C => CLK,
CE => EN);
R1_PIPE_105: FDE port map (
Q => R1IN_2_ADD_1,
D => R1IN_2_2(0),
C => CLK,
CE => EN);
R1_PIPE_589: FDE port map (
Q => R1IN_2_2F(1),
D => R1IN_2_2(1),
C => CLK,
CE => EN);
R1_PIPE_590: FDE port map (
Q => R1IN_2_2F(2),
D => R1IN_2_2(2),
C => CLK,
CE => EN);
R1_PIPE_591: FDE port map (
Q => R1IN_2_2F(3),
D => R1IN_2_2(3),
C => CLK,
CE => EN);
R1_PIPE_592: FDE port map (
Q => R1IN_2_2F(4),
D => R1IN_2_2(4),
C => CLK,
CE => EN);
R1_PIPE_593: FDE port map (
Q => R1IN_2_2F(5),
D => R1IN_2_2(5),
C => CLK,
CE => EN);
R1_PIPE_594: FDE port map (
Q => R1IN_2_2F(6),
D => R1IN_2_2(6),
C => CLK,
CE => EN);
R1_PIPE_595: FDE port map (
Q => R1IN_2_2F(7),
D => R1IN_2_2(7),
C => CLK,
CE => EN);
R1_PIPE_596: FDE port map (
Q => R1IN_2_2F(8),
D => R1IN_2_2(8),
C => CLK,
CE => EN);
R1_PIPE_597: FDE port map (
Q => R1IN_2_2F(9),
D => R1IN_2_2(9),
C => CLK,
CE => EN);
R1_PIPE_598: FDE port map (
Q => R1IN_2_2F(10),
D => R1IN_2_2(10),
C => CLK,
CE => EN);
R1_PIPE_599: FDE port map (
Q => R1IN_2_2F(11),
D => R1IN_2_2(11),
C => CLK,
CE => EN);
R1_PIPE_600: FDE port map (
Q => R1IN_2_2F(12),
D => R1IN_2_2(12),
C => CLK,
CE => EN);
R1_PIPE_601: FDE port map (
Q => R1IN_2_2F(13),
D => R1IN_2_2(13),
C => CLK,
CE => EN);
R1_PIPE_602: FDE port map (
Q => R1IN_2_2F(14),
D => R1IN_2_2(14),
C => CLK,
CE => EN);
R1_PIPE_603: FDE port map (
Q => R1IN_2_2F(15),
D => R1IN_2_2(15),
C => CLK,
CE => EN);
R1_PIPE_604: FDE port map (
Q => R1IN_2_2F(16),
D => R1IN_2_2(16),
C => CLK,
CE => EN);
R1_PIPE_484: FDE port map (
Q => R1IN_3_ADD_1,
D => R1IN_3_2(0),
C => CLK,
CE => EN);
R1_PIPE_649: FDE port map (
Q => R1IN_3_2F(1),
D => R1IN_3_2(1),
C => CLK,
CE => EN);
R1_PIPE_650: FDE port map (
Q => R1IN_3_2F(2),
D => R1IN_3_2(2),
C => CLK,
CE => EN);
R1_PIPE_651: FDE port map (
Q => R1IN_3_2F(3),
D => R1IN_3_2(3),
C => CLK,
CE => EN);
R1_PIPE_652: FDE port map (
Q => R1IN_3_2F(4),
D => R1IN_3_2(4),
C => CLK,
CE => EN);
R1_PIPE_653: FDE port map (
Q => R1IN_3_2F(5),
D => R1IN_3_2(5),
C => CLK,
CE => EN);
R1_PIPE_654: FDE port map (
Q => R1IN_3_2F(6),
D => R1IN_3_2(6),
C => CLK,
CE => EN);
R1_PIPE_655: FDE port map (
Q => R1IN_3_2F(7),
D => R1IN_3_2(7),
C => CLK,
CE => EN);
R1_PIPE_656: FDE port map (
Q => R1IN_3_2F(8),
D => R1IN_3_2(8),
C => CLK,
CE => EN);
R1_PIPE_657: FDE port map (
Q => R1IN_3_2F(9),
D => R1IN_3_2(9),
C => CLK,
CE => EN);
R1_PIPE_658: FDE port map (
Q => R1IN_3_2F(10),
D => R1IN_3_2(10),
C => CLK,
CE => EN);
R1_PIPE_659: FDE port map (
Q => R1IN_3_2F(11),
D => R1IN_3_2(11),
C => CLK,
CE => EN);
R1_PIPE_660: FDE port map (
Q => R1IN_3_2F(12),
D => R1IN_3_2(12),
C => CLK,
CE => EN);
R1_PIPE_661: FDE port map (
Q => R1IN_3_2F(13),
D => R1IN_3_2(13),
C => CLK,
CE => EN);
R1_PIPE_662: FDE port map (
Q => R1IN_3_2F(14),
D => R1IN_3_2(14),
C => CLK,
CE => EN);
R1_PIPE_663: FDE port map (
Q => R1IN_3_2F(15),
D => R1IN_3_2(15),
C => CLK,
CE => EN);
R1_PIPE_664: FDE port map (
Q => R1IN_3_2F(16),
D => R1IN_3_2(16),
C => CLK,
CE => EN);
R2_PIPE_104_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_103_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_0,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_102_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_1,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_101_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_2,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_100_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_3,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_99_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_4,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_98_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_5,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_97_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_6,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_96_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_7,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_95_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_8,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_94_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_9,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_93_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_10,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_92_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_11,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_91_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_12,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_90_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_13,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_89_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_14,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_88_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_15,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_87_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_16,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_86_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_17,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_85_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_18,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_84_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_19,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_83_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_20,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_82_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_21,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_81_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_22,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_80_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_23,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_79_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_24,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_78_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_25,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_77_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_26,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_76_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_27,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_75_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_28,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_74_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_29,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_157_RET_Z5786: FDE port map (
Q => R2_PIPE_157_RET,
D => N_1577,
C => CLK,
CE => EN);
R2_PIPE_157_RET_1_Z5787: FDE port map (
Q => R2_PIPE_157_RET_1,
D => N_1913,
C => CLK,
CE => EN);
R2_PIPE_157_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_73_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_30,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_156_RET_Z5790: FDE port map (
Q => R2_PIPE_156_RET,
D => N_1575,
C => CLK,
CE => EN);
R2_PIPE_156_RET_1_Z5791: FDE port map (
Q => R2_PIPE_156_RET_1,
D => N_1912,
C => CLK,
CE => EN);
R2_PIPE_156_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_0,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_72_RET_2: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_31,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
R2_PIPE_155_RET_Z5794: FDE port map (
Q => R2_PIPE_155_RET,
D => N_1573,
C => CLK,
CE => EN);
R2_PIPE_155_RET_1_Z5795: FDE port map (
Q => R2_PIPE_155_RET_1,
D => N_1911,
C => CLK,
CE => EN);
R2_PIPE_155_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_1,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_154_RET_Z5797: FDE port map (
Q => R2_PIPE_154_RET,
D => N_1571,
C => CLK,
CE => EN);
R2_PIPE_154_RET_1_Z5798: FDE port map (
Q => R2_PIPE_154_RET_1,
D => N_1910,
C => CLK,
CE => EN);
R2_PIPE_154_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_2,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_153_RET_Z5800: FDE port map (
Q => R2_PIPE_153_RET,
D => N_1569,
C => CLK,
CE => EN);
R2_PIPE_153_RET_1_Z5801: FDE port map (
Q => R2_PIPE_153_RET_1,
D => N_1909,
C => CLK,
CE => EN);
R2_PIPE_153_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_3,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_152_RET_Z5803: FDE port map (
Q => R2_PIPE_152_RET,
D => N_1567,
C => CLK,
CE => EN);
R2_PIPE_152_RET_1_Z5804: FDE port map (
Q => R2_PIPE_152_RET_1,
D => N_1908,
C => CLK,
CE => EN);
R2_PIPE_152_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_4,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_151_RET_Z5806: FDE port map (
Q => R2_PIPE_151_RET,
D => N_1565,
C => CLK,
CE => EN);
R2_PIPE_151_RET_1_Z5807: FDE port map (
Q => R2_PIPE_151_RET_1,
D => N_1907,
C => CLK,
CE => EN);
R2_PIPE_151_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_5,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_150_RET_Z5809: FDE port map (
Q => R2_PIPE_150_RET,
D => N_1563,
C => CLK,
CE => EN);
R2_PIPE_150_RET_1_Z5810: FDE port map (
Q => R2_PIPE_150_RET_1,
D => N_1906,
C => CLK,
CE => EN);
R2_PIPE_150_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_6,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_149_RET_Z5812: FDE port map (
Q => R2_PIPE_149_RET,
D => N_1561,
C => CLK,
CE => EN);
R2_PIPE_149_RET_1_Z5813: FDE port map (
Q => R2_PIPE_149_RET_1,
D => N_1905,
C => CLK,
CE => EN);
R2_PIPE_149_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_7,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_148_RET_Z5815: FDE port map (
Q => R2_PIPE_148_RET,
D => N_1559,
C => CLK,
CE => EN);
R2_PIPE_148_RET_1_Z5816: FDE port map (
Q => R2_PIPE_148_RET_1,
D => N_1904,
C => CLK,
CE => EN);
R2_PIPE_148_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_8,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_147_RET_Z5818: FDE port map (
Q => R2_PIPE_147_RET,
D => N_1557,
C => CLK,
CE => EN);
R2_PIPE_147_RET_1_Z5819: FDE port map (
Q => R2_PIPE_147_RET_1,
D => N_1903,
C => CLK,
CE => EN);
R2_PIPE_147_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_9,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_146_RET_Z5821: FDE port map (
Q => R2_PIPE_146_RET,
D => N_1555,
C => CLK,
CE => EN);
R2_PIPE_146_RET_1_Z5822: FDE port map (
Q => R2_PIPE_146_RET_1,
D => N_1902,
C => CLK,
CE => EN);
R2_PIPE_146_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_10,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_145_RET_Z5824: FDE port map (
Q => R2_PIPE_145_RET,
D => N_1553,
C => CLK,
CE => EN);
R2_PIPE_145_RET_1_Z5825: FDE port map (
Q => R2_PIPE_145_RET_1,
D => N_1901,
C => CLK,
CE => EN);
R2_PIPE_145_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_11,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_144_RET_Z5827: FDE port map (
Q => R2_PIPE_144_RET,
D => N_1551,
C => CLK,
CE => EN);
R2_PIPE_144_RET_1_Z5828: FDE port map (
Q => R2_PIPE_144_RET_1,
D => N_1900,
C => CLK,
CE => EN);
R2_PIPE_144_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_12,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_143_RET_Z5830: FDE port map (
Q => R2_PIPE_143_RET,
D => N_1549,
C => CLK,
CE => EN);
R2_PIPE_143_RET_1_Z5831: FDE port map (
Q => R2_PIPE_143_RET_1,
D => N_1899,
C => CLK,
CE => EN);
R2_PIPE_143_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_13,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_142_RET_Z5833: FDE port map (
Q => R2_PIPE_142_RET,
D => N_1547,
C => CLK,
CE => EN);
R2_PIPE_142_RET_1_Z5834: FDE port map (
Q => R2_PIPE_142_RET_1,
D => N_1898,
C => CLK,
CE => EN);
R2_PIPE_142_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_14,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_141_RET_Z5836: FDE port map (
Q => R2_PIPE_141_RET,
D => N_1545,
C => CLK,
CE => EN);
R2_PIPE_141_RET_1_Z5837: FDE port map (
Q => R2_PIPE_141_RET_1,
D => N_1897,
C => CLK,
CE => EN);
R2_PIPE_141_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_15,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_140_RET_Z5839: FDE port map (
Q => R2_PIPE_140_RET,
D => N_1543,
C => CLK,
CE => EN);
R2_PIPE_140_RET_1_Z5840: FDE port map (
Q => R2_PIPE_140_RET_1,
D => N_1896,
C => CLK,
CE => EN);
R2_PIPE_140_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_16,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_139_RET_Z5842: FDE port map (
Q => R2_PIPE_139_RET,
D => N_1541,
C => CLK,
CE => EN);
R2_PIPE_139_RET_1_Z5843: FDE port map (
Q => R2_PIPE_139_RET_1,
D => N_1895,
C => CLK,
CE => EN);
R2_PIPE_139_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_17,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_138_RET_Z5845: FDE port map (
Q => R2_PIPE_138_RET,
D => N_1539,
C => CLK,
CE => EN);
R2_PIPE_138_RET_1_Z5846: FDE port map (
Q => R2_PIPE_138_RET_1,
D => N_1894,
C => CLK,
CE => EN);
R2_PIPE_138_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_18,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_104_RET_3: FDE port map (
Q => R1IN_4_ADD_2_0_CRY_35_RETO_32,
D => R1IN_4_ADD_2_0_CRY_35,
C => CLK,
CE => EN);
\R1IN_3_1[0]\: FDE port map (
Q => R1IN_3F(0),
D => R1IN_3F_0(0),
C => CLK,
CE => EN);
\R1IN_3_1[1]\: FDE port map (
Q => R1IN_3F(1),
D => R1IN_3F_0(1),
C => CLK,
CE => EN);
\R1IN_3_1[2]\: FDE port map (
Q => R1IN_3F(2),
D => R1IN_3F_0(2),
C => CLK,
CE => EN);
\R1IN_3_1[3]\: FDE port map (
Q => R1IN_3F(3),
D => R1IN_3F_0(3),
C => CLK,
CE => EN);
\R1IN_3_1[4]\: FDE port map (
Q => R1IN_3F(4),
D => R1IN_3F_0(4),
C => CLK,
CE => EN);
\R1IN_3_1[5]\: FDE port map (
Q => R1IN_3F(5),
D => R1IN_3F_0(5),
C => CLK,
CE => EN);
\R1IN_3_1[6]\: FDE port map (
Q => R1IN_3F(6),
D => R1IN_3F_0(6),
C => CLK,
CE => EN);
\R1IN_3_1[7]\: FDE port map (
Q => R1IN_3F(7),
D => R1IN_3F_0(7),
C => CLK,
CE => EN);
\R1IN_3_1[8]\: FDE port map (
Q => R1IN_3F(8),
D => R1IN_3F_0(8),
C => CLK,
CE => EN);
\R1IN_3_1[9]\: FDE port map (
Q => R1IN_3F(9),
D => R1IN_3F_0(9),
C => CLK,
CE => EN);
\R1IN_3_1[10]\: FDE port map (
Q => R1IN_3F(10),
D => R1IN_3F_0(10),
C => CLK,
CE => EN);
\R1IN_3_1[11]\: FDE port map (
Q => R1IN_3F(11),
D => R1IN_3F_0(11),
C => CLK,
CE => EN);
\R1IN_3_1[12]\: FDE port map (
Q => R1IN_3F(12),
D => R1IN_3F_0(12),
C => CLK,
CE => EN);
\R1IN_3_1[13]\: FDE port map (
Q => R1IN_3F(13),
D => R1IN_3F_0(13),
C => CLK,
CE => EN);
\R1IN_3_1[14]\: FDE port map (
Q => R1IN_3F(14),
D => R1IN_3F_0(14),
C => CLK,
CE => EN);
\R1IN_3_1[15]\: FDE port map (
Q => R1IN_3F(15),
D => R1IN_3F_0(15),
C => CLK,
CE => EN);
\R1IN_3_1[16]\: FDE port map (
Q => R1IN_3F(16),
D => R1IN_3F_0(16),
C => CLK,
CE => EN);
\R1IN_3_1[17]\: FDE port map (
Q => R1IN_3_1F(17),
D => R1IN_3_1F_0(17),
C => CLK,
CE => EN);
\R1IN_3_1[18]\: FDE port map (
Q => R1IN_3_1F(18),
D => R1IN_3_1F_0(18),
C => CLK,
CE => EN);
\R1IN_3_1[19]\: FDE port map (
Q => R1IN_3_1F(19),
D => R1IN_3_1F_0(19),
C => CLK,
CE => EN);
\R1IN_3_1[20]\: FDE port map (
Q => R1IN_3_1F(20),
D => R1IN_3_1F_0(20),
C => CLK,
CE => EN);
\R1IN_3_1[21]\: FDE port map (
Q => R1IN_3_1F(21),
D => R1IN_3_1F_0(21),
C => CLK,
CE => EN);
\R1IN_3_1[22]\: FDE port map (
Q => R1IN_3_1F(22),
D => R1IN_3_1F_0(22),
C => CLK,
CE => EN);
\R1IN_3_1[23]\: FDE port map (
Q => R1IN_3_1F(23),
D => R1IN_3_1F_0(23),
C => CLK,
CE => EN);
\R1IN_3_1[24]\: FDE port map (
Q => R1IN_3_1F(24),
D => R1IN_3_1F_0(24),
C => CLK,
CE => EN);
\R1IN_3_1[25]\: FDE port map (
Q => R1IN_3_1F(25),
D => R1IN_3_1F_0(25),
C => CLK,
CE => EN);
\R1IN_3_1[26]\: FDE port map (
Q => R1IN_3_1F(26),
D => R1IN_3_1F_0(26),
C => CLK,
CE => EN);
\R1IN_3_1[27]\: FDE port map (
Q => R1IN_3_1F(27),
D => R1IN_3_1F_0(27),
C => CLK,
CE => EN);
\R1IN_3_1[28]\: FDE port map (
Q => R1IN_3_1F(28),
D => R1IN_3_1F_0(28),
C => CLK,
CE => EN);
\R1IN_3_1[29]\: FDE port map (
Q => R1IN_3_1F(29),
D => R1IN_3_1F_0(29),
C => CLK,
CE => EN);
\R1IN_3_1[30]\: FDE port map (
Q => R1IN_3_1F(30),
D => R1IN_3_1F_0(30),
C => CLK,
CE => EN);
\R1IN_3_1[31]\: FDE port map (
Q => R1IN_3_1F(31),
D => R1IN_3_1F_0(31),
C => CLK,
CE => EN);
\R1IN_3_1[32]\: FDE port map (
Q => R1IN_3_1F(32),
D => R1IN_3_1F_0(32),
C => CLK,
CE => EN);
\R1IN_3_1[33]\: FDE port map (
Q => R1IN_3_1F(33),
D => R1IN_3_1F_0(33),
C => CLK,
CE => EN);
\R1IN_2_1[0]\: FDE port map (
Q => R1IN_2F(0),
D => R1IN_2F_0(0),
C => CLK,
CE => EN);
\R1IN_2_1[1]\: FDE port map (
Q => R1IN_2F(1),
D => R1IN_2F_0(1),
C => CLK,
CE => EN);
\R1IN_2_1[2]\: FDE port map (
Q => R1IN_2F(2),
D => R1IN_2F_0(2),
C => CLK,
CE => EN);
\R1IN_2_1[3]\: FDE port map (
Q => R1IN_2F(3),
D => R1IN_2F_0(3),
C => CLK,
CE => EN);
\R1IN_2_1[4]\: FDE port map (
Q => R1IN_2F(4),
D => R1IN_2F_0(4),
C => CLK,
CE => EN);
\R1IN_2_1[5]\: FDE port map (
Q => R1IN_2F(5),
D => R1IN_2F_0(5),
C => CLK,
CE => EN);
\R1IN_2_1[6]\: FDE port map (
Q => R1IN_2F(6),
D => R1IN_2F_0(6),
C => CLK,
CE => EN);
\R1IN_2_1[7]\: FDE port map (
Q => R1IN_2F(7),
D => R1IN_2F_0(7),
C => CLK,
CE => EN);
\R1IN_2_1[8]\: FDE port map (
Q => R1IN_2F(8),
D => R1IN_2F_0(8),
C => CLK,
CE => EN);
\R1IN_2_1[9]\: FDE port map (
Q => R1IN_2F(9),
D => R1IN_2F_0(9),
C => CLK,
CE => EN);
\R1IN_2_1[10]\: FDE port map (
Q => R1IN_2F(10),
D => R1IN_2F_0(10),
C => CLK,
CE => EN);
\R1IN_2_1[11]\: FDE port map (
Q => R1IN_2F(11),
D => R1IN_2F_0(11),
C => CLK,
CE => EN);
\R1IN_2_1[12]\: FDE port map (
Q => R1IN_2F(12),
D => R1IN_2F_0(12),
C => CLK,
CE => EN);
\R1IN_2_1[13]\: FDE port map (
Q => R1IN_2F(13),
D => R1IN_2F_0(13),
C => CLK,
CE => EN);
\R1IN_2_1[14]\: FDE port map (
Q => R1IN_2F(14),
D => R1IN_2F_0(14),
C => CLK,
CE => EN);
\R1IN_2_1[15]\: FDE port map (
Q => R1IN_2F(15),
D => R1IN_2F_0(15),
C => CLK,
CE => EN);
\R1IN_2_1[16]\: FDE port map (
Q => R1IN_2F(16),
D => R1IN_2F_0(16),
C => CLK,
CE => EN);
\R1IN_2_1[17]\: FDE port map (
Q => R1IN_2_1F(17),
D => R1IN_2_1F_0(17),
C => CLK,
CE => EN);
\R1IN_2_1[18]\: FDE port map (
Q => R1IN_2_1F(18),
D => R1IN_2_1F_0(18),
C => CLK,
CE => EN);
\R1IN_2_1[19]\: FDE port map (
Q => R1IN_2_1F(19),
D => R1IN_2_1F_0(19),
C => CLK,
CE => EN);
\R1IN_2_1[20]\: FDE port map (
Q => R1IN_2_1F(20),
D => R1IN_2_1F_0(20),
C => CLK,
CE => EN);
\R1IN_2_1[21]\: FDE port map (
Q => R1IN_2_1F(21),
D => R1IN_2_1F_0(21),
C => CLK,
CE => EN);
\R1IN_2_1[22]\: FDE port map (
Q => R1IN_2_1F(22),
D => R1IN_2_1F_0(22),
C => CLK,
CE => EN);
\R1IN_2_1[23]\: FDE port map (
Q => R1IN_2_1F(23),
D => R1IN_2_1F_0(23),
C => CLK,
CE => EN);
\R1IN_2_1[24]\: FDE port map (
Q => R1IN_2_1F(24),
D => R1IN_2_1F_0(24),
C => CLK,
CE => EN);
\R1IN_2_1[25]\: FDE port map (
Q => R1IN_2_1F(25),
D => R1IN_2_1F_0(25),
C => CLK,
CE => EN);
\R1IN_2_1[26]\: FDE port map (
Q => R1IN_2_1F(26),
D => R1IN_2_1F_0(26),
C => CLK,
CE => EN);
\R1IN_2_1[27]\: FDE port map (
Q => R1IN_2_1F(27),
D => R1IN_2_1F_0(27),
C => CLK,
CE => EN);
\R1IN_2_1[28]\: FDE port map (
Q => R1IN_2_1F(28),
D => R1IN_2_1F_0(28),
C => CLK,
CE => EN);
\R1IN_2_1[29]\: FDE port map (
Q => R1IN_2_1F(29),
D => R1IN_2_1F_0(29),
C => CLK,
CE => EN);
\R1IN_2_1[30]\: FDE port map (
Q => R1IN_2_1F(30),
D => R1IN_2_1F_0(30),
C => CLK,
CE => EN);
\R1IN_2_1[31]\: FDE port map (
Q => R1IN_2_1F(31),
D => R1IN_2_1F_0(31),
C => CLK,
CE => EN);
\R1IN_2_1[32]\: FDE port map (
Q => R1IN_2_1F(32),
D => R1IN_2_1F_0(32),
C => CLK,
CE => EN);
\R1IN_2_1[33]\: FDE port map (
Q => R1IN_2_1F(33),
D => R1IN_2_1F_0(33),
C => CLK,
CE => EN);
R2_PIPE_165_RET_Z5917: FDE port map (
Q => R2_PIPE_165_RET,
D => R1IN_ADD_1_1_S_28,
C => CLK,
CE => EN);
R2_PIPE_165_RET_1_Z5918: FDE port map (
Q => R2_PIPE_165_RET_1,
D => R1IN_ADD_1_1_0_S_28,
C => CLK,
CE => EN);
R2_PIPE_165_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_19,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_164_RET_Z5920: FDE port map (
Q => R2_PIPE_164_RET,
D => R1IN_ADD_1_1_S_27,
C => CLK,
CE => EN);
R2_PIPE_164_RET_1_Z5921: FDE port map (
Q => R2_PIPE_164_RET_1,
D => R1IN_ADD_1_1_0_S_27,
C => CLK,
CE => EN);
R2_PIPE_164_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_20,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_163_RET_Z5923: FDE port map (
Q => R2_PIPE_163_RET,
D => R1IN_ADD_1_1_S_26,
C => CLK,
CE => EN);
R2_PIPE_163_RET_1_Z5924: FDE port map (
Q => R2_PIPE_163_RET_1,
D => R1IN_ADD_1_1_0_S_26,
C => CLK,
CE => EN);
R2_PIPE_163_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_21,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_162_RET_Z5926: FDE port map (
Q => R2_PIPE_162_RET,
D => R1IN_ADD_1_1_S_25,
C => CLK,
CE => EN);
R2_PIPE_162_RET_1_Z5927: FDE port map (
Q => R2_PIPE_162_RET_1,
D => R1IN_ADD_1_1_0_S_25,
C => CLK,
CE => EN);
R2_PIPE_162_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_22,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_161_RET_Z5929: FDE port map (
Q => R2_PIPE_161_RET,
D => R1IN_ADD_1_1_S_24,
C => CLK,
CE => EN);
R2_PIPE_161_RET_1_Z5930: FDE port map (
Q => R2_PIPE_161_RET_1,
D => R1IN_ADD_1_1_0_S_24,
C => CLK,
CE => EN);
R2_PIPE_161_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_23,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_160_RET_Z5932: FDE port map (
Q => R2_PIPE_160_RET,
D => R1IN_ADD_1_1_S_23,
C => CLK,
CE => EN);
R2_PIPE_160_RET_1_Z5933: FDE port map (
Q => R2_PIPE_160_RET_1,
D => R1IN_ADD_1_1_0_S_23,
C => CLK,
CE => EN);
R2_PIPE_160_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_24,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_159_RET_Z5935: FDE port map (
Q => R2_PIPE_159_RET,
D => R1IN_ADD_1_1_S_22,
C => CLK,
CE => EN);
R2_PIPE_159_RET_1_Z5936: FDE port map (
Q => R2_PIPE_159_RET_1,
D => R1IN_ADD_1_1_0_S_22,
C => CLK,
CE => EN);
R2_PIPE_159_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_25,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_158_RET_Z5938: FDE port map (
Q => R2_PIPE_158_RET,
D => R1IN_ADD_1_1_S_21,
C => CLK,
CE => EN);
R2_PIPE_158_RET_1_Z5939: FDE port map (
Q => R2_PIPE_158_RET_1,
D => R1IN_ADD_1_1_0_S_21,
C => CLK,
CE => EN);
R2_PIPE_158_RET_2: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_26,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_166_RET: FDE port map (
Q => R1IN_ADD_1_0_CRY_31_RETO_27,
D => R1IN_ADD_1_0_CRY_31,
C => CLK,
CE => EN);
R2_PIPE_166_RET_1: FDE port map (
Q => R1IN_ADD_1_1_0_CRY_28_RETO,
D => R1IN_ADD_1_1_0_CRY_28,
C => CLK,
CE => EN);
R2_PIPE_166_RET_2: FDE port map (
Q => R1IN_ADD_1_1_CRY_28_RETO,
D => R1IN_ADD_1_1_CRY_28,
C => CLK,
CE => EN);
R2_PIPE_104_RET_48_Z5944: FDE port map (
Q => R2_PIPE_104_RET_48,
D => N_1822_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_49_Z5945: FDE port map (
Q => R2_PIPE_104_RET_49,
D => N_1821_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_93_Z5946: FDE port map (
Q => R2_PIPE_104_RET_93,
D => N_1820_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_94_Z5947: FDE port map (
Q => R2_PIPE_104_RET_94,
D => N_1819_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_95_Z5948: FDE port map (
Q => R2_PIPE_104_RET_95,
D => N_1818_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_96_Z5949: FDE port map (
Q => R2_PIPE_104_RET_96,
D => N_1817_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_97_Z5950: FDE port map (
Q => R2_PIPE_104_RET_97,
D => N_1816_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_98_Z5951: FDE port map (
Q => R2_PIPE_104_RET_98,
D => N_1815_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_99_Z5952: FDE port map (
Q => R2_PIPE_104_RET_99,
D => N_1814_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_100_Z5953: FDE port map (
Q => R2_PIPE_104_RET_100,
D => N_1813_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_101_Z5954: FDE port map (
Q => R2_PIPE_104_RET_101,
D => N_1812_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_102_Z5955: FDE port map (
Q => R2_PIPE_104_RET_102,
D => N_1811_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_103_Z5956: FDE port map (
Q => R2_PIPE_104_RET_103,
D => N_1810_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_104_Z5957: FDE port map (
Q => R2_PIPE_104_RET_104,
D => N_1809_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_105_Z5958: FDE port map (
Q => R2_PIPE_104_RET_105,
D => N_1808_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_106_Z5959: FDE port map (
Q => R2_PIPE_104_RET_106,
D => N_1807_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_107_Z5960: FDE port map (
Q => R2_PIPE_104_RET_107,
D => N_1806_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_108_Z5961: FDE port map (
Q => R2_PIPE_104_RET_108,
D => N_1805_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_109_Z5962: FDE port map (
Q => R2_PIPE_104_RET_109,
D => N_1804_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_110_Z5963: FDE port map (
Q => R2_PIPE_104_RET_110,
D => N_1803_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_111_Z5964: FDE port map (
Q => R2_PIPE_104_RET_111,
D => N_1802_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_112_Z5965: FDE port map (
Q => R2_PIPE_104_RET_112,
D => N_1801_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_113_Z5966: FDE port map (
Q => R2_PIPE_104_RET_113,
D => N_1800_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_114_Z5967: FDE port map (
Q => R2_PIPE_104_RET_114,
D => N_1799_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_115_Z5968: FDE port map (
Q => R2_PIPE_104_RET_115,
D => N_1798_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_116_Z5969: FDE port map (
Q => R2_PIPE_104_RET_116,
D => N_1797_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_117_Z5970: FDE port map (
Q => R2_PIPE_104_RET_117,
D => N_1796_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_118_Z5971: FDE port map (
Q => R2_PIPE_104_RET_118,
D => N_1795_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_119_Z5972: FDE port map (
Q => R2_PIPE_104_RET_119,
D => N_1794_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_120_Z5973: FDE port map (
Q => R2_PIPE_104_RET_120,
D => N_1793_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_121_Z5974: FDE port map (
Q => R2_PIPE_104_RET_121,
D => N_1792_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_122_Z5975: FDE port map (
Q => R2_PIPE_104_RET_122,
D => N_1791_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_123_Z5976: FDE port map (
Q => R2_PIPE_104_RET_123,
D => N_1790_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_124_Z5977: FDE port map (
Q => R2_PIPE_104_RET_124,
D => N_1789_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_125: FDE port map (
Q => R1IN_4_ADD_2_1_0_AXB_0_RETO,
D => R1IN_4_ADD_2_1_0_AXB_0_RET_0I,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1027_Z5979: FDE port map (
Q => R2_PIPE_104_RET_1027,
D => N_1781_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1028_Z5980: FDE port map (
Q => R2_PIPE_104_RET_1028,
D => N_1779_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1029_Z5981: FDE port map (
Q => R2_PIPE_104_RET_1029,
D => N_1777_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1030_Z5982: FDE port map (
Q => R2_PIPE_104_RET_1030,
D => N_1775_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1031_Z5983: FDE port map (
Q => R2_PIPE_104_RET_1031,
D => N_1773_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1032_Z5984: FDE port map (
Q => R2_PIPE_104_RET_1032,
D => N_1771_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1033_Z5985: FDE port map (
Q => R2_PIPE_104_RET_1033,
D => N_1769_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1034_Z5986: FDE port map (
Q => R2_PIPE_104_RET_1034,
D => N_1767_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1035_Z5987: FDE port map (
Q => R2_PIPE_104_RET_1035,
D => N_1765_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1036_Z5988: FDE port map (
Q => R2_PIPE_104_RET_1036,
D => N_1763_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1037_Z5989: FDE port map (
Q => R2_PIPE_104_RET_1037,
D => N_1761_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1038_Z5990: FDE port map (
Q => R2_PIPE_104_RET_1038,
D => N_1759_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1039_Z5991: FDE port map (
Q => R2_PIPE_104_RET_1039,
D => N_1757_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1040_Z5992: FDE port map (
Q => R2_PIPE_104_RET_1040,
D => N_1755_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1041_Z5993: FDE port map (
Q => R2_PIPE_104_RET_1041,
D => N_1753_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1042_Z5994: FDE port map (
Q => R2_PIPE_104_RET_1042,
D => N_1751_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1043_Z5995: FDE port map (
Q => R2_PIPE_104_RET_1043,
D => N_1749_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1044_Z5996: FDE port map (
Q => R2_PIPE_104_RET_1044,
D => N_1747_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1045_Z5997: FDE port map (
Q => R2_PIPE_104_RET_1045,
D => N_1745_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1046_Z5998: FDE port map (
Q => R2_PIPE_104_RET_1046,
D => N_1743_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1047_Z5999: FDE port map (
Q => R2_PIPE_104_RET_1047,
D => N_1741_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1048_Z6000: FDE port map (
Q => R2_PIPE_104_RET_1048,
D => N_1739_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1049_Z6001: FDE port map (
Q => R2_PIPE_104_RET_1049,
D => N_1737_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1050_Z6002: FDE port map (
Q => R2_PIPE_104_RET_1050,
D => N_1735_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1051_Z6003: FDE port map (
Q => R2_PIPE_104_RET_1051,
D => N_1733_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1052_Z6004: FDE port map (
Q => R2_PIPE_104_RET_1052,
D => N_1731_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1053_Z6005: FDE port map (
Q => R2_PIPE_104_RET_1053,
D => N_1729_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1054_Z6006: FDE port map (
Q => R2_PIPE_104_RET_1054,
D => N_1727_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1055_Z6007: FDE port map (
Q => R2_PIPE_104_RET_1055,
D => N_1725_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1056_Z6008: FDE port map (
Q => R2_PIPE_104_RET_1056,
D => N_1723_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1057_Z6009: FDE port map (
Q => R2_PIPE_104_RET_1057,
D => N_1721_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1058_Z6010: FDE port map (
Q => R2_PIPE_104_RET_1058,
D => N_1719_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1059_Z6011: FDE port map (
Q => R2_PIPE_104_RET_1059,
D => N_1717_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1060_Z6012: FDE port map (
Q => R2_PIPE_104_RET_1060,
D => N_1715_RETI,
C => CLK,
CE => EN);
R2_PIPE_104_RET_1061: FDE port map (
Q => R1IN_4_ADD_2_1_AXB_0,
D => R1IN_4_ADD_2_1_AXB_0_RETI,
C => CLK,
CE => EN);
R1IN_ADD_1_1_CRY_28_Z6014: MUXCY port map (
DI => R1IN_3(60),
CI => R1IN_ADD_1_1_CRY_27,
S => R1IN_ADD_1_1_AXB_28,
O => R1IN_ADD_1_1_CRY_28);
R1IN_ADD_2_1_0_AXB_0_Z6015: LUT4
generic map(
INIT => X"596A"
)
port map (
I0 => R1IN_4F(36),
I1 => R1IN_ADD_1_0_CRY_31_RETO_26,
I2 => R2_PIPE_158_RET_1,
I3 => R2_PIPE_158_RET,
O => R1IN_ADD_2_1_0_AXB_0);
R1IN_ADD_2_1_AXB_0_Z6016: LUT4
generic map(
INIT => X"596A"
)
port map (
I0 => R1IN_4F(36),
I1 => R1IN_ADD_1_0_CRY_31_RETO_26,
I2 => R2_PIPE_158_RET_1,
I3 => R2_PIPE_158_RET,
O => R1IN_ADD_2_1_AXB_0);
R1IN_ADD_2_1_AXB_51_Z6017: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO,
I1 => R2_PIPE_104_RET_48,
I2 => R2_PIPE_104_RET_1027,
O => R1IN_ADD_2_1_AXB_51);
R1IN_ADD_2_1_0_AXB_51_Z6018: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => R1IN_4_ADD_2_0_CRY_35_RETO,
I1 => R2_PIPE_104_RET_48,
I2 => R2_PIPE_104_RET_1027,
O => R1IN_ADD_2_1_0_AXB_51);
R1IN_4_ADD_2_1_0_S_34: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_34,
CI => R1IN_4_ADD_2_1_0_CRY_33,
O => N_1822_RET_0I);
R1IN_4_ADD_2_1_0_AXB_34_Z7179: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(53),
LO => R1IN_4_ADD_2_1_0_AXB_34);
R1IN_4_ADD_2_1_0_CRY_33_Z7180: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_32,
S => R1IN_4_ADD_2_1_0_AXB_33,
LO => R1IN_4_ADD_2_1_0_CRY_33);
R1IN_4_ADD_2_1_0_CRY_32_Z7181: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_31,
S => R1IN_4_ADD_2_1_0_AXB_32,
LO => R1IN_4_ADD_2_1_0_CRY_32);
R1IN_4_ADD_2_1_0_S_33: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_33,
CI => R1IN_4_ADD_2_1_0_CRY_32,
O => N_1821_RET_0I);
R1IN_4_ADD_2_1_0_AXB_33_Z7183: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(52),
LO => R1IN_4_ADD_2_1_0_AXB_33);
R1IN_4_ADD_2_1_0_CRY_31_Z7184: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_30,
S => R1IN_4_ADD_2_1_0_AXB_31,
LO => R1IN_4_ADD_2_1_0_CRY_31);
R1IN_4_ADD_2_1_0_S_32: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_32,
CI => R1IN_4_ADD_2_1_0_CRY_31,
O => N_1820_RET_0I);
R1IN_4_ADD_2_1_0_AXB_32_Z7186: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(51),
LO => R1IN_4_ADD_2_1_0_AXB_32);
R1IN_4_ADD_2_1_0_CRY_30_Z7187: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_29,
S => R1IN_4_ADD_2_1_0_AXB_30,
LO => R1IN_4_ADD_2_1_0_CRY_30);
R1IN_4_ADD_2_1_0_S_31: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_31,
CI => R1IN_4_ADD_2_1_0_CRY_30,
O => N_1819_RET_0I);
R1IN_4_ADD_2_1_0_AXB_31_Z7189: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(50),
LO => R1IN_4_ADD_2_1_0_AXB_31);
R1IN_4_ADD_2_1_0_CRY_29_Z7190: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_28,
S => R1IN_4_ADD_2_1_0_AXB_29,
LO => R1IN_4_ADD_2_1_0_CRY_29);
R1IN_4_ADD_2_1_0_S_30: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_30,
CI => R1IN_4_ADD_2_1_0_CRY_29,
O => N_1818_RET_0I);
R1IN_4_ADD_2_1_0_AXB_30_Z7192: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(49),
LO => R1IN_4_ADD_2_1_0_AXB_30);
R1IN_4_ADD_2_1_0_CRY_28_Z7193: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_27,
S => R1IN_4_ADD_2_1_0_AXB_28,
LO => R1IN_4_ADD_2_1_0_CRY_28);
R1IN_4_ADD_2_1_0_S_29: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_29,
CI => R1IN_4_ADD_2_1_0_CRY_28,
O => N_1817_RET_0I);
R1IN_4_ADD_2_1_0_AXB_29_Z7195: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(48),
LO => R1IN_4_ADD_2_1_0_AXB_29);
R1IN_4_ADD_2_1_0_CRY_27_Z7196: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_26,
S => R1IN_4_ADD_2_1_0_AXB_27,
LO => R1IN_4_ADD_2_1_0_CRY_27);
R1IN_4_ADD_2_1_0_S_28: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_28,
CI => R1IN_4_ADD_2_1_0_CRY_27,
O => N_1816_RET_0I);
R1IN_4_ADD_2_1_0_AXB_28_Z7198: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(47),
LO => R1IN_4_ADD_2_1_0_AXB_28);
R1IN_4_ADD_2_1_0_CRY_26_Z7199: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_25,
S => R1IN_4_ADD_2_1_0_AXB_26,
LO => R1IN_4_ADD_2_1_0_CRY_26);
R1IN_4_ADD_2_1_0_S_27: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_27,
CI => R1IN_4_ADD_2_1_0_CRY_26,
O => N_1815_RET_0I);
R1IN_4_ADD_2_1_0_AXB_27_Z7201: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(46),
LO => R1IN_4_ADD_2_1_0_AXB_27);
R1IN_4_ADD_2_1_0_CRY_25_Z7202: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_24,
S => R1IN_4_ADD_2_1_0_AXB_25,
LO => R1IN_4_ADD_2_1_0_CRY_25);
R1IN_4_ADD_2_1_0_S_26: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_26,
CI => R1IN_4_ADD_2_1_0_CRY_25,
O => N_1814_RET_0I);
R1IN_4_ADD_2_1_0_AXB_26_Z7204: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(45),
LO => R1IN_4_ADD_2_1_0_AXB_26);
R1IN_4_ADD_2_1_0_CRY_24_Z7205: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_23,
S => R1IN_4_ADD_2_1_0_AXB_24,
LO => R1IN_4_ADD_2_1_0_CRY_24);
R1IN_4_ADD_2_1_0_S_25: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_25,
CI => R1IN_4_ADD_2_1_0_CRY_24,
O => N_1813_RET_0I);
R1IN_4_ADD_2_1_0_AXB_25_Z7207: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(44),
LO => R1IN_4_ADD_2_1_0_AXB_25);
R1IN_4_ADD_2_1_0_CRY_23_Z7208: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_22,
S => R1IN_4_ADD_2_1_0_AXB_23,
LO => R1IN_4_ADD_2_1_0_CRY_23);
R1IN_4_ADD_2_1_0_S_24: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_24,
CI => R1IN_4_ADD_2_1_0_CRY_23,
O => N_1812_RET_0I);
R1IN_4_ADD_2_1_0_AXB_24_Z7210: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(43),
LO => R1IN_4_ADD_2_1_0_AXB_24);
R1IN_4_ADD_2_1_0_CRY_22_Z7211: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_21,
S => R1IN_4_ADD_2_1_0_AXB_22,
LO => R1IN_4_ADD_2_1_0_CRY_22);
R1IN_4_ADD_2_1_0_S_23: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_23,
CI => R1IN_4_ADD_2_1_0_CRY_22,
O => N_1811_RET_0I);
R1IN_4_ADD_2_1_0_AXB_23_Z7213: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(42),
LO => R1IN_4_ADD_2_1_0_AXB_23);
R1IN_4_ADD_2_1_0_CRY_21_Z7214: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_20,
S => R1IN_4_ADD_2_1_0_AXB_21,
LO => R1IN_4_ADD_2_1_0_CRY_21);
R1IN_4_ADD_2_1_0_S_22: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_22,
CI => R1IN_4_ADD_2_1_0_CRY_21,
O => N_1810_RET_0I);
R1IN_4_ADD_2_1_0_AXB_22_Z7216: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(41),
LO => R1IN_4_ADD_2_1_0_AXB_22);
R1IN_4_ADD_2_1_0_CRY_20_Z7217: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_19,
S => R1IN_4_ADD_2_1_0_AXB_20,
LO => R1IN_4_ADD_2_1_0_CRY_20);
R1IN_4_ADD_2_1_0_S_21: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_21,
CI => R1IN_4_ADD_2_1_0_CRY_20,
O => N_1809_RET_0I);
R1IN_4_ADD_2_1_0_AXB_21_Z7219: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(40),
LO => R1IN_4_ADD_2_1_0_AXB_21);
R1IN_4_ADD_2_1_0_CRY_19_Z7220: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_18,
S => R1IN_4_ADD_2_1_0_AXB_19,
LO => R1IN_4_ADD_2_1_0_CRY_19);
R1IN_4_ADD_2_1_0_S_20: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_20,
CI => R1IN_4_ADD_2_1_0_CRY_19,
O => N_1808_RET_0I);
R1IN_4_ADD_2_1_0_AXB_20_Z7222: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(39),
LO => R1IN_4_ADD_2_1_0_AXB_20);
R1IN_4_ADD_2_1_0_CRY_18_Z7223: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_17,
S => R1IN_4_ADD_2_1_0_AXB_18,
LO => R1IN_4_ADD_2_1_0_CRY_18);
R1IN_4_ADD_2_1_0_S_19: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_19,
CI => R1IN_4_ADD_2_1_0_CRY_18,
O => N_1807_RET_0I);
R1IN_4_ADD_2_1_0_AXB_19_Z7225: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(38),
LO => R1IN_4_ADD_2_1_0_AXB_19);
R1IN_4_ADD_2_1_0_CRY_17_Z7226: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_16,
S => R1IN_4_ADD_2_1_0_AXB_17,
LO => R1IN_4_ADD_2_1_0_CRY_17);
R1IN_4_ADD_2_1_0_S_18: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_18,
CI => R1IN_4_ADD_2_1_0_CRY_17,
O => N_1806_RET_0I);
R1IN_4_ADD_2_1_0_AXB_18_Z7228: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(37),
LO => R1IN_4_ADD_2_1_0_AXB_18);
R1IN_4_ADD_2_1_0_CRY_16_Z7229: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_15,
S => R1IN_4_ADD_2_1_0_AXB_16,
LO => R1IN_4_ADD_2_1_0_CRY_16);
R1IN_4_ADD_2_1_0_S_17: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_17,
CI => R1IN_4_ADD_2_1_0_CRY_16,
O => N_1805_RET_0I);
R1IN_4_ADD_2_1_0_AXB_17_Z7231: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(36),
LO => R1IN_4_ADD_2_1_0_AXB_17);
R1IN_4_ADD_2_1_0_CRY_15_Z7232: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_14,
S => R1IN_4_ADD_2_1_0_AXB_15,
LO => R1IN_4_ADD_2_1_0_CRY_15);
R1IN_4_ADD_2_1_0_S_16: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_16,
CI => R1IN_4_ADD_2_1_0_CRY_15,
O => N_1804_RET_0I);
R1IN_4_ADD_2_1_0_AXB_16_Z7234: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(35),
LO => R1IN_4_ADD_2_1_0_AXB_16);
R1IN_4_ADD_2_1_0_CRY_14_Z7235: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_13,
S => R1IN_4_ADD_2_1_0_AXB_14,
LO => R1IN_4_ADD_2_1_0_CRY_14);
R1IN_4_ADD_2_1_0_S_15: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_15,
CI => R1IN_4_ADD_2_1_0_CRY_14,
O => N_1803_RET_0I);
R1IN_4_ADD_2_1_0_AXB_15_Z7237: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(34),
LO => R1IN_4_ADD_2_1_0_AXB_15);
R1IN_4_ADD_2_1_0_CRY_13_Z7238: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_12,
S => R1IN_4_ADD_2_1_0_AXB_13,
LO => R1IN_4_ADD_2_1_0_CRY_13);
R1IN_4_ADD_2_1_0_S_14: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_14,
CI => R1IN_4_ADD_2_1_0_CRY_13,
O => N_1802_RET_0I);
R1IN_4_ADD_2_1_0_AXB_14_Z7240: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(33),
LO => R1IN_4_ADD_2_1_0_AXB_14);
R1IN_4_ADD_2_1_0_CRY_12_Z7241: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_11,
S => R1IN_4_ADD_2_1_0_AXB_12,
LO => R1IN_4_ADD_2_1_0_CRY_12);
R1IN_4_ADD_2_1_0_S_13: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_13,
CI => R1IN_4_ADD_2_1_0_CRY_12,
O => N_1801_RET_0I);
R1IN_4_ADD_2_1_0_AXB_13_Z7243: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(32),
LO => R1IN_4_ADD_2_1_0_AXB_13);
R1IN_4_ADD_2_1_0_CRY_11_Z7244: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_10,
S => R1IN_4_ADD_2_1_0_AXB_11,
LO => R1IN_4_ADD_2_1_0_CRY_11);
R1IN_4_ADD_2_1_0_S_12: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_12,
CI => R1IN_4_ADD_2_1_0_CRY_11,
O => N_1800_RET_0I);
R1IN_4_ADD_2_1_0_AXB_12_Z7246: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(31),
LO => R1IN_4_ADD_2_1_0_AXB_12);
R1IN_4_ADD_2_1_0_CRY_10_Z7247: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_9,
S => R1IN_4_ADD_2_1_0_AXB_10,
LO => R1IN_4_ADD_2_1_0_CRY_10);
R1IN_4_ADD_2_1_0_S_11: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_11,
CI => R1IN_4_ADD_2_1_0_CRY_10,
O => N_1799_RET_0I);
R1IN_4_ADD_2_1_0_AXB_11_Z7249: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(30),
LO => R1IN_4_ADD_2_1_0_AXB_11);
R1IN_4_ADD_2_1_0_CRY_9_Z7250: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_0_CRY_8,
S => R1IN_4_ADD_2_1_0_AXB_9,
LO => R1IN_4_ADD_2_1_0_CRY_9);
R1IN_4_ADD_2_1_0_S_10: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_10,
CI => R1IN_4_ADD_2_1_0_CRY_9,
O => N_1798_RET_0I);
R1IN_4_ADD_2_1_0_AXB_10_Z7252: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(29),
LO => R1IN_4_ADD_2_1_0_AXB_10);
R1IN_4_ADD_2_1_0_CRY_8_Z7253: MUXCY_L port map (
DI => NN_10,
CI => R1IN_4_ADD_2_1_0_CRY_7,
S => R1IN_4_ADD_2_1_0_AXB_8,
LO => R1IN_4_ADD_2_1_0_CRY_8);
R1IN_4_ADD_2_1_0_S_9: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_9,
CI => R1IN_4_ADD_2_1_0_CRY_8,
O => N_1797_RET_0I);
R1IN_4_ADD_2_1_0_AXB_9_Z7255: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(28),
LO => R1IN_4_ADD_2_1_0_AXB_9);
R1IN_4_ADD_2_1_0_CRY_7_Z7256: MUXCY_L port map (
DI => NN_9,
CI => R1IN_4_ADD_2_1_0_CRY_6,
S => R1IN_4_ADD_2_1_0_AXB_7,
LO => R1IN_4_ADD_2_1_0_CRY_7);
R1IN_4_ADD_2_1_0_S_8: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_8,
CI => R1IN_4_ADD_2_1_0_CRY_7,
O => N_1796_RET_0I);
R1IN_4_ADD_2_1_0_AXB_8_Z7258: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(27),
I1 => NN_10,
LO => R1IN_4_ADD_2_1_0_AXB_8);
R1IN_4_ADD_2_1_0_CRY_6_Z7259: MUXCY_L port map (
DI => NN_8,
CI => R1IN_4_ADD_2_1_0_CRY_5,
S => R1IN_4_ADD_2_1_0_AXB_6,
LO => R1IN_4_ADD_2_1_0_CRY_6);
R1IN_4_ADD_2_1_0_S_7: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_7,
CI => R1IN_4_ADD_2_1_0_CRY_6,
O => N_1795_RET_0I);
R1IN_4_ADD_2_1_0_AXB_7_Z7261: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(26),
I1 => NN_9,
LO => R1IN_4_ADD_2_1_0_AXB_7);
R1IN_4_ADD_2_1_0_CRY_5_Z7262: MUXCY_L port map (
DI => NN_7,
CI => R1IN_4_ADD_2_1_0_CRY_4,
S => R1IN_4_ADD_2_1_0_AXB_5,
LO => R1IN_4_ADD_2_1_0_CRY_5);
R1IN_4_ADD_2_1_0_S_6: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_6,
CI => R1IN_4_ADD_2_1_0_CRY_5,
O => N_1794_RET_0I);
R1IN_4_ADD_2_1_0_AXB_6_Z7264: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(25),
I1 => NN_8,
LO => R1IN_4_ADD_2_1_0_AXB_6);
R1IN_4_ADD_2_1_0_CRY_4_Z7265: MUXCY_L port map (
DI => NN_6,
CI => R1IN_4_ADD_2_1_0_CRY_3,
S => R1IN_4_ADD_2_1_0_AXB_4,
LO => R1IN_4_ADD_2_1_0_CRY_4);
R1IN_4_ADD_2_1_0_S_5: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_5,
CI => R1IN_4_ADD_2_1_0_CRY_4,
O => N_1793_RET_0I);
R1IN_4_ADD_2_1_0_AXB_5_Z7267: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(24),
I1 => NN_7,
LO => R1IN_4_ADD_2_1_0_AXB_5);
R1IN_4_ADD_2_1_0_CRY_3_Z7268: MUXCY_L port map (
DI => NN_5,
CI => R1IN_4_ADD_2_1_0_CRY_2,
S => R1IN_4_ADD_2_1_0_AXB_3,
LO => R1IN_4_ADD_2_1_0_CRY_3);
R1IN_4_ADD_2_1_0_S_4: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_4,
CI => R1IN_4_ADD_2_1_0_CRY_3,
O => N_1792_RET_0I);
R1IN_4_ADD_2_1_0_AXB_4_Z7270: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(23),
I1 => NN_6,
LO => R1IN_4_ADD_2_1_0_AXB_4);
R1IN_4_ADD_2_1_0_CRY_2_Z7271: MUXCY_L port map (
DI => NN_4,
CI => R1IN_4_ADD_2_1_0_CRY_1,
S => R1IN_4_ADD_2_1_0_AXB_2,
LO => R1IN_4_ADD_2_1_0_CRY_2);
R1IN_4_ADD_2_1_0_S_3: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_3,
CI => R1IN_4_ADD_2_1_0_CRY_2,
O => N_1791_RET_0I);
R1IN_4_ADD_2_1_0_AXB_3_Z7273: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(22),
I1 => NN_5,
LO => R1IN_4_ADD_2_1_0_AXB_3);
R1IN_4_ADD_2_1_0_CRY_1_Z7274: MUXCY_L port map (
DI => NN_3,
CI => R1IN_4_ADD_2_1_0_CRY_0,
S => R1IN_4_ADD_2_1_0_AXB_1,
LO => R1IN_4_ADD_2_1_0_CRY_1);
R1IN_4_ADD_2_1_0_S_2: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_2,
CI => R1IN_4_ADD_2_1_0_CRY_1,
O => N_1790_RET_0I);
R1IN_4_ADD_2_1_0_AXB_2_Z7276: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(21),
I1 => NN_4,
LO => R1IN_4_ADD_2_1_0_AXB_2);
R1IN_4_ADD_2_1_0_CRY_0_Z7277: MUXCY_L port map (
DI => R1IN_4_ADD_2_1,
CI => NN_2,
S => R1IN_4_ADD_2_1_0_AXB_0_RET_0I,
LO => R1IN_4_ADD_2_1_0_CRY_0);
R1IN_4_ADD_2_1_0_S_1: XORCY port map (
LI => R1IN_4_ADD_2_1_0_AXB_1,
CI => R1IN_4_ADD_2_1_0_CRY_0,
O => N_1789_RET_0I);
R1IN_4_ADD_2_1_0_AXB_1_Z7279: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(20),
I1 => NN_3,
LO => R1IN_4_ADD_2_1_0_AXB_1);
R1IN_4_ADD_2_1_0_AXB_0: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(19),
I1 => R1IN_4_ADD_2_1,
O => R1IN_4_ADD_2_1_0_AXB_0_RET_0I);
\R1IN_ADD_2_MUX[0]\: LUT3
generic map(
INIT => X"72"
)
port map (
I0 => R1IN_ADD_2_0_CRY_52,
I1 => R1IN_ADD_2_1_0_AXB_0,
I2 => R1IN_ADD_2_1_AXB_0,
O => PRODUCT(70));
\R1IN_ADD_1_MUX[0]\: LUT3_L
generic map(
INIT => X"72"
)
port map (
I0 => R1IN_ADD_1_0_CRY_31,
I1 => R1IN_ADD_1_1_0_AXB_0,
I2 => R1IN_ADD_1_1_AXB_0,
LO => R1IN_ADD_1(32));
R1IN_ADD_1_0_AXB_17_Z7371: LUT4_L
generic map(
INIT => X"6996"
)
port map (
I0 => R1IN_2_1F(17),
I1 => R1IN_2_ADD_1,
I2 => R1IN_3_1F(17),
I3 => R1IN_3_ADD_1,
LO => R1IN_ADD_1_0_AXB_17);
R1IN_4_ADD_2_0_AXB_34_Z7372: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(17),
I1 => R1IN_4_ADD_1(34),
LO => R1IN_4_ADD_2_0_AXB_34);
\R1IN_4_ADD_2_MUX[1]\: LUT3_L
generic map(
INIT => X"CA"
)
port map (
I0 => R2_PIPE_104_RET_1060,
I1 => R2_PIPE_104_RET_124,
I2 => R1IN_4_ADD_2_0_CRY_35_RETO_32,
LO => R1IN_4(54));
\R1IN_ADD_2_MUX[51]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_51,
I1 => R1IN_ADD_2_1_0_S_51,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(121));
\R1IN_ADD_2_MUX[50]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_50,
I1 => R1IN_ADD_2_1_0_S_50,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(120));
\R1IN_ADD_2_MUX[49]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_49,
I1 => R1IN_ADD_2_1_0_S_49,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(119));
\R1IN_ADD_2_MUX[48]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_48,
I1 => R1IN_ADD_2_1_0_S_48,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(118));
\R1IN_ADD_2_MUX[47]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_47,
I1 => R1IN_ADD_2_1_0_S_47,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(117));
\R1IN_ADD_2_MUX[46]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_46,
I1 => R1IN_ADD_2_1_0_S_46,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(116));
\R1IN_ADD_2_MUX[45]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_45,
I1 => R1IN_ADD_2_1_0_S_45,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(115));
\R1IN_ADD_2_MUX[44]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_44,
I1 => R1IN_ADD_2_1_0_S_44,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(114));
\R1IN_ADD_2_MUX[43]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_43,
I1 => R1IN_ADD_2_1_0_S_43,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(113));
\R1IN_ADD_2_MUX[42]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_42,
I1 => R1IN_ADD_2_1_0_S_42,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(112));
\R1IN_ADD_2_MUX[41]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_41,
I1 => R1IN_ADD_2_1_0_S_41,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(111));
\R1IN_ADD_2_MUX[40]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_40,
I1 => R1IN_ADD_2_1_0_S_40,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(110));
\R1IN_ADD_2_MUX[39]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_39,
I1 => R1IN_ADD_2_1_0_S_39,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(109));
\R1IN_ADD_2_MUX[38]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_38,
I1 => R1IN_ADD_2_1_0_S_38,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(108));
\R1IN_ADD_2_MUX[37]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_37,
I1 => R1IN_ADD_2_1_0_S_37,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(107));
\R1IN_ADD_2_MUX[36]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_36,
I1 => R1IN_ADD_2_1_0_S_36,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(106));
\R1IN_ADD_2_MUX[35]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_35,
I1 => R1IN_ADD_2_1_0_S_35,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(105));
\R1IN_ADD_2_MUX[34]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_34,
I1 => R1IN_ADD_2_1_0_S_34,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(104));
\R1IN_ADD_2_MUX[33]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_33,
I1 => R1IN_ADD_2_1_0_S_33,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(103));
\R1IN_ADD_2_MUX[32]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_32,
I1 => R1IN_ADD_2_1_0_S_32,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(102));
\R1IN_ADD_2_MUX[31]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_31,
I1 => R1IN_ADD_2_1_0_S_31,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(101));
\R1IN_ADD_2_MUX[30]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_30,
I1 => R1IN_ADD_2_1_0_S_30,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(100));
\R1IN_ADD_2_MUX[29]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_29,
I1 => R1IN_ADD_2_1_0_S_29,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(99));
\R1IN_ADD_2_MUX[28]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_28,
I1 => R1IN_ADD_2_1_0_S_28,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(98));
\R1IN_ADD_2_MUX[27]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_27,
I1 => R1IN_ADD_2_1_0_S_27,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(97));
\R1IN_ADD_2_MUX[26]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_26,
I1 => R1IN_ADD_2_1_0_S_26,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(96));
\R1IN_ADD_2_MUX[25]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_25,
I1 => R1IN_ADD_2_1_0_S_25,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(95));
\R1IN_ADD_2_MUX[24]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_24,
I1 => R1IN_ADD_2_1_0_S_24,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(94));
\R1IN_ADD_2_MUX[23]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_23,
I1 => R1IN_ADD_2_1_0_S_23,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(93));
\R1IN_ADD_2_MUX[22]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_22,
I1 => R1IN_ADD_2_1_0_S_22,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(92));
\R1IN_ADD_2_MUX[21]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_21,
I1 => R1IN_ADD_2_1_0_S_21,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(91));
\R1IN_ADD_2_MUX[20]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_20,
I1 => R1IN_ADD_2_1_0_S_20,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(90));
\R1IN_ADD_2_MUX[19]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_19,
I1 => R1IN_ADD_2_1_0_S_19,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(89));
\R1IN_ADD_2_MUX[18]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_18,
I1 => R1IN_ADD_2_1_0_S_18,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(88));
\R1IN_ADD_2_MUX[17]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_17,
I1 => R1IN_ADD_2_1_0_S_17,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(87));
\R1IN_ADD_2_MUX[16]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_16,
I1 => R1IN_ADD_2_1_0_S_16,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(86));
\R1IN_ADD_2_MUX[15]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_15,
I1 => R1IN_ADD_2_1_0_S_15,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(85));
\R1IN_ADD_2_MUX[14]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_14,
I1 => R1IN_ADD_2_1_0_S_14,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(84));
\R1IN_ADD_2_MUX[13]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_13,
I1 => R1IN_ADD_2_1_0_S_13,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(83));
\R1IN_ADD_2_MUX[12]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_12,
I1 => R1IN_ADD_2_1_0_S_12,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(82));
\R1IN_ADD_2_MUX[11]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_11,
I1 => R1IN_ADD_2_1_0_S_11,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(81));
\R1IN_ADD_2_MUX[10]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_10,
I1 => R1IN_ADD_2_1_0_S_10,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(80));
\R1IN_ADD_2_MUX[9]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_9,
I1 => R1IN_ADD_2_1_0_S_9,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(79));
\R1IN_ADD_2_MUX[8]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_8,
I1 => R1IN_ADD_2_1_0_S_8,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(78));
\R1IN_ADD_2_MUX[7]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_7,
I1 => R1IN_ADD_2_1_0_S_7,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(77));
\R1IN_ADD_2_MUX[6]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_6,
I1 => R1IN_ADD_2_1_0_S_6,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(76));
\R1IN_ADD_2_MUX[5]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_5,
I1 => R1IN_ADD_2_1_0_S_5,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(75));
\R1IN_ADD_2_MUX[4]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_4,
I1 => R1IN_ADD_2_1_0_S_4,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(74));
\R1IN_ADD_2_MUX[3]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_3,
I1 => R1IN_ADD_2_1_0_S_3,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(73));
\R1IN_ADD_2_MUX[2]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_2,
I1 => R1IN_ADD_2_1_0_S_2,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(72));
\R1IN_ADD_2_MUX[1]\: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => R1IN_ADD_2_1_S_1,
I1 => R1IN_ADD_2_1_0_S_1,
I2 => R1IN_ADD_2_0_CRY_52,
O => PRODUCT(71));
R1IN_4_ADD_1_AXB_0: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_3F(0),
I1 => NN_12,
O => R1IN_4_ADD_2_0);
R1IN_4_4_ADD_2_AXB_36_Z7426: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4_4F(19),
O => R1IN_4_4_ADD_2_AXB_36);
R1IN_4_4_ADD_2_AXB_0: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4_ADD_1F(0),
I1 => R1IN_4_4_ADD_2,
O => R1IN_4_4(17));
R1IN_2_ADD_1_AXB_43_Z7428: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_2_2F(43),
O => R1IN_2_ADD_1_AXB_43);
R1IN_3_ADD_1_AXB_43_Z7429: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_3_2F(43),
O => R1IN_3_ADD_1_AXB_43);
R1IN_3_ADD_1_AXB_0: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_3_1F(17),
I1 => R1IN_3_ADD_1,
O => R1IN_3(17));
R1IN_ADD_1_1_0_AXB_28_Z7431: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(60),
I1 => R1IN_3(60),
LO => R1IN_ADD_1_1_0_AXB_28);
R1IN_ADD_1_1_0_AXB_27_Z7432: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(59),
I1 => R1IN_3(59),
LO => R1IN_ADD_1_1_0_AXB_27);
R1IN_ADD_1_1_0_AXB_26_Z7433: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(58),
I1 => R1IN_3(58),
LO => R1IN_ADD_1_1_0_AXB_26);
R1IN_ADD_1_1_0_AXB_25_Z7434: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(57),
I1 => R1IN_3(57),
LO => R1IN_ADD_1_1_0_AXB_25);
R1IN_ADD_1_1_0_AXB_24_Z7435: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(56),
I1 => R1IN_3(56),
LO => R1IN_ADD_1_1_0_AXB_24);
R1IN_ADD_1_1_0_AXB_23_Z7436: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(55),
I1 => R1IN_3(55),
LO => R1IN_ADD_1_1_0_AXB_23);
R1IN_ADD_1_1_0_AXB_22_Z7437: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(54),
I1 => R1IN_3(54),
LO => R1IN_ADD_1_1_0_AXB_22);
R1IN_ADD_1_1_0_AXB_21_Z7438: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(53),
I1 => R1IN_3(53),
LO => R1IN_ADD_1_1_0_AXB_21);
R1IN_ADD_1_1_0_AXB_20_Z7439: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(52),
I1 => R1IN_3(52),
LO => R1IN_ADD_1_1_0_AXB_20);
R1IN_ADD_1_1_0_AXB_19_Z7440: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(51),
I1 => R1IN_3(51),
LO => R1IN_ADD_1_1_0_AXB_19);
R1IN_ADD_1_1_0_AXB_18_Z7441: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(50),
I1 => R1IN_3(50),
LO => R1IN_ADD_1_1_0_AXB_18);
R1IN_ADD_1_1_0_AXB_17_Z7442: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(49),
I1 => R1IN_3(49),
LO => R1IN_ADD_1_1_0_AXB_17);
R1IN_ADD_1_1_0_AXB_16_Z7443: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(48),
I1 => R1IN_3(48),
LO => R1IN_ADD_1_1_0_AXB_16);
R1IN_ADD_1_1_0_AXB_15_Z7444: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(47),
I1 => R1IN_3(47),
LO => R1IN_ADD_1_1_0_AXB_15);
R1IN_ADD_1_1_0_AXB_14_Z7445: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(46),
I1 => R1IN_3(46),
LO => R1IN_ADD_1_1_0_AXB_14);
R1IN_ADD_1_1_0_AXB_13_Z7446: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(45),
I1 => R1IN_3(45),
LO => R1IN_ADD_1_1_0_AXB_13);
R1IN_ADD_1_1_0_AXB_12_Z7447: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(44),
I1 => R1IN_3(44),
LO => R1IN_ADD_1_1_0_AXB_12);
R1IN_ADD_1_1_0_AXB_11_Z7448: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(43),
I1 => R1IN_3(43),
LO => R1IN_ADD_1_1_0_AXB_11);
R1IN_ADD_1_1_0_AXB_10_Z7449: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(42),
I1 => R1IN_3(42),
LO => R1IN_ADD_1_1_0_AXB_10);
R1IN_ADD_1_1_0_AXB_9_Z7450: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(41),
I1 => R1IN_3(41),
LO => R1IN_ADD_1_1_0_AXB_9);
R1IN_ADD_1_1_0_AXB_8_Z7451: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(40),
I1 => R1IN_3(40),
LO => R1IN_ADD_1_1_0_AXB_8);
R1IN_ADD_1_1_0_AXB_7_Z7452: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(39),
I1 => R1IN_3(39),
LO => R1IN_ADD_1_1_0_AXB_7);
R1IN_ADD_1_1_0_AXB_6_Z7453: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(38),
I1 => R1IN_3(38),
LO => R1IN_ADD_1_1_0_AXB_6);
R1IN_ADD_1_1_0_AXB_5_Z7454: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(37),
I1 => R1IN_3(37),
LO => R1IN_ADD_1_1_0_AXB_5);
R1IN_ADD_1_1_0_AXB_4_Z7455: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(36),
I1 => R1IN_3(36),
LO => R1IN_ADD_1_1_0_AXB_4);
R1IN_ADD_1_1_0_AXB_3_Z7456: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(35),
I1 => R1IN_3(35),
LO => R1IN_ADD_1_1_0_AXB_3);
R1IN_ADD_1_1_0_AXB_2_Z7457: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(34),
I1 => R1IN_3(34),
LO => R1IN_ADD_1_1_0_AXB_2);
R1IN_ADD_1_1_0_AXB_1_Z7458: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(33),
I1 => R1IN_3(33),
LO => R1IN_ADD_1_1_0_AXB_1);
R1IN_ADD_1_1_0_AXB_0_Z7459: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(32),
I1 => R1IN_3(32),
O => R1IN_ADD_1_1_0_AXB_0);
R1IN_ADD_1_1_AXB_28_Z7460: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(60),
I1 => R1IN_3(60),
LO => R1IN_ADD_1_1_AXB_28);
R1IN_ADD_1_1_AXB_27_Z7461: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(59),
I1 => R1IN_3(59),
LO => R1IN_ADD_1_1_AXB_27);
R1IN_ADD_1_1_AXB_26_Z7462: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(58),
I1 => R1IN_3(58),
LO => R1IN_ADD_1_1_AXB_26);
R1IN_ADD_1_1_AXB_25_Z7463: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(57),
I1 => R1IN_3(57),
LO => R1IN_ADD_1_1_AXB_25);
R1IN_ADD_1_1_AXB_24_Z7464: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(56),
I1 => R1IN_3(56),
LO => R1IN_ADD_1_1_AXB_24);
R1IN_ADD_1_1_AXB_23_Z7465: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(55),
I1 => R1IN_3(55),
LO => R1IN_ADD_1_1_AXB_23);
R1IN_ADD_1_1_AXB_22_Z7466: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(54),
I1 => R1IN_3(54),
LO => R1IN_ADD_1_1_AXB_22);
R1IN_ADD_1_1_AXB_21_Z7467: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(53),
I1 => R1IN_3(53),
LO => R1IN_ADD_1_1_AXB_21);
R1IN_ADD_1_1_AXB_20_Z7468: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(52),
I1 => R1IN_3(52),
LO => R1IN_ADD_1_1_AXB_20);
R1IN_ADD_1_1_AXB_19_Z7469: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(51),
I1 => R1IN_3(51),
LO => R1IN_ADD_1_1_AXB_19);
R1IN_ADD_1_1_AXB_18_Z7470: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(50),
I1 => R1IN_3(50),
LO => R1IN_ADD_1_1_AXB_18);
R1IN_ADD_1_1_AXB_17_Z7471: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(49),
I1 => R1IN_3(49),
LO => R1IN_ADD_1_1_AXB_17);
R1IN_ADD_1_1_AXB_16_Z7472: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(48),
I1 => R1IN_3(48),
LO => R1IN_ADD_1_1_AXB_16);
R1IN_ADD_1_1_AXB_15_Z7473: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(47),
I1 => R1IN_3(47),
LO => R1IN_ADD_1_1_AXB_15);
R1IN_ADD_1_1_AXB_14_Z7474: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(46),
I1 => R1IN_3(46),
LO => R1IN_ADD_1_1_AXB_14);
R1IN_ADD_1_1_AXB_13_Z7475: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(45),
I1 => R1IN_3(45),
LO => R1IN_ADD_1_1_AXB_13);
R1IN_ADD_1_1_AXB_12_Z7476: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(44),
I1 => R1IN_3(44),
LO => R1IN_ADD_1_1_AXB_12);
R1IN_ADD_1_1_AXB_11_Z7477: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(43),
I1 => R1IN_3(43),
LO => R1IN_ADD_1_1_AXB_11);
R1IN_ADD_1_1_AXB_10_Z7478: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(42),
I1 => R1IN_3(42),
LO => R1IN_ADD_1_1_AXB_10);
R1IN_ADD_1_1_AXB_9_Z7479: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(41),
I1 => R1IN_3(41),
LO => R1IN_ADD_1_1_AXB_9);
R1IN_ADD_1_1_AXB_8_Z7480: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(40),
I1 => R1IN_3(40),
LO => R1IN_ADD_1_1_AXB_8);
R1IN_ADD_1_1_AXB_7_Z7481: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(39),
I1 => R1IN_3(39),
LO => R1IN_ADD_1_1_AXB_7);
R1IN_ADD_1_1_AXB_6_Z7482: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(38),
I1 => R1IN_3(38),
LO => R1IN_ADD_1_1_AXB_6);
R1IN_ADD_1_1_AXB_5_Z7483: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(37),
I1 => R1IN_3(37),
LO => R1IN_ADD_1_1_AXB_5);
R1IN_ADD_1_1_AXB_4_Z7484: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(36),
I1 => R1IN_3(36),
LO => R1IN_ADD_1_1_AXB_4);
R1IN_ADD_1_1_AXB_3_Z7485: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(35),
I1 => R1IN_3(35),
LO => R1IN_ADD_1_1_AXB_3);
R1IN_ADD_1_1_AXB_2_Z7486: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(34),
I1 => R1IN_3(34),
LO => R1IN_ADD_1_1_AXB_2);
R1IN_ADD_1_1_AXB_1_Z7487: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(33),
I1 => R1IN_3(33),
LO => R1IN_ADD_1_1_AXB_1);
R1IN_ADD_1_1_AXB_0_Z7488: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(32),
I1 => R1IN_3(32),
O => R1IN_ADD_1_1_AXB_0);
R1IN_ADD_1_0_AXB_31_Z7489: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(31),
I1 => R1IN_3(31),
LO => R1IN_ADD_1_0_AXB_31);
R1IN_ADD_1_0_AXB_30_Z7490: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(30),
I1 => R1IN_3(30),
LO => R1IN_ADD_1_0_AXB_30);
R1IN_ADD_1_0_AXB_29_Z7491: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(29),
I1 => R1IN_3(29),
LO => R1IN_ADD_1_0_AXB_29);
R1IN_ADD_1_0_AXB_28_Z7492: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(28),
I1 => R1IN_3(28),
LO => R1IN_ADD_1_0_AXB_28);
R1IN_ADD_1_0_AXB_27_Z7493: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(27),
I1 => R1IN_3(27),
LO => R1IN_ADD_1_0_AXB_27);
R1IN_ADD_1_0_AXB_26_Z7494: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(26),
I1 => R1IN_3(26),
LO => R1IN_ADD_1_0_AXB_26);
R1IN_ADD_1_0_AXB_25_Z7495: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(25),
I1 => R1IN_3(25),
LO => R1IN_ADD_1_0_AXB_25);
R1IN_ADD_1_0_AXB_24_Z7496: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(24),
I1 => R1IN_3(24),
LO => R1IN_ADD_1_0_AXB_24);
R1IN_ADD_1_0_AXB_23_Z7497: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(23),
I1 => R1IN_3(23),
LO => R1IN_ADD_1_0_AXB_23);
R1IN_ADD_1_0_AXB_22_Z7498: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(22),
I1 => R1IN_3(22),
LO => R1IN_ADD_1_0_AXB_22);
R1IN_ADD_1_0_AXB_21_Z7499: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(21),
I1 => R1IN_3(21),
LO => R1IN_ADD_1_0_AXB_21);
R1IN_ADD_1_0_AXB_20_Z7500: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(20),
I1 => R1IN_3(20),
LO => R1IN_ADD_1_0_AXB_20);
R1IN_ADD_1_0_AXB_19_Z7501: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(19),
I1 => R1IN_3(19),
LO => R1IN_ADD_1_0_AXB_19);
R1IN_ADD_1_0_AXB_18_Z7502: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2(18),
I1 => R1IN_3(18),
LO => R1IN_ADD_1_0_AXB_18);
R1IN_ADD_1_0_AXB_16_Z7503: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F(16),
I1 => R1IN_3F(16),
LO => R1IN_ADD_1_0_AXB_16);
R1IN_ADD_1_0_AXB_15_Z7504: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F(15),
I1 => R1IN_3F(15),
LO => R1IN_ADD_1_0_AXB_15);
R1IN_ADD_1_0_AXB_14_Z7505: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F(14),
I1 => R1IN_3F(14),
LO => R1IN_ADD_1_0_AXB_14);
R1IN_ADD_1_0_AXB_13_Z7506: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F(13),
I1 => R1IN_3F(13),
LO => R1IN_ADD_1_0_AXB_13);
R1IN_ADD_1_0_AXB_12_Z7507: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F(12),
I1 => R1IN_3F(12),
LO => R1IN_ADD_1_0_AXB_12);
R1IN_ADD_1_0_AXB_11_Z7508: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F(11),
I1 => R1IN_3F(11),
LO => R1IN_ADD_1_0_AXB_11);
R1IN_ADD_1_0_AXB_10_Z7509: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F(10),
I1 => R1IN_3F(10),
LO => R1IN_ADD_1_0_AXB_10);
R1IN_ADD_1_0_AXB_9_Z7510: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F(9),
I1 => R1IN_3F(9),
LO => R1IN_ADD_1_0_AXB_9);
R1IN_ADD_1_0_AXB_8_Z7511: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F(8),
I1 => R1IN_3F(8),
LO => R1IN_ADD_1_0_AXB_8);
R1IN_ADD_1_0_AXB_7_Z7512: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F(7),
I1 => R1IN_3F(7),
LO => R1IN_ADD_1_0_AXB_7);
R1IN_ADD_1_0_AXB_6_Z7513: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F(6),
I1 => R1IN_3F(6),
LO => R1IN_ADD_1_0_AXB_6);
R1IN_ADD_1_0_AXB_5_Z7514: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F(5),
I1 => R1IN_3F(5),
LO => R1IN_ADD_1_0_AXB_5);
R1IN_ADD_1_0_AXB_4_Z7515: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F(4),
I1 => R1IN_3F(4),
LO => R1IN_ADD_1_0_AXB_4);
R1IN_ADD_1_0_AXB_3_Z7516: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F(3),
I1 => R1IN_3F(3),
LO => R1IN_ADD_1_0_AXB_3);
R1IN_ADD_1_0_AXB_2_Z7517: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F(2),
I1 => R1IN_3F(2),
LO => R1IN_ADD_1_0_AXB_2);
R1IN_ADD_1_0_AXB_1_Z7518: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F(1),
I1 => R1IN_3F(1),
LO => R1IN_ADD_1_0_AXB_1);
R1IN_ADD_1_0_AXB_0: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_2F(0),
I1 => R1IN_3F(0),
O => R1IN_ADD_1(0));
R1IN_ADD_2_0_AXB_0: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_ADD_1FF(0),
I1 => R1IN_ADD_2_0,
O => NN_11);
R1IN_4_ADD_2_1_AXB_34_Z7521: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(53),
LO => R1IN_4_ADD_2_1_AXB_34);
R1IN_4_ADD_2_1_AXB_33_Z7522: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(52),
LO => R1IN_4_ADD_2_1_AXB_33);
R1IN_4_ADD_2_1_AXB_32_Z7523: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(51),
LO => R1IN_4_ADD_2_1_AXB_32);
R1IN_4_ADD_2_1_AXB_31_Z7524: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(50),
LO => R1IN_4_ADD_2_1_AXB_31);
R1IN_4_ADD_2_1_AXB_30_Z7525: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(49),
LO => R1IN_4_ADD_2_1_AXB_30);
R1IN_4_ADD_2_1_AXB_29_Z7526: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(48),
LO => R1IN_4_ADD_2_1_AXB_29);
R1IN_4_ADD_2_1_AXB_28_Z7527: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(47),
LO => R1IN_4_ADD_2_1_AXB_28);
R1IN_4_ADD_2_1_AXB_27_Z7528: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(46),
LO => R1IN_4_ADD_2_1_AXB_27);
R1IN_4_ADD_2_1_AXB_26_Z7529: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(45),
LO => R1IN_4_ADD_2_1_AXB_26);
R1IN_4_ADD_2_1_AXB_25_Z7530: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(44),
LO => R1IN_4_ADD_2_1_AXB_25);
R1IN_4_ADD_2_1_AXB_24_Z7531: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(43),
LO => R1IN_4_ADD_2_1_AXB_24);
R1IN_4_ADD_2_1_AXB_23_Z7532: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(42),
LO => R1IN_4_ADD_2_1_AXB_23);
R1IN_4_ADD_2_1_AXB_22_Z7533: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(41),
LO => R1IN_4_ADD_2_1_AXB_22);
R1IN_4_ADD_2_1_AXB_21_Z7534: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(40),
LO => R1IN_4_ADD_2_1_AXB_21);
R1IN_4_ADD_2_1_AXB_20_Z7535: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(39),
LO => R1IN_4_ADD_2_1_AXB_20);
R1IN_4_ADD_2_1_AXB_19_Z7536: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(38),
LO => R1IN_4_ADD_2_1_AXB_19);
R1IN_4_ADD_2_1_AXB_18_Z7537: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(37),
LO => R1IN_4_ADD_2_1_AXB_18);
R1IN_4_ADD_2_1_AXB_17_Z7538: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(36),
LO => R1IN_4_ADD_2_1_AXB_17);
R1IN_4_ADD_2_1_AXB_16_Z7539: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(35),
LO => R1IN_4_ADD_2_1_AXB_16);
R1IN_4_ADD_2_1_AXB_15_Z7540: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(34),
LO => R1IN_4_ADD_2_1_AXB_15);
R1IN_4_ADD_2_1_AXB_14_Z7541: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(33),
LO => R1IN_4_ADD_2_1_AXB_14);
R1IN_4_ADD_2_1_AXB_13_Z7542: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(32),
LO => R1IN_4_ADD_2_1_AXB_13);
R1IN_4_ADD_2_1_AXB_12_Z7543: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(31),
LO => R1IN_4_ADD_2_1_AXB_12);
R1IN_4_ADD_2_1_AXB_11_Z7544: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(30),
LO => R1IN_4_ADD_2_1_AXB_11);
R1IN_4_ADD_2_1_AXB_10_Z7545: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(29),
LO => R1IN_4_ADD_2_1_AXB_10);
R1IN_4_ADD_2_1_AXB_9_Z7546: LUT1_L
generic map(
INIT => X"2"
)
port map (
I0 => R1IN_4_4(28),
LO => R1IN_4_ADD_2_1_AXB_9);
R1IN_4_ADD_2_1_AXB_8_Z7547: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(27),
I1 => NN_10,
LO => R1IN_4_ADD_2_1_AXB_8);
R1IN_4_ADD_2_1_AXB_7_Z7548: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(26),
I1 => NN_9,
LO => R1IN_4_ADD_2_1_AXB_7);
R1IN_4_ADD_2_1_AXB_6_Z7549: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(25),
I1 => NN_8,
LO => R1IN_4_ADD_2_1_AXB_6);
R1IN_4_ADD_2_1_AXB_5_Z7550: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(24),
I1 => NN_7,
LO => R1IN_4_ADD_2_1_AXB_5);
R1IN_4_ADD_2_1_AXB_4_Z7551: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(23),
I1 => NN_6,
LO => R1IN_4_ADD_2_1_AXB_4);
R1IN_4_ADD_2_1_AXB_3_Z7552: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(22),
I1 => NN_5,
LO => R1IN_4_ADD_2_1_AXB_3);
R1IN_4_ADD_2_1_AXB_2_Z7553: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(21),
I1 => NN_4,
LO => R1IN_4_ADD_2_1_AXB_2);
R1IN_4_ADD_2_1_AXB_1_Z7554: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(20),
I1 => NN_3,
LO => R1IN_4_ADD_2_1_AXB_1);
R1IN_4_ADD_2_1_AXB_0_Z7555: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(19),
I1 => R1IN_4_ADD_2_1,
O => R1IN_4_ADD_2_1_AXB_0_RETI);
R1IN_4_ADD_2_0_AXB_35_Z7556: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4(18),
I1 => R1IN_4_ADD_1(35),
LO => R1IN_4_ADD_2_0_AXB_35);
R1IN_4_ADD_2_0_AXB_33_Z7557: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F(16),
I1 => R1IN_4_ADD_1(33),
LO => R1IN_4_ADD_2_0_AXB_33);
R1IN_4_ADD_2_0_AXB_32_Z7558: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F(15),
I1 => R1IN_4_ADD_1(32),
LO => R1IN_4_ADD_2_0_AXB_32);
R1IN_4_ADD_2_0_AXB_31_Z7559: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F(14),
I1 => R1IN_4_ADD_1(31),
LO => R1IN_4_ADD_2_0_AXB_31);
R1IN_4_ADD_2_0_AXB_30_Z7560: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F(13),
I1 => R1IN_4_ADD_1(30),
LO => R1IN_4_ADD_2_0_AXB_30);
R1IN_4_ADD_2_0_AXB_29_Z7561: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F(12),
I1 => R1IN_4_ADD_1(29),
LO => R1IN_4_ADD_2_0_AXB_29);
R1IN_4_ADD_2_0_AXB_28_Z7562: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F(11),
I1 => R1IN_4_ADD_1(28),
LO => R1IN_4_ADD_2_0_AXB_28);
R1IN_4_ADD_2_0_AXB_27_Z7563: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F(10),
I1 => R1IN_4_ADD_1(27),
LO => R1IN_4_ADD_2_0_AXB_27);
R1IN_4_ADD_2_0_AXB_26_Z7564: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F(9),
I1 => R1IN_4_ADD_1(26),
LO => R1IN_4_ADD_2_0_AXB_26);
R1IN_4_ADD_2_0_AXB_25_Z7565: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F(8),
I1 => R1IN_4_ADD_1(25),
LO => R1IN_4_ADD_2_0_AXB_25);
R1IN_4_ADD_2_0_AXB_24_Z7566: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F(7),
I1 => R1IN_4_ADD_1(24),
LO => R1IN_4_ADD_2_0_AXB_24);
R1IN_4_ADD_2_0_AXB_23_Z7567: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F(6),
I1 => R1IN_4_ADD_1(23),
LO => R1IN_4_ADD_2_0_AXB_23);
R1IN_4_ADD_2_0_AXB_22_Z7568: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F(5),
I1 => R1IN_4_ADD_1(22),
LO => R1IN_4_ADD_2_0_AXB_22);
R1IN_4_ADD_2_0_AXB_21_Z7569: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F(4),
I1 => R1IN_4_ADD_1(21),
LO => R1IN_4_ADD_2_0_AXB_21);
R1IN_4_ADD_2_0_AXB_20_Z7570: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F(3),
I1 => R1IN_4_ADD_1(20),
LO => R1IN_4_ADD_2_0_AXB_20);
R1IN_4_ADD_2_0_AXB_19_Z7571: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F(2),
I1 => R1IN_4_ADD_1(19),
LO => R1IN_4_ADD_2_0_AXB_19);
R1IN_4_ADD_2_0_AXB_18_Z7572: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F(1),
I1 => R1IN_4_ADD_1(18),
LO => R1IN_4_ADD_2_0_AXB_18);
R1IN_4_ADD_2_0_AXB_17_Z7573: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_4F(0),
I1 => R1IN_4_ADD_1(17),
LO => R1IN_4_ADD_2_0_AXB_17);
R1IN_4_ADD_2_0_AXB_16_Z7574: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F(33),
I1 => R1IN_4_ADD_1(16),
LO => R1IN_4_ADD_2_0_AXB_16);
R1IN_4_ADD_2_0_AXB_15_Z7575: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F(32),
I1 => R1IN_4_ADD_1(15),
LO => R1IN_4_ADD_2_0_AXB_15);
R1IN_4_ADD_2_0_AXB_14_Z7576: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F(31),
I1 => R1IN_4_ADD_1(14),
LO => R1IN_4_ADD_2_0_AXB_14);
R1IN_4_ADD_2_0_AXB_13_Z7577: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F(30),
I1 => R1IN_4_ADD_1(13),
LO => R1IN_4_ADD_2_0_AXB_13);
R1IN_4_ADD_2_0_AXB_12_Z7578: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F(29),
I1 => R1IN_4_ADD_1(12),
LO => R1IN_4_ADD_2_0_AXB_12);
R1IN_4_ADD_2_0_AXB_11_Z7579: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F(28),
I1 => R1IN_4_ADD_1(11),
LO => R1IN_4_ADD_2_0_AXB_11);
R1IN_4_ADD_2_0_AXB_10_Z7580: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F(27),
I1 => R1IN_4_ADD_1(10),
LO => R1IN_4_ADD_2_0_AXB_10);
R1IN_4_ADD_2_0_AXB_9_Z7581: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F(26),
I1 => R1IN_4_ADD_1(9),
LO => R1IN_4_ADD_2_0_AXB_9);
R1IN_4_ADD_2_0_AXB_8_Z7582: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F(25),
I1 => R1IN_4_ADD_1(8),
LO => R1IN_4_ADD_2_0_AXB_8);
R1IN_4_ADD_2_0_AXB_7_Z7583: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F(24),
I1 => R1IN_4_ADD_1(7),
LO => R1IN_4_ADD_2_0_AXB_7);
R1IN_4_ADD_2_0_AXB_6_Z7584: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F(23),
I1 => R1IN_4_ADD_1(6),
LO => R1IN_4_ADD_2_0_AXB_6);
R1IN_4_ADD_2_0_AXB_5_Z7585: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F(22),
I1 => R1IN_4_ADD_1(5),
LO => R1IN_4_ADD_2_0_AXB_5);
R1IN_4_ADD_2_0_AXB_4_Z7586: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F(21),
I1 => R1IN_4_ADD_1(4),
LO => R1IN_4_ADD_2_0_AXB_4);
R1IN_4_ADD_2_0_AXB_3_Z7587: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F(20),
I1 => R1IN_4_ADD_1(3),
LO => R1IN_4_ADD_2_0_AXB_3);
R1IN_4_ADD_2_0_AXB_2_Z7588: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F(19),
I1 => R1IN_4_ADD_1(2),
LO => R1IN_4_ADD_2_0_AXB_2);
R1IN_4_ADD_2_0_AXB_1_Z7589: LUT2_L
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F(18),
I1 => R1IN_4_ADD_1(1),
LO => R1IN_4_ADD_2_0_AXB_1);
R1IN_4_ADD_2_0_AXB_0: LUT2
generic map(
INIT => X"6"
)
port map (
I0 => R1IN_4_1F(17),
I1 => R1IN_4_ADD_2_0,
O => R1IN_4(17));
R1IN_4_ADD_1_S_43: XORCY port map (
LI => R1IN_4_ADD_1_AXB_43,
CI => R1IN_4_ADD_1_CRY_42,
O => NN_9);
R1IN_4_ADD_1_CRY_43: MUXCY port map (
DI => R1IN_4_2F(43),
CI => R1IN_4_ADD_1_CRY_42,
S => R1IN_4_ADD_1_AXB_43,
O => NN_10);
R1IN_4_ADD_1_S_42: XORCY port map (
LI => R1IN_4_ADD_1_AXB_42,
CI => R1IN_4_ADD_1_CRY_41,
O => NN_8);
R1IN_4_ADD_1_CRY_42_Z7594: MUXCY_L port map (
DI => R1IN_4_2F(42),
CI => R1IN_4_ADD_1_CRY_41,
S => R1IN_4_ADD_1_AXB_42,
LO => R1IN_4_ADD_1_CRY_42);
R1IN_4_ADD_1_S_41: XORCY port map (
LI => R1IN_4_ADD_1_AXB_41,
CI => R1IN_4_ADD_1_CRY_40,
O => NN_7);
R1IN_4_ADD_1_CRY_41_Z7596: MUXCY_L port map (
DI => R1IN_4_2F(41),
CI => R1IN_4_ADD_1_CRY_40,
S => R1IN_4_ADD_1_AXB_41,
LO => R1IN_4_ADD_1_CRY_41);
R1IN_4_ADD_1_S_40: XORCY port map (
LI => R1IN_4_ADD_1_AXB_40,
CI => R1IN_4_ADD_1_CRY_39,
O => NN_6);
R1IN_4_ADD_1_CRY_40_Z7598: MUXCY_L port map (
DI => R1IN_4_2F(40),
CI => R1IN_4_ADD_1_CRY_39,
S => R1IN_4_ADD_1_AXB_40,
LO => R1IN_4_ADD_1_CRY_40);
R1IN_4_ADD_1_S_39: XORCY port map (
LI => R1IN_4_ADD_1_AXB_39,
CI => R1IN_4_ADD_1_CRY_38,
O => NN_5);
R1IN_4_ADD_1_CRY_39_Z7600: MUXCY_L port map (
DI => R1IN_4_2F(39),
CI => R1IN_4_ADD_1_CRY_38,
S => R1IN_4_ADD_1_AXB_39,
LO => R1IN_4_ADD_1_CRY_39);
R1IN_4_ADD_1_S_38: XORCY port map (
LI => R1IN_4_ADD_1_AXB_38,
CI => R1IN_4_ADD_1_CRY_37,
O => NN_4);
R1IN_4_ADD_1_CRY_38_Z7602: MUXCY_L port map (
DI => R1IN_4_2F(38),
CI => R1IN_4_ADD_1_CRY_37,
S => R1IN_4_ADD_1_AXB_38,
LO => R1IN_4_ADD_1_CRY_38);
R1IN_4_ADD_1_S_37: XORCY port map (
LI => R1IN_4_ADD_1_AXB_37,
CI => R1IN_4_ADD_1_CRY_36,
O => NN_3);
R1IN_4_ADD_1_CRY_37_Z7604: MUXCY_L port map (
DI => R1IN_4_2F(37),
CI => R1IN_4_ADD_1_CRY_36,
S => R1IN_4_ADD_1_AXB_37,
LO => R1IN_4_ADD_1_CRY_37);
R1IN_4_ADD_1_S_36: XORCY port map (
LI => R1IN_4_ADD_1_AXB_36,
CI => R1IN_4_ADD_1_CRY_35,
O => R1IN_4_ADD_2_1);
R1IN_4_ADD_1_CRY_36_Z7606: MUXCY_L port map (
DI => R1IN_4_2F(36),
CI => R1IN_4_ADD_1_CRY_35,
S => R1IN_4_ADD_1_AXB_36,
LO => R1IN_4_ADD_1_CRY_36);
R1IN_4_ADD_1_S_35: XORCY port map (
LI => R1IN_4_ADD_1_AXB_35,
CI => R1IN_4_ADD_1_CRY_34,
O => R1IN_4_ADD_1(35));
R1IN_4_ADD_1_CRY_35_Z7608: MUXCY_L port map (
DI => R1IN_4_2F(35),
CI => R1IN_4_ADD_1_CRY_34,
S => R1IN_4_ADD_1_AXB_35,
LO => R1IN_4_ADD_1_CRY_35);
R1IN_4_ADD_1_S_34: XORCY port map (
LI => R1IN_4_ADD_1_AXB_34,
CI => R1IN_4_ADD_1_CRY_33,
O => R1IN_4_ADD_1(34));
R1IN_4_ADD_1_CRY_34_Z7610: MUXCY_L port map (
DI => R1IN_4_2F(34),
CI => R1IN_4_ADD_1_CRY_33,
S => R1IN_4_ADD_1_AXB_34,
LO => R1IN_4_ADD_1_CRY_34);
R1IN_4_ADD_1_S_33: XORCY port map (
LI => R1IN_4_ADD_1_AXB_33,
CI => R1IN_4_ADD_1_CRY_32,
O => R1IN_4_ADD_1(33));
R1IN_4_ADD_1_CRY_33_Z7612: MUXCY_L port map (
DI => R1IN_4_2F(33),
CI => R1IN_4_ADD_1_CRY_32,
S => R1IN_4_ADD_1_AXB_33,
LO => R1IN_4_ADD_1_CRY_33);
R1IN_4_ADD_1_S_32: XORCY port map (
LI => R1IN_4_ADD_1_AXB_32,
CI => R1IN_4_ADD_1_CRY_31,
O => R1IN_4_ADD_1(32));
R1IN_4_ADD_1_CRY_32_Z7614: MUXCY_L port map (
DI => R1IN_4_2F(32),
CI => R1IN_4_ADD_1_CRY_31,
S => R1IN_4_ADD_1_AXB_32,
LO => R1IN_4_ADD_1_CRY_32);
R1IN_4_ADD_1_S_31: XORCY port map (
LI => R1IN_4_ADD_1_AXB_31,
CI => R1IN_4_ADD_1_CRY_30,
O => R1IN_4_ADD_1(31));
R1IN_4_ADD_1_CRY_31_Z7616: MUXCY_L port map (
DI => R1IN_4_2F(31),
CI => R1IN_4_ADD_1_CRY_30,
S => R1IN_4_ADD_1_AXB_31,
LO => R1IN_4_ADD_1_CRY_31);
R1IN_4_ADD_1_S_30: XORCY port map (
LI => R1IN_4_ADD_1_AXB_30,
CI => R1IN_4_ADD_1_CRY_29,
O => R1IN_4_ADD_1(30));
R1IN_4_ADD_1_CRY_30_Z7618: MUXCY_L port map (
DI => R1IN_4_2F(30),
CI => R1IN_4_ADD_1_CRY_29,
S => R1IN_4_ADD_1_AXB_30,
LO => R1IN_4_ADD_1_CRY_30);
R1IN_4_ADD_1_S_29: XORCY port map (
LI => R1IN_4_ADD_1_AXB_29,
CI => R1IN_4_ADD_1_CRY_28,
O => R1IN_4_ADD_1(29));
R1IN_4_ADD_1_CRY_29_Z7620: MUXCY_L port map (
DI => R1IN_4_2F(29),
CI => R1IN_4_ADD_1_CRY_28,
S => R1IN_4_ADD_1_AXB_29,
LO => R1IN_4_ADD_1_CRY_29);
R1IN_4_ADD_1_S_28: XORCY port map (
LI => R1IN_4_ADD_1_AXB_28,
CI => R1IN_4_ADD_1_CRY_27,
O => R1IN_4_ADD_1(28));
R1IN_4_ADD_1_CRY_28_Z7622: MUXCY_L port map (
DI => R1IN_4_2F(28),
CI => R1IN_4_ADD_1_CRY_27,
S => R1IN_4_ADD_1_AXB_28,
LO => R1IN_4_ADD_1_CRY_28);
R1IN_4_ADD_1_S_27: XORCY port map (
LI => R1IN_4_ADD_1_AXB_27,
CI => R1IN_4_ADD_1_CRY_26,
O => R1IN_4_ADD_1(27));
R1IN_4_ADD_1_CRY_27_Z7624: MUXCY_L port map (
DI => R1IN_4_2F(27),
CI => R1IN_4_ADD_1_CRY_26,
S => R1IN_4_ADD_1_AXB_27,
LO => R1IN_4_ADD_1_CRY_27);
R1IN_4_ADD_1_S_26: XORCY port map (
LI => R1IN_4_ADD_1_AXB_26,
CI => R1IN_4_ADD_1_CRY_25,
O => R1IN_4_ADD_1(26));
R1IN_4_ADD_1_CRY_26_Z7626: MUXCY_L port map (
DI => R1IN_4_2F(26),
CI => R1IN_4_ADD_1_CRY_25,
S => R1IN_4_ADD_1_AXB_26,
LO => R1IN_4_ADD_1_CRY_26);
R1IN_4_ADD_1_S_25: XORCY port map (
LI => R1IN_4_ADD_1_AXB_25,
CI => R1IN_4_ADD_1_CRY_24,
O => R1IN_4_ADD_1(25));
R1IN_4_ADD_1_CRY_25_Z7628: MUXCY_L port map (
DI => R1IN_4_2F(25),
CI => R1IN_4_ADD_1_CRY_24,
S => R1IN_4_ADD_1_AXB_25,
LO => R1IN_4_ADD_1_CRY_25);
R1IN_4_ADD_1_S_24: XORCY port map (
LI => R1IN_4_ADD_1_AXB_24,
CI => R1IN_4_ADD_1_CRY_23,
O => R1IN_4_ADD_1(24));
R1IN_4_ADD_1_CRY_24_Z7630: MUXCY_L port map (
DI => R1IN_4_2F(24),
CI => R1IN_4_ADD_1_CRY_23,
S => R1IN_4_ADD_1_AXB_24,
LO => R1IN_4_ADD_1_CRY_24);
R1IN_4_ADD_1_S_23: XORCY port map (
LI => R1IN_4_ADD_1_AXB_23,
CI => R1IN_4_ADD_1_CRY_22,
O => R1IN_4_ADD_1(23));
R1IN_4_ADD_1_CRY_23_Z7632: MUXCY_L port map (
DI => R1IN_4_2F(23),
CI => R1IN_4_ADD_1_CRY_22,
S => R1IN_4_ADD_1_AXB_23,
LO => R1IN_4_ADD_1_CRY_23);
R1IN_4_ADD_1_S_22: XORCY port map (
LI => R1IN_4_ADD_1_AXB_22,
CI => R1IN_4_ADD_1_CRY_21,
O => R1IN_4_ADD_1(22));
R1IN_4_ADD_1_CRY_22_Z7634: MUXCY_L port map (
DI => R1IN_4_2F(22),
CI => R1IN_4_ADD_1_CRY_21,
S => R1IN_4_ADD_1_AXB_22,
LO => R1IN_4_ADD_1_CRY_22);
R1IN_4_ADD_1_S_21: XORCY port map (
LI => R1IN_4_ADD_1_AXB_21,
CI => R1IN_4_ADD_1_CRY_20,
O => R1IN_4_ADD_1(21));
R1IN_4_ADD_1_CRY_21_Z7636: MUXCY_L port map (
DI => R1IN_4_2F(21),
CI => R1IN_4_ADD_1_CRY_20,
S => R1IN_4_ADD_1_AXB_21,
LO => R1IN_4_ADD_1_CRY_21);
R1IN_4_ADD_1_S_20: XORCY port map (
LI => R1IN_4_ADD_1_AXB_20,
CI => R1IN_4_ADD_1_CRY_19,
O => R1IN_4_ADD_1(20));
R1IN_4_ADD_1_CRY_20_Z7638: MUXCY_L port map (
DI => R1IN_4_2F(20),
CI => R1IN_4_ADD_1_CRY_19,
S => R1IN_4_ADD_1_AXB_20,
LO => R1IN_4_ADD_1_CRY_20);
R1IN_4_ADD_1_S_19: XORCY port map (
LI => R1IN_4_ADD_1_AXB_19,
CI => R1IN_4_ADD_1_CRY_18,
O => R1IN_4_ADD_1(19));
R1IN_4_ADD_1_CRY_19_Z7640: MUXCY_L port map (
DI => R1IN_4_2F(19),
CI => R1IN_4_ADD_1_CRY_18,
S => R1IN_4_ADD_1_AXB_19,
LO => R1IN_4_ADD_1_CRY_19);
R1IN_4_ADD_1_S_18: XORCY port map (
LI => R1IN_4_ADD_1_AXB_18,
CI => R1IN_4_ADD_1_CRY_17,
O => R1IN_4_ADD_1(18));
R1IN_4_ADD_1_CRY_18_Z7642: MUXCY_L port map (
DI => R1IN_4_2F(18),
CI => R1IN_4_ADD_1_CRY_17,
S => R1IN_4_ADD_1_AXB_18,
LO => R1IN_4_ADD_1_CRY_18);
R1IN_4_ADD_1_S_17: XORCY port map (
LI => R1IN_4_ADD_1_AXB_17,
CI => R1IN_4_ADD_1_CRY_16,
O => R1IN_4_ADD_1(17));
R1IN_4_ADD_1_CRY_17_Z7644: MUXCY_L port map (
DI => R1IN_4_2F(17),
CI => R1IN_4_ADD_1_CRY_16,
S => R1IN_4_ADD_1_AXB_17,
LO => R1IN_4_ADD_1_CRY_17);
R1IN_4_ADD_1_S_16: XORCY port map (
LI => R1IN_4_ADD_1_AXB_16,
CI => R1IN_4_ADD_1_CRY_15,
O => R1IN_4_ADD_1(16));
R1IN_4_ADD_1_CRY_16_Z7646: MUXCY_L port map (
DI => R1IN_4_2F(16),
CI => R1IN_4_ADD_1_CRY_15,
S => R1IN_4_ADD_1_AXB_16,
LO => R1IN_4_ADD_1_CRY_16);
R1IN_4_ADD_1_S_15: XORCY port map (
LI => R1IN_4_ADD_1_AXB_15,
CI => R1IN_4_ADD_1_CRY_14,
O => R1IN_4_ADD_1(15));
R1IN_4_ADD_1_CRY_15_Z7648: MUXCY_L port map (
DI => R1IN_4_2F(15),
CI => R1IN_4_ADD_1_CRY_14,
S => R1IN_4_ADD_1_AXB_15,
LO => R1IN_4_ADD_1_CRY_15);
R1IN_4_ADD_1_S_14: XORCY port map (
LI => R1IN_4_ADD_1_AXB_14,
CI => R1IN_4_ADD_1_CRY_13,
O => R1IN_4_ADD_1(14));
R1IN_4_ADD_1_CRY_14_Z7650: MUXCY_L port map (
DI => R1IN_4_2F(14),
CI => R1IN_4_ADD_1_CRY_13,
S => R1IN_4_ADD_1_AXB_14,
LO => R1IN_4_ADD_1_CRY_14);
R1IN_4_ADD_1_S_13: XORCY port map (
LI => R1IN_4_ADD_1_AXB_13,
CI => R1IN_4_ADD_1_CRY_12,
O => R1IN_4_ADD_1(13));
R1IN_4_ADD_1_CRY_13_Z7652: MUXCY_L port map (
DI => R1IN_4_2F(13),
CI => R1IN_4_ADD_1_CRY_12,
S => R1IN_4_ADD_1_AXB_13,
LO => R1IN_4_ADD_1_CRY_13);
R1IN_4_ADD_1_S_12: XORCY port map (
LI => R1IN_4_ADD_1_AXB_12,
CI => R1IN_4_ADD_1_CRY_11,
O => R1IN_4_ADD_1(12));
R1IN_4_ADD_1_CRY_12_Z7654: MUXCY_L port map (
DI => R1IN_4_2F(12),
CI => R1IN_4_ADD_1_CRY_11,
S => R1IN_4_ADD_1_AXB_12,
LO => R1IN_4_ADD_1_CRY_12);
R1IN_4_ADD_1_S_11: XORCY port map (
LI => R1IN_4_ADD_1_AXB_11,
CI => R1IN_4_ADD_1_CRY_10,
O => R1IN_4_ADD_1(11));
R1IN_4_ADD_1_CRY_11_Z7656: MUXCY_L port map (
DI => R1IN_4_2F(11),
CI => R1IN_4_ADD_1_CRY_10,
S => R1IN_4_ADD_1_AXB_11,
LO => R1IN_4_ADD_1_CRY_11);
R1IN_4_ADD_1_S_10: XORCY port map (
LI => R1IN_4_ADD_1_AXB_10,
CI => R1IN_4_ADD_1_CRY_9,
O => R1IN_4_ADD_1(10));
R1IN_4_ADD_1_CRY_10_Z7658: MUXCY_L port map (
DI => R1IN_4_2F(10),
CI => R1IN_4_ADD_1_CRY_9,
S => R1IN_4_ADD_1_AXB_10,
LO => R1IN_4_ADD_1_CRY_10);
R1IN_4_ADD_1_S_9: XORCY port map (
LI => R1IN_4_ADD_1_AXB_9,
CI => R1IN_4_ADD_1_CRY_8,
O => R1IN_4_ADD_1(9));
R1IN_4_ADD_1_CRY_9_Z7660: MUXCY_L port map (
DI => R1IN_4_2F(9),
CI => R1IN_4_ADD_1_CRY_8,
S => R1IN_4_ADD_1_AXB_9,
LO => R1IN_4_ADD_1_CRY_9);
R1IN_4_ADD_1_S_8: XORCY port map (
LI => R1IN_4_ADD_1_AXB_8,
CI => R1IN_4_ADD_1_CRY_7,
O => R1IN_4_ADD_1(8));
R1IN_4_ADD_1_CRY_8_Z7662: MUXCY_L port map (
DI => R1IN_4_2F(8),
CI => R1IN_4_ADD_1_CRY_7,
S => R1IN_4_ADD_1_AXB_8,
LO => R1IN_4_ADD_1_CRY_8);
R1IN_4_ADD_1_S_7: XORCY port map (
LI => R1IN_4_ADD_1_AXB_7,
CI => R1IN_4_ADD_1_CRY_6,
O => R1IN_4_ADD_1(7));
R1IN_4_ADD_1_CRY_7_Z7664: MUXCY_L port map (
DI => R1IN_4_2F(7),
CI => R1IN_4_ADD_1_CRY_6,
S => R1IN_4_ADD_1_AXB_7,
LO => R1IN_4_ADD_1_CRY_7);
R1IN_4_ADD_1_S_6: XORCY port map (
LI => R1IN_4_ADD_1_AXB_6,
CI => R1IN_4_ADD_1_CRY_5,
O => R1IN_4_ADD_1(6));
R1IN_4_ADD_1_CRY_6_Z7666: MUXCY_L port map (
DI => R1IN_4_2F(6),
CI => R1IN_4_ADD_1_CRY_5,
S => R1IN_4_ADD_1_AXB_6,
LO => R1IN_4_ADD_1_CRY_6);
R1IN_4_ADD_1_S_5: XORCY port map (
LI => R1IN_4_ADD_1_AXB_5,
CI => R1IN_4_ADD_1_CRY_4,
O => R1IN_4_ADD_1(5));
R1IN_4_ADD_1_CRY_5_Z7668: MUXCY_L port map (
DI => R1IN_4_2F(5),
CI => R1IN_4_ADD_1_CRY_4,
S => R1IN_4_ADD_1_AXB_5,
LO => R1IN_4_ADD_1_CRY_5);
R1IN_4_ADD_1_S_4: XORCY port map (
LI => R1IN_4_ADD_1_AXB_4,
CI => R1IN_4_ADD_1_CRY_3,
O => R1IN_4_ADD_1(4));
R1IN_4_ADD_1_CRY_4_Z7670: MUXCY_L port map (
DI => R1IN_4_2F(4),
CI => R1IN_4_ADD_1_CRY_3,
S => R1IN_4_ADD_1_AXB_4,
LO => R1IN_4_ADD_1_CRY_4);
R1IN_4_ADD_1_S_3: XORCY port map (
LI => R1IN_4_ADD_1_AXB_3,
CI => R1IN_4_ADD_1_CRY_2,
O => R1IN_4_ADD_1(3));
R1IN_4_ADD_1_CRY_3_Z7672: MUXCY_L port map (
DI => R1IN_4_2F(3),
CI => R1IN_4_ADD_1_CRY_2,
S => R1IN_4_ADD_1_AXB_3,
LO => R1IN_4_ADD_1_CRY_3);
R1IN_4_ADD_1_S_2: XORCY port map (
LI => R1IN_4_ADD_1_AXB_2,
CI => R1IN_4_ADD_1_CRY_1,
O => R1IN_4_ADD_1(2));
R1IN_4_ADD_1_CRY_2_Z7674: MUXCY_L port map (
DI => R1IN_4_2F(2),
CI => R1IN_4_ADD_1_CRY_1,
S => R1IN_4_ADD_1_AXB_2,
LO => R1IN_4_ADD_1_CRY_2);
R1IN_4_ADD_1_S_1: XORCY port map (
LI => R1IN_4_ADD_1_AXB_1,
CI => R1IN_4_ADD_1_CRY_0,
O => R1IN_4_ADD_1(1));
R1IN_4_ADD_1_CRY_1_Z7676: MUXCY_L port map (
DI => R1IN_4_2F(1),
CI => R1IN_4_ADD_1_CRY_0,
S => R1IN_4_ADD_1_AXB_1,
LO => R1IN_4_ADD_1_CRY_1);
R1IN_4_ADD_1_CRY_0_Z7677: MUXCY_L port map (
DI => NN_12,
CI => NN_1,
S => R1IN_4_ADD_2_0,
LO => R1IN_4_ADD_1_CRY_0);
R1IN_4_4_ADD_2_S_36: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_36,
CI => R1IN_4_4_ADD_2_CRY_35,
O => R1IN_4_4(53));
R1IN_4_4_ADD_2_S_35: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_35,
CI => R1IN_4_4_ADD_2_CRY_34,
O => R1IN_4_4(52));
R1IN_4_4_ADD_2_CRY_35_Z7680: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_4_ADD_2_CRY_34,
S => R1IN_4_4_ADD_2_AXB_35,
LO => R1IN_4_4_ADD_2_CRY_35);
R1IN_4_4_ADD_2_S_34: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_34,
CI => R1IN_4_4_ADD_2_CRY_33,
O => R1IN_4_4(51));
R1IN_4_4_ADD_2_CRY_34_Z7682: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_4_ADD_2_CRY_33,
S => R1IN_4_4_ADD_2_AXB_34,
LO => R1IN_4_4_ADD_2_CRY_34);
R1IN_4_4_ADD_2_S_33: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_33,
CI => R1IN_4_4_ADD_2_CRY_32,
O => R1IN_4_4(50));
R1IN_4_4_ADD_2_CRY_33_Z7684: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_4_ADD_2_CRY_32,
S => R1IN_4_4_ADD_2_AXB_33,
LO => R1IN_4_4_ADD_2_CRY_33);
R1IN_4_4_ADD_2_S_32: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_32,
CI => R1IN_4_4_ADD_2_CRY_31,
O => R1IN_4_4(49));
R1IN_4_4_ADD_2_CRY_32_Z7686: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_4_ADD_2_CRY_31,
S => R1IN_4_4_ADD_2_AXB_32,
LO => R1IN_4_4_ADD_2_CRY_32);
R1IN_4_4_ADD_2_S_31: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_31,
CI => R1IN_4_4_ADD_2_CRY_30,
O => R1IN_4_4(48));
R1IN_4_4_ADD_2_CRY_31_Z7688: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_4_ADD_2_CRY_30,
S => R1IN_4_4_ADD_2_AXB_31,
LO => R1IN_4_4_ADD_2_CRY_31);
R1IN_4_4_ADD_2_S_30: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_30,
CI => R1IN_4_4_ADD_2_CRY_29,
O => R1IN_4_4(47));
R1IN_4_4_ADD_2_CRY_30_Z7690: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_4_ADD_2_CRY_29,
S => R1IN_4_4_ADD_2_AXB_30,
LO => R1IN_4_4_ADD_2_CRY_30);
R1IN_4_4_ADD_2_S_29: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_29,
CI => R1IN_4_4_ADD_2_CRY_28,
O => R1IN_4_4(46));
R1IN_4_4_ADD_2_CRY_29_Z7692: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_4_ADD_2_CRY_28,
S => R1IN_4_4_ADD_2_AXB_29,
LO => R1IN_4_4_ADD_2_CRY_29);
R1IN_4_4_ADD_2_S_28: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_28,
CI => R1IN_4_4_ADD_2_CRY_27,
O => R1IN_4_4(45));
R1IN_4_4_ADD_2_CRY_28_Z7694: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_4_ADD_2_CRY_27,
S => R1IN_4_4_ADD_2_AXB_28,
LO => R1IN_4_4_ADD_2_CRY_28);
R1IN_4_4_ADD_2_S_27: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_27,
CI => R1IN_4_4_ADD_2_CRY_26,
O => R1IN_4_4(44));
R1IN_4_4_ADD_2_CRY_27_Z7696: MUXCY_L port map (
DI => R1IN_4_4_4F(10),
CI => R1IN_4_4_ADD_2_CRY_26,
S => R1IN_4_4_ADD_2_AXB_27,
LO => R1IN_4_4_ADD_2_CRY_27);
R1IN_4_4_ADD_2_S_26: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_26,
CI => R1IN_4_4_ADD_2_CRY_25,
O => R1IN_4_4(43));
R1IN_4_4_ADD_2_CRY_26_Z7698: MUXCY_L port map (
DI => R1IN_4_4_4F(9),
CI => R1IN_4_4_ADD_2_CRY_25,
S => R1IN_4_4_ADD_2_AXB_26,
LO => R1IN_4_4_ADD_2_CRY_26);
R1IN_4_4_ADD_2_S_25: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_25,
CI => R1IN_4_4_ADD_2_CRY_24,
O => R1IN_4_4(42));
R1IN_4_4_ADD_2_CRY_25_Z7700: MUXCY_L port map (
DI => R1IN_4_4_4F(8),
CI => R1IN_4_4_ADD_2_CRY_24,
S => R1IN_4_4_ADD_2_AXB_25,
LO => R1IN_4_4_ADD_2_CRY_25);
R1IN_4_4_ADD_2_S_24: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_24,
CI => R1IN_4_4_ADD_2_CRY_23,
O => R1IN_4_4(41));
R1IN_4_4_ADD_2_CRY_24_Z7702: MUXCY_L port map (
DI => R1IN_4_4_4F(7),
CI => R1IN_4_4_ADD_2_CRY_23,
S => R1IN_4_4_ADD_2_AXB_24,
LO => R1IN_4_4_ADD_2_CRY_24);
R1IN_4_4_ADD_2_S_23: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_23,
CI => R1IN_4_4_ADD_2_CRY_22,
O => R1IN_4_4(40));
R1IN_4_4_ADD_2_CRY_23_Z7704: MUXCY_L port map (
DI => R1IN_4_4_4F(6),
CI => R1IN_4_4_ADD_2_CRY_22,
S => R1IN_4_4_ADD_2_AXB_23,
LO => R1IN_4_4_ADD_2_CRY_23);
R1IN_4_4_ADD_2_S_22: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_22,
CI => R1IN_4_4_ADD_2_CRY_21,
O => R1IN_4_4(39));
R1IN_4_4_ADD_2_CRY_22_Z7706: MUXCY_L port map (
DI => R1IN_4_4_4F(5),
CI => R1IN_4_4_ADD_2_CRY_21,
S => R1IN_4_4_ADD_2_AXB_22,
LO => R1IN_4_4_ADD_2_CRY_22);
R1IN_4_4_ADD_2_S_21: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_21,
CI => R1IN_4_4_ADD_2_CRY_20,
O => R1IN_4_4(38));
R1IN_4_4_ADD_2_CRY_21_Z7708: MUXCY_L port map (
DI => R1IN_4_4_4F(4),
CI => R1IN_4_4_ADD_2_CRY_20,
S => R1IN_4_4_ADD_2_AXB_21,
LO => R1IN_4_4_ADD_2_CRY_21);
R1IN_4_4_ADD_2_S_20: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_20,
CI => R1IN_4_4_ADD_2_CRY_19,
O => R1IN_4_4(37));
R1IN_4_4_ADD_2_CRY_20_Z7710: MUXCY_L port map (
DI => R1IN_4_4_4F(3),
CI => R1IN_4_4_ADD_2_CRY_19,
S => R1IN_4_4_ADD_2_AXB_20,
LO => R1IN_4_4_ADD_2_CRY_20);
R1IN_4_4_ADD_2_S_19: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_19,
CI => R1IN_4_4_ADD_2_CRY_18,
O => R1IN_4_4(36));
R1IN_4_4_ADD_2_CRY_19_Z7712: MUXCY_L port map (
DI => R1IN_4_4_4F(2),
CI => R1IN_4_4_ADD_2_CRY_18,
S => R1IN_4_4_ADD_2_AXB_19,
LO => R1IN_4_4_ADD_2_CRY_19);
R1IN_4_4_ADD_2_S_18: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_18,
CI => R1IN_4_4_ADD_2_CRY_17,
O => R1IN_4_4(35));
R1IN_4_4_ADD_2_CRY_18_Z7714: MUXCY_L port map (
DI => R1IN_4_4_4F(1),
CI => R1IN_4_4_ADD_2_CRY_17,
S => R1IN_4_4_ADD_2_AXB_18,
LO => R1IN_4_4_ADD_2_CRY_18);
R1IN_4_4_ADD_2_S_17: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_17,
CI => R1IN_4_4_ADD_2_CRY_16,
O => R1IN_4_4(34));
R1IN_4_4_ADD_2_CRY_17_Z7716: MUXCY_L port map (
DI => R1IN_4_4_4F(0),
CI => R1IN_4_4_ADD_2_CRY_16,
S => R1IN_4_4_ADD_2_AXB_17,
LO => R1IN_4_4_ADD_2_CRY_17);
R1IN_4_4_ADD_2_S_16: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_16,
CI => R1IN_4_4_ADD_2_CRY_15,
O => R1IN_4_4(33));
R1IN_4_4_ADD_2_CRY_16_Z7718: MUXCY_L port map (
DI => R1IN_4_4_1F(33),
CI => R1IN_4_4_ADD_2_CRY_15,
S => R1IN_4_4_ADD_2_AXB_16,
LO => R1IN_4_4_ADD_2_CRY_16);
R1IN_4_4_ADD_2_S_15: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_15,
CI => R1IN_4_4_ADD_2_CRY_14,
O => R1IN_4_4(32));
R1IN_4_4_ADD_2_CRY_15_Z7720: MUXCY_L port map (
DI => R1IN_4_4_1F(32),
CI => R1IN_4_4_ADD_2_CRY_14,
S => R1IN_4_4_ADD_2_AXB_15,
LO => R1IN_4_4_ADD_2_CRY_15);
R1IN_4_4_ADD_2_S_14: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_14,
CI => R1IN_4_4_ADD_2_CRY_13,
O => R1IN_4_4(31));
R1IN_4_4_ADD_2_CRY_14_Z7722: MUXCY_L port map (
DI => R1IN_4_4_1F(31),
CI => R1IN_4_4_ADD_2_CRY_13,
S => R1IN_4_4_ADD_2_AXB_14,
LO => R1IN_4_4_ADD_2_CRY_14);
R1IN_4_4_ADD_2_S_13: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_13,
CI => R1IN_4_4_ADD_2_CRY_12,
O => R1IN_4_4(30));
R1IN_4_4_ADD_2_CRY_13_Z7724: MUXCY_L port map (
DI => R1IN_4_4_1F(30),
CI => R1IN_4_4_ADD_2_CRY_12,
S => R1IN_4_4_ADD_2_AXB_13,
LO => R1IN_4_4_ADD_2_CRY_13);
R1IN_4_4_ADD_2_S_12: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_12,
CI => R1IN_4_4_ADD_2_CRY_11,
O => R1IN_4_4(29));
R1IN_4_4_ADD_2_CRY_12_Z7726: MUXCY_L port map (
DI => R1IN_4_4_1F(29),
CI => R1IN_4_4_ADD_2_CRY_11,
S => R1IN_4_4_ADD_2_AXB_12,
LO => R1IN_4_4_ADD_2_CRY_12);
R1IN_4_4_ADD_2_S_11: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_11,
CI => R1IN_4_4_ADD_2_CRY_10,
O => R1IN_4_4(28));
R1IN_4_4_ADD_2_CRY_11_Z7728: MUXCY_L port map (
DI => R1IN_4_4_1F(28),
CI => R1IN_4_4_ADD_2_CRY_10,
S => R1IN_4_4_ADD_2_AXB_11,
LO => R1IN_4_4_ADD_2_CRY_11);
R1IN_4_4_ADD_2_S_10: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_10,
CI => R1IN_4_4_ADD_2_CRY_9,
O => R1IN_4_4(27));
R1IN_4_4_ADD_2_CRY_10_Z7730: MUXCY_L port map (
DI => R1IN_4_4_1F(27),
CI => R1IN_4_4_ADD_2_CRY_9,
S => R1IN_4_4_ADD_2_AXB_10,
LO => R1IN_4_4_ADD_2_CRY_10);
R1IN_4_4_ADD_2_S_9: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_9,
CI => R1IN_4_4_ADD_2_CRY_8,
O => R1IN_4_4(26));
R1IN_4_4_ADD_2_CRY_9_Z7732: MUXCY_L port map (
DI => R1IN_4_4_1F(26),
CI => R1IN_4_4_ADD_2_CRY_8,
S => R1IN_4_4_ADD_2_AXB_9,
LO => R1IN_4_4_ADD_2_CRY_9);
R1IN_4_4_ADD_2_S_8: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_8,
CI => R1IN_4_4_ADD_2_CRY_7,
O => R1IN_4_4(25));
R1IN_4_4_ADD_2_CRY_8_Z7734: MUXCY_L port map (
DI => R1IN_4_4_1F(25),
CI => R1IN_4_4_ADD_2_CRY_7,
S => R1IN_4_4_ADD_2_AXB_8,
LO => R1IN_4_4_ADD_2_CRY_8);
R1IN_4_4_ADD_2_S_7: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_7,
CI => R1IN_4_4_ADD_2_CRY_6,
O => R1IN_4_4(24));
R1IN_4_4_ADD_2_CRY_7_Z7736: MUXCY_L port map (
DI => R1IN_4_4_1F(24),
CI => R1IN_4_4_ADD_2_CRY_6,
S => R1IN_4_4_ADD_2_AXB_7,
LO => R1IN_4_4_ADD_2_CRY_7);
R1IN_4_4_ADD_2_S_6: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_6,
CI => R1IN_4_4_ADD_2_CRY_5,
O => R1IN_4_4(23));
R1IN_4_4_ADD_2_CRY_6_Z7738: MUXCY_L port map (
DI => R1IN_4_4_1F(23),
CI => R1IN_4_4_ADD_2_CRY_5,
S => R1IN_4_4_ADD_2_AXB_6,
LO => R1IN_4_4_ADD_2_CRY_6);
R1IN_4_4_ADD_2_S_5: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_5,
CI => R1IN_4_4_ADD_2_CRY_4,
O => R1IN_4_4(22));
R1IN_4_4_ADD_2_CRY_5_Z7740: MUXCY_L port map (
DI => R1IN_4_4_1F(22),
CI => R1IN_4_4_ADD_2_CRY_4,
S => R1IN_4_4_ADD_2_AXB_5,
LO => R1IN_4_4_ADD_2_CRY_5);
R1IN_4_4_ADD_2_S_4: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_4,
CI => R1IN_4_4_ADD_2_CRY_3,
O => R1IN_4_4(21));
R1IN_4_4_ADD_2_CRY_4_Z7742: MUXCY_L port map (
DI => R1IN_4_4_1F(21),
CI => R1IN_4_4_ADD_2_CRY_3,
S => R1IN_4_4_ADD_2_AXB_4,
LO => R1IN_4_4_ADD_2_CRY_4);
R1IN_4_4_ADD_2_S_3: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_3,
CI => R1IN_4_4_ADD_2_CRY_2,
O => R1IN_4_4(20));
R1IN_4_4_ADD_2_CRY_3_Z7744: MUXCY_L port map (
DI => R1IN_4_4_1F(20),
CI => R1IN_4_4_ADD_2_CRY_2,
S => R1IN_4_4_ADD_2_AXB_3,
LO => R1IN_4_4_ADD_2_CRY_3);
R1IN_4_4_ADD_2_S_2: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_2,
CI => R1IN_4_4_ADD_2_CRY_1,
O => R1IN_4_4(19));
R1IN_4_4_ADD_2_CRY_2_Z7746: MUXCY_L port map (
DI => R1IN_4_4_1F(19),
CI => R1IN_4_4_ADD_2_CRY_1,
S => R1IN_4_4_ADD_2_AXB_2,
LO => R1IN_4_4_ADD_2_CRY_2);
R1IN_4_4_ADD_2_S_1: XORCY port map (
LI => R1IN_4_4_ADD_2_AXB_1,
CI => R1IN_4_4_ADD_2_CRY_0,
O => R1IN_4_4(18));
R1IN_4_4_ADD_2_CRY_1_Z7748: MUXCY_L port map (
DI => R1IN_4_4_1F(18),
CI => R1IN_4_4_ADD_2_CRY_0,
S => R1IN_4_4_ADD_2_AXB_1,
LO => R1IN_4_4_ADD_2_CRY_1);
R1IN_4_4_ADD_2_CRY_0_Z7749: MUXCY_L port map (
DI => R1IN_4_4_ADD_2,
CI => NN_1,
S => R1IN_4_4(17),
LO => R1IN_4_4_ADD_2_CRY_0);
R1IN_2_ADD_1_S_43: XORCY port map (
LI => R1IN_2_ADD_1_AXB_43,
CI => R1IN_2_ADD_1_CRY_42,
O => R1IN_2(60));
R1IN_2_ADD_1_S_42: XORCY port map (
LI => R1IN_2_ADD_1_AXB_42,
CI => R1IN_2_ADD_1_CRY_41,
O => R1IN_2(59));
R1IN_2_ADD_1_CRY_42_Z7752: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_41,
S => R1IN_2_ADD_1_AXB_42,
LO => R1IN_2_ADD_1_CRY_42);
R1IN_2_ADD_1_S_41: XORCY port map (
LI => R1IN_2_ADD_1_AXB_41,
CI => R1IN_2_ADD_1_CRY_40,
O => R1IN_2(58));
R1IN_2_ADD_1_CRY_41_Z7754: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_40,
S => R1IN_2_ADD_1_AXB_41,
LO => R1IN_2_ADD_1_CRY_41);
R1IN_2_ADD_1_S_40: XORCY port map (
LI => R1IN_2_ADD_1_AXB_40,
CI => R1IN_2_ADD_1_CRY_39,
O => R1IN_2(57));
R1IN_2_ADD_1_CRY_40_Z7756: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_39,
S => R1IN_2_ADD_1_AXB_40,
LO => R1IN_2_ADD_1_CRY_40);
R1IN_2_ADD_1_S_39: XORCY port map (
LI => R1IN_2_ADD_1_AXB_39,
CI => R1IN_2_ADD_1_CRY_38,
O => R1IN_2(56));
R1IN_2_ADD_1_CRY_39_Z7758: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_38,
S => R1IN_2_ADD_1_AXB_39,
LO => R1IN_2_ADD_1_CRY_39);
R1IN_2_ADD_1_S_38: XORCY port map (
LI => R1IN_2_ADD_1_AXB_38,
CI => R1IN_2_ADD_1_CRY_37,
O => R1IN_2(55));
R1IN_2_ADD_1_CRY_38_Z7760: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_37,
S => R1IN_2_ADD_1_AXB_38,
LO => R1IN_2_ADD_1_CRY_38);
R1IN_2_ADD_1_S_37: XORCY port map (
LI => R1IN_2_ADD_1_AXB_37,
CI => R1IN_2_ADD_1_CRY_36,
O => R1IN_2(54));
R1IN_2_ADD_1_CRY_37_Z7762: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_36,
S => R1IN_2_ADD_1_AXB_37,
LO => R1IN_2_ADD_1_CRY_37);
R1IN_2_ADD_1_S_36: XORCY port map (
LI => R1IN_2_ADD_1_AXB_36,
CI => R1IN_2_ADD_1_CRY_35,
O => R1IN_2(53));
R1IN_2_ADD_1_CRY_36_Z7764: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_35,
S => R1IN_2_ADD_1_AXB_36,
LO => R1IN_2_ADD_1_CRY_36);
R1IN_2_ADD_1_S_35: XORCY port map (
LI => R1IN_2_ADD_1_AXB_35,
CI => R1IN_2_ADD_1_CRY_34,
O => R1IN_2(52));
R1IN_2_ADD_1_CRY_35_Z7766: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_34,
S => R1IN_2_ADD_1_AXB_35,
LO => R1IN_2_ADD_1_CRY_35);
R1IN_2_ADD_1_S_34: XORCY port map (
LI => R1IN_2_ADD_1_AXB_34,
CI => R1IN_2_ADD_1_CRY_33,
O => R1IN_2(51));
R1IN_2_ADD_1_CRY_34_Z7768: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_33,
S => R1IN_2_ADD_1_AXB_34,
LO => R1IN_2_ADD_1_CRY_34);
R1IN_2_ADD_1_S_33: XORCY port map (
LI => R1IN_2_ADD_1_AXB_33,
CI => R1IN_2_ADD_1_CRY_32,
O => R1IN_2(50));
R1IN_2_ADD_1_CRY_33_Z7770: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_32,
S => R1IN_2_ADD_1_AXB_33,
LO => R1IN_2_ADD_1_CRY_33);
R1IN_2_ADD_1_S_32: XORCY port map (
LI => R1IN_2_ADD_1_AXB_32,
CI => R1IN_2_ADD_1_CRY_31,
O => R1IN_2(49));
R1IN_2_ADD_1_CRY_32_Z7772: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_31,
S => R1IN_2_ADD_1_AXB_32,
LO => R1IN_2_ADD_1_CRY_32);
R1IN_2_ADD_1_S_31: XORCY port map (
LI => R1IN_2_ADD_1_AXB_31,
CI => R1IN_2_ADD_1_CRY_30,
O => R1IN_2(48));
R1IN_2_ADD_1_CRY_31_Z7774: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_30,
S => R1IN_2_ADD_1_AXB_31,
LO => R1IN_2_ADD_1_CRY_31);
R1IN_2_ADD_1_S_30: XORCY port map (
LI => R1IN_2_ADD_1_AXB_30,
CI => R1IN_2_ADD_1_CRY_29,
O => R1IN_2(47));
R1IN_2_ADD_1_CRY_30_Z7776: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_29,
S => R1IN_2_ADD_1_AXB_30,
LO => R1IN_2_ADD_1_CRY_30);
R1IN_2_ADD_1_S_29: XORCY port map (
LI => R1IN_2_ADD_1_AXB_29,
CI => R1IN_2_ADD_1_CRY_28,
O => R1IN_2(46));
R1IN_2_ADD_1_CRY_29_Z7778: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_28,
S => R1IN_2_ADD_1_AXB_29,
LO => R1IN_2_ADD_1_CRY_29);
R1IN_2_ADD_1_S_28: XORCY port map (
LI => R1IN_2_ADD_1_AXB_28,
CI => R1IN_2_ADD_1_CRY_27,
O => R1IN_2(45));
R1IN_2_ADD_1_CRY_28_Z7780: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_27,
S => R1IN_2_ADD_1_AXB_28,
LO => R1IN_2_ADD_1_CRY_28);
R1IN_2_ADD_1_S_27: XORCY port map (
LI => R1IN_2_ADD_1_AXB_27,
CI => R1IN_2_ADD_1_CRY_26,
O => R1IN_2(44));
R1IN_2_ADD_1_CRY_27_Z7782: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_26,
S => R1IN_2_ADD_1_AXB_27,
LO => R1IN_2_ADD_1_CRY_27);
R1IN_2_ADD_1_S_26: XORCY port map (
LI => R1IN_2_ADD_1_AXB_26,
CI => R1IN_2_ADD_1_CRY_25,
O => R1IN_2(43));
R1IN_2_ADD_1_CRY_26_Z7784: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_25,
S => R1IN_2_ADD_1_AXB_26,
LO => R1IN_2_ADD_1_CRY_26);
R1IN_2_ADD_1_S_25: XORCY port map (
LI => R1IN_2_ADD_1_AXB_25,
CI => R1IN_2_ADD_1_CRY_24,
O => R1IN_2(42));
R1IN_2_ADD_1_CRY_25_Z7786: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_24,
S => R1IN_2_ADD_1_AXB_25,
LO => R1IN_2_ADD_1_CRY_25);
R1IN_2_ADD_1_S_24: XORCY port map (
LI => R1IN_2_ADD_1_AXB_24,
CI => R1IN_2_ADD_1_CRY_23,
O => R1IN_2(41));
R1IN_2_ADD_1_CRY_24_Z7788: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_23,
S => R1IN_2_ADD_1_AXB_24,
LO => R1IN_2_ADD_1_CRY_24);
R1IN_2_ADD_1_S_23: XORCY port map (
LI => R1IN_2_ADD_1_AXB_23,
CI => R1IN_2_ADD_1_CRY_22,
O => R1IN_2(40));
R1IN_2_ADD_1_CRY_23_Z7790: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_22,
S => R1IN_2_ADD_1_AXB_23,
LO => R1IN_2_ADD_1_CRY_23);
R1IN_2_ADD_1_S_22: XORCY port map (
LI => R1IN_2_ADD_1_AXB_22,
CI => R1IN_2_ADD_1_CRY_21,
O => R1IN_2(39));
R1IN_2_ADD_1_CRY_22_Z7792: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_21,
S => R1IN_2_ADD_1_AXB_22,
LO => R1IN_2_ADD_1_CRY_22);
R1IN_2_ADD_1_S_21: XORCY port map (
LI => R1IN_2_ADD_1_AXB_21,
CI => R1IN_2_ADD_1_CRY_20,
O => R1IN_2(38));
R1IN_2_ADD_1_CRY_21_Z7794: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_20,
S => R1IN_2_ADD_1_AXB_21,
LO => R1IN_2_ADD_1_CRY_21);
R1IN_2_ADD_1_S_20: XORCY port map (
LI => R1IN_2_ADD_1_AXB_20,
CI => R1IN_2_ADD_1_CRY_19,
O => R1IN_2(37));
R1IN_2_ADD_1_CRY_20_Z7796: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_19,
S => R1IN_2_ADD_1_AXB_20,
LO => R1IN_2_ADD_1_CRY_20);
R1IN_2_ADD_1_S_19: XORCY port map (
LI => R1IN_2_ADD_1_AXB_19,
CI => R1IN_2_ADD_1_CRY_18,
O => R1IN_2(36));
R1IN_2_ADD_1_CRY_19_Z7798: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_18,
S => R1IN_2_ADD_1_AXB_19,
LO => R1IN_2_ADD_1_CRY_19);
R1IN_2_ADD_1_S_18: XORCY port map (
LI => R1IN_2_ADD_1_AXB_18,
CI => R1IN_2_ADD_1_CRY_17,
O => R1IN_2(35));
R1IN_2_ADD_1_CRY_18_Z7800: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_17,
S => R1IN_2_ADD_1_AXB_18,
LO => R1IN_2_ADD_1_CRY_18);
R1IN_2_ADD_1_S_17: XORCY port map (
LI => R1IN_2_ADD_1_AXB_17,
CI => R1IN_2_ADD_1_CRY_16,
O => R1IN_2(34));
R1IN_2_ADD_1_CRY_17_Z7802: MUXCY_L port map (
DI => NN_1,
CI => R1IN_2_ADD_1_CRY_16,
S => R1IN_2_ADD_1_AXB_17,
LO => R1IN_2_ADD_1_CRY_17);
R1IN_2_ADD_1_S_16: XORCY port map (
LI => R1IN_2_ADD_1_AXB_16,
CI => R1IN_2_ADD_1_CRY_15,
O => R1IN_2(33));
R1IN_2_ADD_1_CRY_16_Z7804: MUXCY_L port map (
DI => R1IN_2_2F(16),
CI => R1IN_2_ADD_1_CRY_15,
S => R1IN_2_ADD_1_AXB_16,
LO => R1IN_2_ADD_1_CRY_16);
R1IN_2_ADD_1_S_15: XORCY port map (
LI => R1IN_2_ADD_1_AXB_15,
CI => R1IN_2_ADD_1_CRY_14,
O => R1IN_2(32));
R1IN_2_ADD_1_CRY_15_Z7806: MUXCY_L port map (
DI => R1IN_2_2F(15),
CI => R1IN_2_ADD_1_CRY_14,
S => R1IN_2_ADD_1_AXB_15,
LO => R1IN_2_ADD_1_CRY_15);
R1IN_2_ADD_1_S_14: XORCY port map (
LI => R1IN_2_ADD_1_AXB_14,
CI => R1IN_2_ADD_1_CRY_13,
O => R1IN_2(31));
R1IN_2_ADD_1_CRY_14_Z7808: MUXCY_L port map (
DI => R1IN_2_2F(14),
CI => R1IN_2_ADD_1_CRY_13,
S => R1IN_2_ADD_1_AXB_14,
LO => R1IN_2_ADD_1_CRY_14);
R1IN_2_ADD_1_S_13: XORCY port map (
LI => R1IN_2_ADD_1_AXB_13,
CI => R1IN_2_ADD_1_CRY_12,
O => R1IN_2(30));
R1IN_2_ADD_1_CRY_13_Z7810: MUXCY_L port map (
DI => R1IN_2_2F(13),
CI => R1IN_2_ADD_1_CRY_12,
S => R1IN_2_ADD_1_AXB_13,
LO => R1IN_2_ADD_1_CRY_13);
R1IN_2_ADD_1_S_12: XORCY port map (
LI => R1IN_2_ADD_1_AXB_12,
CI => R1IN_2_ADD_1_CRY_11,
O => R1IN_2(29));
R1IN_2_ADD_1_CRY_12_Z7812: MUXCY_L port map (
DI => R1IN_2_2F(12),
CI => R1IN_2_ADD_1_CRY_11,
S => R1IN_2_ADD_1_AXB_12,
LO => R1IN_2_ADD_1_CRY_12);
R1IN_2_ADD_1_S_11: XORCY port map (
LI => R1IN_2_ADD_1_AXB_11,
CI => R1IN_2_ADD_1_CRY_10,
O => R1IN_2(28));
R1IN_2_ADD_1_CRY_11_Z7814: MUXCY_L port map (
DI => R1IN_2_2F(11),
CI => R1IN_2_ADD_1_CRY_10,
S => R1IN_2_ADD_1_AXB_11,
LO => R1IN_2_ADD_1_CRY_11);
R1IN_2_ADD_1_S_10: XORCY port map (
LI => R1IN_2_ADD_1_AXB_10,
CI => R1IN_2_ADD_1_CRY_9,
O => R1IN_2(27));
R1IN_2_ADD_1_CRY_10_Z7816: MUXCY_L port map (
DI => R1IN_2_2F(10),
CI => R1IN_2_ADD_1_CRY_9,
S => R1IN_2_ADD_1_AXB_10,
LO => R1IN_2_ADD_1_CRY_10);
R1IN_2_ADD_1_S_9: XORCY port map (
LI => R1IN_2_ADD_1_AXB_9,
CI => R1IN_2_ADD_1_CRY_8,
O => R1IN_2(26));
R1IN_2_ADD_1_CRY_9_Z7818: MUXCY_L port map (
DI => R1IN_2_2F(9),
CI => R1IN_2_ADD_1_CRY_8,
S => R1IN_2_ADD_1_AXB_9,
LO => R1IN_2_ADD_1_CRY_9);
R1IN_2_ADD_1_S_8: XORCY port map (
LI => R1IN_2_ADD_1_AXB_8,
CI => R1IN_2_ADD_1_CRY_7,
O => R1IN_2(25));
R1IN_2_ADD_1_CRY_8_Z7820: MUXCY_L port map (
DI => R1IN_2_2F(8),
CI => R1IN_2_ADD_1_CRY_7,
S => R1IN_2_ADD_1_AXB_8,
LO => R1IN_2_ADD_1_CRY_8);
R1IN_2_ADD_1_S_7: XORCY port map (
LI => R1IN_2_ADD_1_AXB_7,
CI => R1IN_2_ADD_1_CRY_6,
O => R1IN_2(24));
R1IN_2_ADD_1_CRY_7_Z7822: MUXCY_L port map (
DI => R1IN_2_2F(7),
CI => R1IN_2_ADD_1_CRY_6,
S => R1IN_2_ADD_1_AXB_7,
LO => R1IN_2_ADD_1_CRY_7);
R1IN_2_ADD_1_S_6: XORCY port map (
LI => R1IN_2_ADD_1_AXB_6,
CI => R1IN_2_ADD_1_CRY_5,
O => R1IN_2(23));
R1IN_2_ADD_1_CRY_6_Z7824: MUXCY_L port map (
DI => R1IN_2_2F(6),
CI => R1IN_2_ADD_1_CRY_5,
S => R1IN_2_ADD_1_AXB_6,
LO => R1IN_2_ADD_1_CRY_6);
R1IN_2_ADD_1_S_5: XORCY port map (
LI => R1IN_2_ADD_1_AXB_5,
CI => R1IN_2_ADD_1_CRY_4,
O => R1IN_2(22));
R1IN_2_ADD_1_CRY_5_Z7826: MUXCY_L port map (
DI => R1IN_2_2F(5),
CI => R1IN_2_ADD_1_CRY_4,
S => R1IN_2_ADD_1_AXB_5,
LO => R1IN_2_ADD_1_CRY_5);
R1IN_2_ADD_1_S_4: XORCY port map (
LI => R1IN_2_ADD_1_AXB_4,
CI => R1IN_2_ADD_1_CRY_3,
O => R1IN_2(21));
R1IN_2_ADD_1_CRY_4_Z7828: MUXCY_L port map (
DI => R1IN_2_2F(4),
CI => R1IN_2_ADD_1_CRY_3,
S => R1IN_2_ADD_1_AXB_4,
LO => R1IN_2_ADD_1_CRY_4);
R1IN_2_ADD_1_S_3: XORCY port map (
LI => R1IN_2_ADD_1_AXB_3,
CI => R1IN_2_ADD_1_CRY_2,
O => R1IN_2(20));
R1IN_2_ADD_1_CRY_3_Z7830: MUXCY_L port map (
DI => R1IN_2_2F(3),
CI => R1IN_2_ADD_1_CRY_2,
S => R1IN_2_ADD_1_AXB_3,
LO => R1IN_2_ADD_1_CRY_3);
R1IN_2_ADD_1_S_2: XORCY port map (
LI => R1IN_2_ADD_1_AXB_2,
CI => R1IN_2_ADD_1_CRY_1,
O => R1IN_2(19));
R1IN_2_ADD_1_CRY_2_Z7832: MUXCY_L port map (
DI => R1IN_2_2F(2),
CI => R1IN_2_ADD_1_CRY_1,
S => R1IN_2_ADD_1_AXB_2,
LO => R1IN_2_ADD_1_CRY_2);
R1IN_2_ADD_1_S_1: XORCY port map (
LI => R1IN_2_ADD_1_AXB_1,
CI => R1IN_2_ADD_1_CRY_0,
O => R1IN_2(18));
R1IN_2_ADD_1_CRY_1_Z7834: MUXCY_L port map (
DI => R1IN_2_2F(1),
CI => R1IN_2_ADD_1_CRY_0,
S => R1IN_2_ADD_1_AXB_1,
LO => R1IN_2_ADD_1_CRY_1);
R1IN_2_ADD_1_CRY_0_Z7835: MUXCY_L port map (
DI => R1IN_2_ADD_1,
CI => NN_1,
S => R1IN_2(17),
LO => R1IN_2_ADD_1_CRY_0);
R1IN_3_ADD_1_S_43: XORCY port map (
LI => R1IN_3_ADD_1_AXB_43,
CI => R1IN_3_ADD_1_CRY_42,
O => R1IN_3(60));
R1IN_3_ADD_1_S_42: XORCY port map (
LI => R1IN_3_ADD_1_AXB_42,
CI => R1IN_3_ADD_1_CRY_41,
O => R1IN_3(59));
R1IN_3_ADD_1_CRY_42_Z7838: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_41,
S => R1IN_3_ADD_1_AXB_42,
LO => R1IN_3_ADD_1_CRY_42);
R1IN_3_ADD_1_S_41: XORCY port map (
LI => R1IN_3_ADD_1_AXB_41,
CI => R1IN_3_ADD_1_CRY_40,
O => R1IN_3(58));
R1IN_3_ADD_1_CRY_41_Z7840: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_40,
S => R1IN_3_ADD_1_AXB_41,
LO => R1IN_3_ADD_1_CRY_41);
R1IN_3_ADD_1_S_40: XORCY port map (
LI => R1IN_3_ADD_1_AXB_40,
CI => R1IN_3_ADD_1_CRY_39,
O => R1IN_3(57));
R1IN_3_ADD_1_CRY_40_Z7842: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_39,
S => R1IN_3_ADD_1_AXB_40,
LO => R1IN_3_ADD_1_CRY_40);
R1IN_3_ADD_1_S_39: XORCY port map (
LI => R1IN_3_ADD_1_AXB_39,
CI => R1IN_3_ADD_1_CRY_38,
O => R1IN_3(56));
R1IN_3_ADD_1_CRY_39_Z7844: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_38,
S => R1IN_3_ADD_1_AXB_39,
LO => R1IN_3_ADD_1_CRY_39);
R1IN_3_ADD_1_S_38: XORCY port map (
LI => R1IN_3_ADD_1_AXB_38,
CI => R1IN_3_ADD_1_CRY_37,
O => R1IN_3(55));
R1IN_3_ADD_1_CRY_38_Z7846: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_37,
S => R1IN_3_ADD_1_AXB_38,
LO => R1IN_3_ADD_1_CRY_38);
R1IN_3_ADD_1_S_37: XORCY port map (
LI => R1IN_3_ADD_1_AXB_37,
CI => R1IN_3_ADD_1_CRY_36,
O => R1IN_3(54));
R1IN_3_ADD_1_CRY_37_Z7848: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_36,
S => R1IN_3_ADD_1_AXB_37,
LO => R1IN_3_ADD_1_CRY_37);
R1IN_3_ADD_1_S_36: XORCY port map (
LI => R1IN_3_ADD_1_AXB_36,
CI => R1IN_3_ADD_1_CRY_35,
O => R1IN_3(53));
R1IN_3_ADD_1_CRY_36_Z7850: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_35,
S => R1IN_3_ADD_1_AXB_36,
LO => R1IN_3_ADD_1_CRY_36);
R1IN_3_ADD_1_S_35: XORCY port map (
LI => R1IN_3_ADD_1_AXB_35,
CI => R1IN_3_ADD_1_CRY_34,
O => R1IN_3(52));
R1IN_3_ADD_1_CRY_35_Z7852: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_34,
S => R1IN_3_ADD_1_AXB_35,
LO => R1IN_3_ADD_1_CRY_35);
R1IN_3_ADD_1_S_34: XORCY port map (
LI => R1IN_3_ADD_1_AXB_34,
CI => R1IN_3_ADD_1_CRY_33,
O => R1IN_3(51));
R1IN_3_ADD_1_CRY_34_Z7854: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_33,
S => R1IN_3_ADD_1_AXB_34,
LO => R1IN_3_ADD_1_CRY_34);
R1IN_3_ADD_1_S_33: XORCY port map (
LI => R1IN_3_ADD_1_AXB_33,
CI => R1IN_3_ADD_1_CRY_32,
O => R1IN_3(50));
R1IN_3_ADD_1_CRY_33_Z7856: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_32,
S => R1IN_3_ADD_1_AXB_33,
LO => R1IN_3_ADD_1_CRY_33);
R1IN_3_ADD_1_S_32: XORCY port map (
LI => R1IN_3_ADD_1_AXB_32,
CI => R1IN_3_ADD_1_CRY_31,
O => R1IN_3(49));
R1IN_3_ADD_1_CRY_32_Z7858: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_31,
S => R1IN_3_ADD_1_AXB_32,
LO => R1IN_3_ADD_1_CRY_32);
R1IN_3_ADD_1_S_31: XORCY port map (
LI => R1IN_3_ADD_1_AXB_31,
CI => R1IN_3_ADD_1_CRY_30,
O => R1IN_3(48));
R1IN_3_ADD_1_CRY_31_Z7860: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_30,
S => R1IN_3_ADD_1_AXB_31,
LO => R1IN_3_ADD_1_CRY_31);
R1IN_3_ADD_1_S_30: XORCY port map (
LI => R1IN_3_ADD_1_AXB_30,
CI => R1IN_3_ADD_1_CRY_29,
O => R1IN_3(47));
R1IN_3_ADD_1_CRY_30_Z7862: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_29,
S => R1IN_3_ADD_1_AXB_30,
LO => R1IN_3_ADD_1_CRY_30);
R1IN_3_ADD_1_S_29: XORCY port map (
LI => R1IN_3_ADD_1_AXB_29,
CI => R1IN_3_ADD_1_CRY_28,
O => R1IN_3(46));
R1IN_3_ADD_1_CRY_29_Z7864: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_28,
S => R1IN_3_ADD_1_AXB_29,
LO => R1IN_3_ADD_1_CRY_29);
R1IN_3_ADD_1_S_28: XORCY port map (
LI => R1IN_3_ADD_1_AXB_28,
CI => R1IN_3_ADD_1_CRY_27,
O => R1IN_3(45));
R1IN_3_ADD_1_CRY_28_Z7866: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_27,
S => R1IN_3_ADD_1_AXB_28,
LO => R1IN_3_ADD_1_CRY_28);
R1IN_3_ADD_1_S_27: XORCY port map (
LI => R1IN_3_ADD_1_AXB_27,
CI => R1IN_3_ADD_1_CRY_26,
O => R1IN_3(44));
R1IN_3_ADD_1_CRY_27_Z7868: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_26,
S => R1IN_3_ADD_1_AXB_27,
LO => R1IN_3_ADD_1_CRY_27);
R1IN_3_ADD_1_S_26: XORCY port map (
LI => R1IN_3_ADD_1_AXB_26,
CI => R1IN_3_ADD_1_CRY_25,
O => R1IN_3(43));
R1IN_3_ADD_1_CRY_26_Z7870: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_25,
S => R1IN_3_ADD_1_AXB_26,
LO => R1IN_3_ADD_1_CRY_26);
R1IN_3_ADD_1_S_25: XORCY port map (
LI => R1IN_3_ADD_1_AXB_25,
CI => R1IN_3_ADD_1_CRY_24,
O => R1IN_3(42));
R1IN_3_ADD_1_CRY_25_Z7872: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_24,
S => R1IN_3_ADD_1_AXB_25,
LO => R1IN_3_ADD_1_CRY_25);
R1IN_3_ADD_1_S_24: XORCY port map (
LI => R1IN_3_ADD_1_AXB_24,
CI => R1IN_3_ADD_1_CRY_23,
O => R1IN_3(41));
R1IN_3_ADD_1_CRY_24_Z7874: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_23,
S => R1IN_3_ADD_1_AXB_24,
LO => R1IN_3_ADD_1_CRY_24);
R1IN_3_ADD_1_S_23: XORCY port map (
LI => R1IN_3_ADD_1_AXB_23,
CI => R1IN_3_ADD_1_CRY_22,
O => R1IN_3(40));
R1IN_3_ADD_1_CRY_23_Z7876: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_22,
S => R1IN_3_ADD_1_AXB_23,
LO => R1IN_3_ADD_1_CRY_23);
R1IN_3_ADD_1_S_22: XORCY port map (
LI => R1IN_3_ADD_1_AXB_22,
CI => R1IN_3_ADD_1_CRY_21,
O => R1IN_3(39));
R1IN_3_ADD_1_CRY_22_Z7878: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_21,
S => R1IN_3_ADD_1_AXB_22,
LO => R1IN_3_ADD_1_CRY_22);
R1IN_3_ADD_1_S_21: XORCY port map (
LI => R1IN_3_ADD_1_AXB_21,
CI => R1IN_3_ADD_1_CRY_20,
O => R1IN_3(38));
R1IN_3_ADD_1_CRY_21_Z7880: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_20,
S => R1IN_3_ADD_1_AXB_21,
LO => R1IN_3_ADD_1_CRY_21);
R1IN_3_ADD_1_S_20: XORCY port map (
LI => R1IN_3_ADD_1_AXB_20,
CI => R1IN_3_ADD_1_CRY_19,
O => R1IN_3(37));
R1IN_3_ADD_1_CRY_20_Z7882: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_19,
S => R1IN_3_ADD_1_AXB_20,
LO => R1IN_3_ADD_1_CRY_20);
R1IN_3_ADD_1_S_19: XORCY port map (
LI => R1IN_3_ADD_1_AXB_19,
CI => R1IN_3_ADD_1_CRY_18,
O => R1IN_3(36));
R1IN_3_ADD_1_CRY_19_Z7884: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_18,
S => R1IN_3_ADD_1_AXB_19,
LO => R1IN_3_ADD_1_CRY_19);
R1IN_3_ADD_1_S_18: XORCY port map (
LI => R1IN_3_ADD_1_AXB_18,
CI => R1IN_3_ADD_1_CRY_17,
O => R1IN_3(35));
R1IN_3_ADD_1_CRY_18_Z7886: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_17,
S => R1IN_3_ADD_1_AXB_18,
LO => R1IN_3_ADD_1_CRY_18);
R1IN_3_ADD_1_S_17: XORCY port map (
LI => R1IN_3_ADD_1_AXB_17,
CI => R1IN_3_ADD_1_CRY_16,
O => R1IN_3(34));
R1IN_3_ADD_1_CRY_17_Z7888: MUXCY_L port map (
DI => NN_1,
CI => R1IN_3_ADD_1_CRY_16,
S => R1IN_3_ADD_1_AXB_17,
LO => R1IN_3_ADD_1_CRY_17);
R1IN_3_ADD_1_S_16: XORCY port map (
LI => R1IN_3_ADD_1_AXB_16,
CI => R1IN_3_ADD_1_CRY_15,
O => R1IN_3(33));
R1IN_3_ADD_1_CRY_16_Z7890: MUXCY_L port map (
DI => R1IN_3_2F(16),
CI => R1IN_3_ADD_1_CRY_15,
S => R1IN_3_ADD_1_AXB_16,
LO => R1IN_3_ADD_1_CRY_16);
R1IN_3_ADD_1_S_15: XORCY port map (
LI => R1IN_3_ADD_1_AXB_15,
CI => R1IN_3_ADD_1_CRY_14,
O => R1IN_3(32));
R1IN_3_ADD_1_CRY_15_Z7892: MUXCY_L port map (
DI => R1IN_3_2F(15),
CI => R1IN_3_ADD_1_CRY_14,
S => R1IN_3_ADD_1_AXB_15,
LO => R1IN_3_ADD_1_CRY_15);
R1IN_3_ADD_1_S_14: XORCY port map (
LI => R1IN_3_ADD_1_AXB_14,
CI => R1IN_3_ADD_1_CRY_13,
O => R1IN_3(31));
R1IN_3_ADD_1_CRY_14_Z7894: MUXCY_L port map (
DI => R1IN_3_2F(14),
CI => R1IN_3_ADD_1_CRY_13,
S => R1IN_3_ADD_1_AXB_14,
LO => R1IN_3_ADD_1_CRY_14);
R1IN_3_ADD_1_S_13: XORCY port map (
LI => R1IN_3_ADD_1_AXB_13,
CI => R1IN_3_ADD_1_CRY_12,
O => R1IN_3(30));
R1IN_3_ADD_1_CRY_13_Z7896: MUXCY_L port map (
DI => R1IN_3_2F(13),
CI => R1IN_3_ADD_1_CRY_12,
S => R1IN_3_ADD_1_AXB_13,
LO => R1IN_3_ADD_1_CRY_13);
R1IN_3_ADD_1_S_12: XORCY port map (
LI => R1IN_3_ADD_1_AXB_12,
CI => R1IN_3_ADD_1_CRY_11,
O => R1IN_3(29));
R1IN_3_ADD_1_CRY_12_Z7898: MUXCY_L port map (
DI => R1IN_3_2F(12),
CI => R1IN_3_ADD_1_CRY_11,
S => R1IN_3_ADD_1_AXB_12,
LO => R1IN_3_ADD_1_CRY_12);
R1IN_3_ADD_1_S_11: XORCY port map (
LI => R1IN_3_ADD_1_AXB_11,
CI => R1IN_3_ADD_1_CRY_10,
O => R1IN_3(28));
R1IN_3_ADD_1_CRY_11_Z7900: MUXCY_L port map (
DI => R1IN_3_2F(11),
CI => R1IN_3_ADD_1_CRY_10,
S => R1IN_3_ADD_1_AXB_11,
LO => R1IN_3_ADD_1_CRY_11);
R1IN_3_ADD_1_S_10: XORCY port map (
LI => R1IN_3_ADD_1_AXB_10,
CI => R1IN_3_ADD_1_CRY_9,
O => R1IN_3(27));
R1IN_3_ADD_1_CRY_10_Z7902: MUXCY_L port map (
DI => R1IN_3_2F(10),
CI => R1IN_3_ADD_1_CRY_9,
S => R1IN_3_ADD_1_AXB_10,
LO => R1IN_3_ADD_1_CRY_10);
R1IN_3_ADD_1_S_9: XORCY port map (
LI => R1IN_3_ADD_1_AXB_9,
CI => R1IN_3_ADD_1_CRY_8,
O => R1IN_3(26));
R1IN_3_ADD_1_CRY_9_Z7904: MUXCY_L port map (
DI => R1IN_3_2F(9),
CI => R1IN_3_ADD_1_CRY_8,
S => R1IN_3_ADD_1_AXB_9,
LO => R1IN_3_ADD_1_CRY_9);
R1IN_3_ADD_1_S_8: XORCY port map (
LI => R1IN_3_ADD_1_AXB_8,
CI => R1IN_3_ADD_1_CRY_7,
O => R1IN_3(25));
R1IN_3_ADD_1_CRY_8_Z7906: MUXCY_L port map (
DI => R1IN_3_2F(8),
CI => R1IN_3_ADD_1_CRY_7,
S => R1IN_3_ADD_1_AXB_8,
LO => R1IN_3_ADD_1_CRY_8);
R1IN_3_ADD_1_S_7: XORCY port map (
LI => R1IN_3_ADD_1_AXB_7,
CI => R1IN_3_ADD_1_CRY_6,
O => R1IN_3(24));
R1IN_3_ADD_1_CRY_7_Z7908: MUXCY_L port map (
DI => R1IN_3_2F(7),
CI => R1IN_3_ADD_1_CRY_6,
S => R1IN_3_ADD_1_AXB_7,
LO => R1IN_3_ADD_1_CRY_7);
R1IN_3_ADD_1_S_6: XORCY port map (
LI => R1IN_3_ADD_1_AXB_6,
CI => R1IN_3_ADD_1_CRY_5,
O => R1IN_3(23));
R1IN_3_ADD_1_CRY_6_Z7910: MUXCY_L port map (
DI => R1IN_3_2F(6),
CI => R1IN_3_ADD_1_CRY_5,
S => R1IN_3_ADD_1_AXB_6,
LO => R1IN_3_ADD_1_CRY_6);
R1IN_3_ADD_1_S_5: XORCY port map (
LI => R1IN_3_ADD_1_AXB_5,
CI => R1IN_3_ADD_1_CRY_4,
O => R1IN_3(22));
R1IN_3_ADD_1_CRY_5_Z7912: MUXCY_L port map (
DI => R1IN_3_2F(5),
CI => R1IN_3_ADD_1_CRY_4,
S => R1IN_3_ADD_1_AXB_5,
LO => R1IN_3_ADD_1_CRY_5);
R1IN_3_ADD_1_S_4: XORCY port map (
LI => R1IN_3_ADD_1_AXB_4,
CI => R1IN_3_ADD_1_CRY_3,
O => R1IN_3(21));
R1IN_3_ADD_1_CRY_4_Z7914: MUXCY_L port map (
DI => R1IN_3_2F(4),
CI => R1IN_3_ADD_1_CRY_3,
S => R1IN_3_ADD_1_AXB_4,
LO => R1IN_3_ADD_1_CRY_4);
R1IN_3_ADD_1_S_3: XORCY port map (
LI => R1IN_3_ADD_1_AXB_3,
CI => R1IN_3_ADD_1_CRY_2,
O => R1IN_3(20));
R1IN_3_ADD_1_CRY_3_Z7916: MUXCY_L port map (
DI => R1IN_3_2F(3),
CI => R1IN_3_ADD_1_CRY_2,
S => R1IN_3_ADD_1_AXB_3,
LO => R1IN_3_ADD_1_CRY_3);
R1IN_3_ADD_1_S_2: XORCY port map (
LI => R1IN_3_ADD_1_AXB_2,
CI => R1IN_3_ADD_1_CRY_1,
O => R1IN_3(19));
R1IN_3_ADD_1_CRY_2_Z7918: MUXCY_L port map (
DI => R1IN_3_2F(2),
CI => R1IN_3_ADD_1_CRY_1,
S => R1IN_3_ADD_1_AXB_2,
LO => R1IN_3_ADD_1_CRY_2);
R1IN_3_ADD_1_S_1: XORCY port map (
LI => R1IN_3_ADD_1_AXB_1,
CI => R1IN_3_ADD_1_CRY_0,
O => R1IN_3(18));
R1IN_3_ADD_1_CRY_1_Z7920: MUXCY_L port map (
DI => R1IN_3_2F(1),
CI => R1IN_3_ADD_1_CRY_0,
S => R1IN_3_ADD_1_AXB_1,
LO => R1IN_3_ADD_1_CRY_1);
R1IN_3_ADD_1_CRY_0_Z7921: MUXCY_L port map (
DI => R1IN_3_ADD_1,
CI => NN_1,
S => R1IN_3(17),
LO => R1IN_3_ADD_1_CRY_0);
R1IN_ADD_1_1_0_S_28_Z7922: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_28,
CI => R1IN_ADD_1_1_0_CRY_27,
O => R1IN_ADD_1_1_0_S_28);
R1IN_ADD_1_1_0_CRY_28_Z7923: MUXCY port map (
DI => R1IN_3(60),
CI => R1IN_ADD_1_1_0_CRY_27,
S => R1IN_ADD_1_1_0_AXB_28,
O => R1IN_ADD_1_1_0_CRY_28);
R1IN_ADD_1_1_0_S_27_Z7924: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_27,
CI => R1IN_ADD_1_1_0_CRY_26,
O => R1IN_ADD_1_1_0_S_27);
R1IN_ADD_1_1_0_CRY_27_Z7925: MUXCY_L port map (
DI => R1IN_3(59),
CI => R1IN_ADD_1_1_0_CRY_26,
S => R1IN_ADD_1_1_0_AXB_27,
LO => R1IN_ADD_1_1_0_CRY_27);
R1IN_ADD_1_1_0_S_26_Z7926: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_26,
CI => R1IN_ADD_1_1_0_CRY_25,
O => R1IN_ADD_1_1_0_S_26);
R1IN_ADD_1_1_0_CRY_26_Z7927: MUXCY_L port map (
DI => R1IN_3(58),
CI => R1IN_ADD_1_1_0_CRY_25,
S => R1IN_ADD_1_1_0_AXB_26,
LO => R1IN_ADD_1_1_0_CRY_26);
R1IN_ADD_1_1_0_S_25_Z7928: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_25,
CI => R1IN_ADD_1_1_0_CRY_24,
O => R1IN_ADD_1_1_0_S_25);
R1IN_ADD_1_1_0_CRY_25_Z7929: MUXCY_L port map (
DI => R1IN_3(57),
CI => R1IN_ADD_1_1_0_CRY_24,
S => R1IN_ADD_1_1_0_AXB_25,
LO => R1IN_ADD_1_1_0_CRY_25);
R1IN_ADD_1_1_0_S_24_Z7930: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_24,
CI => R1IN_ADD_1_1_0_CRY_23,
O => R1IN_ADD_1_1_0_S_24);
R1IN_ADD_1_1_0_CRY_24_Z7931: MUXCY_L port map (
DI => R1IN_3(56),
CI => R1IN_ADD_1_1_0_CRY_23,
S => R1IN_ADD_1_1_0_AXB_24,
LO => R1IN_ADD_1_1_0_CRY_24);
R1IN_ADD_1_1_0_S_23_Z7932: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_23,
CI => R1IN_ADD_1_1_0_CRY_22,
O => R1IN_ADD_1_1_0_S_23);
R1IN_ADD_1_1_0_CRY_23_Z7933: MUXCY_L port map (
DI => R1IN_3(55),
CI => R1IN_ADD_1_1_0_CRY_22,
S => R1IN_ADD_1_1_0_AXB_23,
LO => R1IN_ADD_1_1_0_CRY_23);
R1IN_ADD_1_1_0_S_22_Z7934: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_22,
CI => R1IN_ADD_1_1_0_CRY_21,
O => R1IN_ADD_1_1_0_S_22);
R1IN_ADD_1_1_0_CRY_22_Z7935: MUXCY_L port map (
DI => R1IN_3(54),
CI => R1IN_ADD_1_1_0_CRY_21,
S => R1IN_ADD_1_1_0_AXB_22,
LO => R1IN_ADD_1_1_0_CRY_22);
R1IN_ADD_1_1_0_S_21_Z7936: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_21,
CI => R1IN_ADD_1_1_0_CRY_20,
O => R1IN_ADD_1_1_0_S_21);
R1IN_ADD_1_1_0_CRY_21_Z7937: MUXCY_L port map (
DI => R1IN_3(53),
CI => R1IN_ADD_1_1_0_CRY_20,
S => R1IN_ADD_1_1_0_AXB_21,
LO => R1IN_ADD_1_1_0_CRY_21);
R1IN_ADD_1_1_0_S_20: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_20,
CI => R1IN_ADD_1_1_0_CRY_19,
O => N_1913);
R1IN_ADD_1_1_0_CRY_20_Z7939: MUXCY_L port map (
DI => R1IN_3(52),
CI => R1IN_ADD_1_1_0_CRY_19,
S => R1IN_ADD_1_1_0_AXB_20,
LO => R1IN_ADD_1_1_0_CRY_20);
R1IN_ADD_1_1_0_S_19: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_19,
CI => R1IN_ADD_1_1_0_CRY_18,
O => N_1912);
R1IN_ADD_1_1_0_CRY_19_Z7941: MUXCY_L port map (
DI => R1IN_3(51),
CI => R1IN_ADD_1_1_0_CRY_18,
S => R1IN_ADD_1_1_0_AXB_19,
LO => R1IN_ADD_1_1_0_CRY_19);
R1IN_ADD_1_1_0_S_18: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_18,
CI => R1IN_ADD_1_1_0_CRY_17,
O => N_1911);
R1IN_ADD_1_1_0_CRY_18_Z7943: MUXCY_L port map (
DI => R1IN_3(50),
CI => R1IN_ADD_1_1_0_CRY_17,
S => R1IN_ADD_1_1_0_AXB_18,
LO => R1IN_ADD_1_1_0_CRY_18);
R1IN_ADD_1_1_0_S_17: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_17,
CI => R1IN_ADD_1_1_0_CRY_16,
O => N_1910);
R1IN_ADD_1_1_0_CRY_17_Z7945: MUXCY_L port map (
DI => R1IN_3(49),
CI => R1IN_ADD_1_1_0_CRY_16,
S => R1IN_ADD_1_1_0_AXB_17,
LO => R1IN_ADD_1_1_0_CRY_17);
R1IN_ADD_1_1_0_S_16: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_16,
CI => R1IN_ADD_1_1_0_CRY_15,
O => N_1909);
R1IN_ADD_1_1_0_CRY_16_Z7947: MUXCY_L port map (
DI => R1IN_3(48),
CI => R1IN_ADD_1_1_0_CRY_15,
S => R1IN_ADD_1_1_0_AXB_16,
LO => R1IN_ADD_1_1_0_CRY_16);
R1IN_ADD_1_1_0_S_15: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_15,
CI => R1IN_ADD_1_1_0_CRY_14,
O => N_1908);
R1IN_ADD_1_1_0_CRY_15_Z7949: MUXCY_L port map (
DI => R1IN_3(47),
CI => R1IN_ADD_1_1_0_CRY_14,
S => R1IN_ADD_1_1_0_AXB_15,
LO => R1IN_ADD_1_1_0_CRY_15);
R1IN_ADD_1_1_0_S_14: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_14,
CI => R1IN_ADD_1_1_0_CRY_13,
O => N_1907);
R1IN_ADD_1_1_0_CRY_14_Z7951: MUXCY_L port map (
DI => R1IN_3(46),
CI => R1IN_ADD_1_1_0_CRY_13,
S => R1IN_ADD_1_1_0_AXB_14,
LO => R1IN_ADD_1_1_0_CRY_14);
R1IN_ADD_1_1_0_S_13: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_13,
CI => R1IN_ADD_1_1_0_CRY_12,
O => N_1906);
R1IN_ADD_1_1_0_CRY_13_Z7953: MUXCY_L port map (
DI => R1IN_3(45),
CI => R1IN_ADD_1_1_0_CRY_12,
S => R1IN_ADD_1_1_0_AXB_13,
LO => R1IN_ADD_1_1_0_CRY_13);
R1IN_ADD_1_1_0_S_12: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_12,
CI => R1IN_ADD_1_1_0_CRY_11,
O => N_1905);
R1IN_ADD_1_1_0_CRY_12_Z7955: MUXCY_L port map (
DI => R1IN_3(44),
CI => R1IN_ADD_1_1_0_CRY_11,
S => R1IN_ADD_1_1_0_AXB_12,
LO => R1IN_ADD_1_1_0_CRY_12);
R1IN_ADD_1_1_0_S_11: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_11,
CI => R1IN_ADD_1_1_0_CRY_10,
O => N_1904);
R1IN_ADD_1_1_0_CRY_11_Z7957: MUXCY_L port map (
DI => R1IN_3(43),
CI => R1IN_ADD_1_1_0_CRY_10,
S => R1IN_ADD_1_1_0_AXB_11,
LO => R1IN_ADD_1_1_0_CRY_11);
R1IN_ADD_1_1_0_S_10: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_10,
CI => R1IN_ADD_1_1_0_CRY_9,
O => N_1903);
R1IN_ADD_1_1_0_CRY_10_Z7959: MUXCY_L port map (
DI => R1IN_3(42),
CI => R1IN_ADD_1_1_0_CRY_9,
S => R1IN_ADD_1_1_0_AXB_10,
LO => R1IN_ADD_1_1_0_CRY_10);
R1IN_ADD_1_1_0_S_9: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_9,
CI => R1IN_ADD_1_1_0_CRY_8,
O => N_1902);
R1IN_ADD_1_1_0_CRY_9_Z7961: MUXCY_L port map (
DI => R1IN_3(41),
CI => R1IN_ADD_1_1_0_CRY_8,
S => R1IN_ADD_1_1_0_AXB_9,
LO => R1IN_ADD_1_1_0_CRY_9);
R1IN_ADD_1_1_0_S_8: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_8,
CI => R1IN_ADD_1_1_0_CRY_7,
O => N_1901);
R1IN_ADD_1_1_0_CRY_8_Z7963: MUXCY_L port map (
DI => R1IN_3(40),
CI => R1IN_ADD_1_1_0_CRY_7,
S => R1IN_ADD_1_1_0_AXB_8,
LO => R1IN_ADD_1_1_0_CRY_8);
R1IN_ADD_1_1_0_S_7: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_7,
CI => R1IN_ADD_1_1_0_CRY_6,
O => N_1900);
R1IN_ADD_1_1_0_CRY_7_Z7965: MUXCY_L port map (
DI => R1IN_3(39),
CI => R1IN_ADD_1_1_0_CRY_6,
S => R1IN_ADD_1_1_0_AXB_7,
LO => R1IN_ADD_1_1_0_CRY_7);
R1IN_ADD_1_1_0_S_6: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_6,
CI => R1IN_ADD_1_1_0_CRY_5,
O => N_1899);
R1IN_ADD_1_1_0_CRY_6_Z7967: MUXCY_L port map (
DI => R1IN_3(38),
CI => R1IN_ADD_1_1_0_CRY_5,
S => R1IN_ADD_1_1_0_AXB_6,
LO => R1IN_ADD_1_1_0_CRY_6);
R1IN_ADD_1_1_0_S_5: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_5,
CI => R1IN_ADD_1_1_0_CRY_4,
O => N_1898);
R1IN_ADD_1_1_0_CRY_5_Z7969: MUXCY_L port map (
DI => R1IN_3(37),
CI => R1IN_ADD_1_1_0_CRY_4,
S => R1IN_ADD_1_1_0_AXB_5,
LO => R1IN_ADD_1_1_0_CRY_5);
R1IN_ADD_1_1_0_S_4: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_4,
CI => R1IN_ADD_1_1_0_CRY_3,
O => N_1897);
R1IN_ADD_1_1_0_CRY_4_Z7971: MUXCY_L port map (
DI => R1IN_3(36),
CI => R1IN_ADD_1_1_0_CRY_3,
S => R1IN_ADD_1_1_0_AXB_4,
LO => R1IN_ADD_1_1_0_CRY_4);
R1IN_ADD_1_1_0_S_3: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_3,
CI => R1IN_ADD_1_1_0_CRY_2,
O => N_1896);
R1IN_ADD_1_1_0_CRY_3_Z7973: MUXCY_L port map (
DI => R1IN_3(35),
CI => R1IN_ADD_1_1_0_CRY_2,
S => R1IN_ADD_1_1_0_AXB_3,
LO => R1IN_ADD_1_1_0_CRY_3);
R1IN_ADD_1_1_0_S_2: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_2,
CI => R1IN_ADD_1_1_0_CRY_1,
O => N_1895);
R1IN_ADD_1_1_0_CRY_2_Z7975: MUXCY_L port map (
DI => R1IN_3(34),
CI => R1IN_ADD_1_1_0_CRY_1,
S => R1IN_ADD_1_1_0_AXB_2,
LO => R1IN_ADD_1_1_0_CRY_2);
R1IN_ADD_1_1_0_S_1: XORCY port map (
LI => R1IN_ADD_1_1_0_AXB_1,
CI => R1IN_ADD_1_1_0_CRY_0,
O => N_1894);
R1IN_ADD_1_1_0_CRY_1_Z7977: MUXCY_L port map (
DI => R1IN_3(33),
CI => R1IN_ADD_1_1_0_CRY_0,
S => R1IN_ADD_1_1_0_AXB_1,
LO => R1IN_ADD_1_1_0_CRY_1);
R1IN_ADD_1_1_0_CRY_0_Z7978: MUXCY_L port map (
DI => R1IN_3(32),
CI => NN_2,
S => R1IN_ADD_1_1_0_AXB_0,
LO => R1IN_ADD_1_1_0_CRY_0);
R1IN_ADD_1_1_S_28_Z7979: XORCY port map (
LI => R1IN_ADD_1_1_AXB_28,
CI => R1IN_ADD_1_1_CRY_27,
O => R1IN_ADD_1_1_S_28);
R1IN_ADD_1_1_S_27_Z7980: XORCY port map (
LI => R1IN_ADD_1_1_AXB_27,
CI => R1IN_ADD_1_1_CRY_26,
O => R1IN_ADD_1_1_S_27);
R1IN_ADD_1_1_CRY_27_Z7981: MUXCY_L port map (
DI => R1IN_3(59),
CI => R1IN_ADD_1_1_CRY_26,
S => R1IN_ADD_1_1_AXB_27,
LO => R1IN_ADD_1_1_CRY_27);
R1IN_ADD_1_1_S_26_Z7982: XORCY port map (
LI => R1IN_ADD_1_1_AXB_26,
CI => R1IN_ADD_1_1_CRY_25,
O => R1IN_ADD_1_1_S_26);
R1IN_ADD_1_1_CRY_26_Z7983: MUXCY_L port map (
DI => R1IN_3(58),
CI => R1IN_ADD_1_1_CRY_25,
S => R1IN_ADD_1_1_AXB_26,
LO => R1IN_ADD_1_1_CRY_26);
R1IN_ADD_1_1_S_25_Z7984: XORCY port map (
LI => R1IN_ADD_1_1_AXB_25,
CI => R1IN_ADD_1_1_CRY_24,
O => R1IN_ADD_1_1_S_25);
R1IN_ADD_1_1_CRY_25_Z7985: MUXCY_L port map (
DI => R1IN_3(57),
CI => R1IN_ADD_1_1_CRY_24,
S => R1IN_ADD_1_1_AXB_25,
LO => R1IN_ADD_1_1_CRY_25);
R1IN_ADD_1_1_S_24_Z7986: XORCY port map (
LI => R1IN_ADD_1_1_AXB_24,
CI => R1IN_ADD_1_1_CRY_23,
O => R1IN_ADD_1_1_S_24);
R1IN_ADD_1_1_CRY_24_Z7987: MUXCY_L port map (
DI => R1IN_3(56),
CI => R1IN_ADD_1_1_CRY_23,
S => R1IN_ADD_1_1_AXB_24,
LO => R1IN_ADD_1_1_CRY_24);
R1IN_ADD_1_1_S_23_Z7988: XORCY port map (
LI => R1IN_ADD_1_1_AXB_23,
CI => R1IN_ADD_1_1_CRY_22,
O => R1IN_ADD_1_1_S_23);
R1IN_ADD_1_1_CRY_23_Z7989: MUXCY_L port map (
DI => R1IN_3(55),
CI => R1IN_ADD_1_1_CRY_22,
S => R1IN_ADD_1_1_AXB_23,
LO => R1IN_ADD_1_1_CRY_23);
R1IN_ADD_1_1_S_22_Z7990: XORCY port map (
LI => R1IN_ADD_1_1_AXB_22,
CI => R1IN_ADD_1_1_CRY_21,
O => R1IN_ADD_1_1_S_22);
R1IN_ADD_1_1_CRY_22_Z7991: MUXCY_L port map (
DI => R1IN_3(54),
CI => R1IN_ADD_1_1_CRY_21,
S => R1IN_ADD_1_1_AXB_22,
LO => R1IN_ADD_1_1_CRY_22);
R1IN_ADD_1_1_S_21_Z7992: XORCY port map (
LI => R1IN_ADD_1_1_AXB_21,
CI => R1IN_ADD_1_1_CRY_20,
O => R1IN_ADD_1_1_S_21);
R1IN_ADD_1_1_CRY_21_Z7993: MUXCY_L port map (
DI => R1IN_3(53),
CI => R1IN_ADD_1_1_CRY_20,
S => R1IN_ADD_1_1_AXB_21,
LO => R1IN_ADD_1_1_CRY_21);
R1IN_ADD_1_1_S_20: XORCY port map (
LI => R1IN_ADD_1_1_AXB_20,
CI => R1IN_ADD_1_1_CRY_19,
O => N_1577);
R1IN_ADD_1_1_CRY_20_Z7995: MUXCY_L port map (
DI => R1IN_3(52),
CI => R1IN_ADD_1_1_CRY_19,
S => R1IN_ADD_1_1_AXB_20,
LO => R1IN_ADD_1_1_CRY_20);
R1IN_ADD_1_1_S_19: XORCY port map (
LI => R1IN_ADD_1_1_AXB_19,
CI => R1IN_ADD_1_1_CRY_18,
O => N_1575);
R1IN_ADD_1_1_CRY_19_Z7997: MUXCY_L port map (
DI => R1IN_3(51),
CI => R1IN_ADD_1_1_CRY_18,
S => R1IN_ADD_1_1_AXB_19,
LO => R1IN_ADD_1_1_CRY_19);
R1IN_ADD_1_1_S_18: XORCY port map (
LI => R1IN_ADD_1_1_AXB_18,
CI => R1IN_ADD_1_1_CRY_17,
O => N_1573);
R1IN_ADD_1_1_CRY_18_Z7999: MUXCY_L port map (
DI => R1IN_3(50),
CI => R1IN_ADD_1_1_CRY_17,
S => R1IN_ADD_1_1_AXB_18,
LO => R1IN_ADD_1_1_CRY_18);
R1IN_ADD_1_1_S_17: XORCY port map (
LI => R1IN_ADD_1_1_AXB_17,
CI => R1IN_ADD_1_1_CRY_16,
O => N_1571);
R1IN_ADD_1_1_CRY_17_Z8001: MUXCY_L port map (
DI => R1IN_3(49),
CI => R1IN_ADD_1_1_CRY_16,
S => R1IN_ADD_1_1_AXB_17,
LO => R1IN_ADD_1_1_CRY_17);
R1IN_ADD_1_1_S_16: XORCY port map (
LI => R1IN_ADD_1_1_AXB_16,
CI => R1IN_ADD_1_1_CRY_15,
O => N_1569);
R1IN_ADD_1_1_CRY_16_Z8003: MUXCY_L port map (
DI => R1IN_3(48),
CI => R1IN_ADD_1_1_CRY_15,
S => R1IN_ADD_1_1_AXB_16,
LO => R1IN_ADD_1_1_CRY_16);
R1IN_ADD_1_1_S_15: XORCY port map (
LI => R1IN_ADD_1_1_AXB_15,
CI => R1IN_ADD_1_1_CRY_14,
O => N_1567);
R1IN_ADD_1_1_CRY_15_Z8005: MUXCY_L port map (
DI => R1IN_3(47),
CI => R1IN_ADD_1_1_CRY_14,
S => R1IN_ADD_1_1_AXB_15,
LO => R1IN_ADD_1_1_CRY_15);
R1IN_ADD_1_1_S_14: XORCY port map (
LI => R1IN_ADD_1_1_AXB_14,
CI => R1IN_ADD_1_1_CRY_13,
O => N_1565);
R1IN_ADD_1_1_CRY_14_Z8007: MUXCY_L port map (
DI => R1IN_3(46),
CI => R1IN_ADD_1_1_CRY_13,
S => R1IN_ADD_1_1_AXB_14,
LO => R1IN_ADD_1_1_CRY_14);
R1IN_ADD_1_1_S_13: XORCY port map (
LI => R1IN_ADD_1_1_AXB_13,
CI => R1IN_ADD_1_1_CRY_12,
O => N_1563);
R1IN_ADD_1_1_CRY_13_Z8009: MUXCY_L port map (
DI => R1IN_3(45),
CI => R1IN_ADD_1_1_CRY_12,
S => R1IN_ADD_1_1_AXB_13,
LO => R1IN_ADD_1_1_CRY_13);
R1IN_ADD_1_1_S_12: XORCY port map (
LI => R1IN_ADD_1_1_AXB_12,
CI => R1IN_ADD_1_1_CRY_11,
O => N_1561);
R1IN_ADD_1_1_CRY_12_Z8011: MUXCY_L port map (
DI => R1IN_3(44),
CI => R1IN_ADD_1_1_CRY_11,
S => R1IN_ADD_1_1_AXB_12,
LO => R1IN_ADD_1_1_CRY_12);
R1IN_ADD_1_1_S_11: XORCY port map (
LI => R1IN_ADD_1_1_AXB_11,
CI => R1IN_ADD_1_1_CRY_10,
O => N_1559);
R1IN_ADD_1_1_CRY_11_Z8013: MUXCY_L port map (
DI => R1IN_3(43),
CI => R1IN_ADD_1_1_CRY_10,
S => R1IN_ADD_1_1_AXB_11,
LO => R1IN_ADD_1_1_CRY_11);
R1IN_ADD_1_1_S_10: XORCY port map (
LI => R1IN_ADD_1_1_AXB_10,
CI => R1IN_ADD_1_1_CRY_9,
O => N_1557);
R1IN_ADD_1_1_CRY_10_Z8015: MUXCY_L port map (
DI => R1IN_3(42),
CI => R1IN_ADD_1_1_CRY_9,
S => R1IN_ADD_1_1_AXB_10,
LO => R1IN_ADD_1_1_CRY_10);
R1IN_ADD_1_1_S_9: XORCY port map (
LI => R1IN_ADD_1_1_AXB_9,
CI => R1IN_ADD_1_1_CRY_8,
O => N_1555);
R1IN_ADD_1_1_CRY_9_Z8017: MUXCY_L port map (
DI => R1IN_3(41),
CI => R1IN_ADD_1_1_CRY_8,
S => R1IN_ADD_1_1_AXB_9,
LO => R1IN_ADD_1_1_CRY_9);
R1IN_ADD_1_1_S_8: XORCY port map (
LI => R1IN_ADD_1_1_AXB_8,
CI => R1IN_ADD_1_1_CRY_7,
O => N_1553);
R1IN_ADD_1_1_CRY_8_Z8019: MUXCY_L port map (
DI => R1IN_3(40),
CI => R1IN_ADD_1_1_CRY_7,
S => R1IN_ADD_1_1_AXB_8,
LO => R1IN_ADD_1_1_CRY_8);
R1IN_ADD_1_1_S_7: XORCY port map (
LI => R1IN_ADD_1_1_AXB_7,
CI => R1IN_ADD_1_1_CRY_6,
O => N_1551);
R1IN_ADD_1_1_CRY_7_Z8021: MUXCY_L port map (
DI => R1IN_3(39),
CI => R1IN_ADD_1_1_CRY_6,
S => R1IN_ADD_1_1_AXB_7,
LO => R1IN_ADD_1_1_CRY_7);
R1IN_ADD_1_1_S_6: XORCY port map (
LI => R1IN_ADD_1_1_AXB_6,
CI => R1IN_ADD_1_1_CRY_5,
O => N_1549);
R1IN_ADD_1_1_CRY_6_Z8023: MUXCY_L port map (
DI => R1IN_3(38),
CI => R1IN_ADD_1_1_CRY_5,
S => R1IN_ADD_1_1_AXB_6,
LO => R1IN_ADD_1_1_CRY_6);
R1IN_ADD_1_1_S_5: XORCY port map (
LI => R1IN_ADD_1_1_AXB_5,
CI => R1IN_ADD_1_1_CRY_4,
O => N_1547);
R1IN_ADD_1_1_CRY_5_Z8025: MUXCY_L port map (
DI => R1IN_3(37),
CI => R1IN_ADD_1_1_CRY_4,
S => R1IN_ADD_1_1_AXB_5,
LO => R1IN_ADD_1_1_CRY_5);
R1IN_ADD_1_1_S_4: XORCY port map (
LI => R1IN_ADD_1_1_AXB_4,
CI => R1IN_ADD_1_1_CRY_3,
O => N_1545);
R1IN_ADD_1_1_CRY_4_Z8027: MUXCY_L port map (
DI => R1IN_3(36),
CI => R1IN_ADD_1_1_CRY_3,
S => R1IN_ADD_1_1_AXB_4,
LO => R1IN_ADD_1_1_CRY_4);
R1IN_ADD_1_1_S_3: XORCY port map (
LI => R1IN_ADD_1_1_AXB_3,
CI => R1IN_ADD_1_1_CRY_2,
O => N_1543);
R1IN_ADD_1_1_CRY_3_Z8029: MUXCY_L port map (
DI => R1IN_3(35),
CI => R1IN_ADD_1_1_CRY_2,
S => R1IN_ADD_1_1_AXB_3,
LO => R1IN_ADD_1_1_CRY_3);
R1IN_ADD_1_1_S_2: XORCY port map (
LI => R1IN_ADD_1_1_AXB_2,
CI => R1IN_ADD_1_1_CRY_1,
O => N_1541);
R1IN_ADD_1_1_CRY_2_Z8031: MUXCY_L port map (
DI => R1IN_3(34),
CI => R1IN_ADD_1_1_CRY_1,
S => R1IN_ADD_1_1_AXB_2,
LO => R1IN_ADD_1_1_CRY_2);
R1IN_ADD_1_1_S_1: XORCY port map (
LI => R1IN_ADD_1_1_AXB_1,
CI => R1IN_ADD_1_1_CRY_0,
O => N_1539);
R1IN_ADD_1_1_CRY_1_Z8033: MUXCY_L port map (
DI => R1IN_3(33),
CI => R1IN_ADD_1_1_CRY_0,
S => R1IN_ADD_1_1_AXB_1,
LO => R1IN_ADD_1_1_CRY_1);
R1IN_ADD_1_1_CRY_0_Z8034: MUXCY_L port map (
DI => R1IN_3(32),
CI => NN_1,
S => R1IN_ADD_1_1_AXB_0,
LO => R1IN_ADD_1_1_CRY_0);
R1IN_ADD_1_0_S_31: XORCY port map (
LI => R1IN_ADD_1_0_AXB_31,
CI => R1IN_ADD_1_0_CRY_30,
O => R1IN_ADD_1(31));
R1IN_ADD_1_0_CRY_31_Z8036: MUXCY port map (
DI => R1IN_3(31),
CI => R1IN_ADD_1_0_CRY_30,
S => R1IN_ADD_1_0_AXB_31,
O => R1IN_ADD_1_0_CRY_31);
R1IN_ADD_1_0_S_30: XORCY port map (
LI => R1IN_ADD_1_0_AXB_30,
CI => R1IN_ADD_1_0_CRY_29,
O => R1IN_ADD_1(30));
R1IN_ADD_1_0_CRY_30_Z8038: MUXCY_L port map (
DI => R1IN_3(30),
CI => R1IN_ADD_1_0_CRY_29,
S => R1IN_ADD_1_0_AXB_30,
LO => R1IN_ADD_1_0_CRY_30);
R1IN_ADD_1_0_S_29: XORCY port map (
LI => R1IN_ADD_1_0_AXB_29,
CI => R1IN_ADD_1_0_CRY_28,
O => R1IN_ADD_1(29));
R1IN_ADD_1_0_CRY_29_Z8040: MUXCY_L port map (
DI => R1IN_3(29),
CI => R1IN_ADD_1_0_CRY_28,
S => R1IN_ADD_1_0_AXB_29,
LO => R1IN_ADD_1_0_CRY_29);
R1IN_ADD_1_0_S_28: XORCY port map (
LI => R1IN_ADD_1_0_AXB_28,
CI => R1IN_ADD_1_0_CRY_27,
O => R1IN_ADD_1(28));
R1IN_ADD_1_0_CRY_28_Z8042: MUXCY_L port map (
DI => R1IN_3(28),
CI => R1IN_ADD_1_0_CRY_27,
S => R1IN_ADD_1_0_AXB_28,
LO => R1IN_ADD_1_0_CRY_28);
R1IN_ADD_1_0_S_27: XORCY port map (
LI => R1IN_ADD_1_0_AXB_27,
CI => R1IN_ADD_1_0_CRY_26,
O => R1IN_ADD_1(27));
R1IN_ADD_1_0_CRY_27_Z8044: MUXCY_L port map (
DI => R1IN_3(27),
CI => R1IN_ADD_1_0_CRY_26,
S => R1IN_ADD_1_0_AXB_27,
LO => R1IN_ADD_1_0_CRY_27);
R1IN_ADD_1_0_S_26: XORCY port map (
LI => R1IN_ADD_1_0_AXB_26,
CI => R1IN_ADD_1_0_CRY_25,
O => R1IN_ADD_1(26));
R1IN_ADD_1_0_CRY_26_Z8046: MUXCY_L port map (
DI => R1IN_3(26),
CI => R1IN_ADD_1_0_CRY_25,
S => R1IN_ADD_1_0_AXB_26,
LO => R1IN_ADD_1_0_CRY_26);
R1IN_ADD_1_0_S_25: XORCY port map (
LI => R1IN_ADD_1_0_AXB_25,
CI => R1IN_ADD_1_0_CRY_24,
O => R1IN_ADD_1(25));
R1IN_ADD_1_0_CRY_25_Z8048: MUXCY_L port map (
DI => R1IN_3(25),
CI => R1IN_ADD_1_0_CRY_24,
S => R1IN_ADD_1_0_AXB_25,
LO => R1IN_ADD_1_0_CRY_25);
R1IN_ADD_1_0_S_24: XORCY port map (
LI => R1IN_ADD_1_0_AXB_24,
CI => R1IN_ADD_1_0_CRY_23,
O => R1IN_ADD_1(24));
R1IN_ADD_1_0_CRY_24_Z8050: MUXCY_L port map (
DI => R1IN_3(24),
CI => R1IN_ADD_1_0_CRY_23,
S => R1IN_ADD_1_0_AXB_24,
LO => R1IN_ADD_1_0_CRY_24);
R1IN_ADD_1_0_S_23: XORCY port map (
LI => R1IN_ADD_1_0_AXB_23,
CI => R1IN_ADD_1_0_CRY_22,
O => R1IN_ADD_1(23));
R1IN_ADD_1_0_CRY_23_Z8052: MUXCY_L port map (
DI => R1IN_3(23),
CI => R1IN_ADD_1_0_CRY_22,
S => R1IN_ADD_1_0_AXB_23,
LO => R1IN_ADD_1_0_CRY_23);
R1IN_ADD_1_0_S_22: XORCY port map (
LI => R1IN_ADD_1_0_AXB_22,
CI => R1IN_ADD_1_0_CRY_21,
O => R1IN_ADD_1(22));
R1IN_ADD_1_0_CRY_22_Z8054: MUXCY_L port map (
DI => R1IN_3(22),
CI => R1IN_ADD_1_0_CRY_21,
S => R1IN_ADD_1_0_AXB_22,
LO => R1IN_ADD_1_0_CRY_22);
R1IN_ADD_1_0_S_21: XORCY port map (
LI => R1IN_ADD_1_0_AXB_21,
CI => R1IN_ADD_1_0_CRY_20,
O => R1IN_ADD_1(21));
R1IN_ADD_1_0_CRY_21_Z8056: MUXCY_L port map (
DI => R1IN_3(21),
CI => R1IN_ADD_1_0_CRY_20,
S => R1IN_ADD_1_0_AXB_21,
LO => R1IN_ADD_1_0_CRY_21);
R1IN_ADD_1_0_S_20: XORCY port map (
LI => R1IN_ADD_1_0_AXB_20,
CI => R1IN_ADD_1_0_CRY_19,
O => R1IN_ADD_1(20));
R1IN_ADD_1_0_CRY_20_Z8058: MUXCY_L port map (
DI => R1IN_3(20),
CI => R1IN_ADD_1_0_CRY_19,
S => R1IN_ADD_1_0_AXB_20,
LO => R1IN_ADD_1_0_CRY_20);
R1IN_ADD_1_0_S_19: XORCY port map (
LI => R1IN_ADD_1_0_AXB_19,
CI => R1IN_ADD_1_0_CRY_18,
O => R1IN_ADD_1(19));
R1IN_ADD_1_0_CRY_19_Z8060: MUXCY_L port map (
DI => R1IN_3(19),
CI => R1IN_ADD_1_0_CRY_18,
S => R1IN_ADD_1_0_AXB_19,
LO => R1IN_ADD_1_0_CRY_19);
R1IN_ADD_1_0_S_18: XORCY port map (
LI => R1IN_ADD_1_0_AXB_18,
CI => R1IN_ADD_1_0_CRY_17,
O => R1IN_ADD_1(18));
R1IN_ADD_1_0_CRY_18_Z8062: MUXCY_L port map (
DI => R1IN_3(18),
CI => R1IN_ADD_1_0_CRY_17,
S => R1IN_ADD_1_0_AXB_18,
LO => R1IN_ADD_1_0_CRY_18);
R1IN_ADD_1_0_S_17: XORCY port map (
LI => R1IN_ADD_1_0_AXB_17,
CI => R1IN_ADD_1_0_CRY_16,
O => R1IN_ADD_1(17));
R1IN_ADD_1_0_CRY_17_Z8064: MUXCY_L port map (
DI => R1IN_3(17),
CI => R1IN_ADD_1_0_CRY_16,
S => R1IN_ADD_1_0_AXB_17,
LO => R1IN_ADD_1_0_CRY_17);
R1IN_ADD_1_0_S_16: XORCY port map (
LI => R1IN_ADD_1_0_AXB_16,
CI => R1IN_ADD_1_0_CRY_15,
O => R1IN_ADD_1(16));
R1IN_ADD_1_0_CRY_16_Z8066: MUXCY_L port map (
DI => R1IN_2F(16),
CI => R1IN_ADD_1_0_CRY_15,
S => R1IN_ADD_1_0_AXB_16,
LO => R1IN_ADD_1_0_CRY_16);
R1IN_ADD_1_0_S_15: XORCY port map (
LI => R1IN_ADD_1_0_AXB_15,
CI => R1IN_ADD_1_0_CRY_14,
O => R1IN_ADD_1(15));
R1IN_ADD_1_0_CRY_15_Z8068: MUXCY_L port map (
DI => R1IN_2F(15),
CI => R1IN_ADD_1_0_CRY_14,
S => R1IN_ADD_1_0_AXB_15,
LO => R1IN_ADD_1_0_CRY_15);
R1IN_ADD_1_0_S_14: XORCY port map (
LI => R1IN_ADD_1_0_AXB_14,
CI => R1IN_ADD_1_0_CRY_13,
O => R1IN_ADD_1(14));
R1IN_ADD_1_0_CRY_14_Z8070: MUXCY_L port map (
DI => R1IN_2F(14),
CI => R1IN_ADD_1_0_CRY_13,
S => R1IN_ADD_1_0_AXB_14,
LO => R1IN_ADD_1_0_CRY_14);
R1IN_ADD_1_0_S_13: XORCY port map (
LI => R1IN_ADD_1_0_AXB_13,
CI => R1IN_ADD_1_0_CRY_12,
O => R1IN_ADD_1(13));
R1IN_ADD_1_0_CRY_13_Z8072: MUXCY_L port map (
DI => R1IN_2F(13),
CI => R1IN_ADD_1_0_CRY_12,
S => R1IN_ADD_1_0_AXB_13,
LO => R1IN_ADD_1_0_CRY_13);
R1IN_ADD_1_0_S_12: XORCY port map (
LI => R1IN_ADD_1_0_AXB_12,
CI => R1IN_ADD_1_0_CRY_11,
O => R1IN_ADD_1(12));
R1IN_ADD_1_0_CRY_12_Z8074: MUXCY_L port map (
DI => R1IN_2F(12),
CI => R1IN_ADD_1_0_CRY_11,
S => R1IN_ADD_1_0_AXB_12,
LO => R1IN_ADD_1_0_CRY_12);
R1IN_ADD_1_0_S_11: XORCY port map (
LI => R1IN_ADD_1_0_AXB_11,
CI => R1IN_ADD_1_0_CRY_10,
O => R1IN_ADD_1(11));
R1IN_ADD_1_0_CRY_11_Z8076: MUXCY_L port map (
DI => R1IN_2F(11),
CI => R1IN_ADD_1_0_CRY_10,
S => R1IN_ADD_1_0_AXB_11,
LO => R1IN_ADD_1_0_CRY_11);
R1IN_ADD_1_0_S_10: XORCY port map (
LI => R1IN_ADD_1_0_AXB_10,
CI => R1IN_ADD_1_0_CRY_9,
O => R1IN_ADD_1(10));
R1IN_ADD_1_0_CRY_10_Z8078: MUXCY_L port map (
DI => R1IN_2F(10),
CI => R1IN_ADD_1_0_CRY_9,
S => R1IN_ADD_1_0_AXB_10,
LO => R1IN_ADD_1_0_CRY_10);
R1IN_ADD_1_0_S_9: XORCY port map (
LI => R1IN_ADD_1_0_AXB_9,
CI => R1IN_ADD_1_0_CRY_8,
O => R1IN_ADD_1(9));
R1IN_ADD_1_0_CRY_9_Z8080: MUXCY_L port map (
DI => R1IN_2F(9),
CI => R1IN_ADD_1_0_CRY_8,
S => R1IN_ADD_1_0_AXB_9,
LO => R1IN_ADD_1_0_CRY_9);
R1IN_ADD_1_0_S_8: XORCY port map (
LI => R1IN_ADD_1_0_AXB_8,
CI => R1IN_ADD_1_0_CRY_7,
O => R1IN_ADD_1(8));
R1IN_ADD_1_0_CRY_8_Z8082: MUXCY_L port map (
DI => R1IN_2F(8),
CI => R1IN_ADD_1_0_CRY_7,
S => R1IN_ADD_1_0_AXB_8,
LO => R1IN_ADD_1_0_CRY_8);
R1IN_ADD_1_0_S_7: XORCY port map (
LI => R1IN_ADD_1_0_AXB_7,
CI => R1IN_ADD_1_0_CRY_6,
O => R1IN_ADD_1(7));
R1IN_ADD_1_0_CRY_7_Z8084: MUXCY_L port map (
DI => R1IN_2F(7),
CI => R1IN_ADD_1_0_CRY_6,
S => R1IN_ADD_1_0_AXB_7,
LO => R1IN_ADD_1_0_CRY_7);
R1IN_ADD_1_0_S_6: XORCY port map (
LI => R1IN_ADD_1_0_AXB_6,
CI => R1IN_ADD_1_0_CRY_5,
O => R1IN_ADD_1(6));
R1IN_ADD_1_0_CRY_6_Z8086: MUXCY_L port map (
DI => R1IN_2F(6),
CI => R1IN_ADD_1_0_CRY_5,
S => R1IN_ADD_1_0_AXB_6,
LO => R1IN_ADD_1_0_CRY_6);
R1IN_ADD_1_0_S_5: XORCY port map (
LI => R1IN_ADD_1_0_AXB_5,
CI => R1IN_ADD_1_0_CRY_4,
O => R1IN_ADD_1(5));
R1IN_ADD_1_0_CRY_5_Z8088: MUXCY_L port map (
DI => R1IN_2F(5),
CI => R1IN_ADD_1_0_CRY_4,
S => R1IN_ADD_1_0_AXB_5,
LO => R1IN_ADD_1_0_CRY_5);
R1IN_ADD_1_0_S_4: XORCY port map (
LI => R1IN_ADD_1_0_AXB_4,
CI => R1IN_ADD_1_0_CRY_3,
O => R1IN_ADD_1(4));
R1IN_ADD_1_0_CRY_4_Z8090: MUXCY_L port map (
DI => R1IN_2F(4),
CI => R1IN_ADD_1_0_CRY_3,
S => R1IN_ADD_1_0_AXB_4,
LO => R1IN_ADD_1_0_CRY_4);
R1IN_ADD_1_0_S_3: XORCY port map (
LI => R1IN_ADD_1_0_AXB_3,
CI => R1IN_ADD_1_0_CRY_2,
O => R1IN_ADD_1(3));
R1IN_ADD_1_0_CRY_3_Z8092: MUXCY_L port map (
DI => R1IN_2F(3),
CI => R1IN_ADD_1_0_CRY_2,
S => R1IN_ADD_1_0_AXB_3,
LO => R1IN_ADD_1_0_CRY_3);
R1IN_ADD_1_0_S_2: XORCY port map (
LI => R1IN_ADD_1_0_AXB_2,
CI => R1IN_ADD_1_0_CRY_1,
O => R1IN_ADD_1(2));
R1IN_ADD_1_0_CRY_2_Z8094: MUXCY_L port map (
DI => R1IN_2F(2),
CI => R1IN_ADD_1_0_CRY_1,
S => R1IN_ADD_1_0_AXB_2,
LO => R1IN_ADD_1_0_CRY_2);
R1IN_ADD_1_0_S_1: XORCY port map (
LI => R1IN_ADD_1_0_AXB_1,
CI => R1IN_ADD_1_0_CRY_0,
O => R1IN_ADD_1(1));
R1IN_ADD_1_0_CRY_1_Z8096: MUXCY_L port map (
DI => R1IN_2F(1),
CI => R1IN_ADD_1_0_CRY_0,
S => R1IN_ADD_1_0_AXB_1,
LO => R1IN_ADD_1_0_CRY_1);
R1IN_ADD_1_0_CRY_0_Z8097: MUXCY_L port map (
DI => R1IN_2F(0),
CI => NN_1,
S => R1IN_ADD_1(0),
LO => R1IN_ADD_1_0_CRY_0);
R1IN_ADD_2_1_0_S_51_Z8098: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_51,
CI => R1IN_ADD_2_1_0_CRY_50,
O => R1IN_ADD_2_1_0_S_51);
R1IN_ADD_2_1_0_S_50_Z8099: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_50,
CI => R1IN_ADD_2_1_0_CRY_49,
O => R1IN_ADD_2_1_0_S_50);
R1IN_ADD_2_1_0_CRY_50_Z8100: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_49,
S => R1IN_ADD_2_1_0_AXB_50,
LO => R1IN_ADD_2_1_0_CRY_50);
R1IN_ADD_2_1_0_S_49_Z8101: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_49,
CI => R1IN_ADD_2_1_0_CRY_48,
O => R1IN_ADD_2_1_0_S_49);
R1IN_ADD_2_1_0_CRY_49_Z8102: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_48,
S => R1IN_ADD_2_1_0_AXB_49,
LO => R1IN_ADD_2_1_0_CRY_49);
R1IN_ADD_2_1_0_S_48_Z8103: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_48,
CI => R1IN_ADD_2_1_0_CRY_47,
O => R1IN_ADD_2_1_0_S_48);
R1IN_ADD_2_1_0_CRY_48_Z8104: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_47,
S => R1IN_ADD_2_1_0_AXB_48,
LO => R1IN_ADD_2_1_0_CRY_48);
R1IN_ADD_2_1_0_S_47_Z8105: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_47,
CI => R1IN_ADD_2_1_0_CRY_46,
O => R1IN_ADD_2_1_0_S_47);
R1IN_ADD_2_1_0_CRY_47_Z8106: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_46,
S => R1IN_ADD_2_1_0_AXB_47,
LO => R1IN_ADD_2_1_0_CRY_47);
R1IN_ADD_2_1_0_S_46_Z8107: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_46,
CI => R1IN_ADD_2_1_0_CRY_45,
O => R1IN_ADD_2_1_0_S_46);
R1IN_ADD_2_1_0_CRY_46_Z8108: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_45,
S => R1IN_ADD_2_1_0_AXB_46,
LO => R1IN_ADD_2_1_0_CRY_46);
R1IN_ADD_2_1_0_S_45_Z8109: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_45,
CI => R1IN_ADD_2_1_0_CRY_44,
O => R1IN_ADD_2_1_0_S_45);
R1IN_ADD_2_1_0_CRY_45_Z8110: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_44,
S => R1IN_ADD_2_1_0_AXB_45,
LO => R1IN_ADD_2_1_0_CRY_45);
R1IN_ADD_2_1_0_S_44_Z8111: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_44,
CI => R1IN_ADD_2_1_0_CRY_43,
O => R1IN_ADD_2_1_0_S_44);
R1IN_ADD_2_1_0_CRY_44_Z8112: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_43,
S => R1IN_ADD_2_1_0_AXB_44,
LO => R1IN_ADD_2_1_0_CRY_44);
R1IN_ADD_2_1_0_S_43_Z8113: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_43,
CI => R1IN_ADD_2_1_0_CRY_42,
O => R1IN_ADD_2_1_0_S_43);
R1IN_ADD_2_1_0_CRY_43_Z8114: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_42,
S => R1IN_ADD_2_1_0_AXB_43,
LO => R1IN_ADD_2_1_0_CRY_43);
R1IN_ADD_2_1_0_S_42_Z8115: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_42,
CI => R1IN_ADD_2_1_0_CRY_41,
O => R1IN_ADD_2_1_0_S_42);
R1IN_ADD_2_1_0_CRY_42_Z8116: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_41,
S => R1IN_ADD_2_1_0_AXB_42,
LO => R1IN_ADD_2_1_0_CRY_42);
R1IN_ADD_2_1_0_S_41_Z8117: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_41,
CI => R1IN_ADD_2_1_0_CRY_40,
O => R1IN_ADD_2_1_0_S_41);
R1IN_ADD_2_1_0_CRY_41_Z8118: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_40,
S => R1IN_ADD_2_1_0_AXB_41,
LO => R1IN_ADD_2_1_0_CRY_41);
R1IN_ADD_2_1_0_S_40_Z8119: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_40,
CI => R1IN_ADD_2_1_0_CRY_39,
O => R1IN_ADD_2_1_0_S_40);
R1IN_ADD_2_1_0_CRY_40_Z8120: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_39,
S => R1IN_ADD_2_1_0_AXB_40,
LO => R1IN_ADD_2_1_0_CRY_40);
R1IN_ADD_2_1_0_S_39_Z8121: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_39,
CI => R1IN_ADD_2_1_0_CRY_38,
O => R1IN_ADD_2_1_0_S_39);
R1IN_ADD_2_1_0_CRY_39_Z8122: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_38,
S => R1IN_ADD_2_1_0_AXB_39,
LO => R1IN_ADD_2_1_0_CRY_39);
R1IN_ADD_2_1_0_S_38_Z8123: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_38,
CI => R1IN_ADD_2_1_0_CRY_37,
O => R1IN_ADD_2_1_0_S_38);
R1IN_ADD_2_1_0_CRY_38_Z8124: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_37,
S => R1IN_ADD_2_1_0_AXB_38,
LO => R1IN_ADD_2_1_0_CRY_38);
R1IN_ADD_2_1_0_S_37_Z8125: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_37,
CI => R1IN_ADD_2_1_0_CRY_36,
O => R1IN_ADD_2_1_0_S_37);
R1IN_ADD_2_1_0_CRY_37_Z8126: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_36,
S => R1IN_ADD_2_1_0_AXB_37,
LO => R1IN_ADD_2_1_0_CRY_37);
R1IN_ADD_2_1_0_S_36_Z8127: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_36,
CI => R1IN_ADD_2_1_0_CRY_35,
O => R1IN_ADD_2_1_0_S_36);
R1IN_ADD_2_1_0_CRY_36_Z8128: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_35,
S => R1IN_ADD_2_1_0_AXB_36,
LO => R1IN_ADD_2_1_0_CRY_36);
R1IN_ADD_2_1_0_S_35_Z8129: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_35,
CI => R1IN_ADD_2_1_0_CRY_34,
O => R1IN_ADD_2_1_0_S_35);
R1IN_ADD_2_1_0_CRY_35_Z8130: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_34,
S => R1IN_ADD_2_1_0_AXB_35,
LO => R1IN_ADD_2_1_0_CRY_35);
R1IN_ADD_2_1_0_S_34_Z8131: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_34,
CI => R1IN_ADD_2_1_0_CRY_33,
O => R1IN_ADD_2_1_0_S_34);
R1IN_ADD_2_1_0_CRY_34_Z8132: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_33,
S => R1IN_ADD_2_1_0_AXB_34,
LO => R1IN_ADD_2_1_0_CRY_34);
R1IN_ADD_2_1_0_S_33_Z8133: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_33,
CI => R1IN_ADD_2_1_0_CRY_32,
O => R1IN_ADD_2_1_0_S_33);
R1IN_ADD_2_1_0_CRY_33_Z8134: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_32,
S => R1IN_ADD_2_1_0_AXB_33,
LO => R1IN_ADD_2_1_0_CRY_33);
R1IN_ADD_2_1_0_S_32_Z8135: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_32,
CI => R1IN_ADD_2_1_0_CRY_31,
O => R1IN_ADD_2_1_0_S_32);
R1IN_ADD_2_1_0_CRY_32_Z8136: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_31,
S => R1IN_ADD_2_1_0_AXB_32,
LO => R1IN_ADD_2_1_0_CRY_32);
R1IN_ADD_2_1_0_S_31_Z8137: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_31,
CI => R1IN_ADD_2_1_0_CRY_30,
O => R1IN_ADD_2_1_0_S_31);
R1IN_ADD_2_1_0_CRY_31_Z8138: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_30,
S => R1IN_ADD_2_1_0_AXB_31,
LO => R1IN_ADD_2_1_0_CRY_31);
R1IN_ADD_2_1_0_S_30_Z8139: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_30,
CI => R1IN_ADD_2_1_0_CRY_29,
O => R1IN_ADD_2_1_0_S_30);
R1IN_ADD_2_1_0_CRY_30_Z8140: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_29,
S => R1IN_ADD_2_1_0_AXB_30,
LO => R1IN_ADD_2_1_0_CRY_30);
R1IN_ADD_2_1_0_S_29_Z8141: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_29,
CI => R1IN_ADD_2_1_0_CRY_28,
O => R1IN_ADD_2_1_0_S_29);
R1IN_ADD_2_1_0_CRY_29_Z8142: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_28,
S => R1IN_ADD_2_1_0_AXB_29,
LO => R1IN_ADD_2_1_0_CRY_29);
R1IN_ADD_2_1_0_S_28_Z8143: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_28,
CI => R1IN_ADD_2_1_0_CRY_27,
O => R1IN_ADD_2_1_0_S_28);
R1IN_ADD_2_1_0_CRY_28_Z8144: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_27,
S => R1IN_ADD_2_1_0_AXB_28,
LO => R1IN_ADD_2_1_0_CRY_28);
R1IN_ADD_2_1_0_S_27_Z8145: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_27,
CI => R1IN_ADD_2_1_0_CRY_26,
O => R1IN_ADD_2_1_0_S_27);
R1IN_ADD_2_1_0_CRY_27_Z8146: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_26,
S => R1IN_ADD_2_1_0_AXB_27,
LO => R1IN_ADD_2_1_0_CRY_27);
R1IN_ADD_2_1_0_S_26_Z8147: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_26,
CI => R1IN_ADD_2_1_0_CRY_25,
O => R1IN_ADD_2_1_0_S_26);
R1IN_ADD_2_1_0_CRY_26_Z8148: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_25,
S => R1IN_ADD_2_1_0_AXB_26,
LO => R1IN_ADD_2_1_0_CRY_26);
R1IN_ADD_2_1_0_S_25_Z8149: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_25,
CI => R1IN_ADD_2_1_0_CRY_24,
O => R1IN_ADD_2_1_0_S_25);
R1IN_ADD_2_1_0_CRY_25_Z8150: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_24,
S => R1IN_ADD_2_1_0_AXB_25,
LO => R1IN_ADD_2_1_0_CRY_25);
R1IN_ADD_2_1_0_S_24_Z8151: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_24,
CI => R1IN_ADD_2_1_0_CRY_23,
O => R1IN_ADD_2_1_0_S_24);
R1IN_ADD_2_1_0_CRY_24_Z8152: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_23,
S => R1IN_ADD_2_1_0_AXB_24,
LO => R1IN_ADD_2_1_0_CRY_24);
R1IN_ADD_2_1_0_S_23_Z8153: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_23,
CI => R1IN_ADD_2_1_0_CRY_22,
O => R1IN_ADD_2_1_0_S_23);
R1IN_ADD_2_1_0_CRY_23_Z8154: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_22,
S => R1IN_ADD_2_1_0_AXB_23,
LO => R1IN_ADD_2_1_0_CRY_23);
R1IN_ADD_2_1_0_S_22_Z8155: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_22,
CI => R1IN_ADD_2_1_0_CRY_21,
O => R1IN_ADD_2_1_0_S_22);
R1IN_ADD_2_1_0_CRY_22_Z8156: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_21,
S => R1IN_ADD_2_1_0_AXB_22,
LO => R1IN_ADD_2_1_0_CRY_22);
R1IN_ADD_2_1_0_S_21_Z8157: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_21,
CI => R1IN_ADD_2_1_0_CRY_20,
O => R1IN_ADD_2_1_0_S_21);
R1IN_ADD_2_1_0_CRY_21_Z8158: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_20,
S => R1IN_ADD_2_1_0_AXB_21,
LO => R1IN_ADD_2_1_0_CRY_21);
R1IN_ADD_2_1_0_S_20_Z8159: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_20,
CI => R1IN_ADD_2_1_0_CRY_19,
O => R1IN_ADD_2_1_0_S_20);
R1IN_ADD_2_1_0_CRY_20_Z8160: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_19,
S => R1IN_ADD_2_1_0_AXB_20,
LO => R1IN_ADD_2_1_0_CRY_20);
R1IN_ADD_2_1_0_S_19_Z8161: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_19,
CI => R1IN_ADD_2_1_0_CRY_18,
O => R1IN_ADD_2_1_0_S_19);
R1IN_ADD_2_1_0_CRY_19_Z8162: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_18,
S => R1IN_ADD_2_1_0_AXB_19,
LO => R1IN_ADD_2_1_0_CRY_19);
R1IN_ADD_2_1_0_S_18_Z8163: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_18,
CI => R1IN_ADD_2_1_0_CRY_17,
O => R1IN_ADD_2_1_0_S_18);
R1IN_ADD_2_1_0_CRY_18_Z8164: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_17,
S => R1IN_ADD_2_1_0_AXB_18,
LO => R1IN_ADD_2_1_0_CRY_18);
R1IN_ADD_2_1_0_S_17_Z8165: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_17,
CI => R1IN_ADD_2_1_0_CRY_16,
O => R1IN_ADD_2_1_0_S_17);
R1IN_ADD_2_1_0_CRY_17_Z8166: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_16,
S => R1IN_ADD_2_1_0_AXB_17,
LO => R1IN_ADD_2_1_0_CRY_17);
R1IN_ADD_2_1_0_S_16_Z8167: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_16,
CI => R1IN_ADD_2_1_0_CRY_15,
O => R1IN_ADD_2_1_0_S_16);
R1IN_ADD_2_1_0_CRY_16_Z8168: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_15,
S => R1IN_ADD_2_1_0_AXB_16,
LO => R1IN_ADD_2_1_0_CRY_16);
R1IN_ADD_2_1_0_S_15_Z8169: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_15,
CI => R1IN_ADD_2_1_0_CRY_14,
O => R1IN_ADD_2_1_0_S_15);
R1IN_ADD_2_1_0_CRY_15_Z8170: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_14,
S => R1IN_ADD_2_1_0_AXB_15,
LO => R1IN_ADD_2_1_0_CRY_15);
R1IN_ADD_2_1_0_S_14_Z8171: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_14,
CI => R1IN_ADD_2_1_0_CRY_13,
O => R1IN_ADD_2_1_0_S_14);
R1IN_ADD_2_1_0_CRY_14_Z8172: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_13,
S => R1IN_ADD_2_1_0_AXB_14,
LO => R1IN_ADD_2_1_0_CRY_14);
R1IN_ADD_2_1_0_S_13_Z8173: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_13,
CI => R1IN_ADD_2_1_0_CRY_12,
O => R1IN_ADD_2_1_0_S_13);
R1IN_ADD_2_1_0_CRY_13_Z8174: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_12,
S => R1IN_ADD_2_1_0_AXB_13,
LO => R1IN_ADD_2_1_0_CRY_13);
R1IN_ADD_2_1_0_S_12_Z8175: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_12,
CI => R1IN_ADD_2_1_0_CRY_11,
O => R1IN_ADD_2_1_0_S_12);
R1IN_ADD_2_1_0_CRY_12_Z8176: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_11,
S => R1IN_ADD_2_1_0_AXB_12,
LO => R1IN_ADD_2_1_0_CRY_12);
R1IN_ADD_2_1_0_S_11_Z8177: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_11,
CI => R1IN_ADD_2_1_0_CRY_10,
O => R1IN_ADD_2_1_0_S_11);
R1IN_ADD_2_1_0_CRY_11_Z8178: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_10,
S => R1IN_ADD_2_1_0_AXB_11,
LO => R1IN_ADD_2_1_0_CRY_11);
R1IN_ADD_2_1_0_S_10_Z8179: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_10,
CI => R1IN_ADD_2_1_0_CRY_9,
O => R1IN_ADD_2_1_0_S_10);
R1IN_ADD_2_1_0_CRY_10_Z8180: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_9,
S => R1IN_ADD_2_1_0_AXB_10,
LO => R1IN_ADD_2_1_0_CRY_10);
R1IN_ADD_2_1_0_S_9_Z8181: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_9,
CI => R1IN_ADD_2_1_0_CRY_8,
O => R1IN_ADD_2_1_0_S_9);
R1IN_ADD_2_1_0_CRY_9_Z8182: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_0_CRY_8,
S => R1IN_ADD_2_1_0_AXB_9,
LO => R1IN_ADD_2_1_0_CRY_9);
R1IN_ADD_2_1_0_S_8_Z8183: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_8,
CI => R1IN_ADD_2_1_0_CRY_7,
O => R1IN_ADD_2_1_0_S_8);
R1IN_ADD_2_1_0_CRY_8_Z8184: MUXCY_L port map (
DI => R1IN_4F(44),
CI => R1IN_ADD_2_1_0_CRY_7,
S => R1IN_ADD_2_1_0_AXB_8,
LO => R1IN_ADD_2_1_0_CRY_8);
R1IN_ADD_2_1_0_S_7_Z8185: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_7,
CI => R1IN_ADD_2_1_0_CRY_6,
O => R1IN_ADD_2_1_0_S_7);
R1IN_ADD_2_1_0_CRY_7_Z8186: MUXCY_L port map (
DI => R1IN_4F(43),
CI => R1IN_ADD_2_1_0_CRY_6,
S => R1IN_ADD_2_1_0_AXB_7,
LO => R1IN_ADD_2_1_0_CRY_7);
R1IN_ADD_2_1_0_S_6_Z8187: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_6,
CI => R1IN_ADD_2_1_0_CRY_5,
O => R1IN_ADD_2_1_0_S_6);
R1IN_ADD_2_1_0_CRY_6_Z8188: MUXCY_L port map (
DI => R1IN_4F(42),
CI => R1IN_ADD_2_1_0_CRY_5,
S => R1IN_ADD_2_1_0_AXB_6,
LO => R1IN_ADD_2_1_0_CRY_6);
R1IN_ADD_2_1_0_S_5_Z8189: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_5,
CI => R1IN_ADD_2_1_0_CRY_4,
O => R1IN_ADD_2_1_0_S_5);
R1IN_ADD_2_1_0_CRY_5_Z8190: MUXCY_L port map (
DI => R1IN_4F(41),
CI => R1IN_ADD_2_1_0_CRY_4,
S => R1IN_ADD_2_1_0_AXB_5,
LO => R1IN_ADD_2_1_0_CRY_5);
R1IN_ADD_2_1_0_S_4_Z8191: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_4,
CI => R1IN_ADD_2_1_0_CRY_3,
O => R1IN_ADD_2_1_0_S_4);
R1IN_ADD_2_1_0_CRY_4_Z8192: MUXCY_L port map (
DI => R1IN_4F(40),
CI => R1IN_ADD_2_1_0_CRY_3,
S => R1IN_ADD_2_1_0_AXB_4,
LO => R1IN_ADD_2_1_0_CRY_4);
R1IN_ADD_2_1_0_S_3_Z8193: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_3,
CI => R1IN_ADD_2_1_0_CRY_2,
O => R1IN_ADD_2_1_0_S_3);
R1IN_ADD_2_1_0_CRY_3_Z8194: MUXCY_L port map (
DI => R1IN_4F(39),
CI => R1IN_ADD_2_1_0_CRY_2,
S => R1IN_ADD_2_1_0_AXB_3,
LO => R1IN_ADD_2_1_0_CRY_3);
R1IN_ADD_2_1_0_S_2_Z8195: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_2,
CI => R1IN_ADD_2_1_0_CRY_1,
O => R1IN_ADD_2_1_0_S_2);
R1IN_ADD_2_1_0_CRY_2_Z8196: MUXCY_L port map (
DI => R1IN_4F(38),
CI => R1IN_ADD_2_1_0_CRY_1,
S => R1IN_ADD_2_1_0_AXB_2,
LO => R1IN_ADD_2_1_0_CRY_2);
R1IN_ADD_2_1_0_S_1_Z8197: XORCY port map (
LI => R1IN_ADD_2_1_0_AXB_1,
CI => R1IN_ADD_2_1_0_CRY_0,
O => R1IN_ADD_2_1_0_S_1);
R1IN_ADD_2_1_0_CRY_1_Z8198: MUXCY_L port map (
DI => R1IN_4F(37),
CI => R1IN_ADD_2_1_0_CRY_0,
S => R1IN_ADD_2_1_0_AXB_1,
LO => R1IN_ADD_2_1_0_CRY_1);
R1IN_ADD_2_1_0_CRY_0_Z8199: MUXCY_L port map (
DI => R1IN_4F(36),
CI => NN_2,
S => R1IN_ADD_2_1_0_AXB_0,
LO => R1IN_ADD_2_1_0_CRY_0);
R1IN_ADD_2_1_S_51_Z8200: XORCY port map (
LI => R1IN_ADD_2_1_AXB_51,
CI => R1IN_ADD_2_1_CRY_50,
O => R1IN_ADD_2_1_S_51);
R1IN_ADD_2_1_S_50_Z8201: XORCY port map (
LI => R1IN_ADD_2_1_AXB_50,
CI => R1IN_ADD_2_1_CRY_49,
O => R1IN_ADD_2_1_S_50);
R1IN_ADD_2_1_CRY_50_Z8202: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_49,
S => R1IN_ADD_2_1_AXB_50,
LO => R1IN_ADD_2_1_CRY_50);
R1IN_ADD_2_1_S_49_Z8203: XORCY port map (
LI => R1IN_ADD_2_1_AXB_49,
CI => R1IN_ADD_2_1_CRY_48,
O => R1IN_ADD_2_1_S_49);
R1IN_ADD_2_1_CRY_49_Z8204: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_48,
S => R1IN_ADD_2_1_AXB_49,
LO => R1IN_ADD_2_1_CRY_49);
R1IN_ADD_2_1_S_48_Z8205: XORCY port map (
LI => R1IN_ADD_2_1_AXB_48,
CI => R1IN_ADD_2_1_CRY_47,
O => R1IN_ADD_2_1_S_48);
R1IN_ADD_2_1_CRY_48_Z8206: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_47,
S => R1IN_ADD_2_1_AXB_48,
LO => R1IN_ADD_2_1_CRY_48);
R1IN_ADD_2_1_S_47_Z8207: XORCY port map (
LI => R1IN_ADD_2_1_AXB_47,
CI => R1IN_ADD_2_1_CRY_46,
O => R1IN_ADD_2_1_S_47);
R1IN_ADD_2_1_CRY_47_Z8208: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_46,
S => R1IN_ADD_2_1_AXB_47,
LO => R1IN_ADD_2_1_CRY_47);
R1IN_ADD_2_1_S_46_Z8209: XORCY port map (
LI => R1IN_ADD_2_1_AXB_46,
CI => R1IN_ADD_2_1_CRY_45,
O => R1IN_ADD_2_1_S_46);
R1IN_ADD_2_1_CRY_46_Z8210: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_45,
S => R1IN_ADD_2_1_AXB_46,
LO => R1IN_ADD_2_1_CRY_46);
R1IN_ADD_2_1_S_45_Z8211: XORCY port map (
LI => R1IN_ADD_2_1_AXB_45,
CI => R1IN_ADD_2_1_CRY_44,
O => R1IN_ADD_2_1_S_45);
R1IN_ADD_2_1_CRY_45_Z8212: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_44,
S => R1IN_ADD_2_1_AXB_45,
LO => R1IN_ADD_2_1_CRY_45);
R1IN_ADD_2_1_S_44_Z8213: XORCY port map (
LI => R1IN_ADD_2_1_AXB_44,
CI => R1IN_ADD_2_1_CRY_43,
O => R1IN_ADD_2_1_S_44);
R1IN_ADD_2_1_CRY_44_Z8214: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_43,
S => R1IN_ADD_2_1_AXB_44,
LO => R1IN_ADD_2_1_CRY_44);
R1IN_ADD_2_1_S_43_Z8215: XORCY port map (
LI => R1IN_ADD_2_1_AXB_43,
CI => R1IN_ADD_2_1_CRY_42,
O => R1IN_ADD_2_1_S_43);
R1IN_ADD_2_1_CRY_43_Z8216: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_42,
S => R1IN_ADD_2_1_AXB_43,
LO => R1IN_ADD_2_1_CRY_43);
R1IN_ADD_2_1_S_42_Z8217: XORCY port map (
LI => R1IN_ADD_2_1_AXB_42,
CI => R1IN_ADD_2_1_CRY_41,
O => R1IN_ADD_2_1_S_42);
R1IN_ADD_2_1_CRY_42_Z8218: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_41,
S => R1IN_ADD_2_1_AXB_42,
LO => R1IN_ADD_2_1_CRY_42);
R1IN_ADD_2_1_S_41_Z8219: XORCY port map (
LI => R1IN_ADD_2_1_AXB_41,
CI => R1IN_ADD_2_1_CRY_40,
O => R1IN_ADD_2_1_S_41);
R1IN_ADD_2_1_CRY_41_Z8220: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_40,
S => R1IN_ADD_2_1_AXB_41,
LO => R1IN_ADD_2_1_CRY_41);
R1IN_ADD_2_1_S_40_Z8221: XORCY port map (
LI => R1IN_ADD_2_1_AXB_40,
CI => R1IN_ADD_2_1_CRY_39,
O => R1IN_ADD_2_1_S_40);
R1IN_ADD_2_1_CRY_40_Z8222: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_39,
S => R1IN_ADD_2_1_AXB_40,
LO => R1IN_ADD_2_1_CRY_40);
R1IN_ADD_2_1_S_39_Z8223: XORCY port map (
LI => R1IN_ADD_2_1_AXB_39,
CI => R1IN_ADD_2_1_CRY_38,
O => R1IN_ADD_2_1_S_39);
R1IN_ADD_2_1_CRY_39_Z8224: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_38,
S => R1IN_ADD_2_1_AXB_39,
LO => R1IN_ADD_2_1_CRY_39);
R1IN_ADD_2_1_S_38_Z8225: XORCY port map (
LI => R1IN_ADD_2_1_AXB_38,
CI => R1IN_ADD_2_1_CRY_37,
O => R1IN_ADD_2_1_S_38);
R1IN_ADD_2_1_CRY_38_Z8226: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_37,
S => R1IN_ADD_2_1_AXB_38,
LO => R1IN_ADD_2_1_CRY_38);
R1IN_ADD_2_1_S_37_Z8227: XORCY port map (
LI => R1IN_ADD_2_1_AXB_37,
CI => R1IN_ADD_2_1_CRY_36,
O => R1IN_ADD_2_1_S_37);
R1IN_ADD_2_1_CRY_37_Z8228: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_36,
S => R1IN_ADD_2_1_AXB_37,
LO => R1IN_ADD_2_1_CRY_37);
R1IN_ADD_2_1_S_36_Z8229: XORCY port map (
LI => R1IN_ADD_2_1_AXB_36,
CI => R1IN_ADD_2_1_CRY_35,
O => R1IN_ADD_2_1_S_36);
R1IN_ADD_2_1_CRY_36_Z8230: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_35,
S => R1IN_ADD_2_1_AXB_36,
LO => R1IN_ADD_2_1_CRY_36);
R1IN_ADD_2_1_S_35_Z8231: XORCY port map (
LI => R1IN_ADD_2_1_AXB_35,
CI => R1IN_ADD_2_1_CRY_34,
O => R1IN_ADD_2_1_S_35);
R1IN_ADD_2_1_CRY_35_Z8232: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_34,
S => R1IN_ADD_2_1_AXB_35,
LO => R1IN_ADD_2_1_CRY_35);
R1IN_ADD_2_1_S_34_Z8233: XORCY port map (
LI => R1IN_ADD_2_1_AXB_34,
CI => R1IN_ADD_2_1_CRY_33,
O => R1IN_ADD_2_1_S_34);
R1IN_ADD_2_1_CRY_34_Z8234: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_33,
S => R1IN_ADD_2_1_AXB_34,
LO => R1IN_ADD_2_1_CRY_34);
R1IN_ADD_2_1_S_33_Z8235: XORCY port map (
LI => R1IN_ADD_2_1_AXB_33,
CI => R1IN_ADD_2_1_CRY_32,
O => R1IN_ADD_2_1_S_33);
R1IN_ADD_2_1_CRY_33_Z8236: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_32,
S => R1IN_ADD_2_1_AXB_33,
LO => R1IN_ADD_2_1_CRY_33);
R1IN_ADD_2_1_S_32_Z8237: XORCY port map (
LI => R1IN_ADD_2_1_AXB_32,
CI => R1IN_ADD_2_1_CRY_31,
O => R1IN_ADD_2_1_S_32);
R1IN_ADD_2_1_CRY_32_Z8238: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_31,
S => R1IN_ADD_2_1_AXB_32,
LO => R1IN_ADD_2_1_CRY_32);
R1IN_ADD_2_1_S_31_Z8239: XORCY port map (
LI => R1IN_ADD_2_1_AXB_31,
CI => R1IN_ADD_2_1_CRY_30,
O => R1IN_ADD_2_1_S_31);
R1IN_ADD_2_1_CRY_31_Z8240: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_30,
S => R1IN_ADD_2_1_AXB_31,
LO => R1IN_ADD_2_1_CRY_31);
R1IN_ADD_2_1_S_30_Z8241: XORCY port map (
LI => R1IN_ADD_2_1_AXB_30,
CI => R1IN_ADD_2_1_CRY_29,
O => R1IN_ADD_2_1_S_30);
R1IN_ADD_2_1_CRY_30_Z8242: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_29,
S => R1IN_ADD_2_1_AXB_30,
LO => R1IN_ADD_2_1_CRY_30);
R1IN_ADD_2_1_S_29_Z8243: XORCY port map (
LI => R1IN_ADD_2_1_AXB_29,
CI => R1IN_ADD_2_1_CRY_28,
O => R1IN_ADD_2_1_S_29);
R1IN_ADD_2_1_CRY_29_Z8244: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_28,
S => R1IN_ADD_2_1_AXB_29,
LO => R1IN_ADD_2_1_CRY_29);
R1IN_ADD_2_1_S_28_Z8245: XORCY port map (
LI => R1IN_ADD_2_1_AXB_28,
CI => R1IN_ADD_2_1_CRY_27,
O => R1IN_ADD_2_1_S_28);
R1IN_ADD_2_1_CRY_28_Z8246: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_27,
S => R1IN_ADD_2_1_AXB_28,
LO => R1IN_ADD_2_1_CRY_28);
R1IN_ADD_2_1_S_27_Z8247: XORCY port map (
LI => R1IN_ADD_2_1_AXB_27,
CI => R1IN_ADD_2_1_CRY_26,
O => R1IN_ADD_2_1_S_27);
R1IN_ADD_2_1_CRY_27_Z8248: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_26,
S => R1IN_ADD_2_1_AXB_27,
LO => R1IN_ADD_2_1_CRY_27);
R1IN_ADD_2_1_S_26_Z8249: XORCY port map (
LI => R1IN_ADD_2_1_AXB_26,
CI => R1IN_ADD_2_1_CRY_25,
O => R1IN_ADD_2_1_S_26);
R1IN_ADD_2_1_CRY_26_Z8250: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_25,
S => R1IN_ADD_2_1_AXB_26,
LO => R1IN_ADD_2_1_CRY_26);
R1IN_ADD_2_1_S_25_Z8251: XORCY port map (
LI => R1IN_ADD_2_1_AXB_25,
CI => R1IN_ADD_2_1_CRY_24,
O => R1IN_ADD_2_1_S_25);
R1IN_ADD_2_1_CRY_25_Z8252: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_24,
S => R1IN_ADD_2_1_AXB_25,
LO => R1IN_ADD_2_1_CRY_25);
R1IN_ADD_2_1_S_24_Z8253: XORCY port map (
LI => R1IN_ADD_2_1_AXB_24,
CI => R1IN_ADD_2_1_CRY_23,
O => R1IN_ADD_2_1_S_24);
R1IN_ADD_2_1_CRY_24_Z8254: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_23,
S => R1IN_ADD_2_1_AXB_24,
LO => R1IN_ADD_2_1_CRY_24);
R1IN_ADD_2_1_S_23_Z8255: XORCY port map (
LI => R1IN_ADD_2_1_AXB_23,
CI => R1IN_ADD_2_1_CRY_22,
O => R1IN_ADD_2_1_S_23);
R1IN_ADD_2_1_CRY_23_Z8256: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_22,
S => R1IN_ADD_2_1_AXB_23,
LO => R1IN_ADD_2_1_CRY_23);
R1IN_ADD_2_1_S_22_Z8257: XORCY port map (
LI => R1IN_ADD_2_1_AXB_22,
CI => R1IN_ADD_2_1_CRY_21,
O => R1IN_ADD_2_1_S_22);
R1IN_ADD_2_1_CRY_22_Z8258: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_21,
S => R1IN_ADD_2_1_AXB_22,
LO => R1IN_ADD_2_1_CRY_22);
R1IN_ADD_2_1_S_21_Z8259: XORCY port map (
LI => R1IN_ADD_2_1_AXB_21,
CI => R1IN_ADD_2_1_CRY_20,
O => R1IN_ADD_2_1_S_21);
R1IN_ADD_2_1_CRY_21_Z8260: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_20,
S => R1IN_ADD_2_1_AXB_21,
LO => R1IN_ADD_2_1_CRY_21);
R1IN_ADD_2_1_S_20_Z8261: XORCY port map (
LI => R1IN_ADD_2_1_AXB_20,
CI => R1IN_ADD_2_1_CRY_19,
O => R1IN_ADD_2_1_S_20);
R1IN_ADD_2_1_CRY_20_Z8262: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_19,
S => R1IN_ADD_2_1_AXB_20,
LO => R1IN_ADD_2_1_CRY_20);
R1IN_ADD_2_1_S_19_Z8263: XORCY port map (
LI => R1IN_ADD_2_1_AXB_19,
CI => R1IN_ADD_2_1_CRY_18,
O => R1IN_ADD_2_1_S_19);
R1IN_ADD_2_1_CRY_19_Z8264: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_18,
S => R1IN_ADD_2_1_AXB_19,
LO => R1IN_ADD_2_1_CRY_19);
R1IN_ADD_2_1_S_18_Z8265: XORCY port map (
LI => R1IN_ADD_2_1_AXB_18,
CI => R1IN_ADD_2_1_CRY_17,
O => R1IN_ADD_2_1_S_18);
R1IN_ADD_2_1_CRY_18_Z8266: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_17,
S => R1IN_ADD_2_1_AXB_18,
LO => R1IN_ADD_2_1_CRY_18);
R1IN_ADD_2_1_S_17_Z8267: XORCY port map (
LI => R1IN_ADD_2_1_AXB_17,
CI => R1IN_ADD_2_1_CRY_16,
O => R1IN_ADD_2_1_S_17);
R1IN_ADD_2_1_CRY_17_Z8268: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_16,
S => R1IN_ADD_2_1_AXB_17,
LO => R1IN_ADD_2_1_CRY_17);
R1IN_ADD_2_1_S_16_Z8269: XORCY port map (
LI => R1IN_ADD_2_1_AXB_16,
CI => R1IN_ADD_2_1_CRY_15,
O => R1IN_ADD_2_1_S_16);
R1IN_ADD_2_1_CRY_16_Z8270: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_15,
S => R1IN_ADD_2_1_AXB_16,
LO => R1IN_ADD_2_1_CRY_16);
R1IN_ADD_2_1_S_15_Z8271: XORCY port map (
LI => R1IN_ADD_2_1_AXB_15,
CI => R1IN_ADD_2_1_CRY_14,
O => R1IN_ADD_2_1_S_15);
R1IN_ADD_2_1_CRY_15_Z8272: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_14,
S => R1IN_ADD_2_1_AXB_15,
LO => R1IN_ADD_2_1_CRY_15);
R1IN_ADD_2_1_S_14_Z8273: XORCY port map (
LI => R1IN_ADD_2_1_AXB_14,
CI => R1IN_ADD_2_1_CRY_13,
O => R1IN_ADD_2_1_S_14);
R1IN_ADD_2_1_CRY_14_Z8274: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_13,
S => R1IN_ADD_2_1_AXB_14,
LO => R1IN_ADD_2_1_CRY_14);
R1IN_ADD_2_1_S_13_Z8275: XORCY port map (
LI => R1IN_ADD_2_1_AXB_13,
CI => R1IN_ADD_2_1_CRY_12,
O => R1IN_ADD_2_1_S_13);
R1IN_ADD_2_1_CRY_13_Z8276: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_12,
S => R1IN_ADD_2_1_AXB_13,
LO => R1IN_ADD_2_1_CRY_13);
R1IN_ADD_2_1_S_12_Z8277: XORCY port map (
LI => R1IN_ADD_2_1_AXB_12,
CI => R1IN_ADD_2_1_CRY_11,
O => R1IN_ADD_2_1_S_12);
R1IN_ADD_2_1_CRY_12_Z8278: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_11,
S => R1IN_ADD_2_1_AXB_12,
LO => R1IN_ADD_2_1_CRY_12);
R1IN_ADD_2_1_S_11_Z8279: XORCY port map (
LI => R1IN_ADD_2_1_AXB_11,
CI => R1IN_ADD_2_1_CRY_10,
O => R1IN_ADD_2_1_S_11);
R1IN_ADD_2_1_CRY_11_Z8280: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_10,
S => R1IN_ADD_2_1_AXB_11,
LO => R1IN_ADD_2_1_CRY_11);
R1IN_ADD_2_1_S_10_Z8281: XORCY port map (
LI => R1IN_ADD_2_1_AXB_10,
CI => R1IN_ADD_2_1_CRY_9,
O => R1IN_ADD_2_1_S_10);
R1IN_ADD_2_1_CRY_10_Z8282: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_9,
S => R1IN_ADD_2_1_AXB_10,
LO => R1IN_ADD_2_1_CRY_10);
R1IN_ADD_2_1_S_9_Z8283: XORCY port map (
LI => R1IN_ADD_2_1_AXB_9,
CI => R1IN_ADD_2_1_CRY_8,
O => R1IN_ADD_2_1_S_9);
R1IN_ADD_2_1_CRY_9_Z8284: MUXCY_L port map (
DI => NN_1,
CI => R1IN_ADD_2_1_CRY_8,
S => R1IN_ADD_2_1_AXB_9,
LO => R1IN_ADD_2_1_CRY_9);
R1IN_ADD_2_1_S_8_Z8285: XORCY port map (
LI => R1IN_ADD_2_1_AXB_8,
CI => R1IN_ADD_2_1_CRY_7,
O => R1IN_ADD_2_1_S_8);
R1IN_ADD_2_1_CRY_8_Z8286: MUXCY_L port map (
DI => R1IN_4F(44),
CI => R1IN_ADD_2_1_CRY_7,
S => R1IN_ADD_2_1_AXB_8,
LO => R1IN_ADD_2_1_CRY_8);
R1IN_ADD_2_1_S_7_Z8287: XORCY port map (
LI => R1IN_ADD_2_1_AXB_7,
CI => R1IN_ADD_2_1_CRY_6,
O => R1IN_ADD_2_1_S_7);
R1IN_ADD_2_1_CRY_7_Z8288: MUXCY_L port map (
DI => R1IN_4F(43),
CI => R1IN_ADD_2_1_CRY_6,
S => R1IN_ADD_2_1_AXB_7,
LO => R1IN_ADD_2_1_CRY_7);
R1IN_ADD_2_1_S_6_Z8289: XORCY port map (
LI => R1IN_ADD_2_1_AXB_6,
CI => R1IN_ADD_2_1_CRY_5,
O => R1IN_ADD_2_1_S_6);
R1IN_ADD_2_1_CRY_6_Z8290: MUXCY_L port map (
DI => R1IN_4F(42),
CI => R1IN_ADD_2_1_CRY_5,
S => R1IN_ADD_2_1_AXB_6,
LO => R1IN_ADD_2_1_CRY_6);
R1IN_ADD_2_1_S_5_Z8291: XORCY port map (
LI => R1IN_ADD_2_1_AXB_5,
CI => R1IN_ADD_2_1_CRY_4,
O => R1IN_ADD_2_1_S_5);
R1IN_ADD_2_1_CRY_5_Z8292: MUXCY_L port map (
DI => R1IN_4F(41),
CI => R1IN_ADD_2_1_CRY_4,
S => R1IN_ADD_2_1_AXB_5,
LO => R1IN_ADD_2_1_CRY_5);
R1IN_ADD_2_1_S_4_Z8293: XORCY port map (
LI => R1IN_ADD_2_1_AXB_4,
CI => R1IN_ADD_2_1_CRY_3,
O => R1IN_ADD_2_1_S_4);
R1IN_ADD_2_1_CRY_4_Z8294: MUXCY_L port map (
DI => R1IN_4F(40),
CI => R1IN_ADD_2_1_CRY_3,
S => R1IN_ADD_2_1_AXB_4,
LO => R1IN_ADD_2_1_CRY_4);
R1IN_ADD_2_1_S_3_Z8295: XORCY port map (
LI => R1IN_ADD_2_1_AXB_3,
CI => R1IN_ADD_2_1_CRY_2,
O => R1IN_ADD_2_1_S_3);
R1IN_ADD_2_1_CRY_3_Z8296: MUXCY_L port map (
DI => R1IN_4F(39),
CI => R1IN_ADD_2_1_CRY_2,
S => R1IN_ADD_2_1_AXB_3,
LO => R1IN_ADD_2_1_CRY_3);
R1IN_ADD_2_1_S_2_Z8297: XORCY port map (
LI => R1IN_ADD_2_1_AXB_2,
CI => R1IN_ADD_2_1_CRY_1,
O => R1IN_ADD_2_1_S_2);
R1IN_ADD_2_1_CRY_2_Z8298: MUXCY_L port map (
DI => R1IN_4F(38),
CI => R1IN_ADD_2_1_CRY_1,
S => R1IN_ADD_2_1_AXB_2,
LO => R1IN_ADD_2_1_CRY_2);
R1IN_ADD_2_1_S_1_Z8299: XORCY port map (
LI => R1IN_ADD_2_1_AXB_1,
CI => R1IN_ADD_2_1_CRY_0,
O => R1IN_ADD_2_1_S_1);
R1IN_ADD_2_1_CRY_1_Z8300: MUXCY_L port map (
DI => R1IN_4F(37),
CI => R1IN_ADD_2_1_CRY_0,
S => R1IN_ADD_2_1_AXB_1,
LO => R1IN_ADD_2_1_CRY_1);
R1IN_ADD_2_1_CRY_0_Z8301: MUXCY_L port map (
DI => R1IN_4F(36),
CI => NN_1,
S => R1IN_ADD_2_1_AXB_0,
LO => R1IN_ADD_2_1_CRY_0);
R1IN_ADD_2_0_S_52: XORCY port map (
LI => R1IN_ADD_2_0_AXB_52,
CI => R1IN_ADD_2_0_CRY_51,
O => PRODUCT(69));
R1IN_ADD_2_0_CRY_52_Z8303: MUXCY port map (
DI => R1IN_4F(35),
CI => R1IN_ADD_2_0_CRY_51,
S => R1IN_ADD_2_0_AXB_52,
O => R1IN_ADD_2_0_CRY_52);
R1IN_ADD_2_0_S_51: XORCY port map (
LI => R1IN_ADD_2_0_AXB_51,
CI => R1IN_ADD_2_0_CRY_50,
O => PRODUCT(68));
R1IN_ADD_2_0_CRY_51_Z8305: MUXCY_L port map (
DI => R1IN_4F(34),
CI => R1IN_ADD_2_0_CRY_50,
S => R1IN_ADD_2_0_AXB_51,
LO => R1IN_ADD_2_0_CRY_51);
R1IN_ADD_2_0_S_50: XORCY port map (
LI => R1IN_ADD_2_0_AXB_50,
CI => R1IN_ADD_2_0_CRY_49,
O => PRODUCT(67));
R1IN_ADD_2_0_CRY_50_Z8307: MUXCY_L port map (
DI => R1IN_4F(33),
CI => R1IN_ADD_2_0_CRY_49,
S => R1IN_ADD_2_0_AXB_50,
LO => R1IN_ADD_2_0_CRY_50);
R1IN_ADD_2_0_S_49: XORCY port map (
LI => R1IN_ADD_2_0_AXB_49,
CI => R1IN_ADD_2_0_CRY_48,
O => PRODUCT(66));
R1IN_ADD_2_0_CRY_49_Z8309: MUXCY_L port map (
DI => R1IN_4F(32),
CI => R1IN_ADD_2_0_CRY_48,
S => R1IN_ADD_2_0_AXB_49,
LO => R1IN_ADD_2_0_CRY_49);
R1IN_ADD_2_0_S_48: XORCY port map (
LI => R1IN_ADD_2_0_AXB_48,
CI => R1IN_ADD_2_0_CRY_47,
O => PRODUCT(65));
R1IN_ADD_2_0_CRY_48_Z8311: MUXCY_L port map (
DI => R1IN_4F(31),
CI => R1IN_ADD_2_0_CRY_47,
S => R1IN_ADD_2_0_AXB_48,
LO => R1IN_ADD_2_0_CRY_48);
R1IN_ADD_2_0_S_47: XORCY port map (
LI => R1IN_ADD_2_0_AXB_47,
CI => R1IN_ADD_2_0_CRY_46,
O => PRODUCT(64));
R1IN_ADD_2_0_CRY_47_Z8313: MUXCY_L port map (
DI => R1IN_4F(30),
CI => R1IN_ADD_2_0_CRY_46,
S => R1IN_ADD_2_0_AXB_47,
LO => R1IN_ADD_2_0_CRY_47);
R1IN_ADD_2_0_S_46: XORCY port map (
LI => R1IN_ADD_2_0_AXB_46,
CI => R1IN_ADD_2_0_CRY_45,
O => PRODUCT(63));
R1IN_ADD_2_0_CRY_46_Z8315: MUXCY_L port map (
DI => R1IN_4F(29),
CI => R1IN_ADD_2_0_CRY_45,
S => R1IN_ADD_2_0_AXB_46,
LO => R1IN_ADD_2_0_CRY_46);
R1IN_ADD_2_0_S_45: XORCY port map (
LI => R1IN_ADD_2_0_AXB_45,
CI => R1IN_ADD_2_0_CRY_44,
O => PRODUCT(62));
R1IN_ADD_2_0_CRY_45_Z8317: MUXCY_L port map (
DI => R1IN_4F(28),
CI => R1IN_ADD_2_0_CRY_44,
S => R1IN_ADD_2_0_AXB_45,
LO => R1IN_ADD_2_0_CRY_45);
R1IN_ADD_2_0_S_44: XORCY port map (
LI => R1IN_ADD_2_0_AXB_44,
CI => R1IN_ADD_2_0_CRY_43,
O => PRODUCT(61));
R1IN_ADD_2_0_CRY_44_Z8319: MUXCY_L port map (
DI => R1IN_4F(27),
CI => R1IN_ADD_2_0_CRY_43,
S => R1IN_ADD_2_0_AXB_44,
LO => R1IN_ADD_2_0_CRY_44);
R1IN_ADD_2_0_S_43: XORCY port map (
LI => R1IN_ADD_2_0_AXB_43,
CI => R1IN_ADD_2_0_CRY_42,
O => PRODUCT(60));
R1IN_ADD_2_0_CRY_43_Z8321: MUXCY_L port map (
DI => R1IN_4F(26),
CI => R1IN_ADD_2_0_CRY_42,
S => R1IN_ADD_2_0_AXB_43,
LO => R1IN_ADD_2_0_CRY_43);
R1IN_ADD_2_0_S_42: XORCY port map (
LI => R1IN_ADD_2_0_AXB_42,
CI => R1IN_ADD_2_0_CRY_41,
O => PRODUCT(59));
R1IN_ADD_2_0_CRY_42_Z8323: MUXCY_L port map (
DI => R1IN_4F(25),
CI => R1IN_ADD_2_0_CRY_41,
S => R1IN_ADD_2_0_AXB_42,
LO => R1IN_ADD_2_0_CRY_42);
R1IN_ADD_2_0_S_41: XORCY port map (
LI => R1IN_ADD_2_0_AXB_41,
CI => R1IN_ADD_2_0_CRY_40,
O => PRODUCT(58));
R1IN_ADD_2_0_CRY_41_Z8325: MUXCY_L port map (
DI => R1IN_4F(24),
CI => R1IN_ADD_2_0_CRY_40,
S => R1IN_ADD_2_0_AXB_41,
LO => R1IN_ADD_2_0_CRY_41);
R1IN_ADD_2_0_S_40: XORCY port map (
LI => R1IN_ADD_2_0_AXB_40,
CI => R1IN_ADD_2_0_CRY_39,
O => PRODUCT(57));
R1IN_ADD_2_0_CRY_40_Z8327: MUXCY_L port map (
DI => R1IN_4F(23),
CI => R1IN_ADD_2_0_CRY_39,
S => R1IN_ADD_2_0_AXB_40,
LO => R1IN_ADD_2_0_CRY_40);
R1IN_ADD_2_0_S_39: XORCY port map (
LI => R1IN_ADD_2_0_AXB_39,
CI => R1IN_ADD_2_0_CRY_38,
O => PRODUCT(56));
R1IN_ADD_2_0_CRY_39_Z8329: MUXCY_L port map (
DI => R1IN_4F(22),
CI => R1IN_ADD_2_0_CRY_38,
S => R1IN_ADD_2_0_AXB_39,
LO => R1IN_ADD_2_0_CRY_39);
R1IN_ADD_2_0_S_38: XORCY port map (
LI => R1IN_ADD_2_0_AXB_38,
CI => R1IN_ADD_2_0_CRY_37,
O => PRODUCT(55));
R1IN_ADD_2_0_CRY_38_Z8331: MUXCY_L port map (
DI => R1IN_4F(21),
CI => R1IN_ADD_2_0_CRY_37,
S => R1IN_ADD_2_0_AXB_38,
LO => R1IN_ADD_2_0_CRY_38);
R1IN_ADD_2_0_S_37: XORCY port map (
LI => R1IN_ADD_2_0_AXB_37,
CI => R1IN_ADD_2_0_CRY_36,
O => PRODUCT(54));
R1IN_ADD_2_0_CRY_37_Z8333: MUXCY_L port map (
DI => R1IN_4F(20),
CI => R1IN_ADD_2_0_CRY_36,
S => R1IN_ADD_2_0_AXB_37,
LO => R1IN_ADD_2_0_CRY_37);
R1IN_ADD_2_0_S_36: XORCY port map (
LI => R1IN_ADD_2_0_AXB_36,
CI => R1IN_ADD_2_0_CRY_35,
O => PRODUCT(53));
R1IN_ADD_2_0_CRY_36_Z8335: MUXCY_L port map (
DI => R1IN_4F(19),
CI => R1IN_ADD_2_0_CRY_35,
S => R1IN_ADD_2_0_AXB_36,
LO => R1IN_ADD_2_0_CRY_36);
R1IN_ADD_2_0_S_35: XORCY port map (
LI => R1IN_ADD_2_0_AXB_35,
CI => R1IN_ADD_2_0_CRY_34,
O => PRODUCT(52));
R1IN_ADD_2_0_CRY_35_Z8337: MUXCY_L port map (
DI => R1IN_4F(18),
CI => R1IN_ADD_2_0_CRY_34,
S => R1IN_ADD_2_0_AXB_35,
LO => R1IN_ADD_2_0_CRY_35);
R1IN_ADD_2_0_S_34: XORCY port map (
LI => R1IN_ADD_2_0_AXB_34,
CI => R1IN_ADD_2_0_CRY_33,
O => PRODUCT(51));
R1IN_ADD_2_0_CRY_34_Z8339: MUXCY_L port map (
DI => R1IN_4F(17),
CI => R1IN_ADD_2_0_CRY_33,
S => R1IN_ADD_2_0_AXB_34,
LO => R1IN_ADD_2_0_CRY_34);
R1IN_ADD_2_0_S_33: XORCY port map (
LI => R1IN_ADD_2_0_AXB_33,
CI => R1IN_ADD_2_0_CRY_32,
O => PRODUCT(50));
R1IN_ADD_2_0_CRY_33_Z8341: MUXCY_L port map (
DI => R1IN_4FF(16),
CI => R1IN_ADD_2_0_CRY_32,
S => R1IN_ADD_2_0_AXB_33,
LO => R1IN_ADD_2_0_CRY_33);
R1IN_ADD_2_0_S_32: XORCY port map (
LI => R1IN_ADD_2_0_AXB_32,
CI => R1IN_ADD_2_0_CRY_31,
O => PRODUCT(49));
R1IN_ADD_2_0_CRY_32_Z8343: MUXCY_L port map (
DI => R1IN_4FF(15),
CI => R1IN_ADD_2_0_CRY_31,
S => R1IN_ADD_2_0_AXB_32,
LO => R1IN_ADD_2_0_CRY_32);
R1IN_ADD_2_0_S_31: XORCY port map (
LI => R1IN_ADD_2_0_AXB_31,
CI => R1IN_ADD_2_0_CRY_30,
O => PRODUCT(48));
R1IN_ADD_2_0_CRY_31_Z8345: MUXCY_L port map (
DI => R1IN_4FF(14),
CI => R1IN_ADD_2_0_CRY_30,
S => R1IN_ADD_2_0_AXB_31,
LO => R1IN_ADD_2_0_CRY_31);
R1IN_ADD_2_0_S_30: XORCY port map (
LI => R1IN_ADD_2_0_AXB_30,
CI => R1IN_ADD_2_0_CRY_29,
O => PRODUCT(47));
R1IN_ADD_2_0_CRY_30_Z8347: MUXCY_L port map (
DI => R1IN_4FF(13),
CI => R1IN_ADD_2_0_CRY_29,
S => R1IN_ADD_2_0_AXB_30,
LO => R1IN_ADD_2_0_CRY_30);
R1IN_ADD_2_0_S_29: XORCY port map (
LI => R1IN_ADD_2_0_AXB_29,
CI => R1IN_ADD_2_0_CRY_28,
O => PRODUCT(46));
R1IN_ADD_2_0_CRY_29_Z8349: MUXCY_L port map (
DI => R1IN_4FF(12),
CI => R1IN_ADD_2_0_CRY_28,
S => R1IN_ADD_2_0_AXB_29,
LO => R1IN_ADD_2_0_CRY_29);
R1IN_ADD_2_0_S_28: XORCY port map (
LI => R1IN_ADD_2_0_AXB_28,
CI => R1IN_ADD_2_0_CRY_27,
O => PRODUCT(45));
R1IN_ADD_2_0_CRY_28_Z8351: MUXCY_L port map (
DI => R1IN_4FF(11),
CI => R1IN_ADD_2_0_CRY_27,
S => R1IN_ADD_2_0_AXB_28,
LO => R1IN_ADD_2_0_CRY_28);
R1IN_ADD_2_0_S_27: XORCY port map (
LI => R1IN_ADD_2_0_AXB_27,
CI => R1IN_ADD_2_0_CRY_26,
O => PRODUCT(44));
R1IN_ADD_2_0_CRY_27_Z8353: MUXCY_L port map (
DI => R1IN_4FF(10),
CI => R1IN_ADD_2_0_CRY_26,
S => R1IN_ADD_2_0_AXB_27,
LO => R1IN_ADD_2_0_CRY_27);
R1IN_ADD_2_0_S_26: XORCY port map (
LI => R1IN_ADD_2_0_AXB_26,
CI => R1IN_ADD_2_0_CRY_25,
O => PRODUCT(43));
R1IN_ADD_2_0_CRY_26_Z8355: MUXCY_L port map (
DI => R1IN_4FF(9),
CI => R1IN_ADD_2_0_CRY_25,
S => R1IN_ADD_2_0_AXB_26,
LO => R1IN_ADD_2_0_CRY_26);
R1IN_ADD_2_0_S_25: XORCY port map (
LI => R1IN_ADD_2_0_AXB_25,
CI => R1IN_ADD_2_0_CRY_24,
O => PRODUCT(42));
R1IN_ADD_2_0_CRY_25_Z8357: MUXCY_L port map (
DI => R1IN_4FF(8),
CI => R1IN_ADD_2_0_CRY_24,
S => R1IN_ADD_2_0_AXB_25,
LO => R1IN_ADD_2_0_CRY_25);
R1IN_ADD_2_0_S_24: XORCY port map (
LI => R1IN_ADD_2_0_AXB_24,
CI => R1IN_ADD_2_0_CRY_23,
O => PRODUCT(41));
R1IN_ADD_2_0_CRY_24_Z8359: MUXCY_L port map (
DI => R1IN_4FF(7),
CI => R1IN_ADD_2_0_CRY_23,
S => R1IN_ADD_2_0_AXB_24,
LO => R1IN_ADD_2_0_CRY_24);
R1IN_ADD_2_0_S_23: XORCY port map (
LI => R1IN_ADD_2_0_AXB_23,
CI => R1IN_ADD_2_0_CRY_22,
O => PRODUCT(40));
R1IN_ADD_2_0_CRY_23_Z8361: MUXCY_L port map (
DI => R1IN_4FF(6),
CI => R1IN_ADD_2_0_CRY_22,
S => R1IN_ADD_2_0_AXB_23,
LO => R1IN_ADD_2_0_CRY_23);
R1IN_ADD_2_0_S_22: XORCY port map (
LI => R1IN_ADD_2_0_AXB_22,
CI => R1IN_ADD_2_0_CRY_21,
O => PRODUCT(39));
R1IN_ADD_2_0_CRY_22_Z8363: MUXCY_L port map (
DI => R1IN_4FF(5),
CI => R1IN_ADD_2_0_CRY_21,
S => R1IN_ADD_2_0_AXB_22,
LO => R1IN_ADD_2_0_CRY_22);
R1IN_ADD_2_0_S_21: XORCY port map (
LI => R1IN_ADD_2_0_AXB_21,
CI => R1IN_ADD_2_0_CRY_20,
O => PRODUCT(38));
R1IN_ADD_2_0_CRY_21_Z8365: MUXCY_L port map (
DI => R1IN_4FF(4),
CI => R1IN_ADD_2_0_CRY_20,
S => R1IN_ADD_2_0_AXB_21,
LO => R1IN_ADD_2_0_CRY_21);
R1IN_ADD_2_0_S_20: XORCY port map (
LI => R1IN_ADD_2_0_AXB_20,
CI => R1IN_ADD_2_0_CRY_19,
O => PRODUCT(37));
R1IN_ADD_2_0_CRY_20_Z8367: MUXCY_L port map (
DI => R1IN_4FF(3),
CI => R1IN_ADD_2_0_CRY_19,
S => R1IN_ADD_2_0_AXB_20,
LO => R1IN_ADD_2_0_CRY_20);
R1IN_ADD_2_0_S_19: XORCY port map (
LI => R1IN_ADD_2_0_AXB_19,
CI => R1IN_ADD_2_0_CRY_18,
O => PRODUCT(36));
R1IN_ADD_2_0_CRY_19_Z8369: MUXCY_L port map (
DI => R1IN_4FF(2),
CI => R1IN_ADD_2_0_CRY_18,
S => R1IN_ADD_2_0_AXB_19,
LO => R1IN_ADD_2_0_CRY_19);
R1IN_ADD_2_0_S_18: XORCY port map (
LI => R1IN_ADD_2_0_AXB_18,
CI => R1IN_ADD_2_0_CRY_17,
O => PRODUCT(35));
R1IN_ADD_2_0_CRY_18_Z8371: MUXCY_L port map (
DI => R1IN_4FF(1),
CI => R1IN_ADD_2_0_CRY_17,
S => R1IN_ADD_2_0_AXB_18,
LO => R1IN_ADD_2_0_CRY_18);
R1IN_ADD_2_0_S_17: XORCY port map (
LI => R1IN_ADD_2_0_AXB_17,
CI => R1IN_ADD_2_0_CRY_16,
O => PRODUCT(34));
R1IN_ADD_2_0_CRY_17_Z8373: MUXCY_L port map (
DI => R1IN_4FF(0),
CI => R1IN_ADD_2_0_CRY_16,
S => R1IN_ADD_2_0_AXB_17,
LO => R1IN_ADD_2_0_CRY_17);
R1IN_ADD_2_0_S_16: XORCY port map (
LI => R1IN_ADD_2_0_AXB_16,
CI => R1IN_ADD_2_0_CRY_15,
O => PRODUCT(33));
R1IN_ADD_2_0_CRY_16_Z8375: MUXCY_L port map (
DI => R1IN_1FF(33),
CI => R1IN_ADD_2_0_CRY_15,
S => R1IN_ADD_2_0_AXB_16,
LO => R1IN_ADD_2_0_CRY_16);
R1IN_ADD_2_0_S_15: XORCY port map (
LI => R1IN_ADD_2_0_AXB_15,
CI => R1IN_ADD_2_0_CRY_14,
O => PRODUCT(32));
R1IN_ADD_2_0_CRY_15_Z8377: MUXCY_L port map (
DI => R1IN_1FF(32),
CI => R1IN_ADD_2_0_CRY_14,
S => R1IN_ADD_2_0_AXB_15,
LO => R1IN_ADD_2_0_CRY_15);
R1IN_ADD_2_0_S_14: XORCY port map (
LI => R1IN_ADD_2_0_AXB_14,
CI => R1IN_ADD_2_0_CRY_13,
O => PRODUCT(31));
R1IN_ADD_2_0_CRY_14_Z8379: MUXCY_L port map (
DI => R1IN_1FF(31),
CI => R1IN_ADD_2_0_CRY_13,
S => R1IN_ADD_2_0_AXB_14,
LO => R1IN_ADD_2_0_CRY_14);
R1IN_ADD_2_0_S_13: XORCY port map (
LI => R1IN_ADD_2_0_AXB_13,
CI => R1IN_ADD_2_0_CRY_12,
O => PRODUCT(30));
R1IN_ADD_2_0_CRY_13_Z8381: MUXCY_L port map (
DI => R1IN_1FF(30),
CI => R1IN_ADD_2_0_CRY_12,
S => R1IN_ADD_2_0_AXB_13,
LO => R1IN_ADD_2_0_CRY_13);
R1IN_ADD_2_0_S_12: XORCY port map (
LI => R1IN_ADD_2_0_AXB_12,
CI => R1IN_ADD_2_0_CRY_11,
O => PRODUCT(29));
R1IN_ADD_2_0_CRY_12_Z8383: MUXCY_L port map (
DI => R1IN_1FF(29),
CI => R1IN_ADD_2_0_CRY_11,
S => R1IN_ADD_2_0_AXB_12,
LO => R1IN_ADD_2_0_CRY_12);
R1IN_ADD_2_0_S_11: XORCY port map (
LI => R1IN_ADD_2_0_AXB_11,
CI => R1IN_ADD_2_0_CRY_10,
O => PRODUCT(28));
R1IN_ADD_2_0_CRY_11_Z8385: MUXCY_L port map (
DI => R1IN_1FF(28),
CI => R1IN_ADD_2_0_CRY_10,
S => R1IN_ADD_2_0_AXB_11,
LO => R1IN_ADD_2_0_CRY_11);
R1IN_ADD_2_0_S_10: XORCY port map (
LI => R1IN_ADD_2_0_AXB_10,
CI => R1IN_ADD_2_0_CRY_9,
O => PRODUCT(27));
R1IN_ADD_2_0_CRY_10_Z8387: MUXCY_L port map (
DI => R1IN_1FF(27),
CI => R1IN_ADD_2_0_CRY_9,
S => R1IN_ADD_2_0_AXB_10,
LO => R1IN_ADD_2_0_CRY_10);
R1IN_ADD_2_0_S_9: XORCY port map (
LI => R1IN_ADD_2_0_AXB_9,
CI => R1IN_ADD_2_0_CRY_8,
O => PRODUCT(26));
R1IN_ADD_2_0_CRY_9_Z8389: MUXCY_L port map (
DI => R1IN_1FF(26),
CI => R1IN_ADD_2_0_CRY_8,
S => R1IN_ADD_2_0_AXB_9,
LO => R1IN_ADD_2_0_CRY_9);
R1IN_ADD_2_0_S_8: XORCY port map (
LI => R1IN_ADD_2_0_AXB_8,
CI => R1IN_ADD_2_0_CRY_7,
O => PRODUCT(25));
R1IN_ADD_2_0_CRY_8_Z8391: MUXCY_L port map (
DI => R1IN_1FF(25),
CI => R1IN_ADD_2_0_CRY_7,
S => R1IN_ADD_2_0_AXB_8,
LO => R1IN_ADD_2_0_CRY_8);
R1IN_ADD_2_0_S_7: XORCY port map (
LI => R1IN_ADD_2_0_AXB_7,
CI => R1IN_ADD_2_0_CRY_6,
O => PRODUCT(24));
R1IN_ADD_2_0_CRY_7_Z8393: MUXCY_L port map (
DI => R1IN_1FF(24),
CI => R1IN_ADD_2_0_CRY_6,
S => R1IN_ADD_2_0_AXB_7,
LO => R1IN_ADD_2_0_CRY_7);
R1IN_ADD_2_0_S_6: XORCY port map (
LI => R1IN_ADD_2_0_AXB_6,
CI => R1IN_ADD_2_0_CRY_5,
O => PRODUCT(23));
R1IN_ADD_2_0_CRY_6_Z8395: MUXCY_L port map (
DI => R1IN_1FF(23),
CI => R1IN_ADD_2_0_CRY_5,
S => R1IN_ADD_2_0_AXB_6,
LO => R1IN_ADD_2_0_CRY_6);
R1IN_ADD_2_0_S_5: XORCY port map (
LI => R1IN_ADD_2_0_AXB_5,
CI => R1IN_ADD_2_0_CRY_4,
O => PRODUCT(22));
R1IN_ADD_2_0_CRY_5_Z8397: MUXCY_L port map (
DI => R1IN_1FF(22),
CI => R1IN_ADD_2_0_CRY_4,
S => R1IN_ADD_2_0_AXB_5,
LO => R1IN_ADD_2_0_CRY_5);
R1IN_ADD_2_0_S_4: XORCY port map (
LI => R1IN_ADD_2_0_AXB_4,
CI => R1IN_ADD_2_0_CRY_3,
O => PRODUCT(21));
R1IN_ADD_2_0_CRY_4_Z8399: MUXCY_L port map (
DI => R1IN_1FF(21),
CI => R1IN_ADD_2_0_CRY_3,
S => R1IN_ADD_2_0_AXB_4,
LO => R1IN_ADD_2_0_CRY_4);
R1IN_ADD_2_0_S_3: XORCY port map (
LI => R1IN_ADD_2_0_AXB_3,
CI => R1IN_ADD_2_0_CRY_2,
O => PRODUCT(20));
R1IN_ADD_2_0_CRY_3_Z8401: MUXCY_L port map (
DI => R1IN_1FF(20),
CI => R1IN_ADD_2_0_CRY_2,
S => R1IN_ADD_2_0_AXB_3,
LO => R1IN_ADD_2_0_CRY_3);
R1IN_ADD_2_0_S_2: XORCY port map (
LI => R1IN_ADD_2_0_AXB_2,
CI => R1IN_ADD_2_0_CRY_1,
O => PRODUCT(19));
R1IN_ADD_2_0_CRY_2_Z8403: MUXCY_L port map (
DI => R1IN_1FF(19),
CI => R1IN_ADD_2_0_CRY_1,
S => R1IN_ADD_2_0_AXB_2,
LO => R1IN_ADD_2_0_CRY_2);
R1IN_ADD_2_0_S_1: XORCY port map (
LI => R1IN_ADD_2_0_AXB_1,
CI => R1IN_ADD_2_0_CRY_0,
O => PRODUCT(18));
R1IN_ADD_2_0_CRY_1_Z8405: MUXCY_L port map (
DI => R1IN_1FF(18),
CI => R1IN_ADD_2_0_CRY_0,
S => R1IN_ADD_2_0_AXB_1,
LO => R1IN_ADD_2_0_CRY_1);
R1IN_ADD_2_0_CRY_0_Z8406: MUXCY_L port map (
DI => R1IN_ADD_2_0,
CI => NN_1,
S => NN_11,
LO => R1IN_ADD_2_0_CRY_0);
R1IN_4_ADD_2_1_S_34: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_34,
CI => R1IN_4_ADD_2_1_CRY_33,
O => N_1781_RETI);
R1IN_4_ADD_2_1_S_33: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_33,
CI => R1IN_4_ADD_2_1_CRY_32,
O => N_1779_RETI);
R1IN_4_ADD_2_1_CRY_33_Z8409: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_32,
S => R1IN_4_ADD_2_1_AXB_33,
LO => R1IN_4_ADD_2_1_CRY_33);
R1IN_4_ADD_2_1_S_32: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_32,
CI => R1IN_4_ADD_2_1_CRY_31,
O => N_1777_RETI);
R1IN_4_ADD_2_1_CRY_32_Z8411: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_31,
S => R1IN_4_ADD_2_1_AXB_32,
LO => R1IN_4_ADD_2_1_CRY_32);
R1IN_4_ADD_2_1_S_31: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_31,
CI => R1IN_4_ADD_2_1_CRY_30,
O => N_1775_RETI);
R1IN_4_ADD_2_1_CRY_31_Z8413: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_30,
S => R1IN_4_ADD_2_1_AXB_31,
LO => R1IN_4_ADD_2_1_CRY_31);
R1IN_4_ADD_2_1_S_30: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_30,
CI => R1IN_4_ADD_2_1_CRY_29,
O => N_1773_RETI);
R1IN_4_ADD_2_1_CRY_30_Z8415: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_29,
S => R1IN_4_ADD_2_1_AXB_30,
LO => R1IN_4_ADD_2_1_CRY_30);
R1IN_4_ADD_2_1_S_29: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_29,
CI => R1IN_4_ADD_2_1_CRY_28,
O => N_1771_RETI);
R1IN_4_ADD_2_1_CRY_29_Z8417: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_28,
S => R1IN_4_ADD_2_1_AXB_29,
LO => R1IN_4_ADD_2_1_CRY_29);
R1IN_4_ADD_2_1_S_28: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_28,
CI => R1IN_4_ADD_2_1_CRY_27,
O => N_1769_RETI);
R1IN_4_ADD_2_1_CRY_28_Z8419: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_27,
S => R1IN_4_ADD_2_1_AXB_28,
LO => R1IN_4_ADD_2_1_CRY_28);
R1IN_4_ADD_2_1_S_27: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_27,
CI => R1IN_4_ADD_2_1_CRY_26,
O => N_1767_RETI);
R1IN_4_ADD_2_1_CRY_27_Z8421: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_26,
S => R1IN_4_ADD_2_1_AXB_27,
LO => R1IN_4_ADD_2_1_CRY_27);
R1IN_4_ADD_2_1_S_26: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_26,
CI => R1IN_4_ADD_2_1_CRY_25,
O => N_1765_RETI);
R1IN_4_ADD_2_1_CRY_26_Z8423: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_25,
S => R1IN_4_ADD_2_1_AXB_26,
LO => R1IN_4_ADD_2_1_CRY_26);
R1IN_4_ADD_2_1_S_25: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_25,
CI => R1IN_4_ADD_2_1_CRY_24,
O => N_1763_RETI);
R1IN_4_ADD_2_1_CRY_25_Z8425: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_24,
S => R1IN_4_ADD_2_1_AXB_25,
LO => R1IN_4_ADD_2_1_CRY_25);
R1IN_4_ADD_2_1_S_24: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_24,
CI => R1IN_4_ADD_2_1_CRY_23,
O => N_1761_RETI);
R1IN_4_ADD_2_1_CRY_24_Z8427: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_23,
S => R1IN_4_ADD_2_1_AXB_24,
LO => R1IN_4_ADD_2_1_CRY_24);
R1IN_4_ADD_2_1_S_23: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_23,
CI => R1IN_4_ADD_2_1_CRY_22,
O => N_1759_RETI);
R1IN_4_ADD_2_1_CRY_23_Z8429: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_22,
S => R1IN_4_ADD_2_1_AXB_23,
LO => R1IN_4_ADD_2_1_CRY_23);
R1IN_4_ADD_2_1_S_22: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_22,
CI => R1IN_4_ADD_2_1_CRY_21,
O => N_1757_RETI);
R1IN_4_ADD_2_1_CRY_22_Z8431: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_21,
S => R1IN_4_ADD_2_1_AXB_22,
LO => R1IN_4_ADD_2_1_CRY_22);
R1IN_4_ADD_2_1_S_21: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_21,
CI => R1IN_4_ADD_2_1_CRY_20,
O => N_1755_RETI);
R1IN_4_ADD_2_1_CRY_21_Z8433: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_20,
S => R1IN_4_ADD_2_1_AXB_21,
LO => R1IN_4_ADD_2_1_CRY_21);
R1IN_4_ADD_2_1_S_20: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_20,
CI => R1IN_4_ADD_2_1_CRY_19,
O => N_1753_RETI);
R1IN_4_ADD_2_1_CRY_20_Z8435: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_19,
S => R1IN_4_ADD_2_1_AXB_20,
LO => R1IN_4_ADD_2_1_CRY_20);
R1IN_4_ADD_2_1_S_19: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_19,
CI => R1IN_4_ADD_2_1_CRY_18,
O => N_1751_RETI);
R1IN_4_ADD_2_1_CRY_19_Z8437: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_18,
S => R1IN_4_ADD_2_1_AXB_19,
LO => R1IN_4_ADD_2_1_CRY_19);
R1IN_4_ADD_2_1_S_18: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_18,
CI => R1IN_4_ADD_2_1_CRY_17,
O => N_1749_RETI);
R1IN_4_ADD_2_1_CRY_18_Z8439: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_17,
S => R1IN_4_ADD_2_1_AXB_18,
LO => R1IN_4_ADD_2_1_CRY_18);
R1IN_4_ADD_2_1_S_17: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_17,
CI => R1IN_4_ADD_2_1_CRY_16,
O => N_1747_RETI);
R1IN_4_ADD_2_1_CRY_17_Z8441: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_16,
S => R1IN_4_ADD_2_1_AXB_17,
LO => R1IN_4_ADD_2_1_CRY_17);
R1IN_4_ADD_2_1_S_16: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_16,
CI => R1IN_4_ADD_2_1_CRY_15,
O => N_1745_RETI);
R1IN_4_ADD_2_1_CRY_16_Z8443: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_15,
S => R1IN_4_ADD_2_1_AXB_16,
LO => R1IN_4_ADD_2_1_CRY_16);
R1IN_4_ADD_2_1_S_15: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_15,
CI => R1IN_4_ADD_2_1_CRY_14,
O => N_1743_RETI);
R1IN_4_ADD_2_1_CRY_15_Z8445: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_14,
S => R1IN_4_ADD_2_1_AXB_15,
LO => R1IN_4_ADD_2_1_CRY_15);
R1IN_4_ADD_2_1_S_14: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_14,
CI => R1IN_4_ADD_2_1_CRY_13,
O => N_1741_RETI);
R1IN_4_ADD_2_1_CRY_14_Z8447: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_13,
S => R1IN_4_ADD_2_1_AXB_14,
LO => R1IN_4_ADD_2_1_CRY_14);
R1IN_4_ADD_2_1_S_13: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_13,
CI => R1IN_4_ADD_2_1_CRY_12,
O => N_1739_RETI);
R1IN_4_ADD_2_1_CRY_13_Z8449: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_12,
S => R1IN_4_ADD_2_1_AXB_13,
LO => R1IN_4_ADD_2_1_CRY_13);
R1IN_4_ADD_2_1_S_12: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_12,
CI => R1IN_4_ADD_2_1_CRY_11,
O => N_1737_RETI);
R1IN_4_ADD_2_1_CRY_12_Z8451: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_11,
S => R1IN_4_ADD_2_1_AXB_12,
LO => R1IN_4_ADD_2_1_CRY_12);
R1IN_4_ADD_2_1_S_11: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_11,
CI => R1IN_4_ADD_2_1_CRY_10,
O => N_1735_RETI);
R1IN_4_ADD_2_1_CRY_11_Z8453: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_10,
S => R1IN_4_ADD_2_1_AXB_11,
LO => R1IN_4_ADD_2_1_CRY_11);
R1IN_4_ADD_2_1_S_10: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_10,
CI => R1IN_4_ADD_2_1_CRY_9,
O => N_1733_RETI);
R1IN_4_ADD_2_1_CRY_10_Z8455: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_9,
S => R1IN_4_ADD_2_1_AXB_10,
LO => R1IN_4_ADD_2_1_CRY_10);
R1IN_4_ADD_2_1_S_9: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_9,
CI => R1IN_4_ADD_2_1_CRY_8,
O => N_1731_RETI);
R1IN_4_ADD_2_1_CRY_9_Z8457: MUXCY_L port map (
DI => NN_1,
CI => R1IN_4_ADD_2_1_CRY_8,
S => R1IN_4_ADD_2_1_AXB_9,
LO => R1IN_4_ADD_2_1_CRY_9);
R1IN_4_ADD_2_1_S_8: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_8,
CI => R1IN_4_ADD_2_1_CRY_7,
O => N_1729_RETI);
R1IN_4_ADD_2_1_CRY_8_Z8459: MUXCY_L port map (
DI => NN_10,
CI => R1IN_4_ADD_2_1_CRY_7,
S => R1IN_4_ADD_2_1_AXB_8,
LO => R1IN_4_ADD_2_1_CRY_8);
R1IN_4_ADD_2_1_S_7: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_7,
CI => R1IN_4_ADD_2_1_CRY_6,
O => N_1727_RETI);
R1IN_4_ADD_2_1_CRY_7_Z8461: MUXCY_L port map (
DI => NN_9,
CI => R1IN_4_ADD_2_1_CRY_6,
S => R1IN_4_ADD_2_1_AXB_7,
LO => R1IN_4_ADD_2_1_CRY_7);
R1IN_4_ADD_2_1_S_6: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_6,
CI => R1IN_4_ADD_2_1_CRY_5,
O => N_1725_RETI);
R1IN_4_ADD_2_1_CRY_6_Z8463: MUXCY_L port map (
DI => NN_8,
CI => R1IN_4_ADD_2_1_CRY_5,
S => R1IN_4_ADD_2_1_AXB_6,
LO => R1IN_4_ADD_2_1_CRY_6);
R1IN_4_ADD_2_1_S_5: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_5,
CI => R1IN_4_ADD_2_1_CRY_4,
O => N_1723_RETI);
R1IN_4_ADD_2_1_CRY_5_Z8465: MUXCY_L port map (
DI => NN_7,
CI => R1IN_4_ADD_2_1_CRY_4,
S => R1IN_4_ADD_2_1_AXB_5,
LO => R1IN_4_ADD_2_1_CRY_5);
R1IN_4_ADD_2_1_S_4: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_4,
CI => R1IN_4_ADD_2_1_CRY_3,
O => N_1721_RETI);
R1IN_4_ADD_2_1_CRY_4_Z8467: MUXCY_L port map (
DI => NN_6,
CI => R1IN_4_ADD_2_1_CRY_3,
S => R1IN_4_ADD_2_1_AXB_4,
LO => R1IN_4_ADD_2_1_CRY_4);
R1IN_4_ADD_2_1_S_3: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_3,
CI => R1IN_4_ADD_2_1_CRY_2,
O => N_1719_RETI);
R1IN_4_ADD_2_1_CRY_3_Z8469: MUXCY_L port map (
DI => NN_5,
CI => R1IN_4_ADD_2_1_CRY_2,
S => R1IN_4_ADD_2_1_AXB_3,
LO => R1IN_4_ADD_2_1_CRY_3);
R1IN_4_ADD_2_1_S_2: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_2,
CI => R1IN_4_ADD_2_1_CRY_1,
O => N_1717_RETI);
R1IN_4_ADD_2_1_CRY_2_Z8471: MUXCY_L port map (
DI => NN_4,
CI => R1IN_4_ADD_2_1_CRY_1,
S => R1IN_4_ADD_2_1_AXB_2,
LO => R1IN_4_ADD_2_1_CRY_2);
R1IN_4_ADD_2_1_S_1: XORCY port map (
LI => R1IN_4_ADD_2_1_AXB_1,
CI => R1IN_4_ADD_2_1_CRY_0,
O => N_1715_RETI);
R1IN_4_ADD_2_1_CRY_1_Z8473: MUXCY_L port map (
DI => NN_3,
CI => R1IN_4_ADD_2_1_CRY_0,
S => R1IN_4_ADD_2_1_AXB_1,
LO => R1IN_4_ADD_2_1_CRY_1);
R1IN_4_ADD_2_1_CRY_0_Z8474: MUXCY_L port map (
DI => R1IN_4_ADD_2_1,
CI => NN_1,
S => R1IN_4_ADD_2_1_AXB_0_RETI,
LO => R1IN_4_ADD_2_1_CRY_0);
R1IN_4_ADD_2_0_S_35: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_35,
CI => R1IN_4_ADD_2_0_CRY_34,
O => R1IN_4(52));
R1IN_4_ADD_2_0_CRY_35_Z8476: MUXCY port map (
DI => R1IN_4_ADD_1(35),
CI => R1IN_4_ADD_2_0_CRY_34,
S => R1IN_4_ADD_2_0_AXB_35,
O => R1IN_4_ADD_2_0_CRY_35);
R1IN_4_ADD_2_0_S_34: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_34,
CI => R1IN_4_ADD_2_0_CRY_33,
O => R1IN_4(51));
R1IN_4_ADD_2_0_CRY_34_Z8478: MUXCY_L port map (
DI => R1IN_4_ADD_1(34),
CI => R1IN_4_ADD_2_0_CRY_33,
S => R1IN_4_ADD_2_0_AXB_34,
LO => R1IN_4_ADD_2_0_CRY_34);
R1IN_4_ADD_2_0_S_33: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_33,
CI => R1IN_4_ADD_2_0_CRY_32,
O => R1IN_4(50));
R1IN_4_ADD_2_0_CRY_33_Z8480: MUXCY_L port map (
DI => R1IN_4_ADD_1(33),
CI => R1IN_4_ADD_2_0_CRY_32,
S => R1IN_4_ADD_2_0_AXB_33,
LO => R1IN_4_ADD_2_0_CRY_33);
R1IN_4_ADD_2_0_S_32: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_32,
CI => R1IN_4_ADD_2_0_CRY_31,
O => R1IN_4(49));
R1IN_4_ADD_2_0_CRY_32_Z8482: MUXCY_L port map (
DI => R1IN_4_ADD_1(32),
CI => R1IN_4_ADD_2_0_CRY_31,
S => R1IN_4_ADD_2_0_AXB_32,
LO => R1IN_4_ADD_2_0_CRY_32);
R1IN_4_ADD_2_0_S_31: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_31,
CI => R1IN_4_ADD_2_0_CRY_30,
O => R1IN_4(48));
R1IN_4_ADD_2_0_CRY_31_Z8484: MUXCY_L port map (
DI => R1IN_4_ADD_1(31),
CI => R1IN_4_ADD_2_0_CRY_30,
S => R1IN_4_ADD_2_0_AXB_31,
LO => R1IN_4_ADD_2_0_CRY_31);
R1IN_4_ADD_2_0_S_30: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_30,
CI => R1IN_4_ADD_2_0_CRY_29,
O => R1IN_4(47));
R1IN_4_ADD_2_0_CRY_30_Z8486: MUXCY_L port map (
DI => R1IN_4_ADD_1(30),
CI => R1IN_4_ADD_2_0_CRY_29,
S => R1IN_4_ADD_2_0_AXB_30,
LO => R1IN_4_ADD_2_0_CRY_30);
R1IN_4_ADD_2_0_S_29: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_29,
CI => R1IN_4_ADD_2_0_CRY_28,
O => R1IN_4(46));
R1IN_4_ADD_2_0_CRY_29_Z8488: MUXCY_L port map (
DI => R1IN_4_ADD_1(29),
CI => R1IN_4_ADD_2_0_CRY_28,
S => R1IN_4_ADD_2_0_AXB_29,
LO => R1IN_4_ADD_2_0_CRY_29);
R1IN_4_ADD_2_0_S_28: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_28,
CI => R1IN_4_ADD_2_0_CRY_27,
O => R1IN_4(45));
R1IN_4_ADD_2_0_CRY_28_Z8490: MUXCY_L port map (
DI => R1IN_4_ADD_1(28),
CI => R1IN_4_ADD_2_0_CRY_27,
S => R1IN_4_ADD_2_0_AXB_28,
LO => R1IN_4_ADD_2_0_CRY_28);
R1IN_4_ADD_2_0_S_27: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_27,
CI => R1IN_4_ADD_2_0_CRY_26,
O => R1IN_4(44));
R1IN_4_ADD_2_0_CRY_27_Z8492: MUXCY_L port map (
DI => R1IN_4_ADD_1(27),
CI => R1IN_4_ADD_2_0_CRY_26,
S => R1IN_4_ADD_2_0_AXB_27,
LO => R1IN_4_ADD_2_0_CRY_27);
R1IN_4_ADD_2_0_S_26: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_26,
CI => R1IN_4_ADD_2_0_CRY_25,
O => R1IN_4(43));
R1IN_4_ADD_2_0_CRY_26_Z8494: MUXCY_L port map (
DI => R1IN_4_ADD_1(26),
CI => R1IN_4_ADD_2_0_CRY_25,
S => R1IN_4_ADD_2_0_AXB_26,
LO => R1IN_4_ADD_2_0_CRY_26);
R1IN_4_ADD_2_0_S_25: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_25,
CI => R1IN_4_ADD_2_0_CRY_24,
O => R1IN_4(42));
R1IN_4_ADD_2_0_CRY_25_Z8496: MUXCY_L port map (
DI => R1IN_4_ADD_1(25),
CI => R1IN_4_ADD_2_0_CRY_24,
S => R1IN_4_ADD_2_0_AXB_25,
LO => R1IN_4_ADD_2_0_CRY_25);
R1IN_4_ADD_2_0_S_24: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_24,
CI => R1IN_4_ADD_2_0_CRY_23,
O => R1IN_4(41));
R1IN_4_ADD_2_0_CRY_24_Z8498: MUXCY_L port map (
DI => R1IN_4_ADD_1(24),
CI => R1IN_4_ADD_2_0_CRY_23,
S => R1IN_4_ADD_2_0_AXB_24,
LO => R1IN_4_ADD_2_0_CRY_24);
R1IN_4_ADD_2_0_S_23: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_23,
CI => R1IN_4_ADD_2_0_CRY_22,
O => R1IN_4(40));
R1IN_4_ADD_2_0_CRY_23_Z8500: MUXCY_L port map (
DI => R1IN_4_ADD_1(23),
CI => R1IN_4_ADD_2_0_CRY_22,
S => R1IN_4_ADD_2_0_AXB_23,
LO => R1IN_4_ADD_2_0_CRY_23);
R1IN_4_ADD_2_0_S_22: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_22,
CI => R1IN_4_ADD_2_0_CRY_21,
O => R1IN_4(39));
R1IN_4_ADD_2_0_CRY_22_Z8502: MUXCY_L port map (
DI => R1IN_4_ADD_1(22),
CI => R1IN_4_ADD_2_0_CRY_21,
S => R1IN_4_ADD_2_0_AXB_22,
LO => R1IN_4_ADD_2_0_CRY_22);
R1IN_4_ADD_2_0_S_21: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_21,
CI => R1IN_4_ADD_2_0_CRY_20,
O => R1IN_4(38));
R1IN_4_ADD_2_0_CRY_21_Z8504: MUXCY_L port map (
DI => R1IN_4_ADD_1(21),
CI => R1IN_4_ADD_2_0_CRY_20,
S => R1IN_4_ADD_2_0_AXB_21,
LO => R1IN_4_ADD_2_0_CRY_21);
R1IN_4_ADD_2_0_S_20: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_20,
CI => R1IN_4_ADD_2_0_CRY_19,
O => R1IN_4(37));
R1IN_4_ADD_2_0_CRY_20_Z8506: MUXCY_L port map (
DI => R1IN_4_ADD_1(20),
CI => R1IN_4_ADD_2_0_CRY_19,
S => R1IN_4_ADD_2_0_AXB_20,
LO => R1IN_4_ADD_2_0_CRY_20);
R1IN_4_ADD_2_0_S_19: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_19,
CI => R1IN_4_ADD_2_0_CRY_18,
O => R1IN_4(36));
R1IN_4_ADD_2_0_CRY_19_Z8508: MUXCY_L port map (
DI => R1IN_4_ADD_1(19),
CI => R1IN_4_ADD_2_0_CRY_18,
S => R1IN_4_ADD_2_0_AXB_19,
LO => R1IN_4_ADD_2_0_CRY_19);
R1IN_4_ADD_2_0_S_18: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_18,
CI => R1IN_4_ADD_2_0_CRY_17,
O => R1IN_4(35));
R1IN_4_ADD_2_0_CRY_18_Z8510: MUXCY_L port map (
DI => R1IN_4_ADD_1(18),
CI => R1IN_4_ADD_2_0_CRY_17,
S => R1IN_4_ADD_2_0_AXB_18,
LO => R1IN_4_ADD_2_0_CRY_18);
R1IN_4_ADD_2_0_S_17: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_17,
CI => R1IN_4_ADD_2_0_CRY_16,
O => R1IN_4(34));
R1IN_4_ADD_2_0_CRY_17_Z8512: MUXCY_L port map (
DI => R1IN_4_ADD_1(17),
CI => R1IN_4_ADD_2_0_CRY_16,
S => R1IN_4_ADD_2_0_AXB_17,
LO => R1IN_4_ADD_2_0_CRY_17);
R1IN_4_ADD_2_0_S_16: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_16,
CI => R1IN_4_ADD_2_0_CRY_15,
O => R1IN_4(33));
R1IN_4_ADD_2_0_CRY_16_Z8514: MUXCY_L port map (
DI => R1IN_4_ADD_1(16),
CI => R1IN_4_ADD_2_0_CRY_15,
S => R1IN_4_ADD_2_0_AXB_16,
LO => R1IN_4_ADD_2_0_CRY_16);
R1IN_4_ADD_2_0_S_15: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_15,
CI => R1IN_4_ADD_2_0_CRY_14,
O => R1IN_4(32));
R1IN_4_ADD_2_0_CRY_15_Z8516: MUXCY_L port map (
DI => R1IN_4_ADD_1(15),
CI => R1IN_4_ADD_2_0_CRY_14,
S => R1IN_4_ADD_2_0_AXB_15,
LO => R1IN_4_ADD_2_0_CRY_15);
R1IN_4_ADD_2_0_S_14: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_14,
CI => R1IN_4_ADD_2_0_CRY_13,
O => R1IN_4(31));
R1IN_4_ADD_2_0_CRY_14_Z8518: MUXCY_L port map (
DI => R1IN_4_ADD_1(14),
CI => R1IN_4_ADD_2_0_CRY_13,
S => R1IN_4_ADD_2_0_AXB_14,
LO => R1IN_4_ADD_2_0_CRY_14);
R1IN_4_ADD_2_0_S_13: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_13,
CI => R1IN_4_ADD_2_0_CRY_12,
O => R1IN_4(30));
R1IN_4_ADD_2_0_CRY_13_Z8520: MUXCY_L port map (
DI => R1IN_4_ADD_1(13),
CI => R1IN_4_ADD_2_0_CRY_12,
S => R1IN_4_ADD_2_0_AXB_13,
LO => R1IN_4_ADD_2_0_CRY_13);
R1IN_4_ADD_2_0_S_12: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_12,
CI => R1IN_4_ADD_2_0_CRY_11,
O => R1IN_4(29));
R1IN_4_ADD_2_0_CRY_12_Z8522: MUXCY_L port map (
DI => R1IN_4_ADD_1(12),
CI => R1IN_4_ADD_2_0_CRY_11,
S => R1IN_4_ADD_2_0_AXB_12,
LO => R1IN_4_ADD_2_0_CRY_12);
R1IN_4_ADD_2_0_S_11: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_11,
CI => R1IN_4_ADD_2_0_CRY_10,
O => R1IN_4(28));
R1IN_4_ADD_2_0_CRY_11_Z8524: MUXCY_L port map (
DI => R1IN_4_ADD_1(11),
CI => R1IN_4_ADD_2_0_CRY_10,
S => R1IN_4_ADD_2_0_AXB_11,
LO => R1IN_4_ADD_2_0_CRY_11);
R1IN_4_ADD_2_0_S_10: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_10,
CI => R1IN_4_ADD_2_0_CRY_9,
O => R1IN_4(27));
R1IN_4_ADD_2_0_CRY_10_Z8526: MUXCY_L port map (
DI => R1IN_4_ADD_1(10),
CI => R1IN_4_ADD_2_0_CRY_9,
S => R1IN_4_ADD_2_0_AXB_10,
LO => R1IN_4_ADD_2_0_CRY_10);
R1IN_4_ADD_2_0_S_9: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_9,
CI => R1IN_4_ADD_2_0_CRY_8,
O => R1IN_4(26));
R1IN_4_ADD_2_0_CRY_9_Z8528: MUXCY_L port map (
DI => R1IN_4_ADD_1(9),
CI => R1IN_4_ADD_2_0_CRY_8,
S => R1IN_4_ADD_2_0_AXB_9,
LO => R1IN_4_ADD_2_0_CRY_9);
R1IN_4_ADD_2_0_S_8: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_8,
CI => R1IN_4_ADD_2_0_CRY_7,
O => R1IN_4(25));
R1IN_4_ADD_2_0_CRY_8_Z8530: MUXCY_L port map (
DI => R1IN_4_ADD_1(8),
CI => R1IN_4_ADD_2_0_CRY_7,
S => R1IN_4_ADD_2_0_AXB_8,
LO => R1IN_4_ADD_2_0_CRY_8);
R1IN_4_ADD_2_0_S_7: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_7,
CI => R1IN_4_ADD_2_0_CRY_6,
O => R1IN_4(24));
R1IN_4_ADD_2_0_CRY_7_Z8532: MUXCY_L port map (
DI => R1IN_4_ADD_1(7),
CI => R1IN_4_ADD_2_0_CRY_6,
S => R1IN_4_ADD_2_0_AXB_7,
LO => R1IN_4_ADD_2_0_CRY_7);
R1IN_4_ADD_2_0_S_6: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_6,
CI => R1IN_4_ADD_2_0_CRY_5,
O => R1IN_4(23));
R1IN_4_ADD_2_0_CRY_6_Z8534: MUXCY_L port map (
DI => R1IN_4_ADD_1(6),
CI => R1IN_4_ADD_2_0_CRY_5,
S => R1IN_4_ADD_2_0_AXB_6,
LO => R1IN_4_ADD_2_0_CRY_6);
R1IN_4_ADD_2_0_S_5: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_5,
CI => R1IN_4_ADD_2_0_CRY_4,
O => R1IN_4(22));
R1IN_4_ADD_2_0_CRY_5_Z8536: MUXCY_L port map (
DI => R1IN_4_ADD_1(5),
CI => R1IN_4_ADD_2_0_CRY_4,
S => R1IN_4_ADD_2_0_AXB_5,
LO => R1IN_4_ADD_2_0_CRY_5);
R1IN_4_ADD_2_0_S_4: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_4,
CI => R1IN_4_ADD_2_0_CRY_3,
O => R1IN_4(21));
R1IN_4_ADD_2_0_CRY_4_Z8538: MUXCY_L port map (
DI => R1IN_4_ADD_1(4),
CI => R1IN_4_ADD_2_0_CRY_3,
S => R1IN_4_ADD_2_0_AXB_4,
LO => R1IN_4_ADD_2_0_CRY_4);
R1IN_4_ADD_2_0_S_3: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_3,
CI => R1IN_4_ADD_2_0_CRY_2,
O => R1IN_4(20));
R1IN_4_ADD_2_0_CRY_3_Z8540: MUXCY_L port map (
DI => R1IN_4_ADD_1(3),
CI => R1IN_4_ADD_2_0_CRY_2,
S => R1IN_4_ADD_2_0_AXB_3,
LO => R1IN_4_ADD_2_0_CRY_3);
R1IN_4_ADD_2_0_S_2: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_2,
CI => R1IN_4_ADD_2_0_CRY_1,
O => R1IN_4(19));
R1IN_4_ADD_2_0_CRY_2_Z8542: MUXCY_L port map (
DI => R1IN_4_ADD_1(2),
CI => R1IN_4_ADD_2_0_CRY_1,
S => R1IN_4_ADD_2_0_AXB_2,
LO => R1IN_4_ADD_2_0_CRY_2);
R1IN_4_ADD_2_0_S_1: XORCY port map (
LI => R1IN_4_ADD_2_0_AXB_1,
CI => R1IN_4_ADD_2_0_CRY_0,
O => R1IN_4(18));
R1IN_4_ADD_2_0_CRY_1_Z8544: MUXCY_L port map (
DI => R1IN_4_ADD_1(1),
CI => R1IN_4_ADD_2_0_CRY_0,
S => R1IN_4_ADD_2_0_AXB_1,
LO => R1IN_4_ADD_2_0_CRY_1);
R1IN_4_ADD_2_0_CRY_0_Z8545: MUXCY_L port map (
DI => R1IN_4_ADD_2_0,
CI => NN_1,
S => R1IN_4(17),
LO => R1IN_4_ADD_2_0_CRY_0);
\R1IN_4_4_4[19:0]\: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 1,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => A(51),
A(1) => A(52),
A(2) => A(53),
A(3) => A(54),
A(4) => A(55),
A(5) => A(56),
A(6) => A(57),
A(7) => A(58),
A(8) => A(59),
A(9) => A(60),
A(10) => NN_1,
A(11) => NN_1,
A(12) => NN_1,
A(13) => NN_1,
A(14) => NN_1,
A(15) => NN_1,
A(16) => NN_1,
A(17) => NN_1,
B(0) => B(51),
B(1) => B(52),
B(2) => B(53),
B(3) => B(54),
B(4) => B(55),
B(5) => B(56),
B(6) => B(57),
B(7) => B(58),
B(8) => B(59),
B(9) => B(60),
B(10) => NN_1,
B(11) => NN_1,
B(12) => NN_1,
B(13) => NN_1,
B(14) => NN_1,
B(15) => NN_1,
B(16) => NN_1,
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => EN,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_4_4_4_BCOUT(0),
BCOUT(1) => R1IN_4_4_4_BCOUT(1),
BCOUT(2) => R1IN_4_4_4_BCOUT(2),
BCOUT(3) => R1IN_4_4_4_BCOUT(3),
BCOUT(4) => R1IN_4_4_4_BCOUT(4),
BCOUT(5) => R1IN_4_4_4_BCOUT(5),
BCOUT(6) => R1IN_4_4_4_BCOUT(6),
BCOUT(7) => R1IN_4_4_4_BCOUT(7),
BCOUT(8) => R1IN_4_4_4_BCOUT(8),
BCOUT(9) => R1IN_4_4_4_BCOUT(9),
BCOUT(10) => R1IN_4_4_4_BCOUT(10),
BCOUT(11) => R1IN_4_4_4_BCOUT(11),
BCOUT(12) => R1IN_4_4_4_BCOUT(12),
BCOUT(13) => R1IN_4_4_4_BCOUT(13),
BCOUT(14) => R1IN_4_4_4_BCOUT(14),
BCOUT(15) => R1IN_4_4_4_BCOUT(15),
BCOUT(16) => R1IN_4_4_4_BCOUT(16),
BCOUT(17) => R1IN_4_4_4_BCOUT(17),
P(0) => R1IN_4_4_4F(0),
P(1) => R1IN_4_4_4F(1),
P(2) => R1IN_4_4_4F(2),
P(3) => R1IN_4_4_4F(3),
P(4) => R1IN_4_4_4F(4),
P(5) => R1IN_4_4_4F(5),
P(6) => R1IN_4_4_4F(6),
P(7) => R1IN_4_4_4F(7),
P(8) => R1IN_4_4_4F(8),
P(9) => R1IN_4_4_4F(9),
P(10) => R1IN_4_4_4F(10),
P(11) => R1IN_4_4_4F(11),
P(12) => R1IN_4_4_4F(12),
P(13) => R1IN_4_4_4F(13),
P(14) => R1IN_4_4_4F(14),
P(15) => R1IN_4_4_4F(15),
P(16) => R1IN_4_4_4F(16),
P(17) => R1IN_4_4_4F(17),
P(18) => R1IN_4_4_4F(18),
P(19) => R1IN_4_4_4F(19),
P(20) => UC_250,
P(21) => UC_251,
P(22) => UC_252,
P(23) => UC_253,
P(24) => UC_254,
P(25) => UC_255,
P(26) => UC_256,
P(27) => UC_257,
P(28) => UC_258,
P(29) => UC_259,
P(30) => UC_260,
P(31) => UC_261,
P(32) => UC_262,
P(33) => UC_263,
P(34) => UC_264,
P(35) => UC_265,
P(36) => UC_266,
P(37) => UC_267,
P(38) => UC_268,
P(39) => UC_269,
P(40) => UC_270,
P(41) => UC_271,
P(42) => UC_272,
P(43) => UC_273,
P(44) => UC_274,
P(45) => UC_275,
P(46) => UC_276,
P(47) => UC_277,
PCOUT(0) => R1IN_4_4_4_PCOUT(0),
PCOUT(1) => R1IN_4_4_4_PCOUT(1),
PCOUT(2) => R1IN_4_4_4_PCOUT(2),
PCOUT(3) => R1IN_4_4_4_PCOUT(3),
PCOUT(4) => R1IN_4_4_4_PCOUT(4),
PCOUT(5) => R1IN_4_4_4_PCOUT(5),
PCOUT(6) => R1IN_4_4_4_PCOUT(6),
PCOUT(7) => R1IN_4_4_4_PCOUT(7),
PCOUT(8) => R1IN_4_4_4_PCOUT(8),
PCOUT(9) => R1IN_4_4_4_PCOUT(9),
PCOUT(10) => R1IN_4_4_4_PCOUT(10),
PCOUT(11) => R1IN_4_4_4_PCOUT(11),
PCOUT(12) => R1IN_4_4_4_PCOUT(12),
PCOUT(13) => R1IN_4_4_4_PCOUT(13),
PCOUT(14) => R1IN_4_4_4_PCOUT(14),
PCOUT(15) => R1IN_4_4_4_PCOUT(15),
PCOUT(16) => R1IN_4_4_4_PCOUT(16),
PCOUT(17) => R1IN_4_4_4_PCOUT(17),
PCOUT(18) => R1IN_4_4_4_PCOUT(18),
PCOUT(19) => R1IN_4_4_4_PCOUT(19),
PCOUT(20) => R1IN_4_4_4_PCOUT(20),
PCOUT(21) => R1IN_4_4_4_PCOUT(21),
PCOUT(22) => R1IN_4_4_4_PCOUT(22),
PCOUT(23) => R1IN_4_4_4_PCOUT(23),
PCOUT(24) => R1IN_4_4_4_PCOUT(24),
PCOUT(25) => R1IN_4_4_4_PCOUT(25),
PCOUT(26) => R1IN_4_4_4_PCOUT(26),
PCOUT(27) => R1IN_4_4_4_PCOUT(27),
PCOUT(28) => R1IN_4_4_4_PCOUT(28),
PCOUT(29) => R1IN_4_4_4_PCOUT(29),
PCOUT(30) => R1IN_4_4_4_PCOUT(30),
PCOUT(31) => R1IN_4_4_4_PCOUT(31),
PCOUT(32) => R1IN_4_4_4_PCOUT(32),
PCOUT(33) => R1IN_4_4_4_PCOUT(33),
PCOUT(34) => R1IN_4_4_4_PCOUT(34),
PCOUT(35) => R1IN_4_4_4_PCOUT(35),
PCOUT(36) => R1IN_4_4_4_PCOUT(36),
PCOUT(37) => R1IN_4_4_4_PCOUT(37),
PCOUT(38) => R1IN_4_4_4_PCOUT(38),
PCOUT(39) => R1IN_4_4_4_PCOUT(39),
PCOUT(40) => R1IN_4_4_4_PCOUT(40),
PCOUT(41) => R1IN_4_4_4_PCOUT(41),
PCOUT(42) => R1IN_4_4_4_PCOUT(42),
PCOUT(43) => R1IN_4_4_4_PCOUT(43),
PCOUT(44) => R1IN_4_4_4_PCOUT(44),
PCOUT(45) => R1IN_4_4_4_PCOUT(45),
PCOUT(46) => R1IN_4_4_4_PCOUT(46),
PCOUT(47) => R1IN_4_4_4_PCOUT(47));
\R1IN_4_4_2[26:0]\: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 0,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => A(51),
A(1) => A(52),
A(2) => A(53),
A(3) => A(54),
A(4) => A(55),
A(5) => A(56),
A(6) => A(57),
A(7) => A(58),
A(8) => A(59),
A(9) => A(60),
A(10) => NN_1,
A(11) => NN_1,
A(12) => NN_1,
A(13) => NN_1,
A(14) => NN_1,
A(15) => NN_1,
A(16) => NN_1,
A(17) => NN_1,
B(0) => B(34),
B(1) => B(35),
B(2) => B(36),
B(3) => B(37),
B(4) => B(38),
B(5) => B(39),
B(6) => B(40),
B(7) => B(41),
B(8) => B(42),
B(9) => B(43),
B(10) => B(44),
B(11) => B(45),
B(12) => B(46),
B(13) => B(47),
B(14) => B(48),
B(15) => B(49),
B(16) => B(50),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => NN_1,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => NN_1,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_4_4_2_BCOUT(0),
BCOUT(1) => R1IN_4_4_2_BCOUT(1),
BCOUT(2) => R1IN_4_4_2_BCOUT(2),
BCOUT(3) => R1IN_4_4_2_BCOUT(3),
BCOUT(4) => R1IN_4_4_2_BCOUT(4),
BCOUT(5) => R1IN_4_4_2_BCOUT(5),
BCOUT(6) => R1IN_4_4_2_BCOUT(6),
BCOUT(7) => R1IN_4_4_2_BCOUT(7),
BCOUT(8) => R1IN_4_4_2_BCOUT(8),
BCOUT(9) => R1IN_4_4_2_BCOUT(9),
BCOUT(10) => R1IN_4_4_2_BCOUT(10),
BCOUT(11) => R1IN_4_4_2_BCOUT(11),
BCOUT(12) => R1IN_4_4_2_BCOUT(12),
BCOUT(13) => R1IN_4_4_2_BCOUT(13),
BCOUT(14) => R1IN_4_4_2_BCOUT(14),
BCOUT(15) => R1IN_4_4_2_BCOUT(15),
BCOUT(16) => R1IN_4_4_2_BCOUT(16),
BCOUT(17) => R1IN_4_4_2_BCOUT(17),
P(0) => R1IN_4_4_2(0),
P(1) => R1IN_4_4_2(1),
P(2) => R1IN_4_4_2(2),
P(3) => R1IN_4_4_2(3),
P(4) => R1IN_4_4_2(4),
P(5) => R1IN_4_4_2(5),
P(6) => R1IN_4_4_2(6),
P(7) => R1IN_4_4_2(7),
P(8) => R1IN_4_4_2(8),
P(9) => R1IN_4_4_2(9),
P(10) => R1IN_4_4_2(10),
P(11) => R1IN_4_4_2(11),
P(12) => R1IN_4_4_2(12),
P(13) => R1IN_4_4_2(13),
P(14) => R1IN_4_4_2(14),
P(15) => R1IN_4_4_2(15),
P(16) => R1IN_4_4_2(16),
P(17) => R1IN_4_4_2(17),
P(18) => R1IN_4_4_2(18),
P(19) => R1IN_4_4_2(19),
P(20) => R1IN_4_4_2(20),
P(21) => R1IN_4_4_2(21),
P(22) => R1IN_4_4_2(22),
P(23) => R1IN_4_4_2(23),
P(24) => R1IN_4_4_2(24),
P(25) => R1IN_4_4_2(25),
P(26) => R1IN_4_4_2(26),
P(27) => UC_229,
P(28) => UC_230,
P(29) => UC_231,
P(30) => UC_232,
P(31) => UC_233,
P(32) => UC_234,
P(33) => UC_235,
P(34) => UC_236,
P(35) => UC_237,
P(36) => UC_238,
P(37) => UC_239,
P(38) => UC_240,
P(39) => UC_241,
P(40) => UC_242,
P(41) => UC_243,
P(42) => UC_244,
P(43) => UC_245,
P(44) => UC_246,
P(45) => UC_247,
P(46) => UC_248,
P(47) => UC_249,
PCOUT(0) => R1IN_4_4_2_0(0),
PCOUT(1) => R1IN_4_4_2_0(1),
PCOUT(2) => R1IN_4_4_2_0(2),
PCOUT(3) => R1IN_4_4_2_0(3),
PCOUT(4) => R1IN_4_4_2_0(4),
PCOUT(5) => R1IN_4_4_2_0(5),
PCOUT(6) => R1IN_4_4_2_0(6),
PCOUT(7) => R1IN_4_4_2_0(7),
PCOUT(8) => R1IN_4_4_2_0(8),
PCOUT(9) => R1IN_4_4_2_0(9),
PCOUT(10) => R1IN_4_4_2_0(10),
PCOUT(11) => R1IN_4_4_2_0(11),
PCOUT(12) => R1IN_4_4_2_0(12),
PCOUT(13) => R1IN_4_4_2_0(13),
PCOUT(14) => R1IN_4_4_2_0(14),
PCOUT(15) => R1IN_4_4_2_0(15),
PCOUT(16) => R1IN_4_4_2_0(16),
PCOUT(17) => R1IN_4_4_2_0(17),
PCOUT(18) => R1IN_4_4_2_0(18),
PCOUT(19) => R1IN_4_4_2_0(19),
PCOUT(20) => R1IN_4_4_2_0(20),
PCOUT(21) => R1IN_4_4_2_0(21),
PCOUT(22) => R1IN_4_4_2_0(22),
PCOUT(23) => R1IN_4_4_2_0(23),
PCOUT(24) => R1IN_4_4_2_0(24),
PCOUT(25) => R1IN_4_4_2_0(25),
PCOUT(26) => R1IN_4_4_2_0(26),
PCOUT(27) => UC_229_0,
PCOUT(28) => UC_230_0,
PCOUT(29) => UC_231_0,
PCOUT(30) => UC_232_0,
PCOUT(31) => UC_233_0,
PCOUT(32) => UC_234_0,
PCOUT(33) => UC_235_0,
PCOUT(34) => UC_236_0,
PCOUT(35) => UC_237_0,
PCOUT(36) => UC_238_0,
PCOUT(37) => UC_239_0,
PCOUT(38) => UC_240_0,
PCOUT(39) => UC_241_0,
PCOUT(40) => UC_242_0,
PCOUT(41) => UC_243_0,
PCOUT(42) => UC_244_0,
PCOUT(43) => UC_245_0,
PCOUT(44) => UC_246_0,
PCOUT(45) => UC_247_0,
PCOUT(46) => UC_248_0,
PCOUT(47) => UC_249_0);
\R1IN_4_4_1[33:0]\: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 1,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => A(34),
A(1) => A(35),
A(2) => A(36),
A(3) => A(37),
A(4) => A(38),
A(5) => A(39),
A(6) => A(40),
A(7) => A(41),
A(8) => A(42),
A(9) => A(43),
A(10) => A(44),
A(11) => A(45),
A(12) => A(46),
A(13) => A(47),
A(14) => A(48),
A(15) => A(49),
A(16) => A(50),
A(17) => NN_1,
B(0) => B(34),
B(1) => B(35),
B(2) => B(36),
B(3) => B(37),
B(4) => B(38),
B(5) => B(39),
B(6) => B(40),
B(7) => B(41),
B(8) => B(42),
B(9) => B(43),
B(10) => B(44),
B(11) => B(45),
B(12) => B(46),
B(13) => B(47),
B(14) => B(48),
B(15) => B(49),
B(16) => B(50),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => EN,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_4_4_1_BCOUT(0),
BCOUT(1) => R1IN_4_4_1_BCOUT(1),
BCOUT(2) => R1IN_4_4_1_BCOUT(2),
BCOUT(3) => R1IN_4_4_1_BCOUT(3),
BCOUT(4) => R1IN_4_4_1_BCOUT(4),
BCOUT(5) => R1IN_4_4_1_BCOUT(5),
BCOUT(6) => R1IN_4_4_1_BCOUT(6),
BCOUT(7) => R1IN_4_4_1_BCOUT(7),
BCOUT(8) => R1IN_4_4_1_BCOUT(8),
BCOUT(9) => R1IN_4_4_1_BCOUT(9),
BCOUT(10) => R1IN_4_4_1_BCOUT(10),
BCOUT(11) => R1IN_4_4_1_BCOUT(11),
BCOUT(12) => R1IN_4_4_1_BCOUT(12),
BCOUT(13) => R1IN_4_4_1_BCOUT(13),
BCOUT(14) => R1IN_4_4_1_BCOUT(14),
BCOUT(15) => R1IN_4_4_1_BCOUT(15),
BCOUT(16) => R1IN_4_4_1_BCOUT(16),
BCOUT(17) => R1IN_4_4_1_BCOUT(17),
P(0) => R1IN_4_4F(0),
P(1) => R1IN_4_4F(1),
P(2) => R1IN_4_4F(2),
P(3) => R1IN_4_4F(3),
P(4) => R1IN_4_4F(4),
P(5) => R1IN_4_4F(5),
P(6) => R1IN_4_4F(6),
P(7) => R1IN_4_4F(7),
P(8) => R1IN_4_4F(8),
P(9) => R1IN_4_4F(9),
P(10) => R1IN_4_4F(10),
P(11) => R1IN_4_4F(11),
P(12) => R1IN_4_4F(12),
P(13) => R1IN_4_4F(13),
P(14) => R1IN_4_4F(14),
P(15) => R1IN_4_4F(15),
P(16) => R1IN_4_4F(16),
P(17) => R1IN_4_4_ADD_2,
P(18) => R1IN_4_4_1F(18),
P(19) => R1IN_4_4_1F(19),
P(20) => R1IN_4_4_1F(20),
P(21) => R1IN_4_4_1F(21),
P(22) => R1IN_4_4_1F(22),
P(23) => R1IN_4_4_1F(23),
P(24) => R1IN_4_4_1F(24),
P(25) => R1IN_4_4_1F(25),
P(26) => R1IN_4_4_1F(26),
P(27) => R1IN_4_4_1F(27),
P(28) => R1IN_4_4_1F(28),
P(29) => R1IN_4_4_1F(29),
P(30) => R1IN_4_4_1F(30),
P(31) => R1IN_4_4_1F(31),
P(32) => R1IN_4_4_1F(32),
P(33) => R1IN_4_4_1F(33),
P(34) => UC_215,
P(35) => UC_216,
P(36) => UC_217,
P(37) => UC_218,
P(38) => UC_219,
P(39) => UC_220,
P(40) => UC_221,
P(41) => UC_222,
P(42) => UC_223,
P(43) => UC_224,
P(44) => UC_225,
P(45) => UC_226,
P(46) => UC_227,
P(47) => UC_228,
PCOUT(0) => R1IN_4_4_1_PCOUT(0),
PCOUT(1) => R1IN_4_4_1_PCOUT(1),
PCOUT(2) => R1IN_4_4_1_PCOUT(2),
PCOUT(3) => R1IN_4_4_1_PCOUT(3),
PCOUT(4) => R1IN_4_4_1_PCOUT(4),
PCOUT(5) => R1IN_4_4_1_PCOUT(5),
PCOUT(6) => R1IN_4_4_1_PCOUT(6),
PCOUT(7) => R1IN_4_4_1_PCOUT(7),
PCOUT(8) => R1IN_4_4_1_PCOUT(8),
PCOUT(9) => R1IN_4_4_1_PCOUT(9),
PCOUT(10) => R1IN_4_4_1_PCOUT(10),
PCOUT(11) => R1IN_4_4_1_PCOUT(11),
PCOUT(12) => R1IN_4_4_1_PCOUT(12),
PCOUT(13) => R1IN_4_4_1_PCOUT(13),
PCOUT(14) => R1IN_4_4_1_PCOUT(14),
PCOUT(15) => R1IN_4_4_1_PCOUT(15),
PCOUT(16) => R1IN_4_4_1_PCOUT(16),
PCOUT(17) => R1IN_4_4_1_PCOUT(17),
PCOUT(18) => R1IN_4_4_1_PCOUT(18),
PCOUT(19) => R1IN_4_4_1_PCOUT(19),
PCOUT(20) => R1IN_4_4_1_PCOUT(20),
PCOUT(21) => R1IN_4_4_1_PCOUT(21),
PCOUT(22) => R1IN_4_4_1_PCOUT(22),
PCOUT(23) => R1IN_4_4_1_PCOUT(23),
PCOUT(24) => R1IN_4_4_1_PCOUT(24),
PCOUT(25) => R1IN_4_4_1_PCOUT(25),
PCOUT(26) => R1IN_4_4_1_PCOUT(26),
PCOUT(27) => R1IN_4_4_1_PCOUT(27),
PCOUT(28) => R1IN_4_4_1_PCOUT(28),
PCOUT(29) => R1IN_4_4_1_PCOUT(29),
PCOUT(30) => R1IN_4_4_1_PCOUT(30),
PCOUT(31) => R1IN_4_4_1_PCOUT(31),
PCOUT(32) => R1IN_4_4_1_PCOUT(32),
PCOUT(33) => R1IN_4_4_1_PCOUT(33),
PCOUT(34) => R1IN_4_4_1_PCOUT(34),
PCOUT(35) => R1IN_4_4_1_PCOUT(35),
PCOUT(36) => R1IN_4_4_1_PCOUT(36),
PCOUT(37) => R1IN_4_4_1_PCOUT(37),
PCOUT(38) => R1IN_4_4_1_PCOUT(38),
PCOUT(39) => R1IN_4_4_1_PCOUT(39),
PCOUT(40) => R1IN_4_4_1_PCOUT(40),
PCOUT(41) => R1IN_4_4_1_PCOUT(41),
PCOUT(42) => R1IN_4_4_1_PCOUT(42),
PCOUT(43) => R1IN_4_4_1_PCOUT(43),
PCOUT(44) => R1IN_4_4_1_PCOUT(44),
PCOUT(45) => R1IN_4_4_1_PCOUT(45),
PCOUT(46) => R1IN_4_4_1_PCOUT(46),
PCOUT(47) => R1IN_4_4_1_PCOUT(47));
\R1IN_4_1[33:0]\: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 1,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => A(17),
A(1) => A(18),
A(2) => A(19),
A(3) => A(20),
A(4) => A(21),
A(5) => A(22),
A(6) => A(23),
A(7) => A(24),
A(8) => A(25),
A(9) => A(26),
A(10) => A(27),
A(11) => A(28),
A(12) => A(29),
A(13) => A(30),
A(14) => A(31),
A(15) => A(32),
A(16) => A(33),
A(17) => NN_1,
B(0) => B(17),
B(1) => B(18),
B(2) => B(19),
B(3) => B(20),
B(4) => B(21),
B(5) => B(22),
B(6) => B(23),
B(7) => B(24),
B(8) => B(25),
B(9) => B(26),
B(10) => B(27),
B(11) => B(28),
B(12) => B(29),
B(13) => B(30),
B(14) => B(31),
B(15) => B(32),
B(16) => B(33),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => EN,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_4_1_BCOUT(0),
BCOUT(1) => R1IN_4_1_BCOUT(1),
BCOUT(2) => R1IN_4_1_BCOUT(2),
BCOUT(3) => R1IN_4_1_BCOUT(3),
BCOUT(4) => R1IN_4_1_BCOUT(4),
BCOUT(5) => R1IN_4_1_BCOUT(5),
BCOUT(6) => R1IN_4_1_BCOUT(6),
BCOUT(7) => R1IN_4_1_BCOUT(7),
BCOUT(8) => R1IN_4_1_BCOUT(8),
BCOUT(9) => R1IN_4_1_BCOUT(9),
BCOUT(10) => R1IN_4_1_BCOUT(10),
BCOUT(11) => R1IN_4_1_BCOUT(11),
BCOUT(12) => R1IN_4_1_BCOUT(12),
BCOUT(13) => R1IN_4_1_BCOUT(13),
BCOUT(14) => R1IN_4_1_BCOUT(14),
BCOUT(15) => R1IN_4_1_BCOUT(15),
BCOUT(16) => R1IN_4_1_BCOUT(16),
BCOUT(17) => R1IN_4_1_BCOUT(17),
P(0) => R1IN_4F(0),
P(1) => R1IN_4F(1),
P(2) => R1IN_4F(2),
P(3) => R1IN_4F(3),
P(4) => R1IN_4F(4),
P(5) => R1IN_4F(5),
P(6) => R1IN_4F(6),
P(7) => R1IN_4F(7),
P(8) => R1IN_4F(8),
P(9) => R1IN_4F(9),
P(10) => R1IN_4F(10),
P(11) => R1IN_4F(11),
P(12) => R1IN_4F(12),
P(13) => R1IN_4F(13),
P(14) => R1IN_4F(14),
P(15) => R1IN_4F(15),
P(16) => R1IN_4F(16),
P(17) => R1IN_4_1F(17),
P(18) => R1IN_4_1F(18),
P(19) => R1IN_4_1F(19),
P(20) => R1IN_4_1F(20),
P(21) => R1IN_4_1F(21),
P(22) => R1IN_4_1F(22),
P(23) => R1IN_4_1F(23),
P(24) => R1IN_4_1F(24),
P(25) => R1IN_4_1F(25),
P(26) => R1IN_4_1F(26),
P(27) => R1IN_4_1F(27),
P(28) => R1IN_4_1F(28),
P(29) => R1IN_4_1F(29),
P(30) => R1IN_4_1F(30),
P(31) => R1IN_4_1F(31),
P(32) => R1IN_4_1F(32),
P(33) => R1IN_4_1F(33),
P(34) => UC_201,
P(35) => UC_202,
P(36) => UC_203,
P(37) => UC_204,
P(38) => UC_205,
P(39) => UC_206,
P(40) => UC_207,
P(41) => UC_208,
P(42) => UC_209,
P(43) => UC_210,
P(44) => UC_211,
P(45) => UC_212,
P(46) => UC_213,
P(47) => UC_214,
PCOUT(0) => R1IN_4_1_PCOUT(0),
PCOUT(1) => R1IN_4_1_PCOUT(1),
PCOUT(2) => R1IN_4_1_PCOUT(2),
PCOUT(3) => R1IN_4_1_PCOUT(3),
PCOUT(4) => R1IN_4_1_PCOUT(4),
PCOUT(5) => R1IN_4_1_PCOUT(5),
PCOUT(6) => R1IN_4_1_PCOUT(6),
PCOUT(7) => R1IN_4_1_PCOUT(7),
PCOUT(8) => R1IN_4_1_PCOUT(8),
PCOUT(9) => R1IN_4_1_PCOUT(9),
PCOUT(10) => R1IN_4_1_PCOUT(10),
PCOUT(11) => R1IN_4_1_PCOUT(11),
PCOUT(12) => R1IN_4_1_PCOUT(12),
PCOUT(13) => R1IN_4_1_PCOUT(13),
PCOUT(14) => R1IN_4_1_PCOUT(14),
PCOUT(15) => R1IN_4_1_PCOUT(15),
PCOUT(16) => R1IN_4_1_PCOUT(16),
PCOUT(17) => R1IN_4_1_PCOUT(17),
PCOUT(18) => R1IN_4_1_PCOUT(18),
PCOUT(19) => R1IN_4_1_PCOUT(19),
PCOUT(20) => R1IN_4_1_PCOUT(20),
PCOUT(21) => R1IN_4_1_PCOUT(21),
PCOUT(22) => R1IN_4_1_PCOUT(22),
PCOUT(23) => R1IN_4_1_PCOUT(23),
PCOUT(24) => R1IN_4_1_PCOUT(24),
PCOUT(25) => R1IN_4_1_PCOUT(25),
PCOUT(26) => R1IN_4_1_PCOUT(26),
PCOUT(27) => R1IN_4_1_PCOUT(27),
PCOUT(28) => R1IN_4_1_PCOUT(28),
PCOUT(29) => R1IN_4_1_PCOUT(29),
PCOUT(30) => R1IN_4_1_PCOUT(30),
PCOUT(31) => R1IN_4_1_PCOUT(31),
PCOUT(32) => R1IN_4_1_PCOUT(32),
PCOUT(33) => R1IN_4_1_PCOUT(33),
PCOUT(34) => R1IN_4_1_PCOUT(34),
PCOUT(35) => R1IN_4_1_PCOUT(35),
PCOUT(36) => R1IN_4_1_PCOUT(36),
PCOUT(37) => R1IN_4_1_PCOUT(37),
PCOUT(38) => R1IN_4_1_PCOUT(38),
PCOUT(39) => R1IN_4_1_PCOUT(39),
PCOUT(40) => R1IN_4_1_PCOUT(40),
PCOUT(41) => R1IN_4_1_PCOUT(41),
PCOUT(42) => R1IN_4_1_PCOUT(42),
PCOUT(43) => R1IN_4_1_PCOUT(43),
PCOUT(44) => R1IN_4_1_PCOUT(44),
PCOUT(45) => R1IN_4_1_PCOUT(45),
PCOUT(46) => R1IN_4_1_PCOUT(46),
PCOUT(47) => R1IN_4_1_PCOUT(47));
\R1IN_3_1[33:0]\: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 0,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => B(17),
A(1) => B(18),
A(2) => B(19),
A(3) => B(20),
A(4) => B(21),
A(5) => B(22),
A(6) => B(23),
A(7) => B(24),
A(8) => B(25),
A(9) => B(26),
A(10) => B(27),
A(11) => B(28),
A(12) => B(29),
A(13) => B(30),
A(14) => B(31),
A(15) => B(32),
A(16) => B(33),
A(17) => NN_1,
B(0) => A(0),
B(1) => A(1),
B(2) => A(2),
B(3) => A(3),
B(4) => A(4),
B(5) => A(5),
B(6) => A(6),
B(7) => A(7),
B(8) => A(8),
B(9) => A(9),
B(10) => A(10),
B(11) => A(11),
B(12) => A(12),
B(13) => A(13),
B(14) => A(14),
B(15) => A(15),
B(16) => A(16),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => NN_1,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_3_1_BCOUT(0),
BCOUT(1) => R1IN_3_1_BCOUT(1),
BCOUT(2) => R1IN_3_1_BCOUT(2),
BCOUT(3) => R1IN_3_1_BCOUT(3),
BCOUT(4) => R1IN_3_1_BCOUT(4),
BCOUT(5) => R1IN_3_1_BCOUT(5),
BCOUT(6) => R1IN_3_1_BCOUT(6),
BCOUT(7) => R1IN_3_1_BCOUT(7),
BCOUT(8) => R1IN_3_1_BCOUT(8),
BCOUT(9) => R1IN_3_1_BCOUT(9),
BCOUT(10) => R1IN_3_1_BCOUT(10),
BCOUT(11) => R1IN_3_1_BCOUT(11),
BCOUT(12) => R1IN_3_1_BCOUT(12),
BCOUT(13) => R1IN_3_1_BCOUT(13),
BCOUT(14) => R1IN_3_1_BCOUT(14),
BCOUT(15) => R1IN_3_1_BCOUT(15),
BCOUT(16) => R1IN_3_1_BCOUT(16),
BCOUT(17) => R1IN_3_1_BCOUT(17),
P(0) => R1IN_3F_0(0),
P(1) => R1IN_3F_0(1),
P(2) => R1IN_3F_0(2),
P(3) => R1IN_3F_0(3),
P(4) => R1IN_3F_0(4),
P(5) => R1IN_3F_0(5),
P(6) => R1IN_3F_0(6),
P(7) => R1IN_3F_0(7),
P(8) => R1IN_3F_0(8),
P(9) => R1IN_3F_0(9),
P(10) => R1IN_3F_0(10),
P(11) => R1IN_3F_0(11),
P(12) => R1IN_3F_0(12),
P(13) => R1IN_3F_0(13),
P(14) => R1IN_3F_0(14),
P(15) => R1IN_3F_0(15),
P(16) => R1IN_3F_0(16),
P(17) => R1IN_3_1F_0(17),
P(18) => R1IN_3_1F_0(18),
P(19) => R1IN_3_1F_0(19),
P(20) => R1IN_3_1F_0(20),
P(21) => R1IN_3_1F_0(21),
P(22) => R1IN_3_1F_0(22),
P(23) => R1IN_3_1F_0(23),
P(24) => R1IN_3_1F_0(24),
P(25) => R1IN_3_1F_0(25),
P(26) => R1IN_3_1F_0(26),
P(27) => R1IN_3_1F_0(27),
P(28) => R1IN_3_1F_0(28),
P(29) => R1IN_3_1F_0(29),
P(30) => R1IN_3_1F_0(30),
P(31) => R1IN_3_1F_0(31),
P(32) => R1IN_3_1F_0(32),
P(33) => R1IN_3_1F_0(33),
P(34) => UC_187_0,
P(35) => UC_188_0,
P(36) => UC_189_0,
P(37) => UC_190_0,
P(38) => UC_191_0,
P(39) => UC_192_0,
P(40) => UC_193_0,
P(41) => UC_194_0,
P(42) => UC_195_0,
P(43) => UC_196_0,
P(44) => UC_197_0,
P(45) => UC_198_0,
P(46) => UC_199_0,
P(47) => UC_200_0,
PCOUT(0) => R1IN_3_1_PCOUT(0),
PCOUT(1) => R1IN_3_1_PCOUT(1),
PCOUT(2) => R1IN_3_1_PCOUT(2),
PCOUT(3) => R1IN_3_1_PCOUT(3),
PCOUT(4) => R1IN_3_1_PCOUT(4),
PCOUT(5) => R1IN_3_1_PCOUT(5),
PCOUT(6) => R1IN_3_1_PCOUT(6),
PCOUT(7) => R1IN_3_1_PCOUT(7),
PCOUT(8) => R1IN_3_1_PCOUT(8),
PCOUT(9) => R1IN_3_1_PCOUT(9),
PCOUT(10) => R1IN_3_1_PCOUT(10),
PCOUT(11) => R1IN_3_1_PCOUT(11),
PCOUT(12) => R1IN_3_1_PCOUT(12),
PCOUT(13) => R1IN_3_1_PCOUT(13),
PCOUT(14) => R1IN_3_1_PCOUT(14),
PCOUT(15) => R1IN_3_1_PCOUT(15),
PCOUT(16) => R1IN_3_1_PCOUT(16),
PCOUT(17) => R1IN_3_1_PCOUT(17),
PCOUT(18) => R1IN_3_1_PCOUT(18),
PCOUT(19) => R1IN_3_1_PCOUT(19),
PCOUT(20) => R1IN_3_1_PCOUT(20),
PCOUT(21) => R1IN_3_1_PCOUT(21),
PCOUT(22) => R1IN_3_1_PCOUT(22),
PCOUT(23) => R1IN_3_1_PCOUT(23),
PCOUT(24) => R1IN_3_1_PCOUT(24),
PCOUT(25) => R1IN_3_1_PCOUT(25),
PCOUT(26) => R1IN_3_1_PCOUT(26),
PCOUT(27) => R1IN_3_1_PCOUT(27),
PCOUT(28) => R1IN_3_1_PCOUT(28),
PCOUT(29) => R1IN_3_1_PCOUT(29),
PCOUT(30) => R1IN_3_1_PCOUT(30),
PCOUT(31) => R1IN_3_1_PCOUT(31),
PCOUT(32) => R1IN_3_1_PCOUT(32),
PCOUT(33) => R1IN_3_1_PCOUT(33),
PCOUT(34) => R1IN_3_1_PCOUT(34),
PCOUT(35) => R1IN_3_1_PCOUT(35),
PCOUT(36) => R1IN_3_1_PCOUT(36),
PCOUT(37) => R1IN_3_1_PCOUT(37),
PCOUT(38) => R1IN_3_1_PCOUT(38),
PCOUT(39) => R1IN_3_1_PCOUT(39),
PCOUT(40) => R1IN_3_1_PCOUT(40),
PCOUT(41) => R1IN_3_1_PCOUT(41),
PCOUT(42) => R1IN_3_1_PCOUT(42),
PCOUT(43) => R1IN_3_1_PCOUT(43),
PCOUT(44) => R1IN_3_1_PCOUT(44),
PCOUT(45) => R1IN_3_1_PCOUT(45),
PCOUT(46) => R1IN_3_1_PCOUT(46),
PCOUT(47) => R1IN_3_1_PCOUT(47));
\R1IN_2_1[33:0]\: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 0,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => A(17),
A(1) => A(18),
A(2) => A(19),
A(3) => A(20),
A(4) => A(21),
A(5) => A(22),
A(6) => A(23),
A(7) => A(24),
A(8) => A(25),
A(9) => A(26),
A(10) => A(27),
A(11) => A(28),
A(12) => A(29),
A(13) => A(30),
A(14) => A(31),
A(15) => A(32),
A(16) => A(33),
A(17) => NN_1,
B(0) => B(0),
B(1) => B(1),
B(2) => B(2),
B(3) => B(3),
B(4) => B(4),
B(5) => B(5),
B(6) => B(6),
B(7) => B(7),
B(8) => B(8),
B(9) => B(9),
B(10) => B(10),
B(11) => B(11),
B(12) => B(12),
B(13) => B(13),
B(14) => B(14),
B(15) => B(15),
B(16) => B(16),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => NN_1,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_2_1_BCOUT(0),
BCOUT(1) => R1IN_2_1_BCOUT(1),
BCOUT(2) => R1IN_2_1_BCOUT(2),
BCOUT(3) => R1IN_2_1_BCOUT(3),
BCOUT(4) => R1IN_2_1_BCOUT(4),
BCOUT(5) => R1IN_2_1_BCOUT(5),
BCOUT(6) => R1IN_2_1_BCOUT(6),
BCOUT(7) => R1IN_2_1_BCOUT(7),
BCOUT(8) => R1IN_2_1_BCOUT(8),
BCOUT(9) => R1IN_2_1_BCOUT(9),
BCOUT(10) => R1IN_2_1_BCOUT(10),
BCOUT(11) => R1IN_2_1_BCOUT(11),
BCOUT(12) => R1IN_2_1_BCOUT(12),
BCOUT(13) => R1IN_2_1_BCOUT(13),
BCOUT(14) => R1IN_2_1_BCOUT(14),
BCOUT(15) => R1IN_2_1_BCOUT(15),
BCOUT(16) => R1IN_2_1_BCOUT(16),
BCOUT(17) => R1IN_2_1_BCOUT(17),
P(0) => R1IN_2F_0(0),
P(1) => R1IN_2F_0(1),
P(2) => R1IN_2F_0(2),
P(3) => R1IN_2F_0(3),
P(4) => R1IN_2F_0(4),
P(5) => R1IN_2F_0(5),
P(6) => R1IN_2F_0(6),
P(7) => R1IN_2F_0(7),
P(8) => R1IN_2F_0(8),
P(9) => R1IN_2F_0(9),
P(10) => R1IN_2F_0(10),
P(11) => R1IN_2F_0(11),
P(12) => R1IN_2F_0(12),
P(13) => R1IN_2F_0(13),
P(14) => R1IN_2F_0(14),
P(15) => R1IN_2F_0(15),
P(16) => R1IN_2F_0(16),
P(17) => R1IN_2_1F_0(17),
P(18) => R1IN_2_1F_0(18),
P(19) => R1IN_2_1F_0(19),
P(20) => R1IN_2_1F_0(20),
P(21) => R1IN_2_1F_0(21),
P(22) => R1IN_2_1F_0(22),
P(23) => R1IN_2_1F_0(23),
P(24) => R1IN_2_1F_0(24),
P(25) => R1IN_2_1F_0(25),
P(26) => R1IN_2_1F_0(26),
P(27) => R1IN_2_1F_0(27),
P(28) => R1IN_2_1F_0(28),
P(29) => R1IN_2_1F_0(29),
P(30) => R1IN_2_1F_0(30),
P(31) => R1IN_2_1F_0(31),
P(32) => R1IN_2_1F_0(32),
P(33) => R1IN_2_1F_0(33),
P(34) => UC_173_0,
P(35) => UC_174_0,
P(36) => UC_175_0,
P(37) => UC_176_0,
P(38) => UC_177_0,
P(39) => UC_178_0,
P(40) => UC_179_0,
P(41) => UC_180_0,
P(42) => UC_181_0,
P(43) => UC_182_0,
P(44) => UC_183_0,
P(45) => UC_184_0,
P(46) => UC_185_0,
P(47) => UC_186_0,
PCOUT(0) => R1IN_2_1_PCOUT(0),
PCOUT(1) => R1IN_2_1_PCOUT(1),
PCOUT(2) => R1IN_2_1_PCOUT(2),
PCOUT(3) => R1IN_2_1_PCOUT(3),
PCOUT(4) => R1IN_2_1_PCOUT(4),
PCOUT(5) => R1IN_2_1_PCOUT(5),
PCOUT(6) => R1IN_2_1_PCOUT(6),
PCOUT(7) => R1IN_2_1_PCOUT(7),
PCOUT(8) => R1IN_2_1_PCOUT(8),
PCOUT(9) => R1IN_2_1_PCOUT(9),
PCOUT(10) => R1IN_2_1_PCOUT(10),
PCOUT(11) => R1IN_2_1_PCOUT(11),
PCOUT(12) => R1IN_2_1_PCOUT(12),
PCOUT(13) => R1IN_2_1_PCOUT(13),
PCOUT(14) => R1IN_2_1_PCOUT(14),
PCOUT(15) => R1IN_2_1_PCOUT(15),
PCOUT(16) => R1IN_2_1_PCOUT(16),
PCOUT(17) => R1IN_2_1_PCOUT(17),
PCOUT(18) => R1IN_2_1_PCOUT(18),
PCOUT(19) => R1IN_2_1_PCOUT(19),
PCOUT(20) => R1IN_2_1_PCOUT(20),
PCOUT(21) => R1IN_2_1_PCOUT(21),
PCOUT(22) => R1IN_2_1_PCOUT(22),
PCOUT(23) => R1IN_2_1_PCOUT(23),
PCOUT(24) => R1IN_2_1_PCOUT(24),
PCOUT(25) => R1IN_2_1_PCOUT(25),
PCOUT(26) => R1IN_2_1_PCOUT(26),
PCOUT(27) => R1IN_2_1_PCOUT(27),
PCOUT(28) => R1IN_2_1_PCOUT(28),
PCOUT(29) => R1IN_2_1_PCOUT(29),
PCOUT(30) => R1IN_2_1_PCOUT(30),
PCOUT(31) => R1IN_2_1_PCOUT(31),
PCOUT(32) => R1IN_2_1_PCOUT(32),
PCOUT(33) => R1IN_2_1_PCOUT(33),
PCOUT(34) => R1IN_2_1_PCOUT(34),
PCOUT(35) => R1IN_2_1_PCOUT(35),
PCOUT(36) => R1IN_2_1_PCOUT(36),
PCOUT(37) => R1IN_2_1_PCOUT(37),
PCOUT(38) => R1IN_2_1_PCOUT(38),
PCOUT(39) => R1IN_2_1_PCOUT(39),
PCOUT(40) => R1IN_2_1_PCOUT(40),
PCOUT(41) => R1IN_2_1_PCOUT(41),
PCOUT(42) => R1IN_2_1_PCOUT(42),
PCOUT(43) => R1IN_2_1_PCOUT(43),
PCOUT(44) => R1IN_2_1_PCOUT(44),
PCOUT(45) => R1IN_2_1_PCOUT(45),
PCOUT(46) => R1IN_2_1_PCOUT(46),
PCOUT(47) => R1IN_2_1_PCOUT(47));
\R1IN_1[33:0]\: DSP48
generic map(
AREG => 1,
BREG => 1,
CREG => 0,
PREG => 1,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "CASCADE",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => A(0),
A(1) => A(1),
A(2) => A(2),
A(3) => A(3),
A(4) => A(4),
A(5) => A(5),
A(6) => A(6),
A(7) => A(7),
A(8) => A(8),
A(9) => A(9),
A(10) => A(10),
A(11) => A(11),
A(12) => A(12),
A(13) => A(13),
A(14) => A(14),
A(15) => A(15),
A(16) => A(16),
A(17) => NN_1,
B(0) => NN_1,
B(1) => NN_1,
B(2) => NN_1,
B(3) => NN_1,
B(4) => NN_1,
B(5) => NN_1,
B(6) => NN_1,
B(7) => NN_1,
B(8) => NN_1,
B(9) => NN_1,
B(10) => NN_1,
B(11) => NN_1,
B(12) => NN_1,
B(13) => NN_1,
B(14) => NN_1,
B(15) => NN_1,
B(16) => NN_1,
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => B_0(0),
BCIN(1) => B_0(1),
BCIN(2) => B_0(2),
BCIN(3) => B_0(3),
BCIN(4) => B_0(4),
BCIN(5) => B_0(5),
BCIN(6) => B_0(6),
BCIN(7) => B_0(7),
BCIN(8) => B_0(8),
BCIN(9) => B_0(9),
BCIN(10) => B_0(10),
BCIN(11) => B_0(11),
BCIN(12) => B_0(12),
BCIN(13) => B_0(13),
BCIN(14) => B_0(14),
BCIN(15) => B_0(15),
BCIN(16) => B_0(16),
BCIN(17) => GND_0,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => EN,
CEB => EN,
CEC => NN_1,
CEP => EN,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_1_BCOUT(0),
BCOUT(1) => R1IN_1_BCOUT(1),
BCOUT(2) => R1IN_1_BCOUT(2),
BCOUT(3) => R1IN_1_BCOUT(3),
BCOUT(4) => R1IN_1_BCOUT(4),
BCOUT(5) => R1IN_1_BCOUT(5),
BCOUT(6) => R1IN_1_BCOUT(6),
BCOUT(7) => R1IN_1_BCOUT(7),
BCOUT(8) => R1IN_1_BCOUT(8),
BCOUT(9) => R1IN_1_BCOUT(9),
BCOUT(10) => R1IN_1_BCOUT(10),
BCOUT(11) => R1IN_1_BCOUT(11),
BCOUT(12) => R1IN_1_BCOUT(12),
BCOUT(13) => R1IN_1_BCOUT(13),
BCOUT(14) => R1IN_1_BCOUT(14),
BCOUT(15) => R1IN_1_BCOUT(15),
BCOUT(16) => R1IN_1_BCOUT(16),
BCOUT(17) => R1IN_1_BCOUT(17),
P(0) => PRODUCT(0),
P(1) => PRODUCT(1),
P(2) => PRODUCT(2),
P(3) => PRODUCT(3),
P(4) => PRODUCT(4),
P(5) => PRODUCT(5),
P(6) => PRODUCT(6),
P(7) => PRODUCT(7),
P(8) => PRODUCT(8),
P(9) => PRODUCT(9),
P(10) => PRODUCT(10),
P(11) => PRODUCT(11),
P(12) => PRODUCT(12),
P(13) => PRODUCT(13),
P(14) => PRODUCT(14),
P(15) => PRODUCT(15),
P(16) => PRODUCT(16),
P(17) => R1IN_ADD_2_0,
P(18) => R1IN_1FF(18),
P(19) => R1IN_1FF(19),
P(20) => R1IN_1FF(20),
P(21) => R1IN_1FF(21),
P(22) => R1IN_1FF(22),
P(23) => R1IN_1FF(23),
P(24) => R1IN_1FF(24),
P(25) => R1IN_1FF(25),
P(26) => R1IN_1FF(26),
P(27) => R1IN_1FF(27),
P(28) => R1IN_1FF(28),
P(29) => R1IN_1FF(29),
P(30) => R1IN_1FF(30),
P(31) => R1IN_1FF(31),
P(32) => R1IN_1FF(32),
P(33) => R1IN_1FF(33),
P(34) => UC_159,
P(35) => UC_160,
P(36) => UC_161,
P(37) => UC_162,
P(38) => UC_163,
P(39) => UC_164,
P(40) => UC_165,
P(41) => UC_166,
P(42) => UC_167,
P(43) => UC_168,
P(44) => UC_169,
P(45) => UC_170,
P(46) => UC_171,
P(47) => UC_172,
PCOUT(0) => R1IN_1_PCOUT(0),
PCOUT(1) => R1IN_1_PCOUT(1),
PCOUT(2) => R1IN_1_PCOUT(2),
PCOUT(3) => R1IN_1_PCOUT(3),
PCOUT(4) => R1IN_1_PCOUT(4),
PCOUT(5) => R1IN_1_PCOUT(5),
PCOUT(6) => R1IN_1_PCOUT(6),
PCOUT(7) => R1IN_1_PCOUT(7),
PCOUT(8) => R1IN_1_PCOUT(8),
PCOUT(9) => R1IN_1_PCOUT(9),
PCOUT(10) => R1IN_1_PCOUT(10),
PCOUT(11) => R1IN_1_PCOUT(11),
PCOUT(12) => R1IN_1_PCOUT(12),
PCOUT(13) => R1IN_1_PCOUT(13),
PCOUT(14) => R1IN_1_PCOUT(14),
PCOUT(15) => R1IN_1_PCOUT(15),
PCOUT(16) => R1IN_1_PCOUT(16),
PCOUT(17) => R1IN_1_PCOUT(17),
PCOUT(18) => R1IN_1_PCOUT(18),
PCOUT(19) => R1IN_1_PCOUT(19),
PCOUT(20) => R1IN_1_PCOUT(20),
PCOUT(21) => R1IN_1_PCOUT(21),
PCOUT(22) => R1IN_1_PCOUT(22),
PCOUT(23) => R1IN_1_PCOUT(23),
PCOUT(24) => R1IN_1_PCOUT(24),
PCOUT(25) => R1IN_1_PCOUT(25),
PCOUT(26) => R1IN_1_PCOUT(26),
PCOUT(27) => R1IN_1_PCOUT(27),
PCOUT(28) => R1IN_1_PCOUT(28),
PCOUT(29) => R1IN_1_PCOUT(29),
PCOUT(30) => R1IN_1_PCOUT(30),
PCOUT(31) => R1IN_1_PCOUT(31),
PCOUT(32) => R1IN_1_PCOUT(32),
PCOUT(33) => R1IN_1_PCOUT(33),
PCOUT(34) => R1IN_1_PCOUT(34),
PCOUT(35) => R1IN_1_PCOUT(35),
PCOUT(36) => R1IN_1_PCOUT(36),
PCOUT(37) => R1IN_1_PCOUT(37),
PCOUT(38) => R1IN_1_PCOUT(38),
PCOUT(39) => R1IN_1_PCOUT(39),
PCOUT(40) => R1IN_1_PCOUT(40),
PCOUT(41) => R1IN_1_PCOUT(41),
PCOUT(42) => R1IN_1_PCOUT(42),
PCOUT(43) => R1IN_1_PCOUT(43),
PCOUT(44) => R1IN_1_PCOUT(44),
PCOUT(45) => R1IN_1_PCOUT(45),
PCOUT(46) => R1IN_1_PCOUT(46),
PCOUT(47) => R1IN_1_PCOUT(47));
\R1IN_4_3_1[33:0]\: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 0,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => B(34),
A(1) => B(35),
A(2) => B(36),
A(3) => B(37),
A(4) => B(38),
A(5) => B(39),
A(6) => B(40),
A(7) => B(41),
A(8) => B(42),
A(9) => B(43),
A(10) => B(44),
A(11) => B(45),
A(12) => B(46),
A(13) => B(47),
A(14) => B(48),
A(15) => B(49),
A(16) => B(50),
A(17) => NN_1,
B(0) => A(17),
B(1) => A(18),
B(2) => A(19),
B(3) => A(20),
B(4) => A(21),
B(5) => A(22),
B(6) => A(23),
B(7) => A(24),
B(8) => A(25),
B(9) => A(26),
B(10) => A(27),
B(11) => A(28),
B(12) => A(29),
B(13) => A(30),
B(14) => A(31),
B(15) => A(32),
B(16) => A(33),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => NN_1,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => NN_1,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_4_3_1_BCOUT(0),
BCOUT(1) => R1IN_4_3_1_BCOUT(1),
BCOUT(2) => R1IN_4_3_1_BCOUT(2),
BCOUT(3) => R1IN_4_3_1_BCOUT(3),
BCOUT(4) => R1IN_4_3_1_BCOUT(4),
BCOUT(5) => R1IN_4_3_1_BCOUT(5),
BCOUT(6) => R1IN_4_3_1_BCOUT(6),
BCOUT(7) => R1IN_4_3_1_BCOUT(7),
BCOUT(8) => R1IN_4_3_1_BCOUT(8),
BCOUT(9) => R1IN_4_3_1_BCOUT(9),
BCOUT(10) => R1IN_4_3_1_BCOUT(10),
BCOUT(11) => R1IN_4_3_1_BCOUT(11),
BCOUT(12) => R1IN_4_3_1_BCOUT(12),
BCOUT(13) => R1IN_4_3_1_BCOUT(13),
BCOUT(14) => R1IN_4_3_1_BCOUT(14),
BCOUT(15) => R1IN_4_3_1_BCOUT(15),
BCOUT(16) => R1IN_4_3_1_BCOUT(16),
BCOUT(17) => R1IN_4_3_1_BCOUT(17),
P(0) => R1IN_4_3(0),
P(1) => R1IN_4_3(1),
P(2) => R1IN_4_3(2),
P(3) => R1IN_4_3(3),
P(4) => R1IN_4_3(4),
P(5) => R1IN_4_3(5),
P(6) => R1IN_4_3(6),
P(7) => R1IN_4_3(7),
P(8) => R1IN_4_3(8),
P(9) => R1IN_4_3(9),
P(10) => R1IN_4_3(10),
P(11) => R1IN_4_3(11),
P(12) => R1IN_4_3(12),
P(13) => R1IN_4_3(13),
P(14) => R1IN_4_3(14),
P(15) => R1IN_4_3(15),
P(16) => R1IN_4_3(16),
P(17) => R1IN_4_3_1(17),
P(18) => R1IN_4_3_1(18),
P(19) => R1IN_4_3_1(19),
P(20) => R1IN_4_3_1(20),
P(21) => R1IN_4_3_1(21),
P(22) => R1IN_4_3_1(22),
P(23) => R1IN_4_3_1(23),
P(24) => R1IN_4_3_1(24),
P(25) => R1IN_4_3_1(25),
P(26) => R1IN_4_3_1(26),
P(27) => R1IN_4_3_1(27),
P(28) => R1IN_4_3_1(28),
P(29) => R1IN_4_3_1(29),
P(30) => R1IN_4_3_1(30),
P(31) => R1IN_4_3_1(31),
P(32) => R1IN_4_3_1(32),
P(33) => R1IN_4_3_1(33),
P(34) => UC_145,
P(35) => UC_146,
P(36) => UC_147,
P(37) => UC_148,
P(38) => UC_149,
P(39) => UC_150,
P(40) => UC_151,
P(41) => UC_152,
P(42) => UC_153,
P(43) => UC_154,
P(44) => UC_155,
P(45) => UC_156,
P(46) => UC_157,
P(47) => UC_158,
PCOUT(0) => R1IN_4_3_0(0),
PCOUT(1) => R1IN_4_3_0(1),
PCOUT(2) => R1IN_4_3_0(2),
PCOUT(3) => R1IN_4_3_0(3),
PCOUT(4) => R1IN_4_3_0(4),
PCOUT(5) => R1IN_4_3_0(5),
PCOUT(6) => R1IN_4_3_0(6),
PCOUT(7) => R1IN_4_3_0(7),
PCOUT(8) => R1IN_4_3_0(8),
PCOUT(9) => R1IN_4_3_0(9),
PCOUT(10) => R1IN_4_3_0(10),
PCOUT(11) => R1IN_4_3_0(11),
PCOUT(12) => R1IN_4_3_0(12),
PCOUT(13) => R1IN_4_3_0(13),
PCOUT(14) => R1IN_4_3_0(14),
PCOUT(15) => R1IN_4_3_0(15),
PCOUT(16) => R1IN_4_3_0(16),
PCOUT(17) => R1IN_4_3_1_0(17),
PCOUT(18) => R1IN_4_3_1_0(18),
PCOUT(19) => R1IN_4_3_1_0(19),
PCOUT(20) => R1IN_4_3_1_0(20),
PCOUT(21) => R1IN_4_3_1_0(21),
PCOUT(22) => R1IN_4_3_1_0(22),
PCOUT(23) => R1IN_4_3_1_0(23),
PCOUT(24) => R1IN_4_3_1_0(24),
PCOUT(25) => R1IN_4_3_1_0(25),
PCOUT(26) => R1IN_4_3_1_0(26),
PCOUT(27) => R1IN_4_3_1_0(27),
PCOUT(28) => R1IN_4_3_1_0(28),
PCOUT(29) => R1IN_4_3_1_0(29),
PCOUT(30) => R1IN_4_3_1_0(30),
PCOUT(31) => R1IN_4_3_1_0(31),
PCOUT(32) => R1IN_4_3_1_0(32),
PCOUT(33) => R1IN_4_3_1_0(33),
PCOUT(34) => UC_145_0,
PCOUT(35) => UC_146_0,
PCOUT(36) => UC_147_0,
PCOUT(37) => UC_148_0,
PCOUT(38) => UC_149_0,
PCOUT(39) => UC_150_0,
PCOUT(40) => UC_151_0,
PCOUT(41) => UC_152_0,
PCOUT(42) => UC_153_0,
PCOUT(43) => UC_154_0,
PCOUT(44) => UC_155_0,
PCOUT(45) => UC_156_0,
PCOUT(46) => UC_157_0,
PCOUT(47) => UC_158_0);
\R1IN_4_2_1[33:0]\: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 0,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => A(34),
A(1) => A(35),
A(2) => A(36),
A(3) => A(37),
A(4) => A(38),
A(5) => A(39),
A(6) => A(40),
A(7) => A(41),
A(8) => A(42),
A(9) => A(43),
A(10) => A(44),
A(11) => A(45),
A(12) => A(46),
A(13) => A(47),
A(14) => A(48),
A(15) => A(49),
A(16) => A(50),
A(17) => NN_1,
B(0) => B(17),
B(1) => B(18),
B(2) => B(19),
B(3) => B(20),
B(4) => B(21),
B(5) => B(22),
B(6) => B(23),
B(7) => B(24),
B(8) => B(25),
B(9) => B(26),
B(10) => B(27),
B(11) => B(28),
B(12) => B(29),
B(13) => B(30),
B(14) => B(31),
B(15) => B(32),
B(16) => B(33),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => NN_1,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => NN_1,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_4_2_1_BCOUT(0),
BCOUT(1) => R1IN_4_2_1_BCOUT(1),
BCOUT(2) => R1IN_4_2_1_BCOUT(2),
BCOUT(3) => R1IN_4_2_1_BCOUT(3),
BCOUT(4) => R1IN_4_2_1_BCOUT(4),
BCOUT(5) => R1IN_4_2_1_BCOUT(5),
BCOUT(6) => R1IN_4_2_1_BCOUT(6),
BCOUT(7) => R1IN_4_2_1_BCOUT(7),
BCOUT(8) => R1IN_4_2_1_BCOUT(8),
BCOUT(9) => R1IN_4_2_1_BCOUT(9),
BCOUT(10) => R1IN_4_2_1_BCOUT(10),
BCOUT(11) => R1IN_4_2_1_BCOUT(11),
BCOUT(12) => R1IN_4_2_1_BCOUT(12),
BCOUT(13) => R1IN_4_2_1_BCOUT(13),
BCOUT(14) => R1IN_4_2_1_BCOUT(14),
BCOUT(15) => R1IN_4_2_1_BCOUT(15),
BCOUT(16) => R1IN_4_2_1_BCOUT(16),
BCOUT(17) => R1IN_4_2_1_BCOUT(17),
P(0) => R1IN_4_2(0),
P(1) => R1IN_4_2(1),
P(2) => R1IN_4_2(2),
P(3) => R1IN_4_2(3),
P(4) => R1IN_4_2(4),
P(5) => R1IN_4_2(5),
P(6) => R1IN_4_2(6),
P(7) => R1IN_4_2(7),
P(8) => R1IN_4_2(8),
P(9) => R1IN_4_2(9),
P(10) => R1IN_4_2(10),
P(11) => R1IN_4_2(11),
P(12) => R1IN_4_2(12),
P(13) => R1IN_4_2(13),
P(14) => R1IN_4_2(14),
P(15) => R1IN_4_2(15),
P(16) => R1IN_4_2(16),
P(17) => R1IN_4_2_1(17),
P(18) => R1IN_4_2_1(18),
P(19) => R1IN_4_2_1(19),
P(20) => R1IN_4_2_1(20),
P(21) => R1IN_4_2_1(21),
P(22) => R1IN_4_2_1(22),
P(23) => R1IN_4_2_1(23),
P(24) => R1IN_4_2_1(24),
P(25) => R1IN_4_2_1(25),
P(26) => R1IN_4_2_1(26),
P(27) => R1IN_4_2_1(27),
P(28) => R1IN_4_2_1(28),
P(29) => R1IN_4_2_1(29),
P(30) => R1IN_4_2_1(30),
P(31) => R1IN_4_2_1(31),
P(32) => R1IN_4_2_1(32),
P(33) => R1IN_4_2_1(33),
P(34) => UC_131,
P(35) => UC_132,
P(36) => UC_133,
P(37) => UC_134,
P(38) => UC_135,
P(39) => UC_136,
P(40) => UC_137,
P(41) => UC_138,
P(42) => UC_139,
P(43) => UC_140,
P(44) => UC_141,
P(45) => UC_142,
P(46) => UC_143,
P(47) => UC_144,
PCOUT(0) => R1IN_4_2_0(0),
PCOUT(1) => R1IN_4_2_0(1),
PCOUT(2) => R1IN_4_2_0(2),
PCOUT(3) => R1IN_4_2_0(3),
PCOUT(4) => R1IN_4_2_0(4),
PCOUT(5) => R1IN_4_2_0(5),
PCOUT(6) => R1IN_4_2_0(6),
PCOUT(7) => R1IN_4_2_0(7),
PCOUT(8) => R1IN_4_2_0(8),
PCOUT(9) => R1IN_4_2_0(9),
PCOUT(10) => R1IN_4_2_0(10),
PCOUT(11) => R1IN_4_2_0(11),
PCOUT(12) => R1IN_4_2_0(12),
PCOUT(13) => R1IN_4_2_0(13),
PCOUT(14) => R1IN_4_2_0(14),
PCOUT(15) => R1IN_4_2_0(15),
PCOUT(16) => R1IN_4_2_0(16),
PCOUT(17) => R1IN_4_2_1_0(17),
PCOUT(18) => R1IN_4_2_1_0(18),
PCOUT(19) => R1IN_4_2_1_0(19),
PCOUT(20) => R1IN_4_2_1_0(20),
PCOUT(21) => R1IN_4_2_1_0(21),
PCOUT(22) => R1IN_4_2_1_0(22),
PCOUT(23) => R1IN_4_2_1_0(23),
PCOUT(24) => R1IN_4_2_1_0(24),
PCOUT(25) => R1IN_4_2_1_0(25),
PCOUT(26) => R1IN_4_2_1_0(26),
PCOUT(27) => R1IN_4_2_1_0(27),
PCOUT(28) => R1IN_4_2_1_0(28),
PCOUT(29) => R1IN_4_2_1_0(29),
PCOUT(30) => R1IN_4_2_1_0(30),
PCOUT(31) => R1IN_4_2_1_0(31),
PCOUT(32) => R1IN_4_2_1_0(32),
PCOUT(33) => R1IN_4_2_1_0(33),
PCOUT(34) => UC_131_0,
PCOUT(35) => UC_132_0,
PCOUT(36) => UC_133_0,
PCOUT(37) => UC_134_0,
PCOUT(38) => UC_135_0,
PCOUT(39) => UC_136_0,
PCOUT(40) => UC_137_0,
PCOUT(41) => UC_138_0,
PCOUT(42) => UC_139_0,
PCOUT(43) => UC_140_0,
PCOUT(44) => UC_141_0,
PCOUT(45) => UC_142_0,
PCOUT(46) => UC_143_0,
PCOUT(47) => UC_144_0);
\R1IN_3_2_1[33:0]\: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 0,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => B(34),
A(1) => B(35),
A(2) => B(36),
A(3) => B(37),
A(4) => B(38),
A(5) => B(39),
A(6) => B(40),
A(7) => B(41),
A(8) => B(42),
A(9) => B(43),
A(10) => B(44),
A(11) => B(45),
A(12) => B(46),
A(13) => B(47),
A(14) => B(48),
A(15) => B(49),
A(16) => B(50),
A(17) => NN_1,
B(0) => A(0),
B(1) => A(1),
B(2) => A(2),
B(3) => A(3),
B(4) => A(4),
B(5) => A(5),
B(6) => A(6),
B(7) => A(7),
B(8) => A(8),
B(9) => A(9),
B(10) => A(10),
B(11) => A(11),
B(12) => A(12),
B(13) => A(13),
B(14) => A(14),
B(15) => A(15),
B(16) => A(16),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => NN_1,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => NN_1,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_3_2_1_BCOUT(0),
BCOUT(1) => R1IN_3_2_1_BCOUT(1),
BCOUT(2) => R1IN_3_2_1_BCOUT(2),
BCOUT(3) => R1IN_3_2_1_BCOUT(3),
BCOUT(4) => R1IN_3_2_1_BCOUT(4),
BCOUT(5) => R1IN_3_2_1_BCOUT(5),
BCOUT(6) => R1IN_3_2_1_BCOUT(6),
BCOUT(7) => R1IN_3_2_1_BCOUT(7),
BCOUT(8) => R1IN_3_2_1_BCOUT(8),
BCOUT(9) => R1IN_3_2_1_BCOUT(9),
BCOUT(10) => R1IN_3_2_1_BCOUT(10),
BCOUT(11) => R1IN_3_2_1_BCOUT(11),
BCOUT(12) => R1IN_3_2_1_BCOUT(12),
BCOUT(13) => R1IN_3_2_1_BCOUT(13),
BCOUT(14) => R1IN_3_2_1_BCOUT(14),
BCOUT(15) => R1IN_3_2_1_BCOUT(15),
BCOUT(16) => R1IN_3_2_1_BCOUT(16),
BCOUT(17) => R1IN_3_2_1_BCOUT(17),
P(0) => R1IN_3_2(0),
P(1) => R1IN_3_2(1),
P(2) => R1IN_3_2(2),
P(3) => R1IN_3_2(3),
P(4) => R1IN_3_2(4),
P(5) => R1IN_3_2(5),
P(6) => R1IN_3_2(6),
P(7) => R1IN_3_2(7),
P(8) => R1IN_3_2(8),
P(9) => R1IN_3_2(9),
P(10) => R1IN_3_2(10),
P(11) => R1IN_3_2(11),
P(12) => R1IN_3_2(12),
P(13) => R1IN_3_2(13),
P(14) => R1IN_3_2(14),
P(15) => R1IN_3_2(15),
P(16) => R1IN_3_2(16),
P(17) => R1IN_3_2_1(17),
P(18) => R1IN_3_2_1(18),
P(19) => R1IN_3_2_1(19),
P(20) => R1IN_3_2_1(20),
P(21) => R1IN_3_2_1(21),
P(22) => R1IN_3_2_1(22),
P(23) => R1IN_3_2_1(23),
P(24) => R1IN_3_2_1(24),
P(25) => R1IN_3_2_1(25),
P(26) => R1IN_3_2_1(26),
P(27) => R1IN_3_2_1(27),
P(28) => R1IN_3_2_1(28),
P(29) => R1IN_3_2_1(29),
P(30) => R1IN_3_2_1(30),
P(31) => R1IN_3_2_1(31),
P(32) => R1IN_3_2_1(32),
P(33) => R1IN_3_2_1(33),
P(34) => UC_117,
P(35) => UC_118,
P(36) => UC_119,
P(37) => UC_120,
P(38) => UC_121,
P(39) => UC_122,
P(40) => UC_123,
P(41) => UC_124,
P(42) => UC_125,
P(43) => UC_126,
P(44) => UC_127,
P(45) => UC_128,
P(46) => UC_129,
P(47) => UC_130,
PCOUT(0) => R1IN_3_2_0(0),
PCOUT(1) => R1IN_3_2_0(1),
PCOUT(2) => R1IN_3_2_0(2),
PCOUT(3) => R1IN_3_2_0(3),
PCOUT(4) => R1IN_3_2_0(4),
PCOUT(5) => R1IN_3_2_0(5),
PCOUT(6) => R1IN_3_2_0(6),
PCOUT(7) => R1IN_3_2_0(7),
PCOUT(8) => R1IN_3_2_0(8),
PCOUT(9) => R1IN_3_2_0(9),
PCOUT(10) => R1IN_3_2_0(10),
PCOUT(11) => R1IN_3_2_0(11),
PCOUT(12) => R1IN_3_2_0(12),
PCOUT(13) => R1IN_3_2_0(13),
PCOUT(14) => R1IN_3_2_0(14),
PCOUT(15) => R1IN_3_2_0(15),
PCOUT(16) => R1IN_3_2_0(16),
PCOUT(17) => R1IN_3_2_1_0(17),
PCOUT(18) => R1IN_3_2_1_0(18),
PCOUT(19) => R1IN_3_2_1_0(19),
PCOUT(20) => R1IN_3_2_1_0(20),
PCOUT(21) => R1IN_3_2_1_0(21),
PCOUT(22) => R1IN_3_2_1_0(22),
PCOUT(23) => R1IN_3_2_1_0(23),
PCOUT(24) => R1IN_3_2_1_0(24),
PCOUT(25) => R1IN_3_2_1_0(25),
PCOUT(26) => R1IN_3_2_1_0(26),
PCOUT(27) => R1IN_3_2_1_0(27),
PCOUT(28) => R1IN_3_2_1_0(28),
PCOUT(29) => R1IN_3_2_1_0(29),
PCOUT(30) => R1IN_3_2_1_0(30),
PCOUT(31) => R1IN_3_2_1_0(31),
PCOUT(32) => R1IN_3_2_1_0(32),
PCOUT(33) => R1IN_3_2_1_0(33),
PCOUT(34) => UC_117_0,
PCOUT(35) => UC_118_0,
PCOUT(36) => UC_119_0,
PCOUT(37) => UC_120_0,
PCOUT(38) => UC_121_0,
PCOUT(39) => UC_122_0,
PCOUT(40) => UC_123_0,
PCOUT(41) => UC_124_0,
PCOUT(42) => UC_125_0,
PCOUT(43) => UC_126_0,
PCOUT(44) => UC_127_0,
PCOUT(45) => UC_128_0,
PCOUT(46) => UC_129_0,
PCOUT(47) => UC_130_0);
\R1IN_2_2_1[33:0]\: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 0,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => A(34),
A(1) => A(35),
A(2) => A(36),
A(3) => A(37),
A(4) => A(38),
A(5) => A(39),
A(6) => A(40),
A(7) => A(41),
A(8) => A(42),
A(9) => A(43),
A(10) => A(44),
A(11) => A(45),
A(12) => A(46),
A(13) => A(47),
A(14) => A(48),
A(15) => A(49),
A(16) => A(50),
A(17) => NN_1,
B(0) => B(0),
B(1) => B(1),
B(2) => B(2),
B(3) => B(3),
B(4) => B(4),
B(5) => B(5),
B(6) => B(6),
B(7) => B(7),
B(8) => B(8),
B(9) => B(9),
B(10) => B(10),
B(11) => B(11),
B(12) => B(12),
B(13) => B(13),
B(14) => B(14),
B(15) => B(15),
B(16) => B(16),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => NN_1,
PCIN(1) => NN_1,
PCIN(2) => NN_1,
PCIN(3) => NN_1,
PCIN(4) => NN_1,
PCIN(5) => NN_1,
PCIN(6) => NN_1,
PCIN(7) => NN_1,
PCIN(8) => NN_1,
PCIN(9) => NN_1,
PCIN(10) => NN_1,
PCIN(11) => NN_1,
PCIN(12) => NN_1,
PCIN(13) => NN_1,
PCIN(14) => NN_1,
PCIN(15) => NN_1,
PCIN(16) => NN_1,
PCIN(17) => NN_1,
PCIN(18) => NN_1,
PCIN(19) => NN_1,
PCIN(20) => NN_1,
PCIN(21) => NN_1,
PCIN(22) => NN_1,
PCIN(23) => NN_1,
PCIN(24) => NN_1,
PCIN(25) => NN_1,
PCIN(26) => NN_1,
PCIN(27) => NN_1,
PCIN(28) => NN_1,
PCIN(29) => NN_1,
PCIN(30) => NN_1,
PCIN(31) => NN_1,
PCIN(32) => NN_1,
PCIN(33) => NN_1,
PCIN(34) => NN_1,
PCIN(35) => NN_1,
PCIN(36) => NN_1,
PCIN(37) => NN_1,
PCIN(38) => NN_1,
PCIN(39) => NN_1,
PCIN(40) => NN_1,
PCIN(41) => NN_1,
PCIN(42) => NN_1,
PCIN(43) => NN_1,
PCIN(44) => NN_1,
PCIN(45) => NN_1,
PCIN(46) => NN_1,
PCIN(47) => NN_1,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_1,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => NN_1,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => NN_1,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_2_2_1_BCOUT(0),
BCOUT(1) => R1IN_2_2_1_BCOUT(1),
BCOUT(2) => R1IN_2_2_1_BCOUT(2),
BCOUT(3) => R1IN_2_2_1_BCOUT(3),
BCOUT(4) => R1IN_2_2_1_BCOUT(4),
BCOUT(5) => R1IN_2_2_1_BCOUT(5),
BCOUT(6) => R1IN_2_2_1_BCOUT(6),
BCOUT(7) => R1IN_2_2_1_BCOUT(7),
BCOUT(8) => R1IN_2_2_1_BCOUT(8),
BCOUT(9) => R1IN_2_2_1_BCOUT(9),
BCOUT(10) => R1IN_2_2_1_BCOUT(10),
BCOUT(11) => R1IN_2_2_1_BCOUT(11),
BCOUT(12) => R1IN_2_2_1_BCOUT(12),
BCOUT(13) => R1IN_2_2_1_BCOUT(13),
BCOUT(14) => R1IN_2_2_1_BCOUT(14),
BCOUT(15) => R1IN_2_2_1_BCOUT(15),
BCOUT(16) => R1IN_2_2_1_BCOUT(16),
BCOUT(17) => R1IN_2_2_1_BCOUT(17),
P(0) => R1IN_2_2(0),
P(1) => R1IN_2_2(1),
P(2) => R1IN_2_2(2),
P(3) => R1IN_2_2(3),
P(4) => R1IN_2_2(4),
P(5) => R1IN_2_2(5),
P(6) => R1IN_2_2(6),
P(7) => R1IN_2_2(7),
P(8) => R1IN_2_2(8),
P(9) => R1IN_2_2(9),
P(10) => R1IN_2_2(10),
P(11) => R1IN_2_2(11),
P(12) => R1IN_2_2(12),
P(13) => R1IN_2_2(13),
P(14) => R1IN_2_2(14),
P(15) => R1IN_2_2(15),
P(16) => R1IN_2_2(16),
P(17) => R1IN_2_2_1(17),
P(18) => R1IN_2_2_1(18),
P(19) => R1IN_2_2_1(19),
P(20) => R1IN_2_2_1(20),
P(21) => R1IN_2_2_1(21),
P(22) => R1IN_2_2_1(22),
P(23) => R1IN_2_2_1(23),
P(24) => R1IN_2_2_1(24),
P(25) => R1IN_2_2_1(25),
P(26) => R1IN_2_2_1(26),
P(27) => R1IN_2_2_1(27),
P(28) => R1IN_2_2_1(28),
P(29) => R1IN_2_2_1(29),
P(30) => R1IN_2_2_1(30),
P(31) => R1IN_2_2_1(31),
P(32) => R1IN_2_2_1(32),
P(33) => R1IN_2_2_1(33),
P(34) => UC_103,
P(35) => UC_104,
P(36) => UC_105,
P(37) => UC_106,
P(38) => UC_107,
P(39) => UC_108,
P(40) => UC_109,
P(41) => UC_110,
P(42) => UC_111,
P(43) => UC_112,
P(44) => UC_113,
P(45) => UC_114,
P(46) => UC_115,
P(47) => UC_116,
PCOUT(0) => R1IN_2_2_0(0),
PCOUT(1) => R1IN_2_2_0(1),
PCOUT(2) => R1IN_2_2_0(2),
PCOUT(3) => R1IN_2_2_0(3),
PCOUT(4) => R1IN_2_2_0(4),
PCOUT(5) => R1IN_2_2_0(5),
PCOUT(6) => R1IN_2_2_0(6),
PCOUT(7) => R1IN_2_2_0(7),
PCOUT(8) => R1IN_2_2_0(8),
PCOUT(9) => R1IN_2_2_0(9),
PCOUT(10) => R1IN_2_2_0(10),
PCOUT(11) => R1IN_2_2_0(11),
PCOUT(12) => R1IN_2_2_0(12),
PCOUT(13) => R1IN_2_2_0(13),
PCOUT(14) => R1IN_2_2_0(14),
PCOUT(15) => R1IN_2_2_0(15),
PCOUT(16) => R1IN_2_2_0(16),
PCOUT(17) => R1IN_2_2_1_0(17),
PCOUT(18) => R1IN_2_2_1_0(18),
PCOUT(19) => R1IN_2_2_1_0(19),
PCOUT(20) => R1IN_2_2_1_0(20),
PCOUT(21) => R1IN_2_2_1_0(21),
PCOUT(22) => R1IN_2_2_1_0(22),
PCOUT(23) => R1IN_2_2_1_0(23),
PCOUT(24) => R1IN_2_2_1_0(24),
PCOUT(25) => R1IN_2_2_1_0(25),
PCOUT(26) => R1IN_2_2_1_0(26),
PCOUT(27) => R1IN_2_2_1_0(27),
PCOUT(28) => R1IN_2_2_1_0(28),
PCOUT(29) => R1IN_2_2_1_0(29),
PCOUT(30) => R1IN_2_2_1_0(30),
PCOUT(31) => R1IN_2_2_1_0(31),
PCOUT(32) => R1IN_2_2_1_0(32),
PCOUT(33) => R1IN_2_2_1_0(33),
PCOUT(34) => UC_103_0,
PCOUT(35) => UC_104_0,
PCOUT(36) => UC_105_0,
PCOUT(37) => UC_106_0,
PCOUT(38) => UC_107_0,
PCOUT(39) => UC_108_0,
PCOUT(40) => UC_109_0,
PCOUT(41) => UC_110_0,
PCOUT(42) => UC_111_0,
PCOUT(43) => UC_112_0,
PCOUT(44) => UC_113_0,
PCOUT(45) => UC_114_0,
PCOUT(46) => UC_115_0,
PCOUT(47) => UC_116_0);
\R1IN_4_3_ADD_1[26:0]\: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 1,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => B(51),
A(1) => B(52),
A(2) => B(53),
A(3) => B(54),
A(4) => B(55),
A(5) => B(56),
A(6) => B(57),
A(7) => B(58),
A(8) => B(59),
A(9) => B(60),
A(10) => NN_1,
A(11) => NN_1,
A(12) => NN_1,
A(13) => NN_1,
A(14) => NN_1,
A(15) => NN_1,
A(16) => NN_1,
A(17) => NN_1,
B(0) => A(17),
B(1) => A(18),
B(2) => A(19),
B(3) => A(20),
B(4) => A(21),
B(5) => A(22),
B(6) => A(23),
B(7) => A(24),
B(8) => A(25),
B(9) => A(26),
B(10) => A(27),
B(11) => A(28),
B(12) => A(29),
B(13) => A(30),
B(14) => A(31),
B(15) => A(32),
B(16) => A(33),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => R1IN_4_3_0(0),
PCIN(1) => R1IN_4_3_0(1),
PCIN(2) => R1IN_4_3_0(2),
PCIN(3) => R1IN_4_3_0(3),
PCIN(4) => R1IN_4_3_0(4),
PCIN(5) => R1IN_4_3_0(5),
PCIN(6) => R1IN_4_3_0(6),
PCIN(7) => R1IN_4_3_0(7),
PCIN(8) => R1IN_4_3_0(8),
PCIN(9) => R1IN_4_3_0(9),
PCIN(10) => R1IN_4_3_0(10),
PCIN(11) => R1IN_4_3_0(11),
PCIN(12) => R1IN_4_3_0(12),
PCIN(13) => R1IN_4_3_0(13),
PCIN(14) => R1IN_4_3_0(14),
PCIN(15) => R1IN_4_3_0(15),
PCIN(16) => R1IN_4_3_0(16),
PCIN(17) => R1IN_4_3_1_0(17),
PCIN(18) => R1IN_4_3_1_0(18),
PCIN(19) => R1IN_4_3_1_0(19),
PCIN(20) => R1IN_4_3_1_0(20),
PCIN(21) => R1IN_4_3_1_0(21),
PCIN(22) => R1IN_4_3_1_0(22),
PCIN(23) => R1IN_4_3_1_0(23),
PCIN(24) => R1IN_4_3_1_0(24),
PCIN(25) => R1IN_4_3_1_0(25),
PCIN(26) => R1IN_4_3_1_0(26),
PCIN(27) => R1IN_4_3_1_0(27),
PCIN(28) => R1IN_4_3_1_0(28),
PCIN(29) => R1IN_4_3_1_0(29),
PCIN(30) => R1IN_4_3_1_0(30),
PCIN(31) => R1IN_4_3_1_0(31),
PCIN(32) => R1IN_4_3_1_0(32),
PCIN(33) => R1IN_4_3_1_0(33),
PCIN(34) => UC_145_0,
PCIN(35) => UC_146_0,
PCIN(36) => UC_147_0,
PCIN(37) => UC_148_0,
PCIN(38) => UC_149_0,
PCIN(39) => UC_150_0,
PCIN(40) => UC_151_0,
PCIN(41) => UC_152_0,
PCIN(42) => UC_153_0,
PCIN(43) => UC_154_0,
PCIN(44) => UC_155_0,
PCIN(45) => UC_156_0,
PCIN(46) => UC_157_0,
PCIN(47) => UC_158_0,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_2,
OPMODE(5) => NN_1,
OPMODE(6) => NN_2,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => EN,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_4_3_ADD_1_BCOUT(0),
BCOUT(1) => R1IN_4_3_ADD_1_BCOUT(1),
BCOUT(2) => R1IN_4_3_ADD_1_BCOUT(2),
BCOUT(3) => R1IN_4_3_ADD_1_BCOUT(3),
BCOUT(4) => R1IN_4_3_ADD_1_BCOUT(4),
BCOUT(5) => R1IN_4_3_ADD_1_BCOUT(5),
BCOUT(6) => R1IN_4_3_ADD_1_BCOUT(6),
BCOUT(7) => R1IN_4_3_ADD_1_BCOUT(7),
BCOUT(8) => R1IN_4_3_ADD_1_BCOUT(8),
BCOUT(9) => R1IN_4_3_ADD_1_BCOUT(9),
BCOUT(10) => R1IN_4_3_ADD_1_BCOUT(10),
BCOUT(11) => R1IN_4_3_ADD_1_BCOUT(11),
BCOUT(12) => R1IN_4_3_ADD_1_BCOUT(12),
BCOUT(13) => R1IN_4_3_ADD_1_BCOUT(13),
BCOUT(14) => R1IN_4_3_ADD_1_BCOUT(14),
BCOUT(15) => R1IN_4_3_ADD_1_BCOUT(15),
BCOUT(16) => R1IN_4_3_ADD_1_BCOUT(16),
BCOUT(17) => R1IN_4_3_ADD_1_BCOUT(17),
P(0) => R1IN_4_3F(17),
P(1) => R1IN_4_3F(18),
P(2) => R1IN_4_3F(19),
P(3) => R1IN_4_3F(20),
P(4) => R1IN_4_3F(21),
P(5) => R1IN_4_3F(22),
P(6) => R1IN_4_3F(23),
P(7) => R1IN_4_3F(24),
P(8) => R1IN_4_3F(25),
P(9) => R1IN_4_3F(26),
P(10) => R1IN_4_3F(27),
P(11) => R1IN_4_3F(28),
P(12) => R1IN_4_3F(29),
P(13) => R1IN_4_3F(30),
P(14) => R1IN_4_3F(31),
P(15) => R1IN_4_3F(32),
P(16) => R1IN_4_3F(33),
P(17) => R1IN_4_3F(34),
P(18) => R1IN_4_3F(35),
P(19) => R1IN_4_3F(36),
P(20) => R1IN_4_3F(37),
P(21) => R1IN_4_3F(38),
P(22) => R1IN_4_3F(39),
P(23) => R1IN_4_3F(40),
P(24) => R1IN_4_3F(41),
P(25) => R1IN_4_3F(42),
P(26) => R1IN_4_3F(43),
P(27) => UC_82,
P(28) => UC_83,
P(29) => UC_84,
P(30) => UC_85,
P(31) => UC_86,
P(32) => UC_87,
P(33) => UC_88,
P(34) => UC_89,
P(35) => UC_90,
P(36) => UC_91,
P(37) => UC_92,
P(38) => UC_93,
P(39) => UC_94,
P(40) => UC_95,
P(41) => UC_96,
P(42) => UC_97,
P(43) => UC_98,
P(44) => UC_99,
P(45) => UC_100,
P(46) => UC_101,
P(47) => UC_102,
PCOUT(0) => R1IN_4_3_ADD_1_PCOUT(0),
PCOUT(1) => R1IN_4_3_ADD_1_PCOUT(1),
PCOUT(2) => R1IN_4_3_ADD_1_PCOUT(2),
PCOUT(3) => R1IN_4_3_ADD_1_PCOUT(3),
PCOUT(4) => R1IN_4_3_ADD_1_PCOUT(4),
PCOUT(5) => R1IN_4_3_ADD_1_PCOUT(5),
PCOUT(6) => R1IN_4_3_ADD_1_PCOUT(6),
PCOUT(7) => R1IN_4_3_ADD_1_PCOUT(7),
PCOUT(8) => R1IN_4_3_ADD_1_PCOUT(8),
PCOUT(9) => R1IN_4_3_ADD_1_PCOUT(9),
PCOUT(10) => R1IN_4_3_ADD_1_PCOUT(10),
PCOUT(11) => R1IN_4_3_ADD_1_PCOUT(11),
PCOUT(12) => R1IN_4_3_ADD_1_PCOUT(12),
PCOUT(13) => R1IN_4_3_ADD_1_PCOUT(13),
PCOUT(14) => R1IN_4_3_ADD_1_PCOUT(14),
PCOUT(15) => R1IN_4_3_ADD_1_PCOUT(15),
PCOUT(16) => R1IN_4_3_ADD_1_PCOUT(16),
PCOUT(17) => R1IN_4_3_ADD_1_PCOUT(17),
PCOUT(18) => R1IN_4_3_ADD_1_PCOUT(18),
PCOUT(19) => R1IN_4_3_ADD_1_PCOUT(19),
PCOUT(20) => R1IN_4_3_ADD_1_PCOUT(20),
PCOUT(21) => R1IN_4_3_ADD_1_PCOUT(21),
PCOUT(22) => R1IN_4_3_ADD_1_PCOUT(22),
PCOUT(23) => R1IN_4_3_ADD_1_PCOUT(23),
PCOUT(24) => R1IN_4_3_ADD_1_PCOUT(24),
PCOUT(25) => R1IN_4_3_ADD_1_PCOUT(25),
PCOUT(26) => R1IN_4_3_ADD_1_PCOUT(26),
PCOUT(27) => R1IN_4_3_ADD_1_PCOUT(27),
PCOUT(28) => R1IN_4_3_ADD_1_PCOUT(28),
PCOUT(29) => R1IN_4_3_ADD_1_PCOUT(29),
PCOUT(30) => R1IN_4_3_ADD_1_PCOUT(30),
PCOUT(31) => R1IN_4_3_ADD_1_PCOUT(31),
PCOUT(32) => R1IN_4_3_ADD_1_PCOUT(32),
PCOUT(33) => R1IN_4_3_ADD_1_PCOUT(33),
PCOUT(34) => R1IN_4_3_ADD_1_PCOUT(34),
PCOUT(35) => R1IN_4_3_ADD_1_PCOUT(35),
PCOUT(36) => R1IN_4_3_ADD_1_PCOUT(36),
PCOUT(37) => R1IN_4_3_ADD_1_PCOUT(37),
PCOUT(38) => R1IN_4_3_ADD_1_PCOUT(38),
PCOUT(39) => R1IN_4_3_ADD_1_PCOUT(39),
PCOUT(40) => R1IN_4_3_ADD_1_PCOUT(40),
PCOUT(41) => R1IN_4_3_ADD_1_PCOUT(41),
PCOUT(42) => R1IN_4_3_ADD_1_PCOUT(42),
PCOUT(43) => R1IN_4_3_ADD_1_PCOUT(43),
PCOUT(44) => R1IN_4_3_ADD_1_PCOUT(44),
PCOUT(45) => R1IN_4_3_ADD_1_PCOUT(45),
PCOUT(46) => R1IN_4_3_ADD_1_PCOUT(46),
PCOUT(47) => R1IN_4_3_ADD_1_PCOUT(47));
\R1IN_4_2_ADD_1[26:0]\: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 1,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => A(51),
A(1) => A(52),
A(2) => A(53),
A(3) => A(54),
A(4) => A(55),
A(5) => A(56),
A(6) => A(57),
A(7) => A(58),
A(8) => A(59),
A(9) => A(60),
A(10) => NN_1,
A(11) => NN_1,
A(12) => NN_1,
A(13) => NN_1,
A(14) => NN_1,
A(15) => NN_1,
A(16) => NN_1,
A(17) => NN_1,
B(0) => B(17),
B(1) => B(18),
B(2) => B(19),
B(3) => B(20),
B(4) => B(21),
B(5) => B(22),
B(6) => B(23),
B(7) => B(24),
B(8) => B(25),
B(9) => B(26),
B(10) => B(27),
B(11) => B(28),
B(12) => B(29),
B(13) => B(30),
B(14) => B(31),
B(15) => B(32),
B(16) => B(33),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => R1IN_4_2_0(0),
PCIN(1) => R1IN_4_2_0(1),
PCIN(2) => R1IN_4_2_0(2),
PCIN(3) => R1IN_4_2_0(3),
PCIN(4) => R1IN_4_2_0(4),
PCIN(5) => R1IN_4_2_0(5),
PCIN(6) => R1IN_4_2_0(6),
PCIN(7) => R1IN_4_2_0(7),
PCIN(8) => R1IN_4_2_0(8),
PCIN(9) => R1IN_4_2_0(9),
PCIN(10) => R1IN_4_2_0(10),
PCIN(11) => R1IN_4_2_0(11),
PCIN(12) => R1IN_4_2_0(12),
PCIN(13) => R1IN_4_2_0(13),
PCIN(14) => R1IN_4_2_0(14),
PCIN(15) => R1IN_4_2_0(15),
PCIN(16) => R1IN_4_2_0(16),
PCIN(17) => R1IN_4_2_1_0(17),
PCIN(18) => R1IN_4_2_1_0(18),
PCIN(19) => R1IN_4_2_1_0(19),
PCIN(20) => R1IN_4_2_1_0(20),
PCIN(21) => R1IN_4_2_1_0(21),
PCIN(22) => R1IN_4_2_1_0(22),
PCIN(23) => R1IN_4_2_1_0(23),
PCIN(24) => R1IN_4_2_1_0(24),
PCIN(25) => R1IN_4_2_1_0(25),
PCIN(26) => R1IN_4_2_1_0(26),
PCIN(27) => R1IN_4_2_1_0(27),
PCIN(28) => R1IN_4_2_1_0(28),
PCIN(29) => R1IN_4_2_1_0(29),
PCIN(30) => R1IN_4_2_1_0(30),
PCIN(31) => R1IN_4_2_1_0(31),
PCIN(32) => R1IN_4_2_1_0(32),
PCIN(33) => R1IN_4_2_1_0(33),
PCIN(34) => UC_131_0,
PCIN(35) => UC_132_0,
PCIN(36) => UC_133_0,
PCIN(37) => UC_134_0,
PCIN(38) => UC_135_0,
PCIN(39) => UC_136_0,
PCIN(40) => UC_137_0,
PCIN(41) => UC_138_0,
PCIN(42) => UC_139_0,
PCIN(43) => UC_140_0,
PCIN(44) => UC_141_0,
PCIN(45) => UC_142_0,
PCIN(46) => UC_143_0,
PCIN(47) => UC_144_0,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_2,
OPMODE(5) => NN_1,
OPMODE(6) => NN_2,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => EN,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_4_2_ADD_1_BCOUT(0),
BCOUT(1) => R1IN_4_2_ADD_1_BCOUT(1),
BCOUT(2) => R1IN_4_2_ADD_1_BCOUT(2),
BCOUT(3) => R1IN_4_2_ADD_1_BCOUT(3),
BCOUT(4) => R1IN_4_2_ADD_1_BCOUT(4),
BCOUT(5) => R1IN_4_2_ADD_1_BCOUT(5),
BCOUT(6) => R1IN_4_2_ADD_1_BCOUT(6),
BCOUT(7) => R1IN_4_2_ADD_1_BCOUT(7),
BCOUT(8) => R1IN_4_2_ADD_1_BCOUT(8),
BCOUT(9) => R1IN_4_2_ADD_1_BCOUT(9),
BCOUT(10) => R1IN_4_2_ADD_1_BCOUT(10),
BCOUT(11) => R1IN_4_2_ADD_1_BCOUT(11),
BCOUT(12) => R1IN_4_2_ADD_1_BCOUT(12),
BCOUT(13) => R1IN_4_2_ADD_1_BCOUT(13),
BCOUT(14) => R1IN_4_2_ADD_1_BCOUT(14),
BCOUT(15) => R1IN_4_2_ADD_1_BCOUT(15),
BCOUT(16) => R1IN_4_2_ADD_1_BCOUT(16),
BCOUT(17) => R1IN_4_2_ADD_1_BCOUT(17),
P(0) => R1IN_4_2F(17),
P(1) => R1IN_4_2F(18),
P(2) => R1IN_4_2F(19),
P(3) => R1IN_4_2F(20),
P(4) => R1IN_4_2F(21),
P(5) => R1IN_4_2F(22),
P(6) => R1IN_4_2F(23),
P(7) => R1IN_4_2F(24),
P(8) => R1IN_4_2F(25),
P(9) => R1IN_4_2F(26),
P(10) => R1IN_4_2F(27),
P(11) => R1IN_4_2F(28),
P(12) => R1IN_4_2F(29),
P(13) => R1IN_4_2F(30),
P(14) => R1IN_4_2F(31),
P(15) => R1IN_4_2F(32),
P(16) => R1IN_4_2F(33),
P(17) => R1IN_4_2F(34),
P(18) => R1IN_4_2F(35),
P(19) => R1IN_4_2F(36),
P(20) => R1IN_4_2F(37),
P(21) => R1IN_4_2F(38),
P(22) => R1IN_4_2F(39),
P(23) => R1IN_4_2F(40),
P(24) => R1IN_4_2F(41),
P(25) => R1IN_4_2F(42),
P(26) => R1IN_4_2F(43),
P(27) => UC_61,
P(28) => UC_62,
P(29) => UC_63,
P(30) => UC_64,
P(31) => UC_65,
P(32) => UC_66,
P(33) => UC_67,
P(34) => UC_68,
P(35) => UC_69,
P(36) => UC_70,
P(37) => UC_71,
P(38) => UC_72,
P(39) => UC_73,
P(40) => UC_74,
P(41) => UC_75,
P(42) => UC_76,
P(43) => UC_77,
P(44) => UC_78,
P(45) => UC_79,
P(46) => UC_80,
P(47) => UC_81,
PCOUT(0) => R1IN_4_2_ADD_1_PCOUT(0),
PCOUT(1) => R1IN_4_2_ADD_1_PCOUT(1),
PCOUT(2) => R1IN_4_2_ADD_1_PCOUT(2),
PCOUT(3) => R1IN_4_2_ADD_1_PCOUT(3),
PCOUT(4) => R1IN_4_2_ADD_1_PCOUT(4),
PCOUT(5) => R1IN_4_2_ADD_1_PCOUT(5),
PCOUT(6) => R1IN_4_2_ADD_1_PCOUT(6),
PCOUT(7) => R1IN_4_2_ADD_1_PCOUT(7),
PCOUT(8) => R1IN_4_2_ADD_1_PCOUT(8),
PCOUT(9) => R1IN_4_2_ADD_1_PCOUT(9),
PCOUT(10) => R1IN_4_2_ADD_1_PCOUT(10),
PCOUT(11) => R1IN_4_2_ADD_1_PCOUT(11),
PCOUT(12) => R1IN_4_2_ADD_1_PCOUT(12),
PCOUT(13) => R1IN_4_2_ADD_1_PCOUT(13),
PCOUT(14) => R1IN_4_2_ADD_1_PCOUT(14),
PCOUT(15) => R1IN_4_2_ADD_1_PCOUT(15),
PCOUT(16) => R1IN_4_2_ADD_1_PCOUT(16),
PCOUT(17) => R1IN_4_2_ADD_1_PCOUT(17),
PCOUT(18) => R1IN_4_2_ADD_1_PCOUT(18),
PCOUT(19) => R1IN_4_2_ADD_1_PCOUT(19),
PCOUT(20) => R1IN_4_2_ADD_1_PCOUT(20),
PCOUT(21) => R1IN_4_2_ADD_1_PCOUT(21),
PCOUT(22) => R1IN_4_2_ADD_1_PCOUT(22),
PCOUT(23) => R1IN_4_2_ADD_1_PCOUT(23),
PCOUT(24) => R1IN_4_2_ADD_1_PCOUT(24),
PCOUT(25) => R1IN_4_2_ADD_1_PCOUT(25),
PCOUT(26) => R1IN_4_2_ADD_1_PCOUT(26),
PCOUT(27) => R1IN_4_2_ADD_1_PCOUT(27),
PCOUT(28) => R1IN_4_2_ADD_1_PCOUT(28),
PCOUT(29) => R1IN_4_2_ADD_1_PCOUT(29),
PCOUT(30) => R1IN_4_2_ADD_1_PCOUT(30),
PCOUT(31) => R1IN_4_2_ADD_1_PCOUT(31),
PCOUT(32) => R1IN_4_2_ADD_1_PCOUT(32),
PCOUT(33) => R1IN_4_2_ADD_1_PCOUT(33),
PCOUT(34) => R1IN_4_2_ADD_1_PCOUT(34),
PCOUT(35) => R1IN_4_2_ADD_1_PCOUT(35),
PCOUT(36) => R1IN_4_2_ADD_1_PCOUT(36),
PCOUT(37) => R1IN_4_2_ADD_1_PCOUT(37),
PCOUT(38) => R1IN_4_2_ADD_1_PCOUT(38),
PCOUT(39) => R1IN_4_2_ADD_1_PCOUT(39),
PCOUT(40) => R1IN_4_2_ADD_1_PCOUT(40),
PCOUT(41) => R1IN_4_2_ADD_1_PCOUT(41),
PCOUT(42) => R1IN_4_2_ADD_1_PCOUT(42),
PCOUT(43) => R1IN_4_2_ADD_1_PCOUT(43),
PCOUT(44) => R1IN_4_2_ADD_1_PCOUT(44),
PCOUT(45) => R1IN_4_2_ADD_1_PCOUT(45),
PCOUT(46) => R1IN_4_2_ADD_1_PCOUT(46),
PCOUT(47) => R1IN_4_2_ADD_1_PCOUT(47));
\R1IN_3_2_ADD_1[26:0]\: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 1,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => B(51),
A(1) => B(52),
A(2) => B(53),
A(3) => B(54),
A(4) => B(55),
A(5) => B(56),
A(6) => B(57),
A(7) => B(58),
A(8) => B(59),
A(9) => B(60),
A(10) => NN_1,
A(11) => NN_1,
A(12) => NN_1,
A(13) => NN_1,
A(14) => NN_1,
A(15) => NN_1,
A(16) => NN_1,
A(17) => NN_1,
B(0) => A(0),
B(1) => A(1),
B(2) => A(2),
B(3) => A(3),
B(4) => A(4),
B(5) => A(5),
B(6) => A(6),
B(7) => A(7),
B(8) => A(8),
B(9) => A(9),
B(10) => A(10),
B(11) => A(11),
B(12) => A(12),
B(13) => A(13),
B(14) => A(14),
B(15) => A(15),
B(16) => A(16),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => R1IN_3_2_0(0),
PCIN(1) => R1IN_3_2_0(1),
PCIN(2) => R1IN_3_2_0(2),
PCIN(3) => R1IN_3_2_0(3),
PCIN(4) => R1IN_3_2_0(4),
PCIN(5) => R1IN_3_2_0(5),
PCIN(6) => R1IN_3_2_0(6),
PCIN(7) => R1IN_3_2_0(7),
PCIN(8) => R1IN_3_2_0(8),
PCIN(9) => R1IN_3_2_0(9),
PCIN(10) => R1IN_3_2_0(10),
PCIN(11) => R1IN_3_2_0(11),
PCIN(12) => R1IN_3_2_0(12),
PCIN(13) => R1IN_3_2_0(13),
PCIN(14) => R1IN_3_2_0(14),
PCIN(15) => R1IN_3_2_0(15),
PCIN(16) => R1IN_3_2_0(16),
PCIN(17) => R1IN_3_2_1_0(17),
PCIN(18) => R1IN_3_2_1_0(18),
PCIN(19) => R1IN_3_2_1_0(19),
PCIN(20) => R1IN_3_2_1_0(20),
PCIN(21) => R1IN_3_2_1_0(21),
PCIN(22) => R1IN_3_2_1_0(22),
PCIN(23) => R1IN_3_2_1_0(23),
PCIN(24) => R1IN_3_2_1_0(24),
PCIN(25) => R1IN_3_2_1_0(25),
PCIN(26) => R1IN_3_2_1_0(26),
PCIN(27) => R1IN_3_2_1_0(27),
PCIN(28) => R1IN_3_2_1_0(28),
PCIN(29) => R1IN_3_2_1_0(29),
PCIN(30) => R1IN_3_2_1_0(30),
PCIN(31) => R1IN_3_2_1_0(31),
PCIN(32) => R1IN_3_2_1_0(32),
PCIN(33) => R1IN_3_2_1_0(33),
PCIN(34) => UC_117_0,
PCIN(35) => UC_118_0,
PCIN(36) => UC_119_0,
PCIN(37) => UC_120_0,
PCIN(38) => UC_121_0,
PCIN(39) => UC_122_0,
PCIN(40) => UC_123_0,
PCIN(41) => UC_124_0,
PCIN(42) => UC_125_0,
PCIN(43) => UC_126_0,
PCIN(44) => UC_127_0,
PCIN(45) => UC_128_0,
PCIN(46) => UC_129_0,
PCIN(47) => UC_130_0,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_2,
OPMODE(5) => NN_1,
OPMODE(6) => NN_2,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => EN,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_3_2_ADD_1_BCOUT(0),
BCOUT(1) => R1IN_3_2_ADD_1_BCOUT(1),
BCOUT(2) => R1IN_3_2_ADD_1_BCOUT(2),
BCOUT(3) => R1IN_3_2_ADD_1_BCOUT(3),
BCOUT(4) => R1IN_3_2_ADD_1_BCOUT(4),
BCOUT(5) => R1IN_3_2_ADD_1_BCOUT(5),
BCOUT(6) => R1IN_3_2_ADD_1_BCOUT(6),
BCOUT(7) => R1IN_3_2_ADD_1_BCOUT(7),
BCOUT(8) => R1IN_3_2_ADD_1_BCOUT(8),
BCOUT(9) => R1IN_3_2_ADD_1_BCOUT(9),
BCOUT(10) => R1IN_3_2_ADD_1_BCOUT(10),
BCOUT(11) => R1IN_3_2_ADD_1_BCOUT(11),
BCOUT(12) => R1IN_3_2_ADD_1_BCOUT(12),
BCOUT(13) => R1IN_3_2_ADD_1_BCOUT(13),
BCOUT(14) => R1IN_3_2_ADD_1_BCOUT(14),
BCOUT(15) => R1IN_3_2_ADD_1_BCOUT(15),
BCOUT(16) => R1IN_3_2_ADD_1_BCOUT(16),
BCOUT(17) => R1IN_3_2_ADD_1_BCOUT(17),
P(0) => R1IN_3_2F(17),
P(1) => R1IN_3_2F(18),
P(2) => R1IN_3_2F(19),
P(3) => R1IN_3_2F(20),
P(4) => R1IN_3_2F(21),
P(5) => R1IN_3_2F(22),
P(6) => R1IN_3_2F(23),
P(7) => R1IN_3_2F(24),
P(8) => R1IN_3_2F(25),
P(9) => R1IN_3_2F(26),
P(10) => R1IN_3_2F(27),
P(11) => R1IN_3_2F(28),
P(12) => R1IN_3_2F(29),
P(13) => R1IN_3_2F(30),
P(14) => R1IN_3_2F(31),
P(15) => R1IN_3_2F(32),
P(16) => R1IN_3_2F(33),
P(17) => R1IN_3_2F(34),
P(18) => R1IN_3_2F(35),
P(19) => R1IN_3_2F(36),
P(20) => R1IN_3_2F(37),
P(21) => R1IN_3_2F(38),
P(22) => R1IN_3_2F(39),
P(23) => R1IN_3_2F(40),
P(24) => R1IN_3_2F(41),
P(25) => R1IN_3_2F(42),
P(26) => R1IN_3_2F(43),
P(27) => UC_40,
P(28) => UC_41,
P(29) => UC_42,
P(30) => UC_43,
P(31) => UC_44,
P(32) => UC_45,
P(33) => UC_46,
P(34) => UC_47,
P(35) => UC_48,
P(36) => UC_49,
P(37) => UC_50,
P(38) => UC_51,
P(39) => UC_52,
P(40) => UC_53,
P(41) => UC_54,
P(42) => UC_55,
P(43) => UC_56,
P(44) => UC_57,
P(45) => UC_58,
P(46) => UC_59,
P(47) => UC_60,
PCOUT(0) => R1IN_3_2_ADD_1_PCOUT(0),
PCOUT(1) => R1IN_3_2_ADD_1_PCOUT(1),
PCOUT(2) => R1IN_3_2_ADD_1_PCOUT(2),
PCOUT(3) => R1IN_3_2_ADD_1_PCOUT(3),
PCOUT(4) => R1IN_3_2_ADD_1_PCOUT(4),
PCOUT(5) => R1IN_3_2_ADD_1_PCOUT(5),
PCOUT(6) => R1IN_3_2_ADD_1_PCOUT(6),
PCOUT(7) => R1IN_3_2_ADD_1_PCOUT(7),
PCOUT(8) => R1IN_3_2_ADD_1_PCOUT(8),
PCOUT(9) => R1IN_3_2_ADD_1_PCOUT(9),
PCOUT(10) => R1IN_3_2_ADD_1_PCOUT(10),
PCOUT(11) => R1IN_3_2_ADD_1_PCOUT(11),
PCOUT(12) => R1IN_3_2_ADD_1_PCOUT(12),
PCOUT(13) => R1IN_3_2_ADD_1_PCOUT(13),
PCOUT(14) => R1IN_3_2_ADD_1_PCOUT(14),
PCOUT(15) => R1IN_3_2_ADD_1_PCOUT(15),
PCOUT(16) => R1IN_3_2_ADD_1_PCOUT(16),
PCOUT(17) => R1IN_3_2_ADD_1_PCOUT(17),
PCOUT(18) => R1IN_3_2_ADD_1_PCOUT(18),
PCOUT(19) => R1IN_3_2_ADD_1_PCOUT(19),
PCOUT(20) => R1IN_3_2_ADD_1_PCOUT(20),
PCOUT(21) => R1IN_3_2_ADD_1_PCOUT(21),
PCOUT(22) => R1IN_3_2_ADD_1_PCOUT(22),
PCOUT(23) => R1IN_3_2_ADD_1_PCOUT(23),
PCOUT(24) => R1IN_3_2_ADD_1_PCOUT(24),
PCOUT(25) => R1IN_3_2_ADD_1_PCOUT(25),
PCOUT(26) => R1IN_3_2_ADD_1_PCOUT(26),
PCOUT(27) => R1IN_3_2_ADD_1_PCOUT(27),
PCOUT(28) => R1IN_3_2_ADD_1_PCOUT(28),
PCOUT(29) => R1IN_3_2_ADD_1_PCOUT(29),
PCOUT(30) => R1IN_3_2_ADD_1_PCOUT(30),
PCOUT(31) => R1IN_3_2_ADD_1_PCOUT(31),
PCOUT(32) => R1IN_3_2_ADD_1_PCOUT(32),
PCOUT(33) => R1IN_3_2_ADD_1_PCOUT(33),
PCOUT(34) => R1IN_3_2_ADD_1_PCOUT(34),
PCOUT(35) => R1IN_3_2_ADD_1_PCOUT(35),
PCOUT(36) => R1IN_3_2_ADD_1_PCOUT(36),
PCOUT(37) => R1IN_3_2_ADD_1_PCOUT(37),
PCOUT(38) => R1IN_3_2_ADD_1_PCOUT(38),
PCOUT(39) => R1IN_3_2_ADD_1_PCOUT(39),
PCOUT(40) => R1IN_3_2_ADD_1_PCOUT(40),
PCOUT(41) => R1IN_3_2_ADD_1_PCOUT(41),
PCOUT(42) => R1IN_3_2_ADD_1_PCOUT(42),
PCOUT(43) => R1IN_3_2_ADD_1_PCOUT(43),
PCOUT(44) => R1IN_3_2_ADD_1_PCOUT(44),
PCOUT(45) => R1IN_3_2_ADD_1_PCOUT(45),
PCOUT(46) => R1IN_3_2_ADD_1_PCOUT(46),
PCOUT(47) => R1IN_3_2_ADD_1_PCOUT(47));
\R1IN_2_2_ADD_1[26:0]\: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 1,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => A(51),
A(1) => A(52),
A(2) => A(53),
A(3) => A(54),
A(4) => A(55),
A(5) => A(56),
A(6) => A(57),
A(7) => A(58),
A(8) => A(59),
A(9) => A(60),
A(10) => NN_1,
A(11) => NN_1,
A(12) => NN_1,
A(13) => NN_1,
A(14) => NN_1,
A(15) => NN_1,
A(16) => NN_1,
A(17) => NN_1,
B(0) => B(0),
B(1) => B(1),
B(2) => B(2),
B(3) => B(3),
B(4) => B(4),
B(5) => B(5),
B(6) => B(6),
B(7) => B(7),
B(8) => B(8),
B(9) => B(9),
B(10) => B(10),
B(11) => B(11),
B(12) => B(12),
B(13) => B(13),
B(14) => B(14),
B(15) => B(15),
B(16) => B(16),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => R1IN_2_2_0(0),
PCIN(1) => R1IN_2_2_0(1),
PCIN(2) => R1IN_2_2_0(2),
PCIN(3) => R1IN_2_2_0(3),
PCIN(4) => R1IN_2_2_0(4),
PCIN(5) => R1IN_2_2_0(5),
PCIN(6) => R1IN_2_2_0(6),
PCIN(7) => R1IN_2_2_0(7),
PCIN(8) => R1IN_2_2_0(8),
PCIN(9) => R1IN_2_2_0(9),
PCIN(10) => R1IN_2_2_0(10),
PCIN(11) => R1IN_2_2_0(11),
PCIN(12) => R1IN_2_2_0(12),
PCIN(13) => R1IN_2_2_0(13),
PCIN(14) => R1IN_2_2_0(14),
PCIN(15) => R1IN_2_2_0(15),
PCIN(16) => R1IN_2_2_0(16),
PCIN(17) => R1IN_2_2_1_0(17),
PCIN(18) => R1IN_2_2_1_0(18),
PCIN(19) => R1IN_2_2_1_0(19),
PCIN(20) => R1IN_2_2_1_0(20),
PCIN(21) => R1IN_2_2_1_0(21),
PCIN(22) => R1IN_2_2_1_0(22),
PCIN(23) => R1IN_2_2_1_0(23),
PCIN(24) => R1IN_2_2_1_0(24),
PCIN(25) => R1IN_2_2_1_0(25),
PCIN(26) => R1IN_2_2_1_0(26),
PCIN(27) => R1IN_2_2_1_0(27),
PCIN(28) => R1IN_2_2_1_0(28),
PCIN(29) => R1IN_2_2_1_0(29),
PCIN(30) => R1IN_2_2_1_0(30),
PCIN(31) => R1IN_2_2_1_0(31),
PCIN(32) => R1IN_2_2_1_0(32),
PCIN(33) => R1IN_2_2_1_0(33),
PCIN(34) => UC_103_0,
PCIN(35) => UC_104_0,
PCIN(36) => UC_105_0,
PCIN(37) => UC_106_0,
PCIN(38) => UC_107_0,
PCIN(39) => UC_108_0,
PCIN(40) => UC_109_0,
PCIN(41) => UC_110_0,
PCIN(42) => UC_111_0,
PCIN(43) => UC_112_0,
PCIN(44) => UC_113_0,
PCIN(45) => UC_114_0,
PCIN(46) => UC_115_0,
PCIN(47) => UC_116_0,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_2,
OPMODE(5) => NN_1,
OPMODE(6) => NN_2,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => EN,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => B_0(0),
BCOUT(1) => B_0(1),
BCOUT(2) => B_0(2),
BCOUT(3) => B_0(3),
BCOUT(4) => B_0(4),
BCOUT(5) => B_0(5),
BCOUT(6) => B_0(6),
BCOUT(7) => B_0(7),
BCOUT(8) => B_0(8),
BCOUT(9) => B_0(9),
BCOUT(10) => B_0(10),
BCOUT(11) => B_0(11),
BCOUT(12) => B_0(12),
BCOUT(13) => B_0(13),
BCOUT(14) => B_0(14),
BCOUT(15) => B_0(15),
BCOUT(16) => B_0(16),
BCOUT(17) => GND_0,
P(0) => R1IN_2_2F(17),
P(1) => R1IN_2_2F(18),
P(2) => R1IN_2_2F(19),
P(3) => R1IN_2_2F(20),
P(4) => R1IN_2_2F(21),
P(5) => R1IN_2_2F(22),
P(6) => R1IN_2_2F(23),
P(7) => R1IN_2_2F(24),
P(8) => R1IN_2_2F(25),
P(9) => R1IN_2_2F(26),
P(10) => R1IN_2_2F(27),
P(11) => R1IN_2_2F(28),
P(12) => R1IN_2_2F(29),
P(13) => R1IN_2_2F(30),
P(14) => R1IN_2_2F(31),
P(15) => R1IN_2_2F(32),
P(16) => R1IN_2_2F(33),
P(17) => R1IN_2_2F(34),
P(18) => R1IN_2_2F(35),
P(19) => R1IN_2_2F(36),
P(20) => R1IN_2_2F(37),
P(21) => R1IN_2_2F(38),
P(22) => R1IN_2_2F(39),
P(23) => R1IN_2_2F(40),
P(24) => R1IN_2_2F(41),
P(25) => R1IN_2_2F(42),
P(26) => R1IN_2_2F(43),
P(27) => UC_19,
P(28) => UC_20,
P(29) => UC_21,
P(30) => UC_22,
P(31) => UC_23,
P(32) => UC_24,
P(33) => UC_25,
P(34) => UC_26,
P(35) => UC_27,
P(36) => UC_28,
P(37) => UC_29,
P(38) => UC_30,
P(39) => UC_31,
P(40) => UC_32,
P(41) => UC_33,
P(42) => UC_34,
P(43) => UC_35,
P(44) => UC_36,
P(45) => UC_37,
P(46) => UC_38,
P(47) => UC_39,
PCOUT(0) => R1IN_2_2_ADD_1_PCOUT(0),
PCOUT(1) => R1IN_2_2_ADD_1_PCOUT(1),
PCOUT(2) => R1IN_2_2_ADD_1_PCOUT(2),
PCOUT(3) => R1IN_2_2_ADD_1_PCOUT(3),
PCOUT(4) => R1IN_2_2_ADD_1_PCOUT(4),
PCOUT(5) => R1IN_2_2_ADD_1_PCOUT(5),
PCOUT(6) => R1IN_2_2_ADD_1_PCOUT(6),
PCOUT(7) => R1IN_2_2_ADD_1_PCOUT(7),
PCOUT(8) => R1IN_2_2_ADD_1_PCOUT(8),
PCOUT(9) => R1IN_2_2_ADD_1_PCOUT(9),
PCOUT(10) => R1IN_2_2_ADD_1_PCOUT(10),
PCOUT(11) => R1IN_2_2_ADD_1_PCOUT(11),
PCOUT(12) => R1IN_2_2_ADD_1_PCOUT(12),
PCOUT(13) => R1IN_2_2_ADD_1_PCOUT(13),
PCOUT(14) => R1IN_2_2_ADD_1_PCOUT(14),
PCOUT(15) => R1IN_2_2_ADD_1_PCOUT(15),
PCOUT(16) => R1IN_2_2_ADD_1_PCOUT(16),
PCOUT(17) => R1IN_2_2_ADD_1_PCOUT(17),
PCOUT(18) => R1IN_2_2_ADD_1_PCOUT(18),
PCOUT(19) => R1IN_2_2_ADD_1_PCOUT(19),
PCOUT(20) => R1IN_2_2_ADD_1_PCOUT(20),
PCOUT(21) => R1IN_2_2_ADD_1_PCOUT(21),
PCOUT(22) => R1IN_2_2_ADD_1_PCOUT(22),
PCOUT(23) => R1IN_2_2_ADD_1_PCOUT(23),
PCOUT(24) => R1IN_2_2_ADD_1_PCOUT(24),
PCOUT(25) => R1IN_2_2_ADD_1_PCOUT(25),
PCOUT(26) => R1IN_2_2_ADD_1_PCOUT(26),
PCOUT(27) => R1IN_2_2_ADD_1_PCOUT(27),
PCOUT(28) => R1IN_2_2_ADD_1_PCOUT(28),
PCOUT(29) => R1IN_2_2_ADD_1_PCOUT(29),
PCOUT(30) => R1IN_2_2_ADD_1_PCOUT(30),
PCOUT(31) => R1IN_2_2_ADD_1_PCOUT(31),
PCOUT(32) => R1IN_2_2_ADD_1_PCOUT(32),
PCOUT(33) => R1IN_2_2_ADD_1_PCOUT(33),
PCOUT(34) => R1IN_2_2_ADD_1_PCOUT(34),
PCOUT(35) => R1IN_2_2_ADD_1_PCOUT(35),
PCOUT(36) => R1IN_2_2_ADD_1_PCOUT(36),
PCOUT(37) => R1IN_2_2_ADD_1_PCOUT(37),
PCOUT(38) => R1IN_2_2_ADD_1_PCOUT(38),
PCOUT(39) => R1IN_2_2_ADD_1_PCOUT(39),
PCOUT(40) => R1IN_2_2_ADD_1_PCOUT(40),
PCOUT(41) => R1IN_2_2_ADD_1_PCOUT(41),
PCOUT(42) => R1IN_2_2_ADD_1_PCOUT(42),
PCOUT(43) => R1IN_2_2_ADD_1_PCOUT(43),
PCOUT(44) => R1IN_2_2_ADD_1_PCOUT(44),
PCOUT(45) => R1IN_2_2_ADD_1_PCOUT(45),
PCOUT(46) => R1IN_2_2_ADD_1_PCOUT(46),
PCOUT(47) => R1IN_2_2_ADD_1_PCOUT(47));
\R1IN_4_4_ADD_1[27:0]\: DSP48
generic map(
AREG => 0,
BREG => 0,
CREG => 0,
PREG => 1,
MREG => 0,
SUBTRACTREG => 0,
OPMODEREG => 0,
CARRYINSELREG => 0,
CARRYINREG => 0,
B_INPUT => "DIRECT",
LEGACY_MODE => "MULT18X18"
)
port map (
A(0) => B(51),
A(1) => B(52),
A(2) => B(53),
A(3) => B(54),
A(4) => B(55),
A(5) => B(56),
A(6) => B(57),
A(7) => B(58),
A(8) => B(59),
A(9) => B(60),
A(10) => NN_1,
A(11) => NN_1,
A(12) => NN_1,
A(13) => NN_1,
A(14) => NN_1,
A(15) => NN_1,
A(16) => NN_1,
A(17) => NN_1,
B(0) => A(34),
B(1) => A(35),
B(2) => A(36),
B(3) => A(37),
B(4) => A(38),
B(5) => A(39),
B(6) => A(40),
B(7) => A(41),
B(8) => A(42),
B(9) => A(43),
B(10) => A(44),
B(11) => A(45),
B(12) => A(46),
B(13) => A(47),
B(14) => A(48),
B(15) => A(49),
B(16) => A(50),
B(17) => NN_1,
C(0) => NN_1,
C(1) => NN_1,
C(2) => NN_1,
C(3) => NN_1,
C(4) => NN_1,
C(5) => NN_1,
C(6) => NN_1,
C(7) => NN_1,
C(8) => NN_1,
C(9) => NN_1,
C(10) => NN_1,
C(11) => NN_1,
C(12) => NN_1,
C(13) => NN_1,
C(14) => NN_1,
C(15) => NN_1,
C(16) => NN_1,
C(17) => NN_1,
C(18) => NN_1,
C(19) => NN_1,
C(20) => NN_1,
C(21) => NN_1,
C(22) => NN_1,
C(23) => NN_1,
C(24) => NN_1,
C(25) => NN_1,
C(26) => NN_1,
C(27) => NN_1,
C(28) => NN_1,
C(29) => NN_1,
C(30) => NN_1,
C(31) => NN_1,
C(32) => NN_1,
C(33) => NN_1,
C(34) => NN_1,
C(35) => NN_1,
C(36) => NN_1,
C(37) => NN_1,
C(38) => NN_1,
C(39) => NN_1,
C(40) => NN_1,
C(41) => NN_1,
C(42) => NN_1,
C(43) => NN_1,
C(44) => NN_1,
C(45) => NN_1,
C(46) => NN_1,
C(47) => NN_1,
BCIN(0) => NN_1,
BCIN(1) => NN_1,
BCIN(2) => NN_1,
BCIN(3) => NN_1,
BCIN(4) => NN_1,
BCIN(5) => NN_1,
BCIN(6) => NN_1,
BCIN(7) => NN_1,
BCIN(8) => NN_1,
BCIN(9) => NN_1,
BCIN(10) => NN_1,
BCIN(11) => NN_1,
BCIN(12) => NN_1,
BCIN(13) => NN_1,
BCIN(14) => NN_1,
BCIN(15) => NN_1,
BCIN(16) => NN_1,
BCIN(17) => NN_1,
PCIN(0) => R1IN_4_4_2_0(0),
PCIN(1) => R1IN_4_4_2_0(1),
PCIN(2) => R1IN_4_4_2_0(2),
PCIN(3) => R1IN_4_4_2_0(3),
PCIN(4) => R1IN_4_4_2_0(4),
PCIN(5) => R1IN_4_4_2_0(5),
PCIN(6) => R1IN_4_4_2_0(6),
PCIN(7) => R1IN_4_4_2_0(7),
PCIN(8) => R1IN_4_4_2_0(8),
PCIN(9) => R1IN_4_4_2_0(9),
PCIN(10) => R1IN_4_4_2_0(10),
PCIN(11) => R1IN_4_4_2_0(11),
PCIN(12) => R1IN_4_4_2_0(12),
PCIN(13) => R1IN_4_4_2_0(13),
PCIN(14) => R1IN_4_4_2_0(14),
PCIN(15) => R1IN_4_4_2_0(15),
PCIN(16) => R1IN_4_4_2_0(16),
PCIN(17) => R1IN_4_4_2_0(17),
PCIN(18) => R1IN_4_4_2_0(18),
PCIN(19) => R1IN_4_4_2_0(19),
PCIN(20) => R1IN_4_4_2_0(20),
PCIN(21) => R1IN_4_4_2_0(21),
PCIN(22) => R1IN_4_4_2_0(22),
PCIN(23) => R1IN_4_4_2_0(23),
PCIN(24) => R1IN_4_4_2_0(24),
PCIN(25) => R1IN_4_4_2_0(25),
PCIN(26) => R1IN_4_4_2_0(26),
PCIN(27) => UC_229_0,
PCIN(28) => UC_230_0,
PCIN(29) => UC_231_0,
PCIN(30) => UC_232_0,
PCIN(31) => UC_233_0,
PCIN(32) => UC_234_0,
PCIN(33) => UC_235_0,
PCIN(34) => UC_236_0,
PCIN(35) => UC_237_0,
PCIN(36) => UC_238_0,
PCIN(37) => UC_239_0,
PCIN(38) => UC_240_0,
PCIN(39) => UC_241_0,
PCIN(40) => UC_242_0,
PCIN(41) => UC_243_0,
PCIN(42) => UC_244_0,
PCIN(43) => UC_245_0,
PCIN(44) => UC_246_0,
PCIN(45) => UC_247_0,
PCIN(46) => UC_248_0,
PCIN(47) => UC_249_0,
OPMODE(0) => NN_2,
OPMODE(1) => NN_1,
OPMODE(2) => NN_2,
OPMODE(3) => NN_1,
OPMODE(4) => NN_2,
OPMODE(5) => NN_1,
OPMODE(6) => NN_1,
SUBTRACT => NN_1,
CARRYIN => NN_1,
CARRYINSEL(0) => NN_1,
CARRYINSEL(1) => NN_1,
CLK => CLK,
CEA => NN_1,
CEB => NN_1,
CEC => NN_1,
CEP => EN,
CEM => NN_1,
CECARRYIN => NN_1,
CECTRL => NN_1,
CECINSUB => NN_1,
RSTA => NN_1,
RSTB => NN_1,
RSTC => NN_1,
RSTP => NN_1,
RSTM => NN_1,
RSTCTRL => NN_1,
RSTCARRYIN => NN_1,
BCOUT(0) => R1IN_4_4_ADD_1_BCOUT(0),
BCOUT(1) => R1IN_4_4_ADD_1_BCOUT(1),
BCOUT(2) => R1IN_4_4_ADD_1_BCOUT(2),
BCOUT(3) => R1IN_4_4_ADD_1_BCOUT(3),
BCOUT(4) => R1IN_4_4_ADD_1_BCOUT(4),
BCOUT(5) => R1IN_4_4_ADD_1_BCOUT(5),
BCOUT(6) => R1IN_4_4_ADD_1_BCOUT(6),
BCOUT(7) => R1IN_4_4_ADD_1_BCOUT(7),
BCOUT(8) => R1IN_4_4_ADD_1_BCOUT(8),
BCOUT(9) => R1IN_4_4_ADD_1_BCOUT(9),
BCOUT(10) => R1IN_4_4_ADD_1_BCOUT(10),
BCOUT(11) => R1IN_4_4_ADD_1_BCOUT(11),
BCOUT(12) => R1IN_4_4_ADD_1_BCOUT(12),
BCOUT(13) => R1IN_4_4_ADD_1_BCOUT(13),
BCOUT(14) => R1IN_4_4_ADD_1_BCOUT(14),
BCOUT(15) => R1IN_4_4_ADD_1_BCOUT(15),
BCOUT(16) => R1IN_4_4_ADD_1_BCOUT(16),
BCOUT(17) => R1IN_4_4_ADD_1_BCOUT(17),
P(0) => R1IN_4_4_ADD_1F(0),
P(1) => R1IN_4_4_ADD_1F(1),
P(2) => R1IN_4_4_ADD_1F(2),
P(3) => R1IN_4_4_ADD_1F(3),
P(4) => R1IN_4_4_ADD_1F(4),
P(5) => R1IN_4_4_ADD_1F(5),
P(6) => R1IN_4_4_ADD_1F(6),
P(7) => R1IN_4_4_ADD_1F(7),
P(8) => R1IN_4_4_ADD_1F(8),
P(9) => R1IN_4_4_ADD_1F(9),
P(10) => R1IN_4_4_ADD_1F(10),
P(11) => R1IN_4_4_ADD_1F(11),
P(12) => R1IN_4_4_ADD_1F(12),
P(13) => R1IN_4_4_ADD_1F(13),
P(14) => R1IN_4_4_ADD_1F(14),
P(15) => R1IN_4_4_ADD_1F(15),
P(16) => R1IN_4_4_ADD_1F(16),
P(17) => R1IN_4_4_ADD_1F(17),
P(18) => R1IN_4_4_ADD_1F(18),
P(19) => R1IN_4_4_ADD_1F(19),
P(20) => R1IN_4_4_ADD_1F(20),
P(21) => R1IN_4_4_ADD_1F(21),
P(22) => R1IN_4_4_ADD_1F(22),
P(23) => R1IN_4_4_ADD_1F(23),
P(24) => R1IN_4_4_ADD_1F(24),
P(25) => R1IN_4_4_ADD_1F(25),
P(26) => R1IN_4_4_ADD_1F(26),
P(27) => R1IN_4_4_ADD_1F(27),
P(28) => UC,
P(29) => UC_0,
P(30) => UC_1,
P(31) => UC_2,
P(32) => UC_3,
P(33) => UC_4,
P(34) => UC_5,
P(35) => UC_6,
P(36) => UC_7,
P(37) => UC_8,
P(38) => UC_9,
P(39) => UC_10,
P(40) => UC_11,
P(41) => UC_12,
P(42) => UC_13,
P(43) => UC_14,
P(44) => UC_15,
P(45) => UC_16,
P(46) => UC_17,
P(47) => UC_18,
PCOUT(0) => R1IN_4_4_ADD_1_PCOUT(0),
PCOUT(1) => R1IN_4_4_ADD_1_PCOUT(1),
PCOUT(2) => R1IN_4_4_ADD_1_PCOUT(2),
PCOUT(3) => R1IN_4_4_ADD_1_PCOUT(3),
PCOUT(4) => R1IN_4_4_ADD_1_PCOUT(4),
PCOUT(5) => R1IN_4_4_ADD_1_PCOUT(5),
PCOUT(6) => R1IN_4_4_ADD_1_PCOUT(6),
PCOUT(7) => R1IN_4_4_ADD_1_PCOUT(7),
PCOUT(8) => R1IN_4_4_ADD_1_PCOUT(8),
PCOUT(9) => R1IN_4_4_ADD_1_PCOUT(9),
PCOUT(10) => R1IN_4_4_ADD_1_PCOUT(10),
PCOUT(11) => R1IN_4_4_ADD_1_PCOUT(11),
PCOUT(12) => R1IN_4_4_ADD_1_PCOUT(12),
PCOUT(13) => R1IN_4_4_ADD_1_PCOUT(13),
PCOUT(14) => R1IN_4_4_ADD_1_PCOUT(14),
PCOUT(15) => R1IN_4_4_ADD_1_PCOUT(15),
PCOUT(16) => R1IN_4_4_ADD_1_PCOUT(16),
PCOUT(17) => R1IN_4_4_ADD_1_PCOUT(17),
PCOUT(18) => R1IN_4_4_ADD_1_PCOUT(18),
PCOUT(19) => R1IN_4_4_ADD_1_PCOUT(19),
PCOUT(20) => R1IN_4_4_ADD_1_PCOUT(20),
PCOUT(21) => R1IN_4_4_ADD_1_PCOUT(21),
PCOUT(22) => R1IN_4_4_ADD_1_PCOUT(22),
PCOUT(23) => R1IN_4_4_ADD_1_PCOUT(23),
PCOUT(24) => R1IN_4_4_ADD_1_PCOUT(24),
PCOUT(25) => R1IN_4_4_ADD_1_PCOUT(25),
PCOUT(26) => R1IN_4_4_ADD_1_PCOUT(26),
PCOUT(27) => R1IN_4_4_ADD_1_PCOUT(27),
PCOUT(28) => R1IN_4_4_ADD_1_PCOUT(28),
PCOUT(29) => R1IN_4_4_ADD_1_PCOUT(29),
PCOUT(30) => R1IN_4_4_ADD_1_PCOUT(30),
PCOUT(31) => R1IN_4_4_ADD_1_PCOUT(31),
PCOUT(32) => R1IN_4_4_ADD_1_PCOUT(32),
PCOUT(33) => R1IN_4_4_ADD_1_PCOUT(33),
PCOUT(34) => R1IN_4_4_ADD_1_PCOUT(34),
PCOUT(35) => R1IN_4_4_ADD_1_PCOUT(35),
PCOUT(36) => R1IN_4_4_ADD_1_PCOUT(36),
PCOUT(37) => R1IN_4_4_ADD_1_PCOUT(37),
PCOUT(38) => R1IN_4_4_ADD_1_PCOUT(38),
PCOUT(39) => R1IN_4_4_ADD_1_PCOUT(39),
PCOUT(40) => R1IN_4_4_ADD_1_PCOUT(40),
PCOUT(41) => R1IN_4_4_ADD_1_PCOUT(41),
PCOUT(42) => R1IN_4_4_ADD_1_PCOUT(42),
PCOUT(43) => R1IN_4_4_ADD_1_PCOUT(43),
PCOUT(44) => R1IN_4_4_ADD_1_PCOUT(44),
PCOUT(45) => R1IN_4_4_ADD_1_PCOUT(45),
PCOUT(46) => R1IN_4_4_ADD_1_PCOUT(46),
PCOUT(47) => R1IN_4_4_ADD_1_PCOUT(47));
II_GND: GND port map (
G => NN_1);
II_VCC: VCC port map (
P => NN_2);
PRODUCT(17) <= NN_11;
end beh;
|
gpl-2.0
|
2207bd4ae33a63c7e607fe0589b7183f
| 0.541659 | 1.940292 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-ztex-ufm-115/ahbrom.vhd
| 6 | 8,224 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 496;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800001";
when 16#00064# => romdata <= X"05000080";
when 16#00065# => romdata <= X"82100000";
when 16#00066# => romdata <= X"80A0E000";
when 16#00067# => romdata <= X"02800005";
when 16#00068# => romdata <= X"01000000";
when 16#00069# => romdata <= X"82004002";
when 16#0006A# => romdata <= X"10BFFFFC";
when 16#0006B# => romdata <= X"8620E001";
when 16#0006C# => romdata <= X"3D1003FF";
when 16#0006D# => romdata <= X"BC17A3E0";
when 16#0006E# => romdata <= X"BC278001";
when 16#0006F# => romdata <= X"9C27A060";
when 16#00070# => romdata <= X"03100000";
when 16#00071# => romdata <= X"81C04000";
when 16#00072# => romdata <= X"01000000";
when 16#00073# => romdata <= X"01000000";
when 16#00074# => romdata <= X"01000000";
when 16#00075# => romdata <= X"01000000";
when 16#00076# => romdata <= X"01000000";
when 16#00077# => romdata <= X"01000000";
when 16#00078# => romdata <= X"00000000";
when 16#00079# => romdata <= X"00000000";
when 16#0007A# => romdata <= X"00000000";
when 16#0007B# => romdata <= X"00000000";
when 16#0007C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
gpl-2.0
|
1a8ffc663961590753f871054f2643ae
| 0.580253 | 3.309457 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/greth/ethernet_mac.vhd
| 1 | 5,146 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.net.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package ethernet_mac is
type eth_tx_in_type is record
start : std_ulogic;
valid : std_ulogic;
data : std_logic_vector(31 downto 0);
full_duplex : std_ulogic;
length : std_logic_vector(10 downto 0);
col : std_ulogic;
crs : std_ulogic;
read_ack : std_ulogic;
end record;
type eth_tx_out_type is record
status : std_logic_vector(1 downto 0);
done : std_ulogic;
restart : std_ulogic;
read : std_ulogic;
tx_er : std_ulogic;
tx_en : std_ulogic;
txd : std_logic_vector(3 downto 0);
end record;
type eth_rx_in_type is record
writeok : std_ulogic;
rxen : std_ulogic;
rx_dv : std_ulogic;
rx_er : std_ulogic;
rxd : std_logic_vector(3 downto 0);
done_ack : std_ulogic;
write_ack : std_ulogic;
end record;
type eth_rx_out_type is record
write : std_ulogic;
data : std_logic_vector(31 downto 0);
done : std_ulogic;
length : std_logic_vector(10 downto 0);
status : std_logic_vector(2 downto 0);
start : std_ulogic;
end record;
type eth_mdio_in_type is record
mdioi : std_ulogic;
write : std_ulogic;
read : std_ulogic;
mdiostart : std_ulogic;
regadr : std_logic_vector(4 downto 0);
phyadr : std_logic_vector(4 downto 0);
data : std_logic_vector(15 downto 0);
end record;
type eth_mdio_out_type is record
mdc : std_ulogic;
mdioo : std_ulogic;
mdioen : std_ulogic;
data : std_logic_vector(15 downto 0);
done : std_ulogic;
error : std_ulogic;
end record;
type eth_tx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_tx_ahb_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_rx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_gbit_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
component eth_ahb_mst is
generic(
hindex : integer := 0;
revision : integer := 0;
irq : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component eth_ahb_mst_gbit is
generic(
hindex : integer := 0;
revision : integer := 0;
irq : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_gbit_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
end package;
|
gpl-2.0
|
b5e4db1ccc0b82174087145cf7781ee6
| 0.55616 | 3.571131 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/usb/grusbdc.in.vhd
| 3 | 2,416 |
-- GR USB 2.0 Device Controller
constant CFG_GRUSBDC : integer := CONFIG_GRUSBDC_ENABLE;
constant CFG_GRUSBDC_AIFACE : integer := CONFIG_GRUSBDC_AIFACE;
constant CFG_GRUSBDC_UIFACE : integer := CONFIG_GRUSBDC_UIFACE;
constant CFG_GRUSBDC_DW : integer := CONFIG_GRUSBDC_DW;
constant CFG_GRUSBDC_NEPI : integer := CONFIG_GRUSBDC_NEPI;
constant CFG_GRUSBDC_NEPO : integer := CONFIG_GRUSBDC_NEPO;
constant CFG_GRUSBDC_I0 : integer := CONFIG_GRUSBDC_I0;
constant CFG_GRUSBDC_I1 : integer := CONFIG_GRUSBDC_I1;
constant CFG_GRUSBDC_I2 : integer := CONFIG_GRUSBDC_I2;
constant CFG_GRUSBDC_I3 : integer := CONFIG_GRUSBDC_I3;
constant CFG_GRUSBDC_I4 : integer := CONFIG_GRUSBDC_I4;
constant CFG_GRUSBDC_I5 : integer := CONFIG_GRUSBDC_I5;
constant CFG_GRUSBDC_I6 : integer := CONFIG_GRUSBDC_I6;
constant CFG_GRUSBDC_I7 : integer := CONFIG_GRUSBDC_I7;
constant CFG_GRUSBDC_I8 : integer := CONFIG_GRUSBDC_I8;
constant CFG_GRUSBDC_I9 : integer := CONFIG_GRUSBDC_I9;
constant CFG_GRUSBDC_I10 : integer := CONFIG_GRUSBDC_I10;
constant CFG_GRUSBDC_I11 : integer := CONFIG_GRUSBDC_I11;
constant CFG_GRUSBDC_I12 : integer := CONFIG_GRUSBDC_I12;
constant CFG_GRUSBDC_I13 : integer := CONFIG_GRUSBDC_I13;
constant CFG_GRUSBDC_I14 : integer := CONFIG_GRUSBDC_I14;
constant CFG_GRUSBDC_I15 : integer := CONFIG_GRUSBDC_I15;
constant CFG_GRUSBDC_O0 : integer := CONFIG_GRUSBDC_O0;
constant CFG_GRUSBDC_O1 : integer := CONFIG_GRUSBDC_O1;
constant CFG_GRUSBDC_O2 : integer := CONFIG_GRUSBDC_O2;
constant CFG_GRUSBDC_O3 : integer := CONFIG_GRUSBDC_O3;
constant CFG_GRUSBDC_O4 : integer := CONFIG_GRUSBDC_O4;
constant CFG_GRUSBDC_O5 : integer := CONFIG_GRUSBDC_O5;
constant CFG_GRUSBDC_O6 : integer := CONFIG_GRUSBDC_O6;
constant CFG_GRUSBDC_O7 : integer := CONFIG_GRUSBDC_O7;
constant CFG_GRUSBDC_O8 : integer := CONFIG_GRUSBDC_O8;
constant CFG_GRUSBDC_O9 : integer := CONFIG_GRUSBDC_O9;
constant CFG_GRUSBDC_O10 : integer := CONFIG_GRUSBDC_O10;
constant CFG_GRUSBDC_O11 : integer := CONFIG_GRUSBDC_O11;
constant CFG_GRUSBDC_O12 : integer := CONFIG_GRUSBDC_O12;
constant CFG_GRUSBDC_O13 : integer := CONFIG_GRUSBDC_O13;
constant CFG_GRUSBDC_O14 : integer := CONFIG_GRUSBDC_O14;
constant CFG_GRUSBDC_O15 : integer := CONFIG_GRUSBDC_O15;
|
gpl-2.0
|
b204a0e717ef679fc9a2fcac6dbab0f8
| 0.690811 | 3.379021 | false | true | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-xup/leon3mp.vhd
| 1 | 23,418 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
sysace_clk : in std_ulogic;
errorn : out std_ulogic;
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb : in std_logic;
ddr_clk_fb_out : out std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
rxd : in std_ulogic;
txd : out std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- gpio : inout std_logic_vector(31 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
eresetn : out std_ulogic;
etx_slew : out std_logic_vector(1 downto 0);
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
cf_mpa : out std_logic_vector(6 downto 0);
cf_mpd : inout std_logic_vector(15 downto 0);
cf_mp_ce_z : out std_ulogic;
cf_mp_oe_z : out std_ulogic;
cf_mp_we_z : out std_ulogic;
cf_mpirq : in std_ulogic
);
end;
architecture rtl of leon3mp is
signal gpio : std_logic_vector(31 downto 0); -- I/O port
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, ddrlock : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal duart, rserrx, rsertx, rdsuen, ldsuen : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
signal ldsubre, lresetn, lock, clkml, clk1x : std_ulogic;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 1;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of ddrlock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of ddrlock : signal is true;
attribute syn_preserve of ddrlock : signal is true;
signal stati : ahbstat_in_type;
signal dac_clk,video_clk, clkvga : std_logic; -- Signals to vgaclock.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
attribute keep of clkvga : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
lock <= ddrlock and cgo.clklock;
sysace_clk_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sysace_clk, clkace);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, pciclk, clkm, open, open, open, pciclk, cgi, cgo, open, clk1x);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, lresetn);
rst0 : rstgen -- reset generator
port map (lresetn, clkm, lock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, ldsubre);
dsui.break <= not ldsubre;
ndsuact <= not dsuo.active;
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 4)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= rxd when dsuen = '1' else '1';
end generate;
led_rx <= rxd;
led_tx <= duo.txd when dsuen = '1' else u1o.txd;
txd <= duo.txd when dsuen = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- DDR RAM
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddr0 : ddrspa generic map (
fabtech => fabtech, memtech => 0, ddrbits => 64,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000,
rskew => CFG_DDRSP_RSKEW )
port map (lresetn, rstn, clk1x, clkm, ddrlock, clkml, clkml,
ahbsi, ahbso(3),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq);
end generate;
noddr : if (CFG_DDRSP = 0) generate ddrlock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd; u1i.ctsn <= '0'; u1i.extclk <= '0'; --txd1 <= u1o.txd;
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 7, paddr => 7, pirq => 4)
port map(rstn, clkm, apbi, apbo(7), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkm, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkm);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, clk0 => 40000,
clk1 => 20000, clk2 => CFG_CLKDIV*10000/CFG_CLKMUL, burstlen => 5)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, virtex2) port map (video_clk, clkvga);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkvga);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vga_pads : if (CFG_VGA_ENABLE /= 0 or CFG_SVGA_ENABLE /=0) generate
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
end generate;
-- gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
-- grgpio0: grgpio
-- generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
-- nbits => CFG_GRGPIO_WIDTH)
-- port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
--
-- pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
-- pio_pad : iopad generic map (tech => padtech)
-- port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
-- end generate;
-- end generate;
-- ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
-- ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
-- nftslv => CFG_AHBSTATN)
-- port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
-- end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), apbi => apbi,
apbo => apbo(11), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
etx_slew <= "00";
eresetn <= rstn;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 5, hirq => 6,
haddr => 16#003#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(5), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL = 0 generate
aceo.addr <= (others => '0'); aceo.cen <= '1'; aceo.do <= (others => '0');
aceo.doen <= '1'; aceo.oen <= '1'; aceo.wen <= '0';
end generate nograce;
cf_mpa_pads : outpadv generic map
(width => 7, tech => padtech, level => cmos, voltage => x25v)
port map (cf_mpa, aceo.addr);
cf_mp_ce_z_pad : outpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mp_ce_z, aceo.cen);
cf_mpd_pads : iopadv generic map
(tech => padtech, width => 16, level => cmos, voltage => x25v)
port map (cf_mpd, aceo.do, aceo.doen, acei.di);
cf_mp_oe_z_pad : outpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mp_oe_z, aceo.oen);
cf_mp_we_z_pad : outpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mp_we_z, aceo.wen);
cf_mpirq_pad : inpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mpirq, acei.irq);
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(0));
end generate;
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Debug ----------------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1));
-- pragma translate_on
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Digilent Virtex2-Pro XUP Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
82cba0000bad1290fb674e41ce67c0ab
| 0.556879 | 3.571995 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/outpad_ddr.vhd
| 1 | 3,802 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: outpad_ddr, outpad_ddrv
-- File: outpad_ddr.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Wrapper that instantiates a DDR register connected to an
-- output pad. The generic tech wrappers are not used for nextreme
-- since this technology requires that the output enable signal is
-- connected between the DDR register and the pad.
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allddr.all;
use techmap.allpads.all;
entity outpad_ddr is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := x33v;
strength : integer := 12
);
port (
pad : out std_ulogic;
i1, i2 : in std_ulogic;
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic
);
end;
architecture rtl of outpad_ddr is
signal q, oe, vcc : std_ulogic;
begin
vcc <= '1';
def: if (tech /= easic90) and (tech /= easic45) generate
ddrreg : ddr_oreg generic map (tech)
port map (q, c1, c2, ce, i1, i2, r, s);
p : outpad generic map (tech, level, slew, voltage, strength)
port map (pad, q);
oe <= '0';
end generate def;
nex : if (tech = easic90) generate
ddrreg : nextreme_oddr_reg
port map (ck => c1, dh => i1, dl => i2, doe => vcc, q => q, oe => oe, rstb => r);
p : nextreme_toutpad generic map (level, slew, voltage, strength)
port map(pad, q, oe);
end generate;
n2x : if (tech = easic45) generate
-- ddrpad : n2x_outpad_ddr generic map (level, slew, voltage, strength)
-- port map ();
--pragma translate_off
assert false report "outpad_ddr: Not yet supported on Nextreme2"
severity failure;
--pragma translate_on
q <= '0'; oe <= '0';
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity outpad_ddrv is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := 0;
strength : integer := 12;
width : integer := 1
);
port (
pad : out std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic
);
end;
architecture rtl of outpad_ddrv is
begin
v : for j in width-1 downto 0 generate
x0 : outpad_ddr generic map (tech, level, slew, voltage, strength)
port map (pad(j), i1(j), i2(j), c1, c2, ce, r, s);
end generate;
end;
|
gpl-2.0
|
ca1d318eb48ab5f60b3cffe303a96698
| 0.59495 | 3.631328 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/sdram_phy.vhd
| 1 | 7,939 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdram_phy
-- File: sdram_phy.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: SDRAM PHY with tech mapping, includes pads and can be
-- implemented with registers on all signals.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allpads.all;
entity sdram_phy is
generic (
tech : integer := spartan3;
oepol : integer := 0;
level : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
aw : integer := 15; -- # address bits
dw : integer := 32; -- # data bits
ncs : integer := 2;
reg : integer := 0); -- 1: include registers on all signals
port (
-- SDRAM interface
addr : out std_logic_vector(aw-1 downto 0);
dq : inout std_logic_vector(dw-1 downto 0);
cke : out std_logic_vector(ncs-1 downto 0);
sn : out std_logic_vector(ncs-1 downto 0);
wen : out std_ulogic;
rasn : out std_ulogic;
casn : out std_ulogic;
dqm : out std_logic_vector(dw/8-1 downto 0);
-- Interface toward memory controller
laddr : in std_logic_vector(aw-1 downto 0);
ldq_din : out std_logic_vector(dw-1 downto 0);
ldq_dout : in std_logic_vector(dw-1 downto 0);
ldq_oen : in std_logic_vector(dw-1 downto 0);
lcke : in std_logic_vector(ncs-1 downto 0);
lsn : in std_logic_vector(ncs-1 downto 0);
lwen : in std_ulogic;
lrasn : in std_ulogic;
lcasn : in std_ulogic;
ldqm : in std_logic_vector(dw/8-1 downto 0);
-- Only used when reg generic is non-zero
rstn : in std_ulogic; -- Registered pads reset
clk : in std_ulogic; -- SDRAM clock for registered pads
-- Optional pad configuration inputs
cfgi_cmd : in std_logic_vector(19 downto 0) := "00000000000000000000"; -- CMD pads
cfgi_dq : in std_logic_vector(19 downto 0) := "00000000000000000000" -- DQ pads
);
end;
architecture rtl of sdram_phy is
signal laddrx : std_logic_vector(aw-1 downto 0);
signal ldq_dinx : std_logic_vector(dw-1 downto 0);
signal ldq_doutx : std_logic_vector(dw-1 downto 0);
signal ldq_oenx : std_logic_vector(dw-1 downto 0);
signal lckex : std_logic_vector(ncs-1 downto 0);
signal lsnx : std_logic_vector(ncs-1 downto 0);
signal lwenx : std_ulogic;
signal lrasnx : std_ulogic;
signal lcasnx : std_ulogic;
signal ldqmx : std_logic_vector(dw/8-1 downto 0);
signal oen : std_ulogic;
signal voen : std_logic_vector(dw-1 downto 0);
-- Determines if there is a customized phy available for target tech,
-- otherwise a generic PHY will be built
constant has_sdram_phy : tech_ability_type :=
(easic45 => 1, others => 0);
-- Determines if target tech has pads with built in registers (or rather if
-- target technology requires special pad instantiations in order to get
-- registers into pad ring).
constant tech_has_padregs : tech_ability_type :=
(easic45 => 1, others => 0);
begin
oen <= not ldq_oen(0) when padoen_polarity(tech) /= oepol else ldq_oen(0);
voen <= not ldq_oen when padoen_polarity(tech) /= oepol else ldq_oen;
nopadregs : if (reg = 0) or (tech_has_padregs(tech) /= 0) generate
laddrx <= laddr;
ldq_din <= ldq_dinx;
ldq_doutx <= ldq_dout;
ldq_oenx <= voen;
lckex <= lcke;
lsnx <= lsn;
lwenx <= lwen;
lrasnx <= lrasn;
lcasnx <= lcasn;
ldqmx <= ldqm;
end generate;
padregs : if (reg /= 0) and (tech_has_padregs(tech) = 0) generate
regproc : process(clk, rstn)
begin
if rising_edge(clk) then
laddrx <= laddr;
ldq_din <= ldq_dinx;
ldq_doutx <= ldq_dout;
ldq_oenx <= (others => oen);
lckex <= lcke;
lsnx <= lsn;
lwenx <= lwen;
lrasnx <= lrasn;
lcasnx <= lcasn;
ldqmx <= ldqm;
end if;
if rstn = '0' then
lsnx <= (others => '1');
for i in ldq_oenx'range loop
ldq_oenx(i) <= conv_std_logic(padoen_polarity(tech) = 0);
end loop;
end if;
end process;
end generate;
gen : if has_sdram_phy(tech) = 0 generate
-- SDRAM address
sa_pad : outpadv
generic map (
width => aw,
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (addr, laddrx, cfgi_cmd);
-- SDRAM data
sd_pad : iopadvv
generic map (
width => dw,
tech => tech,
level => level,
voltage => voltage,
strength => strength,
oepol => padoen_polarity(tech))
port map (dq, ldq_doutx, ldq_oenx, ldq_dinx, cfgi_dq);
-- SDRAM clock enable
sdcke_pad : outpadv
generic map (
width => ncs,
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (cke, lckex, cfgi_cmd);
-- SDRAM write enable
sdwen_pad : outpad generic map (
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (wen, lwenx, cfgi_cmd);
-- SDRAM chip select
sdcsn_pad : outpadv
generic map (
width => ncs,
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (sn, lsnx, cfgi_cmd);
-- SDRAM ras
sdras_pad : outpad
generic map (
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (rasn, lrasnx, cfgi_cmd);
-- SDRAM cas
sdcas_pad : outpad
generic map (
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (casn, lcasnx, cfgi_cmd);
-- SDRAM dqm
sddqm_pad : outpadv
generic map (
width => dw/8,
level => level,
voltage => voltage,
tech => tech,
strength => strength)
port map (dqm, ldqmx, cfgi_cmd);
end generate;
n2x : if (tech = easic45) generate
phy0 : n2x_sdram_phy
generic map (
level => level, voltage => voltage, strength => strength,
aw => aw, dw => dw, ncs => ncs, reg => reg)
port map (
addr, dq, cke, sn, wen, rasn, casn, dqm,
laddrx, ldq_dinx, ldq_doutx, ldq_oenx, lckex,
lsnx, lwenx, lrasnx, lcasnx, ldqmx,
rstn, clk,
cfgi_cmd, cfgi_dq);
end generate;
end;
|
gpl-2.0
|
80c3f18d064c464b11c6abc73bd671f5
| 0.555612 | 3.694276 | false | false | false | false |
ECE492W2014G4/G4Capstone
|
tuner.vhd
| 1 | 1,602 |
-- Design unit: distortion_component
-- Authors : Aaron Arnason, Byron Maroney, Edrick De Guzman
-- tuner.vhd (not working)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tuner is
port(
clk: in std_logic;
reset: in std_logic;
tuner_en: in std_logic;
tuner_in: in std_logic;
tuner_data: in std_logic_vector(15 downto 0);
tuner_data_available: in std_logic;
tuner_out: out std_logic_vector(31 downto 0)
);
end entity tuner;
architecture behavior of tuner is
constant magTol,slopeTol: signed(31 downto 0) := X"00000014";
constant maxCount: unsigned(31 downto 0) := X"000093F7";
signal previous, max: std_logic_vector(15 downto 0) := X"0000";
signal counter, final_count : unsigned(31 downto 0) :=X"00000000";
signal max_slope : signed(15 downto 0);
begin
zcrd:process(clk, reset, tuner_en)
begin
if reset = '0' then
tuner_out <=X"00000000";
elsif rising_edge(clk) then
previous <= tuner_data;
if tuner_data(15 downto 0) > max(15 downto 0) then
max <= tuner_data;
max_slope <= signed(tuner_data) - signed(previous);
counter <= X"00000000";
elsif (abs(signed(max) - signed(tuner_data)) < magTol) and (abs(max_slope + signed(previous) - signed(tuner_data)) < slopeTol) then
tuner_out <= std_logic_vector(counter);
counter <= X"00000000";
elsif counter > maxCount or tuner_en = '0' then
max <= X"0000";
counter <= X"00000000";
else
if tuner_data_available = '1' then
counter <= counter +1;
end if;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
e6844bbc9d24cf22e65c844fa68e9ff5
| 0.661049 | 3.016949 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-terasic-de2-115/testbench.vhd
| 1 | 10,445 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romdepth : integer := 20; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal sma_clkout : std_ulogic;
signal address : std_logic_vector(22 downto 0);
signal data : std_logic_vector(31 downto 24);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic;
signal iosn : std_logic;
signal oen : std_logic;
signal read : std_logic;
signal writen : std_logic;
signal brdyn : std_logic;
signal bexcn : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal test : std_logic;
signal error : std_logic;
signal gpio : std_logic_vector(35 downto 0);
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
signal clk2 : std_logic := '1';
signal sdcke : std_logic;
signal sdcsn : std_logic;
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal txd1, rxd1 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col : std_logic := '0';
signal eth_gtxclk, erx_crs, etx_en, etx_er : std_logic :='0';
signal eth_macclk : std_logic := '0';
signal erxd, etxd : std_logic_vector(7 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal emdintn : std_logic := '1';
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
signal can_txd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_rxd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_stb : std_logic_vector(0 to CFG_CAN_NUM-1);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1';
dsubre <= '1'; -- inverted on the board
rxd1 <= '1';
can_rxd <= (others => 'H'); bexcn <= '1';
gpio(2 downto 0) <= "LHL";
gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H');
eth_macclk <= not eth_macclk after 4 ns;
ereset <= 'H';
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (rst, clk, sma_clkout, error, address(22 downto 0), data,
sa(12 downto 0), sa(14 downto 13), sd, sdclk, sdcke, sdcsn, sdwen,
sdrasn, sdcasn, sddqm, dsutx, dsurx, dsubre, dsuact,
oen, writen, open, open, romsn, gpio,
emdio, eth_macclk, etx_clk, erx_clk, erxd(3 downto 0), erx_dv, erx_er,
erx_col, erx_crs, emdintn, ereset, etxd(3 downto 0), etx_en, etx_er, emdc,
can_txd, can_rxd, can_stb
);
sd1 : if ((CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1)) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
writen, oen);
-- sram0 : for i in 0 to (sramwidth/8)-1 generate
-- sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
-- port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
-- rwen(0), ramoen(0));
-- end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map(address => 16)
port map(ereset, emdio, etx_clk, erx_clk, erxd, erx_dv,
erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, eth_macclk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
-- test0 : grtestmod
-- port map ( rst, clk, error, address(21 downto 2), data,
-- iosn, oen, writen, brdyn);
-- data <= buskeep(data), (others => 'H') after 250 ns;
data <= buskeep(data) after 5 ns;
-- sd <= buskeep(sd), (others => 'H') after 250 ns;
sd <= buskeep(sd) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
gpl-2.0
|
30d149fb306be343b0c13c583a08a456
| 0.58248 | 3.072963 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702/testbench.vhd
| 3 | 7,570 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2012 Fredrik Ringhage, Gaisler Research
-- Modified by Jiri Gaisler, 2014-04-05
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := true
);
end;
architecture behav of testbench is
signal button : std_logic_vector(3 downto 0) := (others => '0');
signal switch : std_logic_vector(7 downto 0); -- I/O port
signal led : std_logic_vector(7 downto 0); -- I/O port
signal processing_system7_0_MIO : std_logic_vector(53 downto 0);
signal processing_system7_0_PS_SRSTB : std_logic;
signal processing_system7_0_PS_CLK : std_logic;
signal processing_system7_0_PS_PORB : std_logic;
signal processing_system7_0_DDR_Clk : std_logic;
signal processing_system7_0_DDR_Clk_n : std_logic;
signal processing_system7_0_DDR_CKE : std_logic;
signal processing_system7_0_DDR_CS_n : std_logic;
signal processing_system7_0_DDR_RAS_n : std_logic;
signal processing_system7_0_DDR_CAS_n : std_logic;
signal processing_system7_0_DDR_WEB_pin : std_logic;
signal processing_system7_0_DDR_BankAddr : std_logic_vector(2 downto 0);
signal processing_system7_0_DDR_Addr : std_logic_vector(14 downto 0);
signal processing_system7_0_DDR_ODT : std_logic;
signal processing_system7_0_DDR_DRSTB : std_logic;
signal processing_system7_0_DDR_DQ : std_logic_vector(31 downto 0);
signal processing_system7_0_DDR_DM : std_logic_vector(3 downto 0);
signal processing_system7_0_DDR_DQS : std_logic_vector(3 downto 0);
signal processing_system7_0_DDR_DQS_n : std_logic_vector(3 downto 0);
signal processing_system7_0_DDR_VRN : std_logic;
signal processing_system7_0_DDR_VRP : std_logic;
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false
);
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB : inout std_logic;
processing_system7_0_PS_CLK : inout std_logic;
processing_system7_0_PS_PORB : inout std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : inout std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0)
);
end component;
begin
-- clock, reset and misc
button <= (others => '0');
switch <= (others => '0');
cpu : leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow,
testahb => testahb
)
port map (
processing_system7_0_MIO => processing_system7_0_MIO,
processing_system7_0_PS_SRSTB => processing_system7_0_PS_SRSTB,
processing_system7_0_PS_CLK => processing_system7_0_PS_CLK,
processing_system7_0_PS_PORB => processing_system7_0_PS_PORB,
processing_system7_0_DDR_Clk => processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n => processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE => processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n => processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n => processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n => processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr => processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT => processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB => processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ => processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM => processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS => processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n => processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN => processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP => processing_system7_0_DDR_VRP,
button => button,
switch => switch,
led => led
);
iuerr : process
begin
wait for 5000 ns;
wait on led(1);
assert (led(1) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
|
gpl-2.0
|
01160313024279fcd53c527f472b05c3
| 0.619947 | 3.557331 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/pci/pcipads.vhd
| 1 | 10,989 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcipads
-- File: pcipads.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: PCI pads module
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use work.pci.all;
library grlib;
use grlib.stdlib.all;
entity pcipads is
generic (
padtech : integer := 0;
noreset : integer := 0;
oepol : integer := 0;
host : integer := 1;
int : integer := 0;
no66 : integer := 0;
onchipreqgnt : integer := 0; -- Internal req and gnt signals
drivereset : integer := 0; -- Drive PCI rst with outpad
constidsel : integer := 0; -- pci_idsel is tied to local constant
level : integer := pci33; -- input/output level
voltage : integer := x33v; -- input/output voltage
nolock : integer := 0
);
port (
pci_rst : inout std_logic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic; -- tristate pad but never read
pci_serr : inout std_ulogic; -- open drain output
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pcii : out pci_in_type;
pcio : in pci_out_type;
pci_int : inout std_logic_vector(3 downto 0) --:= conv_std_logic_vector(16#F#, 4) -- Disable int by default
--pci_int : inout std_logic_vector(3 downto 0) :=
-- conv_std_logic_vector(16#F# - (16#F# * oepol), 4) -- Disable int by default
);
end;
architecture rtl of pcipads is
signal vcc : std_ulogic;
begin
vcc <= '1';
-- Reset
rstpad : if noreset = 0 generate
nodrive: if drivereset = 0 generate
pci_rst_pad : iodpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => 0)
port map (pci_rst, pcio.rst, pcii.rst);
end generate nodrive;
drive: if drivereset /= 0 generate
pci_rst_pad : outpad generic map (tech => padtech, level => level,
voltage => voltage)
port map (pci_rst, pcio.rst);
pcii.rst <= pcio.rst;
end generate drive;
end generate;
norstpad : if noreset = 1 generate
pcii.rst <= pci_rst;
end generate;
localgnt: if onchipreqgnt = 1 generate
pcii.gnt <= pci_gnt;
pci_req <= pcio.req when pcio.reqen = conv_std_logic(oepol=1) else '1';
end generate localgnt;
extgnt: if onchipreqgnt = 0 generate
pad_pci_gnt : inpad generic map (padtech, level, voltage) port map (pci_gnt, pcii.gnt);
pad_pci_req : toutpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_req, pcio.req, pcio.reqen);
end generate extgnt;
idsel_pad: if constidsel = 0 generate
pad_pci_idsel : inpad generic map (padtech, level, voltage) port map (pci_idsel, pcii.idsel);
end generate idsel_pad;
idsel_local: if constidsel /= 0 generate
pcii.idsel <= pci_idsel;
end generate idsel_local;
onlyhost : if host = 2 generate
pcii.host <= '0'; -- Always host
end generate;
dohost : if host = 1 generate
pad_pci_host : inpad generic map (padtech, level, voltage) port map (pci_host, pcii.host);
end generate;
nohost : if host = 0 generate
pcii.host <= '1'; -- disable pci host functionality
end generate;
do66 : if no66 = 0 generate
pad_pci_66 : inpad generic map (padtech, level, voltage) port map (pci_66, pcii.pci66);
end generate;
dono66 : if no66 = 1 generate
pcii.pci66 <= '0';
end generate;
dolock : if nolock = 0 generate
pad_pci_lock : iopad
generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_lock, pcio.lock, pcio.locken, pcii.lock);
end generate;
donolock : if nolock = 1 generate
pcii.lock <= pci_lock;
end generate;
pad_pci_ad : iopadvv generic map (tech => padtech, level => level,
voltage => voltage, width => 32,
oepol => oepol)
port map (pci_ad, pcio.ad, pcio.vaden, pcii.ad);
pad_pci_cbe0 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(0), pcio.cbe(0), pcio.cbeen(0), pcii.cbe(0));
pad_pci_cbe1 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(1), pcio.cbe(1), pcio.cbeen(1), pcii.cbe(1));
pad_pci_cbe2 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(2), pcio.cbe(2), pcio.cbeen(2), pcii.cbe(2));
pad_pci_cbe3 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(3), pcio.cbe(3), pcio.cbeen(3), pcii.cbe(3));
pad_pci_frame : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_frame, pcio.frame, pcio.frameen, pcii.frame);
pad_pci_trdy : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_trdy, pcio.trdy, pcio.trdyen, pcii.trdy);
pad_pci_irdy : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_irdy, pcio.irdy, pcio.irdyen, pcii.irdy);
pad_pci_devsel: iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_devsel, pcio.devsel, pcio.devselen, pcii.devsel);
pad_pci_stop : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_stop, pcio.stop, pcio.stopen, pcii.stop);
pad_pci_perr : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_perr, pcio.perr, pcio.perren, pcii.perr);
pad_pci_par : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_par, pcio.par, pcio.paren, pcii.par);
pad_pci_serr : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_serr, pcio.serr, pcio.serren, pcii.serr);
-- PCI interrupt pads
-- int = 0 => no interrupt
-- int = 1 => PCI_INT[A] = out, PCI_INT[B,C,D] = Not connected
-- int = 2 => PCI_INT[B] = out, PCI_INT[A,C,D] = Not connected
-- int = 3 => PCI_INT[C] = out, PCI_INT[A,B,D] = Not connected
-- int = 4 => PCI_INT[D] = out, PCI_INT[A,B,C] = Not connected
-- int = 10 => PCI_INT[A] = inout, PCI_INT[B,C,D] = in
-- int = 11 => PCI_INT[B] = inout, PCI_INT[A,C,D] = in
-- int = 12 => PCI_INT[C] = inout, PCI_INT[A,B,D] = in
-- int = 13 => PCI_INT[D] = inout, PCI_INT[A,B,C] = in
-- int = 14 => PCI_INT[A,B,C,D] = in
-- int = 100 => PCI_INT[A] = out, PCI_INT[B,C,D] = Not connected
-- int = 101 => PCI_INT[A,B] = out, PCI_INT[C,D] = Not connected
-- int = 102 => PCI_INT[A,B,C] = out, PCI_INT[D] = Not connected
-- int = 103 => PCI_INT[A,B,C,D] = out
-- int = 110 => PCI_INT[A] = inout, PCI_INT[B,C,D] = in
-- int = 111 => PCI_INT[A,B] = inout, PCI_INT[C,D] = in
-- int = 112 => PCI_INT[A,B,C] = inout, PCI_INT[D] = in
-- int = 113 => PCI_INT[A,B,C,D] = inout
interrupt : if int /= 0 generate
x : for i in 0 to 3 generate
xo : if i = int - 1 and int < 10 generate
pad_pci_int : odpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.inten);
end generate;
xonon : if i /= int - 1 and int < 10 and int < 100 generate
pci_int(i) <= '1';
end generate;
xio : if i = (int - 10) and int >= 10 and int < 100 generate
pad_pci_int : iodpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.inten, pcii.int(i));
end generate;
xi : if i /= (int - 10) and int >= 10 and int < 100 generate
pad_pci_int : inpad generic map (tech => padtech, level => level, voltage => voltage)
port map (pci_int(i), pcii.int(i));
end generate;
x2o : if i <= (int - 100) and int < 110 and int >= 100 generate
pad_pci_int : odpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.vinten(i));
end generate;
x2onon : if i > (int - 100) and int < 110 and int >= 100 generate
pci_int(i) <= '1';
end generate;
x2oi : if i <= (int - 110) and int >= 110 generate
pad_pci_int : iodpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.vinten(i), pcii.int(i));
end generate;
x2i : if i > (int - 110) and int >= 110 generate
pad_pci_int : inpad generic map (tech => padtech, level => level, voltage => voltage)
port map (pci_int(i), pcii.int(i));
end generate;
end generate;
end generate;
nointerrupt : if int = 0 generate
pcii.int <= (others => '0');
end generate;
pcii.pme_status <= '0';
end;
|
gpl-2.0
|
f26122a1ecd4492ae1d3365b4b9fa56d
| 0.571754 | 3.510863 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-sp601/testbench.vhd
| 1 | 10,586 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 37 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal clk200p : std_logic := '1';
signal clk200n : std_logic := '0';
signal rst : std_logic := '0';
signal rstn1 : std_logic;
signal rstn2 : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic := '0';
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_dq2 : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Ethernet signals
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic;
signal erxdt : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etxdt : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
-- SVGA signals
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(3 downto 0);
signal vid_g : std_logic_vector(3 downto 0);
signal vid_b : std_logic_vector(3 downto 0);
-- Select signal for SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_logic;
signal spi_mosi : std_logic;
-- Output signals for LEDs
signal led : std_logic_vector(2 downto 0);
signal brdyn : std_ulogic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
rst <= '1', '0' after 100 ns;
dsubre <= '0';
urxd <= 'H';
spi_sel_n <= 'H';
spi_clk <= 'L';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
reset => rst,
reset_o1 => rstn1,
reset_o2 => rstn2,
clk27 => clk,
clk200_p => clk200p,
clk200_n => clk200n,
errorn => error,
-- PROM
address => address(23 downto 0),
data => data(31 downto 24),
romsn => romsn,
oen => oen,
writen => writen,
iosn => iosn,
testdata => data(23 downto 0),
-- DDR2
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_cke => ddr_cke,
ddr_we => ddr_we,
ddr_ras => ddr_ras,
ddr_cas => ddr_cas,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_dqsn => ddr_dqsn,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
ddr_odt => ddr_odt,
ddr_rzq => ddr_rzq,
ddr_zio => ddr_zio,
-- Debug Unit
dsubre => dsubre,
-- AHB Uart
dsutx => dsutx,
dsurx => dsurx,
-- PHY
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxdt(7 downto 0),
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxdt(7 downto 0),
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc,
emdio => emdio,
-- SPI flash select
-- spi_sel_n => spi_sel_n,
-- spi_clk => spi_clk,
-- spi_mosi => spi_mosi,
-- Output signals for LEDs
led => led
);
migddr2mem : if (CFG_MIG_DDR2 = 1) generate
ddr2mem0: ddr2ram
generic map (width => 16, abits => 13, babits => 3,
colbits => 10, rowbits => 13, implbanks => 1,
fname => sdramfile, lddelay => (220 us),
speedbin => 1)
port map (ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb,
odt => ddr_odt, rasn => ddr_ras, casn => ddr_cas, wen => ddr_we,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad,
dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn);
end generate;
ddr2mem : if (CFG_DDR2SP /= 0) generate
ddr2mem0: ddr2ram
generic map (width => 16, abits => 13, babits => 3,
colbits => 10, rowbits => 13, implbanks => 1,
fname => sdramfile, lddelay => (0 us),
speedbin => 1)
port map (ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb,
odt => ddr_odt, rasn => ddr_ras, casn => ddr_cas, wen => ddr_we,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad,
dq => ddr_dq2, dqs => ddr_dqs, dqsn => ddr_dqsn);
ddr2delay0 : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 9.0)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
prom0 : sram
generic map (index => 6, abits => 24, fname => promfile)
port map (address(23 downto 0), data(31 downto 24), romsn, writen, oen);
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map (address => 1)
port map(rstn1, emdio, etx_clk, erx_clk, erxdt, erx_dv, erx_er,
erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, '0');
end generate;
spimem0: if CFG_SPIMCTRL = 1 generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => 0) -- Dual output is not supported in this design
port map (spi_clk, spi_mosi, data(24), spi_sel_n);
end generate spimem0;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data, iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
|
gpl-2.0
|
c20ef38b7250bb672d7c00a1d3639ebd
| 0.538919 | 3.454961 | false | false | false | false |
aortiz49/MIPS-Processor
|
Hardware/register_file.vhd
| 1 | 3,455 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity register_file is
port (
clk : in std_logic;
data : in std_logic_vector (31 downto 0);
rst : in std_logic;
reg_write : in std_logic_vector(4 downto 0);
wr_en : in std_logic;
reg_read1 : in std_logic_vector(4 downto 0);
reg_read0 : in std_logic_vector(4 downto 0);
output1 : out std_logic_vector(31 downto 0);
output0 : out std_logic_vector(31 downto 0)
);
end entity;
architecture ARCH of register_file is
type t_interconnect is array (0 to 31) of std_logic_vector(31 downto 0); -- the new type
signal interconnect : t_interconnect;
signal en_t : std_logic_vector(31 downto 0);
begin
regs: for i in 1 to 31 generate
reg_bank: entity work.reg32
port map(
d => data,
rst => rst,
en => en_t(i),
clk => clk,
q => interconnect(i)
);
end generate;
decode : entity work.decoder
port map(
enable => reg_write,
wr_en => wr_en,
decode_out => en_t(31 downto 0)
);
mux1 : entity work.regFile_mux
port map(
in31 => interconnect(31),
in30 => interconnect(30),
in29 => interconnect(29),
in28 => interconnect(28),
in27 => interconnect(27),
in26 => interconnect(26),
in25 => interconnect(25),
in24 => interconnect(24),
in23 => interconnect(23),
in22 => interconnect(22),
in21 => interconnect(21),
in20 => interconnect(20),
in19 => interconnect(19),
in18 => interconnect(18),
in17 => interconnect(17),
in16 => interconnect(16),
in15 => interconnect(15),
in14 => interconnect(14),
in13 => interconnect(13),
in12 => interconnect(12),
in11 => interconnect(11),
in10 => interconnect(10),
in09 => interconnect(09),
in08 => interconnect(08),
in07 => interconnect(07),
in06 => interconnect(06),
in05 => interconnect(05),
in04 => interconnect(04),
in03 => interconnect(03),
in02 => interconnect(02),
in01 => interconnect(01),
in00 => interconnect(00),
sel => reg_read1,
output => output1
);
mux2 : entity work.regFile_mux
port map(
in31 => interconnect(31),
in30 => interconnect(30),
in29 => interconnect(29),
in28 => interconnect(28),
in27 => interconnect(27),
in26 => interconnect(26),
in25 => interconnect(25),
in24 => interconnect(24),
in23 => interconnect(23),
in22 => interconnect(22),
in21 => interconnect(21),
in20 => interconnect(20),
in19 => interconnect(19),
in18 => interconnect(18),
in17 => interconnect(17),
in16 => interconnect(16),
in15 => interconnect(15),
in14 => interconnect(14),
in13 => interconnect(13),
in12 => interconnect(12),
in11 => interconnect(11),
in10 => interconnect(10),
in09 => interconnect(09),
in08 => interconnect(08),
in07 => interconnect(07),
in06 => interconnect(06),
in05 => interconnect(05),
in04 => interconnect(04),
in03 => interconnect(03),
in02 => interconnect(02),
in01 => interconnect(01),
in00 => interconnect(00),
sel => reg_read0,
output => output0
);
zero: entity work.zeroReg
port map(
clk => clk,
rst => rst,
en => '0',
input => data,
output => interconnect(00)
);
end architecture;
|
mit
|
e980f0ccbf7e645da81659f21463c279
| 0.57974 | 3.073843 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-vc707/ahbrom.vhd
| 18 | 8,961 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2009 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800015";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A033";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539AE1B";
when 16#00069# => romdata <= X"8410A260";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800005";
when 16#00074# => romdata <= X"03200000";
when 16#00075# => romdata <= X"0539A81B";
when 16#00076# => romdata <= X"8410A260";
when 16#00077# => romdata <= X"C4204000";
when 16#00078# => romdata <= X"05000080";
when 16#00079# => romdata <= X"82100000";
when 16#0007A# => romdata <= X"80A0E000";
when 16#0007B# => romdata <= X"02800005";
when 16#0007C# => romdata <= X"01000000";
when 16#0007D# => romdata <= X"82004002";
when 16#0007E# => romdata <= X"10BFFFFC";
when 16#0007F# => romdata <= X"8620E001";
when 16#00080# => romdata <= X"3D1003FF";
when 16#00081# => romdata <= X"BC17A3E0";
when 16#00082# => romdata <= X"BC278001";
when 16#00083# => romdata <= X"9C27A060";
when 16#00084# => romdata <= X"03100000";
when 16#00085# => romdata <= X"81C04000";
when 16#00086# => romdata <= X"01000000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
gpl-2.0
|
c835c7ec3df34070ba5d1df1fa071a4a
| 0.58085 | 3.28844 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep2s60-ddr/leon3mp.vhd
| 1 | 21,068 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- flash/ethernet bus
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(31 downto 0);
romsn : out std_ulogic;
oen : out std_logic;
writen : out std_logic;
byten : out std_logic;
wpn : out std_logic;
-- SSRAM
ssram_ce1n : out std_logic;
ssram_ce2 : out std_logic;
ssram_ce3n : out std_logic;
ssram_wen : out std_logic;
ssram_bw : out std_logic_vector (0 to 3);
ssram_oen : out std_ulogic;
ssaddr : out std_logic_vector(20 downto 2);
ssdata : inout std_logic_vector(31 downto 0);
ssram_clk : out std_ulogic;
ssram_adscn : out std_ulogic;
ssram_adsp_n : out std_ulogic;
ssram_adv_n : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
ddr_clkin : in std_logic;
ddr_clk : out std_logic;
ddr_clkn : out std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console/debug UART
rxd1 : in std_logic;
txd1 : out std_logic;
-- for smsc lan chip
eth_aen : out std_logic;
eth_readn : out std_logic;
eth_writen: out std_logic;
eth_nbe : out std_logic_vector(3 downto 0);
eth_lclk : out std_ulogic;
eth_nads : out std_logic;
eth_ncycle : out std_logic;
eth_wnr : out std_logic;
eth_nvlbus : out std_logic;
eth_nrdyrtn : out std_logic;
eth_ndatacs : out std_logic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi, smemi : memory_in_type;
signal memo, smemo : memory_out_type;
signal wpo : wprot_out_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
-- attribute syn_keep : boolean;
-- attribute syn_preserve : boolean;
-- attribute syn_keep of clkml : signal is true;
-- attribute syn_preserve of clkml : signal is true;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal ssd, prd : std_logic_vector(31 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector;
signal clkm, rstn, ssram_clkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal dsubre : std_ulogic;
component smc_mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type;
eth_aen : out std_ulogic; -- for smsc lan chip
eth_readn : out std_ulogic; -- for smsc lan chip
eth_writen: out std_ulogic; -- for smsc lan chip
eth_nbe : out std_logic_vector(3 downto 0) -- for smsc lan chip
);
end component;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock;
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN,
freq => freq)
port map (clkin => clk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => ssram_clkl, pciclk => open,
cgi => cgi, cgo => cgo);
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (ssram_clk, ssram_clkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, 0, 0,
CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
ramaddr => 16#400#+16#600#*CFG_DDRSP, rammask =>16#F00#, srbanks => 1,
sden => 0, ram8 => 1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, open,
s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe);
end generate;
wpn <= '1'; byten <= '0';
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if CFG_MCTRL_LEON2 = 1 generate -- prom/sram pads
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(23 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
ssram_adv_n_pad : outpad generic map (tech => padtech)
port map (ssram_adv_n, vcc(0));
ssram_adsp_n_pad : outpad generic map (tech => padtech)
port map (ssram_adsp_n, gnd(0));
ssaddr_pad : outpadv generic map (width => 19, tech => padtech)
port map (ssaddr, memo.address(20 downto 2));
ssram_adscn_pad : outpad generic map (tech => padtech)
port map (ssram_adscn, vcc(0));
ssram_ce1n_pad : outpad generic map (tech => padtech)
port map (ssram_ce1n, gnd(0));
ssram_ce2_pad : outpad generic map (tech => padtech)
port map (ssram_ce2, vcc(0));
ssrams_pad : outpad generic map ( tech => padtech)
port map (ssram_ce3n, memo.ramsn(0));
ssram_oen_pad : outpad generic map (tech => padtech)
port map (ssram_oen, memo.oen);
ssram_rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (ssram_bw, memo.wrn);
ssram_wri_pad : outpad generic map (tech => padtech)
port map (ssram_wen, memo.writen);
ssram_data_pads : iopadvv generic map (tech => padtech, width => 32)
port map (ssdata, memo.data, memo.vbdrive, ssd);
memi.data(31 downto 0) <= ssd when memo.ramsn(0) = '0' else prd;
-- for smc lan chip
eth_aen_pad : outpad generic map (tech => padtech)
port map (eth_aen, s_eth_aen);
eth_readn_pad : outpad generic map (tech => padtech)
port map (eth_readn, s_eth_readn);
eth_writen_pad : outpad generic map (tech => padtech)
port map (eth_writen, s_eth_writen);
eth_nbe_pad : outpadv generic map (width => 4, tech => padtech)
port map (eth_nbe, s_eth_nbe);
data_pad : iopadvv generic map (tech => padtech, width => 32)
port map (data(31 downto 0), memo.data(31 downto 0),
memo.vbdrive, prd);
end generate;
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 3, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 16)
port map (
resetn, rstn, ddr_clkin, clkm, lock, clkml, clkml, ahbsi, ahbso(3),
ddr_clkv, ddr_clkbv, open, gnd(0),
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkn <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
ddrsp1 : if (CFG_DDRSP = 0) generate
ddr_cke <= '0'; ddr_csb <= '1'; lock <= '1';
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
upads : if CFG_AHB_UART = 0 generate
u1i.rxd <= rxd1; txd1 <= u1o.txd;
end generate;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-- for smc lan chip
eth_lclk <= vcc(0);
eth_nads <= gnd(0);
eth_ncycle <= vcc(0);
eth_wnr <= vcc(0);
eth_nvlbus <= vcc(0);
eth_nrdyrtn <= vcc(0);
eth_ndatacs <= vcc(0);
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP2C60 SSRAM/DDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
5ecd5dfed10a74c86ec22fe227b180a0
| 0.546231 | 3.659545 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/fmf/utilities/conversions.vhd
| 5 | 39,795 |
--------------------------------------------------------------------------------
-- File Name: conversions_p.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1997, 1998, 2001 Free Model Foundry; http://eda.org/fmf/
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- This package was written by SEVA Technologies, Inc. and donated to the FMF.
-- www.seva.com
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 R. Steele 97 DEC 05 Added header and formatting to SEVA file
-- V1.1 R. Munden 98 NOV 28 Corrected some comments
-- Corrected function b
-- V1.2 R. Munden 01 MAY 27 Corrected function to_nat for weak values
-- and combined into a single file
--
--------------------------------------------------------------------------------
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
--------------------------------------------------------------------------------
-- CONVERSION FUNCTION SELECTION TABLES
--------------------------------------------------------------------------------
--
-- FROM TO: std_logic_vector std_logic natural time string
-- -----------------|---------------|---------|---------|---------|-----------
-- std_logic_vector | N/A | N/A | to_nat | combine | see below
-- std_logic | N/A | N/A | to_nat | combine | see below
-- natural | to_slv | to_sl | N/A | to_time | see below
-- time | N/A | N/A | to_nat | N/A | to_time_str
-- hex string | h | N/A | h | combine | N/A
-- decimal string | d | N/A | d | combine | N/A
-- octal string | o | N/A | o | combine | N/A
-- binary string | b | N/A | b | combine | N/A
-- -----------------|---------------|---------|---------|---------|-----------
--
-- FROM TO: hex string decimal string octal string binary string
-- -----------------|------------|-------------|------------|----------------
-- std_logic_vector | to_hex_str | to_int_str | to_oct_str | to_bin_str
-- std_logic | N/A | N/A | N/A | to_bin_str
-- natural | to_hex_str | to_int_str | to_oct_str | to_bin_str
-- -----------------|------------|-------------|------------|----------------
--
--------------------------------------------------------------------------------
PACKAGE conversions IS
----------------------------------------------------------------------------
-- the conversions in this package are not guaranteed to be synthesizable.
--
-- others functions available
-- fill creates a variable length string of the fill character
--
--
--
-- input parameters of type natural or integer can be in the form:
-- normal -> 8, 99, 4_237
-- base#value# -> 2#0101#, 16#fa4C#, 8#6_734#
-- with exponents(x10) -> 8e4, 16#2e#E4
--
-- input parameters of type string can be in the form:
-- "99", "4_237", "0101", "1010_1010"
--
-- for bit/bit_vector <-> std_logic/std_logic_vector conversions use
-- package std_logic_1164
-- to_bit(std_logic)
-- to_bitvector(std_logic_vector)
-- to_stdlogic(bit)
-- to_stdlogicvector(bit_vector)
--
-- for "synthesizable" signed/unsigned/std_logic_vector/integer
-- conversions use
-- package std_logic_arith
-- conv_integer(signed/unsigned)
-- conv_unsigned(integer/signed,size)
-- conv_signed(integer/unsigned,size)
-- conv_std_logic_vector(integer/signed/unsigned,size)
--
-- for "synthesizable" std_logic_vector -> integer conversions use
-- package std_logic_unsigned/std_logic_signed
-- <these packages are mutually exclusive>
-- conv_integer(std_logic_vector)
-- <except for this conversion, these packages are unnecessary)
-- to minimize compile problems write:
-- use std_logic_unsigned.conv_integer;
-- use std_logic_signed.conv_integer;
--
-- std_logic_vector, signed and unsigned types are "closely related"
-- no type conversion functions are needed, use type casting or qualified
-- expressions
--
-- type1(object of type2) <type casting>
-- type1'(expression of type2) <qualified expression>
--
-- most conversions have 4 parmeters:
-- x : value to be converted
-- rtn_len : size of the return value
-- justify : justify value 'left' or 'right', default is right
-- basespec : print the base of the value - 'yes'/'no', default is yes
--
-- Typical ways to call these functions:
-- simple, all defaults used
-- to_bin_str(x)
-- x will be converted to a string of minimum size with a
-- base specification appended for clarity
-- if x is 10101 then return is b"10101"
--
-- to control size of return string
-- to_hex_str(x,
-- 6)
-- length of string returned will be 6 characters
-- value will be right justified in the field
-- if x is 10101 then return is ....h"15"
-- where '.' represents a blank
-- if 'rtn_len' parm defaults or is set to 0 then
-- return string will always be minimum size
--
-- to left justify and suppress base specification
-- to_int_str(x,
-- 6,
-- justify => left,
-- basespec => yes)
-- length of return string will be 6 characters
-- the base specification will be suppressed
-- if x is 10101 then return is 21....
-- where '.' represents a blank
--
-- other usage notes
--
-- if rtn_len less than or equal to x'length then ignore
-- rtn_len and return string of x'length
-- the 'justify' parm is effectively ignored in this case
--
-- if rtn_len greater than x'length then return string
-- of rtn_len with blanks based on 'justify' parm
--
-- these routines do not handle negative numbers
----------------------------------------------------------------------------
type justify_side is (left, right);
type b_spec is (no , yes);
-- std_logic_vector to binary string
function to_bin_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- std_logic to binary string
function to_bin_str(x : std_logic;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- natural to binary string
function to_bin_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- std_logic_vector to hex string
function to_hex_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- natural to hex string
function to_hex_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- std_logic_vector to octal string
function to_oct_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- natural to octal string
function to_oct_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- natural to integer string
function to_int_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- std_logic_vector to integer string
function to_int_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- time to string
function to_time_str (x : time)
return string;
-- add characters to a string
function fill (fill_char : character := '*';
rtn_len : integer := 1)
return string;
-- usage:
-- fill
-- returns *
-- fill(' ',10)
-- returns .......... when '.' represents a blank
-- fill(lf) or fill(ht)
-- returns line feed character or tab character respectively
-- std_logic_vector to natural
function to_nat (x : std_logic_vector)
return natural;
-- std_logic to natural
function to_nat (x : std_logic)
return natural;
-- time to natural
function to_nat (x : time)
return natural;
-- hex string to std_logic_vector
function h (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 9 or a,A to f,F
-- or x,X,z,Z,u,U,-,w,W, result will be 0
-- decimal string to std_logic_vector
function d (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 9 or x,X,z,Z,u,U,-,w,W,
-- result will be 0
-- octal string to std_logic_vector
function o (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 7 or x,X,z,Z,u,U,-,w,W,
-- result will be 0
-- binary string to std_logic_vector
function b (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W,
-- result will be 0
-- hex string to natural
function h (x : string)
return natural;
-- if x is other than characters 0 to 9 or a,A to f,F, result will be 0
-- decimal string to natural
function d (x : string)
return natural;
-- if x is other than characters 0 to 9, result will be 0
-- octal string to natural
function o (x : string)
return natural;
-- if x is other than characters 0 to 7, result will be 0
-- binary string to natural
function b (x : string)
return natural;
-- if x is other than characters 0 to 1, result will be 0
-- natural to std_logic_vector
function to_slv (x : natural;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than sizeof(x), result will be truncated on the left
-- see note above regarding possible formats for x
-- natural to std_logic
function to_sl (x : natural)
return std_logic;
-- natural to time
function to_time (x : natural)
return time;
-- see note above regarding possible formats for x
END conversions;
--
--------------------------------------------------------------------------------
--
PACKAGE BODY conversions IS
-- private declarations for this package
type basetype is (binary, octal, decimal, hex);
function max(x,y: integer) return integer is
begin
if x > y then return x; else return y; end if;
end max;
function min(x,y: integer) return integer is
begin
if x < y then return x; else return y; end if;
end min;
-- consider function sizeof for string/slv/???, return natural
-- function size(len: natural) return natural is
-- begin
-- if len=0 then
-- return 31;
-- else return len;
-- end if;
-- end size;
function nextmultof (x : positive;
size : positive) return positive is
begin
case x mod size is
when 0 => return size * x/size;
when others => return size * (x/size + 1);
end case;
end nextmultof;
function rtn_base (base : basetype) return character is
begin
case base is
when binary => return 'b';
when octal => return 'o';
when decimal => return 'd';
when hex => return 'h';
end case;
end rtn_base;
function format (r : string;
base : basetype;
rtn_len : natural ;
justify : justify_side;
basespec : b_spec) return string is
variable int_rtn_len : integer;
begin
if basespec=yes then
int_rtn_len := rtn_len - 3;
else
int_rtn_len := rtn_len;
end if;
if int_rtn_len <= r'length then
case basespec is
when no => return r ;
when yes => return rtn_base(base) & '"' & r & '"';
end case;
else
case justify is
when left =>
case basespec is
when no =>
return r & fill(' ',int_rtn_len - r'length);
when yes =>
return rtn_base(base) & '"' & r & '"' &
fill(' ',int_rtn_len - r'length);
end case;
when right =>
case basespec is
when no =>
return fill(' ',int_rtn_len - r'length) & r ;
when yes =>
return fill(' ',int_rtn_len - r'length) &
rtn_base(base) & '"' & r & '"';
end case;
end case;
end if;
end format;
-- convert numeric string of any base to natural
function cnvt_base (x : string;
inbase : natural range 2 to 16) return natural is
-- assumes x is an unsigned number string of base 'inbase'
-- values larger than natural'high are not supported
variable r,t : natural := 0;
variable place : positive := 1;
begin
for i in x'reverse_range loop
case x(i) is
when '0' => t := 0;
when '1' => t := 1;
when '2' => t := 2;
when '3' => t := 3;
when '4' => t := 4;
when '5' => t := 5;
when '6' => t := 6;
when '7' => t := 7;
when '8' => t := 8;
when '9' => t := 9;
when 'a'|'A' => t := 10;
when 'b'|'B' => t := 11;
when 'c'|'C' => t := 12;
when 'd'|'D' => t := 13;
when 'e'|'E' => t := 14;
when 'f'|'F' => t := 15;
when '_' => t := 0; -- ignore these characters
place := place / inbase;
when others =>
assert false
report lf &
"CNVT_BASE found input value larger than base: " & lf &
"Input value: " & x(i) &
" Base: " & to_int_str(inbase) & lf &
"converting input to integer 0"
severity warning;
return 0;
end case;
if t / inbase > 1 then -- invalid value for base
assert false
report lf &
"CNVT_BASE found input value larger than base: " & lf &
"Input value: " & x(i) &
" Base: " & to_int_str(inbase) & lf &
"converting input to integer 0"
severity warning;
return 0;
else
r := r + (t * place);
place := place * inbase;
end if;
end loop;
return r;
end cnvt_base;
function extend (x : std_logic;
len : positive) return std_logic_vector is
variable v : std_logic_vector(1 to len) := (others => x);
begin
return v;
end extend;
-- implementation of public declarations
function to_bin_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : std_logic_vector(1 to x'length):=x;
variable r : string(1 to x'length):=(others=>'$');
begin
for i in int'range loop
r(i to i) := to_bin_str(int(i),basespec=>no);
end loop;
return format (r,binary,rtn_len,justify,basespec);
end to_bin_str;
function to_bin_str(x : std_logic;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable r : string(1 to 1);
begin
case x is
when '0' => r(1) := '0';
when '1' => r(1) := '1';
when 'U' => r(1) := 'U';
when 'X' => r(1) := 'X';
when 'Z' => r(1) := 'Z';
when 'W' => r(1) := 'W';
when 'H' => r(1) := 'H';
when 'L' => r(1) := 'L';
when '-' => r(1) := '-';
end case;
return format (r,binary,rtn_len,justify,basespec);
end to_bin_str;
function to_bin_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 2 to 32 := 32;
variable r : string(2 to 32):=(others=>'$');
begin
if int = 0 then
return format ("0",binary,rtn_len,justify,basespec);
end if;
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & "TO_BIN_STR, shouldn't happen"
severity failure;
return "$";
null;
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 32),binary,rtn_len,justify,basespec);
end to_bin_str;
function to_hex_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
-- will return x'length/4
variable nxt : positive := nextmultof(x'length,4);
variable int : std_logic_vector(1 to nxt):= (others => '0');
variable ptr : positive range 1 to (nxt/4)+1 := 1;
variable r : string(1 to nxt/4):=(others=>'$');
subtype slv4 is std_logic_vector(1 to 4);
begin
int(nxt-x'length+1 to nxt) := x;
if nxt-x'length > 0 and x(x'left) /= '1' then
int(1 to nxt-x'length) := extend(x(x'left),nxt-x'length);
end if;
for i in int'range loop
next when i rem 4 /= 1;
case slv4'(int(i to i+3)) is
when "0000" => r(ptr) := '0';
when "0001" => r(ptr) := '1';
when "0010" => r(ptr) := '2';
when "0011" => r(ptr) := '3';
when "0100" => r(ptr) := '4';
when "0101" => r(ptr) := '5';
when "0110" => r(ptr) := '6';
when "0111" => r(ptr) := '7';
when "1000" => r(ptr) := '8';
when "1001" => r(ptr) := '9';
when "1010" => r(ptr) := 'A';
when "1011" => r(ptr) := 'B';
when "1100" => r(ptr) := 'C';
when "1101" => r(ptr) := 'D';
when "1110" => r(ptr) := 'E';
when "1111" => r(ptr) := 'F';
when "ZZZZ" => r(ptr) := 'Z';
when "WWWW" => r(ptr) := 'W';
when "LLLL" => r(ptr) := 'L';
when "HHHH" => r(ptr) := 'H';
when "UUUU" => r(ptr) := 'U';
when "XXXX" => r(ptr) := 'X';
when "----" => r(ptr) := '-';
when others =>
assert false
report lf &
"TO_HEX_STR found illegal value: " &
to_bin_str(int(i to i+3)) & lf &
"converting input to '-'"
severity warning;
r(ptr) := '-';
end case;
ptr := ptr + 1;
end loop;
return format (r,hex,rtn_len,justify,basespec);
end to_hex_str;
function to_hex_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 1 to 20 := 20;
variable r : string(1 to 20):=(others=>'$');
begin
if x=0 then return format ("0",hex,rtn_len,justify,basespec); end if;
while int > 0 loop
case int rem 16 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when 2 => r(ptr) := '2';
when 3 => r(ptr) := '3';
when 4 => r(ptr) := '4';
when 5 => r(ptr) := '5';
when 6 => r(ptr) := '6';
when 7 => r(ptr) := '7';
when 8 => r(ptr) := '8';
when 9 => r(ptr) := '9';
when 10 => r(ptr) := 'A';
when 11 => r(ptr) := 'B';
when 12 => r(ptr) := 'C';
when 13 => r(ptr) := 'D';
when 14 => r(ptr) := 'E';
when 15 => r(ptr) := 'F';
when others =>
assert false report lf & "TO_HEX_STR, shouldn't happen"
severity failure;
return "$";
end case;
int := int / 16;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 20),hex,rtn_len,justify,basespec);
end to_hex_str;
function to_oct_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
-- will return x'length/3
variable nxt : positive := nextmultof(x'length,3);
variable int : std_logic_vector(1 to nxt):= (others => '0');
variable ptr : positive range 1 to (nxt/3)+1 := 1;
variable r : string(1 to nxt/3):=(others=>'$');
subtype slv3 is std_logic_vector(1 to 3);
begin
int(nxt-x'length+1 to nxt) := x;
if nxt-x'length > 0 and x(x'left) /= '1' then
int(1 to nxt-x'length) := extend(x(x'left),nxt-x'length);
end if;
for i in int'range loop
next when i rem 3 /= 1;
case slv3'(int(i to i+2)) is
when "000" => r(ptr) := '0';
when "001" => r(ptr) := '1';
when "010" => r(ptr) := '2';
when "011" => r(ptr) := '3';
when "100" => r(ptr) := '4';
when "101" => r(ptr) := '5';
when "110" => r(ptr) := '6';
when "111" => r(ptr) := '7';
when "ZZZ" => r(ptr) := 'Z';
when "WWW" => r(ptr) := 'W';
when "LLL" => r(ptr) := 'L';
when "HHH" => r(ptr) := 'H';
when "UUU" => r(ptr) := 'U';
when "XXX" => r(ptr) := 'X';
when "---" => r(ptr) := '-';
when others =>
assert false
report lf &
"TO_OCT_STR found illegal value: " &
to_bin_str(int(i to i+2)) & lf &
"converting input to '-'"
severity warning;
r(ptr) := '-';
end case;
ptr := ptr + 1;
end loop;
return format (r,octal,rtn_len,justify,basespec);
end to_oct_str;
function to_oct_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 1 to 20 := 20;
variable r : string(1 to 20):=(others=>'$');
begin
if x=0 then return format ("0",octal,rtn_len,justify,basespec); end if;
while int > 0 loop
case int rem 8 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when 2 => r(ptr) := '2';
when 3 => r(ptr) := '3';
when 4 => r(ptr) := '4';
when 5 => r(ptr) := '5';
when 6 => r(ptr) := '6';
when 7 => r(ptr) := '7';
when others =>
assert false report lf & "TO_OCT_STR, shouldn't happen"
severity failure;
return "$";
end case;
int := int / 8;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 20),octal,rtn_len,justify,basespec);
end to_oct_str;
function to_int_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 1 to 32 := 32;
variable r : string(1 to 32):=(others=>'$');
begin
if x=0 then return format ("0",hex,rtn_len,justify,basespec);
else
while int > 0 loop
case int rem 10 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when 2 => r(ptr) := '2';
when 3 => r(ptr) := '3';
when 4 => r(ptr) := '4';
when 5 => r(ptr) := '5';
when 6 => r(ptr) := '6';
when 7 => r(ptr) := '7';
when 8 => r(ptr) := '8';
when 9 => r(ptr) := '9';
when others =>
assert false report lf & "TO_INT_STR, shouldn't happen"
severity failure;
return "$";
end case;
int := int / 10;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 32),decimal,rtn_len,justify,basespec);
end if;
end to_int_str;
function to_int_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string is
begin
return to_int_str(to_nat(x),rtn_len,justify,basespec);
end to_int_str;
function to_time_str (x : time)
return string is
begin
return to_int_str(to_nat(x),basespec=>no) & " ns";
end to_time_str;
function fill (fill_char : character := '*';
rtn_len : integer := 1)
return string is
variable r : string(1 to max(rtn_len,1)) := (others => fill_char);
variable len : integer;
begin
if rtn_len < 2 then -- always returns at least 1 fill char
len := 1;
else
len := rtn_len;
end if;
return r(1 to len);
end fill;
function to_nat(x : std_logic_vector) return natural is
-- assumes x is an unsigned number, lsb on right,
-- more than 31 bits are truncated on left
variable t : std_logic_vector(1 to x'length) := x;
variable int : std_logic_vector(1 to 31) := (others => '0');
variable r : natural := 0;
variable place : positive := 1;
begin
if x'length < 32 then
int(max(32-x'length,1) to 31) := t(1 to x'length);
else -- x'length >= 32
int(1 to 31) := t(x'length-30 to x'length);
end if;
for i in int'reverse_range loop
case int(i) is
when '1' | 'H' => r := r + place;
when '0' | 'L' => null;
when others =>
assert false
report lf &
"TO_NAT found illegal value: " & to_bin_str(int(i)) & lf &
"converting input to integer 0"
severity warning;
return 0;
end case;
exit when i=1;
place := place * 2;
end loop;
return r;
end to_nat;
function to_nat (x : std_logic)
return natural is
begin
case x is
when '0' => return 0 ;
when '1' => return 1 ;
when others =>
assert false
report lf &
"TO_NAT found illegal value: " & to_bin_str(x) & lf &
"converting input to integer 0"
severity warning;
return 0;
end case;
end to_nat;
function to_nat (x : time)
return natural is
begin
return x / 1 ns;
end to_nat;
function h(x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 9 or a,A to f,F or
-- x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable int : string(1 to x'length) := x;
variable size: positive := max(x'length*4,rtn_len);
variable ptr : integer range -3 to size := size;
variable r : std_logic_vector(1 to size) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => r(ptr-3 to ptr) := "0000";
when '1' => r(ptr-3 to ptr) := "0001";
when '2' => r(ptr-3 to ptr) := "0010";
when '3' => r(ptr-3 to ptr) := "0011";
when '4' => r(ptr-3 to ptr) := "0100";
when '5' => r(ptr-3 to ptr) := "0101";
when '6' => r(ptr-3 to ptr) := "0110";
when '7' => r(ptr-3 to ptr) := "0111";
when '8' => r(ptr-3 to ptr) := "1000";
when '9' => r(ptr-3 to ptr) := "1001";
when 'a'|'A' => r(ptr-3 to ptr) := "1010";
when 'b'|'B' => r(ptr-3 to ptr) := "1011";
when 'c'|'C' => r(ptr-3 to ptr) := "1100";
when 'd'|'D' => r(ptr-3 to ptr) := "1101";
when 'e'|'E' => r(ptr-3 to ptr) := "1110";
when 'f'|'F' => r(ptr-3 to ptr) := "1111";
when 'U' => r(ptr-3 to ptr) := "UUUU";
when 'X' => r(ptr-3 to ptr) := "XXXX";
when 'Z' => r(ptr-3 to ptr) := "ZZZZ";
when 'W' => r(ptr-3 to ptr) := "WWWW";
when 'H' => r(ptr-3 to ptr) := "HHHH";
when 'L' => r(ptr-3 to ptr) := "LLLL";
when '-' => r(ptr-3 to ptr) := "----";
when '_' => ptr := ptr + 4;
when others =>
assert false
report lf &
"O conversion found illegal input character: " &
int(i) & lf & "converting character to '----'"
severity warning;
r(ptr-3 to ptr) := "----";
end case;
ptr := ptr - 4;
end loop;
return r(size-rtn_len+1 to size);
end h;
function d (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than binary length of x, result will be truncated on
-- the left
-- if x is other than characters 0 to 9, result will be 0
begin
return to_slv(cnvt_base(x,10),rtn_len);
end d;
function o (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than x'length*3, result will be truncated on the left
-- if x is other than characters 0 to 7 or or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable int : string(1 to x'length) := x;
variable size: positive := max(x'length*3,rtn_len);
variable ptr : integer range -2 to size := size;
variable r : std_logic_vector(1 to size) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => r(ptr-2 to ptr) := "000";
when '1' => r(ptr-2 to ptr) := "001";
when '2' => r(ptr-2 to ptr) := "010";
when '3' => r(ptr-2 to ptr) := "011";
when '4' => r(ptr-2 to ptr) := "100";
when '5' => r(ptr-2 to ptr) := "101";
when '6' => r(ptr-2 to ptr) := "110";
when '7' => r(ptr-2 to ptr) := "111";
when 'U' => r(ptr-2 to ptr) := "UUU";
when 'X' => r(ptr-2 to ptr) := "XXX";
when 'Z' => r(ptr-2 to ptr) := "ZZZ";
when 'W' => r(ptr-2 to ptr) := "WWW";
when 'H' => r(ptr-2 to ptr) := "HHH";
when 'L' => r(ptr-2 to ptr) := "LLL";
when '-' => r(ptr-2 to ptr) := "---";
when '_' => ptr := ptr + 3;
when others =>
assert false
report lf &
"O conversion found illegal input character: " &
int(i) & lf & "converting character to '---'"
severity warning;
r(ptr-2 to ptr) := "---";
end case;
ptr := ptr - 3;
end loop;
return r(size-rtn_len+1 to size);
end o;
function b (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than x'length, result will be truncated on the left
-- if x is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable int : string(1 to x'length) := x;
variable size: positive := max(x'length,rtn_len);
variable ptr : integer range 0 to size+1 := size; -- csa
variable r : std_logic_vector(1 to size) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => r(ptr) := '0';
when '1' => r(ptr) := '1';
when 'U' => r(ptr) := 'U';
when 'X' => r(ptr) := 'X';
when 'Z' => r(ptr) := 'Z';
when 'W' => r(ptr) := 'W';
when 'H' => r(ptr) := 'H';
when 'L' => r(ptr) := 'L';
when '-' => r(ptr) := '-';
when '_' => ptr := ptr + 1;
when others =>
assert false
report lf &
"B conversion found illegal input character: " &
int(i) & lf & "converting character to '-'"
severity warning;
r(ptr) := '-';
end case;
ptr := ptr - 1;
end loop;
return r(size-rtn_len+1 to size);
end b;
function h (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 9
-- a,A to f,F
-- blanks, underscore
begin
return cnvt_base(x,16);
end h;
function d (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 9
-- blanks, underscore
begin
return cnvt_base(x,10);
end d;
function o (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 7
-- blanks, underscore
begin
return cnvt_base(x,8);
end o;
function b (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 1
-- blanks, underscore
begin
return cnvt_base(x,2);
end b;
function to_slv(x : natural;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than sizeof(x), result will be truncated on the left
variable int : natural := x;
variable ptr : positive := 32;
variable r : std_logic_vector(1 to 32) := (others=>'0');
begin
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & "TO_SLV, shouldn't happen"
severity failure;
return "0";
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
return r(33-rtn_len to 32);
end to_slv;
function to_sl(x : natural)
return std_logic is
variable r : std_logic := '0';
begin
case x is
when 0 => null;
when 1 => r := '1';
when others =>
assert false
report lf &
"TO_SL found illegal input character: " &
to_int_str(x) & lf & "converting character to '-'"
severity warning;
return '-';
end case;
return r;
end to_sl;
function to_time (x: natural) return time is
begin
return x * 1 ns;
end to_time;
END conversions;
|
gpl-2.0
|
8f0f6d9c1f6e3d0faed9bbb8f0dc4c8b
| 0.443875 | 3.965225 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-xc3sd-1800/config.vhd
| 1 | 7,689 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (25);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#001234#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (125);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (32);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (128);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SVGA controller
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
2fada64cb4893801c097220c03576d9d
| 0.652751 | 3.579609 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/grlib/stdlib/stdio_tb.vhd
| 1 | 4,758 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--------------------------------------------------------------------------------
-- Package: StdIO
-- File: stdio.vhd
-- Author: Gaisler Research
-- Description: Package for common I/O functions
--------------------------------------------------------------------------------
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
library GRLIB;
use GRLIB.StdIO.all;
entity StdIO_TB is
end entity StdIO_TB;
architecture Behavioural of StdIO_TB is
begin
process
variable LW: Line;
variable LR: Line;
file WFile: Text;
file RFile: Text;
constant SUL: Std_ULogic := 'H';
constant SL: Std_Logic := 'L';
constant SULV1: Std_ULogic_Vector := "1";
constant SULV2: Std_ULogic_Vector := "10";
constant SULV3: Std_ULogic_Vector := "011";
constant SULV4: Std_ULogic_Vector := "0100";
constant SULV5: Std_ULogic_Vector := "00101";
constant SULV6: Std_ULogic_Vector := "000110";
constant SULV7: Std_ULogic_Vector := "0000111";
constant SULV8: Std_ULogic_Vector := "00001000";
constant SULV9: Std_ULogic_Vector := "000001001";
constant SULVA: Std_ULogic_Vector := "00000001001000110100010101100111";
constant SULVB: Std_ULogic_Vector := "10001001101010111100110111101111";
variable SULVC: Std_ULogic_Vector(0 to 3);
variable SULVD: Std_ULogic_Vector(0 to 7);
variable SULVE: Std_ULogic_Vector(0 to 15);
variable SULVF: Std_ULogic_Vector(0 to 16);
constant SLVA: Std_Logic_Vector := "00000001001000110100010101100111";
constant SLVB: Std_Logic_Vector := "10001001101010111100110111101111";
variable SLVC: Std_Logic_Vector(0 to 7);
variable SLVD: Std_Logic_Vector(0 to 15);
begin
Write(LW, SUL);
WriteLine(Output, LW);
Write(LW, SL);
WriteLine(Output, LW);
HWrite(LW, SULV1);
WriteLine(Output, LW);
HWrite(LW, SULV2);
WriteLine(Output, LW);
HWrite(LW, SULV3);
WriteLine(Output, LW);
HWrite(LW, SULV4);
WriteLine(Output, LW);
HWrite(LW, SULV5);
WriteLine(Output, LW);
HWrite(LW, SULV6);
WriteLine(Output, LW);
HWrite(LW, SULV7);
WriteLine(Output, LW);
HWrite(LW, SULV8);
WriteLine(Output, LW);
HWrite(LW, SULV9);
WriteLine(Output, LW);
HWrite(LW, SULVA);
WriteLine(Output, LW);
HWrite(LW, SULVB);
WriteLine(Output, LW);
File_Open(WFile, "file.txt", Write_Mode);
HWrite(LW, SULVA);
WriteLine(WFile, LW);
HWrite(LW, SULVB);
WriteLine(WFile, LW);
HWrite(LW, SULVA);
WriteLine(WFile, LW);
HWrite(LW, SULVB);
WriteLine(WFile, LW);
HWrite(LW, SLVA);
WriteLine(WFile, LW);
HWrite(LW, SLVB);
WriteLine(WFile, LW);
File_Close(WFile);
File_Open(RFile, "file.txt", Read_Mode);
ReadLine(RFile, LR);
HRead(LR, SULVC);
HWrite(LW, SULVC);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SULVD);
HWrite(LW, SULVD);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SULVE);
HWrite(LW, SULVE);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SULVF);
HWrite(LW, SULVF);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SLVC);
HWrite(LW, SLVC);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SLVD);
HWrite(LW, SLVD);
WriteLine(Output, LW);
File_Close(RFile);
wait;
end process;
end architecture Behavioural;
|
gpl-2.0
|
bc73f9dbfdf8014d4342a73b170867dd
| 0.582808 | 3.843296 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/synplify/sim/synplify.vhd
| 5 | 9,340 |
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 1997 by Synplicity, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Primitive library for post synthesis simulation --
-- These models are not intended for efficient synthesis --
-- --
-----------------------------------------------------------------------------
--pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
entity prim_counter is
generic (w : integer := 8);
port (
q : buffer std_logic_vector(w - 1 downto 0);
cout : out std_logic;
d : in std_logic_vector(w - 1 downto 0);
cin : in std_logic;
clk : in std_logic;
rst : in std_logic;
load : in std_logic;
en : in std_logic;
updn : in std_logic
);
end prim_counter;
architecture beh of prim_counter is
signal nextq : std_logic_vector(w - 1 downto 0);
begin
nxt: process (q, cin, updn)
variable i : integer;
variable nextc, c : std_logic;
begin
nextc := cin;
for i in 0 to w - 1 loop
c := nextc;
nextq(i) <= c xor (not updn) xor q(i);
nextc := (c and (not updn)) or
(c and q(i)) or
((not updn) and q(i));
end loop;
cout <= nextc;
end process;
ff : process (clk, rst)
begin
if rst = '1' then
q <= (others => '0');
elsif rising_edge(clk) then
q <= nextq;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity prim_dff is
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_dff;
architecture beh of prim_dff is
begin
ff : process (clk, r, s)
begin
if r = '1' then
q <= '0';
elsif s = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_1164.all;
entity prim_sdff is
port (q : out std_logic;
d : in std_logic;
c : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_sdff;
architecture beh of prim_sdff is
begin
ff : process(c)
begin
if rising_edge(c) then
if r = '1' then
q <= '0';
elsif s = '1' then
q <= '1';
else
q <= d;
end if;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity prim_latch is
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_latch;
architecture beh of prim_latch is
begin
q <= '0' when r = '1' else
'1' when s = '1' else
d when clk = '1';
end beh;
----------------------------------------------------------------------------
-- Zero ohm resistors: Hardi's solution to connect two inout ports.
----------------------------------------------------------------------------
-- Copyright (c) 1995, Ben Cohen. All rights reserved.
-- This model can be used in conjunction with the Kluwer Academic book
-- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0
-- "VHDL Amswers to Frequently Asked Questions", Kluwer Academic
-- which discusses guidelines and testbench design issues.
--
-- This source file for the ZERO Ohm resistor model may be used and
-- distributed without restriction provided that this copyright
-- statement is not removed from the file and that any derivative work
-- contains this copyright notice.
-- File name : Zohm_ea.vhd
-- Description: This package, entity, and architecture provide
-- the definition of a zero ohm component (A, B).
--
-- The applications of this component include:
-- . Normal operation of a jumper wire (data flowing in both directions)
--
-- The component consists of 2 ports:
-- . Port A: One side of the pass-through switch
-- . Port B: The other side of the pass-through switch
-- The model is sensitive to transactions on all ports. Once a
-- transaction is detected, all other transactions are ignored
-- for that simulation time (i.e. further transactions in that
-- delta time are ignored).
--
-- The width of the pass-through switch is defined through the
-- generic "width_g". The pass-through control and operation
-- is defined on a per bit basis (i.e. one process per bit).
--
-- Model Limitations and Restrictions:
-- Signals asserted on the ports of the error injector should not have
-- transactions occuring in multiple delta times because the model
-- is sensitive to transactions on port A, B ONLY ONCE during
-- a simulation time. Thus, once fired, a process will
-- not refire if there are multiple transactions occuring in delta times.
-- This condition may occur in gate level simulations with
-- ZERO delays because transactions may occur in multiple delta times.
--
--
-- Acknowledgement: The author thanks Steve Schoessow and Johan Sandstrom
-- for their contributions and discussions in the enhancement and
-- verification of this model.
--
--=================================================================
-- Revisions:
-- Date Author Revision Comment
-- 07-13-95 Ben Cohen Rev A Creation
-- [email protected]
-------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
entity ZeroOhm1 is
port
(A : inout Std_Logic;
B : inout Std_Logic
);
end ZeroOhm1;
architecture ZeroOhm1_a of ZeroOhm1 is
-- attribute syn_black_box : boolean;
-- attribute syn_feedthrough : boolean;
-- attribute syn_black_box of all : architecture is true;
-- attribute syn_feedthrough of all : architecture is true;
begin
ABC0_Lbl: process
variable ThenTime_v : time;
begin
wait on A'transaction, B'transaction
until ThenTime_v /= now;
-- Break
ThenTime_v := now;
A <= 'Z';
B <= 'Z';
wait for 0 ns;
-- Make
A <= B;
B <= A;
end process ABC0_Lbl;
end ZeroOhm1_a;
-------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity prim_ramd is
generic (
data_width : integer := 4;
addr_width : integer := 5);
port (
dout : out std_logic_vector(data_width-1 downto 0);
aout : in std_logic_vector(addr_width-1 downto 0);
din : in std_logic_vector(data_width-1 downto 0);
ain : in std_logic_vector(addr_width-1 downto 0);
we : in std_logic;
clk : in std_logic);
end prim_ramd;
architecture beh of prim_ramd is
constant depth : integer := 2** addr_width;
type mem_type is array (depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);
signal mem: mem_type;
begin
dout <= mem(conv_integer(aout));
process (clk)
begin
if rising_edge(clk) then
if (we = '1') then
mem(conv_integer(ain)) <= din;
end if;
end if;
end process;
end beh ;
library ieee;
use ieee.std_logic_1164.all;
package components is
component prim_counter
generic (w : integer);
port (
q : buffer std_logic_vector(w - 1 downto 0);
cout : out std_logic;
d : in std_logic_vector(w - 1 downto 0);
cin : in std_logic;
clk : in std_logic;
rst : in std_logic;
load : in std_logic;
en : in std_logic;
updn : in std_logic
);
end component;
component prim_dff
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_sdff
port(q : out std_logic;
d : in std_logic;
c : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_latch
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_ramd is
generic (
data_width : integer := 4;
addr_width : integer := 5);
port (
dout : out std_logic_vector(data_width-1 downto 0);
aout : in std_logic_vector(addr_width-1 downto 0);
din : in std_logic_vector(data_width-1 downto 0);
ain : in std_logic_vector(addr_width-1 downto 0);
we : in std_logic;
clk : in std_logic);
end component;
end components;
-- pragma translate_on
|
gpl-2.0
|
b58785c865eae7f07e75aad3e95159a6
| 0.543897 | 3.835729 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/grlib/amba/amba_tp.vhd
| 1 | 72,487 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : AMBA_TestPackage (Package and body declarations)
--
-- File name : amba_tp.vhd
--
-- Purpose : AMBA AHB and APB interface access procedures
--
-- Library : {independent}
--
-- Authors : Aeroflex Gaisler AB
--
-- Contact : mailto:[email protected]
-- http://www.aeroflex.com/gaisler
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--------------------------------------------------------------------------------
-- Version Author Date Changes
-- 0.1 SH 15 Mar 2002 New package
-- 0.2 SH 17 Mar 2003 Updated most packages
-- 0.3 SH 20 May 2003 Memory based on Integer elements
-- 0.4 SH 1 Jul 2003 Name of package changed
-- Compare function improved
-- AHB 32 bit memory with preload added
-- AHB initialisation added
-- 0.5 SH 21 Jul 2003 AHB 32 memory with diagnostics added
-- 0.6 SH 1 Nov 2003 APB read access data sample made earlier
-- AHB 32 memory extended with byte/halfword
-- 0.7 SH 25 Jan 2004 AHB read access data output corrected
-- AHB 32 memory allows overlay addressing
-- 1.7 SH 1 Oct 2004 Ported to GRLIB
-- 1.8 SH 1 Jul 2005 Added configuration support for memories
-- Modified all procedure declarations
-- 1.9 SH 10 Nov 2005 AHB 32 responds with HREADY=0 when error
-- 1.11 SH 27 Dec 2004 Split support added, using HSPLIT element
-- Proper two-cycle error response implemented
-- 1.12 SH 15 Feb 2006 Added bank select to AHB bus accesses
-- 1.13 SH 1 May 2009 AHBQuite gave incorrect TP on error resps.
--------------------------------------------------------------------------------
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
library GRLIB;
use GRLIB.AMBA.all;
use GRLIB.StdLib.all;
use GRLIB.StdIO.all;
package AMBA_TestPackage is
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBInit(
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
constant InstancePath: in String := "APBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True);
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBRead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- Initialise AMBA AHB interface
-----------------------------------------------------------------------------
procedure AHBInit(
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
constant InstancePath: in String := "AHBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWriteQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBRead";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- Diagnstics types for behavioural model of memory with AHB interface
-----------------------------------------------------------------------------
type AHB_Diagnostics_In_Type is
record
HADDR: Std_Logic_Vector(31 downto 0);
HWRITE: Std_ULogic;
HWDATA: Std_Logic_Vector(31 downto 0);
HRESP: Std_Logic_Vector(1 downto 0); -- response type
HSPLIT: Std_Logic_Vector(NAHBMST-1 downto 0); -- split completion
end record AHB_Diagnostics_In_Type;
type AHB_Diagnostics_Out_Type is
record
HRDATA: Std_Logic_Vector(31 downto 0);
end record AHB_Diagnostics_Out_Type;
constant AHB_Diagnostics_Init: AHB_Diagnostics_In_Type :=
(X"00000000", '0', X"00000000", HRESP_OKAY, zero32(NAHBMST-1 downto 0));
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory(
constant gAWidth: in Positive := 15; -- address width
constant gDWidth: in Positive := 8; -- data width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory";
constant ScreenOutput: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#);
-----------------------------------------------------------------------------
-- Behavioural model of memory with AMBA AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- file name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#);
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-- Supporting byte, halfword and word read/write accesses.
-- Provices diagnostic support.
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
signal AHBInDiag: in AHB_Diagnostics_In_Type;
signal AHBOutDiag: out AHB_Diagnostics_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- file name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#);
-----------------------------------------------------------------------------
-- Routine for writig data directly to AHB memory
-----------------------------------------------------------------------------
procedure WrAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RdAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RcAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Expected: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
-----------------------------------------------------------------------------
-- Routine for generating a split ack from AHB memory
-----------------------------------------------------------------------------
procedure SplitAHBMem32(
constant Split: in Integer range 0 to NAHBMST-1;
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
end AMBA_TestPackage;
--============================================================================--
package body AMBA_TestPackage is
-----------------------------------------------------------------------------
-- Compare function handling '-'
-----------------------------------------------------------------------------
function Compare(O, C: in Std_Logic_Vector) return Boolean is
variable T: Std_Logic_Vector(O'Range) := C;
variable Result: Boolean;
begin
Result := True;
for i in O'Range loop
if not (O(i)=T(i) or T(i)='-' or T(i)='U') then
Result := False;
end if;
end loop;
return Result;
end function Compare;
-----------------------------------------------------------------------------
-- Synchronisation with respect to clock and with output offset
-----------------------------------------------------------------------------
procedure Synchronise(
signal Clk: in Std_ULogic;
constant Offset: in Time := 5 ns) is
begin
wait until CLK = '1'; -- Synchronise
wait for Offset; -- output offset delay
end procedure Synchronise;
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBInit(
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
constant InstancePath: in String := "APBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True) is
variable L: Line;
begin
if cBack2Back then
Synchronise(PCLK);
end if;
APBIn.PSEL <= (others => '0');
APBIn.PENABLE <= '0';
APBIn.PADDR <= (others => '0');
APBIn.PWRITE <= '0';
APBIn.PWDATA <= (others => '0');
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : APB initalised"));
WriteLine(Output, L);
end if;
end procedure APBInit;
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(PCLK);
end if;
APBIn.PSEL <= (others => '0');
APBIn.PSEL(PINDEX) <= '1'; -- first clock period
APBIn.PENABLE <= '0';
APBIn.PADDR <= Address;
APBIn.PWRITE <= '1';
APBIn.PWDATA <= Data;
Synchronise(PCLK); -- second clock period
APBIn.PENABLE <= '1';
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : APB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
end if;
Synchronise(PCLK); -- end of access
APBIn.PSEL <= (others => '0');
APBIn.PENABLE <= '0';
APBIn.PADDR <= (others => '-');
APBIn.PWRITE <= '0';
APBIn.PWDATA <= (others => '-');
end procedure APBWrite;
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(PCLK);
end if;
APBIn.PSEL <= (others => '0');
APBIn.PSEL(PINDEX) <= '1'; -- first clock period
APBIn.PENABLE <= '0';
APBIn.PADDR <= Address;
APBIn.PWRITE <= '0';
APBIn.PWDATA <= (others => '-');
Synchronise(PCLK); -- second clock period
APBIn.PENABLE <= '1';
wait for 5 ns;
Data := APBOut.PRDATA;
Synchronise(PCLK); -- end of access
APBIn.PSEL <= (others => '0');
APBIn.PENABLE <= '0';
APBIn.PADDR <= (others => '-');
end procedure APBQuiet;
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBRead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
variable L: Line;
variable Temp: Std_Logic_Vector(31 downto 0);
begin
APBQuiet(Address, Temp, PCLK, APBIn, APBOut, TP, InstancePath, False, cBack2Back, PINDEX);
Data := Temp;
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : APB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Temp);
WriteLine(Output, L);
end if;
end procedure APBRead;
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
variable L: Line;
variable Data: Std_Logic_Vector(31 downto 0);
begin
APBQuiet(Address, Data, PCLK, APBIn, APBOut, TP, InstancePath, False, cBack2Back, PINDEX);
if not Compare(Data, CxData) then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
Write(L, String'(" : expected: "));
HWrite(L, CxData);
Write(L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
end if;
RxData := Data;
end procedure APBComp;
-----------------------------------------------------------------------------
-- Initialise AHB interface
-----------------------------------------------------------------------------
procedure AHBInit(
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
constant InstancePath: in String := "AHBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True) is
variable L: Line;
begin
if cBack2Back then
Synchronise(HCLK);
end if;
AHBIn.HSEL <= (others => '0');
AHBIn.HADDR <= (others => '0');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '0';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB initalised"));
WriteLine(Output, L);
end if;
end procedure AHBInit;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWriteQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK); -- first clock period
end if;
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= Address;
AHBIn.HWRITE <= '1';
AHBIn.HTRANS <= HTRANS_NONSEQ;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
Synchronise(HCLK); -- second clock period
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HWDATA <= ahbdrivedata(Data);
AHBIn.HREADY <= AHBOut.HREADY;
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
while AHBOut.HREADY='0' loop
Synchronise(HCLK);
end loop;
if AHBOut.HRESP=HRESP_ERROR then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" ERROR response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_RETRY then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" RETRY response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_SPLIT then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" SPLIT response "));
WriteLine(Output, L);
end if;
TP := False;
else
end if;
Synchronise(HCLK); -- end of access
AHBIn.HSEL <= (others => '0');
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '1';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
end procedure AHBWriteQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable OK: Boolean := True;
variable L: Line;
begin
AHBWriteQuiet(Address, Data, HCLK, AHBIn, AHBOut, OK,
InstancePath, False, cBack2Back, HINDEX, HMBINDEX);
if ScreenOutput and OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
elsif not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
end if;
end procedure AHBWrite;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= Address;
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_NONSEQ;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
Synchronise(HCLK); -- second clock period
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HREADY <= AHBOut.HREADY;
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
while AHBOut.HREADY='0' loop
Synchronise(HCLK);
end loop;
Data := AHBOut.HRDATA(31 downto 0);
if AHBOut.HRESP=HRESP_ERROR then
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" ERROR response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_RETRY then
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" RETRY response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_SPLIT then
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" SPLIT response "));
WriteLine(Output, L);
end if;
TP := False;
else
end if;
Synchronise(HCLK); -- end of access
AHBIn.HSEL <= (others => '0');
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
end procedure AHBQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBRead";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable OK: Boolean := True;
variable L: Line;
variable Temp: Std_Logic_Vector(31 downto 0);
begin
AHBQuiet(Address, Temp, HCLK, AHBIn, AHBOut, OK,
InstancePath, False, cBack2Back, HINDEX, HMBINDEX);
if ScreenOutput and OK then
Data := Temp;
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Temp);
WriteLine(Output, L);
elsif OK then
Data := Temp;
else
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
Data := (others => '-');
TP := False;
end if;
end procedure AHBRead;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable OK: Boolean := True;
variable L: Line;
variable Data: Std_Logic_Vector(31 downto 0);
variable Failed: Boolean;
begin
AHBQuiet(Address, Data, HCLK, AHBIn, AHBOut, OK,
InstancePath, False, cBack2Back, HINDEX, HMBINDEX);
if not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
RxData := (others => '-');
elsif not Compare(Data, CxData) then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
Write(L, String'(" : expected: "));
HWrite(L, CxData);
Write(L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
RxData := Data;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
RxData := Data;
else
RxData := Data;
end if;
end procedure AHBComp;
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory(
constant gAWidth: in Positive := 15; -- address width
constant gDWidth: in Positive := 8; -- data width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory";
constant ScreenOutput: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#) is
-- memory definition
subtype ARange is Natural range 0 to 2**gAWidth-1;
subtype DRange is Natural range 0 to gDWidth-1;
type MType is array (ARange) of Integer;
-- memory initialisation
function Init return MType is
variable r: MType;
begin
for i in ARange loop
r(i) := -1;
end loop;
return r;
end function Init;
variable M: MType;
variable A: Std_Logic_Vector(gAWidth-1 downto 0);
variable D: Std_Logic_Vector(0 to gDWidth-1);
variable W: Std_Logic;
-- reset values
procedure Reset is
begin
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= (others => '0');
W := '0';
end procedure Reset;
-- plug&play configuration
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg (0, 0, 0, gAWidth, 0),
4 => ahb_membar(HADDR, '1', '1', HMASK),
others => zero32);
variable alow : std_logic_vector(1 downto 0);
begin
-- fixed AMBA AHB signals, etc.
AHBOut.HSPLIT <= (others => '0');
AHBOut.HCONFIG <= HCONFIG;
loop
if HRESETn='0' then -- asynchronous reset
Reset;
elsif HCLK'Event and HCLK='1' then -- rising edge
-- data phase
if AHBIn.HREADY='1' then
if W='1' then
alow := A(1 downto 0);
case alow is
when "00" =>
D := AHBIn.HWDATA(31 downto 24);
when "01" =>
D := AHBIn.HWDATA(23 downto 16);
when "10" =>
D := AHBIn.HWDATA(15 downto 8);
when others =>
D := AHBIn.HWDATA( 7 downto 0);
end case;
M(Conv_Integer(A)) := Conv_Integer(D);
W := '0';
end if;
end if;
-- address phase
if AHBIn.HSEL(HINDEX)='1' and
AHBIn.HREADY='1' and
AHBIn.HSIZE=HSIZE_BYTE and
(AHBIn.HTRANS=HTRANS_SEQ or
AHBIn.HTRANS=HTRANS_NONSEQ) and
AHBIn.HMASTLOCK='0' then
W := AHBIn.HWRITE;
A := AHBIn.HADDR(gAWidth-1 downto 0);
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
D := Conv_Std_Logic_Vector(
M(Conv_Integer(A)), D'Length);
case alow is
when "00" =>
AHBOut.HRDATA(31 downto 24) <= D;
when "01" =>
AHBOut.HRDATA(23 downto 16) <= D;
when "10" =>
AHBOut.HRDATA(15 downto 8) <= D;
when others =>
AHBOut.HRDATA( 7 downto 0) <= D;
end case;
else
w :='0';
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
end if;
end if;
-- signal sensitivity
wait on HCLK, HRESETn;
end loop;
end procedure AHBMemory;
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- File name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#) is
-- memory definition
type MType is array (0 to 2**(gAWidth-2)-1) of
Std_Logic_Vector(31 downto 0);
--------------------------------------------------------------------------
-- Load memory contents
--------------------------------------------------------------------------
-- ## Does not warn if there is insufficient data in a line.
-- Address read from file is always byte oriented, always 32 bit wide
-- For 16 and 32 bit wide data, each data word read from file must be on a
-- single line and without white space between the characters. For 8 bit
-- wide date, no restrictions apply. Files generated for 32 bit wide data
-- can always be read by 16 or 8 bit memories. The byte/halfwrod address
-- is incremented internally.
--------------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- -- PROM Initialisation Example
-- -----------------------------------------------------------------------
-- -- Supports by 8, 16, 32 bit wide memories
-- 00000000 00010203
-- 00000004 04050607 08090A0B
-- 0000000C 0C0D0E0F
--
-- -- Supported by 8, 16 bit wide memories
-- 00000010 1011 1213
-- 00000014 1415
-- 00000016 1617 1819 1A1B 1C1D 1E1F 2021
-- 00000022 2223 2425 2627 2829 2A2B 2C2D 2E2F
--
-- -- Supported by 8 bit wide memories
-- 00000030 30 31 32 33 3435 3637 3839 3A3B 3C3D 3E3F
-- 00000040 40
-- 00000041 41
-- 00000042 42 43
-- 00000044 4445
-- 00000046 46474849
-- 0000004A 4A4B 4C4D4E4F
--------------------------------------------------------------------------
impure function Initialise(
constant FileName: in String := "";
constant AWidth: in Natural;
constant DWidth: in Natural)
return MType is
variable L: Line;
variable Address: Std_Logic_Vector(31 downto 0);
variable Data: Std_Logic_Vector(31 downto 0);
variable Byte: Std_Logic_Vector( 7 downto 0);
variable Addr: Natural range 0 to 2**AWidth-1;
file ReadFile: Text;
variable Test: Boolean;
variable Result: MType;
begin
-- initialse all data to all zeros
Result := (others => (others => 'U'));
-- load contents from file only if a file name has been provided
if FileName /= "" then
File_Open(ReadFile, FileName, Read_Mode);
-- read data from file
while not EndFile(ReadFile) loop
-- read line
ReadLine(ReadFile, L);
-- read address, always byte oriented, always 32 bit wide
HRead(L, Address, Test);
if Test then -- address read
-- check whether byte address aligned with data width
if Conv_Integer(Address) mod (DWidth/8) /= 0 then
report "Unaligned data in memory initalisation file: " &
FileName
severity Failure;
Test := False;
else -- convert address
-- adapt byte address to address corresponding to the data
-- width of the memory
Addr := (Conv_Integer(Address)/(DWidth/8)) mod
(2**AWidth);
end if;
else -- comment detected
null;
end if;
while Test loop
-- read data
HRead(L, Data(DWidth-1 downto 0), Test);
if Test then
-- initialize memory element
Result(Addr) := Data(DWidth-1 downto 0);
-- increment address, with the memory width
Addr := (Addr + 1) mod (2**AWidth);
end if;
end loop;
end loop;
File_Close(ReadFile);
end if;
return Result;
end function Initialise;
-- memory contents
variable M: MType := Initialise(FileName, gAWidth-2, 32);
variable A: Std_Logic_Vector(gAWidth-1 downto 2);
variable W: Std_Logic;
-- reset values
procedure Reset is
begin
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= (others => '0');
W := '0';
end procedure Reset;
-- plug&play configuration
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg (0, 0, 0, gAWidth, 0),
4 => ahb_membar(HADDR, '1', '1', HMASK),
others => zero32);
begin
-- fixed AMBA AHB signals, etc.
AHBOut.HSPLIT <= (others => '0');
AHBOut.HCONFIG <= HCONFIG;
loop
if HRESETn='0' then -- asynchronous reset
Reset;
elsif HCLK'Event and HCLK='1' then -- rising edge
-- data phase
if AHBIn.HREADY='1' then
if W='1' then
M(Conv_Integer(A)) := AHBIn.HWDATA(31 downto 0);
W := '0';
end if;
end if;
-- address phase
if AHBIn.HSEL(HINDEX)='1' and
AHBIn.HREADY='1' and
AHBIn.HSIZE=HSIZE_WORD and
(AHBIn.HTRANS=HTRANS_SEQ or
AHBIn.HTRANS=HTRANS_NONSEQ) and
AHBIn.HMASTLOCK='0' then
W := AHBIn.HWRITE;
A := AHBIn.HADDR(gAWidth-1 downto 2);
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= ahbdrivedata(M(Conv_Integer(A)));
else
W :='0';
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
end if;
end if;
-- signal sensitivity
wait on HCLK, HRESETn;
end loop;
end procedure AHBMemory32;
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-- Supporting byte, halfword and word read/write accesses.
-- Provices diagnostic support.
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
signal AHBInDiag: in AHB_Diagnostics_In_Type;
signal AHBOutDiag: out AHB_Diagnostics_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- File name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#) is
-- memory definition
type MType is array (0 to 2**(gAWidth-2)-1) of
Std_Logic_Vector(31 downto 0);
variable L: Line;
constant Padding: Std_ULogic_Vector(1 to
(4-((gAWidth-2) mod 4))) :=
(others => '0');
--------------------------------------------------------------------------
-- Load memory contents
--------------------------------------------------------------------------
-- ## Does not warn if there is insufficient data in a line.
-- Address read from file is always byte oriented, always 32 bit wide
-- For 16 and 32 bit wide data, each data word read from file must be on a
-- single line and without white space between the characters. For 8 bit
-- wide date, no restrictions apply. Files generated for 32 bit wide data
-- can always be read by 16 or 8 bit memories. The byte/halfwrod address
-- is incremented internally.
--------------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- -- PROM Initialisation Example
-- -----------------------------------------------------------------------
-- -- Supports by 8, 16, 32 bit wide memories
-- 00000000 00010203
-- 00000004 04050607 08090A0B
-- 0000000C 0C0D0E0F
--
-- -- Supported by 8, 16 bit wide memories
-- 00000010 1011 1213
-- 00000014 1415
-- 00000016 1617 1819 1A1B 1C1D 1E1F 2021
-- 00000022 2223 2425 2627 2829 2A2B 2C2D 2E2F
--
-- -- Supported by 8 bit wide memories
-- 00000030 30 31 32 33 3435 3637 3839 3A3B 3C3D 3E3F
-- 00000040 40
-- 00000041 41
-- 00000042 42 43
-- 00000044 4445
-- 00000046 46474849
-- 0000004A 4A4B 4C4D4E4F
--------------------------------------------------------------------------
impure function Initialise(
constant FileName: in String := "";
constant AWidth: in Natural;
constant DWidth: in Natural)
return MType is
variable L: Line;
variable Address: Std_Logic_Vector(31 downto 0);
variable Data: Std_Logic_Vector(31 downto 0);
variable Byte: Std_Logic_Vector( 7 downto 0);
variable Addr: Natural range 0 to 2**AWidth-1;
file ReadFile: Text;
variable Test: Boolean;
variable Result: MType;
begin
-- initialse all data to all zeros
Result := (others => (others => 'U'));
-- load contents from file only if a file name has been provided
if FileName /= "" then
File_Open(ReadFile, FileName, Read_Mode);
-- read data from file
while not EndFile(ReadFile) loop
-- read line
ReadLine(ReadFile, L);
-- read address, always byte oriented, always 32 bit wide
HRead(L, Address, Test);
if Test then -- address read
-- check whether byte address aligned with data width
if Conv_Integer(Address) mod (DWidth/8) /= 0 then
report "Unaligned data in memory initalisation file: " &
FileName
severity Failure;
Test := False;
else -- convert address
-- adapt byte address to address corresponding to the data
-- width of the memory
Addr := (Conv_Integer(Address)/(DWidth/8)) mod
(2**AWidth);
end if;
else -- comment detected
null;
end if;
while Test loop
-- read data
HRead(L, Data(DWidth-1 downto 0), Test);
if Test then
-- initialize memory element
Result(Addr) := Data(DWidth-1 downto 0);
-- increment address, with the memory width
Addr := (Addr + 1) mod (2**AWidth);
end if;
end loop;
end loop;
File_Close(ReadFile);
end if;
return Result;
end function Initialise;
-- memory contents
variable M: MType := Initialise(FileName, gAWidth-2, 32);
variable A: Std_Logic_Vector(gAWidth-1 downto 2);
variable B: Std_Logic_Vector(1 downto 0);
variable W: Std_Logic;
variable S: Std_Logic_Vector(2 downto 0);
variable D: Std_Logic_Vector(31 downto 0);
variable twocycle:Boolean := False;
-- reset values
procedure Reset is
begin
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= (others => '0');
W := '0';
twocycle := False;
end procedure Reset;
-- plug&play configuration
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg (0, 0, 0, gAWidth, 0),
4 => ahb_membar(HADDR, '1', '1', HMASK),
others => zero32);
begin
-- fixed AMBA AHB signals, etc.
AHBOut.HSPLIT <= (others => '0');
AHBOut.HCONFIG <= HCONFIG;
loop
if HRESETn='0' then -- asynchronous reset
Reset;
elsif HCLK'Event and HCLK='1' then -- rising edge
-- data phase
if AHBIn.HREADY='1' then
if W='1' then
-- read back memory
D := M(Conv_Integer(A));
-- replace with new data
if S="000" then -- byte
if B(1 downto 0)="00" then
D := AHBIn.HWDATA(31 downto 24) &
D(23 downto 0);
elsif B(1 downto 0)="01" then
D := D(31 downto 24) &
AHBIn.HWDATA(23 downto 16) &
D(15 downto 0);
elsif B(1 downto 0)="10" then
D := D(31 downto 16) &
AHBIn.HWDATA(15 downto 8) &
D(7 downto 0);
elsif B(1 downto 0)="11" then
D := D(31 downto 8) &
AHBIn.HWDATA(7 downto 0);
end if;
elsif S="001" then -- halfword
if B(1 downto 0)="00" then
D := AHBIn.HWDATA(31 downto 16) &
D(15 downto 0);
elsif B(1 downto 0)="10" then
D := D(31 downto 16) &
AHBIn.HWDATA(15 downto 0);
end if;
else
D := AHBIn.HWDATA(31 downto 0);
end if;
-- write back memory
M(Conv_Integer(A)) := D;
W := '0';
-- comment
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath & " Write acces to address :");
if Padding'Length > 0 and Padding'Length < 4 then
HWrite(L, Std_Logic_Vector(Padding) & Std_Logic_Vector(A));
else
HWrite(L, Std_Logic_Vector(A));
end if;
Write(L, String'(" data :"));
HWrite(L, D);
Write(L, String'(" data :"));
Write(L, To_BitVector(D));
Write(L, String'(" size :"));
HWrite(L, "0" & S);
WriteLine(Output, L);
end if;
end if;
end if;
-- address phase
if AHBIn.HSEL(HINDEX)='1' and
AHBIn.HREADY='1' and
(AHBIn.HSIZE=HSIZE_BYTE or
AHBIn.HSIZE=HSIZE_HWORD or
AHBIn.HSIZE=HSIZE_WORD) and
(AHBIn.HTRANS=HTRANS_SEQ or
AHBIn.HTRANS=HTRANS_NONSEQ) and
AHBIn.HMASTLOCK='0' then
if AHBInDiag.HRESP=HRESP_OKAY then
W := AHBIn.HWRITE;
S := AHBIn.HSIZE;
B := AHBIn.HADDR( 1 downto 0);
A := AHBIn.HADDR(gAWidth-1 downto 2);
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= ahbdrivedata(M(Conv_Integer(A)));
elsif AHBInDiag.HRESP=HRESP_RETRY then
W :='0';
AHBOut.HREADY <= '0';
AHBOut.HRESP <= HRESP_RETRY;
AHBOut.HRDATA <= (others => 'X');
twocycle := True;
elsif AHBInDiag.HRESP=HRESP_SPLIT then
W :='0';
AHBOut.HREADY <= '0';
AHBOut.HRESP <= HRESP_SPLIT;
AHBOut.HRDATA <= (others => 'X');
twocycle := True;
else
W :='0';
AHBOut.HREADY <= '0';
AHBOut.HRESP <= HRESP_ERROR;
AHBOut.HRDATA <= (others => 'X');
twocycle := True;
end if;
else
W :='0';
AHBOut.HREADY <= '1';
if twocycle then
twocycle := False;
else
AHBOut.HRESP <= HRESP_OKAY;
end if;
end if;
end if;
if HCLK'Event and HCLK='1' then -- rising edge
-- diagnostics
AHBOutDiag.HRData <= M((Conv_Integer(AHBInDiag.HAddr)/4) mod (2**(gAWidth-2)));
if AHBInDiag.HWrite='1' then
M((Conv_Integer(AHBInDiag.HAddr)/4) mod (2**(gAWidth-2))) := AHBInDiag.HWData;
-- Print("Diagnostic write to memory, address: " &
-- Integer'Image(Conv_Integer(AHBInDiag.HAddr)) &
-- " data: " &
-- Integer'Image(Conv_Integer(AHBInDiag.HWData)));
end if;
AHBOut.HSPLIT <= AHBInDiag.HSplit;
end if;
-- signal sensitivity
wait on HCLK, HRESETn;
end loop;
end procedure AHBMemory32;
-----------------------------------------------------------------------------
-- Routine for writig data directly to AHB memory
-----------------------------------------------------------------------------
procedure WrAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
if Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : WrAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(Data));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
AHBInDiag.HAddr <= Addr;
AHBInDiag.HWData <= Data;
AHBInDiag.HWrite <= '1';
Synchronise(HCLK);
AHBInDiag.HWrite <= '0';
end procedure WrAHBMem32;
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RdAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
AHBInDiag.HAddr <= Addr;
AHBInDiag.HWrite <= '0';
Synchronise(HCLK);
Data := AHBOutDiag.HRData;
if Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : RdAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(AHBOutDiag.HRData));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
end procedure RdAHBMem32;
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RcAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Expected: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable Data: Std_Logic_Vector(31 downto 0);
variable L: Line;
begin
Synchronise(HCLK);
AHBInDiag.HAddr <= Addr;
AHBInDiag.HWrite <= '0';
Synchronise(HCLK);
Data := AHBOutDiag.HRData;
if not Compare(Data, Expected) then
Write(L, Now, Right, 15);
Write(L, String'(" : RcAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(", value: "));
HWrite(L, Std_Logic_Vector(Data));
Write(L, String'(", expected: "));
HWrite(L, Std_Logic_Vector(Expected));
Write(L, String'(" # Error "));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
TP := False;
elsif Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : RcAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(Data));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(Expected));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
end procedure RcAHBMem32;
-----------------------------------------------------------------------------
-- Routine for generating a split ack from AHB memory
-----------------------------------------------------------------------------
procedure SplitAHBMem32(
constant Split: in Integer range 0 to NAHBMST-1;
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
AHBInDiag.HSPLIT <= (others => '0');
AHBInDiag.HSPLIT(Split) <= '1';
Synchronise(HCLK);
AHBInDiag.HSPLIT <= (others => '0');
if Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : SplitAHBMem32: split acknowledge to master: "));
Write(L, Split);
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
end procedure SplitAHBMem32;
end package body AMBA_TestPackage; --=========================================--
|
gpl-2.0
|
828bebd936fe47c2538efd2f5c23b5ed
| 0.444714 | 4.828604 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-digilent-atlys/leon3mp.vhd
| 1 | 31,663 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Jiri Gaisler, Gaisler Research
--
-- Modified by Joris van Rantwijk to support Digilent Atlys board.
--
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- led(6) = dsuact (LED 6 ON when processor in debug mode)
-- led(7) = not errorn (LED 7 ON when processor in error mode)
-- switch(6) = dsubre (SWITCH 6 ON to force DSU break)
-- switch(7) = dsuen (SWITCH 7 ON to enable debug mode)
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
library unisim;
use unisim.vcomponents.OBUFDS;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic; -- 100 MHz board clock
-- DDR2 memory
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_odt : out std_logic;
ddr_we : out std_ulogic;
ddr_ras : out std_ulogic;
ddr_cas : out std_ulogic;
ddr_dm : out std_logic_vector (1 downto 0);
ddr_dqs : inout std_logic_vector (1 downto 0);
ddr_dqsn : inout std_logic_vector (1 downto 0);
ddr_ad : out std_logic_vector (12 downto 0);
ddr_ba : out std_logic_vector (2 downto 0);
ddr_dq : inout std_logic_vector (15 downto 0);
ddr_rzq : inout std_ulogic;
ddr_zio : inout std_ulogic;
-- dsuen : in std_ulogic; -- switch(7)
-- dsubre : in std_ulogic; -- switch(6)
-- dsuact : out std_ulogic; -- led(6)
-- errorn : out std_ulogic; -- led(7)
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
-- GPIO
pmoda : inout std_logic_vector(7 downto 0);
switch : in std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0);
button : in std_logic_vector(4 downto 0);
-- MII Ethernet
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erst : out std_ulogic;
egtxclk : out std_ulogic;
emdc : out std_ulogic;
emdio : inout std_logic;
emdint : in std_ulogic;
-- PS/2
kbd_clk : inout std_logic;
kbd_data : inout std_logic;
mou_clk : inout std_logic;
mou_data : inout std_logic;
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : inout std_ulogic;
-- HDMI port
tmdstx_clk_p : out std_logic;
tmdstx_clk_n : out std_logic;
tmdstx_dat_p : out std_logic_vector(2 downto 0);
tmdstx_dat_n : out std_logic_vector(2 downto 0)
);
end entity;
architecture rtl of leon3mp is
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw : std_ulogic;
signal clk200 : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lock, calib_done, lclk : std_ulogic;
signal rstext : std_ulogic;
signal rstint : std_ulogic;
signal errorp : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddr2clk : std_ulogic;
signal ddr0_clk_fb : std_ulogic;
signal ddr0_clk : std_logic_vector(2 downto 0);
signal ddr0_clkb : std_logic_vector(2 downto 0);
signal ddr0_cke : std_logic_vector(1 downto 0);
signal ddr0_odt : std_logic_vector(1 downto 0);
signal ddr0_ad : std_logic_vector(13 downto 0);
signal ddr0_lock: std_ulogic;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal video_clk : std_logic;
signal video_fastclk : std_logic;
signal video_clksel : std_logic_vector(1 downto 0);
signal tmds_clk : std_logic;
signal tmds_dat : std_logic_vector(2 downto 0);
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 1;
-- constant DDR2_FREQ : integer := 150000; -- DDR2 input frequency in KHz
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_preserve of ddr2clk : signal is true;
attribute keep of ddr2clk : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of clkm : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
attribute syn_preserve of video_fastclk : signal is true;
attribute keep of video_fastclk : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (clkin => lclk, pciclkin => lclk,
clk => clkm, clkn => open, clk2x => open,
sdclk => open, pciclk => open,
cgi => cgi, cgo => cgo,
clk4x => open, clk1xu => open, clk2xu => clk200);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, rstext);
rst0 : rstgen -- reset generator
port map (rstint, clkm, lock, rstn, rstraw);
lock <= cgo.clklock and ddr0_lock;
-- Generate clean internal reset from external reset and watchdog.
rst1 : process (lclk, rstext) is
variable v_shift: std_logic_vector(3 downto 0);
variable v_wdog: std_logic_vector(2 downto 0);
begin
if rstext = '0' then
rstint <= '0';
v_shift := (others => '0');
v_wdog := (others => '0');
elsif rising_edge(lclk) then
rstint <= v_shift(0);
if CFG_GPT_WDOGEN /= 0 and v_wdog(0) = '1' then
v_shift := (others => '0');
else
v_shift := '1' & v_shift(3 downto 1);
end if;
if CFG_GPT_WDOGEN /= 0 then
v_wdog(0) := v_wdog(2) and not v_wdog(1);
v_wdog(1) := v_wdog(2);
v_wdog(2) := gpto.wdog;
end if;
end if;
end process;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 16)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
-- LED(7) = error
errorp <= not dbgo(0).error;
led1_pad : outpad generic map (tech => padtech) port map (led(7), errorp);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
-- SWITCH(7) = dsuen
dsuen_pad : inpad generic map (tech => padtech) port map (switch(7), dsui.enable);
-- SWITCH(6) = dsubre
dsubre_pad : inpad generic map (tech => padtech) port map (switch(6), dsui.break);
-- LED(6) = dsuact
dsuact_pad : outpad generic map (tech => padtech) port map (led(6), dsuo.active);
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mctrl_gen : if (CFG_MCTRL_LEON2 /= 0) generate
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
memi.data <= (others => '0'); -- Atlys board has no asynchronous memory bus
memi.sd <= (others => '0'); -- Atlys board has no classic SDRAM
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
-- pragma translate_on
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr_gen : if (CFG_DDR2SP = 1) generate
ddr0: ddr2spa
generic map (
fabtech => fabtech,
memtech => memtech,
rskew => 0,
hindex => 4,
haddr => 16#400#,
hmask => 16#f80#,
ioaddr => 16#001#,
iomask => 16#fff#,
MHz => CPU_FREQ/1000,
TRFC => CFG_DDR2SP_TRFC,
clkmul => 6,
clkdiv => 2,
col => CFG_DDR2SP_COL,
Mbyte => CFG_DDR2SP_SIZE,
rstdel => 200,
pwron => CFG_DDR2SP_INIT,
ddrbits => CFG_DDR2SP_DATAWIDTH,
ahbfreq => CPU_FREQ/1000,
readdly => 1,
norefclk => 0,
odten => 3,
dqsgating => 0,
nosync => CFG_DDR2SP_NOSYNC,
eightbanks => 1,
dqsse => 0,
burstlen => 8,
ft => CFG_DDR2SP_FTEN,
ftbits => CFG_DDR2SP_FTWIDTH,
bigmem => 0,
raspipe => 0 )
port map (
rst_ddr => rstraw,
rst_ahb => rstn,
clk_ddr => clkm,
clk_ahb => clkm,
clkref200 => clk200,
lock => ddr0_lock,
clkddro => ddr2clk,
clkddri => ddr2clk,
ahbsi => ahbsi,
ahbso => ahbso(4),
ddr_clk => ddr0_clk,
ddr_clkb => ddr0_clkb,
ddr_clk_fb_out => ddr0_clk_fb,
ddr_clk_fb => ddr0_clk_fb,
ddr_cke => ddr0_cke,
ddr_csb => open,
ddr_web => ddr_we,
ddr_rasb => ddr_ras,
ddr_casb => ddr_cas,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_dqsn => ddr_dqsn,
ddr_ad => ddr0_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
ddr_odt => ddr0_odt,
ce => open );
ddr_clk <= ddr0_clk(0);
ddr_clkb <= ddr0_clkb(0);
ddr_cke <= ddr0_cke(0);
ddr_odt <= ddr0_odt(0);
ddr_ad <= ddr0_ad(12 downto 0);
ddr_rzq <= 'Z';
ddr_zio <= 'Z';
end generate;
ddr_nogen : if (CFG_DDR2SP /= 1) generate
ddr0_lock <= '1';
ddrcke_nopad : outpad generic map (tech => padtech) port map (ddr_cke, gnd);
end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
-- Numonyx N25Q12 16 MByte SPI flash memory
spimc: if CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 3, hirq => 11, faddr => 16#e00#, fmask => 16#ff0#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(3), spmi, spmo);
miso_pad : inpad generic map (tech => padtech)
port map (spi_miso, spmi.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi, spmo.mosioen , spmi.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
spisel_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
u1i.ctsn <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
notxd : if CFG_UART1_ENABLE = 0 and CFG_AHB_UART = 0 generate
notxd_pad : outpad generic map (tech => padtech) port map (txd1, vcc);
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (kbd_clk, kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (kbd_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (mou_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (mou_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map (pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 32)
port map (rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
-- Map GPIO bits 0 to 5 to LEDS 0 to 5.
gpio_led_pads : outpadv
generic map (tech => padtech, width => 6)
port map (led(5 downto 0), gpioo.dout(5 downto 0));
-- Map GPIO bits 8 to 13 to SWITCHES 0 to 5.
gpio_sw_pads : inpadv
generic map (tech => padtech, width => 6)
port map (switch(5 downto 0), gpioi.din(13 downto 8));
-- Map GPIO bits 16 to 20 to BUTTONS 0 to 4.
gpio_button_pads : inpadv
generic map (tech => padtech, width => 5)
port map (button(4 downto 0), gpioi.din(20 downto 16));
-- Map GPIO bits 24 to 31 to PMODA port.
gpio_pmod_pads : for i in 0 to 7 generate
gpio_pmod_padi : iopad
generic map (tech => padtech)
port map (pmoda(i), gpioo.dout(24+i), gpioo.oen(24+i), gpioi.din(24+i));
end generate;
gpioi.din(7 downto 0) <= (others => '0');
gpioi.din(15 downto 14) <= (others => '0');
gpioi.din(23 downto 21) <= (others => '0');
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map (
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => 0)
port map (
rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => ethi, etho => etho);
etxc_pad : clkpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
emdint_pad : inpad generic map (tech => padtech)
port map (emdint, ethi.mdint);
end generate;
eth_nopads : if (CFG_GRETH /= 1) generate -- eth pads
etxd_nopad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, "00000000");
etxen_nopad : outpad generic map (tech => padtech)
port map (etx_en, '0');
etxer_nopad : outpad generic map (tech => padtech)
port map (etx_er, '0');
emdc_nopad : outpad generic map (tech => padtech)
port map (emdc, '0');
emdio_nopad : iopad generic map (tech => padtech)
port map (emdio, '0', '1', open);
end generate;
erst_pad : outpad generic map (tech => padtech)
port map (erst, rstraw);
egtxclk_pad : outpad generic map (tech => padtech)
port map (egtxclk, '0');
ethi.gtx_clk <= '0';
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP )
port map (rstn, clkm, ahbsi, ahbso(6));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- VGA / HDMI ------------------------------------------------------
-----------------------------------------------------------------------
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga
generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao);
video_clksel <= "00"; -- fixed 25 MHz
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl
generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
clk0 => 40000, clk1 => 25000, clk2 => 40000, clk3 => 25000,
burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao,
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH),
video_clksel);
end generate;
tmds : if CFG_VGA_ENABLE /= 0 or CFG_SVGA_ENABLE /= 0 generate
vgaclk0 : entity work.vga_clkgen
port map (resetn => rstraw, clk100 => lclk, sel => video_clksel,
vgaclk => video_clk, fastclk => video_fastclk);
tmds0 : entity work.vga2tmds
generic map (tech => fabtech)
port map (vgaclk => video_clk, fastclk => video_fastclk, vgao => vgao,
tmdsclk => tmds_clk, tmdsdat => tmds_dat );
tmdsc_pad : OBUFDS
port map (O => tmdstx_clk_p, OB => tmdstx_clk_n, I => tmds_clk);
tmdsd_pad : for i in 0 to 2 generate
tmdsdi_pad : OBUFDS
port map (O => tmdstx_dat_p(i), OB => tmdstx_dat_n(i), I => tmds_dat(i));
end generate;
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
tmdsc_pad : OBUFDS
port map (O => tmdstx_clk_p, OB => tmdstx_clk_n, I => gnd);
tmdsd_pad : for i in 0 to 2 generate
tmdsdi_pad : OBUFDS
port map (O => tmdstx_dat_p(i), OB => tmdstx_dat_n(i), I => gnd);
end generate;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Digilent-Atlys-XC6SLX45 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end architecture;
|
gpl-2.0
|
cc49674eb81a08a65b05cff54b296825
| 0.550769 | 3.588689 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-terasic-de0-nano/leon3mp.vhd
| 1 | 20,952 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2012 Aeroflex Gaisler
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
use gaisler.i2c.all;
use gaisler.spi.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS;
dbguart : integer := CFG_DUART;
pclow : integer := CFG_PCLOW
);
port (
clock_50 : in std_logic;
led : inout std_logic_vector(7 downto 0);
key : in std_logic_vector(1 downto 0);
sw : in std_logic_vector(3 downto 0);
dram_ba : out std_logic_vector(1 downto 0);
dram_dqm : out std_logic_vector(1 downto 0);
dram_ras_n : out std_ulogic;
dram_cas_n : out std_ulogic;
dram_cke : out std_ulogic;
dram_clk : out std_ulogic;
dram_we_n : out std_ulogic;
dram_cs_n : out std_ulogic;
dram_dq : inout std_logic_vector(15 downto 0);
dram_addr : out std_logic_vector(12 downto 0);
epcs_data0 : in std_ulogic;
epcs_dclk : out std_ulogic;
epcs_ncso : out std_ulogic;
epcs_asdo : out std_ulogic;
i2c_sclk : inout std_logic;
i2c_sdat : inout std_logic;
g_sensor_cs_n : out std_ulogic;
g_sensor_int : in std_ulogic;
adc_cs_n : out std_ulogic;
adc_saddr : out std_ulogic;
adc_sclk : out std_ulogic;
adc_sdat : in std_ulogic;
gpio_2 : inout std_logic_vector(12 downto 0);
gpio_2_in : in std_logic_vector(2 downto 0);
gpio_1_in : in std_logic_vector(1 downto 0);
gpio_1 : inout std_logic_vector(33 downto 0);
gpio_0_in : in std_logic_vector(1 downto 0);
gpio_0 : inout std_logic_vector(33 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc, gnd : std_logic_vector(4 downto 0);
signal clkm, rstn, rstraw, sdclkl, lclk, rst, clklck : std_ulogic;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal stati : ahbstat_in_type;
signal gpti : gptimer_in_type;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal gpio0i, gpio1i, gpio2i : gpio_in_type;
signal gpio0o, gpio1o, gpio2o : gpio_out_type;
signal dsubren : std_ulogic;
signal tck, tms, tdi, tdo : std_logic;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz, used in clkgen
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;
constant IOAEN : integer := 1;
constant OEPOL : integer := padoen_polarity(padtech);
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
clk_pad : clkpad generic map (tech => padtech) port map (clock_50, lclk);
clkgen0 : entity work.clkgen_de0
generic map (clk_mul => CFG_CLKMUL, clk_div => CFG_CLKDIV,
clk_freq => BOARD_FREQ, sdramen => CFG_SDCTRL)
port map (inclk0 => lclk, c0 => clkm, c0_2x => open, e0 => sdclkl,
locked => clklck);
sdclk_pad : outpad generic map (tech => padtech, slew => 1)
port map (dram_clk, sdclkl);
resetn_pad : inpad generic map (tech => padtech) port map (key(0), rst);
rst0 : rstgen -- reset generator (reset is active LOW)
port map (rst, clkm, clklck, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_JTAG,
nahbs => 6)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
----- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (led(6), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0,
kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (sw(0), dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (key(1), dsubren);
dsui.break <= not dsubren;
dsuact_pad : outpad generic map (tech => padtech) port map (led(7), dsuo.active);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
sdctrl0 : if CFG_SDCTRL = 1 generate -- 16-bit SDRAM controller
sdc : entity work.sdctrl16
generic map (hindex => 3, haddr => 16#400#, hmask => 16#FE0#,
ioaddr => 1, fast => 0, pwron => 0, invclk => 0,
sdbits => 16, pageburst => 2)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo);
sa_pad : outpadv generic map (width => 13, tech => padtech)
port map (dram_addr, sdo.address(14 downto 2));
ba0_pad : outpadv generic map (tech => padtech, width => 2)
port map (dram_ba, sdo.address(16 downto 15));
sd_pad : iopadvv generic map (width => 16, tech => padtech, oepol => OEPOL)
port map (dram_dq(15 downto 0), sdo.data(15 downto 0), sdo.vbdrive(15 downto 0), sdi.data(15 downto 0));
sdcke_pad : outpad generic map (tech => padtech)
port map (dram_cke, sdo.sdcke(0));
sdwen_pad : outpad generic map (tech => padtech)
port map (dram_we_n, sdo.sdwen);
sdcsn_pad : outpad generic map (tech => padtech)
port map (dram_cs_n, sdo.sdcsn(0));
sdras_pad : outpad generic map (tech => padtech)
port map (dram_ras_n, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (dram_cas_n, sdo.casn);
sddqm_pad : outpadv generic map (tech => padtech, width => 2)
port map (dram_dqm, sdo.dqm(1 downto 0));
end generate;
spimctrl0: if CFG_SPIMCTRL /= 0 generate -- SPI Memory Controller
spimc : spimctrl
generic map (hindex => 0, hirq => 10, faddr => 16#000#, fmask => 16#f00#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => OEPOL,sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD, dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT, scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER, pwrupcnt => CFG_SPIMCTRL_PWRUPCNT,
offset => CFG_SPIMCTRL_OFFSET)
port map (rstn, clkm, ahbsi, ahbso(0), spmi, spmo);
end generate;
nospimctrl0 : if CFG_SPIMCTRL = 0 generate spmo <= spimctrl_out_none; end generate;
miso_pad : inpad generic map (tech => padtech)
port map (epcs_data0, spmi.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (epcs_asdo, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (epcs_dclk, spmo.sck);
slvsel0_pad : outpad generic map (tech => padtech)
port map (epcs_ncso, spmo.csn);
----------------------------------------------------------------------
--- AHB ROM ---------------------------------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 and CFG_SPIMCTRL = 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map (rstn, clkm, ahbsi, ahbso(0));
end generate;
noprom : if CFG_AHBROMEN = 0 and CFG_SPIMCTRL = 0 generate
ahbso(0) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various peripherals ------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
apbo(0) <= apb_none; -- Typically occupied by memory controller
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, flow => 0,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
u1i.rxd <= '1';
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 4, paddr => 4, pmask => 16#FFF#,
pirq => 3, filter => 3, dynfilt => 1)
port map (rstn, clkm, apbi, apbo(4), i2ci, i2co);
end generate;
noi2cm: if CFG_I2C_ENABLE = 0 generate
i2co.scloen <= '1'; i2co.sdaoen <= '1';
i2co.scl <= '0'; i2co.sda <= '0';
end generate;
i2c_scl_pad : iopad generic map (tech => padtech)
port map (i2c_sclk, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (i2c_sdat, i2co.sda, i2co.sdaoen, i2ci.sda);
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 5, paddr => 5, pmask => 16#fff#, pirq => 5,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(5), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
spii.astart <= '0';
miso_pad : inpad generic map (tech => padtech)
port map (adc_sdat, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (adc_saddr, spio.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (adc_sclk, spio.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (adc_cs_n, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate
miso_pad : inpad generic map (tech => padtech)
port map (adc_sdat, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (adc_saddr, vcc(0));
sck_pad : outpad generic map (tech => padtech)
port map (adc_sclk, gnd(0));
slvsel_pad : outpad generic map (tech => padtech)
port map (adc_cs_n, vcc(0));
end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GRGPIO0 port
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpio0i, gpio0o);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio_0(i), gpio0o.dout(i), gpio0o.oen(i), gpio0i.din(i));
end generate;
end generate;
nogpio0: if CFG_GRGPIO_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
gpio1 : if CFG_GRGPIO2_ENABLE /= 0 generate -- GRGPIO1 port
grgpio1: grgpio
generic map( pindex => 10, paddr => 10, imask => CFG_GRGPIO2_IMASK, nbits => CFG_GRGPIO2_WIDTH)
port map( rstn, clkm, apbi, apbo(10), gpio1i, gpio1o);
pio_pads : for i in 0 to CFG_GRGPIO2_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio_1(i), gpio1o.dout(i), gpio1o.oen(i), gpio1i.din(i));
end generate;
end generate;
nogpio1: if CFG_GRGPIO2_ENABLE = 0 generate apbo(10) <= apb_none; end generate;
grgpio2: grgpio -- GRGPIO2 port
generic map( pindex => 11, paddr => 11, imask => 2**30, nbits => 31)
port map( rstn, clkm, apbi, apbo(11), gpio2i, gpio2o);
gpio_2_pads : iopadvv generic map (tech => padtech, width => 13)
port map (gpio_2(12 downto 0), gpio2o.dout(12 downto 0), gpio2o.oen(12 downto 0),
gpio2i.din(12 downto 0));
gpio_2_inpads : inpadv generic map (tech => padtech, width => 3)
port map (gpio_2_in, gpio2i.din(15 downto 13));
gpio_0_pads : iopadvv generic map (tech => padtech, width => 2)
port map (gpio_0(33 downto 32), gpio2o.dout(17 downto 16), gpio2o.oen(17 downto 16),
gpio2i.din(17 downto 16));
gpio_0_inpads : inpadv generic map (tech => padtech, width => 2)
port map (gpio_0_in, gpio2i.din(19 downto 18));
gpio_1_pads : iopadvv generic map (tech => padtech, width => 2)
port map (gpio_1(33 downto 32), gpio2o.dout(21 downto 20), gpio2o.oen(21 downto 20),
gpio2i.din(21 downto 20));
gpio_1_inpads : inpadv generic map (tech => padtech, width => 2)
port map (gpio_1_in, gpio2i.din(23 downto 22));
led_pads : iopadvv generic map (tech => padtech, width => 6)
port map (led(5 downto 0), gpio2o.dout(29 downto 24), gpio2o.oen(29 downto 24),
gpio2i.din(29 downto 24));
g_sensor_int_pad : inpad generic map (tech => padtech)
port map (g_sensor_int, gpio2i.din(30));
-- g_sensor_cs_n_pad : outpad generic map (tech => padtech)
-- port map (g_sensor_cs_n, gpio2o.dout(31));
g_sensor_cs_n <= '1';
-- gpio2i.din(31) <= gpio2o.dout(31);
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1, nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map (rstn, clkm, ahbsi, ahbso(4));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(4) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
-- pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera DE0-EP4CE22 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
41b5a947d40f6c821d88efbb677090b9
| 0.560137 | 3.598763 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/grlib/sparc/sparc_disas.vhd
| 1 | 27,772 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: sparc_disas
-- File: sparc_disas.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: SPARC disassembler according to SPARC V8 manual
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.testlib.print;
use std.textio.all;
package sparc_disas is
function tostf(v:std_logic_vector) return string;
procedure print_insn(ndx: integer; pc, op, res : std_logic_vector(31 downto 0);
valid, trap, wr, rest : boolean);
procedure print_fpinsn(ndx: integer; pc, op : std_logic_vector(31 downto 0);
res : std_logic_vector(63 downto 0);
dpres, valid, trap, wr : boolean);
function ins2st(pc, op : std_logic_vector(31 downto 0)) return string;
end;
package body sparc_disas is
type base_type is (hex, dec);
subtype nibble is std_logic_vector(3 downto 0);
type pc_op_type is record
pc, op : std_logic_vector(31 downto 0);
end record;
function tostd(v:std_logic_vector) return string;
function tosth(v:std_logic_vector) return string;
function tostrd(n:integer) return string;
function tohex(n:nibble) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
type carr is array (0 to 9) of character;
constant darr : carr := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
function tostd(v:std_logic_vector) return string is
variable s : string(1 to 2);
variable val : integer;
begin
val := conv_integer(v); s(1) := darr(val / 10); s(2) := darr(val mod 10);
return(s);
end;
function tosth(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(vlen-1 downto 0);
variable s : string(1 to slen);
begin
vv := v;
for i in slen downto 1 loop
s(i) := tohex(vv(3 downto 0));
vv(vlen-5 downto 0) := vv(vlen-1 downto 4);
end loop;
return(s);
end;
function tostf(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(vlen-1 downto 0);
variable s : string(1 to slen);
begin
vv := v;
for i in slen downto 1 loop
s(i) := tohex(vv(3 downto 0));
vv(vlen-5 downto 0) := vv(vlen-1 downto 4);
end loop;
return("0x" & s);
end;
function tostrd(n:integer) return string is
variable len : integer := 0;
variable tmp : string(10 downto 1);
variable v : integer := n;
begin
for i in 0 to 9 loop
tmp(i+1) := darr(v mod 10);
if tmp(i+1) /= '0' then
len := i;
end if;
v := v/10;
end loop;
return(tmp(len+1 downto 1));
end;
function ireg2st(v : std_logic_vector) return string is
variable ctmp : character;
variable reg : std_logic_vector(4 downto 0);
begin
reg := v;
case reg(4 downto 3) is
when "00" => ctmp := 'g'; when "01" => ctmp := 'o';
when "10" => ctmp := 'l'; when "11" => ctmp := 'i';
when others => ctmp := 'X';
end case;
if v(4 downto 0) = "11110" then return("%fp");
elsif v(4 downto 0) = "01110" then return("%sp");
else return('%' & ctmp & tost('0' & reg(2 downto 0))); end if;
end;
function simm13dec(insn : pc_op_type; base : base_type; merge : boolean) return string is
variable simm : std_logic_vector(12 downto 0) := insn.op(12 downto 0);
variable rs1 : std_logic_vector(4 downto 0) := insn.op(18 downto 14);
variable i : std_ulogic := insn.op(13);
variable sig : character;
variable fill : std_logic_vector(31 downto 13) := (others => simm(12));
begin
if i = '0' then
return("");
else
if (simm(12) = '1') and (base = dec) then
sig := '-'; simm := (not simm) + 1;
else
sig := '+';
end if;
if base = dec then
if merge then
if rs1 = "00000" then
return(tost(simm));
else
return(sig & tost(simm));
end if;
else
if rs1 = "00000" then
return(tost(simm));
else
if sig = '-' then
return(", " & sig & tost(simm));
else
return(", " & tost(simm));
end if;
end if;
end if;
else
if rs1 = "00000" then
if simm(12) = '1' then return(tost(fill & simm));
else return(tost(simm)); end if;
else
if simm(12) = '1' then return(", " & tost(fill & simm));
else return(", " & tost(simm)); end if;
end if;
end if;
end if;
end;
function freg2(insn : pc_op_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%f" & tostd(rs2) &
", %f" & tostd(rd));
end;
function creg3(insn : pc_op_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%c" & tostd(rs1) & ", %c" & tostd(rs2) & ", %c" & tostd(rd));
end;
function freg3(insn : pc_op_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%f" & tostd(rs1) & ", %f" & tostd(rs2) & ", %f" & tostd(rd));
end;
function fregc(insn : pc_op_type) return string is
variable rs1, rs2 : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
return("%f" & tostd(rs1) & ", %f" & tostd(rs2));
end;
function regimm(insn : pc_op_type; base : base_type; merge : boolean) return string is
variable rs1, rs2 : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
i := insn.op(13);
if i = '0' then
if (rs1 = "00000") then
if (rs2 = "00000") then return("0");
else return(ireg2st(rs2)); end if;
else
if (rs2 = "00000") then return(ireg2st(rs1));
elsif merge then return(ireg2st(rs1) & " + " & ireg2st(rs2));
else return(ireg2st(rs1) & ", " & ireg2st(rs2)); end if;
end if;
else
if (rs1 = "00000") then return(simm13dec(insn, base, merge));
elsif insn.op(12 downto 0) = "0000000000000" then return(ireg2st(rs1));
else return(ireg2st(rs1) & simm13dec(insn, base, merge)); end if;
end if;
end;
function regres(insn : pc_op_type; base : base_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rd := insn.op(29 downto 25);
return(regimm(insn, base,false) & ", " & ireg2st(rd ));
end;
function branchop(insn : pc_op_type) return string is
variable slice : std_logic_vector(28 downto 25);
begin
slice := insn.op(28 downto 25);
case slice is
when "0000" => return("n");
when "0001" => return("e");
when "0010" => return("le");
when "0011" => return("l");
when "0100" => return("leu");
when "0101" => return("cs");
when "0110" => return("neg");
when "0111" => return("vs");
when "1000" => return("a");
when "1001" => return("ne");
when "1010" => return("g");
when "1011" => return("ge");
when "1100" => return("gu");
when "1101" => return("cc");
when "1110" => return("pos");
when "1111" => return("vc");
when others => return("XXX");
end case;
end;
function fbranchop(insn : pc_op_type) return string is
variable slice : std_logic_vector(28 downto 25);
begin
slice := insn.op(28 downto 25);
case slice is
when "0000" => return("n");
when "0001" => return("ne");
when "0010" => return("lg");
when "0011" => return("ul");
when "0100" => return("l");
when "0101" => return("ug");
when "0110" => return("g");
when "0111" => return("u");
when "1000" => return("a");
when "1001" => return("e");
when "1010" => return("ue");
when "1011" => return("ge");
when "1100" => return("uge");
when "1101" => return("le");
when "1110" => return("ule");
when "1111" => return("o");
when others => return("XXX");
end case;
end;
function ldparcp(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & "%c" & tost(rd));
end;
function ldparf(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & "%f" & tostd(rd));
end;
function ldpar(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & ireg2st(rd));
end;
function ldpara(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & " " & tost(insn.op(12 downto 5)) & ", " & ireg2st(rd));
end;
function ldpara_cas(insn : pc_op_type; rs1, rs2, rd : std_logic_vector; base : base_type) return string is
begin
return("[" & ireg2st(rs1) & "]" & " " & tost(insn.op(12 downto 5)) & ", " &
ireg2st(rs2) & ", " & ireg2st(rd));
end;
function stparc(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
if rd = "00000" then
return("[" & regimm(insn,dec,true) & "]");
else
return(ireg2st(rd) & ", [" & regimm(insn,dec,true) & "]");
end if;
end;
function stparcp(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("%c" & tost(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stparf(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("%f" & tostd(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stpar(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return(ireg2st(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stpara(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return(ireg2st(rd) & ", [" & regimm(insn,dec,true) & "]" & " " & tost(insn.op(12 downto 5)));
end;
function ins2st(pc, op : std_logic_vector(31 downto 0)) return string is
constant STMAX : natural := 9;
constant bl2 : string(1 to 2) := (others => ' ');
constant bb : string(1 to 4) := (others => ' ');
variable op1 : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable opf : std_logic_vector(8 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable addr : std_logic_vector(31 downto 0);
variable annul : std_ulogic;
variable i : std_ulogic;
variable simm : std_logic_vector(12 downto 0);
variable insn : pc_op_type;
begin
op1 := op(31 downto 30);
op2 := op(24 downto 22);
op3 := op(24 downto 19);
opf := op(13 downto 5);
cond := op(28 downto 25);
annul := op(29);
rs1 := op(18 downto 14);
rs2 := op(4 downto 0);
rd := op(29 downto 25);
i := op(13);
simm := op(12 downto 0);
insn.op := op;
insn.pc := pc;
case op1 is
when CALL =>
addr := pc + (op(29 downto 0) & "00");
return(tostf(pc) & bb & "call" & bl2 & tost(addr));
when FMT2 =>
case op2 is
when SETHI =>
if rd = "00000" then
return(tostf(pc) & bb & "nop");
else
return(tostf(pc) & bb & "sethi" & bl2 & "%hi(" &
tost(op(21 downto 0) & "0000000000") & "), " & ireg2st(rd));
end if;
when BICC | FBFCC =>
addr(31 downto 24) := (others => '0');
addr(1 downto 0) := (others => '0');
addr(23 downto 2) := op(21 downto 0);
if addr(23) = '1' then
addr(31 downto 24) := (others => '1');
else
addr(31 downto 24) := (others => '0');
end if;
addr := addr + pc;
if op2 = BICC then
if op(29) = '1' then
return(tostf(pc) & bb & 'b' & branchop(insn) & ",a" & bl2 &
tost(addr));
else
return(tostf(pc) & bb & 'b' & branchop(insn) & bl2 &
tost(addr));
end if;
else
if op(29) = '1' then
return(tostf(pc) & bb & "fb" & fbranchop(insn) & ",a" & bl2 &
tost(addr));
else
return(tostf(pc) & bb & "fb" & fbranchop(insn) & bl2 &
tost(addr));
end if;
end if;
-- when CBCCC => cptrap := '1';
when others => return(tostf(pc) & bb & "unimp");
end case;
when FMT3 =>
case op3 is
when IAND => return(tostf(pc) & bb & "and" & bl2 & regres(insn,hex));
when IADD => return(tostf(pc) & bb & "add" & bl2 & regres(insn,dec));
when IOR =>
if ((i = '0') and (rs1 = "00000") and (rs2 = "00000")) then
return(tostf(pc) & bb & "clr" & bl2 & ireg2st(rd));
elsif ((i = '1') and (simm = "0000000000000")) or (rs1 = "00000") then
return(tostf(pc) & bb & "mov" & bl2 & regres(insn,hex));
else
return(tostf(pc) & bb & "or " & bl2 & regres(insn,hex));
end if;
when IXOR => return(tostf(pc) & bb & "xor" & bl2 & regres(insn,hex));
when ISUB => return(tostf(pc) & bb & "sub" & bl2 & regres(insn,dec));
when ANDN => return(tostf(pc) & bb & "andn" & bl2 & regres(insn,hex));
when ORN => return(tostf(pc) & bb & "orn" & bl2 & regres(insn,hex));
when IXNOR =>
if ((i = '0') and ((rs1 = rd) or (rs2 = "00000"))) then
return(tostf(pc) & bb & "not" & bl2 & ireg2st(rd));
else
return(tostf(pc) & bb & "xnor" & bl2 & ireg2st(rd));
end if;
when ADDX => return(tostf(pc) & bb & "addx" & bl2 & regres(insn,dec));
when SUBX => return(tostf(pc) & bb & "subx" & bl2 & regres(insn,dec));
when ADDCC => return(tostf(pc) & bb & "addcc" & bl2 & regres(insn,dec));
when ANDCC => return(tostf(pc) & bb & "andcc" & bl2 & regres(insn,hex));
when ORCC => return(tostf(pc) & bb & "orcc" & bl2 & regres(insn,hex));
when XORCC => return(tostf(pc) & bb & "xorcc" & bl2 & regres(insn,hex));
when SUBCC => return(tostf(pc) & bb & "subcc" & bl2 & regres(insn,dec));
when ANDNCC => return(tostf(pc) & bb & "andncc" & bl2 & regres(insn,hex));
when ORNCC => return(tostf(pc) & bb & "orncc" & bl2 & regres(insn,hex));
when XNORCC => return(tostf(pc) & bb & "xnorcc" & bl2 & regres(insn,hex));
when ADDXCC => return(tostf(pc) & bb & "addxcc" & bl2 & regres(insn,hex));
when UMAC => return(tostf(pc) & bb & "umac" & bl2 & regres(insn,dec));
when SMAC => return(tostf(pc) & bb & "smac" & bl2 & regres(insn,dec));
when UMUL => return(tostf(pc) & bb & "umul" & bl2 & regres(insn,dec));
when SMUL => return(tostf(pc) & bb & "smul" & bl2 & regres(insn,dec));
when UMULCC => return(tostf(pc) & bb & "umulcc" & bl2 & regres(insn,dec));
when SMULCC => return(tostf(pc) & bb & "smulcc" & bl2 & regres(insn,dec));
when SUBXCC => return(tostf(pc) & bb & "subxcc" & bl2 & regres(insn,dec));
when UDIV => return(tostf(pc) & bb & "udiv" & bl2 & regres(insn,dec));
when SDIV => return(tostf(pc) & bb & "sdiv" & bl2 & regres(insn,dec));
when UDIVCC => return(tostf(pc) & bb & "udivcc" & bl2 & regres(insn,dec));
when SDIVCC => return(tostf(pc) & bb & "sdivcc" & bl2 & regres(insn,dec));
when TADDCC => return(tostf(pc) & bb & "taddcc" & bl2 & regres(insn,dec));
when TSUBCC => return(tostf(pc) & bb & "tsubcc" & bl2 & regres(insn,dec));
when TADDCCTV => return(tostf(pc) & bb & "taddcctv" & bl2 & regres(insn,dec));
when TSUBCCTV => return(tostf(pc) & bb & "tsubcctv" & bl2 & regres(insn,dec));
when MULSCC => return(tostf(pc) & bb & "mulscc" & bl2 & regres(insn,dec));
when ISLL => return(tostf(pc) & bb & "sll" & bl2 & regres(insn,dec));
when ISRL => return(tostf(pc) & bb & "srl" & bl2 & regres(insn,dec));
when ISRA => return(tostf(pc) & bb & "sra" & bl2 & regres(insn,dec));
when RDY =>
if rs1 /= "00000" then
return(tostf(pc) & bb & "mov" & bl2 & "%asr" &
tostd(rs1) & ", " & ireg2st(rd));
else
return(tostf(pc) & bb & "mov" & bl2 & "%y, " & ireg2st(rd));
end if;
when RDPSR => return(tostf(pc) & bb & "mov" & bl2 & "%psr, " & ireg2st(rd));
when RDWIM => return(tostf(pc) & bb & "mov" & bl2 & "%wim, " & ireg2st(rd));
when RDTBR => return(tostf(pc) & bb & "mov" & bl2 & "%tbr, " & ireg2st(rd));
when WRY =>
if (rs1 = "00000") or (rs2 = "00000") then
if rd /= "00000" then
return(tostf(pc) & bb & "mov" & bl2
& regimm(insn,hex,false) & ", %asr" & tostd(rd));
else
return(tostf(pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %y");
end if;
else
if rd /= "00000" then
return(tostf(pc) & bb & "wr " & bl2 & "%asr"
& regimm(insn,hex,false) & ", %asr" & tostd(rd));
else
return(tostf(pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %y");
end if;
end if;
when WRPSR =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %psr");
else
return(tostf(pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %psr");
end if;
when WRWIM =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %wim");
else
return(tostf(pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %wim");
end if;
when WRTBR =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %tbr");
else
return(tostf(pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %tbr");
end if;
when JMPL =>
if (rd = "00000") then
if (i = '1') and (simm = "0000000001000") then
if (rs1 = "11111") then return(tostf(pc) & bb & "ret");
elsif (rs1 = "01111") then return(tostf(pc) & bb & "retl");
else return(tostf(pc) & bb & "jmp" & bl2 & regimm(insn,dec,true));
end if;
else return(tostf(pc) & bb & "jmp" & bl2 & regimm(insn,dec,true));
end if;
else return(tostf(pc) & bb & "jmpl" & bl2 & regres(insn,dec));
end if;
when TICC =>
return(tostf(pc) & bb & 't' & branchop(insn) & bl2 & regimm(insn,hex,false));
when FLUSH =>
return(tostf(pc) & bb & "flush" & bl2 & regimm(insn,hex,false));
when RETT =>
return(tostf(pc) & bb & "rett" & bl2 & regimm(insn,dec,true));
when RESTORE =>
if (rd = "00000") then
return(tostf(pc) & bb & "restore");
else
return(tostf(pc) & bb & "restore" & bl2 & regres(insn,hex));
end if;
when SAVE =>
if (rd = "00000") then return(tostf(pc) & bb & "save");
else return(tostf(pc) & bb & "save" & bl2 & regres(insn,dec)); end if;
when FPOP1 =>
case opf is
when FITOS => return(tostf(pc) & bb & "fitos" & bl2 & freg2(insn));
when FITOD => return(tostf(pc) & bb & "fitod" & bl2 & freg2(insn));
when FSTOI => return(tostf(pc) & bb & "fstoi" & bl2 & freg2(insn));
when FDTOI => return(tostf(pc) & bb & "fdtoi" & bl2 & freg2(insn));
when FSTOD => return(tostf(pc) & bb & "fstod" & bl2 & freg2(insn));
when FDTOS => return(tostf(pc) & bb & "fdtos" & bl2 & freg2(insn));
when FMOVS => return(tostf(pc) & bb & "fmovs" & bl2 & freg2(insn));
when FNEGS => return(tostf(pc) & bb & "fnegs" & bl2 & freg2(insn));
when FABSS => return(tostf(pc) & bb & "fabss" & bl2 & freg2(insn));
when FSQRTS => return(tostf(pc) & bb & "fsqrts" & bl2 & freg2(insn));
when FSQRTD => return(tostf(pc) & bb & "fsqrtd" & bl2 & freg2(insn));
when FADDS => return(tostf(pc) & bb & "fadds" & bl2 & freg3(insn));
when FADDD => return(tostf(pc) & bb & "faddd" & bl2 & freg3(insn));
when FSUBS => return(tostf(pc) & bb & "fsubs" & bl2 & freg3(insn));
when FSUBD => return(tostf(pc) & bb & "fsubd" & bl2 & freg3(insn));
when FMULS => return(tostf(pc) & bb & "fmuls" & bl2 & freg3(insn));
when FMULD => return(tostf(pc) & bb & "fmuld" & bl2 & freg3(insn));
when FSMULD => return(tostf(pc) & bb & "fsmuld" & bl2 & freg3(insn));
when FDIVS => return(tostf(pc) & bb & "fdivs" & bl2 & freg3(insn));
when FDIVD => return(tostf(pc) & bb & "fdivd" & bl2 & freg3(insn));
when others => return(tostf(pc) & bb & "unknown FOP1: " & tost(op));
end case;
when FPOP2 =>
case opf is
when FCMPS => return(tostf(pc) & bb & "fcmps" & bl2 & fregc(insn));
when FCMPD => return(tostf(pc) & bb & "fcmpd" & bl2 & fregc(insn));
when FCMPES => return(tostf(pc) & bb & "fcmpes" & bl2 & fregc(insn));
when FCMPED => return(tostf(pc) & bb & "fcmped" & bl2 & fregc(insn));
when others => return(tostf(pc) & bb & "unknown FOP2: " & tost(insn.op));
end case;
when CPOP1 =>
return(tostf(pc) & bb & "cpop1" & bl2 & tost("000"&opf) & ", " &creg3(insn));
when CPOP2 =>
return(tostf(pc) & bb & "cpop2" & bl2 & tost("000"&opf) & ", " &creg3(insn));
when others => return(tostf(pc) & bb & "unknown opcode: " & tost(insn.op));
end case;
when LDST =>
case op3 is
when STC =>
return(tostf(pc) & bb & "st" & bl2 & stparcp(insn, rd, dec));
when STF =>
return(tostf(pc) & bb & "st" & bl2 & stparf(insn, rd, dec));
when ST =>
if rd = "00000" then
return(tostf(pc) & bb & "clr" & bl2 & stparc(insn, rd, dec));
else
return(tostf(pc) & bb & "st" & bl2 & stpar(insn, rd, dec));
end if;
when STB =>
if rd = "00000" then
return(tostf(pc) & bb & "clrb" & bl2 & stparc(insn, rd, dec));
else
return(tostf(pc) & bb & "stb" & bl2 & stpar(insn, rd, dec));
end if;
when STH =>
if rd = "00000" then
return(tostf(pc) & bb & "clrh" & bl2 & stparc(insn, rd, dec));
else
return(tostf(pc) & bb & "sth" & bl2 & stpar(insn, rd, dec));
end if;
when STDC =>
return(tostf(pc) & bb & "std" & bl2 & stparcp(insn, rd, dec));
when STDF =>
return(tostf(pc) & bb & "std" & bl2 & stparf(insn, rd, dec));
when STCSR =>
return(tostf(pc) & bb & "st" & bl2 & "%csr, [" & regimm(insn,dec,true) & "]");
when STFSR =>
return(tostf(pc) & bb & "st" & bl2 & "%fsr, [" & regimm(insn,dec,true) & "]");
when STDCQ =>
return(tostf(pc) & bb & "std" & bl2 & "%cq, [" & regimm(insn,dec,true) & "]");
when STDFQ =>
return(tostf(pc) & bb & "std" & bl2 & "%fq, [" & regimm(insn,dec,true) & "]");
when ISTD =>
return(tostf(pc) & bb & "std" & bl2 & stpar(insn, rd, dec));
when STA =>
return(tostf(pc) & bb & "sta" & bl2 & stpara(insn, rd, dec));
when STBA =>
return(tostf(pc) & bb & "stba" & bl2 & stpara(insn, rd, dec));
when STHA =>
return(tostf(pc) & bb & "stha" & bl2 & stpara(insn, rd, dec));
when STDA =>
return(tostf(pc) & bb & "stda" & bl2 & stpara(insn, rd, dec));
when LDC =>
return(tostf(pc) & bb & "ld" & bl2 & ldparcp(insn, rd, dec));
when LDF =>
return(tostf(pc) & bb & "ld" & bl2 & ldparf(insn, rd, dec));
when LDCSR =>
return(tostf(pc) & bb & "ld" & bl2 & "[" & regimm(insn,dec,true) & "]" & ", %csr");
when LDFSR =>
return(tostf(pc) & bb & "ld" & bl2 & "[" & regimm(insn,dec,true) & "]" & ", %fsr");
when LD =>
return(tostf(pc) & bb & "ld" & bl2 & ldpar(insn, rd, dec));
when LDUB =>
return(tostf(pc) & bb & "ldub" & bl2 & ldpar(insn, rd, dec));
when LDUH =>
return(tostf(pc) & bb & "lduh" & bl2 & ldpar(insn, rd, dec));
when LDDC =>
return(tostf(pc) & bb & "ldd" & bl2 & ldparcp(insn, rd, dec));
when LDDF =>
return(tostf(pc) & bb & "ldd" & bl2 & ldparf(insn, rd, dec));
when LDD =>
return(tostf(pc) & bb & "ldd" & bl2 & ldpar(insn, rd, dec));
when LDSB =>
return(tostf(pc) & bb & "ldsb" & bl2 & ldpar(insn, rd, dec));
when LDSH =>
return(tostf(pc) & bb & "ldsh" & bl2 & ldpar(insn, rd, dec));
when LDSTUB =>
return(tostf(pc) & bb & "ldstub" & bl2 & ldpar(insn, rd, dec));
when SWAP =>
return(tostf(pc) & bb & "swap" & bl2 & ldpar(insn, rd, dec));
when LDA =>
return(tostf(pc) & bb & "lda" & bl2 & ldpara(insn, rd, dec));
when LDUBA =>
return(tostf(pc) & bb & "lduba" & bl2 & ldpara(insn, rd, dec));
when LDUHA =>
return(tostf(pc) & bb & "lduha" & bl2 & ldpara(insn, rd, dec));
when LDDA =>
return(tostf(pc) & bb & "ldda" & bl2 & ldpara(insn, rd, dec));
when LDSBA =>
return(tostf(pc) & bb & "ldsba" & bl2 & ldpara(insn, rd, dec));
when LDSHA =>
return(tostf(pc) & bb & "ldsha" & bl2 & ldpara(insn, rd, dec));
when LDSTUBA =>
return(tostf(pc) & bb & "ldstuba" & bl2 & ldpara(insn, rd, dec));
when SWAPA =>
return(tostf(pc) & bb & "swapa" & bl2 & ldpara(insn, rd, dec));
when CASA =>
return(tostf(pc) & bb & "casa" & bl2 & ldpara_cas(insn, rs1, rs2, rd, dec));
when others => return(tostf(pc) & bb & "unknown opcode: " & tost(op));
end case;
when others => return(tostf(pc) & bb & "unknown opcode: " & tost(op));
end case;
end;
procedure print_insn(ndx: integer; pc, op, res : std_logic_vector(31 downto 0);
valid, trap, wr, rest : boolean) is
begin
if valid then
if rest then grlib.testlib.print ("cpu" & tost(ndx) &": " & ins2st(pc, op) & " (restart)");
elsif trap then grlib.testlib.print ("cpu" & tost(ndx) &": " & ins2st(pc, op) & " (trapped)");
elsif wr then grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op) & " [" & tost(res) & "]");
else grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op)); end if;
end if;
end;
procedure print_fpinsn(ndx: integer; pc, op : std_logic_vector(31 downto 0);
res : std_logic_vector(63 downto 0);
dpres, valid, trap, wr : boolean) is
variable t : natural;
begin
if valid then
t := now / 1 ns;
if trap then grlib.testlib.print ("cpu" & tost(ndx) &": " & ins2st(pc, op) & " (trapped)");
elsif wr then
if dpres then grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op) & " [" & tost(res) & "]");
else grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op) & " [" & tost(res(63 downto 32)) & "]"); end if;
else grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op)); end if;
end if;
end;
end;
-- pragma translate_on
|
gpl-2.0
|
5f59a2ce58cef04c6c1a49a2f40158ff
| 0.563697 | 2.936971 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica06_SumadorRestador8Bits/topfa00txt.vhd
| 1 | 806 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use packagefa00.all;
entity topfa00 is
port(
C00: in std_logic ;
A00: in std_logic ;
B00: in std_logic ;
S00: out std_logic ;
C01: out std_logic );
end;
architecture topfa0 of topfa00 is
signal Sint1, Cint1, Cint2: std_logic;
begin
U00: topha00 port map(A0 => A00,
B0 => B00,
S0 => Sint1,
C0 => Cint1);
U01: topha00 port map(A0 => C00,
B0 => Sint1,
S0 => S00,
C0 => Cint2);
U02: or00 port map(Ao => Cint2,
Bo => Cint1,
Yo => C01);
end topfa0;
|
apache-2.0
|
bc07cc864e86d355cdd9f55b05107ccb
| 0.465261 | 3.224 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/eth/wrapper/greth_gbit_gen.vhd
| 1 | 13,705 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_gbit_gen
-- File: greth_gbit_gen.vhd
-- Author: Marko Isomaki
-- Description: Generic Gigabit Ethernet MAC
------------------------------------------------------------------------------
library ieee;
library grlib;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library eth;
use eth.ethcomp.all;
entity greth_gbit_gen is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 1;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--edcl ahb mst in
ehgrant : in std_ulogic;
ehready : in std_ulogic;
ehresp : in std_logic_vector(1 downto 0);
ehrdata : in std_logic_vector(31 downto 0);
--edcl ahb mst out
ehbusreq : out std_ulogic;
ehlock : out std_ulogic;
ehtrans : out std_logic_vector(1 downto 0);
ehaddr : out std_logic_vector(31 downto 0);
ehwrite : out std_ulogic;
ehsize : out std_logic_vector(2 downto 0);
ehburst : out std_logic_vector(2 downto 0);
ehprot : out std_logic_vector(3 downto 0);
ehwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
gtx_clk : in std_ulogic;
tx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(7 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
rx_en : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(7 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic;
gbit : out std_ulogic
);
end entity;
architecture rtl of greth_gbit_gen is
--host constants
constant fifosize : integer := 512;
constant fabits : integer := log2(fifosize);
constant fsize : std_logic_vector(fabits downto 0) :=
conv_std_logic_vector(fifosize, fabits+1);
--edcl constants
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits: integer := log2(edclbufsz) + 8;
constant ebufsize : integer := ebuf(log2(edclbufsz));
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(8 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(8 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(8 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(8 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
begin
gtxc0: greth_gbitc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
burstlength => burstlength,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
sim => sim,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => edclsepahbg,
ramdebug => ramdebug,
gmiimode => gmiimode
)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ehgrant,
ehready => ehready,
ehresp => ehresp,
ehrdata => ehrdata,
--edcl ahb mst out
ehbusreq => ehbusreq,
ehlock => ehlock,
ehtrans => ehtrans,
ehaddr => ehaddr,
ehwrite => ehwrite,
ehsize => ehsize,
ehburst => ehburst,
ehprot => ehprot,
ehwdata => ehwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
gtx_clk => gtx_clk,
tx_clk => tx_clk,
tx_dv => tx_dv,
rx_clk => rx_clk,
rxd => rxd,
rx_dv => rx_dv,
rx_er => rx_er,
rx_col => rx_col,
rx_crs => rx_crs,
rx_en => rx_en,
mdio_i => mdio_i,
phyrstaddr => phyrstaddr,
mdint => mdint,
--ethernet output signals
reset => reset,
txd => txd,
tx_en => tx_en,
tx_er => tx_er,
mdc => mdc,
mdio_o => mdio_o,
mdio_oe => mdio_oe,
--scantest
testrst => testrst,
testen => testen,
testoen => testoen,
edcladdr => edcladdr,
edclsepahb => edclsepahb,
edcldisable => edcldisable,
speed => speed,
gbit => gbit);
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, txrenable, txraddress(fabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(fabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
ft1 : if ft /= 0 generate
tx_fifo0 : syncram_2pft generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, txrenable, txraddress(fabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(fabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2pft generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
edclramft1 : if (edcl /= 0) and (edclft /= 0) generate
r0 : syncram_2pft generic map (memtech, eabits, 16, 0, 0, edclft) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2pft generic map (memtech, eabits, 16, 0, 0, edclft) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
end architecture;
|
gpl-2.0
|
35c11b2217b92a837e4efd6f6a188129
| 0.509595 | 4.160595 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml605/leon3mp.vhd
| 1 | 35,626 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.ml605.all;
use work.pcie.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
SIM_BYPASS_INIT_CAL : string := "OFF"
);
port (
reset : in std_ulogic;
errorn : out std_ulogic;
clk_ref_p : in std_logic;
clk_ref_n : in std_logic;
-- PROM interface
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(15 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
alatch : out std_ulogic;
-- DDR3 memory
ddr3_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr3_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr3_odt : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr3_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr3_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
-- AHB Uart
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- Ethernet signals
gmiiclk_p : in std_ulogic;
gmiiclk_n : in std_ulogic;
egtx_clk : out std_ulogic;
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emdio : inout std_logic;
erstn : out std_ulogic;
iic_scl_main : inout std_ulogic;
iic_sda_main : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
clk_33 : in std_ulogic; -- SYSACE clock
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_d : inout std_logic_vector(7 downto 0);
pci_exp_txp : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_txn : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxp : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxn : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- Output signals to LEDs
led : out std_logic_vector(6 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal lclk, clk_ddr, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
signal tb_rst : std_logic;
signal tb_clk : std_logic;
signal phy_init_done : std_logic;
signal lerrorn : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
-- VGA
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal clk100 : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
-- IIC
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
-- SYSACE
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
-- Used for connecting input/output signals to the DDR3 controller
signal migi : mig_app_in_type;
signal migo : mig_app_out_type;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clk_ddr : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_preserve of clk_ddr : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkm : signal is true;
attribute keep of clk_ddr : signal is true;
constant VCO_FREQ : integer := 1200000; -- MMCM VCO frequency in KHz
constant CPU_FREQ : integer := VCO_FREQ / CFG_MIG_CLK4; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
alatch <= '0';
erstn <= rstn;
-- Glitch free reset that can be used for the Eth Phy and flash memory
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE+CFG_PCIEXP,
nahbs => 9)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
lerrorn <= dbgo(0).error and rstn;
error_pad : odpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (errorn, lerrorn);
dsugen : if CFG_DSU = 1 generate
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (level => cmos, voltage => x15v, tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
led(2) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsutx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, iomask => 0, rammask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
roms_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (romsn, vcc);
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 24)
port map (address, memo.address(24 downto 1));
roms_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (writen, memo.writen);
end generate;
bdr : iopadvv generic map (level => cmos, voltage => x25v, tech => padtech, width => 16)
port map (data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
----------------------------------------------------------------------
--- DDR3 memory controller ------------------------------------------
----------------------------------------------------------------------
-- mig_gen : if (CFG_MIG_DDR2 = 1) generate
ahb2mig0 : ahb2mig_ml605
generic map ( hindex => 0, haddr => 16#400#, hmask => 16#E00#,
MHz => 400, Mbyte => 512, nosync => boolean'pos(CFG_MIG_CLK4=12)) --CFG_CLKDIV/12)
port map (
rst => rstn, clk_ahb => clkm, clk_ddr => clk_ddr,
ahbsi => ahbsi, ahbso => ahbso(0), migi => migi, migo => migo);
ddr3ctrl : entity work.mig_37
generic map (SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,CLKOUT_DIVIDE4 => work.config.CFG_MIG_CLK4)
port map(
clk_ref_p => clk_ref_p,
clk_ref_n => clk_ref_n,
ddr3_dq => ddr3_dq,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_cs_n => ddr3_cs_n,
ddr3_odt => ddr3_odt,
ddr3_cke => ddr3_cke,
ddr3_dm => ddr3_dm,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
app_wdf_wren => migi.app_wdf_wren,
app_wdf_data => migi.app_wdf_data,
app_wdf_mask => migi.app_wdf_mask,
app_wdf_end => migi.app_wdf_end,
app_addr => migi.app_addr,
app_cmd => migi.app_cmd,
app_en => migi.app_en,
app_rdy => migo.app_rdy,
app_wdf_rdy => migo.app_wdf_rdy,
app_rd_data => migo.app_rd_data,
app_rd_data_valid => migo.app_rd_data_valid,
tb_rst => open,
tb_clk => clk_ddr,
clk_ahb => clkm,
clk100 => clk100,
phy_init_done => phy_init_done,
sys_rst_13 => reset,
sys_rst_14 => rstraw
);
led(3) <= phy_init_done;
led(4) <= rstn;
led(5) <= reset;
led(6) <= '0';
lock <= phy_init_done; -- and cgo.clklock;
-- end generate;
-- noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate lock <= cgo.clklock; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 7, hirq => 10, mode => 2,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(7), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
clk_33_pad : clkpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (clk_33, clkace);
sysace_mpa_pads : outpadv generic map (level => cmos, voltage => x25v, width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_d_pads : iopadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 8)
port map (sysace_d(7 downto 0), aceo.do(7 downto 0), aceo.doen, acei.di(7 downto 0));
acei.di(15 downto 8) <= (others => '0');
sysace_mpoe_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpirq, acei.irq);
-----------------PCI-EXPRESS-Master-Target------------------------------------------
pcie_mt : if CFG_PCIE_TYPE = 1 generate -- master/target without fifo
EP: pcie_master_target_virtex
generic map (
fabtech => fabtech,
hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE,
hslvndx => 8,
abits => 21,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
pcie_bar_mask => 16#FFE#,
nsync => 2, -- 1 or 2 sync regs between clocks
haddr => 16#a00#,
hmask => 16#fff#,
pindex => 5,
paddr => 5,
pmask => 16#fff#,
Master => CFG_PCIE_SIM_MAS,
lane_width => CFG_NO_OF_LANES
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(8),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5),
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE)
);
end generate;
------------------PCI-EXPRESS-Master-FIFO------------------------------------------
pcie_mf : if CFG_PCIE_TYPE = 3 generate -- master with fifo and DMA
dma:pciedma
generic map (fabtech => fabtech, memtech => memtech, dmstndx =>(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE),
dapbndx => 8, dapbaddr => 8,dapbirq => 8, blength => 12, abits => 21,
device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID, pcie_bar_mask => 16#FFE#,
slvndx => 8, apbndx => 5, apbaddr => 5, haddr => 16#A00#,hmask=> 16#FFF#,
nsync => 2,lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
dapbo => apbo(8),
dahbmo => ahbmo((CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE)),
apbi => apbi,
apbo => apbo(5),
ahbmi => ahbmi,
ahbsi => ahbsi,
ahbso => ahbso(8)
);
end generate;
----------------------------------------------------------------------
pcie_mf_no_dma: if CFG_PCIE_TYPE = 2 generate -- master with fifo
EP:pcie_master_fifo_virtex
generic map (fabtech => fabtech, memtech => memtech,
hslvndx => 8, abits => 21, device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID,
pcie_bar_mask => 16#FFE#, pindex => 5, paddr => 5,
haddr => 16#A00#, hmask => 16#FFF#, nsync => 2, lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(8),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5)
);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
serrx_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurx, rxd1);
sertx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsutx, txd1);
led(0) <= not rxd1;
led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (iic_scl_main, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (iic_sda_main, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- VGA + IIC --------------------------------------------------------
-----------------------------------------------------------------------
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, clk0 => 40000,
clk1 => 24000, clk2 => 20000, clk3 => 16000, burstlen => 4,
ahbaccsz => CFG_AHBDW)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : entity work.svga2ch7301c generic map (tech => fabtech, idf => 2)
port map (clk100, ethi.gtx_clk, lock, clk_sel, vgao, clkvga, clkvga_p, clkvga_n,
lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 7, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none;
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
tft_lcd_data_pad : outpadv generic map (level => cmos, voltage => x25v, width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
end generate;
-- greth1g: if CFG_GRETH1G = 1 generate
gtxclk0 : entity work.gtxclk port map (
clk_p => gmiiclk_p, clk_n => gmiiclk_n, clkint => ethi.gtx_clk,
clkout => egtx_clk);
-- end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (level => cmos, voltage => x25v, tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (level => cmos, voltage => x25v, tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_crs, ethi.rx_crs);
emdint_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (emdint, ethi.mdint);
etxd_pad : outpadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1+CFG_PCIEXP) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Xilinx Virtex6 ML605 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
|
gpl-2.0
|
1685669b5774b8aba3d20ce6fef5d021
| 0.543901 | 3.464216 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/leon3v3/leon3x.vhd
| 1 | 15,407 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Entity: leon3x
-- File: leon3x.vhd
-- Author: Jiri Gaisler, Jan Andersson, Aeroflex Gaisler
-- Description: Top-level LEON3v3 component with all options
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
use gaisler.arith.all;
entity leon3x is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0;
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
clk2x : integer := 1;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end;
architecture rtl of leon3x is
constant IRFBITS : integer range 6 to 10 := log2(NWINDOWS+1) + 4;
constant IREGNUM : integer := NWINDOWS * 16 + 8;
constant IRFWT : integer := 1;--regfile_3p_write_through(memtech);
constant fpuarch : integer := fpu mod 16;
constant fpunet : integer := (fpu mod 32) / 16;
constant fpushared : boolean := (fpu / 32) /= 0;
constant FTSUP : integer := 0
;
-- Create an array length mismatch error if the user tries to enable FT
-- features in non-FT release.
constant dummy_ft_consistency_check:
std_logic_vector(FTSUP*(iuft+fpft+cmft) downto (iuft+fpft+cmft)) := "0";
signal holdn : std_logic;
signal rfi : iregfile_in_type;
signal rfo : iregfile_out_type;
signal crami : cram_in_type;
signal cramo : cram_out_type;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal tbi_2p : tracebuf_2p_in_type;
signal tbo_2p : tracebuf_2p_out_type;
signal rst : std_ulogic;
signal fpi : fpc_in_type;
signal fpo : fpc_out_type;
signal cpi : fpc_in_type;
signal cpo : fpc_out_type;
signal gnd, vcc : std_logic;
attribute sync_set_reset : string;
attribute sync_set_reset of rst : signal is "true";
begin
gnd <= '0'; vcc <= '1';
vhdl : if netlist = 0 generate
-- leon3 processor core (iu, caches & mul/div)
p0 : proc3
generic map (
hindex, fabtech, memtech, nwindows, dsu, fpuarch, v8, cp, mac, pclow,
notag, nwp, icen, irepl, isets, ilinesize, isetsize, isetlock, dcen,
drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram, ilramsize,
ilramstart, dlram, dlramsize, dlramstart, mmuen, itlbnum, dtlbnum,
tlb_type, tlb_rep, lddel, disas, tbuf, pwd, svt, rstaddr, smp,
cached, clk2x, scantest, mmupgsz, bp, npasi, pwrpsr)
port map (gclk2, rst, holdn, ahbi, ahbo, ahbsi, ahbso, rfi, rfo, crami, cramo,
tbi, tbo, tbi_2p, tbo_2p, fpi, fpo, cpi, cpo, irqi, irqo, dbgi, dbgo, clk, clk2, clken
);
-- IU register file
rf0 : regfile_3p_l3 generic map (memtech, IRFBITS, 32, IRFWT, IREGNUM,
scantest)
port map (gclk2, rfi.waddr(IRFBITS-1 downto 0), rfi.wdata, rfi.wren,
gclk2, rfi.raddr1(IRFBITS-1 downto 0), rfi.ren1, rfo.data1,
rfi.raddr2(IRFBITS-1 downto 0), rfi.ren2, rfo.data2,
ahbi.testin
);
-- cache memory
cmem0 : cachemem
generic map (memtech, icen, irepl, isets, ilinesize, isetsize, isetlock, dcen,
drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram,
ilramsize, dlram, dlramsize, mmuen, scantest
)
port map (gclk2, crami, cramo, clk2, ahbi.testin
);
-- instruction trace buffer memory
tbmem_gen : if (tbuf /= 0) generate
tbmem_1p : if (tbuf <= 64) generate
tbmem0 : tbufmem
generic map (tech => memtech, tbuf => tbuf, dwidth => 32, testen => scantest)
port map (gclk2, tbi, tbo, ahbi.testin
);
tbo_2p <= tracebuf_2p_out_type_none;
end generate;
tbmem_2p: if (tbuf > 64) generate
tbmem0 : tbufmem_2p
generic map (tech => memtech, tbuf => (tbuf-64), dwidth => 32, testen => scantest)
port map (gclk2, tbi_2p, tbo_2p, ahbi.testin
);
tbo <= tracebuf_out_type_none;
end generate;
end generate;
notbmem_gen : if (tbuf = 0) generate
tbo <= tracebuf_out_type_none;
tbo_2p <= tracebuf_2p_out_type_none;
end generate;
-- FPU
fpu0 : if (fpu = 0) generate
fpo <= fpc_out_none;
end generate;
fpshare : if fpushared generate
grfpw0gen : if (fpuarch > 0) and (fpuarch < 8) generate
fpu0: grfpwxsh
generic map (memtech, pclow, dsu, disas, hindex,
scantest
)
port map (rst, gclk2, holdn, fpi, fpo, fpui, fpuo, ahbi.testin
);
end generate;
nogrfpw0gen : if not ((fpuarch > 0) and (fpuarch < 8)) generate
fpui <= grfpu_in_none;
end generate;
end generate;
nofpshare : if not fpushared generate
grfpw1gen : if (fpuarch > 0) and (fpuarch < 8) generate
fpu0: grfpwx
generic map (fabtech, memtech, (fpuarch-1), pclow, dsu, disas,
fpunet, hindex, scantest)
port map (rst, gfclk2, holdn, fpi, fpo, ahbi.testin
);
end generate;
grlfpc1gen : if (fpuarch >=8) and (fpuarch < 15) generate
fpu0 : grlfpwx
generic map (memtech, pclow, dsu, disas,
(fpuarch-8), fpunet, hindex, scantest)
port map (rst, gfclk2, holdn, fpi, fpo, ahbi.testin
);
end generate;
fpui <= grfpu_in_none;
end generate;
-- CP
cpo <= fpc_out_none;
-- 1-clock reset delay
rstreg : process(gclk2)
begin if rising_edge(gclk2) then rst <= rstn; end if; end process;
end generate vhdl;
ntl : if netlist /= 0 generate
l3net : leon3_net
generic map (
hindex => hindex,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu,
v8 => v8,
cp => cp,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
iuft => iuft,
fpft => fpft,
cmft => cmft,
cached => cached,
clk2x => clk2x,
scantest => scantest,
mmupgsz => mmupgsz,
bp => bp,
npasi => npasi,
pwrpsr => pwrpsr)
port map (
clk => clk,
gclk2 => gclk2,
gfclk2 => gfclk2,
clk2 => clk2,
rstn => rstn,
ahbi => ahbi,
ahbo => ahbo,
ahbsi => ahbsi,
--ahbso => ahbso,
irqi_irl => irqi.irl,
irqi_rst => irqi.rst,
irqi_run => irqi.run,
irqi_rstvec => irqi.rstvec,
irqi_iact => irqi.iact,
irqi_index => irqi.index,
irqi_hrdrst => irqi.hrdrst,
irqo_intack => irqo.intack,
irqo_irl => irqo.irl,
irqo_pwd => irqo.pwd,
irqo_fpen => irqo.fpen,
irqo_idle => irqo.idle,
dbgi_dsuen => dbgi.dsuen,
dbgi_denable => dbgi.denable,
dbgi_dbreak => dbgi.dbreak,
dbgi_step => dbgi.step,
dbgi_halt => dbgi.halt,
dbgi_reset => dbgi.reset,
dbgi_dwrite => dbgi.dwrite,
dbgi_daddr => dbgi.daddr,
dbgi_ddata => dbgi.ddata,
dbgi_btrapa => dbgi.btrapa,
dbgi_btrape => dbgi.btrape,
dbgi_berror => dbgi.berror,
dbgi_bwatch => dbgi.bwatch,
dbgi_bsoft => dbgi.bsoft,
dbgi_tenable => dbgi.tenable,
dbgi_timer => dbgi.timer,
dbgo_data => dbgo.data,
dbgo_crdy => dbgo.crdy,
dbgo_dsu => dbgo.dsu,
dbgo_dsumode => dbgo.dsumode,
dbgo_error => dbgo.error,
dbgo_halt => dbgo.halt,
dbgo_pwd => dbgo.pwd,
dbgo_idle => dbgo.idle,
dbgo_ipend => dbgo.ipend,
dbgo_icnt => dbgo.icnt,
dbgo_fcnt => dbgo.fcnt,
dbgo_optype => dbgo.optype,
dbgo_bpmiss => dbgo.bpmiss,
dbgo_istat_cmiss => dbgo.istat.cmiss,
dbgo_istat_tmiss => dbgo.istat.tmiss,
dbgo_istat_chold => dbgo.istat.chold,
dbgo_istat_mhold => dbgo.istat.mhold,
dbgo_dstat_cmiss => dbgo.dstat.cmiss,
dbgo_dstat_tmiss => dbgo.dstat.tmiss,
dbgo_dstat_chold => dbgo.dstat.chold,
dbgo_dstat_mhold => dbgo.dstat.mhold,
dbgo_wbhold => dbgo.wbhold,
dbgo_su => dbgo.su,
--fpui => fpui,
--fpuo => fpuo,
clken => clken);
end generate ntl;
-- pragma translate_off
bootmsg : report_version
generic map (
"leon3_" & tost(hindex) & ": LEON3 SPARC V8 processor rev " & tost(LEON3_VERSION)
& ": iuft: " & tost(iuft) & ", fpft: " & tost(fpft) & ", cacheft: " & tost(cmft)
, "leon3_" & tost(hindex) & ": icache " & tost(isets*icen) & "*" & tost(isetsize*icen) &
" kbyte, dcache " & tost(dsets*dcen) & "*" & tost(dsetsize*dcen) & " kbyte"
);
-- pragma translate_on
end;
|
gpl-2.0
|
682326438248e570e182e8388ee5c7b9
| 0.495165 | 3.897546 | false | true | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-asic/spw_lvttl_pads.vhd
| 1 | 4,471 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Copyright (C) 2009-2013, Aeroflex Gaisler AB
-------------------------------------------------------------------------------
-- Entity: spw_2x_lvttl_pads
-- File: spw_2x_lvttl_pads.vhd
-- Author: Marko Isomaki, Aeroflex Gaisler
-- Contact: [email protected]
-- Description: pads for SpW signals in router ASIC LVTTL ports
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.config.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.conv_std_logic;
entity spw_lvttl_pads is
generic (
padtech : integer := 0;
oepol : integer := 0;
level : integer := 0;
voltage : integer := 0;
filter : integer := 0;
strength : integer := 4;
slew : integer := 0;
input_type : integer := 0
);
port (
---------------------------------------------------------------------------
-- Signals going off-chip
---------------------------------------------------------------------------
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
---------------------------------------------------------------------------
-- Signals to core
---------------------------------------------------------------------------
lspw_rxd : out std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_rxs : out std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_txd : in std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_txs : in std_logic_vector(0 to CFG_SPW_NUM-1)
);
end entity;
architecture rtl of spw_lvttl_pads is
begin
------------------------------------------------------------------------------
-- SpW port pads
------------------------------------------------------------------------------
spw_pads : for i in 0 to CFG_SPW_NUM-1 generate
spw_pad_input: if input_type <= 3 generate
spw_rxd_pad : inpad
generic map (
tech => padtech,
level => level,
voltage => voltage,
filter => filter,
strength => strength)
port map (
pad => spw_rxd(i),
o => lspw_rxd(i));
spw_rxs_pad : inpad
generic map (
tech => padtech,
level => level,
voltage => voltage,
filter => filter,
strength => strength)
port map (
pad => spw_rxs(i),
o => lspw_rxs(i));
end generate;
spw_no_pad_input: if input_type >= 4 generate
lspw_rxd(i) <= spw_rxd(i);
lspw_rxs(i) <= spw_rxs(i);
end generate;
spw_txd_pad : outpad
generic map (
tech => padtech,
level => level,
slew => slew,
voltage => voltage,
strength => strength)
port map (
pad => spw_txd(i),
i => lspw_txd(i));
spw_txs_pad : outpad
generic map (
tech => padtech,
level => level,
slew => slew,
voltage => voltage,
strength => strength)
port map (
pad => spw_txs(i),
i => lspw_txs(i));
end generate;
end;
|
gpl-2.0
|
22c4037f8017ee3c3808c50b1c932f61
| 0.473272 | 4.278469 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/syncram128.vhd
| 1 | 5,127 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram128
-- File: syncram128.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 128-bit syncronous 1-port ram with 32-bit write strobes
-- and tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allmem.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncram128 is
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0;
paren : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127+16*paren downto 0);
dataout : out std_logic_vector (127+16*paren downto 0);
enable : in std_logic_vector (3 downto 0);
write : in std_logic_vector (3 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none
);
end;
architecture rtl of syncram128 is
component unisim_syncram128
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (3 downto 0);
write : in std_logic_vector (3 downto 0)
);
end component;
signal dinp, doutp : std_logic_vector(143 downto 0);
signal xenable,xwrite : std_logic_vector(3 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xenable <= enable when testen=0 or testin(TESTIN_WIDTH-2)='0' else "0000";
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else "0000";
custominx <= (others => '0');
nocust: if syncram_has_customif(tech)=0 or has_sram128(tech)=0 or paren=1 generate
customoutx <= (others => '0');
end generate;
nopar : if paren = 0 generate
s128 : if has_sram128(tech) = 1 generate
uni : if (is_unisim(tech) = 1) generate
x0 : unisim_syncram128 generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_syncram_we generic map (abits => abits, dbits => 128)
port map(clk, address, datain, dataout, xenable, xwrite);
end generate;
-- pragma translate_off
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncram128: " & tost(2**abits) & "x128" &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end generate;
nos128 : if has_sram128(tech) = 0 generate
x0 : syncram64 generic map (tech, abits, testen, 0, custombits)
port map (clk, address, datain(127 downto 64), dataout(127 downto 64),
enable(3 downto 2), write(3 downto 2), testin
);
x1 : syncram64 generic map (tech, abits, testen, 0, custombits)
port map (clk, address, datain(63 downto 0), dataout(63 downto 0),
enable(1 downto 0), write(1 downto 0), testin
);
end generate;
end generate;
par : if paren = 1 generate
dinp <= datain(127+16*paren downto 120+16*paren) & datain(127 downto 64) &
datain(127+8*paren downto 120+8*paren) & datain(63 downto 0);
dataout <= doutp(143 downto 136) & doutp(71 downto 64) &
doutp(135 downto 72) & doutp(63-16+16*paren downto 0);
x0 : syncram64 generic map (tech, abits, testen, 1, custombits)
port map (clk, address, dinp(143 downto 72), doutp(143 downto 72),
enable(3 downto 2), write(3 downto 2), testin
);
x1 : syncram64 generic map (tech, abits, testen, 1, custombits)
port map (clk, address, dinp(71 downto 0), doutp(71 downto 0),
enable(1 downto 0), write(1 downto 0), testin
);
end generate;
end;
|
gpl-2.0
|
d22af7d6c07c8fb912cac2827546db77
| 0.621416 | 3.769853 | false | true | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/eth/core/eth_rstgen.vhd
| 1 | 2,291 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: eth_rstgen
-- File: eth_rstgen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Reset generation with glitch filter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity eth_rstgen is
generic (acthigh : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic
);
end;
architecture rtl of eth_rstgen is
signal r : std_logic_vector(4 downto 0);
signal rst : std_ulogic;
attribute equivalent_register_removal : string;
attribute keep : string;
attribute equivalent_register_removal of r : signal is "no";
attribute equivalent_register_removal of rst : signal is "no";
attribute keep of r : signal is "true";
attribute keep of rst : signal is "true";
begin
rst <= not rstin when acthigh = 1 else rstin;
rstoutraw <= rst;
reg1 : process (clk, rst) begin
if rising_edge(clk) then
r <= r(3 downto 0) & clklock;
rstout <= r(4) and r(3) and r(2);
end if;
if rst = '0' then r <= "00000"; rstout <= '0'; end if;
end process;
end;
|
gpl-2.0
|
e63178092836a88d8aab5eed49f153ad
| 0.61065 | 4.047703 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/ddr/ddrphy_wrap.vhd
| 1 | 58,032 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr_phy
-- File: ddr_phy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Wrapper entities for techmap ddrphy/ddr2phy
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
------------------------------------------------------------------
-- DDR1 PHY wrapper -------------------------------------------------------
------------------------------------------------------------------
entity ddrphy_wrap is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0; mobile : integer := 0;
scantest : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic;
clkread : out std_ulogic; -- read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddrphy_wrap is
begin
ddr_phy0 : ddrphy
generic map (tech => tech, MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, dbits => dbits, clk_mul => clk_mul, clk_div => clk_div,
rskew => rskew, mobile => mobile, scantest => scantest,
phyiconf => phyiconf)
port map (
rst, clk, clkout, clkoutret, clkread, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
sdo.address(13 downto 0), sdo.ba(1 downto 0),
sdi.data(dbits*2-1 downto 0), sdo.data(dbits*2-1 downto 0),
sdo.dqm(dbits/4-1 downto 0), sdo.bdrive, sdo.bdrive, sdo.qdrive,
sdo.rasn, sdo.casn, sdo.sdwen, sdo.sdcsn, sdo.sdcke, sdo.sdck(2 downto 0), sdo.moben,
sdi.datavalid, testen, testrst, scanen, testoen);
drvdata : if dbits < 64 generate
sdi.data(127 downto dbits*2) <= (others => '0');
end generate;
sdi.cb <= (others => '0'); sdi.regrdata <= (others => '0');
sdi.writereq <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
------------------------------------------------------------------
-- DDR1 PHY with checkbits merged on data bus --------------------
------------------------------------------------------------------
entity ddrphy_wrap_cbd is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
chkbits: integer := 0; padbits : integer := 0;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2;
scantest: integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkread : out std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddrphy_wrap_cbd is
function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(2*ow-1 downto 0);
constant iw: integer := x'length/2;
begin
r := (others => '0');
if iw <= ow then
r(iw+ow-1 downto ow) := x(2*iw-1 downto iw);
r(iw-1 downto 0) := x(iw-1 downto 0);
else
r := x(iw+ow-1 downto iw) & x(ow-1 downto 0);
end if;
return r;
end;
function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(ow-1 downto 0);
constant iw: integer := x'length;
variable xd : std_logic_vector(iw-1 downto 0);
begin
r := (others => '0'); xd := x;
if iw >= ow then
r := xd(ow-1 downto 0);
else
r(iw-1 downto 0) := xd;
end if;
return r;
end;
function ddrmerge(a,b: std_logic_vector) return std_logic_vector is
constant aw: integer := a'length/2;
constant bw: integer := b'length/2;
begin
return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0);
end;
signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0);
signal cal_en: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0);
signal cal_inc: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0);
signal odt,csn,cke: std_logic_vector(ncs-1 downto 0);
signal sdck: std_logic_vector(nclk-1 downto 0);
begin
-- Merge checkbit and data buses
comb: process(sdo,dqin)
variable dq: std_logic_vector(2*dbits-1 downto 0);
variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0);
variable cb: std_logic_vector(dbits-1 downto 0);
variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0
variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0);
variable dm: std_logic_vector(dbits/4-1 downto 0);
variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0);
variable cbdm: std_logic_vector(dbits/8-1 downto 0);
variable cbdmpad: std_logic_vector(chkbits/4 downto 0);
variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0);
variable vcsn,vcke: std_logic_vector(ncs-1 downto 0);
variable vsdck: std_logic_vector(nclk-1 downto 0);
begin
dq := sdo.data(2*dbits-1 downto 0);
dqpad := ddr_widthconv(dq, dbits+padbits );
if chkbits > 0 then
cb := sdo.cb(dbits-1 downto 0);
cbpad := '0' & ddr_widthconv(cb, chkbits);
dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad);
else
dqcb := dqpad;
end if;
dqout <= dqcb;
dqcb := dqin;
if chkbits > 0 then
cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) &
dqin(chkbits+dbits+padbits-1 downto dbits+padbits);
cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2);
else
cb := (others => '0');
end if;
dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) &
dqcb(dbits-1 downto 0);
sdi.cb(dbits-1 downto 0) <= cb;
sdi.data(2*dbits-1 downto 0) <= dq;
if sdi.cb'length > dbits then
sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0');
end if;
if sdi.data'length > 2*dbits then
sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0');
end if;
dm := sdo.dqm(dbits/4-1 downto 0);
dmpad := ddr_widthconv(dm, (dbits+padbits)/8);
if chkbits > 0 then
cbdm := sdo.cbdqm(dbits/8-1 downto 0);
cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8);
dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad);
else
dqcbdm := dmpad;
end if;
dqm <= dqcbdm;
cal_en <= sdr_widthconv(sdo.cbcal_en (dbits/16-1 downto 0) &
sdo.cal_en (dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 );
cal_inc <= sdr_widthconv(sdo.cbcal_inc(dbits/16-1 downto 0) &
sdo.cal_inc(dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 );
vcsn := (others => '1');
for x in 0 to ncs-1 loop
if x<2 then
vcsn(x) := sdo.sdcsn(x);
end if;
vcke(x) := sdo.sdcke(x mod 2);
end loop;
for x in 0 to nclk-1 loop
vsdck(x) := sdo.sdck(x mod 2);
end loop;
csn <= vcsn;
cke <= vcke;
sdck <= vsdck;
end process;
-- Phy instantiation
ddr_phy0 : ddrphy
generic map (tech => tech, MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, dbits => dbits+padbits+chkbits,clk_mul => clk_mul, clk_div => clk_div,
rskew => rskew, mobile => mobile,
abits => abits, nclk => nclk, ncs => ncs, scantest => scantest,
phyiconf => phyiconf)
port map (
rst, clk, clkout, clkoutret, clkread, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
sdo.address(abits-1 downto 0), sdo.ba(1 downto 0),
dqin, dqout,
dqm, sdo.bdrive, sdo.bdrive, sdo.qdrive,
sdo.rasn, sdo.casn, sdo.sdwen, csn, cke, sdck, sdo.moben,sdi.datavalid,
testen,testrst,scanen,testoen);
sdi.regrdata <= (others => '0');
sdi.writereq <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
------------------------------------------------------------------
-- DDR1 PHY with checkbits merged on data bus, pads not in phy --
------------------------------------------------------------------
entity ddrphy_wrap_cbd_wo_pads is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16; padbits : integer := 0;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer := 0; mobile : integer := 0;
abits : integer := 14; nclk : integer := 3; ncs : integer := 2;
chkbits : integer := 0;
scantest : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0);
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddrphy_wrap_cbd_wo_pads is
function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(2*ow-1 downto 0);
constant iw: integer := x'length/2;
begin
r := (others => '0');
if iw <= ow then
r(iw+ow-1 downto ow) := x(2*iw-1 downto iw);
r(iw-1 downto 0) := x(iw-1 downto 0);
else
r := x(iw+ow-1 downto iw) & x(ow-1 downto 0);
end if;
return r;
end;
function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(ow-1 downto 0);
constant iw: integer := x'length;
variable xd : std_logic_vector(iw-1 downto 0);
begin
r := (others => '0'); xd := x;
if iw >= ow then
r := xd(ow-1 downto 0);
else
r(iw-1 downto 0) := xd;
end if;
return r;
end;
function ddrmerge(a,b: std_logic_vector) return std_logic_vector is
constant aw: integer := a'length/2;
constant bw: integer := b'length/2;
begin
return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0);
end;
signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0);
signal odt,csn,cke: std_logic_vector(ncs-1 downto 0);
signal sdck: std_logic_vector(nclk-1 downto 0);
signal gnd : std_logic_vector(chkbits*2-1 downto 0);
begin
gnd <= (others => '0');
-- Merge checkbit and data buses
comb: process(sdo,dqin)
variable dq: std_logic_vector(2*dbits-1 downto 0);
variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0);
variable cb: std_logic_vector(dbits-1 downto 0);
variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0
variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0);
variable dm: std_logic_vector(dbits/4-1 downto 0);
variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0);
variable cbdm: std_logic_vector(dbits/8-1 downto 0);
variable cbdmpad: std_logic_vector(chkbits/4 downto 0);
variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0);
variable vcsn,vodt,vcke: std_logic_vector(ncs-1 downto 0);
variable vsdck: std_logic_vector(nclk-1 downto 0);
begin
dq := sdo.data(2*dbits-1 downto 0);
dqpad := ddr_widthconv(dq, dbits+padbits );
if chkbits > 0 then
cb := sdo.cb(dbits-1 downto 0);
cbpad := '0' & ddr_widthconv(cb, chkbits);
dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad);
else
dqcb := dqpad;
end if;
dqout <= dqcb;
dqcb := dqin;
if chkbits > 0 then
cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) &
dqin(chkbits+dbits+padbits-1 downto dbits+padbits);
cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2);
else
cb := (others => '0');
end if;
dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) &
dqcb(dbits-1 downto 0);
sdi.cb(dbits-1 downto 0) <= cb;
sdi.data(2*dbits-1 downto 0) <= dq;
if sdi.cb'length > dbits then
sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0');
end if;
if sdi.data'length > 2*dbits then
sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0');
end if;
dm := sdo.dqm(dbits/4-1 downto 0);
dmpad := ddr_widthconv(dm, (dbits+padbits)/8);
if chkbits > 0 then
cbdm := sdo.cbdqm(dbits/8-1 downto 0);
cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8);
dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad);
else
dqcbdm := dmpad;
end if;
dqm <= dqcbdm;
vcsn := (others => '1');
for x in 0 to ncs-1 loop
if x<2 then
vcsn(x) := sdo.sdcsn(x);
end if;
vodt(x) := sdo.odt(x mod 2);
vcke(x) := sdo.sdcke(x mod 2);
end loop;
for x in 0 to nclk-1 loop
vsdck(x) := sdo.sdck(x mod 2);
end loop;
csn <= vcsn;
cke <= vcke;
sdck <= vsdck;
end process;
-- Phy instantiation
ddr_phy0 : ddrphy_wo_pads
generic map (
tech => tech, MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, dbits => dbits+padbits+chkbits, clk_mul => clk_mul, clk_div => clk_div,
rskew => rskew,
abits => abits, nclk => nclk, ncs => ncs, mobile => mobile, scantest => scantest, phyiconf => phyiconf)
port map (
rst => rst, clk => clk, clkout => clkout, clkoutret => clkoutret,
lock => lock,
ddr_clk => ddr_clk, ddr_clkb => ddr_clkb, ddr_clk_fb_out => ddr_clk_fb_out, ddr_clk_fb => ddr_clk_fb,
ddr_cke => ddr_cke, ddr_csb => ddr_csb, ddr_web => ddr_web, ddr_rasb => ddr_rasb, ddr_casb => ddr_casb,
ddr_dm => ddr_dm, ddr_dqs_in => ddr_dqs_in, ddr_dqs_out => ddr_dqs_out, ddr_dqs_oen => ddr_dqs_oen,
ddr_ad => ddr_ad, ddr_ba => ddr_ba, ddr_dq_in => ddr_dq_in, ddr_dq_out => ddr_dq_out, ddr_dq_oen => ddr_dq_oen,
addr => sdo.address(abits-1 downto 0), ba => sdo.ba(1 downto 0), dqin => dqin, dqout => dqout, dm => dqm,
oen => sdo.bdrive,
dqs => sdo.bdrive, dqsoen => sdo.qdrive, rasn => sdo.rasn, casn => sdo.casn, wen => sdo.sdwen, csn => csn,
cke => cke, ck => sdck, moben => sdo.moben, dqvalid => sdi.datavalid,
testen => testen, testrst => testrst, scanen => scanen, testoen => testoen
);
sdi.regrdata <= (others => '0');
sdi.writereq <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
------------------------------------------------------------------
-- DDR2 PHY wrapper -----------------------------------------------
------------------------------------------------------------------
-------------------------------------------------------------------------------
-- There are three variants of the PHY wrapper depending on pads/checkbits:
-- 1. ddr2phy_wrap:
-- This provides pads and outputs checkbits on separate vectors
-- 2. ddr2phy_wrap_cbd:
-- This provides pads and merges checkbits+data on same vector
-- 3. ddr2phy_wrap_cbd_wo_pads:
-- This does not provide pads and merges checkbits+data on same vectors
--
-- Variants (1),(3) can not be used when ddr2phy_builtin_pads(tech)=1
-------------------------------------------------------------------------------
entity ddr2phy_wrap is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16; padbits : integer := 0;
clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
cbdelayb0 : integer := 0; cbdelayb1: integer := 0; cbdelayb2: integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; odten : integer := 0;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk : integer := 3; ncs : integer := 2;
cben : integer := 0; chkbits : integer := 8; ctrl2en : integer := 0;
resync : integer := 0; custombits: integer := 8;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkresync : in std_ulogic; -- resync clock (if resync/=0)
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector ((dbits+padbits)-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
ddr_cbdm : out std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdqs : inout std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdqsn : inout std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdq : inout std_logic_vector(chkbits-1 downto 0);
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end;
architecture rtl of ddr2phy_wrap is
signal lddr_clk,lddr_clkb: std_logic_vector(nclk-1 downto 0);
signal lddr_clk_fb_out,lddr_clk_fb: std_ulogic;
signal lddr_cke,lddr_csb,lddr_odt: std_logic_vector(ncs-1 downto 0);
signal lddr_web,lddr_rasb,lddr_casb: std_ulogic;
signal lddr_dm,lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen: std_logic_vector((dbits+padbits+chkbits)/8-1 downto 0);
signal lddr_ad: std_logic_vector(abits-1 downto 0);
signal lddr_ba: std_logic_vector(1+eightbanks downto 0);
signal lddr_dq_in,lddr_dq_out,lddr_dq_oen: std_logic_vector(dbits+padbits+chkbits-1 downto 0);
begin
-- Instantiate PHY without pads via other wrapper
w0: ddr2phy_wrap_cbd_wo_pads
generic map (tech,MHz,rstdelay,dbits,padbits,clk_mul,clk_div,
ddelayb0,ddelayb1,ddelayb2,ddelayb3,ddelayb4,ddelayb5,ddelayb6,ddelayb7,
cbdelayb0,cbdelayb1,cbdelayb2,cbdelayb3,
numidelctrl,norefclk,odten,rskew,
eightbanks,dqsse,abits,nclk,ncs,chkbits,resync,custombits,scantest)
port map (
rst,clk,clkref200,clkout,clkoutret,clkresync,lock,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,
lddr_cke,lddr_csb,lddr_web,lddr_rasb,lddr_casb,lddr_dm,
lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen,
lddr_ad,lddr_ba,lddr_dq_in,lddr_dq_out,lddr_dq_oen,
lddr_odt,
sdi,sdo,customclk,customdin,customdout,testen,testrst,scanen,testoen);
-- Instantiate pads for control signals and data bus
p0: ddr2pads
generic map (tech,dbits+padbits,eightbanks,dqsse,abits,nclk,ncs,ctrl2en)
port map (
ddr_clk,ddr_clkb,ddr_clk_fb_out,ddr_clk_fb,
ddr_cke,ddr_csb,ddr_web,ddr_rasb,ddr_casb,
ddr_dm,ddr_dqs,ddr_dqsn,ddr_ad,ddr_ba,ddr_dq,ddr_odt,
ddr_web2,ddr_rasb2,ddr_casb2,ddr_ad2,ddr_ba2,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,
lddr_cke,lddr_csb,lddr_web,lddr_rasb,lddr_casb,
lddr_dm(dbits/8+padbits/8-1 downto 0),
lddr_dqs_in(dbits/8+padbits/8-1 downto 0),
lddr_dqs_out(dbits/8+padbits/8-1 downto 0),
lddr_dqs_oen(dbits/8+padbits/8-1 downto 0),
lddr_ad,lddr_ba,
lddr_dq_in(dbits+padbits-1 downto 0),
lddr_dq_out(dbits+padbits-1 downto 0),
lddr_dq_oen(dbits+padbits-1 downto 0),
lddr_odt);
-- Instantiate pads for checkbit bus
cbdqpad: iopadvv
generic map (tech => tech, slew => 1, level => sstl18_ii, width => chkbits)
port map (pad => ddr_cbdq,
i => lddr_dq_out(dbits+padbits+chkbits-1 downto dbits+padbits),
en => lddr_dq_oen(dbits+padbits+chkbits-1 downto dbits+padbits),
o => lddr_dq_in(dbits+padbits+chkbits-1 downto dbits+padbits));
cbdqmpad: outpadv
generic map (tech => tech, slew => 1, level => sstl18_i, width => chkbits/8)
port map (pad => ddr_cbdm,
i => lddr_dm(dbits/8+padbits/8+chkbits/8-1 downto dbits/8+padbits/8));
cbdqspad: iopad_dsvv
generic map (tech => tech, slew => 1, level => sstl18_ii, width => chkbits/8)
port map (padp => ddr_cbdqs, padn => ddr_cbdqsn,
i => lddr_dqs_out(dbits/8+padbits/8+chkbits/8-1 downto dbits/8+padbits/8),
en => lddr_dqs_oen(dbits/8+padbits/8+chkbits/8-1 downto dbits/8+padbits/8),
o => lddr_dqs_in(dbits/8+padbits/8+chkbits/8-1 downto dbits/8+padbits/8));
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
------------------------------------------------------------------
-- DDR2 PHY with checkbits merged on data bus --------------------
------------------------------------------------------------------
entity ddr2phy_wrap_cbd is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16; padbits : integer := 0;
clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
cbdelayb0 : integer := 0; cbdelayb1: integer := 0; cbdelayb2: integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; odten : integer := 0;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk : integer := 3; ncs : integer := 2;
chkbits : integer := 0; ctrl2en : integer := 0;
resync : integer := 0; custombits: integer := 8; extraio : integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (extraio+(dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddr2phy_wrap_cbd is
function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(2*ow-1 downto 0);
constant iw: integer := x'length/2;
begin
r := (others => '0');
if iw <= ow then
r(iw+ow-1 downto ow) := x(2*iw-1 downto iw);
r(iw-1 downto 0) := x(iw-1 downto 0);
else
r := x(iw+ow-1 downto iw) & x(ow-1 downto 0);
end if;
return r;
end;
function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(ow-1 downto 0);
constant iw: integer := x'length;
variable xd : std_logic_vector(iw-1 downto 0);
begin
r := (others => '0'); xd := x;
if iw >= ow then
r := xd(ow-1 downto 0);
else
r(iw-1 downto 0) := xd;
end if;
return r;
end;
function ddrmerge(a,b: std_logic_vector) return std_logic_vector is
constant aw: integer := a'length/2;
constant bw: integer := b'length/2;
begin
return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0);
end;
type int_array is array (natural range <>) of integer;
constant delays: int_array(0 to 7) := (ddelayb0,ddelayb1,ddelayb2,ddelayb3,
ddelayb4,ddelayb5,ddelayb6,ddelayb7);
constant cbdelays: int_array(0 to 11) := (cbdelayb0,cbdelayb1,cbdelayb2,cbdelayb3,0,0,0,0,0,0,0,0);
constant cbddelays: int_array(0 to 11) :=
delays(0 to (dbits+padbits)/8-1) & cbdelays(0 to 11-(dbits+padbits)/8);
signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0);
signal cal_en: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0);
signal cal_inc: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0);
signal odt,csn,cke: std_logic_vector(ncs-1 downto 0);
begin
-- Merge checkbit and data buses
comb: process(sdo,dqin)
variable dq: std_logic_vector(2*dbits-1 downto 0);
variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0);
variable cb: std_logic_vector(dbits-1 downto 0);
variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0
variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0);
variable dm: std_logic_vector(dbits/4-1 downto 0);
variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0);
variable cbdm: std_logic_vector(dbits/8-1 downto 0);
variable cbdmpad: std_logic_vector(chkbits/4 downto 0);
variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0);
variable vcsn,vodt,vcke: std_logic_vector(ncs-1 downto 0);
begin
dq := sdo.data(2*dbits-1 downto 0);
dqpad := ddr_widthconv(dq, dbits+padbits );
if chkbits > 0 then
cb := sdo.cb(dbits-1 downto 0);
cbpad := '0' & ddr_widthconv(cb, chkbits);
dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad);
else
dqcb := dqpad;
end if;
dqout <= dqcb;
dqcb := dqin;
if chkbits > 0 then
cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) &
dqin(chkbits+dbits+padbits-1 downto dbits+padbits);
cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2);
else
cb := (others => '0');
end if;
dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) &
dqcb(dbits-1 downto 0);
sdi.cb(dbits-1 downto 0) <= cb;
sdi.data(2*dbits-1 downto 0) <= dq;
if sdi.cb'length > dbits then
sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0');
end if;
if sdi.data'length > 2*dbits then
sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0');
end if;
dm := sdo.dqm(dbits/4-1 downto 0);
dmpad := ddr_widthconv(dm, (dbits+padbits)/8);
if chkbits > 0 then
cbdm := sdo.cbdqm(dbits/8-1 downto 0);
cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8);
dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad);
else
dqcbdm := dmpad;
end if;
dqm <= dqcbdm;
cal_en <= sdr_widthconv(sdo.cbcal_en (dbits/16-1 downto 0) &
sdo.cal_en (dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 );
cal_inc <= sdr_widthconv(sdo.cbcal_inc(dbits/16-1 downto 0) &
sdo.cal_inc(dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 );
vcsn := (others => '1');
for x in 0 to ncs-1 loop
if x<2 then
vcsn(x) := sdo.sdcsn(x);
end if;
vodt(x) := sdo.odt(x mod 2);
vcke(x) := sdo.sdcke(x mod 2);
end loop;
csn <= vcsn;
odt <= vodt;
cke <= vcke;
end process;
-- Phy instantiation
ddr_phy0 : ddr2phy
generic map (tech => tech, MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, dbits => dbits+padbits+chkbits,clk_mul => clk_mul, clk_div => clk_div,
ddelayb0 => cbddelays(0), ddelayb1 => cbddelays(1), ddelayb2 => cbddelays(2),
ddelayb3 => cbddelays(3), ddelayb4 => cbddelays(4), ddelayb5 => cbddelays(5),
ddelayb6 => cbddelays(6), ddelayb7 => cbddelays(7), ddelayb8 => cbddelays(8),
ddelayb9 => cbddelays(9), ddelayb10 => cbddelays(10), ddelayb11 => cbddelays(11),
numidelctrl => numidelctrl, norefclk => norefclk, rskew => rskew,
eightbanks => eightbanks, dqsse => dqsse,
abits => abits, nclk => nclk, ncs => ncs,
ctrl2en => ctrl2en, resync => resync, custombits => custombits, extraio => extraio,
scantest => scantest)
port map (
rst, clk, clkref200, clkout, clkoutret, clkresync, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
sdo.address(abits-1 downto 0), sdo.ba,
dqin, dqout,
dqm, sdo.bdrive, sdo.nbdrive, sdo.bdrive, sdo.qdrive,
sdo.rasn, sdo.casn, sdo.sdwen, csn, cke,
cal_en, cal_inc,
sdo.cal_pll, sdo.cal_rst, odt, sdo.oct, sdo.read_pend,
sdo.regwdata, sdo.regwrite, sdi.regrdata, sdi.datavalid,
customclk, customdin, customdout,
ddr_web2, ddr_rasb2, ddr_casb2, ddr_ad2, ddr_ba2,
testen, testrst, scanen, testoen
);
sdi.writereq <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
------------------------------------------------------------------
-- DDR2 PHY with checkbits merged on data bus, pads not in phy --
------------------------------------------------------------------
entity ddr2phy_wrap_cbd_wo_pads is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16; padbits : integer := 0;
clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
cbdelayb0 : integer := 0; cbdelayb1: integer := 0; cbdelayb2: integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; odten : integer := 0;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk : integer := 3; ncs : integer := 2;
chkbits : integer := 0; resync : integer := 0; custombits: integer := 8;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddr2phy_wrap_cbd_wo_pads is
function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(2*ow-1 downto 0);
constant iw: integer := x'length/2;
begin
r := (others => '0');
if iw <= ow then
r(iw+ow-1 downto ow) := x(2*iw-1 downto iw);
r(iw-1 downto 0) := x(iw-1 downto 0);
else
r := x(iw+ow-1 downto iw) & x(ow-1 downto 0);
end if;
return r;
end;
function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(ow-1 downto 0);
constant iw: integer := x'length;
variable xd : std_logic_vector(iw-1 downto 0);
begin
r := (others => '0'); xd := x;
if iw >= ow then
r := xd(ow-1 downto 0);
else
r(iw-1 downto 0) := xd;
end if;
return r;
end;
function ddrmerge(a,b: std_logic_vector) return std_logic_vector is
constant aw: integer := a'length/2;
constant bw: integer := b'length/2;
begin
return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0);
end;
type int_array is array (natural range <>) of integer;
constant delays: int_array(0 to 7) := (ddelayb0,ddelayb1,ddelayb2,ddelayb3,
ddelayb4,ddelayb5,ddelayb6,ddelayb7);
constant cbdelays: int_array(0 to 11) := (cbdelayb0,cbdelayb1,cbdelayb2,cbdelayb3,0,0,0,0,0,0,0,0);
constant cbddelays: int_array(0 to 11) :=
delays(0 to (dbits+padbits)/8-1) & cbdelays(0 to 11-(dbits+padbits)/8);
signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0);
signal cal_en: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0);
signal cal_inc: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0);
signal odt,csn,cke: std_logic_vector(ncs-1 downto 0);
signal gnd : std_logic_vector(chkbits*2-1 downto 0);
begin
gnd <= (others => '0');
-- Merge checkbit and data buses
comb: process(sdo,dqin)
variable dq: std_logic_vector(2*dbits-1 downto 0);
variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0);
variable cb: std_logic_vector(dbits-1 downto 0);
variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0
variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0);
variable dm: std_logic_vector(dbits/4-1 downto 0);
variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0);
variable cbdm: std_logic_vector(dbits/8-1 downto 0);
variable cbdmpad: std_logic_vector(chkbits/4 downto 0);
variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0);
variable vcsn,vodt,vcke: std_logic_vector(ncs-1 downto 0);
begin
dq := sdo.data(2*dbits-1 downto 0);
dqpad := ddr_widthconv(dq, dbits+padbits );
if chkbits > 0 then
cb := sdo.cb(dbits-1 downto 0);
cbpad := '0' & ddr_widthconv(cb, chkbits);
dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad);
else
dqcb := dqpad;
end if;
dqout <= dqcb;
dqcb := dqin;
if chkbits > 0 then
cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) &
dqin(chkbits+dbits+padbits-1 downto dbits+padbits);
cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2);
else
cb := (others => '0');
end if;
dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) &
dqcb(dbits-1 downto 0);
sdi.cb(dbits-1 downto 0) <= cb;
sdi.data(2*dbits-1 downto 0) <= dq;
if sdi.cb'length > dbits then
sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0');
end if;
if sdi.data'length > 2*dbits then
sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0');
end if;
dm := sdo.dqm(dbits/4-1 downto 0);
dmpad := ddr_widthconv(dm, (dbits+padbits)/8);
if chkbits > 0 then
cbdm := sdo.cbdqm(dbits/8-1 downto 0);
cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8);
dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad);
else
dqcbdm := dmpad;
end if;
dqm <= dqcbdm;
cal_en <= sdr_widthconv(sdo.cbcal_en (dbits/16-1 downto 0) &
sdo.cal_en (dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 );
cal_inc <= sdr_widthconv(sdo.cbcal_inc(dbits/16-1 downto 0) &
sdo.cal_inc(dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 );
vcsn := (others => '1');
for x in 0 to ncs-1 loop
if x<2 then
vcsn(x) := sdo.sdcsn(x);
end if;
vodt(x) := sdo.odt(x mod 2);
vcke(x) := sdo.sdcke(x mod 2);
end loop;
csn <= vcsn;
odt <= vodt;
cke <= vcke;
end process;
-- Phy instantiation
ddr_phy0 : ddr2phy_wo_pads
generic map (tech => tech, MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, dbits => dbits+padbits+chkbits,clk_mul => clk_mul, clk_div => clk_div,
ddelayb0 => cbddelays(0), ddelayb1 => cbddelays(1), ddelayb2 => cbddelays(2),
ddelayb3 => cbddelays(3), ddelayb4 => cbddelays(4), ddelayb5 => cbddelays(5),
ddelayb6 => cbddelays(6), ddelayb7 => cbddelays(7), ddelayb8 => cbddelays(8),
ddelayb9 => cbddelays(9), ddelayb10 => cbddelays(10), ddelayb11 => cbddelays(11),
numidelctrl => numidelctrl, norefclk => norefclk, rskew => rskew,
eightbanks => eightbanks, dqsse => dqsse,
abits => abits, nclk => nclk, ncs => ncs, resync => resync, custombits => custombits,
scantest => scantest)
port map (
rst => rst, clk => clk, clkref => clkref200, clkout => clkout, clkoutret => clkoutret,
clkresync => clkresync, lock => lock,
ddr_clk => ddr_clk, ddr_clkb => ddr_clkb, ddr_clk_fb_out => ddr_clk_fb_out, ddr_clk_fb => ddr_clk_fb,
ddr_cke => ddr_cke, ddr_csb => ddr_csb, ddr_web => ddr_web, ddr_rasb => ddr_rasb, ddr_casb => ddr_casb,
ddr_dm => ddr_dm, ddr_dqs_in => ddr_dqs_in, ddr_dqs_out => ddr_dqs_out, ddr_dqs_oen => ddr_dqs_oen,
ddr_ad => ddr_ad, ddr_ba => ddr_ba, ddr_dq_in => ddr_dq_in, ddr_dq_out => ddr_dq_out, ddr_dq_oen => ddr_dq_oen,
ddr_odt => ddr_odt,
addr => sdo.address(abits-1 downto 0), ba => sdo.ba, dqin => dqin, dqout => dqout, dm => dqm,
oen => sdo.bdrive, noen => sdo.nbdrive,
dqs => sdo.bdrive, dqsoen => sdo.qdrive, rasn => sdo.rasn, casn => sdo.casn, wen => sdo.sdwen, csn => csn,
cke => cke, cal_en => cal_en, cal_inc => cal_inc, cal_pll => sdo.cal_pll, cal_rst => sdo.cal_rst, odt => odt,
oct => sdo.oct, read_pend => sdo.read_pend, regwdata => sdo.regwdata, regwrite => sdo.regwrite,
regrdata => sdi.regrdata, dqin_valid => sdi.datavalid,
customclk => customclk, customdin => customdin, customdout => customdout,
testen => testen, testrst => testrst, scanen => scanen, testoen => testoen
);
sdi.writereq <= '0';
end;
------------------------------------------------------------------
-- LPDDR2/LPDDR3 PHY with checkbits merged on data bus, no pads --
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
entity lpddr2phy_wrap_cbd_wo_pads is
generic (tech : integer := virtex2;
dbits : integer := 16;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
padbits : integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic; -- input clock
clkin2 : in std_ulogic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkout2 : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0); -- ddr cmd/addr
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0);
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of lpddr2phy_wrap_cbd_wo_pads is
function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(2*ow-1 downto 0);
constant iw: integer := x'length/2;
begin
r := (others => '0');
if iw <= ow then
r(iw+ow-1 downto ow) := x(2*iw-1 downto iw);
r(iw-1 downto 0) := x(iw-1 downto 0);
else
r := x(iw+ow-1 downto iw) & x(ow-1 downto 0);
end if;
return r;
end;
function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(ow-1 downto 0);
constant iw: integer := x'length;
variable xd : std_logic_vector(iw-1 downto 0);
begin
r := (others => '0'); xd := x;
if iw >= ow then
r := xd(ow-1 downto 0);
else
r(iw-1 downto 0) := xd;
end if;
return r;
end;
function ddrmerge(a,b: std_logic_vector) return std_logic_vector is
constant aw: integer := a'length/2;
constant bw: integer := b'length/2;
begin
return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0);
end;
signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0);
signal odt,csn,cke: std_logic_vector(ncs-1 downto 0);
signal sdck: std_logic_vector(nclk-1 downto 0);
signal gnd : std_logic_vector(chkbits*2-1 downto 0);
begin
gnd <= (others => '0');
-- Merge checkbit and data buses
comb: process(sdo,dqin)
variable dq: std_logic_vector(2*dbits-1 downto 0);
variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0);
variable cb: std_logic_vector(dbits-1 downto 0);
variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0
variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0);
variable dm: std_logic_vector(dbits/4-1 downto 0);
variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0);
variable cbdm: std_logic_vector(dbits/8-1 downto 0);
variable cbdmpad: std_logic_vector(chkbits/4 downto 0);
variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0);
variable vcsn,vcke: std_logic_vector(ncs-1 downto 0);
variable vsdck: std_logic_vector(nclk-1 downto 0);
begin
dq := sdo.data(2*dbits-1 downto 0);
dqpad := ddr_widthconv(dq, dbits+padbits );
if chkbits > 0 then
cb := sdo.cb(dbits-1 downto 0);
cbpad := '0' & ddr_widthconv(cb, chkbits);
dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad);
else
dqcb := dqpad;
end if;
dqout <= dqcb;
dqcb := dqin;
if chkbits > 0 then
cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) &
dqin(chkbits+dbits+padbits-1 downto dbits+padbits);
cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2);
else
cb := (others => '0');
end if;
dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) &
dqcb(dbits-1 downto 0);
sdi.cb(dbits-1 downto 0) <= cb;
sdi.data(2*dbits-1 downto 0) <= dq;
if sdi.cb'length > dbits then
sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0');
end if;
if sdi.data'length > 2*dbits then
sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0');
end if;
dm := sdo.dqm(dbits/4-1 downto 0);
dmpad := ddr_widthconv(dm, (dbits+padbits)/8);
if chkbits > 0 then
cbdm := sdo.cbdqm(dbits/8-1 downto 0);
cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8);
dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad);
else
dqcbdm := dmpad;
end if;
dqm <= dqcbdm;
vcsn := (others => '1');
for x in 0 to ncs-1 loop
if x<2 then
vcsn(x) := sdo.sdcsn(x);
end if;
vcke(x) := sdo.sdcke(x mod 2);
end loop;
for x in 0 to nclk-1 loop
vsdck(x) := sdo.sdck(x mod 2);
end loop;
csn <= vcsn;
cke <= vcke;
sdck <= vsdck;
end process;
-- Phy instantiation
ddr_phy0 : lpddr2phy_wo_pads
generic map (
tech => tech,
dbits => dbits+padbits+chkbits,
nclk => nclk,
ncs => ncs,
clkratio => 1,
scantest => scantest)
port map (
rst => rst,
clkin => clkin,
clkin2 => clkin2,
clkout => clkout,
clkoutret => clkoutret,
clkout2 => clkout2,
lock => lock,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_ca => ddr_ca,
ddr_dm => ddr_dm,
ddr_dqs_in => ddr_dqs_in,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ca => sdo.ca,
cke => cke,
csn => csn,
dqin => dqin,
dqout => dqout,
dm => dqm,
ckstop => sdo.sdck(0),
boot => sdo.boot,
wrpend => sdo.wrpend,
rdpend => sdo.read_pend,
wrreq(0) => sdi.writereq,
rdvalid(0) => sdi.datavalid,
refcal => '0',
refcalwu => '0',
refcaldone => open,
phycmd => "00000000",
phycmden => '0',
phycmdin => x"00000000",
phycmdout => open,
testen => '0',
testrst => '1',
scanen => '0',
testoen => '0'
);
sdi.regrdata <= (others => '0');
end;
|
gpl-2.0
|
8957d380744a2a95ca5af3f8f7983b1f
| 0.570427 | 3.391899 | false | false | false | false |
rhexsel/cmips
|
cMIPS/vhdl/tb_cMIPS.vhd
| 1 | 50,797 |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- testbench for classicalMIPS
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity tb_cMIPS is
end tb_cMIPS;
architecture TB of tb_cMIPS is
component FFD is
port(clk, rst, set, D : in std_logic; Q : out std_logic);
end component FFD;
component SDcard is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic_vector; -- a03, a02
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
sdc_cs : out std_logic; -- SDcard chip-select
sdc_clk : out std_logic; -- SDcard serial clock
sdc_mosi_o : out std_logic; -- SDcard serial data out (to card)
sdc_miso_i : in std_logic; -- SDcard serial data inp (fro card)
irq : out std_logic); -- interrupt request (not yet used)
end component SDCard;
component DISK is
port (rst : in std_logic;
clk : in std_logic;
strobe : in std_logic; -- strobe for file reads/writes
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
busFree : in std_logic; -- '1' = bus will be free next cycle
busReq : out std_logic; -- '1' = bus will be used next cycle
busGrant : in std_logic; -- '1' = bus is free in this cycle
addr : in reg3;
data_inp : in reg32;
data_out : out reg32;
irq : out std_logic;
dma_addr : out reg32;
dma_dinp : in reg32;
dma_dout : out reg32;
dma_wr : out std_logic;
dma_aval : out std_logic;
dma_type : out reg4);
end component DISK;
component LCD_display is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic; -- 0=constrol, 1=data
data_inp : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
LCD_DATA : inout std_logic_vector(7 downto 0); -- bidirectional bus
LCD_RS : out std_logic; -- LCD register select 0=ctrl, 1=data
LCD_RW : out std_logic; -- LCD read=1, 0=write
LCD_EN : out std_logic; -- LCD enable=1
LCD_BLON : out std_logic);
end component LCD_display;
component to_7seg is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector;
display0 : out std_logic_vector;
display1 : out std_logic_vector;
red : out std_logic;
green : out std_logic;
blue : out std_logic);
end component to_7seg;
component read_keys is
generic (DEB_CYCLES : natural);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
data : out reg32;
kbd : in std_logic_vector (11 downto 0);
sw : in std_logic_vector (3 downto 0));
end component read_keys;
component to_stdout is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector);
end component to_stdout;
component from_stdin is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : out std_logic_vector);
end component from_stdin;
component print_data is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector);
end component print_data;
component write_data_file is
generic (OUTPUT_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data : in std_logic_vector;
byte_sel : in std_logic_vector;
dump_ram : out std_logic);
end component write_data_file;
component read_data_file is
generic (INPUT_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector;
byte_sel: in std_logic_vector);
end component read_data_file;
component do_interrupt is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
irq : out std_logic);
end component do_interrupt;
component simple_uart is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
txdat : out std_logic;
rxdat : in std_logic;
rts : out std_logic;
cts : in std_logic;
irq : out std_logic;
bit_rt : out std_logic_vector);-- communication speed - TB only
end component simple_uart;
component FPU is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector);
end component FPU;
component remota is
generic(OUTPUT_FILE_NAME : string; INPUT_FILE_NAME : string);
port(rst, clk : in std_logic;
start : in std_logic;
inpDat : in std_logic; -- serial input
outDat : out std_logic; -- serial output
bit_rt : in std_logic_vector);
end component remota;
component sys_stats is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector;
cnt_dc_ref : in integer;
cnt_dc_rd_hit : in integer;
cnt_dc_wr_hit : in integer;
cnt_dc_flush : in integer;
cnt_ic_ref : in integer;
cnt_ic_hit : in integer);
end component sys_stats;
component ram_addr_decode is
port (rst : in std_logic;
cpu_d_aVal : in std_logic;
addr : in std_logic_vector;
aVal : out std_logic;
dev_select : out std_logic_vector);
end component ram_addr_decode;
component sdram_addr_decode is
port (rst : in std_logic;
cpu_d_aVal : in std_logic;
addr : in std_logic_vector;
aVal : out std_logic;
dev_select : out std_logic_vector);
end component sdram_addr_decode;
component io_addr_decode is
port (rst : in std_logic;
clk : in std_logic;
cpu_d_aVal : in std_logic;
addr : in std_logic_vector;
dev_select : out std_logic_vector;
print_sel : out std_logic;
stdout_sel : out std_logic;
stdin_sel : out std_logic;
read_sel : out std_logic;
write_sel : out std_logic;
counter_sel : out std_logic;
FPU_sel : out std_logic;
uart_sel : out std_logic;
sstats_sel : out std_logic;
dsp7seg_sel : out std_logic;
keybd_sel : out std_logic;
lcd_sel : out std_logic;
sdc_sel : out std_logic;
dma_sel : out std_logic;
not_waiting : in std_logic);
end component io_addr_decode;
component busError_addr_decode is
port (rst : in std_logic;
cpu_d_aVal : in std_logic;
addr : in reg32;
d_busError : out std_logic); -- decoded address not in range (act=0)
end component busError_addr_decode;
component inst_addr_decode is
port (rst : in std_logic;
cpu_i_aVal : in std_logic;
addr : in std_logic_vector;
aVal : out std_logic;
i_busError : out std_logic);
end component inst_addr_decode;
component ROM is
generic (LOAD_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
strobe : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector);
end component ROM;
component RAM is
generic (LOAD_FILE_NAME : string; DUMP_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
strobe : in std_logic;
addr : in std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
byte_sel : in std_logic_vector;
dump_ram : in std_logic);
end component RAM;
component SDRAM_controller is
port (rst : in std_logic; -- FPGA reset (=0)
clk : in std_logic; -- CPU clock
clk2x : in std_logic; -- 100MHz clock
sel : in std_logic; -- host side chip select (=0)
rdy : out std_logic; -- tell CPU to wait (=0)
wr : in std_logic; -- host side write enable (=0)
bsel : in reg4; -- byte select
haddr : in reg26; -- host side address
hDinp : in reg32; -- host side data input
hDout : out reg32; -- host side data output
cke : out std_logic; -- ram side clock enable
scs : out std_logic; -- ram side chip select
ras : out std_logic; -- ram side RAS
cas : out std_logic; -- ram side CAS
we : out std_logic; -- ram side write enable
dqm0 : out std_logic; -- ram side byte0 output enable
dqm1 : out std_logic; -- ram side byte0 output enable
ba0 : out std_logic; -- ram side bank select 0
ba1 : out std_logic; -- ram side bank select 1
saddr : out reg12; -- ram side address
sdata : inout reg16); -- ram side data
end component SDRAM_controller;
component I_CACHE is
port (rst : in std_logic;
clk4x : in std_logic;
ic_reset : out std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_addr : in std_logic_vector;
cpu_data : out std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_addr : out std_logic_vector;
mem_data : in std_logic_vector;
ref_cnt : out integer;
hit_cnt : out integer);
end component I_CACHE;
component I_CACHE_fpga is
port (rst : in std_logic;
clk4x : in std_logic;
ic_reset : out std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_addr : in std_logic_vector;
cpu_data : out std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_addr : out std_logic_vector;
mem_data : in std_logic_vector;
ref_cnt : out integer;
hit_cnt : out integer);
end component I_CACHE_fpga;
component D_CACHE is
port (rst : in std_logic;
clk4x : in std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_wr : in std_logic;
cpu_addr : in std_logic_vector;
cpu_data_inp : in std_logic_vector;
cpu_data_out : out std_logic_vector;
cpu_xfer : in std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_wr : out std_logic;
mem_addr : out std_logic_vector;
mem_data_inp : in std_logic_vector;
mem_data_out : out std_logic_vector;
mem_xfer : out std_logic_vector;
ref_cnt : out integer;
rd_hit_cnt : out integer;
wr_hit_cnt : out integer;
flush_cnt : out integer);
end component D_CACHE;
component core is
port (rst : in std_logic;
clk : in std_logic;
phi1 : in std_logic;
phi2 : in std_logic;
phi3 : in std_logic;
i_aVal : out std_logic;
i_wait : in std_logic;
i_addr : out std_logic_vector;
instr : in std_logic_vector;
d_aVal : out std_logic;
d_wait : in std_logic;
d_addr : out std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
wr : out std_logic;
b_sel : out std_logic_vector;
busFree : out std_logic;
nmi : in std_logic;
irq : in std_logic_vector;
i_busErr : in std_logic;
d_busErr : in std_logic);
end component core;
component mf_altpll port (
areset : IN STD_LOGIC;
inclk0 : IN STD_LOGIC;
c0 : OUT STD_LOGIC;
c1 : OUT STD_LOGIC;
c2 : OUT STD_LOGIC;
c3 : OUT STD_LOGIC;
c4 : OUT STD_LOGIC);
end component mf_altpll;
component mf_altpll_io port (
areset : IN STD_LOGIC;
inclk0 : IN STD_LOGIC;
c0 : OUT STD_LOGIC;
c1 : OUT STD_LOGIC;
c2 : OUT STD_LOGIC);
end component mf_altpll_io;
component mf_altclkctrl port (
inclk : IN STD_LOGIC;
outclk : OUT STD_LOGIC);
end component mf_altclkctrl;
-- use simulation / fake
for U_from_stdin : from_stdin use entity work.from_stdin(simulation);
-- use simulation / fake
for U_print_data : print_data use entity work.print_data(simulation);
-- use simulation / fake
for U_to_stdout : to_stdout use entity work.to_stdout(simulation);
-- use simulation / fake
for U_write_out : write_data_file
use entity work.write_data_file(simulation);
-- use simulation / fake
for U_read_inp : read_data_file
use entity work.read_data_file(simulation);
-- use fake / behavioral
for U_I_CACHE : I_cache use entity work.I_cache(fake);
-- use simulation / rtl
for U_ROM : ROM use entity work.ROM(simulation);
-- use simulation / rtl
for U_RAM : RAM use entity work.RAM(simulation);
-- use fake / behavioral
for U_D_CACHE : D_cache use entity work.D_cache(fake);
-- use fake / rtl
for U_FPU: FPU use entity work.FPU(fake); -- rtl);
-- use fake / simple
for U_SDRAMc : SDRAM_controller
use entity work.SDRAM_controller(fake);
-- use simulation / fake
for U_DISK : DISK use entity work.DISK(fake); -- simulation);
-- use fake / rtl
for U_SDcard : SDcard use entity work.SDcard(fake);
-- use fake / rtl
for U_LCD_display : LCD_display use entity work.LCD_display(fake);
-- use simulation / fake
for U_uart_remota: remota use entity work.remota(simulation);
signal clock_50mhz, clk,clkin : std_logic;
signal clk4x,clk4x0, clk4x180, clk2x : std_logic;
signal phi0,phi1,phi2,phi3,phi0in,phi1in,phi2in,phi3in, phi2_dlyd : std_logic;
signal rst,ic_reset,a_rst1,a_rst2,a_rst3, cpu_reset : std_logic;
signal a_reset, async_reset : std_logic;
signal cpu_i_aVal, cpu_i_wait, wr, cpu_d_aVal, cpu_d_wait : std_logic;
signal busFree, nmi, i_busError, d_busError : std_logic;
signal irq : reg6;
signal inst_aVal, inst_wait, rom_rdy : std_logic;
signal data_aVal, data_wait, ram_rdy, mem_wr : std_logic;
signal sdram_aVal, sdram_wait, sdram_wr : std_logic;
signal cpu_xfer, mem_xfer : reg4;
signal dev_select, dev_select_ram, dev_select_io, dev_select_sdram : reg4;
signal io_print_sel : std_logic := '1';
signal io_stdout_sel : std_logic := '1';
signal io_stdin_sel : std_logic := '1';
signal io_write_sel : std_logic := '1';
signal io_read_sel : std_logic := '1';
signal io_counter_sel : std_logic := '1';
signal io_uart_sel : std_logic := '1';
signal io_sstats_sel : std_logic := '1';
signal io_7seg_sel : std_logic := '1';
signal io_keys_sel : std_logic := '1';
signal io_fpu_sel, io_fpu_wait : std_logic := '1';
signal io_lcd_sel, io_lcd_wait : std_logic := '1';
signal io_sdc_sel, io_sdc_wait : std_logic := '1';
signal io_dma_sel : std_logic := '1';
signal d_cache_d_out, stdin_d_out, read_d_out, counter_d_out : reg32;
signal fpu_d_out, uart_d_out, sstats_d_out, keybd_d_out : reg32;
signal lcd_d_out, sdc_d_out, sdram_d_out, dma_d_out : reg32;
signal counter_irq : std_logic;
signal io_wait, not_waiting : std_logic;
signal i_addr,d_addr,p_addr : reg32;
signal datrom, datram_inp,datram_out, cpu_instr : reg32;
signal cpu_data_inp, cpu_data_out, cpu_data : reg32;
signal mem_i_sel, mem_d_sel: std_logic;
signal mem_i_addr, mem_addr, mem_d_addr: reg32;
signal cnt_i_ref,cnt_i_hit : integer;
signal cnt_d_ref,cnt_d_rd_hit,cnt_d_wr_hit,cnt_d_flush : integer;
signal dump_ram : std_logic;
signal bit_rt : reg3;
-- Macnica development board's peripherals
signal disp0,disp1 : reg8; -- 7 segment displays
signal key : reg12; -- 12 key telephone keyboard
signal sw : reg4; -- 4 slide switches
signal led_r, led_g, led_b : std_logic; -- RGB leds (on board signals)
signal LCD_D : std_logic_vector(7 downto 0); -- LCD data bus
signal LCD_RS, LCD_RW, LCD_EN, LCD_BACKLIGHT : std_logic; -- LCD control
signal uart_txd, uart_rxd, uart_rts, uart_cts, uart_irq : std_logic;
signal sdc_cs, sdc_clk, sdc_mosi_o, sdc_miso_i : std_logic;
signal sdcke, sdscs, sdras, sdcas, sdwe : std_logic; -- SDRAM
signal sddqm0, sddqm1, sdba0, sdba1 : std_logic;
signal sdaddr : reg12;
signal sddata : reg16;
signal hDinp, hDout : reg32;
-- disk device, simulation only
signal dma_addr, dma_dinp, dma_dout, ram_addr, ram_inp : reg32;
signal dma_wr, ram_wr, dma_aval, dma_irq, ram_sel : std_logic;
signal dma_type, ram_xfer : reg4;
signal busReq, busFree_dly, dma_grant : std_logic;
begin -- TB
pll : mf_altpll port map (areset => a_reset, inclk0 => clock_50mhz,
c0 => phi0in, c1 => phi1in, c2 => phi2in, c3 => phi3in, c4 => clkin);
-- pll_io : mf_altpll_io port map (areset => a_reset, inclk0 => clock_50mhz,
-- c0 => clk2x, c1 => clk4x0, c2 => clk4x180);
clk4x0 <= '0';
clk4x180 <= '0';
mf_altclkctrl_inst_clk : mf_altclkctrl port map (
inclk => clkin, outclk => clk);
mf_altclkctrl_inst_clk4x : mf_altclkctrl port map (
inclk => clk4x180, outclk => clk4x);
mf_altclkctrl_inst_phi0 : mf_altclkctrl port map (
inclk => phi0in, outclk => phi0);
mf_altclkctrl_inst_phi1 : mf_altclkctrl port map (
inclk => phi1in, outclk => phi1);
mf_altclkctrl_inst_phi2 : mf_altclkctrl port map (
inclk => phi2in, outclk => phi2);
mf_altclkctrl_inst_phi3 : mf_altclkctrl port map (
inclk => phi3in, outclk => phi3);
-- synchronize reset
a_rst1 <= a_reset or rst;
U_SYNC_RESET1: FFD port map (clk, a_rst2, '1', a_rst1, rst);
U_SYNC_RESET2: FFD port map (clk, a_reset, '1', '1', a_rst2);
async_reset <= rst and ic_reset;
U_SYNC_RESET3: FFD port map (clk, rst, '1', async_reset, a_rst3);
U_SYNC_RESET4: FFD port map (clk, rst, '1', a_rst3, cpu_reset);
cpu_i_wait <= inst_wait;
cpu_d_wait <= data_wait and io_wait and sdram_wait;
io_wait <= io_lcd_wait and io_fpu_wait and io_sdc_wait;
not_waiting <= (inst_wait and data_wait and sdram_wait); -- and io_wait);
-- Count=Compare at IRQ7, UART at IRQ6, DMA at IRQ5, extCounter at IRQ4,
-- C=C U D E 0 0 sw1 sw0
-- uart+dma_disk+counter interrupts
irq <= ZERO & uart_irq & dma_irq & counter_irq & ZERO & ZERO;
-- irq <= b"000000"; -- NO interrupt requests
nmi <= NO; -- input port to TB
U_CORE: core
port map (cpu_reset, clk, phi1,phi2,phi3,
cpu_i_aVal, cpu_i_wait, i_addr, cpu_instr,
cpu_d_aVal, cpu_d_wait, d_addr, cpu_data_inp, cpu_data,
wr, cpu_xfer, busFree, nmi, irq, i_busError, d_busError);
U_INST_ADDR_DEC: inst_addr_decode
port map (rst, cpu_i_aVal, i_addr, inst_aVal, i_busError);
U_I_CACHE: i_cache
port map (rst, clk4x, ic_reset,
inst_aVal, inst_wait, i_addr, cpu_instr,
mem_i_sel, rom_rdy, mem_i_addr, datrom, cnt_i_ref,cnt_i_hit);
U_ROM: ROM generic map ("prog.bin")
port map (rst, clk, mem_i_sel,rom_rdy, phi3, mem_i_addr,datrom);
U_DATA_BUS_ERROR_DEC: busError_addr_decode
port map (rst, cpu_d_aVal, d_addr, d_busError);
-- d_busError <= '1'; -- only while testing the SDRAM
U_IO_ADDR_DEC: io_addr_decode
port map (rst, phi0, cpu_d_aVal, d_addr, dev_select_io,
io_print_sel, io_stdout_sel, io_stdin_sel, io_read_sel,
io_write_sel, io_counter_sel, io_fpu_sel, io_uart_sel,
io_sstats_sel, io_7seg_sel, io_keys_sel, io_lcd_sel,
io_sdc_sel, io_dma_sel, not_waiting);
U_DATA_ADDR_DEC: ram_addr_decode
port map (rst, cpu_d_aVal, d_addr,data_aVal, dev_select_ram);
U_SDRAM_ADDR_DEC: sdram_addr_decode
port map (rst, cpu_d_aVal, d_addr,sdram_aVal, dev_select_sdram);
dev_select <= dev_select_io or dev_select_ram; -- or dev_select_sdram;
with dev_select select
cpu_data_inp <= d_cache_d_out when b"0001",
stdin_d_out when b"0100",
read_d_out when b"0101",
counter_d_out when b"0111",
fpu_d_out when b"1000",
uart_d_out when b"1001",
-- sstats_d_out when b"1010",
keybd_d_out when b"1100",
lcd_d_out when b"1101",
sdc_d_out when b"1110",
-- sdram_d_out when b"1110",
dma_d_out when b"1111",
(others => 'X') when others;
U_D_CACHE: d_cache
port map (rst, clk4x,
data_aVal, data_wait, wr,
d_addr, cpu_data, d_cache_d_out, cpu_xfer,
mem_d_sel, ram_rdy, mem_wr,
mem_addr, datram_inp, datram_out, mem_xfer,
cnt_d_ref, cnt_d_rd_hit, cnt_d_wr_hit, cnt_d_flush);
U_BUSFREE_DLY: FFD port map (clk, rst, '1', busFree, busFree_dly);
dma_grant <= busFree_dly and busReq;
ram_xfer <= dma_type when dma_grant = YES else mem_xfer;
ram_addr <= dma_addr when dma_grant = YES else mem_addr;
ram_wr <= dma_wr when dma_grant = YES else mem_wr;
ram_sel <= '0' when dma_grant = YES else mem_d_sel;
ram_inp <= dma_dout when dma_grant = YES else datram_out;
U_RAM: RAM generic map ("data.bin", "dump.data")
port map (rst, clk, ram_sel, ram_rdy, ram_wr, phi3,
ram_addr, ram_inp, datram_inp, ram_xfer, dump_ram);
-- U_RAM: RAM generic map ("data.bin", "dump.data")
-- port map (rst, clk, mem_d_sel, ram_rdy, mem_wr, phi2,
-- mem_addr, datram_out, datram_inp, mem_xfer, dump_ram);
-- busReq <= '0';
U_DISK: DISK
port map (rst,clk, phi1, io_dma_sel, open, wr, -- '1', open,
busFree, busReq, dma_grant,
d_addr(4 downto 2), cpu_data, dma_d_out, dma_irq,
dma_addr, datram_inp, dma_dout, dma_wr, dma_aval, dma_type);
U_SDRAMc: SDRAM_controller port map
(rst, clk, clk2x, sdram_aVal, sdram_wait, wr,
cpu_xfer, d_addr(25 downto 0), hDinp,hDout,
sdcke,sdscs,sdras,sdcas,sdwe,sddqm0,sddqm1,sdba0,sdba1,sdaddr,sddata);
sdcke <= '1';
U_to_stdout: to_stdout
port map (rst,clk, io_stdout_sel, wr, cpu_data);
U_from_stdin: from_stdin
port map (rst,clk, io_stdin_sel, wr, stdin_d_out);
U_read_inp: read_data_file generic map ("input.data")
port map (rst,clk, io_read_sel, wr, d_addr,read_d_out, cpu_xfer);
U_write_out: write_data_file generic map ("output.data")
port map (rst,clk, io_write_sel, wr, d_addr,cpu_data, cpu_xfer, dump_ram);
U_print_data: print_data
port map (rst,clk, io_print_sel, wr, cpu_data);
U_interrupt_counter: do_interrupt -- external counter+interrupt
port map (rst,clk, io_counter_sel, wr, cpu_data,
counter_d_out, counter_irq);
U_to_7seg: to_7seg
port map (rst,clk,io_7seg_sel, wr, cpu_data, disp0, disp1,
led_r, led_g, led_b);
key <= b"000000000000", b"000000000100" after 1 us, b"000000000000" after 2 us, b"001000000000" after 3 us, b"000000000000" after 4 us, b"000001000000" after 5 us, b"000000000000" after 6 us;
sw <= b"0000";
U_read_keys: read_keys
generic map (6) -- debouncing interval, in clock cycles
port map (rst,clk, io_keys_sel, keybd_d_out, key, sw);
U_LCD_display: LCD_display
port map (rst, clk, io_lcd_sel, io_lcd_wait,
wr, d_addr(2), cpu_data, lcd_d_out,
lcd_d, lcd_rs, lcd_rw, lcd_en, lcd_backlight);
U_simple_uart: simple_uart
port map (rst,clk, io_uart_sel, wr, d_addr(3 downto 2),
cpu_data, uart_d_out,
uart_txd, uart_rxd, uart_rts, uart_cts, uart_irq, bit_rt);
-- uncoment next line for loop back, comment out previous line
-- uart_txd, uart_txd, uart_rts, uart_cts, uart_irq, bit_rt);
uart_cts <= uart_rts;
U_uart_remota: remota generic map ("serial.out","serial.inp")
port map (rst, clk, uart_rts, uart_txd, uart_rxd, bit_rt);
U_sdcard: SDcard
port map (rst, clk, io_sdc_sel, io_sdc_wait,
wr, d_addr(3 downto 2), cpu_data, sdc_d_out,
sdc_cs, sdc_clk, sdc_mosi_o, sdc_miso_i, open);
U_FPU: FPU
port map (rst,clk, io_FPU_sel, io_FPU_wait, wr, d_addr(5 downto 2),
cpu_data, fpu_d_out);
-- U_sys_stats: sys_stats -- CPU reads system counters
-- port map (cpu_reset,clk, io_sstats_sel, wr, d_addr, sstats_d_out,
-- cnt_d_ref,cnt_d_rd_hit,cnt_d_wr_hit,cnt_d_flush,
-- cnt_i_ref,cnt_i_hit);
U_clock: process -- simulate external clock
begin
clock_50mhz <= '1';
clk2x <= '1';
wait for CLOCK_PER / 4;
clk2x <= '0';
wait for CLOCK_PER / 4;
clock_50mhz <= '0';
clk2x <= '1';
wait for CLOCK_PER / 4;
clk2x <= '0';
wait for CLOCK_PER / 4;
end process; -- -------------------------------------------------------
-- simulate reset switch bounces
a_reset <= '1', '0' after 5 ns, '1' after 8 ns, '0' after 12 ns, '1' after 14 ns, '0' after 18 ns, '1' after 25 ns;
end architecture TB;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- instruction address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity inst_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_i_aVal : in std_logic; -- CPU instr addr valid (act=0)
addr : in reg32; -- CPU address
aVal : out std_logic; -- decoded address in range (act=0)
i_busError : out std_logic); -- decoded address not in range (act=0)
end entity inst_addr_decode;
architecture behavioral of inst_addr_decode is
constant HI_ADDR : integer := HI_SEL_BITS;
constant LO_ADDR : integer := log2_ceil(INST_BASE_ADDR + INST_MEM_SZ);
constant PREFIX : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'0');
signal in_range : boolean;
begin
in_range <= (addr(HI_ADDR downto LO_ADDR) = PREFIX);
aVal <= '0' when ( cpu_i_aVal = '0' and in_range ) else
'1';
i_busError <= '0' when ( cpu_i_aVal = '0' and not(in_range) ) else
'1';
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- RAM address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity ram_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
aVal : out std_logic; -- data address (act=0)
dev_select : out reg4); -- select input to CPU
constant LO_ADDR : integer := log2_ceil(DATA_BASE_ADDR);
constant HI_ADDR : integer := log2_ceil(DATA_BASE_ADDR + DATA_MEM_SZ - 1);
constant in_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '1');
constant ng_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '0');
constant oth : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'1');
constant ng_o : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'0');
end entity ram_addr_decode;
architecture behavioral of ram_addr_decode is
-- constant LO_ADDR : natural := log2_ceil(DATA_BASE_ADDR);
-- constant HI_ADDR : natural := log2_ceil(DATA_BASE_ADDR + DATA_MEM_SZ - 1);
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
constant a_hi : std_logic_vector(31 downto HI_ADDR+1) := (others=>'0');
constant a_lo : std_logic_vector(LO_ADDR-1 downto 0) := (others=>'0');
constant a_bits : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'1');
constant a_mask : std_logic_vector := a_hi & a_bits & a_lo;
constant LO_RAM : natural := 0;
constant HI_RAM : natural := log2_ceil(DATA_MEM_SZ-1);
constant r_hi : std_logic_vector(31 downto HI_RAM+1) := (others=>'1');
constant r_lo : std_logic_vector(HI_RAM downto LO_RAM) := (others=>'0');
constant r_mask : std_logic_vector := r_hi & r_lo;
signal in_range : boolean;
constant RAM_ADDR_BOTTOM : natural :=
to_integer(signed(x_DATA_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)));
constant RAM_ADDR_RANGE : natural :=
(to_integer(signed(x_DATA_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)))
+
to_integer(signed(x_DATA_MEM_SZ(HI_SEL_BITS downto LO_SEL_BITS))));
constant RAM_ADDR_TOP : natural := RAM_ADDR_BOTTOM + RAM_ADDR_RANGE;
begin
-- in_range <= ( rst = '1'
-- and ((addr and a_mask) = x_DATA_BASE_ADDR)
-- and ((addr and r_mask) = x_DATA_BASE_ADDR) );
-- this works only for small RAMS
-- in_range <= ( addr(HI_SEL_BITS downto LO_SEL_BITS)
-- =
-- x_DATA_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS) );
-- this is ONLY acceptable for simulations;
-- computing these differences is TOO expensive for synthesis
in_range <= ( (to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
>=
RAM_ADDR_BOTTOM)
and
(to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
<
RAM_ADDR_TOP)
);
aVal <= '0' when (cpu_d_aVal = '0' and in_range) else '1';
dev_select <= b"0001" when (cpu_d_aVal = '0' and in_range) else b"0000";
assert TRUE -- cpu_d_aVal = '1'
report LF & "e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" LO_AD " & integer'image(LO_ADDR) &
" HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask)
severity NOTE;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- busError address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity busError_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
d_busError : out std_logic); -- decoded address not in range (act=0)
end entity busError_addr_decode;
architecture behavioral of busError_addr_decode is
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
-- I/O constants
constant IO_RANGE : integer := IO_ADDR_RANGE * IO_MAX_NUM_DEVS;
constant LO_DEV : natural := 0;
constant HI_DEV : natural := log2_ceil(IO_RANGE);
constant x_hi : std_logic_vector(31 downto HI_DEV) := (others=>'1');
constant x_lo : std_logic_vector(HI_DEV-1 downto 0) := (others=>'0');
constant x_mask : std_logic_vector := x_hi & x_lo; -- 1..10..0
-- RAM constants
constant LO_ADDR : natural := log2_ceil(DATA_BASE_ADDR);
constant HI_ADDR : natural := log2_ceil(DATA_BASE_ADDR + DATA_MEM_SZ - 1);
constant a_hi : std_logic_vector(31 downto HI_ADDR+1) := (others=>'0');
constant a_lo : std_logic_vector(LO_ADDR-1 downto 0) := (others=>'0');
constant a_bits : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'1');
constant a_mask : std_logic_vector := a_hi & a_bits & a_lo; -- 0..0110..0
constant LO_RAM : natural := 0;
constant HI_RAM : natural := log2_ceil(DATA_MEM_SZ-1);
constant r_hi : std_logic_vector(31 downto HI_RAM+1) := (others=>'1');
constant r_lo : std_logic_vector(HI_RAM downto LO_RAM) := (others=>'0');
constant r_mask : std_logic_vector := r_hi & r_lo; -- 1..10..0
signal in_range, io_in_range : boolean;
begin
in_range <= ( rst = '1' and
((addr and a_mask) = x_DATA_BASE_ADDR) and
((addr and r_mask) = x_DATA_BASE_ADDR) );
io_in_range <= ( (addr and x_mask) = x_IO_BASE_ADDR );
d_busError <= '0' when ( (cpu_d_aVal = '0') and
(not(in_range) and not(io_in_range)) ) else '1';
assert TRUE -- cpu_d_aVal = '1'
report LF &
" e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" LO_AD " & integer'image(LO_ADDR) &
" HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask)
severity NOTE;
assert TRUE -- cpu_d_aVal = '1' and io_busError
report LF &
" e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" x_hi " & SLV2STR(x_hi) &
" x_lo " & SLV2STR(x_lo) &
" x_mask " & SLV32HEX(x_mask) & LF &
" LO_DEV " & integer'image(LO_DEV) &
" HI_DEV " & integer'image(HI_DEV)
severity NOTE;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- I/O address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity io_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
clk : in std_logic; -- clk sparates back-to-back refs
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
dev_select : out reg4; -- select input to CPU
print_sel : out std_logic; -- std_out (integer) (act=0)
stdout_sel : out std_logic; -- std_out (character) (act=0)
stdin_sel : out std_logic; -- std_inp (character) (act=0)
read_sel : out std_logic; -- file read (act=0)
write_sel : out std_logic; -- file write (act=0)
counter_sel : out std_logic; -- interrupt counter (act=0)
FPU_sel : out std_logic; -- floating point unit (act=0)
UART_sel : out std_logic; -- floating point unit (act=0)
SSTATS_sel : out std_logic; -- system statistics (act=0)
dsp7seg_sel : out std_logic; -- 7 segments display (act=0)
keybd_sel : out std_logic; -- telephone keyboard (act=0)
lcd_sel : out std_logic; -- LCD 2x16 char display (act=0)
sdc_sel : out std_logic; -- SDcard reader/writer (act=0)
dma_sel : out std_logic; -- DMA/disk controller (act=0)
not_waiting : in std_logic); -- no other device is waiting
end entity io_addr_decode;
architecture behavioral of io_addr_decode is
constant LO_SEL_ADDR : integer := log2_ceil(IO_ADDR_RANGE);
constant HI_SEL_ADDR : integer := LO_SEL_ADDR + log2_ceil(IO_ADDR_BITS);
constant IO_RANGE : integer := IO_ADDR_RANGE * IO_MAX_NUM_DEVS;
constant LO_ADDR : integer := log2_ceil(IO_BASE_ADDR);
constant HI_ADDR : integer := log2_ceil(IO_BASE_ADDR + IO_RANGE - 1);
constant in_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '1');
constant ng_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '0');
constant oth : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'1');
constant ng_o : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'0');
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
-- I/O constants
constant LO_DEV : natural := 0;
constant HI_DEV : natural := log2_ceil(IO_RANGE-1);
constant x_hi : std_logic_vector(31 downto HI_DEV) := (others=>'1');
constant x_lo : std_logic_vector(HI_DEV-1 downto 0) := (others=>'0');
constant x_mask : std_logic_vector := x_hi & x_lo; -- 1..10..0
signal in_range : boolean;
signal aVal : std_logic;
signal dev : integer; -- DEBUGGING only
begin
-- in_range <= ((addr and x_mask) = x_IO_BASE_ADDR);
in_range <= ((addr(HI_ADDR downto LO_ADDR) and in_r) /= ng_r) and
((addr(HI_SEL_BITS downto HI_ADDR+1) and oth) = ng_o);
aVal <= '0' when ( cpu_d_aVal = '0' and not_waiting = '1' and
in_range ) else '1';
dev <= to_integer(signed(addr(IO_ADDR_BITS downto LO_SEL_ADDR)))
when aVal = '0' else 0;
U_decode: process(clk, aVal, addr, dev)
variable dev_sel : reg4;
constant is_noise : integer := 0;
constant is_print : integer := 2;
constant is_stdout : integer := 3;
constant is_stdin : integer := 4;
constant is_read : integer := 5;
constant is_write : integer := 6;
constant is_count : integer := 7;
constant is_FPU : integer := 8;
constant is_UART : integer := 9;
constant is_SSTATS : integer := 10;
constant is_dsp7seg : integer := 11;
constant is_keybd : integer := 12;
constant is_lcd : integer := 13;
constant is_sdc : integer := 14;
constant is_dma : integer := 15;
begin
print_sel <= '1';
stdout_sel <= '1';
stdin_sel <= '1';
read_sel <= '1';
write_sel <= '1';
counter_sel <= '1';
FPU_sel <= '1';
UART_sel <= '1';
SSTATS_sel <= '1';
dsp7seg_sel <= '1';
keybd_sel <= '1';
lcd_sel <= '1';
sdc_sel <= '1';
dma_sel <= '1';
case dev is -- to_integer(signed(addr(HI_ADDR downto LO_ADDR))) is
when 0 => dev_sel := std_logic_vector(to_unsigned(is_print, 4));
print_sel <= aVal or clk;
when 1 => dev_sel := std_logic_vector(to_unsigned(is_stdout, 4));
stdout_sel <= aVal or clk;
when 2 => dev_sel := std_logic_vector(to_unsigned(is_stdin, 4));
stdin_sel <= aVal or clk;
when 3 => dev_sel := std_logic_vector(to_unsigned(is_read, 4));
read_sel <= aVal or clk;
when 4 => dev_sel := std_logic_vector(to_unsigned(is_write, 4));
write_sel <= aVal or clk;
when 5 => dev_sel := std_logic_vector(to_unsigned(is_count, 4));
counter_sel <= aVal or clk;
when 6 => dev_sel := std_logic_vector(to_unsigned(is_FPU, 4));
FPU_sel <= aVal;
when 7 => dev_sel := std_logic_vector(to_unsigned(is_UART, 4));
UART_sel <= aVal;
when 8 => dev_sel := std_logic_vector(to_unsigned(is_SSTATS, 4));
SSTATS_sel <= aVal;
when 9 => dev_sel := std_logic_vector(to_unsigned(is_dsp7seg, 4));
dsp7seg_sel <= aVal;
when 10 => dev_sel := std_logic_vector(to_unsigned(is_keybd, 4));
keybd_sel <= aVal;
when 11 => dev_sel := std_logic_vector(to_unsigned(is_lcd, 4));
lcd_sel <= aVal;
when 12 => dev_sel := std_logic_vector(to_unsigned(is_sdc, 4));
sdc_sel <= aVal;
when 13 => dev_sel := std_logic_vector(to_unsigned(is_dma, 4));
dma_sel <= aVal or clk;
when others => dev_sel := std_logic_vector(to_unsigned(is_noise, 4));
end case;
assert TRUE report "IO_addr "& SLV32HEX(addr); -- DEBUG
if aVal = '0' then
dev_select <= dev_sel;
else
dev_select <= std_logic_vector(to_unsigned(is_noise, 4));
end if;
end process U_decode;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- SDRAM address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity sdram_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
aVal : out std_logic; -- data address (act=0)
dev_select : out reg4); -- select input to CPU
constant LO_ADDR : integer := log2_ceil(SDRAM_BASE_ADDR);
constant HI_ADDR : integer := log2_ceil(SDRAM_BASE_ADDR + SDRAM_MEM_SZ - 1);
constant in_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '1');
constant ng_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '0');
constant oth : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'1');
constant ng_o : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'0');
end entity sdram_addr_decode;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture behavioral of sdram_addr_decode is
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
constant a_hi : std_logic_vector(31 downto HI_ADDR+1) := (others=>'0');
constant a_lo : std_logic_vector(LO_ADDR-1 downto 0) := (others=>'0');
constant a_bits : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'1');
constant a_mask : std_logic_vector := a_hi & a_bits & a_lo;
constant LO_RAM : natural := 0;
constant HI_RAM : natural := log2_ceil(SDRAM_MEM_SZ-1);
constant r_hi : std_logic_vector(31 downto HI_RAM+1) := (others=>'1');
constant r_lo : std_logic_vector(HI_RAM downto LO_RAM) := (others=>'0');
constant r_mask : std_logic_vector := r_hi & r_lo;
signal in_range : boolean;
constant SDRAM_ADDR_BOTTOM : natural :=
to_integer(signed(x_SDRAM_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)));
constant SDRAM_ADDR_RANGE : natural :=
(to_integer(signed(x_SDRAM_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)))
+
to_integer(signed(x_SDRAM_MEM_SZ(HI_SEL_BITS downto LO_SEL_BITS))));
constant SDRAM_ADDR_TOP : natural := SDRAM_ADDR_BOTTOM + SDRAM_ADDR_RANGE;
begin
-- this is ONLY acceptable for simulations;
-- computing these differences is TOO expensive for synthesis
in_range <= ( (to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
>=
SDRAM_ADDR_BOTTOM)
and
(to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
<
SDRAM_ADDR_TOP)
);
aVal <= '0' when (cpu_d_aVal = '0' and in_range) else '1';
dev_select <= b"1110" when (cpu_d_aVal = '0' and in_range) else b"0000";
assert TRUE -- cpu_d_aVal = '1'
report "e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" LO_AD " & integer'image(LO_ADDR) &
" HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask)
severity NOTE;
end architecture behavioral;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of sdram_addr_decode is
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
constant a_hi : std_logic_vector(31 downto HI_ADDR+1) := (others=>'0');
constant a_lo : std_logic_vector(LO_ADDR-1 downto 0) := (others=>'0');
constant a_bits : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'1');
constant a_mask : std_logic_vector := a_hi & a_bits & a_lo;
constant LO_RAM : natural := 0;
constant HI_RAM : natural := log2_ceil(SDRAM_MEM_SZ-1);
constant r_hi : std_logic_vector(31 downto HI_RAM+1) := (others=>'1');
constant r_lo : std_logic_vector(HI_RAM downto LO_RAM) := (others=>'0');
constant r_mask : std_logic_vector := r_hi & r_lo;
signal in_range : boolean;
constant SDRAM_ADDR_BOTTOM : natural :=
to_integer(signed(x_SDRAM_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)));
constant SDRAM_ADDR_RANGE : natural :=
(to_integer(signed(x_SDRAM_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)))
+
to_integer(signed(x_SDRAM_MEM_SZ(HI_SEL_BITS downto LO_SEL_BITS))));
constant SDRAM_ADDR_TOP : natural := SDRAM_ADDR_BOTTOM + SDRAM_ADDR_RANGE;
begin
in_range <= FALSE;
-- this is ONLY acceptable for simulations;
-- computing these differences is TOO expensive for synthesis
-- in_range <= ( (to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
-- >=
-- SDRAM_ADDR_BOTTOM)
-- and
-- (to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
-- <
-- SDRAM_ADDR_TOP)
-- );
aVal <= '0' when (cpu_d_aVal = '0' and in_range) else '1';
dev_select <= b"1110" when (cpu_d_aVal = '0' and in_range) else b"0000";
assert TRUE -- cpu_d_aVal = '1'
report "e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" LO_AD " & integer'image(LO_ADDR) &
" HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask)
severity NOTE;
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
use work.all;
configuration CFG_TB of TB_CMIPS is
for TB
end for;
end configuration CFG_TB;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
gpl-3.0
|
07daa48deb91dc0c084b5e47c3ef2d4a
| 0.534598 | 3.273003 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/opencores/i2c/i2c_master_byte_ctrl.vhd
| 4 | 13,633 |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; byte-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004/02/18 11:41:48 rherveille Exp $
--
-- $Date: 2004/02/18 11:41:48 $
-- $Revision: 1.5 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_byte_ctrl.vhd,v $
-- Revision 1.5 2004/02/18 11:41:48 rherveille
-- Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
--
-- Revision 1.4 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.3 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.2 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
-- Modified by Jan Andersson ([email protected]:.
-- Changed std_logic_arith to numeric_std.
-- Propagate filter generic
--
------------------------------------------
-- Byte controller section
------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity i2c_master_byte_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- output signals
cmd_ack : out std_logic; -- command done
ack_out : out std_logic;
i2c_busy : out std_logic; -- arbitration lost
i2c_al : out std_logic; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_byte_ctrl;
architecture structural of i2c_master_byte_ctrl is
component i2c_master_bit_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command done
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_bit_ctrl;
-- commands for bit_controller block
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
-- signals for bit_controller
signal core_cmd : std_logic_vector(3 downto 0);
signal core_ack, core_txd, core_rxd : std_logic;
signal al : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
-- Added init value to dcnt to prevent simulation meta-value
-- - [email protected]
-- removed init value as it is not compatible with Formality
-- - [email protected]
signal dcnt : std_logic_vector(2 downto 0)
-- pragma translate_off
:= (others => '0')
-- pragma translate_on
; -- data counter
signal cnt_done : std_logic;
begin
-- hookup bit_controller
bit_ctrl: i2c_master_bit_ctrl
generic map (filter, dynfilt)
port map(
clk => clk,
rst => rst,
nReset => nReset,
ena => ena,
clk_cnt => clk_cnt,
cmd => core_cmd,
cmd_ack => core_ack,
busy => i2c_busy,
al => al,
din => core_txd,
dout => core_rxd,
filt => filt,
scl_i => scl_i,
scl_o => scl_o,
scl_oen => scl_oen,
sda_i => sda_i,
sda_o => sda_o,
sda_oen => sda_oen
);
i2c_al <= al;
-- generate host-command-acknowledge
cmd_ack <= host_ack;
-- generate go-signal
go <= (read or write or stop) and not host_ack;
-- assign Dout output to shift-register
dout <= sr;
-- generate shift register
shift_register: process(clk, nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
-- generate data-counter
data_cnt: process(clk, nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= (others => '1'); -- load counter with 7
elsif (shift = '1') then
dcnt <= dcnt -1;
end if;
end if;
end process data_cnt;
cnt_done <= '1' when (dcnt = "000") else '0';
--
-- state machine
--
statemachine : block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states;
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder: process(clk, nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or al = '1') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
else
-- initialy reset all signal
core_txd <= sr(7);
shift <= '0';
ld <= '0';
host_ack <= '0';
case c_state is
when st_idle =>
if (go = '1') then
if (start = '1') then
c_state <= st_start;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
else -- stop
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when st_start =>
if (core_ack = '1') then
if (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when st_write =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when st_read =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= st_read; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when st_ack =>
if (core_ack = '1') then
-- check for stop; Should a STOP command be generated ?
if (stop = '1') then
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
else
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when st_stop =>
if (core_ack = '1') then
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
when others => -- illegal states
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
report ("Byte controller entered illegal state.");
end case;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture structural;
|
gpl-2.0
|
71af845a60b279e5d1e63672c20e2e8d
| 0.470403 | 3.870812 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/syncreg.vhd
| 1 | 2,509 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncreg
-- File: syncreg.vhd
-- Author: Aeroflex Gaisler AB
-- Description: Technology wrapper for sync registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity syncreg is
generic (
tech : integer := 0;
stages : integer range 1 to 5 := 2
);
port (
clk : in std_ulogic;
d : in std_ulogic;
q : out std_ulogic
);
end;
architecture tmap of syncreg is
begin
sync0 : if has_syncreg(tech) = 0 generate
--syncreg : block
-- signal c : std_logic_vector(stages-1 downto 0);
--begin
-- x0 : process(clk)
-- begin
-- if rising_edge(clk) then
-- for i in 0 to stages-1 loop
-- c(i) <= d;
-- if i /= 0 then c(i) = c(i-1); end if;
-- end loop;
-- end if;
-- end process;
-- q <= c(stages-1);
--end block syncreg;
syncreg : block
signal c : std_logic_vector(stages downto 0);
attribute keep : boolean;
attribute keep of c : signal is true;
begin
c(0) <= d;
syncregs : for i in 1 to stages generate
dff : grdff
generic map(tech => tech)
port map(clk => clk, d => c(i-1), q => c(i));
end generate;
q <= c(stages);
end block syncreg;
end generate;
end;
|
gpl-2.0
|
2a543c9c40607124868308b489ec3ea5
| 0.556796 | 4.001595 | false | false | false | false |
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/nor00.vhd
| 1 | 1,375 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nor00 is
port(
clknr: in std_logic ;
codopnr: in std_logic_vector ( 3 downto 0 );
portAnr: in std_logic_vector ( 7 downto 0 );
portBnr: in std_logic_vector ( 7 downto 0 );
inFlagnr: in std_logic;
outnr: out std_logic_vector ( 7 downto 0 );
outFlagnr: out std_logic );
end;
architecture nor0 of nor00 is
begin
pnor: process(codopnr, portAnr, portBnr)
begin
if(codopnr = "0101") then
outnr <= portAnr nor portBnr;
outFlagnr <= '1';
else
outnr <= (others => 'Z');
outFlagnr <= 'Z';
end if;
end process pnor;
-- pnand: process(clknd, codopnd, inFlagnd)
-- --variable auxnd: bit:='0';
-- begin
-- if (clknd = '1') then
----clknd'event and
-- if (codopnd = "0100") then
-- if (inFlagnd = '1') then
-- --if (auxnd = '0') then
-- --auxnd:= '1';
-- outnd <= portAnd nand portBnd;
-- outFlagnd <= '1';
-- --end if;
-- else
-- outFlagnd <= '0';
-- end if;
-- else
-- outnd <= (others => 'Z');
-- outFlagnd <= 'Z';
-- --auxnd:='0';
-- end if;
-- end if;
-- end process pnand;
end nor0;
|
apache-2.0
|
11fcd3a868aaab0fe87087585290fc03
| 0.501091 | 3.021978 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-terasic-sockit/ddr3if.vhd
| 1 | 9,971 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
entity ddr3if is
generic (
hindex: integer;
haddr: integer := 16#400#;
hmask: integer := 16#000#;
burstlen: integer := 8
);
port (
pll_ref_clk: in std_ulogic;
global_reset_n: in std_ulogic;
mem_a: out std_logic_vector(14 downto 0);
mem_ba: out std_logic_vector(2 downto 0);
mem_ck: out std_ulogic;
mem_ck_n: out std_ulogic;
mem_cke: out std_ulogic;
mem_reset_n: out std_ulogic;
mem_cs_n: out std_ulogic;
mem_dm: out std_logic_vector(3 downto 0);
mem_ras_n: out std_ulogic;
mem_cas_n: out std_ulogic;
mem_we_n: out std_ulogic;
mem_dq: inout std_logic_vector(31 downto 0);
mem_dqs: inout std_logic_vector(3 downto 0);
mem_dqs_n: inout std_logic_vector(3 downto 0);
mem_odt: out std_ulogic;
oct_rzqin: in std_logic;
ahb_clk: in std_ulogic;
ahb_rst: in std_ulogic;
ahbsi: in ahb_slv_in_type;
ahbso: out ahb_slv_out_type
);
end;
architecture rtl of ddr3if is
component ddr3controller_0002 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_a : out std_logic_vector(14 downto 0); -- mem_a
mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n
mem_reset_n : out std_logic; -- mem_reset_n
mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
avl_ready : out std_logic; -- waitrequest_n
avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer
avl_addr : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
avl_rdata_valid : out std_logic; -- readdatavalid
avl_rdata : out std_logic_vector(127 downto 0); -- readdata
avl_wdata : in std_logic_vector(127 downto 0) := (others => 'X'); -- writedata
avl_be : in std_logic_vector(15 downto 0) := (others => 'X'); -- byteenable
avl_read_req : in std_logic := 'X'; -- read
avl_write_req : in std_logic := 'X'; -- write
avl_size : in std_logic_vector(3 downto 0) := (others => 'X'); -- burstcount
local_init_done : out std_logic; -- local_init_done
local_cal_success : out std_logic; -- local_cal_success
local_cal_fail : out std_logic; -- local_cal_fail
oct_rzqin : in std_logic := 'X'; -- rzqin
pll_mem_clk : out std_logic; -- pll_mem_clk
pll_write_clk : out std_logic; -- pll_write_clk
pll_locked : out std_logic; -- pll_locked
pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk
pll_avl_clk : out std_logic; -- pll_avl_clk
pll_config_clk : out std_logic; -- pll_config_clk
-- pll_dr_clk : out std_logic; -- pll_dr_clk
-- pll_dr_clk_pre_phy_clk : out std_logic; -- pll_dr_clk_pre_phy_clk
pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk
afi_phy_clk : out std_logic; -- afi_phy_clk
pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk
);
end component ddr3controller_0002;
signal vcc: std_ulogic;
signal afi_clk, afi_half_clk, afi_reset_n: std_ulogic;
signal local_init_done, local_cal_success, local_cal_fail: std_ulogic;
signal ck_p_arr, ck_n_arr, cke_arr, cs_arr: std_logic_vector(0 downto 0);
signal rasn_arr, casn_arr, wen_arr, odt_arr: std_logic_vector(0 downto 0);
signal avlsi: ddravl_slv_in_type;
signal avlso: ddravl_slv_out_type;
begin
vcc <= '1';
mem_ck <= ck_p_arr(0);
mem_ck_n <= ck_n_arr(0);
mem_cke <= cke_arr(0);
mem_cs_n <= cs_arr(0);
mem_ras_n <= rasn_arr(0);
mem_cas_n <= casn_arr(0);
mem_we_n <= wen_arr(0);
mem_odt <= odt_arr(0);
ctrl0: ddr3controller_0002
port map (
pll_ref_clk => pll_ref_clk,
global_reset_n => global_reset_n,
soft_reset_n => vcc,
afi_clk => afi_clk,
afi_half_clk => afi_half_clk,
afi_reset_n => afi_reset_n,
afi_reset_export_n => open,
mem_a => mem_a,
mem_ba => mem_ba,
mem_ck => ck_p_arr,
mem_ck_n => ck_n_arr,
mem_cke => cke_arr,
mem_cs_n => cs_arr,
mem_dm => mem_dm,
mem_ras_n => rasn_arr,
mem_cas_n => casn_arr,
mem_we_n => wen_arr,
mem_reset_n => mem_reset_n,
mem_dq => mem_dq,
mem_dqs => mem_dqs,
mem_dqs_n => mem_dqs_n,
mem_odt => odt_arr,
avl_ready => avlso.ready,
avl_burstbegin => avlsi.burstbegin,
avl_addr => avlsi.addr(25 downto 0),
avl_rdata_valid => avlso.rdata_valid,
avl_rdata => avlso.rdata(127 downto 0),
avl_wdata => avlsi.wdata(127 downto 0),
avl_be => avlsi.be(15 downto 0),
avl_read_req => avlsi.read_req,
avl_write_req => avlsi.write_req,
avl_size => avlsi.size(3 downto 0),
local_init_done => local_init_done,
local_cal_success => local_cal_success,
local_cal_fail => local_cal_fail,
oct_rzqin => oct_rzqin,
pll_mem_clk => open,
pll_write_clk => open,
pll_locked => open,
pll_write_clk_pre_phy_clk => open,
pll_addr_cmd_clk => open,
pll_avl_clk => open,
pll_config_clk => open,
-- pll_dr_clk => open,
-- pll_dr_clk_pre_phy_clk => open,
pll_mem_phy_clk => open,
afi_phy_clk => open,
pll_avl_phy_clk => open
);
avlso.rdata(avlso.rdata'high downto 128) <= (others => '0');
ahb2avl0: ahb2avl_async
generic map (
hindex => hindex,
haddr => haddr,
hmask => hmask,
burstlen => burstlen,
nosync => 0,
avldbits => 128,
avlabits => 26
)
port map (
rst_ahb => ahb_rst,
clk_ahb => ahb_clk,
ahbsi => ahbsi,
ahbso => ahbso,
rst_avl => afi_reset_n,
clk_avl => afi_clk,
avlsi => avlsi,
avlso => avlso
);
end;
|
gpl-2.0
|
61b18f717448309787cfeb7af8cd89ec
| 0.463243 | 3.619238 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/tech/ec/orca/mem3.vhd
| 5 | 6,709 |
--
----- package mem3 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
PACKAGE mem3 IS
TYPE mem_type_5 IS array (Integer range <>) OF std_logic_vector(17 downto 0);
TYPE mem_type_6 IS array (Integer range <>) OF std_logic_vector(15 downto 0);
FUNCTION hex2bin (hex: character) RETURN std_logic_vector;
FUNCTION str3_slv12 (hex: string) RETURN std_logic_vector;
FUNCTION data2data (data_w: integer) RETURN integer;
FUNCTION data2addr_w (data_w: integer) RETURN integer;
FUNCTION data2data_w (data_w: integer) RETURN integer;
FUNCTION init_ram (hex: string; DATA_WIDTH_A : integer; DATA_WIDTH_B : integer) RETURN std_logic_vector;
FUNCTION init_ram1 (hex: string) RETURN mem_type_6;
FUNCTION str2slv (str: in string) RETURN std_logic_vector;
FUNCTION Valid_Address (IN_ADDR : in std_logic_vector) return boolean;
END mem3;
PACKAGE BODY mem3 IS
FUNCTION hex2bin (hex: character) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector (3 downto 0);
BEGIN
CASE hex IS
WHEN '0' =>
result := "0000";
WHEN '1' =>
result := "0001";
WHEN '2' =>
result := "0010";
WHEN '3' =>
result := "0011";
WHEN '4' =>
result := "0100";
WHEN '5' =>
result := "0101";
WHEN '6' =>
result := "0110";
WHEN '7' =>
result := "0111";
WHEN '8' =>
result := "1000";
WHEN '9' =>
result := "1001";
WHEN 'A'|'a' =>
result := "1010";
WHEN 'B'|'b' =>
result := "1011";
WHEN 'C'|'c' =>
result := "1100";
WHEN 'D'|'d' =>
result := "1101";
WHEN 'E'|'e' =>
result := "1110";
WHEN 'F'|'f' =>
result := "1111";
WHEN 'X'|'x' =>
result := "XXXX";
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION str5_slv18 (s : string(5 downto 1)) return std_logic_vector is
VARIABLE result : std_logic_vector(17 downto 0);
BEGIN
FOR i in 0 to 3 LOOP
result(((i+1)*4)-1 downto (i*4)) := hex2bin(s(i+1));
END LOOP;
result(17 downto 16) := hex2bin(s(5))(1 downto 0);
RETURN result;
END;
FUNCTION str4_slv16 (s : string(4 downto 1)) return std_logic_vector is
VARIABLE result : std_logic_vector(15 downto 0);
BEGIN
FOR i in 0 to 3 LOOP
result(((i+1)*4)-1 downto (i*4)) := hex2bin(s(i+1));
END LOOP;
RETURN result;
END;
FUNCTION str3_slv12 (hex: string) return std_logic_vector is
VARIABLE result : std_logic_vector(11 downto 0);
BEGIN
FOR i in 0 to 2 LOOP
result(((i+1)*4)-1 downto (i*4)) := hex2bin(hex(i+1));
END LOOP;
RETURN result;
END;
FUNCTION data2addr_w (data_w : integer) return integer is
VARIABLE result : integer;
BEGIN
CASE data_w IS
WHEN 1 =>
result := 13;
WHEN 2 =>
result := 12;
WHEN 4 =>
result := 11;
WHEN 9 =>
result := 10;
WHEN 18 =>
result := 9;
WHEN 36 =>
result := 8;
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION data2data_w (data_w : integer) return integer is
VARIABLE result : integer;
BEGIN
CASE data_w IS
WHEN 1 =>
result := 1;
WHEN 2 =>
result := 2;
WHEN 4 =>
result := 4;
WHEN 9 =>
result := 9;
WHEN 18 =>
result := 18;
WHEN 36 =>
result := 18;
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION data2data (data_w : integer) return integer is
VARIABLE result : integer;
BEGIN
CASE data_w IS
WHEN 1 =>
result := 8;
WHEN 2 =>
result := 4;
WHEN 4 =>
result := 2;
WHEN 9 =>
result := 36864;
WHEN 18 =>
result := 36864;
WHEN 36 =>
result := 36864;
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION init_ram (hex: string; DATA_WIDTH_A : integer; DATA_WIDTH_B : integer) RETURN std_logic_vector IS
CONSTANT length : integer := hex'length;
VARIABLE result1 : mem_type_5 (0 to ((length/5)-1));
VARIABLE result : std_logic_vector(((length*18)/5)-1 downto 0);
BEGIN
FOR i in 0 to ((length/5)-1) LOOP
result1(i) := str5_slv18(hex((i+1)*5 downto (i*5)+1));
END LOOP;
IF (DATA_WIDTH_A >= 9 and DATA_WIDTH_B >= 9) THEN
FOR j in 0 to 511 LOOP
result(((j*18) + 17) downto (j*18)) := result1(j)(17 downto 0);
END LOOP;
ELSE
FOR j in 0 to 511 LOOP
result(((j*18) + 7) downto (j*18)) := result1(j)(7 downto 0);
result((j*18) + 8) := '0';
result(((j*18) + 16) downto ((j*18) + 9)) := result1(j)(15 downto 8);
result((j*18) + 17) := '0';
END LOOP;
END IF;
RETURN result;
END;
FUNCTION init_ram1 (hex: string) RETURN mem_type_6 IS
CONSTANT length : integer := hex'length;
VARIABLE result : mem_type_6 (0 to ((length/4)-1));
BEGIN
FOR i in 0 to ((length/4)-1) LOOP
result(i) := str4_slv16(hex((i+1)*4 downto (i*4)+1));
END LOOP;
RETURN result;
END;
-- String to std_logic_vector
FUNCTION str2slv (
str : in string
) return std_logic_vector is
variable j : integer := str'length;
variable slv : std_logic_vector (str'length downto 1);
begin
for i in str'low to str'high loop
case str(i) is
when '0' => slv(j) := '0';
when '1' => slv(j) := '1';
when 'X' => slv(j) := 'X';
when 'U' => slv(j) := 'U';
when others => slv(j) := 'X';
end case;
j := j - 1;
end loop;
return slv;
end str2slv;
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
END mem3 ;
|
gpl-2.0
|
5b29d66bd42f9a717ec626fece0ca9b9
| 0.493069 | 3.696419 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-avnet-eval-xc4vlx60/leon3mp.vhd
| 1 | 27,385 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.avnet_eval.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
ddrfreq : integer := 100000 -- frequency of ddr clock in kHz
);
port (
resetn : in std_ulogic;
resoutn : out std_logic;
clk_100mhz : in std_ulogic;
clk_50mhz : in std_ulogic;
clk_200p : in std_ulogic;
clk_200n : in std_ulogic;
errorn : out std_ulogic;
-- prom interface
address : out std_logic_vector(21 downto 0);
data : inout std_logic_vector(15 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
romrstn : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(15 downto 0);
-- pragma translate_on
-- ddr memory
ddr_clk0 : out std_logic;
ddr_clk0b : out std_logic;
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke0 : out std_logic;
ddr_cs0b : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
-- UART for serial DCL/console I/O
serrx : in std_ulogic;
sertx : out std_ulogic;
rtsn : out std_ulogic;
ctsn : in std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- ethernet signals
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
erstn : out std_ulogic;
-- OLED display signals
disp_dcn : out std_ulogic;
disp_csn : out std_ulogic;
disp_rdn : out std_ulogic;
disp_wrn : out std_ulogic;
disp_d : inout std_logic_vector(7 downto 0);
phy_done : out std_ulogic;
rst_done : out std_ulogic
);
end;
architecture rtl of leon3mp is
component mig_36_1
port(
cntrl0_ddr_dq : inout std_logic_vector(15 downto 0);
cntrl0_ddr_a : out std_logic_vector(12 downto 0);
cntrl0_ddr_ba : out std_logic_vector(1 downto 0);
cntrl0_ddr_cke : out std_logic;
cntrl0_ddr_cs_n : out std_logic;
cntrl0_ddr_ras_n : out std_logic;
cntrl0_ddr_cas_n : out std_logic;
cntrl0_ddr_we_n : out std_logic;
cntrl0_ddr_dm : out std_logic_vector(1 downto 0);
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk200_p : in std_logic;
clk200_n : in std_logic;
init_done : out std_logic;
sys_reset_in_n : in std_logic;
cntrl0_clk_tb : out std_logic;
cntrl0_reset_tb : out std_logic;
cntrl0_wdf_almost_full : out std_logic;
cntrl0_af_almost_full : out std_logic;
cntrl0_read_data_valid : out std_logic;
cntrl0_app_wdf_wren : in std_logic;
cntrl0_app_af_wren : in std_logic;
cntrl0_burst_length_div2 : out std_logic_vector(2 downto 0);
cntrl0_app_af_addr : in std_logic_vector(35 downto 0);
cntrl0_app_wdf_data : in std_logic_vector(31 downto 0);
cntrl0_read_data_fifo_out : out std_logic_vector(31 downto 0);
cntrl0_app_mask_data : in std_logic_vector(3 downto 0);
cntrl0_ddr_dqs : inout std_logic_vector(1 downto 0);
cntrl0_ddr_ck : out std_logic_vector(0 downto 0);
cntrl0_ddr_ck_n : out std_logic_vector(0 downto 0)
);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal lclk : std_ulogic;
signal ddrclk, ddrrst, ddrclkfb : std_ulogic;
signal clkm, rstn, clkml, clk2x : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal tck, tms, tdi, tdo : std_ulogic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
-- signal dsubre : std_logic;
signal duart, ldsuen : std_logic;
signal rsertx, rserrx, rdsuen : std_logic;
signal rstraw : std_logic;
signal rstneg : std_logic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal lock : std_logic;
signal lclk50 : std_logic;
signal rst0_tb, rst0_tbn, clk0_tb : std_logic;
signal migi : mig_app_in_type;
signal migo : mig_app_out_type;
signal init_done : std_ulogic;
signal migrst : std_ulogic;
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector(13 downto 0); -- ddr address
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
romrstn <= rstn;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstneg;
rstneg <= not resetn;
rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw);
clk50_pad : clkpad generic map (tech => padtech) port map (clk_50mhz, lclk50);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, 0, 1, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk50, gnd(0), clkm, open, open, open, open, cgi, cgo);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
sh : if CFG_GRFPUSH = 1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0,
paddr => 0, srbanks => 1, ramaddr => 16#600#, rammask => 16#F00#, ram16 => 1 )
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none; ahbso(5) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (width => 22, tech => padtech)
port map (address, memo.address(22 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (testdata(15-i*8 downto 8-i*8), memo.data(15-i*8 downto 8-i*8),
memo.bdrive(i+2), memi.data(15-i*8 downto 8-i*8));
end generate;
-- pragma translate_on
bdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(15-i*8 downto 8-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- DDR memory controller -------------------------------------------
----------------------------------------------------------------------
ddrsp0 : if (CFG_DDRSP /= 0) generate
clk_pad : clkpad generic map (tech => padtech) port map (clk_100mhz, lclk);
ddrc : ddrspa generic map ( fabtech => virtex4, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => 100, rskew => -95
-- pragma translate_off
* 0 -- disable clock skew during simulation
-- pragma translate_on
, clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000, ddrbits => 16)
port map (
rstneg, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(4),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0);
ddr_cke0 <= ddr_cke(0); ddr_cs0b <= ddr_csb(0);
ddr_ad <= ddr_adl(12 downto 0);
end generate;
migsp0 : if (CFG_MIG_DDR2 = 1) generate
ahb2mig0 : entity work.ahb2mig_avnet_eval
generic map ( hindex => 0, haddr => 16#400#, hmask => 16#FE0#,
MHz => 100, Mbyte => 32)
port map (
rst_ahb => rstn, rst_ddr => rst0_tbn, rst_50 => rstneg,
clk_ahb => clkm, clk_ddr => clk0_tb, clk_50 => lclk50,
init_done => init_done, ahbsi => ahbsi, ahbso => ahbso(0), migi => migi, migo => migo);
migv5 : mig_36_1
port map(
cntrl0_ddr_dq => ddr_dq,
cntrl0_ddr_a => ddr_ad(12 downto 0),
cntrl0_ddr_ba => ddr_ba,
cntrl0_ddr_cke => ddr_cke0,
cntrl0_ddr_cs_n => ddr_cs0b,
cntrl0_ddr_ras_n => ddr_rasb,
cntrl0_ddr_cas_n => ddr_casb,
cntrl0_ddr_we_n => ddr_web,
cntrl0_ddr_dm => ddr_dm,
sys_clk_p => clk_100mhz, clk200_p => clk_200p,
sys_clk_n => clk_100mhz, clk200_n => clk_200n,
init_done => init_done,
sys_reset_in_n => migi.mig_rst,
cntrl0_reset_tb => rst0_tb, cntrl0_clk_tb => clk0_tb,
cntrl0_wdf_almost_full => migo.app_wdf_afull,
cntrl0_af_almost_full => migo.app_af_afull,
cntrl0_read_data_valid => migo.app_rd_data_valid,
cntrl0_app_wdf_wren => migi.app_wdf_wren,
cntrl0_app_af_wren => migi.app_en,
cntrl0_app_af_addr => migi.app_addr,
cntrl0_app_wdf_data => migi.app_wdf_data,
cntrl0_read_data_fifo_out => migo.app_rd_data,
cntrl0_app_mask_data => migi.app_wdf_mask,
cntrl0_ddr_dqs => ddr_dqs,
cntrl0_ddr_ck => ddr_clk(0 downto 0),
cntrl0_ddr_ck_n => ddr_clkb(0 downto 0)
);
ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0);
rst0_tbn <= not rst0_tb;
-- lock <= cgo.clklock;
lock <= init_done and rst0_tbn;
-- led(7) <= init_done;
end generate;
phy_done <= init_done;
rst_done <= migi.mig_rst;
noddr : if (CFG_DDRSP + CFG_MIG_DDR2) = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => 12 --CFG_GRGPIO_WIDTH
)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
disp_csn_pad : outpad generic map (tech => padtech)
port map (disp_csn, gpioo.dout(8));
disp_dcn_pad : outpad generic map (tech => padtech)
port map (disp_dcn, gpioo.dout(9));
disp_rdn_pad : outpad generic map (tech => padtech)
port map (disp_rdn, gpioo.dout(10));
disp_wrn_pad : outpad generic map (tech => padtech)
port map (disp_wrn, gpioo.dout(11));
disp_d_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech)
port map (disp_d(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
phyrstadr => 3, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
erstn_pad : outpad generic map (tech => padtech)
port map (erstn, rstn);
end generate;
-----------------------------------------------------------------------
--- AHB DMA ----------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH,
-- pindex => 12, paddr => 12, dbuf => 32)
-- port map (rstn, clkm, apbi, apbo(12), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH));
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 9 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
resoutn <= rstn;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design for Avnet Virtex4 Eval board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
-- use switch 1 to multiplex DSU UART and UART1
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, ldsuen);
duart <= rdsuen when CFG_AHB_UART /= 0 else '0';
rxd1 <= txd1 when duart = '1' else rserrx;
rsertx <= duo.txd when duart = '1' else txd1;
dui.rxd <= rserrx when duart = '1' else '1';
led_rx <= not rserrx;
p1 : process(clkm)
begin
if rising_edge(clkm) then
sertx <= rsertx; rserrx <= serrx; rdsuen <= ldsuen;
rtsn <= '0';
led_tx <= not rsertx;
end if;
end process;
end rtl;
|
gpl-2.0
|
2a8809a20915c9edda1f9f43ec4236ec
| 0.541245 | 3.567613 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep3c25-eek/leon3mp.vhd
| 1 | 32,910 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2008 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.i2c.all;
use gaisler.spi.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- flash/ssram bus
address : out std_logic_vector(25 downto 1);
data : inout std_logic_vector(31 downto 0);
romsn : out std_ulogic;
oen : out std_logic;
writen : out std_logic;
rstoutn : out std_ulogic;
ssram_cen : out std_logic;
ssram_wen : out std_logic;
ssram_bw : out std_logic_vector (0 to 3);
ssram_oen : out std_ulogic;
ssram_clk : out std_ulogic;
ssram_adscn : out std_ulogic;
-- ssram_adsp_n : out std_ulogic;
-- ssram_adv_n : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
-- DDR
ddr_clk : out std_logic;
ddr_clkn : out std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- I/O port
gpio : in std_logic_vector(CFG_GRGPIO_WIDTH-3 downto 0);
-- Connections over HSMC connector
-- LCD touch panel display
hc_vd : out std_logic;
hc_hd : out std_logic;
hc_den : out std_logic;
hc_nclk : out std_logic;
hc_lcd_data : out std_logic_vector(7 downto 0);
hc_grest : out std_logic;
hc_scen : out std_logic;
hc_sda : inout std_logic;
hc_adc_penirq_n : in std_logic;
hc_adc_dout : in std_logic;
hc_adc_busy : in std_logic;
hc_adc_din : out std_logic;
hc_adc_dclk : out std_logic;
hc_adc_cs_n : out std_logic; -- Shared with video decoder
-- Shared by video decoder and audio codec
hc_i2c_sclk : out std_logic;
hc_i2c_sdat : inout std_logic;
-- Video decoder
hc_td_d : inout std_logic_vector(7 downto 0);
hc_td_hs : in std_logic;
hc_td_vs : in std_logic;
hc_td_27mhz : in std_logic;
hc_td_reset : out std_logic;
-- Audio codec
hc_aud_adclrck : out std_logic;
hc_aud_adcdat : in std_logic;
hc_aud_daclrck : out std_logic;
hc_aud_dacdat : out std_logic;
hc_aud_bclk : out std_logic;
hc_aud_xck : out std_logic;
-- SD card
hc_sd_dat : inout std_logic;
hc_sd_dat3 : inout std_logic;
hc_sd_cmd : inout std_logic;
hc_sd_clk : inout std_logic;
-- Ethernet PHY
hc_tx_d : out std_logic_vector(3 downto 0);
hc_rx_d : in std_logic_vector(3 downto 0);
hc_tx_clk : in std_logic;
hc_rx_clk : in std_logic;
hc_tx_en : out std_logic;
hc_rx_dv : in std_logic;
hc_rx_crs : in std_logic;
hc_rx_err : in std_logic;
hc_rx_col : in std_logic;
hc_mdio : inout std_logic;
hc_mdc : out std_logic;
hc_eth_reset_n : out std_logic;
-- RX232 (console/debug UART)
hc_uart_rxd : in std_logic;
hc_uart_txd : out std_logic;
-- PS/2
hc_ps2_dat : inout std_logic;
hc_ps2_clk : inout std_logic;
-- VGA/DAC
hc_vga_data : out std_logic_vector(9 downto 0);
hc_vga_clock : out std_ulogic;
hc_vga_hs : out std_ulogic;
hc_vga_vs : out std_ulogic;
hc_vga_blank : out std_ulogic;
hc_vga_sync : out std_ulogic;
-- I2C EEPROM
hc_id_i2cscl : out std_logic;
hc_id_i2cdat : inout std_logic
);
end;
architecture rtl of leon3mp is
component serializer
generic (
length : integer := 8 -- vector length
);
port (
clk : in std_ulogic;
sync : in std_ulogic;
ivec0 : in std_logic_vector((length-1) downto 0);
ivec1 : in std_logic_vector((length-1) downto 0);
ivec2 : in std_logic_vector((length-1) downto 0);
ovec : out std_logic_vector((length-1) downto 0)
);
end component;
component altera_eek_clkgen
generic (
clk0_mul : integer := 1;
clk0_div : integer := 1;
clk1_mul : integer := 1;
clk1_div : integer := 1;
clk_freq : integer := 25000);
port (
inclk0 : in std_ulogic;
clk0 : out std_ulogic;
clk0x3 : out std_ulogic;
clksel : in std_logic_vector(1 downto 0);
locked : out std_ulogic);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+
CFG_SVGA_ENABLE+CFG_GRETH;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi, smemi : memory_in_type;
signal memo, smemo : memory_out_type;
signal wpo : wprot_out_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rawrstn, ssram_clkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal ps2i : ps2_in_type;
signal ps2o : ps2_out_type;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal lcdo : apbvga_out_type;
signal lcd_data : std_logic_vector(7 downto 0);
signal lcd_den : std_ulogic;
signal lcd_grest : std_ulogic;
signal lcdspii : spi_in_type;
signal lcdspio : spi_out_type;
signal lcdslvsel : std_logic_vector(1 downto 0);
signal lcdclksel : std_logic_vector(1 downto 0);
signal lcdclk : std_ulogic;
signal lcdclk3x : std_ulogic;
signal lcdclklck : std_ulogic;
signal vgao : apbvga_out_type;
signal vga_data : std_logic_vector(9 downto 0);
signal vgaclksel : std_logic_vector(1 downto 0);
signal vgaclk : std_ulogic;
signal vgaclk3x : std_ulogic;
signal vgaclklck : std_ulogic;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
signal lclk, lclkout : std_ulogic;
signal dsubre : std_ulogic;
attribute syn_keep : boolean;
attribute syn_keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of lcdclk : signal is true;
attribute syn_keep of lcdclk3x : signal is true;
attribute syn_keep of vgaclk : signal is true;
attribute syn_keep of vgaclk3x : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock and lcdclklck and vgaclklck;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => 1,
freq => freq)
port map (clkin => lclk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => ssram_clkl, pciclk => open,
cgi => cgi, cgo => cgo);
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (ssram_clk, ssram_clkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn, rawrstn);
rstoutn <= resetn;
----------------------------------------------------------------------
--- AVOID BUS CONTENTION --------------------------------------------
----------------------------------------------------------------------
-- This design uses the ethernet PHY and we must therefore disable the
-- video decoder and stay away from the touch panel.
-- Video coder
hc_td_reset <= '0'; -- Video Decoder Reset
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (hc_uart_rxd, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (hc_uart_txd, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 :mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
ramaddr => 16#400#+16#600#*CFG_DDRSP, rammask =>16#F00#, srbanks => 1,
sden => 0, ram16 => 1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
ssr0 : if CFG_SSCTRL = 1 generate
ssrctrl0 : ssrctrl generic map (hindex => 0, pindex => 0,
iomask => 0, ramaddr => 16#400#+16#600#*CFG_DDRSP,
bus16 => CFG_SSCTRLP16)
port map (rstn, clkm, ahbsi, ahbso(0), apbi, apbo(0), memi, memo);
end generate;
mg0 : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) = 0 generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech) port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) /= 0 generate -- prom/sram pads
addr_pad : outpadv generic map (width => 25, tech => padtech)
port map (address, memo.address(25 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
-- ssram_adv_n_pad : outpad generic map (tech => padtech)
-- port map (ssram_adv_n, vcc(0));
-- ssram_adsp_n_pad : outpad generic map (tech => padtech)
-- port map (ssram_adsp_n, gnd(0));
ssram_adscn_pad : outpad generic map (tech => padtech)
port map (ssram_adscn, gnd(0));
ssrams_pad : outpad generic map ( tech => padtech)
port map (ssram_cen, memo.ramsn(0));
ssram_oen_pad : outpad generic map (tech => padtech)
port map (ssram_oen, memo.oen);
ssram_rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (ssram_bw, memo.wrn);
ssram_wri_pad : outpad generic map (tech => padtech)
port map (ssram_wen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 32)
port map (data(31 downto 0), memo.data(31 downto 0),
memo.vbdrive, memi.data(31 downto 0));
end generate;
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 3, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, rskew => CFG_DDRSP_RSKEW,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 16, regoutput => 1)
port map (
resetn, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(3),
ddr_clkv, ddr_clkbv, open, gnd(0),
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkn <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
ddrsp1 : if (CFG_DDRSP = 0) generate
ddr_cke <= '0'; ddr_csb <= '1'; lock <= '1';
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
upads : if CFG_AHB_UART = 0 generate
u1i.rxd <= hc_uart_rxd; hc_uart_txd <= u1o.txd;
end generate;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- Timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-3 generate
gpioi.din(i) <= gpio(i);
end generate;
gpioi.din(3) <= hc_adc_penirq_n;
gpioi.din(4) <= hc_adc_busy;
end generate;
ps2 : if CFG_PS2_ENABLE /= 0 generate -- PS/2 unit
ps20 : apbps2 generic map(pindex => 6, paddr => 6, pirq => 6)
port map(rstn, clkm, apbi, apbo(6), ps2i, ps2o);
end generate;
nops2 : if CFG_PS2_ENABLE = 0 generate
apbo(4) <= apb_none; ps2o <= ps2o_none;
end generate;
ps2clk_pad : iopad generic map (tech => padtech)
port map (hc_ps2_clk, ps2o.ps2_clk_o, ps2o.ps2_clk_oe, ps2i.ps2_clk_i);
ps2data_pad : iopad generic map (tech => padtech)
port map (hc_ps2_dat, ps2o.ps2_data_o, ps2o.ps2_data_oe, ps2i.ps2_data_i);
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 8, paddr => 8, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(8), i2ci, i2co);
-- The EEK does not use a bi-directional line for the I2C clock
i2ci.scl <= i2co.scloen; -- No clock stretch possible
-- When SCL output enable is activated the line should go low
i2c_scl_pad : outpad generic map (tech => padtech)
port map (hc_id_i2cscl, i2co.scloen);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (hc_id_i2cdat, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 9, paddr => 9, pmask => 16#fff#, pirq => 7,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 1,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(9), spii, spio, slvsel);
miso_pad : iopad generic map (tech => padtech)
port map (hc_sd_dat, spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (hc_sd_cmd, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (hc_sd_clk, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (hc_sd_dat3, slvsel(0));
spii.spisel <= '1'; -- Master only
end generate spic;
-----------------------------------------------------------------------
-- LCD touch panel ---------------------------------------------------
-----------------------------------------------------------------------
lcd: if CFG_LCD_ENABLE /= 0 generate -- LCD
lcd0 : svgactrl generic map(memtech => memtech, pindex => 11, paddr => 11,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 30120, clk1 => 0, clk2 => 0, clk3 => 0, burstlen => 4)
port map(rstn, clkm, lcdclk, apbi, apbo(11), lcdo, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
lcdser0: serializer generic map (length => 8)
port map (lcdclk3x, lcdo.hsync, lcdo.video_out_b, lcdo.video_out_g,
lcdo.video_out_r, lcd_data);
lcdclksel <= "00";
lcdclkgen : altera_eek_clkgen
generic map (clk0_mul => 166, clk0_div => 250, clk1_mul => 9,
clk1_div => 50, clk_freq => BOARD_FREQ)
port map (lclk, lcdclk, lcdclk3x, lcdclksel, lcdclklck);
lcd_vert_sync_pad : outpad generic map (tech => padtech)
port map (hc_vd, lcdo.vsync);
lcd_horiz_sync_pad : outpad generic map (tech => padtech)
port map (hc_hd, lcdo.hsync);
lcd_video_out_pad : outpadv generic map (width => 8, tech => padtech)
port map (hc_lcd_data, lcd_data);
lcd_video_clock_pad : outpad generic map (tech => padtech)
port map (hc_nclk, lcdclk3x);
lcd_den <= lcdo.blank;
end generate;
nolcd : if CFG_LCD_ENABLE = 0 generate
apbo(11) <= apb_none; lcdo <= vgao_none;
lcd_den <= '0'; -- LCD RGB Data Enable
lcdclk <= '0'; lcdclk3x <= '0'; lcdclklck <= '1';
end generate;
lcd_den_pad : outpad generic map (tech => padtech)
port map (hc_den, lcd_den);
lcdsysreset: if CFG_LCD_ENABLE /= 0 or CFG_LCD3T_ENABLE /= 0 generate
lcd_grest <= rstn;
end generate;
lcdalwaysreset: if CFG_LCD_ENABLE = 0 and CFG_LCD3T_ENABLE = 0 generate
lcd_grest <= '0';
end generate lcdalwaysreset;
lcd_reset_pad : outpad generic map (tech => padtech) -- LCD Global Reset, active low
port map (hc_grest, lcd_grest);
touch3wire: if CFG_LCD3T_ENABLE /= 0 generate -- LCD 3-wire and touch panel interface
-- TODO:
-- Interrupt and busy signals not connected
touch3spi1 : spictrl
generic map (pindex => 12, paddr => 12, pmask => 16#fff#, pirq => 12,
fdepth => 2, slvselen => 1, slvselsz => 2, odmode => 0,
syncram => 0, ft => 0)
port map (rstn, clkm, apbi, apbo(12), lcdspii, lcdspio, lcdslvsel);
adc_miso_pad : inpad generic map (tech => padtech)
port map (hc_adc_dout, lcdspii.miso);
adc_mosi_pad : outpad generic map (tech => padtech)
port map (hc_adc_din, lcdspio.mosi);
lcd_adc_dclk_pad : outpad generic map (tech => padtech)
port map (hc_adc_dclk, lcdspio.sck);
hcd_sda_pad : iopad generic map (tech => padtech)
port map (hc_sda, lcdspio.mosi, lcdspio.mosioen, lcdspii.mosi);
lcdspii.spisel <= '1'; -- Master only
end generate;
notouch3wire: if CFG_LCD3T_ENABLE = 0 generate
lcdslvsel <= (others => '1');
apbo(12) <= apb_none;
end generate;
hc_adc_cs_n_pad : outpad generic map (tech => padtech)
port map (hc_adc_cs_n, lcdslvsel(0));
hc_scen_pad : outpad generic map (tech => padtech)
port map (hc_scen, lcdslvsel(1));
-----------------------------------------------------------------------
-- SVGA controller ----------------------------------------------------
-----------------------------------------------------------------------
svga : if CFG_SVGA_ENABLE /= 0 generate -- VGA DAC
svga0 : svgactrl generic map(memtech => memtech, pindex => 13, paddr => 13,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE,
clk0 => 40000, clk1 => 25000, clk2 => 0, clk3 => 0, burstlen => 4)
port map(rstn, clkm, vgaclk, apbi, apbo(13), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE),
vgaclksel);
svgaser0: serializer generic map (length => 8)
port map (vgaclk3x, vgao.hsync, vgao.video_out_b, vgao.video_out_g,
vgao.video_out_r, vga_data(9 downto 2));
vga_data(1 downto 0) <= (others => '0');
vgaclkgen : altera_eek_clkgen
generic map (clk0_mul => 1, clk0_div => 2, clk1_mul => 4,
clk1_div => 5, clk_freq => BOARD_FREQ)
port map (lclk, vgaclk, vgaclk3x, vgaclksel, vgaclklck);
vga_blank_pad : outpad generic map (tech => padtech)
port map (hc_vga_blank, vgao.blank);
vga_comp_sync_pad : outpad generic map (tech => padtech)
port map (hc_vga_sync, vgao.comp_sync);
vga_vert_sync_pad : outpad generic map (tech => padtech)
port map (hc_vga_vs, vgao.vsync);
vga_horiz_sync_pad : outpad generic map (tech => padtech)
port map (hc_vga_hs, vgao.hsync);
vga_video_out_pad : outpadv generic map (width => 10, tech => padtech)
port map (hc_vga_data, vga_data);
vga_video_clock_pad : outpad generic map (tech => padtech)
port map (hc_vga_clock, vgaclk3x);
end generate svga;
nosvga : if CFG_SVGA_ENABLE = 0 generate
apbo(13) <= apb_none; vgao <= vgao_none;
vgaclk <= '0'; vgaclk3x <= '0'; vgaclklck <= '1';
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH /= 0 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE,
pindex => 10, paddr => 10, pirq => 10, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(10), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (hc_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (hc_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (hc_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (hc_rx_d, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (hc_rx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (hc_rx_err, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (hc_rx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (hc_rx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (hc_tx_d, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (hc_tx_en, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (hc_mdc, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (hc_eth_reset_n, rawrstn);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE+CFG_GRETH) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera Embedded Evaluation Kit Demonstration Design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
45180590118dcff8992b7950b639a993
| 0.549924 | 3.588094 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/misc/ahbstat.vhd
| 1 | 4,355 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use gaisler.misc.all;
entity ahbstat is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
stati : in ahbstat_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end entity;
architecture rtl of ahbstat is
type reg_type is record
addr : std_logic_vector(31 downto 0); --failing address
hsize : std_logic_vector(2 downto 0); --ahb signals for failing op.
hmaster : std_logic_vector(3 downto 0);
hwrite : std_ulogic;
hresp : std_logic_vector(1 downto 0);
newerr : std_ulogic; --new error detected
cerror : std_ulogic; --correctable error detected
pirq : std_ulogic;
end record;
signal r, rin : reg_type;
constant VERSION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_AHBSTAT, 0, VERSION, pirq),
1 => apb_iobar(paddr, pmask));
begin
comb : process(rst, ahbmi, ahbsi, stati, apbi, r) is
variable v : reg_type;
variable prdata : std_logic_vector(31 downto 0);
variable vpirq : std_logic_vector(NAHBIRQ - 1 downto 0);
variable ce : std_ulogic; --correctable error
begin
v := r; vpirq := (others => '0'); prdata := (others => '0'); v.pirq := '0';
ce := orv(stati.cerror(0 to nftslv-1));
case apbi.paddr(2) is
when '0' => --status values
prdata(2 downto 0) := r.hsize;
prdata(6 downto 3) := r.hmaster;
prdata(7) := r.hwrite;
prdata(8) := r.newerr;
prdata(9) := r.cerror;
when others => --failing address
prdata := r.addr;
end case;
--writes. data is written in setup cycle so that r.newerr is updated
--when hready = '1'
if (apbi.psel(pindex) and not apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(2) is
when '0' =>
v.newerr := apbi.pwdata(8);
v.cerror := apbi.pwdata(9);
when others => null;
end case;
end if;
v.hresp := ahbmi.hresp;
if (ahbsi.hready = '1') and (r.newerr = '0') then
if (r.hresp = HRESP_ERROR) or (ce = '1') then v.newerr := '1';
v.cerror := ce;
else
v.addr := ahbsi.haddr;
v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hwrite := ahbsi.hwrite;
end if;
end if;
--irq generation
v.pirq := v.newerr and not r.newerr;
vpirq(pirq) := r.pirq;
--reset
if rst = '0' then
v.newerr := '0'; v.cerror := '0';
end if;
rin <= v;
apbo.prdata <= prdata;
apbo.pirq <= vpirq;
end process;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("ahbstat" & tost(pindex) &
": AHB status unit rev " & tost(VERSION) &
", irq " & tost(pirq));
-- pragma translate_on
end architecture;
|
gpl-2.0
|
8576a113c9f22426a77862b4389147ef
| 0.599541 | 3.523463 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/stratixii/stratixii_ddr_phy.vhd
| 1 | 39,134 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: stratixii_ddr_phy
-- File: stratixii_ddr_phy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Altera FPGAs
------------------------------------------------------------------------------
LIBRARY stratixii;
USE stratixii.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_stxii IS
generic (width : integer := 2; MHz : integer := 100);
PORT
(
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC := '0';
oe : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1');
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0)
);
END altdqs_stxii;
ARCHITECTURE RTL OF altdqs_stxii IS
COMPONENT stratixii_dll
GENERIC
(
DELAY_BUFFER_MODE : STRING := "none";
DELAY_CHAIN_LENGTH : NATURAL := 12;
DELAYCTRLOUT_MODE : STRING := "normal";
INPUT_FREQUENCY : STRING;
JITTER_REDUCTION : STRING := "false";
OFFSETCTRLOUT_MODE : STRING := "static";
SIM_LOOP_DELAY_INCREMENT : NATURAL := 0;
SIM_LOOP_INTRINSIC_DELAY : NATURAL := 0;
SIM_VALID_LOCK : NATURAL := 5;
SIM_VALID_LOCKCOUNT : NATURAL := 0;
STATIC_DELAY_CTRL : NATURAL := 0;
STATIC_OFFSET : STRING;
USE_UPNDNIN : STRING := "false";
USE_UPNDNINCLKENA : STRING := "false";
lpm_type : STRING := "stratixii_dll"
);
PORT
(
addnsub : IN STD_LOGIC := '1';
aload : IN STD_LOGIC := '0';
clk : IN STD_LOGIC;
delayctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
dqsupdate : OUT STD_LOGIC;
offset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
offsetctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
upndnin : IN STD_LOGIC := '0';
upndninclkena : IN STD_LOGIC := '1';
upndnout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixii_io
GENERIC
(
BUS_HOLD : STRING := "false";
DDIO_MODE : STRING := "none";
DDIOINCLK_INPUT : STRING := "negated_inclk";
DQS_CTRL_LATCHES_ENABLE : STRING := "false";
DQS_DELAY_BUFFER_MODE : STRING := "none";
DQS_EDGE_DETECT_ENABLE : STRING := "false";
DQS_INPUT_FREQUENCY : STRING := "unused";
DQS_OFFSETCTRL_ENABLE : STRING := "false";
DQS_OUT_MODE : STRING := "none";
DQS_PHASE_SHIFT : NATURAL := 0;
EXTEND_OE_DISABLE : STRING := "false";
GATED_DQS : STRING := "false";
INCLK_INPUT : STRING := "normal";
INPUT_ASYNC_RESET : STRING := "none";
INPUT_POWER_UP : STRING := "low";
INPUT_REGISTER_MODE : STRING := "none";
INPUT_SYNC_RESET : STRING := "none";
OE_ASYNC_RESET : STRING := "none";
OE_POWER_UP : STRING := "low";
OE_REGISTER_MODE : STRING := "none";
OE_SYNC_RESET : STRING := "none";
OPEN_DRAIN_OUTPUT : STRING := "false";
OPERATION_MODE : STRING;
OUTPUT_ASYNC_RESET : STRING := "none";
OUTPUT_POWER_UP : STRING := "low";
OUTPUT_REGISTER_MODE : STRING := "none";
OUTPUT_SYNC_RESET : STRING := "none";
SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
lpm_type : STRING := "stratixii_io"
);
PORT
(
areset : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
datain : IN STD_LOGIC := '0';
ddiodatain : IN STD_LOGIC := '0';
ddioinclk : IN STD_LOGIC := '0';
ddioregout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
dqsbusout : OUT STD_LOGIC;
dqsupdateen : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC := '0';
inclkena : IN STD_LOGIC := '1';
linkin : IN STD_LOGIC := '0';
linkout : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
outclk : IN STD_LOGIC := '0';
outclkena : IN STD_LOGIC := '1';
padio : INOUT STD_LOGIC;
regout : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0';
terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
SIGNAL dqs_busout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL dqsbusout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL delay_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
TYPE periodtype IS ARRAY(10 TO 20) of STRING(1 TO 6);
CONSTANT period : periodtype := (
"9999ps", "9090ps", "8333ps", "7692ps", -- 100-130 MHz
"7143ps", "6667ps", "6250ps", "5882ps", -- 140-170 MHz
"5556ps", "5263ps", "5000ps"); -- 180-200 MHz
FUNCTION buffer_mode(MHz : INTEGER) RETURN STRING IS
BEGIN
IF MHz > 175 THEN RETURN "high"; ELSE RETURN "low"; END IF;
END buffer_mode;
FUNCTION out_mode(MHz : INTEGER) RETURN STRING IS
BEGIN
IF MHz > 175 THEN RETURN "delay_chain4";
ELSE RETURN "delay_chain3"; END IF;
END out_mode;
FUNCTION chain_length(MHz : INTEGER) RETURN INTEGER IS
BEGIN
IF MHz > 175 THEN RETURN 16; ELSE RETURN 12; END IF;
END chain_length;
component global
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component stratixii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixii_clkctrl"
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
end component;
subtype v4 is std_logic_vector(3 downto 0);
type vv4 is array (width-1 downto 0) of v4;
signal dqslocal : vv4;
signal gnd : std_logic;
BEGIN
gnd <= '0';
dqinclk <= not dqs_busout;
stxii_dll1 : stratixii_dll
GENERIC MAP (
DELAY_BUFFER_MODE => buffer_mode(MHz),
DELAY_CHAIN_LENGTH => chain_length(MHz),
INPUT_FREQUENCY => period(MHz/10),
OFFSETCTRLOUT_MODE => "static",
DELAYCTRLOUT_MODE => "normal",
JITTER_REDUCTION => "false",
SIM_LOOP_DELAY_INCREMENT => 132,
SIM_LOOP_INTRINSIC_DELAY => 3840,
SIM_VALID_LOCK => 1,
SIM_VALID_LOCKCOUNT => 46,
STATIC_OFFSET => "0",
USE_UPNDNIN => "false",
USE_UPNDNINCLKENA => "false"
)
PORT MAP (
clk => inclk,
delayctrlout => delay_ctrl
);
loop0 : FOR i IN 0 TO width-1 GENERATE
stxii_io2a : stratixii_io
GENERIC MAP (
DDIO_MODE => "output",
DQS_CTRL_LATCHES_ENABLE => "false",
DQS_DELAY_BUFFER_MODE => buffer_mode(MHz),
DQS_EDGE_DETECT_ENABLE => "false",
DQS_INPUT_FREQUENCY => period(MHz/10),
DQS_OFFSETCTRL_ENABLE => "false",
DQS_OUT_MODE => out_mode(MHz),
DQS_PHASE_SHIFT => 9000,
EXTEND_OE_DISABLE => "true",
GATED_DQS => "false",
OE_ASYNC_RESET => "none",
OE_POWER_UP => "low",
OE_REGISTER_MODE => "register",
OE_SYNC_RESET => "none",
OPEN_DRAIN_OUTPUT => "false",
OPERATION_MODE => "bidir",
OUTPUT_ASYNC_RESET => "none",
OUTPUT_POWER_UP => "low",
OUTPUT_REGISTER_MODE => "register",
OUTPUT_SYNC_RESET => "none",
SIM_DQS_DELAY_INCREMENT => 36,
SIM_DQS_INTRINSIC_DELAY => 900,
SIM_DQS_OFFSET_INCREMENT => 0,
TIE_OFF_OE_CLOCK_ENABLE => "false",
TIE_OFF_OUTPUT_CLOCK_ENABLE => "false"
)
PORT MAP (
datain => dqs_datain_h(i),
ddiodatain => dqs_datain_l(i),
delayctrlin => delay_ctrl,
dqsbusout => dqs_busout(i),
oe => oe(i),
outclk => outclk(i),
padio => dqs_padio(i)
);
-- clkbuf : global
-- port map (a_in => dqsbusout(i), a_out => dqs_busout(i));
-- dqslocal(i) <= "000" & dqsbusout(i);
-- clkbuf : stratixii_clkctrl generic map (clock_type => "global clock")
-- port map (inclk => dqslocal(i), outclk => dqs_busout(i));
END GENERATE loop0;
END RTL; --altdqs_stxii
LIBRARY stratixii;
USE stratixii.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdq_stxii IS
generic (width : integer := 8);
PORT
(
datain_h : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
dataout_h : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
dataout_l : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
inclock : IN STD_LOGIC;
oe : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC;
padio : INOUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END altdq_stxii;
ARCHITECTURE RTL OF altdq_stxii IS
COMPONENT stratixii_io
GENERIC
(
BUS_HOLD : STRING := "false";
DDIO_MODE : STRING := "none";
DDIOINCLK_INPUT : STRING := "negated_inclk";
DQS_CTRL_LATCHES_ENABLE : STRING := "false";
DQS_DELAY_BUFFER_MODE : STRING := "none";
DQS_EDGE_DETECT_ENABLE : STRING := "false";
DQS_INPUT_FREQUENCY : STRING := "unused";
DQS_OFFSETCTRL_ENABLE : STRING := "false";
DQS_OUT_MODE : STRING := "none";
DQS_PHASE_SHIFT : NATURAL := 0;
EXTEND_OE_DISABLE : STRING := "false";
GATED_DQS : STRING := "false";
INCLK_INPUT : STRING := "normal";
INPUT_ASYNC_RESET : STRING := "none";
INPUT_POWER_UP : STRING := "low";
INPUT_REGISTER_MODE : STRING := "none";
INPUT_SYNC_RESET : STRING := "none";
OE_ASYNC_RESET : STRING := "none";
OE_POWER_UP : STRING := "low";
OE_REGISTER_MODE : STRING := "none";
OE_SYNC_RESET : STRING := "none";
OPEN_DRAIN_OUTPUT : STRING := "false";
OPERATION_MODE : STRING;
OUTPUT_ASYNC_RESET : STRING := "none";
OUTPUT_POWER_UP : STRING := "low";
OUTPUT_REGISTER_MODE : STRING := "none";
OUTPUT_SYNC_RESET : STRING := "none";
SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
lpm_type : STRING := "stratixii_io"
);
PORT
(
areset : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
datain : IN STD_LOGIC := '0';
ddiodatain : IN STD_LOGIC := '0';
ddioinclk : IN STD_LOGIC := '0';
ddioregout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
dqsbusout : OUT STD_LOGIC;
dqsupdateen : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC := '0';
inclkena : IN STD_LOGIC := '1';
linkin : IN STD_LOGIC := '0';
linkout : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
outclk : IN STD_LOGIC := '0';
outclkena : IN STD_LOGIC := '1';
padio : INOUT STD_LOGIC;
regout : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0';
terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
loop0 : FOR i IN 0 TO width-1 GENERATE
dq_ioa : stratixii_io
GENERIC MAP (
DDIO_MODE => "bidir",
DDIOINCLK_INPUT => "negated_inclk",
EXTEND_OE_DISABLE => "false",
-- INCLK_INPUT => "dqs_bus",
INPUT_ASYNC_RESET => "none",
INPUT_POWER_UP => "low",
INPUT_REGISTER_MODE => "register",
OE_ASYNC_RESET => "none",
OE_POWER_UP => "low",
OE_REGISTER_MODE => "register",
OPERATION_MODE => "bidir",
OUTPUT_ASYNC_RESET => "none",
OUTPUT_POWER_UP => "low",
OUTPUT_REGISTER_MODE => "register"
)
PORT MAP (
datain => datain_h(i),
ddiodatain => datain_l(i),
ddioregout => dataout_l(i),
inclk => inclock,
oe => oe,
outclk => outclock,
padio => padio(i),
regout => dataout_h(i)
);
END GENERATE loop0;
END RTL; --altdq_stxii
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera;
library altera_mf;
--pragma translate_off
use altera_mf.altpll;
use altera_mf.altddio_out;
use altera_mf.altddio_bidir;
--pragma translate_on
------------------------------------------------------------------
-- STRATIX2 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity stratixii_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of stratixii_ddr_phy is
signal vcc, gnd, oe, lockl : std_logic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal clk4, clk5 : std_logic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal gndv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal pclkout : std_logic_vector (5 downto 1);
signal ddr_clkin : std_logic_vector(0 to 2);
signal dqinclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsnv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
component stratixii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixii_clkctrl"
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
end component;
component altddio_out
generic (
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_out" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout : out std_logic_vector(width-1 downto 0));
end component;
component altddio_bidir
generic(
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
implement_input_in_lcell : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_bidir" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
inclock : in std_logic := '0';
inclocken : in std_logic := '1';
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout_h : out std_logic_vector(width-1 downto 0);
dataout_l : out std_logic_vector(width-1 downto 0);
padio : inout std_logic_vector(width-1 downto 0) );
end component;
component altdqs_stxii
generic (width : integer := 2; MHz : integer := 100);
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END component;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 13) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769")); -- 120 & 130 MHz
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
inclk0_input_frequency : positive;
inclk1_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1;
clk3_multiply_by : positive := 1;
clk3_divide_by : positive := 1;
clk4_multiply_by : positive := 1;
clk4_divide_by : positive := 1;
clk3_phase_shift : string := "0";
clk2_phase_shift : string := "0";
clk1_phase_shift : string := "0";
clk0_phase_shift : string := "0"
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
begin
oe <= not oen; vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
mclk <= clk;
-- clkout <= clk_270r;
-- clkout <= clk_0r when DDR_FREQ >= 110 else clk_270r;
clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : altpll
generic map (
intended_device_family => "Stratix II",
operation_mode => "NORMAL",
inclk0_input_frequency => 1000000/MHz,
inclk1_input_frequency => 1000000/MHz,
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
)
port map ( inclk(0) => mclk, inclk(1) => gnd, clk(0) => clk_0r,
clk(1) => clk_90r, clk(2) => clk_180r, clk(3) => clk_270r,
clk(4) => clk4, clk(5) => clk5, locked => lockl);
rstdel : process (mclk, rst)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r, lockl)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
-- fbclkpad : altddio_out generic map (width => 1)
-- port map ( datain_h(0) => vcc, datain_l(0) => gnd,
-- outclock => clk90r, dataout(0) => ddr_clk_fb_out);
ddrclocks : for i in 0 to 2 generate
clkpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => vcc, datain_l(0) => gnd, oe => vcc,
outclock => clk90r, dataout(0) => ddr_clk(i));
clknpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => gnd, datain_l(0) => vcc, oe => vcc,
outclock => clk90r, dataout(0) => ddr_clkb(i));
end generate;
csnpads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => csn, datain_l => csn, oe => vcc,
outclock => clk0r, dataout => ddr_csb);
ckepads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => ckel, datain_l => ckel, oe => vcc,
outclock => clk0r, dataout => ddr_cke);
ddrbanks : for i in 0 to 1 generate
ckel(i) <= cke(i) and locked;
end generate;
rasnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => rasn, datain_l(0) => rasn, oe => vcc,
outclock => clk0r, dataout(0) => ddr_rasb);
casnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => casn, datain_l(0) => casn, oe => vcc,
outclock => clk0r, dataout(0) => ddr_casb);
wenpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => wen, datain_l(0) => wen, oe => vcc,
outclock => clk0r, dataout(0) => ddr_web);
dmpads : altddio_out generic map (width => dbits/8,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => dm(dbits/8*2-1 downto dbits/8),
datain_l => dm(dbits/8-1 downto 0), oe => vcc,
outclock => clk0r, dataout => ddr_dm
);
bapads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => ba, datain_l => ba, oe => vcc,
outclock => clk0r, dataout => ddr_ba
);
addrpads : altddio_out generic map (width => 14,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => addr, datain_l => addr, oe => vcc,
outclock => clk0r, dataout => ddr_ad
);
-- DQS generation
dqsoclk <= (others => clk90r);
altdqs : altdqs_stxii generic map (dbits/8, DDR_FREQ)
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv,
inclk => clk270r, oe => ddr_dqsoen, outclk => dqsoclk,
dqinclk => dqinclk, dqs_padio => ddr_dqs);
-- Data bus
dqgen : for i in 0 to dbits/8-1 generate
qi : altddio_bidir generic map (width => 8, oe_reg =>"REGISTERED",
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_l => dqout(i*8+7 downto i*8),
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
inclock => dqinclk(i), --clk270r,
outclock => clk0r, oe => oe,
dataout_h => dqin(i*8+7 downto i*8),
dataout_l => dqin(i*8+7+dbits downto dbits+i*8), --dqinl(i*8+7 downto i*8),
padio => ddr_dq(i*8+7 downto i*8));
end generate;
dqsreg : process(clk180r)
begin
if rising_edge(clk180r) then
dqsnv <= (others => oe);
end if;
end process;
oereg : process(clk0r)
begin
if rising_edge(clk0r) then
ddr_dqsoen(dbits/8-1 downto 0) <= (others => not dqsoen);
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
--library stratixii;
use altera_mf.altera_mf_components.all;
--use stratixii.stratixii_pll;
------------------------------------------------------------------
-- STRATIX2 DDR2 PHY -----------------------------------------------
------------------------------------------------------------------
entity stratixii_ddr2_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; eightbanks : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 2 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of stratixii_ddr2_phy is
signal vcc, gnd : std_logic;
signal ckel, odtl : std_logic_vector(1 downto 0);
signal clk_0r, clk_90r, clk_120r, clk_180r, clk_270r : std_ulogic;
signal locked, lockl, vlockl : std_ulogic;
signal clk5 : std_ulogic;
signal dllrst : std_logic_vector(0 to 3);
signal gndv : std_logic_vector (dbits/8-1 downto 0);
signal dqsnv : std_logic_vector (dbits/8-1 downto 0);
signal dqsoe : std_logic_vector (dbits/8-1 downto 0);
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0);
signal dqinclk : std_logic_vector (dbits/8-1 downto 0);
signal dqinl : std_logic_vector (dbits*2-1 downto 0);
signal dqoe : std_logic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
component altdqs_stxii
generic (width : integer := 2; Mhz : integer := 100);
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END component;
component altdq_stxii
generic (width : integer := 8);
PORT
(
datain_h : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
dataout_h : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
dataout_l : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
inclock : IN STD_LOGIC;
oe : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC;
padio : INOUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END component;
type phasevec is array (1 to 4) of string(1 to 4);
type phasevecarr is array (13 to 20) of phasevec;
constant phasearr : phasevecarr := (
("1923", "2564", "3846", "5769"), -- 130 MHz
("1786", "2381", "3571", "5357"), -- 140 MHz
("1667", "2222", "3333", "5000"), -- 150 MHz
("1562", "2083", "3125", "4687"), -- 160 MHz
("1471", "1961", "2941", "4412"), -- 160 MHz
("1389", "1852", "2778", "4167"), -- 180 MHz
("1316", "1754", "2632", "3947"), -- 190 MHz
("1250", "1667", "2500", "3750")); -- 200 MHz
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
inclk0_input_frequency : positive;
inclk1_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1;
clk3_multiply_by : positive := 1;
clk3_divide_by : positive := 1;
clk4_multiply_by : positive := 1;
clk4_divide_by : positive := 1;
clk4_phase_shift : string := "0";
clk3_phase_shift : string := "0";
clk2_phase_shift : string := "0";
clk1_phase_shift : string := "0";
clk0_phase_shift : string := "0"
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
component altddio_out
generic (
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_out" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout : out std_logic_vector(width-1 downto 0));
end component;
begin
clkout <= clk_0r;
vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
dll : altpll
generic map (
intended_device_family => "Stratix II",
operation_mode => "NORMAL",
inclk0_input_frequency => 1000000/MHz,
inclk1_input_frequency => 1000000/MHz,
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk4_phase_shift => phasearr(DDR_FREQ/10)(4),
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
)
port map ( inclk(0) => clk, inclk(1) => gnd, clk(0) => clk_0r,
clk(1) => clk_90r, clk(2) => clk_120r, clk(3) => clk_180r,
clk(4) => clk_270r, clk(5) => clk5, locked => lockl);
rstdel : process (clk, rst)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(clk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_180r, lockl)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_180r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
ddrbanks : for i in 0 to 1 generate
ckel(i) <= cke(i) and locked;
odtl(i) <= odt(i) and locked;
end generate;
dqsreg : process (clk_180r)
begin
if rising_edge(clk_180r) then
dqsoe <= (others => not dqsoen);
dqsnv <= (others => not oen);
end if;
end process;
dqinreg : process (clk_120r)
begin
if rising_edge(clk_120r) then
dqin <= dqinl;
end if;
end process;
ddrclocks : for i in 0 to 2 generate
clkpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => vcc, datain_l(0) => gnd, oe => vcc,
outclock => clk_0r, dataout(0) => ddr_clk(i));
clknpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => gnd, datain_l(0) => vcc, oe => vcc,
outclock => clk_0r, dataout(0) => ddr_clkb(i));
end generate;
-- Control signal pads
ckepads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => ckel, datain_l => ckel, oe => vcc,
outclock => clk_180r, dataout => ddr_cke);
csnpads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => csn, datain_l => csn, oe => vcc,
outclock => clk_180r, dataout => ddr_csb);
odtpads : altddio_out generic map (width => 2,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h => odtl, datain_l => odtl, oe => vcc,
outclock => clk_180r, dataout => ddr_odt);
rasnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => rasn, datain_l(0) => rasn, oe => vcc,
outclock => clk_180r, dataout(0) => ddr_rasb);
casnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => casn, datain_l(0) => casn, oe => vcc,
outclock => clk_180r, dataout(0) => ddr_casb);
wenpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map ( datain_h(0) => wen, datain_l(0) => wen, oe => vcc,
outclock => clk_180r, dataout(0) => ddr_web);
bapads : altddio_out generic map (width => 2+eightbanks,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => ba(1+eightbanks downto 0),
datain_l => ba(1+eightbanks downto 0),
oe => vcc,
outclock => clk_180r, dataout => ddr_ba
);
addrpads : altddio_out generic map (width => 14,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => addr, datain_l => addr, oe => vcc,
outclock => clk_180r, dataout => ddr_ad
);
-- DQS generation
dqsoclk <= (others => clk_0r);
altdqs : altdqs_stxii generic map (dbits/8, DDR_FREQ)
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv,
inclk => clk_0r, oe => dqsoe, outclk => dqsoclk,
dqinclk => dqinclk, dqs_padio => ddr_dqs);
-- Data bus
dqoe <= not oen;
dqgen : for i in 0 to dbits/8-1 generate
altdq : altdq_stxii generic map (width => 8)
port map (
datain_l => dqout(i*8+7 downto i*8),
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
inclock => dqinclk(i),
outclock => clk_270r, oe => dqoe,
dataout_h => dqinl(i*8+7 downto i*8),
dataout_l => dqinl(i*8+7+dbits downto dbits+i*8),
padio => ddr_dq(i*8+7 downto i*8));
end generate;
-- Data mask
dmpads : altddio_out generic map (width => dbits/8,
INTENDED_DEVICE_FAMILY => "STRATIXII")
port map (
datain_h => dm(dbits/4-1 downto dbits/8),
datain_l => dm(dbits/8-1 downto 0), oe => vcc,
outclock => clk_270r, dataout => ddr_dm
);
end;
|
gpl-2.0
|
540c8be15318506519528dd978eeb713
| 0.58062 | 3.128718 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-sp605/vga_clkgen.vhd
| 3 | 2,020 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
entity vga_clkgen is
port (
resetn : in std_logic;
sel : in std_logic_vector(1 downto 0);
clk25 : in std_logic;
clkm : in std_logic;
clk50 : in std_logic;
clkout : out std_logic
);
end;
architecture struct of vga_clkgen is
component BUFG port ( O : out std_logic; I : in std_logic); end component;
signal clk65, clksel : std_logic;
begin
-- 65 MHz clock generator
clkgen65 : clkmul_virtex2 generic map (13, 5) port map (resetn, clk25, clk65);
clk_select : process (clk25, clk50, clk65, sel)
begin
case sel is
when "00" => clksel <= clk25;
when "01" => clksel <= clkm;
when "10" => clksel <= clk50;
when "11" => clksel <= clk65;
when others => clksel <= '0';
end case;
end process;
bufg1 : BUFG port map (I => clksel, O => clkout);
end;
|
gpl-2.0
|
24a9bfc9888edad07b6c3c473cd78b92
| 0.652475 | 3.672727 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-terasic-sockit/ddr3sim.vhd
| 1 | 11,124 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity ddr3controller_0002 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_a : out std_logic_vector(14 downto 0); -- mem_a
mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n
mem_reset_n : out std_logic; -- mem_reset_n
mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
avl_ready : out std_logic; -- waitrequest_n
avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer
avl_addr : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
avl_rdata_valid : out std_logic; -- readdatavalid
avl_rdata : out std_logic_vector(127 downto 0); -- readdata
avl_wdata : in std_logic_vector(127 downto 0) := (others => 'X'); -- writedata
avl_be : in std_logic_vector(15 downto 0) := (others => 'X'); -- byteenable
avl_read_req : in std_logic := 'X'; -- read
avl_write_req : in std_logic := 'X'; -- write
avl_size : in std_logic_vector(3 downto 0) := (others => 'X'); -- burstcount
local_init_done : out std_logic; -- local_init_done
local_cal_success : out std_logic; -- local_cal_success
local_cal_fail : out std_logic; -- local_cal_fail
oct_rzqin : in std_logic := 'X'; -- rzqin
pll_mem_clk : out std_logic; -- pll_mem_clk
pll_write_clk : out std_logic; -- pll_write_clk
pll_locked : out std_logic; -- pll_locked
pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk
pll_avl_clk : out std_logic; -- pll_avl_clk
pll_config_clk : out std_logic; -- pll_config_clk
-- pll_dr_clk : out std_logic; -- pll_dr_clk
-- pll_dr_clk_pre_phy_clk : out std_logic; -- pll_dr_clk_pre_phy_clk
pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk
afi_phy_clk : out std_logic; -- afi_phy_clk
pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk
);
end ddr3controller_0002;
architecture sim of ddr3controller_0002 is
signal lafi_clk, lafi_rst_n: std_ulogic;
signal lafi_half_clk: std_ulogic;
begin
afi_clk <= lafi_clk;
afi_half_clk <= lafi_half_clk;
afi_reset_n <= lafi_rst_n;
mem_a <= (others => '0');
mem_ba <= (others => '0');
mem_ck <= (others => '0');
mem_ck_n <= (others => '1');
mem_cke <= (others => '0');
mem_cs_n <= (others => '1');
mem_dm <= (others => '0');
mem_ras_n <= (others => '1');
mem_cas_n <= (others => '1');
mem_we_n <= (others => '1');
mem_dq <= (others => 'Z');
mem_dqs <= (others => 'Z');
mem_dqs_n <= (others => 'Z');
mem_odt <= (others => '0');
avl_ready <= '1';
local_init_done <= '1';
local_cal_success <= '1';
local_cal_fail <= '0';
-- 200 MHz clock
clkproc: process
begin
lafi_clk <= '0';
lafi_half_clk <= '0';
loop
wait for 3.3 ns;
lafi_clk <= not lafi_clk;
if lafi_clk='0' then
lafi_half_clk <= not lafi_half_clk;
end if;
end loop;
end process;
rstproc: process
begin
lafi_rst_n <= '0';
wait for 10 ns;
loop
if global_reset_n='0' then
lafi_rst_n <= '0';
wait until global_reset_n/='0';
wait until rising_edge(lafi_clk);
end if;
lafi_rst_n <= '1';
wait until global_reset_n='0';
end loop;
end process;
avlproc: process
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**20)-1)) of BYTE;
variable MEMA: MEM;
procedure load_srec is
file TCF : text open read_mode is "ram.srec";
variable L1: line;
variable CH: character;
variable ai: integer;
variable rectype: std_logic_vector(3 downto 0);
variable recaddr: std_logic_vector(31 downto 0);
variable reclen: std_logic_vector(7 downto 0);
variable recdata: std_logic_vector(0 to 16*8-1);
variable len: integer;
begin
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
len := len-2;
when "0010" =>
hread(L1, recaddr(23 downto 0));
len := len-3;
when "0011" =>
hread(L1, recaddr);
len := len-4;
when others => next;
end case;
hread(L1, recdata(0 to 8*len-1));
recaddr(31 downto 20) := (others => '0');
ai := conv_integer(recaddr);
-- print("Setting " & tost(len) & "bytes at " & tost(recaddr));
for i in 0 to len-1 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
end if;
end if;
end if;
end loop;
end load_srec;
constant avldbits: integer := 128;
variable outqueue: std_logic_vector(0 to 4*avldbits-1) := (others => 'X');
variable outqueue_valid: std_logic_vector(0 to 3) := (others => '0');
variable ai,p: integer;
variable wbleft: integer := 0;
begin
load_srec;
loop
wait until rising_edge(lafi_clk);
avl_rdata_valid <= outqueue_valid(0);
avl_rdata <= outqueue(0 to avldbits-1);
outqueue(0 to 3*avldbits-1) := outqueue(avldbits to 4*avldbits-1);
outqueue(3*avldbits to 4*avldbits-1) := (others => 'X');
outqueue_valid := outqueue_valid(1 to 3) & '0';
if avl_burstbegin='1' then wbleft:=0; end if;
if lafi_rst_n='0' then
outqueue_valid := (others => '0');
elsif avl_read_req='1' then
ai := conv_integer(avl_addr(16 downto 0));
p := 0;
while outqueue_valid(p)='1' loop p:=p+1; end loop;
for x in 0 to conv_integer(avl_size)-1 loop
for y in 0 to avldbits/8-1 loop
outqueue((p+x)*avldbits+y*8 to (p+x)*avldbits+y*8+7) := MEMA((ai+x)*avldbits/8+y);
end loop;
outqueue_valid(p+x) := '1';
end loop;
elsif avl_write_req='1' then
if wbleft=0 then
wbleft := conv_integer(avl_size);
ai := conv_integer(avl_addr(16 downto 0));
end if;
for y in 0 to avldbits/8-1 loop
if avl_be(avldbits/8-1-y)='1' then
MEMA(ai*avldbits/8+y) := avl_wdata(avldbits-8*y-1 downto avldbits-8*y-8);
end if;
end loop;
wbleft := wbleft-1;
ai := ai+1;
end if;
end loop;
end process;
end;
|
gpl-2.0
|
c192c54a7cfd54c25cb714a1987b613d
| 0.450737 | 3.849135 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/eth/core/greth_pkg.vhd
| 1 | 24,094 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
package grethpkg is
--gigabit sync types
type data_sync_type is array (0 to 3) of std_logic_vector(31 downto 0);
type ctrl_sync_type is array (0 to 3) of std_logic_vector(1 downto 0);
constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
--receiver constants
constant maxsizerx : std_logic_vector(15 downto 0) :=
conv_std_logic_vector(1500, 16);
constant minpload : std_logic_vector(10 downto 0) :=
conv_std_logic_vector(60, 11);
type ahb_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(4 downto 0);
write : std_ulogic;
data : std_logic_vector(31 downto 0);
waddress : std_logic_vector(4 downto 0);
end record;
type ahb_fifo_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type nchar_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(5 downto 0);
write : std_ulogic;
data : std_logic_vector(8 downto 0);
waddress : std_logic_vector(5 downto 0);
end record;
type nchar_fifo_out_type is record
data : std_logic_vector(8 downto 0);
end record;
type rmapbuf_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(7 downto 0);
write : std_ulogic;
data : std_logic_vector(7 downto 0);
waddress : std_logic_vector(7 downto 0);
end record;
type rmapbuf_out_type is record
data : std_logic_vector(7 downto 0);
end record;
type ahbc_mst_in_type is record
hgrant : std_ulogic; -- bus grant
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type ahbc_mst_out_type is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_in_type is record
psel : std_ulogic; -- slave select
penable : std_ulogic; -- strobe
paddr : std_logic_vector(31 downto 0); -- address bus (byte)
pwrite : std_ulogic; -- write
pwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_out_type is record
prdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type eth_tx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_tx_ahb_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_rx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_gbit_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
type gbit_host_tx_type is record
full_duplex : std_ulogic;
start : std_ulogic;
read_ack : std_ulogic;
data : std_logic_vector(31 downto 0);
datavalid : std_ulogic;
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
rx_col : std_ulogic;
rx_crs : std_ulogic;
end record;
type gbit_tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type gbit_rx_host_type is record
sync_start : std_ulogic;
done : std_ulogic;
write : std_logic_vector(3 downto 0);
dataout : data_sync_type;
byte_count : std_logic_vector(10 downto 0);
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
mcasthash : std_logic_vector(5 downto 0);
end record;
type gbit_host_rx_type is record
full_duplex : std_ulogic;
gbit : std_ulogic;
doneack : std_ulogic;
writeack : std_logic_vector(3 downto 0);
speed : std_ulogic;
writeok : std_logic_vector(3 downto 0);
rxenable : std_ulogic;
rxd : std_logic_vector(7 downto 0);
rx_dv : std_ulogic;
rx_er : std_ulogic;
rx_col : std_ulogic;
rx_crs : std_ulogic;
rx_en : std_ulogic;
end record;
type gbit_gtx_host_type is record
txd : std_logic_vector(7 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
read : std_logic_vector(3 downto 0);
status : std_logic_vector(2 downto 0);
end record;
type gbit_host_gtx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
burstmode : std_ulogic;
txen : std_ulogic;
start_sync : std_ulogic;
readack : std_logic_vector(3 downto 0);
valid : std_logic_vector(3 downto 0);
data : data_sync_type;
len : std_logic_vector(10 downto 0);
end record;
type host_tx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
start : std_ulogic;
readack : std_ulogic;
speed : std_ulogic;
data : std_logic_vector(31 downto 0);
datavalid : std_ulogic;
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
end record;
type tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type rx_host_type is record
dataout : std_logic_vector(31 downto 0);
start : std_ulogic;
done : std_ulogic;
write : std_ulogic;
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
lentype : std_logic_vector(15 downto 0);
mcasthash : std_logic_vector(5 downto 0);
end record;
type host_rx_type is record
writeack : std_ulogic;
doneack : std_ulogic;
speed : std_ulogic;
writeok : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rx_dv : std_ulogic;
rx_crs : std_ulogic;
rx_er : std_ulogic;
enable : std_ulogic;
rx_en : std_ulogic;
end record;
component greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
maxsize : integer;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
end component;
component greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
end component;
component eth_rstgen is
generic(acthigh : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic
);
end component;
component greth_gbit_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in gbit_host_tx_type;
txo : out gbit_tx_host_type);
end component;
component greth_gbit_gtx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
iotest : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
gtxi : in gbit_host_gtx_type;
gtxo : out gbit_gtx_host_type;
iotmact : in std_ulogic;
iotdata : in std_logic_vector(9 downto 0)
);
end component;
component greth_gbit_rx is
generic(
multicast : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in gbit_host_rx_type;
rxo : out gbit_rx_host_type;
iotdata : out std_logic_vector(9 downto 0));
end component;
component eth_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component eth_ahb_mst_gbit is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_gbit_ahb_in_type;
rmsto : out eth_rx_ahb_out_type);
end component;
component eth_edcl_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type
);
end component;
function mirror(din : in std_logic_vector) return std_logic_vector;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector;
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer;
function setburstlength(fifosize : in integer) return integer;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector;
end package;
package body grethpkg is
function mirror(din : in std_logic_vector)
return std_logic_vector is
variable do : std_logic_vector(din'range);
begin
for i in 0 to din'length-1 loop
do(din'high-i) := din(i+din'low);
end loop;
return do;
end function;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--16-bit one's complement adder
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(16 downto 0);
variable vd2 : std_logic_vector(16 downto 0);
variable sum : std_logic_vector(16 downto 0);
begin
vd1 := '0' & d1; vd2 := '0' & d2;
sum := vd1 + vd2;
sum(15 downto 0) := sum(15 downto 0) + sum(16);
return sum(15 downto 0);
end function;
--16-bit one's complement adder for ip/tcp checksum detection
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(25 downto 0);
variable vd2 : std_logic_vector(25 downto 0);
variable sum : std_logic_vector(25 downto 0);
begin
vd1 := "0000000000" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic is
variable valid : std_ulogic;
begin
valid := '1';
if usesz = '1' then
if len > minpload then
if bcnt /= len then
valid := '0';
end if;
else
if bcnt /= minpload then
valid := '0';
end if;
end if;
end if;
return valid;
end function;
function setburstlength(fifosize : in integer) return integer is
begin
if fifosize <= 64 then
return fifosize/2;
else
return 32;
end if;
end function;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
function calccrc_8(data : in std_logic_vector( 7 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable d : std_logic_vector(7 downto 0);
begin
d(7) := data(0); d(6) := data(1); d(5) := data(2); d(4) := data(3);
d(3) := data(4); d(2) := data(5); d(1) := data(6); d(0) := data(7);
ncrc(0) := d(6) xor d(0) xor crc(24) xor crc(30);
ncrc(1) := d(7) xor d(6) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(30) xor crc(31);
ncrc(2) := d(7) xor d(6) xor d(2) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(26) xor crc(30) xor crc(31);
ncrc(3) := d(7) xor d(3) xor d(2) xor d(1) xor crc(25) xor crc(26) xor crc(27) xor crc(31);
ncrc(4) := d(6) xor d(4) xor d(3) xor d(2) xor d(0) xor crc(24) xor crc(26) xor crc(27) xor crc(28) xor crc(30);
ncrc(5) := d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(27) xor crc(28) xor crc(29) xor crc(30) xor crc(31);
ncrc(6) := d(7) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor crc(25) xor crc(26) xor crc(28) xor crc(29) xor crc(30) xor crc(31);
ncrc(7) := d(7) xor d(5) xor d(3) xor d(2) xor d(0) xor crc(24) xor crc(26) xor crc(27) xor crc(29) xor crc(31);
ncrc(8) := d(4) xor d(3) xor d(1) xor d(0) xor crc(0) xor crc(24) xor crc(25) xor crc(27) xor crc(28);
ncrc(9) := d(5) xor d(4) xor d(2) xor d(1) xor crc(1) xor crc(25) xor crc(26) xor crc(28) xor crc(29);
ncrc(10) := d(5) xor d(3) xor d(2) xor d(0) xor crc(2) xor crc(24) xor crc(26) xor crc(27) xor crc(29);
ncrc(11) := d(4) xor d(3) xor d(1) xor d(0) xor crc(3) xor crc(24) xor crc(25) xor crc(27) xor crc(28);
ncrc(12) := d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor d(0) xor crc(4) xor crc(24) xor crc(25) xor crc(26) xor crc(28) xor crc(29) xor crc(30);
ncrc(13) := d(7) xor d(6) xor d(5) xor d(3) xor d(2) xor d(1) xor crc(5) xor crc(25) xor crc(26) xor crc(27) xor crc(29) xor crc(30) xor crc(31);
ncrc(14) := d(7) xor d(6) xor d(4) xor d(3) xor d(2) xor crc(6) xor crc(26) xor crc(27) xor crc(28) xor crc(30) xor crc(31);
ncrc(15) := d(7) xor d(5) xor d(4) xor d(3) xor crc(7) xor crc(27) xor crc(28) xor crc(29) xor crc(31);
ncrc(16) := d(5) xor d(4) xor d(0) xor crc(8) xor crc(24) xor crc(28) xor crc(29);
ncrc(17) := d(6) xor d(5) xor d(1) xor crc(9) xor crc(25) xor crc(29) xor crc(30);
ncrc(18) := d(7) xor d(6) xor d(2) xor crc(10) xor crc(26) xor crc(30) xor crc(31);
ncrc(19) := d(7) xor d(3) xor crc(11) xor crc(27) xor crc(31);
ncrc(20) := d(4) xor crc(12) xor crc(28);
ncrc(21) := d(5) xor crc(13) xor crc(29);
ncrc(22) := d(0) xor crc(14) xor crc(24);
ncrc(23) := d(6) xor d(1) xor d(0) xor crc(15) xor crc(24) xor crc(25) xor crc(30);
ncrc(24) := d(7) xor d(2) xor d(1) xor crc(16) xor crc(25) xor crc(26) xor crc(31);
ncrc(25) := d(3) xor d(2) xor crc(17) xor crc(26) xor crc(27);
ncrc(26) := d(6) xor d(4) xor d(3) xor d(0) xor crc(18) xor crc(24) xor crc(27) xor crc(28) xor crc(30);
ncrc(27) := d(7) xor d(5) xor d(4) xor d(1) xor crc(19) xor crc(25) xor crc(28) xor crc(29) xor crc(31);
ncrc(28) := d(6) xor d(5) xor d(2) xor crc(20) xor crc(26) xor crc(29) xor crc(30);
ncrc(29) := d(7) xor d(6) xor d(3) xor crc(21) xor crc(27) xor crc(30) xor crc(31);
ncrc(30) := d(7) xor d(4) xor crc(22) xor crc(28) xor crc(31);
ncrc(31) := d(5) xor crc(23) xor crc(29);
return ncrc;
end function;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(17 downto 0);
variable vd2 : std_logic_vector(17 downto 0);
variable sum : std_logic_vector(17 downto 0);
begin
vd1 := "00" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
end package body;
|
gpl-2.0
|
95eb5c995d12cc88a3140fcfddcdf062
| 0.55188 | 3.075568 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-terasic-de4/config.vhd
| 1 | 6,827 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix4;
constant CFG_MEMTECH : integer := stratix4;
constant CFG_PADTECH : integer := stratix4;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix4;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- L2 Cache
constant CFG_L2_EN : integer := 0;
constant CFG_L2_SIZE : integer := 32;
constant CFG_L2_WAYS : integer := 4;
constant CFG_L2_HPROT : integer := 0;
constant CFG_L2_PEN : integer := 0;
constant CFG_L2_WT : integer := 0;
constant CFG_L2_RAN : integer := 0;
constant CFG_L2_SHARE : integer := 0;
constant CFG_L2_LSZ : integer := 64;
constant CFG_L2_MAP : integer := 16#00F0#;
constant CFG_L2_MTRR : integer := (8);
constant CFG_L2_EDAC : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 1 + 1;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- Gaisler Ethernet core
constant CFG_GRETH2 : integer := 1;
constant CFG_GRETH21G : integer := 0;
constant CFG_ETH2_FIFO : integer := 8;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (2);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 1;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 1;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 1;
constant CFG_SPICTRL_FT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
gpl-2.0
|
e2194828afa79b9d5773820f6056c63d
| 0.645672 | 3.565013 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/unisim/pads_unisim.vhd
| 1 | 40,305 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: pad_xilinx_gen
-- File: pad_xilinx_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Xilinx pads wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUF;
-- pragma translate_on
entity unisim_inpad is
generic (level : integer := 0; voltage : integer := x33v);
port (pad : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of unisim_inpad is
component IBUF generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_ulogic; I : in std_ulogic); end component;
attribute syn_noprune : boolean;
attribute syn_noprune of IBUF : component is true;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_5") port map (O => o, I => pad);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_3") port map (O => o, I => pad);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUF generic map (IOSTANDARD => "LVTTL") port map (O => o, I => pad);
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS33") port map (O => o, I => pad);
end generate;
cmos_25 : if voltage = x25v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS25") port map (O => o, I => pad);
end generate;
cmos_18 : if voltage = x18v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS18") port map (O => o, I => pad);
end generate;
cmos_15 : if voltage = x15v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS15") port map (O => o, I => pad);
end generate;
end generate;
sstl2x : if level = sstl2_i generate
ip : IBUF generic map (IOSTANDARD => "SSTL2_I") port map (O => o, I => pad);
end generate;
sstl2y : if level = sstl2_ii generate
ip : IBUF generic map (IOSTANDARD => "SSTL2_II") port map (O => o, I => pad);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos)
and (level /= sstl2_i)and (level /= sstl2_ii) generate
ip : IBUF port map (O => o, I => pad);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IOBUF;
-- pragma translate_on
entity unisim_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end ;
architecture rtl of unisim_iopad is
component IOBUF generic (
DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic); end component;
attribute syn_noprune : boolean;
attribute syn_noprune of IOBUF : component is true;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : IOBUF generic map (IOSTANDARD => "PCI33_5")
port map (O => o, IO => pad, I => i, T => en);
end generate;
pci_3 : if voltage /= x50v generate
op : IOBUF generic map (IOSTANDARD => "PCI33_3")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
cmos_25 : if voltage = x25v generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS25")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS25", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
cmos_18 : if voltage = x18v generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS18")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS18", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
cmos_15 : if voltage = x15v generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS15")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS15", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
end generate;
sstl2x : if level = sstl2_i generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
port map (O => o, IO => pad, I => i, T => en);
end generate;
sstl2y : if level = sstl2_ii generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
port map (O => o, IO => pad, I => i, T => en);
end generate;
sstl18i : if level = sstl18_i generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
port map (O => o, IO => pad, I => i, T => en);
end generate;
sstl18ii : if level = sstl18_ii generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
port map (O => o, IO => pad, I => i, T => en);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
(level /= sstl2_i) and (level /= sstl2_ii) and (level /= sstl18_i) and (level /= sstl18_ii) generate
op : IOBUF port map (O => o, IO => pad, I => i, T => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUF;
-- pragma translate_on
entity unisim_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic);
end ;
architecture rtl of unisim_outpad is
component OBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I : in std_ulogic); end component;
attribute syn_noprune : boolean;
attribute syn_noprune of OBUF : component is true;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_5")
port map (O => pad, I => i);
end generate;
pci_3 : if voltage /= x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_3")
port map (O => pad, I => i);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
cmos0 : if level = cmos generate
cmos_3: if voltage = x33v generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
cmos_25: if voltage = x25v generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS25")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS25", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
cmos_18: if voltage = x18v generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS18")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS18", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
cmos_15: if voltage = x15v generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS15")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS15", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
end generate;
sstl2x : if level = sstl2_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
port map (O => pad, I => i);
end generate;
sstl2y : if level = sstl2_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
port map (O => pad, I => i);
end generate;
sstl18i : if level = sstl18_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
port map (O => pad, I => i);
end generate;
sstl18ii : if level = sstl18_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
port map (O => pad, I => i);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
(level /= sstl2_i) and (level /= sstl2_ii) and
(level /= sstl18_i) and (level /= sstl18_ii) generate
op : OBUF port map (O => pad, I => i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUFT;
-- pragma translate_on
entity unisim_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12);
port (pad : out std_ulogic; i, en : in std_ulogic);
end ;
architecture rtl of unisim_toutpad is
component OBUFT generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I, T : in std_ulogic); end component;
attribute syn_noprune : boolean;
attribute syn_noprune of OBUFT : component is true;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "PCI33_5")
port map (O => pad, I => i, T => en);
end generate;
pci_3 : if voltage /= x50v generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "PCI33_3")
port map (O => pad, I => i, T => en);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => pad, I => i, T => en);
end generate;
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
slow0 : if slew = 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => pad, I => i, T => en);
end generate;
end generate;
cmos_25 : if voltage = x25v generate
slow0 : if slew = 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS25")
port map (O => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS25", SLEW => "FAST")
port map (O => pad, I => i, T => en);
end generate;
end generate;
cmos_18 : if voltage = x18v generate
slow0 : if slew = 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS18")
port map (O => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS18", SLEW => "FAST")
port map (O => pad, I => i, T => en);
end generate;
end generate;
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
op : OBUFT port map (O => pad, I => i, T => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUF;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
entity unisim_skew_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end ;
architecture rtl of unisim_skew_outpad is
component OBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I : in std_ulogic); end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
signal reset, clk0, clk0b, gnd, vcc : std_ulogic;
attribute syn_noprune : boolean;
attribute syn_noprune of OBUF : component is true;
begin
gnd <= '0'; vcc <= '1';
reset <= not rst;
dll0 : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => skew)
port map ( CLKIN => i, CLKFB => clk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => reset, CLK0 => clk0);
bufg0 : BUFG port map (I => clk0, O => clk0b);
o <= clk0b; -- output before pad
--x0 : unisim_outpad generic map (level, slew, voltage, strength) port map (pad, clk0b);
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_5")
port map (O => pad, I => clk0b);
end generate;
pci_3 : if voltage /= x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_3")
port map (O => pad, I => clk0b);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => pad, I => clk0b);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => pad, I => clk0b);
end generate;
end generate;
cmos0 : if level = cmos generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => pad, I => clk0b);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => pad, I => clk0b);
end generate;
end generate;
sstl2x : if level = sstl2_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
port map (O => pad, I => clk0b);
end generate;
sstl2y : if level = sstl2_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
port map (O => pad, I => clk0b);
end generate;
sstl18i : if level = sstl18_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
port map (O => pad, I => clk0b);
end generate;
sstl18ii : if level = sstl18_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
port map (O => pad, I => clk0b);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
(level /= sstl2_i) and (level /= sstl2_ii) and
(level /= sstl18_i) and (level /= sstl18_ii) generate
op : OBUF port map (O => pad, I => clk0b);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFG;
use unisim.IBUF;
use unisim.BUFGMUX;
use unisim.BUFG;
-- pragma translate_on
entity unisim_clkpad is
generic (level : integer := 0; voltage : integer := x33v; arch : integer := 0; hf : integer := 0;
tech : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : in std_ulogic := '1'; lock : out std_ulogic);
end;
architecture rtl of unisim_clkpad is
component IBUFG generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_logic; I : in std_logic); end component;
component IBUF generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_ulogic; I : in std_ulogic); end component;
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFR port (O : out std_logic; I, CE, CLR : in std_logic); end component;
component CLKDLL port ( CLK0 : out std_ulogic; CLK180 : out std_ulogic; CLK270 : out std_ulogic;
CLK2X : out std_ulogic; CLK90 : out std_ulogic; CLKDV : out std_ulogic;
LOCKED : out std_ulogic; CLKFB : in std_ulogic; CLKIN : in std_ulogic;
RST : in std_ulogic);
end component;
component CLKDLLHF port ( CLK0 : out std_ulogic; CLK180 : out std_ulogic; CLKDV : out std_ulogic;
LOCKED : out std_ulogic; CLKFB : in std_ulogic; CLKIN : in std_ulogic; RST : in std_ulogic);
end component;
component DCM_SP
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLK270 : out std_ulogic := '0';
CLK2X : out std_ulogic := '0';
CLK2X180 : out std_ulogic := '0';
CLK90 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
CLKFX : out std_ulogic := '0';
CLKFX180 : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
STATUS : out std_logic_vector(7 downto 0) := "00000000";
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
DSSEN : in std_ulogic := '0';
PSCLK : in std_ulogic := '0';
PSEN : in std_ulogic := '0';
PSINCDEC : in std_ulogic := '0';
RST : in std_ulogic := '0');
end component;
signal gnd, ol, ol2, ol3 : std_ulogic;
signal rst : std_ulogic;
attribute syn_noprune : boolean;
attribute syn_noprune of IBUFG : component is true;
attribute syn_noprune of IBUF : component is true;
begin
gnd <= '0'; rst <= not rstn;
g0 : if arch = 0 generate
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_5") port map (O => o, I => pad);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_3") port map (O => o, I => pad);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUFG generic map (IOSTANDARD => "LVTTL") port map (O => o, I => pad);
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS33") port map (O => o, I => pad);
end generate;
cmos_25 : if voltage = x25v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS25") port map (O => o, I => pad);
end generate;
cmos_18 : if voltage = x18v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS18") port map (O => o, I => pad);
end generate;
end generate;
sstl2 : if level = sstl2_ii generate
ip : IBUFG generic map (IOSTANDARD => "SSTL2_II") port map (O => o, I => pad);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and (level /= sstl2_ii) generate
ip : IBUFG port map (O => o, I => pad);
end generate;
lock <= '1';
end generate;
g1 : if arch = 1 generate
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_5") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_3") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUF generic map (IOSTANDARD => "LVTTL") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
cmos0 : if level = cmos generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS33") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
ip : IBUF port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
lock <= '1';
end generate;
g2 : if arch = 2 generate
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_5") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_3") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUFG generic map (IOSTANDARD => "LVTTL") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS33") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
cmos_25 : if voltage = x25v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS25") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
cmos_18 : if voltage = x18v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS18") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
ip : IBUFG port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
lock <= '1';
end generate;
g3 : if arch = 3 generate
ip : IBUFG port map (O => ol, I => pad);
sp6 : if tech = spartan6 generate
dll: DCM_SP
generic map (CLK_FEEDBACK => "1X")
port map (
CLK0 => ol2,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLKDV => open,
CLKFX => open,
CLKFX180 => open,
LOCKED => lock,
PSDONE => open,
STATUS => open,
CLKFB => ol3,
CLKIN => ol,
DSSEN => gnd,
PSCLK => gnd,
PSEN => gnd,
PSINCDEC => gnd,
RST => rst);
end generate;
nsp6 : if tech /= spartan6 generate
hf0 : if hf = 0 generate
dll: CLKDLL port map(
CLK0 => ol2,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK90 => open,
CLKDV => open,
LOCKED => lock,
CLKFB => ol3,
CLKIN => ol,
RST => rst);
end generate;
hf1 : if hf = 1 generate
dll : CLKDLLHF
port map(
CLK0 => ol2,
CLK180 => open,
CLKDV => open,
LOCKED => lock,
CLKFB => ol3,
CLKIN => ol,
RST => rst);
end generate;
end generate;
bf : BUFG port map (O => ol3, I => ol2);
o <= ol3;
end generate g3;
g4 : if arch = 4 generate
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS33") port map (O => ol, I => pad);
bf : BUFR port map (O => o, I => ol, CE => '0', CLR => '0');
end generate;
cmos_25 : if voltage /= x33v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS25") port map (O => ol, I => pad);
bf : BUFR port map (O => o, I => ol, CE => '0', CLR => '0');
end generate;
end generate;
gen0 : if (level /= cmos) generate
ip : IBUF port map (O => ol, I => pad);
bf : BUFR port map (O => o, I => ol, CE => '0', CLR => '0');
end generate;
lock <= '1';
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFDS_LVDS_25;
use unisim.IBUFDS_LVDS_33;
-- pragma translate_on
entity unisim_inpad_ds is
generic (level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of unisim_inpad_ds is
component IBUFDS_LVDS_25
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
component IBUFDS_LVDS_33
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFDS_LVDS_33 port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage /= x33v generate
ip : IBUFDS_LVDS_25 port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFGDS;
use unisim.IBUFGDS_LVDS_25;
use unisim.IBUFGDS_LVDS_33;
-- pragma translate_on
entity unisim_clkpad_ds is
generic (level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of unisim_clkpad_ds is
component IBUFGDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
component IBUFGDS_LVDS_25
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
component IBUFGDS_LVDS_33
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
attribute syn_noprune : boolean;
attribute syn_noprune of IBUFGDS_LVDS_25 : component is true;
attribute syn_noprune of IBUFGDS_LVDS_33 : component is true;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFGDS_LVDS_33 port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage = x25v generate
ip : IBUFGDS_LVDS_25 port map (O => o, I => padp, IB => padn);
end generate;
end generate;
xsstl : if level = sstl generate
sstl_18 : if voltage = x18v generate
ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"DIFF_SSTL18")
port map (O => o, I => padp, IB => padn);
end generate;
sstl_15 : if voltage = x15v generate
ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"DIFF_SSTL15")
port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if ((level /= lvds) and (level /= sstl)) generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFDS;
-- pragma translate_on
entity virtex4_inpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex4_inpad_ds is
component IBUFDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
attribute syn_noprune : boolean;
attribute syn_noprune of IBUFDS : component is true;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_33")
port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage /= x33v generate
ip : IBUFDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_25")
port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFGDS;
-- pragma translate_on
entity virtex4_clkpad_ds is
generic (level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex4_clkpad_ds is
component IBUFGDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
attribute syn_noprune : boolean;
attribute syn_noprune of IBUFGDS : component is true;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_33")
port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage = x25v generate
ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_25")
port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IOBUFDS;
-- pragma translate_on
entity unisim_iopad_ds is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; term : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end ;
architecture rtl of unisim_iopad_ds is
component IOBUFDS generic (
CAPACITANCE : string := "DONT_CARE"; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT"; IFD_DELAY_VALUE : string := "AUTO");
port (O : out std_ulogic; IO, IOB : inout std_logic; I, T : in std_ulogic); end component;
attribute syn_noprune : boolean;
attribute syn_noprune of IOBUFDS : component is true;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
iop : IOBUFDS generic map (IOSTANDARD => "LVDS_33")
port map (O => o, IO => padp, IOB => padn, I => i, T => en);
end generate;
lvds_25 : if voltage /= x33v generate
iop : IOBUFDS generic map (IOSTANDARD => "LVDS_25")
port map (O => o, IO => padp, IOB => padn, I => i, T => en);
end generate;
end generate;
xsstl18_i : if level = sstl18_i generate
iop : IOBUFDS generic map (IOSTANDARD => "DIFF_SSTL18_I")
port map (O => o, IO => padp, IOB => padn, I => i, T => en);
end generate;
xsstl18_ii : if level = sstl18_ii generate
iop : IOBUFDS generic map (IOSTANDARD => "DIFF_SSTL18_II")
port map (O => o, IO => padp, IOB => padn, I => i, T => en);
end generate;
default : if (level /= lvds) and (level /= sstl18_i) and (level /= sstl18_ii) generate
iop : IOBUFDS generic map (IOSTANDARD => "DEFAULT")
port map (O => o, IO => padp, IOB => padn, I => i, T => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUFDS;
-- pragma translate_on
entity unisim_outpad_ds is
generic (level : integer := lvds; slew : integer := 0; voltage : integer := x33v);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end ;
architecture rtl of unisim_outpad_ds is
component OBUFDS
generic(
CAPACITANCE : string := "DONT_CARE";
IOSTANDARD : string := "DEFAULT";
SLEW : string := "SLOW"
);
port(
O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic
);
end component;
attribute syn_noprune : boolean;
attribute syn_noprune of OBUFDS : component is true;
begin
slow : if slew = 0 generate
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
op : OBUFDS generic map(IOSTANDARD => "LVDS_33")
port map (O => padp, OB => padn, I => i);
end generate;
lvds_25 : if voltage /= x33v generate
op : OBUFDS generic map(IOSTANDARD => "LVDS_25")
port map (O => padp, OB => padn, I => i);
end generate;
end generate;
xsstl2_i : if level = sstl2_i generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL2_I")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl2_ii : if level = sstl2_ii generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL2_II")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl18_i : if level = sstl18_i generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL18_I")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl18_ii : if level = sstl18_ii generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL18_II")
port map (O => padp, OB => padn, I => i);
end generate;
end generate;
fast : if slew = 1 generate
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
op : OBUFDS generic map(IOSTANDARD => "LVDS_33", SLEW => "FAST")
port map (O => padp, OB => padn, I => i);
end generate;
lvds_25 : if voltage /= x33v generate
op : OBUFDS generic map(IOSTANDARD => "LVDS_25", SLEW => "FAST")
port map (O => padp, OB => padn, I => i);
end generate;
end generate;
xsstl2_i : if level = sstl2_i generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL2_I", SLEW => "FAST")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl2_ii : if level = sstl2_ii generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL2_II", SLEW => "FAST")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl18_i : if level = sstl18_i generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL18_I", SLEW => "FAST")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl18_ii : if level = sstl18_ii generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL18_II", SLEW => "FAST")
port map (O => padp, OB => padn, I => i);
end generate;
end generate;
end;
|
gpl-2.0
|
94671dff90fd18267a5dd858cbd3dc05
| 0.582434 | 3.571872 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/saed32/memory_saed32.vhd
| 1 | 5,570 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: memory_saed32.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
-- Description: Memory generators for SAED32
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library saed32;
use saed32.SRAM1RW64x32;
use saed32.SRAM1RW128x48;
use saed32.SRAM1RW128x48;
-- pragma translate_on
entity saed32_syncram is
generic ( abits : integer := 10; dbits : integer := 8);
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of saed32_syncram is
component SRAM1RW64x32 is
port (
A : in std_logic_vector( 5 downto 0 );
CE : in std_logic;
WEB : in std_logic;
OEB : in std_logic;
CSB : in std_logic;
I : in std_logic_vector( 31 downto 0 );
O : out std_logic_vector( 31 downto 0 )
);
end component;
component SRAM1RW128x48 is
port (
A : in std_logic_vector( 6 downto 0 );
CE : in std_logic;
WEB : in std_logic;
OEB : in std_logic;
CSB : in std_logic;
I : in std_logic_vector( 47 downto 0 );
O : out std_logic_vector( 47 downto 0 )
);
end component;
component SRAM1RW1024x8 is
port (
A : in std_logic_vector( 9 downto 0 );
CE : in std_logic;
WEB : in std_logic;
OEB : in std_logic;
CSB : in std_logic;
I : in std_logic_vector( 7 downto 0 );
O : out std_logic_vector( 7 downto 0 )
);
end component;
signal d, q, gnd : std_logic_vector(48 downto 0);
signal a : std_logic_vector(17 downto 0);
signal vcc, csn, wen : std_ulogic;
--constant synopsys_bug : std_logic_vector(31 downto 0) := (others => '0');
begin
csn <= not enable; wen <= not write;
gnd <= (others => '0'); vcc <= '1';
a(17 downto abits) <= (others => '0');
d(48 downto dbits) <= (others => '0');
a(abits -1 downto 0) <= address;
d(dbits -1 downto 0) <= datain(dbits -1 downto 0);
a6 : if (abits <= 6) generate
id0 : SRAM1RW64x32 port map (A => a(5 downto 0), CE => clk, WEB => wen, OEB => gnd(0), CSB => csn, I => d(31 downto 0), O => q(31 downto 0));
end generate;
a7 : if (abits = 7) generate
id0 : SRAM1RW128x48 port map (A => a(6 downto 0), CE => clk, WEB => wen, OEB => gnd(0), CSB => csn, I => d(47 downto 0), O => q(47 downto 0));
end generate;
a10 : if (abits >= 8 and abits <= 10) generate
x : for i in 0 to ((dbits-1)/8) generate
id0 : SRAM1RW1024x8 port map (A => a(9 downto 0), CE => clk, WEB => wen, OEB => gnd(0), CSB => csn, I => d(((i+1)*8)-1 downto i*8), O => q(((i+1)*8)-1 downto i*8));
end generate;
end generate;
dataout <= q(dbits -1 downto 0);
-- pragma translate_off
a_to_high : if (abits > 10) or (dbits > 32) generate
x : process
begin
assert false
report "Unsupported memory size (saed32)"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
entity saed32_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end;
architecture rtl of saed32_syncram_dp is
begin
end;
library ieee;
use ieee.std_logic_1164.all;
entity saed32_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end;
architecture rtl of saed32_syncram_2p is
begin
end;
|
gpl-2.0
|
03dc219a18df961b1f0c8f43ebc32961
| 0.596409 | 3.293909 | false | false | false | false |
aortiz49/MIPS-Processor
|
Testbenches/reg32_tb.vhd
| 1 | 1,591 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reg32_tb is
end reg32_tb;
architecture TB of reg32_tb is
component reg32
port(
D : in std_logic_vector(31 downto 0);
clk : in std_logic;
wr : in std_logic;
clr : in std_logic;
Q : out std_logic_vector(31 downto 0));
end component;
signal D : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal wr : std_logic;
signal clr : std_logic;
signal Q : std_logic_vector(31 downto 0);
signal sim_done : std_logic := '0';
begin -- TB
UUT: entity work.reg32
port map(
D => D,
clk => clk,
wr => wr,
clr => clr,
Q => Q);
-- toggle clock
clk <= not clk after 20 ns when sim_done = '0' else clk;
process
begin
-- reset
D <= x"1234ABCD";
wr <= '1';
clr <= '0';
wait until rising_edge(clk);
assert(Q = std_logic_vector(to_unsigned(0, 32))) report "Clear failed" severity warning;
-- load 1
D <= x"1234ABCD";
wr <= '1';
clr <= '1';
for i in 0 to 9 loop
wait until rising_edge(clk);
end loop;
assert(Q = std_logic_vector(to_unsigned(305441741, 32))) report "Clear failed" severity warning;
-- load 2
D <= x"ABCD1234";
wr <= '1';
clr <= '1';
for i in 0 to 2 loop
wait until rising_edge(clk);
end loop;
assert(Q = std_logic_vector(to_unsigned(305441741, 32))) report "Clear failed" severity warning;
clr <= '1';
report "SIMULATION FINISHED!";
sim_done <= '1';
end process;
end TB;
|
mit
|
5691fd4207b7649052adff1ac820e689
| 0.57071 | 2.892727 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/leon3v3/proc3.vhd
| 1 | 6,852 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: proc3
-- File: proc3.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 processor core with pipeline, mul/div & cache control
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.arith.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
entity proc3 is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := 0;
memtech : integer range 0 to NTECH := 0;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 0;
svt : integer range 0 to 1 := 0;
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
crami : out cram_in_type;
cramo : in cram_out_type;
tbi : out tracebuf_in_type;
tbo : in tracebuf_out_type;
tbi_2p : out tracebuf_2p_in_type;
tbo_2p : in tracebuf_2p_out_type;
fpi : out fpc_in_type;
fpo : in fpc_out_type;
cpi : out fpc_in_type;
cpo : in fpc_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end;
architecture rtl of proc3 is
constant IRFWT : integer := 1; --regfile_3p_write_through(memtech);
signal ici : icache_in_type;
signal ico : icache_out_type;
signal dci : dcache_in_type;
signal dco : dcache_out_type;
signal holdnx, pholdn : std_logic;
signal muli : mul32_in_type;
signal mulo : mul32_out_type;
signal divi : div32_in_type;
signal divo : div32_out_type;
begin
holdnx <= ico.hold and dco.hold and fpo.holdn; holdn <= holdnx;
pholdn <= fpo.holdn;
-- integer unit
iu : iu3
generic map (nwindows, isets, dsets, fpu, v8, cp, mac, dsu, nwp, pclow,
notag, hindex, lddel, IRFWT, disas, tbuf, pwd, svt, rstaddr, smp, fabtech,
clk2x, bp, npasi, pwrpsr)
port map (clk, rstn, holdnx, ici, ico, dci, dco, rfi, rfo, irqi, irqo,
dbgi, dbgo, muli, mulo, divi, divo, fpo, fpi, cpo, cpi, tbo, tbi, tbo_2p, tbi_2p, sclk);
-- multiply and divide units
mgen : if v8 /= 0 generate
mul0 : mul32 generic map (fabtech, v8/16, (v8 mod 4)/2, mac, (v8 mod 16)/4)
port map (rstn, clk, holdnx, muli, mulo);
div0 : div32 port map (rstn, clk, holdnx, divi, divo);
end generate;
nomgen : if v8 = 0 generate
divo <= ('0', '0', "0000", zero32);
mulo <= ('0', '0', "0000", zero32&zero32);
end generate;
-- cache controller
c0mmu : mmu_cache
generic map (
hindex, memtech, dsu, icen, irepl, isets, ilinesize, isetsize,
isetlock, dcen, drepl, dsets, dlinesize, dsetsize, dsetlock,
dsnoop, ilram, ilramsize, ilramstart, dlram, dlramsize, dlramstart,
itlbnum, dtlbnum, tlb_type, tlb_rep, cached,
clk2x, scantest, mmupgsz, smp, mmuen)
port map (rstn, clk, ici, ico, dci, dco, ahbi, ahbo, ahbsi, ahbso,
crami, cramo, pholdn, hclk, sclk, hclken
);
end;
|
gpl-2.0
|
edae9b65d56213bbc1acdb4547f1d6a1
| 0.548161 | 3.574335 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml510/leon3mp.vhd
| 1 | 56,220 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2008 - 2014 Jiri Gaisler, Jan Andersson, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.pci.all;
use gaisler.ddrpkg.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.IBUFDS;
-- pragma translate_on
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
transtech : integer := CFG_TRANSTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
fpga_cpu_reset_b : in std_ulogic;
user_clksys : in std_ulogic; -- 100 MHz main clock
sysace_fpga_clk : in std_ulogic; -- 33 MHz
-- Flash
flash_we_b : out std_ulogic;
flash_wait : in std_ulogic;
flash_reset_b : out std_ulogic;
flash_oe_b : out std_ulogic;
flash_d : inout std_logic_vector(15 downto 0);
flash_clk : out std_ulogic;
flash_ce_b : out std_ulogic;
flash_adv_b : out std_logic;
flash_a : out std_logic_vector(21 downto 0);
--pragma translate_off
-- For debug output module
sram_bw : out std_ulogic;
sim_d : inout std_logic_vector(31 downto 16);
iosn : out std_ulogic;
--pragma translate_on
-- DDR2 slot 1
dimm1_ddr2_we_b : out std_ulogic;
dimm1_ddr2_s_b : out std_logic_vector(1 downto 0);
dimm1_ddr2_ras_b : out std_ulogic;
dimm1_ddr2_pll_clkin_p : out std_ulogic;
dimm1_ddr2_pll_clkin_n : out std_ulogic;
dimm1_ddr2_odt : out std_logic_vector(1 downto 0);
dimm1_ddr2_dqs_p : inout std_logic_vector(8 downto 0);
dimm1_ddr2_dqs_n : inout std_logic_vector(8 downto 0);
dimm1_ddr2_dqm : out std_logic_vector(8 downto 0);
dimm1_ddr2_dq : inout std_logic_vector(71 downto 0);
dimm1_ddr2_cke : out std_logic_vector(1 downto 0);
-- dimm1_ddr2_cb : inout std_logic_vector(7 downto 0);
dimm1_ddr2_cas_b : out std_ulogic;
dimm1_ddr2_ba : out std_logic_vector(2 downto 0);
dimm1_ddr2_a : out std_logic_vector(13 downto 0);
-- DDR2 slot 0
dimm0_ddr2_we_b : out std_ulogic;
dimm0_ddr2_s_b : out std_logic_vector(1 downto 0);
dimm0_ddr2_ras_b : out std_ulogic;
dimm0_ddr2_pll_clkin_p : out std_ulogic;
dimm0_ddr2_pll_clkin_n : out std_ulogic;
dimm0_ddr2_odt : out std_logic_vector(1 downto 0);
dimm0_ddr2_dqs_p : inout std_logic_vector(8 downto 0);
dimm0_ddr2_dqs_n : inout std_logic_vector(8 downto 0);
dimm0_ddr2_dqm : out std_logic_vector(8 downto 0);
dimm0_ddr2_dq : inout std_logic_vector(71 downto 0);
dimm0_ddr2_cke : out std_logic_vector(1 downto 0);
-- dimm0_ddr2_cb : inout std_logic_vector(7 downto 0);
dimm0_ddr2_cas_b : out std_ulogic;
dimm0_ddr2_ba : out std_logic_vector(2 downto 0);
dimm0_ddr2_a : out std_logic_vector(13 downto 0);
dimm0_ddr2_reset_n : out std_ulogic;
-- Ethernet PHY0
phy0_txer : out std_ulogic;
phy0_txd : out std_logic_vector(3 downto 0);
phy0_txctl_txen : out std_ulogic;
phy0_txclk : in std_ulogic;
phy0_rxer : in std_ulogic;
phy0_rxd : in std_logic_vector(3 downto 0);
phy0_rxctl_rxdv : in std_ulogic;
phy0_rxclk : in std_ulogic;
phy0_reset : out std_ulogic;
phy0_mdio : inout std_logic;
phy0_mdc : out std_ulogic;
-- phy0_int : in std_ulogic;
-- Ethernet PHY1 SGMII
sgmiiclk_qo_p : in std_logic;
sgmiiclk_qo_n : in std_logic;
phy1_reset : out std_logic;
phy1_mdio : inout std_logic;
phy1_mdc : out std_logic;
phy1_int : out std_logic;
phy1_sgmii_tx_p : out std_logic;
phy1_sgmii_tx_n : out std_logic;
phy1_sgmii_rx_p : in std_logic;
phy1_sgmii_rx_n : in std_logic;
-- System ACE MPU
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_mpd : inout std_logic_vector(15 downto 0);
-- GPIO/Green LEDs
dbg_led : inout std_logic_vector(3 downto 0);
-- Red/Green LEDs
opb_bus_error : out std_ulogic;
plb_bus_error : out std_ulogic;
-- LCD
-- fpga_lcd_rw : out std_ulogic;
-- fpga_lcd_rs : out std_ulogic;
-- fpga_lcd_e : out std_ulogic;
-- fpga_lcd_db : out std_logic_vector(7 downto 0);
-- DVI
dvi_xclk_p : out std_ulogic;
dvi_xclk_n : out std_ulogic;
dvi_v : out std_ulogic;
dvi_reset_b : out std_ulogic;
dvi_h : out std_ulogic;
dvi_gpio1 : inout std_logic;
dvi_de : out std_ulogic;
dvi_d : out std_logic_vector(11 downto 0);
-- PCI
pci_p_trdy_b : inout std_logic;
pci_p_stop_b : inout std_logic;
pci_p_serr_b : inout std_logic;
pci_p_rst_b : inout std_logic;
pci_p_req_b : in std_logic_vector(0 to 4);
pci_p_perr_b : inout std_logic;
pci_p_par : inout std_logic;
pci_p_lock_b : inout std_logic;
pci_p_irdy_b : inout std_logic;
pci_p_intd_b : in std_logic;
pci_p_intc_b : in std_logic;
pci_p_intb_b : in std_logic;
pci_p_inta_b : in std_logic;
pci_p_gnt_b : out std_logic_vector(0 to 4);
pci_p_frame_b : inout std_logic;
pci_p_devsel_b : inout std_logic;
pci_p_clk5_r : out std_ulogic;
pci_p_clk5 : in std_ulogic;
pci_p_clk4_r : out std_ulogic;
pci_p_clk3_r : out std_ulogic;
pci_p_clk1_r : out std_ulogic;
pci_p_clk0_r : out std_ulogic;
pci_p_cbe_b : inout std_logic_vector(3 downto 0);
pci_p_ad : inout std_logic_vector(31 downto 0);
-- pci_fpga_idsel : in std_ulogic;
sbr_pwg_rsm_rstj : inout std_logic;
sbr_nmi_r : in std_ulogic;
sbr_intr_r : in std_ulogic;
sbr_ide_rst_b : inout std_logic;
-- IIC/SMBus and sideband signals
iic_sda_dvi : inout std_logic;
iic_scl_dvi : inout std_logic;
fpga_sda : inout std_logic;
fpga_scl : inout std_logic;
iic_therm_b : in std_ulogic;
iic_reset_b : out std_ulogic;
iic_irq_b : in std_ulogic;
iic_alert_b : in std_ulogic;
-- SPI
spi_data_out : in std_logic;
spi_data_in : out std_ulogic;
spi_data_cs_b : out std_ulogic;
spi_clk : out std_ulogic;
-- UARTs
uart1_txd : out std_ulogic;
uart1_rxd : in std_ulogic;
uart1_rts_b : out std_ulogic;
uart1_cts_b : in std_ulogic;
uart0_txd : out std_ulogic;
uart0_rxd : in std_ulogic;
uart0_rts_b : out std_ulogic
-- uart0_cts_b : in std_ulogic
-- System monitor
-- test_mon_vrefp : in std_ulogic;
-- test_mon_vp0_p : in std_ulogic;
-- test_mon_vn0_n : in std_ulogic
-- test_mon_avdd : in std_ulogic
);
end;
architecture rtl of leon3mp is
component svga2ch7301c
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component IBUFDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA;
-- Set this constant to 1 to include an APB bridge with the Logan logic
-- analyzer attached to the PCI signals
constant CFG_LOGAN : integer := 0;
signal ddr0_clk_fb, ddr1_clk_fb : std_logic;
signal vcc, gnd : std_logic_vector(31 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal apbi, apb1i : apb_slv_in_type;
signal apbo, apb1o : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, clkm2x, rstn, rstraw, flashclkl : std_ulogic;
signal clkddr, clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2, cgi3 : clkgen_in_type;
signal cgo, cgo2, cgo3 : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal opb_bus_errorl, plb_bus_errorl : std_ulogic;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock0, lock1, lclk, clkml0, clkml1 : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal rst : std_ulogic;
signal egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal sgmii_refclk, sgmii_rst: std_logic;
signal mdio_reset, mdio_o, mdio_oe, mdio_i, mdc, mdint : std_logic;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal vgalock : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
constant BOARD_FREQ_200 : integer := 200000; -- input frequency in KHz
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
-- DDR clock is 200 MHz clock unless CFG_DDR2SP_NOSYNC is set. If that config
-- option is set the DDR clock is 2x CPU clock.
constant DDR_FREQ : integer :=
BOARD_FREQ_200 - (BOARD_FREQ_200 - 2*CPU_FREQ)*CFG_DDR2SP_NOSYNC;
constant IOAEN : integer := CFG_DDR2SP+CFG_GRACECTRL;
signal stati : ahbstat_in_type;
signal ddr0_clkv : std_logic_vector(2 downto 0);
signal ddr0_clkbv : std_logic_vector(2 downto 0);
signal ddr1_clkv : std_logic_vector(2 downto 0);
signal ddr1_clkbv : std_logic_vector(2 downto 0);
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
signal sysmoni : grsysmon_in_type;
signal sysmono : grsysmon_out_type;
signal pciclk, pci_clk, pci_clk_fb : std_ulogic;
signal pci_arb_gnt : std_logic_vector(0 to 7);
signal pci_arb_req : std_logic_vector(0 to 7);
signal pci_arb_reql : std_logic_vector(0 to 4);
signal pci_reql : std_ulogic;
signal pci_host, pci_66 : std_ulogic;
signal pci_intv : std_logic_vector(3 downto 0);
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal pci_dirq : std_logic_vector(3 downto 0);
signal clkma, clkmb, clkmc : std_ulogic;
signal clk0_tb, rst0_tb, rst0_tbn : std_ulogic;
signal phy_init_done : std_ulogic;
-- Logan signals
signal signals : std_logic_vector(63*CFG_LOGAN downto 0);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkml0 : signal is true;
attribute syn_preserve of clkml0 : signal is true;
attribute syn_keep of clkml1 : signal is true;
attribute syn_preserve of clkml1 : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
attribute syn_keep of clk25 : signal is true;
attribute syn_preserve of clk25 : signal is true;
attribute syn_keep of clk40 : signal is true;
attribute syn_preserve of clk40 : signal is true;
attribute syn_keep of clk65 : signal is true;
attribute syn_preserve of clk65 : signal is true;
attribute syn_keep of phy_init_done : signal is true;
attribute syn_preserve of phy_init_done : signal is true;
attribute syn_keep of pciclk : signal is true;
attribute syn_preserve of pciclk : signal is true;
attribute syn_keep of sgmii_refclk : signal is true;
attribute syn_preserve of sgmii_refclk : signal is true;
attribute keep : boolean;
attribute keep of lock0 : signal is true;
attribute keep of lock1 : signal is true;
attribute keep of clkml0 : signal is true;
attribute keep of clkml1 : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute keep of clkvga : signal is true;
attribute keep of clk25 : signal is true;
attribute keep of clk40 : signal is true;
attribute keep of clk65 : signal is true;
attribute keep of pciclk : signal is true;
attribute keep of sgmii_refclk : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of sysace_fpga_clk_pad : label is true;
begin
vcc <= (others => '1'); gnd <= (others => '0');
rst0_tbn <= not rst0_tb;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
flashclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (flash_clk, flashclkl);
sysace_fpga_clk_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sysace_fpga_clk, clkace);
pci_p_clk5_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (pci_p_clk5, pci_clk_fb);
pci_p_clk5_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk5_r, pci_clk);
pci_p_clk4_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk4_r, pci_clk);
pci_p_clk3_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk3_r, pci_clk);
pci_p_clk1_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk1_r, pci_clk);
pci_p_clk0_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk0_r, pci_clk);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 1,
1, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ, 1)
port map (lclk, pci_clk_fb, clkmc, open, clkm2x, flashclkl, pciclk, cgi, cgo,
open, open, clk_200);
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= '0';
-- clkgen1 : clkgen -- Ethernet 1G PHY clock generator
-- generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
-- port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
-- cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
-- egtx_clk_pad : outpad generic map (tech => padtech)
-- port map (phy_gtx_clk, egtx_clk);
clkgen2 : clkgen -- PCI clock generator
generic map (CFG_FABTECH, 2, 6, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), pci_clk, open, open, open, open, cgi3, cgo3);
cgi3.pllctrl <= "00"; cgi3.pllrst <= rstraw; cgi3.pllref <= '0';
iic_reset_b_pad : outpad generic map (tech => padtech)
port map (iic_reset_b, rstn);
resetn_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (fpga_cpu_reset_b, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock0 and lock1 and cgo.clklock and cgo3.clklock;
clk_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (user_clksys, lclk);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML510,
ioen => IOAEN, nahbm => maxahbm, nahbs => 11 + CFG_LOGAN)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE,
CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
opb_bus_errorl <= not dbgo(0).error;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#D00#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ,
bwidth => AHBDW, ahbpf => CFG_AHBPF)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= not gpioo.val(0); -- Position on on GPIO DIP switch
plb_bus_errorl <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; plb_bus_errorl <= '0';
end generate;
opb_bus_error_pad : outpad generic map (tech => padtech)
port map (opb_bus_error, opb_bus_errorl);
plb_bus_error_pad : outpad generic map (tech => padtech)
port map (plb_bus_error, plb_bus_errorl);
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
end generate;
nodcom : if CFG_AHB_UART = 0 generate
duo.txd <= '0'; duo.rtsn <= '1';
end generate;
dsurx_pad : inpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_rxd, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_txd, duo.txd);
-- dsucts_pad : inpad generic map (tech => padtech, level => cmos, voltage => x33v)
-- port map (uart0_cts_b, dui.ctsn);
dsurts_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_rts_b, duo.rtsn);
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '1'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 0, rammask => 0, paddr => 0, srbanks => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
sden => CFG_MCTRL_SDEN, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo);
end generate;
nomctrl: if CFG_MCTRL_LEON2 = 0 generate
memo.address <= (others => '0'); memo.romsn <= (others => '1');
memo.oen <= '1'; memo.wrn <= (others => '1');
memo.vbdrive <= (others => '1'); memo.writen <= '1';
end generate;
flash_reset_b_pad : outpad generic map (tech => padtech)
port map (flash_reset_b, rstn);
-- flash_wait_pad : inpad generic map (tech => padtech)
-- port map (flash_wait, );
flash_adv_b_pad : outpad generic map (tech => padtech)
port map (flash_adv_b, gnd(0));
flash_a_pads : outpadv generic map (width => 22, tech => padtech)
port map (flash_a, memo.address(22 downto 1));
flash_ce_b_pad : outpad generic map (tech => padtech)
port map (flash_ce_b, memo.romsn(0));
flash_oe_b_pad : outpad generic map (tech => padtech)
port map (flash_oe_b, memo.oen);
--pragma translate_off
rwen_pad : outpad generic map (tech => padtech)
port map (sram_bw, memo.wrn(3));
sim_d_pads : iopadvv generic map (tech => padtech, width => 16)
port map (sim_d, memo.data(15 downto 0),
memo.vbdrive(15 downto 0), memi.data(15 downto 0));
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
flash_we_b_pad : outpad generic map (tech => padtech)
port map (flash_we_b, memo.writen);
flash_d_pads : iopadvv generic map (tech => padtech, width => 16)
port map (flash_d, memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
dbg_led0_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (dbg_led(3), phy_init_done);
clkm <= clkma; clkma <= clkmb; clkmb <= clkmc;
ddrsp0 : if (CFG_DDR2SP /= 0) generate
phy_init_done <= '1';
-- DDR clock selection
-- If the synchronization registers are removed in the DDR controller, we
-- assume that the user wants to run at 2x the system clock. Otherwise the
-- DDR clock is generated from the 200 MHz clock.
ddrclkselarb: if CFG_DDR2SP_NOSYNC = 0 generate
BUFGDDR : BUFG port map (I => clk_200, O => clkddr);
end generate;
ddrclksel2x: if CFG_DDR2SP_NOSYNC /= 0 generate
clkddr <= clkm2x;
end generate;
dimm0_ddr2_reset_n_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (dimm0_ddr2_reset_n, rst);
-- Slot 0
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#e00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => DDR_FREQ/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10 - (CFG_DDR2SP_FREQ/10-1)*CFG_DDR2SP_NOSYNC,
clkdiv => 20 - (19)*CFG_DDR2SP_NOSYNC, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => CFG_DDR2SP_DATAWIDTH,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
readdly => 1, rskew => 0, oepol => 0,
dqsgating => 0, rstdel => 200, eightbanks => 1,
numidelctrl => 2 + CFG_DDR2SP_DATAWIDTH/64, norefclk => 0, odten => 3,
nosync => CFG_DDR2SP_NOSYNC)
port map (rst, rstn, clkddr, clkm, clk_200, lock0, clkml0, clkml0, ahbsi, ahbso(0),
ddr0_clkv, ddr0_clkbv, ddr0_clk_fb, ddr0_clk_fb,
dimm0_ddr2_cke, dimm0_ddr2_s_b, dimm0_ddr2_we_b, dimm0_ddr2_ras_b,
dimm0_ddr2_cas_b, dimm0_ddr2_dqm(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm0_ddr2_dqs_p(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm0_ddr2_dqs_n(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)), dimm0_ddr2_a,
dimm0_ddr2_ba(2 downto 0), dimm0_ddr2_dq(63 downto 32*(32/CFG_DDR2SP_DATAWIDTH)),
dimm0_ddr2_odt);
dimm0_ddr2_pll_clkin_p <= ddr0_clkv(0);
dimm0_ddr2_pll_clkin_n <= ddr0_clkbv(0);
-- Ground unused bank address and memory mask
-- dimm0_ddr2_ba_notused_pad : outpad generic map (tech => padtech, level => SSTL18_I)
-- port map (dimm0_ddr2_ba(2), gnd(0));
dimm0_ddr2_dqm_notused8_pad : outpad generic map (tech => padtech, level => SSTL18_I)
port map (dimm0_ddr2_dqm(8), gnd(0));
-- Tri-state unused data strobe
dimm0_dqsp_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm0_ddr2_dqs_p(8), gnd(0), vcc(0), open);
dimm0_dqsn_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm0_ddr2_dqs_n(8), gnd(0), vcc(0), open);
-- Tristate unused check bits
dimm0_cb_notused_pad : iopadv generic map (tech => padtech, width => 8, level => SSTL18_II)
port map (dimm0_ddr2_dq(71 downto 64), gnd(7 downto 0), vcc(0), open);
-- Handle signals not used with 32-bit interface
ddr032bit: if CFG_DDR2SP_DATAWIDTH /= 64 generate
dimm0_ddr2_dqm_notused30_pads : outpadv generic map (tech => padtech, width => 4, level => SSTL18_I)
port map (dimm0_ddr2_dqm(3 downto 0), gnd(3 downto 0));
dimm0_dqsp_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm0_ddr2_dqs_p(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm0_dqsn_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm0_ddr2_dqs_n(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm0_dq_notused_pads : iopadv generic map (tech => padtech, width => 32, level => SSTL18_II)
port map (dimm0_ddr2_dq(31 downto 0), gnd, vcc(0), open);
end generate;
-- Slot 1
ddrc1 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 1, haddr => 16#600#, hmask => 16#E00#, ioaddr => 2,
pwron => CFG_DDR2SP_INIT, MHz => DDR_FREQ/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10 - (CFG_DDR2SP_FREQ/10-1)*CFG_DDR2SP_NOSYNC,
clkdiv => 20 - (19)*CFG_DDR2SP_NOSYNC, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => CFG_DDR2SP_DATAWIDTH,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
readdly => 1, rskew => 0, oepol => 0,
dqsgating => 0, rstdel => 200, eightbanks => 1,
numidelctrl => 2 + CFG_DDR2SP_DATAWIDTH/64, norefclk => 0, odten => 3,
nosync => CFG_DDR2SP_NOSYNC)
port map (rst, rstn, clkddr, clkm, clk_200, lock1, clkml1, clkml1, ahbsi, ahbso(1),
ddr1_clkv, ddr1_clkbv, ddr1_clk_fb, ddr1_clk_fb,
dimm1_ddr2_cke, dimm1_ddr2_s_b, dimm1_ddr2_we_b, dimm1_ddr2_ras_b,
dimm1_ddr2_cas_b, dimm1_ddr2_dqm(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_dqs_p(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_dqs_n(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)), dimm1_ddr2_a,
dimm1_ddr2_ba(2 downto 0), dimm1_ddr2_dq(63 downto 32*(32/ CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_odt);
dimm1_ddr2_pll_clkin_p <= ddr1_clkv(0);
dimm1_ddr2_pll_clkin_n <= ddr1_clkbv(0);
-- Ground unused bank address and memory mask
-- dimm1_ddr2_ba_notused_pad : outpad generic map (tech => padtech, level => SSTL18_I)
-- port map (dimm1_ddr2_ba(2), gnd(0));
dimm1_ddr2_dqm_notused8_pad : outpad generic map (tech => padtech, level => SSTL18_I)
port map (dimm1_ddr2_dqm(8), gnd(0));
-- Tri-state unused data strobe
dimm1_dqsp_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm1_ddr2_dqs_p(8), gnd(0), vcc(0), open);
dimm1_dqsn_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm1_ddr2_dqs_n(8), gnd(0), vcc(0), open);
-- Tristate unused check bits
dimm1_cb_notused_pad : iopadv generic map (tech => padtech, width => 8, level => SSTL18_II)
port map (dimm1_ddr2_dq(71 downto 64), gnd(7 downto 0), vcc(0), open);
-- Handle signals not used with 32-bit interface
ddr132bit: if CFG_DDR2SP_DATAWIDTH /= 64 generate
dimm1_ddr2_dqm_notused30_pads : outpadv generic map (tech => padtech, width => 4, level => SSTL18_I)
port map (dimm1_ddr2_dqm(3 downto 0), gnd(3 downto 0));
dimm1_dqsp_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm1_ddr2_dqs_p(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm1_dqsn_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm1_ddr2_dqs_n(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm1_dq_notused_pads : iopadv generic map (tech => padtech, width => 32, level => SSTL18_II)
port map (dimm1_ddr2_dq(31 downto 0), gnd, vcc(0), open);
end generate;
end generate;
-- noddr : if (CFG_DDR2SP = 0) generate lock0 <= '1'; lock1 <= '1'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 5, hirq => 5,
haddr => 16#000#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(5), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL = 0 generate
aceo <= gracectrl_none;
end generate nograce;
sysace_mpa_pads : outpadv generic map (width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_mpd_pads : iopadv generic map (tech => padtech, width => 16)
port map (sysace_mpd, aceo.do, aceo.doen, acei.di);
sysace_mpoe_pad : outpad generic map (tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- AHB ROM ---------------------------------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 10, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map (rstn, clkm, ahbsi, ahbso(10));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 4, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(4), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
end generate;
noua1: if CFG_UART1_ENABLE = 0 generate u1o.txd <= '0'; u1o.rtsn <= '1'; end generate;
ua1rx_pad : inpad generic map (tech => padtech) port map (uart1_rxd, u1i.rxd);
ua1tx_pad : outpad generic map (tech => padtech) port map (uart1_txd, u1o.txd);
ua1cts_pad : inpad generic map (tech => padtech) port map (uart1_cts_b, u1i.ctsn);
ua1rts_pad : outpad generic map (tech => padtech) port map (uart1_rts_b, u1o.rtsn);
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
pci_dirq(3 downto 1) <= (others => '0');
pci_dirq(0) <= orv(irqi(0).irl);
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 14, paddr => 14,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 40000, clk2 => 25000, clk3 => 15385, burstlen => 6)
port map(rstn, clkm, clkvga, apbi, apbo(14), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
dvi0 : svga2ch7301c generic map (tech => fabtech, idf => 2)
port map (lclk, rstraw, clk_sel, vgao, clkvga, clk25, clk40, clk65,
clkvga, clk25, clk40, clk65, clkvga_p, clkvga_n,
vgalock, lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 6, paddr => 6, pmask => 16#FFF#,
pirq => 6, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(6), dvi_i2ci, dvi_i2co);
end generate;
novga : if CFG_SVGA_ENABLE = 0 generate
apbo(14) <= apb_none; apbo(6) <= apb_none;
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
dvi_d_pad : outpadv generic map (width => 12, tech => padtech)
port map (dvi_d, lcd_datal);
dvi_xclk_p_pad : outpad generic map (tech => padtech)
port map (dvi_xclk_p, clkvga_p);
dvi_xclk_n_pad : outpad generic map (tech => padtech)
port map (dvi_xclk_n, clkvga_n);
dvi_h_pad : outpad generic map (tech => padtech)
port map (dvi_h, lcd_hsyncl);
dvi_v_pad : outpad generic map (tech => padtech)
port map (dvi_v, lcd_vsyncl);
dvi_de_pad : outpad generic map (tech => padtech)
port map (dvi_de, lcd_del);
dvi_reset_b_pad : outpad generic map (tech => padtech)
port map (dvi_reset_b, rstn);
iic_scl_dvi_pad : iopad generic map (tech => padtech)
port map (iic_scl_dvi, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
iic_sda_dvi_pad : iopad generic map (tech => padtech)
port map (iic_sda_dvi, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
end generate;
nogpio0: if CFG_GRGPIO_ENABLE = 0 generate
gpioo.oen <= (others => '1'); gpioo.val <= (others => '0');
gpioo.dout <= (others => '1');
end generate;
dbg_led_pads : iopadvv generic map (tech => padtech, width => 3, level => cmos, voltage => x33v)
port map (dbg_led(2 downto 0), gpioo.dout(2 downto 0), gpioo.oen(2 downto 0),
gpioi.din(2 downto 0));
dvi_gpio_pad : iopad generic map (tech => padtech)
port map (dvi_gpio1, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
iic_therm_b_pad : inpad generic map (tech => padtech)
port map (iic_therm_b, gpioi.din(9));
iic_irq_b_pad : inpad generic map (tech => padtech)
port map (iic_irq_b, gpioi.din(10));
iic_alert_b_pad : inpad generic map (tech => padtech)
port map (iic_alert_b, gpioi.din(11));
sbr_pwg_rsm_rstj_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sbr_pwg_rsm_rstj, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
sbr_nmi_r_pad : inpad generic map (tech => padtech)
port map (sbr_nmi_r, gpioi.din(6));
sbr_intr_r_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sbr_intr_r, gpioi.din(5));
sbr_ide_rst_b_pad : iopad generic map (tech => padtech)
port map (sbr_ide_rst_b, gpioo.dout(8), gpioo.oen(8), gpioi.din(8));
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 3, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), i2ci, i2co);
end generate;
noi2cm: if CFG_I2C_ENABLE = 0 generate
i2co.scloen <= '1'; i2co.sdaoen <= '1';
i2co.scl <= '0'; i2co.sda <= '0';
end generate;
i2c_scl_pad : iopad generic map (tech => padtech)
port map (fpga_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (fpga_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 10, paddr => 10, pmask => 16#fff#, pirq => 12,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(10), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
miso_pad : inpad generic map (tech => padtech)
port map (spi_data_out, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_data_in, spio.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spio.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (spi_data_cs_b, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate
miso_pad : inpad generic map (tech => padtech)
port map (spi_data_out, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_data_in, vcc(0));
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, gnd(0));
slvsel_pad : outpad generic map (tech => padtech)
port map (spi_data_cs_b, vcc(0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
apb1 : apbctrl -- AHB/APB bridge
generic map (hindex => 6, haddr => CFG_APBADDR + 1, nslaves => 3)
port map (rstn, clkm, ahbsi, ahbso(6), apb1i, apb1o);
-- log: if CFG_LOGAN = 1 generate -- Logan is enabled by constant
-- -- declared above
-- apb0 : apbctrl -- AHB/APB bridge
-- generic map (hindex => 11, haddr => 16#F00#, nslaves => 1)
-- port map (rstn, clkm, ahbsi, ahbso(11), apb1i, apb1o);
-- logan0 : logan -- Logic analyzer
-- generic map (dbits => 64, depth => 4096, trigl => 2, usereg => 1,
-- usequal => 0, pindex => 0, paddr => 0, pmask => 16#F00#,
-- memtech => memtech)
-- port map (rstn, clkm, pciclk, apb1i, apb1o(0), signals);
-- signals(0) <= pcii.rst;
-- signals(1) <= pcii.gnt;
-- signals(2) <= pcii.idsel;
-- signals(34 downto 3) <= pcii.ad;
-- signals(38 downto 35) <= pcii.cbe;
-- signals(39) <= pcii.frame;
-- signals(40) <= pcii.irdy;
-- signals(41) <= pcii.trdy;
-- signals(42) <= pcii.devsel;
-- signals(43) <= pcii.stop;
-- signals(44) <= pcii.lock;
-- signals(45) <= pcii.perr;
-- signals(46) <= pcii.serr;
-- signals(47) <= pcii.par;
-- signals(48) <= pcii.host;
-- signals(49) <= pcii.pci66;
-- signals(53 downto 50) <= pcii.int;
-- signals(58 downto 54) <= pci_arb_gnt(0 to 4);
-- signals(63 downto 59) <= pci_arb_req(0 to 4);
-- end generate log;
nolog: if CFG_LOGAN /= 1 generate
signals <= (others => '0');
apb1o(0) <= apb_none;
end generate nolog;
l3sgen : if CFG_L3S_ENABLE /= 0 generate
l3s : l3stat
generic map (pindex => 1, paddr => 1, pmask => 16#fff#,
ncnt => CFG_L3S_CNT, ncpu => CFG_NCPU,
nmax => CFG_L3S_NMAX, lahben => 1, dsuen => CFG_DSU)
port map (rstn => rstn, clk => clkm, apbi => apb1i, apbo => apb1o(1),
ahbsi => ahbsi, dbgo => dbgo);
end generate;
nol3s : if CFG_L3S_ENABLE = 0 generate
apb1o(1) <= apb_none;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 4, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy0_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (phy0_txclk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (phy0_rxclk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (phy0_rxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy0_rxctl_rxdv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy0_rxer, ethi.rx_er);
-- Collision detect and carrier sense are not connected on the
-- board.
ethi.rx_col <= '0';
ethi.rx_crs <= ethi.rx_dv;
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (phy0_txd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (phy0_txctl_txen, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy0_txer, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy0_mdc, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy0_reset, rstn);
-- ethi.gtx_clk <= egtx_clk;
end generate;
eth2 : if CFG_GRETH2 = 1 generate -- Gaisler ethernet MAC
sgmii_rst <= not rst;
refclk_bufds : IBUFDS
port map (
I => sgmiiclk_qo_p,
IB => sgmiiclk_qo_n,
O => sgmii_refclk);
e2 : greths generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH,
pindex => 2, paddr => 2, pirq => 10,
fabtech => fabtech, memtech => memtech, transtech => transtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH2_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH21G)
port map(
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH),
apbi => apb1i,
apbo => apb1o(2),
-- High-speed Serial Interface
clk_125 => sgmii_refclk,
rst_125 => sgmii_rst,
eth_rx_p => phy1_sgmii_rx_p,
eth_rx_n => phy1_sgmii_rx_n,
eth_tx_p => phy1_sgmii_tx_p,
eth_tx_n => phy1_sgmii_tx_n,
-- MDIO interface
reset => mdio_reset,
mdio_o => mdio_o,
mdio_oe => mdio_oe,
mdio_i => mdio_i,
mdc => mdc,
mdint => mdint,
-- Control signals
phyrstaddr => "00000",
edcladdr => "0000",
edclsepahb => '0',
edcldisable => '0'
);
e2mdio_pad : iopad generic map (tech => padtech)
port map (phy1_mdio, mdio_o, mdio_oe, mdio_i);
e2mdc_pad : outpad generic map (tech => padtech)
port map (phy1_mdc, mdc);
e2rst_pad : outpad generic map (tech => padtech)
port map (phy1_reset, mdio_reset);
e2int_pad : outpad generic map (tech => padtech)
port map (phy1_int, mdint);
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
----------------------------------------------------------------------
pp : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
oepol => 0,
hmindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2,
hdmindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2+1,
hsindex => 7,
haddr => 16#800#,
hmask => 16#c00#,
ioaddr => 16#400#,
pindex => 4,
paddr => 4,
irq => 5,
irqmode => 0,
master => CFG_GRPCI2_MASTER,
target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA,
tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID,
deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS,
revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP,
ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO,
extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0,
bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2,
bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4,
bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH,
fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN,
deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK,
hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2,
hostrst => 1,
bypass => CFG_GRPCI2_BYPASS,
debug => 0,
tbapben => 0,
tbpindex => 5,
tbpaddr => 16#400#,
tbpmask => 16#C00#
)
port map (
rstn,
clkm,
pciclk,
pci_dirq,
pcii,
pcio,
apbi,
apbo(4),
ahbsi,
ahbso(7),
ahbmi,
ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2),
ahbmi,
ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2+1)
);
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 13, paddr => 13, nb_agents => CFG_PCI_ARB_NGNT,
apb_en => CFG_PCI_ARBAPB)
port map (clk => pciclk, rst_n => pcii.rst, req_n => pci_arb_req, frame_n => pcii.frame,
gnt_n => pci_arb_gnt, pclk => clkm, prst_n => rstn, apbi => apbi, apbo => apbo(13));
-- Internal connection of req(2)
pci_arb_req(0 to 4) <= pci_arb_reql(0 to 1) & pci_reql & pci_arb_reql(3 to 4);
pci_arb_req(5 to 7) <= (others => '1');
end generate;
end generate;
nopcia0: if CFG_GRPCI2_MASTER = 0 or CFG_PCI_ARB = 0 generate
pci_arb_gnt <= (others => '1');
end generate;
nopci_mtf: if CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET = 0 generate
pcio <= pci_out_none;
end generate;
pgnt_pad : outpadv generic map (tech => padtech, width => 5, level => pci33)
port map (pci_p_gnt_b, pci_arb_gnt(0 to 4));
preq_pad : inpadv generic map (tech => padtech, width => 5, level => pci33)
port map (pci_p_req_b, pci_arb_reql);
pcipads0 : pcipads -- PCI pads
generic map (padtech => padtech, host => 2, int => 14, no66 => 1, onchipreqgnt => 1,
drivereset => 1, constidsel => 1)
port map (pci_rst => pci_p_rst_b, pci_gnt => pci_arb_gnt(2), pci_idsel => '0', --pci_fpga_idsel,
pci_lock => pci_p_lock_b, pci_ad => pci_p_ad, pci_cbe => pci_p_cbe_b,
pci_frame => pci_p_frame_b, pci_irdy => pci_p_irdy_b, pci_trdy => pci_p_trdy_b,
pci_devsel => pci_p_devsel_b, pci_stop => pci_p_stop_b, pci_perr => pci_p_perr_b,
pci_par => pci_p_par, pci_req => pci_reql, pci_serr => pci_p_serr_b,
pci_host => pci_host, pci_66 => pci_66, pcii => pcii, pcio => pcio, pci_int => pci_intv);
pci_intv <= pci_p_intd_b & pci_p_intc_b & pci_p_intb_b & pci_p_inta_b;
pci_host <= '0'; -- Always host
pci_66 <= '0';
-----------------------------------------------------------------------
--- SYSTEM MONITOR ---------------------------------------------------
-----------------------------------------------------------------------
grsmon: if CFG_GRSYSMON = 1 generate
sysm0 : grsysmon generic map (tech => fabtech, hindex => 8,
hirq => 1, caddr => 16#003#, cmask => 16#fff#,
saddr => 16#004#, smask => 16#ffe#, split => CFG_SPLIT,
extconvst => 0, wrdalign => 1, INIT_40 => X"0000",
INIT_41 => X"0000", INIT_42 => X"0800", INIT_43 => X"0000",
INIT_44 => X"0000", INIT_45 => X"0000", INIT_46 => X"0000",
INIT_47 => X"0000", INIT_48 => X"0000", INIT_49 => X"0000",
INIT_4A => X"0000", INIT_4B => X"0000", INIT_4C => X"0000",
INIT_4D => X"0000", INIT_4E => X"0000", INIT_4F => X"0000",
INIT_50 => X"0000", INIT_51 => X"0000", INIT_52 => X"0000",
INIT_53 => X"0000", INIT_54 => X"0000", INIT_55 => X"0000",
INIT_56 => X"0000", INIT_57 => X"0000",
SIM_MONITOR_FILE => "sysmon.txt")
port map (rstn, clkm, ahbsi, ahbso(8), sysmoni, sysmono);
sysmoni.convst <= '0';
sysmoni.convstclk <= '0';
sysmoni.vauxn <= (others => '0');
sysmoni.vauxp <= (others => '0');
-- sysmoni.vn <= test_mon_vn0_n;
-- sysmoni.vp <= test_mon_vp0_p;
end generate grsmon;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 9, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(9));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_GRETH2+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_GRETH2+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => system_table(XILINX_ML510),
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
gpl-2.0
|
7cb32153b1870fee1dc6912e68ac5b6e
| 0.572234 | 3.305503 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-gr-xc6s/ahb2mig_grxc6s_2p.vhd
| 1 | 23,100 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_grxc6s_2p
-- File: ahb2mig_grxc6s_2p.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Spartan-6 MIG.
-- One bidir 32-bit port is used for the main AHB bus, while
-- a second read-only port can be enabled for a VGA frame buffer.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2mig_grxc6s_2p is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
vgamst : integer := 0;
vgaburst : integer := 0;
clkdiv : integer := 2
);
port(
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
ahbmi : out ahb_mst_in_type;
ahbmo : in ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
test_error : out std_logic;
rst_n_syn : out std_logic;
rst_n_async : in std_logic;
clk_amba : out std_logic;
clk_mem_n : in std_logic;
clk_mem_p : in std_logic;
clk_125 : out std_logic;
clk_100 : out std_logic
);
end ;
architecture rtl of ahb2mig_grxc6s_2p is
component mig_37
generic
(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000; -- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0; -- # = 1 for active low reset, -- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED"; -- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE"; -- # = TRUE, Enables the soft calibration logic, -- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE"; -- # = TRUE, Simulating the design. Useful to reduce the simulation time, -- # = FALSE, Implementing the design.
DEBUG_EN : integer := 0; -- # = 1, Enable debug signals/controls, -- = 0, Disable debug signals/controls.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; -- The order in which user address is provided to the memory controller, -- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16; -- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 13; -- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3; -- External memory bank address width.
C3_CLKOUT5_DIVIDE : integer := 10 -- Extra clock divider
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
clk_125 : out std_logic; -- 125 MHz for RGMII
clk_100 : out std_logic; -- Extra clock
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_rd_clk : in std_logic;
c3_p2_rd_en : in std_logic;
c3_p2_rd_data : out std_logic_vector(31 downto 0);
c3_p2_rd_full : out std_logic;
c3_p2_rd_empty : out std_logic;
c3_p2_rd_count : out std_logic_vector(6 downto 0);
c3_p2_rd_overflow : out std_logic;
c3_p2_rd_error : out std_logic
);
end component;
type bstate_type is (idle, start, read1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
end record;
type mcb_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
cmd_bl : std_logic_vector(5 downto 0);
cmd_byte_addr : std_logic_vector(29 downto 0);
wr_full : std_logic;
wr_empty : std_logic;
wr_underrun : std_logic;
wr_error : std_logic;
wr_mask : std_logic_vector(3 downto 0);
wr_en : std_logic;
wr_data : std_logic_vector(31 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
rd_en : std_logic;
end record;
type reg2_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
end record;
type p2_if_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_bl : std_logic_vector(5 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
rd_en : std_logic;
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
end record;
signal r, rin : reg_type;
signal r2, r2in : reg2_type;
signal i : mcb_type;
signal p2 : p2_if_type;
signal clk_amba_i : std_logic;
signal rst_n_syn_i : std_logic;
signal rst_syn : std_logic;
signal calib_done_i : std_logic;
begin
clk_amba <= clk_amba_i;
rst_n_syn <= rst_n_syn_i and calib_done_i;
rst_n_syn_i <= not rst_syn;
calib_done <= calib_done_i;
comb: process( rst_n_syn_i, r, ahbsi, i )
variable v : reg_type;
variable wmask : std_logic_vector(3 downto 0);
variable wr_en : std_logic;
variable cmd_en : std_logic;
variable cmd_instr : std_logic_vector(2 downto 0);
variable rd_en : std_logic;
variable cmd_bl : std_logic_vector(5 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
begin
v := r; wr_en := '0'; cmd_en := '0'; cmd_instr := "000";
rd_en := '0';
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
if ahbsi.htrans(0) = '0' then v.haddr := ahbsi.haddr; end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
hwdata := ahbsi.hwdata(15 downto 0) & ahbsi.hwdata(31 downto 16);
case r.hsize(1 downto 0) is
when "00" => wmask := not decode(r.haddr(1 downto 0));
case r.haddr(1 downto 0) is
when "00" => wmask := "1101";
when "01" => wmask := "1110";
when "10" => wmask := "0111";
when others => wmask := "1011";
end case;
when "01" => wmask := not decode(r.haddr(1 downto 0));
wmask(3) := wmask(2); wmask(1) := wmask(0);
when others => wmask := "0000";
end case;
i.wr_mask <= wmask;
cmd_bl := r.cmd_bl;
case r.bstate is
when idle =>
if v.hsel = '1' then
v.bstate := start;
v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.haddr := ahbsi.haddr;
end if;
v.cmd_bl := (others => '0');
when start =>
if r.hwrite = '1' then
v.haddr := r.haddr;
if r.hready = '1' then
v.cmd_bl := r.cmd_bl + 1; v.hready := '1'; wr_en := '1';
if (ahbsi.htrans /= "11") then
if v.hsel = '1' then
if (ahbsi.hwrite = '0') or (i.wr_count >= "0000100") then
v.hready := '0';
else v.hready := '1'; end if;
else v.bstate := idle; end if;
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
cmd_en := '1';
elsif (i.cmd_full = '1') then
v.hready := '0';
elsif (i.wr_count >= "0101111") then
v.hready := '0'; cmd_en := '1';
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
end if;
else
if (i.cmd_full = '0') and (i.wr_count <= "0001111") then
v.hready := '1';
end if;
end if;
else
if i.cmd_full = '0' then
cmd_en := '1'; cmd_instr(0) := '1';
v.cmd_bl := "000" & not r.haddr(4 downto 2);
cmd_bl := v.cmd_bl;
v.bstate := read1;
end if;
end if;
when read1 =>
v.hready := '0';
if (r.rd_cnt = "000000") then -- flush data from previous line
if (i.rd_empty = '0') or ((r.hready = '1') and (ahbsi.htrans /= "11")) then
v.hrdata(31 downto 0) := i.rd_data(15 downto 0) & i.rd_data(31 downto 16);
v.hready := '1';
if (i.rd_empty = '0') then v.cmd_bl := r.cmd_bl - 1; rd_en := '1'; end if;
if (r.cmd_bl = "000000") or (ahbsi.htrans /= "11") then
if (ahbsi.hsel(hindex) = '1') and (ahbsi.htrans = "10") and (r.hready = '1') then
v.bstate := start; v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.cmd_bl := (others => '0');
else
v.bstate := idle;
end if;
if (i.rd_empty = '1') then v.rd_cnt := r.cmd_bl + 1;
else v.rd_cnt := r.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
readdata := (others => '0');
-- case apbi.paddr(5 downto 2) is
-- when "0000" => readdata(nbits-1 downto 0) := r.din2;
-- when "0001" => readdata(nbits-1 downto 0) := r.dout;
-- when others =>
-- end case;
readdata(20 downto 0) :=
i.rd_error & i.rd_overflow & i.wr_error & i.wr_underrun &
i.cmd_full & i.rd_full & i.rd_empty & i.wr_full & i.wr_empty &
r.rd_cnt & r.cmd_bl;
if (r.rd_cnt /= "000000") and (i.rd_empty = '0') then
rd_en := '1'; v.rd_cnt := r.rd_cnt - 1;
end if;
if rst_n_syn_i = '0' then
v.rd_cnt := "000000"; v.bstate := idle; v.hready := '1';
end if;
rin <= v;
apbo.prdata <= readdata;
i.rd_en <= rd_en;
i.wr_en <= wr_en;
i.cmd_bl <= cmd_bl;
i.cmd_en <= cmd_en;
i.cmd_instr <= cmd_instr;
i.wr_data <= hwdata;
end process;
i.cmd_byte_addr <= r.haddr(29 downto 2) & "00";
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
regs : process(clk_amba_i)
begin
if rising_edge(clk_amba_i) then
r <= rin;
end if;
end process;
port2 : if vgamst /= 0 generate
comb2: process( rst_n_syn_i, r2, ahbmo, p2 )
variable v2 : reg2_type;
variable cmd_en : std_logic;
variable rd_en : std_logic;
begin
v2 := r2; cmd_en := '0'; rd_en := '0';
case r2.bstate is
when idle =>
if ahbmo.htrans(1) = '1' then
v2.bstate := start;
v2.hready := '0';
v2.haddr := ahbmo.haddr;
else v2.hready := '1'; end if;
v2.cmd_bl := (others => '0');
when start =>
if p2.cmd_full = '0' then
cmd_en := '1';
v2.cmd_bl := conv_std_logic_vector(vgaburst-1, 6);
v2.bstate := read1;
end if;
when read1 =>
v2.hready := '0';
if (r2.rd_cnt = "000000") then -- flush data from previous line
if (p2.rd_empty = '0') or ((r2.hready = '1') and (ahbmo.htrans /= "11")) then
v2.hrdata(31 downto 0) := p2.rd_data(15 downto 0) & p2.rd_data(31 downto 16);
v2.hready := '1';
if (p2.rd_empty = '0') then v2.cmd_bl := r2.cmd_bl - 1; rd_en := '1'; end if;
if (r2.cmd_bl = "000000") or (ahbmo.htrans /= "11") then
if (ahbmo.htrans = "10") and (r2.hready = '1') then
v2.bstate := start; v2.hready := '0';
v2.cmd_bl := (others => '0');
else
v2.bstate := idle;
end if;
if (p2.rd_empty = '1') then v2.rd_cnt := r2.cmd_bl + 1;
else v2.rd_cnt := r2.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
if (r2.rd_cnt /= "000000") and (p2.rd_empty = '0') then
rd_en := '1'; v2.rd_cnt := r2.rd_cnt - 1;
end if;
v2.haddr(1 downto 0) := "00";
if rst_n_syn_i = '0' then
v2.rd_cnt := "000000"; v2.bstate := idle; v2.hready := '1';
end if;
r2in <= v2;
p2.rd_en <= rd_en;
p2.cmd_bl <= v2.cmd_bl;
p2.cmd_en <= cmd_en;
p2.cmd_instr <= "001";
end process;
ahbmi.hrdata <= r2.hrdata;
ahbmi.hresp <= "00";
ahbmi.hgrant <= (others => '1');
ahbmi.hready <= r2.hready;
ahbmi.testen <= '0';
ahbmi.testrst <= '0';
ahbmi.scanen <= '0';
ahbmi.testoen <= '0';
ahbmi.hirq <= (others => '0');
ahbmi.testin <= (others => '0');
regs : process(clk_amba_i)
begin
if rising_edge(clk_amba_i) then
r2 <= r2in;
end if;
end process;
end generate;
noport2 : if vgamst = 0 generate
p2.cmd_en <= '0';
p2.rd_en <= '0';
end generate;
MCB_inst : mig_37 generic map(
C3_P0_MASK_SIZE => 4,
C3_P0_DATA_PORT_SIZE => 32,
C3_P1_MASK_SIZE => 4,
C3_P1_DATA_PORT_SIZE => 32,
C3_MEMCLK_PERIOD => 4000,
C3_RST_ACT_LOW => 1,
-- C3_INPUT_CLK_TYPE => "DIFFERENTIAL",
C3_CALIB_SOFT_IP => "TRUE",
-- pragma translate_off
C3_SIMULATION => "TRUE",
-- pragma translate_on
C3_MEM_ADDR_ORDER => "BANK_ROW_COLUMN",
C3_NUM_DQ_PINS => 16,
C3_MEM_ADDR_WIDTH => 13,
C3_MEM_BANKADDR_WIDTH => 3,
C3_CLKOUT5_DIVIDE => clkdiv
-- C3_MC_CALIB_BYPASS => "YES"
)
port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
-- c3_sys_clk_p => clk_mem_p,
-- c3_sys_clk_n => clk_mem_n,
c3_sys_clk => clk_mem_p,
c3_sys_rst_n => rst_n_async,
c3_calib_done => calib_done_i,
c3_clk0 => clk_amba_i,
c3_rst0 => rst_syn,
clk_125 => clk_125,
clk_100 => clk_100,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
c3_p0_cmd_clk => clk_amba_i,
c3_p0_cmd_en => i.cmd_en,
c3_p0_cmd_instr => i.cmd_instr,
c3_p0_cmd_bl => i.cmd_bl,
c3_p0_cmd_byte_addr => i.cmd_byte_addr,
c3_p0_cmd_empty => i.cmd_empty,
c3_p0_cmd_full => i.cmd_full,
c3_p0_wr_clk => clk_amba_i,
c3_p0_wr_en => i.wr_en,
c3_p0_wr_mask => i.wr_mask,
c3_p0_wr_data => i.wr_data,
c3_p0_wr_full => i.wr_full,
c3_p0_wr_empty => i.wr_empty,
c3_p0_wr_count => i.wr_count,
c3_p0_wr_underrun => i.wr_underrun,
c3_p0_wr_error => i.wr_error,
c3_p0_rd_clk => clk_amba_i,
c3_p0_rd_en => i.rd_en,
c3_p0_rd_data => i.rd_data,
c3_p0_rd_full => i.rd_full,
c3_p0_rd_empty => i.rd_empty,
c3_p0_rd_count => i.rd_count,
c3_p0_rd_overflow => i.rd_overflow,
c3_p0_rd_error => i.rd_error,
c3_p2_cmd_clk => clk_amba_i,
c3_p2_cmd_en => p2.cmd_en,
c3_p2_cmd_instr => p2.cmd_instr,
c3_p2_cmd_bl => p2.cmd_bl,
c3_p2_cmd_byte_addr => r2.haddr(29 downto 0),
c3_p2_cmd_empty => p2.cmd_empty,
c3_p2_cmd_full => p2.cmd_full,
c3_p2_rd_clk => clk_amba_i,
c3_p2_rd_en => p2.rd_en,
c3_p2_rd_data => p2.rd_data,
c3_p2_rd_full => p2.rd_full,
c3_p2_rd_empty => p2.rd_empty,
c3_p2_rd_count => p2.rd_count,
c3_p2_rd_overflow => p2.rd_overflow,
c3_p2_rd_error => p2.rd_error
);
end;
|
gpl-2.0
|
8acda1969f5317bec8a0cc7f66190130
| 0.502251 | 3.034682 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/leon3/grfpushwx.vhd
| 4 | 10,156 |
-----------------------------------------------------------------------------
-- Entity: grfpushwx
-- File: grfpushwx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU (shared version) wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.leon3.all;
entity grfpushwx is
generic (mul : integer := 0;
nshare : integer range 0 to 8 := 0;
tech : integer;
arb : integer range 0 to 2 := 1);
port(
clk : in std_logic;
reset : in std_logic;
fpvi : in grfpu_in_vector_type;
fpvo : out grfpu_out_vector_type
);
end;
architecture rtl of grfpushwx is
component grfpushw
generic (mul : integer range 0 to 3 := 0;
nshare : integer range 0 to 8 := 0;
tech : integer;
arb : integer range 0 to 2 := 1);
port(
clk : in std_logic;
reset : in std_logic;
cpu0_start : in std_logic;
cpu0_nonstd : in std_logic;
cpu0_flop : in std_logic_vector(8 downto 0);
cpu0_op1 : in std_logic_vector(63 downto 0);
cpu0_op2 : in std_logic_vector(63 downto 0);
cpu0_opid : in std_logic_vector(7 downto 0);
cpu0_flush : in std_logic;
cpu0_flushid : in std_logic_vector(5 downto 0);
cpu0_rndmode : in std_logic_vector(1 downto 0);
cpu0_req : in std_logic_vector(2 downto 0);
cpu0_res : out std_logic_vector(63 downto 0);
cpu0_exc : out std_logic_vector(5 downto 0);
cpu0_allow : out std_logic_vector(2 downto 0);
cpu0_rdy : out std_logic;
cpu0_cc : out std_logic_vector(1 downto 0);
cpu0_idout : out std_logic_vector(7 downto 0);
cpu1_start : in std_logic;
cpu1_nonstd : in std_logic;
cpu1_flop : in std_logic_vector(8 downto 0);
cpu1_op1 : in std_logic_vector(63 downto 0);
cpu1_op2 : in std_logic_vector(63 downto 0);
cpu1_opid : in std_logic_vector(7 downto 0);
cpu1_flush : in std_logic;
cpu1_flushid : in std_logic_vector(5 downto 0);
cpu1_rndmode : in std_logic_vector(1 downto 0);
cpu1_req : in std_logic_vector(2 downto 0);
cpu1_res : out std_logic_vector(63 downto 0);
cpu1_exc : out std_logic_vector(5 downto 0);
cpu1_allow : out std_logic_vector(2 downto 0);
cpu1_rdy : out std_logic;
cpu1_cc : out std_logic_vector(1 downto 0);
cpu1_idout : out std_logic_vector(7 downto 0);
cpu2_start : in std_logic;
cpu2_nonstd : in std_logic;
cpu2_flop : in std_logic_vector(8 downto 0);
cpu2_op1 : in std_logic_vector(63 downto 0);
cpu2_op2 : in std_logic_vector(63 downto 0);
cpu2_opid : in std_logic_vector(7 downto 0);
cpu2_flush : in std_logic;
cpu2_flushid : in std_logic_vector(5 downto 0);
cpu2_rndmode : in std_logic_vector(1 downto 0);
cpu2_req : in std_logic_vector(2 downto 0);
cpu2_res : out std_logic_vector(63 downto 0);
cpu2_exc : out std_logic_vector(5 downto 0);
cpu2_allow : out std_logic_vector(2 downto 0);
cpu2_rdy : out std_logic;
cpu2_cc : out std_logic_vector(1 downto 0);
cpu2_idout : out std_logic_vector(7 downto 0);
cpu3_start : in std_logic;
cpu3_nonstd : in std_logic;
cpu3_flop : in std_logic_vector(8 downto 0);
cpu3_op1 : in std_logic_vector(63 downto 0);
cpu3_op2 : in std_logic_vector(63 downto 0);
cpu3_opid : in std_logic_vector(7 downto 0);
cpu3_flush : in std_logic;
cpu3_flushid : in std_logic_vector(5 downto 0);
cpu3_rndmode : in std_logic_vector(1 downto 0);
cpu3_req : in std_logic_vector(2 downto 0);
cpu3_res : out std_logic_vector(63 downto 0);
cpu3_exc : out std_logic_vector(5 downto 0);
cpu3_allow : out std_logic_vector(2 downto 0);
cpu3_rdy : out std_logic;
cpu3_cc : out std_logic_vector(1 downto 0);
cpu3_idout : out std_logic_vector(7 downto 0);
cpu4_start : in std_logic;
cpu4_nonstd : in std_logic;
cpu4_flop : in std_logic_vector(8 downto 0);
cpu4_op1 : in std_logic_vector(63 downto 0);
cpu4_op2 : in std_logic_vector(63 downto 0);
cpu4_opid : in std_logic_vector(7 downto 0);
cpu4_flush : in std_logic;
cpu4_flushid : in std_logic_vector(5 downto 0);
cpu4_rndmode : in std_logic_vector(1 downto 0);
cpu4_req : in std_logic_vector(2 downto 0);
cpu4_res : out std_logic_vector(63 downto 0);
cpu4_exc : out std_logic_vector(5 downto 0);
cpu4_allow : out std_logic_vector(2 downto 0);
cpu4_rdy : out std_logic;
cpu4_cc : out std_logic_vector(1 downto 0);
cpu4_idout : out std_logic_vector(7 downto 0);
cpu5_start : in std_logic;
cpu5_nonstd : in std_logic;
cpu5_flop : in std_logic_vector(8 downto 0);
cpu5_op1 : in std_logic_vector(63 downto 0);
cpu5_op2 : in std_logic_vector(63 downto 0);
cpu5_opid : in std_logic_vector(7 downto 0);
cpu5_flush : in std_logic;
cpu5_flushid : in std_logic_vector(5 downto 0);
cpu5_rndmode : in std_logic_vector(1 downto 0);
cpu5_req : in std_logic_vector(2 downto 0);
cpu5_res : out std_logic_vector(63 downto 0);
cpu5_exc : out std_logic_vector(5 downto 0);
cpu5_allow : out std_logic_vector(2 downto 0);
cpu5_rdy : out std_logic;
cpu5_cc : out std_logic_vector(1 downto 0);
cpu5_idout : out std_logic_vector(7 downto 0);
cpu6_start : in std_logic;
cpu6_nonstd : in std_logic;
cpu6_flop : in std_logic_vector(8 downto 0);
cpu6_op1 : in std_logic_vector(63 downto 0);
cpu6_op2 : in std_logic_vector(63 downto 0);
cpu6_opid : in std_logic_vector(7 downto 0);
cpu6_flush : in std_logic;
cpu6_flushid : in std_logic_vector(5 downto 0);
cpu6_rndmode : in std_logic_vector(1 downto 0);
cpu6_req : in std_logic_vector(2 downto 0);
cpu6_res : out std_logic_vector(63 downto 0);
cpu6_exc : out std_logic_vector(5 downto 0);
cpu6_allow : out std_logic_vector(2 downto 0);
cpu6_rdy : out std_logic;
cpu6_cc : out std_logic_vector(1 downto 0);
cpu6_idout : out std_logic_vector(7 downto 0);
cpu7_start : in std_logic;
cpu7_nonstd : in std_logic;
cpu7_flop : in std_logic_vector(8 downto 0);
cpu7_op1 : in std_logic_vector(63 downto 0);
cpu7_op2 : in std_logic_vector(63 downto 0);
cpu7_opid : in std_logic_vector(7 downto 0);
cpu7_flush : in std_logic;
cpu7_flushid : in std_logic_vector(5 downto 0);
cpu7_rndmode : in std_logic_vector(1 downto 0);
cpu7_req : in std_logic_vector(2 downto 0);
cpu7_res : out std_logic_vector(63 downto 0);
cpu7_exc : out std_logic_vector(5 downto 0);
cpu7_allow : out std_logic_vector(2 downto 0);
cpu7_rdy : out std_logic;
cpu7_cc : out std_logic_vector(1 downto 0);
cpu7_idout : out std_logic_vector(7 downto 0)
);
end component;
begin
x0 : grfpushw generic map ((mul mod 4), nshare, tech, arb)
port map (
clk ,
reset ,
fpvi(0).start ,
fpvi(0).nonstd ,
fpvi(0).flop ,
fpvi(0).op1 ,
fpvi(0).op2 ,
fpvi(0).opid ,
fpvi(0).flush ,
fpvi(0).flushid ,
fpvi(0).rndmode ,
fpvi(0).req ,
fpvo(0).res ,
fpvo(0).exc ,
fpvo(0).allow ,
fpvo(0).rdy ,
fpvo(0).cc ,
fpvo(0).idout ,
fpvi(1).start ,
fpvi(1).nonstd ,
fpvi(1).flop ,
fpvi(1).op1 ,
fpvi(1).op2 ,
fpvi(1).opid ,
fpvi(1).flush ,
fpvi(1).flushid ,
fpvi(1).rndmode ,
fpvi(1).req ,
fpvo(1).res ,
fpvo(1).exc ,
fpvo(1).allow ,
fpvo(1).rdy ,
fpvo(1).cc ,
fpvo(1).idout ,
fpvi(2).start ,
fpvi(2).nonstd ,
fpvi(2).flop ,
fpvi(2).op1 ,
fpvi(2).op2 ,
fpvi(2).opid ,
fpvi(2).flush ,
fpvi(2).flushid ,
fpvi(2).rndmode ,
fpvi(2).req ,
fpvo(2).res ,
fpvo(2).exc ,
fpvo(2).allow ,
fpvo(2).rdy ,
fpvo(2).cc ,
fpvo(2).idout ,
fpvi(3).start ,
fpvi(3).nonstd ,
fpvi(3).flop ,
fpvi(3).op1 ,
fpvi(3).op2 ,
fpvi(3).opid ,
fpvi(3).flush ,
fpvi(3).flushid ,
fpvi(3).rndmode ,
fpvi(3).req ,
fpvo(3).res ,
fpvo(3).exc ,
fpvo(3).allow ,
fpvo(3).rdy ,
fpvo(3).cc ,
fpvo(3).idout ,
fpvi(4).start ,
fpvi(4).nonstd ,
fpvi(4).flop ,
fpvi(4).op1 ,
fpvi(4).op2 ,
fpvi(4).opid ,
fpvi(4).flush ,
fpvi(4).flushid ,
fpvi(4).rndmode ,
fpvi(4).req ,
fpvo(4).res ,
fpvo(4).exc ,
fpvo(4).allow ,
fpvo(4).rdy ,
fpvo(4).cc ,
fpvo(4).idout ,
fpvi(5).start ,
fpvi(5).nonstd ,
fpvi(5).flop ,
fpvi(5).op1 ,
fpvi(5).op2 ,
fpvi(5).opid ,
fpvi(5).flush ,
fpvi(5).flushid ,
fpvi(5).rndmode ,
fpvi(5).req ,
fpvo(5).res ,
fpvo(5).exc ,
fpvo(5).allow ,
fpvo(5).rdy ,
fpvo(5).cc ,
fpvo(5).idout ,
fpvi(6).start ,
fpvi(6).nonstd ,
fpvi(6).flop ,
fpvi(6).op1 ,
fpvi(6).op2 ,
fpvi(6).opid ,
fpvi(6).flush ,
fpvi(6).flushid ,
fpvi(6).rndmode ,
fpvi(6).req ,
fpvo(6).res ,
fpvo(6).exc ,
fpvo(6).allow ,
fpvo(6).rdy ,
fpvo(6).cc ,
fpvo(6).idout ,
fpvi(7).start ,
fpvi(7).nonstd ,
fpvi(7).flop ,
fpvi(7).op1 ,
fpvi(7).op2 ,
fpvi(7).opid ,
fpvi(7).flush ,
fpvi(7).flushid ,
fpvi(7).rndmode ,
fpvi(7).req ,
fpvo(7).res ,
fpvo(7).exc ,
fpvo(7).allow ,
fpvo(7).rdy ,
fpvo(7).cc ,
fpvo(7).idout);
end;
|
gpl-2.0
|
e068b19b17dd1e8808ebcb698765f61c
| 0.544998 | 2.952326 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/designs/leon3-altera-c5ekit/testbench.vhd
| 1 | 19,744 |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- Clock and reset
diff_clkin_top_125_p: in std_ulogic;
diff_clkin_bot_125_p: in std_ulogic;
clkin_50_fpga_right: in std_ulogic;
clkin_50_fpga_top: in std_ulogic;
clkout_sma: out std_ulogic;
cpu_resetn: in std_ulogic;
-- DDR3
ddr3_ck_p: out std_ulogic;
ddr3_ck_n: out std_ulogic;
ddr3_cke: out std_ulogic;
ddr3_rstn: out std_ulogic;
ddr3_csn: out std_ulogic;
ddr3_rasn: out std_ulogic;
ddr3_casn: out std_ulogic;
ddr3_wen: out std_ulogic;
ddr3_ba: out std_logic_vector(2 downto 0);
ddr3_a : out std_logic_vector(13 downto 0);
ddr3_dqs_p: inout std_logic_vector(3 downto 0);
ddr3_dqs_n: inout std_logic_vector(3 downto 0);
ddr3_dq: inout std_logic_vector(31 downto 0);
ddr3_dm: out std_logic_vector(3 downto 0);
ddr3_odt: out std_ulogic;
ddr3_oct_rzq: in std_ulogic;
-- LPDDR2
lpddr2_ck_p: out std_ulogic;
lpddr2_ck_n: out std_ulogic;
lpddr2_cke: out std_ulogic;
lpddr2_a: out std_logic_vector(9 downto 0);
lpddr2_dqs_p: inout std_logic_vector(1 downto 0);
lpddr2_dqs_n: inout std_logic_vector(1 downto 0);
lpddr2_dq: inout std_logic_vector(15 downto 0);
lpddr2_dm: out std_logic_vector(1 downto 0);
lpddr2_csn: out std_ulogic;
lpddr2_oct_rzq: in std_ulogic;
-- Flash and SSRAM interface
fm_a: out std_logic_vector(26 downto 1);
fm_d: in std_logic_vector(15 downto 0);
flash_clk: out std_ulogic;
flash_resetn: out std_ulogic;
flash_cen: out std_ulogic;
flash_advn: out std_ulogic;
flash_wen: out std_ulogic;
flash_oen: out std_ulogic;
flash_rdybsyn: in std_ulogic;
ssram_clk: out std_ulogic;
ssram_oen: out std_ulogic;
sram_cen: out std_ulogic;
ssram_bwen: out std_ulogic;
ssram_bwan: out std_ulogic;
ssram_bwbn: out std_ulogic;
ssram_adscn: out std_ulogic;
ssram_adspn: out std_ulogic;
ssram_zzn: out std_ulogic; -- Name incorrect, this is active high
ssram_advn: out std_ulogic;
-- EEPROM
eeprom_scl : out std_ulogic;
eeprom_sda : inout std_ulogic;
-- UART
uart_rxd : in std_ulogic;
uart_rts : in std_ulogic; -- Note CTS and RTS mixed up on PCB
uart_txd : out std_ulogic;
uart_cts : out std_ulogic;
-- USB UART Interface
usb_uart_rstn : in std_ulogic; -- inout
usb_uart_ri : in std_ulogic;
usb_uart_dcd : in std_ulogic;
usb_uart_dtr : out std_ulogic;
usb_uart_dsr : in std_ulogic;
usb_uart_txd : out std_ulogic;
usb_uart_rxd : in std_ulogic;
usb_uart_rts : in std_ulogic;
usb_uart_cts : out std_ulogic;
usb_uart_gpio2 : in std_ulogic;
usb_uart_suspend : in std_ulogic;
usb_uart_suspendn : in std_ulogic;
-- Ethernet port A
eneta_rx_clk: in std_ulogic;
eneta_tx_clk: in std_ulogic;
eneta_intn: in std_ulogic;
eneta_resetn: out std_ulogic;
eneta_mdio: inout std_ulogic;
eneta_mdc: out std_ulogic;
eneta_rx_er: in std_ulogic;
eneta_tx_er: out std_ulogic;
eneta_rx_col: in std_ulogic;
eneta_rx_crs: in std_ulogic;
eneta_tx_d: out std_logic_vector(3 downto 0);
eneta_rx_d: in std_logic_vector(3 downto 0);
eneta_gtx_clk: out std_ulogic;
eneta_tx_en: out std_ulogic;
eneta_rx_dv: in std_ulogic;
-- Ethernet port B
enetb_rx_clk: in std_ulogic;
enetb_tx_clk: in std_ulogic;
enetb_intn: in std_ulogic;
enetb_resetn: out std_ulogic;
enetb_mdio: inout std_ulogic;
enetb_mdc: out std_ulogic;
enetb_rx_er: in std_ulogic;
enetb_tx_er: out std_ulogic;
enetb_rx_col: in std_ulogic;
enetb_rx_crs: in std_ulogic;
enetb_tx_d: out std_logic_vector(3 downto 0);
enetb_rx_d: in std_logic_vector(3 downto 0);
enetb_gtx_clk: out std_ulogic;
enetb_tx_en: out std_ulogic;
enetb_rx_dv: in std_ulogic;
-- LEDs, switches, GPIO
user_led : out std_logic_vector(3 downto 0);
user_dipsw : in std_logic_vector(3 downto 0);
dip_3p3V : in std_ulogic;
user_pb : in std_logic_vector(3 downto 0);
overtemp_fpga : out std_ulogic;
header_p : in std_logic_vector(5 downto 0); -- inout
header_n : in std_logic_vector(5 downto 0); -- inout
header_d : in std_logic_vector(7 downto 0); -- inout
-- LCD
lcd_data : in std_logic_vector(7 downto 0); -- inout
lcd_wen : out std_ulogic;
lcd_csn : out std_ulogic;
lcd_d_cn : out std_ulogic;
-- HIGH-SPEED-MEZZANINE-CARD Interface
-- hsmc_clk_in0: in std_ulogic;
-- hsmc_clk_out0: out std_ulogic;
-- hsmc_clk_in_p: in std_logic_vector(2 downto 1);
-- hsmc_clk_out_p: out std_logic_vector(2 downto 1);
-- hsmc_d: in std_logic_vector(3 downto 0); -- inout
-- hsmc_tx_d_p: out std_logic_vector(16 downto 0);
-- hsmc_rx_d_p: in std_logic_vector(16 downto 0);
-- hsmc_rx_led: out std_ulogic;
-- hsmc_tx_led: out std_ulogic;
-- hsmc_scl: out std_ulogic;
-- hsmc_sda: in std_ulogic; -- inout
-- hsmc_prsntn: in std_ulogic;
-- MAX V CPLD interface
max5_csn: out std_ulogic;
max5_wen: out std_ulogic;
max5_oen: out std_ulogic;
max5_ben: out std_logic_vector(3 downto 0);
max5_clk: out std_ulogic;
-- USB Blaster II
usb_clk : in std_ulogic;
usb_data : in std_logic_vector(7 downto 0); -- inout
usb_addr : in std_logic_vector(1 downto 0); -- inout
usb_scl : in std_ulogic; -- inout
usb_sda : in std_ulogic; -- inout
usb_resetn : in std_ulogic;
usb_oen : in std_ulogic;
usb_rdn : in std_ulogic;
usb_wrn : in std_ulogic;
usb_full : out std_ulogic;
usb_empty : out std_ulogic;
fx2_resetn : in std_ulogic
);
end component;
signal clk125, clk50, clkout: std_ulogic := '0';
signal rst: std_ulogic;
signal user_led: std_logic_vector(3 downto 0);
signal address : std_logic_vector(26 downto 1);
signal data : std_logic_vector(15 downto 0);
signal ramsn : std_ulogic;
signal ramoen : std_ulogic;
signal rwen : std_ulogic;
signal mben : std_logic_vector(3 downto 0);
--signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
--signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(7 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
constant lresp : boolean := false;
signal eneta_rx_clk, eneta_tx_clk, enetb_rx_clk, enetb_tx_clk: std_ulogic;
signal eneta_intn, eneta_resetn, enetb_intn, enetb_resetn: std_ulogic;
signal eneta_mdio, enetb_mdio: std_logic;
signal eneta_mdc, enetb_mdc: std_ulogic;
signal eneta_rx_er, eneta_rx_col, eneta_rx_crs, eneta_rx_dv: std_ulogic;
signal enetb_rx_er, enetb_rx_col, enetb_rx_crs, enetb_rx_dv: std_ulogic;
signal eneta_rx_d, enetb_rx_d: std_logic_vector(7 downto 0);
signal eneta_tx_d, enetb_tx_d: std_logic_vector(7 downto 0);
signal eneta_tx_en, eneta_tx_er, enetb_tx_en, enetb_tx_er: std_ulogic;
signal lpddr2_ck, lpddr2_ck_n, lpddr2_cke, lpddr2_cs_n: std_ulogic;
signal lpddr2_ca: std_logic_vector(9 downto 0);
signal lpddr2_dm, lpddr2_dqs, lpddr2_dqs_n: std_logic_vector(3 downto 0);
signal lpddr2_dq: std_logic_vector(31 downto 0);
begin
-- clock and reset
clk125 <= not clk125 after 4 ns;
clk50 <= not clk50 after 10 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
d3 : leon3mp
generic map ( fabtech, memtech, padtech, disas, dbguart, pclow )
port map (
-- Clock and reset
diff_clkin_top_125_p => clk125,
diff_clkin_bot_125_p => clk125,
clkin_50_fpga_right => clk50,
clkin_50_fpga_top => clk50,
clkout_sma => clkout,
cpu_resetn => rst,
-- DDR3
ddr3_ck_p => open,
ddr3_ck_n => open,
ddr3_cke => open,
ddr3_rstn => open,
ddr3_csn => open,
ddr3_rasn => open,
ddr3_casn => open,
ddr3_wen => open,
ddr3_ba => open,
ddr3_a => open,
ddr3_dqs_p => open,
ddr3_dqs_n => open,
ddr3_dq => open,
ddr3_dm => open,
ddr3_odt => open,
ddr3_oct_rzq => '0',
-- LPDDR2
lpddr2_ck_p => lpddr2_ck,
lpddr2_ck_n => lpddr2_ck_n,
lpddr2_cke => lpddr2_cke,
lpddr2_a => lpddr2_ca,
lpddr2_dqs_p => lpddr2_dqs(1 downto 0),
lpddr2_dqs_n => lpddr2_dqs_n(1 downto 0),
lpddr2_dq => lpddr2_dq(15 downto 0),
lpddr2_dm => lpddr2_dm(1 downto 0),
lpddr2_csn => lpddr2_cs_n,
lpddr2_oct_rzq => '0',
-- Flash and SSRAM interface
fm_a => address(26 downto 1),
fm_d => data,
flash_clk => open,
flash_resetn => open,
flash_cen => romsn,
flash_advn => open,
flash_wen => rwen,
flash_oen => oen,
flash_rdybsyn => '1',
ssram_clk => open,
ssram_oen => open,
sram_cen => open,
ssram_bwen => open,
ssram_bwan => open,
ssram_bwbn => open,
ssram_adscn => open,
ssram_adspn => open,
ssram_zzn => open,
ssram_advn => open,
-- EEPROM
eeprom_scl => open,
eeprom_sda => open,
-- UART
uart_rxd => rxd1,
uart_rts => '1',
uart_txd => txd1,
uart_cts => open,
-- USB UART Interface
usb_uart_rstn => '1',
usb_uart_ri => '0',
usb_uart_dcd => '1',
usb_uart_dtr => open,
usb_uart_dsr => '1',
usb_uart_txd => open,
usb_uart_rxd => '1',
usb_uart_rts => '1',
usb_uart_cts => open,
usb_uart_gpio2 => '0',
usb_uart_suspend => '0',
usb_uart_suspendn => '1',
-- Ethernet port A
eneta_rx_clk => eneta_rx_clk,
eneta_tx_clk => eneta_tx_clk,
eneta_intn => eneta_intn,
eneta_resetn => eneta_resetn,
eneta_mdio => eneta_mdio,
eneta_mdc => eneta_mdc,
eneta_rx_er => eneta_rx_er,
eneta_tx_er => eneta_tx_er,
eneta_rx_col => eneta_rx_col,
eneta_rx_crs => eneta_rx_crs,
eneta_tx_d => eneta_tx_d(3 downto 0),
eneta_rx_d => eneta_rx_d(3 downto 0),
eneta_gtx_clk => open,
eneta_tx_en => eneta_tx_en,
eneta_rx_dv => eneta_rx_dv,
-- Ethernet port B
enetb_rx_clk => enetb_rx_clk,
enetb_tx_clk => enetb_tx_clk,
enetb_intn => enetb_intn,
enetb_resetn => enetb_resetn,
enetb_mdio => enetb_mdio,
enetb_mdc => enetb_mdc,
enetb_rx_er => enetb_rx_er,
enetb_tx_er => enetb_tx_er,
enetb_rx_col => enetb_rx_col,
enetb_rx_crs => enetb_rx_crs,
enetb_tx_d => enetb_tx_d(3 downto 0),
enetb_rx_d => enetb_rx_d(3 downto 0),
enetb_gtx_clk => open,
enetb_tx_en => enetb_tx_en,
enetb_rx_dv => enetb_rx_dv,
-- LEDs, switches, GPIO
user_led => user_led,
user_dipsw => "1111",
dip_3p3V => '0',
user_pb => "0000",
overtemp_fpga => open,
header_p => "000000",
header_n => "000000",
header_d => "00000000",
-- LCD
lcd_data => "00000000",
lcd_wen => open,
lcd_csn => open,
lcd_d_cn => open,
-- HIGH-SPEED-MEZZANINE-CARD Interface
-- hsmc_clk_in0 => '0',
-- hsmc_clk_out0 => open,
-- hsmc_clk_in_p => "00",
-- hsmc_clk_out_p => open,
-- hsmc_d => "0000",
-- hsmc_tx_d_p => open,
-- hsmc_rx_d_p => (others => '0'),
-- hsmc_rx_led => open,
-- hsmc_tx_led => open,
-- hsmc_scl => open,
-- hsmc_sda => '0',
-- hsmc_prsntn => '0',
-- MAX V CPLD interface
max5_csn => open,
max5_wen => open,
max5_oen => open,
max5_ben => open,
max5_clk => open,
-- USB Blaster II
usb_clk => '0',
usb_data => (others => '0'),
usb_addr => "00",
usb_scl => '0',
usb_sda => '0',
usb_resetn => '0',
usb_oen => '0',
usb_rdn => '0',
usb_wrn => '0',
usb_full => open,
usb_empty => open,
fx2_resetn => '1'
);
-- 16 bit prom
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data,
romsn, romsn, romsn, rwen, oen);
-- ROMSN is pulled down by the MAX V system controller after FPGA programming
-- completed (bug?)
romsn <= 'L';
data <= buskeep(data), (others => 'H') after 250 ns;
error <= user_led(3);
eneta_mdio <= 'H';
enetb_mdio <= 'H';
eneta_tx_d(7 downto 4) <= "0000";
enetb_tx_d(7 downto 4) <= "0000";
p1: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 0)
port map(rst, eneta_mdio, eneta_tx_clk, eneta_rx_clk, eneta_rx_d, eneta_rx_dv,
eneta_rx_er, eneta_rx_col, eneta_rx_crs, eneta_tx_d, eneta_tx_en, eneta_tx_er, eneta_mdc,
'0');
p2: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 1)
port map(rst, enetb_mdio, enetb_tx_clk, enetb_rx_clk, enetb_rx_d, enetb_rx_dv,
enetb_rx_er, enetb_rx_col, enetb_rx_crs, enetb_tx_d, enetb_tx_en, enetb_tx_er, enetb_mdc,
'0');
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod generic map (width => 16)
port map ( rst, clk50, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
gpl-2.0
|
8cb6be382d070bfff14efea0f80bc413
| 0.572528 | 3.015732 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/techmap/maps/outpad.vhd
| 1 | 5,956 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: outpad
-- File: outpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity outpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of outpad is
signal padx, gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
gen0 : if has_pads(tech) = 0 generate
pad <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when slew = 0 else i;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
igl2 : if (tech = igloo2) generate
x0 : igloo2_outpad port map (pad, i);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
um : if (tech = umc) generate
x0 : umc_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
saed : if (tech = saed32) generate
x0 : saed32_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
rhs : if (tech = rhs65) generate
x0 : rhs65_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
dar : if (tech = dare) generate
x0 : dare_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
ihprh : if (tech = ihp25rh) generate
x0 : ihp25rh_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength) port map (padx, i, gnd, open);
pad <= padx;
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, vcc);
end generate;
nex : if (tech = easic90) generate
x0 : nextreme_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, vcc);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_outpad generic map (level, slew, voltage, strength)
port map(pad, i, cfgi(0), cfgi(1),
cfgi(19 downto 15), cfgi(14 downto 10), cfgi(9 downto 6), cfgi(5 downto 2));
end generate;
ut90nhbd : if (tech = ut90) generate
x0 : ut90nhbd_outpad generic map (level, slew, voltage, strength)
port map(pad, i, cfgi(0));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity outpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12; width : integer := 1);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of outpadv is
begin
v : for j in width-1 downto 0 generate
x0 : outpad generic map (tech, level, slew, voltage, strength)
port map (pad(j), i(j), cfgi);
end generate;
end;
|
gpl-2.0
|
633fd07b9aa3d82437849f4471455131
| 0.643721 | 3.534718 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/leon3v3/mmu_acache.vhd
| 1 | 14,327 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_acache
-- File: mmu_acache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Interface module between (MMU,I/D cache controllers) and Amba AHB
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.leon3.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmu_acache is
generic (
hindex : integer range 0 to NAHBMST-1 := 0;
ilinesize : integer range 4 to 8 := 4;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mcii : in memory_ic_in_type;
mcio : out memory_ic_out_type;
mcdi : in memory_dc_in_type;
mcdo : out memory_dc_out_type;
mcmmi : in memory_mm_in_type;
mcmmo : out memory_mm_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbso : in ahb_slv_out_vector;
hclken : in std_ulogic
);
end;
architecture rtl of mmu_acache is
type reg_type is record -- cache control register type
bg : std_logic; -- bus grant
bo : std_logic_vector(1 downto 0); -- bus owner
ba : std_logic; -- bus active
lb : std_ulogic; -- last burst cycle
retry : std_logic; -- retry/split pending
retry2 : std_ulogic; -- retry/split pending
werr : std_logic; -- write error
hlocken : std_ulogic; -- ready to perform locked transaction
hcache : std_logic; -- cacheable access
nba : std_ulogic;
nbo : std_logic_vector(1 downto 0); -- bus owner
end record;
type reg2_type is record
reqmsk : std_logic_vector(2 downto 0);
hclken2 : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : reg_type := (
bg => '0',
bo => (others => '0'),
ba => '0',
lb => '0',
retry => '0',
retry2 => '0',
werr => '0',
hlocken => '0',
hcache => '0',
nba => '0',
nbo => (others => '0')
);
constant R2RES : reg2_type := (
reqmsk => (others => '0'), hclken2 => '0'
);
constant L3DI :integer := GAISLER_LEON3
;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, L3DI, 0, LEON3_VERSION, 0),
others => zero32);
constant ctbl : std_logic_vector(15 downto 0) := conv_std_logic_vector(cached, 16);
function dec_fixed(haddr : std_logic_vector(3 downto 0);
cached : integer)
return std_ulogic is
begin
if (cached /= 0) then return ctbl(conv_integer(haddr(3 downto 0)));
else return('1'); end if;
end;
signal r, rin : reg_type;
signal r2, r2in : reg2_type;
begin
comb : process(ahbi, r, rst, mcii, mcdi, mcmmi, ahbso, hclken, r2)
variable v : reg_type;
variable v2 : reg2_type;
variable haddr : std_logic_vector(31 downto 0); -- address bus
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_logic; -- read/write
variable hlock : std_logic; -- bus lock
variable hsize : std_logic_vector(2 downto 0); -- transfer size
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable hwdata : std_logic_vector(31 downto 0); -- write data
variable hbusreq : std_logic; -- bus request
variable iready, dready, mmready : std_logic;
variable igrant, dgrant, mmgrant : std_logic;
variable iretry, dretry, mmretry : std_logic;
variable ihcache, dhcache, mmhcache, dec_hcache : std_logic;
variable imexc, dmexc, mmmexc : std_logic;
variable dreq : std_logic;
variable nbo : std_logic_vector(1 downto 0);
variable su, nb, bo_icache : std_ulogic;
variable scanen : std_ulogic;
variable vreqmsk: std_ulogic;
variable burst : std_ulogic;
begin
-- initialisation
htrans := HTRANS_IDLE;
v := r; v.werr := '0'; v2 := r2;
iready := '0'; dready := '0'; mmready := '0';
igrant := '0'; dgrant := '0'; mmgrant := '0';
imexc := '0'; dmexc := '0'; mmmexc := '0'; hlock := '0';
iretry := '0'; dretry := '0'; mmretry := '0';
ihcache := '0'; dhcache := '0'; mmhcache := '0'; su := '0';
if (r.bo = "00") then bo_icache := '1'; else bo_icache := '0'; end if;
haddr := (others => '0');
hwrite := '0';
hsize := (others => '0');
hlock := '0';
hburst := (others => '0');
if ahbi.hready = '1' then v.lb := '0'; end if;
v.retry2 := (r.retry or r.retry2) and not (r.ba and not r.retry);
vreqmsk := orv(r2.reqmsk);
-- generate AHB signals
dreq := mcdi.req;
hwdata := mcdi.data;
hbusreq := '0';
if (mcii.req = '1') and ((clk2x = 0) or (r2.reqmsk(2) = '1')) and (r.hlocken = '0') and
not (( ((r.ba and dreq) = '1') and (r.bo = "01")) or
( ((r.ba and mcmmi.req) = '1') and (r.bo = "10"))) then
nbo := "00";
hbusreq := '1'; burst := mcii.burst;
htrans := HTRANS_NONSEQ;
elsif (dreq = '1') and ((clk2x = 0) or (r2.reqmsk(1) = '1')) and
not (( ((r.ba and mcii.req) = '1') and (r.bo = "00")) or
( ((r.ba and mcmmi.req) = '1') and (r.bo = "10"))) then
nbo := "01";
hbusreq := '1'; burst := mcdi.burst;
if (not mcdi.lock or r.hlocken) = '1' then htrans := HTRANS_NONSEQ; end if;
elsif (mcmmi.req = '1') and ((clk2x = 0) or (r2.reqmsk(0) = '1')) and (r.hlocken = '0') and
not (( ((r.ba and mcii.req) = '1') and (r.bo = "00")) or
( ((r.ba and dreq) = '1') and (r.bo = "01"))) then
nbo := "10";
hbusreq := '1'; burst := '0';
htrans := HTRANS_NONSEQ;
else
nbo := "11"; burst := '0';
end if;
-- dont change bus master if we have started driving htrans
if r.nba = '1' then
nbo := r.nbo; hbusreq := '1'; htrans := HTRANS_NONSEQ;
end if;
-- dont change bus master on retry
if (r.retry2 and not r.ba) = '1' then
nbo := r.bo; hbusreq := '1'; htrans := HTRANS_NONSEQ;
end if;
dec_hcache := ahb_slv_dec_cache(mcdi.address, ahbso, cached);
if nbo = "10" then
haddr := mcmmi.address; hwrite := not mcmmi.read; hsize := '0' & mcmmi.size;
hlock := mcmmi.lock;
htrans := HTRANS_NONSEQ; hburst := HBURST_SINGLE;
if (mcmmi.req and r.bg and ahbi.hready and not r.retry) = '1'
then mmgrant := '1'; v.hcache := dec_fixed(haddr(31 downto 28), cached); end if;
elsif nbo = "00" then
haddr := mcii.address; hwrite := '0'; hsize := HSIZE_WORD; hlock := '0';
su := mcii.su;
if ((mcii.req and r.ba) = '1') and (r.bo = "00") and ((not r.retry) = '1') then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
if (((ilinesize = 4) and haddr(3 downto 2) = "10")
or ((ilinesize = 8) and haddr(4 downto 2) = "110")) and (ahbi.hready = '1')
then v.lb := '1'; end if;
end if;
if mcii.burst = '1' then hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if (mcii.req and r.bg and ahbi.hready and not r.retry) = '1'
then igrant := '1'; v.hcache := dec_fixed(haddr(31 downto 28), cached); end if;
elsif nbo = "01" then
haddr := mcdi.address; hwrite := not mcdi.read; hsize := '0' & mcdi.size;
hlock := mcdi.lock;
if mcdi.asi /= "1010" then su := '1'; else su := '0'; end if; --ASI_UDATA
if mcdi.burst = '1' then hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if ((dreq and r.ba) = '1') and (r.bo = "01") and ((not r.retry) = '1') then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
hburst := HBURST_INCR;
end if;
if (dreq and r.bg and ahbi.hready and not r.retry) = '1' then
dgrant := (not mcdi.lock or r.hlocken) or (r.retry2 and (not r.bo(1) and r.bo(0)));
v.hcache := dec_hcache;
end if;
end if;
if (hclken = '1') or (clk2x = 0) then
if (r.ba = '1') and ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT))
then v.retry := not ahbi.hready; else v.retry := '0'; end if;
end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if r.bo = "10" then
hwdata := mcmmi.data;
if r.ba = '1' then
mmhcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => mmready := '1';
when HRESP_RETRY | HRESP_SPLIT=> mmretry := '1';
when others => mmready := '1'; mmmexc := '1'; v.werr := not mcmmi.read;
end case;
end if;
end if;
elsif r.bo = "00" then
if r.ba = '1' then
ihcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => iready := '1';
when HRESP_RETRY | HRESP_SPLIT=> iretry := '1';
when others => iready := '1'; imexc := '1';
end case;
end if;
end if;
elsif r.bo = "01" then
if r.ba = '1' then
dhcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => dready := '1';
when HRESP_RETRY | HRESP_SPLIT=> dretry := '1';
when others => dready := '1'; dmexc := '1'; v.werr := not mcdi.read;
end case;
end if;
end if;
hlock := mcdi.lock or ((r.retry or (r.retry2 and not r.ba)) and r.hlocken);
end if;
if nbo = "01" and ((hsize = "011") or ((mcdi.read and mcdi.cache) = '1')) then
hsize := "010";
end if;
if (r.bo = "01") and (hlock = '1') then nbo := "01"; end if;
if ahbi.hready = '1' then
if r.retry = '0' then v.bo := nbo; end if;
v.bg := ahbi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else v.ba := '0'; end if;
v.hlocken := hlock and ahbi.hgrant(hindex);
if (clk2x /= 0) then
igrant := igrant and vreqmsk;
dgrant := dgrant and vreqmsk;
mmgrant := mmgrant and vreqmsk;
if (r.bo = nbo) then v.ba := v.ba and vreqmsk; end if;
end if;
end if;
if hburst = HBURST_SINGLE then nb := '1'; else nb := '0'; end if;
v.nbo := nbo; v.nba := orv(htrans) and not v.ba;
-- parity generation
if (clk2x /= 0) then
v2.hclken2 := hclken;
if hclken = '1' then
v2.reqmsk := mcii.req & mcdi.req & mcmmi.req;
if (clk2x > 8) and (r2.hclken2 = '1') then v2.reqmsk := "111"; end if;
end if;
end if;
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.bg := '0'; v.bo := "00"; v.ba := '0'; v.retry := '0'; v.werr := '0'; v.lb := '0';
v.hcache := '0'; v.hlocken := '0'; v.nba := '0'; v.nbo := "00";
v.retry2 := '0';
end if;
-- drive ports
ahbo.haddr <= haddr ;
ahbo.htrans <= htrans;
-- ahbo.hbusreq <= hbusreq and not r.lb and not ((((not bo_icache) and r.ba) or nb) and r.bg);
-- ahbo.hbusreq <= hbusreq and not r.lb and not((not burst) and r.bg);
ahbo.hbusreq <= hbusreq and (not r.lb or orv(nbo)) and (burst or not r.bg);
ahbo.hwdata <= ahbdrivedata(hwdata);
ahbo.hlock <= hlock;
ahbo.hwrite <= hwrite;
ahbo.hsize <= hsize;
ahbo.hburst <= hburst;
ahbo.hindex <= hindex;
if nbo = "00" then ahbo.hprot <= "11" & su & '0';
else ahbo.hprot <= "11" & su & '1'; end if;
mcio.grant <= igrant;
mcio.ready <= iready;
mcio.mexc <= imexc;
mcio.retry <= iretry;
mcio.cache <= ihcache;
mcdo.grant <= dgrant;
mcdo.ready <= dready;
mcdo.mexc <= dmexc;
mcdo.retry <= dretry;
mcdo.werr <= r.werr;
mcdo.cache <= dhcache;
mcdo.ba <= r.ba;
mcdo.bg <= r.bg and not v.bo(1);
mcmmo.grant <= mmgrant;
mcmmo.ready <= mmready;
mcmmo.mexc <= mmmexc;
mcmmo.retry <= mmretry;
mcmmo.werr <= r.werr;
mcmmo.cache <= mmhcache;
rin <= v; r2in <= v2;
end process;
mcio.data <= ahbreadword(ahbi.hrdata);
mcdo.data <= ahbreadword(ahbi.hrdata);
mcmmo.data <= ahbreadword(ahbi.hrdata);
ahbo.hirq <= (others => '0');
ahbo.hconfig <= hconfig;
reg : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and (rst = '0') then r <= RRES; end if;
end if;
end process;
reg2gen : if (clk2x /= 0) generate
reg2 : process(clk)
begin
if rising_edge(clk) then
r2 <= r2in;
if RESET_ALL and (rst = '0') then r2 <= R2RES; end if;
end if;
end process;
end generate;
noreg2gen : if (clk2x = 0) generate
r2.reqmsk <= "000";
end generate;
end;
|
gpl-2.0
|
92f731d85e0308cd3a461df0927b6721
| 0.535911 | 3.317203 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/srmmu/mmulrue.vhd
| 1 | 3,779 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmulrue
-- File: mmulrue.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU LRU logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmulrue is
generic (
position : integer;
entries : integer := 8 );
port (
rst : in std_logic;
clk : in std_logic;
lruei : in mmulrue_in_type;
lrueo : out mmulrue_out_type );
end mmulrue;
architecture rtl of mmulrue is
constant entries_log : integer := log2(entries);
type lru_rtype is record
pos : std_logic_vector(entries_log-1 downto 0);
movetop : std_logic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
signal c,r : lru_rtype;
begin
p0: process (rst, r, lruei)
variable v : lru_rtype;
variable ov : mmulrue_out_type;
begin
v := r; ov := mmulrue_out_none;
-- #init
if (r.movetop) = '1' then
if (lruei.fromleft) = '0' then
v.pos := lruei.left(entries_log-1 downto 0);
v.movetop := '0';
end if;
elsif (lruei.fromright) = '1' then
v.pos := lruei.right(entries_log-1 downto 0);
v.movetop := not lruei.clear;
end if;
if (lruei.touch and not lruei.clear) = '1' then -- touch request
if (v.pos = lruei.pos(entries_log-1 downto 0)) then -- check
v.movetop := '1';
end if;
end if;
if ((not ASYNC_RESET) and (not RESET_ALL) and (rst = '0')) or (lruei.flush = '1') then
v.pos := conv_std_logic_vector(position, entries_log);
v.movetop := '0';
end if;
--# Drive signals
ov.pos(entries_log-1 downto 0) := r.pos;
ov.movetop := r.movetop;
lrueo <= ov;
c <= v;
end process p0;
syncrregs : if not ASYNC_RESET generate
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r.pos <= conv_std_logic_vector(position, entries_log);
r.movetop <= '0';
end if;
end if;
end process p1;
end generate;
asyncrregs : if ASYNC_RESET generate
p1: process (clk, rst)
begin
if rst = '0' then
r.pos <= conv_std_logic_vector(position, entries_log);
r.movetop <= '0';
elsif rising_edge(clk) then
r <= c;
end if;
end process p1;
end generate;
end rtl;
|
gpl-2.0
|
bc8e510432b6786e1820253b228f0fbc
| 0.591162 | 3.630163 | false | false | false | false |
elkhadiy/xph-leons
|
grlib-gpl-1.4.1-b4156/lib/gaisler/jtag/jtag.vhd
| 1 | 6,810 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: jtag
-- File: jtag.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package jtag is
-- JTAG manufacturer IDs
constant JTAG_MANF_ID_GR : integer range 0 to 2047 := 804;
-- JTAG part numbers
-- Do NOT select an existing part number for your custom design!
--
-- For your design, please select a JTAG ID that starts with 16#a--#
-- and notify Aeroflex Gaisler (in case do not change the manufacturer
-- ID to your own ID).
constant JTAG_EXAMPLE_PART : integer range 0 to 65535 := 16#300#;
component ahbjtag
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3;
scantest : integer := 0;
oepol : integer := 1;
tcknen : integer := 0;
versel : integer range 0 to 1 := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapi_tdo : in std_ulogic;
trst : in std_ulogic := '1';
tdoen : out std_ulogic;
tckn : in std_ulogic := '0';
tapo_tckn : out std_ulogic;
tapo_ninst : out std_logic_vector(7 downto 0);
tapo_iupd : out std_ulogic
);
end component;
component ahbjtag_bsd
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
asel : in std_ulogic;
dsel : in std_ulogic;
tck : in std_ulogic;
regi : in std_ulogic;
shift : in std_ulogic;
rego : out std_ulogic
);
end component;
component bscanctrl
generic (
spinst: integer := 5; -- sample/preload
etinst: integer := 6; -- extest
itinst: integer := 7; --intest
hzinst: integer := 8; -- highz
clinst: integer := 10; -- clamp
mbist : integer := 11; -- mbist
testx1: integer := 12; -- generic test command
scantest : integer := 0
);
port (
trst : in std_ulogic;
tapo_tck : in std_ulogic;
tapo_tckn : in std_ulogic;
tapo_tdi : in std_ulogic;
tapo_ninst : in std_logic_vector(7 downto 0);
tapo_iupd : in std_ulogic;
tapo_rst : in std_ulogic;
tapo_capt : in std_ulogic;
tapo_shft : in std_ulogic;
tapo_upd : in std_ulogic;
tapi_tdo : out std_ulogic;
chain_tdi : out std_ulogic;
chain_tdo : in std_ulogic;
bsshft : out std_ulogic;
bscapt : out std_ulogic;
bsupdi : out std_ulogic;
bsupdo : out std_ulogic;
bsdrive : out std_ulogic;
bshighz : out std_ulogic;
bsmbist : out std_ulogic;
bstestx1 : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
bypass_tdo : out std_ulogic;
mbist_tdo : in std_ulogic := '0'
);
end component;
component bscanregs
generic (
tech: integer := 0;
nsigs: integer range 1 to 30 := 8;
dirmask: integer := 2#00000000#;
enable: integer range 0 to 1 := 1
);
port (
sigi: in std_logic_vector(nsigs-1 downto 0);
sigo: out std_logic_vector(nsigs-1 downto 0);
tck: in std_ulogic;
tckn:in std_ulogic;
tdi: in std_ulogic;
tdo: out std_ulogic;
bsshft: in std_ulogic;
bscapt: in std_ulogic;
bsupdi: in std_ulogic;
bsupdo: in std_ulogic;
bsdrive: in std_ulogic;
bshighz: in std_ulogic
);
end component;
component bscanregsbd
generic (
tech: integer:= 0;
nsigs: integer := 8;
enable: integer range 0 to 1 := 1;
hzsup: integer range 0 to 1 := 1
);
port (
pado : out std_logic_vector(nsigs-1 downto 0);
padoen : out std_logic_vector(nsigs-1 downto 0);
padi : in std_logic_vector(nsigs-1 downto 0);
coreo : in std_logic_vector(nsigs-1 downto 0);
coreoen : in std_logic_vector(nsigs-1 downto 0);
corei : out std_logic_vector(nsigs-1 downto 0);
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signals to scan regs on next tck edge
bsupdi : in std_ulogic; -- update indata reg from scan reg on next tck edge
bsupdo : in std_ulogic; -- update outdata reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive outdata regs to pad,
-- drive datareg(coreoen=0) or coreo(coreoen=1) to corei
bshighz : in std_ulogic -- tri-state output if hzsup, sample 1 on input
);
end component;
end;
|
gpl-2.0
|
da98ff927cd71af52098f352dc78128b
| 0.576358 | 3.637821 | false | false | false | false |
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