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xylnao/w11a-extra
|
rtl/vlib/serport/serport_uart_rxtx_ab.vhd
| 1 | 3,865 |
-- $Id: serport_uart_rxtx_ab.vhd 417 2011-10-22 10:30:29Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_uart_rxtx_ab - syn
-- Description: serial port UART - transmitter-receiver + autobauder
--
-- Dependencies: serport_uart_autobaud
-- serport_uart_rxtx
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-25 348 12.1 M53d xc3s1000-4 99 197 - 124 s 9.8
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 417 1.1.1 now numeric_std clean
-- 2010-12-26 348 1.1 add ABCLKDIV port for clock divider setting
-- 2007-06-24 60 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serport.all;
entity serport_uart_rxtx_ab is -- serial port uart: rx+tx+autobaud
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT: natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit; -- receiver active
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid
ABDONE : out slbit; -- autobaud resync done
ABCLKDIV : out slv(CDWIDTH-1 downto 0) -- autobaud clock divider setting
);
end serport_uart_rxtx_ab;
architecture syn of serport_uart_rxtx_ab is
signal CLKDIV : slv(CDWIDTH-1 downto 0) := slv(to_unsigned(0, CDWIDTH));
signal ABACT_L : slbit := '0'; -- local readable copy of ABACT
signal UART_RESET : slbit := '0';
begin
AB : serport_uart_autobaud
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
RXSD => RXSD,
CLKDIV => CLKDIV,
ACT => ABACT_L,
DONE => ABDONE
);
UART_RESET <= ABACT_L or RESET;
ABACT <= ABACT_L;
ABCLKDIV <= CLKDIV;
RXTX : serport_uart_rxtx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
end syn;
|
gpl-2.0
|
c68436bf9cd48ecc8f61a6f80ddeb89d
| 0.551876 | 4.013499 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/rbus/rblib.vhd
| 1 | 7,598 |
-- $Id: rblib.vhd 405 2011-08-14 08:16:28Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: rblib
-- Description: Definitions for rbus interface and bus entities
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-13 405 3.0.3 add in direction for FADDR,SEL ports
-- 2010-12-26 349 3.0.2 add rb_sel
-- 2010-12-22 346 3.0.1 add rb_mon and rb_mon_sb;
-- 2010-12-04 343 3.0 extracted from rrilib and rritblib;
-- rbus V3 interface: use aval,re,we
-- ... rrilib history removed ...
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package rblib is
type rb_mreq_type is record -- rbus - master request
aval : slbit; -- address valid
re : slbit; -- read enable
we : slbit; -- write enable
init : slbit; -- init
addr : slv8; -- address
din : slv16; -- data (input to slave)
end record rb_mreq_type;
constant rb_mreq_init : rb_mreq_type :=
('0','0','0','0', -- aval, re, we, init
(others=>'0'), -- addr
(others=>'0')); -- din
type rb_sres_type is record -- rbus - slave response
ack : slbit; -- acknowledge
busy : slbit; -- busy
err : slbit; -- error
dout : slv16; -- data (output from slave)
end record rb_sres_type;
constant rb_sres_init : rb_sres_type :=
('0','0','0', -- ack, busy, err
(others=>'0')); -- dout
component rb_sel is -- rbus address select logic
generic (
RB_ADDR : slv8; -- rbus address base
SAWIDTH : natural := 0); -- device subaddress space width
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- rbus request
SEL : out slbit -- select state bit
);
end component;
component rb_sres_or_2 is -- rbus result or, 2 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end component;
component rb_sres_or_3 is -- rbus result or, 3 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end component;
component rb_sres_or_4 is -- rbus result or, 4 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end component;
component rbus_aif is -- rbus, abstract interface
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv3 -- rbus: status flags
);
end component;
component rb_wreg_rw_3 is -- rbus: wide register r/w 3 bit select
generic (
DWIDTH : positive := 16);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
FADDR : in slv3; -- field address
SEL : in slbit; -- select
DATA : out slv(DWIDTH-1 downto 0); -- data
RB_MREQ : in rb_mreq_type; -- rbus request
RB_SRES : out rb_sres_type -- rbus response
);
end component;
component rb_wreg_w_3 is -- rbus: wide register w-o 3 bit select
generic (
DWIDTH : positive := 16);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
FADDR : in slv3; -- field address
SEL : in slbit; -- select
DATA : out slv(DWIDTH-1 downto 0); -- data
RB_MREQ : in rb_mreq_type; -- rbus request
RB_SRES : out rb_sres_type -- rbus response
);
end component;
component rb_wreg_r_3 is -- rbus: wide register r-o 3 bit select
generic (
DWIDTH : positive := 16);
port (
FADDR : in slv3; -- field address
SEL : in slbit; -- select
DATA : in slv(DWIDTH-1 downto 0); -- data
RB_SRES : out rb_sres_type -- rbus response
);
end component;
--
-- components for use in test benches (not synthesizable)
--
component rb_sres_or_mon is -- rbus result or monitor
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_4 : in rb_sres_type := rb_sres_init -- rb_sres input 4
);
end component;
-- simbus sb_cntl field usage for rbus
constant sbcntl_sbf_rbmon : integer := 14;
component rb_mon is -- rbus monitor
generic (
DBASE : positive := 2); -- base for writing data values
port (
CLK : in slbit; -- clock
CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end component;
component rb_mon_sb is -- simbus wrapper for rbus monitor
generic (
DBASE : positive := 2; -- base for writing data values
ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end component;
end package rblib;
|
gpl-2.0
|
e87e1aa5870696ff2c2aa10a16c88e2a
| 0.511582 | 3.717221 | false | false | false | false |
xylnao/w11a-extra
|
rtl/w11a/pdp11_core_rbus.vhd
| 1 | 15,805 |
-- $Id: pdp11_core_rbus.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_core_rbus - syn
-- Description: pdp11: core to rbus interface
--
-- Dependencies: -
-- Test bench: tb/tb_rlink_tba_pdp11core
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History: -
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-12-29 351 1.1 renamed from pdp11_core_rri; ported to rbv3
-- 2010-10-23 335 1.2.3 rename RRI_LAM->RB_LAM;
-- 2010-06-20 308 1.2.2 use c_ibrb_ibf_ def's
-- 2010-06-18 306 1.2.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
-- add ibrb register and ibr window logic
-- 2010-06-13 305 1.2 add CP_ADDR in port; mostly rewritten for new
-- rri <-> cp mapping
-- 2010-06-03 299 1.1.2 correct rbus init logic (use we, din, RB_ADDR)
-- 2010-05-02 287 1.1.1 rename RP_STAT->RB_STAT; remove unneeded unsigned()
-- 2010-05-01 285 1.1 port to rri V2 interface, add RB_ADDR generic;
-- rename c_rp_addr_* -> c_rb_addr_*
-- 2008-05-03 143 1.0.8 rename _cpursta->_cpurust
-- 2008-04-27 140 1.0.7 use cpursta interface, remove cpufail
-- 2008-03-02 121 1.0.6 set RP_ERR when cmderr or cmdmerr status seen
-- 2008-02-24 119 1.0.5 support lah,rps,wps cp commands
-- 2008-01-20 113 1.0.4 use single LAM; change to RRI_LAM interface
-- 2007-10-12 88 1.0.3 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-16 74 1.0.2 add AP_LAM interface to pdp11_core_rri
-- 2007-08-12 73 1.0.1 use def's; add stat command; wait for step complete
-- 2007-07-08 65 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Address Bits Name r/w/i Function
--
-- bbb00000 conf r/w/- cpu configuration (e.g. cpu type)
-- (currently unused, all bits MBZ)
-- bbb00001 cntl -/f/- cpu control
-- 3:0 func function code
-- 0000: noop
-- 0001: start
-- 0010: stop
-- 0011: continue
-- 0100: step
-- 1111: reset (soft)
-- bbb00010 stat r/-/- cpu status
-- 7:04 cpurust r/-/- cp_stat: cpurust
-- 3 cpuhalt r/-/- cp_stat: cpuhalt
-- 2 cpugo r/-/- cp_stat: cpugo
-- 1 cmdmerr r/-/- cp_stat: cmdmerr
-- 0 cmderr r/-/- cp_stat: cmderr
-- bbb00011 psw r/w/- processor status word access
-- bbb00100 al r/w/- address register, low
-- bbb00101 ah r/w/- address register, high
-- bbb00110 mem r/w/- memory access
-- bbb00111 memi r/w/- memory access, inc address
-- bbb01rrr gpr[] r/w/- general purpose regs
-- bbb10000 ibrb r/w/- ibr base address
-- 12:06 base r/w/- ibr window base address
-- 1:00 we r/w/- byte enables (00 equivalent to 11)
-- www----- ibr[] r/w/- ibr window (32 words)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_core_rbus is -- core to rbus interface
generic (
RB_ADDR_CORE : slv8 := slv(to_unsigned(2#00000000#,8));
RB_ADDR_IBUS : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_STAT : out slv3; -- rbus: status flags
RB_LAM : out slbit; -- remote attention
CPU_RESET : out slbit; -- cpu master reset
CP_CNTL : out cp_cntl_type; -- console control port
CP_ADDR : out cp_addr_type; -- console address port
CP_DIN : out slv16; -- console data in
CP_STAT : in cp_stat_type; -- console status port
CP_DOUT : in slv16 -- console data out
);
end pdp11_core_rbus;
architecture syn of pdp11_core_rbus is
type state_type is (
s_idle, -- s_idle: wait for rp access
s_cpwait, -- s_cpwait: wait for cp port ack
s_cpstep -- s_cpstep: wait for cpustep done
);
type regs_type is record
state : state_type; -- state
rbselc : slbit; -- rbus select for core
rbseli : slbit; -- rbus select for ibus
cpreq : slbit; -- cp request flag
cpfunc : slv5; -- cp function
cpugo_1 : slbit; -- prev cycle cpugo
addr : slv22_1; -- address register
ena_22bit : slbit; -- 22bit enable
ena_ubmap : slbit; -- ubmap enable
ibrbase : slv(c_ibrb_ibf_base); -- ibr base address
ibrbe : slv2; -- ibr byte enables
ibrberet : slv2; -- ibr byte enables (for readback)
doinc : slbit; -- at cmdack: do addr reg inc
waitstep : slbit; -- at cmdack: wait for cpu step complete
end record regs_type;
constant regs_init : regs_type := (
s_idle, -- state
'0','0', -- rbselc,rbseli
'0', -- cpreq
(others=>'0'), -- cpfunc
'0', -- cpugo_1
(others=>'0'), -- addr
'0','0', -- ena_22bit, ena_ubmap
(others=>'0'),"00","00", -- ibrbase, ibrbe, ibrberet
'0','0' -- doinc, waitstep
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, CP_STAT, CP_DOUT)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irb_lam : slbit := '0';
variable irbena : slbit := '0';
variable icpreq : slbit := '0';
variable icpureset : slbit := '0';
variable icpaddr : cp_addr_type := cp_addr_init;
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irb_lam := '0';
irbena := RB_MREQ.re or RB_MREQ.we;
icpreq := '0';
icpureset := '0';
-- look for init's against the rbus base address, generate subsystem resets
if RB_MREQ.init='1' and RB_MREQ.we='1' and RB_MREQ.addr=RB_ADDR_CORE then
icpureset := RB_MREQ.din(0);
end if;
-- rbus address decoder
n.rbseli := '0';
n.rbselc := '0';
if RB_MREQ.aval='1' then
if RB_MREQ.addr(7 downto 5)=RB_ADDR_CORE(7 downto 5) then
n.rbselc := '1';
end if;
if RB_MREQ.addr(7 downto 5)=RB_ADDR_IBUS(7 downto 5) then
n.rbseli := '1';
end if;
end if;
if (r.rbselc='1' or r.rbseli='1') and irbena='1' then
irb_ack := '1'; -- ack all (maybe rejected later)
end if;
case r.state is
when s_idle => -- s_idle: wait for rbus access ------
n.doinc := '0';
n.waitstep := '0';
if r.rbseli = '1' then
if irbena = '1' then
n.cpfunc := c_cpfunc_rmem;
n.cpfunc(0) := RB_MREQ.we;
icpreq := '1';
end if;
elsif r.rbselc = '1' then
case RB_MREQ.addr(4 downto 0) is
when c_rbaddr_conf => -- conf -------------------------
null; -- currently no action
when c_rbaddr_cntl => -- cntl -------------------------
if irbena = '1' then
n.cpfunc := RB_MREQ.din(n.cpfunc'range);
end if;
if RB_MREQ.we = '1' then
icpreq := '1';
if RB_MREQ.din(3 downto 0) = c_cpfunc_step(3 downto 0) then
n.waitstep := '1';
end if;
end if;
when c_rbaddr_stat => -- stat -------------------------
irb_dout(c_stat_rbf_cmderr) := CP_STAT.cmderr;
irb_dout(c_stat_rbf_cmdmerr) := CP_STAT.cmdmerr;
irb_dout(c_stat_rbf_cpugo) := CP_STAT.cpugo;
irb_dout(c_stat_rbf_cpuhalt) := CP_STAT.cpuhalt;
irb_dout(c_stat_rbf_cpurust) := CP_STAT.cpurust;
when c_rbaddr_psw => -- psw --------------------------
if irbena = '1' then
n.cpfunc := c_cpfunc_rpsw;
n.cpfunc(0) := RB_MREQ.we;
icpreq := '1';
end if;
when c_rbaddr_al => -- al ---------------------------
irb_dout(c_al_rbf_addr) := r.addr(c_al_rbf_addr);
if RB_MREQ.we = '1' then
n.addr := (others=>'0'); -- write to al clears ah !!
n.ena_22bit := '0';
n.ena_ubmap := '0';
n.addr(c_al_rbf_addr) := RB_MREQ.din(c_al_rbf_addr);
end if;
when c_rbaddr_ah => -- ah ---------------------------
irb_dout(c_ah_rbf_ena_ubmap) := r.ena_ubmap;
irb_dout(c_ah_rbf_ena_22bit) := r.ena_22bit;
irb_dout(c_ah_rbf_addr) := r.addr(21 downto 16);
if RB_MREQ.we = '1' then
n.addr(21 downto 16) := RB_MREQ.din(c_ah_rbf_addr);
n.ena_22bit := RB_MREQ.din(c_ah_rbf_ena_22bit);
n.ena_ubmap := RB_MREQ.din(c_ah_rbf_ena_ubmap);
end if;
when c_rbaddr_mem => -- mem -----------------
if irbena = '1' then
n.cpfunc := c_cpfunc_rmem;
n.cpfunc(0) := RB_MREQ.we;
icpreq := '1';
end if;
when c_rbaddr_memi => -- memi ----------------
if irbena = '1' then
n.cpfunc := c_cpfunc_rmem;
n.cpfunc(0) := RB_MREQ.we;
n.doinc := '1';
icpreq := '1';
end if;
when c_rbaddr_r0 | c_rbaddr_r1 |
c_rbaddr_r2 | c_rbaddr_r3 |
c_rbaddr_r4 | c_rbaddr_r5 |
c_rbaddr_sp | c_rbaddr_pc => -- r* ------------------
if irbena = '1' then
n.cpfunc := c_cpfunc_rreg;
n.cpfunc(0) := RB_MREQ.we;
icpreq := '1';
end if;
when c_rbaddr_ibrb => -- ibrb ----------------
irb_dout(c_ibrb_ibf_base) := r.ibrbase;
irb_dout(c_ibrb_ibf_be) := r.ibrberet;
if RB_MREQ.we = '1' then
n.ibrbase := RB_MREQ.din(c_ibrb_ibf_base);
n.ibrberet := RB_MREQ.din(c_ibrb_ibf_be);
if RB_MREQ.din(c_ibrb_ibf_be) = "00" then -- both be=0 ?
n.ibrbe := "11";
else -- otherwise take 2 LSB's
n.ibrbe := RB_MREQ.din(c_ibrb_ibf_be);
end if;
end if;
when others =>
irb_ack := '0';
end case;
end if;
if icpreq = '1' then
irb_busy := '1';
n.cpreq := '1';
n.state := s_cpwait;
end if;
when s_cpwait => -- s_cpwait: wait for cp port ack ----
n.cpreq := '0'; -- cpreq only for 1 cycle
if (r.rbselc or r.rbseli)='0' or irbena='0' then -- rbus cycle abort
n.state := s_idle; -- quit
else
irb_dout := CP_DOUT;
irb_err := CP_STAT.cmderr or CP_STAT.cmdmerr;
if CP_STAT.cmdack = '1' then -- normal cycle end
if r.doinc = '1' then
n.addr := slv(unsigned(r.addr) + 1);
end if;
if r.waitstep = '1' then
irb_busy := '1';
n.state := s_cpstep;
else
n.state := s_idle;
end if;
else
irb_busy := '1';
end if;
end if;
when s_cpstep => -- s_cpstep: wait for cpustep done ---
if r.rbselc='0' or irbena='0' then -- rbus cycle abort
n.state := s_idle; -- quit
else
if CP_STAT.cpustep = '0' then -- cpustep done
n.state := s_idle;
else
irb_busy := '1';
end if;
end if;
when others => null;
end case;
icpaddr := cp_addr_init;
icpaddr.addr := r.addr;
icpaddr.racc := '0';
icpaddr.be := "11";
icpaddr.ena_22bit := r.ena_22bit;
icpaddr.ena_ubmap := r.ena_ubmap;
if r.rbseli = '1' and irbena = '1' then
icpaddr.addr(15 downto 13) := "111";
icpaddr.addr(c_ibrb_ibf_base) := r.ibrbase;
icpaddr.addr(5 downto 1) := RB_MREQ.addr(4 downto 0);
icpaddr.racc := '1';
icpaddr.be := r.ibrbe;
icpaddr.ena_22bit := '0';
icpaddr.ena_ubmap := '0';
end if;
n.cpugo_1 := CP_STAT.cpugo; -- delay cpugo
if CP_STAT.cpugo='0' and r.cpugo_1='1' then -- cpugo 1 -> 0 transition ?
irb_lam := '1';
end if;
N_REGS <= n;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
RB_SRES.dout <= irb_dout;
RB_STAT(0) <= CP_STAT.cpugo;
RB_STAT(1) <= CP_STAT.cpuhalt or CP_STAT.cpurust(CP_STAT.cpurust'left);
RB_STAT(2) <= CP_STAT.cmderr or CP_STAT.cmdmerr;
RB_LAM <= irb_lam;
CPU_RESET <= icpureset;
CP_CNTL.req <= r.cpreq;
CP_CNTL.func <= r.cpfunc;
CP_CNTL.rnum <= RB_MREQ.addr(2 downto 0);
CP_ADDR <= icpaddr;
CP_DIN <= RB_MREQ.din;
end process proc_next;
end syn;
|
gpl-2.0
|
0143601b69bb4fb412b2e61ff23b9666
| 0.455868 | 3.661107 | false | false | false | false |
rogerioag/gcg
|
samples/unidade_a0/src/unidade_a0.vhd
| 1 | 846 |
-- Project generated by script.
-- Date: Seg,18/11/2013-19:27:07
-- Author: rogerio
-- Comments: Entity Description: unidade_a0.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity unidade_a0 is
port (a, b, c, d: in std_logic; f: out std_logic);
end unidade_a0;
architecture estrutural of unidade_a0 is
-- Declaration of Components.
component and2
port(x, y: in std_logic; z: out std_logic);
end component;
component or2
port(x, y: in std_logic; z: out std_logic);
end component;
-- Signals declaration.
signal s_a0_o0, s_a1_o0: std_logic;
begin
-- Commands.
-- Component instantiation and port mapping.
a0: and2 port map(x=>a, y=>b, z=>s_a0_o0);
a1: and2 port map(x=>c, y=>d, z=>s_a1_o0);
o0: or2 port map(x=>s_a0_o0, y=>s_a1_o0, z=>f);
end estrutural;
|
gpl-3.0
|
81dbff2b2b171ee19ff4538b2c127ac0
| 0.676123 | 2.595092 | false | false | false | false |
xylnao/w11a-extra
|
rtl/bplib/nexys3/tb/tb_nexys3_core.vhd
| 1 | 3,201 |
-- $Id: tb_nexys3_core.vhd 432 2011-11-25 20:16:28Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_core - sim
-- Description: Test bench for nexys3 - core device handling
--
-- Dependencies: vlib/parts/micron/mt45w8mw16b
--
-- To test: generic, any nexys3 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serport.all;
use work.simbus.all;
entity tb_nexys3_core is
port (
I_SWI : out slv8; -- n3 switches
I_BTN : out slv5; -- n3 buttons
O_MEM_CE_N : in slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : in slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : in slbit; -- cram: write enable (act.low)
O_MEM_OE_N : in slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : in slbit; -- cram: address valid (act.low)
O_MEM_CLK : in slbit; -- cram: clock
O_MEM_CRE : in slbit; -- cram: command register enable
I_MEM_WAIT : out slbit; -- cram: mem wait
O_MEM_ADDR : in slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end tb_nexys3_core;
architecture sim of tb_nexys3_core is
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv5 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
);
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
|
gpl-2.0
|
e430fe072f4e9ffa94e0c49cc473207d
| 0.560762 | 3.213855 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega2/ALU_tb.vhd
| 2 | 2,478 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:02:39 09/28/2017
-- Design Name:
-- Module Name: C:/Users/utp/Desktop/TEMPORAL/ALU/ALU_tb.vhd
-- Project Name: ALU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ALU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ALU_tb IS
END ALU_tb;
ARCHITECTURE behavior OF ALU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
ALUOP : IN std_logic_vector(5 downto 0);
Salida : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Oper1 : std_logic_vector(31 downto 0) := (others => '0');
signal Oper2 : std_logic_vector(31 downto 0) := (others => '0');
signal ALUOP : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal Salida : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP (
Oper1 => Oper1,
Oper2 => Oper2,
ALUOP => ALUOP,
Salida => Salida
);
-- Clock process definitions
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
Oper1 <= "00000000000000001110000000000111";
Oper2 <= "00000000000000000000000000000111";
ALUOP <= "000001";
-- insert stimulus here
wait;
end process;
END;
|
mit
|
cf23d4037593a4a19a96459b54ecf1ab
| 0.577078 | 4.055646 | false | true | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega3/psr_mod.vhd
| 1 | 1,977 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity PSR_Modifier is
Port (
rst : in STD_LOGIC;
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
OP1 : in STD_LOGIC_VECTOR (31 downto 0);
OP2 : in STD_LOGIC_VECTOR (31 downto 0);
AluOp : in STD_LOGIC_VECTOR (5 downto 0);
NZVC : out STD_LOGIC_VECTOR (3 downto 0)
);
end PSR_Modifier;
architecture Behavioral of PSR_Modifier is
begin
process(AluResult, OP1, OP2, AluOp)
begin
if (rst = '1') then
NZVC <= (others => '0');
else
-- addcc or addxcc
if (AluOp = "010011" or AluOp = "010010") then
NZVC(3) <= AluResult(31);
if (AluResult = X"00000000") then
NZVC(2) <= '1';
else
NZVC(2) <= '0';
end if;
NZVC(1) <= (OP1(31) and OP2(31) and (not AluResult(31))) or ((not OP1(31)) and (not OP2(31)) and AluResult(31));
NZVC(0) <= (OP1(31) and OP2(31)) or ((not AluResult(31)) and (OP1(31) or OP2(31)) );
end if;
--subcc or subxcc
if (AluOp = "001000" or AluOp = "001010") then
NZVC(3) <= AluResult(31);
if (AluResult = X"00000000") then
NZVC(2) <= '1';
else
NZVC(2) <= '0';
end if;
NZVC(1) <= (OP1(31) and (not OP2(31)) and (not AluResult(31))) or ((not OP1(31)) and OP2(31) and AluResult(31));
NZVC(0) <= ((not OP1(31)) and OP2(31)) or (AluResult(31) and ((not OP1(31)) or OP2(31)));
end if;
-- operadores logicos
-- andcc or andncc or orcc or orncc or xorcc or xnorcc
if (AluOp = "001011" or AluOp = "001100" or AluOp = "001101" or AluOp = "001110" or AluOp = "001111" or AluOp = "010000") then
NZVC(3) <= AluResult(31);
if (AluResult = X"00000000") then
NZVC(2) <= '1';
else
NZVC(2) <= '0';
end if;
NZVC(1) <= '0';
NZVC(0) <= '0';
else
NZVC <= "1000";
end if;
end if;
end process;
end Behavioral;
|
mit
|
f3e46a8cc9fafec6e3b72c0e5dac281a
| 0.539707 | 3.113386 | false | false | false | false |
os-cillation/easyfpga-soc
|
easy_cores/uart16750/uart_16750_wb.vhd
| 1 | 4,856 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- E A S Y C O R E U A R T 1 6 7 5 0
--
-- wishbone-wrapper for uart_16750.vhd
--
-- @author Simon Gansen
-------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use work.interfaces.all;
use work.constants.all;
-------------------------------------------------------------------------------
ENTITY uart_16750_wb is
-------------------------------------------------------------------------------
port(
-- wishbone interface
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type;
-- uart interface
TXD_o : out std_logic; -- Transmitter output
RXD_i : in std_logic; -- Receiver input
CTSn_i : in std_logic := '1'; -- Clear to send input
RTSn_o : out std_logic; -- Request to send output
DSRn_i : in std_logic := '1'; -- Data set ready input
RIn_i : in std_logic := '1'; -- Ring indicator input
DCDn_i : in std_logic := '1'; -- Data carrier detect input
DTRn_o : out std_logic; -- Data terminal ready output
AUX1_o : out std_logic; -- MCR auxiliary output 1
AUX2_o : out std_logic -- MCR auxiliary output 2
);
end uart_16750_wb;
-------------------------------------------------------------------------------
ARCHITECTURE structural of uart_16750_wb is
-------------------------------------------------------------------------------
signal c_rst_s : std_logic;
signal c_wr_s : std_logic;
signal c_rd_s : std_logic;
signal c_adr_s : std_logic_vector(2 downto 0);
signal c_din_s : std_logic_vector(7 downto 0);
signal c_dout_s : std_logic_vector(7 downto 0);
signal c_aux1n_s : std_logic;
signal c_aux2n_s : std_logic;
signal c_baudoutn_s : std_logic;
signal c_rclk_s : std_logic;
-------------------------------------------------------------------------------
begin -- architecture structural
-------------------------------------------------------------------------------
-- address in
c_adr_s <= wbs_in.adr(2 downto 0);
-- data in/out
c_din_s <= wbs_in.dat;
wbs_out.dat <= c_dout_s;
-- wishbone acknowledge output
wbs_out.ack <= wbs_in.stb;
-- read/write lines are only asserted when cyc is high
c_wr_s <= wbs_in.stb and wbs_in.cyc and wbs_in.we;
c_rd_s <= wbs_in.stb and wbs_in.cyc and not wbs_in.we;
-- reset input (async <= sync)
c_rst_s <= wbs_in.rst;
-- feedback clock (16x baudrate)
c_rclk_s <= c_baudoutn_s;
-- re-invert auxiliary outputs
AUX1_o <= not c_aux1n_s;
AUX2_o <= not c_aux2n_s;
-------------------------------------------------------------------------------
UART_CORE : entity work.uart_16750
-------------------------------------------------------------------------------
port map (
-- internal bus interface to be adapted to wishbone
CLK => wbs_in.clk, -- Clock
RST => c_rst_s, -- Async Reset
WR => c_wr_s, -- Write to UART
RD => c_rd_s, -- Read from UART
A => c_adr_s, -- Register select
DIN => c_din_s, -- Data bus input
DOUT => c_dout_s, -- Data bus output
INT => wbs_out.irq, -- Interrupt output
-- UART interface
RTSN => RTSn_o, -- RTS output
DTRN => DTRn_o, -- DTR output
CTSN => CTSn_i, -- CTS input
DSRN => DSRn_i, -- DSR input
DCDN => DCDn_i, -- DCD input
RIN => RIn_i, -- RI input
SIN => RXD_i, -- Receiver input
SOUT => TXD_o, -- Transmitter output
OUT1N => c_aux1n_s, -- MCR auxiliary output 1
OUT2N => c_aux2n_s, -- MCR auxiliary output 2
-- to be tied together
BAUDOUTN => c_baudoutn_s, -- Baudrate generator output (16x baudrate)
RCLK => c_rclk_s -- Receiver clock (16x baudrate)
);
end structural;
|
gpl-3.0
|
59796e92e86bf67606b7f1dd1ac9cef1
| 0.480025 | 4.050042 | false | false | false | false |
rogerioag/gcg
|
tutorial/ula/src/decodificador.vhd
| 1 | 1,339 |
-- Projeto gerado via script.
-- Data: Sáb,31/12/2011-00:58:50
-- Autor: rogerio
-- Comentario: Descrição da Entidade: decodificador.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity decodificador is
port (F2, F1, F0: in std_logic; Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7: out std_logic);
end decodificador;
architecture estrutural of decodificador is
-- Declaração dos componentes.
component and3
port (a,b,c: in std_logic; y: out std_logic);
end component;
component inversor is
port (a: in std_logic; y: out std_logic);
end component;
-- Declaração dos sinais.
signal s_I1_n, s_I2_n, s_I3_n: std_logic;
begin
-- Comandos.
-- Instanciação dos componentes e o mapeamento de portas.
I1: inversor port map(a=>F2, y=>s_I1_n);
I2: inversor port map(a=>F1, y=>s_I2_n);
I3: inversor port map(a=>F0, y=>s_I3_n);
A1: and3 port map(a=>s_I1_n, b=>s_I2_n, c=>s_I3_n, y=>Op0);
A2: and3 port map(a=>s_I1_n, b=>s_I2_n, c=>F0, y=>Op1);
A3: and3 port map(a=>s_I1_n, b=>F1, c=>s_I3_n, y=>Op2);
A4: and3 port map(a=>s_I1_n, b=>F1, c=>F0, y=>Op3);
A5: and3 port map(a=>F2, b=>s_I2_n, c=>s_I3_n, y=>Op4);
A6: and3 port map(a=>F2, b=>s_I2_n, c=>F0, y=>Op5);
A7: and3 port map(a=>F2, b=>F1, c=>s_I3_n, y=>Op6);
A8: and3 port map(a=>F2, b=>F1, c=>F0, y=>Op7);
end estrutural;
|
gpl-3.0
|
3f4c7570b2d7457d0dc667bcf9f92ae5
| 0.636842 | 2.235294 | false | false | false | false |
gtarciso/INE5406
|
switch2x2.vhd
| 1 | 755 |
library ieee;
use ieee.std_logic_1164.all;
entity switch is
generic (width:integer:=8);
port(
inpt0: in std_logic_vector(width-1 downto 0);
inpt1: in std_logic_vector(width-1 downto 0);
ctrl: in std_logic_vector(1 downto 0);
outp0: out std_logic_vector(width-1 downto 0);
outp1: out std_logic_vector(width-1 downto 0)
);
end entity;
architecture switch2x2 of switch is
begin
process(inpt0, inpt1, ctrl)
begin
case ctrl is
when "00" =>
outp0 <= inpt0;
outp1 <= inpt1;
when "01" =>
outp0 <= inpt1;
outp1 <= inpt0;
when "10" =>
outp0 <= inpt0;
outp1 <= inpt0;
when others =>
outp0 <= inpt1;
outp1 <= inpt1;
end case;
end process;
end switch2x2;
|
cc0-1.0
|
d55dc0d4429406d281c3bdb1ef90e8ae
| 0.602649 | 3.119835 | false | false | false | false |
os-cillation/easyfpga-soc
|
templates/testbench.vhd
| 1 | 2,331 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- <UUT NAME> T E S T B E N C H (<uut_name>_tb.vhd)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
ENTITY <uut_name>_tb is
-------------------------------------------------------------------------------
begin
end <uut_name>_tb;
-------------------------------------------------------------------------------
ARCHITECTURE simulation of <uut_name>_tb is
-------------------------------------------------------------------------------
-- constants
constant CLK_PERIOD : time := 10 ns;
-- signals
signal clk : std_logic;
signal rst : std_logic;
begin
-------------------------------------------------
STIMULI_PROC :
-------------------------------------------------
process begin
-- hold reset for 100 ns and 10 clock cycles
rst <= '1';
wait for 100 ns;
wait for CLK_PERIOD*10;
-- place stimuli here:
wait; -- forever
end process STIMULI_PROC;
-------------------------------------------------
-- UUT instantiation
-------------------------------------------------
UUT : soc_bridge
port map (
clk_i => clk,
rst_i => rst
);
-------------------------------------------------
CLK_GENERATOR :
-------------------------------------------------
process begin
clk <= '0';
wait for CLK_PERIOD/2;
clk <= '1';
wait for CLK_PERIOD/2;
end process CLK_GENERATOR;
end simulation;
|
gpl-3.0
|
a9715a7f1849d5a340764eccfc24d1c9
| 0.450879 | 5.134361 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vhd
| 1 | 7,254 |
-- $Id: sys_tst_serloop_s3.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop_s3 - syn
-- Description: Tester serial link for s3board
--
-- Dependencies: vlib/xlib/dcm_sfs
-- genlib/clkdivce
-- bpgen/bp_rs232_2l4l_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_1clock
-- tst_serloop
-- s3board/s3_sram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-11-16 426 13.1 O40d xc3s1000-4 424 602 64 476 t 13.6
-- 2011-11-13 425 13.1 O40d xc3s1000-4 421 586 64 466 t 13.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-09 437 1.0.2 rename serport stat->moni port
-- 2011-11-17 426 1.0.1 use dcm_sfs now
-- 2011-11-12 423 1.0 Initial version
-- 2011-10-25 419 0.5 First draft
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serport.all;
use work.s3boardlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop_s3 is -- top level
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32; -- sram: data lines
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_serloop_s3;
architecture syn of sys_tst_serloop_s3 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
begin
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 6,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 60 sim: 12
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0), -- port selection
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
SERPORT : serport_1clock
generic map (
CDWIDTH => 15,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
SRAM : s3_sram_dummy -- connect SRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;
|
gpl-2.0
|
99a433b42d090e8cc4d5de6ddccbdbd3
| 0.49614 | 3.309307 | false | false | false | false |
os-cillation/easyfpga-soc
|
easy_cores/wishbone_slave/wbs_256.vhd
| 1 | 178,450 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
--===========================================================================--
-- WISHBONE SLAVE (256 registers)
-- generated with sdk-java for testing purposes
--===========================================================================--
--===========================================================================--
-- Type and component definition package
--===========================================================================--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.constants.all;
use work.interfaces.all;
package package_wbs256 is
type reg_wbs256_t is record
reg0 : std_logic_vector(WB_DW-1 downto 0);
reg1 : std_logic_vector(WB_DW-1 downto 0);
reg2 : std_logic_vector(WB_DW-1 downto 0);
reg3 : std_logic_vector(WB_DW-1 downto 0);
reg4 : std_logic_vector(WB_DW-1 downto 0);
reg5 : std_logic_vector(WB_DW-1 downto 0);
reg6 : std_logic_vector(WB_DW-1 downto 0);
reg7 : std_logic_vector(WB_DW-1 downto 0);
reg8 : std_logic_vector(WB_DW-1 downto 0);
reg9 : std_logic_vector(WB_DW-1 downto 0);
reg10 : std_logic_vector(WB_DW-1 downto 0);
reg11 : std_logic_vector(WB_DW-1 downto 0);
reg12 : std_logic_vector(WB_DW-1 downto 0);
reg13 : std_logic_vector(WB_DW-1 downto 0);
reg14 : std_logic_vector(WB_DW-1 downto 0);
reg15 : std_logic_vector(WB_DW-1 downto 0);
reg16 : std_logic_vector(WB_DW-1 downto 0);
reg17 : std_logic_vector(WB_DW-1 downto 0);
reg18 : std_logic_vector(WB_DW-1 downto 0);
reg19 : std_logic_vector(WB_DW-1 downto 0);
reg20 : std_logic_vector(WB_DW-1 downto 0);
reg21 : std_logic_vector(WB_DW-1 downto 0);
reg22 : std_logic_vector(WB_DW-1 downto 0);
reg23 : std_logic_vector(WB_DW-1 downto 0);
reg24 : std_logic_vector(WB_DW-1 downto 0);
reg25 : std_logic_vector(WB_DW-1 downto 0);
reg26 : std_logic_vector(WB_DW-1 downto 0);
reg27 : std_logic_vector(WB_DW-1 downto 0);
reg28 : std_logic_vector(WB_DW-1 downto 0);
reg29 : std_logic_vector(WB_DW-1 downto 0);
reg30 : std_logic_vector(WB_DW-1 downto 0);
reg31 : std_logic_vector(WB_DW-1 downto 0);
reg32 : std_logic_vector(WB_DW-1 downto 0);
reg33 : std_logic_vector(WB_DW-1 downto 0);
reg34 : std_logic_vector(WB_DW-1 downto 0);
reg35 : std_logic_vector(WB_DW-1 downto 0);
reg36 : std_logic_vector(WB_DW-1 downto 0);
reg37 : std_logic_vector(WB_DW-1 downto 0);
reg38 : std_logic_vector(WB_DW-1 downto 0);
reg39 : std_logic_vector(WB_DW-1 downto 0);
reg40 : std_logic_vector(WB_DW-1 downto 0);
reg41 : std_logic_vector(WB_DW-1 downto 0);
reg42 : std_logic_vector(WB_DW-1 downto 0);
reg43 : std_logic_vector(WB_DW-1 downto 0);
reg44 : std_logic_vector(WB_DW-1 downto 0);
reg45 : std_logic_vector(WB_DW-1 downto 0);
reg46 : std_logic_vector(WB_DW-1 downto 0);
reg47 : std_logic_vector(WB_DW-1 downto 0);
reg48 : std_logic_vector(WB_DW-1 downto 0);
reg49 : std_logic_vector(WB_DW-1 downto 0);
reg50 : std_logic_vector(WB_DW-1 downto 0);
reg51 : std_logic_vector(WB_DW-1 downto 0);
reg52 : std_logic_vector(WB_DW-1 downto 0);
reg53 : std_logic_vector(WB_DW-1 downto 0);
reg54 : std_logic_vector(WB_DW-1 downto 0);
reg55 : std_logic_vector(WB_DW-1 downto 0);
reg56 : std_logic_vector(WB_DW-1 downto 0);
reg57 : std_logic_vector(WB_DW-1 downto 0);
reg58 : std_logic_vector(WB_DW-1 downto 0);
reg59 : std_logic_vector(WB_DW-1 downto 0);
reg60 : std_logic_vector(WB_DW-1 downto 0);
reg61 : std_logic_vector(WB_DW-1 downto 0);
reg62 : std_logic_vector(WB_DW-1 downto 0);
reg63 : std_logic_vector(WB_DW-1 downto 0);
reg64 : std_logic_vector(WB_DW-1 downto 0);
reg65 : std_logic_vector(WB_DW-1 downto 0);
reg66 : std_logic_vector(WB_DW-1 downto 0);
reg67 : std_logic_vector(WB_DW-1 downto 0);
reg68 : std_logic_vector(WB_DW-1 downto 0);
reg69 : std_logic_vector(WB_DW-1 downto 0);
reg70 : std_logic_vector(WB_DW-1 downto 0);
reg71 : std_logic_vector(WB_DW-1 downto 0);
reg72 : std_logic_vector(WB_DW-1 downto 0);
reg73 : std_logic_vector(WB_DW-1 downto 0);
reg74 : std_logic_vector(WB_DW-1 downto 0);
reg75 : std_logic_vector(WB_DW-1 downto 0);
reg76 : std_logic_vector(WB_DW-1 downto 0);
reg77 : std_logic_vector(WB_DW-1 downto 0);
reg78 : std_logic_vector(WB_DW-1 downto 0);
reg79 : std_logic_vector(WB_DW-1 downto 0);
reg80 : std_logic_vector(WB_DW-1 downto 0);
reg81 : std_logic_vector(WB_DW-1 downto 0);
reg82 : std_logic_vector(WB_DW-1 downto 0);
reg83 : std_logic_vector(WB_DW-1 downto 0);
reg84 : std_logic_vector(WB_DW-1 downto 0);
reg85 : std_logic_vector(WB_DW-1 downto 0);
reg86 : std_logic_vector(WB_DW-1 downto 0);
reg87 : std_logic_vector(WB_DW-1 downto 0);
reg88 : std_logic_vector(WB_DW-1 downto 0);
reg89 : std_logic_vector(WB_DW-1 downto 0);
reg90 : std_logic_vector(WB_DW-1 downto 0);
reg91 : std_logic_vector(WB_DW-1 downto 0);
reg92 : std_logic_vector(WB_DW-1 downto 0);
reg93 : std_logic_vector(WB_DW-1 downto 0);
reg94 : std_logic_vector(WB_DW-1 downto 0);
reg95 : std_logic_vector(WB_DW-1 downto 0);
reg96 : std_logic_vector(WB_DW-1 downto 0);
reg97 : std_logic_vector(WB_DW-1 downto 0);
reg98 : std_logic_vector(WB_DW-1 downto 0);
reg99 : std_logic_vector(WB_DW-1 downto 0);
reg100 : std_logic_vector(WB_DW-1 downto 0);
reg101 : std_logic_vector(WB_DW-1 downto 0);
reg102 : std_logic_vector(WB_DW-1 downto 0);
reg103 : std_logic_vector(WB_DW-1 downto 0);
reg104 : std_logic_vector(WB_DW-1 downto 0);
reg105 : std_logic_vector(WB_DW-1 downto 0);
reg106 : std_logic_vector(WB_DW-1 downto 0);
reg107 : std_logic_vector(WB_DW-1 downto 0);
reg108 : std_logic_vector(WB_DW-1 downto 0);
reg109 : std_logic_vector(WB_DW-1 downto 0);
reg110 : std_logic_vector(WB_DW-1 downto 0);
reg111 : std_logic_vector(WB_DW-1 downto 0);
reg112 : std_logic_vector(WB_DW-1 downto 0);
reg113 : std_logic_vector(WB_DW-1 downto 0);
reg114 : std_logic_vector(WB_DW-1 downto 0);
reg115 : std_logic_vector(WB_DW-1 downto 0);
reg116 : std_logic_vector(WB_DW-1 downto 0);
reg117 : std_logic_vector(WB_DW-1 downto 0);
reg118 : std_logic_vector(WB_DW-1 downto 0);
reg119 : std_logic_vector(WB_DW-1 downto 0);
reg120 : std_logic_vector(WB_DW-1 downto 0);
reg121 : std_logic_vector(WB_DW-1 downto 0);
reg122 : std_logic_vector(WB_DW-1 downto 0);
reg123 : std_logic_vector(WB_DW-1 downto 0);
reg124 : std_logic_vector(WB_DW-1 downto 0);
reg125 : std_logic_vector(WB_DW-1 downto 0);
reg126 : std_logic_vector(WB_DW-1 downto 0);
reg127 : std_logic_vector(WB_DW-1 downto 0);
reg128 : std_logic_vector(WB_DW-1 downto 0);
reg129 : std_logic_vector(WB_DW-1 downto 0);
reg130 : std_logic_vector(WB_DW-1 downto 0);
reg131 : std_logic_vector(WB_DW-1 downto 0);
reg132 : std_logic_vector(WB_DW-1 downto 0);
reg133 : std_logic_vector(WB_DW-1 downto 0);
reg134 : std_logic_vector(WB_DW-1 downto 0);
reg135 : std_logic_vector(WB_DW-1 downto 0);
reg136 : std_logic_vector(WB_DW-1 downto 0);
reg137 : std_logic_vector(WB_DW-1 downto 0);
reg138 : std_logic_vector(WB_DW-1 downto 0);
reg139 : std_logic_vector(WB_DW-1 downto 0);
reg140 : std_logic_vector(WB_DW-1 downto 0);
reg141 : std_logic_vector(WB_DW-1 downto 0);
reg142 : std_logic_vector(WB_DW-1 downto 0);
reg143 : std_logic_vector(WB_DW-1 downto 0);
reg144 : std_logic_vector(WB_DW-1 downto 0);
reg145 : std_logic_vector(WB_DW-1 downto 0);
reg146 : std_logic_vector(WB_DW-1 downto 0);
reg147 : std_logic_vector(WB_DW-1 downto 0);
reg148 : std_logic_vector(WB_DW-1 downto 0);
reg149 : std_logic_vector(WB_DW-1 downto 0);
reg150 : std_logic_vector(WB_DW-1 downto 0);
reg151 : std_logic_vector(WB_DW-1 downto 0);
reg152 : std_logic_vector(WB_DW-1 downto 0);
reg153 : std_logic_vector(WB_DW-1 downto 0);
reg154 : std_logic_vector(WB_DW-1 downto 0);
reg155 : std_logic_vector(WB_DW-1 downto 0);
reg156 : std_logic_vector(WB_DW-1 downto 0);
reg157 : std_logic_vector(WB_DW-1 downto 0);
reg158 : std_logic_vector(WB_DW-1 downto 0);
reg159 : std_logic_vector(WB_DW-1 downto 0);
reg160 : std_logic_vector(WB_DW-1 downto 0);
reg161 : std_logic_vector(WB_DW-1 downto 0);
reg162 : std_logic_vector(WB_DW-1 downto 0);
reg163 : std_logic_vector(WB_DW-1 downto 0);
reg164 : std_logic_vector(WB_DW-1 downto 0);
reg165 : std_logic_vector(WB_DW-1 downto 0);
reg166 : std_logic_vector(WB_DW-1 downto 0);
reg167 : std_logic_vector(WB_DW-1 downto 0);
reg168 : std_logic_vector(WB_DW-1 downto 0);
reg169 : std_logic_vector(WB_DW-1 downto 0);
reg170 : std_logic_vector(WB_DW-1 downto 0);
reg171 : std_logic_vector(WB_DW-1 downto 0);
reg172 : std_logic_vector(WB_DW-1 downto 0);
reg173 : std_logic_vector(WB_DW-1 downto 0);
reg174 : std_logic_vector(WB_DW-1 downto 0);
reg175 : std_logic_vector(WB_DW-1 downto 0);
reg176 : std_logic_vector(WB_DW-1 downto 0);
reg177 : std_logic_vector(WB_DW-1 downto 0);
reg178 : std_logic_vector(WB_DW-1 downto 0);
reg179 : std_logic_vector(WB_DW-1 downto 0);
reg180 : std_logic_vector(WB_DW-1 downto 0);
reg181 : std_logic_vector(WB_DW-1 downto 0);
reg182 : std_logic_vector(WB_DW-1 downto 0);
reg183 : std_logic_vector(WB_DW-1 downto 0);
reg184 : std_logic_vector(WB_DW-1 downto 0);
reg185 : std_logic_vector(WB_DW-1 downto 0);
reg186 : std_logic_vector(WB_DW-1 downto 0);
reg187 : std_logic_vector(WB_DW-1 downto 0);
reg188 : std_logic_vector(WB_DW-1 downto 0);
reg189 : std_logic_vector(WB_DW-1 downto 0);
reg190 : std_logic_vector(WB_DW-1 downto 0);
reg191 : std_logic_vector(WB_DW-1 downto 0);
reg192 : std_logic_vector(WB_DW-1 downto 0);
reg193 : std_logic_vector(WB_DW-1 downto 0);
reg194 : std_logic_vector(WB_DW-1 downto 0);
reg195 : std_logic_vector(WB_DW-1 downto 0);
reg196 : std_logic_vector(WB_DW-1 downto 0);
reg197 : std_logic_vector(WB_DW-1 downto 0);
reg198 : std_logic_vector(WB_DW-1 downto 0);
reg199 : std_logic_vector(WB_DW-1 downto 0);
reg200 : std_logic_vector(WB_DW-1 downto 0);
reg201 : std_logic_vector(WB_DW-1 downto 0);
reg202 : std_logic_vector(WB_DW-1 downto 0);
reg203 : std_logic_vector(WB_DW-1 downto 0);
reg204 : std_logic_vector(WB_DW-1 downto 0);
reg205 : std_logic_vector(WB_DW-1 downto 0);
reg206 : std_logic_vector(WB_DW-1 downto 0);
reg207 : std_logic_vector(WB_DW-1 downto 0);
reg208 : std_logic_vector(WB_DW-1 downto 0);
reg209 : std_logic_vector(WB_DW-1 downto 0);
reg210 : std_logic_vector(WB_DW-1 downto 0);
reg211 : std_logic_vector(WB_DW-1 downto 0);
reg212 : std_logic_vector(WB_DW-1 downto 0);
reg213 : std_logic_vector(WB_DW-1 downto 0);
reg214 : std_logic_vector(WB_DW-1 downto 0);
reg215 : std_logic_vector(WB_DW-1 downto 0);
reg216 : std_logic_vector(WB_DW-1 downto 0);
reg217 : std_logic_vector(WB_DW-1 downto 0);
reg218 : std_logic_vector(WB_DW-1 downto 0);
reg219 : std_logic_vector(WB_DW-1 downto 0);
reg220 : std_logic_vector(WB_DW-1 downto 0);
reg221 : std_logic_vector(WB_DW-1 downto 0);
reg222 : std_logic_vector(WB_DW-1 downto 0);
reg223 : std_logic_vector(WB_DW-1 downto 0);
reg224 : std_logic_vector(WB_DW-1 downto 0);
reg225 : std_logic_vector(WB_DW-1 downto 0);
reg226 : std_logic_vector(WB_DW-1 downto 0);
reg227 : std_logic_vector(WB_DW-1 downto 0);
reg228 : std_logic_vector(WB_DW-1 downto 0);
reg229 : std_logic_vector(WB_DW-1 downto 0);
reg230 : std_logic_vector(WB_DW-1 downto 0);
reg231 : std_logic_vector(WB_DW-1 downto 0);
reg232 : std_logic_vector(WB_DW-1 downto 0);
reg233 : std_logic_vector(WB_DW-1 downto 0);
reg234 : std_logic_vector(WB_DW-1 downto 0);
reg235 : std_logic_vector(WB_DW-1 downto 0);
reg236 : std_logic_vector(WB_DW-1 downto 0);
reg237 : std_logic_vector(WB_DW-1 downto 0);
reg238 : std_logic_vector(WB_DW-1 downto 0);
reg239 : std_logic_vector(WB_DW-1 downto 0);
reg240 : std_logic_vector(WB_DW-1 downto 0);
reg241 : std_logic_vector(WB_DW-1 downto 0);
reg242 : std_logic_vector(WB_DW-1 downto 0);
reg243 : std_logic_vector(WB_DW-1 downto 0);
reg244 : std_logic_vector(WB_DW-1 downto 0);
reg245 : std_logic_vector(WB_DW-1 downto 0);
reg246 : std_logic_vector(WB_DW-1 downto 0);
reg247 : std_logic_vector(WB_DW-1 downto 0);
reg248 : std_logic_vector(WB_DW-1 downto 0);
reg249 : std_logic_vector(WB_DW-1 downto 0);
reg250 : std_logic_vector(WB_DW-1 downto 0);
reg251 : std_logic_vector(WB_DW-1 downto 0);
reg252 : std_logic_vector(WB_DW-1 downto 0);
reg253 : std_logic_vector(WB_DW-1 downto 0);
reg254 : std_logic_vector(WB_DW-1 downto 0);
reg255 : std_logic_vector(WB_DW-1 downto 0);
end record;
component wbs256
port (
-- register outputs
reg0_out : out std_logic_vector(WB_DW-1 downto 0);
reg1_out : out std_logic_vector(WB_DW-1 downto 0);
reg2_out : out std_logic_vector(WB_DW-1 downto 0);
reg3_out : out std_logic_vector(WB_DW-1 downto 0);
reg4_out : out std_logic_vector(WB_DW-1 downto 0);
reg5_out : out std_logic_vector(WB_DW-1 downto 0);
reg6_out : out std_logic_vector(WB_DW-1 downto 0);
reg7_out : out std_logic_vector(WB_DW-1 downto 0);
reg8_out : out std_logic_vector(WB_DW-1 downto 0);
reg9_out : out std_logic_vector(WB_DW-1 downto 0);
reg10_out : out std_logic_vector(WB_DW-1 downto 0);
reg11_out : out std_logic_vector(WB_DW-1 downto 0);
reg12_out : out std_logic_vector(WB_DW-1 downto 0);
reg13_out : out std_logic_vector(WB_DW-1 downto 0);
reg14_out : out std_logic_vector(WB_DW-1 downto 0);
reg15_out : out std_logic_vector(WB_DW-1 downto 0);
reg16_out : out std_logic_vector(WB_DW-1 downto 0);
reg17_out : out std_logic_vector(WB_DW-1 downto 0);
reg18_out : out std_logic_vector(WB_DW-1 downto 0);
reg19_out : out std_logic_vector(WB_DW-1 downto 0);
reg20_out : out std_logic_vector(WB_DW-1 downto 0);
reg21_out : out std_logic_vector(WB_DW-1 downto 0);
reg22_out : out std_logic_vector(WB_DW-1 downto 0);
reg23_out : out std_logic_vector(WB_DW-1 downto 0);
reg24_out : out std_logic_vector(WB_DW-1 downto 0);
reg25_out : out std_logic_vector(WB_DW-1 downto 0);
reg26_out : out std_logic_vector(WB_DW-1 downto 0);
reg27_out : out std_logic_vector(WB_DW-1 downto 0);
reg28_out : out std_logic_vector(WB_DW-1 downto 0);
reg29_out : out std_logic_vector(WB_DW-1 downto 0);
reg30_out : out std_logic_vector(WB_DW-1 downto 0);
reg31_out : out std_logic_vector(WB_DW-1 downto 0);
reg32_out : out std_logic_vector(WB_DW-1 downto 0);
reg33_out : out std_logic_vector(WB_DW-1 downto 0);
reg34_out : out std_logic_vector(WB_DW-1 downto 0);
reg35_out : out std_logic_vector(WB_DW-1 downto 0);
reg36_out : out std_logic_vector(WB_DW-1 downto 0);
reg37_out : out std_logic_vector(WB_DW-1 downto 0);
reg38_out : out std_logic_vector(WB_DW-1 downto 0);
reg39_out : out std_logic_vector(WB_DW-1 downto 0);
reg40_out : out std_logic_vector(WB_DW-1 downto 0);
reg41_out : out std_logic_vector(WB_DW-1 downto 0);
reg42_out : out std_logic_vector(WB_DW-1 downto 0);
reg43_out : out std_logic_vector(WB_DW-1 downto 0);
reg44_out : out std_logic_vector(WB_DW-1 downto 0);
reg45_out : out std_logic_vector(WB_DW-1 downto 0);
reg46_out : out std_logic_vector(WB_DW-1 downto 0);
reg47_out : out std_logic_vector(WB_DW-1 downto 0);
reg48_out : out std_logic_vector(WB_DW-1 downto 0);
reg49_out : out std_logic_vector(WB_DW-1 downto 0);
reg50_out : out std_logic_vector(WB_DW-1 downto 0);
reg51_out : out std_logic_vector(WB_DW-1 downto 0);
reg52_out : out std_logic_vector(WB_DW-1 downto 0);
reg53_out : out std_logic_vector(WB_DW-1 downto 0);
reg54_out : out std_logic_vector(WB_DW-1 downto 0);
reg55_out : out std_logic_vector(WB_DW-1 downto 0);
reg56_out : out std_logic_vector(WB_DW-1 downto 0);
reg57_out : out std_logic_vector(WB_DW-1 downto 0);
reg58_out : out std_logic_vector(WB_DW-1 downto 0);
reg59_out : out std_logic_vector(WB_DW-1 downto 0);
reg60_out : out std_logic_vector(WB_DW-1 downto 0);
reg61_out : out std_logic_vector(WB_DW-1 downto 0);
reg62_out : out std_logic_vector(WB_DW-1 downto 0);
reg63_out : out std_logic_vector(WB_DW-1 downto 0);
reg64_out : out std_logic_vector(WB_DW-1 downto 0);
reg65_out : out std_logic_vector(WB_DW-1 downto 0);
reg66_out : out std_logic_vector(WB_DW-1 downto 0);
reg67_out : out std_logic_vector(WB_DW-1 downto 0);
reg68_out : out std_logic_vector(WB_DW-1 downto 0);
reg69_out : out std_logic_vector(WB_DW-1 downto 0);
reg70_out : out std_logic_vector(WB_DW-1 downto 0);
reg71_out : out std_logic_vector(WB_DW-1 downto 0);
reg72_out : out std_logic_vector(WB_DW-1 downto 0);
reg73_out : out std_logic_vector(WB_DW-1 downto 0);
reg74_out : out std_logic_vector(WB_DW-1 downto 0);
reg75_out : out std_logic_vector(WB_DW-1 downto 0);
reg76_out : out std_logic_vector(WB_DW-1 downto 0);
reg77_out : out std_logic_vector(WB_DW-1 downto 0);
reg78_out : out std_logic_vector(WB_DW-1 downto 0);
reg79_out : out std_logic_vector(WB_DW-1 downto 0);
reg80_out : out std_logic_vector(WB_DW-1 downto 0);
reg81_out : out std_logic_vector(WB_DW-1 downto 0);
reg82_out : out std_logic_vector(WB_DW-1 downto 0);
reg83_out : out std_logic_vector(WB_DW-1 downto 0);
reg84_out : out std_logic_vector(WB_DW-1 downto 0);
reg85_out : out std_logic_vector(WB_DW-1 downto 0);
reg86_out : out std_logic_vector(WB_DW-1 downto 0);
reg87_out : out std_logic_vector(WB_DW-1 downto 0);
reg88_out : out std_logic_vector(WB_DW-1 downto 0);
reg89_out : out std_logic_vector(WB_DW-1 downto 0);
reg90_out : out std_logic_vector(WB_DW-1 downto 0);
reg91_out : out std_logic_vector(WB_DW-1 downto 0);
reg92_out : out std_logic_vector(WB_DW-1 downto 0);
reg93_out : out std_logic_vector(WB_DW-1 downto 0);
reg94_out : out std_logic_vector(WB_DW-1 downto 0);
reg95_out : out std_logic_vector(WB_DW-1 downto 0);
reg96_out : out std_logic_vector(WB_DW-1 downto 0);
reg97_out : out std_logic_vector(WB_DW-1 downto 0);
reg98_out : out std_logic_vector(WB_DW-1 downto 0);
reg99_out : out std_logic_vector(WB_DW-1 downto 0);
reg100_out : out std_logic_vector(WB_DW-1 downto 0);
reg101_out : out std_logic_vector(WB_DW-1 downto 0);
reg102_out : out std_logic_vector(WB_DW-1 downto 0);
reg103_out : out std_logic_vector(WB_DW-1 downto 0);
reg104_out : out std_logic_vector(WB_DW-1 downto 0);
reg105_out : out std_logic_vector(WB_DW-1 downto 0);
reg106_out : out std_logic_vector(WB_DW-1 downto 0);
reg107_out : out std_logic_vector(WB_DW-1 downto 0);
reg108_out : out std_logic_vector(WB_DW-1 downto 0);
reg109_out : out std_logic_vector(WB_DW-1 downto 0);
reg110_out : out std_logic_vector(WB_DW-1 downto 0);
reg111_out : out std_logic_vector(WB_DW-1 downto 0);
reg112_out : out std_logic_vector(WB_DW-1 downto 0);
reg113_out : out std_logic_vector(WB_DW-1 downto 0);
reg114_out : out std_logic_vector(WB_DW-1 downto 0);
reg115_out : out std_logic_vector(WB_DW-1 downto 0);
reg116_out : out std_logic_vector(WB_DW-1 downto 0);
reg117_out : out std_logic_vector(WB_DW-1 downto 0);
reg118_out : out std_logic_vector(WB_DW-1 downto 0);
reg119_out : out std_logic_vector(WB_DW-1 downto 0);
reg120_out : out std_logic_vector(WB_DW-1 downto 0);
reg121_out : out std_logic_vector(WB_DW-1 downto 0);
reg122_out : out std_logic_vector(WB_DW-1 downto 0);
reg123_out : out std_logic_vector(WB_DW-1 downto 0);
reg124_out : out std_logic_vector(WB_DW-1 downto 0);
reg125_out : out std_logic_vector(WB_DW-1 downto 0);
reg126_out : out std_logic_vector(WB_DW-1 downto 0);
reg127_out : out std_logic_vector(WB_DW-1 downto 0);
reg128_out : out std_logic_vector(WB_DW-1 downto 0);
reg129_out : out std_logic_vector(WB_DW-1 downto 0);
reg130_out : out std_logic_vector(WB_DW-1 downto 0);
reg131_out : out std_logic_vector(WB_DW-1 downto 0);
reg132_out : out std_logic_vector(WB_DW-1 downto 0);
reg133_out : out std_logic_vector(WB_DW-1 downto 0);
reg134_out : out std_logic_vector(WB_DW-1 downto 0);
reg135_out : out std_logic_vector(WB_DW-1 downto 0);
reg136_out : out std_logic_vector(WB_DW-1 downto 0);
reg137_out : out std_logic_vector(WB_DW-1 downto 0);
reg138_out : out std_logic_vector(WB_DW-1 downto 0);
reg139_out : out std_logic_vector(WB_DW-1 downto 0);
reg140_out : out std_logic_vector(WB_DW-1 downto 0);
reg141_out : out std_logic_vector(WB_DW-1 downto 0);
reg142_out : out std_logic_vector(WB_DW-1 downto 0);
reg143_out : out std_logic_vector(WB_DW-1 downto 0);
reg144_out : out std_logic_vector(WB_DW-1 downto 0);
reg145_out : out std_logic_vector(WB_DW-1 downto 0);
reg146_out : out std_logic_vector(WB_DW-1 downto 0);
reg147_out : out std_logic_vector(WB_DW-1 downto 0);
reg148_out : out std_logic_vector(WB_DW-1 downto 0);
reg149_out : out std_logic_vector(WB_DW-1 downto 0);
reg150_out : out std_logic_vector(WB_DW-1 downto 0);
reg151_out : out std_logic_vector(WB_DW-1 downto 0);
reg152_out : out std_logic_vector(WB_DW-1 downto 0);
reg153_out : out std_logic_vector(WB_DW-1 downto 0);
reg154_out : out std_logic_vector(WB_DW-1 downto 0);
reg155_out : out std_logic_vector(WB_DW-1 downto 0);
reg156_out : out std_logic_vector(WB_DW-1 downto 0);
reg157_out : out std_logic_vector(WB_DW-1 downto 0);
reg158_out : out std_logic_vector(WB_DW-1 downto 0);
reg159_out : out std_logic_vector(WB_DW-1 downto 0);
reg160_out : out std_logic_vector(WB_DW-1 downto 0);
reg161_out : out std_logic_vector(WB_DW-1 downto 0);
reg162_out : out std_logic_vector(WB_DW-1 downto 0);
reg163_out : out std_logic_vector(WB_DW-1 downto 0);
reg164_out : out std_logic_vector(WB_DW-1 downto 0);
reg165_out : out std_logic_vector(WB_DW-1 downto 0);
reg166_out : out std_logic_vector(WB_DW-1 downto 0);
reg167_out : out std_logic_vector(WB_DW-1 downto 0);
reg168_out : out std_logic_vector(WB_DW-1 downto 0);
reg169_out : out std_logic_vector(WB_DW-1 downto 0);
reg170_out : out std_logic_vector(WB_DW-1 downto 0);
reg171_out : out std_logic_vector(WB_DW-1 downto 0);
reg172_out : out std_logic_vector(WB_DW-1 downto 0);
reg173_out : out std_logic_vector(WB_DW-1 downto 0);
reg174_out : out std_logic_vector(WB_DW-1 downto 0);
reg175_out : out std_logic_vector(WB_DW-1 downto 0);
reg176_out : out std_logic_vector(WB_DW-1 downto 0);
reg177_out : out std_logic_vector(WB_DW-1 downto 0);
reg178_out : out std_logic_vector(WB_DW-1 downto 0);
reg179_out : out std_logic_vector(WB_DW-1 downto 0);
reg180_out : out std_logic_vector(WB_DW-1 downto 0);
reg181_out : out std_logic_vector(WB_DW-1 downto 0);
reg182_out : out std_logic_vector(WB_DW-1 downto 0);
reg183_out : out std_logic_vector(WB_DW-1 downto 0);
reg184_out : out std_logic_vector(WB_DW-1 downto 0);
reg185_out : out std_logic_vector(WB_DW-1 downto 0);
reg186_out : out std_logic_vector(WB_DW-1 downto 0);
reg187_out : out std_logic_vector(WB_DW-1 downto 0);
reg188_out : out std_logic_vector(WB_DW-1 downto 0);
reg189_out : out std_logic_vector(WB_DW-1 downto 0);
reg190_out : out std_logic_vector(WB_DW-1 downto 0);
reg191_out : out std_logic_vector(WB_DW-1 downto 0);
reg192_out : out std_logic_vector(WB_DW-1 downto 0);
reg193_out : out std_logic_vector(WB_DW-1 downto 0);
reg194_out : out std_logic_vector(WB_DW-1 downto 0);
reg195_out : out std_logic_vector(WB_DW-1 downto 0);
reg196_out : out std_logic_vector(WB_DW-1 downto 0);
reg197_out : out std_logic_vector(WB_DW-1 downto 0);
reg198_out : out std_logic_vector(WB_DW-1 downto 0);
reg199_out : out std_logic_vector(WB_DW-1 downto 0);
reg200_out : out std_logic_vector(WB_DW-1 downto 0);
reg201_out : out std_logic_vector(WB_DW-1 downto 0);
reg202_out : out std_logic_vector(WB_DW-1 downto 0);
reg203_out : out std_logic_vector(WB_DW-1 downto 0);
reg204_out : out std_logic_vector(WB_DW-1 downto 0);
reg205_out : out std_logic_vector(WB_DW-1 downto 0);
reg206_out : out std_logic_vector(WB_DW-1 downto 0);
reg207_out : out std_logic_vector(WB_DW-1 downto 0);
reg208_out : out std_logic_vector(WB_DW-1 downto 0);
reg209_out : out std_logic_vector(WB_DW-1 downto 0);
reg210_out : out std_logic_vector(WB_DW-1 downto 0);
reg211_out : out std_logic_vector(WB_DW-1 downto 0);
reg212_out : out std_logic_vector(WB_DW-1 downto 0);
reg213_out : out std_logic_vector(WB_DW-1 downto 0);
reg214_out : out std_logic_vector(WB_DW-1 downto 0);
reg215_out : out std_logic_vector(WB_DW-1 downto 0);
reg216_out : out std_logic_vector(WB_DW-1 downto 0);
reg217_out : out std_logic_vector(WB_DW-1 downto 0);
reg218_out : out std_logic_vector(WB_DW-1 downto 0);
reg219_out : out std_logic_vector(WB_DW-1 downto 0);
reg220_out : out std_logic_vector(WB_DW-1 downto 0);
reg221_out : out std_logic_vector(WB_DW-1 downto 0);
reg222_out : out std_logic_vector(WB_DW-1 downto 0);
reg223_out : out std_logic_vector(WB_DW-1 downto 0);
reg224_out : out std_logic_vector(WB_DW-1 downto 0);
reg225_out : out std_logic_vector(WB_DW-1 downto 0);
reg226_out : out std_logic_vector(WB_DW-1 downto 0);
reg227_out : out std_logic_vector(WB_DW-1 downto 0);
reg228_out : out std_logic_vector(WB_DW-1 downto 0);
reg229_out : out std_logic_vector(WB_DW-1 downto 0);
reg230_out : out std_logic_vector(WB_DW-1 downto 0);
reg231_out : out std_logic_vector(WB_DW-1 downto 0);
reg232_out : out std_logic_vector(WB_DW-1 downto 0);
reg233_out : out std_logic_vector(WB_DW-1 downto 0);
reg234_out : out std_logic_vector(WB_DW-1 downto 0);
reg235_out : out std_logic_vector(WB_DW-1 downto 0);
reg236_out : out std_logic_vector(WB_DW-1 downto 0);
reg237_out : out std_logic_vector(WB_DW-1 downto 0);
reg238_out : out std_logic_vector(WB_DW-1 downto 0);
reg239_out : out std_logic_vector(WB_DW-1 downto 0);
reg240_out : out std_logic_vector(WB_DW-1 downto 0);
reg241_out : out std_logic_vector(WB_DW-1 downto 0);
reg242_out : out std_logic_vector(WB_DW-1 downto 0);
reg243_out : out std_logic_vector(WB_DW-1 downto 0);
reg244_out : out std_logic_vector(WB_DW-1 downto 0);
reg245_out : out std_logic_vector(WB_DW-1 downto 0);
reg246_out : out std_logic_vector(WB_DW-1 downto 0);
reg247_out : out std_logic_vector(WB_DW-1 downto 0);
reg248_out : out std_logic_vector(WB_DW-1 downto 0);
reg249_out : out std_logic_vector(WB_DW-1 downto 0);
reg250_out : out std_logic_vector(WB_DW-1 downto 0);
reg251_out : out std_logic_vector(WB_DW-1 downto 0);
reg252_out : out std_logic_vector(WB_DW-1 downto 0);
reg253_out : out std_logic_vector(WB_DW-1 downto 0);
reg254_out : out std_logic_vector(WB_DW-1 downto 0);
reg255_out : out std_logic_vector(WB_DW-1 downto 0);
-- wishbone interface
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type
);
end component;
end package;
--===========================================================================--
-- Entity
--===========================================================================--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.interfaces.all;
use work.constants.all;
use work.package_wbs256.all;
-------------------------------------------------------------------------------
entity wbs256 is
-------------------------------------------------------------------------------
port (
-- register outputs
reg0_out : out std_logic_vector(WB_DW-1 downto 0);
reg1_out : out std_logic_vector(WB_DW-1 downto 0);
reg2_out : out std_logic_vector(WB_DW-1 downto 0);
reg3_out : out std_logic_vector(WB_DW-1 downto 0);
reg4_out : out std_logic_vector(WB_DW-1 downto 0);
reg5_out : out std_logic_vector(WB_DW-1 downto 0);
reg6_out : out std_logic_vector(WB_DW-1 downto 0);
reg7_out : out std_logic_vector(WB_DW-1 downto 0);
reg8_out : out std_logic_vector(WB_DW-1 downto 0);
reg9_out : out std_logic_vector(WB_DW-1 downto 0);
reg10_out : out std_logic_vector(WB_DW-1 downto 0);
reg11_out : out std_logic_vector(WB_DW-1 downto 0);
reg12_out : out std_logic_vector(WB_DW-1 downto 0);
reg13_out : out std_logic_vector(WB_DW-1 downto 0);
reg14_out : out std_logic_vector(WB_DW-1 downto 0);
reg15_out : out std_logic_vector(WB_DW-1 downto 0);
reg16_out : out std_logic_vector(WB_DW-1 downto 0);
reg17_out : out std_logic_vector(WB_DW-1 downto 0);
reg18_out : out std_logic_vector(WB_DW-1 downto 0);
reg19_out : out std_logic_vector(WB_DW-1 downto 0);
reg20_out : out std_logic_vector(WB_DW-1 downto 0);
reg21_out : out std_logic_vector(WB_DW-1 downto 0);
reg22_out : out std_logic_vector(WB_DW-1 downto 0);
reg23_out : out std_logic_vector(WB_DW-1 downto 0);
reg24_out : out std_logic_vector(WB_DW-1 downto 0);
reg25_out : out std_logic_vector(WB_DW-1 downto 0);
reg26_out : out std_logic_vector(WB_DW-1 downto 0);
reg27_out : out std_logic_vector(WB_DW-1 downto 0);
reg28_out : out std_logic_vector(WB_DW-1 downto 0);
reg29_out : out std_logic_vector(WB_DW-1 downto 0);
reg30_out : out std_logic_vector(WB_DW-1 downto 0);
reg31_out : out std_logic_vector(WB_DW-1 downto 0);
reg32_out : out std_logic_vector(WB_DW-1 downto 0);
reg33_out : out std_logic_vector(WB_DW-1 downto 0);
reg34_out : out std_logic_vector(WB_DW-1 downto 0);
reg35_out : out std_logic_vector(WB_DW-1 downto 0);
reg36_out : out std_logic_vector(WB_DW-1 downto 0);
reg37_out : out std_logic_vector(WB_DW-1 downto 0);
reg38_out : out std_logic_vector(WB_DW-1 downto 0);
reg39_out : out std_logic_vector(WB_DW-1 downto 0);
reg40_out : out std_logic_vector(WB_DW-1 downto 0);
reg41_out : out std_logic_vector(WB_DW-1 downto 0);
reg42_out : out std_logic_vector(WB_DW-1 downto 0);
reg43_out : out std_logic_vector(WB_DW-1 downto 0);
reg44_out : out std_logic_vector(WB_DW-1 downto 0);
reg45_out : out std_logic_vector(WB_DW-1 downto 0);
reg46_out : out std_logic_vector(WB_DW-1 downto 0);
reg47_out : out std_logic_vector(WB_DW-1 downto 0);
reg48_out : out std_logic_vector(WB_DW-1 downto 0);
reg49_out : out std_logic_vector(WB_DW-1 downto 0);
reg50_out : out std_logic_vector(WB_DW-1 downto 0);
reg51_out : out std_logic_vector(WB_DW-1 downto 0);
reg52_out : out std_logic_vector(WB_DW-1 downto 0);
reg53_out : out std_logic_vector(WB_DW-1 downto 0);
reg54_out : out std_logic_vector(WB_DW-1 downto 0);
reg55_out : out std_logic_vector(WB_DW-1 downto 0);
reg56_out : out std_logic_vector(WB_DW-1 downto 0);
reg57_out : out std_logic_vector(WB_DW-1 downto 0);
reg58_out : out std_logic_vector(WB_DW-1 downto 0);
reg59_out : out std_logic_vector(WB_DW-1 downto 0);
reg60_out : out std_logic_vector(WB_DW-1 downto 0);
reg61_out : out std_logic_vector(WB_DW-1 downto 0);
reg62_out : out std_logic_vector(WB_DW-1 downto 0);
reg63_out : out std_logic_vector(WB_DW-1 downto 0);
reg64_out : out std_logic_vector(WB_DW-1 downto 0);
reg65_out : out std_logic_vector(WB_DW-1 downto 0);
reg66_out : out std_logic_vector(WB_DW-1 downto 0);
reg67_out : out std_logic_vector(WB_DW-1 downto 0);
reg68_out : out std_logic_vector(WB_DW-1 downto 0);
reg69_out : out std_logic_vector(WB_DW-1 downto 0);
reg70_out : out std_logic_vector(WB_DW-1 downto 0);
reg71_out : out std_logic_vector(WB_DW-1 downto 0);
reg72_out : out std_logic_vector(WB_DW-1 downto 0);
reg73_out : out std_logic_vector(WB_DW-1 downto 0);
reg74_out : out std_logic_vector(WB_DW-1 downto 0);
reg75_out : out std_logic_vector(WB_DW-1 downto 0);
reg76_out : out std_logic_vector(WB_DW-1 downto 0);
reg77_out : out std_logic_vector(WB_DW-1 downto 0);
reg78_out : out std_logic_vector(WB_DW-1 downto 0);
reg79_out : out std_logic_vector(WB_DW-1 downto 0);
reg80_out : out std_logic_vector(WB_DW-1 downto 0);
reg81_out : out std_logic_vector(WB_DW-1 downto 0);
reg82_out : out std_logic_vector(WB_DW-1 downto 0);
reg83_out : out std_logic_vector(WB_DW-1 downto 0);
reg84_out : out std_logic_vector(WB_DW-1 downto 0);
reg85_out : out std_logic_vector(WB_DW-1 downto 0);
reg86_out : out std_logic_vector(WB_DW-1 downto 0);
reg87_out : out std_logic_vector(WB_DW-1 downto 0);
reg88_out : out std_logic_vector(WB_DW-1 downto 0);
reg89_out : out std_logic_vector(WB_DW-1 downto 0);
reg90_out : out std_logic_vector(WB_DW-1 downto 0);
reg91_out : out std_logic_vector(WB_DW-1 downto 0);
reg92_out : out std_logic_vector(WB_DW-1 downto 0);
reg93_out : out std_logic_vector(WB_DW-1 downto 0);
reg94_out : out std_logic_vector(WB_DW-1 downto 0);
reg95_out : out std_logic_vector(WB_DW-1 downto 0);
reg96_out : out std_logic_vector(WB_DW-1 downto 0);
reg97_out : out std_logic_vector(WB_DW-1 downto 0);
reg98_out : out std_logic_vector(WB_DW-1 downto 0);
reg99_out : out std_logic_vector(WB_DW-1 downto 0);
reg100_out : out std_logic_vector(WB_DW-1 downto 0);
reg101_out : out std_logic_vector(WB_DW-1 downto 0);
reg102_out : out std_logic_vector(WB_DW-1 downto 0);
reg103_out : out std_logic_vector(WB_DW-1 downto 0);
reg104_out : out std_logic_vector(WB_DW-1 downto 0);
reg105_out : out std_logic_vector(WB_DW-1 downto 0);
reg106_out : out std_logic_vector(WB_DW-1 downto 0);
reg107_out : out std_logic_vector(WB_DW-1 downto 0);
reg108_out : out std_logic_vector(WB_DW-1 downto 0);
reg109_out : out std_logic_vector(WB_DW-1 downto 0);
reg110_out : out std_logic_vector(WB_DW-1 downto 0);
reg111_out : out std_logic_vector(WB_DW-1 downto 0);
reg112_out : out std_logic_vector(WB_DW-1 downto 0);
reg113_out : out std_logic_vector(WB_DW-1 downto 0);
reg114_out : out std_logic_vector(WB_DW-1 downto 0);
reg115_out : out std_logic_vector(WB_DW-1 downto 0);
reg116_out : out std_logic_vector(WB_DW-1 downto 0);
reg117_out : out std_logic_vector(WB_DW-1 downto 0);
reg118_out : out std_logic_vector(WB_DW-1 downto 0);
reg119_out : out std_logic_vector(WB_DW-1 downto 0);
reg120_out : out std_logic_vector(WB_DW-1 downto 0);
reg121_out : out std_logic_vector(WB_DW-1 downto 0);
reg122_out : out std_logic_vector(WB_DW-1 downto 0);
reg123_out : out std_logic_vector(WB_DW-1 downto 0);
reg124_out : out std_logic_vector(WB_DW-1 downto 0);
reg125_out : out std_logic_vector(WB_DW-1 downto 0);
reg126_out : out std_logic_vector(WB_DW-1 downto 0);
reg127_out : out std_logic_vector(WB_DW-1 downto 0);
reg128_out : out std_logic_vector(WB_DW-1 downto 0);
reg129_out : out std_logic_vector(WB_DW-1 downto 0);
reg130_out : out std_logic_vector(WB_DW-1 downto 0);
reg131_out : out std_logic_vector(WB_DW-1 downto 0);
reg132_out : out std_logic_vector(WB_DW-1 downto 0);
reg133_out : out std_logic_vector(WB_DW-1 downto 0);
reg134_out : out std_logic_vector(WB_DW-1 downto 0);
reg135_out : out std_logic_vector(WB_DW-1 downto 0);
reg136_out : out std_logic_vector(WB_DW-1 downto 0);
reg137_out : out std_logic_vector(WB_DW-1 downto 0);
reg138_out : out std_logic_vector(WB_DW-1 downto 0);
reg139_out : out std_logic_vector(WB_DW-1 downto 0);
reg140_out : out std_logic_vector(WB_DW-1 downto 0);
reg141_out : out std_logic_vector(WB_DW-1 downto 0);
reg142_out : out std_logic_vector(WB_DW-1 downto 0);
reg143_out : out std_logic_vector(WB_DW-1 downto 0);
reg144_out : out std_logic_vector(WB_DW-1 downto 0);
reg145_out : out std_logic_vector(WB_DW-1 downto 0);
reg146_out : out std_logic_vector(WB_DW-1 downto 0);
reg147_out : out std_logic_vector(WB_DW-1 downto 0);
reg148_out : out std_logic_vector(WB_DW-1 downto 0);
reg149_out : out std_logic_vector(WB_DW-1 downto 0);
reg150_out : out std_logic_vector(WB_DW-1 downto 0);
reg151_out : out std_logic_vector(WB_DW-1 downto 0);
reg152_out : out std_logic_vector(WB_DW-1 downto 0);
reg153_out : out std_logic_vector(WB_DW-1 downto 0);
reg154_out : out std_logic_vector(WB_DW-1 downto 0);
reg155_out : out std_logic_vector(WB_DW-1 downto 0);
reg156_out : out std_logic_vector(WB_DW-1 downto 0);
reg157_out : out std_logic_vector(WB_DW-1 downto 0);
reg158_out : out std_logic_vector(WB_DW-1 downto 0);
reg159_out : out std_logic_vector(WB_DW-1 downto 0);
reg160_out : out std_logic_vector(WB_DW-1 downto 0);
reg161_out : out std_logic_vector(WB_DW-1 downto 0);
reg162_out : out std_logic_vector(WB_DW-1 downto 0);
reg163_out : out std_logic_vector(WB_DW-1 downto 0);
reg164_out : out std_logic_vector(WB_DW-1 downto 0);
reg165_out : out std_logic_vector(WB_DW-1 downto 0);
reg166_out : out std_logic_vector(WB_DW-1 downto 0);
reg167_out : out std_logic_vector(WB_DW-1 downto 0);
reg168_out : out std_logic_vector(WB_DW-1 downto 0);
reg169_out : out std_logic_vector(WB_DW-1 downto 0);
reg170_out : out std_logic_vector(WB_DW-1 downto 0);
reg171_out : out std_logic_vector(WB_DW-1 downto 0);
reg172_out : out std_logic_vector(WB_DW-1 downto 0);
reg173_out : out std_logic_vector(WB_DW-1 downto 0);
reg174_out : out std_logic_vector(WB_DW-1 downto 0);
reg175_out : out std_logic_vector(WB_DW-1 downto 0);
reg176_out : out std_logic_vector(WB_DW-1 downto 0);
reg177_out : out std_logic_vector(WB_DW-1 downto 0);
reg178_out : out std_logic_vector(WB_DW-1 downto 0);
reg179_out : out std_logic_vector(WB_DW-1 downto 0);
reg180_out : out std_logic_vector(WB_DW-1 downto 0);
reg181_out : out std_logic_vector(WB_DW-1 downto 0);
reg182_out : out std_logic_vector(WB_DW-1 downto 0);
reg183_out : out std_logic_vector(WB_DW-1 downto 0);
reg184_out : out std_logic_vector(WB_DW-1 downto 0);
reg185_out : out std_logic_vector(WB_DW-1 downto 0);
reg186_out : out std_logic_vector(WB_DW-1 downto 0);
reg187_out : out std_logic_vector(WB_DW-1 downto 0);
reg188_out : out std_logic_vector(WB_DW-1 downto 0);
reg189_out : out std_logic_vector(WB_DW-1 downto 0);
reg190_out : out std_logic_vector(WB_DW-1 downto 0);
reg191_out : out std_logic_vector(WB_DW-1 downto 0);
reg192_out : out std_logic_vector(WB_DW-1 downto 0);
reg193_out : out std_logic_vector(WB_DW-1 downto 0);
reg194_out : out std_logic_vector(WB_DW-1 downto 0);
reg195_out : out std_logic_vector(WB_DW-1 downto 0);
reg196_out : out std_logic_vector(WB_DW-1 downto 0);
reg197_out : out std_logic_vector(WB_DW-1 downto 0);
reg198_out : out std_logic_vector(WB_DW-1 downto 0);
reg199_out : out std_logic_vector(WB_DW-1 downto 0);
reg200_out : out std_logic_vector(WB_DW-1 downto 0);
reg201_out : out std_logic_vector(WB_DW-1 downto 0);
reg202_out : out std_logic_vector(WB_DW-1 downto 0);
reg203_out : out std_logic_vector(WB_DW-1 downto 0);
reg204_out : out std_logic_vector(WB_DW-1 downto 0);
reg205_out : out std_logic_vector(WB_DW-1 downto 0);
reg206_out : out std_logic_vector(WB_DW-1 downto 0);
reg207_out : out std_logic_vector(WB_DW-1 downto 0);
reg208_out : out std_logic_vector(WB_DW-1 downto 0);
reg209_out : out std_logic_vector(WB_DW-1 downto 0);
reg210_out : out std_logic_vector(WB_DW-1 downto 0);
reg211_out : out std_logic_vector(WB_DW-1 downto 0);
reg212_out : out std_logic_vector(WB_DW-1 downto 0);
reg213_out : out std_logic_vector(WB_DW-1 downto 0);
reg214_out : out std_logic_vector(WB_DW-1 downto 0);
reg215_out : out std_logic_vector(WB_DW-1 downto 0);
reg216_out : out std_logic_vector(WB_DW-1 downto 0);
reg217_out : out std_logic_vector(WB_DW-1 downto 0);
reg218_out : out std_logic_vector(WB_DW-1 downto 0);
reg219_out : out std_logic_vector(WB_DW-1 downto 0);
reg220_out : out std_logic_vector(WB_DW-1 downto 0);
reg221_out : out std_logic_vector(WB_DW-1 downto 0);
reg222_out : out std_logic_vector(WB_DW-1 downto 0);
reg223_out : out std_logic_vector(WB_DW-1 downto 0);
reg224_out : out std_logic_vector(WB_DW-1 downto 0);
reg225_out : out std_logic_vector(WB_DW-1 downto 0);
reg226_out : out std_logic_vector(WB_DW-1 downto 0);
reg227_out : out std_logic_vector(WB_DW-1 downto 0);
reg228_out : out std_logic_vector(WB_DW-1 downto 0);
reg229_out : out std_logic_vector(WB_DW-1 downto 0);
reg230_out : out std_logic_vector(WB_DW-1 downto 0);
reg231_out : out std_logic_vector(WB_DW-1 downto 0);
reg232_out : out std_logic_vector(WB_DW-1 downto 0);
reg233_out : out std_logic_vector(WB_DW-1 downto 0);
reg234_out : out std_logic_vector(WB_DW-1 downto 0);
reg235_out : out std_logic_vector(WB_DW-1 downto 0);
reg236_out : out std_logic_vector(WB_DW-1 downto 0);
reg237_out : out std_logic_vector(WB_DW-1 downto 0);
reg238_out : out std_logic_vector(WB_DW-1 downto 0);
reg239_out : out std_logic_vector(WB_DW-1 downto 0);
reg240_out : out std_logic_vector(WB_DW-1 downto 0);
reg241_out : out std_logic_vector(WB_DW-1 downto 0);
reg242_out : out std_logic_vector(WB_DW-1 downto 0);
reg243_out : out std_logic_vector(WB_DW-1 downto 0);
reg244_out : out std_logic_vector(WB_DW-1 downto 0);
reg245_out : out std_logic_vector(WB_DW-1 downto 0);
reg246_out : out std_logic_vector(WB_DW-1 downto 0);
reg247_out : out std_logic_vector(WB_DW-1 downto 0);
reg248_out : out std_logic_vector(WB_DW-1 downto 0);
reg249_out : out std_logic_vector(WB_DW-1 downto 0);
reg250_out : out std_logic_vector(WB_DW-1 downto 0);
reg251_out : out std_logic_vector(WB_DW-1 downto 0);
reg252_out : out std_logic_vector(WB_DW-1 downto 0);
reg253_out : out std_logic_vector(WB_DW-1 downto 0);
reg254_out : out std_logic_vector(WB_DW-1 downto 0);
reg255_out : out std_logic_vector(WB_DW-1 downto 0);
-- wishbone interface
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type
);
end wbs256;
-------------------------------------------------------------------------------
architecture behavioral of wbs256 is
-------------------------------------------------------------------------------
----------------------------------------------
-- register addresses
----------------------------------------------
constant REG0_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"00";
constant REG1_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"01";
constant REG2_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"02";
constant REG3_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"03";
constant REG4_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"04";
constant REG5_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"05";
constant REG6_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"06";
constant REG7_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"07";
constant REG8_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"08";
constant REG9_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"09";
constant REG10_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"0A";
constant REG11_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"0B";
constant REG12_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"0C";
constant REG13_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"0D";
constant REG14_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"0E";
constant REG15_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"0F";
constant REG16_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"10";
constant REG17_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"11";
constant REG18_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"12";
constant REG19_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"13";
constant REG20_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"14";
constant REG21_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"15";
constant REG22_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"16";
constant REG23_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"17";
constant REG24_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"18";
constant REG25_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"19";
constant REG26_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"1A";
constant REG27_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"1B";
constant REG28_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"1C";
constant REG29_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"1D";
constant REG30_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"1E";
constant REG31_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"1F";
constant REG32_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"20";
constant REG33_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"21";
constant REG34_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"22";
constant REG35_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"23";
constant REG36_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"24";
constant REG37_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"25";
constant REG38_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"26";
constant REG39_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"27";
constant REG40_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"28";
constant REG41_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"29";
constant REG42_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"2A";
constant REG43_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"2B";
constant REG44_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"2C";
constant REG45_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"2D";
constant REG46_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"2E";
constant REG47_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"2F";
constant REG48_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"30";
constant REG49_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"31";
constant REG50_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"32";
constant REG51_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"33";
constant REG52_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"34";
constant REG53_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"35";
constant REG54_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"36";
constant REG55_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"37";
constant REG56_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"38";
constant REG57_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"39";
constant REG58_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"3A";
constant REG59_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"3B";
constant REG60_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"3C";
constant REG61_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"3D";
constant REG62_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"3E";
constant REG63_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"3F";
constant REG64_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"40";
constant REG65_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"41";
constant REG66_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"42";
constant REG67_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"43";
constant REG68_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"44";
constant REG69_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"45";
constant REG70_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"46";
constant REG71_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"47";
constant REG72_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"48";
constant REG73_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"49";
constant REG74_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"4A";
constant REG75_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"4B";
constant REG76_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"4C";
constant REG77_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"4D";
constant REG78_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"4E";
constant REG79_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"4F";
constant REG80_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"50";
constant REG81_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"51";
constant REG82_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"52";
constant REG83_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"53";
constant REG84_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"54";
constant REG85_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"55";
constant REG86_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"56";
constant REG87_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"57";
constant REG88_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"58";
constant REG89_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"59";
constant REG90_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"5A";
constant REG91_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"5B";
constant REG92_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"5C";
constant REG93_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"5D";
constant REG94_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"5E";
constant REG95_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"5F";
constant REG96_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"60";
constant REG97_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"61";
constant REG98_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"62";
constant REG99_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"63";
constant REG100_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"64";
constant REG101_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"65";
constant REG102_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"66";
constant REG103_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"67";
constant REG104_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"68";
constant REG105_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"69";
constant REG106_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"6A";
constant REG107_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"6B";
constant REG108_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"6C";
constant REG109_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"6D";
constant REG110_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"6E";
constant REG111_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"6F";
constant REG112_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"70";
constant REG113_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"71";
constant REG114_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"72";
constant REG115_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"73";
constant REG116_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"74";
constant REG117_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"75";
constant REG118_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"76";
constant REG119_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"77";
constant REG120_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"78";
constant REG121_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"79";
constant REG122_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"7A";
constant REG123_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"7B";
constant REG124_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"7C";
constant REG125_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"7D";
constant REG126_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"7E";
constant REG127_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"7F";
constant REG128_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"80";
constant REG129_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"81";
constant REG130_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"82";
constant REG131_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"83";
constant REG132_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"84";
constant REG133_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"85";
constant REG134_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"86";
constant REG135_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"87";
constant REG136_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"88";
constant REG137_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"89";
constant REG138_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"8A";
constant REG139_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"8B";
constant REG140_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"8C";
constant REG141_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"8D";
constant REG142_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"8E";
constant REG143_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"8F";
constant REG144_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"90";
constant REG145_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"91";
constant REG146_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"92";
constant REG147_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"93";
constant REG148_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"94";
constant REG149_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"95";
constant REG150_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"96";
constant REG151_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"97";
constant REG152_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"98";
constant REG153_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"99";
constant REG154_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"9A";
constant REG155_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"9B";
constant REG156_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"9C";
constant REG157_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"9D";
constant REG158_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"9E";
constant REG159_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"9F";
constant REG160_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A0";
constant REG161_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A1";
constant REG162_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A2";
constant REG163_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A3";
constant REG164_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A4";
constant REG165_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A5";
constant REG166_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A6";
constant REG167_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A7";
constant REG168_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A8";
constant REG169_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"A9";
constant REG170_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"AA";
constant REG171_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"AB";
constant REG172_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"AC";
constant REG173_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"AD";
constant REG174_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"AE";
constant REG175_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"AF";
constant REG176_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B0";
constant REG177_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B1";
constant REG178_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B2";
constant REG179_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B3";
constant REG180_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B4";
constant REG181_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B5";
constant REG182_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B6";
constant REG183_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B7";
constant REG184_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B8";
constant REG185_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"B9";
constant REG186_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"BA";
constant REG187_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"BB";
constant REG188_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"BC";
constant REG189_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"BD";
constant REG190_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"BE";
constant REG191_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"BF";
constant REG192_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C0";
constant REG193_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C1";
constant REG194_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C2";
constant REG195_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C3";
constant REG196_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C4";
constant REG197_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C5";
constant REG198_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C6";
constant REG199_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C7";
constant REG200_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C8";
constant REG201_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"C9";
constant REG202_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"CA";
constant REG203_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"CB";
constant REG204_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"CC";
constant REG205_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"CD";
constant REG206_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"CE";
constant REG207_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"CF";
constant REG208_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D0";
constant REG209_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D1";
constant REG210_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D2";
constant REG211_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D3";
constant REG212_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D4";
constant REG213_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D5";
constant REG214_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D6";
constant REG215_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D7";
constant REG216_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D8";
constant REG217_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"D9";
constant REG218_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"DA";
constant REG219_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"DB";
constant REG220_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"DC";
constant REG221_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"DD";
constant REG222_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"DE";
constant REG223_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"DF";
constant REG224_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E0";
constant REG225_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E1";
constant REG226_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E2";
constant REG227_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E3";
constant REG228_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E4";
constant REG229_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E5";
constant REG230_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E6";
constant REG231_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E7";
constant REG232_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E8";
constant REG233_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"E9";
constant REG234_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"EA";
constant REG235_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"EB";
constant REG236_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"EC";
constant REG237_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"ED";
constant REG238_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"EE";
constant REG239_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"EF";
constant REG240_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F0";
constant REG241_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F1";
constant REG242_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F2";
constant REG243_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F3";
constant REG244_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F4";
constant REG245_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F5";
constant REG246_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F6";
constant REG247_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F7";
constant REG248_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F8";
constant REG249_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"F9";
constant REG250_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"FA";
constant REG251_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"FB";
constant REG252_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"FC";
constant REG253_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"FD";
constant REG254_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"FE";
constant REG255_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"FF";
----------------------------------------------
-- signals
----------------------------------------------
signal reg_out_s, reg_in_s : reg_wbs256_t;
signal reg0_adr_match_s, reg1_adr_match_s, reg2_adr_match_s, reg3_adr_match_s, reg4_adr_match_s, reg5_adr_match_s, reg6_adr_match_s, reg7_adr_match_s, reg8_adr_match_s, reg9_adr_match_s, reg10_adr_match_s, reg11_adr_match_s, reg12_adr_match_s, reg13_adr_match_s, reg14_adr_match_s, reg15_adr_match_s, reg16_adr_match_s, reg17_adr_match_s, reg18_adr_match_s, reg19_adr_match_s, reg20_adr_match_s, reg21_adr_match_s, reg22_adr_match_s, reg23_adr_match_s, reg24_adr_match_s, reg25_adr_match_s, reg26_adr_match_s, reg27_adr_match_s, reg28_adr_match_s, reg29_adr_match_s, reg30_adr_match_s, reg31_adr_match_s, reg32_adr_match_s, reg33_adr_match_s, reg34_adr_match_s, reg35_adr_match_s, reg36_adr_match_s, reg37_adr_match_s, reg38_adr_match_s, reg39_adr_match_s, reg40_adr_match_s, reg41_adr_match_s, reg42_adr_match_s, reg43_adr_match_s, reg44_adr_match_s, reg45_adr_match_s, reg46_adr_match_s, reg47_adr_match_s, reg48_adr_match_s, reg49_adr_match_s, reg50_adr_match_s, reg51_adr_match_s, reg52_adr_match_s, reg53_adr_match_s, reg54_adr_match_s, reg55_adr_match_s, reg56_adr_match_s, reg57_adr_match_s, reg58_adr_match_s, reg59_adr_match_s, reg60_adr_match_s, reg61_adr_match_s, reg62_adr_match_s, reg63_adr_match_s, reg64_adr_match_s, reg65_adr_match_s, reg66_adr_match_s, reg67_adr_match_s, reg68_adr_match_s, reg69_adr_match_s, reg70_adr_match_s, reg71_adr_match_s, reg72_adr_match_s, reg73_adr_match_s, reg74_adr_match_s, reg75_adr_match_s, reg76_adr_match_s, reg77_adr_match_s, reg78_adr_match_s, reg79_adr_match_s, reg80_adr_match_s, reg81_adr_match_s, reg82_adr_match_s, reg83_adr_match_s, reg84_adr_match_s, reg85_adr_match_s, reg86_adr_match_s, reg87_adr_match_s, reg88_adr_match_s, reg89_adr_match_s, reg90_adr_match_s, reg91_adr_match_s, reg92_adr_match_s, reg93_adr_match_s, reg94_adr_match_s, reg95_adr_match_s, reg96_adr_match_s, reg97_adr_match_s, reg98_adr_match_s, reg99_adr_match_s, reg100_adr_match_s, reg101_adr_match_s, reg102_adr_match_s, reg103_adr_match_s, reg104_adr_match_s, reg105_adr_match_s, reg106_adr_match_s, reg107_adr_match_s, reg108_adr_match_s, reg109_adr_match_s, reg110_adr_match_s, reg111_adr_match_s, reg112_adr_match_s, reg113_adr_match_s, reg114_adr_match_s, reg115_adr_match_s, reg116_adr_match_s, reg117_adr_match_s, reg118_adr_match_s, reg119_adr_match_s, reg120_adr_match_s, reg121_adr_match_s, reg122_adr_match_s, reg123_adr_match_s, reg124_adr_match_s, reg125_adr_match_s, reg126_adr_match_s, reg127_adr_match_s, reg128_adr_match_s, reg129_adr_match_s, reg130_adr_match_s, reg131_adr_match_s, reg132_adr_match_s, reg133_adr_match_s, reg134_adr_match_s, reg135_adr_match_s, reg136_adr_match_s, reg137_adr_match_s, reg138_adr_match_s, reg139_adr_match_s, reg140_adr_match_s, reg141_adr_match_s, reg142_adr_match_s, reg143_adr_match_s, reg144_adr_match_s, reg145_adr_match_s, reg146_adr_match_s, reg147_adr_match_s, reg148_adr_match_s, reg149_adr_match_s, reg150_adr_match_s, reg151_adr_match_s, reg152_adr_match_s, reg153_adr_match_s, reg154_adr_match_s, reg155_adr_match_s, reg156_adr_match_s, reg157_adr_match_s, reg158_adr_match_s, reg159_adr_match_s, reg160_adr_match_s, reg161_adr_match_s, reg162_adr_match_s, reg163_adr_match_s, reg164_adr_match_s, reg165_adr_match_s, reg166_adr_match_s, reg167_adr_match_s, reg168_adr_match_s, reg169_adr_match_s, reg170_adr_match_s, reg171_adr_match_s, reg172_adr_match_s, reg173_adr_match_s, reg174_adr_match_s, reg175_adr_match_s, reg176_adr_match_s, reg177_adr_match_s, reg178_adr_match_s, reg179_adr_match_s, reg180_adr_match_s, reg181_adr_match_s, reg182_adr_match_s, reg183_adr_match_s, reg184_adr_match_s, reg185_adr_match_s, reg186_adr_match_s, reg187_adr_match_s, reg188_adr_match_s, reg189_adr_match_s, reg190_adr_match_s, reg191_adr_match_s, reg192_adr_match_s, reg193_adr_match_s, reg194_adr_match_s, reg195_adr_match_s, reg196_adr_match_s, reg197_adr_match_s, reg198_adr_match_s, reg199_adr_match_s, reg200_adr_match_s, reg201_adr_match_s, reg202_adr_match_s, reg203_adr_match_s, reg204_adr_match_s, reg205_adr_match_s, reg206_adr_match_s, reg207_adr_match_s, reg208_adr_match_s, reg209_adr_match_s, reg210_adr_match_s, reg211_adr_match_s, reg212_adr_match_s, reg213_adr_match_s, reg214_adr_match_s, reg215_adr_match_s, reg216_adr_match_s, reg217_adr_match_s, reg218_adr_match_s, reg219_adr_match_s, reg220_adr_match_s, reg221_adr_match_s, reg222_adr_match_s, reg223_adr_match_s, reg224_adr_match_s, reg225_adr_match_s, reg226_adr_match_s, reg227_adr_match_s, reg228_adr_match_s, reg229_adr_match_s, reg230_adr_match_s, reg231_adr_match_s, reg232_adr_match_s, reg233_adr_match_s, reg234_adr_match_s, reg235_adr_match_s, reg236_adr_match_s, reg237_adr_match_s, reg238_adr_match_s, reg239_adr_match_s, reg240_adr_match_s, reg241_adr_match_s, reg242_adr_match_s, reg243_adr_match_s, reg244_adr_match_s, reg245_adr_match_s, reg246_adr_match_s, reg247_adr_match_s, reg248_adr_match_s, reg249_adr_match_s, reg250_adr_match_s, reg251_adr_match_s, reg252_adr_match_s, reg253_adr_match_s, reg254_adr_match_s, reg255_adr_match_s : std_logic;
signal reg0_re_s, reg1_re_s, reg2_re_s, reg3_re_s, reg4_re_s, reg5_re_s, reg6_re_s, reg7_re_s, reg8_re_s, reg9_re_s, reg10_re_s, reg11_re_s, reg12_re_s, reg13_re_s, reg14_re_s, reg15_re_s, reg16_re_s, reg17_re_s, reg18_re_s, reg19_re_s, reg20_re_s, reg21_re_s, reg22_re_s, reg23_re_s, reg24_re_s, reg25_re_s, reg26_re_s, reg27_re_s, reg28_re_s, reg29_re_s, reg30_re_s, reg31_re_s, reg32_re_s, reg33_re_s, reg34_re_s, reg35_re_s, reg36_re_s, reg37_re_s, reg38_re_s, reg39_re_s, reg40_re_s, reg41_re_s, reg42_re_s, reg43_re_s, reg44_re_s, reg45_re_s, reg46_re_s, reg47_re_s, reg48_re_s, reg49_re_s, reg50_re_s, reg51_re_s, reg52_re_s, reg53_re_s, reg54_re_s, reg55_re_s, reg56_re_s, reg57_re_s, reg58_re_s, reg59_re_s, reg60_re_s, reg61_re_s, reg62_re_s, reg63_re_s, reg64_re_s, reg65_re_s, reg66_re_s, reg67_re_s, reg68_re_s, reg69_re_s, reg70_re_s, reg71_re_s, reg72_re_s, reg73_re_s, reg74_re_s, reg75_re_s, reg76_re_s, reg77_re_s, reg78_re_s, reg79_re_s, reg80_re_s, reg81_re_s, reg82_re_s, reg83_re_s, reg84_re_s, reg85_re_s, reg86_re_s, reg87_re_s, reg88_re_s, reg89_re_s, reg90_re_s, reg91_re_s, reg92_re_s, reg93_re_s, reg94_re_s, reg95_re_s, reg96_re_s, reg97_re_s, reg98_re_s, reg99_re_s, reg100_re_s, reg101_re_s, reg102_re_s, reg103_re_s, reg104_re_s, reg105_re_s, reg106_re_s, reg107_re_s, reg108_re_s, reg109_re_s, reg110_re_s, reg111_re_s, reg112_re_s, reg113_re_s, reg114_re_s, reg115_re_s, reg116_re_s, reg117_re_s, reg118_re_s, reg119_re_s, reg120_re_s, reg121_re_s, reg122_re_s, reg123_re_s, reg124_re_s, reg125_re_s, reg126_re_s, reg127_re_s, reg128_re_s, reg129_re_s, reg130_re_s, reg131_re_s, reg132_re_s, reg133_re_s, reg134_re_s, reg135_re_s, reg136_re_s, reg137_re_s, reg138_re_s, reg139_re_s, reg140_re_s, reg141_re_s, reg142_re_s, reg143_re_s, reg144_re_s, reg145_re_s, reg146_re_s, reg147_re_s, reg148_re_s, reg149_re_s, reg150_re_s, reg151_re_s, reg152_re_s, reg153_re_s, reg154_re_s, reg155_re_s, reg156_re_s, reg157_re_s, reg158_re_s, reg159_re_s, reg160_re_s, reg161_re_s, reg162_re_s, reg163_re_s, reg164_re_s, reg165_re_s, reg166_re_s, reg167_re_s, reg168_re_s, reg169_re_s, reg170_re_s, reg171_re_s, reg172_re_s, reg173_re_s, reg174_re_s, reg175_re_s, reg176_re_s, reg177_re_s, reg178_re_s, reg179_re_s, reg180_re_s, reg181_re_s, reg182_re_s, reg183_re_s, reg184_re_s, reg185_re_s, reg186_re_s, reg187_re_s, reg188_re_s, reg189_re_s, reg190_re_s, reg191_re_s, reg192_re_s, reg193_re_s, reg194_re_s, reg195_re_s, reg196_re_s, reg197_re_s, reg198_re_s, reg199_re_s, reg200_re_s, reg201_re_s, reg202_re_s, reg203_re_s, reg204_re_s, reg205_re_s, reg206_re_s, reg207_re_s, reg208_re_s, reg209_re_s, reg210_re_s, reg211_re_s, reg212_re_s, reg213_re_s, reg214_re_s, reg215_re_s, reg216_re_s, reg217_re_s, reg218_re_s, reg219_re_s, reg220_re_s, reg221_re_s, reg222_re_s, reg223_re_s, reg224_re_s, reg225_re_s, reg226_re_s, reg227_re_s, reg228_re_s, reg229_re_s, reg230_re_s, reg231_re_s, reg232_re_s, reg233_re_s, reg234_re_s, reg235_re_s, reg236_re_s, reg237_re_s, reg238_re_s, reg239_re_s, reg240_re_s, reg241_re_s, reg242_re_s, reg243_re_s, reg244_re_s, reg245_re_s, reg246_re_s, reg247_re_s, reg248_re_s, reg249_re_s, reg250_re_s, reg251_re_s, reg252_re_s, reg253_re_s, reg254_re_s, reg255_re_s : std_logic;
begin
-------------------------------------------------------------------------------
-- Concurrent
-------------------------------------------------------------------------------
-- register address decoder/comparator
reg0_adr_match_s <= '1' when wbs_in.adr = REG0_ADR else '0';
reg1_adr_match_s <= '1' when wbs_in.adr = REG1_ADR else '0';
reg2_adr_match_s <= '1' when wbs_in.adr = REG2_ADR else '0';
reg3_adr_match_s <= '1' when wbs_in.adr = REG3_ADR else '0';
reg4_adr_match_s <= '1' when wbs_in.adr = REG4_ADR else '0';
reg5_adr_match_s <= '1' when wbs_in.adr = REG5_ADR else '0';
reg6_adr_match_s <= '1' when wbs_in.adr = REG6_ADR else '0';
reg7_adr_match_s <= '1' when wbs_in.adr = REG7_ADR else '0';
reg8_adr_match_s <= '1' when wbs_in.adr = REG8_ADR else '0';
reg9_adr_match_s <= '1' when wbs_in.adr = REG9_ADR else '0';
reg10_adr_match_s <= '1' when wbs_in.adr = REG10_ADR else '0';
reg11_adr_match_s <= '1' when wbs_in.adr = REG11_ADR else '0';
reg12_adr_match_s <= '1' when wbs_in.adr = REG12_ADR else '0';
reg13_adr_match_s <= '1' when wbs_in.adr = REG13_ADR else '0';
reg14_adr_match_s <= '1' when wbs_in.adr = REG14_ADR else '0';
reg15_adr_match_s <= '1' when wbs_in.adr = REG15_ADR else '0';
reg16_adr_match_s <= '1' when wbs_in.adr = REG16_ADR else '0';
reg17_adr_match_s <= '1' when wbs_in.adr = REG17_ADR else '0';
reg18_adr_match_s <= '1' when wbs_in.adr = REG18_ADR else '0';
reg19_adr_match_s <= '1' when wbs_in.adr = REG19_ADR else '0';
reg20_adr_match_s <= '1' when wbs_in.adr = REG20_ADR else '0';
reg21_adr_match_s <= '1' when wbs_in.adr = REG21_ADR else '0';
reg22_adr_match_s <= '1' when wbs_in.adr = REG22_ADR else '0';
reg23_adr_match_s <= '1' when wbs_in.adr = REG23_ADR else '0';
reg24_adr_match_s <= '1' when wbs_in.adr = REG24_ADR else '0';
reg25_adr_match_s <= '1' when wbs_in.adr = REG25_ADR else '0';
reg26_adr_match_s <= '1' when wbs_in.adr = REG26_ADR else '0';
reg27_adr_match_s <= '1' when wbs_in.adr = REG27_ADR else '0';
reg28_adr_match_s <= '1' when wbs_in.adr = REG28_ADR else '0';
reg29_adr_match_s <= '1' when wbs_in.adr = REG29_ADR else '0';
reg30_adr_match_s <= '1' when wbs_in.adr = REG30_ADR else '0';
reg31_adr_match_s <= '1' when wbs_in.adr = REG31_ADR else '0';
reg32_adr_match_s <= '1' when wbs_in.adr = REG32_ADR else '0';
reg33_adr_match_s <= '1' when wbs_in.adr = REG33_ADR else '0';
reg34_adr_match_s <= '1' when wbs_in.adr = REG34_ADR else '0';
reg35_adr_match_s <= '1' when wbs_in.adr = REG35_ADR else '0';
reg36_adr_match_s <= '1' when wbs_in.adr = REG36_ADR else '0';
reg37_adr_match_s <= '1' when wbs_in.adr = REG37_ADR else '0';
reg38_adr_match_s <= '1' when wbs_in.adr = REG38_ADR else '0';
reg39_adr_match_s <= '1' when wbs_in.adr = REG39_ADR else '0';
reg40_adr_match_s <= '1' when wbs_in.adr = REG40_ADR else '0';
reg41_adr_match_s <= '1' when wbs_in.adr = REG41_ADR else '0';
reg42_adr_match_s <= '1' when wbs_in.adr = REG42_ADR else '0';
reg43_adr_match_s <= '1' when wbs_in.adr = REG43_ADR else '0';
reg44_adr_match_s <= '1' when wbs_in.adr = REG44_ADR else '0';
reg45_adr_match_s <= '1' when wbs_in.adr = REG45_ADR else '0';
reg46_adr_match_s <= '1' when wbs_in.adr = REG46_ADR else '0';
reg47_adr_match_s <= '1' when wbs_in.adr = REG47_ADR else '0';
reg48_adr_match_s <= '1' when wbs_in.adr = REG48_ADR else '0';
reg49_adr_match_s <= '1' when wbs_in.adr = REG49_ADR else '0';
reg50_adr_match_s <= '1' when wbs_in.adr = REG50_ADR else '0';
reg51_adr_match_s <= '1' when wbs_in.adr = REG51_ADR else '0';
reg52_adr_match_s <= '1' when wbs_in.adr = REG52_ADR else '0';
reg53_adr_match_s <= '1' when wbs_in.adr = REG53_ADR else '0';
reg54_adr_match_s <= '1' when wbs_in.adr = REG54_ADR else '0';
reg55_adr_match_s <= '1' when wbs_in.adr = REG55_ADR else '0';
reg56_adr_match_s <= '1' when wbs_in.adr = REG56_ADR else '0';
reg57_adr_match_s <= '1' when wbs_in.adr = REG57_ADR else '0';
reg58_adr_match_s <= '1' when wbs_in.adr = REG58_ADR else '0';
reg59_adr_match_s <= '1' when wbs_in.adr = REG59_ADR else '0';
reg60_adr_match_s <= '1' when wbs_in.adr = REG60_ADR else '0';
reg61_adr_match_s <= '1' when wbs_in.adr = REG61_ADR else '0';
reg62_adr_match_s <= '1' when wbs_in.adr = REG62_ADR else '0';
reg63_adr_match_s <= '1' when wbs_in.adr = REG63_ADR else '0';
reg64_adr_match_s <= '1' when wbs_in.adr = REG64_ADR else '0';
reg65_adr_match_s <= '1' when wbs_in.adr = REG65_ADR else '0';
reg66_adr_match_s <= '1' when wbs_in.adr = REG66_ADR else '0';
reg67_adr_match_s <= '1' when wbs_in.adr = REG67_ADR else '0';
reg68_adr_match_s <= '1' when wbs_in.adr = REG68_ADR else '0';
reg69_adr_match_s <= '1' when wbs_in.adr = REG69_ADR else '0';
reg70_adr_match_s <= '1' when wbs_in.adr = REG70_ADR else '0';
reg71_adr_match_s <= '1' when wbs_in.adr = REG71_ADR else '0';
reg72_adr_match_s <= '1' when wbs_in.adr = REG72_ADR else '0';
reg73_adr_match_s <= '1' when wbs_in.adr = REG73_ADR else '0';
reg74_adr_match_s <= '1' when wbs_in.adr = REG74_ADR else '0';
reg75_adr_match_s <= '1' when wbs_in.adr = REG75_ADR else '0';
reg76_adr_match_s <= '1' when wbs_in.adr = REG76_ADR else '0';
reg77_adr_match_s <= '1' when wbs_in.adr = REG77_ADR else '0';
reg78_adr_match_s <= '1' when wbs_in.adr = REG78_ADR else '0';
reg79_adr_match_s <= '1' when wbs_in.adr = REG79_ADR else '0';
reg80_adr_match_s <= '1' when wbs_in.adr = REG80_ADR else '0';
reg81_adr_match_s <= '1' when wbs_in.adr = REG81_ADR else '0';
reg82_adr_match_s <= '1' when wbs_in.adr = REG82_ADR else '0';
reg83_adr_match_s <= '1' when wbs_in.adr = REG83_ADR else '0';
reg84_adr_match_s <= '1' when wbs_in.adr = REG84_ADR else '0';
reg85_adr_match_s <= '1' when wbs_in.adr = REG85_ADR else '0';
reg86_adr_match_s <= '1' when wbs_in.adr = REG86_ADR else '0';
reg87_adr_match_s <= '1' when wbs_in.adr = REG87_ADR else '0';
reg88_adr_match_s <= '1' when wbs_in.adr = REG88_ADR else '0';
reg89_adr_match_s <= '1' when wbs_in.adr = REG89_ADR else '0';
reg90_adr_match_s <= '1' when wbs_in.adr = REG90_ADR else '0';
reg91_adr_match_s <= '1' when wbs_in.adr = REG91_ADR else '0';
reg92_adr_match_s <= '1' when wbs_in.adr = REG92_ADR else '0';
reg93_adr_match_s <= '1' when wbs_in.adr = REG93_ADR else '0';
reg94_adr_match_s <= '1' when wbs_in.adr = REG94_ADR else '0';
reg95_adr_match_s <= '1' when wbs_in.adr = REG95_ADR else '0';
reg96_adr_match_s <= '1' when wbs_in.adr = REG96_ADR else '0';
reg97_adr_match_s <= '1' when wbs_in.adr = REG97_ADR else '0';
reg98_adr_match_s <= '1' when wbs_in.adr = REG98_ADR else '0';
reg99_adr_match_s <= '1' when wbs_in.adr = REG99_ADR else '0';
reg100_adr_match_s <= '1' when wbs_in.adr = REG100_ADR else '0';
reg101_adr_match_s <= '1' when wbs_in.adr = REG101_ADR else '0';
reg102_adr_match_s <= '1' when wbs_in.adr = REG102_ADR else '0';
reg103_adr_match_s <= '1' when wbs_in.adr = REG103_ADR else '0';
reg104_adr_match_s <= '1' when wbs_in.adr = REG104_ADR else '0';
reg105_adr_match_s <= '1' when wbs_in.adr = REG105_ADR else '0';
reg106_adr_match_s <= '1' when wbs_in.adr = REG106_ADR else '0';
reg107_adr_match_s <= '1' when wbs_in.adr = REG107_ADR else '0';
reg108_adr_match_s <= '1' when wbs_in.adr = REG108_ADR else '0';
reg109_adr_match_s <= '1' when wbs_in.adr = REG109_ADR else '0';
reg110_adr_match_s <= '1' when wbs_in.adr = REG110_ADR else '0';
reg111_adr_match_s <= '1' when wbs_in.adr = REG111_ADR else '0';
reg112_adr_match_s <= '1' when wbs_in.adr = REG112_ADR else '0';
reg113_adr_match_s <= '1' when wbs_in.adr = REG113_ADR else '0';
reg114_adr_match_s <= '1' when wbs_in.adr = REG114_ADR else '0';
reg115_adr_match_s <= '1' when wbs_in.adr = REG115_ADR else '0';
reg116_adr_match_s <= '1' when wbs_in.adr = REG116_ADR else '0';
reg117_adr_match_s <= '1' when wbs_in.adr = REG117_ADR else '0';
reg118_adr_match_s <= '1' when wbs_in.adr = REG118_ADR else '0';
reg119_adr_match_s <= '1' when wbs_in.adr = REG119_ADR else '0';
reg120_adr_match_s <= '1' when wbs_in.adr = REG120_ADR else '0';
reg121_adr_match_s <= '1' when wbs_in.adr = REG121_ADR else '0';
reg122_adr_match_s <= '1' when wbs_in.adr = REG122_ADR else '0';
reg123_adr_match_s <= '1' when wbs_in.adr = REG123_ADR else '0';
reg124_adr_match_s <= '1' when wbs_in.adr = REG124_ADR else '0';
reg125_adr_match_s <= '1' when wbs_in.adr = REG125_ADR else '0';
reg126_adr_match_s <= '1' when wbs_in.adr = REG126_ADR else '0';
reg127_adr_match_s <= '1' when wbs_in.adr = REG127_ADR else '0';
reg128_adr_match_s <= '1' when wbs_in.adr = REG128_ADR else '0';
reg129_adr_match_s <= '1' when wbs_in.adr = REG129_ADR else '0';
reg130_adr_match_s <= '1' when wbs_in.adr = REG130_ADR else '0';
reg131_adr_match_s <= '1' when wbs_in.adr = REG131_ADR else '0';
reg132_adr_match_s <= '1' when wbs_in.adr = REG132_ADR else '0';
reg133_adr_match_s <= '1' when wbs_in.adr = REG133_ADR else '0';
reg134_adr_match_s <= '1' when wbs_in.adr = REG134_ADR else '0';
reg135_adr_match_s <= '1' when wbs_in.adr = REG135_ADR else '0';
reg136_adr_match_s <= '1' when wbs_in.adr = REG136_ADR else '0';
reg137_adr_match_s <= '1' when wbs_in.adr = REG137_ADR else '0';
reg138_adr_match_s <= '1' when wbs_in.adr = REG138_ADR else '0';
reg139_adr_match_s <= '1' when wbs_in.adr = REG139_ADR else '0';
reg140_adr_match_s <= '1' when wbs_in.adr = REG140_ADR else '0';
reg141_adr_match_s <= '1' when wbs_in.adr = REG141_ADR else '0';
reg142_adr_match_s <= '1' when wbs_in.adr = REG142_ADR else '0';
reg143_adr_match_s <= '1' when wbs_in.adr = REG143_ADR else '0';
reg144_adr_match_s <= '1' when wbs_in.adr = REG144_ADR else '0';
reg145_adr_match_s <= '1' when wbs_in.adr = REG145_ADR else '0';
reg146_adr_match_s <= '1' when wbs_in.adr = REG146_ADR else '0';
reg147_adr_match_s <= '1' when wbs_in.adr = REG147_ADR else '0';
reg148_adr_match_s <= '1' when wbs_in.adr = REG148_ADR else '0';
reg149_adr_match_s <= '1' when wbs_in.adr = REG149_ADR else '0';
reg150_adr_match_s <= '1' when wbs_in.adr = REG150_ADR else '0';
reg151_adr_match_s <= '1' when wbs_in.adr = REG151_ADR else '0';
reg152_adr_match_s <= '1' when wbs_in.adr = REG152_ADR else '0';
reg153_adr_match_s <= '1' when wbs_in.adr = REG153_ADR else '0';
reg154_adr_match_s <= '1' when wbs_in.adr = REG154_ADR else '0';
reg155_adr_match_s <= '1' when wbs_in.adr = REG155_ADR else '0';
reg156_adr_match_s <= '1' when wbs_in.adr = REG156_ADR else '0';
reg157_adr_match_s <= '1' when wbs_in.adr = REG157_ADR else '0';
reg158_adr_match_s <= '1' when wbs_in.adr = REG158_ADR else '0';
reg159_adr_match_s <= '1' when wbs_in.adr = REG159_ADR else '0';
reg160_adr_match_s <= '1' when wbs_in.adr = REG160_ADR else '0';
reg161_adr_match_s <= '1' when wbs_in.adr = REG161_ADR else '0';
reg162_adr_match_s <= '1' when wbs_in.adr = REG162_ADR else '0';
reg163_adr_match_s <= '1' when wbs_in.adr = REG163_ADR else '0';
reg164_adr_match_s <= '1' when wbs_in.adr = REG164_ADR else '0';
reg165_adr_match_s <= '1' when wbs_in.adr = REG165_ADR else '0';
reg166_adr_match_s <= '1' when wbs_in.adr = REG166_ADR else '0';
reg167_adr_match_s <= '1' when wbs_in.adr = REG167_ADR else '0';
reg168_adr_match_s <= '1' when wbs_in.adr = REG168_ADR else '0';
reg169_adr_match_s <= '1' when wbs_in.adr = REG169_ADR else '0';
reg170_adr_match_s <= '1' when wbs_in.adr = REG170_ADR else '0';
reg171_adr_match_s <= '1' when wbs_in.adr = REG171_ADR else '0';
reg172_adr_match_s <= '1' when wbs_in.adr = REG172_ADR else '0';
reg173_adr_match_s <= '1' when wbs_in.adr = REG173_ADR else '0';
reg174_adr_match_s <= '1' when wbs_in.adr = REG174_ADR else '0';
reg175_adr_match_s <= '1' when wbs_in.adr = REG175_ADR else '0';
reg176_adr_match_s <= '1' when wbs_in.adr = REG176_ADR else '0';
reg177_adr_match_s <= '1' when wbs_in.adr = REG177_ADR else '0';
reg178_adr_match_s <= '1' when wbs_in.adr = REG178_ADR else '0';
reg179_adr_match_s <= '1' when wbs_in.adr = REG179_ADR else '0';
reg180_adr_match_s <= '1' when wbs_in.adr = REG180_ADR else '0';
reg181_adr_match_s <= '1' when wbs_in.adr = REG181_ADR else '0';
reg182_adr_match_s <= '1' when wbs_in.adr = REG182_ADR else '0';
reg183_adr_match_s <= '1' when wbs_in.adr = REG183_ADR else '0';
reg184_adr_match_s <= '1' when wbs_in.adr = REG184_ADR else '0';
reg185_adr_match_s <= '1' when wbs_in.adr = REG185_ADR else '0';
reg186_adr_match_s <= '1' when wbs_in.adr = REG186_ADR else '0';
reg187_adr_match_s <= '1' when wbs_in.adr = REG187_ADR else '0';
reg188_adr_match_s <= '1' when wbs_in.adr = REG188_ADR else '0';
reg189_adr_match_s <= '1' when wbs_in.adr = REG189_ADR else '0';
reg190_adr_match_s <= '1' when wbs_in.adr = REG190_ADR else '0';
reg191_adr_match_s <= '1' when wbs_in.adr = REG191_ADR else '0';
reg192_adr_match_s <= '1' when wbs_in.adr = REG192_ADR else '0';
reg193_adr_match_s <= '1' when wbs_in.adr = REG193_ADR else '0';
reg194_adr_match_s <= '1' when wbs_in.adr = REG194_ADR else '0';
reg195_adr_match_s <= '1' when wbs_in.adr = REG195_ADR else '0';
reg196_adr_match_s <= '1' when wbs_in.adr = REG196_ADR else '0';
reg197_adr_match_s <= '1' when wbs_in.adr = REG197_ADR else '0';
reg198_adr_match_s <= '1' when wbs_in.adr = REG198_ADR else '0';
reg199_adr_match_s <= '1' when wbs_in.adr = REG199_ADR else '0';
reg200_adr_match_s <= '1' when wbs_in.adr = REG200_ADR else '0';
reg201_adr_match_s <= '1' when wbs_in.adr = REG201_ADR else '0';
reg202_adr_match_s <= '1' when wbs_in.adr = REG202_ADR else '0';
reg203_adr_match_s <= '1' when wbs_in.adr = REG203_ADR else '0';
reg204_adr_match_s <= '1' when wbs_in.adr = REG204_ADR else '0';
reg205_adr_match_s <= '1' when wbs_in.adr = REG205_ADR else '0';
reg206_adr_match_s <= '1' when wbs_in.adr = REG206_ADR else '0';
reg207_adr_match_s <= '1' when wbs_in.adr = REG207_ADR else '0';
reg208_adr_match_s <= '1' when wbs_in.adr = REG208_ADR else '0';
reg209_adr_match_s <= '1' when wbs_in.adr = REG209_ADR else '0';
reg210_adr_match_s <= '1' when wbs_in.adr = REG210_ADR else '0';
reg211_adr_match_s <= '1' when wbs_in.adr = REG211_ADR else '0';
reg212_adr_match_s <= '1' when wbs_in.adr = REG212_ADR else '0';
reg213_adr_match_s <= '1' when wbs_in.adr = REG213_ADR else '0';
reg214_adr_match_s <= '1' when wbs_in.adr = REG214_ADR else '0';
reg215_adr_match_s <= '1' when wbs_in.adr = REG215_ADR else '0';
reg216_adr_match_s <= '1' when wbs_in.adr = REG216_ADR else '0';
reg217_adr_match_s <= '1' when wbs_in.adr = REG217_ADR else '0';
reg218_adr_match_s <= '1' when wbs_in.adr = REG218_ADR else '0';
reg219_adr_match_s <= '1' when wbs_in.adr = REG219_ADR else '0';
reg220_adr_match_s <= '1' when wbs_in.adr = REG220_ADR else '0';
reg221_adr_match_s <= '1' when wbs_in.adr = REG221_ADR else '0';
reg222_adr_match_s <= '1' when wbs_in.adr = REG222_ADR else '0';
reg223_adr_match_s <= '1' when wbs_in.adr = REG223_ADR else '0';
reg224_adr_match_s <= '1' when wbs_in.adr = REG224_ADR else '0';
reg225_adr_match_s <= '1' when wbs_in.adr = REG225_ADR else '0';
reg226_adr_match_s <= '1' when wbs_in.adr = REG226_ADR else '0';
reg227_adr_match_s <= '1' when wbs_in.adr = REG227_ADR else '0';
reg228_adr_match_s <= '1' when wbs_in.adr = REG228_ADR else '0';
reg229_adr_match_s <= '1' when wbs_in.adr = REG229_ADR else '0';
reg230_adr_match_s <= '1' when wbs_in.adr = REG230_ADR else '0';
reg231_adr_match_s <= '1' when wbs_in.adr = REG231_ADR else '0';
reg232_adr_match_s <= '1' when wbs_in.adr = REG232_ADR else '0';
reg233_adr_match_s <= '1' when wbs_in.adr = REG233_ADR else '0';
reg234_adr_match_s <= '1' when wbs_in.adr = REG234_ADR else '0';
reg235_adr_match_s <= '1' when wbs_in.adr = REG235_ADR else '0';
reg236_adr_match_s <= '1' when wbs_in.adr = REG236_ADR else '0';
reg237_adr_match_s <= '1' when wbs_in.adr = REG237_ADR else '0';
reg238_adr_match_s <= '1' when wbs_in.adr = REG238_ADR else '0';
reg239_adr_match_s <= '1' when wbs_in.adr = REG239_ADR else '0';
reg240_adr_match_s <= '1' when wbs_in.adr = REG240_ADR else '0';
reg241_adr_match_s <= '1' when wbs_in.adr = REG241_ADR else '0';
reg242_adr_match_s <= '1' when wbs_in.adr = REG242_ADR else '0';
reg243_adr_match_s <= '1' when wbs_in.adr = REG243_ADR else '0';
reg244_adr_match_s <= '1' when wbs_in.adr = REG244_ADR else '0';
reg245_adr_match_s <= '1' when wbs_in.adr = REG245_ADR else '0';
reg246_adr_match_s <= '1' when wbs_in.adr = REG246_ADR else '0';
reg247_adr_match_s <= '1' when wbs_in.adr = REG247_ADR else '0';
reg248_adr_match_s <= '1' when wbs_in.adr = REG248_ADR else '0';
reg249_adr_match_s <= '1' when wbs_in.adr = REG249_ADR else '0';
reg250_adr_match_s <= '1' when wbs_in.adr = REG250_ADR else '0';
reg251_adr_match_s <= '1' when wbs_in.adr = REG251_ADR else '0';
reg252_adr_match_s <= '1' when wbs_in.adr = REG252_ADR else '0';
reg253_adr_match_s <= '1' when wbs_in.adr = REG253_ADR else '0';
reg254_adr_match_s <= '1' when wbs_in.adr = REG254_ADR else '0';
reg255_adr_match_s <= '1' when wbs_in.adr = REG255_ADR else '0';
-- register enable signals
reg0_re_s <= wbs_in.stb AND wbs_in.we AND reg0_adr_match_s;
reg1_re_s <= wbs_in.stb AND wbs_in.we AND reg1_adr_match_s;
reg2_re_s <= wbs_in.stb AND wbs_in.we AND reg2_adr_match_s;
reg3_re_s <= wbs_in.stb AND wbs_in.we AND reg3_adr_match_s;
reg4_re_s <= wbs_in.stb AND wbs_in.we AND reg4_adr_match_s;
reg5_re_s <= wbs_in.stb AND wbs_in.we AND reg5_adr_match_s;
reg6_re_s <= wbs_in.stb AND wbs_in.we AND reg6_adr_match_s;
reg7_re_s <= wbs_in.stb AND wbs_in.we AND reg7_adr_match_s;
reg8_re_s <= wbs_in.stb AND wbs_in.we AND reg8_adr_match_s;
reg9_re_s <= wbs_in.stb AND wbs_in.we AND reg9_adr_match_s;
reg10_re_s <= wbs_in.stb AND wbs_in.we AND reg10_adr_match_s;
reg11_re_s <= wbs_in.stb AND wbs_in.we AND reg11_adr_match_s;
reg12_re_s <= wbs_in.stb AND wbs_in.we AND reg12_adr_match_s;
reg13_re_s <= wbs_in.stb AND wbs_in.we AND reg13_adr_match_s;
reg14_re_s <= wbs_in.stb AND wbs_in.we AND reg14_adr_match_s;
reg15_re_s <= wbs_in.stb AND wbs_in.we AND reg15_adr_match_s;
reg16_re_s <= wbs_in.stb AND wbs_in.we AND reg16_adr_match_s;
reg17_re_s <= wbs_in.stb AND wbs_in.we AND reg17_adr_match_s;
reg18_re_s <= wbs_in.stb AND wbs_in.we AND reg18_adr_match_s;
reg19_re_s <= wbs_in.stb AND wbs_in.we AND reg19_adr_match_s;
reg20_re_s <= wbs_in.stb AND wbs_in.we AND reg20_adr_match_s;
reg21_re_s <= wbs_in.stb AND wbs_in.we AND reg21_adr_match_s;
reg22_re_s <= wbs_in.stb AND wbs_in.we AND reg22_adr_match_s;
reg23_re_s <= wbs_in.stb AND wbs_in.we AND reg23_adr_match_s;
reg24_re_s <= wbs_in.stb AND wbs_in.we AND reg24_adr_match_s;
reg25_re_s <= wbs_in.stb AND wbs_in.we AND reg25_adr_match_s;
reg26_re_s <= wbs_in.stb AND wbs_in.we AND reg26_adr_match_s;
reg27_re_s <= wbs_in.stb AND wbs_in.we AND reg27_adr_match_s;
reg28_re_s <= wbs_in.stb AND wbs_in.we AND reg28_adr_match_s;
reg29_re_s <= wbs_in.stb AND wbs_in.we AND reg29_adr_match_s;
reg30_re_s <= wbs_in.stb AND wbs_in.we AND reg30_adr_match_s;
reg31_re_s <= wbs_in.stb AND wbs_in.we AND reg31_adr_match_s;
reg32_re_s <= wbs_in.stb AND wbs_in.we AND reg32_adr_match_s;
reg33_re_s <= wbs_in.stb AND wbs_in.we AND reg33_adr_match_s;
reg34_re_s <= wbs_in.stb AND wbs_in.we AND reg34_adr_match_s;
reg35_re_s <= wbs_in.stb AND wbs_in.we AND reg35_adr_match_s;
reg36_re_s <= wbs_in.stb AND wbs_in.we AND reg36_adr_match_s;
reg37_re_s <= wbs_in.stb AND wbs_in.we AND reg37_adr_match_s;
reg38_re_s <= wbs_in.stb AND wbs_in.we AND reg38_adr_match_s;
reg39_re_s <= wbs_in.stb AND wbs_in.we AND reg39_adr_match_s;
reg40_re_s <= wbs_in.stb AND wbs_in.we AND reg40_adr_match_s;
reg41_re_s <= wbs_in.stb AND wbs_in.we AND reg41_adr_match_s;
reg42_re_s <= wbs_in.stb AND wbs_in.we AND reg42_adr_match_s;
reg43_re_s <= wbs_in.stb AND wbs_in.we AND reg43_adr_match_s;
reg44_re_s <= wbs_in.stb AND wbs_in.we AND reg44_adr_match_s;
reg45_re_s <= wbs_in.stb AND wbs_in.we AND reg45_adr_match_s;
reg46_re_s <= wbs_in.stb AND wbs_in.we AND reg46_adr_match_s;
reg47_re_s <= wbs_in.stb AND wbs_in.we AND reg47_adr_match_s;
reg48_re_s <= wbs_in.stb AND wbs_in.we AND reg48_adr_match_s;
reg49_re_s <= wbs_in.stb AND wbs_in.we AND reg49_adr_match_s;
reg50_re_s <= wbs_in.stb AND wbs_in.we AND reg50_adr_match_s;
reg51_re_s <= wbs_in.stb AND wbs_in.we AND reg51_adr_match_s;
reg52_re_s <= wbs_in.stb AND wbs_in.we AND reg52_adr_match_s;
reg53_re_s <= wbs_in.stb AND wbs_in.we AND reg53_adr_match_s;
reg54_re_s <= wbs_in.stb AND wbs_in.we AND reg54_adr_match_s;
reg55_re_s <= wbs_in.stb AND wbs_in.we AND reg55_adr_match_s;
reg56_re_s <= wbs_in.stb AND wbs_in.we AND reg56_adr_match_s;
reg57_re_s <= wbs_in.stb AND wbs_in.we AND reg57_adr_match_s;
reg58_re_s <= wbs_in.stb AND wbs_in.we AND reg58_adr_match_s;
reg59_re_s <= wbs_in.stb AND wbs_in.we AND reg59_adr_match_s;
reg60_re_s <= wbs_in.stb AND wbs_in.we AND reg60_adr_match_s;
reg61_re_s <= wbs_in.stb AND wbs_in.we AND reg61_adr_match_s;
reg62_re_s <= wbs_in.stb AND wbs_in.we AND reg62_adr_match_s;
reg63_re_s <= wbs_in.stb AND wbs_in.we AND reg63_adr_match_s;
reg64_re_s <= wbs_in.stb AND wbs_in.we AND reg64_adr_match_s;
reg65_re_s <= wbs_in.stb AND wbs_in.we AND reg65_adr_match_s;
reg66_re_s <= wbs_in.stb AND wbs_in.we AND reg66_adr_match_s;
reg67_re_s <= wbs_in.stb AND wbs_in.we AND reg67_adr_match_s;
reg68_re_s <= wbs_in.stb AND wbs_in.we AND reg68_adr_match_s;
reg69_re_s <= wbs_in.stb AND wbs_in.we AND reg69_adr_match_s;
reg70_re_s <= wbs_in.stb AND wbs_in.we AND reg70_adr_match_s;
reg71_re_s <= wbs_in.stb AND wbs_in.we AND reg71_adr_match_s;
reg72_re_s <= wbs_in.stb AND wbs_in.we AND reg72_adr_match_s;
reg73_re_s <= wbs_in.stb AND wbs_in.we AND reg73_adr_match_s;
reg74_re_s <= wbs_in.stb AND wbs_in.we AND reg74_adr_match_s;
reg75_re_s <= wbs_in.stb AND wbs_in.we AND reg75_adr_match_s;
reg76_re_s <= wbs_in.stb AND wbs_in.we AND reg76_adr_match_s;
reg77_re_s <= wbs_in.stb AND wbs_in.we AND reg77_adr_match_s;
reg78_re_s <= wbs_in.stb AND wbs_in.we AND reg78_adr_match_s;
reg79_re_s <= wbs_in.stb AND wbs_in.we AND reg79_adr_match_s;
reg80_re_s <= wbs_in.stb AND wbs_in.we AND reg80_adr_match_s;
reg81_re_s <= wbs_in.stb AND wbs_in.we AND reg81_adr_match_s;
reg82_re_s <= wbs_in.stb AND wbs_in.we AND reg82_adr_match_s;
reg83_re_s <= wbs_in.stb AND wbs_in.we AND reg83_adr_match_s;
reg84_re_s <= wbs_in.stb AND wbs_in.we AND reg84_adr_match_s;
reg85_re_s <= wbs_in.stb AND wbs_in.we AND reg85_adr_match_s;
reg86_re_s <= wbs_in.stb AND wbs_in.we AND reg86_adr_match_s;
reg87_re_s <= wbs_in.stb AND wbs_in.we AND reg87_adr_match_s;
reg88_re_s <= wbs_in.stb AND wbs_in.we AND reg88_adr_match_s;
reg89_re_s <= wbs_in.stb AND wbs_in.we AND reg89_adr_match_s;
reg90_re_s <= wbs_in.stb AND wbs_in.we AND reg90_adr_match_s;
reg91_re_s <= wbs_in.stb AND wbs_in.we AND reg91_adr_match_s;
reg92_re_s <= wbs_in.stb AND wbs_in.we AND reg92_adr_match_s;
reg93_re_s <= wbs_in.stb AND wbs_in.we AND reg93_adr_match_s;
reg94_re_s <= wbs_in.stb AND wbs_in.we AND reg94_adr_match_s;
reg95_re_s <= wbs_in.stb AND wbs_in.we AND reg95_adr_match_s;
reg96_re_s <= wbs_in.stb AND wbs_in.we AND reg96_adr_match_s;
reg97_re_s <= wbs_in.stb AND wbs_in.we AND reg97_adr_match_s;
reg98_re_s <= wbs_in.stb AND wbs_in.we AND reg98_adr_match_s;
reg99_re_s <= wbs_in.stb AND wbs_in.we AND reg99_adr_match_s;
reg100_re_s <= wbs_in.stb AND wbs_in.we AND reg100_adr_match_s;
reg101_re_s <= wbs_in.stb AND wbs_in.we AND reg101_adr_match_s;
reg102_re_s <= wbs_in.stb AND wbs_in.we AND reg102_adr_match_s;
reg103_re_s <= wbs_in.stb AND wbs_in.we AND reg103_adr_match_s;
reg104_re_s <= wbs_in.stb AND wbs_in.we AND reg104_adr_match_s;
reg105_re_s <= wbs_in.stb AND wbs_in.we AND reg105_adr_match_s;
reg106_re_s <= wbs_in.stb AND wbs_in.we AND reg106_adr_match_s;
reg107_re_s <= wbs_in.stb AND wbs_in.we AND reg107_adr_match_s;
reg108_re_s <= wbs_in.stb AND wbs_in.we AND reg108_adr_match_s;
reg109_re_s <= wbs_in.stb AND wbs_in.we AND reg109_adr_match_s;
reg110_re_s <= wbs_in.stb AND wbs_in.we AND reg110_adr_match_s;
reg111_re_s <= wbs_in.stb AND wbs_in.we AND reg111_adr_match_s;
reg112_re_s <= wbs_in.stb AND wbs_in.we AND reg112_adr_match_s;
reg113_re_s <= wbs_in.stb AND wbs_in.we AND reg113_adr_match_s;
reg114_re_s <= wbs_in.stb AND wbs_in.we AND reg114_adr_match_s;
reg115_re_s <= wbs_in.stb AND wbs_in.we AND reg115_adr_match_s;
reg116_re_s <= wbs_in.stb AND wbs_in.we AND reg116_adr_match_s;
reg117_re_s <= wbs_in.stb AND wbs_in.we AND reg117_adr_match_s;
reg118_re_s <= wbs_in.stb AND wbs_in.we AND reg118_adr_match_s;
reg119_re_s <= wbs_in.stb AND wbs_in.we AND reg119_adr_match_s;
reg120_re_s <= wbs_in.stb AND wbs_in.we AND reg120_adr_match_s;
reg121_re_s <= wbs_in.stb AND wbs_in.we AND reg121_adr_match_s;
reg122_re_s <= wbs_in.stb AND wbs_in.we AND reg122_adr_match_s;
reg123_re_s <= wbs_in.stb AND wbs_in.we AND reg123_adr_match_s;
reg124_re_s <= wbs_in.stb AND wbs_in.we AND reg124_adr_match_s;
reg125_re_s <= wbs_in.stb AND wbs_in.we AND reg125_adr_match_s;
reg126_re_s <= wbs_in.stb AND wbs_in.we AND reg126_adr_match_s;
reg127_re_s <= wbs_in.stb AND wbs_in.we AND reg127_adr_match_s;
reg128_re_s <= wbs_in.stb AND wbs_in.we AND reg128_adr_match_s;
reg129_re_s <= wbs_in.stb AND wbs_in.we AND reg129_adr_match_s;
reg130_re_s <= wbs_in.stb AND wbs_in.we AND reg130_adr_match_s;
reg131_re_s <= wbs_in.stb AND wbs_in.we AND reg131_adr_match_s;
reg132_re_s <= wbs_in.stb AND wbs_in.we AND reg132_adr_match_s;
reg133_re_s <= wbs_in.stb AND wbs_in.we AND reg133_adr_match_s;
reg134_re_s <= wbs_in.stb AND wbs_in.we AND reg134_adr_match_s;
reg135_re_s <= wbs_in.stb AND wbs_in.we AND reg135_adr_match_s;
reg136_re_s <= wbs_in.stb AND wbs_in.we AND reg136_adr_match_s;
reg137_re_s <= wbs_in.stb AND wbs_in.we AND reg137_adr_match_s;
reg138_re_s <= wbs_in.stb AND wbs_in.we AND reg138_adr_match_s;
reg139_re_s <= wbs_in.stb AND wbs_in.we AND reg139_adr_match_s;
reg140_re_s <= wbs_in.stb AND wbs_in.we AND reg140_adr_match_s;
reg141_re_s <= wbs_in.stb AND wbs_in.we AND reg141_adr_match_s;
reg142_re_s <= wbs_in.stb AND wbs_in.we AND reg142_adr_match_s;
reg143_re_s <= wbs_in.stb AND wbs_in.we AND reg143_adr_match_s;
reg144_re_s <= wbs_in.stb AND wbs_in.we AND reg144_adr_match_s;
reg145_re_s <= wbs_in.stb AND wbs_in.we AND reg145_adr_match_s;
reg146_re_s <= wbs_in.stb AND wbs_in.we AND reg146_adr_match_s;
reg147_re_s <= wbs_in.stb AND wbs_in.we AND reg147_adr_match_s;
reg148_re_s <= wbs_in.stb AND wbs_in.we AND reg148_adr_match_s;
reg149_re_s <= wbs_in.stb AND wbs_in.we AND reg149_adr_match_s;
reg150_re_s <= wbs_in.stb AND wbs_in.we AND reg150_adr_match_s;
reg151_re_s <= wbs_in.stb AND wbs_in.we AND reg151_adr_match_s;
reg152_re_s <= wbs_in.stb AND wbs_in.we AND reg152_adr_match_s;
reg153_re_s <= wbs_in.stb AND wbs_in.we AND reg153_adr_match_s;
reg154_re_s <= wbs_in.stb AND wbs_in.we AND reg154_adr_match_s;
reg155_re_s <= wbs_in.stb AND wbs_in.we AND reg155_adr_match_s;
reg156_re_s <= wbs_in.stb AND wbs_in.we AND reg156_adr_match_s;
reg157_re_s <= wbs_in.stb AND wbs_in.we AND reg157_adr_match_s;
reg158_re_s <= wbs_in.stb AND wbs_in.we AND reg158_adr_match_s;
reg159_re_s <= wbs_in.stb AND wbs_in.we AND reg159_adr_match_s;
reg160_re_s <= wbs_in.stb AND wbs_in.we AND reg160_adr_match_s;
reg161_re_s <= wbs_in.stb AND wbs_in.we AND reg161_adr_match_s;
reg162_re_s <= wbs_in.stb AND wbs_in.we AND reg162_adr_match_s;
reg163_re_s <= wbs_in.stb AND wbs_in.we AND reg163_adr_match_s;
reg164_re_s <= wbs_in.stb AND wbs_in.we AND reg164_adr_match_s;
reg165_re_s <= wbs_in.stb AND wbs_in.we AND reg165_adr_match_s;
reg166_re_s <= wbs_in.stb AND wbs_in.we AND reg166_adr_match_s;
reg167_re_s <= wbs_in.stb AND wbs_in.we AND reg167_adr_match_s;
reg168_re_s <= wbs_in.stb AND wbs_in.we AND reg168_adr_match_s;
reg169_re_s <= wbs_in.stb AND wbs_in.we AND reg169_adr_match_s;
reg170_re_s <= wbs_in.stb AND wbs_in.we AND reg170_adr_match_s;
reg171_re_s <= wbs_in.stb AND wbs_in.we AND reg171_adr_match_s;
reg172_re_s <= wbs_in.stb AND wbs_in.we AND reg172_adr_match_s;
reg173_re_s <= wbs_in.stb AND wbs_in.we AND reg173_adr_match_s;
reg174_re_s <= wbs_in.stb AND wbs_in.we AND reg174_adr_match_s;
reg175_re_s <= wbs_in.stb AND wbs_in.we AND reg175_adr_match_s;
reg176_re_s <= wbs_in.stb AND wbs_in.we AND reg176_adr_match_s;
reg177_re_s <= wbs_in.stb AND wbs_in.we AND reg177_adr_match_s;
reg178_re_s <= wbs_in.stb AND wbs_in.we AND reg178_adr_match_s;
reg179_re_s <= wbs_in.stb AND wbs_in.we AND reg179_adr_match_s;
reg180_re_s <= wbs_in.stb AND wbs_in.we AND reg180_adr_match_s;
reg181_re_s <= wbs_in.stb AND wbs_in.we AND reg181_adr_match_s;
reg182_re_s <= wbs_in.stb AND wbs_in.we AND reg182_adr_match_s;
reg183_re_s <= wbs_in.stb AND wbs_in.we AND reg183_adr_match_s;
reg184_re_s <= wbs_in.stb AND wbs_in.we AND reg184_adr_match_s;
reg185_re_s <= wbs_in.stb AND wbs_in.we AND reg185_adr_match_s;
reg186_re_s <= wbs_in.stb AND wbs_in.we AND reg186_adr_match_s;
reg187_re_s <= wbs_in.stb AND wbs_in.we AND reg187_adr_match_s;
reg188_re_s <= wbs_in.stb AND wbs_in.we AND reg188_adr_match_s;
reg189_re_s <= wbs_in.stb AND wbs_in.we AND reg189_adr_match_s;
reg190_re_s <= wbs_in.stb AND wbs_in.we AND reg190_adr_match_s;
reg191_re_s <= wbs_in.stb AND wbs_in.we AND reg191_adr_match_s;
reg192_re_s <= wbs_in.stb AND wbs_in.we AND reg192_adr_match_s;
reg193_re_s <= wbs_in.stb AND wbs_in.we AND reg193_adr_match_s;
reg194_re_s <= wbs_in.stb AND wbs_in.we AND reg194_adr_match_s;
reg195_re_s <= wbs_in.stb AND wbs_in.we AND reg195_adr_match_s;
reg196_re_s <= wbs_in.stb AND wbs_in.we AND reg196_adr_match_s;
reg197_re_s <= wbs_in.stb AND wbs_in.we AND reg197_adr_match_s;
reg198_re_s <= wbs_in.stb AND wbs_in.we AND reg198_adr_match_s;
reg199_re_s <= wbs_in.stb AND wbs_in.we AND reg199_adr_match_s;
reg200_re_s <= wbs_in.stb AND wbs_in.we AND reg200_adr_match_s;
reg201_re_s <= wbs_in.stb AND wbs_in.we AND reg201_adr_match_s;
reg202_re_s <= wbs_in.stb AND wbs_in.we AND reg202_adr_match_s;
reg203_re_s <= wbs_in.stb AND wbs_in.we AND reg203_adr_match_s;
reg204_re_s <= wbs_in.stb AND wbs_in.we AND reg204_adr_match_s;
reg205_re_s <= wbs_in.stb AND wbs_in.we AND reg205_adr_match_s;
reg206_re_s <= wbs_in.stb AND wbs_in.we AND reg206_adr_match_s;
reg207_re_s <= wbs_in.stb AND wbs_in.we AND reg207_adr_match_s;
reg208_re_s <= wbs_in.stb AND wbs_in.we AND reg208_adr_match_s;
reg209_re_s <= wbs_in.stb AND wbs_in.we AND reg209_adr_match_s;
reg210_re_s <= wbs_in.stb AND wbs_in.we AND reg210_adr_match_s;
reg211_re_s <= wbs_in.stb AND wbs_in.we AND reg211_adr_match_s;
reg212_re_s <= wbs_in.stb AND wbs_in.we AND reg212_adr_match_s;
reg213_re_s <= wbs_in.stb AND wbs_in.we AND reg213_adr_match_s;
reg214_re_s <= wbs_in.stb AND wbs_in.we AND reg214_adr_match_s;
reg215_re_s <= wbs_in.stb AND wbs_in.we AND reg215_adr_match_s;
reg216_re_s <= wbs_in.stb AND wbs_in.we AND reg216_adr_match_s;
reg217_re_s <= wbs_in.stb AND wbs_in.we AND reg217_adr_match_s;
reg218_re_s <= wbs_in.stb AND wbs_in.we AND reg218_adr_match_s;
reg219_re_s <= wbs_in.stb AND wbs_in.we AND reg219_adr_match_s;
reg220_re_s <= wbs_in.stb AND wbs_in.we AND reg220_adr_match_s;
reg221_re_s <= wbs_in.stb AND wbs_in.we AND reg221_adr_match_s;
reg222_re_s <= wbs_in.stb AND wbs_in.we AND reg222_adr_match_s;
reg223_re_s <= wbs_in.stb AND wbs_in.we AND reg223_adr_match_s;
reg224_re_s <= wbs_in.stb AND wbs_in.we AND reg224_adr_match_s;
reg225_re_s <= wbs_in.stb AND wbs_in.we AND reg225_adr_match_s;
reg226_re_s <= wbs_in.stb AND wbs_in.we AND reg226_adr_match_s;
reg227_re_s <= wbs_in.stb AND wbs_in.we AND reg227_adr_match_s;
reg228_re_s <= wbs_in.stb AND wbs_in.we AND reg228_adr_match_s;
reg229_re_s <= wbs_in.stb AND wbs_in.we AND reg229_adr_match_s;
reg230_re_s <= wbs_in.stb AND wbs_in.we AND reg230_adr_match_s;
reg231_re_s <= wbs_in.stb AND wbs_in.we AND reg231_adr_match_s;
reg232_re_s <= wbs_in.stb AND wbs_in.we AND reg232_adr_match_s;
reg233_re_s <= wbs_in.stb AND wbs_in.we AND reg233_adr_match_s;
reg234_re_s <= wbs_in.stb AND wbs_in.we AND reg234_adr_match_s;
reg235_re_s <= wbs_in.stb AND wbs_in.we AND reg235_adr_match_s;
reg236_re_s <= wbs_in.stb AND wbs_in.we AND reg236_adr_match_s;
reg237_re_s <= wbs_in.stb AND wbs_in.we AND reg237_adr_match_s;
reg238_re_s <= wbs_in.stb AND wbs_in.we AND reg238_adr_match_s;
reg239_re_s <= wbs_in.stb AND wbs_in.we AND reg239_adr_match_s;
reg240_re_s <= wbs_in.stb AND wbs_in.we AND reg240_adr_match_s;
reg241_re_s <= wbs_in.stb AND wbs_in.we AND reg241_adr_match_s;
reg242_re_s <= wbs_in.stb AND wbs_in.we AND reg242_adr_match_s;
reg243_re_s <= wbs_in.stb AND wbs_in.we AND reg243_adr_match_s;
reg244_re_s <= wbs_in.stb AND wbs_in.we AND reg244_adr_match_s;
reg245_re_s <= wbs_in.stb AND wbs_in.we AND reg245_adr_match_s;
reg246_re_s <= wbs_in.stb AND wbs_in.we AND reg246_adr_match_s;
reg247_re_s <= wbs_in.stb AND wbs_in.we AND reg247_adr_match_s;
reg248_re_s <= wbs_in.stb AND wbs_in.we AND reg248_adr_match_s;
reg249_re_s <= wbs_in.stb AND wbs_in.we AND reg249_adr_match_s;
reg250_re_s <= wbs_in.stb AND wbs_in.we AND reg250_adr_match_s;
reg251_re_s <= wbs_in.stb AND wbs_in.we AND reg251_adr_match_s;
reg252_re_s <= wbs_in.stb AND wbs_in.we AND reg252_adr_match_s;
reg253_re_s <= wbs_in.stb AND wbs_in.we AND reg253_adr_match_s;
reg254_re_s <= wbs_in.stb AND wbs_in.we AND reg254_adr_match_s;
reg255_re_s <= wbs_in.stb AND wbs_in.we AND reg255_adr_match_s;
-- acknowledge output
wbs_out.ack <= wbs_in.stb;
-- register inputs always get data from wbs_in
reg_in_s.reg0 <= wbs_in.dat;
reg_in_s.reg1 <= wbs_in.dat;
reg_in_s.reg2 <= wbs_in.dat;
reg_in_s.reg3 <= wbs_in.dat;
reg_in_s.reg4 <= wbs_in.dat;
reg_in_s.reg5 <= wbs_in.dat;
reg_in_s.reg6 <= wbs_in.dat;
reg_in_s.reg7 <= wbs_in.dat;
reg_in_s.reg8 <= wbs_in.dat;
reg_in_s.reg9 <= wbs_in.dat;
reg_in_s.reg10 <= wbs_in.dat;
reg_in_s.reg11 <= wbs_in.dat;
reg_in_s.reg12 <= wbs_in.dat;
reg_in_s.reg13 <= wbs_in.dat;
reg_in_s.reg14 <= wbs_in.dat;
reg_in_s.reg15 <= wbs_in.dat;
reg_in_s.reg16 <= wbs_in.dat;
reg_in_s.reg17 <= wbs_in.dat;
reg_in_s.reg18 <= wbs_in.dat;
reg_in_s.reg19 <= wbs_in.dat;
reg_in_s.reg20 <= wbs_in.dat;
reg_in_s.reg21 <= wbs_in.dat;
reg_in_s.reg22 <= wbs_in.dat;
reg_in_s.reg23 <= wbs_in.dat;
reg_in_s.reg24 <= wbs_in.dat;
reg_in_s.reg25 <= wbs_in.dat;
reg_in_s.reg26 <= wbs_in.dat;
reg_in_s.reg27 <= wbs_in.dat;
reg_in_s.reg28 <= wbs_in.dat;
reg_in_s.reg29 <= wbs_in.dat;
reg_in_s.reg30 <= wbs_in.dat;
reg_in_s.reg31 <= wbs_in.dat;
reg_in_s.reg32 <= wbs_in.dat;
reg_in_s.reg33 <= wbs_in.dat;
reg_in_s.reg34 <= wbs_in.dat;
reg_in_s.reg35 <= wbs_in.dat;
reg_in_s.reg36 <= wbs_in.dat;
reg_in_s.reg37 <= wbs_in.dat;
reg_in_s.reg38 <= wbs_in.dat;
reg_in_s.reg39 <= wbs_in.dat;
reg_in_s.reg40 <= wbs_in.dat;
reg_in_s.reg41 <= wbs_in.dat;
reg_in_s.reg42 <= wbs_in.dat;
reg_in_s.reg43 <= wbs_in.dat;
reg_in_s.reg44 <= wbs_in.dat;
reg_in_s.reg45 <= wbs_in.dat;
reg_in_s.reg46 <= wbs_in.dat;
reg_in_s.reg47 <= wbs_in.dat;
reg_in_s.reg48 <= wbs_in.dat;
reg_in_s.reg49 <= wbs_in.dat;
reg_in_s.reg50 <= wbs_in.dat;
reg_in_s.reg51 <= wbs_in.dat;
reg_in_s.reg52 <= wbs_in.dat;
reg_in_s.reg53 <= wbs_in.dat;
reg_in_s.reg54 <= wbs_in.dat;
reg_in_s.reg55 <= wbs_in.dat;
reg_in_s.reg56 <= wbs_in.dat;
reg_in_s.reg57 <= wbs_in.dat;
reg_in_s.reg58 <= wbs_in.dat;
reg_in_s.reg59 <= wbs_in.dat;
reg_in_s.reg60 <= wbs_in.dat;
reg_in_s.reg61 <= wbs_in.dat;
reg_in_s.reg62 <= wbs_in.dat;
reg_in_s.reg63 <= wbs_in.dat;
reg_in_s.reg64 <= wbs_in.dat;
reg_in_s.reg65 <= wbs_in.dat;
reg_in_s.reg66 <= wbs_in.dat;
reg_in_s.reg67 <= wbs_in.dat;
reg_in_s.reg68 <= wbs_in.dat;
reg_in_s.reg69 <= wbs_in.dat;
reg_in_s.reg70 <= wbs_in.dat;
reg_in_s.reg71 <= wbs_in.dat;
reg_in_s.reg72 <= wbs_in.dat;
reg_in_s.reg73 <= wbs_in.dat;
reg_in_s.reg74 <= wbs_in.dat;
reg_in_s.reg75 <= wbs_in.dat;
reg_in_s.reg76 <= wbs_in.dat;
reg_in_s.reg77 <= wbs_in.dat;
reg_in_s.reg78 <= wbs_in.dat;
reg_in_s.reg79 <= wbs_in.dat;
reg_in_s.reg80 <= wbs_in.dat;
reg_in_s.reg81 <= wbs_in.dat;
reg_in_s.reg82 <= wbs_in.dat;
reg_in_s.reg83 <= wbs_in.dat;
reg_in_s.reg84 <= wbs_in.dat;
reg_in_s.reg85 <= wbs_in.dat;
reg_in_s.reg86 <= wbs_in.dat;
reg_in_s.reg87 <= wbs_in.dat;
reg_in_s.reg88 <= wbs_in.dat;
reg_in_s.reg89 <= wbs_in.dat;
reg_in_s.reg90 <= wbs_in.dat;
reg_in_s.reg91 <= wbs_in.dat;
reg_in_s.reg92 <= wbs_in.dat;
reg_in_s.reg93 <= wbs_in.dat;
reg_in_s.reg94 <= wbs_in.dat;
reg_in_s.reg95 <= wbs_in.dat;
reg_in_s.reg96 <= wbs_in.dat;
reg_in_s.reg97 <= wbs_in.dat;
reg_in_s.reg98 <= wbs_in.dat;
reg_in_s.reg99 <= wbs_in.dat;
reg_in_s.reg100 <= wbs_in.dat;
reg_in_s.reg101 <= wbs_in.dat;
reg_in_s.reg102 <= wbs_in.dat;
reg_in_s.reg103 <= wbs_in.dat;
reg_in_s.reg104 <= wbs_in.dat;
reg_in_s.reg105 <= wbs_in.dat;
reg_in_s.reg106 <= wbs_in.dat;
reg_in_s.reg107 <= wbs_in.dat;
reg_in_s.reg108 <= wbs_in.dat;
reg_in_s.reg109 <= wbs_in.dat;
reg_in_s.reg110 <= wbs_in.dat;
reg_in_s.reg111 <= wbs_in.dat;
reg_in_s.reg112 <= wbs_in.dat;
reg_in_s.reg113 <= wbs_in.dat;
reg_in_s.reg114 <= wbs_in.dat;
reg_in_s.reg115 <= wbs_in.dat;
reg_in_s.reg116 <= wbs_in.dat;
reg_in_s.reg117 <= wbs_in.dat;
reg_in_s.reg118 <= wbs_in.dat;
reg_in_s.reg119 <= wbs_in.dat;
reg_in_s.reg120 <= wbs_in.dat;
reg_in_s.reg121 <= wbs_in.dat;
reg_in_s.reg122 <= wbs_in.dat;
reg_in_s.reg123 <= wbs_in.dat;
reg_in_s.reg124 <= wbs_in.dat;
reg_in_s.reg125 <= wbs_in.dat;
reg_in_s.reg126 <= wbs_in.dat;
reg_in_s.reg127 <= wbs_in.dat;
reg_in_s.reg128 <= wbs_in.dat;
reg_in_s.reg129 <= wbs_in.dat;
reg_in_s.reg130 <= wbs_in.dat;
reg_in_s.reg131 <= wbs_in.dat;
reg_in_s.reg132 <= wbs_in.dat;
reg_in_s.reg133 <= wbs_in.dat;
reg_in_s.reg134 <= wbs_in.dat;
reg_in_s.reg135 <= wbs_in.dat;
reg_in_s.reg136 <= wbs_in.dat;
reg_in_s.reg137 <= wbs_in.dat;
reg_in_s.reg138 <= wbs_in.dat;
reg_in_s.reg139 <= wbs_in.dat;
reg_in_s.reg140 <= wbs_in.dat;
reg_in_s.reg141 <= wbs_in.dat;
reg_in_s.reg142 <= wbs_in.dat;
reg_in_s.reg143 <= wbs_in.dat;
reg_in_s.reg144 <= wbs_in.dat;
reg_in_s.reg145 <= wbs_in.dat;
reg_in_s.reg146 <= wbs_in.dat;
reg_in_s.reg147 <= wbs_in.dat;
reg_in_s.reg148 <= wbs_in.dat;
reg_in_s.reg149 <= wbs_in.dat;
reg_in_s.reg150 <= wbs_in.dat;
reg_in_s.reg151 <= wbs_in.dat;
reg_in_s.reg152 <= wbs_in.dat;
reg_in_s.reg153 <= wbs_in.dat;
reg_in_s.reg154 <= wbs_in.dat;
reg_in_s.reg155 <= wbs_in.dat;
reg_in_s.reg156 <= wbs_in.dat;
reg_in_s.reg157 <= wbs_in.dat;
reg_in_s.reg158 <= wbs_in.dat;
reg_in_s.reg159 <= wbs_in.dat;
reg_in_s.reg160 <= wbs_in.dat;
reg_in_s.reg161 <= wbs_in.dat;
reg_in_s.reg162 <= wbs_in.dat;
reg_in_s.reg163 <= wbs_in.dat;
reg_in_s.reg164 <= wbs_in.dat;
reg_in_s.reg165 <= wbs_in.dat;
reg_in_s.reg166 <= wbs_in.dat;
reg_in_s.reg167 <= wbs_in.dat;
reg_in_s.reg168 <= wbs_in.dat;
reg_in_s.reg169 <= wbs_in.dat;
reg_in_s.reg170 <= wbs_in.dat;
reg_in_s.reg171 <= wbs_in.dat;
reg_in_s.reg172 <= wbs_in.dat;
reg_in_s.reg173 <= wbs_in.dat;
reg_in_s.reg174 <= wbs_in.dat;
reg_in_s.reg175 <= wbs_in.dat;
reg_in_s.reg176 <= wbs_in.dat;
reg_in_s.reg177 <= wbs_in.dat;
reg_in_s.reg178 <= wbs_in.dat;
reg_in_s.reg179 <= wbs_in.dat;
reg_in_s.reg180 <= wbs_in.dat;
reg_in_s.reg181 <= wbs_in.dat;
reg_in_s.reg182 <= wbs_in.dat;
reg_in_s.reg183 <= wbs_in.dat;
reg_in_s.reg184 <= wbs_in.dat;
reg_in_s.reg185 <= wbs_in.dat;
reg_in_s.reg186 <= wbs_in.dat;
reg_in_s.reg187 <= wbs_in.dat;
reg_in_s.reg188 <= wbs_in.dat;
reg_in_s.reg189 <= wbs_in.dat;
reg_in_s.reg190 <= wbs_in.dat;
reg_in_s.reg191 <= wbs_in.dat;
reg_in_s.reg192 <= wbs_in.dat;
reg_in_s.reg193 <= wbs_in.dat;
reg_in_s.reg194 <= wbs_in.dat;
reg_in_s.reg195 <= wbs_in.dat;
reg_in_s.reg196 <= wbs_in.dat;
reg_in_s.reg197 <= wbs_in.dat;
reg_in_s.reg198 <= wbs_in.dat;
reg_in_s.reg199 <= wbs_in.dat;
reg_in_s.reg200 <= wbs_in.dat;
reg_in_s.reg201 <= wbs_in.dat;
reg_in_s.reg202 <= wbs_in.dat;
reg_in_s.reg203 <= wbs_in.dat;
reg_in_s.reg204 <= wbs_in.dat;
reg_in_s.reg205 <= wbs_in.dat;
reg_in_s.reg206 <= wbs_in.dat;
reg_in_s.reg207 <= wbs_in.dat;
reg_in_s.reg208 <= wbs_in.dat;
reg_in_s.reg209 <= wbs_in.dat;
reg_in_s.reg210 <= wbs_in.dat;
reg_in_s.reg211 <= wbs_in.dat;
reg_in_s.reg212 <= wbs_in.dat;
reg_in_s.reg213 <= wbs_in.dat;
reg_in_s.reg214 <= wbs_in.dat;
reg_in_s.reg215 <= wbs_in.dat;
reg_in_s.reg216 <= wbs_in.dat;
reg_in_s.reg217 <= wbs_in.dat;
reg_in_s.reg218 <= wbs_in.dat;
reg_in_s.reg219 <= wbs_in.dat;
reg_in_s.reg220 <= wbs_in.dat;
reg_in_s.reg221 <= wbs_in.dat;
reg_in_s.reg222 <= wbs_in.dat;
reg_in_s.reg223 <= wbs_in.dat;
reg_in_s.reg224 <= wbs_in.dat;
reg_in_s.reg225 <= wbs_in.dat;
reg_in_s.reg226 <= wbs_in.dat;
reg_in_s.reg227 <= wbs_in.dat;
reg_in_s.reg228 <= wbs_in.dat;
reg_in_s.reg229 <= wbs_in.dat;
reg_in_s.reg230 <= wbs_in.dat;
reg_in_s.reg231 <= wbs_in.dat;
reg_in_s.reg232 <= wbs_in.dat;
reg_in_s.reg233 <= wbs_in.dat;
reg_in_s.reg234 <= wbs_in.dat;
reg_in_s.reg235 <= wbs_in.dat;
reg_in_s.reg236 <= wbs_in.dat;
reg_in_s.reg237 <= wbs_in.dat;
reg_in_s.reg238 <= wbs_in.dat;
reg_in_s.reg239 <= wbs_in.dat;
reg_in_s.reg240 <= wbs_in.dat;
reg_in_s.reg241 <= wbs_in.dat;
reg_in_s.reg242 <= wbs_in.dat;
reg_in_s.reg243 <= wbs_in.dat;
reg_in_s.reg244 <= wbs_in.dat;
reg_in_s.reg245 <= wbs_in.dat;
reg_in_s.reg246 <= wbs_in.dat;
reg_in_s.reg247 <= wbs_in.dat;
reg_in_s.reg248 <= wbs_in.dat;
reg_in_s.reg249 <= wbs_in.dat;
reg_in_s.reg250 <= wbs_in.dat;
reg_in_s.reg251 <= wbs_in.dat;
reg_in_s.reg252 <= wbs_in.dat;
reg_in_s.reg253 <= wbs_in.dat;
reg_in_s.reg254 <= wbs_in.dat;
reg_in_s.reg255 <= wbs_in.dat;
-- register output -> wbs_out via demultiplexer
with wbs_in.adr select
wbs_out.dat <= reg_out_s.reg0 when REG0_ADR,
reg_out_s.reg1 when REG1_ADR,
reg_out_s.reg2 when REG2_ADR,
reg_out_s.reg3 when REG3_ADR,
reg_out_s.reg4 when REG4_ADR,
reg_out_s.reg5 when REG5_ADR,
reg_out_s.reg6 when REG6_ADR,
reg_out_s.reg7 when REG7_ADR,
reg_out_s.reg8 when REG8_ADR,
reg_out_s.reg9 when REG9_ADR,
reg_out_s.reg10 when REG10_ADR,
reg_out_s.reg11 when REG11_ADR,
reg_out_s.reg12 when REG12_ADR,
reg_out_s.reg13 when REG13_ADR,
reg_out_s.reg14 when REG14_ADR,
reg_out_s.reg15 when REG15_ADR,
reg_out_s.reg16 when REG16_ADR,
reg_out_s.reg17 when REG17_ADR,
reg_out_s.reg18 when REG18_ADR,
reg_out_s.reg19 when REG19_ADR,
reg_out_s.reg20 when REG20_ADR,
reg_out_s.reg21 when REG21_ADR,
reg_out_s.reg22 when REG22_ADR,
reg_out_s.reg23 when REG23_ADR,
reg_out_s.reg24 when REG24_ADR,
reg_out_s.reg25 when REG25_ADR,
reg_out_s.reg26 when REG26_ADR,
reg_out_s.reg27 when REG27_ADR,
reg_out_s.reg28 when REG28_ADR,
reg_out_s.reg29 when REG29_ADR,
reg_out_s.reg30 when REG30_ADR,
reg_out_s.reg31 when REG31_ADR,
reg_out_s.reg32 when REG32_ADR,
reg_out_s.reg33 when REG33_ADR,
reg_out_s.reg34 when REG34_ADR,
reg_out_s.reg35 when REG35_ADR,
reg_out_s.reg36 when REG36_ADR,
reg_out_s.reg37 when REG37_ADR,
reg_out_s.reg38 when REG38_ADR,
reg_out_s.reg39 when REG39_ADR,
reg_out_s.reg40 when REG40_ADR,
reg_out_s.reg41 when REG41_ADR,
reg_out_s.reg42 when REG42_ADR,
reg_out_s.reg43 when REG43_ADR,
reg_out_s.reg44 when REG44_ADR,
reg_out_s.reg45 when REG45_ADR,
reg_out_s.reg46 when REG46_ADR,
reg_out_s.reg47 when REG47_ADR,
reg_out_s.reg48 when REG48_ADR,
reg_out_s.reg49 when REG49_ADR,
reg_out_s.reg50 when REG50_ADR,
reg_out_s.reg51 when REG51_ADR,
reg_out_s.reg52 when REG52_ADR,
reg_out_s.reg53 when REG53_ADR,
reg_out_s.reg54 when REG54_ADR,
reg_out_s.reg55 when REG55_ADR,
reg_out_s.reg56 when REG56_ADR,
reg_out_s.reg57 when REG57_ADR,
reg_out_s.reg58 when REG58_ADR,
reg_out_s.reg59 when REG59_ADR,
reg_out_s.reg60 when REG60_ADR,
reg_out_s.reg61 when REG61_ADR,
reg_out_s.reg62 when REG62_ADR,
reg_out_s.reg63 when REG63_ADR,
reg_out_s.reg64 when REG64_ADR,
reg_out_s.reg65 when REG65_ADR,
reg_out_s.reg66 when REG66_ADR,
reg_out_s.reg67 when REG67_ADR,
reg_out_s.reg68 when REG68_ADR,
reg_out_s.reg69 when REG69_ADR,
reg_out_s.reg70 when REG70_ADR,
reg_out_s.reg71 when REG71_ADR,
reg_out_s.reg72 when REG72_ADR,
reg_out_s.reg73 when REG73_ADR,
reg_out_s.reg74 when REG74_ADR,
reg_out_s.reg75 when REG75_ADR,
reg_out_s.reg76 when REG76_ADR,
reg_out_s.reg77 when REG77_ADR,
reg_out_s.reg78 when REG78_ADR,
reg_out_s.reg79 when REG79_ADR,
reg_out_s.reg80 when REG80_ADR,
reg_out_s.reg81 when REG81_ADR,
reg_out_s.reg82 when REG82_ADR,
reg_out_s.reg83 when REG83_ADR,
reg_out_s.reg84 when REG84_ADR,
reg_out_s.reg85 when REG85_ADR,
reg_out_s.reg86 when REG86_ADR,
reg_out_s.reg87 when REG87_ADR,
reg_out_s.reg88 when REG88_ADR,
reg_out_s.reg89 when REG89_ADR,
reg_out_s.reg90 when REG90_ADR,
reg_out_s.reg91 when REG91_ADR,
reg_out_s.reg92 when REG92_ADR,
reg_out_s.reg93 when REG93_ADR,
reg_out_s.reg94 when REG94_ADR,
reg_out_s.reg95 when REG95_ADR,
reg_out_s.reg96 when REG96_ADR,
reg_out_s.reg97 when REG97_ADR,
reg_out_s.reg98 when REG98_ADR,
reg_out_s.reg99 when REG99_ADR,
reg_out_s.reg100 when REG100_ADR,
reg_out_s.reg101 when REG101_ADR,
reg_out_s.reg102 when REG102_ADR,
reg_out_s.reg103 when REG103_ADR,
reg_out_s.reg104 when REG104_ADR,
reg_out_s.reg105 when REG105_ADR,
reg_out_s.reg106 when REG106_ADR,
reg_out_s.reg107 when REG107_ADR,
reg_out_s.reg108 when REG108_ADR,
reg_out_s.reg109 when REG109_ADR,
reg_out_s.reg110 when REG110_ADR,
reg_out_s.reg111 when REG111_ADR,
reg_out_s.reg112 when REG112_ADR,
reg_out_s.reg113 when REG113_ADR,
reg_out_s.reg114 when REG114_ADR,
reg_out_s.reg115 when REG115_ADR,
reg_out_s.reg116 when REG116_ADR,
reg_out_s.reg117 when REG117_ADR,
reg_out_s.reg118 when REG118_ADR,
reg_out_s.reg119 when REG119_ADR,
reg_out_s.reg120 when REG120_ADR,
reg_out_s.reg121 when REG121_ADR,
reg_out_s.reg122 when REG122_ADR,
reg_out_s.reg123 when REG123_ADR,
reg_out_s.reg124 when REG124_ADR,
reg_out_s.reg125 when REG125_ADR,
reg_out_s.reg126 when REG126_ADR,
reg_out_s.reg127 when REG127_ADR,
reg_out_s.reg128 when REG128_ADR,
reg_out_s.reg129 when REG129_ADR,
reg_out_s.reg130 when REG130_ADR,
reg_out_s.reg131 when REG131_ADR,
reg_out_s.reg132 when REG132_ADR,
reg_out_s.reg133 when REG133_ADR,
reg_out_s.reg134 when REG134_ADR,
reg_out_s.reg135 when REG135_ADR,
reg_out_s.reg136 when REG136_ADR,
reg_out_s.reg137 when REG137_ADR,
reg_out_s.reg138 when REG138_ADR,
reg_out_s.reg139 when REG139_ADR,
reg_out_s.reg140 when REG140_ADR,
reg_out_s.reg141 when REG141_ADR,
reg_out_s.reg142 when REG142_ADR,
reg_out_s.reg143 when REG143_ADR,
reg_out_s.reg144 when REG144_ADR,
reg_out_s.reg145 when REG145_ADR,
reg_out_s.reg146 when REG146_ADR,
reg_out_s.reg147 when REG147_ADR,
reg_out_s.reg148 when REG148_ADR,
reg_out_s.reg149 when REG149_ADR,
reg_out_s.reg150 when REG150_ADR,
reg_out_s.reg151 when REG151_ADR,
reg_out_s.reg152 when REG152_ADR,
reg_out_s.reg153 when REG153_ADR,
reg_out_s.reg154 when REG154_ADR,
reg_out_s.reg155 when REG155_ADR,
reg_out_s.reg156 when REG156_ADR,
reg_out_s.reg157 when REG157_ADR,
reg_out_s.reg158 when REG158_ADR,
reg_out_s.reg159 when REG159_ADR,
reg_out_s.reg160 when REG160_ADR,
reg_out_s.reg161 when REG161_ADR,
reg_out_s.reg162 when REG162_ADR,
reg_out_s.reg163 when REG163_ADR,
reg_out_s.reg164 when REG164_ADR,
reg_out_s.reg165 when REG165_ADR,
reg_out_s.reg166 when REG166_ADR,
reg_out_s.reg167 when REG167_ADR,
reg_out_s.reg168 when REG168_ADR,
reg_out_s.reg169 when REG169_ADR,
reg_out_s.reg170 when REG170_ADR,
reg_out_s.reg171 when REG171_ADR,
reg_out_s.reg172 when REG172_ADR,
reg_out_s.reg173 when REG173_ADR,
reg_out_s.reg174 when REG174_ADR,
reg_out_s.reg175 when REG175_ADR,
reg_out_s.reg176 when REG176_ADR,
reg_out_s.reg177 when REG177_ADR,
reg_out_s.reg178 when REG178_ADR,
reg_out_s.reg179 when REG179_ADR,
reg_out_s.reg180 when REG180_ADR,
reg_out_s.reg181 when REG181_ADR,
reg_out_s.reg182 when REG182_ADR,
reg_out_s.reg183 when REG183_ADR,
reg_out_s.reg184 when REG184_ADR,
reg_out_s.reg185 when REG185_ADR,
reg_out_s.reg186 when REG186_ADR,
reg_out_s.reg187 when REG187_ADR,
reg_out_s.reg188 when REG188_ADR,
reg_out_s.reg189 when REG189_ADR,
reg_out_s.reg190 when REG190_ADR,
reg_out_s.reg191 when REG191_ADR,
reg_out_s.reg192 when REG192_ADR,
reg_out_s.reg193 when REG193_ADR,
reg_out_s.reg194 when REG194_ADR,
reg_out_s.reg195 when REG195_ADR,
reg_out_s.reg196 when REG196_ADR,
reg_out_s.reg197 when REG197_ADR,
reg_out_s.reg198 when REG198_ADR,
reg_out_s.reg199 when REG199_ADR,
reg_out_s.reg200 when REG200_ADR,
reg_out_s.reg201 when REG201_ADR,
reg_out_s.reg202 when REG202_ADR,
reg_out_s.reg203 when REG203_ADR,
reg_out_s.reg204 when REG204_ADR,
reg_out_s.reg205 when REG205_ADR,
reg_out_s.reg206 when REG206_ADR,
reg_out_s.reg207 when REG207_ADR,
reg_out_s.reg208 when REG208_ADR,
reg_out_s.reg209 when REG209_ADR,
reg_out_s.reg210 when REG210_ADR,
reg_out_s.reg211 when REG211_ADR,
reg_out_s.reg212 when REG212_ADR,
reg_out_s.reg213 when REG213_ADR,
reg_out_s.reg214 when REG214_ADR,
reg_out_s.reg215 when REG215_ADR,
reg_out_s.reg216 when REG216_ADR,
reg_out_s.reg217 when REG217_ADR,
reg_out_s.reg218 when REG218_ADR,
reg_out_s.reg219 when REG219_ADR,
reg_out_s.reg220 when REG220_ADR,
reg_out_s.reg221 when REG221_ADR,
reg_out_s.reg222 when REG222_ADR,
reg_out_s.reg223 when REG223_ADR,
reg_out_s.reg224 when REG224_ADR,
reg_out_s.reg225 when REG225_ADR,
reg_out_s.reg226 when REG226_ADR,
reg_out_s.reg227 when REG227_ADR,
reg_out_s.reg228 when REG228_ADR,
reg_out_s.reg229 when REG229_ADR,
reg_out_s.reg230 when REG230_ADR,
reg_out_s.reg231 when REG231_ADR,
reg_out_s.reg232 when REG232_ADR,
reg_out_s.reg233 when REG233_ADR,
reg_out_s.reg234 when REG234_ADR,
reg_out_s.reg235 when REG235_ADR,
reg_out_s.reg236 when REG236_ADR,
reg_out_s.reg237 when REG237_ADR,
reg_out_s.reg238 when REG238_ADR,
reg_out_s.reg239 when REG239_ADR,
reg_out_s.reg240 when REG240_ADR,
reg_out_s.reg241 when REG241_ADR,
reg_out_s.reg242 when REG242_ADR,
reg_out_s.reg243 when REG243_ADR,
reg_out_s.reg244 when REG244_ADR,
reg_out_s.reg245 when REG245_ADR,
reg_out_s.reg246 when REG246_ADR,
reg_out_s.reg247 when REG247_ADR,
reg_out_s.reg248 when REG248_ADR,
reg_out_s.reg249 when REG249_ADR,
reg_out_s.reg250 when REG250_ADR,
reg_out_s.reg251 when REG251_ADR,
reg_out_s.reg252 when REG252_ADR,
reg_out_s.reg253 when REG253_ADR,
reg_out_s.reg254 when REG254_ADR,
reg_out_s.reg255 when REG255_ADR,
(others => '-') when others;
-- register outputs -> non-wishbone outputs
reg0_out <= reg_out_s.reg0;
reg1_out <= reg_out_s.reg1;
reg2_out <= reg_out_s.reg2;
reg3_out <= reg_out_s.reg3;
reg4_out <= reg_out_s.reg4;
reg5_out <= reg_out_s.reg5;
reg6_out <= reg_out_s.reg6;
reg7_out <= reg_out_s.reg7;
reg8_out <= reg_out_s.reg8;
reg9_out <= reg_out_s.reg9;
reg10_out <= reg_out_s.reg10;
reg11_out <= reg_out_s.reg11;
reg12_out <= reg_out_s.reg12;
reg13_out <= reg_out_s.reg13;
reg14_out <= reg_out_s.reg14;
reg15_out <= reg_out_s.reg15;
reg16_out <= reg_out_s.reg16;
reg17_out <= reg_out_s.reg17;
reg18_out <= reg_out_s.reg18;
reg19_out <= reg_out_s.reg19;
reg20_out <= reg_out_s.reg20;
reg21_out <= reg_out_s.reg21;
reg22_out <= reg_out_s.reg22;
reg23_out <= reg_out_s.reg23;
reg24_out <= reg_out_s.reg24;
reg25_out <= reg_out_s.reg25;
reg26_out <= reg_out_s.reg26;
reg27_out <= reg_out_s.reg27;
reg28_out <= reg_out_s.reg28;
reg29_out <= reg_out_s.reg29;
reg30_out <= reg_out_s.reg30;
reg31_out <= reg_out_s.reg31;
reg32_out <= reg_out_s.reg32;
reg33_out <= reg_out_s.reg33;
reg34_out <= reg_out_s.reg34;
reg35_out <= reg_out_s.reg35;
reg36_out <= reg_out_s.reg36;
reg37_out <= reg_out_s.reg37;
reg38_out <= reg_out_s.reg38;
reg39_out <= reg_out_s.reg39;
reg40_out <= reg_out_s.reg40;
reg41_out <= reg_out_s.reg41;
reg42_out <= reg_out_s.reg42;
reg43_out <= reg_out_s.reg43;
reg44_out <= reg_out_s.reg44;
reg45_out <= reg_out_s.reg45;
reg46_out <= reg_out_s.reg46;
reg47_out <= reg_out_s.reg47;
reg48_out <= reg_out_s.reg48;
reg49_out <= reg_out_s.reg49;
reg50_out <= reg_out_s.reg50;
reg51_out <= reg_out_s.reg51;
reg52_out <= reg_out_s.reg52;
reg53_out <= reg_out_s.reg53;
reg54_out <= reg_out_s.reg54;
reg55_out <= reg_out_s.reg55;
reg56_out <= reg_out_s.reg56;
reg57_out <= reg_out_s.reg57;
reg58_out <= reg_out_s.reg58;
reg59_out <= reg_out_s.reg59;
reg60_out <= reg_out_s.reg60;
reg61_out <= reg_out_s.reg61;
reg62_out <= reg_out_s.reg62;
reg63_out <= reg_out_s.reg63;
reg64_out <= reg_out_s.reg64;
reg65_out <= reg_out_s.reg65;
reg66_out <= reg_out_s.reg66;
reg67_out <= reg_out_s.reg67;
reg68_out <= reg_out_s.reg68;
reg69_out <= reg_out_s.reg69;
reg70_out <= reg_out_s.reg70;
reg71_out <= reg_out_s.reg71;
reg72_out <= reg_out_s.reg72;
reg73_out <= reg_out_s.reg73;
reg74_out <= reg_out_s.reg74;
reg75_out <= reg_out_s.reg75;
reg76_out <= reg_out_s.reg76;
reg77_out <= reg_out_s.reg77;
reg78_out <= reg_out_s.reg78;
reg79_out <= reg_out_s.reg79;
reg80_out <= reg_out_s.reg80;
reg81_out <= reg_out_s.reg81;
reg82_out <= reg_out_s.reg82;
reg83_out <= reg_out_s.reg83;
reg84_out <= reg_out_s.reg84;
reg85_out <= reg_out_s.reg85;
reg86_out <= reg_out_s.reg86;
reg87_out <= reg_out_s.reg87;
reg88_out <= reg_out_s.reg88;
reg89_out <= reg_out_s.reg89;
reg90_out <= reg_out_s.reg90;
reg91_out <= reg_out_s.reg91;
reg92_out <= reg_out_s.reg92;
reg93_out <= reg_out_s.reg93;
reg94_out <= reg_out_s.reg94;
reg95_out <= reg_out_s.reg95;
reg96_out <= reg_out_s.reg96;
reg97_out <= reg_out_s.reg97;
reg98_out <= reg_out_s.reg98;
reg99_out <= reg_out_s.reg99;
reg100_out <= reg_out_s.reg100;
reg101_out <= reg_out_s.reg101;
reg102_out <= reg_out_s.reg102;
reg103_out <= reg_out_s.reg103;
reg104_out <= reg_out_s.reg104;
reg105_out <= reg_out_s.reg105;
reg106_out <= reg_out_s.reg106;
reg107_out <= reg_out_s.reg107;
reg108_out <= reg_out_s.reg108;
reg109_out <= reg_out_s.reg109;
reg110_out <= reg_out_s.reg110;
reg111_out <= reg_out_s.reg111;
reg112_out <= reg_out_s.reg112;
reg113_out <= reg_out_s.reg113;
reg114_out <= reg_out_s.reg114;
reg115_out <= reg_out_s.reg115;
reg116_out <= reg_out_s.reg116;
reg117_out <= reg_out_s.reg117;
reg118_out <= reg_out_s.reg118;
reg119_out <= reg_out_s.reg119;
reg120_out <= reg_out_s.reg120;
reg121_out <= reg_out_s.reg121;
reg122_out <= reg_out_s.reg122;
reg123_out <= reg_out_s.reg123;
reg124_out <= reg_out_s.reg124;
reg125_out <= reg_out_s.reg125;
reg126_out <= reg_out_s.reg126;
reg127_out <= reg_out_s.reg127;
reg128_out <= reg_out_s.reg128;
reg129_out <= reg_out_s.reg129;
reg130_out <= reg_out_s.reg130;
reg131_out <= reg_out_s.reg131;
reg132_out <= reg_out_s.reg132;
reg133_out <= reg_out_s.reg133;
reg134_out <= reg_out_s.reg134;
reg135_out <= reg_out_s.reg135;
reg136_out <= reg_out_s.reg136;
reg137_out <= reg_out_s.reg137;
reg138_out <= reg_out_s.reg138;
reg139_out <= reg_out_s.reg139;
reg140_out <= reg_out_s.reg140;
reg141_out <= reg_out_s.reg141;
reg142_out <= reg_out_s.reg142;
reg143_out <= reg_out_s.reg143;
reg144_out <= reg_out_s.reg144;
reg145_out <= reg_out_s.reg145;
reg146_out <= reg_out_s.reg146;
reg147_out <= reg_out_s.reg147;
reg148_out <= reg_out_s.reg148;
reg149_out <= reg_out_s.reg149;
reg150_out <= reg_out_s.reg150;
reg151_out <= reg_out_s.reg151;
reg152_out <= reg_out_s.reg152;
reg153_out <= reg_out_s.reg153;
reg154_out <= reg_out_s.reg154;
reg155_out <= reg_out_s.reg155;
reg156_out <= reg_out_s.reg156;
reg157_out <= reg_out_s.reg157;
reg158_out <= reg_out_s.reg158;
reg159_out <= reg_out_s.reg159;
reg160_out <= reg_out_s.reg160;
reg161_out <= reg_out_s.reg161;
reg162_out <= reg_out_s.reg162;
reg163_out <= reg_out_s.reg163;
reg164_out <= reg_out_s.reg164;
reg165_out <= reg_out_s.reg165;
reg166_out <= reg_out_s.reg166;
reg167_out <= reg_out_s.reg167;
reg168_out <= reg_out_s.reg168;
reg169_out <= reg_out_s.reg169;
reg170_out <= reg_out_s.reg170;
reg171_out <= reg_out_s.reg171;
reg172_out <= reg_out_s.reg172;
reg173_out <= reg_out_s.reg173;
reg174_out <= reg_out_s.reg174;
reg175_out <= reg_out_s.reg175;
reg176_out <= reg_out_s.reg176;
reg177_out <= reg_out_s.reg177;
reg178_out <= reg_out_s.reg178;
reg179_out <= reg_out_s.reg179;
reg180_out <= reg_out_s.reg180;
reg181_out <= reg_out_s.reg181;
reg182_out <= reg_out_s.reg182;
reg183_out <= reg_out_s.reg183;
reg184_out <= reg_out_s.reg184;
reg185_out <= reg_out_s.reg185;
reg186_out <= reg_out_s.reg186;
reg187_out <= reg_out_s.reg187;
reg188_out <= reg_out_s.reg188;
reg189_out <= reg_out_s.reg189;
reg190_out <= reg_out_s.reg190;
reg191_out <= reg_out_s.reg191;
reg192_out <= reg_out_s.reg192;
reg193_out <= reg_out_s.reg193;
reg194_out <= reg_out_s.reg194;
reg195_out <= reg_out_s.reg195;
reg196_out <= reg_out_s.reg196;
reg197_out <= reg_out_s.reg197;
reg198_out <= reg_out_s.reg198;
reg199_out <= reg_out_s.reg199;
reg200_out <= reg_out_s.reg200;
reg201_out <= reg_out_s.reg201;
reg202_out <= reg_out_s.reg202;
reg203_out <= reg_out_s.reg203;
reg204_out <= reg_out_s.reg204;
reg205_out <= reg_out_s.reg205;
reg206_out <= reg_out_s.reg206;
reg207_out <= reg_out_s.reg207;
reg208_out <= reg_out_s.reg208;
reg209_out <= reg_out_s.reg209;
reg210_out <= reg_out_s.reg210;
reg211_out <= reg_out_s.reg211;
reg212_out <= reg_out_s.reg212;
reg213_out <= reg_out_s.reg213;
reg214_out <= reg_out_s.reg214;
reg215_out <= reg_out_s.reg215;
reg216_out <= reg_out_s.reg216;
reg217_out <= reg_out_s.reg217;
reg218_out <= reg_out_s.reg218;
reg219_out <= reg_out_s.reg219;
reg220_out <= reg_out_s.reg220;
reg221_out <= reg_out_s.reg221;
reg222_out <= reg_out_s.reg222;
reg223_out <= reg_out_s.reg223;
reg224_out <= reg_out_s.reg224;
reg225_out <= reg_out_s.reg225;
reg226_out <= reg_out_s.reg226;
reg227_out <= reg_out_s.reg227;
reg228_out <= reg_out_s.reg228;
reg229_out <= reg_out_s.reg229;
reg230_out <= reg_out_s.reg230;
reg231_out <= reg_out_s.reg231;
reg232_out <= reg_out_s.reg232;
reg233_out <= reg_out_s.reg233;
reg234_out <= reg_out_s.reg234;
reg235_out <= reg_out_s.reg235;
reg236_out <= reg_out_s.reg236;
reg237_out <= reg_out_s.reg237;
reg238_out <= reg_out_s.reg238;
reg239_out <= reg_out_s.reg239;
reg240_out <= reg_out_s.reg240;
reg241_out <= reg_out_s.reg241;
reg242_out <= reg_out_s.reg242;
reg243_out <= reg_out_s.reg243;
reg244_out <= reg_out_s.reg244;
reg245_out <= reg_out_s.reg245;
reg246_out <= reg_out_s.reg246;
reg247_out <= reg_out_s.reg247;
reg248_out <= reg_out_s.reg248;
reg249_out <= reg_out_s.reg249;
reg250_out <= reg_out_s.reg250;
reg251_out <= reg_out_s.reg251;
reg252_out <= reg_out_s.reg252;
reg253_out <= reg_out_s.reg253;
reg254_out <= reg_out_s.reg254;
reg255_out <= reg_out_s.reg255;
-------------------------------------------------------------------------------
REGISTERS : process(wbs_in.clk)
-------------------------------------------------------------------------------
begin
-- everything sync to clk
if (rising_edge(wbs_in.clk)) then
-- reset all registers
if (wbs_in.rst = '1') then
reg_out_s.reg0 <= (others => '0');
reg_out_s.reg1 <= (others => '0');
reg_out_s.reg2 <= (others => '0');
reg_out_s.reg3 <= (others => '0');
reg_out_s.reg4 <= (others => '0');
reg_out_s.reg5 <= (others => '0');
reg_out_s.reg6 <= (others => '0');
reg_out_s.reg7 <= (others => '0');
reg_out_s.reg8 <= (others => '0');
reg_out_s.reg9 <= (others => '0');
reg_out_s.reg10 <= (others => '0');
reg_out_s.reg11 <= (others => '0');
reg_out_s.reg12 <= (others => '0');
reg_out_s.reg13 <= (others => '0');
reg_out_s.reg14 <= (others => '0');
reg_out_s.reg15 <= (others => '0');
reg_out_s.reg16 <= (others => '0');
reg_out_s.reg17 <= (others => '0');
reg_out_s.reg18 <= (others => '0');
reg_out_s.reg19 <= (others => '0');
reg_out_s.reg20 <= (others => '0');
reg_out_s.reg21 <= (others => '0');
reg_out_s.reg22 <= (others => '0');
reg_out_s.reg23 <= (others => '0');
reg_out_s.reg24 <= (others => '0');
reg_out_s.reg25 <= (others => '0');
reg_out_s.reg26 <= (others => '0');
reg_out_s.reg27 <= (others => '0');
reg_out_s.reg28 <= (others => '0');
reg_out_s.reg29 <= (others => '0');
reg_out_s.reg30 <= (others => '0');
reg_out_s.reg31 <= (others => '0');
reg_out_s.reg32 <= (others => '0');
reg_out_s.reg33 <= (others => '0');
reg_out_s.reg34 <= (others => '0');
reg_out_s.reg35 <= (others => '0');
reg_out_s.reg36 <= (others => '0');
reg_out_s.reg37 <= (others => '0');
reg_out_s.reg38 <= (others => '0');
reg_out_s.reg39 <= (others => '0');
reg_out_s.reg40 <= (others => '0');
reg_out_s.reg41 <= (others => '0');
reg_out_s.reg42 <= (others => '0');
reg_out_s.reg43 <= (others => '0');
reg_out_s.reg44 <= (others => '0');
reg_out_s.reg45 <= (others => '0');
reg_out_s.reg46 <= (others => '0');
reg_out_s.reg47 <= (others => '0');
reg_out_s.reg48 <= (others => '0');
reg_out_s.reg49 <= (others => '0');
reg_out_s.reg50 <= (others => '0');
reg_out_s.reg51 <= (others => '0');
reg_out_s.reg52 <= (others => '0');
reg_out_s.reg53 <= (others => '0');
reg_out_s.reg54 <= (others => '0');
reg_out_s.reg55 <= (others => '0');
reg_out_s.reg56 <= (others => '0');
reg_out_s.reg57 <= (others => '0');
reg_out_s.reg58 <= (others => '0');
reg_out_s.reg59 <= (others => '0');
reg_out_s.reg60 <= (others => '0');
reg_out_s.reg61 <= (others => '0');
reg_out_s.reg62 <= (others => '0');
reg_out_s.reg63 <= (others => '0');
reg_out_s.reg64 <= (others => '0');
reg_out_s.reg65 <= (others => '0');
reg_out_s.reg66 <= (others => '0');
reg_out_s.reg67 <= (others => '0');
reg_out_s.reg68 <= (others => '0');
reg_out_s.reg69 <= (others => '0');
reg_out_s.reg70 <= (others => '0');
reg_out_s.reg71 <= (others => '0');
reg_out_s.reg72 <= (others => '0');
reg_out_s.reg73 <= (others => '0');
reg_out_s.reg74 <= (others => '0');
reg_out_s.reg75 <= (others => '0');
reg_out_s.reg76 <= (others => '0');
reg_out_s.reg77 <= (others => '0');
reg_out_s.reg78 <= (others => '0');
reg_out_s.reg79 <= (others => '0');
reg_out_s.reg80 <= (others => '0');
reg_out_s.reg81 <= (others => '0');
reg_out_s.reg82 <= (others => '0');
reg_out_s.reg83 <= (others => '0');
reg_out_s.reg84 <= (others => '0');
reg_out_s.reg85 <= (others => '0');
reg_out_s.reg86 <= (others => '0');
reg_out_s.reg87 <= (others => '0');
reg_out_s.reg88 <= (others => '0');
reg_out_s.reg89 <= (others => '0');
reg_out_s.reg90 <= (others => '0');
reg_out_s.reg91 <= (others => '0');
reg_out_s.reg92 <= (others => '0');
reg_out_s.reg93 <= (others => '0');
reg_out_s.reg94 <= (others => '0');
reg_out_s.reg95 <= (others => '0');
reg_out_s.reg96 <= (others => '0');
reg_out_s.reg97 <= (others => '0');
reg_out_s.reg98 <= (others => '0');
reg_out_s.reg99 <= (others => '0');
reg_out_s.reg100 <= (others => '0');
reg_out_s.reg101 <= (others => '0');
reg_out_s.reg102 <= (others => '0');
reg_out_s.reg103 <= (others => '0');
reg_out_s.reg104 <= (others => '0');
reg_out_s.reg105 <= (others => '0');
reg_out_s.reg106 <= (others => '0');
reg_out_s.reg107 <= (others => '0');
reg_out_s.reg108 <= (others => '0');
reg_out_s.reg109 <= (others => '0');
reg_out_s.reg110 <= (others => '0');
reg_out_s.reg111 <= (others => '0');
reg_out_s.reg112 <= (others => '0');
reg_out_s.reg113 <= (others => '0');
reg_out_s.reg114 <= (others => '0');
reg_out_s.reg115 <= (others => '0');
reg_out_s.reg116 <= (others => '0');
reg_out_s.reg117 <= (others => '0');
reg_out_s.reg118 <= (others => '0');
reg_out_s.reg119 <= (others => '0');
reg_out_s.reg120 <= (others => '0');
reg_out_s.reg121 <= (others => '0');
reg_out_s.reg122 <= (others => '0');
reg_out_s.reg123 <= (others => '0');
reg_out_s.reg124 <= (others => '0');
reg_out_s.reg125 <= (others => '0');
reg_out_s.reg126 <= (others => '0');
reg_out_s.reg127 <= (others => '0');
reg_out_s.reg128 <= (others => '0');
reg_out_s.reg129 <= (others => '0');
reg_out_s.reg130 <= (others => '0');
reg_out_s.reg131 <= (others => '0');
reg_out_s.reg132 <= (others => '0');
reg_out_s.reg133 <= (others => '0');
reg_out_s.reg134 <= (others => '0');
reg_out_s.reg135 <= (others => '0');
reg_out_s.reg136 <= (others => '0');
reg_out_s.reg137 <= (others => '0');
reg_out_s.reg138 <= (others => '0');
reg_out_s.reg139 <= (others => '0');
reg_out_s.reg140 <= (others => '0');
reg_out_s.reg141 <= (others => '0');
reg_out_s.reg142 <= (others => '0');
reg_out_s.reg143 <= (others => '0');
reg_out_s.reg144 <= (others => '0');
reg_out_s.reg145 <= (others => '0');
reg_out_s.reg146 <= (others => '0');
reg_out_s.reg147 <= (others => '0');
reg_out_s.reg148 <= (others => '0');
reg_out_s.reg149 <= (others => '0');
reg_out_s.reg150 <= (others => '0');
reg_out_s.reg151 <= (others => '0');
reg_out_s.reg152 <= (others => '0');
reg_out_s.reg153 <= (others => '0');
reg_out_s.reg154 <= (others => '0');
reg_out_s.reg155 <= (others => '0');
reg_out_s.reg156 <= (others => '0');
reg_out_s.reg157 <= (others => '0');
reg_out_s.reg158 <= (others => '0');
reg_out_s.reg159 <= (others => '0');
reg_out_s.reg160 <= (others => '0');
reg_out_s.reg161 <= (others => '0');
reg_out_s.reg162 <= (others => '0');
reg_out_s.reg163 <= (others => '0');
reg_out_s.reg164 <= (others => '0');
reg_out_s.reg165 <= (others => '0');
reg_out_s.reg166 <= (others => '0');
reg_out_s.reg167 <= (others => '0');
reg_out_s.reg168 <= (others => '0');
reg_out_s.reg169 <= (others => '0');
reg_out_s.reg170 <= (others => '0');
reg_out_s.reg171 <= (others => '0');
reg_out_s.reg172 <= (others => '0');
reg_out_s.reg173 <= (others => '0');
reg_out_s.reg174 <= (others => '0');
reg_out_s.reg175 <= (others => '0');
reg_out_s.reg176 <= (others => '0');
reg_out_s.reg177 <= (others => '0');
reg_out_s.reg178 <= (others => '0');
reg_out_s.reg179 <= (others => '0');
reg_out_s.reg180 <= (others => '0');
reg_out_s.reg181 <= (others => '0');
reg_out_s.reg182 <= (others => '0');
reg_out_s.reg183 <= (others => '0');
reg_out_s.reg184 <= (others => '0');
reg_out_s.reg185 <= (others => '0');
reg_out_s.reg186 <= (others => '0');
reg_out_s.reg187 <= (others => '0');
reg_out_s.reg188 <= (others => '0');
reg_out_s.reg189 <= (others => '0');
reg_out_s.reg190 <= (others => '0');
reg_out_s.reg191 <= (others => '0');
reg_out_s.reg192 <= (others => '0');
reg_out_s.reg193 <= (others => '0');
reg_out_s.reg194 <= (others => '0');
reg_out_s.reg195 <= (others => '0');
reg_out_s.reg196 <= (others => '0');
reg_out_s.reg197 <= (others => '0');
reg_out_s.reg198 <= (others => '0');
reg_out_s.reg199 <= (others => '0');
reg_out_s.reg200 <= (others => '0');
reg_out_s.reg201 <= (others => '0');
reg_out_s.reg202 <= (others => '0');
reg_out_s.reg203 <= (others => '0');
reg_out_s.reg204 <= (others => '0');
reg_out_s.reg205 <= (others => '0');
reg_out_s.reg206 <= (others => '0');
reg_out_s.reg207 <= (others => '0');
reg_out_s.reg208 <= (others => '0');
reg_out_s.reg209 <= (others => '0');
reg_out_s.reg210 <= (others => '0');
reg_out_s.reg211 <= (others => '0');
reg_out_s.reg212 <= (others => '0');
reg_out_s.reg213 <= (others => '0');
reg_out_s.reg214 <= (others => '0');
reg_out_s.reg215 <= (others => '0');
reg_out_s.reg216 <= (others => '0');
reg_out_s.reg217 <= (others => '0');
reg_out_s.reg218 <= (others => '0');
reg_out_s.reg219 <= (others => '0');
reg_out_s.reg220 <= (others => '0');
reg_out_s.reg221 <= (others => '0');
reg_out_s.reg222 <= (others => '0');
reg_out_s.reg223 <= (others => '0');
reg_out_s.reg224 <= (others => '0');
reg_out_s.reg225 <= (others => '0');
reg_out_s.reg226 <= (others => '0');
reg_out_s.reg227 <= (others => '0');
reg_out_s.reg228 <= (others => '0');
reg_out_s.reg229 <= (others => '0');
reg_out_s.reg230 <= (others => '0');
reg_out_s.reg231 <= (others => '0');
reg_out_s.reg232 <= (others => '0');
reg_out_s.reg233 <= (others => '0');
reg_out_s.reg234 <= (others => '0');
reg_out_s.reg235 <= (others => '0');
reg_out_s.reg236 <= (others => '0');
reg_out_s.reg237 <= (others => '0');
reg_out_s.reg238 <= (others => '0');
reg_out_s.reg239 <= (others => '0');
reg_out_s.reg240 <= (others => '0');
reg_out_s.reg241 <= (others => '0');
reg_out_s.reg242 <= (others => '0');
reg_out_s.reg243 <= (others => '0');
reg_out_s.reg244 <= (others => '0');
reg_out_s.reg245 <= (others => '0');
reg_out_s.reg246 <= (others => '0');
reg_out_s.reg247 <= (others => '0');
reg_out_s.reg248 <= (others => '0');
reg_out_s.reg249 <= (others => '0');
reg_out_s.reg250 <= (others => '0');
reg_out_s.reg251 <= (others => '0');
reg_out_s.reg252 <= (others => '0');
reg_out_s.reg253 <= (others => '0');
reg_out_s.reg254 <= (others => '0');
reg_out_s.reg255 <= (others => '0');
-- store reg0
elsif(reg0_re_s = '1') then
reg_out_s.reg0 <= reg_in_s.reg0;
-- store reg1
elsif(reg1_re_s = '1') then
reg_out_s.reg1 <= reg_in_s.reg1;
-- store reg2
elsif(reg2_re_s = '1') then
reg_out_s.reg2 <= reg_in_s.reg2;
-- store reg3
elsif(reg3_re_s = '1') then
reg_out_s.reg3 <= reg_in_s.reg3;
-- store reg4
elsif(reg4_re_s = '1') then
reg_out_s.reg4 <= reg_in_s.reg4;
-- store reg5
elsif(reg5_re_s = '1') then
reg_out_s.reg5 <= reg_in_s.reg5;
-- store reg6
elsif(reg6_re_s = '1') then
reg_out_s.reg6 <= reg_in_s.reg6;
-- store reg7
elsif(reg7_re_s = '1') then
reg_out_s.reg7 <= reg_in_s.reg7;
-- store reg8
elsif(reg8_re_s = '1') then
reg_out_s.reg8 <= reg_in_s.reg8;
-- store reg9
elsif(reg9_re_s = '1') then
reg_out_s.reg9 <= reg_in_s.reg9;
-- store reg10
elsif(reg10_re_s = '1') then
reg_out_s.reg10 <= reg_in_s.reg10;
-- store reg11
elsif(reg11_re_s = '1') then
reg_out_s.reg11 <= reg_in_s.reg11;
-- store reg12
elsif(reg12_re_s = '1') then
reg_out_s.reg12 <= reg_in_s.reg12;
-- store reg13
elsif(reg13_re_s = '1') then
reg_out_s.reg13 <= reg_in_s.reg13;
-- store reg14
elsif(reg14_re_s = '1') then
reg_out_s.reg14 <= reg_in_s.reg14;
-- store reg15
elsif(reg15_re_s = '1') then
reg_out_s.reg15 <= reg_in_s.reg15;
-- store reg16
elsif(reg16_re_s = '1') then
reg_out_s.reg16 <= reg_in_s.reg16;
-- store reg17
elsif(reg17_re_s = '1') then
reg_out_s.reg17 <= reg_in_s.reg17;
-- store reg18
elsif(reg18_re_s = '1') then
reg_out_s.reg18 <= reg_in_s.reg18;
-- store reg19
elsif(reg19_re_s = '1') then
reg_out_s.reg19 <= reg_in_s.reg19;
-- store reg20
elsif(reg20_re_s = '1') then
reg_out_s.reg20 <= reg_in_s.reg20;
-- store reg21
elsif(reg21_re_s = '1') then
reg_out_s.reg21 <= reg_in_s.reg21;
-- store reg22
elsif(reg22_re_s = '1') then
reg_out_s.reg22 <= reg_in_s.reg22;
-- store reg23
elsif(reg23_re_s = '1') then
reg_out_s.reg23 <= reg_in_s.reg23;
-- store reg24
elsif(reg24_re_s = '1') then
reg_out_s.reg24 <= reg_in_s.reg24;
-- store reg25
elsif(reg25_re_s = '1') then
reg_out_s.reg25 <= reg_in_s.reg25;
-- store reg26
elsif(reg26_re_s = '1') then
reg_out_s.reg26 <= reg_in_s.reg26;
-- store reg27
elsif(reg27_re_s = '1') then
reg_out_s.reg27 <= reg_in_s.reg27;
-- store reg28
elsif(reg28_re_s = '1') then
reg_out_s.reg28 <= reg_in_s.reg28;
-- store reg29
elsif(reg29_re_s = '1') then
reg_out_s.reg29 <= reg_in_s.reg29;
-- store reg30
elsif(reg30_re_s = '1') then
reg_out_s.reg30 <= reg_in_s.reg30;
-- store reg31
elsif(reg31_re_s = '1') then
reg_out_s.reg31 <= reg_in_s.reg31;
-- store reg32
elsif(reg32_re_s = '1') then
reg_out_s.reg32 <= reg_in_s.reg32;
-- store reg33
elsif(reg33_re_s = '1') then
reg_out_s.reg33 <= reg_in_s.reg33;
-- store reg34
elsif(reg34_re_s = '1') then
reg_out_s.reg34 <= reg_in_s.reg34;
-- store reg35
elsif(reg35_re_s = '1') then
reg_out_s.reg35 <= reg_in_s.reg35;
-- store reg36
elsif(reg36_re_s = '1') then
reg_out_s.reg36 <= reg_in_s.reg36;
-- store reg37
elsif(reg37_re_s = '1') then
reg_out_s.reg37 <= reg_in_s.reg37;
-- store reg38
elsif(reg38_re_s = '1') then
reg_out_s.reg38 <= reg_in_s.reg38;
-- store reg39
elsif(reg39_re_s = '1') then
reg_out_s.reg39 <= reg_in_s.reg39;
-- store reg40
elsif(reg40_re_s = '1') then
reg_out_s.reg40 <= reg_in_s.reg40;
-- store reg41
elsif(reg41_re_s = '1') then
reg_out_s.reg41 <= reg_in_s.reg41;
-- store reg42
elsif(reg42_re_s = '1') then
reg_out_s.reg42 <= reg_in_s.reg42;
-- store reg43
elsif(reg43_re_s = '1') then
reg_out_s.reg43 <= reg_in_s.reg43;
-- store reg44
elsif(reg44_re_s = '1') then
reg_out_s.reg44 <= reg_in_s.reg44;
-- store reg45
elsif(reg45_re_s = '1') then
reg_out_s.reg45 <= reg_in_s.reg45;
-- store reg46
elsif(reg46_re_s = '1') then
reg_out_s.reg46 <= reg_in_s.reg46;
-- store reg47
elsif(reg47_re_s = '1') then
reg_out_s.reg47 <= reg_in_s.reg47;
-- store reg48
elsif(reg48_re_s = '1') then
reg_out_s.reg48 <= reg_in_s.reg48;
-- store reg49
elsif(reg49_re_s = '1') then
reg_out_s.reg49 <= reg_in_s.reg49;
-- store reg50
elsif(reg50_re_s = '1') then
reg_out_s.reg50 <= reg_in_s.reg50;
-- store reg51
elsif(reg51_re_s = '1') then
reg_out_s.reg51 <= reg_in_s.reg51;
-- store reg52
elsif(reg52_re_s = '1') then
reg_out_s.reg52 <= reg_in_s.reg52;
-- store reg53
elsif(reg53_re_s = '1') then
reg_out_s.reg53 <= reg_in_s.reg53;
-- store reg54
elsif(reg54_re_s = '1') then
reg_out_s.reg54 <= reg_in_s.reg54;
-- store reg55
elsif(reg55_re_s = '1') then
reg_out_s.reg55 <= reg_in_s.reg55;
-- store reg56
elsif(reg56_re_s = '1') then
reg_out_s.reg56 <= reg_in_s.reg56;
-- store reg57
elsif(reg57_re_s = '1') then
reg_out_s.reg57 <= reg_in_s.reg57;
-- store reg58
elsif(reg58_re_s = '1') then
reg_out_s.reg58 <= reg_in_s.reg58;
-- store reg59
elsif(reg59_re_s = '1') then
reg_out_s.reg59 <= reg_in_s.reg59;
-- store reg60
elsif(reg60_re_s = '1') then
reg_out_s.reg60 <= reg_in_s.reg60;
-- store reg61
elsif(reg61_re_s = '1') then
reg_out_s.reg61 <= reg_in_s.reg61;
-- store reg62
elsif(reg62_re_s = '1') then
reg_out_s.reg62 <= reg_in_s.reg62;
-- store reg63
elsif(reg63_re_s = '1') then
reg_out_s.reg63 <= reg_in_s.reg63;
-- store reg64
elsif(reg64_re_s = '1') then
reg_out_s.reg64 <= reg_in_s.reg64;
-- store reg65
elsif(reg65_re_s = '1') then
reg_out_s.reg65 <= reg_in_s.reg65;
-- store reg66
elsif(reg66_re_s = '1') then
reg_out_s.reg66 <= reg_in_s.reg66;
-- store reg67
elsif(reg67_re_s = '1') then
reg_out_s.reg67 <= reg_in_s.reg67;
-- store reg68
elsif(reg68_re_s = '1') then
reg_out_s.reg68 <= reg_in_s.reg68;
-- store reg69
elsif(reg69_re_s = '1') then
reg_out_s.reg69 <= reg_in_s.reg69;
-- store reg70
elsif(reg70_re_s = '1') then
reg_out_s.reg70 <= reg_in_s.reg70;
-- store reg71
elsif(reg71_re_s = '1') then
reg_out_s.reg71 <= reg_in_s.reg71;
-- store reg72
elsif(reg72_re_s = '1') then
reg_out_s.reg72 <= reg_in_s.reg72;
-- store reg73
elsif(reg73_re_s = '1') then
reg_out_s.reg73 <= reg_in_s.reg73;
-- store reg74
elsif(reg74_re_s = '1') then
reg_out_s.reg74 <= reg_in_s.reg74;
-- store reg75
elsif(reg75_re_s = '1') then
reg_out_s.reg75 <= reg_in_s.reg75;
-- store reg76
elsif(reg76_re_s = '1') then
reg_out_s.reg76 <= reg_in_s.reg76;
-- store reg77
elsif(reg77_re_s = '1') then
reg_out_s.reg77 <= reg_in_s.reg77;
-- store reg78
elsif(reg78_re_s = '1') then
reg_out_s.reg78 <= reg_in_s.reg78;
-- store reg79
elsif(reg79_re_s = '1') then
reg_out_s.reg79 <= reg_in_s.reg79;
-- store reg80
elsif(reg80_re_s = '1') then
reg_out_s.reg80 <= reg_in_s.reg80;
-- store reg81
elsif(reg81_re_s = '1') then
reg_out_s.reg81 <= reg_in_s.reg81;
-- store reg82
elsif(reg82_re_s = '1') then
reg_out_s.reg82 <= reg_in_s.reg82;
-- store reg83
elsif(reg83_re_s = '1') then
reg_out_s.reg83 <= reg_in_s.reg83;
-- store reg84
elsif(reg84_re_s = '1') then
reg_out_s.reg84 <= reg_in_s.reg84;
-- store reg85
elsif(reg85_re_s = '1') then
reg_out_s.reg85 <= reg_in_s.reg85;
-- store reg86
elsif(reg86_re_s = '1') then
reg_out_s.reg86 <= reg_in_s.reg86;
-- store reg87
elsif(reg87_re_s = '1') then
reg_out_s.reg87 <= reg_in_s.reg87;
-- store reg88
elsif(reg88_re_s = '1') then
reg_out_s.reg88 <= reg_in_s.reg88;
-- store reg89
elsif(reg89_re_s = '1') then
reg_out_s.reg89 <= reg_in_s.reg89;
-- store reg90
elsif(reg90_re_s = '1') then
reg_out_s.reg90 <= reg_in_s.reg90;
-- store reg91
elsif(reg91_re_s = '1') then
reg_out_s.reg91 <= reg_in_s.reg91;
-- store reg92
elsif(reg92_re_s = '1') then
reg_out_s.reg92 <= reg_in_s.reg92;
-- store reg93
elsif(reg93_re_s = '1') then
reg_out_s.reg93 <= reg_in_s.reg93;
-- store reg94
elsif(reg94_re_s = '1') then
reg_out_s.reg94 <= reg_in_s.reg94;
-- store reg95
elsif(reg95_re_s = '1') then
reg_out_s.reg95 <= reg_in_s.reg95;
-- store reg96
elsif(reg96_re_s = '1') then
reg_out_s.reg96 <= reg_in_s.reg96;
-- store reg97
elsif(reg97_re_s = '1') then
reg_out_s.reg97 <= reg_in_s.reg97;
-- store reg98
elsif(reg98_re_s = '1') then
reg_out_s.reg98 <= reg_in_s.reg98;
-- store reg99
elsif(reg99_re_s = '1') then
reg_out_s.reg99 <= reg_in_s.reg99;
-- store reg100
elsif(reg100_re_s = '1') then
reg_out_s.reg100 <= reg_in_s.reg100;
-- store reg101
elsif(reg101_re_s = '1') then
reg_out_s.reg101 <= reg_in_s.reg101;
-- store reg102
elsif(reg102_re_s = '1') then
reg_out_s.reg102 <= reg_in_s.reg102;
-- store reg103
elsif(reg103_re_s = '1') then
reg_out_s.reg103 <= reg_in_s.reg103;
-- store reg104
elsif(reg104_re_s = '1') then
reg_out_s.reg104 <= reg_in_s.reg104;
-- store reg105
elsif(reg105_re_s = '1') then
reg_out_s.reg105 <= reg_in_s.reg105;
-- store reg106
elsif(reg106_re_s = '1') then
reg_out_s.reg106 <= reg_in_s.reg106;
-- store reg107
elsif(reg107_re_s = '1') then
reg_out_s.reg107 <= reg_in_s.reg107;
-- store reg108
elsif(reg108_re_s = '1') then
reg_out_s.reg108 <= reg_in_s.reg108;
-- store reg109
elsif(reg109_re_s = '1') then
reg_out_s.reg109 <= reg_in_s.reg109;
-- store reg110
elsif(reg110_re_s = '1') then
reg_out_s.reg110 <= reg_in_s.reg110;
-- store reg111
elsif(reg111_re_s = '1') then
reg_out_s.reg111 <= reg_in_s.reg111;
-- store reg112
elsif(reg112_re_s = '1') then
reg_out_s.reg112 <= reg_in_s.reg112;
-- store reg113
elsif(reg113_re_s = '1') then
reg_out_s.reg113 <= reg_in_s.reg113;
-- store reg114
elsif(reg114_re_s = '1') then
reg_out_s.reg114 <= reg_in_s.reg114;
-- store reg115
elsif(reg115_re_s = '1') then
reg_out_s.reg115 <= reg_in_s.reg115;
-- store reg116
elsif(reg116_re_s = '1') then
reg_out_s.reg116 <= reg_in_s.reg116;
-- store reg117
elsif(reg117_re_s = '1') then
reg_out_s.reg117 <= reg_in_s.reg117;
-- store reg118
elsif(reg118_re_s = '1') then
reg_out_s.reg118 <= reg_in_s.reg118;
-- store reg119
elsif(reg119_re_s = '1') then
reg_out_s.reg119 <= reg_in_s.reg119;
-- store reg120
elsif(reg120_re_s = '1') then
reg_out_s.reg120 <= reg_in_s.reg120;
-- store reg121
elsif(reg121_re_s = '1') then
reg_out_s.reg121 <= reg_in_s.reg121;
-- store reg122
elsif(reg122_re_s = '1') then
reg_out_s.reg122 <= reg_in_s.reg122;
-- store reg123
elsif(reg123_re_s = '1') then
reg_out_s.reg123 <= reg_in_s.reg123;
-- store reg124
elsif(reg124_re_s = '1') then
reg_out_s.reg124 <= reg_in_s.reg124;
-- store reg125
elsif(reg125_re_s = '1') then
reg_out_s.reg125 <= reg_in_s.reg125;
-- store reg126
elsif(reg126_re_s = '1') then
reg_out_s.reg126 <= reg_in_s.reg126;
-- store reg127
elsif(reg127_re_s = '1') then
reg_out_s.reg127 <= reg_in_s.reg127;
-- store reg128
elsif(reg128_re_s = '1') then
reg_out_s.reg128 <= reg_in_s.reg128;
-- store reg129
elsif(reg129_re_s = '1') then
reg_out_s.reg129 <= reg_in_s.reg129;
-- store reg130
elsif(reg130_re_s = '1') then
reg_out_s.reg130 <= reg_in_s.reg130;
-- store reg131
elsif(reg131_re_s = '1') then
reg_out_s.reg131 <= reg_in_s.reg131;
-- store reg132
elsif(reg132_re_s = '1') then
reg_out_s.reg132 <= reg_in_s.reg132;
-- store reg133
elsif(reg133_re_s = '1') then
reg_out_s.reg133 <= reg_in_s.reg133;
-- store reg134
elsif(reg134_re_s = '1') then
reg_out_s.reg134 <= reg_in_s.reg134;
-- store reg135
elsif(reg135_re_s = '1') then
reg_out_s.reg135 <= reg_in_s.reg135;
-- store reg136
elsif(reg136_re_s = '1') then
reg_out_s.reg136 <= reg_in_s.reg136;
-- store reg137
elsif(reg137_re_s = '1') then
reg_out_s.reg137 <= reg_in_s.reg137;
-- store reg138
elsif(reg138_re_s = '1') then
reg_out_s.reg138 <= reg_in_s.reg138;
-- store reg139
elsif(reg139_re_s = '1') then
reg_out_s.reg139 <= reg_in_s.reg139;
-- store reg140
elsif(reg140_re_s = '1') then
reg_out_s.reg140 <= reg_in_s.reg140;
-- store reg141
elsif(reg141_re_s = '1') then
reg_out_s.reg141 <= reg_in_s.reg141;
-- store reg142
elsif(reg142_re_s = '1') then
reg_out_s.reg142 <= reg_in_s.reg142;
-- store reg143
elsif(reg143_re_s = '1') then
reg_out_s.reg143 <= reg_in_s.reg143;
-- store reg144
elsif(reg144_re_s = '1') then
reg_out_s.reg144 <= reg_in_s.reg144;
-- store reg145
elsif(reg145_re_s = '1') then
reg_out_s.reg145 <= reg_in_s.reg145;
-- store reg146
elsif(reg146_re_s = '1') then
reg_out_s.reg146 <= reg_in_s.reg146;
-- store reg147
elsif(reg147_re_s = '1') then
reg_out_s.reg147 <= reg_in_s.reg147;
-- store reg148
elsif(reg148_re_s = '1') then
reg_out_s.reg148 <= reg_in_s.reg148;
-- store reg149
elsif(reg149_re_s = '1') then
reg_out_s.reg149 <= reg_in_s.reg149;
-- store reg150
elsif(reg150_re_s = '1') then
reg_out_s.reg150 <= reg_in_s.reg150;
-- store reg151
elsif(reg151_re_s = '1') then
reg_out_s.reg151 <= reg_in_s.reg151;
-- store reg152
elsif(reg152_re_s = '1') then
reg_out_s.reg152 <= reg_in_s.reg152;
-- store reg153
elsif(reg153_re_s = '1') then
reg_out_s.reg153 <= reg_in_s.reg153;
-- store reg154
elsif(reg154_re_s = '1') then
reg_out_s.reg154 <= reg_in_s.reg154;
-- store reg155
elsif(reg155_re_s = '1') then
reg_out_s.reg155 <= reg_in_s.reg155;
-- store reg156
elsif(reg156_re_s = '1') then
reg_out_s.reg156 <= reg_in_s.reg156;
-- store reg157
elsif(reg157_re_s = '1') then
reg_out_s.reg157 <= reg_in_s.reg157;
-- store reg158
elsif(reg158_re_s = '1') then
reg_out_s.reg158 <= reg_in_s.reg158;
-- store reg159
elsif(reg159_re_s = '1') then
reg_out_s.reg159 <= reg_in_s.reg159;
-- store reg160
elsif(reg160_re_s = '1') then
reg_out_s.reg160 <= reg_in_s.reg160;
-- store reg161
elsif(reg161_re_s = '1') then
reg_out_s.reg161 <= reg_in_s.reg161;
-- store reg162
elsif(reg162_re_s = '1') then
reg_out_s.reg162 <= reg_in_s.reg162;
-- store reg163
elsif(reg163_re_s = '1') then
reg_out_s.reg163 <= reg_in_s.reg163;
-- store reg164
elsif(reg164_re_s = '1') then
reg_out_s.reg164 <= reg_in_s.reg164;
-- store reg165
elsif(reg165_re_s = '1') then
reg_out_s.reg165 <= reg_in_s.reg165;
-- store reg166
elsif(reg166_re_s = '1') then
reg_out_s.reg166 <= reg_in_s.reg166;
-- store reg167
elsif(reg167_re_s = '1') then
reg_out_s.reg167 <= reg_in_s.reg167;
-- store reg168
elsif(reg168_re_s = '1') then
reg_out_s.reg168 <= reg_in_s.reg168;
-- store reg169
elsif(reg169_re_s = '1') then
reg_out_s.reg169 <= reg_in_s.reg169;
-- store reg170
elsif(reg170_re_s = '1') then
reg_out_s.reg170 <= reg_in_s.reg170;
-- store reg171
elsif(reg171_re_s = '1') then
reg_out_s.reg171 <= reg_in_s.reg171;
-- store reg172
elsif(reg172_re_s = '1') then
reg_out_s.reg172 <= reg_in_s.reg172;
-- store reg173
elsif(reg173_re_s = '1') then
reg_out_s.reg173 <= reg_in_s.reg173;
-- store reg174
elsif(reg174_re_s = '1') then
reg_out_s.reg174 <= reg_in_s.reg174;
-- store reg175
elsif(reg175_re_s = '1') then
reg_out_s.reg175 <= reg_in_s.reg175;
-- store reg176
elsif(reg176_re_s = '1') then
reg_out_s.reg176 <= reg_in_s.reg176;
-- store reg177
elsif(reg177_re_s = '1') then
reg_out_s.reg177 <= reg_in_s.reg177;
-- store reg178
elsif(reg178_re_s = '1') then
reg_out_s.reg178 <= reg_in_s.reg178;
-- store reg179
elsif(reg179_re_s = '1') then
reg_out_s.reg179 <= reg_in_s.reg179;
-- store reg180
elsif(reg180_re_s = '1') then
reg_out_s.reg180 <= reg_in_s.reg180;
-- store reg181
elsif(reg181_re_s = '1') then
reg_out_s.reg181 <= reg_in_s.reg181;
-- store reg182
elsif(reg182_re_s = '1') then
reg_out_s.reg182 <= reg_in_s.reg182;
-- store reg183
elsif(reg183_re_s = '1') then
reg_out_s.reg183 <= reg_in_s.reg183;
-- store reg184
elsif(reg184_re_s = '1') then
reg_out_s.reg184 <= reg_in_s.reg184;
-- store reg185
elsif(reg185_re_s = '1') then
reg_out_s.reg185 <= reg_in_s.reg185;
-- store reg186
elsif(reg186_re_s = '1') then
reg_out_s.reg186 <= reg_in_s.reg186;
-- store reg187
elsif(reg187_re_s = '1') then
reg_out_s.reg187 <= reg_in_s.reg187;
-- store reg188
elsif(reg188_re_s = '1') then
reg_out_s.reg188 <= reg_in_s.reg188;
-- store reg189
elsif(reg189_re_s = '1') then
reg_out_s.reg189 <= reg_in_s.reg189;
-- store reg190
elsif(reg190_re_s = '1') then
reg_out_s.reg190 <= reg_in_s.reg190;
-- store reg191
elsif(reg191_re_s = '1') then
reg_out_s.reg191 <= reg_in_s.reg191;
-- store reg192
elsif(reg192_re_s = '1') then
reg_out_s.reg192 <= reg_in_s.reg192;
-- store reg193
elsif(reg193_re_s = '1') then
reg_out_s.reg193 <= reg_in_s.reg193;
-- store reg194
elsif(reg194_re_s = '1') then
reg_out_s.reg194 <= reg_in_s.reg194;
-- store reg195
elsif(reg195_re_s = '1') then
reg_out_s.reg195 <= reg_in_s.reg195;
-- store reg196
elsif(reg196_re_s = '1') then
reg_out_s.reg196 <= reg_in_s.reg196;
-- store reg197
elsif(reg197_re_s = '1') then
reg_out_s.reg197 <= reg_in_s.reg197;
-- store reg198
elsif(reg198_re_s = '1') then
reg_out_s.reg198 <= reg_in_s.reg198;
-- store reg199
elsif(reg199_re_s = '1') then
reg_out_s.reg199 <= reg_in_s.reg199;
-- store reg200
elsif(reg200_re_s = '1') then
reg_out_s.reg200 <= reg_in_s.reg200;
-- store reg201
elsif(reg201_re_s = '1') then
reg_out_s.reg201 <= reg_in_s.reg201;
-- store reg202
elsif(reg202_re_s = '1') then
reg_out_s.reg202 <= reg_in_s.reg202;
-- store reg203
elsif(reg203_re_s = '1') then
reg_out_s.reg203 <= reg_in_s.reg203;
-- store reg204
elsif(reg204_re_s = '1') then
reg_out_s.reg204 <= reg_in_s.reg204;
-- store reg205
elsif(reg205_re_s = '1') then
reg_out_s.reg205 <= reg_in_s.reg205;
-- store reg206
elsif(reg206_re_s = '1') then
reg_out_s.reg206 <= reg_in_s.reg206;
-- store reg207
elsif(reg207_re_s = '1') then
reg_out_s.reg207 <= reg_in_s.reg207;
-- store reg208
elsif(reg208_re_s = '1') then
reg_out_s.reg208 <= reg_in_s.reg208;
-- store reg209
elsif(reg209_re_s = '1') then
reg_out_s.reg209 <= reg_in_s.reg209;
-- store reg210
elsif(reg210_re_s = '1') then
reg_out_s.reg210 <= reg_in_s.reg210;
-- store reg211
elsif(reg211_re_s = '1') then
reg_out_s.reg211 <= reg_in_s.reg211;
-- store reg212
elsif(reg212_re_s = '1') then
reg_out_s.reg212 <= reg_in_s.reg212;
-- store reg213
elsif(reg213_re_s = '1') then
reg_out_s.reg213 <= reg_in_s.reg213;
-- store reg214
elsif(reg214_re_s = '1') then
reg_out_s.reg214 <= reg_in_s.reg214;
-- store reg215
elsif(reg215_re_s = '1') then
reg_out_s.reg215 <= reg_in_s.reg215;
-- store reg216
elsif(reg216_re_s = '1') then
reg_out_s.reg216 <= reg_in_s.reg216;
-- store reg217
elsif(reg217_re_s = '1') then
reg_out_s.reg217 <= reg_in_s.reg217;
-- store reg218
elsif(reg218_re_s = '1') then
reg_out_s.reg218 <= reg_in_s.reg218;
-- store reg219
elsif(reg219_re_s = '1') then
reg_out_s.reg219 <= reg_in_s.reg219;
-- store reg220
elsif(reg220_re_s = '1') then
reg_out_s.reg220 <= reg_in_s.reg220;
-- store reg221
elsif(reg221_re_s = '1') then
reg_out_s.reg221 <= reg_in_s.reg221;
-- store reg222
elsif(reg222_re_s = '1') then
reg_out_s.reg222 <= reg_in_s.reg222;
-- store reg223
elsif(reg223_re_s = '1') then
reg_out_s.reg223 <= reg_in_s.reg223;
-- store reg224
elsif(reg224_re_s = '1') then
reg_out_s.reg224 <= reg_in_s.reg224;
-- store reg225
elsif(reg225_re_s = '1') then
reg_out_s.reg225 <= reg_in_s.reg225;
-- store reg226
elsif(reg226_re_s = '1') then
reg_out_s.reg226 <= reg_in_s.reg226;
-- store reg227
elsif(reg227_re_s = '1') then
reg_out_s.reg227 <= reg_in_s.reg227;
-- store reg228
elsif(reg228_re_s = '1') then
reg_out_s.reg228 <= reg_in_s.reg228;
-- store reg229
elsif(reg229_re_s = '1') then
reg_out_s.reg229 <= reg_in_s.reg229;
-- store reg230
elsif(reg230_re_s = '1') then
reg_out_s.reg230 <= reg_in_s.reg230;
-- store reg231
elsif(reg231_re_s = '1') then
reg_out_s.reg231 <= reg_in_s.reg231;
-- store reg232
elsif(reg232_re_s = '1') then
reg_out_s.reg232 <= reg_in_s.reg232;
-- store reg233
elsif(reg233_re_s = '1') then
reg_out_s.reg233 <= reg_in_s.reg233;
-- store reg234
elsif(reg234_re_s = '1') then
reg_out_s.reg234 <= reg_in_s.reg234;
-- store reg235
elsif(reg235_re_s = '1') then
reg_out_s.reg235 <= reg_in_s.reg235;
-- store reg236
elsif(reg236_re_s = '1') then
reg_out_s.reg236 <= reg_in_s.reg236;
-- store reg237
elsif(reg237_re_s = '1') then
reg_out_s.reg237 <= reg_in_s.reg237;
-- store reg238
elsif(reg238_re_s = '1') then
reg_out_s.reg238 <= reg_in_s.reg238;
-- store reg239
elsif(reg239_re_s = '1') then
reg_out_s.reg239 <= reg_in_s.reg239;
-- store reg240
elsif(reg240_re_s = '1') then
reg_out_s.reg240 <= reg_in_s.reg240;
-- store reg241
elsif(reg241_re_s = '1') then
reg_out_s.reg241 <= reg_in_s.reg241;
-- store reg242
elsif(reg242_re_s = '1') then
reg_out_s.reg242 <= reg_in_s.reg242;
-- store reg243
elsif(reg243_re_s = '1') then
reg_out_s.reg243 <= reg_in_s.reg243;
-- store reg244
elsif(reg244_re_s = '1') then
reg_out_s.reg244 <= reg_in_s.reg244;
-- store reg245
elsif(reg245_re_s = '1') then
reg_out_s.reg245 <= reg_in_s.reg245;
-- store reg246
elsif(reg246_re_s = '1') then
reg_out_s.reg246 <= reg_in_s.reg246;
-- store reg247
elsif(reg247_re_s = '1') then
reg_out_s.reg247 <= reg_in_s.reg247;
-- store reg248
elsif(reg248_re_s = '1') then
reg_out_s.reg248 <= reg_in_s.reg248;
-- store reg249
elsif(reg249_re_s = '1') then
reg_out_s.reg249 <= reg_in_s.reg249;
-- store reg250
elsif(reg250_re_s = '1') then
reg_out_s.reg250 <= reg_in_s.reg250;
-- store reg251
elsif(reg251_re_s = '1') then
reg_out_s.reg251 <= reg_in_s.reg251;
-- store reg252
elsif(reg252_re_s = '1') then
reg_out_s.reg252 <= reg_in_s.reg252;
-- store reg253
elsif(reg253_re_s = '1') then
reg_out_s.reg253 <= reg_in_s.reg253;
-- store reg254
elsif(reg254_re_s = '1') then
reg_out_s.reg254 <= reg_in_s.reg254;
-- store reg255
elsif(reg255_re_s = '1') then
reg_out_s.reg255 <= reg_in_s.reg255;
-- hold
else
reg_out_s <= reg_out_s;
end if;
end if;
end process REGISTERS;
end behavioral;
|
gpl-3.0
|
cc6391ef6a1a8b173f657dfcdb20919b
| 0.586405 | 2.628749 | false | false | false | false |
xylnao/w11a-extra
|
rtl/bplib/bpgen/sn_humanio_rbus.vhd
| 1 | 11,488 |
-- $Id: sn_humanio_rbus.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_humanio_rbus - syn
-- Description: sn_humanio with rbus interceptor
--
-- Dependencies: bpgen/sn_humanio
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1, 13.1, 13.4; ghdl 0.26-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-08-14 406 12.1 M53d xc3s1000-4 142 156 0 123 s 5.1 ns
-- 2011-08-07 404 12.1 M53d xc3s1000-4 142 157 0 124 s 5.1 ns
-- 2010-12-29 351 12.1 M53d xc3s1000-4 93 138 0 111 s 6.8 ns
-- 2010-06-03 300 11.4 L68 xc3s1000-4 92 137 0 111 s 6.7 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-02-24 ??? 1.2.? made SWIDTH and LWIDTH generic
-- 2011-11-19 427 1.2.1 now numeric_std clean
-- 2011-08-14 406 1.2 common register layout with bp_swibtnled_rbus
-- 2011-08-07 404 1.3 add pipeline regs ledin,(swi,btn,led,dp,dat)eff
-- 2011-07-08 390 1.2 renamed from s3_humanio_rbus, add BWIDTH generic
-- 2010-12-29 351 1.1 renamed from s3_humanio_rri; ported to rbv3
-- 2010-06-18 306 1.0.1 rename rbus data fields to _rbf_
-- 2010-06-03 300 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Address Bits Name r/w/f Function
-- bbbbbb00 cntl r/w/- Control register and BTN access
-- x:08 btn r/w/- r: return hio BTN status
-- w: ored with hio BTN to drive BTN
-- 3 dsp_en r/w/- if 1 display data will be driven by rbus
-- 2 dp_en r/w/- if 1 display dp's will be driven by rbus
-- 1 led_en r/w/- if 1 LED will be driven by rri
-- 0 swi_en r/w/- if 1 SWI will be driven by rri
--
-- bbbbbb01 7:00 swi r/w/- r: return hio SWI status
-- w: will drive SWI when swi_en=1
--
-- bbbbbb10 led r/w/- Interface to LED and DSP_DP
-- 15:12 dp r/w/- r: returns DSP_DP status
-- w: will drive display dp's when dp_en=1
-- 7:00 led r/w/- r: returns LED status
-- w: will drive led's when led_en=1
--
-- bbbbbb11 15:00 dsp r/w/- r: return hio DSP_DAT status
-- w: will drive DSP_DAT when dsp_en=1
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity sn_humanio_rbus is -- human i/o handling /w rbus intercept
generic (
SWIDTH : positive := 8; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
);
end sn_humanio_rbus;
architecture syn of sn_humanio_rbus is
type regs_type is record
rbsel : slbit; -- rbus select
swi : slv(SWIDTH-1 downto 0); -- rbus swi
btn : slv(BWIDTH-1 downto 0); -- rbus btn
led : slv(LWIDTH-1 downto 0); -- rbus led
dsp_dat : slv16; -- rbus dsp_dat
dsp_dp : slv4; -- rbus dsp_dp
ledin : slv(LWIDTH-1 downto 0); -- led from design
swieff : slv(SWIDTH-1 downto 0); -- effective swi
btneff : slv(BWIDTH-1 downto 0); -- effective btn
ledeff : slv(LWIDTH-1 downto 0); -- effective led
dpeff : slv4; -- effective dsp_dp
dateff : slv16; -- effective dsp_dat
swi_en : slbit; -- enable: swi from rbus
led_en : slbit; -- enable: led from rbus
dsp_en : slbit; -- enable: dsp_dat from rbus
dp_en : slbit; -- enable: dsp_dp from rbus
end record regs_type;
constant btnzero : slv(BWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
'0', -- rbsel
(others=>'0'), -- swi
btnzero, -- btn
(others=>'0'), -- led
(others=>'0'), -- dsp_dat
(others=>'0'), -- dsp_dp
(others=>'0'), -- ledin
(others=>'0'), -- swieff
btnzero, -- btneff
(others=>'0'), -- ledeff
(others=>'0'), -- dpeff
(others=>'0'), -- dateff
'0','0','0','0' -- (swi|led|dsp|dp)_en
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
subtype cntl_rbf_btn is integer range BWIDTH+8-1 downto 8;
constant cntl_rbf_dsp_en: integer := 3;
constant cntl_rbf_dp_en: integer := 2;
constant cntl_rbf_led_en: integer := 1;
constant cntl_rbf_swi_en: integer := 0;
subtype led_rbf_dp is integer range 15 downto 12;
subtype led_rbf_led is integer range LWIDTH-1 downto 0;
constant rbaddr_cntl: slv2 := "00"; -- 0 r/w/-
constant rbaddr_swi: slv2 := "01"; -- 1 r/w/-
constant rbaddr_led: slv2 := "10"; -- 2 r/w/-
constant rbaddr_dsp: slv2 := "11"; -- 3 r/w/-
signal HIO_SWI : slv(SWIDTH-1 downto 0) := (others=>'0');
signal HIO_BTN : slv(BWIDTH-1 downto 0) := (others=>'0');
signal HIO_LED : slv(LWIDTH-1 downto 0) := (others=>'0');
signal HIO_DSP_DAT : slv16 := (others=>'0');
signal HIO_DSP_DP : slv4 := (others=>'0');
begin
HIO : sn_humanio
generic map (
SWIDTH => SWIDTH,
BWIDTH => BWIDTH,
LWIDTH => LWIDTH,
DEBOUNCE => DEBOUNCE)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => HIO_SWI,
BTN => HIO_BTN,
LED => HIO_LED,
DSP_DAT => HIO_DSP_DAT,
DSP_DP => HIO_DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, LED, DSP_DAT, DSP_DP,
HIO_SWI, HIO_BTN, HIO_DSP_DAT, HIO_DSP_DP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
-- input register for LED signal
n.ledin := LED;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 2)=RB_ADDR(7 downto 2) then
n.rbsel := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl =>
irb_dout(cntl_rbf_btn) := HIO_BTN;
irb_dout(cntl_rbf_dsp_en) := r.dsp_en;
irb_dout(cntl_rbf_dp_en) := r.dp_en;
irb_dout(cntl_rbf_led_en) := r.led_en;
irb_dout(cntl_rbf_swi_en) := r.swi_en;
if RB_MREQ.we = '1' then
n.btn := RB_MREQ.din(cntl_rbf_btn);
n.dsp_en := RB_MREQ.din(cntl_rbf_dsp_en);
n.dp_en := RB_MREQ.din(cntl_rbf_dp_en);
n.led_en := RB_MREQ.din(cntl_rbf_led_en);
n.swi_en := RB_MREQ.din(cntl_rbf_swi_en);
end if;
when rbaddr_swi =>
irb_dout(HIO_SWI'range) := HIO_SWI;
if RB_MREQ.we = '1' then
n.swi := RB_MREQ.din(n.swi'range);
end if;
when rbaddr_led =>
irb_dout(led_rbf_dp) := HIO_DSP_DP;
irb_dout(led_rbf_led) := r.ledin;
if RB_MREQ.we = '1' then
n.dsp_dp := RB_MREQ.din(led_rbf_dp);
n.led := RB_MREQ.din(led_rbf_led);
end if;
when rbaddr_dsp =>
irb_dout := HIO_DSP_DAT;
if RB_MREQ.we = '1' then
n.dsp_dat := RB_MREQ.din;
end if;
when others => null;
end case;
end if;
n.btneff := HIO_BTN or r.btn;
if r.swi_en = '0' then
n.swieff := HIO_SWI;
else
n.swieff := r.swi;
end if;
if r.led_en = '0' then
n.ledeff := r.ledin;
else
n.ledeff := r.led;
end if;
if r.dp_en = '0' then
n.dpeff := DSP_DP;
else
n.dpeff := r.dsp_dp;
end if;
if r.dsp_en = '0' then
n.dateff := DSP_DAT;
else
n.dateff := r.dsp_dat;
end if;
N_REGS <= n;
BTN <= R_REGS.btneff;
SWI <= R_REGS.swieff;
HIO_LED <= R_REGS.ledeff;
HIO_DSP_DP <= R_REGS.dpeff;
HIO_DSP_DAT <= R_REGS.dateff;
RB_SRES <= rb_sres_init;
RB_SRES.ack <= irb_ack;
RB_SRES.busy <= irb_busy;
RB_SRES.err <= irb_err;
RB_SRES.dout <= irb_dout;
end process proc_next;
end syn;
|
gpl-2.0
|
ab6ecbd04fda7e1ec8a7bf3f34c54d84
| 0.494429 | 3.369903 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vhd
| 1 | 7,515 |
-- $Id: sys_tst_serloop1_n2.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop1_n2 - syn
-- Description: Tester serial link for nexys2
--
-- Dependencies: genlib/clkdivce
-- bpgen/bp_rs232_2l4l_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_1clock
-- tst_serloop
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-16 439 13.1 O40d xc3s1200e-4 433 634 64 490 t 13.1
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-16 439 0.5 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serport.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop1_n2 is -- top level
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_serloop1_n2;
architecture syn of sys_tst_serloop1_n2 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
begin
CLK <= I_CLK50;
O_CLKSYS <= CLK;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0), -- port selection
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
SERPORT : serport_1clock
generic map (
CDWIDTH => 15,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
|
gpl-2.0
|
e77f65d561e6a91b98a5b2128cdc3ed4
| 0.491417 | 3.347439 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd
| 1 | 8,250 |
-- $Id: sys_tst_rlink_s3.vhd 442 2011-12-23 10:03:28Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_s3 - syn
-- Description: rlink tester design for s3board
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- vlib/rbus/rb_sres_or_2
-- bplib/s3board/s3_sram_dummy
--
-- Test bench: tb/tb_tst_rlink_s3
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-22 442 13.1 O40d xc3s1000e-4 765 1672 96 1088 t 12.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-22 442 1.0 Initial version (derived from sys_tst_rlink_n2)
------------------------------------------------------------------------------
-- Usage of S3board switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7): SER_MONI.abact
-- LED(6:2): no function (only connected to sn_humanio_rbus)
-- LED(0): timer 0 busy
-- LED(1): timer 1 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- DP(3): not SER_MONI.txok (shows tx back preasure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back preasure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.serport.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.s3boardlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_s3 is -- top level
-- implements s3board_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32; -- sram: data lines
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_rlink_s3;
architecture syn of sys_tst_rlink_s3 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
RESET <= '0'; -- so far not used
CLK <= I_CLK50;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
ATOWIDTH => 6,
ITOWIDTH => 6,
CPREF => c_rlink_cpref,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 15,
CDINIT => sys_conf_ser2rri_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RB_SRES_OR1 : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_HIO,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_OR => RB_SRES
);
SRAM : s3_sram_dummy -- connect SRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
DSP_DAT <= SER_MONI.abclkdiv;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
end syn;
|
gpl-2.0
|
d3a0ccb4efdb94e8e0f2d91e33f4b48f
| 0.497576 | 3.213868 | false | false | false | false |
vhavlena/appreal
|
netbench/pattern_match/vhdl/state.vhd
| 1 | 1,414 |
-- ----------------------------------------------------------------------------
-- Entity for state representation of Clark NFA
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity STATE is
generic(
DEFAULT : std_logic := '0'
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- input data interface
INPUT : in std_logic;
WE : in std_logic;
-- output data interface
OUTPUT : out std_logic
);
end entity STATE;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of STATE is
begin
reg: process(CLK)
begin
if (CLK'event and CLK = '1') then
if (RESET = '1') then
OUTPUT <= DEFAULT;
else
if WE = '1' then
OUTPUT <= INPUT;
end if;
end if;
end if;
end process reg;
end architecture full;
|
gpl-2.0
|
09816be3c3ca7561d90525bb3b547f51
| 0.34017 | 5.656 | false | false | false | false |
vhavlena/appreal
|
netbench/pattern_match/vhdl/encoder.vhd
| 1 | 1,544 |
-- ----------------------------------------------------------------------------
-- Entity for conversion from one hot encoding to binary state encoding
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity ENCODER%$% is
generic(
INPUT_DATA_WIDTH : integer := %$%;
OUTPUT_DATA_WIDTH : integer := %$%
);
port(
-- input data interface
INPUT : in std_logic_vector(INPUT_DATA_WIDTH - 1 downto 0);
-- output data interface
OUTPUT : out std_logic_vector(OUTPUT_DATA_WIDTH - 1 downto 0);
VLD : out std_logic
);
end entity ENCODER%$%;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of ENCODER%$% is
signal bin : std_logic_vector(OUTPUT_DATA_WIDTH - 1 downto 0);
begin
%$%
OUTPUT <= bin;
generic_or: process(INPUT)
begin
if (INPUT = conv_std_logic_vector(0, INPUT_DATA_WIDTH)) then
VLD <= '0';
else
VLD <= '1';
end if;
end process generic_or;
end architecture full;
|
gpl-2.0
|
3e10647b28344584ad1189e52b0d9dfb
| 0.395078 | 5.342561 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd
| 1 | 17,785 |
-- $Id: sys_w11a_n3.vhd 440 2011-12-18 20:08:09Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_n3 - syn
-- Description: w11a test design for nexys3
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- vlib/rri/rb_sres_or_3
-- w11a/pdp11_core_rbus
-- w11a/pdp11_core
-- w11a/pdp11_bram
-- vlib/nxcramlib/nx_cram_dummy
-- w11a/pdp11_cache
-- w11a/pdp11_mem70
-- bplib/nxcramlib/nx_cram_memctl_as
-- ibus/ib_sres_or_2
-- ibus/ibdr_minisys
-- ibus/ibdr_maxisys
-- w11a/pdp11_tmu_sb [sim only]
--
-- Test bench: tb/tb_sys_w11a_n3
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-18 440 13.1 O40d xc6slx16-2 1441 3161 96 1084 ok: LP+PC+DL+II
-- 2011-11-20 430 13.1 O40d xc6slx16-2 1412 3206 84 1063 ok: LP+PC+DL+II
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-18 440 1.0.4 use rlink_sp1c
-- 2011-12-04 435 1.0.3 increase ATOWIDTH 6->7 (saw i/o timeouts on wblks)
-- 2011-11-26 433 1.0.2 use nx_cram_(dummy|memctl_as) now
-- 2011-11-23 432 1.0.1 fixup PPCM handling
-- 2011-11-20 430 1.0 Initial version (derived from sys_w11a_n2)
------------------------------------------------------------------------------
--
-- w11a test design for nexys3
-- w11a + rlink + serport
--
-- Usage of Nexys 3 Switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port
-- 1 -> Pmod B/top RS232 port
--
-- LED(7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0): if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- if cpugo=0 shows cpurust
-- (3:0) cpurust code
-- (4) '1'
--
-- DP(3): not SER_MONI.txok (shows tx back preasure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back preasure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serport.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.nxcramlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_n3 is -- top level
-- implements nexys3_fusp_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_w11a_n3;
architecture syn of sys_w11a_n3 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CPU_RESET : slbit := '0';
signal CP_CNTL : cp_cntl_type := cp_cntl_init;
signal CP_ADDR : cp_addr_type := cp_addr_init;
signal CP_DIN : slv16 := (others=>'0');
signal CP_STAT : cp_stat_type := cp_stat_init;
signal CP_DOUT : slv16 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal EM_MREQ : em_mreq_type := em_mreq_init;
signal EM_SRES : em_sres_type := em_sres_init;
signal HM_ENA : slbit := '0';
signal MEM70_FMISS : slbit := '0';
signal CACHE_FMISS : slbit := '0';
signal CACHE_CHIT : slbit := '0';
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MEM_ADDR_EXT : slv22 := (others=>'0');
signal BRESET : slbit := '0';
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES : ib_sres_type := ib_sres_init;
signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init;
signal DISPREG : slv16 := (others=>'0');
constant rbaddr_core0 : slv8 := "00000000";
constant rbaddr_ibus : slv8 := "10000000";
constant rbaddr_hio : slv8 := "11000000";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
ATOWIDTH => 7, -- 128 cycles access timeout
ITOWIDTH => 6, -- 64 periods max idle timeout
CPREF => c_rlink_cpref,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RB_SRES_OR : rb_sres_or_3
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_IBD,
RB_SRES_3 => RB_SRES_HIO,
RB_SRES_OR => RB_SRES
);
RB2CP : pdp11_core_rbus
generic map (
RB_ADDR_CORE => rbaddr_core0,
RB_ADDR_IBUS => rbaddr_ibus)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM(0),
CPU_RESET => CPU_RESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT
);
CORE : pdp11_core
port map (
CLK => CLK,
RESET => CPU_RESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
BRESET => BRESET,
IB_MREQ_M => IB_MREQ,
IB_SRES_M => IB_SRES,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO
);
MEM_BRAM: if sys_conf_bram > 0 generate
signal HM_VAL_BRAM : slbit := '0';
begin
MEM : pdp11_bram
generic map (
AWIDTH => sys_conf_bram_awidth)
port map (
CLK => CLK,
GRESET => CPU_RESET,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES
);
HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write
MEM70: pdp11_mem70
port map (
CLK => CLK,
CRESET => BRESET,
HM_ENA => EM_MREQ.req,
HM_VAL => HM_VAL_BRAM,
CACHE_FMISS => MEM70_FMISS,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MEM70
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end generate MEM_BRAM;
MEM_SRAM: if sys_conf_bram = 0 generate
CACHE: pdp11_cache
port map (
CLK => CLK,
GRESET => CPU_RESET,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
FMISS => CACHE_FMISS,
CHIT => CACHE_CHIT,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO
);
MEM70: pdp11_mem70
port map (
CLK => CLK,
CRESET => BRESET,
HM_ENA => HM_ENA,
HM_VAL => CACHE_CHIT,
CACHE_FMISS => MEM70_FMISS,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MEM70
);
HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w;
CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss;
MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
SRAM_CTL: nx_cram_memctl_as
generic map (
READ0DELAY => sys_conf_memctl_read0delay,
READ1DELAY => sys_conf_memctl_read1delay,
WRITEDELAY => sys_conf_memctl_writedelay)
port map (
CLK => CLK,
RESET => CPU_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR_EXT,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end generate MEM_SRAM;
IB_SRES_OR : ib_sres_or_2
port map (
IB_SRES_1 => IB_SRES_MEM70,
IB_SRES_2 => IB_SRES_IBDR,
IB_SRES_OR => IB_SRES
);
IBD_MINI : if false generate
begin
IBDR_SYS : ibdr_minisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => CPU_RESET,
BRESET => BRESET,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
end generate IBD_MINI;
IBD_MAXI : if true generate
begin
IBDR_SYS : ibdr_maxisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => CPU_RESET,
BRESET => BRESET,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
end generate IBD_MAXI;
DSP_DAT(15 downto 0) <= DISPREG;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
variable iled : slv8 := (others=>'0');
begin
iled := (others=>'0');
iled(7) := MEM_ACT_W;
iled(6) := MEM_ACT_R;
iled(5) := CP_STAT.cmdbusy;
if CP_STAT.cpugo = '1' then
case DM_STAT_DP.psw.cmode is
when c_psw_kmode =>
if CP_STAT.cpuwait = '1' then
iled(2) := '1';
elsif unsigned(DM_STAT_DP.psw.pri) = 0 then
iled(3) := '1';
else
iled(4) := '1';
end if;
when c_psw_smode =>
iled(1) := '1';
when c_psw_umode =>
iled(0) := '1';
when others => null;
end case;
else
iled(4) := '1';
iled(3 downto 0) := CP_STAT.cpurust;
end if;
LED <= iled;
end process;
-- synthesis translate_off
DM_STAT_SY.emmreq <= EM_MREQ;
DM_STAT_SY.emsres <= EM_SRES;
DM_STAT_SY.chit <= CACHE_CHIT;
TMU : pdp11_tmu_sb
generic map (
ENAPIN => 13)
port map (
CLK => CLK,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
DM_STAT_SY => DM_STAT_SY
);
-- synthesis translate_on
end syn;
|
gpl-2.0
|
cf7a1563b0cc506f9ae00b29480fb5db
| 0.487771 | 3.142226 | false | false | false | false |
willprice/build-a-comp-vhdl-modules
|
base/AU.vhd
| 1 | 1,099 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AU is
port(
a_in : in unsigned(3 downto 0);
b_in : in unsigned(3 downto 0);
control_in : in unsigned(3 downto 0);
control_out : out unsigned(3 downto 0);
data_out : out unsigned(3 downto 0);
comparison_out : out unsigned(3 downto 0)
);
end entity AU;
architecture Behavioural of AU is
begin
control_out <= control_in;
process(a_in, b_in, control_in) is
begin
case (control_in(2 downto 0)) is
when "000" =>
data_out <= a_in + b_in;
comparison_out <= "0000";
when "001" =>
data_out <= a_in;
comparison_out <= "0000";
when "110" =>
data_out <= (a_in + not b_in) + 1;
if (a_in = b_in) then
comparison_out <= "1111";
else
comparison_out <= "0000";
end if;
when "111" =>
data_out <= a_in - b_in;
if (a_in < b_in) then
comparison_out <= "1111";
else
comparison_out <= "0000";
end if;
when others => data_out <= "0000";
end case;
end process;
end architecture Behavioural;
|
mit
|
de3b35f5eef29c7a2cc415f50ed7853a
| 0.571429 | 2.803571 | false | false | false | false |
Kolchuzhin/LMGT_MEMS_component_library
|
clamped_beam/hAMSter_model/testbench.vhd
| 1 | 7,540 |
--*****************************************************************************
--*****************************************************************************
-- Model: testbench for cbeam.vhd in hAMSter
--
-- clamped /one side fixed/ beam
-- is driven by a voltage (see key_load):
-- 20. constant load
-- 21. ramp/sweep computing the pull-in voltage
-- 22. sin/chirp
-- 23. puls
--
-- Author: <[email protected]>
-- Date: 19.10.2011
-- Library dependencies:
-- VHDL-AMS generated code from ANSYS for hAMSter: cbeam.vhd
-- uMKSV units
-------------------------------------------------------------------------------
-- Beam parameters, um
-- B_L=100 Beam length
-- B_W=20 Beam width
-- B_T=2 Beam thickness
-- E_G=4 Electrode gap
--
-- Material properties <110> Si
-- EX=169e3 MPa, Young's modulus
-- NUXY=0.066, Poisson's ratio
-- DENS=2.329e-15 kg/um/um/um. density
-- ALPX=1e-6
--
-- Calculation of voltage displacement functions up to pull-in:
-- Linear analysis: 157 volts (stress stiffening is OFF)
-- Nonlinear analysis: 160 volts (stress stiffening is ON)
--
-- There are two element loads: acceleration and a uniform pressure load:
-- acel,,,9.81e12 ! acceleration in Z-direction 9.81e6 m/s**2
-- sf,all,pres,0.1 ! uniform 100 kPa pressure load
--
-- Damping: modal quality factors in cbeam.vhd
--
-------------------------------------------------------------------------------
-- Euler solver:
-- time=50u; step=10n
-------------------------------------------------------------------------------
-- ID: testbench.vhd
-- ver. 0.20 19.11.2011
-- ver. 0.30 02.05.2019 updated
--*****************************************************************************
--*****************************************************************************
use work.electromagnetic_system.all;
use work.all;
library ieee;
use ieee.math_real.all;
entity testbench is
end;
architecture behav of testbench is
terminal struc1_ext,struc2_ext: translational; --
terminal lagrange1_ext,lagrange2_ext:translational; --
terminal master1_ext,master2_ext:translational; --
terminal elec1_ext,elec2_ext: electrical; --
-- Modal displacement
quantity q_ext1 across fm_ext1 through struc1_ext; -- Modal amplitude 1
quantity q_ext2 across fm_ext2 through struc2_ext; -- Modal amplitude 2
-- Lagrangian multipler
quantity p_ext1 across r_ext1 through lagrange1_ext;
quantity p_ext2 across r_ext2 through lagrange2_ext;
-- Nodal displacement
quantity u_ext1 across f_ext1 through master1_ext; -- Nodal amplitude 1
quantity u_ext2 across f_ext2 through master1_ext; -- Nodal amplitude 2
-- Electrical ports
quantity v_ext1 across i_ext1 through elec1_ext; -- Conductor 1
quantity v_ext2 across i_ext2 through elec2_ext; -- Conductor 2
constant digital_delay:time:=10.0 ns; -- digital time step size for matrix update == analog time step
constant el_load1:real:=0.0;
constant el_load2:real:=0.0;
constant t_end:real:=50.0e-06;
constant dt:real:=10.0E-09; -- time step
constant ac_value:real:= 10.0;
constant dc_value:real:=160.0;
-- puls
constant t1:real:= 1.0E-06;
constant t2:real:=10.0E-06; -- 5.0E-06
-- chirp
constant f_begin:real:= 0.27544E+06*0.1; -- begin of frequency sweep
constant f_end:real:= 0.27544E+06*3.0; -- end of frequency sweep
constant fm1_test:real:= 0.232818464746E-11*(2.0*3.14*0.27544E+06)**2;
constant fm2_test:real:= 0.231854244007E-11*(2.0*3.14*0.17337E+07)**2;
-- 10/11/12/13 == const/ramp/chirp/puls mechanical load/test
constant key_load:integer:=21; -- 20/21/22/23 == const/ramp/chirp/puls electromechanical test w/electrical load
begin
-- Loads
if key_load = 10 use -- static mechanical modal
v_ext1==0.0;
v_ext2==0.0;
fm_ext1==fm1_test; -- external modal force 1 f=k*u
fm_ext2==fm2_test; -- external modal force 2 f=k*u
end use;
if key_load = 11 use -- ramp/sweep
v_ext1==0.0;
v_ext2==0.0;
fm_ext1==fm1_test/t_end/1.0*now;
fm_ext2==fm2_test/t_end/1.0*now;
end use;
if key_load = 12 use -- sin/chirp
v_ext1==0.0;
v_ext2==0.0;
fm_ext1==0.0 + fm1_test*sin(2.0*3.14*(f_begin + (f_end-f_begin)/t_end*now) * now);
fm_ext2==0.0;
end use;
if key_load = 13 use -- puls
v_ext1==0.0;
v_ext2==0.0;
fm_ext2==0.0;
if now <= t1-dt use
fm_ext1 == 0.0;
end use;
if now > t1-dt and now <= t1 use
fm_ext1 == 0.0;
end use;
if now > t1 and now <= t2 use
fm_ext1 == fm1_test*0.2;
end use;
if now > t2 and now <= t2+dt use
fm_ext1 == 0.0;
end use;
if now > t2+dt use
fm_ext1 == 0.0;
end use;
end use;
if key_load = 20 use -- static electrical
v_ext1==10.0;
v_ext2== 0.0; -- ground electrode
fm_ext1==0.0;
fm_ext2==0.0;
end use;
if key_load = 21 use -- ramp/sweep
v_ext1 == dc_value/t_end*now;
v_ext2== 0.0;
fm_ext1==0.0;
fm_ext2==0.0;
end use;
if key_load = 22 use -- chirp
v_ext1 == dc_value*0.0 + ac_value*sin(2.0*3.14*(f_begin + (f_end-f_begin)/t_end*now) * now);
v_ext2== 0.0;
fm_ext1==0.0;
fm_ext2==0.0;
end use;
if key_load = 23 use -- puls
if now <= t1-dt use
v_ext1 == 0.0;
end use;
if now > t1-dt and now <= t1 use
v_ext1 == 0.0;
end use;
if now > t1 and now <= t2 use
v_ext1 == dc_value*0.1;
end use;
if now > t2 and now <= t2+dt use
v_ext1 == 0.0;
end use;
if now > t2+dt use
v_ext1 == 0.0;
end use;
v_ext2== 0.0;
fm_ext1==0.0;
fm_ext2==0.0;
end use;
-- BCs:
--i_ext1==0.0;
--v_ext2==0.0;
--fm_ext1==0.0; -- external modal force 1
--fm_ext2==0.0; -- external modal force 2
-- Lagrangian ports: p/r
r_ext1==0.0; -- must be zero
r_ext2==0.0; -- must be zero
-- nodal ports: u/f
f_ext1==0.0; -- external nodal force on master node 1
f_ext2==0.0; -- external nodal force on master node 2
-------------------------------------------------------------------------------
--
-- Lagrangian ports
--
-- p1 p2
-- r_ext1=0 ->>- o o -<<- r_ext2=0
-- | |
-- modal ports o------o---------o------o nodal ports
-- | |
-- fm_ext1=0 ->>- q1 o---o o---o u1 -<<- f_ext1=0
-- | element1: cbeam |
-- fm_ext2=0 ->>- q2 o---o o---o u2 -<<- f_ext2=0
-- | |
-- o------o---------o------o
-- | |
-- o o
-- input: v1_ext v2_ext=0 (ground)
--
-- electrical ports
--
-- ASCII-Schematic of the MEMS-component: cbeam
-------------------------------------------------------------------------------
element1:
entity cbeam(behav)
generic map (digital_delay,el_load1,el_load2)
port map (struc1_ext,struc2_ext,
lagrange1_ext,lagrange2_ext,
master1_ext,master2_ext,
elec1_ext,elec2_ext);
end;
-------------------------------------------------------------------------------
|
mit
|
e9884f2a82a875dd11d62b93ddf3ccf1
| 0.492175 | 3.145599 | false | true | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vhd
| 1 | 8,742 |
-- $Id: sys_tst_serloop2_n2.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop2_n2 - syn
-- Description: Tester serial link for nexys2
--
-- Dependencies: vlib/xlib/dcm_sfs
-- genlib/clkdivce
-- bpgen/bp_rs232_2l4l_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_2clock
-- tst_serloop
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-16 439 13.1 O40d xc3s1200e-4 516 696 64 575 t xx.x
-- 2011-11-16 426 13.1 O40d xc3s1200e-4 494 661 64 547 t xx.x
-- 2011-11-13 425 13.1 O40d xc3s1200e-4 487 645 64 532 t xx.x
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-09 437 1.0.4 rename serport stat->moni port
-- 2011-11-26 433 1.0.3 use nx_cram_dummy now
-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage
-- 2011-11-17 426 1.0.1 use dcm_sfs now
-- 2011-11-12 423 1.0 Initial version
-- 2011-11-09 422 0.5 First draft
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serport.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop2_n2 is -- top level
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_serloop2_n2;
architecture syn of sys_tst_serloop2_n2 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
begin
DCM_U : dcm_sfs
generic map (
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY => 4,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
O_CLKSYS <= '0';
CLKDIV_U : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clkudiv_usecdiv, -- syn: 100 sim: 20
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
DCM_S : dcm_sfs
generic map (
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 6,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLKS,
LOCKED => open
);
CLKDIV_S : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => sys_conf_clksdiv_usecdiv, -- syn: 60 sim: 12
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLKS,
CE_USEC => open,
CE_MSEC => CES_MSEC
);
HIO : sn_humanio
generic map (
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLKS,
RESET => '0',
SEL => SWI(0), -- port selection
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
SERPORT : serport_2clock
generic map (
CDWIDTH => 15,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLKU => CLK,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
|
gpl-2.0
|
42b1ec28a5537f77ca287701da685788
| 0.494395 | 3.27907 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/serport/serport_2clock.vhd
| 1 | 12,219 |
-- $Id: serport_2clock.vhd 438 2011-12-11 23:40:52Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_2clock - syn
-- Description: serial port: serial port module, 2 clock domain
--
-- Dependencies: genlib/cdc_pulse
-- serport_uart_rxtx_ab
-- serport_xonrx
-- serport_xontx
-- memlib/fifo_2c_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-11-13 424 13.1 O40d xc3s1000-4 224 362 64 295 s 8.6/10.1
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-10 438 1.0.2 internal reset on abact
-- 2011-12-09 437 1.0.1 rename stat->moni port
-- 2011-11-13 424 1.0 Initial version
-- 2011-11-07 421 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serport.all;
use work.genlib.all;
use work.memlib.all;
entity serport_2clock is -- serial port module, 2 clock domain
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLKU : in slbit; -- clock (backend:user)
RESET : in slbit; -- reset
CLKS : in slbit; -- clock (frontend:serial)
CES_MSEC : in slbit; -- S|1 msec clock enable
ENAXON : in slbit; -- U|enable xon/xoff handling
ENAESC : in slbit; -- U|enable xon/xoff escaping
RXDATA : out slv8; -- U|receiver data out
RXVAL : out slbit; -- U|receiver data valid
RXHOLD : in slbit; -- U|receiver data hold
TXDATA : in slv8; -- U|transmit data in
TXENA : in slbit; -- U|transmit data enable
TXBUSY : out slbit; -- U|transmit busy
MONI : out serport_moni_type; -- U|serport monitor port
RXSD : in slbit; -- S|receive serial data (uart view)
TXSD : out slbit; -- S|transmit serial data (uart view)
RXRTS_N : out slbit; -- S|receive rts (uart view, act.low)
TXCTS_N : in slbit -- S|transmit cts (uart view, act.low)
);
end serport_2clock;
architecture syn of serport_2clock is
type synu_type is record
rxact_c : slbit; -- rxact (capt from CLKS->CLKU)
rxact_s : slbit; -- rxact (sync in CLKU)
txact_c : slbit; -- txact (capt from CLKS->CLKU)
txact_s : slbit; -- txact (sync in CLKU)
abact_c : slbit; -- abact (capt from CLKS->CLKU)
abact_s : slbit; -- abact (sync in CLKU)
rxok_c : slbit; -- rxok (capt from CLKS->CLKU)
rxok_s : slbit; -- rxok (sync in CLKU)
txok_c : slbit; -- txok (capt from CLKS->CLKU)
txok_s : slbit; -- txok (sync in CLKU)
abclkdiv_c : slv(CDWIDTH-1 downto 0); -- abclkdiv (capt from CLKS->CLKU)
abclkdiv_s : slv(CDWIDTH-1 downto 0); -- abclkdiv (sync in CLKU)
end record synu_type;
constant synu_init : synu_type := (
'0','0', -- rxact_c,_s
'0','0', -- txact_c,_s
'0','0', -- abact_c,_s
'0','0', -- rxok_c,_s
'0','0', -- txok_c,_s
slv(to_unsigned(0,CDWIDTH)), -- abclkdiv_c
slv(to_unsigned(0,CDWIDTH)) -- abclkdiv_s
);
type syns_type is record
enaxon_c : slbit; -- enaxon (capt from CLKU->CLKS)
enaxon_s : slbit; -- enaxon (sync in CLKS)
enaesc_c : slbit; -- enaesc (capt from CLKU->CLKS)
enaesc_s : slbit; -- enaesc (sync in CLKS)
end record syns_type;
constant syns_init : syns_type := (
'0','0', -- enaxon_c,_s
'0','0' -- enaxon_c,_s
);
signal R_SYNU : synu_type := synu_init; -- sync registers (clku)
signal R_SYNS : syns_type := syns_init; -- sync registers (clks)
signal R_RXOK : slbit := '1';
signal RESET_INT : slbit := '0';
signal RESET_CLKS : slbit := '0';
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal XONTX_TXENA : slbit := '0';
signal XONTX_TXBUSY : slbit := '0';
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXFIFO_SIZEW : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal RXERR : slbit := '0';
signal RXOVR : slbit := '0';
signal RXACT : slbit := '0';
signal ABACT : slbit := '0';
signal ABDONE : slbit := '0';
signal ABCLKDIV : slv(CDWIDTH-1 downto 0) := (others=>'0');
signal TXOK : slbit := '0';
signal RXOK : slbit := '0';
signal RXERR_CLKU : slbit := '0';
signal RXOVR_CLKU : slbit := '0';
signal ABDONE_CLKU : slbit := '0';
begin
assert CDWIDTH<=16
report "assert(CDWIDTH<=16): max width of UART clock divider"
severity failure;
CDC_RESET : cdc_pulse
generic map (
POUT_SINGLE => false,
BUSY_WACK => false)
port map (
CLKM => CLKU,
RESET => '0',
CLKS => CLKS,
PIN => RESET,
BUSY => open,
POUT => RESET_CLKS
);
UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT)
port map (
CLK => CLKS,
CE_MSEC => CES_MSEC,
RESET => RESET_CLKS,
RXSD => RXSD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY,
ABACT => ABACT,
ABDONE => ABDONE,
ABCLKDIV => ABCLKDIV
);
RESET_INT <= RESET_CLKS or ABACT;
XONRX : serport_xonrx -- xon/xoff logic rx path
port map (
CLK => CLKS,
RESET => RESET_INT,
ENAXON => R_SYNS.enaxon_s,
ENAESC => R_SYNS.enaesc_s,
UART_RXDATA => UART_RXDATA,
UART_RXVAL => UART_RXVAL,
RXDATA => RXFIFO_DI,
RXVAL => RXFIFO_ENA,
RXHOLD => RXFIFO_BUSY,
RXOVR => RXOVR,
TXOK => TXOK
);
XONTX : serport_xontx -- xon/xoff logic tx path
port map (
CLK => CLKS,
RESET => RESET_INT,
ENAXON => R_SYNS.enaxon_s,
ENAESC => R_SYNS.enaesc_s,
UART_TXDATA => UART_TXDATA,
UART_TXENA => XONTX_TXENA,
UART_TXBUSY => XONTX_TXBUSY,
TXDATA => TXFIFO_DO,
TXENA => TXFIFO_VAL,
TXBUSY => TXFIFO_HOLD,
RXOK => RXOK,
TXOK => TXOK
);
RXFIFO : fifo_2c_dram -- input fifo, 2 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLKS,
CLKR => CLKU,
RESETW => ABACT, -- clear fifo on abact
RESETR => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZEW => RXFIFO_SIZEW,
SIZER => open
);
TXFIFO : fifo_2c_dram -- output fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLKU,
CLKR => CLKS,
RESETW => RESET,
RESETR => ABACT, -- clear fifo on abact
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZEW => open,
SIZER => open
);
-- receive back preasure
-- on if fifo more than 3/4 full (less than 1/4 free)
-- off if fifo less than 1/2 full (more than 1/2 free)
proc_rxok: process (CLKS)
constant rxsize_rxok_off : slv2 := "01";
constant rxsize_rxok_on : slv2 := "10";
variable rxsize_msb : slv2 := "00";
begin
if rising_edge(CLKS) then
if RESET_INT = '1' then
R_RXOK <= '1';
else
rxsize_msb := RXFIFO_SIZEW(RXFAWIDTH-1 downto RXFAWIDTH-2);
if unsigned(rxsize_msb) < unsigned(rxsize_rxok_off) then
R_RXOK <= '0';
elsif unsigned(RXSIZE_MSB) >= unsigned(rxsize_rxok_on) then
R_RXOK <= '1';
end if;
end if;
end if;
end process proc_rxok;
RXOK <= R_RXOK;
RXRTS_N <= not R_RXOK;
proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY)
begin
if TXCTS_N = '0' then -- transmit cts asserted
UART_TXENA <= XONTX_TXENA;
XONTX_TXBUSY <= UART_TXBUSY;
else -- transmit cts not asserted
UART_TXENA <= '0';
XONTX_TXBUSY <= '1';
end if;
end process proc_cts;
proc_synu: process (CLKU)
begin
if rising_edge(CLKU) then
R_SYNU.rxact_c <= RXACT;
R_SYNU.rxact_s <= R_SYNU.rxact_c;
R_SYNU.txact_c <= UART_TXBUSY;
R_SYNU.txact_s <= R_SYNU.txact_c;
R_SYNU.abact_c <= ABACT;
R_SYNU.abact_s <= R_SYNU.abact_c;
R_SYNU.rxok_c <= RXOK;
R_SYNU.rxok_s <= R_SYNU.rxok_c;
R_SYNU.txok_c <= TXOK;
R_SYNU.txok_s <= R_SYNU.txok_c;
R_SYNU.abclkdiv_c <= ABCLKDIV;
R_SYNU.abclkdiv_s <= R_SYNU.abclkdiv_c;
end if;
end process proc_synu;
proc_syns: process (CLKS)
begin
if rising_edge(CLKS) then
R_SYNS.enaxon_c <= ENAXON;
R_SYNS.enaxon_s <= R_SYNS.enaxon_c;
R_SYNS.enaesc_c <= ENAESC;
R_SYNS.enaesc_s <= R_SYNS.enaesc_c;
end if;
end process proc_syns;
CDC_RXERR : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => RXERR,
BUSY => open,
POUT => RXERR_CLKU
);
CDC_RXOVR : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => RXOVR,
BUSY => open,
POUT => RXOVR_CLKU
);
CDC_ABDONE : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => ABDONE,
BUSY => open,
POUT => ABDONE_CLKU
);
MONI.rxerr <= RXERR_CLKU;
MONI.rxovr <= RXOVR_CLKU;
MONI.rxact <= R_SYNU.rxact_s;
MONI.txact <= R_SYNU.txact_s;
MONI.abact <= R_SYNU.abact_s;
MONI.abdone <= ABDONE_CLKU;
MONI.rxok <= R_SYNU.rxok_s;
MONI.txok <= R_SYNU.txok_s;
proc_abclkdiv: process (R_SYNU.abclkdiv_s)
begin
MONI.abclkdiv <= (others=>'0');
MONI.abclkdiv(R_SYNU.abclkdiv_s'range) <= R_SYNU.abclkdiv_s;
end process proc_abclkdiv;
end syn;
|
gpl-2.0
|
4e6b325a8c6de4db34119e16d0b78cb3
| 0.518537 | 3.615089 | false | false | false | false |
Azbesciak/digitalTechnology
|
cw13/binary_counter_mod_16.vhd
| 1 | 751 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity binary_counter_mod_16 is
generic(
MIN_COUNT : natural := 0;
MAX_COUNT : natural := 15
);
port(
clk, reset, enable : in std_logic;
q : out integer range MIN_COUNT to MAX_COUNT;
carry : out std_logic
);
end entity;
architecture rtl of binary_counter_mod_16 is
begin
process (clk, reset)
variable cnt: integer range MIN_COUNT to MAX_COUNT;
begin
if reset = '1' then
-- Reset the counter to 0
cnt := 0;
elsif (rising_edge(clk) and enable = '1') then
if cnt = MAX_COUNT then
carry <= '1';
else carry <= '0';
end if;
cnt := cnt + 1;
end if;
-- Output the current count
q <= cnt;
end process;
end rtl;
|
mit
|
45b33446a5a7c63bc7d63334ac9cf3ed
| 0.620506 | 2.922179 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega2/MUX.vhd
| 2 | 567 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX is
PORT( Crs2 : IN std_logic_vector(31 DOWNTO 0);
SEUimm13 : IN std_logic_vector(31 DOWNTO 0);
i : IN std_logic;
Oper2 : OUT std_logic_vector(31 DOWNTO 0));
end MUX;
architecture Behavioral of MUX is
begin
PROCESS (i, Crs2, SEUimm13) IS
BEGIN
CASE i IS
WHEN '0' => Oper2 <= Crs2;
WHEN '1' => Oper2 <= SEUimm13;
WHEN OTHERS => Oper2 <= (others => '1');
END CASE;
END PROCESS;
end Behavioral;
|
mit
|
3beb780dd89a4b1b250060645f9f22ce
| 0.546737 | 3.478528 | false | false | false | false |
os-cillation/easyfpga-soc
|
infrastructure/soc_bridge.vhd
| 1 | 9,355 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- S O C B R I D G E
--
-- Purpose: Bridge FT245 style FIFO interface and Wishbone interconnection
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--library unisim;
--use unisim.vcomponents.all;
use work.constants.all;
use work.interfaces.all;
-------------------------------------------------------------------------------
ENTITY soc_bridge is
-------------------------------------------------------------------------------
port (
-- mcu
fpga_active_i : in std_logic;
mcu_active_o : out std_logic;
-- fifo interface
fifo_data_io : inout std_logic_vector(7 downto 0);
fifo_rxf_n_i : in std_logic;
fifo_txe_n_i : in std_logic;
fifo_rd_n_o : out std_logic;
fifo_wr_o : out std_logic;
-- wishbone master
wbm_i : in wbm_in_type;
wbm_o : out wbm_out_type
);
end soc_bridge;
-------------------------------------------------------------------------------
ARCHITECTURE structural of soc_bridge is
-------------------------------------------------------------------------------
----------------------------------------------
-- Constants
----------------------------------------------
constant FIFO_WIDTH : natural := 8;
----------------------------------------------
-- Signals
----------------------------------------------
-- global signals
signal clk, rst : std_logic;
-- signals connecting ...
-- ... fifo_adapter and fifo_controller
signal fifo_ctrl_direction_s : std_logic;
signal rxf_s, txe_s, wr_s, rd_s : std_logic;
signal data_transmit_s, data_receive_s : std_logic_vector(FIFO_WIDTH -1 downto 0);
-- ... fifo_adapter and enable_controller
signal fifo_enable_s : std_logic;
-- ... receive buffer and fifo controller
signal fifo_controller_word_s : std_logic_vector(FIFO_WIDTH -1 downto 0);
signal fifo_controller_receive_store_s : std_logic;
signal receive_buffer_busy_s : std_logic;
-- ... receive buffer and frame controller
signal frame_ctrl_clear_recbuf_s : std_logic;
signal receive_buffer_frame_s : std_logic_vector(PROTO_WC_RX_MAX*FIFO_WIDTH -1 downto 0);
signal receive_buffer_complete_s : std_logic;
-- ... frame controller, transmit buffer and fifo controller
signal transmitter_mode_s : std_logic;
-- ... frame controller and enable controller
signal mcu_select_s : std_logic;
-- ... frame controller and transmit buffer
signal frame_ctrl_trabuf_frame_s : std_logic_vector(PROTO_WC_TX_MAX*FIFO_WIDTH -1 downto 0);
signal frame_ctrl_trabuf_valid_s : std_logic;
signal frame_ctrl_trabuf_length_s : integer range 0 to PROTO_WC_TX_MAX;
signal trabuf_frame_ctrl_busy_s : std_logic;
-- ... transmit buffer and fifo controller
signal trabuf_word_out_s : std_logic_vector(FIFO_WIDTH -1 downto 0);
signal trabuf_send_s : std_logic;
-- ... wishbone master and the intercon (outside this entity)
signal wbm_i_s : wbm_in_type;
signal wbm_o_s : wbm_out_type;
-------------------------------------------------------------------------------
begin -- architecture structural
-------------------------------------------------------------------------------
----------------------------------------------
-- global signals
----------------------------------------------
clk <= wbm_i.clk;
rst <= not fpga_active_i;
wbm_o <= wbm_o_s;
wbm_i_s <= wbm_i;
-------------------------------------------------------------------------------
FRAME_CTRL : entity work.frame_ctrl
-------------------------------------------------------------------------------
port map (
clk => clk,
rst => rst,
-- inputs
d.recbuf_frame => receive_buffer_frame_s ,
d.recbuf_complete => receive_buffer_complete_s,
d.trabuf_busy => trabuf_frame_ctrl_busy_s,
-- outputs
q.recbuf_clear => frame_ctrl_clear_recbuf_s,
q.trabuf_frame => frame_ctrl_trabuf_frame_s,
q.trabuf_valid => frame_ctrl_trabuf_valid_s,
q.mcu_select => mcu_select_s,
q.transmitter_mode => transmitter_mode_s,
q.trabuf_length => frame_ctrl_trabuf_length_s,
-- wishbone
wbo => wbm_o_s,
wbi => wbm_i_s
);
-------------------------------------------------------------------------------
FIFO_ADAPTER : entity work.fifo_adapter
-------------------------------------------------------------------------------
port map (
-- external fifo pins (ucf)
data_pins => fifo_data_io(FIFO_WIDTH -1 downto 0),
rxf_pin => fifo_rxf_n_i,
txd_pin => fifo_txe_n_i,
wr_pin => fifo_wr_o,
rd_pin => fifo_rd_n_o,
-- internal fifo signals
enable_i => fifo_enable_s, -- async enable
direction_i => fifo_ctrl_direction_s, -- data direction (0:receive, 1:send)
data_transmit_i => data_transmit_s,
data_receive_o => data_receive_s,
rxf_o => rxf_s,
txd_o => txe_s,
wr_i => wr_s,
rd_i => rd_s
);
-------------------------------------------------------------------------------
FIFO_CONTROLLER : entity work.fifo_controller
-------------------------------------------------------------------------------
port map (
-- fifo adapter interface
data_transmit_o => data_transmit_s,
txe_i => txe_s,
wr_o => wr_s,
data_receive_i => data_receive_s,
rxf_i => rxf_s,
rd_o => rd_s,
direction_o => fifo_ctrl_direction_s, -- 0:receiver, 1:transmitter
-- receive buffer interface
word_recbuf_o => fifo_controller_word_s,
store_recbuf_o => fifo_controller_receive_store_s,
busy_recbuf_i => receive_buffer_busy_s,
-- transmit buffer interface
word_trabuf_i => trabuf_word_out_s,
send_trabuf_i => trabuf_send_s,
-- misc
transmitter_mode_i=> transmitter_mode_s,
clk_i => clk,
rst_i => rst
);
-------------------------------------------------------------------------------
RECEIVE_FRAME_BUFFER : entity work.receive_frame_buffer
-------------------------------------------------------------------------------
port map (
clk_i => clk,
clear_i => frame_ctrl_clear_recbuf_s,
store_i => fifo_controller_receive_store_s,
frame_complete_o => receive_buffer_complete_s,
word_i => fifo_controller_word_s,
frame_o => receive_buffer_frame_s,
busy_o => receive_buffer_busy_s
);
-------------------------------------------------------------------------------
TRANSMIT_FRAME_BUFFER : entity work.transmit_frame_buffer
-------------------------------------------------------------------------------
port map (
clk => clk,
rst => rst,
-- inputs
d.frame => frame_ctrl_trabuf_frame_s,
d.frame_valid => frame_ctrl_trabuf_valid_s,
d.transmit_mode => transmitter_mode_s,
d.fifo_busy => fifo_ctrl_direction_s,
d.fifo_wr => wr_s,
d.length => frame_ctrl_trabuf_length_s,
-- outputs
q.trabuf_busy => trabuf_frame_ctrl_busy_s,
q.word => trabuf_word_out_s,
q.send => trabuf_send_s
);
-------------------------------------------------------------------------------
ENABLE_CONTROLLER : entity work.enable_controller
-------------------------------------------------------------------------------
port map (
-- mcu interface
fpga_active_i => fpga_active_i, -- ucf
mcu_active_o => mcu_active_o, -- ucf
-- soc interface
mcu_select_i => mcu_select_s,
fifo_enable_o => fifo_enable_s,
clk_i => clk,
rst_i => rst
);
end structural;
|
gpl-3.0
|
ce0679ad2c2889860a17aa68cfa27809
| 0.43891 | 4.493276 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/genlib/genlib.vhd
| 1 | 6,631 |
-- $Id: genlib.vhd 422 2011-11-10 18:44:06Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: genlib
-- Description: some general purpose components
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-09 421 1.0.8 add cdc_pulse
-- 2010-04-17 277 1.0.7 timer: no default for START,DONE,BUSY; drop STOP
-- 2010-04-02 273 1.0.6 add timer
-- 2008-01-20 112 1.0.5 rename clkgen->clkdivce
-- 2007-12-26 106 1.0.4 added gray_cnt_(4|5|n|gen) and gray2bin_gen
-- 2007-12-25 105 1.0.3 RESET:='0' defaults
-- 2007-06-17 58 1.0.2 added debounce_gen
-- 2007-06-16 57 1.0.1 added cnt_array_dram, cnt_array_regs
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package genlib is
component clkdivce is -- generate usec/msec ce pulses
generic (
CDUWIDTH : positive := 6; -- usec clock divider width
USECDIV : positive := 50; -- divider ratio for usec pulse
MSECDIV : positive := 1000); -- divider ratio for msec pulse
port (
CLK : in slbit; -- input clock
CE_USEC : out slbit; -- usec pulse
CE_MSEC : out slbit -- msec pulse
);
end component;
component cnt_array_dram is -- counter array, dram based
generic (
AWIDTH : positive := 4; -- address width
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- clear counters
CE : in slv(2**AWIDTH-1 downto 0); -- count enables
ADDR : out slv(AWIDTH-1 downto 0); -- counter address
DATA : out slv(DWIDTH-1 downto 0); -- counter data
ACT : out slbit -- active (not reseting)
);
end component;
component cnt_array_regs is -- counter array, register based
generic (
AWIDTH : positive := 4; -- address width
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- clear counters
CE : in slv(2**AWIDTH-1 downto 0); -- count enables
ADDR : in slv(AWIDTH-1 downto 0); -- address
DATA : out slv(DWIDTH-1 downto 0) -- counter data
);
end component;
component debounce_gen is -- debounce, generic vector
generic (
CWIDTH : positive := 2; -- clock interval counter width
CEDIV : positive := 3; -- clock interval divider
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_INT : in slbit; -- clock interval enable (usec or msec)
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
component gray_cnt_gen is -- gray code counter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
component gray_cnt_4 is -- 4 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv4 -- data out
);
end component;
component gray_cnt_5 is -- 5 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv5 -- data out
);
end component;
component gray_cnt_n is -- n bit gray code counter
generic (
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
component gray2bin_gen is -- gray->bin converter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
DI : in slv(DWIDTH-1 downto 0); -- gray code input
DO : out slv(DWIDTH-1 downto 0) -- binary code output
);
end component;
component timer is -- retriggerable timer
generic (
TWIDTH : positive := 4; -- timer counter width
RETRIG : boolean := true); -- re-triggerable true/false
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DELAY : in slv(TWIDTH-1 downto 0) := (others=>'1'); -- timer delay
START : in slbit; -- start timer
STOP : in slbit := '0'; -- stop timer
DONE : out slbit; -- mark last delay cycle
BUSY : out slbit -- timer running
);
end component;
component cdc_pulse is -- clock domain cross for pulse
generic (
POUT_SINGLE : boolean := false; -- if true: single cycle pout
BUSY_WACK : boolean := false); -- if true: busy waits for ack
port (
CLKM : in slbit; -- clock master
RESET : in slbit := '0'; -- M|reset
CLKS : in slbit; -- clock slave
PIN : in slbit; -- M|pulse in
BUSY : out slbit; -- M|busy
POUT : out slbit -- S|pulse out
);
end component;
end package genlib;
|
gpl-2.0
|
7444e7a9ccd44c4ad5b7ce1669673dbc
| 0.520133 | 4.055657 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_serloop/tst_serloop_hiomap.vhd
| 1 | 7,318 |
-- $Id: tst_serloop_hiomap.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_serloop_hiomap - syn
-- Description: default human I/O mapper
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-09 437 1.0.2 rename serport stat->moni port
-- 2011-11-16 426 1.0.1 setup leds and dps
-- 2011-11-05 420 1.0 Initial version
------------------------------------------------------------------------------
--
-- Usage of Switches, Buttons, LEDs:
--
-- BTN(3): -- unused --
-- (2): -- unused --
-- (1): load enables from SWI(7:4)
-- SWI(7) -> ENAFTDI
-- SWI(6) -> ENATHROTTLE
-- SWI(5) -> ENAESC
-- SWI(4) -> ENAXON
-- (0): reset state [!! decoded by top level design !!]
--
-- SWI(7:4) select display or enable pattern (when BTN(1) pressed)
-- (3) -- unused --
-- (2:1): mode 00 idle
-- 01 rxblast
-- 10 txblast
-- 11 loop
-- SWI(0) 0 -> main board RS232 port
-- 1 -> Pmod1 RS232 port
--
-- LED(7) enaesc
-- (6) enaxon
-- (5) rxfecnt > 0 (frame error)
-- (4) rxoecnt > 0 (overrun error)
-- (3) rxsecnt > 0 (sequence error)
-- (2) abact (shows ab activity)
-- (1) (not rxok) or (not txok) (shows back preasure)
-- (0) rxact or txact (shows activity)
--
-- DSP data as selected by SWI(7:4)
-- 0000 -> rxfecnt
-- 0001 -> rxoecnt
-- 0010 -> rxsecnt
-- 0100 -> rxcnt.l
-- 0101 -> rxcnt.h
-- 0110 -> txcnt.l
-- 0111 -> txcnt.h
-- 1000 -> rxokcnt
-- 1001 -> txokcnt
-- 1010 -> rxuicnt,rxuidat
-- 1111 -> abclkdiv
--
-- DP(3): not SER_MONI.txok (shows tx back preasure)
-- (2): SER_MONI.txact (shows tx activity)
-- (1): not SER_MONI.rxok (shows rx back preasure)
-- (0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serport.all;
use work.tst_serlooplib.all;
-- ----------------------------------------------------------------------------
entity tst_serloop_hiomap is -- default human I/O mapper
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
HIO_CNTL : out hio_cntl_type; -- tester controls from hio
HIO_STAT : in hio_stat_type; -- tester status to diaplay by hio
SER_MONI : in serport_moni_type; -- serport monitor to display by hio
SWI : in slv8; -- switch settings
BTN : in slv4; -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end tst_serloop_hiomap;
architecture syn of tst_serloop_hiomap is
type regs_type is record
enaxon : slbit; -- enable xon/xoff handling
enaesc : slbit; -- enable xon/xoff escaping
enathrottle : slbit; -- enable 1 msec tx throttling
enaftdi : slbit; -- enable ftdi flush handling
dspdat : slv16; -- display data
end record regs_type;
constant regs_init : regs_type := (
'0','0','0','0', -- enaxon,enaesc,enathrottle,enaftdi
(others=>'0') -- dspdat
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, HIO_STAT, SER_MONI, SWI, BTN)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable icntl : hio_cntl_type := hio_cntl_init;
variable iled : slv8 := (others=>'0');
variable idat : slv16 := (others=>'0');
variable idp : slv4 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
icntl := hio_cntl_init;
iled := (others=>'0');
idat := (others=>'0');
idp := (others=>'0');
-- handle BTN(1) "load enables" press
if BTN(1) = '1' then
n.enaxon := SWI(4);
n.enaesc := SWI(5);
n.enathrottle := SWI(6);
n.enaftdi := SWI(7);
end if;
-- setup tester controls
icntl.mode := SWI(2 downto 1);
icntl.enaxon := r.enaxon;
icntl.enaesc := r.enaesc;
icntl.enathrottle := r.enathrottle;
icntl.enaftdi := r.enaftdi;
-- setup leds
iled(7) := icntl.enaesc;
iled(6) := icntl.enaxon;
if unsigned(HIO_STAT.rxfecnt) > 0 then iled(5) := '1'; end if;
if unsigned(HIO_STAT.rxoecnt) > 0 then iled(4) := '1'; end if;
if unsigned(HIO_STAT.rxsecnt) > 0 then iled(3) := '1'; end if;
iled(2) := SER_MONI.abact;
iled(1) := (not SER_MONI.rxok) or (not SER_MONI.txok);
iled(0) := SER_MONI.rxact or SER_MONI.txact;
-- setup display data
case SWI(7 downto 4) is
when "0000" => idat := HIO_STAT.rxfecnt;
when "0001" => idat := HIO_STAT.rxoecnt;
when "0010" => idat := HIO_STAT.rxsecnt;
when "0100" => idat := HIO_STAT.rxcnt(15 downto 0);
when "0101" => idat := HIO_STAT.rxcnt(31 downto 16);
when "0110" => idat := HIO_STAT.txcnt(15 downto 0);
when "0111" => idat := HIO_STAT.txcnt(31 downto 16);
when "1000" => idat := HIO_STAT.rxokcnt;
when "1001" => idat := HIO_STAT.txokcnt;
when "1010" => idat := HIO_STAT.rxuicnt & HIO_STAT.rxuidat;
when "1111" => idat := SER_MONI.abclkdiv;
when others => null;
end case;
n.dspdat := idat;
-- setup display decimal points
idp(3) := not SER_MONI.txok; -- tx back preasure
idp(2) := SER_MONI.txact; -- tx activity
idp(1) := not SER_MONI.rxok; -- rx back preasure
idp(0) := SER_MONI.rxact; -- rx activity
N_REGS <= n;
HIO_CNTL <= icntl;
LED <= iled;
DSP_DAT <= r.dspdat;
DSP_DP <= idp;
end process proc_next;
end syn;
|
gpl-2.0
|
d3fdbd9185a16e6807abd5919b0e3860
| 0.509292 | 3.662663 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_snhumanio/nexys3/sys_tst_snhumanio_n3.vhd
| 2 | 5,191 |
-- $Id: sys_tst_snhumanio_n3.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_snhumanio_n3 - syn
-- Description: snhumanio tester design for nexys3
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/sn_humanio
-- tst_snhumanio
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-11-27 433 13.1 O40d xc3s1200e-4 151 195 - 65 t 6.1
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-27 433 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_snhumanio_n3 is -- top level
-- implements nexys3_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit -- ppcm: ...
);
end sys_tst_snhumanio_n3;
architecture syn of sys_tst_snhumanio_n3 is
signal CLK : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_MSEC : slbit := '0';
begin
RESET <= '0'; -- so far not used
CLK <= I_CLK100;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => 100,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
HIOTEST : entity work.tst_snhumanio
generic map (
BWIDTH => 5)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
O_TXD <= I_RXD;
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end syn;
|
gpl-2.0
|
50bc5351258bac3635ee66908a3a6eb7
| 0.486804 | 3.476892 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_rlink/nexys3/sys_conf.vhd
| 1 | 1,722 |
-- $Id: sys_conf.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1; --
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer :=
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
gpl-2.0
|
fefc3269ce8e67e0257b9a1a57cb3282
| 0.642276 | 3.878378 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega2/Procesador_2.vhd
| 1 | 5,704 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Processor is
Port ( rst : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (31 downto 0);
clk : in STD_LOGIC);
end Processor;
architecture Behavioral of Processor is
signal out_nPC: STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
signal data_in: STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
signal pc_out: STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
signal im_out: STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
signal seu_out: STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
signal imm13_aux: STD_LOGIC_VECTOR(12 downto 0):=(others=>'0');--en formato3
--el inmmediato va del bit 0 al 12
signal crs1_aux: STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
signal crs2_aux: STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
signal mux_out: STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
signal cpu_out: STD_LOGIC_VECTOR(5 downto 0):=(others=>'0');
signal alu_out: STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
signal cwp: std_logic:= '0';
signal nrs1: STD_LOGIC_VECTOR (5 downto 0):=(others => '0');
signal nrs2: STD_LOGIC_VECTOR (5 downto 0):=(others => '0');
signal nrd: STD_LOGIC_VECTOR (5 downto 0):=(others => '0');
signal Ncwp: std_logic:= '0';
signal carry: std_logic:= '0';
signal nzvc: STD_LOGIC_VECTOR (3 downto 0):=(others => '0');
COMPONENT PC
PORT(
rst : IN std_logic;
clk : IN std_logic;
DAT_in : IN std_logic_vector(31 downto 0);
DAT_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT Sumador
PORT(
operador1 : IN std_logic_vector(31 downto 0);
operador2 : IN std_logic_vector(31 downto 0);
resultado : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT IM
PORT(
rst : in STD_LOGIC;
addr : IN std_logic_vector(31 downto 0);
data : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT windows_manager_arch
Port ( rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
CWP : in STD_LOGIC;
nrs1 : out STD_LOGIC_VECTOR (5 downto 0);
nrs2 : out STD_LOGIC_VECTOR (5 downto 0);
nrd : out STD_LOGIC_VECTOR (5 downto 0);
Ncwp : out STD_LOGIC);
END COMPONENT;
COMPONENT Mod5Seu
PORT(
imm13 : IN std_logic_vector(12 downto 0);
SEUimm32 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT MUX
PORT(
Crs2 : IN std_logic_vector(31 downto 0);
SEUimm13 : IN std_logic_vector(31 downto 0);
i : IN std_logic;
Oper2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT RF
PORT(
rst : in STD_LOGIC;
rs1 : IN std_logic_vector(5 downto 0);
rs2 : IN std_logic_vector(5 downto 0);
rd : IN std_logic_vector(5 downto 0);
dwr : IN std_logic_vector(31 downto 0);
ORs1 : OUT std_logic_vector(31 downto 0);
ORs2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT ALU
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
ALUOP : IN std_logic_vector(5 downto 0);
carry : in std_logic;
Salida : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT CU
PORT(
op : IN std_logic_vector(1 downto 0);
op3 : IN std_logic_vector(5 downto 0);
aluop : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
COMPONENT PSR
Port ( NZVC : in STD_LOGIC_VECTOR (3 downto 0);
Rst : in STD_LOGIC;
clk : in STD_LOGIC;
Ncwp : in STD_LOGIC;
Carry : out STD_LOGIC;
Cwp : out STD_LOGIC
);
END COMPONENT;
COMPONENT PSR_Modifier
Port( AluResult : in STD_LOGIC_VECTOR (31 downto 0);
OP1 : in STD_LOGIC;
OP2 : in STD_LOGIC;
AluOp : in STD_LOGIC_VECTOR (5 downto 0);
NZVC : out STD_LOGIC_VECTOR (3 downto 0));
END COMPONENT;
begin
Inst_PC: PC PORT MAP(
rst => rst,
clk => clk,
DAT_in => out_nPC,
DAT_out => pc_out
);
Inst_nPC: PC PORT MAP(
rst => rst,
clk => clk,
DAT_in => data_in,
DAT_out => out_nPC
);
Inst_Sumador: Sumador PORT MAP(
operador1 => "00000000000000000000000000000001",
operador2 => pc_out,
resultado => data_in
);
Inst_IM: IM PORT MAP(
rst => rst,
addr => pc_out,
data => im_out
);
Inst_SEU: Mod5Seu PORT MAP(
imm13 => im_out(12 downto 0),
SEUimm32 => seu_out
);
Inst_MUX: MUX PORT MAP(
Crs2 => crs2_aux,
SEUimm13 => seu_out,
i => im_out(13),
Oper2 => mux_out
);
Inst_WM : windows_manager_arch port map(
rs1 => im_out(18 downto 14),
rs2 => im_out(4 downto 0),
rd => im_out(29 downto 25),
op => im_out(31 downto 30),
op3 => im_out(24 downto 19),
CWP => cwp,
nrs1 => nrs1,
nrs2 => nrs2,
nrd => nrd,
Ncwp => Ncwp
);
Inst_PSR : PSR port map(
NZVC => nzvc,
rst => rst,
clk => clk,
Ncwp => Ncwp,
Carry => carry,
cwp => cwp
);
Inst_PSR_mod : PSR_modifier port map(
AluResult => alu_out,
OP1 => crs1_aux(31),
OP2 => mux_out(31),
AluOp => cpu_out,
NZVC => nzvc
);
Inst_RF: RF PORT MAP(
rst => rst,
rs1 => nrs1,
rs2 => nrs2,
rd => nrd,
dwr => alu_out,
ORs1 => crs1_aux,
ORs2 => crs2_aux
);
Inst_ALU: ALU PORT MAP(
Oper1 => crs1_aux,
Oper2 => mux_out,
ALUOP => cpu_out,
carry => carry,
Salida => alu_out
);
Inst_CU: CU PORT MAP(
op => im_out(31 downto 30),
op3 => im_out(24 downto 19),
aluop => cpu_out
);
data_out <= alu_out;
end Behavioral;
|
mit
|
09246df9eb8d91ab2e26d7960d4babc4
| 0.593093 | 2.90872 | false | false | false | false |
os-cillation/easyfpga-soc
|
infrastructure/syscon.vhd
| 1 | 3,399 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- W I S H B O N E S Y S C O N
-- (syscon.vhd)
--
-- Structural
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;
--------------------------------------------------------------------------------
ENTITY syscon is
--------------------------------------------------------------------------------
generic (
-- multiply clock to 80 MHz
MULTIPLY : natural := 10
);
port (
clk_in : in std_logic;
clk_out : out std_logic;
rst_out : out std_logic
);
end syscon;
--------------------------------------------------------------------------------
ARCHITECTURE structural of syscon is
--------------------------------------------------------------------------------
signal dcm_status_s : std_logic_vector(7 downto 0);
signal reset_dcm : std_logic;
signal clk_feedback1x_s : std_logic;
--------------------------------------------------------------------------------
begin -- architecture structural
--------------------------------------------------------------------------------
-- tie rst_out to zero
rst_out <= '0';
-- reset if status(1) is asserted (clk_in is not toggling)
reset_dcm <= dcm_status_s(1);
--------------------------------------------------------------------------------
Clock_Manager : DCM_SP
--------------------------------------------------------------------------------
generic map (
CLKDV_DIVIDE => 2.0, -- CLKDV divide value
CLKFX_DIVIDE => 1, -- Divide value on CLKFX outputs - D - (1-32)
CLKFX_MULTIPLY => MULTIPLY, -- Multiply value on CLKFX outputs - M - (2-32)
CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE)
CLKIN_PERIOD => 125.0, -- Input clock period specified in nS
CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE)
CLK_FEEDBACK => "1X", -- Feedback source (NONE, 1X, 2X)
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255)
STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
)
port map (
CLKIN => clk_in,
CLKFX => clk_out,
CLK0 => clk_feedback1x_s,
CLKFB => clk_feedback1x_s,
STATUS => dcm_status_s,
RST => reset_dcm
);
end structural;
|
gpl-3.0
|
70b029078adbb5b1774caa9b50591ec9
| 0.46396 | 4.855714 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/serport/tb/tb_serport_uart_rxtx.vhd
| 1 | 7,601 |
-- $Id: tb_serport_uart_rxtx.vhd 417 2011-10-22 10:30:29Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_serport_uart_rxtx - sim
-- Description: Test bench for serport_uart_rxtx
--
-- Dependencies: simlib/simclk
-- tbd_serport_uart_rxtx [UUT]
--
-- To test: serport_uart_rxtx
--
-- Target Devices: generic
--
-- Verified (with tb_serport_uart_rxtx_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2007-11-02 93 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-21 91 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-10-21 91 - 0.26 - - c:ok
-- 2007-10-14 89 - 0.26 - - c:ok
-- 2007-10-12 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-10-12 88 - 0.26 - - c:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 417 1.1.3 now numeric_std clean
-- 2010-04-24 281 1.1.2 use direct instatiation for tbd_
-- 2008-03-24 129 1.1.1 CLK_CYCLE now 31 bits
-- 2007-10-21 91 1.1 now use 'send' command, self-checking (FAIL's)
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.serport.all;
entity tb_serport_uart_rxtx is
end tb_serport_uart_rxtx;
architecture sim of tb_serport_uart_rxtx is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CLKDIV : slv13 := slv(to_unsigned(15, 13));
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXSD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : slv31 := (others=>'0');
signal N_MON_VAL : slbit := '0';
signal N_MON_DAT : slv8 := (others=>'0');
signal R_MON_VAL_1 : slbit := '0';
signal R_MON_DAT_1 : slv8 := (others=>'0');
signal R_MON_VAL_2 : slbit := '0';
signal R_MON_DAT_2 : slv8 := (others=>'0');
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 10 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
CLK_STOP => CLK_STOP
);
UUT : entity work.tbd_serport_uart_rxtx
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => TXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
proc_stim: process
file fstim : text open read_mode is "tb_serport_uart_rxtx_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable itxdata : slv8 := (others=>'0');
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable irate : integer := 16;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".rate " => -- .rate
read_ea(iline, irate);
CLKDIV <= slv(to_unsigned(irate-1, 13));
when "send " => -- send
read_ea(iline, idelta);
read_ea(iline, itxdata);
while TXBUSY='1' loop
wait for clock_period;
end loop;
wait for idelta*clock_period;
writetimestamp(oline, CLK_CYCLE, ": send ");
write(oline, itxdata, right, 10);
writeline(output, oline);
TXDATA <= itxdata;
TXENA <= '1';
N_MON_VAL <= '1';
N_MON_DAT <= itxdata;
wait for clock_period;
TXENA <= '0';
N_MON_VAL <= '0';
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop
idelta := 0;
while TXBUSY='1' or RXACT='1' loop
wait for clock_period;
idelta := idelta + 1;
exit when idelta>3000;
end loop;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait for 12*irate*clock_period;
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if R_MON_VAL_1 = '1' then
if R_MON_VAL_2 = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, string'(" FAIL MISSING DATA="));
write(oline, R_MON_DAT_2);
writeline(output, oline);
end if;
R_MON_VAL_2 <= R_MON_VAL_1;
R_MON_DAT_2 <= R_MON_DAT_1;
end if;
R_MON_VAL_1 <= N_MON_VAL;
R_MON_DAT_1 <= N_MON_DAT;
if RXVAL='1' or RXERR='1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, RXDATA, right, 10);
if RXERR = '1' then
write(oline, string'(" RXERR=1"));
end if;
if R_MON_VAL_2 = '0' then
write(oline, string'(" FAIL UNEXPECTED"));
else
write(oline, string'(" CHECK"));
R_MON_VAL_2 <= '0';
if R_MON_DAT_2 = RXDATA and
RXERR='0' then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL"));
end if;
end if;
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;
|
gpl-2.0
|
3ff433395d6b0c1bde04a17926f4c381
| 0.522563 | 3.673755 | false | false | false | false |
willprice/build-a-comp-vhdl-modules
|
base/DMux.vhd
| 1 | 911 |
library ieee, base;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use base.base.all;
entity DMux is
port(
data_in : in unsigned(3 downto 0);
data_out_array : out FourInput(3 downto 0);
control_in : in unsigned(3 downto 0);
control_out : out unsigned(3 downto 0)
);
end entity DMux;
architecture DataFlow of DMux is
signal control : unsigned(1 downto 0);
begin
control <= control_in(1 downto 0);
control_out <= control_in;
process(control, data_in)
begin
-- Set default values
for i in data_out_array'range loop
data_out_array(i) <= "0000";
end loop;
case (control) is
when "00" => data_out_array(0) <= data_in;
when "01" => data_out_array(1) <= data_in;
when "10" => data_out_array(2) <= data_in;
when "11" => data_out_array(3) <= data_in;
when others => data_out_array(0) <= data_in;
end case;
end process;
end architecture;
|
mit
|
a533fbdc52a759dea24123b2d499cac0
| 0.639956 | 2.735736 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_rlink/nexys2/sys_conf.vhd
| 2 | 1,721 |
-- $Id: sys_conf.vhd 351 2010-12-30 21:50:54Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 12.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1; --
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
gpl-2.0
|
aefd7ae15a1903983de222a55c2478c6
| 0.642069 | 3.876126 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega3/ALU.vhd
| 1 | 2,357 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU is
Port ( Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0);
carry : in std_logic;
Salida : out STD_LOGIC_VECTOR (31 downto 0)
);
end ALU;
architecture Behavioral of ALU is
begin
process(ALUOP,Oper1,Oper2)
begin
case ALUOP is
when "000000" => --ADD
Salida <= Oper1 + Oper2;
when "000001" => --SUB
Salida <= Oper1 - Oper2;
when "000010" => --AND
Salida <= Oper1 and Oper2;
when "000011" => --ANDN
Salida <= Oper1 and not Oper2;
when "000100" => --OR
Salida <= Oper1 or Oper2;
when "000101" => --ORN
Salida <= Oper1 or not Oper2;
when "000110" => --XOR
Salida <= Oper1 xor Oper2;
when "000111" => --XNOR
Salida <= Oper1 xnor Oper2;
when "001000" => --SUBcc
Salida <= Oper1 - Oper2;
when "001001" => -- SUBx
Salida <= Oper1 - Oper2 - Carry;
when "001010" => --SUBxcc
Salida <= Oper1 - Oper2 - Carry;
when "001011" => --ANDcc
Salida <= Oper1 and Oper2;
when "001100" => --ANDNcc
Salida <= Oper1 and not Oper2;
when "001101" => --ORcc
Salida <= Oper1 or Oper2;
when "001110" => --ORNcc
Salida <= Oper1 or not Oper2;
when "001111" => --XORcc
Salida <= Oper1 xor Oper2;
when "010000" => --XNORcc
Salida <= Oper1 xnor Oper2;
when "010001" => --ADDx
Salida <= Oper1 + Oper2 + Carry;
when "010010" => --ADDxcc
Salida <= Oper1 + Oper2 + Carry;
when "010011" => --ADDcc
Salida <= Oper1 + Oper2;
when "100101" => --sll
Salida <= std_logic_vector(unsigned(Oper1) sll to_integer(unsigned(Oper2)));
when "100110" => --srl
Salida <= std_logic_vector(unsigned(Oper1) srl to_integer(unsigned(Oper2)));
--SAVE 57
when "111001" =>
Salida <= Oper1 + Oper2;
--RESTORE 58
when "111101" =>
Salida <= Oper1 + Oper2;
when others =>
Salida <= (others=>'1'); --error
end case;
end process;
end Behavioral;
|
mit
|
da4fb33e77c11eaa3f793f72f07f17a9
| 0.529062 | 3.497033 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/rlink/rlink_sp1c.vhd
| 1 | 4,885 |
-- $Id: rlink_sp1c.vhd 437 2011-12-09 19:38:07Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_sp1c - syn
-- Description: rlink_core8 + serport_1clock combo
--
-- Dependencies: rlink_core8
-- serport/serport_1clock
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa
-- 2011-12-09 437 13.1 O40d xc3s1000-4 337 733 64 469 s 9.8 - -
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-09 437 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serport.all;
entity rlink_sp1c is -- rlink_core8+serport_1clock combo
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6; -- idle timeout counter width
CPREF : slv4 := c_rlink_cpref; -- comma prefix
IFAWIDTH : natural := 5; -- input fifo address width (0=none)
OFAWIDTH : natural := 5; -- output fifo address width (0=none)
ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
SER_MONI : out serport_moni_type -- serport: monitor port
);
end entity rlink_sp1c;
architecture syn of rlink_sp1c is
signal RLB_DI : slv8 := (others=>'0');
signal RLB_ENA : slbit := '0';
signal RLB_BUSY : slbit := '0';
signal RLB_DO : slv8 := (others=>'0');
signal RLB_VAL : slbit := '0';
signal RLB_HOLD : slbit := '0';
begin
CORE : rlink_core8
generic map (
ATOWIDTH => ATOWIDTH,
ITOWIDTH => ITOWIDTH,
CPREF => CPREF,
ENAPIN_RLMON => ENAPIN_RLMON,
ENAPIN_RBMON => ENAPIN_RBMON)
port map (
CLK => CLK,
CE_INT => CE_INT,
RESET => RESET,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
SERPORT : serport_1clock
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT,
RXFAWIDTH => IFAWIDTH,
TXFAWIDTH => OFAWIDTH)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => ENAXON,
ENAESC => ENAESC,
RXDATA => RLB_DI,
RXVAL => RLB_ENA,
RXHOLD => RLB_BUSY,
TXDATA => RLB_DO,
TXENA => RLB_VAL,
TXBUSY => RLB_HOLD,
MONI => SER_MONI,
RXSD => RXSD,
TXSD => TXSD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
end syn;
|
gpl-2.0
|
7d388d13a7f6906e75ba62582c729464
| 0.529171 | 3.726163 | false | false | false | false |
Kolchuzhin/LMGT_MEMS_component_library
|
tensoresistor/tensoresitor.vhd
| 1 | 1,688 |
-- Model: tensoresistor
-- Author: Vladimir Kolchuzhin, LMGT, TU Chemnitz
-- <[email protected]>
--
-- Date: 07.06.2011
-- Library: kvl in hAMSter
-------------------------------------------------------------------------------
-- ID: tensoresistor.vhd
-- Modification History (rev, date, author):
--
-- Revision 1.0 25.04.2012 official release for ForGr1713, www.zfm.tu-chemnitz.de/for1713
-- 28.02.2015 GitHub
-- Status: Compile OK, model was compiled with hAMSter simulator
-------------------------------------------------------------------------------
library ieee;
use ieee.math_real.all;
--use ieee.electrical_systems.all;
--use ieee.mechanical_systems.all;
--use ieee.fundamental_constants.all;
use work.electromagnetic_system.all;
use work.all;
-------------------------------------------------------------------------------
entity tensoresistor is
-- input parameters:
-- strain == axial strain = (L-L0)/L0 = f/c1/L0; (L-L0=u; f=c1*u)
-- Gf == gauge factor
-- Rc == initial undeformed resistance in Ohm
generic(Rc,Gf:real); -- given as a generic parameter
port(terminal input1,input2:translational;
terminal node1,node2:electrical); -- electrical ports
end entity tensoresistor;
-------------------------------------------------------------------------------
architecture basic of tensoresistor is
quantity strain across input1 to input2;
quantity v1 across i1 through node1;
quantity v2 across i2 through node2;
begin
i1 == (v1-v2)/(Rc*(1.0 + Gf*strain)); -- metal-film tensoresistor
i2 == -i1;
end architecture basic;
-------------------------------------------------------------------------------
|
mit
|
7b3a293711a7165b8bf25bc3b6e5f77e
| 0.542654 | 4.019048 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/rlink/tb/tbd_rlink_sp1c.vhd
| 1 | 9,306 |
-- $Id: tbd_rlink_sp1c.vhd 442 2011-12-23 10:03:28Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_rlink_sp1c - syn
-- Description: Wrapper for rlink_core plus rlink_serport with an interface
-- compatible to the rlink_core only module.
-- NOTE: this implementation is a hack, should be redone
-- using configurations.
--
-- Dependencies: tbu_rlink_sp1c [UUT]
-- serport_uart_tx
-- serport_uart_rx
-- byte2cdata
-- cdata2byte
--
-- To test: rlink_sp1c
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-22 442 3.1 renamed and retargeted to tbu_rlink_sp1c
-- 2011-11-19 427 3.0.5 now numeric_std clean
-- 2010-12-28 350 3.0.4 use CLKDIV/CDINIT=0;
-- 2010-12-26 348 3.0.3 add RTS/CTS ports for tbu_;
-- 2010-12-24 347 3.0.2 rename: CP_*->RL->*
-- 2010-12-22 346 3.0.1 removed proc_moni, use .rlmon cmd in test bench
-- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol;
-- 2010-06-06 301 2.3 use NCOMM=4 (new eop,nak commas)
-- 2010-05-02 287 2.2.2 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2010-04-24 281 2.2.1 use serport_uart_[tr]x directly again
-- 2010-04-03 274 2.2 add CE_USEC
-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2007-11-25 98 1.1 added RP_IINT support; use entity rather arch
-- name to switch core/serport;
-- use serport_uart_[tr]x_tb to allow that UUT is a
-- [sft]sim model compiled with keep hierarchy
-- 2007-07-02 63 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.comlib.all;
use work.serport.all;
use work.simlib.all;
use work.simbus.all;
entity tbd_rlink_sp1c is -- rlink_sp1c tb design
-- implements tbd_rlink_gen
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- rlink ito time unit clock enable
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
RL_DI : in slv9; -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : out slbit; -- rlink: data busy
RL_DO : out slv9; -- rlink: data out
RL_VAL : out slbit; -- rlink: data valid
RL_HOLD : in slbit; -- rlink: data hold
RB_MREQ_aval : out slbit; -- rbus: request - aval
RB_MREQ_re : out slbit; -- rbus: request - re
RB_MREQ_we : out slbit; -- rbus: request - we
RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : out slv8; -- rbus: request - addr
RB_MREQ_din : out slv16; -- rbus: request - din
RB_SRES_ack : in slbit; -- rbus: response - ack
RB_SRES_busy : in slbit; -- rbus: response - busy
RB_SRES_err : in slbit; -- rbus: response - err
RB_SRES_dout : in slv16; -- rbus: response - dout
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
TXRXACT : out slbit -- txrx active flag
);
end entity tbd_rlink_sp1c;
architecture syn of tbd_rlink_sp1c is
constant CDWIDTH : positive := 13;
constant c_cdinit : natural := 0; -- NOTE: change in tbu_rlink_sp1c !!
signal RRI_RXSD : slbit := '0';
signal RRI_TXSD : slbit := '0';
signal RTS_N : slbit := '0';
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal CLKDIV : slv13 := slv(to_unsigned(c_cdinit,CDWIDTH));
component tbu_rlink_sp1c is -- rlink core+serport combo
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- rlink ito time unit clock enable
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ_aval : out slbit; -- rbus: request - aval
RB_MREQ_re : out slbit; -- rbus: request - re
RB_MREQ_we : out slbit; -- rbus: request - we
RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : out slv8; -- rbus: request - addr
RB_MREQ_din : out slv16; -- rbus: request - din
RB_SRES_ack : in slbit; -- rbus: response - ack
RB_SRES_busy : in slbit; -- rbus: response - busy
RB_SRES_err : in slbit; -- rbus: response - err
RB_SRES_dout : in slv16; -- rbus: response - dout
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end component;
begin
UUT : tbu_rlink_sp1c
port map (
CLK => CLK,
CE_INT => CE_INT,
CE_USEC => CE_USEC,
CE_MSEC => '1',
RESET => RESET,
RXSD => RRI_RXSD,
TXSD => RRI_TXSD,
CTS_N => '0',
RTS_N => RTS_N,
RB_MREQ_aval => RB_MREQ_aval,
RB_MREQ_re => RB_MREQ_re,
RB_MREQ_we => RB_MREQ_we,
RB_MREQ_initt=> RB_MREQ_initt,
RB_MREQ_addr => RB_MREQ_addr,
RB_MREQ_din => RB_MREQ_din,
RB_SRES_ack => RB_SRES_ack,
RB_SRES_busy => RB_SRES_busy,
RB_SRES_err => RB_SRES_err,
RB_SRES_dout => RB_SRES_dout,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
UARTRX : serport_uart_rx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RRI_TXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => open,
RXACT => RXACT
);
UARTTX : serport_uart_tx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
TXSD => RRI_RXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
TXRXACT <= RXACT or TXBUSY;
B2CD : byte2cdata -- byte stream -> 9bit comma,data
generic map (
CPREF => c_rlink_cpref,
NCOMM => c_rlink_ncomm)
port map (
CLK => CLK,
RESET => RESET,
DI => RXDATA,
ENA => RXVAL,
BUSY => open,
DO => RL_DO,
VAL => RL_VAL,
HOLD => RL_HOLD
);
CD2B : cdata2byte -- 9bit comma,data -> byte stream
generic map (
CPREF => c_rlink_cpref,
NCOMM => c_rlink_ncomm)
port map (
CLK => CLK,
RESET => RESET,
DI => RL_DI,
ENA => RL_ENA,
BUSY => RL_BUSY,
DO => TXDATA,
VAL => TXENA,
HOLD => TXBUSY
);
proc_moni: process
variable oline : line;
variable rts_last : slbit := '0';
variable ncycle : integer := 0;
begin
loop
wait until rising_edge(CLK); -- check at end of clock cycle
if RTS_N /= rts_last then
writetimestamp(oline, SB_CLKCYCLE, ": rts ");
write(oline, string'(" RTS_N "));
write(oline, rts_last, right, 1);
write(oline, string'(" -> "));
write(oline, RTS_N, right, 1);
write(oline, string'(" after "));
write(oline, ncycle, right, 5);
write(oline, string'(" cycles"));
writeline(output, oline);
rts_last := RTS_N;
ncycle := 0;
end if;
ncycle := ncycle + 1;
end loop;
end process proc_moni;
end syn;
|
gpl-2.0
|
f9e7e4b3d43cc3e979d8fa6398dae158
| 0.517301 | 3.609775 | false | false | false | false |
rogerioag/gcg
|
samples/and2/testbench/and2_tb.vhd
| 1 | 3,427 |
-- Testbench generated by script.
-- Date: Dom,20/01/2013-11:22:53
-- Author: rogerio
-- Comments: Test of and2 entity..
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- print messages.
use std.textio.all;
use ieee.std_logic_textio.all;
entity and2_tb is
end and2_tb;
architecture logic of and2_tb is
-- Component declaration.
component and2
port (x, y: in std_logic; z: out std_logic);
end component;
-- Specifies the entity which is linked with the component. (Especifica qual a entidade está vinculada com o componente).
for and2_0: and2 use entity work.and2;
signal s_t_x, s_t_y, s_t_z: std_logic;
-- procedure print messages definition.
procedure print_message( pi_s_t_x, pi_s_t_y: std_logic; po_s_t_z: std_logic; pe_z: std_logic) is
variable line_out: line;
begin
write(line_out, string'(" At time "));
write(line_out, now);
write(line_out, string'(", inputs ["));
write(line_out, string'(" s_t_x: "));
write(line_out, pi_s_t_x);
write(line_out, string'(" s_t_y: "));
write(line_out, pi_s_t_y);
write(line_out, string'("]"));
write(line_out, string'(", outputs ["));
write(line_out, string'(" s_t_z: "));
write(line_out, string'("(generated: "));
write(line_out, po_s_t_z);
write(line_out, string'(", expected: "));
write(line_out, pe_z);
write(line_out, string'(")"));
write(line_out, string'("]"));
if (s_t_z = pe_z) then
write(line_out, string'(" [OK]"));
else
write(line_out, string'(" [Error]"));
end if;
writeline(output, line_out);
end procedure print_message;
begin
-- Component instantiation.
-- port map (<<p_in_1>> => <<s_t_in_1>>)
and2_0: and2 port map ( x=>s_t_x, y=>s_t_y, z=>s_t_z);
-- Process that works.
process
-- line to print.
variable line_out: line;
-- A record is created with the inputs and outputs of the entity.
-- (<<entrada1>>, <<entradaN>>, <<saida1>>, <<saidaN>>)
type pattern_type is record
-- inputs.
vi_x, vi_y: std_logic;
-- outputs.
vo_z: std_logic;
end record;
-- The input patterns are applied (injected) to the inputs of the entity under test.
type pattern_array is array (natural range <>) of pattern_type;
-- Test cases.
constant patterns : pattern_array :=
(
('0','0','0'),
('0','1','0'),
('1','0','0'),
('1','1','1')
);
begin
-- Message starting...
write(line_out, string'("Running testbench: and2_tb."));
writeline(output, line_out);
write(line_out, string'(" Testing entity: and2."));
writeline(output, line_out);
-- Injects the inputs and check thte outputs.
for i in patterns'range loop
-- Injects the inputs.
s_t_x <= patterns(i).vi_x;
s_t_y <= patterns(i).vi_y;
-- wait for results.
wait for 1 ns;
-- Checks the result with the expected output in the pattern.
print_message( s_t_x, s_t_y, s_t_z, patterns(i).vo_z);
assert (s_t_z = patterns(i).vo_z) report "Valor de s_t_z não confere com o resultado esperado." severity error;
end loop;
write(line_out, string'("Execution of and2_tb finished."));
writeline(output, line_out);
assert false report "End of test." severity note;
-- Wait forever; Isto finaliza a simulação.
wait;
end process;
end logic;
|
gpl-3.0
|
5e9f523f774ffa85f38b827cc82e87d8
| 0.605609 | 3.081008 | false | true | false | false |
AdanDuM/INE5406-SD
|
timer_2sec.vhd
| 1 | 1,197 |
library IEEE;
use IEEE.std_logic_1164.all;
use iEEE.numeric_std.all;
-- Alunos: Adan Pereira Gomes e Wesley Mayk Gama Luz
entity timer_2sec is
port (
clock, reset: in std_logic;
time_out : out std_logic
);
end entity;
architecture sequencial of timer_2sec is
type State is (init, count, sm0, sm1, zero);
signal actualState, nextState: State;
signal tempo: positive range 0 to 5;
begin
-- next state logic
LPE: process(actualState, tempo, sn_m0, sn_m1) is
begin
nextState <= actualState;
case actualState is
when init =>
nextState <= count;
when count =>
if tempo = 2 then
nextState <= zero;
end if;
when zero =>
nextState <= actualState;
end case;
end process;
-- state element (memory)
ME: process (clock, reset)
begin
if reset = '0' then
actualState <= init;
elsif rising_edge(clock) then
actualState <= nextState;
end if;
end process;
-- output-logic
OL: process(actualState) is
begin
case actualState is
when init =>
tempo <= 0;
time_out <= 0;
when count =>
tempo <= tempo + 1 ;
zero <= 0;
when zero =>
tempo <= tempo;
zero <= 1;
end case;
end process;
end architecture;
|
gpl-2.0
|
5c197dc123622d4bce53a36078ef76e0
| 0.645781 | 3.053571 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/serport/serport.vhd
| 1 | 11,456 |
-- $Id: serport.vhd 437 2011-12-09 19:38:07Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: serport
-- Description: serial port interface components
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-09 437 1.2.5 rename stat->moni port
-- 2011-10-23 419 1.2.4 remove serport_clkdiv_ consts;
-- 2011-10-22 417 1.2.3 add serport_xon(rx|tx) defs
-- 2011-10-14 416 1.2.2 add c_serport defs
-- 2010-12-26 348 1.2.1 add ABCLKDIV to serport_uart_rxtx_ab
-- 2010-04-10 276 1.2 add clock divider constant defs
-- 2007-10-22 88 1.1 renames (in prev revs); remove std_logic_unsigned
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package serport is
constant c_serport_xon : slv8 := "00010001"; -- char xon: ^Q = hex 11
constant c_serport_xoff : slv8 := "00010011"; -- char xoff ^S = hex 13
constant c_serport_xesc : slv8 := "00011011"; -- char xesc ^[ = ESC = hex 1B
component serport_uart_rxtx is -- serial port uart: rx+tx combo
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit; -- receiver active
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit -- transmit busy
);
end component;
component serport_uart_rx is -- serial port uart: receive part
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit -- receiver active
);
end component;
component serport_uart_tx is -- serial port uart: transmit part
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit -- transmit busy
);
end component;
component serport_uart_rxtx_ab is -- serial port uart: rx+tx+autobaud
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT: natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit; -- receiver active
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid
ABDONE : out slbit; -- autobaud resync done
ABCLKDIV : out slv(CDWIDTH-1 downto 0) -- autobaud clock divider setting
);
end component;
component serport_uart_autobaud is -- serial port uart: autobauder
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT: natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (uart view)
CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting
ACT : out slbit; -- active; if 1 clkdiv is invalid
DONE : out slbit -- resync done
);
end component;
component serport_xonrx is -- serial port: xon/xoff logic rx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_RXDATA : in slv8; -- uart data out
UART_RXVAL : in slbit; -- uart data valid
RXDATA : out slv8; -- user data out
RXVAL : out slbit; -- user data valid
RXHOLD : in slbit; -- user data hold
RXOVR : out slbit; -- user data overrun
TXOK : out slbit -- tx channel ok
);
end component;
component serport_xontx is -- serial port: xon/xoff logic tx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_TXDATA : out slv8; -- uart data in
UART_TXENA : out slbit; -- uart data enable
UART_TXBUSY : in slbit; -- uart data busy
TXDATA : in slv8; -- user data in
TXENA : in slbit; -- user data enable
TXBUSY : out slbit; -- user data busy
RXOK : in slbit; -- rx channel ok
TXOK : in slbit -- tx channel ok
);
end component;
type serport_moni_type is record -- serport monitor port
rxerr : slbit; -- receiver data error (frame error)
rxovr : slbit; -- receiver data overrun
rxact : slbit; -- receiver active
txact : slbit; -- transceiver active
abact : slbit; -- autobauder active;if 1 clkdiv invalid
abdone : slbit; -- autobauder resync done
abclkdiv : slv16; -- autobauder clock divider
rxok : slbit; -- rx channel ok
txok : slbit; -- tx channel ok
end record serport_moni_type;
constant serport_moni_init : serport_moni_type := (
'0','0', -- rxerr,rxovr
'0','0', -- rxact,txact
'0','0', -- abact,abdone
(others=>'0'), -- abclkdiv
'0','0' -- rxok,txok
);
component serport_1clock is -- serial port module, 1 clock domain
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXHOLD : in slbit; -- receiver data hold
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
MONI : out serport_moni_type; -- serport monitor port
RXSD : in slbit; -- receive serial data (uart view)
TXSD : out slbit; -- transmit serial data (uart view)
RXRTS_N : out slbit; -- receive rts (uart view, act.low)
TXCTS_N : in slbit -- transmit cts (uart view, act.low)
);
end component;
component serport_2clock is -- serial port module, 2 clock domain
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLKU : in slbit; -- clock (backend:user)
RESET : in slbit; -- reset
CLKS : in slbit; -- clock (frontend:serial)
CES_MSEC : in slbit; -- S|1 msec clock enable
ENAXON : in slbit; -- U|enable xon/xoff handling
ENAESC : in slbit; -- U|enable xon/xoff escaping
RXDATA : out slv8; -- U|receiver data out
RXVAL : out slbit; -- U|receiver data valid
RXHOLD : in slbit; -- U|receiver data hold
TXDATA : in slv8; -- U|transmit data in
TXENA : in slbit; -- U|transmit data enable
TXBUSY : out slbit; -- U|transmit busy
MONI : out serport_moni_type; -- U|serport monitor port
RXSD : in slbit; -- S|receive serial data (uart view)
TXSD : out slbit; -- S|transmit serial data (uart view)
RXRTS_N : out slbit; -- S|receive rts (uart view, act.low)
TXCTS_N : in slbit -- S|transmit cts (uart view, act.low)
);
end component;
end package serport;
|
gpl-2.0
|
e64c7f81c63e04eee3b5eddfb800f1b9
| 0.50934 | 4.56051 | false | false | false | false |
xylnao/w11a-extra
|
rtl/bplib/bpgen/bpgenlib.vhd
| 1 | 9,787 |
-- $Id: bpgenlib.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: bpliblib
-- Description: Generic Board/Part components
--
-- Dependencies: -
-- Tool versions: xst 12.1, 13.4; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-02-24 ??? 1.0.? made SWIDTH and LWIDTH generic
-- 2011-11-16 426 1.0.6 now numeric_std clean
-- 2011-10-10 413 1.0.5 add sn_humanio_demu
-- 2011-08-07 404 1.0.4 add RELAY generic for bp_rs232_2l4l_iob
-- 2011-08-06 403 1.0.3 add RESET port for bp_rs232_2l4l_iob
-- 2011-07-09 391 1.0.2 move in bp_rs232_2l4l_iob from s3boardlib
-- 2011-07-08 390 1.0.1 move in sn_(4x7segctl|humanio*) from s3boardlib
-- 2011-07-01 386 1.0 Initial version (with rs232_iob's and bp_swibtnled)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
package bpgenlib is
component bp_rs232_2line_iob is -- iob's for 2 line rs232 (RXD,TXD)
port (
CLK : in slbit; -- clock
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
I_RXD : in slbit; -- pad-i: receive data (board view)
O_TXD : out slbit -- pad-o: transmit data (board view)
);
end component;
component bp_rs232_4line_iob is -- iob's for 4 line rs232 (w/ RTS,CTS)
port (
CLK : in slbit; -- clock
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD : in slbit; -- pad-i: receive data (board view)
O_TXD : out slbit; -- pad-o: transmit data (board view)
I_CTS_N : in slbit; -- pad-i: clear to send (act. low)
O_RTS_N : out slbit -- pad-o: request to send (act. low)
);
end component;
component bp_rs232_2l4l_iob is -- iob's for dual 2l+4l rs232, w/ select
generic (
RELAY : boolean := false); -- add a relay stage towards IOB's
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
SEL : in slbit; -- select, '0' for port 0
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD0 : in slbit; -- pad-i: p0: receive data (board view)
O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view)
I_RXD1 : in slbit; -- pad-i: p1: receive data (board view)
O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view)
I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low)
O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low)
);
end component;
component bp_swibtnled is -- generic SWI, BTN and LED handling
generic (
SWIDTH : positive := 4; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 4; -- LED port width
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0) -- pad-o: leds
);
end component;
component bp_swibtnled_rbus is -- swi,btn,led handling /w rbus icept
generic (
SWIDTH : positive := 4; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 4; -- LED port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0) -- pad-o: leds
);
end component;
component sn_4x7segctl is -- Quad 7 segment display controller
generic (
CDWIDTH : positive := 6); -- clk divider width (must be >= 5)
port (
CLK : in slbit; -- clock
DIN : in slv16; -- data
DP : in slv4; -- decimal points
ANO_N : out slv4; -- anodes (act.low)
SEG_N : out slv8 -- segements (act.low)
);
end component;
component sn_humanio is -- human i/o handling: swi,btn,led,dsp
generic (
SWIDTH : positive := 8; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
);
end component;
component sn_humanio_demu is -- human i/o handling: swi,btn,led only
generic (
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv8; -- switch settings, debounced
BTN : out slv4; -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv6; -- pad-i: buttons
O_LED : out slv8 -- pad-o: leds
);
end component;
component sn_humanio_rbus is -- human i/o handling /w rbus intercept
generic (
SWIDTH : positive := 8; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
);
end component;
end package bpgenlib;
|
gpl-2.0
|
fbb4aab97cc7e0380b0d13fced10dfbc
| 0.522326 | 3.722708 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/genlib/gray2bin_gen.vhd
| 2 | 1,819 |
-- $Id: gray2bin_gen.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gray2bin_gen - syn
-- Description: Gray code to binary converter
--
-- Dependencies: -
-- Test bench: tb/tb_debounce_gen
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity gray2bin_gen is -- gray->bin converter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
DI : in slv(DWIDTH-1 downto 0); -- gray code input
DO : out slv(DWIDTH-1 downto 0) -- binary code output
);
end entity gray2bin_gen;
architecture syn of gray2bin_gen is
begin
proc_comb: process (DI)
variable ido : slv(DWIDTH-1 downto 0);
begin
ido := (others=>'0');
ido(DWIDTH-1) := DI(DWIDTH-1);
for i in DWIDTH-2 downto 0 loop
ido(i) := ido(i+1) xor DI(i);
end loop;
DO <= ido;
end process proc_comb;
end syn;
|
gpl-2.0
|
4e68d8b578721b21db804eab4882f25f
| 0.597031 | 3.719836 | false | false | false | false |
rogerioag/gcg
|
tutorial/ula/testbench/xor2_tb.vhd
| 1 | 1,860 |
-- Testebench gerado via script.
-- Data: Qua,20/07/2011-13:51:42
-- Autor: rogerio
-- Comentario: Teste da entidade xor2.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xor2_tb is
end xor2_tb;
architecture logica of xor2_tb is
-- Declaração do componente.
component xor2
port (a,b: in std_logic; y: out std_logic);
end component;
-- Especifica qual a entidade está vinculada com o componente.
for xor2_0: xor2 use entity work.xor2;
signal s_t_a, s_t_b, s_t_y: std_logic;
begin
-- Instanciação do Componente.
-- port map (<<p_in_1>> => <<s_t_in_1>>)
xor2_0: xor2 port map (a=>s_t_a,b=>s_t_b,y=>s_t_y);
-- Processo que faz o trabalho.
process
-- Um registro é criado com as entradas e saídas da entidade.
-- (<<entrada1>>, <<entradaN>>, <<saida1>>, <<saidaN>>)
type pattern_type is record
-- entradas.
vi_a, vi_b: std_logic;
-- saídas.
vo_y: std_logic;
end record;
-- Os padrões de entrada são aplicados (injetados) às entradas.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
(
('0', '0', '0'),
('0', '1', '1'),
('1', '0', '1'),
('1', '1', '0')
);
begin
-- Checagem de padrões.
for i in patterns'range loop
-- Injeta as entradas.
s_t_a <= patterns(i).vi_a;
s_t_b <= patterns(i).vi_b;
-- Aguarda os resultados.
wait for 1 ns;
-- Checa o resultado com a saída esperada no padrão.
assert s_t_y = patterns(i).vo_y report "Valor de s_t_y não confere com o resultado esperado." severity error;
end loop;
assert false report "Fim do teste." severity note;
-- Wait forever; Isto finaliza a simulação.
wait;
end process;
end logica;
|
gpl-3.0
|
9060bbd3a0b0b5105945d1e4909b08b8
| 0.598481 | 3.08194 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd
| 2 | 3,019 |
-- $Id: ram_2swsr_rfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2008- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_rfirst_gen - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- and 'read-before-write' semantics (as block RAM).
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2008-03-08 123 1.1 use now ram_2swsr_xfirst_gen_unisim
-- 2008-03-02 122 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
use work.memlib.all;
entity ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first
generic (
AWIDTH : positive := 13; -- address port width 11/9 or 13/8
DWIDTH : positive := 8); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_rfirst_gen;
architecture syn of ram_2swsr_rfirst_gen is
begin
UMEM: ram_2swsr_xfirst_gen_unisim
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH,
WRITE_MODE => "READ_FIRST")
port map (
CLKA => CLKA,
CLKB => CLKB,
ENA => ENA,
ENB => ENB,
WEA => WEA,
WEB => WEB,
ADDRA => ADDRA,
ADDRB => ADDRB,
DIA => DIA,
DIB => DIB,
DOA => DOA,
DOB => DOB
);
end syn;
|
gpl-2.0
|
0ad42905195f84b47cc49df28690ea39
| 0.542895 | 3.699755 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega3/MUX_rf.vhd
| 1 | 549 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_rf is
Port( Crs2 : in std_logic_vector(31 downto 0);
SEUimm13 : in std_logic_vector(31 downto 0);
i : in std_logic;
Oper2 : out std_logic_vector(31 downto 0)
);
end MUX_rf;
architecture Behavioral of MUX_rf is
begin
process (i, Crs2, SEUimm13) is
begin
case i is
when '0' => Oper2 <= Crs2;
when '1' => Oper2 <= SEUimm13;
when others => Oper2 <= (others => '1');
end case;
end process;
end Behavioral;
|
mit
|
f6209359204257798967c3b66f8b2835
| 0.575592 | 3.229412 | false | false | false | false |
os-cillation/easyfpga-soc
|
easy_cores/pwm/pwm8.vhd
| 1 | 3,837 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- 8-bit PWM using two-process design pattern
-- (pwm8.vhd)
--
-- @author Simon Gansen
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Type and component definition package
-------------------------------------------------------------------------------
package pwm8_comp is
type pwm8_in_type is record
duty_cycle : std_logic_vector(7 downto 0);
end record;
component pwm8
port (
clk : in std_logic;
rst : in std_logic;
d : in pwm8_in_type;
pwm : out std_logic
);
end component;
end package;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pwm8_comp.all;
-------------------------------------------------------------------------------
ENTITY pwm8 is
-------------------------------------------------------------------------------
port (
clk : in std_logic;
rst : in std_logic;
d : in pwm8_in_type;
pwm : out std_logic
);
end pwm8;
-------------------------------------------------------------------------------
ARCHITECTURE two_proc of pwm8 is
-------------------------------------------------------------------------------
type reg_type is record
pwm_cnt : unsigned(7 downto 0); -- pwm counter
end record;
signal reg_out, reg_in : reg_type;
begin
-------------------------------------------------------------------------------
COMBINATIONAL : process(d, reg_out)
-------------------------------------------------------------------------------
variable tmp_var : reg_type;
begin
tmp_var := reg_out; -- default assignments
---algorithm-------------------------------------------------------------
-- PWM: reset on overflow, increment otherwise
if (tmp_var.pwm_cnt = 2**8-1) then
tmp_var.pwm_cnt := (others => '0');
else
tmp_var.pwm_cnt := reg_out.pwm_cnt + 1;
end if;
-- compare and drive output
if (tmp_var.pwm_cnt >= unsigned(d.duty_cycle)) then
pwm <= '0';
else
pwm <= '1';
end if;
-------------------------------------------------------------------------
reg_in <= tmp_var; -- drive register inputs
end process COMBINATIONAL;
-------------------------------------------------------------------------------
REGISTERS : process(clk,rst)
-------------------------------------------------------------------------------
begin
if (rst = '1') then
reg_out.pwm_cnt <= (others => '0');
elsif rising_edge(clk) then
reg_out <= reg_in;
end if;
end process REGISTERS;
end two_proc;
|
gpl-3.0
|
5399d0f7bbbc5b93e8384e1c76c675a4
| 0.40761 | 5.136546 | false | false | false | false |
xylnao/w11a-extra
|
rtl/w11a/pdp11_sequencer.vhd
| 1 | 90,142 |
-- $Id: pdp11_sequencer.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_sequencer - syn
-- Description: pdp11: CPU sequencer
--
-- Dependencies: ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.4.2 now numeric_std clean
-- 2010-10-23 335 1.4.1 use ib_sel
-- 2010-10-17 333 1.4 use ibus V2 interface
-- 2010-09-18 300 1.3.2 rename (adlm)box->(oalm)unit
-- 2010-06-20 307 1.3.1 rename cpacc to cacc in vm_cntl_type
-- 2010-06-13 305 1.3 remove CPDIN_WE, CPDOUT_WE out ports; set
-- CNTL.cpdout_we instead of CPDOUT_WE
-- 2010-06-12 304 1.2.8 signal cpuwait when spinning in s_op_wait
-- 2009-05-30 220 1.2.7 final removal of snoopers (were already commented)
-- 2009-05-09 213 1.2.6 BUGFIX: use is_dstkstack1246, stklim for mode=6
-- 2009-05-02 211 1.2.5 BUGFIX: 11/70 spl semantics again in kernel mode
-- 2009-04-26 209 1.2.4 BUGFIX: give interrupts priority over trap handling
-- 2008-12-14 177 1.2.3 BUGFIX: use is_dstkstack124, fix stklim check bug
-- 2008-12-13 176 1.2.2 BUGFIX: use is_pci in s_dstw_inc if DSTDEF='1'
-- 2008-11-30 174 1.2.1 BUGFIX: add updt_dstadsrc; prevent stale DSRC
-- 2008-08-22 161 1.2 rename ubf_ -> ibf_; use iblib
-- 2008-05-03 143 1.1.9 rename _cpursta->_cpurust; cp reset sets now
-- c_cpurust_reset; proper c_cpurust_vfail handling
-- 2008-04-27 140 1.1.8 BUGFIX: halt cpu in case of a vector fetch error
-- use cpursta to encode why cpu halts, remove cpufail
-- 2008-04-27 139 1.1.7 BUGFIX: correct bytop handling for address fetches;
-- BUGFIX: redo mtp flow; add fork_dsta fork and ddst
-- reload in s_opa_mtp_pop_w;
-- 2008-04-19 137 1.1.6 BUGFIX: fix loop state in s_rti_getpc_w
-- 2008-03-30 131 1.1.5 BUGFIX: inc/dec by 2 for byte mode -(sp),(sp)+
-- inc/dec by 2 for @(R)+ and @-(R) also for bytop's
-- 2008-03-02 121 1.1.4 remove snoopers; add waitsusp, redo WAIT handling
-- 2008-02-24 119 1.1.3 add lah,rps,wps command; revamp cp memory access
-- change WAIT logic, now also bails out on cp command
-- 2008-01-20 112 1.1.2 rename PRESET->BRESET
-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_sequencer is -- CPU sequencer
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
PSW : in psw_type; -- processor status
PC : in slv16; -- program counter
IREG : in slv16; -- IREG
ID_STAT : in decode_stat_type; -- instr. decoder status
DP_STAT : in dpath_stat_type; -- data path status
CP_CNTL : in cp_cntl_type; -- console port control
VM_STAT : in vm_stat_type; -- virtual memory status port
INT_PRI : in slv3; -- interrupt priority
INT_VECT : in slv9_2; -- interrupt vector
CRESET : out slbit; -- console reset
BRESET : out slbit; -- ibus reset
MMU_MONI : out mmu_moni_type; -- mmu monitor port
DP_CNTL : out dpath_cntl_type; -- data path control
VM_CNTL : out vm_cntl_type; -- virtual memory control port
CP_STAT : out cp_stat_type; -- console port status
INT_ACK : out slbit; -- interrupt acknowledge
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_sequencer;
architecture syn of pdp11_sequencer is
constant ibaddr_cpuerr : slv16 := slv(to_unsigned(8#177766#,16));
constant cpuerr_ibf_illhlt : integer := 7;
constant cpuerr_ibf_adderr : integer := 6;
constant cpuerr_ibf_nxm : integer := 5;
constant cpuerr_ibf_iobto : integer := 4;
constant cpuerr_ibf_ysv : integer := 3;
constant cpuerr_ibf_rsv : integer := 2;
type state_type is (
s_idle,
s_cp_regread,
s_cp_rps,
s_cp_memr_w,
s_cp_memw_w,
s_ifetch,
s_ifetch_w,
s_idecode,
s_srcr_def,
s_srcr_def_w,
s_srcr_inc,
s_srcr_inc_w,
s_srcr_dec,
s_srcr_dec1,
s_srcr_ind,
s_srcr_ind1_w,
s_srcr_ind2,
s_srcr_ind2_w,
s_dstr_def,
s_dstr_def_w,
s_dstr_inc,
s_dstr_inc_w,
s_dstr_dec,
s_dstr_dec1,
s_dstr_ind,
s_dstr_ind1_w,
s_dstr_ind2,
s_dstr_ind2_w,
s_dstw_def,
s_dstw_def_w,
s_dstw_inc,
s_dstw_inc_w,
s_dstw_incdef_w,
s_dstw_dec,
s_dstw_dec1,
s_dstw_ind,
s_dstw_ind_w,
s_dstw_def246,
s_dsta_inc,
s_dsta_incdef_w,
s_dsta_dec,
s_dsta_dec1,
s_dsta_ind,
s_dsta_ind_w,
s_op_halt,
s_op_wait,
s_op_trap,
s_op_reset,
s_op_rts,
s_op_rts_pop,
s_op_rts_pop_w,
s_op_spl,
s_op_mcc,
s_op_br,
s_op_mark,
s_op_mark1,
s_op_mark_pop,
s_op_mark_pop_w,
s_op_sob,
s_op_sob1,
s_opg_gen,
s_opg_gen_rmw_w,
s_opg_mul,
s_opg_mul1,
s_opg_div,
s_opg_div_cn,
s_opg_div_cr,
s_opg_div_sq,
s_opg_div_sr,
s_opg_div_zero,
s_opg_ash,
s_opg_ash_cn,
s_opg_ashc,
s_opg_ashc_cn,
s_opg_ashc_wl,
s_opa_jsr,
s_opa_jsr1,
s_opa_jsr_push,
s_opa_jsr_push_w,
s_opa_jsr2,
s_opa_jmp,
s_opa_mtp,
s_opa_mtp_pop_w,
s_opa_mtp_reg,
s_opa_mtp_mem,
s_opa_mtp_mem_w,
s_opa_mfp_reg,
s_opa_mfp_mem,
s_opa_mfp_mem_w,
s_opa_mfp_dec,
s_opa_mfp_push,
s_opa_mfp_push_w,
s_trap_4,
s_trap_10,
s_trap_disp,
s_int_ext,
s_int_getpc,
s_int_getpc_w,
s_int_getps,
s_int_getps_w,
s_int_getsp,
s_int_decsp,
s_int_pushps,
s_int_pushps_w,
s_int_pushpc,
s_int_pushpc_w,
s_rti_getpc,
s_rti_getpc_w,
s_rti_getps,
s_rti_getps_w,
s_rti_newpc,
s_vmerr,
s_cpufail
);
signal R_STATE : state_type := s_idle; -- state register
signal N_STATE : state_type := s_idle;
signal R_STATUS : cpustat_type := cpustat_init;
signal N_STATUS : cpustat_type := cpustat_init;
signal R_CPUERR : cpuerr_type := cpuerr_init;
signal N_CPUERR : cpuerr_type := cpuerr_init;
signal R_IDSTAT : decode_stat_type := decode_stat_init;
signal N_IDSTAT : decode_stat_type := decode_stat_init;
signal R_VMSTAT : vm_stat_type := vm_stat_init;
signal IBSEL_CPUERR : slbit := '0';
begin
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_cpuerr)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_CPUERR
);
proc_ibres : process (IBSEL_CPUERR, IB_MREQ, R_CPUERR)
variable idout : slv16 := (others=>'0');
begin
idout := (others=>'0');
if IBSEL_CPUERR = '1' then
idout(cpuerr_ibf_illhlt) := R_CPUERR.illhlt;
idout(cpuerr_ibf_adderr) := R_CPUERR.adderr;
idout(cpuerr_ibf_nxm) := R_CPUERR.nxm;
idout(cpuerr_ibf_iobto) := R_CPUERR.iobto;
idout(cpuerr_ibf_ysv) := R_CPUERR.ysv;
idout(cpuerr_ibf_rsv) := R_CPUERR.rsv;
end if;
IB_SRES.dout <= idout;
IB_SRES.ack <= IBSEL_CPUERR and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES.busy <= '0';
end process proc_ibres;
proc_status: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_STATUS <= cpustat_init;
R_CPUERR <= cpuerr_init;
R_IDSTAT <= decode_stat_init;
R_VMSTAT <= vm_stat_init;
else
R_STATUS <= N_STATUS;
R_CPUERR <= N_CPUERR;
R_IDSTAT <= N_IDSTAT;
R_VMSTAT <= VM_STAT;
end if;
end if;
end process proc_status;
proc_state: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_STATE <= s_idle;
else
R_STATE <= N_STATE;
end if;
end if;
end process proc_state;
proc_next: process (R_STATE, R_STATUS, PSW, PC, CP_CNTL,
ID_STAT, R_IDSTAT, IREG, VM_STAT, DP_STAT,
R_CPUERR, R_VMSTAT, IB_MREQ, IBSEL_CPUERR,
INT_PRI, INT_VECT)
variable nstate : state_type;
variable nstatus : cpustat_type := cpustat_init;
variable ncpuerr : cpuerr_type := cpuerr_init;
variable ncreset : slbit := '0';
variable nbreset : slbit := '0';
variable nintack : slbit := '0';
variable ndpcntl : dpath_cntl_type := dpath_cntl_init;
variable nvmcntl : vm_cntl_type := vm_cntl_init;
variable nidstat : decode_stat_type := decode_stat_init;
variable nmmumoni : mmu_moni_type := mmu_moni_init;
variable imemok : boolean;
variable bytop : slbit := '0'; -- local bytop access flag
variable macc : slbit := '0'; -- local modify access flag
variable lvector : slv9_2 := (others=>'0'); -- local trap/interrupt vector
variable brcode : slv4 := (others=>'0'); -- reduced br opcode (15,10-8)
variable brcond : slbit := '0'; -- br condition value
variable is_kmode : slbit := '0'; -- cmode is kernel mode
variable is_dstkstack1246 : slbit := '0'; -- dest is k-stack & mode= 1,2,4,6
variable int_pending : slbit := '0'; -- an interrupt is pending
alias SRCMOD : slv2 is IREG(11 downto 10); -- src register mode high
alias SRCDEF : slbit is IREG(9); -- src register mode defered
alias SRCREG : slv3 is IREG(8 downto 6); -- src register number
alias DSTMODF : slv3 is IREG(5 downto 3); -- dst register full mode
alias DSTMOD : slv2 is IREG(5 downto 4); -- dst register mode high
alias DSTDEF : slbit is IREG(3); -- dst register mode defered
alias DSTREG : slv3 is IREG(2 downto 0); -- dst register number
procedure do_memread_i(nstate : inout state_type;
ndpcntl : inout dpath_cntl_type;
nvmcntl : inout vm_cntl_type;
wstate : in state_type) is
begin
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
nvmcntl.dspace := '0';
nvmcntl.req := '1';
ndpcntl.gpr_pcinc := '1'; -- (pc)++
nstate := wstate;
end procedure do_memread_i;
procedure do_memread_d(nstate : inout state_type;
nvmcntl : inout vm_cntl_type;
wstate : in state_type;
bytop : in slbit := '0';
macc : in slbit := '0';
is_pci : in slbit := '0') is
begin
nvmcntl.dspace := not is_pci; -- ispace if pc immediate modes
-- bytop := R_IDSTAT.is_bytop and not is_addr;
nvmcntl.bytop := bytop;
nvmcntl.macc := macc;
nvmcntl.req := '1';
nstate := wstate;
end procedure do_memread_d;
procedure do_memread_srcinc(nstate : inout state_type;
ndpcntl : inout dpath_cntl_type;
nvmcntl : inout vm_cntl_type;
wstate : in state_type;
nmmumoni : inout mmu_moni_type;
updt_sp : in slbit := '0') is
begin
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010"; -- OUNIT const=2
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
if updt_sp = '1' then
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
ndpcntl.gpr_adst := c_gpr_sp; -- update SP too
ndpcntl.gpr_we := '1';
end if;
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.dspace := '1';
nvmcntl.req := '1';
nstate := wstate;
end procedure do_memread_srcinc;
procedure do_memwrite(nstate : inout state_type;
nvmcntl : inout vm_cntl_type;
wstate : in state_type;
macc : in slbit :='0') is
begin
nvmcntl.dspace := '1';
nvmcntl.bytop := R_IDSTAT.is_bytop;
nvmcntl.wacc := '1';
nvmcntl.macc := macc;
nvmcntl.req := '1';
nstate := wstate;
end procedure do_memwrite;
procedure do_memcheck(nstate : inout state_type;
nstatus : inout cpustat_type;
mok : out boolean) is
begin
mok := false;
if VM_STAT.ack = '1' then
mok := true;
nstatus.trap_mmu := VM_STAT.trap_mmu;
if R_CPUERR.ysv = '0' then -- ysv trap when cpuerr not yet set
nstatus.trap_ysv := VM_STAT.trap_ysv;
end if;
elsif VM_STAT.err='1' or VM_STAT.fail='1' then
nstate := s_vmerr;
end if;
end procedure do_memcheck;
procedure do_const_opsize(ndpcntl : inout dpath_cntl_type;
bytop : in slbit;
isdef : in slbit;
regnum : in slv3) is
begin
if bytop='0' or isdef='1' or
regnum=c_gpr_pc or regnum=c_gpr_sp then
ndpcntl.ounit_const := "000000010";
else
ndpcntl.ounit_const := "000000001";
end if;
end procedure do_const_opsize;
procedure do_fork_dstr(nstate : inout state_type;
idstat : in decode_stat_type) is
begin
case idstat.fork_dstr is
when c_fork_dstr_def => nstate := s_dstr_def;
when c_fork_dstr_inc => nstate := s_dstr_inc;
when c_fork_dstr_dec => nstate := s_dstr_dec;
when c_fork_dstr_ind => nstate := s_dstr_ind;
when others => nstate := s_cpufail;
end case;
end procedure do_fork_dstr;
procedure do_fork_opg(nstate : inout state_type;
idstat : in decode_stat_type) is
begin
case idstat.fork_opg is
when c_fork_opg_gen => nstate := s_opg_gen;
when c_fork_opg_wdef => nstate := s_dstw_def;
when c_fork_opg_winc => nstate := s_dstw_inc;
when c_fork_opg_wdec => nstate := s_dstw_dec;
when c_fork_opg_wind => nstate := s_dstw_ind;
when c_fork_opg_mul => nstate := s_opg_mul;
when c_fork_opg_div => nstate := s_opg_div;
when c_fork_opg_ash => nstate := s_opg_ash;
when c_fork_opg_ashc => nstate := s_opg_ashc;
when others => nstate := s_cpufail;
end case;
end procedure do_fork_opg;
procedure do_fork_opa(nstate : inout state_type;
idstat : in decode_stat_type) is
begin
case idstat.fork_opa is
when c_fork_opa_jmp => nstate := s_opa_jmp;
when c_fork_opa_jsr => nstate := s_opa_jsr;
when c_fork_opa_mtp => nstate := s_opa_mtp_mem;
when c_fork_opa_mfp_reg => nstate := s_opa_mfp_reg;
when c_fork_opa_mfp_mem => nstate := s_opa_mfp_mem;
when others => nstate := s_cpufail;
end case;
end procedure do_fork_opa;
procedure do_fork_next(nstate : inout state_type;
nstatus : inout cpustat_type;
nmmumoni : inout mmu_moni_type) is
begin
nmmumoni.idone := '1';
if unsigned(INT_PRI) > unsigned(PSW.pri) then
nstate := s_idle;
elsif R_STATUS.trap_mmu='1' or nstatus.trap_mmu='1' or
R_STATUS.trap_ysv='1' or nstatus.trap_ysv='1' or
PSW.tflag='1' then
nstate := s_trap_disp;
elsif R_STATUS.cpugo='1' and not R_STATUS.cmdbusy='1' then
nstate := s_ifetch;
else
nstate := s_idle;
end if;
end procedure do_fork_next;
procedure do_fork_next_pref(nstate : inout state_type;
nstatus : inout cpustat_type;
ndpcntl : inout dpath_cntl_type;
nvmcntl : inout vm_cntl_type;
nmmumoni : inout mmu_moni_type) is
begin
nmmumoni.idone := '1';
if unsigned(INT_PRI) > unsigned(PSW.pri) then
nstate := s_idle;
elsif R_STATUS.trap_mmu='1' or nstatus.trap_mmu='1' or
R_STATUS.trap_ysv='1' or nstatus.trap_ysv='1' or
PSW.tflag='1' then
nstate := s_trap_disp;
elsif R_STATUS.cpugo='1' and not R_STATUS.cmdbusy='1' then
nvmcntl.req := '1';
ndpcntl.gpr_pcinc := '1';
nmmumoni.istart := '1';
nstate := s_ifetch_w;
else
nstate := s_idle;
end if;
end procedure do_fork_next_pref;
procedure do_start_int(nstate : inout state_type;
ndpcntl : inout dpath_cntl_type;
vector : in slv9_2) is
begin
ndpcntl.dtmp_sel := c_dpath_dtmp_psw; -- DTMP = PSW
ndpcntl.dtmp_we := '1';
ndpcntl.ounit_azero := '1'; -- OUNIT A = 0
ndpcntl.ounit_const := vector & "00"; -- vector
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const(vector)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- DSRC = vector
nstate := s_int_getpc;
end procedure do_start_int;
begin
nstate := R_STATE;
nstatus := R_STATUS;
ncpuerr := R_CPUERR;
nstatus.cpuwait := '0'; -- wait flag 0 unless set in s_op_wait
ncreset := '0';
nbreset := '0';
nintack := '0';
nidstat := R_IDSTAT;
if IBSEL_CPUERR='1' and IB_MREQ.we='1' then -- write to CPUERR clears it !
ncpuerr := cpuerr_init;
end if;
int_pending := '0';
if unsigned(INT_PRI) > unsigned(PSW.pri) then
int_pending := '1';
end if;
imemok := false;
nmmumoni := mmu_moni_init;
nmmumoni.pc := PC;
macc := '0';
bytop := '0';
brcode := IREG(15) & IREG(10 downto 8);
brcond := '1';
is_kmode := '0';
is_dstkstack1246 := '0';
if PSW.cmode = c_psw_kmode then
is_kmode := '1';
if DSTREG = c_gpr_sp and
(DSTMODF="001" or DSTMODF="010" or
DSTMODF="100" or DSTMODF="110") then
is_dstkstack1246 := '1';
end if;
end if;
lvector := (others=>'0');
nvmcntl := vm_cntl_init;
nvmcntl.dspace := '1'; -- DEFAULT
nvmcntl.mode := PSW.cmode; -- DEFAULT
nvmcntl.intrsv := R_STATUS.do_intrsv; -- DEFAULT
ndpcntl := dpath_cntl_init;
ndpcntl.gpr_asrc := SRCREG; -- DEFAULT
ndpcntl.gpr_adst := DSTREG; -- DEFAULT
ndpcntl.gpr_mode := PSW.cmode; -- DEFAULT
ndpcntl.gpr_rset := PSW.rset; -- DEFAULT
ndpcntl.gpr_we := '0'; -- DEFAULT
ndpcntl.gpr_bytop := '0'; -- DEFAULT
ndpcntl.gpr_pcinc := '0'; -- DEFAULT
ndpcntl.psr_ccwe := '0'; -- DEFAULT
ndpcntl.psr_we := '0'; -- DEFAULT
ndpcntl.psr_func := "000"; -- DEFAULT
ndpcntl.dsrc_sel := c_dpath_dsrc_src;
ndpcntl.dsrc_we := '0';
ndpcntl.ddst_sel := c_dpath_ddst_dst;
ndpcntl.ddst_we := '0';
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
ndpcntl.dtmp_we := '0';
ndpcntl.ounit_asel := c_ounit_asel_ddst;
ndpcntl.ounit_azero := '0'; -- DEFAULT
ndpcntl.ounit_const := (others=>'0'); -- DEFAULT
ndpcntl.ounit_bsel := c_ounit_bsel_const;
ndpcntl.ounit_opsub := '0'; -- DEFAULT
ndpcntl.aunit_srcmod := R_IDSTAT.aunit_srcmod; -- STATIC
ndpcntl.aunit_dstmod := R_IDSTAT.aunit_dstmod; -- STATIC
ndpcntl.aunit_cimod := R_IDSTAT.aunit_cimod; -- STATIC
ndpcntl.aunit_cc1op := R_IDSTAT.aunit_cc1op; -- STATIC
ndpcntl.aunit_ccmode := R_IDSTAT.aunit_ccmode; -- STATIC
ndpcntl.aunit_bytop := R_IDSTAT.is_bytop; -- STATIC
ndpcntl.lunit_func := R_IDSTAT.lunit_func; -- STATIC
ndpcntl.lunit_bytop := R_IDSTAT.is_bytop; -- STATIC
ndpcntl.munit_func := R_IDSTAT.munit_func; -- STATIC
ndpcntl.ireg_we := '0';
ndpcntl.cres_sel := R_IDSTAT.res_sel; -- DEFAULT
ndpcntl.dres_sel := c_dpath_res_ounit;
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc;
if CP_CNTL.req='1' and R_STATUS.cmdbusy='0' then
nstatus.cmdbusy := '1';
nstatus.cpfunc := CP_CNTL.func;
nstatus.cprnum := CP_CNTL.rnum;
end if;
if R_STATUS.cmdack = '1' then
nstatus.cmdack := '0';
nstatus.cmderr := '0';
nstatus.cmdmerr := '0';
end if;
case R_STATE is
-- idle and command port states ---------------------------------------------
-- Note: s_idle was entered from suspended WAIT when waitsusp='1'
-- --> all exits must check this and either return to s_op_wait
-- or abort the WAIT and set waitsusp='0'
when s_idle =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST (do mux early)
nstatus.cpustep := '0';
if R_STATUS.cmdbusy = '1' then
case R_STATUS.cpfunc is
when c_cpfunc_noop => -- noop : no operation --------
nstatus.cmdack := '1';
nstate := s_idle;
when c_cpfunc_sta => -- sta : cpu start -----------
ncreset := '1';
nstatus.cmdack := '1';
nstatus.cpugo := '1';
nstatus.cpuhalt := '0';
nstatus.cpurust := c_cpurust_runs;
nstatus.waitsusp := '0';
nstate := s_idle;
when c_cpfunc_sto => -- sto : cpu stop ------------
nstatus.cmdack := '1';
nstatus.cpugo := '0';
nstatus.cpurust := c_cpurust_stop;
nstatus.waitsusp := '0';
nstate := s_idle;
when c_cpfunc_cont => -- cont : cpu continue --------
nstatus.cmdack := '1';
nstatus.cpugo := '1';
nstatus.cpuhalt := '0';
nstatus.cpurust := c_cpurust_runs;
nstatus.waitsusp := '0';
nstate := s_idle;
when c_cpfunc_step => -- step : cpu step ------------
nstatus.cmdack := '1';
nstatus.cpustep := '1';
nstatus.cpuhalt := '0';
nstatus.cpurust := c_cpurust_step;
nstatus.waitsusp := '0';
if int_pending = '1' then
nintack := '1';
nstatus.intvect := INT_VECT;
nstate := s_int_ext;
else
nstate := s_ifetch;
end if;
when c_cpfunc_rst => -- rst : cpu reset (soft) ----
ncreset := '1';
nstatus.cmdack := '1';
nstatus.cpugo := '0';
nstatus.cpuhalt := '0';
nstatus.cpurust := c_cpurust_reset;
nstatus.waitsusp := '0';
nstate := s_idle;
when c_cpfunc_rreg => -- rreg : read register ------
ndpcntl.gpr_adst := R_STATUS.cprnum;
ndpcntl.ddst_sel := c_dpath_ddst_dst;
ndpcntl.ddst_we := '1';
nstate := s_cp_regread;
when c_cpfunc_wreg => -- wreg : write register -----
ndpcntl.dres_sel := c_dpath_res_cpdin; -- DRES = CPDIN
ndpcntl.gpr_adst := R_STATUS.cprnum;
ndpcntl.gpr_we := '1';
nstatus.cmdack := '1';
nstate := s_idle;
when c_cpfunc_rpsw => -- rpsw : read psw -----------
ndpcntl.dtmp_sel := c_dpath_dtmp_psw; -- DTMP = PSW
ndpcntl.dtmp_we := '1';
nstate := s_cp_rps;
when c_cpfunc_wpsw => -- wpsw : write psw ----------
ndpcntl.dres_sel := c_dpath_res_cpdin; -- DRES = CPDIN
ndpcntl.psr_func := c_psr_func_wall; -- write all fields
ndpcntl.psr_we := '1'; -- load new PS
nstatus.cmdack := '1';
nstate := s_idle;
when c_cpfunc_rmem => -- rmem : read memory --------
nvmcntl.cacc := '1';
nvmcntl.req := '1';
nstate := s_cp_memr_w;
when c_cpfunc_wmem => -- wmem : write memory -------
ndpcntl.dres_sel := c_dpath_res_cpdin; -- DRES = CPDIN
nvmcntl.wacc := '1'; -- write mem
nvmcntl.cacc := '1';
nvmcntl.req := '1';
nstate := s_cp_memw_w;
when others =>
nstatus.cmdack := '1';
nstatus.cmderr := '1';
nstate := s_idle;
end case;
elsif R_STATUS.waitsusp = '1' then
nstatus.waitsusp := '0';
nstate := s_op_wait;
elsif R_STATUS.cpugo = '1' then
if int_pending = '1' then
nintack := '1';
nstatus.intvect := INT_VECT;
nstate := s_int_ext;
else
nstate := s_ifetch;
end if;
end if;
when s_cp_regread =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
nstatus.cmdack := '1';
nstate := s_idle;
when s_cp_rps =>
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
nstatus.cmdack := '1';
nstate := s_idle;
when s_cp_memr_w =>
nstate := s_cp_memr_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
if (VM_STAT.ack or VM_STAT.err or VM_STAT.fail)='1' then
nstatus.cmdack := '1';
nstatus.trap_ysv := '0'; -- suppress traps on console
nstatus.trap_mmu := '0';
nstatus.cmdmerr := VM_STAT.err or VM_STAT.fail;
nstate := s_idle;
end if;
when s_cp_memw_w =>
nstate := s_cp_memw_w;
if (VM_STAT.ack or VM_STAT.err or VM_STAT.fail)='1' then
nstatus.cmdack := '1';
nstatus.trap_ysv := '0'; -- suppress traps on console
nstatus.trap_mmu := '0';
nstatus.cmdmerr := VM_STAT.err or VM_STAT.fail;
nstate := s_idle;
end if;
-- instruction fetch and decode ---------------------------------------------
when s_ifetch =>
nmmumoni.istart := '1'; -- do here; memread_i inc PC !
do_memread_i(nstate, ndpcntl, nvmcntl, s_ifetch_w);
when s_ifetch_w =>
nstate := s_ifetch_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ireg_we := '1';
nstate := s_idecode;
end if;
when s_idecode =>
nidstat := ID_STAT; -- register decode status
if ID_STAT.force_srcsp = '1' then
ndpcntl.gpr_asrc := c_gpr_sp;
end if;
ndpcntl.dsrc_sel := c_dpath_dsrc_src;
ndpcntl.dsrc_we := '1';
ndpcntl.ddst_sel := c_dpath_ddst_dst;
ndpcntl.ddst_we := '1';
nvmcntl.dspace := '0';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
if ID_STAT.do_pref_dec='1' and PSW.tflag='0' and int_pending='0' and
R_STATUS.cpugo='1' and not R_STATUS.cmdbusy='1'
then
nvmcntl.req := '1';
ndpcntl.gpr_pcinc := '1'; -- (pc)++
nmmumoni.istart := '1';
nstatus.prefdone := '1';
end if;
if ID_STAT.do_fork_op = '1' then
case ID_STAT.fork_op is
when c_fork_op_halt => nstate := s_op_halt;
when c_fork_op_wait => nstate := s_op_wait;
when c_fork_op_rtti => nstate := s_rti_getpc;
when c_fork_op_trap => nstate := s_op_trap;
when c_fork_op_reset=> nstate := s_op_reset;
when c_fork_op_rts => nstate := s_op_rts;
when c_fork_op_spl => nstate := s_op_spl;
when c_fork_op_mcc => nstate := s_op_mcc;
when c_fork_op_br => nstate := s_op_br;
when c_fork_op_mark => nstate := s_op_mark;
when c_fork_op_sob => nstate := s_op_sob;
when c_fork_op_mtp => nstate := s_opa_mtp;
when others => nstate := s_cpufail;
end case;
elsif ID_STAT.do_fork_srcr = '1' then
case ID_STAT.fork_srcr is
when c_fork_srcr_def => nstate := s_srcr_def;
when c_fork_srcr_inc => nstate := s_srcr_inc;
when c_fork_srcr_dec => nstate := s_srcr_dec;
when c_fork_srcr_ind => nstate := s_srcr_ind;
when others => nstate := s_cpufail;
end case;
elsif ID_STAT.do_fork_dstr = '1' then
do_fork_dstr(nstate, ID_STAT);
elsif ID_STAT.do_fork_dsta = '1' then
case ID_STAT.fork_dsta is -- 2nd dsta fork in s_opa_mtp_pop_w
when c_fork_dsta_def => do_fork_opa(nstate, ID_STAT);
when c_fork_dsta_inc => nstate := s_dsta_inc;
when c_fork_dsta_dec => nstate := s_dsta_dec;
when c_fork_dsta_ind => nstate := s_dsta_ind;
when others => nstate := s_cpufail;
end case;
elsif ID_STAT.do_fork_opg = '1' then
do_fork_opg(nstate, ID_STAT);
elsif ID_STAT.is_res = '1' then
nstate := s_trap_10; -- do trap 10;
else
nstate := s_cpufail; -- catch mistakes here...
end if;
-- source read states -------------------------------------------------------
-- flows:
-- 1 (r) s_srcr_def req (r)
-- s_srcr_def_w get (r)
-- -> do_fork_dstr or do_fork_opg
--
-- 2 (r)+ s_srcr_inc req (r); r+=s
-- s_srcr_inc_w get (r)
-- -> do_fork_dstr or do_fork_opg
--
-- 3 @(r)+ s_srcr_inc req (r); r+=s
-- s_srcr_inc_w get (r)
-- s_srcr_def req @(r)
-- s_srcr_def_w get @(r)
-- -> do_fork_dstr or do_fork_opg
--
-- 4 -(r) s_srcr_dec r-=s
-- s_srcr_dec1 req (r)
-- s_srcr_inc_w get (r)
-- -> do_fork_dstr or do_fork_opg
--
-- 5 @-(r) s_srcr_dec r-=s
-- s_srcr_dec1 req (r)
-- s_srcr_inc_w get (r)
-- s_srcr_def req @(r)
-- s_srcr_def_w get @(r)
-- -> do_fork_dstr or do_fork_opg
--
-- 6 n(r) s_srcr_ind req n
-- s_srcr_ind1_w get n; ea=r+n
-- s_srcr_ind2 req n(r)
-- s_srcr_ind2_w get n(r)
-- -> do_fork_dstr or do_fork_opg
--
-- 7 @n(r) s_srcr_ind req n
-- s_srcr_ind1_w get n; ea=r+n
-- s_srcr_ind2 req n(r)
-- s_srcr_ind2_w get n(r)
-- s_srcr_def req @n(r)
-- s_srcr_def_w get @n(r)
-- -> do_fork_dstr or do_fork_opg
when s_srcr_def =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
do_memread_d(nstate, nvmcntl, s_srcr_def_w,
bytop=>R_IDSTAT.is_bytop,
is_pci=>R_IDSTAT.is_srcpcmode1);
when s_srcr_def_w =>
nstate := s_srcr_def_w;
do_memcheck(nstate, nstatus, imemok);
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
if R_IDSTAT.do_fork_dstr = '1' then
do_fork_dstr(nstate, R_IDSTAT);
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
when s_srcr_inc =>
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, SRCDEF, SRCREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES (for if)
if DSTREG = SRCREG then -- prevent stale DDST copy
ndpcntl.ddst_we := '1'; -- update DDST
end if;
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
bytop := R_IDSTAT.is_bytop and not SRCDEF;
do_memread_d(nstate, nvmcntl, s_srcr_inc_w,
bytop=>bytop, is_pci=>R_IDSTAT.is_srcpc);
when s_srcr_inc_w =>
nstate := s_srcr_inc_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
if SRCDEF = '1' then
nstate := s_srcr_def;
else
if R_IDSTAT.do_fork_dstr = '1' then
do_fork_dstr(nstate, R_IDSTAT);
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
end if;
when s_srcr_dec =>
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, SRCDEF, SRCREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gpr_adst := SRCREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES (for if)
if DSTREG = SRCREG then -- prevent stale DDST copy
ndpcntl.ddst_we := '1'; -- update DDST
end if;
nstate := s_srcr_dec1;
when s_srcr_dec1 =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
bytop := R_IDSTAT.is_bytop and not SRCDEF;
do_memread_d(nstate, nvmcntl, s_srcr_inc_w, bytop=>bytop);
when s_srcr_ind =>
do_memread_i(nstate, ndpcntl, nvmcntl, s_srcr_ind1_w);
when s_srcr_ind1_w =>
nstate := s_srcr_ind1_w;
if R_IDSTAT.is_srcpc = '0' then
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A = DSRC
else
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout; -- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = R(DST)
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.ddst_we := '1'; -- update DDST (to reload PC)
nstate := s_srcr_ind2;
end if;
when s_srcr_ind2 =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
bytop := R_IDSTAT.is_bytop and not SRCDEF;
do_memread_d(nstate, nvmcntl, s_srcr_ind2_w, bytop=>bytop);
when s_srcr_ind2_w =>
nstate := s_srcr_ind2_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
if SRCDEF = '1' then
nstate := s_srcr_def;
else
if R_IDSTAT.do_fork_dstr = '1' then
do_fork_dstr(nstate, R_IDSTAT);
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
end if;
-- destination read states --------------------------------------------------
-- flows:
-- 1 (r) s_dstr_def req (r) (rmw if rmw op)
-- s_dstr_def_w get (r)
-- -> do_fork_opg
--
-- 2 (r)+ s_dstr_inc req (r); r+=s (rmw if rmw op)
-- s_dstr_inc_w get (r)
-- -> do_fork_opg
--
-- 3 @(r)+ s_dstr_inc req (r); r+=s
-- s_dstr_inc_w get (r)
-- s_dstr_def req @(r) (rmw if rmw op)
-- s_dstr_def_w get @(r)
-- -> do_fork_opg
--
-- 4 -(r) s_dstr_dec r-=s
-- s_dstr_dec1 req (r) (rmw if rmw op)
-- s_dstr_inc_w get (r)
-- -> do_fork_opg
--
-- 5 @-(r) s_dstr_dec r-=s
-- s_dstr_dec1 req (r)
-- s_dstr_inc_w get (r)
-- s_dstr_def req @(r) (rmw if rmw op)
-- s_dstr_def_w get @(r)
-- -> do_fork_opg
--
-- 6 n(r) s_dstr_ind req n
-- s_dstr_ind1_w get n; ea=r+n
-- s_dstr_ind2 req n(r) (rmw if rmw op)
-- s_dstr_ind2_w get n(r)
-- -> do_fork_opg
--
-- 7 @n(r) s_dstr_ind req n
-- s_dstr_ind1_w get n; ea=r+n
-- s_dstr_ind2 req n(r)
-- s_dstr_ind2_w get n(r)
-- s_dstr_def req @n(r) (rmw if rmw op)
-- s_dstr_def_w get @n(r)
-- -> do_fork_opg
when s_dstr_def =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
do_memread_d(nstate, nvmcntl, s_dstr_def_w,
bytop=>R_IDSTAT.is_bytop, macc=>R_IDSTAT.is_rmwop);
when s_dstr_def_w =>
nstate := s_dstr_def_w;
do_memcheck(nstate, nstatus, imemok);
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
do_fork_opg(nstate, R_IDSTAT);
end if;
when s_dstr_inc =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
macc := R_IDSTAT.is_rmwop and not DSTDEF;
bytop := R_IDSTAT.is_bytop and not DSTDEF;
do_memread_d(nstate, nvmcntl, s_dstr_inc_w,
bytop=>bytop, macc=>macc, is_pci=>R_IDSTAT.is_dstpc);
when s_dstr_inc_w =>
nstate := s_dstr_inc_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
if DSTDEF = '1' then
nstate := s_dstr_def;
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
when s_dstr_dec =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
ndpcntl.ddst_we := '1'; -- update DDST
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_dstr_dec1;
when s_dstr_dec1 =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
macc := R_IDSTAT.is_rmwop and not DSTDEF;
bytop := R_IDSTAT.is_bytop and not DSTDEF;
do_memread_d(nstate, nvmcntl, s_dstr_inc_w,
bytop=>bytop, macc=>macc);
when s_dstr_ind =>
do_memread_i(nstate, ndpcntl, nvmcntl, s_dstr_ind1_w);
when s_dstr_ind1_w =>
nstate := s_dstr_ind1_w;
if R_IDSTAT.is_dstpc = '0' then
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
else
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
nstate := s_dstr_ind2;
end if;
when s_dstr_ind2 =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
macc := R_IDSTAT.is_rmwop and not DSTDEF;
bytop := R_IDSTAT.is_bytop and not DSTDEF;
do_memread_d(nstate, nvmcntl, s_dstr_ind2_w,
bytop=>bytop, macc=>macc);
when s_dstr_ind2_w =>
nstate := s_dstr_ind2_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
if DSTDEF = '1' then
nstate := s_dstr_def;
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
-- destination write states -------------------------------------------------
-- flows:
-- 1 (r) s_dstw_def wreq (r) check kstack
-- s_dstw_def_w ack (r)
-- -> do_fork_next
--
-- 2 (r)+ s_dstw_inc wreq (r) check kstack
-- s_dstw_inc_w ack (r); r+=s
-- -> do_fork_next
--
-- 3 @(r)+ s_dstw_inc rreq (r); r+=s
-- s_dstw_incdef_w get (r)
-- s_dstw_def246 wreq @(r)
-- s_dstw_def_w ack @(r)
-- -> do_fork_next
--
-- 4 -(r) s_dstw_dec r-=s
-- s_dstw_dec1 wreq (r) check kstack
-- s_dstw_def_w ack (r)
-- -> do_fork_next
--
-- 5 @-(r) s_dstw_dec r-=s
-- s_dstw_dec1 rreq (r)
-- s_dstw_incdef_w get (r)
-- s_dstw_def246 wreq @(r)
-- s_dstw_def_w ack @(r)
-- -> do_fork_next
--
-- 6 n(r) s_dstw_ind rreq n
-- s_dstw_ind_w get n; ea=r+n
-- s_dstw_dec1 wreq n(r) check kstack
-- s_dstw_def_w ack n(r)
-- -> do_fork_next
--
-- 7 @n(r) s_dstw_ind rreq n
-- s_dstw_ind_w get n; ea=r+n
-- s_dstw_dec1 rreq n(r)
-- s_dstw_incdef_w get n(r)
-- s_dstw_def246 wreq @n(r)
-- s_dstw_def_w ack @n(r)
-- -> do_fork_next
when s_dstw_def =>
ndpcntl.psr_ccwe := '1';
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
nvmcntl.kstack := is_dstkstack1246;
do_memwrite(nstate, nvmcntl, s_dstw_def_w);
when s_dstw_def_w =>
nstate := s_dstw_def_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
do_fork_next(nstate, nstatus, nmmumoni);
end if;
when s_dstw_inc =>
ndpcntl.psr_ccwe := '1';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST (for else)
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG); --(...)
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (for else)
if DSTDEF = '0' then
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
nvmcntl.kstack := is_dstkstack1246;
do_memwrite(nstate, nvmcntl, s_dstw_inc_w);
nstatus.do_gprwe := '1';
else
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
do_memread_d(nstate, nvmcntl, s_dstw_incdef_w,
is_pci=>R_IDSTAT.is_dstpc);
end if;
when s_dstw_inc_w =>
nstate := s_dstw_inc_w;
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := DSTREG;
if R_STATUS.do_gprwe = '1' then
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
nmmumoni.trace_prev := '1'; -- ssr freeze of prev state
ndpcntl.gpr_we := '1'; -- update DST reg
end if;
nstatus.do_gprwe := '0';
do_memcheck(nstate, nstatus, imemok);
if imemok then
do_fork_next(nstate, nstatus, nmmumoni);
end if;
when s_dstw_incdef_w =>
nstate := s_dstw_incdef_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
nstate := s_dstw_def246;
end if;
when s_dstw_dec =>
ndpcntl.psr_ccwe := '1';
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
ndpcntl.ddst_we := '1'; -- update DDST
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_dstw_dec1;
when s_dstw_dec1 =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = from idec (for if)
if DSTDEF = '0' then
nvmcntl.kstack := is_dstkstack1246;
do_memwrite(nstate, nvmcntl, s_dstw_def_w);
else
do_memread_d(nstate, nvmcntl, s_dstw_incdef_w);
end if;
when s_dstw_ind =>
ndpcntl.psr_ccwe := '1';
do_memread_i(nstate, ndpcntl, nvmcntl, s_dstw_ind_w);
when s_dstw_ind_w =>
nstate := s_dstw_ind_w;
if R_IDSTAT.is_dstpc = '0' then
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
else
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
nstate := s_dstw_dec1;
end if;
when s_dstw_def246 =>
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
do_memwrite(nstate, nvmcntl, s_dstw_def_w);
-- destination address states -----------------------------------------------
-- flows:
-- 1 (r) -> do_fork_opa
--
-- 2 (r)+ s_dsta_inc r+=2
-- -> do_fork_opa
--
-- 3 @(r)+ s_dsta_inc req (r); r+=s
-- s_dsta_incdef_w get (r)
-- -> do_fork_opa
--
-- 4 -(r) s_dsta_dec r-=s
-- s_dsta_dec1 ?? FIXME ?? what is done here ??
-- -> do_fork_opa
--
-- 5 @-(r) s_dsta_dec r-=s
-- s_dsta_dec1 req (r)
-- s_dsta_incdef_w get (r)
-- -> do_fork_opa
--
-- 6 n(r) s_dsta_ind req n
-- s_dsta_ind_w get n; ea=r+n
-- s_dsta_dec1 ?? FIXME ?? what is done here ??
-- -> do_fork_opa
--
-- 7 @n(r) s_dsta_ind req n
-- s_dsta_ind_w get n; ea=r+n
-- s_dsta_dec1 req n(r)
-- s_dsta_incdef_w get n(r)
-- -> do_fork_opa
when s_dsta_inc =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES (for if)
if R_IDSTAT.updt_dstadsrc = '1' then -- prevent stale DSRC copy
ndpcntl.dsrc_we := '1'; -- update DSRC
end if;
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
if DSTDEF = '0' then
do_fork_opa(nstate, R_IDSTAT);
else
do_memread_d(nstate, nvmcntl, s_dsta_incdef_w,
is_pci=>R_IDSTAT.is_dstpc);
end if;
when s_dsta_incdef_w =>
nstate := s_dsta_incdef_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
do_fork_opa(nstate, R_IDSTAT);
end if;
when s_dsta_dec =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const(2)
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
ndpcntl.ddst_we := '1'; -- update DDST
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES (for if)
if R_IDSTAT.updt_dstadsrc = '1' then -- prevent stale DSRC copy
ndpcntl.dsrc_we := '1'; -- update DSRC
end if;
nstate := s_dsta_dec1;
when s_dsta_dec1 =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
if DSTDEF = '0' then -- check here used also by
do_fork_opa(nstate, R_IDSTAT); -- s_dsta_ind flow !!
else
do_memread_d(nstate, nvmcntl, s_dsta_incdef_w);
end if;
when s_dsta_ind =>
do_memread_i(nstate, ndpcntl, nvmcntl, s_dsta_ind_w);
when s_dsta_ind_w =>
nstate := s_dsta_ind_w;
if R_IDSTAT.is_dstpc = '0' then
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
else
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
nstate := s_dsta_dec1;
end if;
-- instruction operate states -----------------------------------------------
when s_op_halt => -- HALT
if is_kmode = '1' then -- if in kernel mode execute
nmmumoni.idone := '1';
nstatus.cpugo := '0';
nstatus.cpuhalt := '1';
nstatus.cpurust := c_cpurust_halt;
nstate := s_idle;
else -- otherwise trap
ncpuerr.illhlt := '1';
nstate := s_trap_4; -- trap 4 like 11/70
end if;
when s_op_wait => -- WAIT
nstate := s_op_wait; -- spin here
if is_kmode = '0' then -- but act as nop if not in kernel
nstate := s_idle;
elsif int_pending = '1' or -- bail out if pending interrupt
R_STATUS.cpustep='1' then -- or the instruction is only stepped
nstate := s_idle;
elsif R_STATUS.cmdbusy = '1' then -- suspend if a cp command is pending
nstatus.waitsusp := '1';
nstate := s_idle;
else
nstatus.cpuwait := '1'; -- if spinning here, signal with cpuwait
end if;
when s_op_trap => -- traps
lvector := "0000" & R_IDSTAT.trap_vec; -- vector
do_start_int(nstate, ndpcntl, lvector);
when s_op_reset => -- RESET
if is_kmode = '1' then -- if in kernel mode execute
nbreset := '1';
end if;
nstate := s_idle;
when s_op_rts => -- RTS
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1'; -- load PC with reg(dst)
nstate := s_op_rts_pop;
when s_op_rts_pop =>
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_op_rts_pop_w,
nmmumoni, updt_sp=>'1');
when s_op_rts_pop_w =>
nstate := s_op_rts_pop_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.gpr_adst := DSTREG;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.gpr_we := '1'; -- load R with (SP)+
do_fork_next(nstate, nstatus, nmmumoni);
end if;
when s_op_spl => -- SPL
ndpcntl.dres_sel := c_dpath_res_ireg; -- DRES = IREG
ndpcntl.psr_func := c_psr_func_wspl;
if is_kmode = '1' then -- active only in kernel mode
ndpcntl.psr_we := '1';
nstate := s_ifetch; -- unconditionally fetch next
-- instruction like a 11/70
-- no interrupt recognition !
else
do_fork_next(nstate, nstatus, nmmumoni); -- in non-kernel, noop
end if;
when s_op_mcc => -- CLx/SEx
ndpcntl.dres_sel := c_dpath_res_ireg; -- DRES = IREG
ndpcntl.psr_func := c_psr_func_wcc;
ndpcntl.psr_we := '1';
do_fork_next(nstate, nstatus, nmmumoni);
when s_op_br => -- BR
nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
ndpcntl.ounit_bsel := c_ounit_bsel_ireg8;-- OUNIT B = IREG8
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
-- note: cc are NZVC
case brcode(3 downto 1) is
when "000" => -- BR
brcond := '1';
when "001" => -- BNE/BEQ: if Z = x
brcond := PSW.cc(2);
when "010" => -- BGE/BLT: if N xor V = x
brcond := PSW.cc(3) xor PSW.cc(1);
when "011" => -- BGT/BLE: if Z or (N xor V) = x
brcond := PSW.cc(2) or (PSW.cc(3) xor PSW.cc(1));
when "100" => -- BPL/BMI: if N = x
brcond := PSW.cc(3);
when "101" => -- BHI/BLOS:if C or Z = x
brcond := PSW.cc(2) or PSW.cc(0);
when "110" => -- BVC/BVS: if V = x
brcond := PSW.cc(1);
when "111" => -- BCC/BCS: if C = x
brcond := PSW.cc(0);
when others => null;
end case;
ndpcntl.gpr_adst := c_gpr_pc;
if brcond = brcode(0) then -- this coding creates redundant code
ndpcntl.gpr_we := '1'; -- but synthesis optimizes this way !
do_fork_next(nstate, nstatus, nmmumoni);
else
do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
end if;
when s_op_mark => -- MARK
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
ndpcntl.ounit_bsel := c_ounit_bsel_ireg6;-- OUNIT B = IREG6
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC (with PC+2*nn)
ndpcntl.gpr_adst := c_gpr_r5; -- fetch r5
ndpcntl.ddst_sel := c_dpath_ddst_dst;
ndpcntl.ddst_we := '1';
nstate := s_op_mark1;
when s_op_mark1 =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1'; -- load PC with r5
nstate := s_op_mark_pop;
when s_op_mark_pop =>
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_op_mark_pop_w,
nmmumoni, updt_sp=>'1');
when s_op_mark_pop_w =>
nstate := s_op_mark_pop_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.gpr_adst := c_gpr_r5;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.gpr_we := '1'; -- load R5 with (sp)+
do_fork_next(nstate, nstatus, nmmumoni);
end if;
when s_op_sob => -- SOB (dec)
-- comment fork_next_pref out (blog 2006-10-02) due to synthesis impact
--nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
--ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
ndpcntl.dres_sel := R_IDSTAT.res_sel;
ndpcntl.gpr_adst := SRCREG;
ndpcntl.gpr_we := '1';
if DP_STAT.ccout_z = '0' then -- if z=0 branch, if z=1 fall thru
nstate := s_op_sob1;
else
--do_fork_next_pref(nstate, ndpcntl, nvmcntl, nmmumoni);
do_fork_next(nstate, nstatus, nmmumoni);
end if;
when s_op_sob1 => -- SOB (br)
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
ndpcntl.ounit_bsel := c_ounit_bsel_ireg6;-- OUNIT B = IREG6
ndpcntl.ounit_opsub := '1'; -- OUNIT = A - B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1';
do_fork_next(nstate, nstatus, nmmumoni);
when s_opg_gen =>
nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
ndpcntl.gpr_bytop := R_IDSTAT.is_bytop;
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
if R_IDSTAT.op_mov = '1' then -- in case of MOV xx,R
ndpcntl.gpr_bytop := '0'; -- no bytop, do sign extend
end if;
ndpcntl.psr_ccwe := '1';
if R_IDSTAT.is_dstw_reg = '1' then
ndpcntl.gpr_we := '1';
end if;
if R_IDSTAT.is_rmwop = '1' then
do_memwrite(nstate, nvmcntl, s_opg_gen_rmw_w, macc=>'1');
else
if R_STATUS.prefdone = '1' then
nstatus.prefdone :='0';
nstate := s_ifetch_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ireg_we := '1';
nstate := s_idecode;
end if;
else
if R_IDSTAT.is_dstw_pc = '1' then
nstate := s_idle;
else
do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
end if;
end if;
end if;
when s_opg_gen_rmw_w =>
nstate := s_opg_gen_rmw_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
do_fork_next(nstate, nstatus, nmmumoni);
end if;
when s_opg_mul => -- MUL (oper)
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.gpr_adst := SRCREG; -- write high order result
ndpcntl.gpr_we := '1';
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- capture high order part
ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
ndpcntl.dtmp_we := '1'; -- capture low order part
nstate := s_opg_mul1;
when s_opg_mul1 => -- MUL (write odd reg)
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG(2 downto 1) & "1";-- write odd reg !
ndpcntl.gpr_we := '1';
ndpcntl.psr_ccwe := '1';
do_fork_next(nstate, nstatus, nmmumoni);
when s_opg_div => -- DIV (load dd_low)
ndpcntl.munit_s_div := '1';
ndpcntl.gpr_asrc := SRCREG(2 downto 1) & "1";-- read odd reg !
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
ndpcntl.dtmp_we := '1';
nstate := s_opg_div_cn;
when s_opg_div_cn => -- DIV (1st...16th cycle)
ndpcntl.munit_s_div_cn := '1';
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
nstate := s_opg_div_cn;
if DP_STAT.div_zero='1' or DP_STAT.div_ovfl='1' then
nstate := s_opg_div_zero;
else
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.dtmp_we := '1'; -- update DTMP
end if;
if DP_STAT.shc_tc = '1' then
nstate := s_opg_div_cr;
end if;
when s_opg_div_cr => -- DIV (reminder correction)
ndpcntl.munit_s_div_cr := '1';
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := DP_STAT.div_cr; -- update DSRC
nstate := s_opg_div_sq;
when s_opg_div_sq => -- DIV (store quotient)
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP
ndpcntl.ounit_const := "00000000"&DP_STAT.div_cq;-- OUNIT const = Q corr.
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (q cor)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG; -- write result
ndpcntl.gpr_we := '1';
ndpcntl.dtmp_sel := c_dpath_dtmp_dres; -- DTMP = DRES
ndpcntl.dtmp_we := '1'; -- update DTMP (Q)
nstate := s_opg_div_sr;
when s_opg_div_sr => -- DIV (store reminder)
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG(2 downto 1) & "1";-- write odd reg !
ndpcntl.gpr_we := '1';
ndpcntl.psr_ccwe := '1';
do_fork_next(nstate, nstatus, nmmumoni);
when s_opg_div_zero => -- DIV (/0 or 0/ abort)
ndpcntl.psr_ccwe := '1';
do_fork_next(nstate, nstatus, nmmumoni);
when s_opg_ash => -- ASH (load shc)
ndpcntl.munit_s_ash := '1';
nstate := s_opg_ash_cn;
when s_opg_ash_cn => -- ASH (shift cycles)
nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.gpr_adst := SRCREG; -- write result
ndpcntl.munit_s_ash_cn := '1';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
nstate := s_opg_ash_cn;
if DP_STAT.shc_tc = '0' then
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.dsrc_we := '1'; -- update DSRC
else
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_we := '1';
ndpcntl.psr_ccwe := '1';
do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
end if;
when s_opg_ashc => -- ASHC (load low, load shc)
ndpcntl.gpr_asrc := SRCREG(2 downto 1) & "1";-- read odd reg !
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
ndpcntl.dtmp_we := '1';
ndpcntl.munit_s_ashc := '1';
nstate := s_opg_ashc_cn;
when s_opg_ashc_cn => -- ASHC (shift cycles)
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.gpr_adst := SRCREG; -- write result
ndpcntl.munit_s_ashc_cn := '1';
nstate := s_opg_ashc_cn;
if DP_STAT.shc_tc = '0' then
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.dtmp_we := '1'; -- update DTMP
else
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_we := '1';
ndpcntl.psr_ccwe := '1';
nstate := s_opg_ashc_wl;
end if;
when s_opg_ashc_wl => -- ASHC (write low)
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG(2 downto 1) & "1";-- write odd reg !
ndpcntl.gpr_we := '1';
do_fork_next(nstate, nstatus, nmmumoni);
-- dsta mode operations -----------------------------------------------------
when s_opa_jsr =>
ndpcntl.gpr_asrc := c_gpr_sp; -- (for else)
ndpcntl.dsrc_sel := c_dpath_dsrc_src; -- DSRC = regfile (for else)
if R_IDSTAT.is_dstmode0 = '1' then
nstate := s_trap_10; -- trap 10 like 11/70
else
ndpcntl.dsrc_we := '1';
nstate := s_opa_jsr1;
end if;
when s_opa_jsr1 =>
ndpcntl.gpr_asrc := SRCREG;
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc; -- DTMP = regfile
ndpcntl.dtmp_we := '1';
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DDST = DRES
ndpcntl.dsrc_we := '1'; -- update DDST
ndpcntl.gpr_adst := c_gpr_sp;
ndpcntl.gpr_we := '1'; -- update SP
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_opa_jsr_push;
when s_opa_jsr_push =>
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.dspace := '1';
nvmcntl.kstack := is_kmode;
nvmcntl.wacc := '1';
nvmcntl.req := '1';
nstate := s_opa_jsr_push_w;
when s_opa_jsr_push_w =>
nstate := s_opa_jsr_push_w;
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A=PC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.gpr_we := '1'; -- load R with PC
nstate := s_opa_jsr2;
end if;
when s_opa_jsr2 =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1'; -- load PC with dsta
do_fork_next(nstate, nstatus, nmmumoni);
when s_opa_jmp =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
if R_IDSTAT.is_dstmode0 = '1' then
nstate := s_trap_10; -- trap 10 like 11/70
else
ndpcntl.gpr_we := '1'; -- load PC with dsta
do_fork_next(nstate, nstatus, nmmumoni);
end if;
when s_opa_mtp =>
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_opa_mtp_pop_w,
nmmumoni, updt_sp=>'1');
when s_opa_mtp_pop_w =>
nstate := s_opa_mtp_pop_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.dtmp_sel := c_dpath_dtmp_dres; -- DTMP = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dtmp_we := '1'; -- load DTMP
if R_IDSTAT.is_dstmode0 = '1' then -- handle register access
nstate := s_opa_mtp_reg;
else
case R_IDSTAT.fork_dsta is -- 2nd dsta fork in s_idecode
when c_fork_dsta_def => nstate := s_opa_mtp_mem;
when c_fork_dsta_inc => nstate := s_dsta_inc;
when c_fork_dsta_dec => nstate := s_dsta_dec;
when c_fork_dsta_ind => nstate := s_dsta_ind;
when others => nstate := s_cpufail;
end case;
end if;
end if;
ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = R(DST)
ndpcntl.ddst_we := '1'; -- update DDST (needed for sp)
when s_opa_mtp_reg =>
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
ndpcntl.gpr_mode := PSW.pmode; -- load reg in pmode
ndpcntl.gpr_we := '1';
do_fork_next(nstate, nstatus, nmmumoni);
when s_opa_mtp_mem =>
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst;-- VA = DDST
nvmcntl.dspace := IREG(15); -- msb indicates I/D: 0->I, 1->D
nvmcntl.mode := PSW.pmode;
nvmcntl.wacc := '1';
nvmcntl.req := '1';
nstate := s_opa_mtp_mem_w;
when s_opa_mtp_mem_w =>
nstate := s_opa_mtp_mem_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
do_fork_next(nstate, nstatus, nmmumoni);
end if;
when s_opa_mfp_reg =>
ndpcntl.gpr_mode := PSW.pmode; -- fetch reg in pmode
ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = reg(dst)
ndpcntl.ddst_we := '1';
nstate := s_opa_mfp_dec;
when s_opa_mfp_mem =>
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
if PSW.cmode=c_psw_umode and -- if cm=pm=user then
PSW.cmode=c_psw_umode then -- MFPI works like it
nvmcntl.dspace := '1'; -- were MFPD
else
nvmcntl.dspace := IREG(15); -- msb indicates I/D: 0->I, 1->D
end if;
nvmcntl.mode := PSW.pmode;
nvmcntl.req := '1';
nstate := s_opa_mfp_mem_w;
when s_opa_mfp_mem_w =>
nstate := s_opa_mfp_mem_w;
do_memcheck(nstate, nstatus, imemok);
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
if imemok then
ndpcntl.ddst_we := '1';
nstate := s_opa_mfp_dec;
end if;
when s_opa_mfp_dec =>
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gpr_adst := c_gpr_sp;
ndpcntl.gpr_we := '1'; -- update SP
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_opa_mfp_push;
when s_opa_mfp_push =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.dspace := '1';
nvmcntl.kstack := is_kmode;
nvmcntl.wacc := '1';
nvmcntl.req := '1';
nstate := s_opa_mfp_push_w;
when s_opa_mfp_push_w =>
nstate := s_opa_mfp_push_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
do_fork_next(nstate, nstatus, nmmumoni);
end if;
-- trap and interrupt handling states ---------------------------------------
when s_trap_4 =>
lvector := "0000001"; -- vector (4)
do_start_int(nstate, ndpcntl, lvector);
when s_trap_10 =>
lvector := "0000010"; -- vector (10)
do_start_int(nstate, ndpcntl, lvector);
when s_trap_disp =>
if R_STATUS.trap_mmu = '1' then
nvmcntl.trap_done := '1'; -- mmu trap taken: set ssr0 trap bit
lvector := "0101010"; -- mmu trap: vector (250)
elsif R_STATUS.trap_ysv = '1' then
lvector := "0000001"; -- ysv trap: vector (4)
ncpuerr.ysv := '1';
else
lvector := "0000011"; -- trace trap: vector (14)
end if;
nstatus.trap_mmu := '0'; -- clear pending trap flags
nstatus.trap_ysv := '0'; --
do_start_int(nstate, ndpcntl, lvector);
when s_int_ext =>
lvector := R_STATUS.intvect; -- external vector
do_start_int(nstate, ndpcntl, lvector);
when s_int_getpc =>
nvmcntl.mode := c_psw_kmode; -- fetch PC from kernel D space
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_int_getpc_w, nmmumoni);
when s_int_getpc_w =>
nstate := s_int_getpc_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if VM_STAT.err = '1' then -- in case of vm-err
nstatus.cpugo := '0'; -- non-recoverable error
nstatus.cpurust := c_cpurust_vecfet; -- halt CPU
nstate := s_idle;
end if;
if imemok then
ndpcntl.ddst_we := '1'; -- DDST = new PC
nstate := s_int_getps;
end if;
when s_int_getps =>
nvmcntl.mode := c_psw_kmode; -- fetch PS from kernel D space
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_int_getps_w, nmmumoni);
when s_int_getps_w =>
nstate := s_int_getps_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.psr_func := c_psr_func_wint; -- interupt mode write
do_memcheck(nstate, nstatus, imemok);
if VM_STAT.err = '1' then -- in case of vm-err
nstatus.cpugo := '0'; -- non-recoverable error
nstatus.cpurust := c_cpurust_vecfet; -- halt CPU
nstate := s_idle;
end if;
if imemok then
ndpcntl.psr_we := '1'; -- store new PS
nstate := s_int_getsp;
end if;
when s_int_getsp =>
ndpcntl.gpr_asrc := c_gpr_sp;
ndpcntl.dsrc_we := '1'; -- DSRC = SP (in new mode)
nstate := s_int_decsp;
when s_int_decsp =>
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010"; -- OUNIT const=2
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gpr_adst := c_gpr_sp;
ndpcntl.gpr_we := '1'; -- update SP too
nstate := s_int_pushps;
when s_int_pushps =>
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP (old PS)
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.wacc := '1'; -- write mem
nvmcntl.dspace := '1';
nvmcntl.kstack := is_kmode;
nvmcntl.req := '1';
nstate := s_int_pushps_w;
when s_int_pushps_w =>
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010"; -- OUNIT const=2
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.gpr_adst := c_gpr_sp;
nstate := s_int_pushps_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gpr_we := '1'; -- update SP too
nstate := s_int_pushpc;
end if;
when s_int_pushpc =>
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A=PC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.wacc := '1'; -- write mem
nvmcntl.dspace := '1';
nvmcntl.kstack := is_kmode;
nvmcntl.req := '1';
nstate := s_int_pushpc_w;
when s_int_pushpc_w =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
nstate := s_int_pushpc_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
nstatus.do_intrsv := '0'; -- signal end of rsv
ndpcntl.gpr_we := '1'; -- load new PC
do_fork_next(nstate, nstatus, nmmumoni); -- ???
end if;
-- return from trap or interrupt handling states ----------------------------
when s_rti_getpc =>
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_rti_getpc_w,
nmmumoni, updt_sp=>'1');
when s_rti_getpc_w =>
nstate := s_rti_getpc_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- DDST = new PC
nstate := s_rti_getps;
end if;
when s_rti_getps =>
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_rti_getps_w,
nmmumoni, updt_sp=>'1');
when s_rti_getps_w =>
nstate := s_rti_getps_w;
do_memcheck(nstate, nstatus, imemok);
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
if is_kmode = '1' then -- if in kernel mode
ndpcntl.psr_func := c_psr_func_wall; -- write all fields
else
ndpcntl.psr_func := c_psr_func_wrti; -- otherwise filter
end if;
if imemok then
ndpcntl.psr_we := '1'; -- load new PS
nstate := s_rti_newpc;
end if;
when s_rti_newpc =>
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1'; -- load new PC
if R_IDSTAT.op_rtt = '1' then -- if RTT instruction
nstate := s_ifetch; -- force fetch
else -- otherwise RTI
do_fork_next(nstate, nstatus, nmmumoni);
end if;
-- exception abort states ---------------------------------------------------
when s_vmerr =>
nstate := s_cpufail;
-- setup for R_VMSTAT.err_rsv='1'
ndpcntl.ounit_azero := '1'; -- OUNIT A = 0
ndpcntl.ounit_const := "000000100"; -- emergency stack pointer
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(vector)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_mode := c_psw_kmode; -- set kmode SP to 4
ndpcntl.gpr_adst := c_gpr_sp;
nstatus.trap_mmu :='0'; -- drop pending mmu trap
if R_VMSTAT.fail = '1' then -- vmbox failure
nstatus.cpugo := '0'; -- halt cpu
nstatus.cpurust := c_cpurust_vfail;
nstate := s_idle;
elsif R_STATUS.do_intrsv = '1' then -- double error
nstatus.cpugo := '0'; -- give up, HALT cpu
nstatus.cpurust := c_cpurust_recrsv;
nstate := s_idle;
elsif R_VMSTAT.err = '1' then -- normal vm errors
if R_VMSTAT.err_rsv = '1' then
nstatus.do_intrsv := '1'; -- signal start of rsv
ndpcntl.gpr_we := '1';
if R_VMSTAT.err_odd='1' or R_VMSTAT.err_mmu='1' then
ncpuerr.adderr := '1';
elsif R_VMSTAT.err_nxm = '1' then
ncpuerr.nxm := '1';
elsif R_VMSTAT.err_iobto = '1' then
ncpuerr.iobto := '1';
end if;
ncpuerr.rsv := '1';
nstate := s_trap_4;
elsif R_VMSTAT.err_odd = '1' then
ncpuerr.adderr := '1';
nstate := s_trap_4;
elsif R_VMSTAT.err_nxm = '1' then
ncpuerr.nxm := '1';
nstate := s_trap_4;
elsif R_VMSTAT.err_iobto = '1' then
ncpuerr.iobto := '1';
nstate := s_trap_4;
elsif R_VMSTAT.err_mmu = '1' then
lvector := "0101010"; -- vector (250)
do_start_int(nstate, ndpcntl, lvector);
end if;
end if;
when s_cpufail =>
nstatus.cpugo := '0';
nstatus.cpurust := c_cpurust_sfail;
nstate := s_idle;
when others =>
nstate := s_cpufail; --!!! catch undefined states !!!
end case;
if nstatus.cmdack = '1' then -- cmdack in next cycle ? Yes we test
-- nstatus here !!
nstatus.cmdbusy := '0';
ndpcntl.cpdout_we := '1';
end if;
N_STATE <= nstate;
N_STATUS <= nstatus;
N_CPUERR <= ncpuerr;
N_IDSTAT <= nidstat;
CRESET <= ncreset;
BRESET <= nbreset;
INT_ACK <= nintack;
DP_CNTL <= ndpcntl;
VM_CNTL <= nvmcntl;
nmmumoni.regnum := ndpcntl.gpr_adst;
nmmumoni.delta := ndpcntl.ounit_const(3 downto 0);
MMU_MONI <= nmmumoni;
end process proc_next;
proc_cpstat : process (R_STATUS)
begin
CP_STAT <= cp_stat_init;
CP_STAT.cmdbusy <= R_STATUS.cmdbusy;
CP_STAT.cmdack <= R_STATUS.cmdack;
CP_STAT.cmderr <= R_STATUS.cmderr;
CP_STAT.cmdmerr <= R_STATUS.cmdmerr;
CP_STAT.cpugo <= R_STATUS.cpugo;
CP_STAT.cpustep <= R_STATUS.cpustep;
CP_STAT.cpuhalt <= R_STATUS.cpuhalt;
CP_STAT.cpuwait <= R_STATUS.cpuwait;
CP_STAT.cpurust <= R_STATUS.cpurust;
end process proc_cpstat;
end syn;
|
gpl-2.0
|
a003cbba60dd30c45ecc5ccbb1a13fe3
| 0.489627 | 3.559267 | false | false | false | false |
xylnao/w11a-extra
|
rtl/bplib/s3board/tb/tb_s3board_fusp.vhd
| 1 | 6,721 |
-- $Id: tb_s3board_fusp.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_s3board_fusp - sim
-- Description: Test bench for s3board (base+fusp)
--
-- Dependencies: vlib/rlink/tb/tbcore_rlink_dcm
-- tb_s3board_core
-- vlib/serport/serport_uart_rxtx
-- s3board_fusp_aif [UUT]
--
-- To test: generic, any s3board_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-30 351 3.0 use rlink/tb now
-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50
-- 2010-05-21 292 1.0.3 rename _PM1_ -> _FUSP_
-- 2010-05-16 291 1.0.2 rename tb_s3board_usp->tb_s3board_fusp
-- 2010-05-02 287 1.0.1 add sbaddr_portsel def, now sbus addr 8
-- 2010-05-01 286 1.0 Initial version (derived from tb_s3board)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serport.all;
use work.s3boardlib.all;
use work.simlib.all;
use work.simbus.all;
entity tb_s3board_fusp is
end tb_s3board_fusp;
architecture sim of tb_s3board_fusp is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal RX_HOLD : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slv2 := (others=>'1');
signal O_MEM_BE_N : slv4 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADDR : slv18 := (others=>'Z');
signal IO_MEM_DATA : slv32 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL : slbit := '0';
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 10 ns;
begin
TBCORE : tbcore_rlink
generic map (
CLK_PERIOD => clock_period,
CLK_OFFSET => clock_offset,
SETUP_TIME => setup_time,
C2OUT_TIME => c2out_time)
port map (
CLK => CLK,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
S3CORE : entity work.tb_s3board_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : s3board_fusp_aif
port map (
I_CLK50 => CLK,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
UART : serport_uart_rxtx
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLK,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_port_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
wait for c2out_time;
if RXERR = '1' then
writetimestamp(oline, SB_CLKCYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL <= to_x01(SB_DATA(0));
end if;
end if;
end process proc_simbus;
end sim;
|
gpl-2.0
|
1730d0d7977133fe7a334ef466ff05ee
| 0.538462 | 3.102955 | false | false | false | false |
Kolchuzhin/LMGT_MEMS_component_library
|
electrostatically_actuated_membrane/ememb_160.vhd
| 1 | 7,446 |
package electromagnetic_system is
nature electrical is real across real through electrical_ground reference;
nature translational is real across real through mechanical_ground reference;
end package electromagnetic_system;
use work.s_dat_160.all;
use work.ca12_dat_160.all;
use work.initial_160.all;
use work.electromagnetic_system.all;
entity ememb_160 is
generic (delay:time);
port (terminal struc1,struc2:translational;
terminal lagrange1,lagrange2:translational;
terminal master1,master2:translational;
terminal elec1,elec2:electrical);
end;
architecture behav of ememb_160 is
type ret_type is array(1 to 4) of real;
quantity q1 across fm1 through struc1;
quantity q2 across fm2 through struc2;
quantity p1 across r1 through lagrange1;
quantity p2 across r2 through lagrange2;
quantity u1 across f1 through master1;
quantity u2 across f2 through master2;
quantity v1 across i1 through elec1;
quantity v2 across i2 through elec2;
function spoly_calc(qx, qy, qz : in real:=0.0; s_type,s_inve : integer :=0;
s_ord, s_fak, s_data:real_vector) return ret_type is
constant Sx:integer:=integer(s_ord(1))+1;
constant Sy:integer:=integer(s_ord(2))+1;
constant Sz:integer:=integer(s_ord(3))+1;
variable fwx:real_vector(1 to Sx):=(others=>0.0);
variable fwy:real_vector(1 to Sy):=(others=>0.0);
variable fwz:real_vector(1 to 1):=(others=>0.0);
variable dfwx:real_vector(1 to Sx):=(others=>0.0);
variable dfwy:real_vector(1 to Sy):=(others=>0.0);
variable dfwz:real_vector(1 to 1):=(others=>0.0);
variable res_val:ret_type:=(others=>0.0);
variable fwv,dfwvx,dfwvy,dfwvz,fak2:real:=0.0;
variable Px_s,Py_s,Px,Py,Lx,Ly,Lz,ii:integer:=0;
begin
Lx:=integer(s_ord(1));
Ly:=integer(s_ord(2));
Lz:=integer(s_ord(3));
for i in 1 to Lx+1 loop
fwx(i):=qx**(i-1)*s_fak(1)**(i-1);
if i=2 then
dfwx(i):=s_fak(1)**(i-1);
end if;
if i>2 then
dfwx(i):=real(i-1)*qx**(i-2)*s_fak(1)**(i-1);
end if;
end loop;
for i in 1 to Ly+1 loop
fwy(i):=qy**(i-1)*s_fak(2)**(i-1);
if i=2 then
dfwy(i):=s_fak(2)**(i-1);
end if;
if i>2 then
dfwy(i):=real(i-1)*qy**(i-2)*s_fak(2)**(i-1);
end if;
end loop;
for i in 1 to Lz+1 loop
fwz(i):=qz**(i-1)*s_fak(3)**(i-1);
if i=2 then
dfwz(i):=s_fak(3)**(i-1);
end if;
if i>2 then
dfwz(i):=real(i-1)*qz**(i-2)*s_fak(3)**(i-1);
end if;
end loop;
if s_type=1 then
ii:=1;
for zi in 0 to Lz loop
for yi in 0 to Ly loop
for xi in 0 to Lx loop
fwv:=fwv+s_data(ii)*fwx(xi+1)*fwy(yi+1)*fwz(zi+1);
dfwvx:=dfwvx+s_data(ii)*dfwx(xi+1)*fwy(yi+1)*fwz(zi+1);
dfwvy:=dfwvy+s_data(ii)*fwx(xi+1)*dfwy(yi+1)*fwz(zi+1);
dfwvz:=dfwvz+s_data(ii)*fwx(xi+1)*fwy(yi+1)*dfwz(zi+1);
ii:=ii+1;
end loop;
end loop;
end loop;
end if;
if s_type=2 then
ii:=1;
Px_s:=integer(s_ord(1));
Py_s:=integer(s_ord(2));
for zi in 0 to Lz loop
Px:=Px_s-zi;
Py:=Py_s;
for yi in 0 to Py loop
for xi in 0 to Px loop
fwv:=fwv+s_data(ii)*fwx(xi+1)*fwy(yi+1)*fwz(zi+1);
dfwvx:=dfwvx+s_data(ii)*dfwx(xi+1)*fwy(yi+1)*fwz(zi+1);
dfwvy:=dfwvy+s_data(ii)*fwx(xi+1)*dfwy(yi+1)*fwz(zi+1);
dfwvz:=dfwvz+s_data(ii)*fwx(xi+1)*fwy(yi+1)*dfwz(zi+1);
ii:=ii+1;
end loop;
Px:=Px-1;
end loop;
Py:=Py-1;
end loop;
end if;
if s_type=3 then
ii:=1;
for yi in 0 to Ly loop
for xi in 0 to Lx loop
fwv:=fwv+s_data(ii)*fwx(xi+1)*fwy(yi+1);
dfwvx:=dfwvx+s_data(ii)*dfwx(xi+1)*fwy(yi+1);
dfwvy:=dfwvy+s_data(ii)*fwx(xi+1)*dfwy(yi+1);
dfwvz:=dfwvz+0.0;
ii:=ii+1;
end loop;
end loop;
for zi in 1 to Lz loop
for xi in 0 to Lx loop
fwv:=fwv+s_data(ii)*fwx(xi+1)*fwz(zi+1);
dfwvx:=dfwvx+s_data(ii)*dfwx(xi+1)*fwz(zi+1);
dfwvy:=dfwvy+0.0;
dfwvz:=dfwvz+s_data(ii)*fwx(xi+1)*dfwz(zi+1);
ii:=ii+1;
end loop;
end loop;
for zi in 1 to Lz loop
for yi in 1 to Ly loop
fwv:=fwv+s_data(ii)*fwy(yi+1)*fwz(zi+1);
dfwvx:=dfwvx+0.0;
dfwvy:=dfwvy+s_data(ii)*dfwy(yi+1)*fwz(zi+1);
dfwvz:=dfwvz+s_data(ii)*fwy(yi+1)*dfwz(zi+1);
ii:=ii+1;
end loop;
end loop;
end if;
if s_type=4 then
ii:=1;
Px:=integer(s_ord(1));
Py:=integer(s_ord(2));
for yi in 0 to Py loop
for xi in 0 to Px loop
fwv:=fwv+s_data(ii)*fwx(xi+1)*fwy(yi+1);
dfwvx:=dfwvx+s_data(ii)*dfwx(xi+1)*fwy(yi+1);
dfwvy:=dfwvy+s_data(ii)*fwx(xi+1)*dfwy(yi+1);
dfwvz:=dfwvz+0.0;
ii:=ii+1;
end loop;
Px:=Px-1;
end loop;
Px:=integer(s_ord(1));
for zi in 1 to Lz loop
for xi in 0 to Px-1 loop
fwv:=fwv+s_data(ii)*fwx(xi+1)*fwz(zi+1);
dfwvx:=dfwvx+s_data(ii)*dfwx(xi+1)*fwz(zi+1);
dfwvy:=dfwvy+0.0;
dfwvz:=dfwvz+s_data(ii)*fwx(xi+1)*dfwz(zi+1);
ii:=ii+1;
end loop;
Px:=Px-1;
end loop;
for zi in 1 to Lz-1 loop
for yi in 1 to Py-1 loop
fwv:=fwv+s_data(ii)*fwy(yi+1)*fwz(zi+1);
dfwvx:=dfwvx+0.0;
dfwvy:=dfwvy+s_data(ii)*dfwy(yi+1)*fwz(zi+1);
dfwvz:=dfwvz+s_data(ii)*fwy(yi+1)*dfwz(zi+1);
ii:=ii+1;
end loop;
Py:=Py-1;
end loop;
end if;
if s_inve=1 then
fwv:=fwv*s_fak(4);
dfwvx:=dfwvx*s_fak(4);
dfwvy:=dfwvy*s_fak(4);
dfwvz:=dfwvz*s_fak(4);
else
fak2:=1.0/s_fak(4);
dfwvx:=-dfwvx/(fwv**2);
dfwvy:=-dfwvy/(fwv**2);
dfwvz:=-dfwvz/(fwv**2);
fwv:=1.0/fwv;
fwv:=fwv*fak2;
dfwvx:=dfwvx*fak2;
dfwvy:=dfwvy*fak2;
dfwvz:=dfwvz*fak2;
end if;
res_val:=(fwv, dfwvx, dfwvy, dfwvz);
return res_val;
end spoly_calc;
signal sene_160:ret_type;
signal ca12_160:ret_type;
begin
p1:process
begin
sene_160<= spoly_calc(q1,q2,0.0,s_type160,s_inve160,s_ord160,s_fak160,s_data160);
ca12_160<= spoly_calc(q1,q2,0.0,ca12_type160,ca12_inve160,ca12_ord160,ca12_fak160,ca12_data160);
wait for delay;
end process;
break on sene_160(2),sene_160(3),sene_160(4),ca12_160(2),ca12_160(3),ca12_160(4);
-- LIN w/o stress stiffening: fqr1=km_1*q1, fqr2=km_2*q2
--fm1==mm_1*q1'dot'dot + dm_1*q1'dot +km_1*q1 -ca12_160(2)*(v1-v2)**2/2.0 +fi1_1*p1 +fi2_1*p2;
--fm2==mm_2*q2'dot'dot + dm_2*q2'dot +km_2*q2 -ca12_160(3)*(v1-v2)**2/2.0 +fi1_2*p1 +fi2_2*p2;
-- stress stiffening NL: fqr1=sene_160(2), fqr2=sene_160(3)
fm1==mm_1*q1'dot'dot + dm_1*q1'dot +sene_160(2) -ca12_160(2)*(v1-v2)**2/2.0 +fi1_1*p1 +fi2_1*p2;
fm2==mm_2*q2'dot'dot + dm_2*q2'dot +sene_160(3) -ca12_160(3)*(v1-v2)**2/2.0 +fi1_2*p1 +fi2_2*p2;
r1==fi1_1*q1+fi1_2*q2-u1;
r2==fi2_1*q1+fi2_2*q2-u2;
f1==-p1;
f2==-p2;
i1==+((v1-v2)*(ca12_160(2)*q1'dot+ca12_160(3)*q2'dot)+(v1'dot-v2'dot)*ca12_160(1));
i2==-((v1-v2)*(ca12_160(2)*q1'dot+ca12_160(3)*q2'dot)+(v1'dot-v2'dot)*ca12_160(1));
end;
|
mit
|
cd2209fd4bc899f502ff8fec9c0f93a9
| 0.543916 | 2.582726 | false | false | false | false |
rogerioag/gcg
|
tutorial/ula/testbench/or3_tb.vhd
| 1 | 2,004 |
-- Testebench gerado via script.
-- Data: Qua,20/07/2011-13:51:40
-- Autor: rogerio
-- Comentario: Teste da entidade or3.
library ieee;
use ieee.std_logic_1164.all;
entity or3_tb is
end or3_tb;
architecture logica of or3_tb is
-- Declaração do componente.
component or3
port (a,b,c: in std_logic; y: out std_logic);
end component;
-- Especifica qual a entidade está vinculada com o componente.
for or3_0: or3 use entity work.or3;
signal s_t_a, s_t_b, s_t_c, s_t_y: std_logic;
begin
-- Instanciação do Componente.
-- port map (<<p_in_1>> => <<s_t_in_1>>)
or3_0: or3 port map (a=>s_t_a,b=>s_t_b,c=>s_t_c,y=>s_t_y);
-- Processo que faz o trabalho.
process
-- Um registro é criado com as entradas e saídas da entidade.
-- (<<entrada1>>, <<entradaN>>, <<saida1>>, <<saidaN>>)
type pattern_type is record
-- entradas.
vi_a,vi_b,vi_c: std_logic;
-- saídas.
vo_y: std_logic;
end record;
-- Os padrões de entrada são aplicados (injetados) às entradas.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
(
('0', '0', '0', '0'),
('0', '0', '1', '1'),
('0', '1', '0', '1'),
('0', '1', '1', '1'),
('1', '0', '0', '1'),
('1', '0', '1', '1'),
('1', '1', '0', '1'),
('1', '1', '1', '1')
);
begin
-- Checagem de padrões.
for i in patterns'range loop
-- Injeta as entradas.
s_t_a <= patterns(i).vi_a;
s_t_b <= patterns(i).vi_b;
s_t_c <= patterns(i).vi_c;
-- Aguarda os resultados.
wait for 1 ns;
-- Checa o resultado com a saída esperada no padrão.
assert s_t_y = patterns(i).vo_y report "Valor de s_t_y não confere com o resultado esperado." severity error;
end loop;
assert false report "Fim do teste." severity note;
-- Wait forever; Isto finaliza a simulação.
wait;
end process;
end logica;
|
gpl-3.0
|
726f21987a9dd5c25326c0efb7847c32
| 0.560141 | 2.87971 | false | false | false | false |
Kolchuzhin/LMGT_MEMS_component_library
|
electrostatically_actuated_membrane/s_ams_160.vhd
| 1 | 868 |
package s_dat_160 is
constant s_type160:integer:=1;
constant s_inve160:integer:=1;
signal s_ord160:real_vector(1 to 3):=( 4.0, 4.0, 0.0 );
signal s_fak160:real_vector(1 to 4):=( 0.114386722375, 0.795085352965, 0.0, 2107.233904 );
constant s_anz160:integer:= 25;
signal s_data160:real_vector(1 to 25):=
(
0.832702752873E-07,
-0.140453798427E-14,
0.429309184785 ,
0.109391250030E-14,
0.291985344904 ,
0.207339774625E-14,
-0.186971620812E-05,
-0.152582657928E-13,
0.124224281759 ,
0.148706670364E-13,
0.798129483956E-01,
0.206229910840E-13,
0.627255053996E-01,
-0.205185875145E-13,
0.153987606242E-05,
-0.247538941670E-14,
0.104493898549E-01,
0.183901764210E-13,
0.516669367876E-06,
-0.179097341258E-13,
0.149282741683E-02,
-0.189532739990E-13,
0.143077040992E-06,
0.189540164009E-13,
0.216911589898E-08
);
end;
|
mit
|
febfba18184d6d13b6a0e0580dc10e8a
| 0.701613 | 2.14321 | false | false | false | false |
wgml/sysrek
|
skin_color_segm/ipcore_dir/BINARYZACJA/simulation/BINARYZACJA_tb_agen.vhd
| 4 | 4,340 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: BINARYZACJA_tb_agen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY BINARYZACJA_TB_AGEN IS
GENERIC (
C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END BINARYZACJA_TB_AGEN;
ARCHITECTURE BEHAVIORAL OF BINARYZACJA_TB_AGEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
gpl-2.0
|
de51ce90459f9df3e57da7094ca7d47b
| 0.597465 | 4.488108 | false | false | false | false |
os-cillation/easyfpga-soc
|
easy_cores/uart16750/uart_16750.vhd
| 1 | 52,253 |
--
-- UART 16750
--
-- Author: Sebastian Witt
-- Date: 29.01.2008
-- Version: 1.5
--
-- History: 1.0 - Initial version
-- 1.1 - THR empty interrupt register connected to RST
-- 1.2 - Registered outputs
-- 1.3 - Automatic flow control
-- 1.4 - De-assert IIR FIFO64 when FIFO is disabled
-- 1.5 - Inverted low active outputs when RST is active
--
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART
entity uart_16750 is
port (
-- To be adapted to Wishbone
CLK : in std_logic; -- Clock
RST : in std_logic; -- Async Reset
WR : in std_logic; -- Write to UART
RD : in std_logic; -- Read from UART
A : in std_logic_vector(2 downto 0); -- Register select
DIN : in std_logic_vector(7 downto 0); -- Data bus input
DOUT : out std_logic_vector(7 downto 0); -- Data bus output
INT : out std_logic; -- Interrupt output (INT <= not IIR(0))
-- UART interface
RTSN : out std_logic; -- RTS output
DTRN : out std_logic; -- DTR output
CTSN : in std_logic; -- CTS input
DSRN : in std_logic; -- DSR input
DCDN : in std_logic; -- DCD input
RIN : in std_logic; -- RI input
SIN : in std_logic; -- Receiver input
SOUT : out std_logic; -- Transmitter output
OUT1N : out std_logic; -- MCR auxiliary output 1
OUT2N : out std_logic; -- MCR auxiliary output 2
-- To be tied together
BAUDOUTN : out std_logic; -- Baudrate generator output (16x baudrate)
RCLK : in std_logic; -- Receiver clock (16x baudrate)
-- For now ignored
CS : in std_logic := '1'; -- Chip select
BAUDCE : in std_logic := '1'; -- Baudrate generator clock enable
DDIS : out std_logic -- Driver disable
);
end uart_16750;
architecture rtl of uart_16750 is
-- UART transmitter
component uart_transmitter is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
TXCLK : in std_logic; -- Transmitter clock (2x baudrate)
TXSTART : in std_logic; -- Start transmitter
CLEAR : in std_logic; -- Clear transmitter state
WLS : in std_logic_vector(1 downto 0); -- Word length select
STB : in std_logic; -- Number of stop bits
PEN : in std_logic; -- Parity enable
EPS : in std_logic; -- Even parity select
SP : in std_logic; -- Stick parity
BC : in std_logic; -- Break control
DIN : in std_logic_vector(7 downto 0); -- Input data
TXFINISHED : out std_logic; -- Transmitter operation finished
SOUT : out std_logic -- Transmitter output
);
end component;
-- UART receiver
component uart_receiver is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
RXCLK : in std_logic; -- Receiver clock (16x baudrate)
RXCLEAR : in std_logic; -- Reset receiver state
WLS : in std_logic_vector(1 downto 0); -- Word length select
STB : in std_logic; -- Number of stop bits
PEN : in std_logic; -- Parity enable
EPS : in std_logic; -- Even parity select
SP : in std_logic; -- Stick parity
SIN : in std_logic; -- Receiver input
PE : out std_logic; -- Parity error
FE : out std_logic; -- Framing error
BI : out std_logic; -- Break interrupt
DOUT : out std_logic_vector(7 downto 0); -- Output data
RXFINISHED : out std_logic -- Receiver operation finished
);
end component;
-- UART interrupt control
component uart_interrupt is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
IER : in std_logic_vector(3 downto 0); -- IER 3:0
LSR : in std_logic_vector(4 downto 0); -- LSR 4:0
THI : in std_logic; -- Transmitter holding register empty interrupt
RDA : in std_logic; -- Receiver data available
CTI : in std_logic; -- Character timeout indication
AFE : in std_logic; -- Automatic flow control enable
MSR : in std_logic_vector(3 downto 0); -- MSR 3:0
IIR : out std_logic_vector(3 downto 0); -- IIR 3:0
INT : out std_logic -- Interrupt
);
end component;
-- UART baudrate generator
component uart_baudgen is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
CLEAR : in std_logic; -- Reset generator (synchronization)
DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider
BAUDTICK : out std_logic -- 16xBaudrate tick
);
end component;
-- UART FIFO
component slib_fifo is
generic (
WIDTH : integer := 8; -- FIFO width
SIZE_E : integer := 6 -- FIFO size (2^SIZE_E)
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear FIFO
WRITE : in std_logic; -- Write to FIFO
READ : in std_logic; -- Read from FIFO
D : in std_logic_vector(WIDTH-1 downto 0); -- FIFO input
Q : out std_logic_vector(WIDTH-1 downto 0); -- FIFO output
EMPTY : out std_logic; -- FIFO is empty
FULL : out std_logic; -- FIFO is full
USAGE : out std_logic_vector(SIZE_E-1 downto 0) -- FIFO usage
);
end component;
-- Edge detect
component slib_edge_detect is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
RE : out std_logic; -- Rising edge detected
FE : out std_logic -- Falling edge detected
);
end component;
-- Input synchronization
component slib_input_sync is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end component;
-- Input filter
component slib_input_filter is
generic (
SIZE : natural := 4 -- Filter width
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end component;
-- Clock enable generation
component slib_clock_div is
generic (
RATIO : integer := 8 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end component;
-- Global device signals
signal iCSWR : std_logic; -- Chipselect and write
signal iCSRD : std_logic; -- Chipselect and read
signal iWriteFE : std_logic; -- Write falling edge
signal iReadFE : std_logic; -- Read falling edge
signal iWrite : std_logic; -- Write to UART
signal iRead : std_logic; -- Read from UART
signal iA : std_logic_vector(2 downto 0); -- UART register address
signal iDIN : std_logic_vector(7 downto 0); -- UART data input
-- UART registers read/write signals
signal iRBRRead : std_logic; -- Read from RBR
signal iTHRWrite : std_logic; -- Write to THR
signal iDLLWrite : std_logic; -- Write to DLL
signal iDLMWrite : std_logic; -- Write to DLM
signal iIERWrite : std_logic; -- Write to IER
signal iIIRRead : std_logic; -- Read from IIR
signal iFCRWrite : std_logic; -- Write to FCR
signal iLCRWrite : std_logic; -- Write to LCR
signal iMCRWrite : std_logic; -- Write to MCR
signal iLSRRead : std_logic; -- Read from LSR
signal iMSRRead : std_logic; -- Read from MSR
signal iSCRWrite : std_logic; -- Write to SCR
-- UART registers
signal iTSR : std_logic_vector(7 downto 0); -- Transmitter holding register
signal iRBR : std_logic_vector(7 downto 0); -- Receiver buffer register
signal iDLL : std_logic_vector(7 downto 0); -- Divisor latch LSB
signal iDLM : std_logic_vector(7 downto 0); -- Divisor latch MSB
signal iIER : std_logic_vector(7 downto 0); -- Interrupt enable register
signal iIIR : std_logic_vector(7 downto 0); -- Interrupt identification register
signal iFCR : std_logic_vector(7 downto 0); -- FIFO control register
signal iLCR : std_logic_vector(7 downto 0); -- Line control register
signal iMCR : std_logic_vector(7 downto 0); -- Modem control register
signal iLSR : std_logic_vector(7 downto 0); -- Line status register
signal iMSR : std_logic_vector(7 downto 0); -- Modem status register
signal iSCR : std_logic_vector(7 downto 0); -- Scratch register
-- IER register signals
signal iIER_ERBI : std_logic; -- IER: Enable received data available interrupt
signal iIER_ETBEI : std_logic; -- IER: Enable transmitter holding register empty interrupt
signal iIER_ELSI : std_logic; -- IER: Enable receiver line status interrupt
signal iIER_EDSSI : std_logic; -- IER: Enable modem status interrupt
-- IIR register signals
signal iIIR_PI : std_logic; -- IIR: Pending interrupt
signal iIIR_ID0 : std_logic; -- IIR: Interrupt ID0
signal iIIR_ID1 : std_logic; -- IIR: Interrupt ID1
signal iIIR_ID2 : std_logic; -- IIR: Interrupt ID2
signal iIIR_FIFO64 : std_logic; -- IIR: 64 byte FIFO enabled
-- FCR register signals
signal iFCR_FIFOEnable : std_logic; -- FCR: FIFO enable
signal iFCR_RXFIFOReset : std_logic; -- FCR: Receiver FIFO reset
signal iFCR_TXFIFOReset : std_logic; -- FCR: Transmitter FIFO reset
signal iFCR_DMAMode : std_logic; -- FCR: DMA mode select
signal iFCR_FIFO64E : std_logic; -- FCR: 64 byte FIFO enable
signal iFCR_RXTrigger : std_logic_vector(1 downto 0); -- FCR: Receiver trigger
-- LCR register signals
signal iLCR_WLS : std_logic_vector(1 downto 0); -- LCR: Word length select
signal iLCR_STB : std_logic; -- LCR: Number of stop bits
signal iLCR_PEN : std_logic; -- LCR: Parity enable
signal iLCR_EPS : std_logic; -- LCR: Even parity select
signal iLCR_SP : std_logic; -- LCR: Sticky parity
signal iLCR_BC : std_logic; -- LCR: Break control
signal iLCR_DLAB : std_logic; -- LCR: Divisor latch access bit
-- MCR register signals
signal iMCR_DTR : std_logic; -- MCR: Data terminal ready
signal iMCR_RTS : std_logic; -- MCR: Request to send
signal iMCR_OUT1 : std_logic; -- MCR: OUT1
signal iMCR_OUT2 : std_logic; -- MCR: OUT2
signal iMCR_LOOP : std_logic; -- MCR: Loop
signal iMCR_AFE : std_logic; -- MCR: Auto flow control enable
-- LSR register signals
signal iLSR_DR : std_logic; -- LSR: Data ready
signal iLSR_OE : std_logic; -- LSR: Overrun error
signal iLSR_PE : std_logic; -- LSR: Parity error
signal iLSR_FE : std_logic; -- LSR: Framing error
signal iLSR_BI : std_logic; -- LSR: Break Interrupt
signal iLSR_THRE : std_logic; -- LSR: Transmitter holding register empty
signal iLSR_TEMT : std_logic; -- LSR: Transmitter empty
signal iLSR_FIFOERR : std_logic; -- LSR: Error in receiver FIFO
-- MSR register signals
signal iMSR_dCTS : std_logic; -- MSR: Delta CTS
signal iMSR_dDSR : std_logic; -- MSR: Delta DSR
signal iMSR_TERI : std_logic; -- MSR: Trailing edge ring indicator
signal iMSR_dDCD : std_logic; -- MSR: Delta DCD
signal iMSR_CTS : std_logic; -- MSR: CTS
signal iMSR_DSR : std_logic; -- MSR: DSR
signal iMSR_RI : std_logic; -- MSR: RI
signal iMSR_DCD : std_logic; -- MSR: DCD
-- UART MSR signals
signal iCTSNs : std_logic; -- Synchronized CTSN input
signal iDSRNs : std_logic; -- Synchronized DSRN input
signal iDCDNs : std_logic; -- Synchronized DCDN input
signal iRINs : std_logic; -- Synchronized RIN input
signal iCTSn : std_logic; -- Filtered CTSN input
signal iDSRn : std_logic; -- Filtered DSRN input
signal iDCDn : std_logic; -- Filtered DCDN input
signal iRIn : std_logic; -- Filtered RIN input
signal iCTSnRE : std_logic; -- CTSn rising edge
signal iCTSnFE : std_logic; -- CTSn falling edge
signal iDSRnRE : std_logic; -- DSRn rising edge
signal iDSRnFE : std_logic; -- DSRn falling edge
signal iDCDnRE : std_logic; -- DCDn rising edge
signal iDCDnFE : std_logic; -- DCDn falling edge
signal iRInRE : std_logic; -- RIn rising edge
signal iRInFE : std_logic; -- RIn falling edge
-- UART baudrate generation signals
signal iBaudgenDiv : std_logic_vector(15 downto 0); -- Baudrate divider
signal iBaudtick16x : std_logic; -- 16x Baudrate output from baudrate generator
signal iBaudtick2x : std_logic; -- 2x Baudrate for transmitter
signal iRCLK : std_logic; -- 16x Baudrate for receiver
-- UART FIFO signals
signal iTXFIFOClear : std_logic; -- Clear TX FIFO
signal iTXFIFOWrite : std_logic; -- Write to TX FIFO
signal iTXFIFORead : std_logic; -- Read from TX FIFO
signal iTXFIFOEmpty : std_logic; -- TX FIFO is empty
signal iTXFIFOFull : std_logic; -- TX FIFO is full
signal iTXFIFO16Full : std_logic; -- TX FIFO 16 byte mode is full
signal iTXFIFO64Full : std_logic; -- TX FIFO 64 byte mode is full
signal iTXFIFOUsage : std_logic_vector(5 downto 0); -- RX FIFO usage
signal iTXFIFOQ : std_logic_vector(7 downto 0); -- TX FIFO output
signal iRXFIFOClear : std_logic; -- Clear RX FIFO
signal iRXFIFOWrite : std_logic; -- Write to RX FIFO
signal iRXFIFORead : std_logic; -- Read from RX FIFO
signal iRXFIFOEmpty : std_logic; -- RX FIFO is empty
signal iRXFIFOFull : std_logic; -- RX FIFO is full
signal iRXFIFO16Full : std_logic; -- RX FIFO 16 byte mode is full
signal iRXFIFO64Full : std_logic; -- RX FIFO 64 byte mode is full
signal iRXFIFOD : std_logic_vector(10 downto 0); -- RX FIFO input
signal iRXFIFOQ : std_logic_vector(10 downto 0); -- RX FIFO output
signal iRXFIFOUsage : std_logic_vector(5 downto 0); -- RX FIFO usage
signal iRXFIFOTrigger : std_logic; -- FIFO trigger level reached
signal iRXFIFO16Trigger : std_logic; -- FIFO 16 byte mode trigger level reached
signal iRXFIFO64Trigger : std_logic; -- FIFO 64 byte mode trigger level reached
signal iRXFIFOPE : std_logic; -- Parity error from FIFO
signal iRXFIFOFE : std_logic; -- Frame error from FIFO
signal iRXFIFOBI : std_logic; -- Break interrupt from FIFO
-- UART transmitter signals
signal iSOUT : std_logic; -- Transmitter output
signal iTXStart : std_logic; -- Start transmitter
signal iTXClear : std_logic; -- Clear transmitter status
signal iTXFinished : std_logic; -- TX finished, character transmitted
signal iTXRunning : std_logic; -- TX in progress
-- UART receiver signals
signal iSINr : std_logic; -- Synchronized SIN input
signal iSIN : std_logic; -- Receiver input
signal iRXFinished : std_logic; -- RX finished, character received
signal iRXClear : std_logic; -- Clear receiver status
signal iRXData : std_logic_vector(7 downto 0); -- RX data
signal iRXPE : std_logic; -- RX parity error
signal iRXFE : std_logic; -- RX frame error
signal iRXBI : std_logic; -- RX break interrupt
-- UART control signals
signal iFERE : std_logic; -- Frame error detected
signal iPERE : std_logic; -- Parity error detected
signal iBIRE : std_logic; -- Break interrupt detected
signal iFECounter : integer range 0 to 64; -- FIFO error counter
signal iFEIncrement : std_logic; -- FIFO error counter increment
signal iFEDecrement : std_logic; -- FIFO error counter decrement
signal iRDAInterrupt : std_logic; -- Receiver data available interrupt (DA or FIFO trigger level)
signal iTimeoutCount : unsigned(5 downto 0); -- Character timeout counter (FIFO mode)
signal iCharTimeout : std_logic; -- Character timeout indication (FIFO mode)
signal iLSR_THRERE : std_logic; -- LSR THRE rising edge for interrupt generation
signal iTHRInterrupt : std_logic; -- Transmitter holding register empty interrupt
signal iTXEnable : std_logic; -- Transmitter enable signal
signal iRTS : std_logic; -- Internal RTS signal with/without automatic flow control
begin
-- Global device signals
iCSWR <= '1' when CS = '1' and WR = '1' else '0';
iCSRD <= '1' when CS = '1' and RD = '1' else '0';
UART_ED_WRITE: slib_edge_detect port map (CLK => CLK, RST => RST, D => iCSWR, FE => iWriteFE);
UART_ED_READ: slib_edge_detect port map (CLK => CLK, RST => RST, D => iCSRD, FE => iReadFE);
iWrite <= '1' when iWriteFE = '1' else '0';
iRead <= '1' when iReadFE = '1' else '0';
-- UART registers read/write signals
iRBRRead <= '1' when iRead = '1' and iA = "000" and iLCR_DLAB = '0' else '0';
iTHRWrite <= '1' when iWrite = '1' and iA = "000" and iLCR_DLAB = '0' else '0';
iDLLWrite <= '1' when iWrite = '1' and iA = "000" and iLCR_DLAB = '1' else '0';
iDLMWrite <= '1' when iWrite = '1' and iA = "001" and iLCR_DLAB = '1' else '0';
iIERWrite <= '1' when iWrite = '1' and iA = "001" and iLCR_DLAB = '0' else '0';
iIIRRead <= '1' when iRead = '1' and iA = "010" else '0';
iFCRWrite <= '1' when iWrite = '1' and iA = "010" else '0';
iLCRWrite <= '1' when iWrite = '1' and iA = "011" else '0';
iMCRWrite <= '1' when iWrite = '1' and iA = "100" else '0';
iLSRRead <= '1' when iRead = '1' and iA = "101" else '0';
iMSRRead <= '1' when iRead = '1' and iA = "110" else '0';
iSCRWrite <= '1' when iWrite = '1' and iA = "111" else '0';
-- Async. input synchronization
UART_IS_SIN: slib_input_sync port map (CLK, RST, SIN, iSINr);
UART_IS_CTS: slib_input_sync port map (CLK, RST, CTSN, iCTSNs);
UART_IS_DSR: slib_input_sync port map (CLK, RST, DSRN, iDSRNs);
UART_IS_DCD: slib_input_sync port map (CLK, RST, DCDN, iDCDNs);
UART_IS_RI: slib_input_sync port map (CLK, RST, RIN, iRINs);
-- Input filter for UART control signals
UART_IF_CTS: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iCTSNs, iCTSn);
UART_IF_DSR: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iDSRNs, iDSRn);
UART_IF_DCD: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iDCDNs, iDCDn);
UART_IF_RI: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iRINs, iRIn);
-- Sync. input synchronization
UART_SIS: process (CLK, RST)
begin
if (RST = '1') then
iA <= (others => '0');
iDIN <= (others => '0');
elsif (CLK'event and CLK = '1') then
iA <= A;
iDIN <= DIN;
end if;
end process;
-- Divisor latch register
UART_DLR: process (CLK, RST)
begin
if (RST = '1') then
iDLL <= (others => '0');
iDLM <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iDLLWrite = '1') then
iDLL <= iDIN;
end if;
if (iDLMWrite = '1') then
iDLM <= iDIN;
end if;
end if;
end process;
-- Interrupt enable register
UART_IER: process (CLK, RST)
begin
if (RST = '1') then
iIER(3 downto 0) <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iIERWrite = '1') then
iIER(3 downto 0) <= iDIN(3 downto 0);
end if;
end if;
end process;
iIER_ERBI <= iIER(0);
iIER_ETBEI <= iIER(1);
iIER_ELSI <= iIER(2);
iIER_EDSSI <= iIER(3);
iIER(7 downto 4) <= (others => '0');
-- Interrupt control and IIR
UART_IIC: uart_interrupt port map (CLK => CLK,
RST => RST,
IER => iIER(3 downto 0),
LSR => iLSR(4 downto 0),
THI => iTHRInterrupt,
RDA => iRDAInterrupt,
CTI => iCharTimeout,
AFE => iMCR_AFE,
MSR => iMSR(3 downto 0),
IIR => iIIR(3 downto 0),
INT => INT
);
-- THR empty interrupt
UART_IIC_THRE_ED: slib_edge_detect port map (CLK => CLK, RST => RST, D => iLSR_THRE, RE => iLSR_THRERE);
UART_IIC_THREI: process (CLK, RST)
begin
if (RST = '1') then
iTHRInterrupt <= '0';
elsif (CLK'event and CLK = '1') then
if (iLSR_THRERE = '1' or iFCR_TXFIFOReset = '1' or (iIERWrite = '1' and iDIN(1) = '1' and iLSR_THRE = '1')) then
iTHRInterrupt <= '1'; -- Set on THRE, TX FIFO reset (FIFO enable) or ETBEI enable
elsif ((iIIRRead = '1' and iIIR(3 downto 1) = "001") or iTHRWrite = '1') then
iTHRInterrupt <= '0'; -- Clear on IIR read (if source of interrupt) or THR write
end if;
end if;
end process;
iRDAInterrupt <= '1' when (iFCR_FIFOEnable = '0' and iLSR_DR = '1') or
(iFCR_FIFOEnable = '1' and iRXFIFOTrigger = '1') else '0';
iIIR_PI <= iIIR(0);
iIIR_ID0 <= iIIR(1);
iIIR_ID1 <= iIIR(2);
iIIR_ID2 <= iIIR(3);
iIIR_FIFO64 <= iIIR(5);
iIIR(4) <= '0';
iIIR(5) <= iFCR_FIFO64E when iFCR_FIFOEnable = '1' else '0';
iIIR(6) <= iFCR_FIFOEnable;
iIIR(7) <= iFCR_FIFOEnable;
-- Character timeout indication
UART_CTI: process (CLK, RST)
begin
if (RST = '1') then
iTimeoutCount <= (others => '0');
iCharTimeout <= '0';
elsif (CLK'event and CLK = '1') then
if (iRXFIFOEmpty = '1' or iRBRRead = '1' or iRXFIFOWrite = '1') then
iTimeoutCount <= (others => '0');
elsif (iRXFIFOEmpty = '0' and iBaudtick2x = '1' and iTimeoutCount(5) = '0') then
iTimeoutCount <= iTimeoutCount + 1;
end if;
-- Timeout indication
if (iFCR_FIFOEnable = '1') then
if (iRBRRead = '1') then
iCharTimeout <= '0';
elsif (iTimeoutCount(5) = '1') then
iCharTimeout <= '1';
end if;
else
iCharTimeout <= '0';
end if;
end if;
end process;
-- FIFO control register
UART_FCR: process (CLK, RST)
begin
if (RST = '1') then
iFCR_FIFOEnable <= '0';
iFCR_RXFIFOReset <= '0';
iFCR_TXFIFOReset <= '0';
iFCR_DMAMode <= '0';
iFCR_FIFO64E <= '0';
iFCR_RXTrigger <= (others => '0');
elsif (CLK'event and CLK = '1') then
-- FIFO reset pulse only
iFCR_RXFIFOReset <= '0';
iFCR_TXFIFOReset <= '0';
if (iFCRWrite = '1') then
iFCR_FIFOEnable <= iDIN(0);
iFCR_DMAMode <= iDIN(3);
iFCR_RXTrigger <= iDIN(7 downto 6);
if (iLCR_DLAB = '1') then
iFCR_FIFO64E <= iDIN(5);
end if;
-- RX FIFO reset control, reset on FIFO enable/disable
if (iDIN(1) = '1' or (iFCR_FIFOEnable = '0' and iDIN(0) = '1') or (iFCR_FIFOEnable = '1' and iDIN(0) = '0')) then
iFCR_RXFIFOReset <= '1';
end if;
-- TX FIFO reset control, reset on FIFO enable/disable
if (iDIN(2) = '1' or (iFCR_FIFOEnable = '0' and iDIN(0) = '1') or (iFCR_FIFOEnable = '1' and iDIN(0) = '0')) then
iFCR_TXFIFOReset <= '1';
end if;
end if;
end if;
end process;
iFCR(0) <= iFCR_FIFOEnable;
iFCR(1) <= iFCR_RXFIFOReset;
iFCR(2) <= iFCR_TXFIFOReset;
iFCR(3) <= iFCR_DMAMode;
iFCR(4) <= '0';
iFCR(5) <= iFCR_FIFO64E;
iFCR(7 downto 6) <= iFCR_RXTrigger;
-- Line control register
UART_LCR: process (CLK, RST)
begin
if (RST = '1') then
iLCR <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iLCRWrite = '1') then
iLCR <= iDIN;
end if;
end if;
end process;
iLCR_WLS <= iLCR(1 downto 0);
iLCR_STB <= iLCR(2);
iLCR_PEN <= iLCR(3);
iLCR_EPS <= iLCR(4);
iLCR_SP <= iLCR(5);
iLCR_BC <= iLCR(6);
iLCR_DLAB <= iLCR(7);
-- Modem control register
UART_MCR: process (CLK, RST)
begin
if (RST = '1') then
iMCR(5 downto 0) <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iMCRWrite = '1') then
iMCR(5 downto 0) <= iDIN(5 downto 0);
end if;
end if;
end process;
iMCR_DTR <= iMCR(0);
iMCR_RTS <= iMCR(1);
iMCR_OUT1 <= iMCR(2);
iMCR_OUT2 <= iMCR(3);
iMCR_LOOP <= iMCR(4);
iMCR_AFE <= iMCR(5);
iMCR(6) <= '0';
iMCR(7) <= '0';
-- Line status register
UART_LSR: process (CLK, RST)
begin
if (RST = '1') then
iLSR_OE <= '0';
iLSR_PE <= '0';
iLSR_FE <= '0';
iLSR_BI <= '0';
iFECounter <= 0;
elsif (CLK'event and CLK = '1') then
-- Overrun error
if ((iFCR_FIFOEnable = '0' and iLSR_DR = '1' and iRXFinished = '1') or
(iFCR_FIFOEnable = '1' and iRXFIFOFull = '1' and iRXFinished = '1')) then
iLSR_OE <= '1';
elsif (iLSRRead = '1') then
iLSR_OE <= '0';
end if;
-- Parity error
if (iPERE = '1') then
iLSR_PE <= '1';
elsif (iLSRRead = '1') then
iLSR_PE <= '0';
end if;
-- Frame error
if (iFERE = '1') then
iLSR_FE <= '1';
elsif (iLSRRead = '1') then
iLSR_FE <= '0';
end if;
-- Break interrupt
if (iBIRE = '1') then
iLSR_BI <= '1';
elsif (iLSRRead = '1') then
iLSR_BI <= '0';
end if;
-- FIFO error
-- Datasheet: Cleared by LSR read when no subsequent errors in FIFO
-- Observed: Cleared when no subsequent errors in FIFO
if (iFECounter /= 0) then
iLSR_FIFOERR <= '1';
--elsif (iLSRRead = '1' and iFECounter = 0 and not (iRXFIFOEmpty = '0' and iRXFIFOQ(10 downto 8) /= "000")) then
elsif (iRXFIFOEmpty = '1' or iRXFIFOQ(10 downto 8) = "000") then
iLSR_FIFOERR <= '0';
end if;
-- FIFO error counter
if (iRXFIFOClear = '1') then
iFECounter <= 0;
else
if (iFEIncrement = '1' and iFEDecrement = '0') then
iFECounter <= iFECounter + 1;
elsif (iFEIncrement = '0' and iFEDecrement = '1') then
iFECounter <= iFECounter - 1;
end if;
end if;
end if;
end process;
iRXFIFOPE <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(8) = '1' else '0';
iRXFIFOFE <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(9) = '1' else '0';
iRXFIFOBI <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(10) = '1' else '0';
UART_PEDET: slib_edge_detect port map (CLK, RST, iRXFIFOPE, iPERE);
UART_FEDET: slib_edge_detect port map (CLK, RST, iRXFIFOFE, iFERE);
UART_BIDET: slib_edge_detect port map (CLK, RST, iRXFIFOBI, iBIRE);
iFEIncrement <= '1' when iRXFIFOWrite = '1' and iRXFIFOD(10 downto 8) /= "000" else '0';
iFEDecrement <= '1' when iFECounter /= 0 and iRXFIFOEmpty = '0' and (iPERE = '1' or iFERE = '1' or iBIRE = '1') else '0';
iLSR(0) <= iLSR_DR;
iLSR(1) <= iLSR_OE;
iLSR(2) <= iLSR_PE;
iLSR(3) <= iLSR_FE;
iLSR(4) <= iLSR_BI;
iLSR(5) <= iLSR_THRE;
iLSR(6) <= iLSR_TEMT;
iLSR(7) <= '1' when iFCR_FIFOEnable = '1' and iLSR_FIFOERR = '1' else '0';
iLSR_DR <= '1' when iRXFIFOEmpty = '0' or iRXFIFOWrite = '1' else '0';
iLSR_THRE <= '1' when iTXFIFOEmpty = '1' else '0';
iLSR_TEMT <= '1' when iTXRunning = '0' and iLSR_THRE = '1' else '0';
-- Modem status register
iMSR_CTS <= '1' when (iMCR_LOOP = '1' and iRTS = '1') or (iMCR_LOOP = '0' and iCTSn = '0') else '0';
iMSR_DSR <= '1' when (iMCR_LOOP = '1' and iMCR_DTR = '1') or (iMCR_LOOP = '0' and iDSRn = '0') else '0';
iMSR_RI <= '1' when (iMCR_LOOP = '1' and iMCR_OUT1 = '1') or (iMCR_LOOP = '0' and iRIn = '0') else '0';
iMSR_DCD <= '1' when (iMCR_LOOP = '1' and iMCR_OUT2 = '1') or (iMCR_LOOP = '0' and iDCDn = '0') else '0';
-- Edge detection for CTS, DSR, DCD and RI
UART_ED_CTS: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_CTS, RE => iCTSnRE, FE => iCTSnFE);
UART_ED_DSR: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_DSR, RE => iDSRnRE, FE => iDSRnFE);
UART_ED_RI: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_RI, RE => iRInRE, FE => iRInFE);
UART_ED_DCD: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_DCD, RE => iDCDnRE, FE => iDCDnFE);
UART_MSR: process (CLK, RST)
begin
if (RST = '1') then
iMSR_dCTS <= '0';
iMSR_dDSR <= '0';
iMSR_TERI <= '0';
iMSR_dDCD <= '0';
elsif (CLK'event and CLK = '1') then
-- Delta CTS
if (iCTSnRE = '1' or iCTSnFE = '1') then
iMSR_dCTS <= '1';
elsif (iMSRRead = '1') then
iMSR_dCTS <= '0';
end if;
-- Delta DSR
if (iDSRnRE = '1' or iDSRnFE = '1') then
iMSR_dDSR <= '1';
elsif (iMSRRead = '1') then
iMSR_dDSR <= '0';
end if;
-- Trailing edge RI
if (iRInFE = '1') then
iMSR_TERI <= '1';
elsif (iMSRRead = '1') then
iMSR_TERI <= '0';
end if;
-- Delta DCD
if (iDCDnRE = '1' or iDCDnFE = '1') then
iMSR_dDCD <= '1';
elsif (iMSRRead = '1') then
iMSR_dDCD <= '0';
end if;
end if;
end process;
iMSR(0) <= iMSR_dCTS;
iMSR(1) <= iMSR_dDSR;
iMSR(2) <= iMSR_TERI;
iMSR(3) <= iMSR_dDCD;
iMSR(4) <= iMSR_CTS;
iMSR(5) <= iMSR_DSR;
iMSR(6) <= iMSR_RI;
iMSR(7) <= iMSR_DCD;
-- Scratch register
UART_SCR: process (CLK, RST)
begin
if (RST = '1') then
iSCR <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iSCRWrite = '1') then
iSCR <= iDIN;
end if;
end if;
end process;
-- Baudrate generator
iBaudgenDiv <= iDLM & iDLL;
UART_BG16: uart_baudgen port map (CLK => CLK,
RST => RST,
CE => BAUDCE,
CLEAR => '0',
DIVIDER => iBaudgenDiv,
BAUDTICK => iBaudtick16x
);
UART_BG2: slib_clock_div generic map (RATIO => 8)
port map (CLK => CLK,
RST => RST,
CE => iBaudtick16x,
Q => iBaudtick2x
);
UART_RCLK: slib_edge_detect port map (CLK => CLK,
RST => RST,
D => RCLK,
RE => iRCLK
);
-- Transmitter FIFO
UART_TXFF: slib_fifo generic map (WIDTH => 8, SIZE_E => 6)
port map (CLK => CLK,
RST => RST,
CLEAR => iTXFIFOClear,
WRITE => iTXFIFOWrite,
READ => iTXFIFORead,
D => iDIN,
Q => iTXFIFOQ,
EMPTY => iTXFIFOEmpty,
FULL => iTXFIFO64Full,
USAGE => iTXFIFOUsage
);
-- Transmitter FIFO inputs
iTXFIFO16Full <= iTXFIFOUsage(4);
iTXFIFOFull <= iTXFIFO16Full when iFCR_FIFO64E = '0' else iTXFIFO64Full;
iTXFIFOWrite <= '1' when ((iFCR_FIFOEnable = '0' and iTXFIFOEmpty = '1') or (iFCR_FIFOEnable = '1' and iTXFIFOFull = '0')) and iTHRWrite = '1' else '0';
iTXFIFOClear <= '1' when iFCR_TXFIFOReset = '1' else '0';
-- Receiver FIFO
UART_RXFF: slib_fifo generic map (WIDTH => 11, SIZE_E => 6)
port map (CLK => CLK,
RST => RST,
CLEAR => iRXFIFOClear,
WRITE => iRXFIFOWrite,
READ => iRXFIFORead,
D => iRXFIFOD,
Q => iRXFIFOQ,
EMPTY => iRXFIFOEmpty,
FULL => iRXFIFO64Full,
USAGE => iRXFIFOUsage
);
-- Receiver FIFO inputs
iRXFIFORead <= '1' when iRBRRead = '1' else '0';
iRXFIFO16Full <= iRXFIFOUsage(4);
iRXFIFOFull <= iRXFIFO16Full when iFCR_FIFO64E = '0' else iRXFIFO64Full;
-- Receiver FIFO outputs
iRBR <= iRXFIFOQ(7 downto 0);
-- FIFO trigger level: 1, 4, 8, 14
iRXFIFO16Trigger <= '1' when (iFCR_RXTrigger = "00" and iRXFIFOEmpty = '0') or
(iFCR_RXTrigger = "01" and (iRXFIFOUsage(2) = '1' or iRXFIFOUsage(3) = '1')) or
(iFCR_RXTrigger = "10" and iRXFIFOUsage(3) = '1') or
(iFCR_RXTrigger = "11" and iRXFIFOUsage(3) = '1' and iRXFIFOUsage(2) = '1' and iRXFIFOUsage(1) = '1') or
iRXFIFO16Full = '1' else '0';
-- FIFO 64 trigger level: 1, 16, 32, 56
iRXFIFO64Trigger <= '1' when (iFCR_RXTrigger = "00" and iRXFIFOEmpty = '0') or
(iFCR_RXTrigger = "01" and (iRXFIFOUsage(4) = '1' or iRXFIFOUsage(5) = '1')) or
(iFCR_RXTrigger = "10" and iRXFIFOUsage(5) = '1') or
(iFCR_RXTrigger = "11" and iRXFIFOUsage(5) = '1' and iRXFIFOUsage(4) = '1' and iRXFIFOUsage(3) = '1') or
iRXFIFO64Full = '1' else '0';
iRXFIFOTrigger <= iRXFIFO16Trigger when iFCR_FIFO64E = '0' else iRXFIFO64Trigger;
-- Transmitter
UART_TX: uart_transmitter port map (CLK => CLK,
RST => RST,
TXCLK => iBaudtick2x,
TXSTART => iTXStart,
CLEAR => iTXClear,
WLS => iLCR_WLS,
STB => iLCR_STB,
PEN => iLCR_PEN,
EPS => iLCR_EPS,
SP => iLCR_SP,
BC => iLCR_BC,
DIN => iTSR,
TXFINISHED => iTXFinished,
SOUT => iSOUT
);
iTXClear <= '0';
-- Receiver
UART_RX: uart_receiver port map (CLK => CLK,
RST => RST,
RXCLK => iRCLK,
RXCLEAR => iRXClear,
WLS => iLCR_WLS,
STB => iLCR_STB,
PEN => iLCR_PEN,
EPS => iLCR_EPS,
SP => iLCR_SP,
SIN => iSIN,
PE => iRXPE,
FE => iRXFE,
BI => iRXBI,
DOUT => iRXData,
RXFINISHED => iRXFinished
);
iRXClear <= '0';
iSIN <= iSINr when iMCR_LOOP = '0' else iSOUT;
-- Transmitter enable signal
-- TODO: Use iCTSNs instead of iMSR_CTS? Input filter increases delay for Auto-CTS recognition.
iTXEnable <= '1' when iTXFIFOEmpty = '0' and (iMCR_AFE = '0' or (iMCR_AFE = '1' and iMSR_CTS = '1')) else '0';
-- Transmitter process
UART_TXPROC: process (CLK, RST)
type state_type is (IDLE, TXSTART, TXRUN, TXEND);
variable State : state_type;
begin
if (RST = '1') then
State := IDLE;
iTSR <= (others => '0');
iTXStart <= '0';
iTXFIFORead <= '0';
iTXRunning <= '0';
elsif (CLK'event and CLK = '1') then
-- Defaults
iTXStart <= '0';
iTXFIFORead <= '0';
iTXRunning <= '0';
case State is
when IDLE => if (iTXEnable = '1') then
iTXStart <= '1'; -- Start transmitter
State := TXSTART;
else
State := IDLE;
end if;
when TXSTART => iTSR <= iTXFIFOQ;
iTXStart <= '1'; -- Start transmitter
iTXFIFORead <= '1'; -- Increment TX FIFO read counter
State := TXRUN;
when TXRUN => if (iTXFinished = '1') then -- TX finished
State := TXEND;
else
State := TXRUN;
end if;
iTXRunning <= '1';
iTXStart <= '1';
when TXEND => State := IDLE;
when others => State := IDLE;
end case;
end if;
end process;
-- Receiver process
UART_RXPROC: process (CLK, RST)
type state_type is (IDLE, RXSAVE);
variable State : state_type;
begin
if (RST = '1') then
State := IDLE;
iRXFIFOWrite <= '0';
iRXFIFOClear <= '0';
iRXFIFOD <= (others => '0');
elsif (CLK'event and CLK = '1') then
-- Defaults
iRXFIFOWrite <= '0';
iRXFIFOClear <= iFCR_RXFIFOReset;
case State is
when IDLE => if (iRXFinished = '1') then -- Receive finished
iRXFIFOD <= iRXBI & iRXFE & iRXPE & iRXData;
if (iFCR_FIFOEnable = '0') then
iRXFIFOClear <= '1'; -- Non-FIFO mode
end if;
State := RXSAVE;
else
State := IDLE;
end if;
when RXSAVE => if (iFCR_FIFOEnable = '0') then
iRXFIFOWrite <= '1'; -- Non-FIFO mode: Overwrite
elsif (iRXFIFOFull = '0') then
iRXFIFOWrite <= '1'; -- FIFO mode
end if;
State := IDLE;
when others => State := IDLE;
end case;
end if;
end process;
-- Automatic flow control
UART_AFC: process (CLK, RST)
begin
if (RST = '1') then
iRTS <= '0';
elsif (CLK'event and CLK = '1') then
if (iMCR_RTS = '0' or (iMCR_AFE = '1' and iRXFIFOTrigger = '1')) then
-- Deassert when MCR_RTS is not set or AFC is enabled and the RX FIFO trigger level is reached
iRTS <= '0';
elsif (iMCR_RTS = '1' and (iMCR_AFE = '0' or (iMCR_AFE = '1' and iRXFIFOEmpty = '1'))) then
-- Assert when MCR_RTS is set and AFC is disabled or when AFC is enabled and the RX FIFO is empty
iRTS <= '1';
end if;
end if;
end process;
-- Output registers
UART_OUTREGS: process (CLK, RST)
begin
if (RST = '1') then
DDIS <= '1';
BAUDOUTN <= '1';
OUT1N <= '1';
OUT2N <= '1';
RTSN <= '1';
DTRN <= '1';
SOUT <= '1';
elsif (CLK'event and CLK = '1') then
-- Default values
DDIS <= '0';
BAUDOUTN <= '0';
OUT1N <= '0';
OUT2N <= '0';
RTSN <= '0';
DTRN <= '0';
SOUT <= '0';
-- DDIS
if (CS = '0' or RD = '0') then
DDIS <= '1';
end if;
-- BAUDOUTN
if (iBaudtick16x = '0') then
BAUDOUTN <= '1';
end if;
-- OUT1N
if (iMCR_LOOP = '1' or iMCR_OUT1 = '0') then
OUT1N <= '1';
end if;
-- OUT2N
if (iMCR_LOOP = '1' or iMCR_OUT2 = '0') then
OUT2N <= '1';
end if;
-- RTS
if (iMCR_LOOP = '1' or iRTS = '0') then
RTSN <= '1';
end if;
-- DTR
if (iMCR_LOOP = '1' or iMCR_DTR = '0') then
DTRN <= '1';
end if;
-- SOUT
if (iMCR_LOOP = '1' or iSOUT = '1') then
SOUT <= '1';
end if;
end if;
end process;
-- UART data output
UART_DOUT: process (A, iLCR_DLAB, iRBR, iDLL, iDLM, iIER, iIIR, iLCR, iMCR, iLSR, iMSR, iSCR)
begin
case A is
when "000" => if (iLCR_DLAB = '0') then
DOUT <= iRBR;
else
DOUT <= iDLL;
end if;
when "001" => if (iLCR_DLAB = '0') then
DOUT <= iIER;
else
DOUT <= iDLM;
end if;
when "010" => DOUT <= iIIR;
when "011" => DOUT <= iLCR;
when "100" => DOUT <= iMCR;
when "101" => DOUT <= iLSR;
when "110" => DOUT <= iMSR;
when "111" => DOUT <= iSCR;
when others => DOUT <= iRBR;
end case;
end process;
end rtl;
|
gpl-3.0
|
8a3bc11f837780fa93b4c8dabdd513c6
| 0.42788 | 4.680491 | false | false | false | false |
wgml/sysrek
|
skin_color_segm/ipcore_dir/delayLineBRAM/example_design/delayLineBRAM_exdes.vhd
| 2 | 4,641 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: delayLineBRAM_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY delayLineBRAM_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END delayLineBRAM_exdes;
ARCHITECTURE xilinx OF delayLineBRAM_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT delayLineBRAM IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : delayLineBRAM
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
gpl-2.0
|
200af85a4d11883c0540ef1d1d7e9f8e
| 0.570998 | 4.819315 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/serport/tb/tb_serport_autobaud.vhd
| 1 | 8,826 |
-- $Id: tb_serport_autobaud.vhd 417 2011-10-22 10:30:29Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_serport_autobaud - sim
-- Description: Test bench for serport_autobaud
--
-- Dependencies: simlib/simclk
-- tbd_serport_autobaud [UUT]
--
-- To test: serport_autobaud
--
-- Target Devices: generic
--
-- Verified (with tb_serport_autobaud_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2007-11-02 93 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-21 91 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-10-21 91 - 0.26 - - c:ok
-- 2007-10-14 89 - 0.26 - - c:ok
-- 2007-10-12 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-10-12 88 - 0.26 - - c:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 417 1.1.3 now numeric_std clean
-- 2010-04-24 281 1.1.2 use direct instatiation for tbd_
-- 2008-03-24 129 1.1.1 CLK_CYCLE now 31 bits
-- 2007-10-21 91 1.1 now use 'send' command, self-checking (FAIL's)
-- 2007-10-14 89 1.1 add extra stop bit for CLKDIV=0; drop c2out wait;
-- add moni for autobauder
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.serport.all;
entity tb_serport_autobaud is
end tb_serport_autobaud;
architecture sim of tb_serport_autobaud is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal RXSD : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKDIV : slv13 := (others=>'0');
signal ABACT : slbit := '0';
signal ABDONE : slbit := '0';
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXSD2 : slbit := '0';
signal RXDATA3 : slv8 := (others=>'0');
signal RXVAL3 : slbit := '0';
signal RXERR3 : slbit := '0';
signal RXACT3 : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : slv31 := (others=>'0');
signal N_MON_VAL : slbit := '0';
signal N_MON_DAT : slv8 := (others=>'0');
signal R_MON_VAL_1 : slbit := '0';
signal R_MON_DAT_1 : slv8 := (others=>'0');
signal R_MON_VAL_2 : slbit := '0';
signal R_MON_DAT_2 : slv8 := (others=>'0');
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 10 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
CLK_STOP => CLK_STOP
);
UUT : entity work.tbd_serport_autobaud
port map (
CLK => CLK,
RESET => RESET,
RXSD => RXSD,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CLKDIV => CLKDIV,
ABACT => ABACT,
ABDONE => ABDONE,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD2 => TXSD2,
RXDATA3 => RXDATA3,
RXVAL3 => RXVAL3,
RXERR3 => RXERR3,
RXACT3 => RXACT3
);
proc_stim: process
file fstim : text open read_mode is "tb_serport_autobaud_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable irate : integer := 16;
variable ival : slbit;
variable itxdata : slv8 := (others=>'0');
begin
RXSD <= '1';
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".break" => -- .break
read_ea(iline, idelta);
write(oline, string'(".break"));
writeline(output, oline);
RXSD <= '0';
wait for idelta*clock_period;
RXSD <= '1';
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".rate " => -- .rate
read_ea(iline, irate);
when "send " => -- send
read_ea(iline, ival);
read_ea(iline, itxdata);
writetimestamp(oline, CLK_CYCLE, ": send ");
write(oline, itxdata, right, 10);
writeline(output, oline);
RXSD <= '0'; -- start bit
N_MON_VAL <= ival;
N_MON_DAT <= itxdata;
wait for clock_period;
N_MON_VAL <= '0';
wait for (irate-1)*clock_period;
RXSD <= '1';
for i in itxdata'reverse_range loop -- transmit lsb first
RXSD <= itxdata(i); -- data bit
wait for irate*clock_period;
end loop;
RXSD <= '1'; -- stop bit (plus extra cycle)
wait for (irate+1)*clock_period;
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
end loop;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait for 25*irate*clock_period;
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
variable iabact : slbit := '0';
begin
loop
wait until rising_edge(CLK);
if R_MON_VAL_1 = '1' then
if R_MON_VAL_2 = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, string'(" FAIL MISSING DATA="));
write(oline, R_MON_DAT_2);
writeline(output, oline);
end if;
R_MON_VAL_2 <= R_MON_VAL_1;
R_MON_DAT_2 <= R_MON_DAT_1;
end if;
R_MON_VAL_1 <= N_MON_VAL;
R_MON_DAT_1 <= N_MON_DAT;
if (ABACT xor iabact)='1' then
writetimestamp(oline, CLK_CYCLE, ": auto ABACT =");
write(oline, ABACT, right, 2);
iabact := ABACT;
writeline(output, oline);
end if;
if ABDONE = '1' then
writetimestamp(oline, CLK_CYCLE, ": auto CLKDIV =");
write(oline, to_integer(unsigned(CLKDIV)), right, 3);
writeline(output, oline);
end if;
if RXVAL='1' or (ABACT='0' and RXERR='1' and unsigned(RXDATA)/=0) then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, RXDATA, right, 10);
if RXERR = '1' then
write(oline, string'(" RXERR=1"));
end if;
if R_MON_VAL_2 = '0' then
write(oline, string'(" FAIL UNEXPECTED"));
else
write(oline, string'(" CHECK"));
R_MON_VAL_2 <= '0';
if R_MON_DAT_2 = RXDATA and
RXERR='0' then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL"));
end if;
end if;
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;
|
gpl-2.0
|
75b0eafa4e5d58e4eb29bff2eb8aaee3
| 0.517335 | 3.744591 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/rlink/rlink_mon.vhd
| 1 | 4,716 |
-- $Id: rlink_mon.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_mon - sim
-- Description: rlink monitor (for tb's)
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 3.0.2 now numeric_std clean
-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.0 renamed rritb_cpmon -> rlink_mon
-- 2010-06-11 303 2.5.1 fix data9 assignment, always proper width now
-- 2010-06-07 302 2.5 use sop/eop framing instead of soc+chaining
-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.rlinklib.all;
entity rlink_mon is -- rlink monitor
generic (
DWIDTH : positive := 9); -- data port width (8 or 9)
port (
CLK : in slbit; -- clock
CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : in slbit -- rlink: data hold
);
end rlink_mon;
architecture sim of rlink_mon is
begin
assert DWIDTH=8 or DWIDTH=9
report "assert(DWIDTH=8 or DWIDTH=9)" severity failure;
proc_moni: process
variable oline : line;
variable nbusy : integer := 0;
variable nhold : integer := 0;
procedure write_val(L: inout line;
data: in slv(DWIDTH-1 downto 0);
nwait: in integer;
txt1: in string;
txt2: in string) is
variable data9 : slv9 := (others=>'0');
begin
writetimestamp(L, CLK_CYCLE, txt1);
if DWIDTH = 9 then
write(L, data(data'left), right, 1);
else
write(L, string'(" "));
end if;
write(L, data(7 downto 0), right, 9);
if nwait > 0 then
write(L, txt2);
write(L, nwait);
end if;
if DWIDTH=9 and data(data'left)='1' then
-- a copy to data9 needed to allow following case construct
-- using data directly gives a 'subtype is not locally static' error
data9 := (others=>'0');
data9(data'range) := data;
write(L, string'(" comma"));
case data9 is
when c_rlink_dat_idle => write(L, string'(" idle"));
when c_rlink_dat_sop => write(L, string'(" sop"));
when c_rlink_dat_eop => write(L, string'(" eop"));
when c_rlink_dat_nak => write(L, string'(" nak"));
when c_rlink_dat_attn => write(L, string'(" attn"));
when others => null;
end case;
end if;
writeline(output, L);
end procedure write_val;
begin
loop
if ENA='0' then -- if disabled
wait until ENA='1'; -- stall process till enabled
end if;
wait until rising_edge(CLK); -- check at end of clock cycle
if RL_ENA = '1' then
if RL_BUSY = '1' then
nbusy := nbusy + 1;
else
write_val(oline, RL_DI, nbusy, ": rlrx ", " nbusy=");
nbusy := 0;
end if;
else
nbusy := 0;
end if;
if RL_VAL = '1' then
if RL_HOLD = '1' then
nhold := nhold + 1;
else
write_val(oline, RL_DO, nhold, ": rltx ", " nhold=");
nhold := 0;
end if;
else
nhold := 0;
end if;
end loop;
end process proc_moni;
end sim;
|
gpl-2.0
|
09b3f0edfced50a5247ad090c2782b85
| 0.534987 | 3.701727 | false | false | false | false |
wgml/sysrek
|
skin_color_segm/ipcore_dir/BINARYZACJA/simulation/BINARYZACJA_tb_synth.vhd
| 4 | 7,106 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: BINARYZACJA_tb_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BINARYZACJA_TB_PKG.ALL;
ENTITY BINARYZACJA_tb_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 0
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END BINARYZACJA_tb_synth;
ARCHITECTURE BINARYZACJA_synth_ARCH OF BINARYZACJA_tb_synth IS
COMPONENT BINARYZACJA_exdes
PORT (
CLK : IN STD_LOGIC := '0';
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0')
);
END COMPONENT;
CONSTANT STIM_CNT : INTEGER := if_then_else(C_ROM_SYNTH = 0, 8, 22);
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i : STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ADDR: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDR_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL QSPO: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL QSPO_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BINARYZACJA_TB_STIM_GEN_INST:ENTITY work.BINARYZACJA_TB_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
A => ADDR,
DATA_IN => QSPO_R,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(STIM_CNT);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDR(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW + 1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
QSPO_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
QSPO_R <= QSPO AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDR_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDR_R <= ADDR AFTER 50 ns;
END IF;
END IF;
END PROCESS;
DMG_PORT: BINARYZACJA_exdes PORT MAP (
CLK => CLKA,
QSPO => QSPO,
A => ADDR_R
);
END ARCHITECTURE;
|
gpl-2.0
|
cf7e436a2f17f92bf7ba7ea790bd3955
| 0.572052 | 3.853579 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/w11a/avmb/tb/sys_conf_sim.vhd
| 1 | 3,165 |
-- $Id$
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_mb (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.4; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-02-24 ??? 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1; -- no dcm in sim...
-- constant sys_conf_memctl_read0delay : positive := 5;
-- constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
-- constant sys_conf_memctl_writedelay : positive := 5;
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- constant sys_conf_bram : integer := 0; -- no bram, use cache
-- constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
-- constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug)
constant sys_conf_bram : integer := 1; -- bram only
constant sys_conf_bram_awidth : integer := 15; -- bram size (32 kB)
constant sys_conf_mem_losize : integer := 8#000777#; -- 32 kByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
-- derived constants
constant sys_conf_clksys : integer :=
(40000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
end package sys_conf;
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
-- 2 211 111 111 110 000 000 000
-- 1 098 765 432 109 876 543 210
--
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
-- upper 256 kB excluded for 11/70 UB
|
gpl-2.0
|
56914ea0940f121cf3f060a50e3536a4
| 0.604423 | 3.741135 | false | false | false | false |
Kolchuzhin/LMGT_MEMS_component_library
|
Spiegel/spiegel.vhd
| 1 | 2,749 |
-------------------------------------------------------------------------------
-- Model: Spiegel (analytical model of micromirror)
--
-- Author: Jan E. Mehner, LMGT, ET/IT, TU Chemnitz
-- www.tu-chemnitz.de/etit/microsys/
-- Date:
-- Library: kvl in hAMSter
-------------------------------------------------------------------------------
-- ID: spiegel.vhd
--
-- Revision:
-- Revision 1.0 - porting a code to Simplorer by Vladimir Kolchuzhin
-- 23.02.2015 GitHub
--
-- Status: Compile OK, model was compiled with hAMSter simulator
-------------------------------------------------------------------------------
LIBRARY ieee;
--LIBRARY user; -- Simplorer
USE ieee.math_real.all;
use work.electromagnetic_system.all; -- hAMSter
--USE ieee.electrical_systems.ALL; -- Simplorer
--USE ieee.mechanical_systems.ALL; -- Simplorer
ENTITY Spiegel IS
port (terminal elec1,elec2,elec3:electrical;
terminal struc1,struc2:translational); -- mechanical -> translational
--terminal struc1:translational; -- Simplorer
--terminal struc2:rotational); -- Simplorer
END ENTITY Spiegel;
-------------------------------------------------------------------------------
ARCHITECTURE basic OF Spiegel IS
quantity v1 across i1 through elec1;
quantity v2 across i2 through elec2;
quantity v3 across i3 through elec3;
quantity u1 across f1 through struc1;
quantity u2 across f2 through struc2;
constant eps:real:=8.85e-12;
constant m:real:=4.658e-8;
constant J:real:=3.8832e-15;
constant Kuz:real:=1.9108e+5;
constant Krx:real:=2.7945e-5;
constant d1:real:=0.0094;
constant d2:real:=3.2942e-11;
constant aeps:real:=3.54e-18;
constant egap:real:=90.0e-6;
constant e_di:real:=200.0e-6;
constant b:real:=1000.0e-6;
quantity cap1:real;
quantity cap2:real;
quantity dcap12_t:real;
quantity dcap13_t:real;
quantity dcap12_r:real;
quantity dcap13_r:real;
BEGIN
f1==m*u1'dot'dot + d1*u1'dot + Kuz*u1 - dcap12_t*(v1-v2)**2/2.0 - dcap13_t*(v1-v3)**2/2.0;
f2==J*u2'dot'dot + d2*u2'dot + Krx*u2 - dcap12_r*(v1-v2)**2/2.0 - dcap13_r*(v1-v3)**2/2.0;
i1==(+(v1'dot-v2'dot)*cap1 + (dcap12_t*u1'dot+dcap12_r*u2'dot)*(v1-v2)+(v1'dot-v3'dot)*cap2 + (dcap13_t*u1'dot+dcap13_r*u2'dot)*(v1-v3));
i2==(-(v1'dot-v2'dot)*cap1 - (dcap12_t*u1'dot+dcap12_r*u2'dot)*(v1-v2));
i3==(-(v1'dot-v3'dot)*cap2 - (dcap13_t*u1'dot+dcap13_r*u2'dot)*(v1-v3));
cap1==+aeps/(egap+u1+(b+e_di)*0.25*u2);
cap2==+aeps/(egap+u1-(b+e_di)*0.25*u2);
dcap12_t==-aeps/((egap+u1+(b+e_di)*0.25*u2)**2);
dcap13_t==-aeps/((egap+u1-(b+e_di)*0.25*u2)**2);
dcap12_r==-aeps*0.25*b/((egap+u1+(b+e_di)*0.25*u2)**2);
dcap13_r==+aeps*0.25*b/((egap+u1-(b+e_di)*0.25*u2)**2);
END ARCHITECTURE basic;
|
mit
|
8b723aa3b49e57c633f2c34e6c2b6381
| 0.580211 | 2.703048 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/rbus/rb_mon_sb.vhd
| 1 | 2,754 |
-- $Id: rb_mon_sb.vhd 346 2010-12-22 22:59:26Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rb_mon_sb - sim
-- Description: simbus wrapper for rbus monitor (for tb's)
--
-- Dependencies: simbus
-- Test bench: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-22 346 3.0 renamed rritb_rbmon_sb -> rb_mon_sb
-- 2010-06-05 301 2.0.2 renamed _rpmon -> _rbmon
-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- use sbcntl_sbf_cpmon def
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2007-12-23 105 1.2 added AP_LAM display
-- 2007-11-24 98 1.1 added RP_IINT support
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.rblib.all;
entity rb_mon_sb is -- simbus wrapper for rbus monitor
generic (
DBASE : positive := 2; -- base for writing data values
ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end rb_mon_sb;
architecture sim of rb_mon_sb is
signal ENA : slbit := '0';
begin
assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
report "assert(ENAPIN in SB_CNTL'range)" severity failure;
ENA <= to_x01(SB_CNTL(ENAPIN));
RBMON : rb_mon
generic map (
DBASE => DBASE)
port map (
CLK => CLK,
CLK_CYCLE => SB_CLKCYCLE,
ENA => ENA,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
end sim;
|
gpl-2.0
|
6d4074c5429decce1e828fd27f010f95
| 0.567538 | 3.512755 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega1/CU.vhd
| 1 | 1,007 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CU is
Port ( op : in STD_LOGIC_VECTOR(1 DOWNTO 0);
op3 : in STD_LOGIC_VECTOR(5 DOWNTO 0);
aluop : out STD_LOGIC_VECTOR(5 DOWNTO 0));
end CU;
architecture Behavioral of CU is
begin
process(op, op3)
begin
if(op = "10") then
case op3 is
when "000000" => --Add
aluop <= "000000";
when "000100" => --Sub
aluop <= "000001";
when "000001" => -- And
aluop <= "000010";
when "000101" => --Andn
aluop <= "000011";
when "000010" => --or
aluop <= "000100";
when "000110" => --orn
aluop <= "000101";
when "000011" => --xor
aluop <= "000110";
when "000111" => --xnor
aluop <= "000111";
when others =>
aluop <= (others=>'1');
end case;
else
aluop <= (others=>'1');
end if;
end process;
end Behavioral;
|
mit
|
cc88d1f6c184148ca2224f61b7658312
| 0.486594 | 3.345515 | false | false | false | false |
hdlguy/vivado_tcl
|
source/top.vhd
| 1 | 937 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top is
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
cos : out std_logic_vector(7 downto 0);
sin : out std_logic_vector(7 downto 0));
end top;
architecture rtl of top is
--
signal reset_reg : std_logic;
signal pre_cos, pre_sin : std_logic_vector(7 downto 0);
--
attribute dont_touch : string;
attribute dont_touch of reset_reg : signal is "true";
attribute dont_touch of pre_cos : signal is "true";
attribute dont_touch of pre_sin : signal is "true";
--
begin
regs_proc: process
begin
wait until rising_edge(clk);
reset_reg <= reset;
cos <= pre_cos;
sin <= pre_sin;
end process;
uut: entity work.chirp_gen
port map (
clk => clk,
reset => reset_reg,
cos => pre_cos,
sin => pre_sin);
end rtl;
|
gpl-3.0
|
65a28d772e46041e33f0736d2b28ee06
| 0.55603 | 3.496269 | false | false | false | false |
wgml/sysrek
|
skin_color_segm/ipcore_dir/delayLineBRAM/simulation/delayLineBRAM_tb.vhd
| 2 | 4,352 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: delayLineBRAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY delayLineBRAM_tb IS
END ENTITY;
ARCHITECTURE delayLineBRAM_tb_ARCH OF delayLineBRAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
delayLineBRAM_synth_inst:ENTITY work.delayLineBRAM_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
gpl-2.0
|
419fbc098eb03a20b84e6e5d6a7d2391
| 0.623162 | 4.735582 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/serport/tb/tbd_serport_uart_rxtx.vhd
| 1 | 3,178 |
-- $Id: tbd_serport_uart_rxtx.vhd 417 2011-10-22 10:30:29Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_serport_uart_rxtx - syn
-- Description: Wrapper for serport_uart_rxtx to avoid records. It
-- has a port interface which will not be modified by xst
-- synthesis (no records, no generic port).
--
-- Dependencies: serport_uart_rxtx
--
-- To test: serport_uart_rxtx
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 69 122 0 - t 9.13
-- 2007-10-27 92 9.1 J30 xc3s1000-4 69 122 0 - t 9.13
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 73 152 0 81 s 9.30
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 73 125 0 - s 9.30
--
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2007-10-21 91 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serport.all;
entity tbd_serport_uart_rxtx is -- serial port uart [tb design]
-- generic: CDWIDTH=13
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv13; -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit; -- receiver active
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit -- transmit busy
);
end tbd_serport_uart_rxtx;
architecture syn of tbd_serport_uart_rxtx is
begin
UART : serport_uart_rxtx
generic map (
CDWIDTH => 13)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
end syn;
|
gpl-2.0
|
3946fbc75fd33f2279ceec51e90a648b
| 0.54185 | 3.852121 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_serloop/nexys2/tb/sys_conf2_sim.vhd
| 2 | 1,902 |
-- $Id: sys_conf2_sim.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop2_n2 (for test bench)
--
-- Dependencies: -
-- Tool versions: xst 11.4; ghdl 0.26
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 424 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- in simulation a usec is shortened to 12 cycles (0.2 usec) and a msec
-- to 60 cycles (1 usec). This affects the pulse generators (usec) and
-- mainly the autobauder. A break will be detected after 128 msec periods,
-- this in simulation after 128 usec or 6400 cycles. This is compatible with
-- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles)
constant sys_conf_clkudiv_usecdiv : integer := 20; -- default usec
constant sys_conf_clksdiv_usecdiv : integer := 12; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened !
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
end package sys_conf;
|
gpl-2.0
|
0458dc4195ae1a789572fb46508e1705
| 0.644585 | 4.004211 | false | false | false | false |
alex-gudilko/FPGA-DATA-CONVERTER
|
HDL stimulus files/bcd_testbench.vhd
| 1 | 1,462 |
------------------------------------------------------------------------------
-- Company: <Mehatronika>
-- Author: <Aleksandr Gudilko>
-- Email: [email protected]
--
-- Description:
-- Testbench for integer-to-BCD decoder
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY TB_bcd IS
END TB_bcd;
ARCHITECTURE behavior OF TB_bcd IS
-- Component Declaration for the Unit Under Test (UUT)
component bcd
port(
number : in std_logic_vector(7 downto 0);
hundreds : out std_logic_vector(3 downto 0);
tens : out std_logic_vector(3 downto 0);
ones : out std_logic_vector(3 downto 0)
);
end component;
--Inputs
signal number : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal hundreds : std_logic_vector(3 downto 0);
signal tens : std_logic_vector(3 downto 0);
signal ones : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bcd
port map (
number => number,
hundreds => hundreds,
tens => tens,
ones => ones
);
-- Stimulus process
stim_proc: process
begin
loop
number <= std_logic_vector(unsigned(number) + 1);
wait for 10 ns;
end loop;
wait;
end process;
end;
|
gpl-2.0
|
173d67e8fb8e8d04a1ccf805ec6764ee
| 0.516416 | 4.201149 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Talleres/TallerVhdl/sumador_tb.vhd
| 1 | 2,133 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
-- Create Date: 16:32:32 09/21/2017
-- Project Name: Tarea
-- VHDL Test Bench Created by ISE for module: sumador
-- Dependencies:
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY sumador_tb IS
END sumador_tb;
ARCHITECTURE behavior OF sumador_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sumador
PORT(
value1 : IN std_logic_vector(31 downto 0);
value2 : IN std_logic_vector(31 downto 0);
result : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal value1 : std_logic_vector(31 downto 0) := (others => '0');
signal value2 : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal result : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sumador PORT MAP (
value1 => value1,
value2 => value2,
result => result
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
value1 <= "00000000000000000000000000000100";
value2 <= "00000000000000001110000000000111";
-- insert stimulus here
wait;
end process;
END;
|
mit
|
d20dbaa0b1d7daae7bb290aa5941aaf1
| 0.592124 | 4.317814 | false | true | false | false |
adelapie/noekeon_inner_round
|
noekeon_pipelining_inner_k_3/noekeon.vhd
| 1 | 7,968 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- This is an iterative implementation of the NOEKEON block
-- cipher relying on the direct mode of the cipher. This means that
-- key schedule is not performed.
entity noekeon is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end noekeon;
architecture Behavioral of noekeon is
component round_f is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic;
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component rc_gen is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_out : out std_logic_vector(7 downto 0));
end component;
component output_trans is
port(clk : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component theta is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component rc_shr is
port(clk : in std_logic;
rst : in std_logic;
rc_in : in std_logic_vector(543 downto 0);
rc_out : out std_logic_vector(7 downto 0));
end component;
signal rc_s : std_logic_vector(7 downto 0);
signal rc_ext_s : std_logic_vector(31 downto 0);
signal a_0_in_s : std_logic_vector(31 downto 0);
signal a_1_in_s : std_logic_vector(31 downto 0);
signal a_2_in_s : std_logic_vector(31 downto 0);
signal a_3_in_s : std_logic_vector(31 downto 0);
signal out_t_a_0_in_s : std_logic_vector(31 downto 0);
signal out_t_a_1_in_s : std_logic_vector(31 downto 0);
signal out_t_a_2_in_s : std_logic_vector(31 downto 0);
signal out_t_a_3_in_s : std_logic_vector(31 downto 0);
signal a_0_out_s : std_logic_vector(31 downto 0);
signal a_1_out_s : std_logic_vector(31 downto 0);
signal a_2_out_s : std_logic_vector(31 downto 0);
signal a_3_out_s : std_logic_vector(31 downto 0);
signal k_0_d_s : std_logic_vector(31 downto 0);
signal k_1_d_s : std_logic_vector(31 downto 0);
signal k_2_d_s : std_logic_vector(31 downto 0);
signal k_3_d_s : std_logic_vector(31 downto 0);
signal k_0_mux_s : std_logic_vector(31 downto 0);
signal k_1_mux_s : std_logic_vector(31 downto 0);
signal k_2_mux_s : std_logic_vector(31 downto 0);
signal k_3_mux_s : std_logic_vector(31 downto 0);
signal rc_in_s : std_logic_vector(543 downto 0);
begin
-- rc_in_s <= X"80 1b 36 6c d8 ab 4d 9a 2f 5e bc 63 c6 97 35 6a d4";
rc_in_s <= X"808080801b1b1b1b363636366c6c6c6cd8d8d8d8abababab4d4d4d4d9a9a9a9a2f2f2f2f5e5e5e5ebcbcbcbc63636363c6c6c6c697979797353535356a6a6a6ad4d4d4d4";
--RC_GEN_0 : rc_gen port map (clk, rst, enc, rc_s);
RC_SHR_0: rc_shr port map (clk, rst, rc_in_s, rc_s);
rc_ext_s <= X"000000" & rc_s;
ROUND_F_0 : round_f port map (clk,
rst,
enc,
rc_ext_s,
a_0_in_s,
a_1_in_s,
a_2_in_s,
a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out_s,
a_1_out_s,
a_2_out_s,
a_3_out_s);
pr_noe: process(clk, rst, enc)
begin
if rising_edge(clk) then
if rst = '1' then
a_0_in_s <= a_0_in;
a_1_in_s <= a_1_in;
a_2_in_s <= a_2_in;
a_3_in_s <= a_3_in;
else
a_0_in_s <= a_0_out_s;
a_1_in_s <= a_1_out_s;
a_2_in_s <= a_2_out_s;
a_3_in_s <= a_3_out_s;
end if;
end if;
end process;
-- Key decryption as k' = theta(0, k)
-- This is the key required for decryption
-- in NOEKEON
THETA_DECRYPT_0 : theta port map (
k_0_in,
k_1_in,
k_2_in,
k_3_in,
(others => '0'),
(others => '0'),
(others => '0'),
(others => '0'),
k_0_d_s,
k_1_d_s,
k_2_d_s,
k_3_d_s);
-- These multiplexers select the key that is used
-- in each mode i.e. during decryption the key generated
-- as k' = theta(0, k) (THETA_DECRYPT_0) is utilized.
k_0_mux_s <= k_0_in when enc = '0' else k_0_d_s;
k_1_mux_s <= k_1_in when enc = '0' else k_1_d_s;
k_2_mux_s <= k_2_in when enc = '0' else k_2_d_s;
k_3_mux_s <= k_3_in when enc = '0' else k_3_d_s;
out_trans_pr: process(clk, rst, a_0_out_s, a_1_out_s, a_2_out_s, a_3_out_s)
begin
if rising_edge(clk) then
out_t_a_0_in_s <= a_0_out_s;
out_t_a_1_in_s <= a_1_out_s;
out_t_a_2_in_s <= a_2_out_s;
out_t_a_3_in_s <= a_3_out_s;
end if;
end process;
-- This component performs the last operation
-- with theta.
OUT_TRANS_0 : output_trans port map (clk, enc, rc_ext_s,
out_t_a_0_in_s,
out_t_a_1_in_s,
out_t_a_2_in_s,
out_t_a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out,
a_1_out,
a_2_out,
a_3_out);
end Behavioral;
|
gpl-3.0
|
1fcb35e0ea767b92ea0f03ecf79907c0
| 0.588604 | 2.536772 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega3/windows_manager_arch.vhd
| 1 | 3,080 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Notas:
-- La idea de este modulo es expandir la cantidad de registros disponibles
-- con 5 bits yo solo tengo 2**5 -1 registros. Las ventanas nos dejar ir moviendonos
-- para tener mas ventanas, en nuestra arquitectura de 40 a 520.
-- Los registros globales siempre van a estar en la misma posicion, los unicos que se mueven son los locales,outs, inputs.
--Basado en https://www.educreations.com/lesson/view/procesador-sparc-v8-soportando-windowing/13230159/
-- analizar el estado del psr en los primeros 5 bits que son cwp
--save: cwp<=cwp-1 >> cwp<='0'
--restore: cwp<=cwp+1 >> cwp<='1'
entity windows_manager_arch is
Port (
rst : in std_logic;
rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
CWP : in STD_LOGIC_VECTOR (4 downto 0);
nrs1 : out STD_LOGIC_VECTOR (5 downto 0);
nrs2 : out STD_LOGIC_VECTOR (5 downto 0);
nrd : out STD_LOGIC_VECTOR (5 downto 0);
nCWP : out STD_LOGIC_VECTOR (4 downto 0);
no7 : out STD_LOGIC_VECTOR (5 downto 0)
);
end windows_manager_arch;
architecture Behavioral of windows_manager_arch is
begin
process(rs1, rs2, rd, op, op3, CWP)
begin
no7 <= conv_std_logic_vector(15 + (conv_integer(cwp) * 16), 6);
--save
if(op = "10" and op3 = "111100")then
nCWP <= "0000";
end if;
--restore
if(op = "10" and op3 = "111101")then
nCWP <= "1111";
end if;
--si es locales y salida, usa la logica del video:
-- 10 y 23
if (rs1 >= "01000" and rs1 <= "10111") then
nrs1 <= conv_std_logic_vector(conv_integer(rs1) + (conv_integer(cwp) * 16), 6);
end if;
if (rs2 >= "01000" and rs2 <= "10111") then
nrs2 <= conv_std_logic_vector(conv_integer(rs2) + (conv_integer(cwp) * 16), 6);
end if;
if (rd >= "01000" and rd <= "10111") then
nrd <= conv_std_logic_vector(conv_integer(rd) + (conv_integer(cwp) * 16), 6);
end if;
--si es entrada
if (rs1 >= "11000" and rs1 <= "11111") then
nrs1 <= conv_std_logic_vector(conv_integer(rs1) - (conv_integer(cwp) * 16), 6);
end if;
if (rs2 >= "11000" and rs2 <= "11111") then
nrs2 <= conv_std_logic_vector(conv_integer(rs2) - (conv_integer(cwp) * 16), 6);
end if;
if (rd >= "11000" and rd <= "11111") then
nrd <= conv_std_logic_vector(conv_integer(rd) - (conv_integer(cwp) * 16), 6);
end if;
--si son globales esas siempre van a quedar en la misma parte
if (rs1 >= "00000" and rs1 <= "00111") then
nrs1 <= '0' & rs1;
end if;
if (rs2 >= "00000" and rs2 <= "00111") then
nrs2 <= '0' & rs2;
end if;
if (rd >= "00000" and rd <= "00111") then
nrd <= '0' & rd;
end if;
end process;
end Behavioral;
|
mit
|
c160c7913b5554cab9e943f48e2ce01b
| 0.594481 | 3.049505 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/genlib/gray_cnt_5.vhd
| 2 | 4,280 |
-- $Id: gray_cnt_5.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_5 - syn
-- Description: 5 bit Gray code counter (ROM based)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- LUT Flop clock(xst est.)
-- 9 5 302MHz/ 3.31ns
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity gray_cnt_5 is -- 5 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv5 -- data out
);
end entity gray_cnt_5;
architecture syn of gray_cnt_5 is
signal R_DATA : slv5 := (others=>'0');
signal N_DATA : slv5 := (others=>'0');
-- Note: in xst 8.2.03 fsm_extract="no" is needed. Otherwise an fsm
-- is inferred, using 'Johnson' encoding. DATA will be deduced
-- in a combinatorial logic, and will thus have very likely some
-- glitches at the clock transitions, rendering the whole Gray
-- coding useless.
attribute fsm_extract : string;
attribute fsm_extract of R_DATA : signal is "no";
attribute rom_style : string;
attribute rom_style of N_DATA : signal is "distributed";
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_DATA <= (others=>'0');
elsif CE = '1' then
R_DATA <= N_DATA;
end if;
end if;
end process proc_regs;
proc_next: process (R_DATA)
begin
N_DATA <= (others=>'0');
case R_DATA is
when "00000" => N_DATA <= "00001"; -- 0
when "00001" => N_DATA <= "00011"; -- 1
when "00011" => N_DATA <= "00010"; -- 2
when "00010" => N_DATA <= "00110"; -- 3
when "00110" => N_DATA <= "00111"; -- 4
when "00111" => N_DATA <= "00101"; -- 5
when "00101" => N_DATA <= "00100"; -- 6
when "00100" => N_DATA <= "01100"; -- 7
when "01100" => N_DATA <= "01101"; -- 8
when "01101" => N_DATA <= "01111"; -- 9
when "01111" => N_DATA <= "01110"; -- 10
when "01110" => N_DATA <= "01010"; -- 11
when "01010" => N_DATA <= "01011"; -- 12
when "01011" => N_DATA <= "01001"; -- 13
when "01001" => N_DATA <= "01000"; -- 14
when "01000" => N_DATA <= "11000"; -- 15
when "11000" => N_DATA <= "11001"; -- 16
when "11001" => N_DATA <= "11011"; -- 17
when "11011" => N_DATA <= "11010"; -- 18
when "11010" => N_DATA <= "11110"; -- 19
when "11110" => N_DATA <= "11111"; -- 20
when "11111" => N_DATA <= "11101"; -- 21
when "11101" => N_DATA <= "11100"; -- 22
when "11100" => N_DATA <= "10100"; -- 23
when "10100" => N_DATA <= "10101"; -- 24
when "10101" => N_DATA <= "10111"; -- 25
when "10111" => N_DATA <= "10110"; -- 26
when "10110" => N_DATA <= "10010"; -- 27
when "10010" => N_DATA <= "10011"; -- 28
when "10011" => N_DATA <= "10001"; -- 29
when "10001" => N_DATA <= "10000"; -- 30
when "10000" => N_DATA <= "00000"; -- 31
when others => null;
end case;
end process proc_next;
DATA <= R_DATA;
end syn;
|
gpl-2.0
|
fda7ff8d94f8a122262d865810aa7fc6
| 0.516822 | 3.41853 | false | false | false | false |
Azbesciak/digitalTechnology
|
cw13/thirda.vhd
| 1 | 795 |
-- Quartus II VHDL Template
-- Binary Counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity thirda is
port(
clk, enable : in std_logic;
reset: buffer std_logic;
q : out integer range 0 to 64
);
end entity;
architecture rtl of thirda is
component binary_counter_mod_16 is
port(
clk, reset, enable : in std_logic;
q : out integer range 0 to 15;
carry: out std_logic
);
end component;
signal carry : std_logic;
signal a, b: integer range 0 to 16;
begin
coun1 :binary_counter_mod_16 port map(
clk, reset, enable, a, carry
);
coun2 : binary_counter_mod_16 port map(
carry, reset, enable, b
);
q <= b * 16 + a;
process (a, b)
begin
if b = 3 and a = 7 then
reset <= '1';
else reset <= '0';
end if;
end process;
end rtl;
|
mit
|
48117e77d0ae089036e9fcc32e1fe5cc
| 0.65283 | 2.731959 | false | false | false | false |
vhavlena/appreal
|
netbench/pattern_match/vhdl/onehot2binary.vhd
| 1 | 1,847 |
-- ----------------------------------------------------------------------------
-- Entity for conversion from one hot encoding to binary encoding
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity ONEHOT2BINARY is
generic(
INPUT_DATA_WIDTH : integer := 16;
OUTPUT_DATA_WIDTH : integer := 4
);
port(
-- input data interface
INPUT : in std_logic_vector(INPUT_DATA_WIDTH - 1 downto 0);
-- output data interface
OUTPUT : out std_logic_vector(OUTPUT_DATA_WIDTH - 1 downto 0);
VLD : out std_logic
);
end entity ONEHOT2BINARY;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of ONEHOT2BINARY is
begin
one_hot_2_binary: process(INPUT)
variable bin : std_logic_vector(OUTPUT_DATA_WIDTH - 1 downto 0);
begin
bin:= (others => '0');
for i in INPUT_DATA_WIDTH-1 downto 0 loop
if (INPUT(i) = '1') then
bin := conv_std_logic_vector(i, 32);
end if;
end loop;
OUTPUT <= bin;
end process one_hot_2_binary;
generic_or: process(INPUT)
begin
if (INPUT = conv_std_logic_vector(0, INPUT_DATA_WIDTH)) then
VLD <= '0';
else
VLD <= '1';
end if;
end process generic_or;
end architecture full;
|
gpl-2.0
|
ed04b2a8420d9a5e43f29ddd7b3621db
| 0.417975 | 4.899204 | false | false | false | false |
xylnao/w11a-extra
|
rtl/bplib/avmb/tb/tb_avmb_core.vhd
| 1 | 2,008 |
-- $Id$
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_avmb_core - sim
-- Description: Test bench for avmb - core device handling
--
-- To test: generic, any avmb target
--
-- Target Devices: generic
-- Tool versions: xst 13.4; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-02-04 ??? 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serport.all;
use work.simbus.all;
entity tb_avmb_core is
port (
I_SWI : out slv4; -- mb switches
I_BTN : out slv1 -- mb button
);
end tb_avmb_core;
architecture sim of tb_avmb_core is
signal R_SWI : slv4 := (others=>'0');
signal R_BTN : slv1 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
|
gpl-2.0
|
7aa64927aeb24725784aff4f45c24fa9
| 0.593127 | 3.516637 | false | false | false | false |
rogerioag/gcg
|
tutorial/ula/testbench/unidadeLogica_tb.vhd
| 1 | 2,461 |
-- Testebench gerado via script.
-- Data: Sáb,31/12/2011-01:39:29
-- Autor: rogerio
-- Comentario: Teste da entidade unidadeLogica.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity unidadeLogica_tb is
end unidadeLogica_tb;
architecture estrutural of unidadeLogica_tb is
-- Declaração do componente.
component unidadeLogica
port (A, B, OpAND, OpOR, OpNAND, OpNOR, OpXOR, OpXNOR, OpNOT: in <<type>>; S: out <<type>>);
end component;
-- Especifica qual a entidade está vinculada com o componente.
for unidadeLogica_0: unidadeLogica use entity work.unidadeLogica;
signal s_t_A, s_t_B, s_t_OpAND, s_t_OpOR, s_t_OpNAND, s_t_OpNOR, s_t_OpXOR, s_t_OpXNOR, s_t_OpNOT, s_t_S: <<type>>;
begin
-- Instanciação do Componente.
-- port map (<<p_in_1>> => <<s_t_in_1>>)
unidadeLogica_0: unidadeLogica port map ( A=>s_t_A, B=>s_t_B, OpAND=>s_t_OpAND, OpOR=>s_t_OpOR, OpNAND=>s_t_OpNAND, OpNOR=>s_t_OpNOR, OpXOR=>s_t_OpXOR, OpXNOR=>s_t_OpXNOR, OpNOT=>s_t_OpNOT, S=>s_t_S);
-- Processo que faz o trabalho.
process
-- Um registro é criado com as entradas e saídas da entidade.
-- (<<entrada1>>, <<entradaN>>, <<saida1>>, <<saidaN>>)
type pattern_type is record
-- entradas.
vi_A, vi_B, vi_OpAND, vi_OpOR, vi_OpNAND, vi_OpNOR, vi_OpXOR, vi_OpXNOR, vi_OpNOT: <<type>>;
-- saídas.
vo_S: <<type>>;
end record;
-- Os padrões de entrada que são aplicados (injetados) às entradas.
type pattern_array is array (natural range <>) of pattern_type;
-- Casos de teste.
constant patterns : pattern_array :=
(
(casos de testes com 10 colunas, '0'...),
(...)
);
begin
-- Checagem de padrões.
for i in patterns'range loop
-- Injeta as entradas.
s_t_A <= patterns(i).vi_A;
s_t_B <= patterns(i).vi_B;
s_t_OpAND <= patterns(i).vi_OpAND;
s_t_OpOR <= patterns(i).vi_OpOR;
s_t_OpNAND <= patterns(i).vi_OpNAND;
s_t_OpNOR <= patterns(i).vi_OpNOR;
s_t_OpXOR <= patterns(i).vi_OpXOR;
s_t_OpXNOR <= patterns(i).vi_OpXNOR;
s_t_OpNOT <= patterns(i).vi_OpNOT;
-- Aguarda os resultados.
wait for 1 ns;
-- Checa o resultado com a saída esperada no padrão.
assert s_t_S = patterns(i).vo_S report "Valor de s_t_S não confere com o resultado esperado." severity error;
end loop;
assert false report "Fim do teste." severity note;
-- Wait forever; Isto finaliza a simulação.
wait;
end process;
end estrutural;
|
gpl-3.0
|
5243f0cb65eab988262c724d927b7449
| 0.652886 | 2.801606 | false | true | false | false |
xylnao/w11a-extra
|
rtl/vlib/rlink/rlink_core8.vhd
| 2 | 5,364 |
-- $Id: rlink_core8.vhd 440 2011-12-18 20:08:09Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_core8 - syn
-- Description: rlink core with 8bit interface (core+b2c/c2b+rlmon+rbmon)
--
-- Dependencies: rlink_core
-- comlib/byte2cdata
-- comlib/cdata2byte
-- rlink_mon_sb [sim only]
-- rbus/rb_mon_sb [sim only]
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-09 437 13.1 O40d xc3s1000-4 184 403 0 244 s 9.1
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-09 437 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
use work.rblib.all;
use work.rlinklib.all;
entity rlink_core8 is -- rlink core with 8bit interface
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6; -- idle timeout counter width
CPREF : slv4 := c_rlink_cpref; -- comma prefix
ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RBMON : integer := sbcntl_sbf_rbmon); -- SB_CNTL for rbmon (-1=none)
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rlink ito time unit clock enable
RESET : in slbit; -- reset
RLB_DI : in slv8; -- rlink 8b: data in
RLB_ENA : in slbit; -- rlink 8b: data enable
RLB_BUSY : out slbit; -- rlink 8b: data busy
RLB_DO : out slv8; -- rlink 8b: data out
RLB_VAL : out slbit; -- rlink 8b: data valid
RLB_HOLD : in slbit; -- rlink 8b: data hold
RL_MONI : out rl_moni_type; -- rlink: monitor port
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end entity rlink_core8;
architecture syn of rlink_core8 is
signal RL_DI : slv9 := (others=>'0');
signal RL_ENA : slbit := '0';
signal RL_BUSY : slbit := '0';
signal RL_DO : slv9 := (others=>'0');
signal RL_VAL : slbit := '0';
signal RL_HOLD : slbit := '0';
signal RB_MREQ_L : rb_mreq_type := rb_mreq_init; -- local, readable RB_MREQ
begin
RL : rlink_core
generic map (
ATOWIDTH => ATOWIDTH,
ITOWIDTH => ITOWIDTH)
port map (
CLK => CLK,
CE_INT => CE_INT,
RESET => RESET,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ_L,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
RB_MREQ <= RB_MREQ_L;
-- RLB -> RL converter (DI handling) -------------
B2CD : byte2cdata -- byte stream -> 9bit comma,data
generic map (
CPREF => CPREF,
NCOMM => c_rlink_ncomm)
port map (
CLK => CLK,
RESET => RESET,
DI => RLB_DI,
ENA => RLB_ENA,
BUSY => RLB_BUSY,
DO => RL_DI,
VAL => RL_ENA,
HOLD => RL_BUSY
);
-- RL -> RLB converter (DO handling) -------------
CD2B : cdata2byte -- 9bit comma,data -> byte stream
generic map (
CPREF => CPREF,
NCOMM => c_rlink_ncomm)
port map (
CLK => CLK,
RESET => RESET,
DI => RL_DO,
ENA => RL_VAL,
BUSY => RL_HOLD,
DO => RLB_DO,
VAL => RLB_VAL,
HOLD => RLB_HOLD
);
-- synthesis translate_off
RLMON: if ENAPIN_RLMON >= 0 generate
MON : rlink_mon_sb
generic map (
DWIDTH => RL_DI'length,
ENAPIN => ENAPIN_RLMON)
port map (
CLK => CLK,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD
);
end generate RLMON;
RBMON: if ENAPIN_RBMON >= 0 generate
MON : rb_mon_sb
generic map (
DBASE => 8,
ENAPIN => ENAPIN_RBMON)
port map (
CLK => CLK,
RB_MREQ => RB_MREQ_L,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
end generate RBMON;
-- synthesis translate_on
end syn;
|
gpl-2.0
|
601cfa96da07b2caedcd47bc93df66b7
| 0.513236 | 3.538259 | false | false | false | false |
willprice/build-a-comp-vhdl-modules
|
base/Mux.vhd
| 1 | 790 |
library ieee, base;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use base.base.all;
entity Mux is
port(
data_in_array : in FourInput(3 downto 0);
data_out : out unsigned(3 downto 0);
control_in : in unsigned(3 downto 0);
control_out : out unsigned(3 downto 0)
);
end entity Mux;
architecture rtl of Mux is
signal control : unsigned(1 downto 0);
begin
control <= control_in(1 downto 0);
control_out <= control_in;
process(control, data_in_array)
begin
case (control) is
when "00" => data_out <= data_in_array(0);
when "01" => data_out <= data_in_array(1);
when "10" => data_out <= data_in_array(2);
when "11" => data_out <= data_in_array(3);
when others => data_out <= "0000";
end case;
end process;
end architecture;
|
mit
|
66cd9f28d46837aa8aa926719bea132c
| 0.639241 | 2.78169 | false | false | false | false |
Azbesciak/digitalTechnology
|
cw13/UpDownMod16.vhd
| 1 | 868 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity UpDownMod16 is
generic(
MIN_COUNT : natural := 0;
MAX_COUNT : natural := 15
);
port(
clk, load, enable, up : in std_logic;
toLoad: in integer range MIN_COUNT to MAX_COUNT;
q : out integer range MIN_COUNT to MAX_COUNT;
carry : out std_logic
);
end entity;
architecture rtl of UpDownMod16 is
begin
process (clk, load)
variable cnt: integer range MIN_COUNT to MAX_COUNT;
begin
if load = '1' then
cnt := toLoad;
elsif (rising_edge(clk) and enable = '1') then
if up = '1' then
if cnt = MAX_COUNT then
carry <= '1';
else carry <= '0';
end if;
cnt := cnt + 1;
else
if cnt = MIN_COUNT then
carry <= '1';
else carry <= '0';
end if;
cnt := cnt - 1;
end if;
end if;
q <= cnt;
end process;
end rtl;
|
mit
|
98d0dd2f8806bf2e3297d2b46df8d1c9
| 0.596774 | 2.809061 | false | false | false | false |
armandas/FPGalaxy
|
graphics.vhd
| 2 | 9,377 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fpgalaxy_graphics is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
video_on: in std_logic;
nes_a, nes_b, nes_left, nes_right: in std_logic;
rgb_stream: out std_logic_vector(2 downto 0);
shooting_sound, destruction_sound: out std_logic
);
end fpgalaxy_graphics;
architecture dispatcher of fpgalaxy_graphics is
constant A_WIDTH: integer := 256;
constant DELAY: integer := 25000000;
type states is (left, right);
signal state, state_next: states;
type states_v is (up, down);
signal state_v, state_v_next: states_v;
-- alien movement counter
signal counter, counter_next: std_logic_vector(24 downto 0);
signal master_coord_x, master_coord_x_next,
master_coord_y, master_coord_y_next: std_logic_vector(9 downto 0);
signal missile_coord_x, missile_coord_y: std_logic_vector(9 downto 0);
-- x-coordinate of the spaceship
signal spaceship_x, spaceship_y: std_logic_vector(9 downto 0);
-- origin for explosion animation
signal origin_x, origin_x_next: std_logic_vector(9 downto 0);
signal origin_y, origin_y_next: std_logic_vector(9 downto 0);
-- alien-level-specific origins
signal origin1_x, origin1_y,
origin2_x, origin2_y,
origin3_x, origin3_y: std_logic_vector(9 downto 0);
signal alien1_rgb, alien2_rgb, alien3_rgb: std_logic_vector(2 downto 0);
signal spaceship_rgb: std_logic_vector(2 downto 0);
signal missile_rgb: std_logic_vector(2 downto 0);
signal explosion_rgb: std_logic_vector(2 downto 0);
signal level_rgb, score_rgb: std_logic_vector(2 downto 0);
signal destruction: std_logic;
signal destroyed1, destroyed2, destroyed3: std_logic;
signal defeated1, defeated2, defeated3: std_logic;
-- for starting a new level
signal restart, restart_next: std_logic;
signal level, level_next: std_logic_vector(8 downto 0);
signal score, score_next: std_logic_vector(15 downto 0);
begin
process(clk, not_reset)
begin
if not_reset = '0' then
master_coord_x <= conv_std_logic_vector(192, 10);
master_coord_y <= conv_std_logic_vector(34, 10);
origin_x <= (others => '0');
origin_y <= (others => '0');
level <= (0 => '1', others => '0');
score <= (others => '0');
state <= right;
state_v <= up;
counter <= (others => '0');
restart <= '0';
elsif falling_edge(clk) then
master_coord_x <= master_coord_x_next;
master_coord_y <= master_coord_y_next;
origin_x <= origin_x_next;
origin_y <= origin_y_next;
level <= level_next;
score <= score_next;
state <= state_next;
state_v <= state_v_next;
counter <= counter_next;
restart <= restart_next;
end if;
end process;
counter_next <= counter + 1 when counter < DELAY else (others => '0');
restart_next <= '1' when defeated1 = '1' and
defeated2 = '1' and
defeated3 = '1' else
'0';
level_next <= level + 1 when counter(0) = '0' and
defeated1 = '1' and
defeated2 = '1' and
defeated3 = '1' else
level;
score_next <= score + 2 when destruction = '1' else score;
alien_movement:
process(state, state_v, state_next,
master_coord_x, master_coord_y,
counter)
begin
state_next <= state;
state_v_next <= state_v;
master_coord_x_next <= master_coord_x;
master_coord_y_next <= master_coord_y;
if counter = 0 then
case state_v is
when up =>
state_v_next <= down;
master_coord_y_next <= master_coord_y - 4;
when down =>
state_v_next <= up;
master_coord_y_next <= master_coord_y + 4;
end case;
case state is
when right =>
if master_coord_x + A_WIDTH = 640 then
state_next <= left;
else
master_coord_x_next <= master_coord_x + 16;
end if;
when left =>
if master_coord_x = 0 then
state_next <= right;
else
master_coord_x_next <= master_coord_x - 16;
end if;
end case;
end if;
end process;
process(video_on,
alien1_rgb, alien2_rgb, alien3_rgb,
spaceship_rgb,
missile_rgb, explosion_rgb,
level_rgb, score_rgb)
begin
if video_on = '1' then
rgb_stream <= "000" or
alien1_rgb or
alien2_rgb or
alien3_rgb or
spaceship_rgb or
missile_rgb or
explosion_rgb or
level_rgb or
score_rgb;
else
rgb_stream <= (others => '0');
end if;
end process;
destruction <= destroyed1 or destroyed2 or destroyed3;
destruction_sound <= destruction;
origin_x_next <= origin1_x when destroyed1 = '1' else
origin2_x when destroyed2 = '1' else
origin3_x when destroyed3 = '1' else
origin_x;
origin_y_next <= origin1_y when destroyed1 = '1' else
origin2_y when destroyed2 = '1' else
origin3_y when destroyed3 = '1' else
origin_y;
alien1:
entity work.alien(generator)
port map(
clk => clk, not_reset => not_reset,
px_x => px_x, px_y => px_y,
master_coord_x => master_coord_x,
master_coord_y => master_coord_y,
missile_coord_x => missile_coord_x,
missile_coord_y => missile_coord_y,
restart => restart,
destroyed => destroyed1,
defeated => defeated1,
explosion_x => origin1_x, explosion_y => origin1_y,
rgb_pixel => alien1_rgb
);
alien2:
entity work.alien2(generator)
port map(
clk => clk, not_reset => not_reset,
px_x => px_x, px_y => px_y,
master_coord_x => master_coord_x,
master_coord_y => master_coord_y,
missile_coord_x => missile_coord_x,
missile_coord_y => missile_coord_y,
restart => restart,
destroyed => destroyed2,
defeated => defeated2,
explosion_x => origin2_x, explosion_y => origin2_y,
rgb_pixel => alien2_rgb
);
alien3:
entity work.alien3(generator)
port map(
clk => clk, not_reset => not_reset,
px_x => px_x, px_y => px_y,
master_coord_x => master_coord_x,
master_coord_y => master_coord_y,
missile_coord_x => missile_coord_x,
missile_coord_y => missile_coord_y,
restart => restart,
destroyed => destroyed3,
defeated => defeated3,
explosion_x => origin3_x, explosion_y => origin3_y,
rgb_pixel => alien3_rgb
);
spaceship:
entity work.spaceship(behaviour)
port map(
clk => clk, not_reset => not_reset,
px_x => px_x, px_y => px_y,
nes_left => nes_left, nes_right => nes_right,
spaceship_x => spaceship_x,
spaceship_y => spaceship_y,
rgb_pixel => spaceship_rgb
);
missile:
entity work.missile(behaviour)
port map(
clk => clk, not_reset => not_reset,
px_x => px_x, px_y => px_y,
nes_a => nes_a, nes_b => nes_b,
x_position => spaceship_x,
y_position => spaceship_y,
destruction => destruction,
missile_coord_x => missile_coord_x,
missile_coord_y => missile_coord_y,
shooting => shooting_sound,
rgb_pixel => missile_rgb
);
explosion:
entity work.explosion(behaviour)
port map(
clk => clk, not_reset => not_reset,
px_x => px_x, px_y => px_y,
destruction => destruction,
origin_x => origin_x, origin_y => origin_y,
rgb_pixel => explosion_rgb
);
level_display:
entity work.level_info(display)
port map(
clk => clk, not_reset => not_reset,
px_x => px_x, px_y => px_y,
level => level,
rgb_pixel => level_rgb
);
score_display:
entity work.score_info(display)
port map(
clk => clk, not_reset => not_reset,
px_x => px_x, px_y => px_y,
score => score,
rgb_pixel => score_rgb
);
end dispatcher;
|
bsd-2-clause
|
8de3f09957464ae5ff60c8de844e6178
| 0.503573 | 3.930008 | false | false | false | false |
armandas/FPGalaxy
|
main.vhd
| 1 | 2,603 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fpgalaxy is
port(
clk, not_reset: in std_logic;
hsync, vsync: out std_logic;
nes_data: in std_logic;
rgb: out std_logic_vector(2 downto 0);
buzzer: out std_logic;
nes_clk_out: out std_logic;
nes_ps_control: out std_logic
);
end fpgalaxy;
architecture behaviour of fpgalaxy is
signal rgb_reg, rgb_next: std_logic_vector(2 downto 0);
signal video_on: std_logic;
signal px_x, px_y: std_logic_vector(9 downto 0);
signal shot, destroyed: std_logic;
signal nes_a, nes_b,
nes_select, nes_start,
nes_up, nes_down,
nes_left, nes_right: std_logic;
signal buzzer1, buzzer2: std_logic;
begin
process(clk)
begin
if falling_edge(clk) then
rgb_reg <= rgb_next;
end if;
end process;
vga:
entity work.vga(sync)
port map(
clk => clk, not_reset => not_reset,
hsync => hsync, vsync => vsync,
video_on => video_on, p_tick => open,
pixel_x => px_x, pixel_y => px_y
);
graphics:
entity work.fpgalaxy_graphics(dispatcher)
port map(
clk => clk, not_reset => not_reset,
px_x => px_x, px_y => px_y,
video_on => video_on,
nes_a => nes_a, nes_b => nes_b,
nes_left => nes_left, nes_right => nes_right,
rgb_stream => rgb_next,
shooting_sound => shot, destruction_sound => destroyed
);
sound1:
entity work.player(behaviour)
port map(
clk => clk, not_reset => not_reset,
shooting_sound => shot, explosion_sound => '0',
buzzer => buzzer1
);
buzzer <= buzzer1 or buzzer2;
sound2:
entity work.player(behaviour)
port map(
clk => clk, not_reset => not_reset,
shooting_sound => '0', explosion_sound => destroyed,
buzzer => buzzer2
);
NES_controller:
entity work.controller(arch)
port map(
clk => clk, not_reset => not_reset,
data_in => nes_data,
clk_out => nes_clk_out,
ps_control => nes_ps_control,
gamepad(0) => nes_a, gamepad(1) => nes_b,
gamepad(2) => nes_select, gamepad(3) => nes_start,
gamepad(4) => nes_up, gamepad(5) => nes_down,
gamepad(6) => nes_left, gamepad(7) => nes_right
);
rgb <= rgb_reg;
end behaviour;
|
bsd-2-clause
|
d55af6af42735872a633be475c797864
| 0.521322 | 3.580468 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/rbus/rb_mon.vhd
| 1 | 4,886 |
-- $Id: rb_mon.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rb_mon - sim
-- Description: rbus monitor (for tb's)
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-22 346 3.0 renamed rritb_rbmon -> rb_mon
-- 2010-06-05 301 2.1.1 renamed _rpmon -> _rbmon
-- 2010-06-03 299 2.1 new init encoding (WE=0/1 int/ext)
-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2008-03-24 129 1.2.1 CLK_CYCLE now 31 bits
-- 2007-12-23 105 1.2 added AP_LAM display
-- 2007-11-24 98 1.1 added RP_IINT support
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.rblib.all;
entity rb_mon is -- rbus monitor (for tb's)
generic (
DBASE : positive := 2); -- base for writing data values
port (
CLK : in slbit; -- clock
CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end rb_mon;
architecture sim of rb_mon is
begin
proc_moni: process
variable oline : line;
variable nhold : integer := 0;
variable data : slv16 := (others=>'0');
variable tag : string(1 to 8) := (others=>' ');
variable err : slbit := '0';
procedure write_data(L: inout line;
tag: in string;
data: in slv16;
nhold: in integer := 0;
cond: in boolean := false;
ctxt: in string := " ") is
begin
writetimestamp(L, CLK_CYCLE, tag);
write(L, RB_MREQ.addr, right, 10);
write(L, string'(" "));
writegen(L, data, right, 0, DBASE);
write(L, RB_STAT, right, 4);
if nhold > 0 then
write(L, string'(" nhold="));
write(L, nhold);
end if;
if cond then
write(L, ctxt);
end if;
writeline(output, L);
end procedure write_data;
begin
loop
if ENA = '0' then -- if disabled
wait until ENA='1'; -- stall process till enabled
end if;
wait until rising_edge(CLK); -- check at end of clock cycle
if RB_MREQ.aval='1' and (RB_MREQ.re='1' or RB_MREQ.we='1') then
if RB_SRES.err = '1' then
err := '1';
end if;
if RB_SRES.busy = '1' then
nhold := nhold + 1;
else
data := (others=>'0');
tag := ": ???? ";
if RB_MREQ.re = '1' then
data := RB_SRES.dout;
tag := ": rbre ";
end if;
if RB_MREQ.we = '1' then
data := RB_MREQ.din;
tag := ": rbwe ";
end if;
write_data(oline, tag, data, nhold, err='1', " ERR='1'");
nhold := 0;
end if;
else
if nhold > 0 then
write_data(oline, tag, data, nhold, true, " TIMEOUT");
end if;
nhold := 0;
err := '0';
end if;
if RB_MREQ.init = '1' then -- init
if RB_MREQ.we = '1' then
write_data(oline, ": rbini ", RB_MREQ.din); -- external
else
write_data(oline, ": rbint ", RB_MREQ.din); -- internal
end if;
end if;
if unsigned(RB_LAM) /= 0 then
write_data(oline, ": rblam ", RB_LAM, 0, true, " RB_LAM active");
end if;
end loop;
end process proc_moni;
end sim;
|
gpl-2.0
|
743b29d49d34223814393e350aebe613
| 0.510643 | 3.558631 | false | false | false | false |
Kolchuzhin/LMGT_MEMS_component_library
|
microelectromechanical_transducer/transducer.vhd
| 1 | 2,966 |
-------------------------------------------------------------------------------
-- Model: micro-electro-mechanical transducer (analytical model)
--
-- Author: Vladimir Kolchuzhin, LMGT, TU Chemnitz
-- <[email protected]>
-- Date: 21.10.2008
-- Library: kvl in hAMSter
-------------------------------------------------------------------------------
-- ID: transducer.vhd
--
-- Revision:
-- Revision 1.0 - 23.02.2015 GitHub
--
-- Status: Compile OK, model was compiled with hAMSter simulator
-------------------------------------------------------------------------------
LIBRARY ieee;
--LIBRARY user; -- Simplorer
USE ieee.math_real.all;
use work.electromagnetic_system.all; -- hAMSter
--USE ieee.electrical_systems.ALL; -- Simplorer
--USE ieee.mechanical_systems.ALL; -- Simplorer
ENTITY transducer IS
-- abstract microelectomechanical transducer parameters:
-- constant m:real:=4.658e-7; -- mass
-- constant d:real:=2.245e-3; -- damping coefficient
-- constant c:real:=270.4; -- spring constant
-- constant A:real:=1.0e-6; -- plate area
-- constant h:real:=10.0e-6; -- initial gap
--generic (m,d,c,A,h:real); -- generic tranducer parameters
port (terminal n0,n1:electrical; -- electrical pins
terminal m0,m1:translational); -- mechanical pins
END ENTITY transducer;
-------------------------------------------------------------------------------
ARCHITECTURE basic OF transducer IS
quantity v across i through n1 to n0;
quantity u across f through m1 to m0;
quantity cap:real; -- capacitance
quantity dcdu:real; -- Fel ~ dC/du
-- MKS unit
constant eps:real:=8.85e-12; -- permittivity F/m, MKS unit
-- input parameters:
-- set#1
-- constant m:real:=4.658e-7; -- mass
-- constant d:real:=2.245e-3; -- damping coefficient
-- constant c:real:=270.4; -- spring constant
-- constant A:real:=1.0e-6; -- plate area
-- constant h:real:=10.0e-6; -- initial gap
-- set#2
-- [Release 11.0 Documentation for ANSYS: 7.4. Sample Electromechanical-Circuit Analysis, MKS unit]:
constant m:real:=1.0e-4; -- mass, kg
constant d:real:=40.0e-3; -- damping coefficient, uNs/um
constant c:real:=200.0; -- spring constant, uN/um
constant A:real:=(1.0e+8)*1.0e-12; -- plate area, m^2
constant h:real:=150.0e-6; -- initial gap, m
-- set#3
-- Übung: Microsystem design: Analysis of electromechanical system by Prof. M. Naumann
-- constant m:real:=1.0; -- mass, kg
-- constant d:real:=0.0; -- damping coefficient, Ns/m
-- constant c:real:=1.46; -- spring constant, N/m
-- constant A:real:=50.0e-6*50.0e-6; -- plate area, m*m
-- constant h:real:=3.0e-6; -- initial gap, m
BEGIN
cap==eps*A/(h-u);
dcdu==eps*A/((h-u)**2);
f==m*u'dot'dot + d*u'dot + c*u - dcdu*v**2/2.0;
i==v'dot*cap + cap'dot*v;
END ARCHITECTURE basic;
-------------------------------------------------------------------------------
|
mit
|
a320badb0d256728ae11ebd3cf990404
| 0.562226 | 3.254665 | false | false | false | false |
wgml/sysrek
|
skin_color_segm/ipcore_dir/BINARYZACJA/simulation/BINARYZACJA_tb_stim_gen.vhd
| 4 | 10,579 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: BINARYZACJA_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BINARYZACJA_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BINARYZACJA_TB_PKG.ALL;
ENTITY BINARYZACJA_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BINARYZACJA_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BINARYZACJA_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= std_logic_vector_len("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (255 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"BINARYZACJA.mif",
DEFAULT_DATA,
8,
256);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.BINARYZACJA_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(3),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.BINARYZACJA_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 3 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<3)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
|
gpl-2.0
|
d8ebbe04712afce14ef4ca2d7fb97a42
| 0.594196 | 3.751418 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd
| 1 | 3,447 |
-- $Id: sys_conf_sim.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_n2 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-27 433 1.1.1 use /1*1 to skip dcm in sim, _ssim fails with dcm
-- 2010-11-27 341 1.1 add dcm and memctl related constants (clksys=58)
-- 2010-05-28 295 1.0 Initial version (cloned from _s3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1; -- no dcm in sim...
-- constant sys_conf_clkfx_divide : positive := 25;
-- constant sys_conf_clkfx_multiply : positive := 28; -- ==> 56 MHz
constant sys_conf_memctl_read0delay : positive := 3;
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
constant sys_conf_memctl_writedelay : positive := 4;
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_bram : integer := 0; -- no bram, use cache
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug)
-- constant sys_conf_bram : integer := 1; -- bram only
-- constant sys_conf_bram_awidth : integer := 16; -- bram size (64 kB)
-- constant sys_conf_mem_losize : integer := 8#001777#; -- 64 kByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
-- 2 211 111 111 110 000 000 000
-- 1 098 765 432 109 876 543 210
--
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
-- upper 256 kB excluded for 11/70 UB
|
gpl-2.0
|
31b68a947fa82ba47d43f8532cc3a5bb
| 0.608065 | 3.616999 | false | false | false | false |
xylnao/w11a-extra
|
rtl/bplib/s3board/tb/tb_s3_sram_memctl.vhd
| 1 | 10,540 |
-- $Id: tb_s3_sram_memctl.vhd 432 2011-11-25 20:16:28Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_s3_sram_memctl - sim
-- Description: Test bench for s3_sram_memctl
--
-- Dependencies: vlib/simlib/simclk
-- bplib/issi/is61lv25616al
-- s3_sram_memctl [UUT]
--
-- To test: s3_sram_memctl
--
-- Verified (with tb_s3_sram_memctl_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2007-12-16 101 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-12-16 101 - 0.26 - - c:ok
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-21 432 1.0.6 now numeric_std clean
-- 2010-05-23 293 1.0.5 output # busy cycles; change CHK pipeline logic
-- 2010-05-16 291 1.0.4 rename tb_memctl_s3sram->tb_s3_sram_memctl
-- 2008-03-24 129 1.0.3 CLK_CYCLE now 31 bits
-- 2008-02-17 117 1.0.2 use req,we rather req_r,req_w interface
-- 2008-01-20 113 1.0.1 rename memdrv -> memctl_s3sram
-- 2007-12-15 101 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.s3boardlib.all;
use work.simlib.all;
entity tb_s3_sram_memctl is
end tb_s3_sram_memctl;
architecture sim of tb_s3_sram_memctl is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal REQ : slbit := '0';
signal WE : slbit := '0';
signal BUSY : slbit := '0';
signal ACK_R : slbit := '0';
signal ACK_W : slbit := '0';
signal ACT_R : slbit := '0';
signal ACT_W : slbit := '0';
signal ADDR : slv18 := (others=>'0');
signal BE : slv4 := (others=>'0');
signal DI : slv32 := (others=>'0');
signal DO : slv32 := (others=>'0');
signal O_MEM_CE_N : slv2 := (others=>'0');
signal O_MEM_BE_N : slv4 := (others=>'0');
signal O_MEM_WE_N : slbit := '0';
signal O_MEM_OE_N : slbit := '0';
signal O_MEM_ADDR : slv18 := (others=>'0');
signal IO_MEM_DATA : slv32 := (others=>'0');
signal R_MEMON : slbit := '0';
signal N_CHK_DATA : slbit := '0';
signal N_REF_DATA : slv32 := (others=>'0');
signal N_REF_ADDR : slv18 := (others=>'0');
signal R_CHK_DATA_AL : slbit := '0';
signal R_REF_DATA_AL : slv32 := (others=>'0');
signal R_REF_ADDR_AL : slv18 := (others=>'0');
signal R_CHK_DATA_DL : slbit := '0';
signal R_REF_DATA_DL : slv32 := (others=>'0');
signal R_REF_ADDR_DL : slv18 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : slv31 := (others=>'0');
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 10 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
CLK_STOP => CLK_STOP
);
MEM_L : entity work.is61lv25616al
port map (
CE_N => O_MEM_CE_N(0),
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA(15 downto 0)
);
MEM_U : entity work.is61lv25616al
port map (
CE_N => O_MEM_CE_N(1),
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(3),
LB_N => O_MEM_BE_N(2),
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA(31 downto 16)
);
UUT : s3_sram_memctl
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR,
BE => BE,
DI => DI,
DO => DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
proc_stim: process
file fstim : text open read_mode is "tb_s3_sram_memctl_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable iaddr : slv18 := (others=>'0');
variable idata : slv32 := (others=>'0');
variable ibe : slv4 := (others=>'0');
variable ival : slbit := '0';
variable nbusy : integer := 0;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".memon" => -- .memon
read_ea(iline, ival);
R_MEMON <= ival;
wait for 2*clock_period;
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when "read " => -- read
readgen_ea(iline, iaddr, 16);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
REQ <= '1';
WE <= '0';
writetimestamp(oline, CLK_CYCLE, ": stim read ");
writegen(oline, iaddr, right, 6, 16);
write(oline, string'(" "));
writegen(oline, idata, right, 9, 16);
nbusy := 0;
while BUSY = '1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
N_CHK_DATA <= '1', '0' after clock_period;
N_REF_DATA <= idata;
N_REF_ADDR <= iaddr;
wait for clock_period;
REQ <= '0';
when "write " => -- write
readgen_ea(iline, iaddr, 16);
read_ea(iline, ibe);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
BE <= ibe;
DI <= idata;
REQ <= '1';
WE <= '1';
writetimestamp(oline, CLK_CYCLE, ": stim write");
writegen(oline, iaddr, right, 6, 16);
writegen(oline, ibe , right, 5, 2);
writegen(oline, idata, right, 9, 16);
nbusy := 0;
while BUSY = '1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
wait for clock_period;
REQ <= '0';
when others => -- bad directive
write(oline, string'("?? unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file fstim
wait for 10*clock_period;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if ACK_R = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
writegen(oline, DO, right, 9, 16);
if R_CHK_DATA_DL = '1' then
write(oline, string'(" CHECK"));
if R_REF_DATA_DL = DO then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
writegen(oline, R_REF_DATA_DL, right, 9, 16);
write(oline, string'(" for a="));
writegen(oline, R_REF_ADDR_DL, right, 5, 16);
end if;
R_CHK_DATA_DL <= '0';
end if;
writeline(output, oline);
end if;
if R_CHK_DATA_AL = '1' then
R_CHK_DATA_DL <= R_CHK_DATA_AL;
R_REF_DATA_DL <= R_REF_DATA_AL;
R_REF_ADDR_DL <= R_REF_ADDR_AL;
R_CHK_DATA_AL <= '0';
end if;
if N_CHK_DATA = '1' then
R_CHK_DATA_AL <= N_CHK_DATA;
R_REF_DATA_AL <= N_REF_DATA;
R_REF_ADDR_AL <= N_REF_ADDR;
end if;
end loop;
end process proc_moni;
proc_memon: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if R_MEMON = '1' then
writetimestamp(oline, CLK_CYCLE, ": mem ");
write(oline, string'(" ce="));
write(oline, not O_MEM_CE_N, right, 2);
write(oline, string'(" be="));
write(oline, not O_MEM_BE_N, right, 4);
write(oline, string'(" we="));
write(oline, not O_MEM_WE_N, right);
write(oline, string'(" oe="));
write(oline, not O_MEM_OE_N, right);
write(oline, string'(" a="));
writegen(oline, O_MEM_ADDR, right, 5, 16);
write(oline, string'(" d="));
writegen(oline, IO_MEM_DATA, right, 8, 16);
writeline(output, oline);
end if;
end loop;
end process proc_memon;
end sim;
|
gpl-2.0
|
8e71442c61dcc427da86065c2cf5472d
| 0.503036 | 3.438825 | false | false | false | false |
gtarciso/INE5406
|
aritmetico.vhd
| 1 | 638 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity aritmetico is
generic (width: integer:= 8);
port (
inpt0: in signed(width-1 downto 0);
inpt1: in signed(width-1 downto 0);
ctrl: in std_logic_vector(1 downto 0);
outp: out signed(width-1 downto 0)
);
end;
architecture arch of aritmetico is
begin
process(inpt0, inpt1, ctrl)
begin
if ctrl="00" then
outp <= inpt0 + inpt1;
elsif ctrl="01" then
outp <= inpt0 - inpt1;
elsif ctrl="10" then
outp <= inpt0 + 1;
else
outp <= inpt0 - 1;
end if;
end process;
end;
|
cc0-1.0
|
fd8e1a69db1db0ee7939a616701786a2
| 0.590909 | 3.20603 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/comlib/misc/gen_crc8_tbl_check.vhd
| 2 | 3,499 |
-- $Id: gen_crc8_tbl_check.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gen_crc8_tbl - sim
-- Description: stand-alone program to test crc8 transition table
--
-- Dependencies: -
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.1 use now 'A6' polynomial of Koopman et al.
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-07-08 65 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity gen_crc8_tbl_check is
end gen_crc8_tbl_check;
architecture sim of gen_crc8_tbl_check is
begin
process
type crc8_tbl_type is array (0 to 255) of integer;
variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl
( 0, 77, 154, 215, 121, 52, 227, 174,
242, 191, 104, 37, 139, 198, 17, 92,
169, 228, 51, 126, 208, 157, 74, 7,
91, 22, 193, 140, 34, 111, 184, 245,
31, 82, 133, 200, 102, 43, 252, 177,
237, 160, 119, 58, 148, 217, 14, 67,
182, 251, 44, 97, 207, 130, 85, 24,
68, 9, 222, 147, 61, 112, 167, 234,
62, 115, 164, 233, 71, 10, 221, 144,
204, 129, 86, 27, 181, 248, 47, 98,
151, 218, 13, 64, 238, 163, 116, 57,
101, 40, 255, 178, 28, 81, 134, 203,
33, 108, 187, 246, 88, 21, 194, 143,
211, 158, 73, 4, 170, 231, 48, 125,
136, 197, 18, 95, 241, 188, 107, 38,
122, 55, 224, 173, 3, 78, 153, 212,
124, 49, 230, 171, 5, 72, 159, 210,
142, 195, 20, 89, 247, 186, 109, 32,
213, 152, 79, 2, 172, 225, 54, 123,
39, 106, 189, 240, 94, 19, 196, 137,
99, 46, 249, 180, 26, 87, 128, 205,
145, 220, 11, 70, 232, 165, 114, 63,
202, 135, 80, 29, 179, 254, 41, 100,
56, 117, 162, 239, 65, 12, 219, 150,
66, 15, 216, 149, 59, 118, 161, 236,
176, 253, 42, 103, 201, 132, 83, 30,
235, 166, 113, 60, 146, 223, 8, 69,
25, 84, 131, 206, 96, 45, 250, 183,
93, 16, 199, 138, 36, 105, 190, 243,
175, 226, 53, 120, 214, 155, 76, 1,
244, 185, 110, 35, 141, 192, 23, 90,
6, 75, 156, 209, 127, 50, 229, 168
);
variable crc : integer := 0;
variable oline : line;
begin
loop_i: for i in 0 to 255 loop
write(oline, i, right, 4);
write(oline, string'(": cycle length = "));
crc := i;
loop_n: for n in 1 to 256 loop
crc := crc8_tbl(crc);
if crc = i then
write(oline, n, right, 4);
writeline(output, oline);
exit loop_n;
end if;
end loop; -- n
end loop; -- i
wait;
end process;
end sim;
|
gpl-2.0
|
38787ff4f6f10b2706c5da4e588a1094
| 0.524721 | 2.98295 | false | false | false | false |
xylnao/w11a-extra
|
rtl/ibus/ibdr_lp11.vhd
| 1 | 7,331 |
-- $Id: ibdr_lp11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2009-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibdr_lp11 - syn
-- Description: ibus dev(rem): LP11
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 12 35 0 24 s 5.6
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 11 30 0 19 s 5.8
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-06-21 228 1.0.1 generate interrupt locally when err=1
-- 2009-05-30 220 1.0 Initial version
------------------------------------------------------------------------------
--
-- Notes:
-- - the ERR bit is just a status flag
-- - no hardware interlock (DONE forced 0 when ERR=1), like in simh
-- - also no interrupt when ERR goes 1, like in simh
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_lp11 is -- ibus dev(rem): LP11
-- fixed address: 177514
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end ibdr_lp11;
architecture syn of ibdr_lp11 is
constant ibaddr_lp11 : slv16 := slv(to_unsigned(8#177514#,16));
constant ibaddr_csr : slv1 := "0"; -- csr address offset
constant ibaddr_buf : slv1 := "1"; -- buf address offset
constant csr_ibf_err : integer := 15;
constant csr_ibf_done : integer := 7;
constant csr_ibf_ie : integer := 6;
constant buf_ibf_val : integer := 8;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
err : slbit; -- csr: error flag
done : slbit; -- csr: done flag
ie : slbit; -- csr: interrupt enable
buf : slv7; -- buf:
intreq : slbit; -- interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'1', -- err !! is set !!
'1', -- done !! is set !!
'0', -- ie
(others=>'0'), -- buf
'0' -- intreq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.err <= N_REGS.err; -- don't reset ERR flag
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ilam : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ilam := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 2)=ibaddr_lp11(12 downto 2) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then
case IB_MREQ.addr(1 downto 1) is
when ibaddr_csr => -- CSR -- control status -------------
idout(csr_ibf_err) := r.err;
idout(csr_ibf_done) := r.done;
idout(csr_ibf_ie) := r.ie;
if IB_MREQ.racc = '0' then -- cpu
if ibw0 = '1' then
n.ie := IB_MREQ.din(csr_ibf_ie);
if IB_MREQ.din(csr_ibf_ie) = '1' then
if r.done='1' and r.ie='0' then -- ie set while done=1
n.intreq := '1'; -- request interrupt
end if;
else
n.intreq := '0';
end if;
end if;
else -- rri
n.err := IB_MREQ.din(csr_ibf_err);
end if;
when ibaddr_buf => -- BUF -- data buffer ----------------
if IB_MREQ.racc = '0' then -- cpu
if ibw0 = '1' then
n.buf := IB_MREQ.din(n.buf'range);
if r.err = '0' then -- if online (handle via rbus)
ilam := '1'; -- request attention
n.done := '0'; -- clear done
n.intreq := '0'; -- clear interrupt
else -- if offline (discard locally)
n.done := '1'; -- set done
if r.ie = '1' then -- if interrupts enabled
n.intreq := '1'; -- request interrupt
end if;
end if;
end if;
else -- rri
idout(r.buf'range) := r.buf;
idout(buf_ibf_val) := not r.done;
if ibrd = '1' then
n.done := '1';
if r.ie = '1' then
n.intreq := '1';
end if;
end if;
end if;
when others => null;
end case;
end if;
-- other state changes
if EI_ACK = '1' then
n.intreq := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ <= r.intreq;
end process proc_next;
end syn;
|
gpl-2.0
|
77a4a240d05c4d49cc931ffd4503d47f
| 0.468695 | 3.761416 | false | false | false | false |
wgml/sysrek
|
skin_color_segm/ipcore_dir/BINARYZACJA/simulation/BINARYZACJA_tb_pkg.vhd
| 4 | 5,868 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: BINARYZACJA_tb_pkg.vhd
--
-- Description:
-- DMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BINARYZACJA_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BINARYZACJA_TB_PKG;
PACKAGE BODY BINARYZACJA_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BINARYZACJA_TB_PKG;
|
gpl-2.0
|
31dbb2ace0fec2cc86355a009dee732c
| 0.597648 | 4.517321 | false | false | false | false |
os-cillation/easyfpga-soc
|
infrastructure/receive_frame_buffer.vhd
| 1 | 11,560 |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- R E C E I V E F R A M E B U F F E R (receive_frame_buffer.vhd)
--
-- Statemachine using two-process-pattern
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.constants.all;
-------------------------------------------------------------------------------
ENTITY receive_frame_buffer is
-------------------------------------------------------------------------------
generic (
WIDTH : natural := FIFO_WIDTH -- width of a data word
);
port (
clk_i : in std_logic; -- clock input
clear_i : in std_logic; -- synchronous clear input
store_i : in std_logic; -- asserted when valid word is applied
frame_complete_o : out std_logic; -- frame complete detected
word_i : in std_logic_vector(WIDTH - 1 downto 0); -- word input
frame_o : out std_logic_vector((WIDTH * PROTO_WC_RX_MAX) - 1 downto 0); -- frame output
busy_o : out std_logic -- asserted when forwarding to frame controller
);
end receive_frame_buffer;
-------------------------------------------------------------------------------
ARCHITECTURE two_proc of receive_frame_buffer is
-------------------------------------------------------------------------------
-- frame buffer type
type buffer_type is array (0 to PROTO_WC_RX_MAX - 1) of std_logic_vector(WIDTH -1 downto 0);
-- state type
type state_type is (
init,
-- states for reception of frames that fit into the buffer
receive,
increment,
clear,
-- for partial reception (mwr/awr)
receive_part,
increment_part,
clear_part
);
-- register type (includes frame buffer and state)
type reg_type is record
state : state_type;
frame : buffer_type;
buffer_ptr : integer range 0 to PROTO_WC_RX_MAX; -- position of the next word
-- if PROTO_WC_RX_MAX, buffer is full
receive_cnt : integer range 0 to PROTO_WC_MAX; -- counts the number of received bytes
length : integer range 0 to PROTO_WC_MAX; -- number of bytes to receive in total
end record;
signal reg_out, reg_in : reg_type;
signal frame_complete_s : std_logic;
-------------------------------------------------------------------------------
begin -- architecture
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- STRUCTURAL
-------------------------------------------------------------------------------
-- complete and busy output
frame_complete_o <= frame_complete_s;
busy_o <= frame_complete_s or clear_i;
-------------------------------------------------------------------------------
COMBINATIONAL : process(reg_out, clear_i, store_i, word_i)
-------------------------------------------------------------------------------
variable tmp : reg_type;
begin
-- default assignments
tmp := reg_out;
-- state machine
case tmp.state is
----------------------------------------
when init =>
----------------------------------------
-- outputs
frame_complete_s <= '0';
frame_o <= (others => '-');
-- init register
tmp.buffer_ptr := 0;
tmp.state := receive;
tmp.receive_cnt := 0;
tmp.length := 0;
----------------------------------------
when receive =>
----------------------------------------
-- output frame
for word_index in 0 to (PROTO_WC_RX_MAX - 1) loop
frame_o(((word_index * WIDTH) + (WIDTH - 1)) downto word_index * WIDTH) <= tmp.frame(word_index);
end loop;
-- if the opcode is received
if (tmp.buffer_ptr >= 1) then
-- assert frame_complete depending on opcode.
case tmp.frame(0) is
when MCU_SEL_OPC =>
if (tmp.buffer_ptr = MCU_SEL_LEN) then
frame_complete_s <= '1';
else
frame_complete_s <= '0';
end if;
when SOC_INT_EN_OPC =>
if (tmp.buffer_ptr = SOC_INT_EN_LEN) then
frame_complete_s <= '1';
else
frame_complete_s <= '0';
end if;
when REGISTER_WR_OPC =>
if (tmp.buffer_ptr = REGISTER_WR_LEN ) then
frame_complete_s <= '1';
else
frame_complete_s <= '0';
end if;
when REGISTER_RD_OPC =>
if (tmp.buffer_ptr = REGISTER_RD_LEN ) then
frame_complete_s <= '1';
else
frame_complete_s <= '0';
end if;
when REGISTER_MRD_OPC =>
if (tmp.buffer_ptr = REGISTER_MRD_LEN ) then
frame_complete_s <= '1';
else
frame_complete_s <= '0';
end if;
when REGISTER_ARD_OPC =>
if (tmp.buffer_ptr = REGISTER_ARD_LEN ) then
frame_complete_s <= '1';
else
frame_complete_s <= '0';
end if;
when DETECT_OPC =>
frame_complete_s <= '1';
-- OPC unknown
when others =>
frame_complete_s <= '1';
end case;
-- if pointer is zero
else
frame_complete_s <= '0';
frame_o <= (others => '-');
end if;
-- next state
if (clear_i = '1') then
tmp.state := clear;
-- enter increment_part when storing mwr/awr opcode
elsif (tmp.buffer_ptr = 0 and store_i = '1' and (word_i = REGISTER_MWR_OPC or word_i = REGISTER_AWR_OPC)) then
tmp.state := increment_part;
tmp.frame(0) := word_i;
-- enter increment when storing other opcode
elsif (store_i = '1') then
tmp.frame(tmp.buffer_ptr) := word_i;
tmp.state := increment;
end if;
----------------------------------------
when increment =>
----------------------------------------
-- outputs
frame_complete_s <= '0';
frame_o <= (others => '-');
-- increment pointer and counter
tmp.buffer_ptr := tmp.buffer_ptr + 1;
tmp.receive_cnt := tmp.receive_cnt + 1;
-- next state
tmp.state := receive;
----------------------------------------
when clear =>
----------------------------------------
-- outputs
frame_complete_s <= '0';
frame_o <= (others => '-');
-- clear
tmp.buffer_ptr := 0;
tmp.receive_cnt := 0;
-- next state
if (clear_i = '0') then
tmp.state := receive;
else
tmp.state := clear;
end if;
----------------------------------------
when receive_part =>
----------------------------------------
-- output frame
for word_index in 0 to (PROTO_WC_RX_MAX - 1) loop
frame_o(((word_index * WIDTH) + (WIDTH - 1)) downto word_index * WIDTH) <= tmp.frame(word_index);
end loop;
-- complete when full
if (tmp.buffer_ptr = PROTO_WC_RX_MAX) then
frame_complete_s <= '1';
-- complete when completely received
elsif (tmp.receive_cnt = tmp.length) then
frame_complete_s <= '1';
-- incomplete
else
frame_complete_s <= '0';
end if;
-- store length (header and parity inclusive) when 5 bytes received
if (tmp.receive_cnt = 5) then
-- MWR length
if (tmp.frame(0) = REGISTER_MWR_OPC) then
tmp.length := to_integer(unsigned(tmp.frame(4))) + REGISTER_MWR_LEN;
-- AWR length
elsif (tmp.frame(0) = REGISTER_AWR_OPC) then
tmp.length := to_integer(unsigned(tmp.frame(4))) + REGISTER_AWR_LEN;
end if;
end if;
-- next state
-- if fully received enter clear to return to receive state
if (clear_i = '1' and tmp.receive_cnt = tmp.length) then
tmp.state := clear;
-- if clear enter clear_part to prepare for next partial buffering
elsif (clear_i = '1') then
tmp.state := clear_part;
-- store and enter increment_part
elsif (store_i = '1') then
tmp.frame(tmp.buffer_ptr) := word_i;
tmp.state := increment_part;
end if;
----------------------------------------
when increment_part =>
----------------------------------------
-- outputs
frame_complete_s <= '0';
frame_o <= (others => '-');
-- increment pointer and counter
tmp.buffer_ptr := tmp.buffer_ptr + 1;
tmp.receive_cnt := tmp.receive_cnt + 1;
-- next state
tmp.state := receive_part;
----------------------------------------
when clear_part =>
----------------------------------------
-- outputs
frame_complete_s <= '0';
frame_o <= (others => '-');
-- clear
tmp.buffer_ptr := 0;
-- next state
if (clear_i = '0') then
tmp.state := receive_part;
else
tmp.state := clear_part;
end if;
end case;
-- drive register inputs
reg_in <= tmp;
end process COMBINATIONAL;
-------------------------------------------------------------------------------
REGISTERS : process(clk_i) -- sequential process
-------------------------------------------------------------------------------
begin
if rising_edge(clk_i) then
reg_out <= reg_in;
end if;
end process REGISTERS;
end two_proc;
|
gpl-3.0
|
1276123283d6de1488d833f4bfa8be2d
| 0.411938 | 5.002164 | false | false | false | false |
Kolchuzhin/LMGT_MEMS_component_library
|
miscellaneous/vsrc_gaussian_pulse.vhd
| 1 | 2,029 |
-------------------------------------------------------------------------------
-- Model Title: Voltage Source - Gaussian pulse
-- Entity Name: vsrc_gaussian_pulse
-- Author: Vladimir Kolchuzhin <[email protected]>
-- Created: 2021/01/07
-- Library: kvl in hAMSter
-------------------------------------------------------------------------------
-- ID: vsrc_gaussian_pulse.vhd
-- Last update: ver. 1.0
-- status: tested
-------------------------------------------------------------------------------
-- Description: Ideal Gaussian pulse electrical voltage source
--
-- This model is an ideal voltage source, zero (Thevenin) source impedance.
-- It drives the differential voltage across its terminals (from pos to neg)
-- to the values specified by the generic parameters:
-- pulse_value is the height of the curve's peak, [V]
-- start_delay (tau) is the position of the center of the peak, [sec]
-- pulse_width is the standard deviation [sec]
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- SystemVision
--use IEEE.electrical_systems.all;
--use IEEE.energy_systems.all;
-- hAMSter
use work.electromagnetic_system.all;
use work.all;
entity vsrc_gaussian_pulse is
generic (
pulse_value : real; -- pulse_value is the height of the curve's peak, 1 [V] (real==voltage)
start_delay : real := 0.0; -- start_delay (tau) is the position of the center of the peak, 3.0E-09 [sec]
pulse_width : real); -- pulse_width is the standard deviation 0.25E-09 [sec] / Tend = 6ns
port (terminal pos, neg : electrical);
end entity vsrc_gaussian_pulse;
architecture basic of vsrc_gaussian_pulse is
quantity v across i through pos to neg;
begin
if domain = quiescent_domain or domain = time_domain use
v == pulse_value*exp(-((now-start_delay)**2)/(2.0*pulse_width**2));
else
v == 0.0;
end use;
end architecture basic;
|
mit
|
9fd806ce67388d5fd4f4c356330398b7
| 0.561853 | 3.850095 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_serloop/nexys2/sys_conf2.vhd
| 2 | 1,562 |
-- $Id: sys_conf2.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop2_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 424 1.0 Initial version
-- 2011-10-25 419 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkudiv_usecdiv : integer := 100; -- default usec
constant sys_conf_clksdiv_usecdiv : integer := 60; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_uart_cdinit : integer := 521-1; -- 60000000/115200
end package sys_conf;
|
gpl-2.0
|
b902876fe5db6f52a8612dc63b6af6af
| 0.634443 | 3.944444 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vhd
| 1 | 4,127 |
-- $Id: tb_tst_serloop_s3.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop_s3 - sim
-- Description: Test bench for sys_tst_serloop_s3
--
-- Dependencies: simlib/simclk
-- vlib/xlib/dcm_sfs
-- sys_tst_serloop_s3 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop_s3
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-17 426 1.0.1 use dcm_sfs now
-- 2011-11-06 420 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
entity tb_tst_serloop_s3 is
end tb_tst_serloop_s3;
architecture sim of tb_tst_serloop_s3 is
signal CLK50 : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLKS : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant delay_time : time := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK50,
CLK_CYCLE => open,
CLK_STOP => CLK_STOP
);
DCM_S : dcm_sfs
generic map (
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 6,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLK50,
CLKFX => CLKS,
LOCKED => open
);
UUT : entity work.sys_tst_serloop_s3
port map (
I_CLK50 => CLK50,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLKS,
CLKH => CLKS,
CLK_STOP => CLK_STOP,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
|
gpl-2.0
|
cdb9a0c67906e31c446de644816fcddf
| 0.529198 | 3.160031 | false | false | false | false |
xylnao/w11a-extra
|
rtl/vlib/rlink/rlink_mon_sb.vhd
| 1 | 2,639 |
-- $Id: rlink_mon_sb.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_mon_sb - sim
-- Description: simbus wrapper for rlink monitor
--
-- Dependencies: simbus
-- Test bench: -
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.0 renamed rritb_cpmon_sb -> rlink_mon_sb
-- 2010-05-02 287 1.0.1 use sbcntl_sbf_cpmon def
-- 2007-08-25 75 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.rlinklib.all;
entity rlink_mon_sb is -- simbus wrap for rlink monitor
generic (
DWIDTH : positive := 9; -- data port width (8 or 9)
ENAPIN : integer := sbcntl_sbf_rlmon); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : in slbit -- rlink: data hold
);
end rlink_mon_sb;
architecture sim of rlink_mon_sb is
signal ENA : slbit := '0';
begin
assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
report "assert(ENAPIN in SB_CNTL'range)" severity failure;
ENA <= to_x01(SB_CNTL(ENAPIN));
CPMON : rlink_mon
generic map (
DWIDTH => DWIDTH)
port map (
CLK => CLK,
CLK_CYCLE => SB_CLKCYCLE,
ENA => ENA,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD
);
end sim;
|
gpl-2.0
|
d72aefe47bc5c316724cf62c109b909c
| 0.562713 | 3.551817 | false | false | false | false |
Azbesciak/digitalTechnology
|
cw 5/counter.vhd
| 1 | 591 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
generic(n: natural := 2);
port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end counter;
architecture behv of counter is
signal Pre_Q: std_logic_vector(n-1 downto 0);
begin
process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clock='1' and clock'event) then
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
Q <= Pre_Q;
end behv;
|
mit
|
d8c22c96dae395b29593bfb8a4b0d153
| 0.631134 | 2.662162 | false | false | false | false |
alex-gudilko/FPGA-DATA-CONVERTER
|
HDL stimulus files/24bit_reg_testbench.vhd
| 1 | 2,256 |
--------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: 24bit_reg_testbench.vhd
-- File history:
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- <Description here>
--
-- Targeted device: <Family::ProASIC3> <Die::M1A3P400> <Package::208 PQFP>
-- Author: <Name>
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity bit24_reg_testbench is
end bit24_reg_testbench;
architecture a_24bit_reg_testbench of bit24_reg_testbench is
-- signal, component etc. declarations
constant SYSCLK_PERIOD : time := 20 ns; -- 50MHZ
signal SYSCLK : std_logic := '0';
signal NSYSRESET : std_logic := '0';
signal Data_value : std_logic_vector(23 downto 0) := (others => '0');
component Reg_24B_NRes_Pload
-- ports
port( Data : in std_logic_vector(23 downto 0);
Enable : in std_logic;
Aclr : in std_logic;
Clock : in std_logic;
Q : out std_logic_vector(23 downto 0)
);
end component;
begin
--Data_value <= 0x"000000", 0x"AABBCC" after SYSCLK_PERIOD * 10, 0x"CCBBAA" after SYSCLK_PERIOD * 20;
Data_value <= "000000000000000000000000", "111111000000111111000000" after SYSCLK_PERIOD * 10, "000000111111000000111111" after SYSCLK_PERIOD * 20;
process
variable vhdl_initial : BOOLEAN := TRUE;
begin
if ( vhdl_initial ) then
-- Assert Reset
NSYSRESET <= '0';
wait for ( SYSCLK_PERIOD * 5 );
NSYSRESET <= '1';
wait;
end if;
end process;
-- Clock Driver
SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );
-- Instantiate Unit Under Test: MAIN_CANVAS
Reg_24B_NRes_Pload_0 : Reg_24B_NRes_Pload
-- port map
port map(
-- Inputs
Clock => SYSCLK,
Enable => '1',
Aclr => NSYSRESET,
Data => Data_value,
-- Outputs
Q => open
);
-- architecture body
end a_24bit_reg_testbench;
|
gpl-2.0
|
8bc1de4037d281b4a446203d8a048faf
| 0.526596 | 3.937173 | false | true | false | false |
xylnao/w11a-extra
|
rtl/vlib/simlib/simlib.vhd
| 1 | 28,203 |
-- $Id: simlib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: simlib - sim
-- Description: Support routines for test benches
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.3.8 now numeric_std clean
-- 2010-12-22 346 1.3.7 rename readcommand -> readdotcomm
-- 2010-11-13 338 1.3.6 add simclkcnt; xx.x ns time in writetimestamp()
-- 2008-03-24 129 1.3.5 CLK_CYCLE now 31 bits
-- 2008-03-02 121 1.3.4 added readempty (to discard rest of line)
-- 2007-12-27 106 1.3.3 added simclk2v
-- 2007-12-15 101 1.3.2 add read_ea(time), readtagval[_ea](std_logic)
-- 2007-10-12 88 1.3.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-28 76 1.3 added writehex and writegen
-- 2007-08-10 72 1.2.2 remove entity simclk, put into separate source
-- 2007-08-03 71 1.2.1 readgen, readtagval, readtagval2: add base arg
-- 2007-07-29 70 1.2 readtagval2: add tag=- support; add readword_ea,
-- readoptchar, writetimestamp
-- 2007-07-28 69 1.1.1 rename readrest -> testempty; add readgen
-- use readgen in readtagval() and readtagval2()
-- 2007-07-22 68 1.1 add readrest, readtagval, readtagval2
-- 2007-06-30 62 1.0.1 remove clock_period ect constant defs
-- 2007-06-14 56 1.0 Initial version (renamed from pdp11_sim.vhd)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
package simlib is
constant null_char : character := character'val(0); -- '\0'
constant null_string : string(1 to 1) := (others=>null_char); -- "\0"
procedure readwhite( -- read over white space
L: inout line); -- line
procedure readoct( -- read slv in octal base (arb. length)
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean); -- success flag
procedure readhex( -- read slv in hex base (arb. length)
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean); -- success flag
procedure readgen( -- read slv generic base
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean; -- success flag
base: in integer:= 2); -- default base
procedure readcomment(
L: inout line;
good: out boolean);
procedure readdotcomm(
L: inout line;
name: out string;
good: out boolean);
procedure readword(
L: inout line;
name: out string;
good: out boolean);
procedure readoptchar(
L: inout line;
char: in character;
good: out boolean);
procedure readempty(
L: inout line);
procedure testempty(
L: inout line;
good: out boolean);
procedure testempty_ea(
L: inout line);
procedure read_ea(
L: inout line;
value: out integer);
procedure read_ea(
L: inout line;
value: out time);
procedure read_ea(
L: inout line;
value: out std_logic);
procedure read_ea(
L: inout line;
value: out std_logic_vector);
procedure readoct_ea(
L: inout line;
value: out std_logic_vector);
procedure readhex_ea(
L: inout line;
value: out std_logic_vector);
procedure readgen_ea(
L: inout line;
value: out std_logic_vector;
base: in integer:= 2);
procedure readword_ea(
L: inout line;
name: out string);
procedure readtagval(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic_vector;
good: out boolean;
base: in integer:= 2);
procedure readtagval_ea(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic_vector;
base: in integer:= 2);
procedure readtagval(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic;
good: out boolean);
procedure readtagval_ea(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic);
procedure readtagval2(
L: inout line;
tag: in string;
match: out boolean;
val1: out std_logic_vector;
val2: out std_logic_vector;
good: out boolean;
base: in integer:= 2);
procedure readtagval2_ea(
L: inout line;
tag: in string;
match: out boolean;
val1: out std_logic_vector;
val2: out std_logic_vector;
base: in integer:= 2);
procedure writeoct( -- write slv in octal base (arb. length)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0); -- field width
procedure writehex( -- write slv in hex base (arb. length)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0); -- field width
procedure writegen( -- write slv in generic base (arb. lth)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0; -- field width
base: in integer:= 2); -- default base
procedure writetimestamp(
L: inout line;
clkcyc: in slv31;
str : in string := null_string);
-- ----------------------------------------------------------------------------
component simclk is -- test bench clock generator
generic (
PERIOD : time := 20 ns; -- clock period
OFFSET : time := 200 ns); -- clock offset (first up transition)
port (
CLK : out slbit; -- clock
CLK_CYCLE : out slv31; -- clock cycle number
CLK_STOP : in slbit -- clock stop trigger
);
end component;
component simclkv is -- test bench clock generator
-- with variable periods
port (
CLK : out slbit; -- clock
CLK_CYCLE : out slv31; -- clock cycle number
CLK_PERIOD : in time; -- clock period
CLK_HOLD : in slbit; -- if 1, hold clocks in 0 state
CLK_STOP : in slbit -- clock stop trigger
);
end component;
component simclkcnt is -- test bench system clock cycle counter
port (
CLK : in slbit; -- clock
CLK_CYCLE : out slv31 -- clock cycle number
);
end component;
end package simlib;
-- ----------------------------------------------------------------------------
package body simlib is
procedure readwhite( -- read over white space
L: inout line) is -- line
variable ch : character;
begin
while L'length>0 loop
ch := L(L'left);
exit when (ch/=' ' and ch/=HT);
read(L,ch);
end loop;
end procedure readwhite;
-- -------------------------------------
procedure readoct( -- read slv in octal base (arb. length)
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean) is -- success flag
variable nibble : std_logic_vector(2 downto 0);
variable sum : std_logic_vector(31 downto 0);
variable ndig : integer; -- number of digits
variable ok : boolean;
variable ichar : character;
begin
assert not value'ascending(1)
report "readoct called with ascending range"
severity failure;
assert value'length<=32
report "readoct called with value'length > 32"
severity failure;
readwhite(L);
ndig := 0;
sum := (others=>'U');
while L'length>0 loop
ok := true;
case L(L'left) is
when '0' => nibble := "000";
when '1' => nibble := "001";
when '2' => nibble := "010";
when '3' => nibble := "011";
when '4' => nibble := "100";
when '5' => nibble := "101";
when '6' => nibble := "110";
when '7' => nibble := "111";
when 'u'|'U' => nibble := "UUU";
when 'x'|'X' => nibble := "XXX";
when 'z'|'Z' => nibble := "ZZZ";
when '-' => nibble := "---";
when others => ok := false;
end case;
exit when not ok;
read(L,ichar);
ndig := ndig + 1;
sum(sum'left downto 3) := sum(sum'left-3 downto 0);
sum(2 downto 0) := nibble;
end loop;
ok := ndig>0;
value := sum(value'range);
good := ok;
end procedure readoct;
-- -------------------------------------
procedure readhex( -- read slv in hex base (arb. length)
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean) is -- success flag
variable nibble : std_logic_vector(3 downto 0);
variable sum : std_logic_vector(31 downto 0);
variable ndig : integer; -- number of digits
variable ok : boolean;
variable ichar : character;
begin
assert not value'ascending(1)
report "readhex called with ascending range"
severity failure;
assert value'length<=32
report "readhex called with value'length > 32"
severity failure;
readwhite(L);
ndig := 0;
sum := (others=>'U');
while L'length>0 loop
ok := true;
case L(L'left) is
when '0' => nibble := "0000";
when '1' => nibble := "0001";
when '2' => nibble := "0010";
when '3' => nibble := "0011";
when '4' => nibble := "0100";
when '5' => nibble := "0101";
when '6' => nibble := "0110";
when '7' => nibble := "0111";
when '8' => nibble := "1000";
when '9' => nibble := "1001";
when 'a'|'A' => nibble := "1010";
when 'b'|'B' => nibble := "1011";
when 'c'|'C' => nibble := "1100";
when 'd'|'D' => nibble := "1101";
when 'e'|'E' => nibble := "1110";
when 'f'|'F' => nibble := "1111";
when 'u'|'U' => nibble := "UUUU";
when 'x'|'X' => nibble := "XXXX";
when 'z'|'Z' => nibble := "ZZZZ";
when '-' => nibble := "----";
when others => ok := false;
end case;
exit when not ok;
read(L,ichar);
ndig := ndig + 1;
sum(sum'left downto 4) := sum(sum'left-4 downto 0);
sum(3 downto 0) := nibble;
end loop;
ok := ndig>0;
value := sum(value'range);
good := ok;
end procedure readhex;
-- -------------------------------------
procedure readgen( -- read slv generic base
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean; -- success flag
base: in integer := 2) is -- default base
variable nibble : std_logic_vector(3 downto 0);
variable sum : std_logic_vector(31 downto 0);
variable lbase : integer; -- local base
variable cbase : integer; -- current base
variable ok : boolean;
variable ivalue : integer;
variable ichar : character;
begin
assert not value'ascending(1)
report "readgen called with ascending range"
severity failure;
assert value'length<=32
report "readgen called with value'length > 32"
severity failure;
assert base=2 or base=8 or base=10 or base=16
report "readgen base not 2,8,10, or 16"
severity failure;
readwhite(L);
cbase := base;
lbase := 0;
ok := true;
if L'length >= 2 then
if L(L'left+1) = '"' then
case L(L'left) is
when 'b'|'B' => lbase := 2;
when 'o'|'O' => lbase := 8;
when 'd'|'D' => lbase := 10;
when 'x'|'X' => lbase := 16;
when others => ok := false;
end case;
end if;
if lbase /= 0 then
read(L, ichar);
read(L, ichar);
cbase := lbase;
end if;
end if;
if ok then
case cbase is
when 2 => read(L, value, ok);
when 8 => readoct(L, value, ok);
when 16 => readhex(L, value, ok);
when 10 =>
read(L, ivalue, ok);
-- the following if allows to enter negative integers, e.g. -1 for all-1
if ivalue >= 0 then
value := slv(to_unsigned(ivalue, value'length));
else
value := slv(to_signed(ivalue, value'length));
end if;
when others => null;
end case;
end if;
if ok and lbase/=0 then
if L'length>0 and L(L'left)='"' then
read(L, ichar);
else
ok := false;
end if;
end if;
good := ok;
end procedure readgen;
-- -------------------------------------
procedure readcomment(
L: inout line;
good: out boolean) is
variable ichar : character;
begin
readwhite(L);
good := true;
if L'length > 0 then
good := false;
if L(L'left) = '#' then
good := true;
elsif L(L'left) = 'C' then
good := true;
writeline(output, L);
end if;
end if;
end procedure readcomment;
-- -------------------------------------
procedure readdotcomm(
L: inout line;
name: out string;
good: out boolean) is
begin
for i in name'range loop
name(i) := ' ';
end loop;
good := false;
if L'length>0 and L(L'left)='.' then
readword(L, name, good);
end if;
end procedure readdotcomm;
-- -------------------------------------
procedure readword(
L: inout line;
name: out string;
good: out boolean) is
variable ichar : character;
variable ind : integer;
begin
assert name'ascending(1)
report "readword called with descending range for name"
severity failure;
readwhite(L);
for i in name'range loop
name(i) := ' ';
end loop;
ind := name'left;
while L'length>0 and ind<=name'right loop
ichar := L(L'left);
exit when ichar=' ' or ichar=',' or ichar='|';
read(L,ichar);
name(ind) := ichar;
ind := ind + 1;
end loop;
good := ind /= name'left; -- ok if one non-blank found
end procedure readword;
-- -------------------------------------
procedure readoptchar(
L: inout line;
char: in character;
good: out boolean) is
variable ichar : character;
begin
good := false;
if L'length > 0 then
if L(L'left) = char then
read(L, ichar);
good := true;
end if;
end if;
end procedure readoptchar;
-- -------------------------------------
procedure readempty(
L: inout line) is
variable ch : character;
begin
while L'length>0 loop -- anything left ?
read(L,ch); -- read and discard it
end loop;
end procedure readempty;
-- -------------------------------------
procedure testempty(
L: inout line;
good: out boolean) is
begin
readwhite(L); -- discard white space
good := true; -- good if now empty
if L'length > 0 then -- anything left ?
good := false; -- assume bad
if L'length >= 2 and -- check for "--"
L(L'left)='-' and L(L'left+1)='-' then
good := true; -- in that case comment -> good
end if;
end if;
end procedure testempty;
-- -------------------------------------
procedure testempty_ea(
L: inout line) is
variable ok : boolean := false;
begin
testempty(L, ok);
assert ok report "extra chars in """ & L.all & """" severity failure;
end procedure testempty_ea;
-- -------------------------------------
procedure read_ea(
L: inout line;
value: out integer) is
variable ok : boolean := false;
begin
read(L, value, ok);
assert ok report "read(integer) conversion error in """ &
L.all & """" severity failure;
end procedure read_ea;
-- -------------------------------------
procedure read_ea(
L: inout line;
value: out time) is
variable ok : boolean := false;
begin
read(L, value, ok);
assert ok report "read(time) conversion error in """ &
L.all & """" severity failure;
end procedure read_ea;
-- -------------------------------------
procedure read_ea(
L: inout line;
value: out std_logic) is
variable ok : boolean := false;
begin
read(L, value, ok);
assert ok report "read(std_logic) conversion error in """ &
L.all & """" severity failure;
end procedure read_ea;
-- -------------------------------------
procedure read_ea(
L: inout line;
value: out std_logic_vector) is
variable ok : boolean := false;
begin
read(L, value, ok);
assert ok report "read(std_logic_vector) conversion error in """ &
L.all & """" severity failure;
end procedure read_ea;
-- -------------------------------------
procedure readoct_ea(
L: inout line;
value: out std_logic_vector) is
variable ok : boolean := false;
begin
readoct(L, value, ok);
assert ok report "readoct() conversion error in """ &
L.all & """" severity failure;
end procedure readoct_ea;
-- -------------------------------------
procedure readhex_ea(
L: inout line;
value: out std_logic_vector) is
variable ok : boolean := false;
begin
readhex(L, value, ok);
assert ok report "readhex() conversion error in """ &
L.all & """" severity failure;
end procedure readhex_ea;
-- -------------------------------------
procedure readgen_ea(
L: inout line;
value: out std_logic_vector;
base: in integer := 2) is
variable ok : boolean := false;
begin
readgen(L, value, ok, base);
assert ok report "readgen() conversion error in """ &
L.all & """" severity failure;
end procedure readgen_ea;
-- -------------------------------------
procedure readword_ea(
L: inout line;
name: out string) is
variable ok : boolean := false;
begin
readword(L, name, ok);
assert ok report "readword() read error in """ &
L.all & """" severity failure;
end procedure readword_ea;
-- -------------------------------------
procedure readtagval(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic_vector;
good: out boolean;
base: in integer:= 2) is
variable itag : string(tag'range);
variable ichar : character;
variable imatch : boolean;
begin
readwhite(L);
for i in val'range loop
val(i) := '0';
end loop;
good := true;
imatch := false;
if L'length > tag'length then
imatch := L(L'left to L'left+tag'length-1) = tag and
L(L'left+tag'length) = '=';
if imatch then
read(L, itag);
read(L, ichar);
readgen(L, val, good, base);
end if;
end if;
match := imatch;
end procedure readtagval;
-- -------------------------------------
procedure readtagval_ea(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic_vector;
base: in integer:= 2) is
variable ok : boolean := false;
begin
readtagval(L, tag, match, val, ok, base);
assert ok report "readtagval(std_logic_vector) conversion error in """ &
L.all & """" severity failure;
end procedure readtagval_ea;
-- -------------------------------------
procedure readtagval(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic;
good: out boolean) is
variable itag : string(tag'range);
variable ichar : character;
variable imatch : boolean;
begin
readwhite(L);
val := '0';
good := true;
imatch := false;
if L'length > tag'length then
imatch := L(L'left to L'left+tag'length-1) = tag and
L(L'left+tag'length) = '=';
if imatch then
read(L, itag);
read(L, ichar);
read(L, val, good);
end if;
end if;
match := imatch;
end procedure readtagval;
-- -------------------------------------
procedure readtagval_ea(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic) is
variable ok : boolean := false;
begin
readtagval(L, tag, match, val, ok);
assert ok report "readtagval(std_logic) conversion error in """ &
L.all & """" severity failure;
end procedure readtagval_ea;
-- -------------------------------------
procedure readtagval2(
L: inout line;
tag: in string;
match: out boolean;
val1: out std_logic_vector;
val2: out std_logic_vector;
good: out boolean;
base: in integer:= 2) is
variable itag : string(tag'range);
variable imatch : boolean;
variable igood : boolean;
variable ichar : character;
variable ok : boolean;
begin
readwhite(L);
for i in val1'range loop -- zero val1
val1(i) := '0';
end loop;
for i in val2'range loop -- zero val2
val2(i) := '0';
end loop;
igood := true;
imatch := false;
if L'length > tag'length then -- check for tag
imatch := L(L'left to L'left+tag'length-1) = tag and
L(L'left+tag'length) = '=';
if imatch then -- if found
read(L, itag); -- remove tag
read(L, ichar); -- remove =
igood := false;
readoptchar(L, '-', ok); -- check for tag=-
if ok then
for i in val2'range loop -- set mask to all 1 (ignore)
val2(i) := '1';
end loop;
igood := true;
else -- here if tag=bit[,bit]
readgen(L, val1, igood, base); -- read val1
if igood then
readoptchar(L, ',', ok); -- check(and remove) ,
if ok then
readgen(L, val2, igood, base); -- and read val2
end if;
end if;
end if;
end if;
end if;
match := imatch;
good := igood;
end procedure readtagval2;
-- -------------------------------------
procedure readtagval2_ea(
L: inout line;
tag: in string;
match: out boolean;
val1: out std_logic_vector;
val2: out std_logic_vector;
base: in integer:= 2) is
variable ok : boolean := false;
begin
readtagval2(L, tag, match, val1, val2, ok, base);
assert ok report "readtagval2() conversion error in """ &
L.all & """" severity failure;
end procedure readtagval2_ea;
-- -------------------------------------
procedure writeoct( -- write slv in octal base (arb. length)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0) is -- field width
variable nbit : integer; -- number of bits
variable ndig : integer; -- number of digits
variable iwidth : integer;
variable ioffset : integer;
variable nibble : std_logic_vector(2 downto 0);
variable ochar : character;
begin
assert not value'ascending(1)
report "writeoct called with ascending range"
severity failure;
nbit := value'length(1);
ndig := (nbit+2)/3;
iwidth := nbit mod 3;
if iwidth = 0 then
iwidth := 3;
end if;
ioffset := value'left(1) - iwidth+1;
if justified=right and field>ndig then
for i in ndig+1 to field loop
write(L,' ');
end loop; -- i
end if;
for i in 0 to ndig-1 loop
nibble := "000";
nibble(iwidth-1 downto 0) := value(ioffset+iwidth-1 downto ioffset);
ochar := ' ';
for i in nibble'range loop
case nibble(i) is
when 'U' => ochar := 'U';
when 'X' => ochar := 'X';
when 'Z' => ochar := 'Z';
when '-' => ochar := '-';
when others => null;
end case;
end loop; -- i
if ochar = ' ' then
write(L,to_integer(unsigned(nibble)));
else
write(L,ochar);
end if;
iwidth := 3;
ioffset := ioffset - 3;
end loop; -- i
if justified=left and field>ndig then
for i in ndig+1 to field loop
write(L,' ');
end loop; -- i
end if;
end procedure writeoct;
-- -------------------------------------
procedure writehex( -- write slv in hex base (arb. length)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0) is -- field width
variable nbit : integer; -- number of bits
variable ndig : integer; -- number of digits
variable iwidth : integer;
variable ioffset : integer;
variable nibble : std_logic_vector(3 downto 0);
variable ochar : character;
variable hextab : string(1 to 16) := "0123456789abcdef";
begin
assert not value'ascending(1)
report "writehex called with ascending range"
severity failure;
nbit := value'length(1);
ndig := (nbit+3)/4;
iwidth := nbit mod 4;
if iwidth = 0 then
iwidth := 4;
end if;
ioffset := value'left(1) - iwidth+1;
if justified=right and field>ndig then
for i in ndig+1 to field loop
write(L,' ');
end loop; -- i
end if;
for i in 0 to ndig-1 loop
nibble := "0000";
nibble(iwidth-1 downto 0) := value(ioffset+iwidth-1 downto ioffset);
ochar := ' ';
for i in nibble'range loop
case nibble(i) is
when 'U' => ochar := 'U';
when 'X' => ochar := 'X';
when 'Z' => ochar := 'Z';
when '-' => ochar := '-';
when others => null;
end case;
end loop; -- i
if ochar = ' ' then
write(L,hextab(to_integer(unsigned(nibble))+1));
else
write(L,ochar);
end if;
iwidth := 4;
ioffset := ioffset - 4;
end loop; -- i
if justified=left and field>ndig then
for i in ndig+1 to field loop
write(L,' ');
end loop; -- i
end if;
end procedure writehex;
-- -------------------------------------
procedure writegen( -- write slv in generic base (arb. lth)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0; -- field width
base: in integer:=2) is -- default base
begin
case base is
when 2 => write(L, value, justified, field);
when 8 => writeoct(L, value, justified, field);
when 16 => writehex(L, value, justified, field);
when others => report "writegen base not 2,8, or 16"
severity failure;
end case;
end procedure writegen;
-- -------------------------------------
procedure writetimestamp(
L: inout line;
clkcyc: in slv31;
str: in string := null_string) is
variable t_nsec : integer := 0;
variable t_psec : integer := 0;
variable t_dnsec : integer := 0;
begin
t_nsec := now / 1 ns;
t_psec := (now - t_nsec * 1 ns) / 1 ps;
t_dnsec := t_psec/100;
-- write(L, now, right, 12);
write(L, t_nsec, right, 8);
write(L,'.');
write(L, t_dnsec, right, 1);
write(L, string'(" ns"));
write(L, to_integer(unsigned(clkcyc)), right, 7);
if str /= null_string then
write(L, str);
end if;
end procedure writetimestamp;
end package body simlib;
|
gpl-2.0
|
73b696c90817d0d9d9700238e74030ed
| 0.538879 | 3.810186 | false | false | false | false |
xylnao/w11a-extra
|
rtl/sys_gen/w11a/avmb/sys_w11a_mb.vhd
| 1 | 12,315 |
-- $Id$
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_mb - syn
-- Description: w11a test design for avmb
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- vlib/rri/rb_sres_or_3
-- w11a/pdp11_core_rbus
-- w11a/pdp11_core
-- w11a/pdp11_bram
-- w11a/pdp11_cache
-- w11a/pdp11_mem70
-- ibus/ib_sres_or_2
-- ibus/ibdr_minisys
-- ibus/ibdr_maxisys
-- w11a/pdp11_tmu_sb [sim only]
--
-- Test bench: tb/tb_sys_w11a_mb
--
-- Target Devices: generic
-- Tool versions: xst 13.4; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-02-24 ??? 1.0 Initial version
------------------------------------------------------------------------------
--
-- w11a test design for avmb
-- w11a + rlink + serport
--
-- Usage of Avnet MicroBoard Switches, Buttons, LEDs:
--
-- SWI(3:2): no function (only connected to mb_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port
-- 1 -> Pmod 2/top RS232 port
--
-- LED(3) MEM_ACT_W or MEM_ACT_R
-- (2) cmdbusy (all rlink access, mostly rdma)
-- (1) cpugo
-- (0) user mode
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serport.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_mb is -- top level
-- implements avmb_fusp_aif
port (
I_CLK40 : in slbit; -- 40 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- avmb switches
I_BTN : in slv1; -- avmb button
O_LED : out slv4; -- avmb leds
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_w11a_mb;
architecture syn of sys_w11a_mb is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv4 := (others=>'0');
signal BTN : slv1 := (others=>'0');
signal LED : slv4 := (others=>'0');
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CPU_RESET : slbit := '0';
signal CP_CNTL : cp_cntl_type := cp_cntl_init;
signal CP_ADDR : cp_addr_type := cp_addr_init;
signal CP_DIN : slv16 := (others=>'0');
signal CP_STAT : cp_stat_type := cp_stat_init;
signal CP_DOUT : slv16 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal EM_MREQ : em_mreq_type := em_mreq_init;
signal EM_SRES : em_sres_type := em_sres_init;
signal HM_ENA : slbit := '0';
signal MEM70_FMISS : slbit := '0';
signal CACHE_FMISS : slbit := '0';
signal CACHE_CHIT : slbit := '0';
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MEM_ADDR_EXT : slv22 := (others=>'0');
signal BRESET : slbit := '0';
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES : ib_sres_type := ib_sres_init;
signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init;
signal DISPREG : slv16 := (others=>'0');
constant rbaddr_core0 : slv8 := "00000000";
constant rbaddr_ibus : slv8 := "10000000";
constant rbaddr_hio : slv8 := "11000000";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => I_CLK40,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
SWIDTH => 4,
BWIDTH => 1,
LWIDTH => 4,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => (others => '0'),
DSP_DP => (others => '0'),
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => open,
O_SEG_N => open
);
RLINK : rlink_sp1c
generic map (
ATOWIDTH => 7, -- 128 cycles access timeout
ITOWIDTH => 6, -- 64 periods max idle timeout
CPREF => c_rlink_cpref,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RB_SRES_OR : rb_sres_or_3
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_IBD,
RB_SRES_3 => RB_SRES_HIO,
RB_SRES_OR => RB_SRES
);
RB2CP : pdp11_core_rbus
generic map (
RB_ADDR_CORE => rbaddr_core0,
RB_ADDR_IBUS => rbaddr_ibus)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM(0),
CPU_RESET => CPU_RESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT
);
CORE : pdp11_core
port map (
CLK => CLK,
RESET => CPU_RESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
BRESET => BRESET,
IB_MREQ_M => IB_MREQ,
IB_SRES_M => IB_SRES,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO
);
MEM_BRAM: if true generate
signal HM_VAL_BRAM : slbit := '0';
begin
MEM : pdp11_bram
generic map (
AWIDTH => sys_conf_bram_awidth)
port map (
CLK => CLK,
GRESET => CPU_RESET,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES
);
HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write
MEM70: pdp11_mem70
port map (
CLK => CLK,
CRESET => BRESET,
HM_ENA => EM_MREQ.req,
HM_VAL => HM_VAL_BRAM,
CACHE_FMISS => MEM70_FMISS,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MEM70
);
end generate MEM_BRAM;
IB_SRES_OR : ib_sres_or_2
port map (
IB_SRES_1 => IB_SRES_MEM70,
IB_SRES_2 => IB_SRES_IBDR,
IB_SRES_OR => IB_SRES
);
IBD_MINI : if false generate
begin
IBDR_SYS : ibdr_minisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => CPU_RESET,
BRESET => BRESET,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
end generate IBD_MINI;
IBD_MAXI : if true generate
begin
IBDR_SYS : ibdr_maxisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => CPU_RESET,
BRESET => BRESET,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
end generate IBD_MAXI;
proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
variable iled : slv4 := (others=>'0');
begin
iled := (others=>'0');
iled(3) := MEM_ACT_W or MEM_ACT_R;
iled(2) := CP_STAT.cmdbusy;
iled(1) := CP_STAT.cpugo;
if CP_STAT.cpugo = '1' then
case DM_STAT_DP.psw.cmode is
when c_psw_umode =>
iled(0) := '1';
when others => null;
end case;
else
null;
end if;
LED <= iled;
end process;
-- synthesis translate_off
DM_STAT_SY.emmreq <= EM_MREQ;
DM_STAT_SY.emsres <= EM_SRES;
DM_STAT_SY.chit <= CACHE_CHIT;
TMU : pdp11_tmu_sb
generic map (
ENAPIN => 13)
port map (
CLK => CLK,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
DM_STAT_SY => DM_STAT_SY
);
-- synthesis translate_on
end syn;
|
gpl-2.0
|
e3456d026e1818656938c7fc74e77d66
| 0.501421 | 3.199532 | false | false | false | false |
AdanDuM/INE5406-SD
|
contador_decrescente.vhd
| 1 | 1,926 |
library IEEE;
use IEEE.std_logic_1164.all;
use iEEE.numeric_std.all;
-- Alunos: Adan Pereira Gomes e Wesley Mayk Gama Luz
entity contador_decrescente is
generic (
in_width : positive := 4;
out_width: positive := 4
);
port (
clock, reset, enable: in std_logic;
in_value : in std_logic_vector(in_width-1 downto 0);
m0, m1 : out std_logic_vector(out_width-1 downto 0)
);
end entity;
architecture FSM of contador_decrescente is
type State is (init, count, sm0, sm1, zero);
signal actualState, nextState: State;
signal sn_m0, sn_m1: positive range 0 to 9;
signal tempo: positive range 0 to 59;
begin
-- next state logic
LPE: process(actualState, tempo, sn_m0, sn_m1) is
begin
nextState <= actualState;
case actualState is
when init =>
nextState <= count;
when count =>
if tempo = 59 and sn_m1 /= 0 and sn_m0 /= 0 then
nextState <= sm0;
elsif tempo = 59 and sn_m1 /= 0 and sn_m0 = 0 then
nextState <= sm1;
elsif tempo = 59 and sn_m1 = 0 and sn_m0 = 0 then
nextState <= zero;
end if;
when sm0 =>
nextState <= count;
when sm1 =>
nextState <= count;
end case;
end process;
-- state element (memory)
ME: process(clock, reset) is
begin
if reset = '0' then
actualState <= init;
elsif rising_edge(clock) then
if enable = '1' then
actualState <= nextState;
end if;
end if;
end process;
-- output-logic
OL: process(actualState) is
begin
case actualState is
when init =>
tempo <= 0;
sn_m0 <= 0;
sn_m1 <= unsigned(in_value);
when count =>
tempo <= tempo + 1 ;
sn_m0 <= 0;
sn_m1 <= 0;
when sm0 =>
tempo <= 0 ;
sn_m0 <= sn_m0 - 1;
sn_m1 <= sn_m1;
when sm1 =>
tempo <= 0;
sn_m0 <= 9;
sn_m1 <= sn_m1 - 1;
end case;
m0 <= std_logic_vector(to_unsigned(sn_m0, m0'length));
m1 <= std_logic_vector(to_unsigned(sn_m1, m1'length));
end process;
end architecture;
|
gpl-2.0
|
8c67146a9406918c5de81de9edb32c09
| 0.61838 | 2.731915 | false | false | false | false |
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