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stringlengths 6
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int64 137
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stringlengths 137
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stringclasses 15
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stringlengths 32
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float64 0.25
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float64 1.51
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thasti/dvbs
|
hdl/interleaver/interleaver_tb.vhd
| 1 | 948 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity interleaver_tb is
end interleaver_tb;
architecture tb of interleaver_tb is
constant width : positive := 8;
-- interface signals
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal clk_en : std_logic := '0';
signal sync : std_logic := '0';
signal d : std_logic_vector(7 downto 0);
signal q : std_logic_vector(7 downto 0);
begin
dut : entity work.interleaver
generic map (I => 12, M => 17)
port map(clk => clk, rst => rst, clk_en => clk_en, sync => sync, d => d, q => q);
clk <= not clk after 100 ns;
rst <= '0' after 500 ns;
test : process
variable cnt : unsigned(7 downto 0) := to_unsigned(0, 8);
begin
wait until falling_edge(rst);
while true loop
wait until rising_edge(clk);
clk_en <= '1';
d <= std_logic_vector(cnt);
cnt := cnt + to_unsigned(1, 8);
end loop;
end process;
end tb;
|
gpl-2.0
|
4f9148e050beb2c6f6c2a7c6600eb4a5
| 0.639241 | 2.739884 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pctrl.vhd
| 1 | 17,171 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL data_chk_wr : STD_LOGIC := '0';
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0 AND C_CH_TYPE /= 2) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
pwr_tb_stop_run:IF(C_CH_TYPE = 2) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE pwr_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
fifo_flags_checks:IF(C_CH_TYPE /= 2) GENERATE
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
END GENERATE fifo_flags_checks;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- Wiring logic data checks
-----------------------------------------------------
wiring_d_chk:IF(C_CH_TYPE = 2) GENERATE
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
data_chk_wr <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF ((DATA_OUT = DATA_IN) AND (FULL = NOT rd_en_i) AND (EMPTY = NOT wr_en_i)) THEN
data_chk_wr <= '0';
ELSE
data_chk_wr <= '1';
END IF;
END IF;
END PROCESS;
data_chk_i <= data_chk_wr;
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
END GENERATE wiring_d_chk;
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
-----------------------------------------------------
-- Wiring logic enable generation
-----------------------------------------------------
axi_pw_enable:IF(C_CH_TYPE = 2) GENERATE
RESET_EN <= '1';
PROCESS(WR_CLK)
BEGIN
IF (WR_CLK'event AND WR_CLK='1') THEN
wr_en_i <= NOT wr_en_i;
rd_en_i <= NOT rd_en_i;
END IF;
END PROCESS;
END GENERATE axi_pw_enable;
END ARCHITECTURE;
|
mit
|
4786f7670a9faf605a592d4bf9df1243
| 0.520704 | 3.358302 | false | false | false | false |
medav/conware
|
conware_final/system/hdl/system_v_tc_0_wrapper.vhd
| 1 | 10,151 |
-------------------------------------------------------------------------------
-- system_v_tc_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library v_tc_v5_01_a;
use v_tc_v5_01_a.all;
entity system_v_tc_0_wrapper is
port (
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_aclken : in std_logic;
s_axi_awaddr : in std_logic_vector(8 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(8 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
irq : out std_logic;
intc_if : out std_logic_vector(31 downto 0);
clk : in std_logic;
resetn : in std_logic;
clken : in std_logic;
det_clken : in std_logic;
gen_clken : in std_logic;
fsync_in : in std_logic;
vblank_in : in std_logic;
vsync_in : in std_logic;
hblank_in : in std_logic;
hsync_in : in std_logic;
active_video_in : in std_logic;
active_chroma_in : in std_logic;
vblank_out : out std_logic;
vsync_out : out std_logic;
hblank_out : out std_logic;
hsync_out : out std_logic;
active_video_out : out std_logic;
active_chroma_out : out std_logic;
fsync_out : out std_logic_vector(0 to 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_v_tc_0_wrapper : entity is "v_tc_v5_01_a";
end system_v_tc_0_wrapper;
architecture STRUCTURE of system_v_tc_0_wrapper is
component v_tc is
generic (
C_HAS_AXI4_LITE : INTEGER;
C_HAS_INTC_IF : INTEGER;
C_GEN_AUTO_SWITCH : integer;
C_MAX_PIXELS : integer;
C_MAX_LINES : integer;
C_NUM_FSYNCS : integer;
C_DETECT_EN : integer;
C_GENERATE_EN : integer;
C_DET_HSYNC_EN : integer;
C_DET_VSYNC_EN : integer;
C_DET_HBLANK_EN : integer;
C_DET_VBLANK_EN : integer;
C_DET_AVIDEO_EN : integer;
C_DET_ACHROMA_EN : integer;
C_GEN_HSYNC_EN : integer;
C_GEN_VSYNC_EN : integer;
C_GEN_HBLANK_EN : integer;
C_GEN_VBLANK_EN : integer;
C_GEN_AVIDEO_EN : integer;
C_GEN_ACHROMA_EN : integer;
C_GEN_VIDEO_FORMAT : INTEGER;
C_GEN_CPARITY : integer;
C_SYNC_EN : integer;
C_GEN_VBLANK_POLARITY : integer;
C_GEN_HBLANK_POLARITY : integer;
C_GEN_VSYNC_POLARITY : integer;
C_GEN_HSYNC_POLARITY : integer;
C_GEN_AVIDEO_POLARITY : integer;
C_GEN_ACHROMA_POLARITY : integer;
C_GEN_VACTIVE_SIZE : integer;
C_GEN_HACTIVE_SIZE : integer;
C_GEN_HFRAME_SIZE : integer;
C_GEN_F0_VFRAME_SIZE : integer;
C_GEN_HSYNC_START : integer;
C_GEN_HSYNC_END : integer;
C_GEN_F0_VBLANK_HSTART : integer;
C_GEN_F0_VBLANK_HEND : integer;
C_GEN_F0_VSYNC_VSTART : integer;
C_GEN_F0_VSYNC_VEND : integer;
C_GEN_F0_VSYNC_HSTART : integer;
C_GEN_F0_VSYNC_HEND : integer;
C_FSYNC_HSTART0 : integer;
C_FSYNC_VSTART0 : integer;
C_FSYNC_HSTART1 : integer;
C_FSYNC_VSTART1 : integer;
C_FSYNC_HSTART2 : integer;
C_FSYNC_VSTART2 : integer;
C_FSYNC_HSTART3 : integer;
C_FSYNC_VSTART3 : integer;
C_FSYNC_HSTART4 : integer;
C_FSYNC_VSTART4 : integer;
C_FSYNC_HSTART5 : integer;
C_FSYNC_VSTART5 : integer;
C_FSYNC_HSTART6 : integer;
C_FSYNC_VSTART6 : integer;
C_FSYNC_HSTART7 : integer;
C_FSYNC_VSTART7 : integer;
C_FSYNC_HSTART8 : integer;
C_FSYNC_VSTART8 : integer;
C_FSYNC_HSTART9 : integer;
C_FSYNC_VSTART9 : integer;
C_FSYNC_HSTART10 : integer;
C_FSYNC_VSTART10 : integer;
C_FSYNC_HSTART11 : integer;
C_FSYNC_VSTART11 : integer;
C_FSYNC_HSTART12 : integer;
C_FSYNC_VSTART12 : integer;
C_FSYNC_HSTART13 : integer;
C_FSYNC_VSTART13 : integer;
C_FSYNC_HSTART14 : integer;
C_FSYNC_VSTART14 : integer;
C_FSYNC_HSTART15 : integer;
C_FSYNC_VSTART15 : integer;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_CLK_FREQ_HZ : INTEGER;
C_FAMILY : STRING
);
port (
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_aclken : in std_logic;
s_axi_awaddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_wstrb : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
irq : out std_logic;
intc_if : out std_logic_vector(31 downto 0);
clk : in std_logic;
resetn : in std_logic;
clken : in std_logic;
det_clken : in std_logic;
gen_clken : in std_logic;
fsync_in : in std_logic;
vblank_in : in std_logic;
vsync_in : in std_logic;
hblank_in : in std_logic;
hsync_in : in std_logic;
active_video_in : in std_logic;
active_chroma_in : in std_logic;
vblank_out : out std_logic;
vsync_out : out std_logic;
hblank_out : out std_logic;
hsync_out : out std_logic;
active_video_out : out std_logic;
active_chroma_out : out std_logic;
fsync_out : out std_logic_vector(C_NUM_FSYNCS-1 to 0)
);
end component;
begin
v_tc_0 : v_tc
generic map (
C_HAS_AXI4_LITE => 1,
C_HAS_INTC_IF => 0,
C_GEN_AUTO_SWITCH => 1,
C_MAX_PIXELS => 4096,
C_MAX_LINES => 4096,
C_NUM_FSYNCS => 1,
C_DETECT_EN => 0,
C_GENERATE_EN => 1,
C_DET_HSYNC_EN => 1,
C_DET_VSYNC_EN => 1,
C_DET_HBLANK_EN => 1,
C_DET_VBLANK_EN => 1,
C_DET_AVIDEO_EN => 1,
C_DET_ACHROMA_EN => 0,
C_GEN_HSYNC_EN => 1,
C_GEN_VSYNC_EN => 1,
C_GEN_HBLANK_EN => 1,
C_GEN_VBLANK_EN => 1,
C_GEN_AVIDEO_EN => 1,
C_GEN_ACHROMA_EN => 0,
C_GEN_VIDEO_FORMAT => 0,
C_GEN_CPARITY => 0,
C_SYNC_EN => 0,
C_GEN_VBLANK_POLARITY => 1,
C_GEN_HBLANK_POLARITY => 1,
C_GEN_VSYNC_POLARITY => 1,
C_GEN_HSYNC_POLARITY => 1,
C_GEN_AVIDEO_POLARITY => 1,
C_GEN_ACHROMA_POLARITY => 1,
C_GEN_VACTIVE_SIZE => 720,
C_GEN_HACTIVE_SIZE => 1280,
C_GEN_HFRAME_SIZE => 1650,
C_GEN_F0_VFRAME_SIZE => 750,
C_GEN_HSYNC_START => 1390,
C_GEN_HSYNC_END => 1430,
C_GEN_F0_VBLANK_HSTART => 1280,
C_GEN_F0_VBLANK_HEND => 1280,
C_GEN_F0_VSYNC_VSTART => 724,
C_GEN_F0_VSYNC_VEND => 729,
C_GEN_F0_VSYNC_HSTART => 1280,
C_GEN_F0_VSYNC_HEND => 1280,
C_FSYNC_HSTART0 => 0,
C_FSYNC_VSTART0 => 0,
C_FSYNC_HSTART1 => 0,
C_FSYNC_VSTART1 => 0,
C_FSYNC_HSTART2 => 0,
C_FSYNC_VSTART2 => 0,
C_FSYNC_HSTART3 => 0,
C_FSYNC_VSTART3 => 0,
C_FSYNC_HSTART4 => 0,
C_FSYNC_VSTART4 => 0,
C_FSYNC_HSTART5 => 0,
C_FSYNC_VSTART5 => 0,
C_FSYNC_HSTART6 => 0,
C_FSYNC_VSTART6 => 0,
C_FSYNC_HSTART7 => 0,
C_FSYNC_VSTART7 => 0,
C_FSYNC_HSTART8 => 0,
C_FSYNC_VSTART8 => 0,
C_FSYNC_HSTART9 => 0,
C_FSYNC_VSTART9 => 0,
C_FSYNC_HSTART10 => 0,
C_FSYNC_VSTART10 => 0,
C_FSYNC_HSTART11 => 0,
C_FSYNC_VSTART11 => 0,
C_FSYNC_HSTART12 => 0,
C_FSYNC_VSTART12 => 0,
C_FSYNC_HSTART13 => 0,
C_FSYNC_VSTART13 => 0,
C_FSYNC_HSTART14 => 0,
C_FSYNC_VSTART14 => 0,
C_FSYNC_HSTART15 => 0,
C_FSYNC_VSTART15 => 0,
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_CLK_FREQ_HZ => 100000000,
C_FAMILY => "zynq"
)
port map (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aclken => s_axi_aclken,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
irq => irq,
intc_if => intc_if,
clk => clk,
resetn => resetn,
clken => clken,
det_clken => det_clken,
gen_clken => gen_clken,
fsync_in => fsync_in,
vblank_in => vblank_in,
vsync_in => vsync_in,
hblank_in => hblank_in,
hsync_in => hsync_in,
active_video_in => active_video_in,
active_chroma_in => active_chroma_in,
vblank_out => vblank_out,
vsync_out => vsync_out,
hblank_out => hblank_out,
hsync_out => hsync_out,
active_video_out => active_video_out,
active_chroma_out => active_chroma_out,
fsync_out => fsync_out
);
end architecture STRUCTURE;
|
mit
|
66458c998da4bc86fc77b93497096aaa
| 0.56822 | 2.996163 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_2/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_2_dverif.vhd
| 1 | 6,008 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_2_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pkg.ALL;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_2_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_2_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
PROCESS (RD_CLK,RESET)
BEGIN
IF (RESET = '1') THEN
rd_en_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
rd_en_d1 <= '1';
END IF;
END IF;
END PROCESS;
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_dma_0_wrapper_fifo_generator_v9_3_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
mit
|
ab839cd391d94542edcbf13ac5994092
| 0.574401 | 3.911458 | false | false | false | false |
DanielSouzaBertoldi/VHDL
|
ProjetoFinal/ProjFinal.vhd
| 1 | 9,745 |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ProjFinal IS
PORT(
reset : IN STD_LOGIC;
clock48MHz : IN STD_LOGIC;
LCD_RS, LCD_E : OUT STD_LOGIC;
LCD_RW, LCD_ON : OUT STD_LOGIC;
DATA : INOUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
InstrALU : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 );
clockPB : IN STD_LOGIC
);
END ProjFinal;
ARCHITECTURE exec OF ProjFinal IS
COMPONENT LCD_Display
GENERIC(NumHexDig: Integer:= 11);
PORT(
reset, clk_48Mhz : IN STD_LOGIC;
HexDisplayData : IN STD_LOGIC_VECTOR((NumHexDig*4)-1 DOWNTO 0);
LCD_RS, LCD_E : OUT STD_LOGIC;
LCD_RW : OUT STD_LOGIC;
DATA_BUS : INOUT STD_LOGIC_VECTOR( 7 DOWNTO 0 )
);
END COMPONENT;
COMPONENT Ifetch
PORT(
reset : IN STD_LOGIC;
clock : IN STD_LOGIC;
PC_out : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
Instruction : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
ADDResult : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
Reg31 : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
Beq : IN STD_LOGIC;
Bne : IN STD_LOGIC;
Zero : IN STD_LOGIC;
Jump : IN STD_LOGIC;
Jal : IN STD_LOGIC;
Jr : IN STD_LOGIC;
PC_inc : INOUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
J_Address : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 )
);
END COMPONENT;
COMPONENT Idecode
PORT(
read_data_1 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
read_data_2 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Instruction : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
ALU_result : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
RegWrite : IN STD_LOGIC;
RegDst : IN STD_LOGIC;
Sign_extend : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
clock,reset : IN STD_LOGIC;
MemToReg : IN STD_LOGIC;
read_data : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Jal : IN STD_LOGIC;
L_Address : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
Reg31 : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
a1 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
a2 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
a3 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )
);
END COMPONENT;
COMPONENT Execute
PORT(
read_data_1 : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
read_data_2 : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
ALU_result : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
ALUSrc : IN STD_LOGIC;
SignExtend : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
PC : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
Zero : OUT STD_LOGIC;
ADDResult : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
Sl : IN STD_LOGIC;
Sr : IN STD_LOGIC;
Shamt : IN STD_LOGIC_VECTOR( 4 DOWNTO 0);
ALUOp : IN STD_LOGIC_VECTOR( 1 DOWNTO 0);
Function_opcode : IN STD_LOGIC_VECTOR( 5 DOWNTO 0 )
);
END COMPONENT;
COMPONENT Control
PORT(
Opcode : IN STD_LOGIC_VECTOR( 5 DOWNTO 0 );
Function_opcode : IN STD_LOGIC_VECTOR( 5 DOWNTO 0 );
RegDst : OUT STD_LOGIC;
RegWrite : OUT STD_LOGIC;
ALUSrc : OUT STD_LOGIC;
MemToReg : OUT STD_LOGIC;
MemRead : OUT STD_LOGIC;
MemWrite : OUT STD_LOGIC;
Beq : INOUT STD_LOGIC;
Bne : INOUT STD_LOGIC;
Jump : INOUT STD_LOGIC;
Jal : INOUT STD_LOGIC;
Jr : INOUT STD_LOGIC;
Sl : INOUT STD_LOGIC;
Sr : INOUT STD_LOGIC;
ALUOp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 )
);
END COMPONENT;
COMPONENT dmemory
PORT(
read_data : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
address : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
write_data : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
MemRead, Memwrite : IN STD_LOGIC;
clock,reset : IN STD_LOGIC
);
END COMPONENT;
SIGNAL DataInstr : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL DisplayData : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL PCAddr : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL RegDst : STD_LOGIC;
SIGNAL RegWrite : STD_LOGIC;
SIGNAL ALUResult : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL SignExtend : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL readData1 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL readData2 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL HexDisplayDT : STD_LOGIC_VECTOR( 43 DOWNTO 0 );
SIGNAL MemToReg : STD_LOGIC;
SIGNAL MemRead : STD_LOGIC;
SIGNAL MemWrite : STD_LOGIC;
SIGNAL ALUSrc : STD_LOGIC;
SIGNAL read_data : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL ADDResult : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL Zero : STD_LOGIC;
SIGNAL clock : STD_LOGIC;
SIGNAL Beq : STD_LOGIC;
SIGNAL Bne : STD_LOGIC;
SIGNAL Jump : STD_LOGIC;
SIGNAL Jal : STD_LOGIC;
SIGNAL Jr : STD_LOGIC;
SIGNAL Sl : STD_LOGIC;
SIGNAL Sr : STD_LOGIC;
SIGNAL PC_inc : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL ALUOp : STD_LOGIC_VECTOR( 1 DOWNTO 0 );
SIGNAL Reg31 : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL a1 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL a2 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL a3 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
BEGIN
LCD_ON <= '1';
clock <= NOT clockPB;
-- Inserir MUX para DisplayData
DisplayData <= ALUResult WHEN InstrALU = "001" ELSE
a1 WHEN InstrALU = "010" ELSE
a2 WHEN InstrALU = "011" ELSE
a3 WHEN InstrALU = "100" ELSE
DataInstr;
HexDisplayDT <= "0000"&PCAddr&DisplayData;
lcd: LCD_Display
PORT MAP(
reset => reset,
clk_48Mhz => clock48MHz,
HexDisplayData => HexDisplayDT,
LCD_RS => LCD_RS,
LCD_E => LCD_E,
LCD_RW => LCD_RW,
DATA_BUS => DATA
);
IFT: Ifetch
PORT MAP(
reset => reset,
clock => clock,
PC_out => PCAddr,
Instruction => DataInstr,
ADDResult => ADDResult,
Reg31 => Reg31,
Beq => Beq,
Bne => Bne,
Zero => Zero,
Jump => Jump,
Jal => Jal,
Jr => Jr,
PC_inc => PC_inc,
J_Address => DataInstr( 7 DOWNTO 0 )
);
CTR: Control
PORT MAP(
Opcode => DataInstr( 31 DOWNTO 26 ),
Function_opcode => DataInstr( 5 DOWNTO 0 ),
RegDst => RegDst,
RegWrite => RegWrite,
MemRead => MemRead,
MemWrite => MemWrite,
MemToReg => MemToReg,
ALUSrc => ALUSrc,
Beq => Beq,
Bne => Bne,
Jump => Jump,
Jal => Jal,
Jr => Jr,
Sl => Sl,
Sr => Sr,
ALUOp => ALUOp( 1 DOWNTO 0 )
);
IDEC: Idecode
PORT MAP(
read_data_1 => readData1,
read_data_2 => readData2,
Instruction => dataInstr,
ALU_result => ALUResult,
RegWrite => RegWrite,
RegDst => RegDst,
Sign_extend => SignExtend,
clock => clock,
reset => reset,
MemToReg => MemToReg,
read_data => read_data,
Jal => Jal,
L_Address => PC_inc,
Reg31 => Reg31,
a1 => a1,
a2 => a2,
a3 => a3
);
EXE: Execute
PORT MAP(
read_data_1 => readData1,
read_data_2 => readData2,
ALU_result => ALUResult,
ALUSrc => ALUSrc,
SignExtend => SignExtend,
PC => PCAddr,
Zero => Zero,
ADDResult => ADDResult,
Sl => Sl,
Sr => Sr,
Shamt => DataInstr( 10 DOWNTO 6 ),
ALUOp => ALUOp,
Function_opcode => DataInstr( 5 DOWNTO 0 )
);
DMEM: dmemory
PORT MAP(
read_data => read_data,
address => ALUResult( 7 DOWNTO 0 ),
write_data => readData2,
MemRead => MemRead,
MemWrite => MemWrite,
clock => clock,
reset => reset
);
END exec;
|
gpl-3.0
|
6e7439d24f107b181b232b59e0dec581
| 0.439405 | 4.175236 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_2/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_2_tb.vhd
| 1 | 6,199 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_2_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pkg.ALL;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_2_tb IS
END ENTITY;
ARCHITECTURE system_axi_dma_0_wrapper_fifo_generator_v9_3_2_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_2_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2100 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_dma_0_wrapper_fifo_generator_v9_3_2_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_dma_0_wrapper_fifo_generator_v9_3_2_synth
system_axi_dma_0_wrapper_fifo_generator_v9_3_2_synth_inst:system_axi_dma_0_wrapper_fifo_generator_v9_3_2_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 20
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
mit
|
b14f2a6caddafe8fc4398924394f0be6
| 0.62623 | 4.007111 | false | false | false | false |
meninge/dauphin
|
test_bench/test_fsm.vhd
| 1 | 5,013 |
----------------------------------------------------------------
-- uut:
-- fsm.vhd
-- description:
-- simple test_bench to verify fsm behavior in simple cases
-- expected result:
-- fsm should behave as we describe in the fsm graph
----------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;
-- entity declaration for your testbench.Dont declare any ports here
ENTITY test_fsm IS
END test_fsm;
ARCHITECTURE behavior OF test_fsm IS
constant WDATA : natural := 32;
-- add component under test
component fsm
generic ( NB_NEURONS : natural);
port (
reset : in std_logic;
clk : in std_logic;
-- Control signals
ctrl_we_mode : out std_logic;
ctrl_we_shift : out std_logic;
ctrl_we_valid : out std_logic;
ctrl_accu_clear : out std_logic;
ctrl_accu_add : out std_logic;
ctrl_shift_en : out std_logic;
ctrl_shift_copy : out std_logic;
-- Address used for Read and Write
addr : out std_logic_vector(9 downto 0);
-- Ports for Write Enable
n0_we_prev : out std_logic;
nN_we_next : in std_logic;
-- Sensors, for synchronization with the controller
sensor_shift : in std_logic;
sensor_copy : in std_logic;
sensor_we_mode : in std_logic;
sensor_we_shift : in std_logic;
sensor_we_valid : in std_logic;
-- inputs
fsm_mode : in std_logic;
-- out FIFO
out_fifo_in_cnt : in std_logic_vector(15 downto 0)
);
end component;
signal clk : std_logic := '0';
signal reset : std_logic := '0';
-- Control signals
signal ctrl_we_mode : std_logic := '0';
signal ctrl_we_shift : std_logic := '0';
signal ctrl_we_valid : std_logic := '0';
signal ctrl_accu_clear : std_logic := '0';
signal ctrl_accu_add : std_logic := '0';
signal ctrl_shift_en : std_logic := '0';
signal ctrl_shift_copy : std_logic := '0';
-- Address used for Read and Write
signal addr : std_logic_vector(9 downto 0);
-- Ports for Write Enable
signal n0_we_prev : std_logic := '0';
signal nN_we_next : std_logic := '0';
-- Sensors, for synchronization with the controller
signal sensor_shift : std_logic := '0';
signal sensor_copy : std_logic := '0';
signal sensor_we_mode : std_logic := '0';
signal sensor_we_shift : std_logic := '0';
signal sensor_we_valid : std_logic := '0';
signal out_fifo_in_cnt : std_logic_vector(15 downto 0);
-- puts
signal fsm_mode : std_logic := '0';
-- clock period definitions
constant clk_period : time := 1 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut: fsm
generic map (
NB_NEURONS => 1
)
port map (
reset => reset,
clk => clk ,
-- Control signals
ctrl_we_mode => ctrl_we_mode ,
ctrl_we_shift => ctrl_we_shift ,
ctrl_we_valid => ctrl_we_valid ,
ctrl_accu_clear => ctrl_accu_clear,
ctrl_accu_add => ctrl_accu_add ,
ctrl_shift_en => ctrl_shift_en ,
ctrl_shift_copy => ctrl_shift_copy,
-- Address used for Read and Write
addr => addr ,
-- Ports for Write Enable
n0_we_prev => n0_we_prev ,
nN_we_next => nN_we_next ,
-- Sensors, for synchronization with the controller
sensor_shift => sensor_shift ,
sensor_copy => sensor_copy ,
sensor_we_mode => sensor_we_mode ,
sensor_we_shift => sensor_we_shift,
sensor_we_valid => sensor_we_valid,
-- inputs
fsm_mode => fsm_mode,
-- out FIFO
out_fifo_in_cnt => out_fifo_in_cnt
);
-- Clock process definitions( clock with 50% duty cycle is generated here.
clk_process :process
begin
clk <= '1';
wait for clk_period/2; --for 0.5 ns signal is '1'.
clk <= '0';
wait for clk_period/2; --for next 0.5 ns signal is '0'.
end process;
-- Stimulus process
stim_proc: process
begin
wait for 1 ns;
-- reset component
reset <= '1';
fsm_mode <= '0';
wait for 1 ns;
-- accu_mode
reset <= '0';
fsm_mode <= '0';
wait for 1 ns;
-- data incoming accu_data
reset <= '0';
sensor_we_valid <= '1';
wait for 2000 ns;
-- weight mode
reset <= '0';
sensor_we_valid <= '0';
fsm_mode <= '1';
wait for 1 ns;
-- neuron is in weight mode
sensor_we_mode <= '1';
fsm_mode <= '0';
reset <= '0';
wait for 2 ns;
-- neuron has copied buffer
-- neuron shifted reg_config
sensor_copy <= '1';
sensor_we_shift <= '1';
sensor_we_mode <= '0';
wait for 1 ns;
-- data is incoming
sensor_copy <= '0';
sensor_we_shift <= '0';
sensor_we_valid <= '1';
wait for 2000 ns;
-- mirror chain received shift
sensor_shift <= '1';
sensor_we_valid <= '0';
wait for 1 ns;
sensor_shift <= '0';
wait;
end process;
END;
|
mit
|
6bfbbc158bc59f6bfb85409431922975
| 0.574506 | 3.081131 | false | false | false | false |
groggemans/block-mario
|
Broncode/CMU.vhd
| 1 | 1,941 |
--
-- @file CMU.vhd
-- @date December, 2013
-- @author G. Roggemans <[email protected]>
-- @copyright Copyright (c) GROG [https://grog.be] 2013, All Rights Reserved
--
-- This application is free software: you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- This application is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
-- for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this application. If not, see <http://www.gnu.org/licenses/>.
--
--
-- entity CMU
--
-- CMU(Clock Managment Unit) verzorgt de verscheidene klokken die gebruikt worden in dit project
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CMU is
Port ( clk : in STD_LOGIC; -- basis klok 50Mhz
clk_25MHz : out STD_LOGIC; -- uitgang klok 25Mhz
clk_25Hz : out STD_LOGIC); -- uitgang klok 25Hz
end CMU;
architecture Behavioral of CMU is
signal c_clk_25MHz : STD_LOGIC:='0'; -- klok 25Mhz
signal c_clk_25Hz : STD_LOGIC:='0'; -- klok 25Hz
signal count : integer range 0 to 999999; -- counter value
begin
process (clk) begin
if rising_edge (clk) then
c_clk_25MHz <= not c_clk_25MHz; -- telkens op rising edge togle geeft 50Mhz/2 -> 25Mhz
if count = 999999 then -- telken op rising maar slechts om de (50Mhz/2) / 1 000 000 -> 25Hz
c_clk_25Hz <= not c_clk_25Hz;
count <= 0;
else
count <= count + 1;
end if;
end if;
end process;
clk_25MHz <= c_clk_25MHz;
clk_25Hz <= c_clk_25Hz;
end Behavioral;
|
lgpl-3.0
|
9826e6fc5e9b6402cbd42866d829869a
| 0.654817 | 3.491007 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pctrl.vhd
| 1 | 15,659 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
mit
|
b4b569cf9383d607f5c57816d7452203
| 0.525193 | 3.365356 | false | false | false | false |
groggemans/block-mario
|
Broncode/Main.vhd
| 1 | 9,846 |
--
-- @file Main.vhd
-- @date December, 2013
-- @author G. Roggemans <[email protected]>
-- @copyright Copyright (c) GROG [https://grog.be] 2013, All Rights Reserved
--
-- This application is free software: you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- This application is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
-- for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this application. If not, see <http://www.gnu.org/licenses/>.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.sig_pkg.all;
entity Block_Mario is
Port ( mclk: in STD_LOGIC;
HSYNC : out STD_LOGIC;
VSYNC : out STD_LOGIC;
OutRed : out STD_LOGIC_VECTOR (2 downto 0);
OutGreen : out STD_LOGIC_VECTOR (2 downto 0);
OutBlue : out STD_LOGIC_VECTOR (2 downto 1);
PS2C : in STD_LOGIC;
PS2D : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR (6 downto 0);
dp : out STD_LOGIC_VECTOR (0 downto 0);
an : out STD_LOGIC_VECTOR (3 downto 0);
sw : in STD_LOGIC_VECTOR (7 downto 0));
end Block_Mario;
architecture Behavioral of Block_Mario is
component VGA_driver is
Port ( clk_25MHz: in std_logic;
color: in std_logic_vector (7 downto 0);
HSYNC : out STD_LOGIC;
VSYNC : out STD_LOGIC;
OutRed : out STD_LOGIC_VECTOR (2 downto 0);
OutGreen : out STD_LOGIC_VECTOR (2 downto 0);
OutBlue : out STD_LOGIC_VECTOR (2 downto 1);
hmemc : out integer range 0 to 31;
vmemc : out integer range 0 to 23;
hbmpc : out integer range 0 to 19;
vbmpc : out integer range 0 to 19);
end component VGA_driver;
component Color_ROM IS
Port ( clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end component Color_ROM;
component LVL_ROM IS
Port ( clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
end component LVL_ROM;
component RAM IS
Port ( clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
end component RAM;
component MMU is
Port ( clk : in STD_LOGIC;
com : in STD_LOGIC_VECTOR (2 downto 0);
com_ok : inout STD_LOGIC_VECTOR (0 downto 0);
data_in : in core_register;
data_out : out core_register;
f_ram_do : in STD_LOGIC_VECTOR (3 downto 0);
f_ram_di : out STD_LOGIC_VECTOR (3 downto 0);
f_ram_adr : out STD_LOGIC_VECTOR (9 downto 0);
f_ram_we : out STD_LOGIC_VECTOR(0 DOWNTO 0);
lvl_rom_do : in STD_LOGIC_VECTOR (3 downto 0);
lvl_rom_adr : out STD_LOGIC_VECTOR (11 downto 0);
rom_lvl : in integer range 0 to 4;
X : in integer range 0 to 31;
Y : in integer range 0 to 23);
end component MMU;
component Block_Mario_Core is
Port ( clk : in STD_LOGIC;
com : inout STD_LOGIC_VECTOR (2 downto 0);
com_ok : in STD_LOGIC_VECTOR (0 downto 0);
data_in : in core_register;
data_out : out core_register;
rom_lvl : out integer range 0 to 4;
lvl : inout integer range 0 to 10;
the_end : out STD_LOGIC;
X : out integer range 0 to 31;
Y : out integer range 0 to 23;
ps2_data : in STD_LOGIC_VECTOR (7 downto 0));
end component Block_Mario_Core;
component PS2_driver is
Port ( clk: in STD_LOGIC;
clk_slow: in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0);
PS2C : in STD_LOGIC;
PS2D : in STD_LOGIC);
end component PS2_driver;
component CMU is
Port ( clk : in STD_LOGIC;
clk_25MHz : out STD_LOGIC;
clk_25Hz : out STD_LOGIC);
end component CMU;
component sevenSEG_driver is
Port ( lvl : in integer range 0 to 10;
end_game : in STD_LOGIC;
segment : out STD_LOGIC_VECTOR (6 downto 0);
anode : out STD_LOGIC_VECTOR (3 downto 0);
clock : in STD_LOGIC);
end component sevenSEG_driver;
signal clk_25MHz : STD_LOGIC := '0';
signal clk_25Hz : STD_LOGIC := '0';
signal color : STD_LOGIC_VECTOR (7 downto 0);
signal color_mem : STD_LOGIC_VECTOR (7 downto 0);
signal hmemc : integer range 0 to 31;
signal vmemc : integer range 0 to 23;
signal hbmpc : integer range 0 to 19;
signal vbmpc : integer range 0 to 19;
signal bmp_nr_v : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal ps2_data : STD_LOGIC_VECTOR (7 downto 0);
signal c_feed_adr : STD_LOGIC_VECTOR (11 downto 0);
signal f_ram_wra : STD_LOGIC_VECTOR(0 DOWNTO 0) := "0";
signal f_ram_wrb : STD_LOGIC_VECTOR(0 DOWNTO 0) := "0";
signal f_ram_adra : STD_LOGIC_VECTOR (9 downto 0);
signal f_ram_adrb : STD_LOGIC_VECTOR (9 downto 0);
signal f_ram_dia : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal f_ram_dib : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal f_ram_dob : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal lvl_rom_adr : STD_LOGIC_VECTOR(11 DOWNTO 0);
signal lvl_rom_do : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal rom_lvl : integer range 0 to 4 := 0;
signal lvl : integer range 0 to 10 := 0;
signal the_end : STD_LOGIC := '0';
signal X : integer range 0 to 31;
signal Y : integer range 0 to 23;
signal com : STD_LOGIC_VECTOR ( 2 downto 0) := "000";
signal com_ok : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal data_cm : core_register;
signal data_mc : core_register;
signal bmp_nr_v_buf : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal hbmpc_buf : integer range 0 to 19 := 0;
signal vbmpc_buf : integer range 0 to 19 := 0;
begin
process (clk_25MHz) begin
if rising_edge(clk_25MHz) then
-- buffers voor timing in orde te krijgen
bmp_nr_v_buf <= bmp_nr_v;
hbmpc_buf <= hbmpc;
vbmpc_buf <= vbmpc;
-- pixel value color overide voor vaste kleuren
if bmp_nr_v_buf >= "1010" then
case bmp_nr_v_buf is
when "1010" => color <= "11111111";
when "1011" => color <= "00000000";
when "1100" => color <= sw; --"11111111"; -- schakelaars voor experimenteren met kleuren
when "1101" => color <= "10111100";
when "1110" => color <= "10111001";
when others => color <= "11101000";
end case;
else
color <= color_mem;
end if;
end if;
end process;
process (mclk) begin
if rising_edge (mclk) then
-- adressen voor scherm sturing bepalen
c_feed_adr <= std_logic_vector(to_unsigned(((conv_integer(unsigned(bmp_nr_v)) * 400) + (vbmpc_buf * 20) + hbmpc_buf ),12));
f_ram_adra <= std_logic_vector(to_unsigned(((vmemc * 32) + hmemc),10));
dp <= "1"; -- dubbele punt van de 7 segment uitzetten
end if;
end process;
VGA: VGA_driver
Port map ( clk_25MHz => clk_25MHz,
color => color,
HSYNC => HSYNC,
VSYNC => VSYNC,
OutRed => OutRed,
OutGreen => OutGreen,
OutBlue => OutBlue,
hmemc => hmemc,
vmemc => vmemc,
hbmpc => hbmpc,
vbmpc => vbmpc);
Color_feed: Color_ROM
port map( clka => clk_25MHz,
addra => c_feed_adr,
douta => color_mem);
Level_Rom: LVL_ROM
port map ( clka => mclk,
addra => lvl_rom_adr,
douta => lvl_rom_do);
Field_ram: RAM
port map ( clka => mclk,
wea => f_ram_wra,
addra => f_ram_adra,
dina => f_ram_dia,
douta => bmp_nr_v,
clkb => clk_25MHz,
web => f_ram_wrb,
addrb => f_ram_adrb,
dinb => f_ram_dib,
doutb => f_ram_dob);
mem_controle: MMU
Port map ( clk => clk_25MHz,
com => com,
com_ok => com_ok,
data_in => data_cm,
data_out => data_mc,
f_ram_do => f_ram_dob,
f_ram_di => f_ram_dib,
f_ram_adr => f_ram_adrb,
f_ram_we => f_ram_wrb,
lvl_rom_do => lvl_rom_do,
lvl_rom_adr => lvl_rom_adr,
rom_lvl => rom_lvl,
X => X,
Y => Y);
core: Block_Mario_core
Port map( clk => clk_25MHz,
com => com,
com_ok => com_ok,
data_in => data_mc,
data_out => data_cm,
rom_lvl => rom_lvl,
lvl => lvl,
the_end => the_end,
X => X,
Y => Y,
ps2_data => ps2_data);
PS2_in: PS2_driver
Port map ( clk => clk_25MHz,
clk_slow => clk_25Hz,
data_out => ps2_data,
PS2C => PS2C,
PS2D => PS2D);
Klok : CMU
Port map ( clk => mclk,
clk_25MHz => clk_25MHz,
clk_25Hz => clk_25Hz);
lvl_disp : sevenSEG_driver
Port map ( lvl => lvl,
end_game => the_end,
segment => seg,
anode => an,
clock => mclk);
end Behavioral;
|
lgpl-3.0
|
66dc3bc39debf9279037f24389a72f8b
| 0.565915 | 3.443861 | false | false | false | false |
meninge/dauphin
|
myaxifullmaster_v1_0.vhd
| 1 | 14,936 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity myaxifullmaster_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 6;
-- Parameters of Axi Master Bus Interface M00_AXI
C_M00_AXI_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"40000000";
C_M00_AXI_BURST_LEN : integer := 16;
C_M00_AXI_ID_WIDTH : integer := 1;
C_M00_AXI_ADDR_WIDTH : integer := 32;
C_M00_AXI_DATA_WIDTH : integer := 32;
C_M00_AXI_AWUSER_WIDTH : integer := 0;
C_M00_AXI_ARUSER_WIDTH : integer := 0;
C_M00_AXI_WUSER_WIDTH : integer := 0;
C_M00_AXI_RUSER_WIDTH : integer := 0;
C_M00_AXI_BUSER_WIDTH : integer := 0
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic;
-- Ports of Axi Master Bus Interface M00_AXI
m00_axi_aclk : in std_logic;
m00_axi_aresetn : in std_logic;
m00_axi_awid : out std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0);
m00_axi_awaddr : out std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0);
m00_axi_awlen : out std_logic_vector(7 downto 0);
m00_axi_awsize : out std_logic_vector(2 downto 0);
m00_axi_awburst : out std_logic_vector(1 downto 0);
m00_axi_awlock : out std_logic;
m00_axi_awcache : out std_logic_vector(3 downto 0);
m00_axi_awprot : out std_logic_vector(2 downto 0);
m00_axi_awqos : out std_logic_vector(3 downto 0);
m00_axi_awuser : out std_logic_vector(C_M00_AXI_AWUSER_WIDTH-1 downto 0);
m00_axi_awvalid : out std_logic;
m00_axi_awready : in std_logic;
m00_axi_wdata : out std_logic_vector(C_M00_AXI_DATA_WIDTH-1 downto 0);
m00_axi_wstrb : out std_logic_vector(C_M00_AXI_DATA_WIDTH/8-1 downto 0);
m00_axi_wlast : out std_logic;
m00_axi_wuser : out std_logic_vector(C_M00_AXI_WUSER_WIDTH-1 downto 0);
m00_axi_wvalid : out std_logic;
m00_axi_wready : in std_logic;
m00_axi_bid : in std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0);
m00_axi_bresp : in std_logic_vector(1 downto 0);
m00_axi_buser : in std_logic_vector(C_M00_AXI_BUSER_WIDTH-1 downto 0);
m00_axi_bvalid : in std_logic;
m00_axi_bready : out std_logic;
m00_axi_arid : out std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0);
m00_axi_araddr : out std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0);
m00_axi_arlen : out std_logic_vector(7 downto 0);
m00_axi_arsize : out std_logic_vector(2 downto 0);
m00_axi_arburst : out std_logic_vector(1 downto 0);
m00_axi_arlock : out std_logic;
m00_axi_arcache : out std_logic_vector(3 downto 0);
m00_axi_arprot : out std_logic_vector(2 downto 0);
m00_axi_arqos : out std_logic_vector(3 downto 0);
m00_axi_aruser : out std_logic_vector(C_M00_AXI_ARUSER_WIDTH-1 downto 0);
m00_axi_arvalid : out std_logic;
m00_axi_arready : in std_logic;
m00_axi_rid : in std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0);
m00_axi_rdata : in std_logic_vector(C_M00_AXI_DATA_WIDTH-1 downto 0);
m00_axi_rresp : in std_logic_vector(1 downto 0);
m00_axi_rlast : in std_logic;
m00_axi_ruser : in std_logic_vector(C_M00_AXI_RUSER_WIDTH-1 downto 0);
m00_axi_rvalid : in std_logic;
m00_axi_rready : out std_logic
);
end myaxifullmaster_v1_0;
architecture arch_imp of myaxifullmaster_v1_0 is
-- component declaration
component myaxifullmaster_v1_0_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
mymaster_addr_inw : out std_logic_vector(31 downto 0);
mymaster_addr_inr : out std_logic_vector(31 downto 0);
mymaster_burstnb_inw : out std_logic_vector(31 downto 0);
mymaster_burstnb_inr : out std_logic_vector(31 downto 0);
mymaster_startw : out std_logic;
mymaster_startr : out std_logic;
mymaster_busyw : in std_logic;
mymaster_busyr : in std_logic;
mymaster_sensor : in std_logic_vector(31 downto 0); -- For various debug signals
mymaster_fifor_data : in std_logic_vector(31 downto 0);
mymaster_fifor_en : in std_logic;
mymaster_fifor_cnt : out std_logic_vector(15 downto 0);
mymaster_fifow_data : out std_logic_vector(31 downto 0);
mymaster_fifow_en : in std_logic;
mymaster_fifow_cnt : out std_logic_vector(15 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component myaxifullmaster_v1_0_S00_AXI;
component myaxifullmaster_v1_0_M00_AXI is
generic (
C_M_AXI_BURST_LEN : integer := 16;
C_M_AXI_ID_WIDTH : integer := 1;
C_M_AXI_ADDR_WIDTH : integer := 32;
C_M_AXI_DATA_WIDTH : integer := 32;
C_M_AXI_AWUSER_WIDTH : integer := 0;
C_M_AXI_ARUSER_WIDTH : integer := 0;
C_M_AXI_WUSER_WIDTH : integer := 0;
C_M_AXI_RUSER_WIDTH : integer := 0;
C_M_AXI_BUSER_WIDTH : integer := 0
);
port (
mymaster_addr_inw : in std_logic_vector(31 downto 0);
mymaster_addr_inr : in std_logic_vector(31 downto 0);
mymaster_startw : in std_logic;
mymaster_startr : in std_logic;
mymaster_busyw : out std_logic;
mymaster_busyr : out std_logic;
mymaster_sensor : out std_logic_vector(31 downto 0); -- For various debug signals
mymaster_burstnb_inw : in std_logic_vector(31 downto 0);
mymaster_burstnb_inr : in std_logic_vector(31 downto 0);
mymaster_fifor_data : out std_logic_vector(31 downto 0);
mymaster_fifor_en : out std_logic;
mymaster_fifor_cnt : in std_logic_vector(15 downto 0);
mymaster_fifow_data : in std_logic_vector(31 downto 0);
mymaster_fifow_en : out std_logic;
mymaster_fifow_cnt : in std_logic_vector(15 downto 0);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
M_AXI_AWID : out std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(C_M_AXI_AWUSER_WIDTH-1 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_WUSER : out std_logic_vector(C_M_AXI_WUSER_WIDTH-1 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BID : in std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BUSER : in std_logic_vector(C_M_AXI_BUSER_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARID : out std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARUSER : out std_logic_vector(C_M_AXI_ARUSER_WIDTH-1 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_RUSER : in std_logic_vector(C_M_AXI_RUSER_WIDTH-1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic
);
end component myaxifullmaster_v1_0_M00_AXI;
signal mymaster_addr_inw : std_logic_vector(31 downto 0);
signal mymaster_addr_inr : std_logic_vector(31 downto 0);
signal mymaster_burstnb_inw : std_logic_vector(31 downto 0);
signal mymaster_burstnb_inr : std_logic_vector(31 downto 0);
signal mymaster_startw : std_logic;
signal mymaster_startr : std_logic;
signal mymaster_busyw : std_logic;
signal mymaster_busyr : std_logic;
signal mymaster_sensor : std_logic_vector(31 downto 0);
signal mymaster_fifor_data : std_logic_vector(31 downto 0);
signal mymaster_fifor_en : std_logic;
signal mymaster_fifor_cnt : std_logic_vector(15 downto 0);
signal mymaster_fifow_data : std_logic_vector(31 downto 0);
signal mymaster_fifow_en : std_logic;
signal mymaster_fifow_cnt : std_logic_vector(15 downto 0);
begin
-- Instantiation of Axi Bus Interface S00_AXI
myaxifullmaster_v1_0_S00_AXI_inst : myaxifullmaster_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
mymaster_addr_inw => mymaster_addr_inw,
mymaster_addr_inr => mymaster_addr_inr,
mymaster_burstnb_inw => mymaster_burstnb_inw,
mymaster_burstnb_inr => mymaster_burstnb_inr,
mymaster_startw => mymaster_startw,
mymaster_startr => mymaster_startr,
mymaster_busyw => mymaster_busyw,
mymaster_busyr => mymaster_busyr,
mymaster_sensor => mymaster_sensor,
mymaster_fifor_data => mymaster_fifor_data,
mymaster_fifor_en => mymaster_fifor_en,
mymaster_fifor_cnt => mymaster_fifor_cnt,
mymaster_fifow_data => mymaster_fifow_data,
mymaster_fifow_en => mymaster_fifow_en,
mymaster_fifow_cnt => mymaster_fifow_cnt,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Instantiation of Axi Bus Interface M00_AXI
myaxifullmaster_v1_0_M00_AXI_inst : myaxifullmaster_v1_0_M00_AXI
generic map (
C_M_AXI_BURST_LEN => C_M00_AXI_BURST_LEN,
C_M_AXI_ID_WIDTH => C_M00_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M00_AXI_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M00_AXI_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M00_AXI_AWUSER_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M00_AXI_ARUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M00_AXI_WUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M00_AXI_RUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M00_AXI_BUSER_WIDTH
)
port map (
mymaster_addr_inw => mymaster_addr_inw,
mymaster_addr_inr => mymaster_addr_inr,
mymaster_burstnb_inw => mymaster_burstnb_inw,
mymaster_burstnb_inr => mymaster_burstnb_inr,
mymaster_startw => mymaster_startw,
mymaster_startr => mymaster_startr,
mymaster_busyw => mymaster_busyw,
mymaster_busyr => mymaster_busyr,
mymaster_sensor => mymaster_sensor,
mymaster_fifor_data => mymaster_fifor_data,
mymaster_fifor_en => mymaster_fifor_en,
mymaster_fifor_cnt => mymaster_fifor_cnt,
mymaster_fifow_data => mymaster_fifow_data,
mymaster_fifow_en => mymaster_fifow_en,
mymaster_fifow_cnt => mymaster_fifow_cnt,
M_AXI_ACLK => m00_axi_aclk,
M_AXI_ARESETN => m00_axi_aresetn,
M_AXI_AWID => m00_axi_awid,
M_AXI_AWADDR => m00_axi_awaddr,
M_AXI_AWLEN => m00_axi_awlen,
M_AXI_AWSIZE => m00_axi_awsize,
M_AXI_AWBURST => m00_axi_awburst,
M_AXI_AWLOCK => m00_axi_awlock,
M_AXI_AWCACHE => m00_axi_awcache,
M_AXI_AWPROT => m00_axi_awprot,
M_AXI_AWQOS => m00_axi_awqos,
M_AXI_AWUSER => m00_axi_awuser,
M_AXI_AWVALID => m00_axi_awvalid,
M_AXI_AWREADY => m00_axi_awready,
M_AXI_WDATA => m00_axi_wdata,
M_AXI_WSTRB => m00_axi_wstrb,
M_AXI_WLAST => m00_axi_wlast,
M_AXI_WUSER => m00_axi_wuser,
M_AXI_WVALID => m00_axi_wvalid,
M_AXI_WREADY => m00_axi_wready,
M_AXI_BID => m00_axi_bid,
M_AXI_BRESP => m00_axi_bresp,
M_AXI_BUSER => m00_axi_buser,
M_AXI_BVALID => m00_axi_bvalid,
M_AXI_BREADY => m00_axi_bready,
M_AXI_ARID => m00_axi_arid,
M_AXI_ARADDR => m00_axi_araddr,
M_AXI_ARLEN => m00_axi_arlen,
M_AXI_ARSIZE => m00_axi_arsize,
M_AXI_ARBURST => m00_axi_arburst,
M_AXI_ARLOCK => m00_axi_arlock,
M_AXI_ARCACHE => m00_axi_arcache,
M_AXI_ARPROT => m00_axi_arprot,
M_AXI_ARQOS => m00_axi_arqos,
M_AXI_ARUSER => m00_axi_aruser,
M_AXI_ARVALID => m00_axi_arvalid,
M_AXI_ARREADY => m00_axi_arready,
M_AXI_RID => m00_axi_rid,
M_AXI_RDATA => m00_axi_rdata,
M_AXI_RRESP => m00_axi_rresp,
M_AXI_RLAST => m00_axi_rlast,
M_AXI_RUSER => m00_axi_ruser,
M_AXI_RVALID => m00_axi_rvalid,
M_AXI_RREADY => m00_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
|
mit
|
3bc8dc4cdafc8a93d466e9521af4ee3d
| 0.678763 | 2.484778 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_tb.vhd
| 1 | 6,128 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_tb IS
END ENTITY;
ARCHITECTURE system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2000 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_synth
system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_synth_inst:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 36
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
mit
|
67a70dc15532bac4dc26ddf3cce02240
| 0.63267 | 4.050231 | false | false | false | false |
Drowze/vhdl-calculator
|
AdderSub.vhd
| 1 | 1,090 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY AdderSub is
PORT( mode : IN std_logic; -- ou seja, CIN e seletor do modo
X : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT_ADDERSUB : OUT std_logic);
END AdderSub;
ARCHITECTURE behavior OF AdderSub is
component fulladder is
PORT( cin, x0, y0 : IN std_logic;
s0, cout : OUT std_logic);
END component;
signal C1, C2, C3, C4 : std_logic; --Carries intermediários
signal X0_XOR, X1_XOR, X2_XOR, X3_XOR : std_logic;
BEGIN
X0_XOR <= Y(0) XOR mode;
X1_XOR <= Y(1) XOR mode;
X2_XOR <= Y(2) XOR mode;
X3_XOR <= Y(3) XOR mode;
FA0: fulladder PORT map(X(0), X0_XOR, mode,S(0), C1); -- S0
FA1: fulladder PORT map(X(1), X1_XOR, C1, S(1), C2); -- S1
FA2: fulladder PORT map(X(2), X2_XOR, C2, S(2), C3); -- S2
FA3: fulladder PORT map(X(3), X3_XOR, C3, S(3), C4); -- S3
COUT_ADDERSUB <= C3 XOR C4;
END behavior;
|
gpl-2.0
|
1302d0ad3d851d3a8f7fbda4d4e6113f
| 0.55831 | 2.682266 | false | false | false | false |
thasti/dvbs
|
hdl/mapper/mapper_tb.vhd
| 1 | 1,449 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity mapper_tb is
end mapper_tb;
architecture tb of mapper_tb is
constant width : positive := 8;
-- interface signals
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal clk_en : std_logic := '0';
signal d_valid : std_logic := '0';
signal d_i : std_logic := '0';
signal d_q : std_logic := '0';
signal q_i : std_logic_vector(width-1 downto 0);
signal q_q : std_logic_vector(width-1 downto 0);
begin
dut : entity work.mapper
generic map (width => width)
port map(clk => clk, rst => rst, clk_en => clk_en, d_valid => d_valid, d_i => d_i, d_q => d_q, q_i => q_i, q_q => q_q);
clk <= not clk after 100 ns;
rst <= '0' after 500 ns;
test : process
begin
wait until falling_edge(rst);
wait until rising_edge(clk);
clk_en <= '1';
d_valid <= '1';
d_i <= '0';
d_q <= '0';
wait until rising_edge(clk);
d_valid <= '0';
wait until rising_edge(clk);
d_valid <= '1';
d_i <= '0';
d_q <= '1';
wait until rising_edge(clk);
d_valid <= '0';
wait until rising_edge(clk);
d_valid <= '1';
d_i <= '1';
d_q <= '0';
wait until rising_edge(clk);
d_valid <= '0';
wait until rising_edge(clk);
d_valid <= '1';
d_i <= '1';
d_q <= '1';
wait until rising_edge(clk);
d_valid <= '0';
wait until rising_edge(clk);
clk_en <= '0';
d_i <= '0';
d_q <= '0';
wait;
end process;
end tb;
|
gpl-2.0
|
c84499e263d5166f87599147b42e8d4a
| 0.573499 | 2.37931 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg.vhd
| 1 | 11,785 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_exdes IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg;
PACKAGE BODY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg;
|
mit
|
426badd314a13c925c0a399096c9163a
| 0.519813 | 3.87537 | false | false | false | false |
SamTheDev/VGA-VHDL-Simulator
|
MIRE.vhd
| 1 | 2,604 |
------------------------------------------------------------
-- VGA SimuLator projet VHDL
-- Generate RGB colors based on the Pixel-clk
-- Elhamer Oussama abdelkhalek
-- Generate a Pixel color at each Pixel-clk rising edge
-- No control on the count of received Pixel-clk edges
------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
entity MIRE is
generic ( V_SIZE, H_SIZE : integer);
Port ( Reset : in STD_LOGIC;
Pixel_clk : in STD_LOGIC;
R : out STD_LOGIC_VECTOR (7 downto 0);
G : out STD_LOGIC_VECTOR (7 downto 0);
B : out STD_LOGIC_VECTOR (7 downto 0));
end MIRE;
architecture Behavioral of MIRE is
begin
colors: process (Pixel_clk, Reset)
variable vcount : integer :=0;
variable hcount : integer :=0;
begin
if Reset='1'
then
R <= "11111111" ;
G <= "11111111" ;
B <= "11111111" ;
vcount := 0;
hcount := 0;
elsif (rising_edge(Pixel_clk) and Pixel_clk='1')
then
if(vcount >=0 and vcount < (V_SIZE / 3))
then
if (hcount >=0 and hcount < (H_SIZE /3) )
then
R <= "11111111";
G <= "00000000";
B <= "00000000";
elsif (hcount >=(H_SIZE /3) and hcount <(2 * H_SIZE /3) )
then
R <= "00000000";
G <= "11111111";
B <= "00000000";
elsif (hcount >=(2 * H_SIZE /3) and hcount < H_SIZE )
then
R <= "00000000";
G <= "00000000";
B <= "11111111";
end if;
elsif (vcount >=( V_SIZE / 3) and vcount <( 2 * (V_SIZE / 3)))
then
R <= conv_std_logic_vector((hcount MOD 255),8);
G <= conv_std_logic_vector((hcount MOD 255),8);
B <= conv_std_logic_vector((hcount MOD 255),8);
elsif(vcount >=( 2 * (V_SIZE / 3)) and vcount < V_SIZE)
then
if ((hcount / 5) MOD 2 = 0 and (vcount / 5) MOD 2 = 0 ) or
((hcount / 5) MOD 2 = 1 and (vcount / 5) MOD 2 = 1 )
then
R <= "11111111";
else
R <= "00000000" ;
end if;
if ((hcount / 5) MOD 2 = 0 and (vcount / 5) MOD 2 = 0 ) or
((hcount / 5) MOD 2 = 1 and (vcount / 5) MOD 2 = 1 )
then
G <= "11111111" ;
else
G <= "00000000" ;
end if;
if ((hcount / 5) MOD 2 = 0 and (vcount / 5) MOD 2 = 0 ) or
((hcount / 5) MOD 2 = 1 and (vcount / 5) MOD 2 = 1 )
then
B <= "11111111" ;
else
B <= "00000000" ;
end if;
end if;
if(hcount = (H_SIZE - 1)) then
vcount := (vcount +1) MOD V_SIZE;
end if;
hcount := (hcount +1) MOD H_SIZE;
end if;
end process;
end Behavioral;
|
mit
|
01355e616a3ededdcf0f6c1e73921c03
| 0.511521 | 3.152542 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_1/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_1_dgen.vhd
| 1 | 4,715 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_1_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pkg.ALL;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_1_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_1_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_dma_0_wrapper_fifo_generator_v9_3_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
mit
|
213f68c21f42fee2bd985dec39283b0c
| 0.607211 | 4.07872 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/i2s_ctrl.vhd
| 3 | 16,906 |
------------------------------------------------------------------------------
-- i2s_ctrl.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: i2s_ctrl.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed Aug 15 18:20:40 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.common_types.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity i2s_ctrl is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
BCLK : out STD_LOGIC;
LRCLK : out STD_LOGIC;
SDATA_I : in STD_LOGIC;
SDATA_O : out STD_LOGIC;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity i2s_ctrl;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of i2s_ctrl is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 5;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity work.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity work.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
BCLK => BCLK,
LRCLK => LRCLK,
SDATA_O => SDATA_O,
SDATA_I => SDATA_I,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
mit
|
9af1cd24d3fc5426d99c032ee51e2680
| 0.444458 | 4.19712 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pctrl.vhd
| 1 | 17,171 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL data_chk_wr : STD_LOGIC := '0';
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0 AND C_CH_TYPE /= 2) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
pwr_tb_stop_run:IF(C_CH_TYPE = 2) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE pwr_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
fifo_flags_checks:IF(C_CH_TYPE /= 2) GENERATE
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
END GENERATE fifo_flags_checks;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- Wiring logic data checks
-----------------------------------------------------
wiring_d_chk:IF(C_CH_TYPE = 2) GENERATE
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
data_chk_wr <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF ((DATA_OUT = DATA_IN) AND (FULL = NOT rd_en_i) AND (EMPTY = NOT wr_en_i)) THEN
data_chk_wr <= '0';
ELSE
data_chk_wr <= '1';
END IF;
END IF;
END PROCESS;
data_chk_i <= data_chk_wr;
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
END GENERATE wiring_d_chk;
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
-----------------------------------------------------
-- Wiring logic enable generation
-----------------------------------------------------
axi_pw_enable:IF(C_CH_TYPE = 2) GENERATE
RESET_EN <= '1';
PROCESS(WR_CLK)
BEGIN
IF (WR_CLK'event AND WR_CLK='1') THEN
wr_en_i <= NOT wr_en_i;
rd_en_i <= NOT rd_en_i;
END IF;
END PROCESS;
END GENERATE axi_pw_enable;
END ARCHITECTURE;
|
mit
|
95f1131b65b63837247663ae01427a2d
| 0.520704 | 3.358302 | false | false | false | false |
Drowze/vhdl-calculator
|
projetofinal.vhd
| 1 | 3,559 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY projetofinal IS
PORT (X1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
X2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
somador : IN STD_LOGIC;
subtrator : IN STD_LOGIC;
modulo : IN STD_LOGIC;
salvar : IN STD_LOGIC;
carregar : IN STD_LOGIC;
LED1 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
LED2 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
LED3 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
LED_SALVO : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
SINAL_DE_MENOS : OUT STD_LOGIC_VECTOR(0 TO 3) -- 0: X1, 1: X2, 2: Resultado, 3: salvo
);
END projetofinal;
ARCHITECTURE behavior OF projetofinal IS
COMPONENT bcd
PORT (S : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
F : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END COMPONENT;
COMPONENT AdderSub is
PORT( mode : IN std_logic;
X : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT_ADDERSUB : OUT std_logic);
END COMPONENT;
signal overflow : std_logic; --deu ruim
signal mode : std_logic; --0: soma || 1: sub
signal ONOFF : std_logic; --BCD ligado?
signal resultado : std_logic_vector(3 DOWNTO 0);
signal LED3_aux : STD_LOGIC_VECTOR(6 DOWNTO 0);
signal sinal_resultado : std_logic;
signal LED1_aux : STD_LOGIC_VECTOR(6 DOWNTO 0);
signal salvo : STD_LOGIC_VECTOR(6 DOWNTO 0);
signal sinal_salvo : std_logic;
signal is_it_salvo : std_logic;
BEGIN
process(mode, somador, subtrator) begin
IF (subtrator = '1') THEN
mode <= '1';
ELSE
mode <= '0';
END IF;
end process;
stage0: bcd port map(X1, LED1_aux);
stage1: bcd port map(X2, LED2);
stage2: AdderSub port map(mode, X1, X2, resultado, overflow);
stage3: bcd port map(resultado, LED3_aux);
ONOFF <= somador OR subtrator OR modulo;
SINAL_DE_MENOS(0) <= NOT(X1(3));
SINAL_DE_MENOS(1) <= NOT(X2(3));
process(ONOFF, overflow, modulo, salvar) begin
IF (ONOFF = '0') THEN
LED3(0) <= '1'; LED3(1) <= '1'; LED3(2) <= '1'; LED3(3) <= '1'; LED3(4) <= '1'; LED3(5) <= '1'; LED3(6) <= '1';
ELSIF (modulo = '1') THEN
SINAL_DE_MENOS(2) <= '1';
LED3 <= LED1_aux;
ELSIF (overflow = '1') THEN
LED3(0) <= '0'; LED3(1) <= '0'; LED3(2) <= '0'; LED3(3) <= '0'; LED3(4) <= '1'; LED3(5) <= '1'; LED3(6) <= '0';
ELSE
LED3 <= LED3_aux;
SINAL_DE_MENOS(2) <= NOT(resultado(3) AND ONOFF AND NOT overflow);
END IF;
----------------
IF (modulo = '0') THEN
SINAL_DE_MENOS(2) <= NOT(resultado(3) AND ONOFF AND NOT overflow);
END IF;
----------------
IF (salvar = '1' AND ONOFF = '1') THEN
IF (modulo = '1') THEN
sinal_salvo <= '1';
salvo <= LED1_aux;
is_it_salvo <= '1';
ELSIF (overflow = '0') THEN
sinal_salvo <= NOT(resultado(3) AND ONOFF AND NOT overflow);
salvo <= LED3_aux;
is_it_salvo <= '1';
END IF;
END IF;
IF (carregar = '1' AND is_it_salvo = '1') THEN
LED_SALVO <= salvo;
SINAL_DE_MENOS(3) <= sinal_salvo;
ELSIF (carregar = '1' AND is_it_salvo = '0') THEN
LED_SALVO(0) <= '1'; LED_SALVO(1) <= '1'; LED_SALVO(2) <= '1'; LED_SALVO(3) <= '1'; LED_SALVO(4) <= '1'; LED_SALVO(5) <= '1'; LED_SALVO(6) <= '1';
END IF;
LED1 <= LED1_aux;
end process;
END behavior;
|
gpl-2.0
|
002401b4731c8b78eff04c33df39e015
| 0.537792 | 2.822363 | false | false | false | false |
thasti/dvbs
|
hdl/scrambler/prbs.vhd
| 1 | 1,012 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- implements n-th order prbs with common polynomials y = x^n + x^(n-1) + 1
entity prbs is
generic (
n : positive;
width : positive
);
port (
clk : in std_logic;
clk_en : in std_logic;
rst : in std_logic;
q : out std_logic_vector(width-1 downto 0);
def_val : in std_logic_vector(n-1 downto 0)
);
end entity prbs;
architecture rtl of prbs is
signal sr : std_logic_vector(n-1 downto 0) := def_val;
begin
process
begin
wait until rising_edge(clk);
if rst = '1' then
sr <= def_val;
elsif clk_en = '1' then
for i in 0 to width-1 loop
sr(width-1-i) <= sr(n-1-i) xor sr(n-2-i);
end loop;
for i in 0 to n-width-1 loop
sr(width+i) <= sr(i);
end loop;
end if;
end process;
bla : for i in 0 to width-1 generate
q(width-1-i) <= sr(n-1-i) xor sr(n-2-i);
end generate bla;
assert (n>width) report "mode not supported: n should be greater than width" severity failure;
end architecture rtl;
|
gpl-2.0
|
0c7a908b3c5e0e69d50b84022d02affd
| 0.642292 | 2.555556 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_trem_1.0/sources_1/new/trem.vhd
| 1 | 4,386 |
----------------------------------------------------
-- Vladi & Adi --
-- TAU EE Senior year project --
-- --
--************************************************--
--****************** Trem ************************--
--************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity trem is
Port ( x : in STD_LOGIC_VECTOR(31 downto 0);
y : out STD_LOGIC_VECTOR(31 downto 0);
clk_48 : in std_logic;
clk_190 : in std_logic;
clk_380 : in std_logic;
clk_95 : in std_logic;
clk_48hz : in std_logic;
options : in STD_LOGIC_VECTOR(0 to 3);
en : in STD_LOGIC_VECTOR(0 to 3)
);
end trem;
architecture Behavioral of trem is
signal data_o : STD_LOGIC_VECTOR(31 downto 0);
signal data_i : STD_LOGIC_VECTOR(31 downto 0);
signal temp_vec_64 : STD_LOGIC_VECTOR(63 downto 0);
--*************triangular wave signals*************************
signal count_int: integer ;
signal count_int2: integer;
signal count_int4: integer ;
signal count_int6: integer ;
signal direction: std_logic := '0';
signal direction_s2: std_logic := '0';
signal direction_s4: std_logic := '0';
signal direction_s6: std_logic := '0';
--**********************************************
begin
--*************generate various triangular waves*************************
process(count_int) --tremolo frequency - 1.6hz
begin
if (count_int=30) then
direction <= '1';
end if;
if (count_int=1) then
direction <= '0';
end if;
end process;
dir:process(direction, clk_95)
begin
if rising_edge(clk_95) then
if (direction='0') then
count_int <= count_int+1;
end if;
if (direction='1') then
count_int <= count_int-1;
end if;
end if;
end process;
process(count_int2) --tremolo frequency - 3.2 hz
begin
if (count_int2=30) then
direction_s2 <= '1';
end if;
if (count_int2=1) then
direction_s2 <= '0';
end if;
end process;
dir2:process(direction_s2, clk_190)
begin
if rising_edge(clk_190) then
if (direction_s2='0') then
count_int2 <= count_int2+1;
end if;
if (direction_s2='1') then
count_int2 <= count_int2-1;
end if;
end if;
end process;
process(count_int4) --tremolo frequency - 6.35hz
begin
if (count_int4=30) then
direction_s4 <= '1';
end if;
if (count_int4=1) then
direction_s4 <= '0';
end if;
end process;
dir4:process(direction_s4, clk_380)
begin
if rising_edge(clk_380) then
if (direction_s4='0') then
count_int4 <= count_int4+1;
end if;
if (direction_s4='1') then
count_int4 <= count_int4-1;
end if;
end if;
end process;
process(count_int6) --tremolo frequency - 0.8hz
begin
if (count_int6=30) then
direction_s6 <= '1';
end if;
if (count_int6=1) then
direction_s6 <= '0';
end if;
end process;
dir6:process(direction_s6, clk_48hz)
begin
if rising_edge(clk_48hz) then
if (direction_s6='0') then
count_int6 <= count_int6+1;
end if;
if (direction_s6='1') then
count_int6 <= count_int6-1;
end if;
end if;
end process;
--***********************************************
process (clk_48, options)
begin
if en(2)= '1' then
if rising_edge(clk_48) then
if options="1000" then --tremolo frequency - 1.6hz
temp_vec_64 <= std_logic_vector((signed(x))*count_int); --yes
y <= "00000000" & std_logic_vector(shift_right(signed(temp_vec_64(23 downto 0)),4));
end if;
if options="0100" then --tremolo frequency - 3.2 hz
temp_vec_64 <= std_logic_vector((signed(x))*count_int2);
y <= "00000000" & std_logic_vector(shift_right(signed(temp_vec_64(23 downto 0)),4));
end if;
if options="0010" then --tremolo frequency - 6.35hz
temp_vec_64 <= std_logic_vector((signed(x))*count_int4);
y <= "00000000" & std_logic_vector(shift_right(signed(temp_vec_64(23 downto 0)),4));
end if;
if options="0001" then --tremolo frequency - 0.8hz
temp_vec_64 <= std_logic_vector((signed(x))*count_int6);
y <= "00000000" & std_logic_vector(shift_right(signed(temp_vec_64(23 downto 0)),4));
end if;
end if;
else
y<=x;
end if;
end process;
end Behavioral;
|
mit
|
4112a59e1124b455e3bfc0c9abcddf4c
| 0.546284 | 3.248889 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_2/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_2_dgen.vhd
| 1 | 4,715 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_2_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pkg.ALL;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_2_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_2_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_dma_0_wrapper_fifo_generator_v9_3_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
mit
|
f36006a0ce6d4e11d03028d510b719cc
| 0.607211 | 4.07872 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pkg.vhd
| 1 | 11,785 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(6-1 DOWNTO 0);
DOUT : OUT std_logic_vector(6-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pkg;
PACKAGE BODY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pkg;
|
mit
|
0e67c64332ec0dcce2df0866369bcdae
| 0.519813 | 3.87537 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/slave_attachment.vhd
| 7 | 21,369 |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v1.01.a
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common_types.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
when (S_AXI_ARVALID='1')
else
ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity work.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI_ARVALID,
Bus_RNW_Erly => S_AXI_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
mit
|
4a0296c4a72dce44f32c03c701cf9832
| 0.495297 | 3.988986 | false | false | false | false |
groggemans/block-mario
|
Broncode/PS2_driver.vhd
| 1 | 3,145 |
--
-- @file PS2_Driver.vhd
-- @date December, 2013
-- @author G. Roggemans <[email protected]>
-- @copyright Copyright (c) GROG [https://grog.be] 2013, All Rights Reserved
--
-- This application is free software: you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- This application is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
-- for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this application. If not, see <http://www.gnu.org/licenses/>.
--
--
-- entity PS2_driver
--
-- PS2_driver zorgt voor de uitlezing van het toetsenbord (PS2 interface).
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PS2_driver is
Port ( clk : in STD_LOGIC; -- klok
clk_slow: in STD_LOGIC; -- vertraagde klok
data_out : out STD_LOGIC_VECTOR (7 downto 0); -- PS2 data output
PS2C : in STD_LOGIC; -- PS2_clk pin
PS2D : in STD_LOGIC); -- PS2_data pin
end PS2_driver;
architecture Behavioral of PS2_driver is
signal count : integer range 0 to 10 :=0; -- counter voor inkomende data
signal data_driver: std_logic_vector (10 downto 0); -- vector om inkomende bits in te bewaren
signal data_in : STD_LOGIC_VECTOR (7 downto 0); -- vector om nutige data
signal pulse : STD_LOGIC:='0'; -- hulp var
signal pulsemem : STD_LOGIC:='0'; -- hulp var
signal ipulse : STD_LOGIC:='0'; -- hulp var
signal ipulsemem : STD_LOGIC:='0'; -- hulp var
begin
-- Input van PS2 interface binnen halen
process (PS2C) begin
if (falling_edge (PS2C)) then
count <= count + 1;
data_driver (count)<=PS2D;
if count = 10 then
count <= 0;
data_in <= data_driver (8 downto 1);
ipulse <= not ipulse;
end if;
end if;
end process;
-- Input vertraging
process (clk_slow) begin
if rising_edge (clk_slow) then
-- verandering (input) controleren
if not (ipulsemem = ipulse) then
pulse <= not pulse;
ipulsemem <= ipulse; -- detectie doorgeven aan volgende stap
end if;
end if;
end process;
-- Output timem met interne werking van de andere componenten
process (clk) begin
if rising_edge (clk) then
-- als input binnen gekomen is input naar buiten sturen, anders uitgang resetten
if pulse = pulsemem then
data_out <= "00000000";
else
data_out <= data_in;
pulsemem <= pulse;
end if;
end if;
end process;
end Behavioral;
|
lgpl-3.0
|
6dbf89cfb9e85d619195cbdca2f26815
| 0.605723 | 3.780048 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_3/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pctrl.vhd
| 1 | 16,635 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pkg.ALL;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND FULL = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_dma_0_wrapper_fifo_generator_v9_3_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_dma_0_wrapper_fifo_generator_v9_3_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
mit
|
2db6ea05d52160094cf2d7cc8438a7a1
| 0.523895 | 3.332332 | false | false | false | false |
groggemans/block-mario
|
Broncode/sevenSEG_driver.vhd
| 1 | 2,460 |
--
-- @file sevenSEG_driver.vhd
-- @date December, 2013
-- @author G. Roggemans <[email protected]>
-- @copyright Copyright (c) GROG [https://grog.be] 2013, All Rights Reserved
--
-- This application is free software: you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- This application is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
-- for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this application. If not, see <http://www.gnu.org/licenses/>.
--
--
-- entity sevenSEG_driver
--
-- sevenSEG_driver stuurt 1 van de seven-segment display's op het gebruikte FPGA bordje aan.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity sevenSEG_driver is
Port ( lvl : in integer range 0 to 10 := 0; -- Level van 0 tot 10
end_game : in STD_LOGIC := '0'; -- Indicatie bit voor einde spel
segment : out STD_LOGIC_VECTOR (6 downto 0):= "1111111"; -- segment output
anode : out STD_LOGIC_VECTOR (3 downto 0) := "1111"; -- anode output
clock : in STD_LOGIC); -- klok signaal
end sevenSEG_driver;
architecture Behavioral of sevenSEG_driver is
-- waarde voor segement output per level/einde
type digit is array (0 to 11) of STD_LOGIC_VECTOR (6 downto 0);
constant digits : digit :=(
"1111111", -- 0
"1111001", -- 1
"0100100", -- 2
"0110000", -- 3
"0011001", -- 4
"0010010", -- 5
"0000010", -- 6
"1111000", -- 7
"0000000", -- 8
"0010000", -- 9
"0001110", -- F
"1111111"); -- einde
begin
process (clock) begin
if (rising_edge(clock)) then
-- niet naar buiten sturen
if end_game = '1' then
segment <= digits(11);
-- juiste getal (of F van final) naar buiten sturen
else
segment <= digits(lvl);
end if;
anode <= "1110"; -- enkel het uiterst rechtse segment word gebruikt
end if;
end process;
end Behavioral;
|
lgpl-3.0
|
f6bdc340c00ba5c9725398971a3504fb
| 0.622764 | 3.580786 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_octaver_1.0/sources_1/new/bram_oct.vhd
| 1 | 997 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bram_oct is
generic (
T: integer := 20000;
B: integer := 15 --15 bits for 20,000 memory places
);
port (clk : in std_logic;
we : in std_logic;
addr1 : in std_logic_vector(B-1 downto 0);
addr2 : in std_logic_vector(B-1 downto 0);
di : in std_logic_vector(31 downto 0); --32 bit word
do1 : out std_logic_vector(31 downto 0);
do2 : out std_logic_vector(31 downto 0));
end bram_oct;
architecture arch of bram_oct is
type ram_type is array (0 to T-1) of std_logic_vector (31 downto 0);
signal RAM : ram_type:= (T-1 downto 0 => x"00000000"); --define and initialize RAM
begin
process (clk)
begin
if rising_edge(clk) then
if we = '1' then
RAM(conv_integer(addr1)) <= di;
end if;
do1 <= RAM(conv_integer(addr1));
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
do2 <= RAM(conv_integer(addr2));
end if;
end process;
end arch;
|
mit
|
57039b30657865cab6dd93c22d08c056
| 0.644935 | 2.958457 | false | false | false | false |
medav/conware
|
conware_test/system/hdl/system.vhd
| 1 | 134,730 |
-------------------------------------------------------------------------------
-- system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
SWs_8Bits_TRI_IO : inout std_logic_vector(7 downto 0);
BTNs_5Bits_TRI_IO : inout std_logic_vector(4 downto 0);
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB : in std_logic;
processing_system7_0_PS_CLK : in std_logic;
processing_system7_0_PS_PORB : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
conware_0_M_AXIS_TVALID_pin : out std_logic;
conware_0_M_AXIS_TLAST_pin : out std_logic;
conware_0_M_AXIS_TREADY_pin : out std_logic;
conware_0_M_AXIS_TKEEP_pin : out std_logic_vector(3 downto 0);
conware_0_ACLK_pin : out std_logic;
cownare_ctl_0_in_states_pin : out std_logic_vector(7 downto 0)
);
end system;
architecture STRUCTURE of system is
component system_axi4lite_0_wrapper is
port (
INTERCONNECT_ACLK : in std_logic;
INTERCONNECT_ARESETN : in std_logic;
S_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
M_AXI_ARESET_OUT_N : out std_logic_vector(3 downto 0);
IRQ : out std_logic;
S_AXI_ACLK : in std_logic_vector(0 to 0);
S_AXI_AWID : in std_logic_vector(11 downto 0);
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_AWUSER : in std_logic_vector(0 to 0);
S_AXI_AWVALID : in std_logic_vector(0 to 0);
S_AXI_AWREADY : out std_logic_vector(0 to 0);
S_AXI_WID : in std_logic_vector(11 downto 0);
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WLAST : in std_logic_vector(0 to 0);
S_AXI_WUSER : in std_logic_vector(0 to 0);
S_AXI_WVALID : in std_logic_vector(0 to 0);
S_AXI_WREADY : out std_logic_vector(0 to 0);
S_AXI_BID : out std_logic_vector(11 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BUSER : out std_logic_vector(0 to 0);
S_AXI_BVALID : out std_logic_vector(0 to 0);
S_AXI_BREADY : in std_logic_vector(0 to 0);
S_AXI_ARID : in std_logic_vector(11 downto 0);
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ARUSER : in std_logic_vector(0 to 0);
S_AXI_ARVALID : in std_logic_vector(0 to 0);
S_AXI_ARREADY : out std_logic_vector(0 to 0);
S_AXI_RID : out std_logic_vector(11 downto 0);
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic_vector(0 to 0);
S_AXI_RUSER : out std_logic_vector(0 to 0);
S_AXI_RVALID : out std_logic_vector(0 to 0);
S_AXI_RREADY : in std_logic_vector(0 to 0);
M_AXI_ACLK : in std_logic_vector(3 downto 0);
M_AXI_AWID : out std_logic_vector(47 downto 0);
M_AXI_AWADDR : out std_logic_vector(127 downto 0);
M_AXI_AWLEN : out std_logic_vector(31 downto 0);
M_AXI_AWSIZE : out std_logic_vector(11 downto 0);
M_AXI_AWBURST : out std_logic_vector(7 downto 0);
M_AXI_AWLOCK : out std_logic_vector(7 downto 0);
M_AXI_AWCACHE : out std_logic_vector(15 downto 0);
M_AXI_AWPROT : out std_logic_vector(11 downto 0);
M_AXI_AWREGION : out std_logic_vector(15 downto 0);
M_AXI_AWQOS : out std_logic_vector(15 downto 0);
M_AXI_AWUSER : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic_vector(3 downto 0);
M_AXI_AWREADY : in std_logic_vector(3 downto 0);
M_AXI_WID : out std_logic_vector(47 downto 0);
M_AXI_WDATA : out std_logic_vector(127 downto 0);
M_AXI_WSTRB : out std_logic_vector(15 downto 0);
M_AXI_WLAST : out std_logic_vector(3 downto 0);
M_AXI_WUSER : out std_logic_vector(3 downto 0);
M_AXI_WVALID : out std_logic_vector(3 downto 0);
M_AXI_WREADY : in std_logic_vector(3 downto 0);
M_AXI_BID : in std_logic_vector(47 downto 0);
M_AXI_BRESP : in std_logic_vector(7 downto 0);
M_AXI_BUSER : in std_logic_vector(3 downto 0);
M_AXI_BVALID : in std_logic_vector(3 downto 0);
M_AXI_BREADY : out std_logic_vector(3 downto 0);
M_AXI_ARID : out std_logic_vector(47 downto 0);
M_AXI_ARADDR : out std_logic_vector(127 downto 0);
M_AXI_ARLEN : out std_logic_vector(31 downto 0);
M_AXI_ARSIZE : out std_logic_vector(11 downto 0);
M_AXI_ARBURST : out std_logic_vector(7 downto 0);
M_AXI_ARLOCK : out std_logic_vector(7 downto 0);
M_AXI_ARCACHE : out std_logic_vector(15 downto 0);
M_AXI_ARPROT : out std_logic_vector(11 downto 0);
M_AXI_ARREGION : out std_logic_vector(15 downto 0);
M_AXI_ARQOS : out std_logic_vector(15 downto 0);
M_AXI_ARUSER : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic_vector(3 downto 0);
M_AXI_ARREADY : in std_logic_vector(3 downto 0);
M_AXI_RID : in std_logic_vector(47 downto 0);
M_AXI_RDATA : in std_logic_vector(127 downto 0);
M_AXI_RRESP : in std_logic_vector(7 downto 0);
M_AXI_RLAST : in std_logic_vector(3 downto 0);
M_AXI_RUSER : in std_logic_vector(3 downto 0);
M_AXI_RVALID : in std_logic_vector(3 downto 0);
M_AXI_RREADY : out std_logic_vector(3 downto 0);
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
INTERCONNECT_ARESET_OUT_N : out std_logic;
DEBUG_AW_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AR_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AW_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AW_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AW_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AW_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AW_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AR_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AR_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AR_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AR_TARGET : out std_logic_vector(7 downto 0);
DEBUG_B_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_R_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_R_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_BID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_BID_ERROR : out std_logic;
DEBUG_RID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_RID_ERROR : out std_logic;
DEBUG_SR_SC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SR_SC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SR_SC_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SR_SC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SR_SC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SC_SF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SC_SF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SC_SF_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SC_SF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SC_SF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SF_CB_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SF_CB_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SF_CB_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SF_CB_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SF_CB_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_CB_MF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_CB_MF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_CB_MF_BRESP : out std_logic_vector(15 downto 0);
DEBUG_CB_MF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_CB_MF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MF_MC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MF_MC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MF_MC_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MF_MC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MF_MC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MC_MP_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MC_MP_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MC_MP_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MC_MP_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MC_MP_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MP_MR_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MP_MR_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MP_MR_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MP_MR_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MP_MR_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_WDATACONTROL : out std_logic_vector(6 downto 0)
);
end component;
component system_sws_8bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(7 downto 0);
GPIO_IO_O : out std_logic_vector(7 downto 0);
GPIO_IO_T : out std_logic_vector(7 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
end component;
component system_btns_5bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(4 downto 0);
GPIO_IO_O : out std_logic_vector(4 downto 0);
GPIO_IO_T : out std_logic_vector(4 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
end component;
component system_processing_system7_0_wrapper is
port (
CAN0_PHY_TX : out std_logic;
CAN0_PHY_RX : in std_logic;
CAN1_PHY_TX : out std_logic;
CAN1_PHY_RX : in std_logic;
ENET0_GMII_TX_EN : out std_logic;
ENET0_GMII_TX_ER : out std_logic;
ENET0_MDIO_MDC : out std_logic;
ENET0_MDIO_O : out std_logic;
ENET0_MDIO_T : out std_logic;
ENET0_PTP_DELAY_REQ_RX : out std_logic;
ENET0_PTP_DELAY_REQ_TX : out std_logic;
ENET0_PTP_PDELAY_REQ_RX : out std_logic;
ENET0_PTP_PDELAY_REQ_TX : out std_logic;
ENET0_PTP_PDELAY_RESP_RX : out std_logic;
ENET0_PTP_PDELAY_RESP_TX : out std_logic;
ENET0_PTP_SYNC_FRAME_RX : out std_logic;
ENET0_PTP_SYNC_FRAME_TX : out std_logic;
ENET0_SOF_RX : out std_logic;
ENET0_SOF_TX : out std_logic;
ENET0_GMII_TXD : out std_logic_vector(7 downto 0);
ENET0_GMII_COL : in std_logic;
ENET0_GMII_CRS : in std_logic;
ENET0_EXT_INTIN : in std_logic;
ENET0_GMII_RX_CLK : in std_logic;
ENET0_GMII_RX_DV : in std_logic;
ENET0_GMII_RX_ER : in std_logic;
ENET0_GMII_TX_CLK : in std_logic;
ENET0_MDIO_I : in std_logic;
ENET0_GMII_RXD : in std_logic_vector(7 downto 0);
ENET1_GMII_TX_EN : out std_logic;
ENET1_GMII_TX_ER : out std_logic;
ENET1_MDIO_MDC : out std_logic;
ENET1_MDIO_O : out std_logic;
ENET1_MDIO_T : out std_logic;
ENET1_PTP_DELAY_REQ_RX : out std_logic;
ENET1_PTP_DELAY_REQ_TX : out std_logic;
ENET1_PTP_PDELAY_REQ_RX : out std_logic;
ENET1_PTP_PDELAY_REQ_TX : out std_logic;
ENET1_PTP_PDELAY_RESP_RX : out std_logic;
ENET1_PTP_PDELAY_RESP_TX : out std_logic;
ENET1_PTP_SYNC_FRAME_RX : out std_logic;
ENET1_PTP_SYNC_FRAME_TX : out std_logic;
ENET1_SOF_RX : out std_logic;
ENET1_SOF_TX : out std_logic;
ENET1_GMII_TXD : out std_logic_vector(7 downto 0);
ENET1_GMII_COL : in std_logic;
ENET1_GMII_CRS : in std_logic;
ENET1_EXT_INTIN : in std_logic;
ENET1_GMII_RX_CLK : in std_logic;
ENET1_GMII_RX_DV : in std_logic;
ENET1_GMII_RX_ER : in std_logic;
ENET1_GMII_TX_CLK : in std_logic;
ENET1_MDIO_I : in std_logic;
ENET1_GMII_RXD : in std_logic_vector(7 downto 0);
GPIO_I : in std_logic_vector(63 downto 0);
GPIO_O : out std_logic_vector(63 downto 0);
GPIO_T : out std_logic_vector(63 downto 0);
I2C0_SDA_I : in std_logic;
I2C0_SDA_O : out std_logic;
I2C0_SDA_T : out std_logic;
I2C0_SCL_I : in std_logic;
I2C0_SCL_O : out std_logic;
I2C0_SCL_T : out std_logic;
I2C1_SDA_I : in std_logic;
I2C1_SDA_O : out std_logic;
I2C1_SDA_T : out std_logic;
I2C1_SCL_I : in std_logic;
I2C1_SCL_O : out std_logic;
I2C1_SCL_T : out std_logic;
PJTAG_TCK : in std_logic;
PJTAG_TMS : in std_logic;
PJTAG_TD_I : in std_logic;
PJTAG_TD_T : out std_logic;
PJTAG_TD_O : out std_logic;
SDIO0_CLK : out std_logic;
SDIO0_CLK_FB : in std_logic;
SDIO0_CMD_O : out std_logic;
SDIO0_CMD_I : in std_logic;
SDIO0_CMD_T : out std_logic;
SDIO0_DATA_I : in std_logic_vector(3 downto 0);
SDIO0_DATA_O : out std_logic_vector(3 downto 0);
SDIO0_DATA_T : out std_logic_vector(3 downto 0);
SDIO0_LED : out std_logic;
SDIO0_CDN : in std_logic;
SDIO0_WP : in std_logic;
SDIO0_BUSPOW : out std_logic;
SDIO0_BUSVOLT : out std_logic_vector(2 downto 0);
SDIO1_CLK : out std_logic;
SDIO1_CLK_FB : in std_logic;
SDIO1_CMD_O : out std_logic;
SDIO1_CMD_I : in std_logic;
SDIO1_CMD_T : out std_logic;
SDIO1_DATA_I : in std_logic_vector(3 downto 0);
SDIO1_DATA_O : out std_logic_vector(3 downto 0);
SDIO1_DATA_T : out std_logic_vector(3 downto 0);
SDIO1_LED : out std_logic;
SDIO1_CDN : in std_logic;
SDIO1_WP : in std_logic;
SDIO1_BUSPOW : out std_logic;
SDIO1_BUSVOLT : out std_logic_vector(2 downto 0);
SPI0_SCLK_I : in std_logic;
SPI0_SCLK_O : out std_logic;
SPI0_SCLK_T : out std_logic;
SPI0_MOSI_I : in std_logic;
SPI0_MOSI_O : out std_logic;
SPI0_MOSI_T : out std_logic;
SPI0_MISO_I : in std_logic;
SPI0_MISO_O : out std_logic;
SPI0_MISO_T : out std_logic;
SPI0_SS_I : in std_logic;
SPI0_SS_O : out std_logic;
SPI0_SS1_O : out std_logic;
SPI0_SS2_O : out std_logic;
SPI0_SS_T : out std_logic;
SPI1_SCLK_I : in std_logic;
SPI1_SCLK_O : out std_logic;
SPI1_SCLK_T : out std_logic;
SPI1_MOSI_I : in std_logic;
SPI1_MOSI_O : out std_logic;
SPI1_MOSI_T : out std_logic;
SPI1_MISO_I : in std_logic;
SPI1_MISO_O : out std_logic;
SPI1_MISO_T : out std_logic;
SPI1_SS_I : in std_logic;
SPI1_SS_O : out std_logic;
SPI1_SS1_O : out std_logic;
SPI1_SS2_O : out std_logic;
SPI1_SS_T : out std_logic;
UART0_DTRN : out std_logic;
UART0_RTSN : out std_logic;
UART0_TX : out std_logic;
UART0_CTSN : in std_logic;
UART0_DCDN : in std_logic;
UART0_DSRN : in std_logic;
UART0_RIN : in std_logic;
UART0_RX : in std_logic;
UART1_DTRN : out std_logic;
UART1_RTSN : out std_logic;
UART1_TX : out std_logic;
UART1_CTSN : in std_logic;
UART1_DCDN : in std_logic;
UART1_DSRN : in std_logic;
UART1_RIN : in std_logic;
UART1_RX : in std_logic;
TTC0_WAVE0_OUT : out std_logic;
TTC0_WAVE1_OUT : out std_logic;
TTC0_WAVE2_OUT : out std_logic;
TTC0_CLK0_IN : in std_logic;
TTC0_CLK1_IN : in std_logic;
TTC0_CLK2_IN : in std_logic;
TTC1_WAVE0_OUT : out std_logic;
TTC1_WAVE1_OUT : out std_logic;
TTC1_WAVE2_OUT : out std_logic;
TTC1_CLK0_IN : in std_logic;
TTC1_CLK1_IN : in std_logic;
TTC1_CLK2_IN : in std_logic;
WDT_CLK_IN : in std_logic;
WDT_RST_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(31 downto 0);
USB0_PORT_INDCTL : out std_logic_vector(1 downto 0);
USB1_PORT_INDCTL : out std_logic_vector(1 downto 0);
USB0_VBUS_PWRSELECT : out std_logic;
USB1_VBUS_PWRSELECT : out std_logic;
USB0_VBUS_PWRFAULT : in std_logic;
USB1_VBUS_PWRFAULT : in std_logic;
SRAM_INTIN : in std_logic;
M_AXI_GP0_ARESETN : out std_logic;
M_AXI_GP0_ARVALID : out std_logic;
M_AXI_GP0_AWVALID : out std_logic;
M_AXI_GP0_BREADY : out std_logic;
M_AXI_GP0_RREADY : out std_logic;
M_AXI_GP0_WLAST : out std_logic;
M_AXI_GP0_WVALID : out std_logic;
M_AXI_GP0_ARID : out std_logic_vector(11 downto 0);
M_AXI_GP0_AWID : out std_logic_vector(11 downto 0);
M_AXI_GP0_WID : out std_logic_vector(11 downto 0);
M_AXI_GP0_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_GP0_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP0_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP0_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_GP0_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP0_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP0_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_GP0_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_GP0_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_GP0_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_GP0_WDATA : out std_logic_vector(31 downto 0);
M_AXI_GP0_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP0_ARLEN : out std_logic_vector(3 downto 0);
M_AXI_GP0_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWLEN : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_GP0_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_GP0_ACLK : in std_logic;
M_AXI_GP0_ARREADY : in std_logic;
M_AXI_GP0_AWREADY : in std_logic;
M_AXI_GP0_BVALID : in std_logic;
M_AXI_GP0_RLAST : in std_logic;
M_AXI_GP0_RVALID : in std_logic;
M_AXI_GP0_WREADY : in std_logic;
M_AXI_GP0_BID : in std_logic_vector(11 downto 0);
M_AXI_GP0_RID : in std_logic_vector(11 downto 0);
M_AXI_GP0_BRESP : in std_logic_vector(1 downto 0);
M_AXI_GP0_RRESP : in std_logic_vector(1 downto 0);
M_AXI_GP0_RDATA : in std_logic_vector(31 downto 0);
M_AXI_GP1_ARESETN : out std_logic;
M_AXI_GP1_ARVALID : out std_logic;
M_AXI_GP1_AWVALID : out std_logic;
M_AXI_GP1_BREADY : out std_logic;
M_AXI_GP1_RREADY : out std_logic;
M_AXI_GP1_WLAST : out std_logic;
M_AXI_GP1_WVALID : out std_logic;
M_AXI_GP1_ARID : out std_logic_vector(11 downto 0);
M_AXI_GP1_AWID : out std_logic_vector(11 downto 0);
M_AXI_GP1_WID : out std_logic_vector(11 downto 0);
M_AXI_GP1_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_GP1_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP1_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP1_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_GP1_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP1_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP1_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_GP1_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_GP1_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_GP1_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_GP1_WDATA : out std_logic_vector(31 downto 0);
M_AXI_GP1_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP1_ARLEN : out std_logic_vector(3 downto 0);
M_AXI_GP1_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWLEN : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_GP1_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_GP1_ACLK : in std_logic;
M_AXI_GP1_ARREADY : in std_logic;
M_AXI_GP1_AWREADY : in std_logic;
M_AXI_GP1_BVALID : in std_logic;
M_AXI_GP1_RLAST : in std_logic;
M_AXI_GP1_RVALID : in std_logic;
M_AXI_GP1_WREADY : in std_logic;
M_AXI_GP1_BID : in std_logic_vector(11 downto 0);
M_AXI_GP1_RID : in std_logic_vector(11 downto 0);
M_AXI_GP1_BRESP : in std_logic_vector(1 downto 0);
M_AXI_GP1_RRESP : in std_logic_vector(1 downto 0);
M_AXI_GP1_RDATA : in std_logic_vector(31 downto 0);
S_AXI_GP0_ARESETN : out std_logic;
S_AXI_GP0_ARREADY : out std_logic;
S_AXI_GP0_AWREADY : out std_logic;
S_AXI_GP0_BVALID : out std_logic;
S_AXI_GP0_RLAST : out std_logic;
S_AXI_GP0_RVALID : out std_logic;
S_AXI_GP0_WREADY : out std_logic;
S_AXI_GP0_BRESP : out std_logic_vector(1 downto 0);
S_AXI_GP0_RRESP : out std_logic_vector(1 downto 0);
S_AXI_GP0_RDATA : out std_logic_vector(31 downto 0);
S_AXI_GP0_BID : out std_logic_vector(5 downto 0);
S_AXI_GP0_RID : out std_logic_vector(5 downto 0);
S_AXI_GP0_ACLK : in std_logic;
S_AXI_GP0_ARVALID : in std_logic;
S_AXI_GP0_AWVALID : in std_logic;
S_AXI_GP0_BREADY : in std_logic;
S_AXI_GP0_RREADY : in std_logic;
S_AXI_GP0_WLAST : in std_logic;
S_AXI_GP0_WVALID : in std_logic;
S_AXI_GP0_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_GP0_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP0_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP0_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_GP0_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP0_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP0_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_GP0_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_GP0_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_GP0_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_GP0_WDATA : in std_logic_vector(31 downto 0);
S_AXI_GP0_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_GP0_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARID : in std_logic_vector(5 downto 0);
S_AXI_GP0_AWID : in std_logic_vector(5 downto 0);
S_AXI_GP0_WID : in std_logic_vector(5 downto 0);
S_AXI_GP1_ARESETN : out std_logic;
S_AXI_GP1_ARREADY : out std_logic;
S_AXI_GP1_AWREADY : out std_logic;
S_AXI_GP1_BVALID : out std_logic;
S_AXI_GP1_RLAST : out std_logic;
S_AXI_GP1_RVALID : out std_logic;
S_AXI_GP1_WREADY : out std_logic;
S_AXI_GP1_BRESP : out std_logic_vector(1 downto 0);
S_AXI_GP1_RRESP : out std_logic_vector(1 downto 0);
S_AXI_GP1_RDATA : out std_logic_vector(31 downto 0);
S_AXI_GP1_BID : out std_logic_vector(5 downto 0);
S_AXI_GP1_RID : out std_logic_vector(5 downto 0);
S_AXI_GP1_ACLK : in std_logic;
S_AXI_GP1_ARVALID : in std_logic;
S_AXI_GP1_AWVALID : in std_logic;
S_AXI_GP1_BREADY : in std_logic;
S_AXI_GP1_RREADY : in std_logic;
S_AXI_GP1_WLAST : in std_logic;
S_AXI_GP1_WVALID : in std_logic;
S_AXI_GP1_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_GP1_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP1_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP1_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_GP1_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP1_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP1_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_GP1_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_GP1_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_GP1_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_GP1_WDATA : in std_logic_vector(31 downto 0);
S_AXI_GP1_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_GP1_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARID : in std_logic_vector(5 downto 0);
S_AXI_GP1_AWID : in std_logic_vector(5 downto 0);
S_AXI_GP1_WID : in std_logic_vector(5 downto 0);
S_AXI_ACP_ARESETN : out std_logic;
S_AXI_ACP_AWREADY : out std_logic;
S_AXI_ACP_ARREADY : out std_logic;
S_AXI_ACP_BVALID : out std_logic;
S_AXI_ACP_RLAST : out std_logic;
S_AXI_ACP_RVALID : out std_logic;
S_AXI_ACP_WREADY : out std_logic;
S_AXI_ACP_BRESP : out std_logic_vector(1 downto 0);
S_AXI_ACP_RRESP : out std_logic_vector(1 downto 0);
S_AXI_ACP_BID : out std_logic_vector(2 downto 0);
S_AXI_ACP_RID : out std_logic_vector(2 downto 0);
S_AXI_ACP_RDATA : out std_logic_vector(63 downto 0);
S_AXI_ACP_ACLK : in std_logic;
S_AXI_ACP_ARVALID : in std_logic;
S_AXI_ACP_AWVALID : in std_logic;
S_AXI_ACP_BREADY : in std_logic;
S_AXI_ACP_RREADY : in std_logic;
S_AXI_ACP_WLAST : in std_logic;
S_AXI_ACP_WVALID : in std_logic;
S_AXI_ACP_ARID : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWID : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_ACP_WID : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ACP_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_ACP_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ACP_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ACP_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_ACP_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_ACP_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARUSER : in std_logic_vector(4 downto 0);
S_AXI_ACP_AWUSER : in std_logic_vector(4 downto 0);
S_AXI_ACP_WDATA : in std_logic_vector(63 downto 0);
S_AXI_ACP_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP0_ARESETN : out std_logic;
S_AXI_HP0_ARREADY : out std_logic;
S_AXI_HP0_AWREADY : out std_logic;
S_AXI_HP0_BVALID : out std_logic;
S_AXI_HP0_RLAST : out std_logic;
S_AXI_HP0_RVALID : out std_logic;
S_AXI_HP0_WREADY : out std_logic;
S_AXI_HP0_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP0_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP0_BID : out std_logic_vector(1 downto 0);
S_AXI_HP0_RID : out std_logic_vector(1 downto 0);
S_AXI_HP0_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP0_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP0_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP0_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP0_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP0_ACLK : in std_logic;
S_AXI_HP0_ARVALID : in std_logic;
S_AXI_HP0_AWVALID : in std_logic;
S_AXI_HP0_BREADY : in std_logic;
S_AXI_HP0_RDISSUECAP1_EN : in std_logic;
S_AXI_HP0_RREADY : in std_logic;
S_AXI_HP0_WLAST : in std_logic;
S_AXI_HP0_WRISSUECAP1_EN : in std_logic;
S_AXI_HP0_WVALID : in std_logic;
S_AXI_HP0_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP0_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP0_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP0_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP0_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP0_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP0_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP0_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP0_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP0_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP0_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARID : in std_logic_vector(1 downto 0);
S_AXI_HP0_AWID : in std_logic_vector(1 downto 0);
S_AXI_HP0_WID : in std_logic_vector(1 downto 0);
S_AXI_HP0_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP0_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP1_ARESETN : out std_logic;
S_AXI_HP1_ARREADY : out std_logic;
S_AXI_HP1_AWREADY : out std_logic;
S_AXI_HP1_BVALID : out std_logic;
S_AXI_HP1_RLAST : out std_logic;
S_AXI_HP1_RVALID : out std_logic;
S_AXI_HP1_WREADY : out std_logic;
S_AXI_HP1_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP1_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP1_BID : out std_logic_vector(5 downto 0);
S_AXI_HP1_RID : out std_logic_vector(5 downto 0);
S_AXI_HP1_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP1_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP1_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP1_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP1_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP1_ACLK : in std_logic;
S_AXI_HP1_ARVALID : in std_logic;
S_AXI_HP1_AWVALID : in std_logic;
S_AXI_HP1_BREADY : in std_logic;
S_AXI_HP1_RDISSUECAP1_EN : in std_logic;
S_AXI_HP1_RREADY : in std_logic;
S_AXI_HP1_WLAST : in std_logic;
S_AXI_HP1_WRISSUECAP1_EN : in std_logic;
S_AXI_HP1_WVALID : in std_logic;
S_AXI_HP1_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP1_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP1_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP1_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP1_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP1_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP1_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP1_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP1_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP1_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP1_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP1_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP1_WID : in std_logic_vector(5 downto 0);
S_AXI_HP1_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP1_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP2_ARESETN : out std_logic;
S_AXI_HP2_ARREADY : out std_logic;
S_AXI_HP2_AWREADY : out std_logic;
S_AXI_HP2_BVALID : out std_logic;
S_AXI_HP2_RLAST : out std_logic;
S_AXI_HP2_RVALID : out std_logic;
S_AXI_HP2_WREADY : out std_logic;
S_AXI_HP2_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP2_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP2_BID : out std_logic_vector(5 downto 0);
S_AXI_HP2_RID : out std_logic_vector(5 downto 0);
S_AXI_HP2_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP2_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP2_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP2_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP2_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP2_ACLK : in std_logic;
S_AXI_HP2_ARVALID : in std_logic;
S_AXI_HP2_AWVALID : in std_logic;
S_AXI_HP2_BREADY : in std_logic;
S_AXI_HP2_RDISSUECAP1_EN : in std_logic;
S_AXI_HP2_RREADY : in std_logic;
S_AXI_HP2_WLAST : in std_logic;
S_AXI_HP2_WRISSUECAP1_EN : in std_logic;
S_AXI_HP2_WVALID : in std_logic;
S_AXI_HP2_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP2_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP2_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP2_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP2_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP2_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP2_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP2_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP2_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP2_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP2_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP2_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP2_WID : in std_logic_vector(5 downto 0);
S_AXI_HP2_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP2_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP3_ARESETN : out std_logic;
S_AXI_HP3_ARREADY : out std_logic;
S_AXI_HP3_AWREADY : out std_logic;
S_AXI_HP3_BVALID : out std_logic;
S_AXI_HP3_RLAST : out std_logic;
S_AXI_HP3_RVALID : out std_logic;
S_AXI_HP3_WREADY : out std_logic;
S_AXI_HP3_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP3_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP3_BID : out std_logic_vector(5 downto 0);
S_AXI_HP3_RID : out std_logic_vector(5 downto 0);
S_AXI_HP3_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP3_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP3_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP3_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP3_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP3_ACLK : in std_logic;
S_AXI_HP3_ARVALID : in std_logic;
S_AXI_HP3_AWVALID : in std_logic;
S_AXI_HP3_BREADY : in std_logic;
S_AXI_HP3_RDISSUECAP1_EN : in std_logic;
S_AXI_HP3_RREADY : in std_logic;
S_AXI_HP3_WLAST : in std_logic;
S_AXI_HP3_WRISSUECAP1_EN : in std_logic;
S_AXI_HP3_WVALID : in std_logic;
S_AXI_HP3_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP3_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP3_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP3_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP3_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP3_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP3_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP3_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP3_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP3_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP3_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP3_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP3_WID : in std_logic_vector(5 downto 0);
S_AXI_HP3_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP3_WSTRB : in std_logic_vector(7 downto 0);
DMA0_DATYPE : out std_logic_vector(1 downto 0);
DMA0_DAVALID : out std_logic;
DMA0_DRREADY : out std_logic;
DMA0_RSTN : out std_logic;
DMA0_ACLK : in std_logic;
DMA0_DAREADY : in std_logic;
DMA0_DRLAST : in std_logic;
DMA0_DRVALID : in std_logic;
DMA0_DRTYPE : in std_logic_vector(1 downto 0);
DMA1_DATYPE : out std_logic_vector(1 downto 0);
DMA1_DAVALID : out std_logic;
DMA1_DRREADY : out std_logic;
DMA1_RSTN : out std_logic;
DMA1_ACLK : in std_logic;
DMA1_DAREADY : in std_logic;
DMA1_DRLAST : in std_logic;
DMA1_DRVALID : in std_logic;
DMA1_DRTYPE : in std_logic_vector(1 downto 0);
DMA2_DATYPE : out std_logic_vector(1 downto 0);
DMA2_DAVALID : out std_logic;
DMA2_DRREADY : out std_logic;
DMA2_RSTN : out std_logic;
DMA2_ACLK : in std_logic;
DMA2_DAREADY : in std_logic;
DMA2_DRLAST : in std_logic;
DMA2_DRVALID : in std_logic;
DMA3_DRVALID : in std_logic;
DMA3_DATYPE : out std_logic_vector(1 downto 0);
DMA3_DAVALID : out std_logic;
DMA3_DRREADY : out std_logic;
DMA3_RSTN : out std_logic;
DMA3_ACLK : in std_logic;
DMA3_DAREADY : in std_logic;
DMA3_DRLAST : in std_logic;
DMA2_DRTYPE : in std_logic_vector(1 downto 0);
DMA3_DRTYPE : in std_logic_vector(1 downto 0);
FTMD_TRACEIN_DATA : in std_logic_vector(31 downto 0);
FTMD_TRACEIN_VALID : in std_logic;
FTMD_TRACEIN_CLK : in std_logic;
FTMD_TRACEIN_ATID : in std_logic_vector(3 downto 0);
FTMT_F2P_TRIG : in std_logic_vector(3 downto 0);
FTMT_F2P_TRIGACK : out std_logic_vector(3 downto 0);
FTMT_F2P_DEBUG : in std_logic_vector(31 downto 0);
FTMT_P2F_TRIGACK : in std_logic_vector(3 downto 0);
FTMT_P2F_TRIG : out std_logic_vector(3 downto 0);
FTMT_P2F_DEBUG : out std_logic_vector(31 downto 0);
FCLK_CLK3 : out std_logic;
FCLK_CLK2 : out std_logic;
FCLK_CLK1 : out std_logic;
FCLK_CLK0 : out std_logic;
FCLK_CLKTRIG3_N : in std_logic;
FCLK_CLKTRIG2_N : in std_logic;
FCLK_CLKTRIG1_N : in std_logic;
FCLK_CLKTRIG0_N : in std_logic;
FCLK_RESET3_N : out std_logic;
FCLK_RESET2_N : out std_logic;
FCLK_RESET1_N : out std_logic;
FCLK_RESET0_N : out std_logic;
FPGA_IDLE_N : in std_logic;
DDR_ARB : in std_logic_vector(3 downto 0);
IRQ_F2P : in std_logic_vector(1 downto 0);
Core0_nFIQ : in std_logic;
Core0_nIRQ : in std_logic;
Core1_nFIQ : in std_logic;
Core1_nIRQ : in std_logic;
EVENT_EVENTO : out std_logic;
EVENT_STANDBYWFE : out std_logic_vector(1 downto 0);
EVENT_STANDBYWFI : out std_logic_vector(1 downto 0);
EVENT_EVENTI : in std_logic;
MIO : inout std_logic_vector(53 downto 0);
DDR_Clk : inout std_logic;
DDR_Clk_n : inout std_logic;
DDR_CKE : inout std_logic;
DDR_CS_n : inout std_logic;
DDR_RAS_n : inout std_logic;
DDR_CAS_n : inout std_logic;
DDR_WEB : out std_logic;
DDR_BankAddr : inout std_logic_vector(2 downto 0);
DDR_Addr : inout std_logic_vector(14 downto 0);
DDR_ODT : inout std_logic;
DDR_DRSTB : inout std_logic;
DDR_DQ : inout std_logic_vector(31 downto 0);
DDR_DM : inout std_logic_vector(3 downto 0);
DDR_DQS : inout std_logic_vector(3 downto 0);
DDR_DQS_n : inout std_logic_vector(3 downto 0);
DDR_VRN : inout std_logic;
DDR_VRP : inout std_logic;
PS_SRSTB : in std_logic;
PS_CLK : in std_logic;
PS_PORB : in std_logic;
IRQ_P2F_DMAC_ABORT : out std_logic;
IRQ_P2F_DMAC0 : out std_logic;
IRQ_P2F_DMAC1 : out std_logic;
IRQ_P2F_DMAC2 : out std_logic;
IRQ_P2F_DMAC3 : out std_logic;
IRQ_P2F_DMAC4 : out std_logic;
IRQ_P2F_DMAC5 : out std_logic;
IRQ_P2F_DMAC6 : out std_logic;
IRQ_P2F_DMAC7 : out std_logic;
IRQ_P2F_SMC : out std_logic;
IRQ_P2F_QSPI : out std_logic;
IRQ_P2F_CTI : out std_logic;
IRQ_P2F_GPIO : out std_logic;
IRQ_P2F_USB0 : out std_logic;
IRQ_P2F_ENET0 : out std_logic;
IRQ_P2F_ENET_WAKE0 : out std_logic;
IRQ_P2F_SDIO0 : out std_logic;
IRQ_P2F_I2C0 : out std_logic;
IRQ_P2F_SPI0 : out std_logic;
IRQ_P2F_UART0 : out std_logic;
IRQ_P2F_CAN0 : out std_logic;
IRQ_P2F_USB1 : out std_logic;
IRQ_P2F_ENET1 : out std_logic;
IRQ_P2F_ENET_WAKE1 : out std_logic;
IRQ_P2F_SDIO1 : out std_logic;
IRQ_P2F_I2C1 : out std_logic;
IRQ_P2F_SPI1 : out std_logic;
IRQ_P2F_UART1 : out std_logic;
IRQ_P2F_CAN1 : out std_logic
);
end component;
component system_axi_dma_0_wrapper is
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(9 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(9 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_awaddr : out std_logic_vector(31 downto 0);
m_axi_sg_awlen : out std_logic_vector(7 downto 0);
m_axi_sg_awsize : out std_logic_vector(2 downto 0);
m_axi_sg_awburst : out std_logic_vector(1 downto 0);
m_axi_sg_awprot : out std_logic_vector(2 downto 0);
m_axi_sg_awcache : out std_logic_vector(3 downto 0);
m_axi_sg_awuser : out std_logic_vector(3 downto 0);
m_axi_sg_awvalid : out std_logic;
m_axi_sg_awready : in std_logic;
m_axi_sg_wdata : out std_logic_vector(31 downto 0);
m_axi_sg_wstrb : out std_logic_vector(3 downto 0);
m_axi_sg_wlast : out std_logic;
m_axi_sg_wvalid : out std_logic;
m_axi_sg_wready : in std_logic;
m_axi_sg_bresp : in std_logic_vector(1 downto 0);
m_axi_sg_bvalid : in std_logic;
m_axi_sg_bready : out std_logic;
m_axi_sg_araddr : out std_logic_vector(31 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_aruser : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(31 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(31 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(3 downto 0);
m_axis_mm2s_tid : out std_logic_vector(4 downto 0);
m_axis_mm2s_tdest : out std_logic_vector(4 downto 0);
mm2s_cntrl_reset_out_n : out std_logic;
m_axis_mm2s_cntrl_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_cntrl_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_cntrl_tvalid : out std_logic;
m_axis_mm2s_cntrl_tready : in std_logic;
m_axis_mm2s_cntrl_tlast : out std_logic;
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(31 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(3 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(3 downto 0);
s_axis_s2mm_tid : in std_logic_vector(4 downto 0);
s_axis_s2mm_tdest : in std_logic_vector(4 downto 0);
s2mm_sts_reset_out_n : out std_logic;
s_axis_s2mm_sts_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_sts_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_sts_tvalid : in std_logic;
s_axis_s2mm_sts_tready : out std_logic;
s_axis_s2mm_sts_tlast : in std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_dma_tstvec : out std_logic_vector(31 downto 0)
);
end component;
component system_axi_interconnect_1_wrapper is
port (
INTERCONNECT_ACLK : in std_logic;
INTERCONNECT_ARESETN : in std_logic;
S_AXI_ARESET_OUT_N : out std_logic_vector(2 downto 0);
M_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
IRQ : out std_logic;
S_AXI_ACLK : in std_logic_vector(2 downto 0);
S_AXI_AWID : in std_logic_vector(5 downto 0);
S_AXI_AWADDR : in std_logic_vector(95 downto 0);
S_AXI_AWLEN : in std_logic_vector(23 downto 0);
S_AXI_AWSIZE : in std_logic_vector(8 downto 0);
S_AXI_AWBURST : in std_logic_vector(5 downto 0);
S_AXI_AWLOCK : in std_logic_vector(5 downto 0);
S_AXI_AWCACHE : in std_logic_vector(11 downto 0);
S_AXI_AWPROT : in std_logic_vector(8 downto 0);
S_AXI_AWQOS : in std_logic_vector(11 downto 0);
S_AXI_AWUSER : in std_logic_vector(11 downto 0);
S_AXI_AWVALID : in std_logic_vector(2 downto 0);
S_AXI_AWREADY : out std_logic_vector(2 downto 0);
S_AXI_WID : in std_logic_vector(5 downto 0);
S_AXI_WDATA : in std_logic_vector(191 downto 0);
S_AXI_WSTRB : in std_logic_vector(23 downto 0);
S_AXI_WLAST : in std_logic_vector(2 downto 0);
S_AXI_WUSER : in std_logic_vector(2 downto 0);
S_AXI_WVALID : in std_logic_vector(2 downto 0);
S_AXI_WREADY : out std_logic_vector(2 downto 0);
S_AXI_BID : out std_logic_vector(5 downto 0);
S_AXI_BRESP : out std_logic_vector(5 downto 0);
S_AXI_BUSER : out std_logic_vector(2 downto 0);
S_AXI_BVALID : out std_logic_vector(2 downto 0);
S_AXI_BREADY : in std_logic_vector(2 downto 0);
S_AXI_ARID : in std_logic_vector(5 downto 0);
S_AXI_ARADDR : in std_logic_vector(95 downto 0);
S_AXI_ARLEN : in std_logic_vector(23 downto 0);
S_AXI_ARSIZE : in std_logic_vector(8 downto 0);
S_AXI_ARBURST : in std_logic_vector(5 downto 0);
S_AXI_ARLOCK : in std_logic_vector(5 downto 0);
S_AXI_ARCACHE : in std_logic_vector(11 downto 0);
S_AXI_ARPROT : in std_logic_vector(8 downto 0);
S_AXI_ARQOS : in std_logic_vector(11 downto 0);
S_AXI_ARUSER : in std_logic_vector(11 downto 0);
S_AXI_ARVALID : in std_logic_vector(2 downto 0);
S_AXI_ARREADY : out std_logic_vector(2 downto 0);
S_AXI_RID : out std_logic_vector(5 downto 0);
S_AXI_RDATA : out std_logic_vector(191 downto 0);
S_AXI_RRESP : out std_logic_vector(5 downto 0);
S_AXI_RLAST : out std_logic_vector(2 downto 0);
S_AXI_RUSER : out std_logic_vector(2 downto 0);
S_AXI_RVALID : out std_logic_vector(2 downto 0);
S_AXI_RREADY : in std_logic_vector(2 downto 0);
M_AXI_ACLK : in std_logic_vector(0 to 0);
M_AXI_AWID : out std_logic_vector(1 downto 0);
M_AXI_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWREGION : out std_logic_vector(3 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic_vector(0 to 0);
M_AXI_AWREADY : in std_logic_vector(0 to 0);
M_AXI_WID : out std_logic_vector(1 downto 0);
M_AXI_WDATA : out std_logic_vector(63 downto 0);
M_AXI_WSTRB : out std_logic_vector(7 downto 0);
M_AXI_WLAST : out std_logic_vector(0 to 0);
M_AXI_WUSER : out std_logic_vector(0 to 0);
M_AXI_WVALID : out std_logic_vector(0 to 0);
M_AXI_WREADY : in std_logic_vector(0 to 0);
M_AXI_BID : in std_logic_vector(1 downto 0);
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BUSER : in std_logic_vector(0 to 0);
M_AXI_BVALID : in std_logic_vector(0 to 0);
M_AXI_BREADY : out std_logic_vector(0 to 0);
M_AXI_ARID : out std_logic_vector(1 downto 0);
M_AXI_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARREGION : out std_logic_vector(3 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARUSER : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic_vector(0 to 0);
M_AXI_ARREADY : in std_logic_vector(0 to 0);
M_AXI_RID : in std_logic_vector(1 downto 0);
M_AXI_RDATA : in std_logic_vector(63 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic_vector(0 to 0);
M_AXI_RUSER : in std_logic_vector(0 to 0);
M_AXI_RVALID : in std_logic_vector(0 to 0);
M_AXI_RREADY : out std_logic_vector(0 to 0);
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
INTERCONNECT_ARESET_OUT_N : out std_logic;
DEBUG_AW_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AR_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AW_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AW_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AW_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AW_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AW_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AR_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AR_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AR_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AR_TARGET : out std_logic_vector(7 downto 0);
DEBUG_B_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_R_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_R_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_BID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_BID_ERROR : out std_logic;
DEBUG_RID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_RID_ERROR : out std_logic;
DEBUG_SR_SC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_ARADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_SR_SC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_AWADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_SR_SC_BRESP : out std_logic_vector(5 downto 0);
DEBUG_SR_SC_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SR_SC_RDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SR_SC_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SR_SC_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_SC_SF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_ARADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_SC_SF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_AWADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_SC_SF_BRESP : out std_logic_vector(5 downto 0);
DEBUG_SC_SF_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SC_SF_RDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SC_SF_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SC_SF_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_SF_CB_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_ARADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_SF_CB_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_AWADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_SF_CB_BRESP : out std_logic_vector(5 downto 0);
DEBUG_SF_CB_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SF_CB_RDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SF_CB_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SF_CB_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_CB_MF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_ARADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_CB_MF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_AWADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_CB_MF_BRESP : out std_logic_vector(5 downto 0);
DEBUG_CB_MF_RDATA : out std_logic_vector(63 downto 0);
DEBUG_CB_MF_RDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_CB_MF_WDATA : out std_logic_vector(63 downto 0);
DEBUG_CB_MF_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MF_MC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_ARADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_MF_MC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_AWADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_MF_MC_BRESP : out std_logic_vector(5 downto 0);
DEBUG_MF_MC_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MF_MC_RDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MF_MC_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MF_MC_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MC_MP_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_ARADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_MC_MP_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_AWADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_MC_MP_BRESP : out std_logic_vector(5 downto 0);
DEBUG_MC_MP_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MC_MP_RDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MC_MP_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MC_MP_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MP_MR_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_ARADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_MP_MR_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_AWADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_MP_MR_BRESP : out std_logic_vector(5 downto 0);
DEBUG_MP_MR_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MP_MR_RDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MP_MR_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MP_MR_WDATACONTROL : out std_logic_vector(10 downto 0)
);
end component;
component system_conware_0_wrapper is
port (
ACLK : in std_logic;
ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
M_AXIS_TSTRB : out std_logic_vector(3 downto 0);
in_states : out std_logic_vector(7 downto 0);
out_states : out std_logic_vector(7 downto 0);
num_reads : out std_logic_vector(31 downto 0);
num_writes : out std_logic_vector(31 downto 0);
read_ctr : out std_logic_vector(7 downto 0);
write_ctr : out std_logic_vector(7 downto 0)
);
end component;
component system_cownare_ctl_0_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
in_states : in std_logic_vector(7 downto 0);
out_states : in std_logic_vector(7 downto 0);
num_reads : in std_logic_vector(31 downto 0);
num_writes : in std_logic_vector(31 downto 0);
read_ctr : in std_logic_vector(7 downto 0);
write_ctr : in std_logic_vector(7 downto 0)
);
end component;
component IOBUF is
port (
I : in std_logic;
IO : inout std_logic;
O : out std_logic;
T : in std_logic
);
end component;
-- Internal signals
signal BTNs_5Bits_TRI_IO_I : std_logic_vector(4 downto 0);
signal BTNs_5Bits_TRI_IO_O : std_logic_vector(4 downto 0);
signal BTNs_5Bits_TRI_IO_T : std_logic_vector(4 downto 0);
signal SWs_8Bits_TRI_IO_I : std_logic_vector(7 downto 0);
signal SWs_8Bits_TRI_IO_O : std_logic_vector(7 downto 0);
signal SWs_8Bits_TRI_IO_T : std_logic_vector(7 downto 0);
signal axi4lite_0_M_ARADDR : std_logic_vector(127 downto 0);
signal axi4lite_0_M_ARESETN : std_logic_vector(3 downto 0);
signal axi4lite_0_M_ARREADY : std_logic_vector(3 downto 0);
signal axi4lite_0_M_ARVALID : std_logic_vector(3 downto 0);
signal axi4lite_0_M_AWADDR : std_logic_vector(127 downto 0);
signal axi4lite_0_M_AWREADY : std_logic_vector(3 downto 0);
signal axi4lite_0_M_AWVALID : std_logic_vector(3 downto 0);
signal axi4lite_0_M_BREADY : std_logic_vector(3 downto 0);
signal axi4lite_0_M_BRESP : std_logic_vector(7 downto 0);
signal axi4lite_0_M_BVALID : std_logic_vector(3 downto 0);
signal axi4lite_0_M_RDATA : std_logic_vector(127 downto 0);
signal axi4lite_0_M_RREADY : std_logic_vector(3 downto 0);
signal axi4lite_0_M_RRESP : std_logic_vector(7 downto 0);
signal axi4lite_0_M_RVALID : std_logic_vector(3 downto 0);
signal axi4lite_0_M_WDATA : std_logic_vector(127 downto 0);
signal axi4lite_0_M_WREADY : std_logic_vector(3 downto 0);
signal axi4lite_0_M_WSTRB : std_logic_vector(15 downto 0);
signal axi4lite_0_M_WVALID : std_logic_vector(3 downto 0);
signal axi4lite_0_S_ARADDR : std_logic_vector(31 downto 0);
signal axi4lite_0_S_ARBURST : std_logic_vector(1 downto 0);
signal axi4lite_0_S_ARCACHE : std_logic_vector(3 downto 0);
signal axi4lite_0_S_ARID : std_logic_vector(11 downto 0);
signal axi4lite_0_S_ARLEN : std_logic_vector(7 downto 0);
signal axi4lite_0_S_ARLOCK : std_logic_vector(1 downto 0);
signal axi4lite_0_S_ARPROT : std_logic_vector(2 downto 0);
signal axi4lite_0_S_ARQOS : std_logic_vector(3 downto 0);
signal axi4lite_0_S_ARREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_ARSIZE : std_logic_vector(2 downto 0);
signal axi4lite_0_S_ARVALID : std_logic_vector(0 to 0);
signal axi4lite_0_S_AWADDR : std_logic_vector(31 downto 0);
signal axi4lite_0_S_AWBURST : std_logic_vector(1 downto 0);
signal axi4lite_0_S_AWCACHE : std_logic_vector(3 downto 0);
signal axi4lite_0_S_AWID : std_logic_vector(11 downto 0);
signal axi4lite_0_S_AWLEN : std_logic_vector(7 downto 0);
signal axi4lite_0_S_AWLOCK : std_logic_vector(1 downto 0);
signal axi4lite_0_S_AWPROT : std_logic_vector(2 downto 0);
signal axi4lite_0_S_AWQOS : std_logic_vector(3 downto 0);
signal axi4lite_0_S_AWREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_AWSIZE : std_logic_vector(2 downto 0);
signal axi4lite_0_S_AWVALID : std_logic_vector(0 to 0);
signal axi4lite_0_S_BID : std_logic_vector(11 downto 0);
signal axi4lite_0_S_BREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_BRESP : std_logic_vector(1 downto 0);
signal axi4lite_0_S_BVALID : std_logic_vector(0 to 0);
signal axi4lite_0_S_RDATA : std_logic_vector(31 downto 0);
signal axi4lite_0_S_RID : std_logic_vector(11 downto 0);
signal axi4lite_0_S_RLAST : std_logic_vector(0 to 0);
signal axi4lite_0_S_RREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_RRESP : std_logic_vector(1 downto 0);
signal axi4lite_0_S_RVALID : std_logic_vector(0 to 0);
signal axi4lite_0_S_WDATA : std_logic_vector(31 downto 0);
signal axi4lite_0_S_WID : std_logic_vector(11 downto 0);
signal axi4lite_0_S_WLAST : std_logic_vector(0 to 0);
signal axi4lite_0_S_WREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_WSTRB : std_logic_vector(3 downto 0);
signal axi4lite_0_S_WVALID : std_logic_vector(0 to 0);
signal axi_dma_0_M_AXIS_MM2S_TDATA : std_logic_vector(31 downto 0);
signal axi_dma_0_M_AXIS_MM2S_TLAST : std_logic;
signal axi_dma_0_M_AXIS_MM2S_TREADY : std_logic;
signal axi_dma_0_M_AXIS_MM2S_TVALID : std_logic;
signal axi_dma_0_mm2s_introut : std_logic;
signal axi_dma_0_s2mm_introut : std_logic;
signal axi_interconnect_1_M_ARADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_M_ARBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_ARCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_ARID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_ARLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_M_ARLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_ARPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_M_ARQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_ARREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_ARSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_M_ARVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_AWADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_M_AWBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_AWCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_AWID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_AWLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_M_AWLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_AWPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_M_AWQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_AWREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_AWSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_M_AWVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_BID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_BREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_BRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_BVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_RDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_RID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_RLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_RREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_RRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_RVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_WDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_WID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_WLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_WREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_WSTRB : std_logic_vector(7 downto 0);
signal axi_interconnect_1_M_WVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_ARADDR : std_logic_vector(95 downto 0);
signal axi_interconnect_1_S_ARBURST : std_logic_vector(5 downto 0);
signal axi_interconnect_1_S_ARCACHE : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_ARLEN : std_logic_vector(23 downto 0);
signal axi_interconnect_1_S_ARPROT : std_logic_vector(8 downto 0);
signal axi_interconnect_1_S_ARREADY : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_ARSIZE : std_logic_vector(8 downto 0);
signal axi_interconnect_1_S_ARUSER : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_ARVALID : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_AWADDR : std_logic_vector(95 downto 0);
signal axi_interconnect_1_S_AWBURST : std_logic_vector(5 downto 0);
signal axi_interconnect_1_S_AWCACHE : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_AWLEN : std_logic_vector(23 downto 0);
signal axi_interconnect_1_S_AWPROT : std_logic_vector(8 downto 0);
signal axi_interconnect_1_S_AWREADY : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_AWSIZE : std_logic_vector(8 downto 0);
signal axi_interconnect_1_S_AWUSER : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_AWVALID : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_BREADY : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_BRESP : std_logic_vector(5 downto 0);
signal axi_interconnect_1_S_BVALID : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_RDATA : std_logic_vector(191 downto 0);
signal axi_interconnect_1_S_RLAST : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_RREADY : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_RRESP : std_logic_vector(5 downto 0);
signal axi_interconnect_1_S_RVALID : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_WDATA : std_logic_vector(191 downto 0);
signal axi_interconnect_1_S_WLAST : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_WREADY : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_WSTRB : std_logic_vector(23 downto 0);
signal axi_interconnect_1_S_WVALID : std_logic_vector(2 downto 0);
signal conware_0_M_AXIS_TDATA : std_logic_vector(31 downto 0);
signal conware_0_M_AXIS_TKEEP : std_logic_vector(3 downto 0);
signal conware_0_M_AXIS_TLAST : std_logic;
signal conware_0_M_AXIS_TREADY : std_logic;
signal conware_0_M_AXIS_TVALID : std_logic;
signal conware_0_in_states : std_logic_vector(7 downto 0);
signal conware_0_num_reads : std_logic_vector(31 downto 0);
signal conware_0_num_writes : std_logic_vector(31 downto 0);
signal conware_0_out_states : std_logic_vector(7 downto 0);
signal conware_0_read_ctr : std_logic_vector(7 downto 0);
signal conware_0_write_ctr : std_logic_vector(7 downto 0);
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd2 : std_logic_vector(1 downto 0);
signal net_gnd3 : std_logic_vector(2 downto 0);
signal net_gnd4 : std_logic_vector(3 downto 0);
signal net_gnd5 : std_logic_vector(4 downto 0);
signal net_gnd6 : std_logic_vector(5 downto 0);
signal net_gnd8 : std_logic_vector(7 downto 0);
signal net_gnd12 : std_logic_vector(11 downto 0);
signal net_gnd32 : std_logic_vector(31 downto 0);
signal net_gnd48 : std_logic_vector(47 downto 0);
signal net_gnd64 : std_logic_vector(63 downto 0);
signal net_vcc4 : std_logic_vector(3 downto 0);
signal pgassign1 : std_logic_vector(3 downto 0);
signal pgassign2 : std_logic_vector(1 downto 0);
signal pgassign3 : std_logic_vector(2 downto 0);
signal processing_system7_0_DDR_WEB : std_logic;
signal processing_system7_0_FCLK_CLK0 : std_logic_vector(0 to 0);
signal processing_system7_0_FCLK_RESET0_N_0 : std_logic;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system_axi4lite_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_sws_8bits_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_btns_5bits_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_processing_system7_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_dma_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_interconnect_1_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_conware_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_cownare_ctl_0_wrapper : component is "user_black_box";
begin
-- Internal assignments
processing_system7_0_DDR_WEB_pin <= processing_system7_0_DDR_WEB;
conware_0_M_AXIS_TVALID_pin <= conware_0_M_AXIS_TVALID;
conware_0_M_AXIS_TLAST_pin <= conware_0_M_AXIS_TLAST;
conware_0_M_AXIS_TREADY_pin <= conware_0_M_AXIS_TREADY;
conware_0_M_AXIS_TKEEP_pin <= conware_0_M_AXIS_TKEEP;
conware_0_ACLK_pin <= processing_system7_0_FCLK_CLK0(0);
cownare_ctl_0_in_states_pin <= conware_0_in_states;
axi_interconnect_1_S_AWADDR(63 downto 32) <= B"00000000000000000000000000000000";
axi_interconnect_1_S_AWLEN(15 downto 8) <= B"00000000";
axi_interconnect_1_S_AWSIZE(5 downto 3) <= B"000";
axi_interconnect_1_S_AWBURST(3 downto 2) <= B"00";
axi_interconnect_1_S_AWPROT(5 downto 3) <= B"000";
axi_interconnect_1_S_AWCACHE(7 downto 4) <= B"0000";
axi_interconnect_1_S_AWUSER(7 downto 4) <= B"0000";
axi_interconnect_1_S_AWVALID(1 downto 1) <= B"0";
axi_interconnect_1_S_WDATA(127 downto 64) <= B"0000000000000000000000000000000000000000000000000000000000000000";
axi_interconnect_1_S_WSTRB(15 downto 8) <= B"00000000";
axi_interconnect_1_S_WLAST(1 downto 1) <= B"0";
axi_interconnect_1_S_WVALID(1 downto 1) <= B"0";
axi_interconnect_1_S_BREADY(1 downto 1) <= B"0";
axi_interconnect_1_S_ARADDR(95 downto 64) <= B"00000000000000000000000000000000";
axi_interconnect_1_S_ARLEN(23 downto 16) <= B"00000000";
axi_interconnect_1_S_ARSIZE(8 downto 6) <= B"000";
axi_interconnect_1_S_ARBURST(5 downto 4) <= B"00";
axi_interconnect_1_S_ARPROT(8 downto 6) <= B"000";
axi_interconnect_1_S_ARCACHE(11 downto 8) <= B"0000";
axi_interconnect_1_S_ARUSER(11 downto 8) <= B"0000";
axi_interconnect_1_S_ARVALID(2 downto 2) <= B"0";
axi_interconnect_1_S_RREADY(2 downto 2) <= B"0";
pgassign1(3 downto 3) <= processing_system7_0_FCLK_CLK0(0 to 0);
pgassign1(2 downto 2) <= processing_system7_0_FCLK_CLK0(0 to 0);
pgassign1(1 downto 1) <= processing_system7_0_FCLK_CLK0(0 to 0);
pgassign1(0 downto 0) <= processing_system7_0_FCLK_CLK0(0 to 0);
pgassign2(1) <= axi_dma_0_mm2s_introut;
pgassign2(0) <= axi_dma_0_s2mm_introut;
pgassign3(2 downto 2) <= processing_system7_0_FCLK_CLK0(0 to 0);
pgassign3(1 downto 1) <= processing_system7_0_FCLK_CLK0(0 to 0);
pgassign3(0 downto 0) <= processing_system7_0_FCLK_CLK0(0 to 0);
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd12(11 downto 0) <= B"000000000000";
net_gnd2(1 downto 0) <= B"00";
net_gnd3(2 downto 0) <= B"000";
net_gnd32(31 downto 0) <= B"00000000000000000000000000000000";
net_gnd4(3 downto 0) <= B"0000";
net_gnd48(47 downto 0) <= B"000000000000000000000000000000000000000000000000";
net_gnd5(4 downto 0) <= B"00000";
net_gnd6(5 downto 0) <= B"000000";
net_gnd64(63 downto 0) <= B"0000000000000000000000000000000000000000000000000000000000000000";
net_gnd8(7 downto 0) <= B"00000000";
net_vcc4(3 downto 0) <= B"1111";
axi4lite_0 : system_axi4lite_0_wrapper
port map (
INTERCONNECT_ACLK => processing_system7_0_FCLK_CLK0(0),
INTERCONNECT_ARESETN => processing_system7_0_FCLK_RESET0_N_0,
S_AXI_ARESET_OUT_N => open,
M_AXI_ARESET_OUT_N => axi4lite_0_M_ARESETN,
IRQ => open,
S_AXI_ACLK => processing_system7_0_FCLK_CLK0(0 to 0),
S_AXI_AWID => axi4lite_0_S_AWID,
S_AXI_AWADDR => axi4lite_0_S_AWADDR,
S_AXI_AWLEN => axi4lite_0_S_AWLEN,
S_AXI_AWSIZE => axi4lite_0_S_AWSIZE,
S_AXI_AWBURST => axi4lite_0_S_AWBURST,
S_AXI_AWLOCK => axi4lite_0_S_AWLOCK,
S_AXI_AWCACHE => axi4lite_0_S_AWCACHE,
S_AXI_AWPROT => axi4lite_0_S_AWPROT,
S_AXI_AWQOS => axi4lite_0_S_AWQOS,
S_AXI_AWUSER => net_gnd1(0 to 0),
S_AXI_AWVALID => axi4lite_0_S_AWVALID(0 to 0),
S_AXI_AWREADY => axi4lite_0_S_AWREADY(0 to 0),
S_AXI_WID => axi4lite_0_S_WID,
S_AXI_WDATA => axi4lite_0_S_WDATA,
S_AXI_WSTRB => axi4lite_0_S_WSTRB,
S_AXI_WLAST => axi4lite_0_S_WLAST(0 to 0),
S_AXI_WUSER => net_gnd1(0 to 0),
S_AXI_WVALID => axi4lite_0_S_WVALID(0 to 0),
S_AXI_WREADY => axi4lite_0_S_WREADY(0 to 0),
S_AXI_BID => axi4lite_0_S_BID,
S_AXI_BRESP => axi4lite_0_S_BRESP,
S_AXI_BUSER => open,
S_AXI_BVALID => axi4lite_0_S_BVALID(0 to 0),
S_AXI_BREADY => axi4lite_0_S_BREADY(0 to 0),
S_AXI_ARID => axi4lite_0_S_ARID,
S_AXI_ARADDR => axi4lite_0_S_ARADDR,
S_AXI_ARLEN => axi4lite_0_S_ARLEN,
S_AXI_ARSIZE => axi4lite_0_S_ARSIZE,
S_AXI_ARBURST => axi4lite_0_S_ARBURST,
S_AXI_ARLOCK => axi4lite_0_S_ARLOCK,
S_AXI_ARCACHE => axi4lite_0_S_ARCACHE,
S_AXI_ARPROT => axi4lite_0_S_ARPROT,
S_AXI_ARQOS => axi4lite_0_S_ARQOS,
S_AXI_ARUSER => net_gnd1(0 to 0),
S_AXI_ARVALID => axi4lite_0_S_ARVALID(0 to 0),
S_AXI_ARREADY => axi4lite_0_S_ARREADY(0 to 0),
S_AXI_RID => axi4lite_0_S_RID,
S_AXI_RDATA => axi4lite_0_S_RDATA,
S_AXI_RRESP => axi4lite_0_S_RRESP,
S_AXI_RLAST => axi4lite_0_S_RLAST(0 to 0),
S_AXI_RUSER => open,
S_AXI_RVALID => axi4lite_0_S_RVALID(0 to 0),
S_AXI_RREADY => axi4lite_0_S_RREADY(0 to 0),
M_AXI_ACLK => pgassign1,
M_AXI_AWID => open,
M_AXI_AWADDR => axi4lite_0_M_AWADDR,
M_AXI_AWLEN => open,
M_AXI_AWSIZE => open,
M_AXI_AWBURST => open,
M_AXI_AWLOCK => open,
M_AXI_AWCACHE => open,
M_AXI_AWPROT => open,
M_AXI_AWREGION => open,
M_AXI_AWQOS => open,
M_AXI_AWUSER => open,
M_AXI_AWVALID => axi4lite_0_M_AWVALID,
M_AXI_AWREADY => axi4lite_0_M_AWREADY,
M_AXI_WID => open,
M_AXI_WDATA => axi4lite_0_M_WDATA,
M_AXI_WSTRB => axi4lite_0_M_WSTRB,
M_AXI_WLAST => open,
M_AXI_WUSER => open,
M_AXI_WVALID => axi4lite_0_M_WVALID,
M_AXI_WREADY => axi4lite_0_M_WREADY,
M_AXI_BID => net_gnd48,
M_AXI_BRESP => axi4lite_0_M_BRESP,
M_AXI_BUSER => net_gnd4,
M_AXI_BVALID => axi4lite_0_M_BVALID,
M_AXI_BREADY => axi4lite_0_M_BREADY,
M_AXI_ARID => open,
M_AXI_ARADDR => axi4lite_0_M_ARADDR,
M_AXI_ARLEN => open,
M_AXI_ARSIZE => open,
M_AXI_ARBURST => open,
M_AXI_ARLOCK => open,
M_AXI_ARCACHE => open,
M_AXI_ARPROT => open,
M_AXI_ARREGION => open,
M_AXI_ARQOS => open,
M_AXI_ARUSER => open,
M_AXI_ARVALID => axi4lite_0_M_ARVALID,
M_AXI_ARREADY => axi4lite_0_M_ARREADY,
M_AXI_RID => net_gnd48,
M_AXI_RDATA => axi4lite_0_M_RDATA,
M_AXI_RRESP => axi4lite_0_M_RRESP,
M_AXI_RLAST => net_gnd4,
M_AXI_RUSER => net_gnd4,
M_AXI_RVALID => axi4lite_0_M_RVALID,
M_AXI_RREADY => axi4lite_0_M_RREADY,
S_AXI_CTRL_AWADDR => net_gnd32,
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32,
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32,
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0,
INTERCONNECT_ARESET_OUT_N => open,
DEBUG_AW_TRANS_SEQ => open,
DEBUG_AW_ARB_GRANT => open,
DEBUG_AR_TRANS_SEQ => open,
DEBUG_AR_ARB_GRANT => open,
DEBUG_AW_TRANS_QUAL => open,
DEBUG_AW_ACCEPT_CNT => open,
DEBUG_AW_ACTIVE_THREAD => open,
DEBUG_AW_ACTIVE_TARGET => open,
DEBUG_AW_ACTIVE_REGION => open,
DEBUG_AW_ERROR => open,
DEBUG_AW_TARGET => open,
DEBUG_AR_TRANS_QUAL => open,
DEBUG_AR_ACCEPT_CNT => open,
DEBUG_AR_ACTIVE_THREAD => open,
DEBUG_AR_ACTIVE_TARGET => open,
DEBUG_AR_ACTIVE_REGION => open,
DEBUG_AR_ERROR => open,
DEBUG_AR_TARGET => open,
DEBUG_B_TRANS_SEQ => open,
DEBUG_R_BEAT_CNT => open,
DEBUG_R_TRANS_SEQ => open,
DEBUG_AW_ISSUING_CNT => open,
DEBUG_AR_ISSUING_CNT => open,
DEBUG_W_BEAT_CNT => open,
DEBUG_W_TRANS_SEQ => open,
DEBUG_BID_TARGET => open,
DEBUG_BID_ERROR => open,
DEBUG_RID_TARGET => open,
DEBUG_RID_ERROR => open,
DEBUG_SR_SC_ARADDR => open,
DEBUG_SR_SC_ARADDRCONTROL => open,
DEBUG_SR_SC_AWADDR => open,
DEBUG_SR_SC_AWADDRCONTROL => open,
DEBUG_SR_SC_BRESP => open,
DEBUG_SR_SC_RDATA => open,
DEBUG_SR_SC_RDATACONTROL => open,
DEBUG_SR_SC_WDATA => open,
DEBUG_SR_SC_WDATACONTROL => open,
DEBUG_SC_SF_ARADDR => open,
DEBUG_SC_SF_ARADDRCONTROL => open,
DEBUG_SC_SF_AWADDR => open,
DEBUG_SC_SF_AWADDRCONTROL => open,
DEBUG_SC_SF_BRESP => open,
DEBUG_SC_SF_RDATA => open,
DEBUG_SC_SF_RDATACONTROL => open,
DEBUG_SC_SF_WDATA => open,
DEBUG_SC_SF_WDATACONTROL => open,
DEBUG_SF_CB_ARADDR => open,
DEBUG_SF_CB_ARADDRCONTROL => open,
DEBUG_SF_CB_AWADDR => open,
DEBUG_SF_CB_AWADDRCONTROL => open,
DEBUG_SF_CB_BRESP => open,
DEBUG_SF_CB_RDATA => open,
DEBUG_SF_CB_RDATACONTROL => open,
DEBUG_SF_CB_WDATA => open,
DEBUG_SF_CB_WDATACONTROL => open,
DEBUG_CB_MF_ARADDR => open,
DEBUG_CB_MF_ARADDRCONTROL => open,
DEBUG_CB_MF_AWADDR => open,
DEBUG_CB_MF_AWADDRCONTROL => open,
DEBUG_CB_MF_BRESP => open,
DEBUG_CB_MF_RDATA => open,
DEBUG_CB_MF_RDATACONTROL => open,
DEBUG_CB_MF_WDATA => open,
DEBUG_CB_MF_WDATACONTROL => open,
DEBUG_MF_MC_ARADDR => open,
DEBUG_MF_MC_ARADDRCONTROL => open,
DEBUG_MF_MC_AWADDR => open,
DEBUG_MF_MC_AWADDRCONTROL => open,
DEBUG_MF_MC_BRESP => open,
DEBUG_MF_MC_RDATA => open,
DEBUG_MF_MC_RDATACONTROL => open,
DEBUG_MF_MC_WDATA => open,
DEBUG_MF_MC_WDATACONTROL => open,
DEBUG_MC_MP_ARADDR => open,
DEBUG_MC_MP_ARADDRCONTROL => open,
DEBUG_MC_MP_AWADDR => open,
DEBUG_MC_MP_AWADDRCONTROL => open,
DEBUG_MC_MP_BRESP => open,
DEBUG_MC_MP_RDATA => open,
DEBUG_MC_MP_RDATACONTROL => open,
DEBUG_MC_MP_WDATA => open,
DEBUG_MC_MP_WDATACONTROL => open,
DEBUG_MP_MR_ARADDR => open,
DEBUG_MP_MR_ARADDRCONTROL => open,
DEBUG_MP_MR_AWADDR => open,
DEBUG_MP_MR_AWADDRCONTROL => open,
DEBUG_MP_MR_BRESP => open,
DEBUG_MP_MR_RDATA => open,
DEBUG_MP_MR_RDATACONTROL => open,
DEBUG_MP_MR_WDATA => open,
DEBUG_MP_MR_WDATACONTROL => open
);
SWs_8Bits : system_sws_8bits_wrapper
port map (
S_AXI_ACLK => processing_system7_0_FCLK_CLK0(0),
S_AXI_ARESETN => axi4lite_0_M_ARESETN(0),
S_AXI_AWADDR => axi4lite_0_M_AWADDR(8 downto 0),
S_AXI_AWVALID => axi4lite_0_M_AWVALID(0),
S_AXI_AWREADY => axi4lite_0_M_AWREADY(0),
S_AXI_WDATA => axi4lite_0_M_WDATA(31 downto 0),
S_AXI_WSTRB => axi4lite_0_M_WSTRB(3 downto 0),
S_AXI_WVALID => axi4lite_0_M_WVALID(0),
S_AXI_WREADY => axi4lite_0_M_WREADY(0),
S_AXI_BRESP => axi4lite_0_M_BRESP(1 downto 0),
S_AXI_BVALID => axi4lite_0_M_BVALID(0),
S_AXI_BREADY => axi4lite_0_M_BREADY(0),
S_AXI_ARADDR => axi4lite_0_M_ARADDR(8 downto 0),
S_AXI_ARVALID => axi4lite_0_M_ARVALID(0),
S_AXI_ARREADY => axi4lite_0_M_ARREADY(0),
S_AXI_RDATA => axi4lite_0_M_RDATA(31 downto 0),
S_AXI_RRESP => axi4lite_0_M_RRESP(1 downto 0),
S_AXI_RVALID => axi4lite_0_M_RVALID(0),
S_AXI_RREADY => axi4lite_0_M_RREADY(0),
IP2INTC_Irpt => open,
GPIO_IO_I => SWs_8Bits_TRI_IO_I,
GPIO_IO_O => SWs_8Bits_TRI_IO_O,
GPIO_IO_T => SWs_8Bits_TRI_IO_T,
GPIO2_IO_I => net_gnd32,
GPIO2_IO_O => open,
GPIO2_IO_T => open
);
BTNs_5Bits : system_btns_5bits_wrapper
port map (
S_AXI_ACLK => processing_system7_0_FCLK_CLK0(0),
S_AXI_ARESETN => axi4lite_0_M_ARESETN(1),
S_AXI_AWADDR => axi4lite_0_M_AWADDR(40 downto 32),
S_AXI_AWVALID => axi4lite_0_M_AWVALID(1),
S_AXI_AWREADY => axi4lite_0_M_AWREADY(1),
S_AXI_WDATA => axi4lite_0_M_WDATA(63 downto 32),
S_AXI_WSTRB => axi4lite_0_M_WSTRB(7 downto 4),
S_AXI_WVALID => axi4lite_0_M_WVALID(1),
S_AXI_WREADY => axi4lite_0_M_WREADY(1),
S_AXI_BRESP => axi4lite_0_M_BRESP(3 downto 2),
S_AXI_BVALID => axi4lite_0_M_BVALID(1),
S_AXI_BREADY => axi4lite_0_M_BREADY(1),
S_AXI_ARADDR => axi4lite_0_M_ARADDR(40 downto 32),
S_AXI_ARVALID => axi4lite_0_M_ARVALID(1),
S_AXI_ARREADY => axi4lite_0_M_ARREADY(1),
S_AXI_RDATA => axi4lite_0_M_RDATA(63 downto 32),
S_AXI_RRESP => axi4lite_0_M_RRESP(3 downto 2),
S_AXI_RVALID => axi4lite_0_M_RVALID(1),
S_AXI_RREADY => axi4lite_0_M_RREADY(1),
IP2INTC_Irpt => open,
GPIO_IO_I => BTNs_5Bits_TRI_IO_I,
GPIO_IO_O => BTNs_5Bits_TRI_IO_O,
GPIO_IO_T => BTNs_5Bits_TRI_IO_T,
GPIO2_IO_I => net_gnd32,
GPIO2_IO_O => open,
GPIO2_IO_T => open
);
processing_system7_0 : system_processing_system7_0_wrapper
port map (
CAN0_PHY_TX => open,
CAN0_PHY_RX => net_gnd0,
CAN1_PHY_TX => open,
CAN1_PHY_RX => net_gnd0,
ENET0_GMII_TX_EN => open,
ENET0_GMII_TX_ER => open,
ENET0_MDIO_MDC => open,
ENET0_MDIO_O => open,
ENET0_MDIO_T => open,
ENET0_PTP_DELAY_REQ_RX => open,
ENET0_PTP_DELAY_REQ_TX => open,
ENET0_PTP_PDELAY_REQ_RX => open,
ENET0_PTP_PDELAY_REQ_TX => open,
ENET0_PTP_PDELAY_RESP_RX => open,
ENET0_PTP_PDELAY_RESP_TX => open,
ENET0_PTP_SYNC_FRAME_RX => open,
ENET0_PTP_SYNC_FRAME_TX => open,
ENET0_SOF_RX => open,
ENET0_SOF_TX => open,
ENET0_GMII_TXD => open,
ENET0_GMII_COL => net_gnd0,
ENET0_GMII_CRS => net_gnd0,
ENET0_EXT_INTIN => net_gnd0,
ENET0_GMII_RX_CLK => net_gnd0,
ENET0_GMII_RX_DV => net_gnd0,
ENET0_GMII_RX_ER => net_gnd0,
ENET0_GMII_TX_CLK => net_gnd0,
ENET0_MDIO_I => net_gnd0,
ENET0_GMII_RXD => net_gnd8,
ENET1_GMII_TX_EN => open,
ENET1_GMII_TX_ER => open,
ENET1_MDIO_MDC => open,
ENET1_MDIO_O => open,
ENET1_MDIO_T => open,
ENET1_PTP_DELAY_REQ_RX => open,
ENET1_PTP_DELAY_REQ_TX => open,
ENET1_PTP_PDELAY_REQ_RX => open,
ENET1_PTP_PDELAY_REQ_TX => open,
ENET1_PTP_PDELAY_RESP_RX => open,
ENET1_PTP_PDELAY_RESP_TX => open,
ENET1_PTP_SYNC_FRAME_RX => open,
ENET1_PTP_SYNC_FRAME_TX => open,
ENET1_SOF_RX => open,
ENET1_SOF_TX => open,
ENET1_GMII_TXD => open,
ENET1_GMII_COL => net_gnd0,
ENET1_GMII_CRS => net_gnd0,
ENET1_EXT_INTIN => net_gnd0,
ENET1_GMII_RX_CLK => net_gnd0,
ENET1_GMII_RX_DV => net_gnd0,
ENET1_GMII_RX_ER => net_gnd0,
ENET1_GMII_TX_CLK => net_gnd0,
ENET1_MDIO_I => net_gnd0,
ENET1_GMII_RXD => net_gnd8,
GPIO_I => net_gnd64,
GPIO_O => open,
GPIO_T => open,
I2C0_SDA_I => net_gnd0,
I2C0_SDA_O => open,
I2C0_SDA_T => open,
I2C0_SCL_I => net_gnd0,
I2C0_SCL_O => open,
I2C0_SCL_T => open,
I2C1_SDA_I => net_gnd0,
I2C1_SDA_O => open,
I2C1_SDA_T => open,
I2C1_SCL_I => net_gnd0,
I2C1_SCL_O => open,
I2C1_SCL_T => open,
PJTAG_TCK => net_gnd0,
PJTAG_TMS => net_gnd0,
PJTAG_TD_I => net_gnd0,
PJTAG_TD_T => open,
PJTAG_TD_O => open,
SDIO0_CLK => open,
SDIO0_CLK_FB => net_gnd0,
SDIO0_CMD_O => open,
SDIO0_CMD_I => net_gnd0,
SDIO0_CMD_T => open,
SDIO0_DATA_I => net_gnd4,
SDIO0_DATA_O => open,
SDIO0_DATA_T => open,
SDIO0_LED => open,
SDIO0_CDN => net_gnd0,
SDIO0_WP => net_gnd0,
SDIO0_BUSPOW => open,
SDIO0_BUSVOLT => open,
SDIO1_CLK => open,
SDIO1_CLK_FB => net_gnd0,
SDIO1_CMD_O => open,
SDIO1_CMD_I => net_gnd0,
SDIO1_CMD_T => open,
SDIO1_DATA_I => net_gnd4,
SDIO1_DATA_O => open,
SDIO1_DATA_T => open,
SDIO1_LED => open,
SDIO1_CDN => net_gnd0,
SDIO1_WP => net_gnd0,
SDIO1_BUSPOW => open,
SDIO1_BUSVOLT => open,
SPI0_SCLK_I => net_gnd0,
SPI0_SCLK_O => open,
SPI0_SCLK_T => open,
SPI0_MOSI_I => net_gnd0,
SPI0_MOSI_O => open,
SPI0_MOSI_T => open,
SPI0_MISO_I => net_gnd0,
SPI0_MISO_O => open,
SPI0_MISO_T => open,
SPI0_SS_I => net_gnd0,
SPI0_SS_O => open,
SPI0_SS1_O => open,
SPI0_SS2_O => open,
SPI0_SS_T => open,
SPI1_SCLK_I => net_gnd0,
SPI1_SCLK_O => open,
SPI1_SCLK_T => open,
SPI1_MOSI_I => net_gnd0,
SPI1_MOSI_O => open,
SPI1_MOSI_T => open,
SPI1_MISO_I => net_gnd0,
SPI1_MISO_O => open,
SPI1_MISO_T => open,
SPI1_SS_I => net_gnd0,
SPI1_SS_O => open,
SPI1_SS1_O => open,
SPI1_SS2_O => open,
SPI1_SS_T => open,
UART0_DTRN => open,
UART0_RTSN => open,
UART0_TX => open,
UART0_CTSN => net_gnd0,
UART0_DCDN => net_gnd0,
UART0_DSRN => net_gnd0,
UART0_RIN => net_gnd0,
UART0_RX => net_gnd0,
UART1_DTRN => open,
UART1_RTSN => open,
UART1_TX => open,
UART1_CTSN => net_gnd0,
UART1_DCDN => net_gnd0,
UART1_DSRN => net_gnd0,
UART1_RIN => net_gnd0,
UART1_RX => net_gnd0,
TTC0_WAVE0_OUT => open,
TTC0_WAVE1_OUT => open,
TTC0_WAVE2_OUT => open,
TTC0_CLK0_IN => net_gnd0,
TTC0_CLK1_IN => net_gnd0,
TTC0_CLK2_IN => net_gnd0,
TTC1_WAVE0_OUT => open,
TTC1_WAVE1_OUT => open,
TTC1_WAVE2_OUT => open,
TTC1_CLK0_IN => net_gnd0,
TTC1_CLK1_IN => net_gnd0,
TTC1_CLK2_IN => net_gnd0,
WDT_CLK_IN => net_gnd0,
WDT_RST_OUT => open,
TRACE_CLK => net_gnd0,
TRACE_CTL => open,
TRACE_DATA => open,
USB0_PORT_INDCTL => open,
USB1_PORT_INDCTL => open,
USB0_VBUS_PWRSELECT => open,
USB1_VBUS_PWRSELECT => open,
USB0_VBUS_PWRFAULT => net_gnd0,
USB1_VBUS_PWRFAULT => net_gnd0,
SRAM_INTIN => net_gnd0,
M_AXI_GP0_ARESETN => open,
M_AXI_GP0_ARVALID => axi4lite_0_S_ARVALID(0),
M_AXI_GP0_AWVALID => axi4lite_0_S_AWVALID(0),
M_AXI_GP0_BREADY => axi4lite_0_S_BREADY(0),
M_AXI_GP0_RREADY => axi4lite_0_S_RREADY(0),
M_AXI_GP0_WLAST => axi4lite_0_S_WLAST(0),
M_AXI_GP0_WVALID => axi4lite_0_S_WVALID(0),
M_AXI_GP0_ARID => axi4lite_0_S_ARID,
M_AXI_GP0_AWID => axi4lite_0_S_AWID,
M_AXI_GP0_WID => axi4lite_0_S_WID,
M_AXI_GP0_ARBURST => axi4lite_0_S_ARBURST,
M_AXI_GP0_ARLOCK => axi4lite_0_S_ARLOCK,
M_AXI_GP0_ARSIZE => axi4lite_0_S_ARSIZE,
M_AXI_GP0_AWBURST => axi4lite_0_S_AWBURST,
M_AXI_GP0_AWLOCK => axi4lite_0_S_AWLOCK,
M_AXI_GP0_AWSIZE => axi4lite_0_S_AWSIZE,
M_AXI_GP0_ARPROT => axi4lite_0_S_ARPROT,
M_AXI_GP0_AWPROT => axi4lite_0_S_AWPROT,
M_AXI_GP0_ARADDR => axi4lite_0_S_ARADDR,
M_AXI_GP0_AWADDR => axi4lite_0_S_AWADDR,
M_AXI_GP0_WDATA => axi4lite_0_S_WDATA,
M_AXI_GP0_ARCACHE => axi4lite_0_S_ARCACHE,
M_AXI_GP0_ARLEN => axi4lite_0_S_ARLEN(3 downto 0),
M_AXI_GP0_ARQOS => axi4lite_0_S_ARQOS,
M_AXI_GP0_AWCACHE => axi4lite_0_S_AWCACHE,
M_AXI_GP0_AWLEN => axi4lite_0_S_AWLEN(3 downto 0),
M_AXI_GP0_AWQOS => axi4lite_0_S_AWQOS,
M_AXI_GP0_WSTRB => axi4lite_0_S_WSTRB,
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0(0),
M_AXI_GP0_ARREADY => axi4lite_0_S_ARREADY(0),
M_AXI_GP0_AWREADY => axi4lite_0_S_AWREADY(0),
M_AXI_GP0_BVALID => axi4lite_0_S_BVALID(0),
M_AXI_GP0_RLAST => axi4lite_0_S_RLAST(0),
M_AXI_GP0_RVALID => axi4lite_0_S_RVALID(0),
M_AXI_GP0_WREADY => axi4lite_0_S_WREADY(0),
M_AXI_GP0_BID => axi4lite_0_S_BID,
M_AXI_GP0_RID => axi4lite_0_S_RID,
M_AXI_GP0_BRESP => axi4lite_0_S_BRESP,
M_AXI_GP0_RRESP => axi4lite_0_S_RRESP,
M_AXI_GP0_RDATA => axi4lite_0_S_RDATA,
M_AXI_GP1_ARESETN => open,
M_AXI_GP1_ARVALID => open,
M_AXI_GP1_AWVALID => open,
M_AXI_GP1_BREADY => open,
M_AXI_GP1_RREADY => open,
M_AXI_GP1_WLAST => open,
M_AXI_GP1_WVALID => open,
M_AXI_GP1_ARID => open,
M_AXI_GP1_AWID => open,
M_AXI_GP1_WID => open,
M_AXI_GP1_ARBURST => open,
M_AXI_GP1_ARLOCK => open,
M_AXI_GP1_ARSIZE => open,
M_AXI_GP1_AWBURST => open,
M_AXI_GP1_AWLOCK => open,
M_AXI_GP1_AWSIZE => open,
M_AXI_GP1_ARPROT => open,
M_AXI_GP1_AWPROT => open,
M_AXI_GP1_ARADDR => open,
M_AXI_GP1_AWADDR => open,
M_AXI_GP1_WDATA => open,
M_AXI_GP1_ARCACHE => open,
M_AXI_GP1_ARLEN => open,
M_AXI_GP1_ARQOS => open,
M_AXI_GP1_AWCACHE => open,
M_AXI_GP1_AWLEN => open,
M_AXI_GP1_AWQOS => open,
M_AXI_GP1_WSTRB => open,
M_AXI_GP1_ACLK => net_gnd0,
M_AXI_GP1_ARREADY => net_gnd0,
M_AXI_GP1_AWREADY => net_gnd0,
M_AXI_GP1_BVALID => net_gnd0,
M_AXI_GP1_RLAST => net_gnd0,
M_AXI_GP1_RVALID => net_gnd0,
M_AXI_GP1_WREADY => net_gnd0,
M_AXI_GP1_BID => net_gnd12,
M_AXI_GP1_RID => net_gnd12,
M_AXI_GP1_BRESP => net_gnd2,
M_AXI_GP1_RRESP => net_gnd2,
M_AXI_GP1_RDATA => net_gnd32,
S_AXI_GP0_ARESETN => open,
S_AXI_GP0_ARREADY => open,
S_AXI_GP0_AWREADY => open,
S_AXI_GP0_BVALID => open,
S_AXI_GP0_RLAST => open,
S_AXI_GP0_RVALID => open,
S_AXI_GP0_WREADY => open,
S_AXI_GP0_BRESP => open,
S_AXI_GP0_RRESP => open,
S_AXI_GP0_RDATA => open,
S_AXI_GP0_BID => open,
S_AXI_GP0_RID => open,
S_AXI_GP0_ACLK => net_gnd0,
S_AXI_GP0_ARVALID => net_gnd0,
S_AXI_GP0_AWVALID => net_gnd0,
S_AXI_GP0_BREADY => net_gnd0,
S_AXI_GP0_RREADY => net_gnd0,
S_AXI_GP0_WLAST => net_gnd0,
S_AXI_GP0_WVALID => net_gnd0,
S_AXI_GP0_ARBURST => net_gnd2,
S_AXI_GP0_ARLOCK => net_gnd2,
S_AXI_GP0_ARSIZE => net_gnd3,
S_AXI_GP0_AWBURST => net_gnd2,
S_AXI_GP0_AWLOCK => net_gnd2,
S_AXI_GP0_AWSIZE => net_gnd3,
S_AXI_GP0_ARPROT => net_gnd3,
S_AXI_GP0_AWPROT => net_gnd3,
S_AXI_GP0_ARADDR => net_gnd32,
S_AXI_GP0_AWADDR => net_gnd32,
S_AXI_GP0_WDATA => net_gnd32,
S_AXI_GP0_ARCACHE => net_gnd4,
S_AXI_GP0_ARLEN => net_gnd4,
S_AXI_GP0_ARQOS => net_gnd4,
S_AXI_GP0_AWCACHE => net_gnd4,
S_AXI_GP0_AWLEN => net_gnd4,
S_AXI_GP0_AWQOS => net_gnd4,
S_AXI_GP0_WSTRB => net_gnd4,
S_AXI_GP0_ARID => net_gnd6,
S_AXI_GP0_AWID => net_gnd6,
S_AXI_GP0_WID => net_gnd6,
S_AXI_GP1_ARESETN => open,
S_AXI_GP1_ARREADY => open,
S_AXI_GP1_AWREADY => open,
S_AXI_GP1_BVALID => open,
S_AXI_GP1_RLAST => open,
S_AXI_GP1_RVALID => open,
S_AXI_GP1_WREADY => open,
S_AXI_GP1_BRESP => open,
S_AXI_GP1_RRESP => open,
S_AXI_GP1_RDATA => open,
S_AXI_GP1_BID => open,
S_AXI_GP1_RID => open,
S_AXI_GP1_ACLK => net_gnd0,
S_AXI_GP1_ARVALID => net_gnd0,
S_AXI_GP1_AWVALID => net_gnd0,
S_AXI_GP1_BREADY => net_gnd0,
S_AXI_GP1_RREADY => net_gnd0,
S_AXI_GP1_WLAST => net_gnd0,
S_AXI_GP1_WVALID => net_gnd0,
S_AXI_GP1_ARBURST => net_gnd2,
S_AXI_GP1_ARLOCK => net_gnd2,
S_AXI_GP1_ARSIZE => net_gnd3,
S_AXI_GP1_AWBURST => net_gnd2,
S_AXI_GP1_AWLOCK => net_gnd2,
S_AXI_GP1_AWSIZE => net_gnd3,
S_AXI_GP1_ARPROT => net_gnd3,
S_AXI_GP1_AWPROT => net_gnd3,
S_AXI_GP1_ARADDR => net_gnd32,
S_AXI_GP1_AWADDR => net_gnd32,
S_AXI_GP1_WDATA => net_gnd32,
S_AXI_GP1_ARCACHE => net_gnd4,
S_AXI_GP1_ARLEN => net_gnd4,
S_AXI_GP1_ARQOS => net_gnd4,
S_AXI_GP1_AWCACHE => net_gnd4,
S_AXI_GP1_AWLEN => net_gnd4,
S_AXI_GP1_AWQOS => net_gnd4,
S_AXI_GP1_WSTRB => net_gnd4,
S_AXI_GP1_ARID => net_gnd6,
S_AXI_GP1_AWID => net_gnd6,
S_AXI_GP1_WID => net_gnd6,
S_AXI_ACP_ARESETN => open,
S_AXI_ACP_AWREADY => open,
S_AXI_ACP_ARREADY => open,
S_AXI_ACP_BVALID => open,
S_AXI_ACP_RLAST => open,
S_AXI_ACP_RVALID => open,
S_AXI_ACP_WREADY => open,
S_AXI_ACP_BRESP => open,
S_AXI_ACP_RRESP => open,
S_AXI_ACP_BID => open,
S_AXI_ACP_RID => open,
S_AXI_ACP_RDATA => open,
S_AXI_ACP_ACLK => net_gnd0,
S_AXI_ACP_ARVALID => net_gnd0,
S_AXI_ACP_AWVALID => net_gnd0,
S_AXI_ACP_BREADY => net_gnd0,
S_AXI_ACP_RREADY => net_gnd0,
S_AXI_ACP_WLAST => net_gnd0,
S_AXI_ACP_WVALID => net_gnd0,
S_AXI_ACP_ARID => net_gnd3,
S_AXI_ACP_ARPROT => net_gnd3,
S_AXI_ACP_AWID => net_gnd3,
S_AXI_ACP_AWPROT => net_gnd3,
S_AXI_ACP_WID => net_gnd3,
S_AXI_ACP_ARADDR => net_gnd32,
S_AXI_ACP_AWADDR => net_gnd32,
S_AXI_ACP_ARCACHE => net_gnd4,
S_AXI_ACP_ARLEN => net_gnd4,
S_AXI_ACP_ARQOS => net_gnd4,
S_AXI_ACP_AWCACHE => net_gnd4,
S_AXI_ACP_AWLEN => net_gnd4,
S_AXI_ACP_AWQOS => net_gnd4,
S_AXI_ACP_ARBURST => net_gnd2,
S_AXI_ACP_ARLOCK => net_gnd2,
S_AXI_ACP_ARSIZE => net_gnd3,
S_AXI_ACP_AWBURST => net_gnd2,
S_AXI_ACP_AWLOCK => net_gnd2,
S_AXI_ACP_AWSIZE => net_gnd3,
S_AXI_ACP_ARUSER => net_gnd5,
S_AXI_ACP_AWUSER => net_gnd5,
S_AXI_ACP_WDATA => net_gnd64,
S_AXI_ACP_WSTRB => net_gnd8,
S_AXI_HP0_ARESETN => open,
S_AXI_HP0_ARREADY => axi_interconnect_1_M_ARREADY(0),
S_AXI_HP0_AWREADY => axi_interconnect_1_M_AWREADY(0),
S_AXI_HP0_BVALID => axi_interconnect_1_M_BVALID(0),
S_AXI_HP0_RLAST => axi_interconnect_1_M_RLAST(0),
S_AXI_HP0_RVALID => axi_interconnect_1_M_RVALID(0),
S_AXI_HP0_WREADY => axi_interconnect_1_M_WREADY(0),
S_AXI_HP0_BRESP => axi_interconnect_1_M_BRESP,
S_AXI_HP0_RRESP => axi_interconnect_1_M_RRESP,
S_AXI_HP0_BID => axi_interconnect_1_M_BID,
S_AXI_HP0_RID => axi_interconnect_1_M_RID,
S_AXI_HP0_RDATA => axi_interconnect_1_M_RDATA,
S_AXI_HP0_RCOUNT => open,
S_AXI_HP0_WCOUNT => open,
S_AXI_HP0_RACOUNT => open,
S_AXI_HP0_WACOUNT => open,
S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0(0),
S_AXI_HP0_ARVALID => axi_interconnect_1_M_ARVALID(0),
S_AXI_HP0_AWVALID => axi_interconnect_1_M_AWVALID(0),
S_AXI_HP0_BREADY => axi_interconnect_1_M_BREADY(0),
S_AXI_HP0_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP0_RREADY => axi_interconnect_1_M_RREADY(0),
S_AXI_HP0_WLAST => axi_interconnect_1_M_WLAST(0),
S_AXI_HP0_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP0_WVALID => axi_interconnect_1_M_WVALID(0),
S_AXI_HP0_ARBURST => axi_interconnect_1_M_ARBURST,
S_AXI_HP0_ARLOCK => axi_interconnect_1_M_ARLOCK,
S_AXI_HP0_ARSIZE => axi_interconnect_1_M_ARSIZE,
S_AXI_HP0_AWBURST => axi_interconnect_1_M_AWBURST,
S_AXI_HP0_AWLOCK => axi_interconnect_1_M_AWLOCK,
S_AXI_HP0_AWSIZE => axi_interconnect_1_M_AWSIZE,
S_AXI_HP0_ARPROT => axi_interconnect_1_M_ARPROT,
S_AXI_HP0_AWPROT => axi_interconnect_1_M_AWPROT,
S_AXI_HP0_ARADDR => axi_interconnect_1_M_ARADDR,
S_AXI_HP0_AWADDR => axi_interconnect_1_M_AWADDR,
S_AXI_HP0_ARCACHE => axi_interconnect_1_M_ARCACHE,
S_AXI_HP0_ARLEN => axi_interconnect_1_M_ARLEN(3 downto 0),
S_AXI_HP0_ARQOS => axi_interconnect_1_M_ARQOS,
S_AXI_HP0_AWCACHE => axi_interconnect_1_M_AWCACHE,
S_AXI_HP0_AWLEN => axi_interconnect_1_M_AWLEN(3 downto 0),
S_AXI_HP0_AWQOS => axi_interconnect_1_M_AWQOS,
S_AXI_HP0_ARID => axi_interconnect_1_M_ARID,
S_AXI_HP0_AWID => axi_interconnect_1_M_AWID,
S_AXI_HP0_WID => axi_interconnect_1_M_WID,
S_AXI_HP0_WDATA => axi_interconnect_1_M_WDATA,
S_AXI_HP0_WSTRB => axi_interconnect_1_M_WSTRB,
S_AXI_HP1_ARESETN => open,
S_AXI_HP1_ARREADY => open,
S_AXI_HP1_AWREADY => open,
S_AXI_HP1_BVALID => open,
S_AXI_HP1_RLAST => open,
S_AXI_HP1_RVALID => open,
S_AXI_HP1_WREADY => open,
S_AXI_HP1_BRESP => open,
S_AXI_HP1_RRESP => open,
S_AXI_HP1_BID => open,
S_AXI_HP1_RID => open,
S_AXI_HP1_RDATA => open,
S_AXI_HP1_RCOUNT => open,
S_AXI_HP1_WCOUNT => open,
S_AXI_HP1_RACOUNT => open,
S_AXI_HP1_WACOUNT => open,
S_AXI_HP1_ACLK => net_gnd0,
S_AXI_HP1_ARVALID => net_gnd0,
S_AXI_HP1_AWVALID => net_gnd0,
S_AXI_HP1_BREADY => net_gnd0,
S_AXI_HP1_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP1_RREADY => net_gnd0,
S_AXI_HP1_WLAST => net_gnd0,
S_AXI_HP1_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP1_WVALID => net_gnd0,
S_AXI_HP1_ARBURST => net_gnd2,
S_AXI_HP1_ARLOCK => net_gnd2,
S_AXI_HP1_ARSIZE => net_gnd3,
S_AXI_HP1_AWBURST => net_gnd2,
S_AXI_HP1_AWLOCK => net_gnd2,
S_AXI_HP1_AWSIZE => net_gnd3,
S_AXI_HP1_ARPROT => net_gnd3,
S_AXI_HP1_AWPROT => net_gnd3,
S_AXI_HP1_ARADDR => net_gnd32,
S_AXI_HP1_AWADDR => net_gnd32,
S_AXI_HP1_ARCACHE => net_gnd4,
S_AXI_HP1_ARLEN => net_gnd4,
S_AXI_HP1_ARQOS => net_gnd4,
S_AXI_HP1_AWCACHE => net_gnd4,
S_AXI_HP1_AWLEN => net_gnd4,
S_AXI_HP1_AWQOS => net_gnd4,
S_AXI_HP1_ARID => net_gnd6,
S_AXI_HP1_AWID => net_gnd6,
S_AXI_HP1_WID => net_gnd6,
S_AXI_HP1_WDATA => net_gnd64,
S_AXI_HP1_WSTRB => net_gnd8,
S_AXI_HP2_ARESETN => open,
S_AXI_HP2_ARREADY => open,
S_AXI_HP2_AWREADY => open,
S_AXI_HP2_BVALID => open,
S_AXI_HP2_RLAST => open,
S_AXI_HP2_RVALID => open,
S_AXI_HP2_WREADY => open,
S_AXI_HP2_BRESP => open,
S_AXI_HP2_RRESP => open,
S_AXI_HP2_BID => open,
S_AXI_HP2_RID => open,
S_AXI_HP2_RDATA => open,
S_AXI_HP2_RCOUNT => open,
S_AXI_HP2_WCOUNT => open,
S_AXI_HP2_RACOUNT => open,
S_AXI_HP2_WACOUNT => open,
S_AXI_HP2_ACLK => net_gnd0,
S_AXI_HP2_ARVALID => net_gnd0,
S_AXI_HP2_AWVALID => net_gnd0,
S_AXI_HP2_BREADY => net_gnd0,
S_AXI_HP2_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP2_RREADY => net_gnd0,
S_AXI_HP2_WLAST => net_gnd0,
S_AXI_HP2_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP2_WVALID => net_gnd0,
S_AXI_HP2_ARBURST => net_gnd2,
S_AXI_HP2_ARLOCK => net_gnd2,
S_AXI_HP2_ARSIZE => net_gnd3,
S_AXI_HP2_AWBURST => net_gnd2,
S_AXI_HP2_AWLOCK => net_gnd2,
S_AXI_HP2_AWSIZE => net_gnd3,
S_AXI_HP2_ARPROT => net_gnd3,
S_AXI_HP2_AWPROT => net_gnd3,
S_AXI_HP2_ARADDR => net_gnd32,
S_AXI_HP2_AWADDR => net_gnd32,
S_AXI_HP2_ARCACHE => net_gnd4,
S_AXI_HP2_ARLEN => net_gnd4,
S_AXI_HP2_ARQOS => net_gnd4,
S_AXI_HP2_AWCACHE => net_gnd4,
S_AXI_HP2_AWLEN => net_gnd4,
S_AXI_HP2_AWQOS => net_gnd4,
S_AXI_HP2_ARID => net_gnd6,
S_AXI_HP2_AWID => net_gnd6,
S_AXI_HP2_WID => net_gnd6,
S_AXI_HP2_WDATA => net_gnd64,
S_AXI_HP2_WSTRB => net_gnd8,
S_AXI_HP3_ARESETN => open,
S_AXI_HP3_ARREADY => open,
S_AXI_HP3_AWREADY => open,
S_AXI_HP3_BVALID => open,
S_AXI_HP3_RLAST => open,
S_AXI_HP3_RVALID => open,
S_AXI_HP3_WREADY => open,
S_AXI_HP3_BRESP => open,
S_AXI_HP3_RRESP => open,
S_AXI_HP3_BID => open,
S_AXI_HP3_RID => open,
S_AXI_HP3_RDATA => open,
S_AXI_HP3_RCOUNT => open,
S_AXI_HP3_WCOUNT => open,
S_AXI_HP3_RACOUNT => open,
S_AXI_HP3_WACOUNT => open,
S_AXI_HP3_ACLK => net_gnd0,
S_AXI_HP3_ARVALID => net_gnd0,
S_AXI_HP3_AWVALID => net_gnd0,
S_AXI_HP3_BREADY => net_gnd0,
S_AXI_HP3_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP3_RREADY => net_gnd0,
S_AXI_HP3_WLAST => net_gnd0,
S_AXI_HP3_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP3_WVALID => net_gnd0,
S_AXI_HP3_ARBURST => net_gnd2,
S_AXI_HP3_ARLOCK => net_gnd2,
S_AXI_HP3_ARSIZE => net_gnd3,
S_AXI_HP3_AWBURST => net_gnd2,
S_AXI_HP3_AWLOCK => net_gnd2,
S_AXI_HP3_AWSIZE => net_gnd3,
S_AXI_HP3_ARPROT => net_gnd3,
S_AXI_HP3_AWPROT => net_gnd3,
S_AXI_HP3_ARADDR => net_gnd32,
S_AXI_HP3_AWADDR => net_gnd32,
S_AXI_HP3_ARCACHE => net_gnd4,
S_AXI_HP3_ARLEN => net_gnd4,
S_AXI_HP3_ARQOS => net_gnd4,
S_AXI_HP3_AWCACHE => net_gnd4,
S_AXI_HP3_AWLEN => net_gnd4,
S_AXI_HP3_AWQOS => net_gnd4,
S_AXI_HP3_ARID => net_gnd6,
S_AXI_HP3_AWID => net_gnd6,
S_AXI_HP3_WID => net_gnd6,
S_AXI_HP3_WDATA => net_gnd64,
S_AXI_HP3_WSTRB => net_gnd8,
DMA0_DATYPE => open,
DMA0_DAVALID => open,
DMA0_DRREADY => open,
DMA0_RSTN => open,
DMA0_ACLK => net_gnd0,
DMA0_DAREADY => net_gnd0,
DMA0_DRLAST => net_gnd0,
DMA0_DRVALID => net_gnd0,
DMA0_DRTYPE => net_gnd2,
DMA1_DATYPE => open,
DMA1_DAVALID => open,
DMA1_DRREADY => open,
DMA1_RSTN => open,
DMA1_ACLK => net_gnd0,
DMA1_DAREADY => net_gnd0,
DMA1_DRLAST => net_gnd0,
DMA1_DRVALID => net_gnd0,
DMA1_DRTYPE => net_gnd2,
DMA2_DATYPE => open,
DMA2_DAVALID => open,
DMA2_DRREADY => open,
DMA2_RSTN => open,
DMA2_ACLK => net_gnd0,
DMA2_DAREADY => net_gnd0,
DMA2_DRLAST => net_gnd0,
DMA2_DRVALID => net_gnd0,
DMA3_DRVALID => net_gnd0,
DMA3_DATYPE => open,
DMA3_DAVALID => open,
DMA3_DRREADY => open,
DMA3_RSTN => open,
DMA3_ACLK => net_gnd0,
DMA3_DAREADY => net_gnd0,
DMA3_DRLAST => net_gnd0,
DMA2_DRTYPE => net_gnd2,
DMA3_DRTYPE => net_gnd2,
FTMD_TRACEIN_DATA => net_gnd32,
FTMD_TRACEIN_VALID => net_gnd0,
FTMD_TRACEIN_CLK => net_gnd0,
FTMD_TRACEIN_ATID => net_gnd4,
FTMT_F2P_TRIG => net_gnd4,
FTMT_F2P_TRIGACK => open,
FTMT_F2P_DEBUG => net_gnd32,
FTMT_P2F_TRIGACK => net_gnd4,
FTMT_P2F_TRIG => open,
FTMT_P2F_DEBUG => open,
FCLK_CLK3 => open,
FCLK_CLK2 => open,
FCLK_CLK1 => open,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0(0),
FCLK_CLKTRIG3_N => net_gnd0,
FCLK_CLKTRIG2_N => net_gnd0,
FCLK_CLKTRIG1_N => net_gnd0,
FCLK_CLKTRIG0_N => net_gnd0,
FCLK_RESET3_N => open,
FCLK_RESET2_N => open,
FCLK_RESET1_N => open,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N_0,
FPGA_IDLE_N => net_gnd0,
DDR_ARB => net_gnd4,
IRQ_F2P => pgassign2,
Core0_nFIQ => net_gnd0,
Core0_nIRQ => net_gnd0,
Core1_nFIQ => net_gnd0,
Core1_nIRQ => net_gnd0,
EVENT_EVENTO => open,
EVENT_STANDBYWFE => open,
EVENT_STANDBYWFI => open,
EVENT_EVENTI => net_gnd0,
MIO => processing_system7_0_MIO,
DDR_Clk => processing_system7_0_DDR_Clk,
DDR_Clk_n => processing_system7_0_DDR_Clk_n,
DDR_CKE => processing_system7_0_DDR_CKE,
DDR_CS_n => processing_system7_0_DDR_CS_n,
DDR_RAS_n => processing_system7_0_DDR_RAS_n,
DDR_CAS_n => processing_system7_0_DDR_CAS_n,
DDR_WEB => processing_system7_0_DDR_WEB,
DDR_BankAddr => processing_system7_0_DDR_BankAddr,
DDR_Addr => processing_system7_0_DDR_Addr,
DDR_ODT => processing_system7_0_DDR_ODT,
DDR_DRSTB => processing_system7_0_DDR_DRSTB,
DDR_DQ => processing_system7_0_DDR_DQ,
DDR_DM => processing_system7_0_DDR_DM,
DDR_DQS => processing_system7_0_DDR_DQS,
DDR_DQS_n => processing_system7_0_DDR_DQS_n,
DDR_VRN => processing_system7_0_DDR_VRN,
DDR_VRP => processing_system7_0_DDR_VRP,
PS_SRSTB => processing_system7_0_PS_SRSTB,
PS_CLK => processing_system7_0_PS_CLK,
PS_PORB => processing_system7_0_PS_PORB,
IRQ_P2F_DMAC_ABORT => open,
IRQ_P2F_DMAC0 => open,
IRQ_P2F_DMAC1 => open,
IRQ_P2F_DMAC2 => open,
IRQ_P2F_DMAC3 => open,
IRQ_P2F_DMAC4 => open,
IRQ_P2F_DMAC5 => open,
IRQ_P2F_DMAC6 => open,
IRQ_P2F_DMAC7 => open,
IRQ_P2F_SMC => open,
IRQ_P2F_QSPI => open,
IRQ_P2F_CTI => open,
IRQ_P2F_GPIO => open,
IRQ_P2F_USB0 => open,
IRQ_P2F_ENET0 => open,
IRQ_P2F_ENET_WAKE0 => open,
IRQ_P2F_SDIO0 => open,
IRQ_P2F_I2C0 => open,
IRQ_P2F_SPI0 => open,
IRQ_P2F_UART0 => open,
IRQ_P2F_CAN0 => open,
IRQ_P2F_USB1 => open,
IRQ_P2F_ENET1 => open,
IRQ_P2F_ENET_WAKE1 => open,
IRQ_P2F_SDIO1 => open,
IRQ_P2F_I2C1 => open,
IRQ_P2F_SPI1 => open,
IRQ_P2F_UART1 => open,
IRQ_P2F_CAN1 => open
);
axi_dma_0 : system_axi_dma_0_wrapper
port map (
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0(0),
m_axi_sg_aclk => processing_system7_0_FCLK_CLK0(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0(0),
m_axi_s2mm_aclk => processing_system7_0_FCLK_CLK0(0),
axi_resetn => axi4lite_0_M_ARESETN(2),
s_axi_lite_awvalid => axi4lite_0_M_AWVALID(2),
s_axi_lite_awready => axi4lite_0_M_AWREADY(2),
s_axi_lite_awaddr => axi4lite_0_M_AWADDR(73 downto 64),
s_axi_lite_wvalid => axi4lite_0_M_WVALID(2),
s_axi_lite_wready => axi4lite_0_M_WREADY(2),
s_axi_lite_wdata => axi4lite_0_M_WDATA(95 downto 64),
s_axi_lite_bresp => axi4lite_0_M_BRESP(5 downto 4),
s_axi_lite_bvalid => axi4lite_0_M_BVALID(2),
s_axi_lite_bready => axi4lite_0_M_BREADY(2),
s_axi_lite_arvalid => axi4lite_0_M_ARVALID(2),
s_axi_lite_arready => axi4lite_0_M_ARREADY(2),
s_axi_lite_araddr => axi4lite_0_M_ARADDR(73 downto 64),
s_axi_lite_rvalid => axi4lite_0_M_RVALID(2),
s_axi_lite_rready => axi4lite_0_M_RREADY(2),
s_axi_lite_rdata => axi4lite_0_M_RDATA(95 downto 64),
s_axi_lite_rresp => axi4lite_0_M_RRESP(5 downto 4),
m_axi_sg_awaddr => axi_interconnect_1_S_AWADDR(31 downto 0),
m_axi_sg_awlen => axi_interconnect_1_S_AWLEN(7 downto 0),
m_axi_sg_awsize => axi_interconnect_1_S_AWSIZE(2 downto 0),
m_axi_sg_awburst => axi_interconnect_1_S_AWBURST(1 downto 0),
m_axi_sg_awprot => axi_interconnect_1_S_AWPROT(2 downto 0),
m_axi_sg_awcache => axi_interconnect_1_S_AWCACHE(3 downto 0),
m_axi_sg_awuser => axi_interconnect_1_S_AWUSER(3 downto 0),
m_axi_sg_awvalid => axi_interconnect_1_S_AWVALID(0),
m_axi_sg_awready => axi_interconnect_1_S_AWREADY(0),
m_axi_sg_wdata => axi_interconnect_1_S_WDATA(31 downto 0),
m_axi_sg_wstrb => axi_interconnect_1_S_WSTRB(3 downto 0),
m_axi_sg_wlast => axi_interconnect_1_S_WLAST(0),
m_axi_sg_wvalid => axi_interconnect_1_S_WVALID(0),
m_axi_sg_wready => axi_interconnect_1_S_WREADY(0),
m_axi_sg_bresp => axi_interconnect_1_S_BRESP(1 downto 0),
m_axi_sg_bvalid => axi_interconnect_1_S_BVALID(0),
m_axi_sg_bready => axi_interconnect_1_S_BREADY(0),
m_axi_sg_araddr => axi_interconnect_1_S_ARADDR(31 downto 0),
m_axi_sg_arlen => axi_interconnect_1_S_ARLEN(7 downto 0),
m_axi_sg_arsize => axi_interconnect_1_S_ARSIZE(2 downto 0),
m_axi_sg_arburst => axi_interconnect_1_S_ARBURST(1 downto 0),
m_axi_sg_arprot => axi_interconnect_1_S_ARPROT(2 downto 0),
m_axi_sg_arcache => axi_interconnect_1_S_ARCACHE(3 downto 0),
m_axi_sg_aruser => axi_interconnect_1_S_ARUSER(3 downto 0),
m_axi_sg_arvalid => axi_interconnect_1_S_ARVALID(0),
m_axi_sg_arready => axi_interconnect_1_S_ARREADY(0),
m_axi_sg_rdata => axi_interconnect_1_S_RDATA(31 downto 0),
m_axi_sg_rresp => axi_interconnect_1_S_RRESP(1 downto 0),
m_axi_sg_rlast => axi_interconnect_1_S_RLAST(0),
m_axi_sg_rvalid => axi_interconnect_1_S_RVALID(0),
m_axi_sg_rready => axi_interconnect_1_S_RREADY(0),
m_axi_mm2s_araddr => axi_interconnect_1_S_ARADDR(63 downto 32),
m_axi_mm2s_arlen => axi_interconnect_1_S_ARLEN(15 downto 8),
m_axi_mm2s_arsize => axi_interconnect_1_S_ARSIZE(5 downto 3),
m_axi_mm2s_arburst => axi_interconnect_1_S_ARBURST(3 downto 2),
m_axi_mm2s_arprot => axi_interconnect_1_S_ARPROT(5 downto 3),
m_axi_mm2s_arcache => axi_interconnect_1_S_ARCACHE(7 downto 4),
m_axi_mm2s_aruser => axi_interconnect_1_S_ARUSER(7 downto 4),
m_axi_mm2s_arvalid => axi_interconnect_1_S_ARVALID(1),
m_axi_mm2s_arready => axi_interconnect_1_S_ARREADY(1),
m_axi_mm2s_rdata => axi_interconnect_1_S_RDATA(95 downto 64),
m_axi_mm2s_rresp => axi_interconnect_1_S_RRESP(3 downto 2),
m_axi_mm2s_rlast => axi_interconnect_1_S_RLAST(1),
m_axi_mm2s_rvalid => axi_interconnect_1_S_RVALID(1),
m_axi_mm2s_rready => axi_interconnect_1_S_RREADY(1),
mm2s_prmry_reset_out_n => open,
m_axis_mm2s_tdata => axi_dma_0_M_AXIS_MM2S_TDATA,
m_axis_mm2s_tkeep => open,
m_axis_mm2s_tvalid => axi_dma_0_M_AXIS_MM2S_TVALID,
m_axis_mm2s_tready => axi_dma_0_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tlast => axi_dma_0_M_AXIS_MM2S_TLAST,
m_axis_mm2s_tuser => open,
m_axis_mm2s_tid => open,
m_axis_mm2s_tdest => open,
mm2s_cntrl_reset_out_n => open,
m_axis_mm2s_cntrl_tdata => open,
m_axis_mm2s_cntrl_tkeep => open,
m_axis_mm2s_cntrl_tvalid => open,
m_axis_mm2s_cntrl_tready => net_gnd0,
m_axis_mm2s_cntrl_tlast => open,
m_axi_s2mm_awaddr => axi_interconnect_1_S_AWADDR(95 downto 64),
m_axi_s2mm_awlen => axi_interconnect_1_S_AWLEN(23 downto 16),
m_axi_s2mm_awsize => axi_interconnect_1_S_AWSIZE(8 downto 6),
m_axi_s2mm_awburst => axi_interconnect_1_S_AWBURST(5 downto 4),
m_axi_s2mm_awprot => axi_interconnect_1_S_AWPROT(8 downto 6),
m_axi_s2mm_awcache => axi_interconnect_1_S_AWCACHE(11 downto 8),
m_axi_s2mm_awuser => axi_interconnect_1_S_AWUSER(11 downto 8),
m_axi_s2mm_awvalid => axi_interconnect_1_S_AWVALID(2),
m_axi_s2mm_awready => axi_interconnect_1_S_AWREADY(2),
m_axi_s2mm_wdata => axi_interconnect_1_S_WDATA(159 downto 128),
m_axi_s2mm_wstrb => axi_interconnect_1_S_WSTRB(19 downto 16),
m_axi_s2mm_wlast => axi_interconnect_1_S_WLAST(2),
m_axi_s2mm_wvalid => axi_interconnect_1_S_WVALID(2),
m_axi_s2mm_wready => axi_interconnect_1_S_WREADY(2),
m_axi_s2mm_bresp => axi_interconnect_1_S_BRESP(5 downto 4),
m_axi_s2mm_bvalid => axi_interconnect_1_S_BVALID(2),
m_axi_s2mm_bready => axi_interconnect_1_S_BREADY(2),
s2mm_prmry_reset_out_n => open,
s_axis_s2mm_tdata => conware_0_M_AXIS_TDATA,
s_axis_s2mm_tkeep => conware_0_M_AXIS_TKEEP,
s_axis_s2mm_tvalid => conware_0_M_AXIS_TVALID,
s_axis_s2mm_tready => conware_0_M_AXIS_TREADY,
s_axis_s2mm_tlast => conware_0_M_AXIS_TLAST,
s_axis_s2mm_tuser => net_gnd4,
s_axis_s2mm_tid => net_gnd5,
s_axis_s2mm_tdest => net_gnd5,
s2mm_sts_reset_out_n => open,
s_axis_s2mm_sts_tdata => net_gnd32,
s_axis_s2mm_sts_tkeep => net_vcc4,
s_axis_s2mm_sts_tvalid => net_gnd0,
s_axis_s2mm_sts_tready => open,
s_axis_s2mm_sts_tlast => net_gnd0,
mm2s_introut => axi_dma_0_mm2s_introut,
s2mm_introut => axi_dma_0_s2mm_introut,
axi_dma_tstvec => open
);
axi_interconnect_1 : system_axi_interconnect_1_wrapper
port map (
INTERCONNECT_ACLK => processing_system7_0_FCLK_CLK0(0),
INTERCONNECT_ARESETN => processing_system7_0_FCLK_RESET0_N_0,
S_AXI_ARESET_OUT_N => open,
M_AXI_ARESET_OUT_N => open,
IRQ => open,
S_AXI_ACLK => pgassign3,
S_AXI_AWID => net_gnd6,
S_AXI_AWADDR => axi_interconnect_1_S_AWADDR,
S_AXI_AWLEN => axi_interconnect_1_S_AWLEN,
S_AXI_AWSIZE => axi_interconnect_1_S_AWSIZE,
S_AXI_AWBURST => axi_interconnect_1_S_AWBURST,
S_AXI_AWLOCK => net_gnd6,
S_AXI_AWCACHE => axi_interconnect_1_S_AWCACHE,
S_AXI_AWPROT => axi_interconnect_1_S_AWPROT,
S_AXI_AWQOS => net_gnd12,
S_AXI_AWUSER => axi_interconnect_1_S_AWUSER,
S_AXI_AWVALID => axi_interconnect_1_S_AWVALID,
S_AXI_AWREADY => axi_interconnect_1_S_AWREADY,
S_AXI_WID => net_gnd6,
S_AXI_WDATA => axi_interconnect_1_S_WDATA,
S_AXI_WSTRB => axi_interconnect_1_S_WSTRB,
S_AXI_WLAST => axi_interconnect_1_S_WLAST,
S_AXI_WUSER => net_gnd3,
S_AXI_WVALID => axi_interconnect_1_S_WVALID,
S_AXI_WREADY => axi_interconnect_1_S_WREADY,
S_AXI_BID => open,
S_AXI_BRESP => axi_interconnect_1_S_BRESP,
S_AXI_BUSER => open,
S_AXI_BVALID => axi_interconnect_1_S_BVALID,
S_AXI_BREADY => axi_interconnect_1_S_BREADY,
S_AXI_ARID => net_gnd6,
S_AXI_ARADDR => axi_interconnect_1_S_ARADDR,
S_AXI_ARLEN => axi_interconnect_1_S_ARLEN,
S_AXI_ARSIZE => axi_interconnect_1_S_ARSIZE,
S_AXI_ARBURST => axi_interconnect_1_S_ARBURST,
S_AXI_ARLOCK => net_gnd6,
S_AXI_ARCACHE => axi_interconnect_1_S_ARCACHE,
S_AXI_ARPROT => axi_interconnect_1_S_ARPROT,
S_AXI_ARQOS => net_gnd12,
S_AXI_ARUSER => axi_interconnect_1_S_ARUSER,
S_AXI_ARVALID => axi_interconnect_1_S_ARVALID,
S_AXI_ARREADY => axi_interconnect_1_S_ARREADY,
S_AXI_RID => open,
S_AXI_RDATA => axi_interconnect_1_S_RDATA,
S_AXI_RRESP => axi_interconnect_1_S_RRESP,
S_AXI_RLAST => axi_interconnect_1_S_RLAST,
S_AXI_RUSER => open,
S_AXI_RVALID => axi_interconnect_1_S_RVALID,
S_AXI_RREADY => axi_interconnect_1_S_RREADY,
M_AXI_ACLK => processing_system7_0_FCLK_CLK0(0 to 0),
M_AXI_AWID => axi_interconnect_1_M_AWID,
M_AXI_AWADDR => axi_interconnect_1_M_AWADDR,
M_AXI_AWLEN => axi_interconnect_1_M_AWLEN,
M_AXI_AWSIZE => axi_interconnect_1_M_AWSIZE,
M_AXI_AWBURST => axi_interconnect_1_M_AWBURST,
M_AXI_AWLOCK => axi_interconnect_1_M_AWLOCK,
M_AXI_AWCACHE => axi_interconnect_1_M_AWCACHE,
M_AXI_AWPROT => axi_interconnect_1_M_AWPROT,
M_AXI_AWREGION => open,
M_AXI_AWQOS => axi_interconnect_1_M_AWQOS,
M_AXI_AWUSER => open,
M_AXI_AWVALID => axi_interconnect_1_M_AWVALID(0 to 0),
M_AXI_AWREADY => axi_interconnect_1_M_AWREADY(0 to 0),
M_AXI_WID => axi_interconnect_1_M_WID,
M_AXI_WDATA => axi_interconnect_1_M_WDATA,
M_AXI_WSTRB => axi_interconnect_1_M_WSTRB,
M_AXI_WLAST => axi_interconnect_1_M_WLAST(0 to 0),
M_AXI_WUSER => open,
M_AXI_WVALID => axi_interconnect_1_M_WVALID(0 to 0),
M_AXI_WREADY => axi_interconnect_1_M_WREADY(0 to 0),
M_AXI_BID => axi_interconnect_1_M_BID,
M_AXI_BRESP => axi_interconnect_1_M_BRESP,
M_AXI_BUSER => net_gnd1(0 to 0),
M_AXI_BVALID => axi_interconnect_1_M_BVALID(0 to 0),
M_AXI_BREADY => axi_interconnect_1_M_BREADY(0 to 0),
M_AXI_ARID => axi_interconnect_1_M_ARID,
M_AXI_ARADDR => axi_interconnect_1_M_ARADDR,
M_AXI_ARLEN => axi_interconnect_1_M_ARLEN,
M_AXI_ARSIZE => axi_interconnect_1_M_ARSIZE,
M_AXI_ARBURST => axi_interconnect_1_M_ARBURST,
M_AXI_ARLOCK => axi_interconnect_1_M_ARLOCK,
M_AXI_ARCACHE => axi_interconnect_1_M_ARCACHE,
M_AXI_ARPROT => axi_interconnect_1_M_ARPROT,
M_AXI_ARREGION => open,
M_AXI_ARQOS => axi_interconnect_1_M_ARQOS,
M_AXI_ARUSER => open,
M_AXI_ARVALID => axi_interconnect_1_M_ARVALID(0 to 0),
M_AXI_ARREADY => axi_interconnect_1_M_ARREADY(0 to 0),
M_AXI_RID => axi_interconnect_1_M_RID,
M_AXI_RDATA => axi_interconnect_1_M_RDATA,
M_AXI_RRESP => axi_interconnect_1_M_RRESP,
M_AXI_RLAST => axi_interconnect_1_M_RLAST(0 to 0),
M_AXI_RUSER => net_gnd1(0 to 0),
M_AXI_RVALID => axi_interconnect_1_M_RVALID(0 to 0),
M_AXI_RREADY => axi_interconnect_1_M_RREADY(0 to 0),
S_AXI_CTRL_AWADDR => net_gnd32,
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32,
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32,
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0,
INTERCONNECT_ARESET_OUT_N => open,
DEBUG_AW_TRANS_SEQ => open,
DEBUG_AW_ARB_GRANT => open,
DEBUG_AR_TRANS_SEQ => open,
DEBUG_AR_ARB_GRANT => open,
DEBUG_AW_TRANS_QUAL => open,
DEBUG_AW_ACCEPT_CNT => open,
DEBUG_AW_ACTIVE_THREAD => open,
DEBUG_AW_ACTIVE_TARGET => open,
DEBUG_AW_ACTIVE_REGION => open,
DEBUG_AW_ERROR => open,
DEBUG_AW_TARGET => open,
DEBUG_AR_TRANS_QUAL => open,
DEBUG_AR_ACCEPT_CNT => open,
DEBUG_AR_ACTIVE_THREAD => open,
DEBUG_AR_ACTIVE_TARGET => open,
DEBUG_AR_ACTIVE_REGION => open,
DEBUG_AR_ERROR => open,
DEBUG_AR_TARGET => open,
DEBUG_B_TRANS_SEQ => open,
DEBUG_R_BEAT_CNT => open,
DEBUG_R_TRANS_SEQ => open,
DEBUG_AW_ISSUING_CNT => open,
DEBUG_AR_ISSUING_CNT => open,
DEBUG_W_BEAT_CNT => open,
DEBUG_W_TRANS_SEQ => open,
DEBUG_BID_TARGET => open,
DEBUG_BID_ERROR => open,
DEBUG_RID_TARGET => open,
DEBUG_RID_ERROR => open,
DEBUG_SR_SC_ARADDR => open,
DEBUG_SR_SC_ARADDRCONTROL => open,
DEBUG_SR_SC_AWADDR => open,
DEBUG_SR_SC_AWADDRCONTROL => open,
DEBUG_SR_SC_BRESP => open,
DEBUG_SR_SC_RDATA => open,
DEBUG_SR_SC_RDATACONTROL => open,
DEBUG_SR_SC_WDATA => open,
DEBUG_SR_SC_WDATACONTROL => open,
DEBUG_SC_SF_ARADDR => open,
DEBUG_SC_SF_ARADDRCONTROL => open,
DEBUG_SC_SF_AWADDR => open,
DEBUG_SC_SF_AWADDRCONTROL => open,
DEBUG_SC_SF_BRESP => open,
DEBUG_SC_SF_RDATA => open,
DEBUG_SC_SF_RDATACONTROL => open,
DEBUG_SC_SF_WDATA => open,
DEBUG_SC_SF_WDATACONTROL => open,
DEBUG_SF_CB_ARADDR => open,
DEBUG_SF_CB_ARADDRCONTROL => open,
DEBUG_SF_CB_AWADDR => open,
DEBUG_SF_CB_AWADDRCONTROL => open,
DEBUG_SF_CB_BRESP => open,
DEBUG_SF_CB_RDATA => open,
DEBUG_SF_CB_RDATACONTROL => open,
DEBUG_SF_CB_WDATA => open,
DEBUG_SF_CB_WDATACONTROL => open,
DEBUG_CB_MF_ARADDR => open,
DEBUG_CB_MF_ARADDRCONTROL => open,
DEBUG_CB_MF_AWADDR => open,
DEBUG_CB_MF_AWADDRCONTROL => open,
DEBUG_CB_MF_BRESP => open,
DEBUG_CB_MF_RDATA => open,
DEBUG_CB_MF_RDATACONTROL => open,
DEBUG_CB_MF_WDATA => open,
DEBUG_CB_MF_WDATACONTROL => open,
DEBUG_MF_MC_ARADDR => open,
DEBUG_MF_MC_ARADDRCONTROL => open,
DEBUG_MF_MC_AWADDR => open,
DEBUG_MF_MC_AWADDRCONTROL => open,
DEBUG_MF_MC_BRESP => open,
DEBUG_MF_MC_RDATA => open,
DEBUG_MF_MC_RDATACONTROL => open,
DEBUG_MF_MC_WDATA => open,
DEBUG_MF_MC_WDATACONTROL => open,
DEBUG_MC_MP_ARADDR => open,
DEBUG_MC_MP_ARADDRCONTROL => open,
DEBUG_MC_MP_AWADDR => open,
DEBUG_MC_MP_AWADDRCONTROL => open,
DEBUG_MC_MP_BRESP => open,
DEBUG_MC_MP_RDATA => open,
DEBUG_MC_MP_RDATACONTROL => open,
DEBUG_MC_MP_WDATA => open,
DEBUG_MC_MP_WDATACONTROL => open,
DEBUG_MP_MR_ARADDR => open,
DEBUG_MP_MR_ARADDRCONTROL => open,
DEBUG_MP_MR_AWADDR => open,
DEBUG_MP_MR_AWADDRCONTROL => open,
DEBUG_MP_MR_BRESP => open,
DEBUG_MP_MR_RDATA => open,
DEBUG_MP_MR_RDATACONTROL => open,
DEBUG_MP_MR_WDATA => open,
DEBUG_MP_MR_WDATACONTROL => open
);
conware_0 : system_conware_0_wrapper
port map (
ACLK => processing_system7_0_FCLK_CLK0(0),
ARESETN => processing_system7_0_FCLK_RESET0_N_0,
S_AXIS_TREADY => axi_dma_0_M_AXIS_MM2S_TREADY,
S_AXIS_TDATA => axi_dma_0_M_AXIS_MM2S_TDATA,
S_AXIS_TLAST => axi_dma_0_M_AXIS_MM2S_TLAST,
S_AXIS_TVALID => axi_dma_0_M_AXIS_MM2S_TVALID,
M_AXIS_TVALID => conware_0_M_AXIS_TVALID,
M_AXIS_TDATA => conware_0_M_AXIS_TDATA,
M_AXIS_TLAST => conware_0_M_AXIS_TLAST,
M_AXIS_TREADY => conware_0_M_AXIS_TREADY,
M_AXIS_TKEEP => conware_0_M_AXIS_TKEEP,
M_AXIS_TSTRB => open,
in_states => conware_0_in_states,
out_states => conware_0_out_states,
num_reads => conware_0_num_reads,
num_writes => conware_0_num_writes,
read_ctr => conware_0_read_ctr,
write_ctr => conware_0_write_ctr
);
cownare_ctl_0 : system_cownare_ctl_0_wrapper
port map (
S_AXI_ACLK => processing_system7_0_FCLK_CLK0(0),
S_AXI_ARESETN => axi4lite_0_M_ARESETN(3),
S_AXI_AWADDR => axi4lite_0_M_AWADDR(127 downto 96),
S_AXI_AWVALID => axi4lite_0_M_AWVALID(3),
S_AXI_WDATA => axi4lite_0_M_WDATA(127 downto 96),
S_AXI_WSTRB => axi4lite_0_M_WSTRB(15 downto 12),
S_AXI_WVALID => axi4lite_0_M_WVALID(3),
S_AXI_BREADY => axi4lite_0_M_BREADY(3),
S_AXI_ARADDR => axi4lite_0_M_ARADDR(127 downto 96),
S_AXI_ARVALID => axi4lite_0_M_ARVALID(3),
S_AXI_RREADY => axi4lite_0_M_RREADY(3),
S_AXI_ARREADY => axi4lite_0_M_ARREADY(3),
S_AXI_RDATA => axi4lite_0_M_RDATA(127 downto 96),
S_AXI_RRESP => axi4lite_0_M_RRESP(7 downto 6),
S_AXI_RVALID => axi4lite_0_M_RVALID(3),
S_AXI_WREADY => axi4lite_0_M_WREADY(3),
S_AXI_BRESP => axi4lite_0_M_BRESP(7 downto 6),
S_AXI_BVALID => axi4lite_0_M_BVALID(3),
S_AXI_AWREADY => axi4lite_0_M_AWREADY(3),
in_states => conware_0_in_states,
out_states => conware_0_out_states,
num_reads => conware_0_num_reads,
num_writes => conware_0_num_writes,
read_ctr => conware_0_read_ctr,
write_ctr => conware_0_write_ctr
);
iobuf_0 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(7),
IO => SWs_8Bits_TRI_IO(7),
O => SWs_8Bits_TRI_IO_I(7),
T => SWs_8Bits_TRI_IO_T(7)
);
iobuf_1 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(6),
IO => SWs_8Bits_TRI_IO(6),
O => SWs_8Bits_TRI_IO_I(6),
T => SWs_8Bits_TRI_IO_T(6)
);
iobuf_2 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(5),
IO => SWs_8Bits_TRI_IO(5),
O => SWs_8Bits_TRI_IO_I(5),
T => SWs_8Bits_TRI_IO_T(5)
);
iobuf_3 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(4),
IO => SWs_8Bits_TRI_IO(4),
O => SWs_8Bits_TRI_IO_I(4),
T => SWs_8Bits_TRI_IO_T(4)
);
iobuf_4 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(3),
IO => SWs_8Bits_TRI_IO(3),
O => SWs_8Bits_TRI_IO_I(3),
T => SWs_8Bits_TRI_IO_T(3)
);
iobuf_5 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(2),
IO => SWs_8Bits_TRI_IO(2),
O => SWs_8Bits_TRI_IO_I(2),
T => SWs_8Bits_TRI_IO_T(2)
);
iobuf_6 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(1),
IO => SWs_8Bits_TRI_IO(1),
O => SWs_8Bits_TRI_IO_I(1),
T => SWs_8Bits_TRI_IO_T(1)
);
iobuf_7 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(0),
IO => SWs_8Bits_TRI_IO(0),
O => SWs_8Bits_TRI_IO_I(0),
T => SWs_8Bits_TRI_IO_T(0)
);
iobuf_8 : IOBUF
port map (
I => BTNs_5Bits_TRI_IO_O(4),
IO => BTNs_5Bits_TRI_IO(4),
O => BTNs_5Bits_TRI_IO_I(4),
T => BTNs_5Bits_TRI_IO_T(4)
);
iobuf_9 : IOBUF
port map (
I => BTNs_5Bits_TRI_IO_O(3),
IO => BTNs_5Bits_TRI_IO(3),
O => BTNs_5Bits_TRI_IO_I(3),
T => BTNs_5Bits_TRI_IO_T(3)
);
iobuf_10 : IOBUF
port map (
I => BTNs_5Bits_TRI_IO_O(2),
IO => BTNs_5Bits_TRI_IO(2),
O => BTNs_5Bits_TRI_IO_I(2),
T => BTNs_5Bits_TRI_IO_T(2)
);
iobuf_11 : IOBUF
port map (
I => BTNs_5Bits_TRI_IO_O(1),
IO => BTNs_5Bits_TRI_IO(1),
O => BTNs_5Bits_TRI_IO_I(1),
T => BTNs_5Bits_TRI_IO_T(1)
);
iobuf_12 : IOBUF
port map (
I => BTNs_5Bits_TRI_IO_O(0),
IO => BTNs_5Bits_TRI_IO(0),
O => BTNs_5Bits_TRI_IO_I(0),
T => BTNs_5Bits_TRI_IO_T(0)
);
end architecture STRUCTURE;
|
mit
|
5842ac18e044f5a9ebbb551d214724eb
| 0.618155 | 2.81538 | false | false | false | false |
medav/conware
|
conware_test/system/hdl/system_axi_dma_0_wrapper.vhd
| 1 | 20,344 |
-------------------------------------------------------------------------------
-- system_axi_dma_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_dma_v6_03_a;
use axi_dma_v6_03_a.all;
entity system_axi_dma_0_wrapper is
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(9 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(9 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_awaddr : out std_logic_vector(31 downto 0);
m_axi_sg_awlen : out std_logic_vector(7 downto 0);
m_axi_sg_awsize : out std_logic_vector(2 downto 0);
m_axi_sg_awburst : out std_logic_vector(1 downto 0);
m_axi_sg_awprot : out std_logic_vector(2 downto 0);
m_axi_sg_awcache : out std_logic_vector(3 downto 0);
m_axi_sg_awuser : out std_logic_vector(3 downto 0);
m_axi_sg_awvalid : out std_logic;
m_axi_sg_awready : in std_logic;
m_axi_sg_wdata : out std_logic_vector(31 downto 0);
m_axi_sg_wstrb : out std_logic_vector(3 downto 0);
m_axi_sg_wlast : out std_logic;
m_axi_sg_wvalid : out std_logic;
m_axi_sg_wready : in std_logic;
m_axi_sg_bresp : in std_logic_vector(1 downto 0);
m_axi_sg_bvalid : in std_logic;
m_axi_sg_bready : out std_logic;
m_axi_sg_araddr : out std_logic_vector(31 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_aruser : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(31 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(31 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(3 downto 0);
m_axis_mm2s_tid : out std_logic_vector(4 downto 0);
m_axis_mm2s_tdest : out std_logic_vector(4 downto 0);
mm2s_cntrl_reset_out_n : out std_logic;
m_axis_mm2s_cntrl_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_cntrl_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_cntrl_tvalid : out std_logic;
m_axis_mm2s_cntrl_tready : in std_logic;
m_axis_mm2s_cntrl_tlast : out std_logic;
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(31 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(3 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(3 downto 0);
s_axis_s2mm_tid : in std_logic_vector(4 downto 0);
s_axis_s2mm_tdest : in std_logic_vector(4 downto 0);
s2mm_sts_reset_out_n : out std_logic;
s_axis_s2mm_sts_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_sts_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_sts_tvalid : in std_logic;
s_axis_s2mm_sts_tready : out std_logic;
s_axis_s2mm_sts_tlast : in std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_dma_tstvec : out std_logic_vector(31 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_axi_dma_0_wrapper : entity is "axi_dma_v6_03_a";
end system_axi_dma_0_wrapper;
architecture STRUCTURE of system_axi_dma_0_wrapper is
component axi_dma is
generic (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_INCLUDE_SG : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_SG_INCLUDE_DESC_QUEUE : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_FAMILY : STRING;
C_INSTANCE : STRING
);
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_awaddr : out std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_sg_awlen : out std_logic_vector(7 downto 0);
m_axi_sg_awsize : out std_logic_vector(2 downto 0);
m_axi_sg_awburst : out std_logic_vector(1 downto 0);
m_axi_sg_awprot : out std_logic_vector(2 downto 0);
m_axi_sg_awcache : out std_logic_vector(3 downto 0);
m_axi_sg_awuser : out std_logic_vector(3 downto 0);
m_axi_sg_awvalid : out std_logic;
m_axi_sg_awready : in std_logic;
m_axi_sg_wdata : out std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0);
m_axi_sg_wstrb : out std_logic_vector((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0);
m_axi_sg_wlast : out std_logic;
m_axi_sg_wvalid : out std_logic;
m_axi_sg_wready : in std_logic;
m_axi_sg_bresp : in std_logic_vector(1 downto 0);
m_axi_sg_bvalid : in std_logic;
m_axi_sg_bready : out std_logic;
m_axi_sg_araddr : out std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_aruser : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(3 downto 0);
m_axis_mm2s_tid : out std_logic_vector(4 downto 0);
m_axis_mm2s_tdest : out std_logic_vector(4 downto 0);
mm2s_cntrl_reset_out_n : out std_logic;
m_axis_mm2s_cntrl_tdata : out std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
m_axis_mm2s_cntrl_tkeep : out std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);
m_axis_mm2s_cntrl_tvalid : out std_logic;
m_axis_mm2s_cntrl_tready : in std_logic;
m_axis_mm2s_cntrl_tlast : out std_logic;
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(3 downto 0);
s_axis_s2mm_tid : in std_logic_vector(4 downto 0);
s_axis_s2mm_tdest : in std_logic_vector(4 downto 0);
s2mm_sts_reset_out_n : out std_logic;
s_axis_s2mm_sts_tdata : in std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0);
s_axis_s2mm_sts_tkeep : in std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0);
s_axis_s2mm_sts_tvalid : in std_logic;
s_axis_s2mm_sts_tready : out std_logic;
s_axis_s2mm_sts_tlast : in std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_dma_tstvec : out std_logic_vector(31 downto 0)
);
end component;
begin
axi_dma_0 : axi_dma
generic map (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_INCLUDE_SG => 1,
C_ENABLE_MULTI_CHANNEL => 0,
C_SG_INCLUDE_DESC_QUEUE => 1,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 1,
C_SG_LENGTH_WIDTH => 23,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_INCLUDE_MM2S_DRE => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_INCLUDE_S2MM_DRE => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_NUM_S2MM_CHANNELS => 1,
C_NUM_MM2S_CHANNELS => 1,
C_FAMILY => "zynq",
C_INSTANCE => "axi_dma_0"
)
port map (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => m_axi_sg_aclk,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awaddr => m_axi_sg_awaddr,
m_axi_sg_awlen => m_axi_sg_awlen,
m_axi_sg_awsize => m_axi_sg_awsize,
m_axi_sg_awburst => m_axi_sg_awburst,
m_axi_sg_awprot => m_axi_sg_awprot,
m_axi_sg_awcache => m_axi_sg_awcache,
m_axi_sg_awuser => m_axi_sg_awuser,
m_axi_sg_awvalid => m_axi_sg_awvalid,
m_axi_sg_awready => m_axi_sg_awready,
m_axi_sg_wdata => m_axi_sg_wdata,
m_axi_sg_wstrb => m_axi_sg_wstrb,
m_axi_sg_wlast => m_axi_sg_wlast,
m_axi_sg_wvalid => m_axi_sg_wvalid,
m_axi_sg_wready => m_axi_sg_wready,
m_axi_sg_bresp => m_axi_sg_bresp,
m_axi_sg_bvalid => m_axi_sg_bvalid,
m_axi_sg_bready => m_axi_sg_bready,
m_axi_sg_araddr => m_axi_sg_araddr,
m_axi_sg_arlen => m_axi_sg_arlen,
m_axi_sg_arsize => m_axi_sg_arsize,
m_axi_sg_arburst => m_axi_sg_arburst,
m_axi_sg_arprot => m_axi_sg_arprot,
m_axi_sg_arcache => m_axi_sg_arcache,
m_axi_sg_aruser => m_axi_sg_aruser,
m_axi_sg_arvalid => m_axi_sg_arvalid,
m_axi_sg_arready => m_axi_sg_arready,
m_axi_sg_rdata => m_axi_sg_rdata,
m_axi_sg_rresp => m_axi_sg_rresp,
m_axi_sg_rlast => m_axi_sg_rlast,
m_axi_sg_rvalid => m_axi_sg_rvalid,
m_axi_sg_rready => m_axi_sg_rready,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_aruser => m_axi_mm2s_aruser,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axis_mm2s_tid => m_axis_mm2s_tid,
m_axis_mm2s_tdest => m_axis_mm2s_tdest,
mm2s_cntrl_reset_out_n => mm2s_cntrl_reset_out_n,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awuser => m_axi_s2mm_awuser,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => s_axis_s2mm_tuser,
s_axis_s2mm_tid => s_axis_s2mm_tid,
s_axis_s2mm_tdest => s_axis_s2mm_tdest,
s2mm_sts_reset_out_n => s2mm_sts_reset_out_n,
s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata,
s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep,
s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid,
s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready,
s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast,
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
end architecture STRUCTURE;
|
mit
|
edeabbe29230a8f21c54d29de8eb4e76
| 0.622739 | 2.576494 | false | false | false | false |
thasti/dvbs
|
hdl/scrambler/scrambler.vhd
| 1 | 1,417 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- this unit introduces 1 cycle delay between d and q
entity scrambler is
generic (
width : positive := 8
);
port (
clk : in std_logic;
clk_en : in std_logic;
rst : in std_logic;
sync : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0)
);
end entity scrambler;
architecture rtl of scrambler is
signal prbs_rst : std_logic;
signal prbs : std_logic_vector(width-1 downto 0);
signal enable : std_logic;
signal invert : std_logic;
signal first_sync : std_logic;
signal cnt : unsigned(2 downto 0) := (others => '0');
begin
prbs15 : entity work.prbs
generic map(
n => 15,
width => width
)
port map (
clk => clk,
clk_en => clk_en,
rst => prbs_rst,
q => prbs,
def_val => "100101010000000"
);
prbs_rst <= rst or first_sync;
process
begin
wait until rising_edge(clk);
if rst = '1' then
cnt <= (others => '0');
elsif (clk_en = '1') and (sync = '1') then
cnt <= cnt + 1;
end if;
end process;
process
begin
wait until rising_edge(clk);
if rst = '1' then
q <= (others => '0');
elsif clk_en = '1' then
for i in 0 to width-1 loop
q(i) <= d(i) xor ((prbs(i) and enable) or invert);
end loop;
end if;
end process;
enable <= not sync;
first_sync <= sync when cnt = 0 else '0';
invert <= first_sync;
end architecture rtl;
|
gpl-2.0
|
9c696203edf24948099df7c8df09a6ae
| 0.62597 | 2.678639 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_3/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_3_tb.vhd
| 1 | 6,199 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_3_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pkg.ALL;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_3_tb IS
END ENTITY;
ARCHITECTURE system_axi_dma_0_wrapper_fifo_generator_v9_3_3_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_3_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_dma_0_wrapper_fifo_generator_v9_3_3_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_dma_0_wrapper_fifo_generator_v9_3_3_synth
system_axi_dma_0_wrapper_fifo_generator_v9_3_3_synth_inst:system_axi_dma_0_wrapper_fifo_generator_v9_3_3_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 41
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
mit
|
811a21ac20e4a49f22547ee254d66228
| 0.62623 | 4.007111 | false | false | false | false |
meninge/dauphin
|
test_bench/test_nnlayer.vhd
| 1 | 6,044 |
----------------------------------------------------------------
-- uut:
-- nnlayer.vhd
-- neuron.vhd
-- fsm.vhd
-- distribuf.vhd
-- description:
-- simple test_bench to verify nnlayer behavior in normal
-- operating conditions
-- expected result:
-- neurons should be configured in weight configuration mode
-- in normal mode, neurons should input accumulation of
-- data*weights
----------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;
use ieee.numeric_std.all;
-- entity declaration for your testbench.Dont declare any ports here
ENTITY test_nnlayer IS
END test_nnlayer;
ARCHITECTURE behavior OF test_nnlayer IS
-- add component under test
-- Parameters for the neurons
constant WDATA : natural := 16;
constant WWEIGHT : natural := 16;
constant WACCU : natural := 48;
-- Parameters for frame and number of neurons
constant FSIZE : natural := 784;
constant NBNEU : natural := 10;
component nnlayer is
generic (
-- Parameters for the neurons
WDATA : natural := WDATA;
WWEIGHT : natural := WWEIGHT;
WACCU : natural := WACCU;
-- Parameters for frame and number of neurons
FSIZE : natural := FSIZE;
NBNEU : natural := NBNEU
);
port (
clk : in std_logic;
clear : in std_logic;
-- Ports for Write Enable
write_mode : in std_logic;
write_data : in std_logic_vector(WWEIGHT-1 downto 0);
write_enable : in std_logic;
write_ready : out std_logic;
-- The user-specified frame size and number of neurons
user_fsize : in std_logic_vector(15 downto 0);
user_nbneu : in std_logic_vector(15 downto 0);
-- Data input, 2 bits
data_in : in std_logic_vector(WDATA-1 downto 0);
data_in_valid : in std_logic;
data_in_ready : out std_logic;
-- Scan chain to extract values
data_out : out std_logic_vector(WACCU-1 downto 0);
data_out_valid : out std_logic;
-- Indicate to the parent component that we are reaching the end of the current frame
end_of_frame : out std_logic;
-- The output data enters a FIFO. This indicates the available room.
out_fifo_room : in std_logic_vector(15 downto 0)
);
end component;
-- clock period definition
constant clk_period : time := 1 ns;
-- Control signals
signal clk : std_logic := '0';
signal clear : std_logic := '0';
-- Ports for Write Enable
signal write_mode : std_logic := '0';
signal write_data : std_logic_vector(WWEIGHT-1 downto 0);
signal write_enable : std_logic := '0';
signal write_ready : std_logic := '0';
-- The user-specified frame size and number of neurons
signal user_fsize : std_logic_vector(15 downto 0);
signal user_nbneu : std_logic_vector(15 downto 0);
signal data_in : std_logic_vector(WDATA-1 downto 0);
signal data_in_valid : std_logic := '0';
signal data_in_ready : std_logic := '0';
-- Scan chain to extract values
signal data_out : std_logic_vector(WACCU-1 downto 0);
signal data_out_valid : std_logic := '0';
-- Indicate to the parent component that we are reaching the end of the current frame
signal end_of_frame : std_logic := '0';
-- The output data enters a FIFO. This indicates the available room.
signal out_fifo_room : std_logic_vector(15 downto 0);
begin
-- Instantiate the Uni../recode.vhd:12:t Under Test (UUT)
uut: nnlayer
port map (
clk => clk,
clear => clear,
-- Ports for Write Enable
write_mode => write_mode,
write_data => write_data,
write_enable => write_enable,
write_ready => write_ready,
-- The user-specified frame size and number of neurons
user_fsize => user_fsize,
user_nbneu => user_nbneu,
-- Data input, 2 bits
data_in => data_in,
data_in_valid => data_in_valid,
data_in_ready => data_in_ready,
-- Scan chain to extract values
data_out => data_out,
data_out_valid => data_out_valid,
-- Indicate to the parent component that we are reaching the end of the current frame
end_of_frame => end_of_frame,
-- The output data enters a FIFO. This indicates the available room.
out_fifo_room => out_fifo_room
);
-- Clock process definitions( clock with 50% duty cycle is generated here.
clk_process : process
begin
clk <= '1';
wait for clk_period/2; --for 0.5 ns signal is '1'.
clk <= '0';
wait for clk_period/2; --for next 0.5 ns signal is '0'.
end process;
--spy_process : process
--begin
-- init_signal_spy("/test_nnlayer/uut/fsm_gen/sensor_we_mode","sensor_we_mode",1,-1);
--end process;
-- Stimulus process
out_fifo_room_proc : process
begin
wait for clk_period;
out_fifo_room <= X"0007";
wait for clk_period;
wait for clk_period;
out_fifo_room <= X"0002";
end process;
stim_proc: process
variable counter : integer := 0;
variable neurons : integer := 0;
begin
-------------------------------
-- TEST CHARGEMENT DES POIDS --
-------------------------------
-- reset
clear <= '1';
wait for 3*clk_period;
clear <= '0';
write_data <= X"0001";
write_mode <= '1'; -- load weights
data_in_valid <= '1'; -- data is in FIFO
write_enable<='1';
wait for 9 * clk_period;
write_mode <= '0'; -- accu add
data_in <= X"0001";
while neurons < NBNEU loop
counter := 0;
write_data <= std_logic_vector(to_unsigned((neurons) mod 2 +1, write_data'length));
while (counter < FSIZE) loop
wait for clk_period;
ASSERT ( data_in_ready = '1')
REPORT "data_in_ready != 1";
counter := counter + 1;
wait for clk_period;
end loop;
neurons := neurons +1;
wait for 10 * clk_period;
end loop;
----------------------------
-- TEST MODE ACCUMULATION --
----------------------------
write_data <= X"0000";
data_in_valid <= '1'; -- data is in FIFO
counter := 0;
while (counter < FSIZE) loop
wait for clk_period;
counter := counter + 1;
wait for clk_period;
end loop;
wait;
end process;
END;
|
mit
|
9468f960b51a1d684e804c4dd6357f6d
| 0.630046 | 3.270563 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_1/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_1_synth.vhd
| 1 | 11,105 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_1_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_1_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(7-1 DOWNTO 0);
SIGNAL wr_ack : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(39-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(39-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(39-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(39-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 50 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
fg_dg_nv: system_axi_dma_0_wrapper_fifo_generator_v9_3_1_dgen
GENERIC MAP (
C_DIN_WIDTH => 39,
C_DOUT_WIDTH => 39,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_dma_0_wrapper_fifo_generator_v9_3_1_dverif
GENERIC MAP (
C_DOUT_WIDTH => 39,
C_DIN_WIDTH => 39,
C_USE_EMBEDDED_REG => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 39,
C_DIN_WIDTH => 39,
C_WR_PNTR_WIDTH => 7,
C_RD_PNTR_WIDTH => 7,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_dma_0_wrapper_fifo_generator_v9_3_1_inst : system_axi_dma_0_wrapper_fifo_generator_v9_3_1_exdes
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
mit
|
b33312c51264b8502ca3da4b0c9aa29e
| 0.466997 | 4.045537 | false | false | false | false |
meninge/dauphin
|
recode_bram.vhd
| 1 | 5,370 |
-- This block recodes data on-the-fly
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity recode is
generic(
WDATA : natural := 32;
WWEIGHT : natural := 16;
WOUT : natural := 32;
FSIZE : natural := 200 -- warning, this is NB_NEU
);
port(
clk : in std_logic;
-- Ports for address control
addr_clear : in std_logic;
-- Ports for Write into memory
write_mode : in std_logic;
write_data : in std_logic_vector(WDATA - 1 downto 0);
write_enable : in std_logic;
write_ready : out std_logic; -- not used
-- The user-specified number of neurons
user_nbneu : in std_logic_vector(15 downto 0);
-- Data input
data_in : in std_logic_vector(WDATA-1 downto 0);
data_in_valid : in std_logic;
data_in_ready : out std_logic;
-- Data output
data_out : out std_logic_vector(WOUT-1 downto 0);
data_out_valid : out std_logic;
-- The output data enters a FIFO. This indicates the available room.
out_fifo_room : in std_logic_vector(15 downto 0)
);
end recode;
architecture synth of recode is
type STATE is (RESET, WRITE_INPUT, WRITE_WAIT, DATA);
signal current_state : STATE := RESET;
signal next_state : STATE := RESET;
-- table containing constants to add to incoming neuron data.
--type ram_t is array (0 to FSIZE-1) of std_logic_vector(WWEIGHT-1 downto 0);
--signal ram : ram_t := (others => (others => '0'));
signal addr : integer := 0;
signal next_addr : integer := 0;
-- output signals
signal out_write_ready : std_logic := '0';
signal out_data_in_ready : std_logic := '0';
signal out_data_out : std_logic_vector(WOUT-1 downto 0) := (others => '0');
signal out_data_out_valid : std_logic := '0';
signal cur_ram : std_logic_vector(WWEIGHT-1 downto 0);
signal config_written : boolean := false;
signal next_config_written : boolean := false;
component ram is
generic (
WDATA : natural := 16;
SIZE : natural := 784;
WADDR : natural := 10
);
port ( clk : in std_logic;
we : in std_logic;
en : in std_logic;
addr : in std_logic_vector(WADDR-1 downto 0);
di : in std_logic_vector(WDATA-1 downto 0);
do : out std_logic_vector(WDATA-1 downto 0));
end component;
signal we_ram : std_logic := '0';
begin
-------------------------------------------------------------------
-- instanciation of component
-------------------------------------------------------------------
i_ram: ram
generic map (
WDATA => WWEIGHT,
SIZE => FSIZE,
WADDR => 10
)
port map (
clk => clk,
we => we_ram,
en => '1',
addr => std_logic_vector(to_unsigned(addr, 10)),
di => write_data(WWEIGHT-1 downto 0),
do => cur_ram
);
-- Sequential process
process (clk)
begin
if rising_edge(clk) then
if (addr_clear = '1') then
current_state <= RESET;
else
current_state <= next_state;
addr <= next_addr;
end if;
config_written <= next_config_written;
if next_state = WRITE_INPUT then
we_ram <= '1';
else
we_ram <= '0';
end if;
end if;
end process;
-- Process combinatoire de la FSM
process (current_state, write_mode, write_enable, addr, out_fifo_room, data_in_valid, write_data, cur_ram, data_in)
begin
out_write_ready <= '0';
out_data_out <= (others => '0');
out_data_out_valid <= '0';
out_data_in_ready <= '0';
next_state <= RESET;
next_addr <= 0;
if (config_written = false) then
next_config_written <= false;
else
next_config_written <= true;
end if;
case current_state is
when RESET =>
next_addr <= 0;
if (write_mode = '1' and write_enable = '1') then
if (not(config_written)) then
next_state <= WRITE_INPUT;
end if;
elsif (write_mode = '0' and data_in_valid = '1') then
next_state <= DATA;
else
next_state <= RESET;
end if;
when WRITE_INPUT =>
next_config_written <= true;
out_write_ready <= '1';
next_addr <= addr + 1;
if (addr = FSIZE - 1) then
next_state <= RESET;
next_addr <= 0;
elsif (write_enable = '1') then
next_state <= WRITE_INPUT;
else
next_state <= WRITE_WAIT;
end if;
when WRITE_WAIT =>
next_addr <= addr;
if (write_enable = '1') then
next_state <= WRITE_INPUT;
else
next_state <= WRITE_WAIT;
end if;
when DATA =>
if ( unsigned(out_fifo_room) > 0 and data_in_valid = '1') then
if (signed(data_in) + signed(cur_ram) > 0) then
out_data_out <= std_logic_vector(signed(data_in) + signed(cur_ram));
else
out_data_out <= (others => '0');
end if;
out_data_out_valid <= '1';
out_data_in_ready <= '1';
next_addr <= addr + 1;
if (addr = FSIZE-1) then
next_config_written <= false;
next_state <= RESET;
next_addr <= 0;
else
next_state <= DATA;
end if;
else
next_state <= DATA;
end if;
when others =>
end case;
end process;
-- write_ready <= '1';
-- data_in_ready <= '1' when unsigned(out_fifo_room) > 0 else '0';
-- data_out <= std_logic_vector(resize(signed(data_in), WOUT));
-- data_out_valid <= data_in_valid;
write_ready <= out_write_ready;
data_in_ready <= out_data_in_ready;
data_out <= out_data_out;
data_out_valid <= out_data_out_valid;
end architecture;
|
mit
|
49cf4e107ab388e67647331c16ca3b60
| 0.580261 | 2.983333 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_rng.vhd
| 1 | 4,028 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
mit
|
ddeace91d6a975a4586501c2f52ff304
| 0.643992 | 4.266949 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_control_1.0/control.vhd
| 1 | 3,137 |
----------------------------------------------------
-- Vladi & Adi --
-- TAU EE Senior year project --
-- --
--************************************************--
--*************** User Interface *****************--
--************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity control is
Port ( Switches : in STD_LOGIC_VECTOR (0 to 7); --left to right
clk_12hz : in std_logic;
clk_1hz5 : in std_logic;
Leds : out STD_LOGIC_VECTOR (0 to 7) := "10000000"; --left to right
butn_in : in STD_LOGIC_VECTOR (0 to 2); -- left to right- L,C,R
en : out STD_LOGIC_VECTOR (0 to 3):= "0000";
options0 : out STD_LOGIC_VECTOR (0 to 3);
options1 : out STD_LOGIC_VECTOR (0 to 3);
options2 : out STD_LOGIC_VECTOR (0 to 3);
options3 : out STD_LOGIC_VECTOR (0 to 3)
);
end control;
architecture Behavioral of control is
signal ok : std_logic := '0';
signal butn_i : STD_LOGIC_VECTOR (0 to 2);
signal sele : integer :=0;
begin
butn_i <= butn_in;
ena:process(Switches) --enable
begin
if Switches(0)='1' then En(0) <= '1'; end if;
if Switches(0)='0' then En(0) <= '0'; end if;
if Switches(1)='1' then En(1) <= '1'; end if;
if Switches(1)='0' then En(1) <= '0'; end if;
if Switches(2)='1' then En(2) <= '1'; end if;
if Switches(2)='0' then En(2) <= '0'; end if;
if Switches(3)='1' then En(3) <= '1'; end if;
if Switches(3)='0' then En(3) <= '0'; end if;
end process;
sele_p:process(clk_12hz) --scroll between effects
begin
if rising_edge(clk_12hz) then
if (ok = '0') then
if (sele=0 and butn_i="001") then sele <= 1; end if;
if (sele=1 and butn_i="100") then sele <= 0; end if;
if (sele=1 and butn_i="001") then sele <= 2; end if;
if (sele=2 and butn_i="100") then sele <= 1; end if;
if (sele=2 and butn_i="001") then sele <= 3; end if;
if (sele=3 and butn_i="100") then sele <= 2; end if;
end if;
end if;
end process;
process(clk_12hz, sele,butn_i) --scroll between effects
begin
if (ok = '0') then --buttons L,R control effect selection
if (sele=0) then Leds <= "10000000"; end if;
if (sele=1) then Leds <= "01000000"; end if;
if (sele=2) then Leds <= "00100000"; end if;
if (sele=3) then Leds <= "00010000"; end if;
end if;
end process;
process(clk_12hz, sele, butn_i) -- change effect parameters
begin
if (ok = '1') then --buttons L,R control selected effect
if (sele=0) then options0 <= Switches(4 to 7); end if;
if (sele=1) then options1 <= Switches(4 to 7); end if;
if (sele=2) then options2 <= Switches(4 to 7); end if;
if (sele=3) then options3 <= Switches(4 to 7); end if;
end if;
end process;
o:process(butn_i, clk_1hz5)
begin
if rising_edge(clk_1hz5) then
if butn_i="010" then
if (ok='0') then
ok <= '1'; --control effect itself
end if;
if (ok='1') then
ok <= '0'; --control effect selection
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
8cc61479df419d1e06fdaf0ccbe908c3
| 0.541281 | 3.048591 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5/example_design/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_exdes.vhd
| 1 | 21,095 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_exdes is
PORT (
S_ARESETN : IN std_logic;
M_AXI_AWID : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(64/8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
S_AXI_AWID : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(64/8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
M_AXI_ARID : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
S_AXI_ARID : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
AXI_AW_PROG_FULL : OUT std_logic;
AXI_AW_PROG_EMPTY : OUT std_logic;
AXI_W_PROG_FULL : OUT std_logic;
AXI_W_PROG_EMPTY : OUT std_logic;
AXI_B_PROG_FULL : OUT std_logic;
AXI_B_PROG_EMPTY : OUT std_logic;
AXI_AR_PROG_FULL : OUT std_logic;
AXI_AR_PROG_EMPTY : OUT std_logic;
AXI_R_PROG_FULL : OUT std_logic;
AXI_R_PROG_EMPTY : OUT std_logic;
S_ACLK : IN std_logic);
end system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_exdes;
architecture xilinx of system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_exdes is
signal s_aclk_i : std_logic;
component system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5 is
PORT (
S_ARESETN : IN std_logic;
M_AXI_AWID : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(64/8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
S_AXI_AWID : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(64/8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
M_AXI_ARID : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
S_AXI_ARID : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
AXI_AW_PROG_FULL : OUT std_logic;
AXI_AW_PROG_EMPTY : OUT std_logic;
AXI_W_PROG_FULL : OUT std_logic;
AXI_W_PROG_EMPTY : OUT std_logic;
AXI_B_PROG_FULL : OUT std_logic;
AXI_B_PROG_EMPTY : OUT std_logic;
AXI_AR_PROG_FULL : OUT std_logic;
AXI_AR_PROG_EMPTY : OUT std_logic;
AXI_R_PROG_FULL : OUT std_logic;
AXI_R_PROG_EMPTY : OUT std_logic;
S_ACLK : IN std_logic);
end component;
begin
s_aclk_buf: bufg
PORT map(
i => S_ACLK,
o => s_aclk_i
);
exdes_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5
PORT MAP (
S_ARESETN => s_aresetn,
M_AXI_AWID => m_axi_awid,
M_AXI_AWADDR => m_axi_awaddr,
M_AXI_AWLEN => m_axi_awlen,
M_AXI_AWSIZE => m_axi_awsize,
M_AXI_AWBURST => m_axi_awburst,
M_AXI_AWLOCK => m_axi_awlock,
M_AXI_AWCACHE => m_axi_awcache,
M_AXI_AWPROT => m_axi_awprot,
M_AXI_AWQOS => m_axi_awqos,
M_AXI_AWREGION => m_axi_awregion,
M_AXI_AWVALID => m_axi_awvalid,
M_AXI_AWREADY => m_axi_awready,
M_AXI_WID => m_axi_wid,
M_AXI_WDATA => m_axi_wdata,
M_AXI_WSTRB => m_axi_wstrb,
M_AXI_WLAST => m_axi_wlast,
M_AXI_WVALID => m_axi_wvalid,
M_AXI_WREADY => m_axi_wready,
M_AXI_BID => m_axi_bid,
M_AXI_BRESP => m_axi_bresp,
M_AXI_BVALID => m_axi_bvalid,
M_AXI_BREADY => m_axi_bready,
S_AXI_AWID => s_axi_awid,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWLEN => s_axi_awlen,
S_AXI_AWSIZE => s_axi_awsize,
S_AXI_AWBURST => s_axi_awburst,
S_AXI_AWLOCK => s_axi_awlock,
S_AXI_AWCACHE => s_axi_awcache,
S_AXI_AWPROT => s_axi_awprot,
S_AXI_AWQOS => s_axi_awqos,
S_AXI_AWREGION => s_axi_awregion,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WID => s_axi_wid,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WLAST => s_axi_wlast,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BID => s_axi_bid,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
M_AXI_ARID => m_axi_arid,
M_AXI_ARADDR => m_axi_araddr,
M_AXI_ARLEN => m_axi_arlen,
M_AXI_ARSIZE => m_axi_arsize,
M_AXI_ARBURST => m_axi_arburst,
M_AXI_ARLOCK => m_axi_arlock,
M_AXI_ARCACHE => m_axi_arcache,
M_AXI_ARPROT => m_axi_arprot,
M_AXI_ARQOS => m_axi_arqos,
M_AXI_ARREGION => m_axi_arregion,
M_AXI_ARVALID => m_axi_arvalid,
M_AXI_ARREADY => m_axi_arready,
M_AXI_RID => m_axi_rid,
M_AXI_RDATA => m_axi_rdata,
M_AXI_RRESP => m_axi_rresp,
M_AXI_RLAST => m_axi_rlast,
M_AXI_RVALID => m_axi_rvalid,
M_AXI_RREADY => m_axi_rready,
S_AXI_ARID => s_axi_arid,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARLEN => s_axi_arlen,
S_AXI_ARSIZE => s_axi_arsize,
S_AXI_ARBURST => s_axi_arburst,
S_AXI_ARLOCK => s_axi_arlock,
S_AXI_ARCACHE => s_axi_arcache,
S_AXI_ARPROT => s_axi_arprot,
S_AXI_ARQOS => s_axi_arqos,
S_AXI_ARREGION => s_axi_arregion,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RID => s_axi_rid,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RLAST => s_axi_rlast,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
AXI_AW_PROG_FULL => axi_aw_prog_full,
AXI_AW_PROG_EMPTY => axi_aw_prog_empty,
AXI_W_PROG_FULL => axi_w_prog_full,
AXI_W_PROG_EMPTY => axi_w_prog_empty,
AXI_B_PROG_FULL => axi_b_prog_full,
AXI_B_PROG_EMPTY => axi_b_prog_empty,
AXI_AR_PROG_FULL => axi_ar_prog_full,
AXI_AR_PROG_EMPTY => axi_ar_prog_empty,
AXI_R_PROG_FULL => axi_r_prog_full,
AXI_R_PROG_EMPTY => axi_r_prog_empty,
S_ACLK => s_aclk_i);
end xilinx;
|
mit
|
df17f3b55748e07543fd066b7f2b8d6e
| 0.461342 | 3.798847 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_PS_to_PL_1.0/hdl/PS_to_PL_v1_0_S00_AXI.vhd
| 1 | 15,511 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PS_to_PL_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
AUDIO_OUT_FROM_AXI_TO_EFFECT : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); --VL
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end PS_to_PL_v1_0_S00_AXI;
architecture arch_imp of PS_to_PL_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 4
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00" =>
reg_data_out <= slv_reg0;
when b"01" =>
reg_data_out <= slv_reg1;
when b"10" =>
reg_data_out <= slv_reg2;
when b"11" =>
reg_data_out <= slv_reg3;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
AUDIO_OUT_FROM_AXI_TO_EFFECT <= slv_reg0; --vl
-- User logic ends
end arch_imp;
|
mit
|
111e4f359b550112150e5e5b4d56f4b1
| 0.602411 | 3.511659 | false | false | false | false |
thasti/dvbs
|
hdl/network/rmii_tx/rmii_tx_tb.vhd
| 1 | 748 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rmii_tx_tb is
end rmii_tx_tb;
architecture behav of rmii_tx_tb is
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal txd : std_logic_vector(1 downto 0) := "00";
signal txen : std_logic := '0';
signal start_tx : std_logic := '0';
signal d_in : std_logic_vector(7 downto 0) := (others => '0');
begin
dut : entity work.rmii_tx port map(clk, rst, txd, txen, start_tx, d_in);
rst <= '1', '0' after 100 ns;
clk <= not clk after 10 ns;
tx_test : process
begin
wait until falling_edge(rst);
wait until rising_edge(clk);
d_in <= x"5a";
start_tx <= '1';
wait until rising_edge(clk);
d_in <= x"a5";
wait;
end process;
end behav;
|
gpl-2.0
|
0143a1e52b11425c9ddb06f75a2b1af2
| 0.629679 | 2.544218 | false | false | false | false |
medav/conware
|
conware_test/system/hdl/system_stub.vhd
| 1 | 5,918 |
-------------------------------------------------------------------------------
-- system_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_stub is
port (
SWs_8Bits_TRI_IO : inout std_logic_vector(7 downto 0);
BTNs_5Bits_TRI_IO : inout std_logic_vector(4 downto 0);
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB : in std_logic;
processing_system7_0_PS_CLK : in std_logic;
processing_system7_0_PS_PORB : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
conware_0_M_AXIS_TVALID_pin : out std_logic;
conware_0_M_AXIS_TLAST_pin : out std_logic;
conware_0_M_AXIS_TREADY_pin : out std_logic;
conware_0_M_AXIS_TKEEP_pin : out std_logic_vector(3 downto 0);
conware_0_ACLK_pin : out std_logic;
cownare_ctl_0_in_states_pin : out std_logic_vector(7 downto 0)
);
end system_stub;
architecture STRUCTURE of system_stub is
component system is
port (
SWs_8Bits_TRI_IO : inout std_logic_vector(7 downto 0);
BTNs_5Bits_TRI_IO : inout std_logic_vector(4 downto 0);
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB : in std_logic;
processing_system7_0_PS_CLK : in std_logic;
processing_system7_0_PS_PORB : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
conware_0_M_AXIS_TVALID_pin : out std_logic;
conware_0_M_AXIS_TLAST_pin : out std_logic;
conware_0_M_AXIS_TREADY_pin : out std_logic;
conware_0_M_AXIS_TKEEP_pin : out std_logic_vector(3 downto 0);
conware_0_ACLK_pin : out std_logic;
cownare_ctl_0_in_states_pin : out std_logic_vector(7 downto 0)
);
end component;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system : component is "user_black_box";
begin
system_i : system
port map (
SWs_8Bits_TRI_IO => SWs_8Bits_TRI_IO,
BTNs_5Bits_TRI_IO => BTNs_5Bits_TRI_IO,
processing_system7_0_MIO => processing_system7_0_MIO,
processing_system7_0_PS_SRSTB => processing_system7_0_PS_SRSTB,
processing_system7_0_PS_CLK => processing_system7_0_PS_CLK,
processing_system7_0_PS_PORB => processing_system7_0_PS_PORB,
processing_system7_0_DDR_Clk => processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n => processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE => processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n => processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n => processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n => processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr => processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT => processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB => processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ => processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM => processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS => processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n => processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN => processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP => processing_system7_0_DDR_VRP,
conware_0_M_AXIS_TVALID_pin => conware_0_M_AXIS_TVALID_pin,
conware_0_M_AXIS_TLAST_pin => conware_0_M_AXIS_TLAST_pin,
conware_0_M_AXIS_TREADY_pin => conware_0_M_AXIS_TREADY_pin,
conware_0_M_AXIS_TKEEP_pin => conware_0_M_AXIS_TKEEP_pin,
conware_0_ACLK_pin => conware_0_ACLK_pin,
cownare_ctl_0_in_states_pin => cownare_ctl_0_in_states_pin
);
end architecture STRUCTURE;
|
mit
|
b5e8d882bfe740bc3f88c14a999dd2f9
| 0.672693 | 3.047374 | false | false | false | false |
medav/conware
|
conware_final/system/hdl/system_axi_vdma_0_wrapper.vhd
| 1 | 17,773 |
-------------------------------------------------------------------------------
-- system_axi_vdma_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_vdma_v5_04_a;
use axi_vdma_v5_04_a.all;
entity system_axi_vdma_0_wrapper is
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(8 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(8 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(31 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(31 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(31 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(0 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(31 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(3 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(0 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector(5 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector(5 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_axi_vdma_0_wrapper : entity is "axi_vdma_v5_04_a";
end system_axi_vdma_0_wrapper;
architecture STRUCTURE of system_axi_vdma_0_wrapper is
component axi_vdma is
generic (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_INCLUDE_SG : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_FAMILY : STRING;
C_INSTANCE : STRING
);
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(C_M_AXIS_MM2S_TUSER_BITS-1 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(C_S_AXIS_S2MM_TUSER_BITS-1 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector((C_MM2S_GENLOCK_NUM_MASTERS*6)-1 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector((C_S2MM_GENLOCK_NUM_MASTERS*6)-1 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
end component;
begin
axi_vdma_0 : axi_vdma
generic map (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 0,
C_FLUSH_ON_FSYNC => 1,
C_DYNAMIC_RESOLUTION => 1,
C_INCLUDE_SG => 0,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_ENABLE_VIDPRMTR_READS => 1,
C_INCLUDE_MM2S => 1,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_SOF_ENABLE => 1,
C_MM2S_MAX_BURST_LENGTH => 16,
C_MM2S_GENLOCK_MODE => 0,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_LINEBUFFER_DEPTH => 128,
C_MM2S_LINEBUFFER_THRESH => 4,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 0,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_SOF_ENABLE => 1,
C_S2MM_MAX_BURST_LENGTH => 16,
C_S2MM_GENLOCK_MODE => 0,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_LINEBUFFER_DEPTH => 128,
C_S2MM_LINEBUFFER_THRESH => 4,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_FAMILY => "zynq",
C_INSTANCE => "axi_vdma_0"
)
port map (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => m_axi_sg_aclk,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
s_axis_s2mm_aclk => s_axis_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_araddr => m_axi_sg_araddr,
m_axi_sg_arlen => m_axi_sg_arlen,
m_axi_sg_arsize => m_axi_sg_arsize,
m_axi_sg_arburst => m_axi_sg_arburst,
m_axi_sg_arprot => m_axi_sg_arprot,
m_axi_sg_arcache => m_axi_sg_arcache,
m_axi_sg_arvalid => m_axi_sg_arvalid,
m_axi_sg_arready => m_axi_sg_arready,
m_axi_sg_rdata => m_axi_sg_rdata,
m_axi_sg_rresp => m_axi_sg_rresp,
m_axi_sg_rlast => m_axi_sg_rlast,
m_axi_sg_rvalid => m_axi_sg_rvalid,
m_axi_sg_rready => m_axi_sg_rready,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => s_axis_s2mm_tuser,
mm2s_fsync => mm2s_fsync,
mm2s_frame_ptr_in => mm2s_frame_ptr_in,
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
mm2s_fsync_out => mm2s_fsync_out,
mm2s_prmtr_update => mm2s_prmtr_update,
mm2s_buffer_empty => mm2s_buffer_empty,
mm2s_buffer_almost_empty => mm2s_buffer_almost_empty,
s2mm_fsync => s2mm_fsync,
s2mm_frame_ptr_in => s2mm_frame_ptr_in,
s2mm_frame_ptr_out => s2mm_frame_ptr_out,
s2mm_fsync_out => s2mm_fsync_out,
s2mm_buffer_full => s2mm_buffer_full,
s2mm_buffer_almost_full => s2mm_buffer_almost_full,
s2mm_prmtr_update => s2mm_prmtr_update,
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_vdma_tstvec => axi_vdma_tstvec
);
end architecture STRUCTURE;
|
mit
|
46e15586d0b1f62acbfb77c6f7098c86
| 0.620492 | 2.604484 | false | false | false | false |
ciroceissler/sva_example
|
dut/FSM5.vhd
| 1 | 2,209 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:04:25 05/29/2014
-- Design Name:
-- Module Name: FSM1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FSM5 is
Port (
reset : in std_logic;
clk : in std_logic;
start: in std_logic;
data_in : in std_logic_vector(3 downto 0);
AVAIL : out std_logic;
DONE : out std_logic;
flag : out std_logic_vector(1 downto 0));
end FSM5;
architecture Behavioral of FSM5 is
type tipoestado is (s0, s1, s2, s3, s4, s5, s6);
signal estado : tipoestado;
begin
process(reset, clk)
variable regd : std_logic_vector(3 downto 0);
variable cont : std_logic_vector(6 downto 0);
begin
if reset = '1' then
estado <= s0;
AVAIL <= '1'; done <= '0'; flag <= "00"; regd := "0000"; cont := "0000000";
elsif (clk'event and clk='1') then
CASE estado IS
WHEN s0 =>
AVAIL <= '1'; done <= '0'; flag <= "00"; regd := "0000"; cont := "0000000"; if start='0'then estado
<= s0; else estado <= s1; end if;
WHEN s1 =>
AVAIL <= '0'; done <= '0'; flag <= "00"; regd := data_in; cont := cont+1;
if (regd = "1011" and cont <= "1100100") then estado <= s2;
elsif cont="1100100" then estado <= s4;
else estado <= s1;
end if;
WHEN s2 => -- achou um valor em <=100
AVAIL <= '0'; done <= '1'; flag <= "01"; estado <= s3;
WHEN s3 =>
AVAIL <= '0'; done <= '1'; flag <= "01"; estado <= s0;
WHEN s4 => -- nao achou valor ate 100 dados
AVAIL <= '0'; done <= '1'; flag <= "00"; estado <= s5;
WHEN s5 =>
AVAIL <= '0'; done <= '1'; flag <= "00"; estado <= s0;
WHEN others =>
AVAIL <= '1'; done <= '0'; flag <= "00"; estado <= s0;
end CASE;
end if;
end process;
end Behavioral;
|
apache-2.0
|
7b614dec021db1a239014d714c03011a
| 0.507922 | 3.306886 | false | false | false | false |
meninge/dauphin
|
recode.vhd
| 1 | 5,423 |
-- This block recodes data on-the-fly
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity recode is
generic(
WDATA : natural := 32;
WWEIGHT : natural := 16;
WOUT : natural := 32;
FSIZE : natural := 200 -- warning, this is NB_NEU
);
port(
clk : in std_logic;
-- Ports for address control
addr_clear : in std_logic;
-- Ports for Write into memory
write_mode : in std_logic;
write_data : in std_logic_vector(WDATA - 1 downto 0);
write_enable : in std_logic;
write_ready : out std_logic; -- not used
-- The user-specified number of neurons
user_nbneu : in std_logic_vector(15 downto 0);
-- Data input
data_in : in std_logic_vector(WDATA-1 downto 0);
data_in_valid : in std_logic;
data_in_ready : out std_logic;
-- Data output
data_out : out std_logic_vector(WOUT-1 downto 0);
data_out_valid : out std_logic;
-- The output data enters a FIFO. This indicates the available room.
out_fifo_room : in std_logic_vector(15 downto 0)
);
end recode;
architecture synth of recode is
type STATE is (RESET, WRITE_INPUT, WRITE_WAIT, DATA);
signal current_state : STATE := RESET;
signal next_state : STATE := RESET;
-- table containing constants to add to incoming neuron data.
type ram_t is array (0 to FSIZE-1) of std_logic_vector(WWEIGHT-1 downto 0);
signal ram : ram_t := (others => (others => '0'));
signal addr : integer := 0;
signal next_addr : integer := 0;
-- input signal
signal write_data_in : std_logic_vector(WDATA - 1 downto 0);
signal out_fifo_room_in : std_logic_vector(15 downto 0);
signal data_in_valid_in : std_logic;
signal data_in_in : std_logic_vector(WDATA-1 downto 0);
signal write_enable_in : std_logic;
signal write_mode_in : std_logic;
-- output signals
signal out_write_ready : std_logic := '0';
signal out_data_in_ready : std_logic := '0';
signal out_data_out : std_logic_vector(WOUT-1 downto 0) := (others => '0');
signal out_data_out_valid : std_logic := '0';
signal cur_ram : std_logic_vector(WWEIGHT-1 downto 0);
signal config_written : boolean := false;
signal next_config_written : boolean := false;
begin
---------------------------------------------
----------- Sequential processes ------------
---------------------------------------------
process (clk)
begin
if rising_edge(clk) then
if (addr_clear = '1') then
current_state <= RESET;
addr <= 0;
else
-- update the the ram
if (next_state = WRITE_INPUT) then
ram(next_addr) <= std_logic_vector(resize(signed(write_data_in), WWEIGHT));
end if;
current_state <= next_state;
addr <= next_addr;
config_written <= next_config_written;
cur_ram <= ram(next_addr);
end if;
end if;
end process;
---------------------------------------------
--------- Combinatorial processes -----------
---------------------------------------------
-- Process combinatoire de la FSM
process (current_state, write_mode_in, write_enable_in, addr, out_fifo_room_in, data_in_valid_in, cur_ram, data_in_in, config_written)
begin
out_write_ready <= '0';
out_data_out <= (others => '0');
out_data_out_valid <= '0';
out_data_in_ready <= '0';
next_state <= RESET;
next_config_written <= config_written;
case current_state is
when RESET =>
next_addr <= 0;
if (write_mode_in = '1' and write_enable_in = '1') then
if (not(config_written)) then
next_state <= WRITE_INPUT;
out_write_ready <= '1';
end if;
elsif (write_mode_in = '0' and data_in_valid_in = '1') then
next_state <= DATA;
else
next_state <= RESET;
end if;
when WRITE_INPUT =>
next_config_written <= true;
next_addr <= addr + 1;
if (addr = FSIZE - 1) then
next_state <= RESET;
next_addr <= 0;
elsif (write_enable_in = '1') then
next_state <= WRITE_INPUT;
out_write_ready <= '1';
else
next_state <= WRITE_WAIT;
end if;
when WRITE_WAIT =>
next_addr <= addr;
if (write_enable_in = '1') then
next_state <= WRITE_INPUT;
out_write_ready <= '1';
else
next_state <= WRITE_WAIT;
end if;
when DATA =>
next_addr <= addr;
if ( unsigned(out_fifo_room_in) > 0 and data_in_valid_in = '1') then
if (signed(data_in_in) + signed(cur_ram) > 0) then
out_data_out <= std_logic_vector(signed(data_in_in) + signed(cur_ram));
else
out_data_out <= (others => '0');
end if;
out_data_out_valid <= '1';
out_data_in_ready <= '1';
next_addr <= addr + 1;
if (addr = FSIZE - 1) then
next_config_written <= false;
next_state <= RESET;
next_addr <= 0;
else
next_state <= DATA;
end if;
else
next_state <= DATA;
end if;
when others =>
end case;
end process;
---------------------------------------------
----------- Ports assignements --------------
---------------------------------------------
write_ready <= out_write_ready;
data_in_ready <= out_data_in_ready;
data_out <= out_data_out;
data_out_valid <= out_data_out_valid;
-- input signal
write_data_in <= write_data;
out_fifo_room_in <= out_fifo_room;
data_in_valid_in <= data_in_valid;
data_in_in <= data_in;
write_enable_in <= write_enable;
write_mode_in <= write_mode;
end architecture;
|
mit
|
06e920254d7b54035b99b2d2b7c68b80
| 0.570902 | 3.097087 | false | true | false | false |
thasti/dvbs
|
hdl/network/rmii_rx/rmii_rx_tb.vhd
| 1 | 1,353 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rmii_rx_tb is
end rmii_rx_tb;
architecture behav of rmii_rx_tb is
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal rxd : std_logic_vector(1 downto 0) := "00";
signal crsdv : std_logic := '0';
signal rx_dv : std_logic := '0';
signal rx_byte : std_logic_vector(7 downto 0) := (others => '0');
signal rx_crs : std_logic := '0';
begin
dut : entity work.rmii_rx port map(clk, rst, rxd, crsdv, rx_byte, rx_dv, rx_crs);
rst <= '1', '0' after 100 ns;
clk <= not clk after 10 ns;
rx_test : process
begin
wait until falling_edge(rst);
wait until rising_edge(clk);
wait until rising_edge(clk);
crsdv <= '1';
rxd <= "01";
for i in 0 to 10 loop
wait until rising_edge(clk);
end loop;
rxd <= "11";
for i in 0 to 13 loop
wait until rising_edge(clk);
rxd <= std_logic_vector(to_unsigned(i mod 4,2));
wait until rising_edge(clk);
rxd <= std_logic_vector(to_unsigned(i mod 4,2));
end loop;
for i in 0 to 1 loop
wait until rising_edge(clk);
rxd <= not std_logic_vector(to_unsigned(i mod 4,2));
crsdv <= '0';
wait until rising_edge(clk);
rxd <= not std_logic_vector(to_unsigned(i mod 4,2));
crsdv <= '1';
end loop;
wait until rising_edge(clk);
crsdv <= '0';
wait;
end process;
end behav;
|
gpl-2.0
|
619a7c02ddecb2b75b5fd3161a281395
| 0.626016 | 2.663386 | false | false | false | false |
medav/conware
|
conware_final/system/hdl/system.vhd
| 1 | 150,873 |
-------------------------------------------------------------------------------
-- system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
SWs_8Bits_TRI_IO : inout std_logic_vector(7 downto 0);
LEDs_8Bits_TRI_IO : out std_logic_vector(7 downto 0);
BTNs_5Bits_TRI_IO : inout std_logic_vector(4 downto 0);
v_axi4s_vid_out_0_video_vsync_pin : out std_logic;
v_axi4s_vid_out_0_video_hsync_pin : out std_logic;
v_axi4s_vid_out_0_video_data_pin : out std_logic_vector(31 downto 0);
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic
);
end system;
architecture STRUCTURE of system is
component system_axi4lite_0_wrapper is
port (
INTERCONNECT_ACLK : in std_logic;
INTERCONNECT_ARESETN : in std_logic;
S_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
M_AXI_ARESET_OUT_N : out std_logic_vector(5 downto 0);
IRQ : out std_logic;
S_AXI_ACLK : in std_logic_vector(0 to 0);
S_AXI_AWID : in std_logic_vector(11 downto 0);
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_AWUSER : in std_logic_vector(0 to 0);
S_AXI_AWVALID : in std_logic_vector(0 to 0);
S_AXI_AWREADY : out std_logic_vector(0 to 0);
S_AXI_WID : in std_logic_vector(11 downto 0);
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WLAST : in std_logic_vector(0 to 0);
S_AXI_WUSER : in std_logic_vector(0 to 0);
S_AXI_WVALID : in std_logic_vector(0 to 0);
S_AXI_WREADY : out std_logic_vector(0 to 0);
S_AXI_BID : out std_logic_vector(11 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BUSER : out std_logic_vector(0 to 0);
S_AXI_BVALID : out std_logic_vector(0 to 0);
S_AXI_BREADY : in std_logic_vector(0 to 0);
S_AXI_ARID : in std_logic_vector(11 downto 0);
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ARUSER : in std_logic_vector(0 to 0);
S_AXI_ARVALID : in std_logic_vector(0 to 0);
S_AXI_ARREADY : out std_logic_vector(0 to 0);
S_AXI_RID : out std_logic_vector(11 downto 0);
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic_vector(0 to 0);
S_AXI_RUSER : out std_logic_vector(0 to 0);
S_AXI_RVALID : out std_logic_vector(0 to 0);
S_AXI_RREADY : in std_logic_vector(0 to 0);
M_AXI_ACLK : in std_logic_vector(5 downto 0);
M_AXI_AWID : out std_logic_vector(71 downto 0);
M_AXI_AWADDR : out std_logic_vector(191 downto 0);
M_AXI_AWLEN : out std_logic_vector(47 downto 0);
M_AXI_AWSIZE : out std_logic_vector(17 downto 0);
M_AXI_AWBURST : out std_logic_vector(11 downto 0);
M_AXI_AWLOCK : out std_logic_vector(11 downto 0);
M_AXI_AWCACHE : out std_logic_vector(23 downto 0);
M_AXI_AWPROT : out std_logic_vector(17 downto 0);
M_AXI_AWREGION : out std_logic_vector(23 downto 0);
M_AXI_AWQOS : out std_logic_vector(23 downto 0);
M_AXI_AWUSER : out std_logic_vector(5 downto 0);
M_AXI_AWVALID : out std_logic_vector(5 downto 0);
M_AXI_AWREADY : in std_logic_vector(5 downto 0);
M_AXI_WID : out std_logic_vector(71 downto 0);
M_AXI_WDATA : out std_logic_vector(191 downto 0);
M_AXI_WSTRB : out std_logic_vector(23 downto 0);
M_AXI_WLAST : out std_logic_vector(5 downto 0);
M_AXI_WUSER : out std_logic_vector(5 downto 0);
M_AXI_WVALID : out std_logic_vector(5 downto 0);
M_AXI_WREADY : in std_logic_vector(5 downto 0);
M_AXI_BID : in std_logic_vector(71 downto 0);
M_AXI_BRESP : in std_logic_vector(11 downto 0);
M_AXI_BUSER : in std_logic_vector(5 downto 0);
M_AXI_BVALID : in std_logic_vector(5 downto 0);
M_AXI_BREADY : out std_logic_vector(5 downto 0);
M_AXI_ARID : out std_logic_vector(71 downto 0);
M_AXI_ARADDR : out std_logic_vector(191 downto 0);
M_AXI_ARLEN : out std_logic_vector(47 downto 0);
M_AXI_ARSIZE : out std_logic_vector(17 downto 0);
M_AXI_ARBURST : out std_logic_vector(11 downto 0);
M_AXI_ARLOCK : out std_logic_vector(11 downto 0);
M_AXI_ARCACHE : out std_logic_vector(23 downto 0);
M_AXI_ARPROT : out std_logic_vector(17 downto 0);
M_AXI_ARREGION : out std_logic_vector(23 downto 0);
M_AXI_ARQOS : out std_logic_vector(23 downto 0);
M_AXI_ARUSER : out std_logic_vector(5 downto 0);
M_AXI_ARVALID : out std_logic_vector(5 downto 0);
M_AXI_ARREADY : in std_logic_vector(5 downto 0);
M_AXI_RID : in std_logic_vector(71 downto 0);
M_AXI_RDATA : in std_logic_vector(191 downto 0);
M_AXI_RRESP : in std_logic_vector(11 downto 0);
M_AXI_RLAST : in std_logic_vector(5 downto 0);
M_AXI_RUSER : in std_logic_vector(5 downto 0);
M_AXI_RVALID : in std_logic_vector(5 downto 0);
M_AXI_RREADY : out std_logic_vector(5 downto 0);
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
INTERCONNECT_ARESET_OUT_N : out std_logic;
DEBUG_AW_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AR_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AW_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AW_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AW_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AW_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AW_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AR_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AR_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AR_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AR_TARGET : out std_logic_vector(7 downto 0);
DEBUG_B_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_R_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_R_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_BID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_BID_ERROR : out std_logic;
DEBUG_RID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_RID_ERROR : out std_logic;
DEBUG_SR_SC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SR_SC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SR_SC_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SR_SC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SR_SC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SC_SF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SC_SF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SC_SF_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SC_SF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SC_SF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SF_CB_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SF_CB_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SF_CB_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SF_CB_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SF_CB_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_CB_MF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_CB_MF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_CB_MF_BRESP : out std_logic_vector(15 downto 0);
DEBUG_CB_MF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_CB_MF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MF_MC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MF_MC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MF_MC_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MF_MC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MF_MC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MC_MP_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MC_MP_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MC_MP_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MC_MP_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MC_MP_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MP_MR_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MP_MR_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MP_MR_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MP_MR_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MP_MR_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_WDATACONTROL : out std_logic_vector(6 downto 0)
);
end component;
component system_sws_8bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(7 downto 0);
GPIO_IO_O : out std_logic_vector(7 downto 0);
GPIO_IO_T : out std_logic_vector(7 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
end component;
component system_leds_8bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(7 downto 0);
GPIO_IO_O : out std_logic_vector(7 downto 0);
GPIO_IO_T : out std_logic_vector(7 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
end component;
component system_btns_5bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(4 downto 0);
GPIO_IO_O : out std_logic_vector(4 downto 0);
GPIO_IO_T : out std_logic_vector(4 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
end component;
component system_axi_dma_0_wrapper is
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(9 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(9 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_awaddr : out std_logic_vector(31 downto 0);
m_axi_sg_awlen : out std_logic_vector(7 downto 0);
m_axi_sg_awsize : out std_logic_vector(2 downto 0);
m_axi_sg_awburst : out std_logic_vector(1 downto 0);
m_axi_sg_awprot : out std_logic_vector(2 downto 0);
m_axi_sg_awcache : out std_logic_vector(3 downto 0);
m_axi_sg_awuser : out std_logic_vector(3 downto 0);
m_axi_sg_awvalid : out std_logic;
m_axi_sg_awready : in std_logic;
m_axi_sg_wdata : out std_logic_vector(31 downto 0);
m_axi_sg_wstrb : out std_logic_vector(3 downto 0);
m_axi_sg_wlast : out std_logic;
m_axi_sg_wvalid : out std_logic;
m_axi_sg_wready : in std_logic;
m_axi_sg_bresp : in std_logic_vector(1 downto 0);
m_axi_sg_bvalid : in std_logic;
m_axi_sg_bready : out std_logic;
m_axi_sg_araddr : out std_logic_vector(31 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_aruser : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(31 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(31 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(3 downto 0);
m_axis_mm2s_tid : out std_logic_vector(4 downto 0);
m_axis_mm2s_tdest : out std_logic_vector(4 downto 0);
mm2s_cntrl_reset_out_n : out std_logic;
m_axis_mm2s_cntrl_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_cntrl_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_cntrl_tvalid : out std_logic;
m_axis_mm2s_cntrl_tready : in std_logic;
m_axis_mm2s_cntrl_tlast : out std_logic;
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(31 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(3 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(3 downto 0);
s_axis_s2mm_tid : in std_logic_vector(4 downto 0);
s_axis_s2mm_tdest : in std_logic_vector(4 downto 0);
s2mm_sts_reset_out_n : out std_logic;
s_axis_s2mm_sts_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_sts_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_sts_tvalid : in std_logic;
s_axis_s2mm_sts_tready : out std_logic;
s_axis_s2mm_sts_tlast : in std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_dma_tstvec : out std_logic_vector(31 downto 0)
);
end component;
component system_axi_interconnect_1_wrapper is
port (
INTERCONNECT_ACLK : in std_logic;
INTERCONNECT_ARESETN : in std_logic;
S_AXI_ARESET_OUT_N : out std_logic_vector(3 downto 0);
M_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
IRQ : out std_logic;
S_AXI_ACLK : in std_logic_vector(3 downto 0);
S_AXI_AWID : in std_logic_vector(7 downto 0);
S_AXI_AWADDR : in std_logic_vector(127 downto 0);
S_AXI_AWLEN : in std_logic_vector(31 downto 0);
S_AXI_AWSIZE : in std_logic_vector(11 downto 0);
S_AXI_AWBURST : in std_logic_vector(7 downto 0);
S_AXI_AWLOCK : in std_logic_vector(7 downto 0);
S_AXI_AWCACHE : in std_logic_vector(15 downto 0);
S_AXI_AWPROT : in std_logic_vector(11 downto 0);
S_AXI_AWQOS : in std_logic_vector(15 downto 0);
S_AXI_AWUSER : in std_logic_vector(15 downto 0);
S_AXI_AWVALID : in std_logic_vector(3 downto 0);
S_AXI_AWREADY : out std_logic_vector(3 downto 0);
S_AXI_WID : in std_logic_vector(7 downto 0);
S_AXI_WDATA : in std_logic_vector(255 downto 0);
S_AXI_WSTRB : in std_logic_vector(31 downto 0);
S_AXI_WLAST : in std_logic_vector(3 downto 0);
S_AXI_WUSER : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic_vector(3 downto 0);
S_AXI_WREADY : out std_logic_vector(3 downto 0);
S_AXI_BID : out std_logic_vector(7 downto 0);
S_AXI_BRESP : out std_logic_vector(7 downto 0);
S_AXI_BUSER : out std_logic_vector(3 downto 0);
S_AXI_BVALID : out std_logic_vector(3 downto 0);
S_AXI_BREADY : in std_logic_vector(3 downto 0);
S_AXI_ARID : in std_logic_vector(7 downto 0);
S_AXI_ARADDR : in std_logic_vector(127 downto 0);
S_AXI_ARLEN : in std_logic_vector(31 downto 0);
S_AXI_ARSIZE : in std_logic_vector(11 downto 0);
S_AXI_ARBURST : in std_logic_vector(7 downto 0);
S_AXI_ARLOCK : in std_logic_vector(7 downto 0);
S_AXI_ARCACHE : in std_logic_vector(15 downto 0);
S_AXI_ARPROT : in std_logic_vector(11 downto 0);
S_AXI_ARQOS : in std_logic_vector(15 downto 0);
S_AXI_ARUSER : in std_logic_vector(15 downto 0);
S_AXI_ARVALID : in std_logic_vector(3 downto 0);
S_AXI_ARREADY : out std_logic_vector(3 downto 0);
S_AXI_RID : out std_logic_vector(7 downto 0);
S_AXI_RDATA : out std_logic_vector(255 downto 0);
S_AXI_RRESP : out std_logic_vector(7 downto 0);
S_AXI_RLAST : out std_logic_vector(3 downto 0);
S_AXI_RUSER : out std_logic_vector(3 downto 0);
S_AXI_RVALID : out std_logic_vector(3 downto 0);
S_AXI_RREADY : in std_logic_vector(3 downto 0);
M_AXI_ACLK : in std_logic_vector(0 to 0);
M_AXI_AWID : out std_logic_vector(1 downto 0);
M_AXI_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWREGION : out std_logic_vector(3 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic_vector(0 to 0);
M_AXI_AWREADY : in std_logic_vector(0 to 0);
M_AXI_WID : out std_logic_vector(1 downto 0);
M_AXI_WDATA : out std_logic_vector(63 downto 0);
M_AXI_WSTRB : out std_logic_vector(7 downto 0);
M_AXI_WLAST : out std_logic_vector(0 to 0);
M_AXI_WUSER : out std_logic_vector(0 to 0);
M_AXI_WVALID : out std_logic_vector(0 to 0);
M_AXI_WREADY : in std_logic_vector(0 to 0);
M_AXI_BID : in std_logic_vector(1 downto 0);
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BUSER : in std_logic_vector(0 to 0);
M_AXI_BVALID : in std_logic_vector(0 to 0);
M_AXI_BREADY : out std_logic_vector(0 to 0);
M_AXI_ARID : out std_logic_vector(1 downto 0);
M_AXI_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARREGION : out std_logic_vector(3 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARUSER : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic_vector(0 to 0);
M_AXI_ARREADY : in std_logic_vector(0 to 0);
M_AXI_RID : in std_logic_vector(1 downto 0);
M_AXI_RDATA : in std_logic_vector(63 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic_vector(0 to 0);
M_AXI_RUSER : in std_logic_vector(0 to 0);
M_AXI_RVALID : in std_logic_vector(0 to 0);
M_AXI_RREADY : out std_logic_vector(0 to 0);
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
INTERCONNECT_ARESET_OUT_N : out std_logic;
DEBUG_AW_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AR_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AW_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AW_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AW_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AW_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AW_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AR_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AR_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AR_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AR_TARGET : out std_logic_vector(7 downto 0);
DEBUG_B_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_R_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_R_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_BID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_BID_ERROR : out std_logic;
DEBUG_RID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_RID_ERROR : out std_logic;
DEBUG_SR_SC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_ARADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_SR_SC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_AWADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_SR_SC_BRESP : out std_logic_vector(5 downto 0);
DEBUG_SR_SC_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SR_SC_RDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SR_SC_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SR_SC_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_SC_SF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_ARADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_SC_SF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_AWADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_SC_SF_BRESP : out std_logic_vector(5 downto 0);
DEBUG_SC_SF_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SC_SF_RDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SC_SF_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SC_SF_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_SF_CB_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_ARADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_SF_CB_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_AWADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_SF_CB_BRESP : out std_logic_vector(5 downto 0);
DEBUG_SF_CB_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SF_CB_RDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SF_CB_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SF_CB_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_CB_MF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_ARADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_CB_MF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_AWADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_CB_MF_BRESP : out std_logic_vector(5 downto 0);
DEBUG_CB_MF_RDATA : out std_logic_vector(63 downto 0);
DEBUG_CB_MF_RDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_CB_MF_WDATA : out std_logic_vector(63 downto 0);
DEBUG_CB_MF_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MF_MC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_ARADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_MF_MC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_AWADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_MF_MC_BRESP : out std_logic_vector(5 downto 0);
DEBUG_MF_MC_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MF_MC_RDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MF_MC_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MF_MC_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MC_MP_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_ARADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_MC_MP_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_AWADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_MC_MP_BRESP : out std_logic_vector(5 downto 0);
DEBUG_MC_MP_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MC_MP_RDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MC_MP_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MC_MP_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MP_MR_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_ARADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_MP_MR_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_AWADDRCONTROL : out std_logic_vector(24 downto 0);
DEBUG_MP_MR_BRESP : out std_logic_vector(5 downto 0);
DEBUG_MP_MR_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MP_MR_RDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MP_MR_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MP_MR_WDATACONTROL : out std_logic_vector(10 downto 0)
);
end component;
component system_v_axi4s_vid_out_0_wrapper is
port (
aclk : in std_logic;
rst : in std_logic;
aresetn : in std_logic;
aclken : in std_logic;
s_axis_video_tdata : in std_logic_vector(31 downto 0);
s_axis_video_tvalid : in std_logic;
s_axis_video_tready : out std_logic;
s_axis_video_tuser : in std_logic;
s_axis_video_tlast : in std_logic;
video_out_clk : in std_logic;
video_de : out std_logic;
video_vsync : out std_logic;
video_hsync : out std_logic;
video_vblank : out std_logic;
video_hblank : out std_logic;
video_data : out std_logic_vector(31 downto 0);
vtg_vsync : in std_logic;
vtg_hsync : in std_logic;
vtg_vblank : in std_logic;
vtg_hblank : in std_logic;
vtg_act_vid : in std_logic;
vtg_ce : out std_logic;
vtg_fsync : out std_logic;
locked : out std_logic;
wr_error : out std_logic;
empty : out std_logic
);
end component;
component system_axi_vdma_0_wrapper is
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(8 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(8 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(31 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(31 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(31 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(0 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(31 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(3 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(0 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector(5 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector(5 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
end component;
component system_v_tc_0_wrapper is
port (
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_aclken : in std_logic;
s_axi_awaddr : in std_logic_vector(8 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(8 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
irq : out std_logic;
intc_if : out std_logic_vector(31 downto 0);
clk : in std_logic;
resetn : in std_logic;
clken : in std_logic;
det_clken : in std_logic;
gen_clken : in std_logic;
fsync_in : in std_logic;
vblank_in : in std_logic;
vsync_in : in std_logic;
hblank_in : in std_logic;
hsync_in : in std_logic;
active_video_in : in std_logic;
active_chroma_in : in std_logic;
vblank_out : out std_logic;
vsync_out : out std_logic;
hblank_out : out std_logic;
hsync_out : out std_logic;
active_video_out : out std_logic;
active_chroma_out : out std_logic;
fsync_out : out std_logic_vector(0 to 0)
);
end component;
component system_processing_system7_0_wrapper is
port (
CAN0_PHY_TX : out std_logic;
CAN0_PHY_RX : in std_logic;
CAN1_PHY_TX : out std_logic;
CAN1_PHY_RX : in std_logic;
ENET0_GMII_TX_EN : out std_logic;
ENET0_GMII_TX_ER : out std_logic;
ENET0_MDIO_MDC : out std_logic;
ENET0_MDIO_O : out std_logic;
ENET0_MDIO_T : out std_logic;
ENET0_PTP_DELAY_REQ_RX : out std_logic;
ENET0_PTP_DELAY_REQ_TX : out std_logic;
ENET0_PTP_PDELAY_REQ_RX : out std_logic;
ENET0_PTP_PDELAY_REQ_TX : out std_logic;
ENET0_PTP_PDELAY_RESP_RX : out std_logic;
ENET0_PTP_PDELAY_RESP_TX : out std_logic;
ENET0_PTP_SYNC_FRAME_RX : out std_logic;
ENET0_PTP_SYNC_FRAME_TX : out std_logic;
ENET0_SOF_RX : out std_logic;
ENET0_SOF_TX : out std_logic;
ENET0_GMII_TXD : out std_logic_vector(7 downto 0);
ENET0_GMII_COL : in std_logic;
ENET0_GMII_CRS : in std_logic;
ENET0_EXT_INTIN : in std_logic;
ENET0_GMII_RX_CLK : in std_logic;
ENET0_GMII_RX_DV : in std_logic;
ENET0_GMII_RX_ER : in std_logic;
ENET0_GMII_TX_CLK : in std_logic;
ENET0_MDIO_I : in std_logic;
ENET0_GMII_RXD : in std_logic_vector(7 downto 0);
ENET1_GMII_TX_EN : out std_logic;
ENET1_GMII_TX_ER : out std_logic;
ENET1_MDIO_MDC : out std_logic;
ENET1_MDIO_O : out std_logic;
ENET1_MDIO_T : out std_logic;
ENET1_PTP_DELAY_REQ_RX : out std_logic;
ENET1_PTP_DELAY_REQ_TX : out std_logic;
ENET1_PTP_PDELAY_REQ_RX : out std_logic;
ENET1_PTP_PDELAY_REQ_TX : out std_logic;
ENET1_PTP_PDELAY_RESP_RX : out std_logic;
ENET1_PTP_PDELAY_RESP_TX : out std_logic;
ENET1_PTP_SYNC_FRAME_RX : out std_logic;
ENET1_PTP_SYNC_FRAME_TX : out std_logic;
ENET1_SOF_RX : out std_logic;
ENET1_SOF_TX : out std_logic;
ENET1_GMII_TXD : out std_logic_vector(7 downto 0);
ENET1_GMII_COL : in std_logic;
ENET1_GMII_CRS : in std_logic;
ENET1_EXT_INTIN : in std_logic;
ENET1_GMII_RX_CLK : in std_logic;
ENET1_GMII_RX_DV : in std_logic;
ENET1_GMII_RX_ER : in std_logic;
ENET1_GMII_TX_CLK : in std_logic;
ENET1_MDIO_I : in std_logic;
ENET1_GMII_RXD : in std_logic_vector(7 downto 0);
GPIO_I : in std_logic_vector(63 downto 0);
GPIO_O : out std_logic_vector(63 downto 0);
GPIO_T : out std_logic_vector(63 downto 0);
I2C0_SDA_I : in std_logic;
I2C0_SDA_O : out std_logic;
I2C0_SDA_T : out std_logic;
I2C0_SCL_I : in std_logic;
I2C0_SCL_O : out std_logic;
I2C0_SCL_T : out std_logic;
I2C1_SDA_I : in std_logic;
I2C1_SDA_O : out std_logic;
I2C1_SDA_T : out std_logic;
I2C1_SCL_I : in std_logic;
I2C1_SCL_O : out std_logic;
I2C1_SCL_T : out std_logic;
PJTAG_TCK : in std_logic;
PJTAG_TMS : in std_logic;
PJTAG_TD_I : in std_logic;
PJTAG_TD_T : out std_logic;
PJTAG_TD_O : out std_logic;
SDIO0_CLK : out std_logic;
SDIO0_CLK_FB : in std_logic;
SDIO0_CMD_O : out std_logic;
SDIO0_CMD_I : in std_logic;
SDIO0_CMD_T : out std_logic;
SDIO0_DATA_I : in std_logic_vector(3 downto 0);
SDIO0_DATA_O : out std_logic_vector(3 downto 0);
SDIO0_DATA_T : out std_logic_vector(3 downto 0);
SDIO0_LED : out std_logic;
SDIO0_CDN : in std_logic;
SDIO0_WP : in std_logic;
SDIO0_BUSPOW : out std_logic;
SDIO0_BUSVOLT : out std_logic_vector(2 downto 0);
SDIO1_CLK : out std_logic;
SDIO1_CLK_FB : in std_logic;
SDIO1_CMD_O : out std_logic;
SDIO1_CMD_I : in std_logic;
SDIO1_CMD_T : out std_logic;
SDIO1_DATA_I : in std_logic_vector(3 downto 0);
SDIO1_DATA_O : out std_logic_vector(3 downto 0);
SDIO1_DATA_T : out std_logic_vector(3 downto 0);
SDIO1_LED : out std_logic;
SDIO1_CDN : in std_logic;
SDIO1_WP : in std_logic;
SDIO1_BUSPOW : out std_logic;
SDIO1_BUSVOLT : out std_logic_vector(2 downto 0);
SPI0_SCLK_I : in std_logic;
SPI0_SCLK_O : out std_logic;
SPI0_SCLK_T : out std_logic;
SPI0_MOSI_I : in std_logic;
SPI0_MOSI_O : out std_logic;
SPI0_MOSI_T : out std_logic;
SPI0_MISO_I : in std_logic;
SPI0_MISO_O : out std_logic;
SPI0_MISO_T : out std_logic;
SPI0_SS_I : in std_logic;
SPI0_SS_O : out std_logic;
SPI0_SS1_O : out std_logic;
SPI0_SS2_O : out std_logic;
SPI0_SS_T : out std_logic;
SPI1_SCLK_I : in std_logic;
SPI1_SCLK_O : out std_logic;
SPI1_SCLK_T : out std_logic;
SPI1_MOSI_I : in std_logic;
SPI1_MOSI_O : out std_logic;
SPI1_MOSI_T : out std_logic;
SPI1_MISO_I : in std_logic;
SPI1_MISO_O : out std_logic;
SPI1_MISO_T : out std_logic;
SPI1_SS_I : in std_logic;
SPI1_SS_O : out std_logic;
SPI1_SS1_O : out std_logic;
SPI1_SS2_O : out std_logic;
SPI1_SS_T : out std_logic;
UART0_DTRN : out std_logic;
UART0_RTSN : out std_logic;
UART0_TX : out std_logic;
UART0_CTSN : in std_logic;
UART0_DCDN : in std_logic;
UART0_DSRN : in std_logic;
UART0_RIN : in std_logic;
UART0_RX : in std_logic;
UART1_DTRN : out std_logic;
UART1_RTSN : out std_logic;
UART1_TX : out std_logic;
UART1_CTSN : in std_logic;
UART1_DCDN : in std_logic;
UART1_DSRN : in std_logic;
UART1_RIN : in std_logic;
UART1_RX : in std_logic;
TTC0_WAVE0_OUT : out std_logic;
TTC0_WAVE1_OUT : out std_logic;
TTC0_WAVE2_OUT : out std_logic;
TTC0_CLK0_IN : in std_logic;
TTC0_CLK1_IN : in std_logic;
TTC0_CLK2_IN : in std_logic;
TTC1_WAVE0_OUT : out std_logic;
TTC1_WAVE1_OUT : out std_logic;
TTC1_WAVE2_OUT : out std_logic;
TTC1_CLK0_IN : in std_logic;
TTC1_CLK1_IN : in std_logic;
TTC1_CLK2_IN : in std_logic;
WDT_CLK_IN : in std_logic;
WDT_RST_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(31 downto 0);
USB0_PORT_INDCTL : out std_logic_vector(1 downto 0);
USB1_PORT_INDCTL : out std_logic_vector(1 downto 0);
USB0_VBUS_PWRSELECT : out std_logic;
USB1_VBUS_PWRSELECT : out std_logic;
USB0_VBUS_PWRFAULT : in std_logic;
USB1_VBUS_PWRFAULT : in std_logic;
SRAM_INTIN : in std_logic;
M_AXI_GP0_ARESETN : out std_logic;
M_AXI_GP0_ARVALID : out std_logic;
M_AXI_GP0_AWVALID : out std_logic;
M_AXI_GP0_BREADY : out std_logic;
M_AXI_GP0_RREADY : out std_logic;
M_AXI_GP0_WLAST : out std_logic;
M_AXI_GP0_WVALID : out std_logic;
M_AXI_GP0_ARID : out std_logic_vector(11 downto 0);
M_AXI_GP0_AWID : out std_logic_vector(11 downto 0);
M_AXI_GP0_WID : out std_logic_vector(11 downto 0);
M_AXI_GP0_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_GP0_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP0_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP0_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_GP0_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP0_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP0_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_GP0_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_GP0_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_GP0_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_GP0_WDATA : out std_logic_vector(31 downto 0);
M_AXI_GP0_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP0_ARLEN : out std_logic_vector(3 downto 0);
M_AXI_GP0_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWLEN : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_GP0_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_GP0_ACLK : in std_logic;
M_AXI_GP0_ARREADY : in std_logic;
M_AXI_GP0_AWREADY : in std_logic;
M_AXI_GP0_BVALID : in std_logic;
M_AXI_GP0_RLAST : in std_logic;
M_AXI_GP0_RVALID : in std_logic;
M_AXI_GP0_WREADY : in std_logic;
M_AXI_GP0_BID : in std_logic_vector(11 downto 0);
M_AXI_GP0_RID : in std_logic_vector(11 downto 0);
M_AXI_GP0_BRESP : in std_logic_vector(1 downto 0);
M_AXI_GP0_RRESP : in std_logic_vector(1 downto 0);
M_AXI_GP0_RDATA : in std_logic_vector(31 downto 0);
M_AXI_GP1_ARESETN : out std_logic;
M_AXI_GP1_ARVALID : out std_logic;
M_AXI_GP1_AWVALID : out std_logic;
M_AXI_GP1_BREADY : out std_logic;
M_AXI_GP1_RREADY : out std_logic;
M_AXI_GP1_WLAST : out std_logic;
M_AXI_GP1_WVALID : out std_logic;
M_AXI_GP1_ARID : out std_logic_vector(11 downto 0);
M_AXI_GP1_AWID : out std_logic_vector(11 downto 0);
M_AXI_GP1_WID : out std_logic_vector(11 downto 0);
M_AXI_GP1_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_GP1_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP1_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP1_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_GP1_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP1_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP1_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_GP1_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_GP1_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_GP1_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_GP1_WDATA : out std_logic_vector(31 downto 0);
M_AXI_GP1_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP1_ARLEN : out std_logic_vector(3 downto 0);
M_AXI_GP1_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWLEN : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_GP1_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_GP1_ACLK : in std_logic;
M_AXI_GP1_ARREADY : in std_logic;
M_AXI_GP1_AWREADY : in std_logic;
M_AXI_GP1_BVALID : in std_logic;
M_AXI_GP1_RLAST : in std_logic;
M_AXI_GP1_RVALID : in std_logic;
M_AXI_GP1_WREADY : in std_logic;
M_AXI_GP1_BID : in std_logic_vector(11 downto 0);
M_AXI_GP1_RID : in std_logic_vector(11 downto 0);
M_AXI_GP1_BRESP : in std_logic_vector(1 downto 0);
M_AXI_GP1_RRESP : in std_logic_vector(1 downto 0);
M_AXI_GP1_RDATA : in std_logic_vector(31 downto 0);
S_AXI_GP0_ARESETN : out std_logic;
S_AXI_GP0_ARREADY : out std_logic;
S_AXI_GP0_AWREADY : out std_logic;
S_AXI_GP0_BVALID : out std_logic;
S_AXI_GP0_RLAST : out std_logic;
S_AXI_GP0_RVALID : out std_logic;
S_AXI_GP0_WREADY : out std_logic;
S_AXI_GP0_BRESP : out std_logic_vector(1 downto 0);
S_AXI_GP0_RRESP : out std_logic_vector(1 downto 0);
S_AXI_GP0_RDATA : out std_logic_vector(31 downto 0);
S_AXI_GP0_BID : out std_logic_vector(5 downto 0);
S_AXI_GP0_RID : out std_logic_vector(5 downto 0);
S_AXI_GP0_ACLK : in std_logic;
S_AXI_GP0_ARVALID : in std_logic;
S_AXI_GP0_AWVALID : in std_logic;
S_AXI_GP0_BREADY : in std_logic;
S_AXI_GP0_RREADY : in std_logic;
S_AXI_GP0_WLAST : in std_logic;
S_AXI_GP0_WVALID : in std_logic;
S_AXI_GP0_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_GP0_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP0_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP0_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_GP0_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP0_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP0_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_GP0_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_GP0_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_GP0_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_GP0_WDATA : in std_logic_vector(31 downto 0);
S_AXI_GP0_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_GP0_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARID : in std_logic_vector(5 downto 0);
S_AXI_GP0_AWID : in std_logic_vector(5 downto 0);
S_AXI_GP0_WID : in std_logic_vector(5 downto 0);
S_AXI_GP1_ARESETN : out std_logic;
S_AXI_GP1_ARREADY : out std_logic;
S_AXI_GP1_AWREADY : out std_logic;
S_AXI_GP1_BVALID : out std_logic;
S_AXI_GP1_RLAST : out std_logic;
S_AXI_GP1_RVALID : out std_logic;
S_AXI_GP1_WREADY : out std_logic;
S_AXI_GP1_BRESP : out std_logic_vector(1 downto 0);
S_AXI_GP1_RRESP : out std_logic_vector(1 downto 0);
S_AXI_GP1_RDATA : out std_logic_vector(31 downto 0);
S_AXI_GP1_BID : out std_logic_vector(5 downto 0);
S_AXI_GP1_RID : out std_logic_vector(5 downto 0);
S_AXI_GP1_ACLK : in std_logic;
S_AXI_GP1_ARVALID : in std_logic;
S_AXI_GP1_AWVALID : in std_logic;
S_AXI_GP1_BREADY : in std_logic;
S_AXI_GP1_RREADY : in std_logic;
S_AXI_GP1_WLAST : in std_logic;
S_AXI_GP1_WVALID : in std_logic;
S_AXI_GP1_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_GP1_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP1_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP1_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_GP1_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP1_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP1_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_GP1_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_GP1_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_GP1_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_GP1_WDATA : in std_logic_vector(31 downto 0);
S_AXI_GP1_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_GP1_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARID : in std_logic_vector(5 downto 0);
S_AXI_GP1_AWID : in std_logic_vector(5 downto 0);
S_AXI_GP1_WID : in std_logic_vector(5 downto 0);
S_AXI_ACP_ARESETN : out std_logic;
S_AXI_ACP_AWREADY : out std_logic;
S_AXI_ACP_ARREADY : out std_logic;
S_AXI_ACP_BVALID : out std_logic;
S_AXI_ACP_RLAST : out std_logic;
S_AXI_ACP_RVALID : out std_logic;
S_AXI_ACP_WREADY : out std_logic;
S_AXI_ACP_BRESP : out std_logic_vector(1 downto 0);
S_AXI_ACP_RRESP : out std_logic_vector(1 downto 0);
S_AXI_ACP_BID : out std_logic_vector(2 downto 0);
S_AXI_ACP_RID : out std_logic_vector(2 downto 0);
S_AXI_ACP_RDATA : out std_logic_vector(63 downto 0);
S_AXI_ACP_ACLK : in std_logic;
S_AXI_ACP_ARVALID : in std_logic;
S_AXI_ACP_AWVALID : in std_logic;
S_AXI_ACP_BREADY : in std_logic;
S_AXI_ACP_RREADY : in std_logic;
S_AXI_ACP_WLAST : in std_logic;
S_AXI_ACP_WVALID : in std_logic;
S_AXI_ACP_ARID : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWID : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_ACP_WID : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ACP_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_ACP_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ACP_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ACP_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_ACP_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_ACP_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARUSER : in std_logic_vector(4 downto 0);
S_AXI_ACP_AWUSER : in std_logic_vector(4 downto 0);
S_AXI_ACP_WDATA : in std_logic_vector(63 downto 0);
S_AXI_ACP_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP0_ARESETN : out std_logic;
S_AXI_HP0_ARREADY : out std_logic;
S_AXI_HP0_AWREADY : out std_logic;
S_AXI_HP0_BVALID : out std_logic;
S_AXI_HP0_RLAST : out std_logic;
S_AXI_HP0_RVALID : out std_logic;
S_AXI_HP0_WREADY : out std_logic;
S_AXI_HP0_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP0_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP0_BID : out std_logic_vector(1 downto 0);
S_AXI_HP0_RID : out std_logic_vector(1 downto 0);
S_AXI_HP0_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP0_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP0_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP0_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP0_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP0_ACLK : in std_logic;
S_AXI_HP0_ARVALID : in std_logic;
S_AXI_HP0_AWVALID : in std_logic;
S_AXI_HP0_BREADY : in std_logic;
S_AXI_HP0_RDISSUECAP1_EN : in std_logic;
S_AXI_HP0_RREADY : in std_logic;
S_AXI_HP0_WLAST : in std_logic;
S_AXI_HP0_WRISSUECAP1_EN : in std_logic;
S_AXI_HP0_WVALID : in std_logic;
S_AXI_HP0_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP0_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP0_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP0_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP0_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP0_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP0_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP0_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP0_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP0_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP0_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARID : in std_logic_vector(1 downto 0);
S_AXI_HP0_AWID : in std_logic_vector(1 downto 0);
S_AXI_HP0_WID : in std_logic_vector(1 downto 0);
S_AXI_HP0_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP0_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP1_ARESETN : out std_logic;
S_AXI_HP1_ARREADY : out std_logic;
S_AXI_HP1_AWREADY : out std_logic;
S_AXI_HP1_BVALID : out std_logic;
S_AXI_HP1_RLAST : out std_logic;
S_AXI_HP1_RVALID : out std_logic;
S_AXI_HP1_WREADY : out std_logic;
S_AXI_HP1_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP1_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP1_BID : out std_logic_vector(5 downto 0);
S_AXI_HP1_RID : out std_logic_vector(5 downto 0);
S_AXI_HP1_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP1_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP1_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP1_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP1_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP1_ACLK : in std_logic;
S_AXI_HP1_ARVALID : in std_logic;
S_AXI_HP1_AWVALID : in std_logic;
S_AXI_HP1_BREADY : in std_logic;
S_AXI_HP1_RDISSUECAP1_EN : in std_logic;
S_AXI_HP1_RREADY : in std_logic;
S_AXI_HP1_WLAST : in std_logic;
S_AXI_HP1_WRISSUECAP1_EN : in std_logic;
S_AXI_HP1_WVALID : in std_logic;
S_AXI_HP1_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP1_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP1_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP1_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP1_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP1_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP1_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP1_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP1_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP1_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP1_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP1_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP1_WID : in std_logic_vector(5 downto 0);
S_AXI_HP1_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP1_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP2_ARESETN : out std_logic;
S_AXI_HP2_ARREADY : out std_logic;
S_AXI_HP2_AWREADY : out std_logic;
S_AXI_HP2_BVALID : out std_logic;
S_AXI_HP2_RLAST : out std_logic;
S_AXI_HP2_RVALID : out std_logic;
S_AXI_HP2_WREADY : out std_logic;
S_AXI_HP2_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP2_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP2_BID : out std_logic_vector(5 downto 0);
S_AXI_HP2_RID : out std_logic_vector(5 downto 0);
S_AXI_HP2_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP2_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP2_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP2_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP2_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP2_ACLK : in std_logic;
S_AXI_HP2_ARVALID : in std_logic;
S_AXI_HP2_AWVALID : in std_logic;
S_AXI_HP2_BREADY : in std_logic;
S_AXI_HP2_RDISSUECAP1_EN : in std_logic;
S_AXI_HP2_RREADY : in std_logic;
S_AXI_HP2_WLAST : in std_logic;
S_AXI_HP2_WRISSUECAP1_EN : in std_logic;
S_AXI_HP2_WVALID : in std_logic;
S_AXI_HP2_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP2_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP2_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP2_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP2_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP2_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP2_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP2_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP2_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP2_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP2_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP2_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP2_WID : in std_logic_vector(5 downto 0);
S_AXI_HP2_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP2_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP3_ARESETN : out std_logic;
S_AXI_HP3_ARREADY : out std_logic;
S_AXI_HP3_AWREADY : out std_logic;
S_AXI_HP3_BVALID : out std_logic;
S_AXI_HP3_RLAST : out std_logic;
S_AXI_HP3_RVALID : out std_logic;
S_AXI_HP3_WREADY : out std_logic;
S_AXI_HP3_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP3_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP3_BID : out std_logic_vector(5 downto 0);
S_AXI_HP3_RID : out std_logic_vector(5 downto 0);
S_AXI_HP3_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP3_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP3_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP3_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP3_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP3_ACLK : in std_logic;
S_AXI_HP3_ARVALID : in std_logic;
S_AXI_HP3_AWVALID : in std_logic;
S_AXI_HP3_BREADY : in std_logic;
S_AXI_HP3_RDISSUECAP1_EN : in std_logic;
S_AXI_HP3_RREADY : in std_logic;
S_AXI_HP3_WLAST : in std_logic;
S_AXI_HP3_WRISSUECAP1_EN : in std_logic;
S_AXI_HP3_WVALID : in std_logic;
S_AXI_HP3_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP3_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP3_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP3_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP3_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP3_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP3_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP3_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP3_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP3_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP3_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP3_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP3_WID : in std_logic_vector(5 downto 0);
S_AXI_HP3_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP3_WSTRB : in std_logic_vector(7 downto 0);
DMA0_DATYPE : out std_logic_vector(1 downto 0);
DMA0_DAVALID : out std_logic;
DMA0_DRREADY : out std_logic;
DMA0_RSTN : out std_logic;
DMA0_ACLK : in std_logic;
DMA0_DAREADY : in std_logic;
DMA0_DRLAST : in std_logic;
DMA0_DRVALID : in std_logic;
DMA0_DRTYPE : in std_logic_vector(1 downto 0);
DMA1_DATYPE : out std_logic_vector(1 downto 0);
DMA1_DAVALID : out std_logic;
DMA1_DRREADY : out std_logic;
DMA1_RSTN : out std_logic;
DMA1_ACLK : in std_logic;
DMA1_DAREADY : in std_logic;
DMA1_DRLAST : in std_logic;
DMA1_DRVALID : in std_logic;
DMA1_DRTYPE : in std_logic_vector(1 downto 0);
DMA2_DATYPE : out std_logic_vector(1 downto 0);
DMA2_DAVALID : out std_logic;
DMA2_DRREADY : out std_logic;
DMA2_RSTN : out std_logic;
DMA2_ACLK : in std_logic;
DMA2_DAREADY : in std_logic;
DMA2_DRLAST : in std_logic;
DMA2_DRVALID : in std_logic;
DMA3_DRVALID : in std_logic;
DMA3_DATYPE : out std_logic_vector(1 downto 0);
DMA3_DAVALID : out std_logic;
DMA3_DRREADY : out std_logic;
DMA3_RSTN : out std_logic;
DMA3_ACLK : in std_logic;
DMA3_DAREADY : in std_logic;
DMA3_DRLAST : in std_logic;
DMA2_DRTYPE : in std_logic_vector(1 downto 0);
DMA3_DRTYPE : in std_logic_vector(1 downto 0);
FTMD_TRACEIN_DATA : in std_logic_vector(31 downto 0);
FTMD_TRACEIN_VALID : in std_logic;
FTMD_TRACEIN_CLK : in std_logic;
FTMD_TRACEIN_ATID : in std_logic_vector(3 downto 0);
FTMT_F2P_TRIG : in std_logic_vector(3 downto 0);
FTMT_F2P_TRIGACK : out std_logic_vector(3 downto 0);
FTMT_F2P_DEBUG : in std_logic_vector(31 downto 0);
FTMT_P2F_TRIGACK : in std_logic_vector(3 downto 0);
FTMT_P2F_TRIG : out std_logic_vector(3 downto 0);
FTMT_P2F_DEBUG : out std_logic_vector(31 downto 0);
FCLK_CLK3 : out std_logic;
FCLK_CLK2 : out std_logic;
FCLK_CLK1 : out std_logic;
FCLK_CLK0 : out std_logic;
FCLK_CLKTRIG3_N : in std_logic;
FCLK_CLKTRIG2_N : in std_logic;
FCLK_CLKTRIG1_N : in std_logic;
FCLK_CLKTRIG0_N : in std_logic;
FCLK_RESET3_N : out std_logic;
FCLK_RESET2_N : out std_logic;
FCLK_RESET1_N : out std_logic;
FCLK_RESET0_N : out std_logic;
FPGA_IDLE_N : in std_logic;
DDR_ARB : in std_logic_vector(3 downto 0);
IRQ_F2P : in std_logic_vector(0 to 0);
Core0_nFIQ : in std_logic;
Core0_nIRQ : in std_logic;
Core1_nFIQ : in std_logic;
Core1_nIRQ : in std_logic;
EVENT_EVENTO : out std_logic;
EVENT_STANDBYWFE : out std_logic_vector(1 downto 0);
EVENT_STANDBYWFI : out std_logic_vector(1 downto 0);
EVENT_EVENTI : in std_logic;
MIO : inout std_logic_vector(53 downto 0);
DDR_Clk : inout std_logic;
DDR_Clk_n : inout std_logic;
DDR_CKE : inout std_logic;
DDR_CS_n : inout std_logic;
DDR_RAS_n : inout std_logic;
DDR_CAS_n : inout std_logic;
DDR_WEB : out std_logic;
DDR_BankAddr : inout std_logic_vector(2 downto 0);
DDR_Addr : inout std_logic_vector(14 downto 0);
DDR_ODT : inout std_logic;
DDR_DRSTB : inout std_logic;
DDR_DQ : inout std_logic_vector(31 downto 0);
DDR_DM : inout std_logic_vector(3 downto 0);
DDR_DQS : inout std_logic_vector(3 downto 0);
DDR_DQS_n : inout std_logic_vector(3 downto 0);
DDR_VRN : inout std_logic;
DDR_VRP : inout std_logic;
PS_SRSTB : in std_logic;
PS_CLK : in std_logic;
PS_PORB : in std_logic;
IRQ_P2F_DMAC_ABORT : out std_logic;
IRQ_P2F_DMAC0 : out std_logic;
IRQ_P2F_DMAC1 : out std_logic;
IRQ_P2F_DMAC2 : out std_logic;
IRQ_P2F_DMAC3 : out std_logic;
IRQ_P2F_DMAC4 : out std_logic;
IRQ_P2F_DMAC5 : out std_logic;
IRQ_P2F_DMAC6 : out std_logic;
IRQ_P2F_DMAC7 : out std_logic;
IRQ_P2F_SMC : out std_logic;
IRQ_P2F_QSPI : out std_logic;
IRQ_P2F_CTI : out std_logic;
IRQ_P2F_GPIO : out std_logic;
IRQ_P2F_USB0 : out std_logic;
IRQ_P2F_ENET0 : out std_logic;
IRQ_P2F_ENET_WAKE0 : out std_logic;
IRQ_P2F_SDIO0 : out std_logic;
IRQ_P2F_I2C0 : out std_logic;
IRQ_P2F_SPI0 : out std_logic;
IRQ_P2F_UART0 : out std_logic;
IRQ_P2F_CAN0 : out std_logic;
IRQ_P2F_USB1 : out std_logic;
IRQ_P2F_ENET1 : out std_logic;
IRQ_P2F_ENET_WAKE1 : out std_logic;
IRQ_P2F_SDIO1 : out std_logic;
IRQ_P2F_I2C1 : out std_logic;
IRQ_P2F_SPI1 : out std_logic;
IRQ_P2F_UART1 : out std_logic;
IRQ_P2F_CAN1 : out std_logic
);
end component;
component system_conware_0_wrapper is
port (
ACLK : in std_logic;
ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
M_AXIS_TSTRB : out std_logic_vector(3 downto 0);
in_states : out std_logic_vector(7 downto 0);
out_states : out std_logic_vector(7 downto 0);
num_reads : out std_logic_vector(31 downto 0);
num_writes : out std_logic_vector(31 downto 0);
read_ctr : out std_logic_vector(7 downto 0);
write_ctr : out std_logic_vector(7 downto 0)
);
end component;
component IOBUF is
port (
I : in std_logic;
IO : inout std_logic;
O : out std_logic;
T : in std_logic
);
end component;
-- Internal signals
signal BTNs_5Bits_TRI_IO_I : std_logic_vector(4 downto 0);
signal BTNs_5Bits_TRI_IO_O : std_logic_vector(4 downto 0);
signal BTNs_5Bits_TRI_IO_T : std_logic_vector(4 downto 0);
signal SWs_8Bits_TRI_IO_I : std_logic_vector(7 downto 0);
signal SWs_8Bits_TRI_IO_O : std_logic_vector(7 downto 0);
signal SWs_8Bits_TRI_IO_T : std_logic_vector(7 downto 0);
signal axi4lite_0_M_ARADDR : std_logic_vector(191 downto 0);
signal axi4lite_0_M_ARESETN : std_logic_vector(5 downto 0);
signal axi4lite_0_M_ARREADY : std_logic_vector(5 downto 0);
signal axi4lite_0_M_ARVALID : std_logic_vector(5 downto 0);
signal axi4lite_0_M_AWADDR : std_logic_vector(191 downto 0);
signal axi4lite_0_M_AWREADY : std_logic_vector(5 downto 0);
signal axi4lite_0_M_AWVALID : std_logic_vector(5 downto 0);
signal axi4lite_0_M_BREADY : std_logic_vector(5 downto 0);
signal axi4lite_0_M_BRESP : std_logic_vector(11 downto 0);
signal axi4lite_0_M_BVALID : std_logic_vector(5 downto 0);
signal axi4lite_0_M_RDATA : std_logic_vector(191 downto 0);
signal axi4lite_0_M_RREADY : std_logic_vector(5 downto 0);
signal axi4lite_0_M_RRESP : std_logic_vector(11 downto 0);
signal axi4lite_0_M_RVALID : std_logic_vector(5 downto 0);
signal axi4lite_0_M_WDATA : std_logic_vector(191 downto 0);
signal axi4lite_0_M_WREADY : std_logic_vector(5 downto 0);
signal axi4lite_0_M_WSTRB : std_logic_vector(23 downto 0);
signal axi4lite_0_M_WVALID : std_logic_vector(5 downto 0);
signal axi4lite_0_S_ARADDR : std_logic_vector(31 downto 0);
signal axi4lite_0_S_ARBURST : std_logic_vector(1 downto 0);
signal axi4lite_0_S_ARCACHE : std_logic_vector(3 downto 0);
signal axi4lite_0_S_ARESETN : std_logic_vector(0 to 0);
signal axi4lite_0_S_ARID : std_logic_vector(11 downto 0);
signal axi4lite_0_S_ARLEN : std_logic_vector(7 downto 0);
signal axi4lite_0_S_ARLOCK : std_logic_vector(1 downto 0);
signal axi4lite_0_S_ARPROT : std_logic_vector(2 downto 0);
signal axi4lite_0_S_ARQOS : std_logic_vector(3 downto 0);
signal axi4lite_0_S_ARREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_ARSIZE : std_logic_vector(2 downto 0);
signal axi4lite_0_S_ARVALID : std_logic_vector(0 to 0);
signal axi4lite_0_S_AWADDR : std_logic_vector(31 downto 0);
signal axi4lite_0_S_AWBURST : std_logic_vector(1 downto 0);
signal axi4lite_0_S_AWCACHE : std_logic_vector(3 downto 0);
signal axi4lite_0_S_AWID : std_logic_vector(11 downto 0);
signal axi4lite_0_S_AWLEN : std_logic_vector(7 downto 0);
signal axi4lite_0_S_AWLOCK : std_logic_vector(1 downto 0);
signal axi4lite_0_S_AWPROT : std_logic_vector(2 downto 0);
signal axi4lite_0_S_AWQOS : std_logic_vector(3 downto 0);
signal axi4lite_0_S_AWREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_AWSIZE : std_logic_vector(2 downto 0);
signal axi4lite_0_S_AWVALID : std_logic_vector(0 to 0);
signal axi4lite_0_S_BID : std_logic_vector(11 downto 0);
signal axi4lite_0_S_BREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_BRESP : std_logic_vector(1 downto 0);
signal axi4lite_0_S_BVALID : std_logic_vector(0 to 0);
signal axi4lite_0_S_RDATA : std_logic_vector(31 downto 0);
signal axi4lite_0_S_RID : std_logic_vector(11 downto 0);
signal axi4lite_0_S_RLAST : std_logic_vector(0 to 0);
signal axi4lite_0_S_RREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_RRESP : std_logic_vector(1 downto 0);
signal axi4lite_0_S_RVALID : std_logic_vector(0 to 0);
signal axi4lite_0_S_WDATA : std_logic_vector(31 downto 0);
signal axi4lite_0_S_WID : std_logic_vector(11 downto 0);
signal axi4lite_0_S_WLAST : std_logic_vector(0 to 0);
signal axi4lite_0_S_WREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_WSTRB : std_logic_vector(3 downto 0);
signal axi4lite_0_S_WVALID : std_logic_vector(0 to 0);
signal axi_dma_0_M_AXIS_MM2S_TDATA : std_logic_vector(31 downto 0);
signal axi_dma_0_M_AXIS_MM2S_TLAST : std_logic;
signal axi_dma_0_M_AXIS_MM2S_TREADY : std_logic;
signal axi_dma_0_M_AXIS_MM2S_TVALID : std_logic;
signal axi_interconnect_1_M_ARADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_M_ARBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_ARCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_ARID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_ARLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_M_ARLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_ARPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_M_ARQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_ARREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_ARSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_M_ARVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_AWADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_M_AWBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_AWCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_AWID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_AWLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_M_AWLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_AWPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_M_AWQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_AWREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_AWSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_M_AWVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_BID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_BREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_BRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_BVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_RDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_RID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_RLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_RREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_RRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_RVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_WDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_WID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_WLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_WREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_WSTRB : std_logic_vector(7 downto 0);
signal axi_interconnect_1_M_WVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_ARADDR : std_logic_vector(127 downto 0);
signal axi_interconnect_1_S_ARBURST : std_logic_vector(7 downto 0);
signal axi_interconnect_1_S_ARCACHE : std_logic_vector(15 downto 0);
signal axi_interconnect_1_S_ARLEN : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_ARPROT : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_ARREADY : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_ARSIZE : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_ARUSER : std_logic_vector(15 downto 0);
signal axi_interconnect_1_S_ARVALID : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_AWADDR : std_logic_vector(127 downto 0);
signal axi_interconnect_1_S_AWBURST : std_logic_vector(7 downto 0);
signal axi_interconnect_1_S_AWCACHE : std_logic_vector(15 downto 0);
signal axi_interconnect_1_S_AWLEN : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_AWPROT : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_AWREADY : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_AWSIZE : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_AWUSER : std_logic_vector(15 downto 0);
signal axi_interconnect_1_S_AWVALID : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_BREADY : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_BRESP : std_logic_vector(7 downto 0);
signal axi_interconnect_1_S_BVALID : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_RDATA : std_logic_vector(255 downto 0);
signal axi_interconnect_1_S_RLAST : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_RREADY : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_RRESP : std_logic_vector(7 downto 0);
signal axi_interconnect_1_S_RVALID : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_WDATA : std_logic_vector(255 downto 0);
signal axi_interconnect_1_S_WLAST : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_WREADY : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_WSTRB : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_WVALID : std_logic_vector(3 downto 0);
signal axi_vdma_0_M_AXIS_MM2S_tdata : std_logic_vector(31 downto 0);
signal axi_vdma_0_M_AXIS_MM2S_tlast : std_logic;
signal axi_vdma_0_M_AXIS_MM2S_tready : std_logic;
signal axi_vdma_0_M_AXIS_MM2S_tuser : std_logic_vector(0 to 0);
signal axi_vdma_0_M_AXIS_MM2S_tvalid : std_logic;
signal conware_0_M_AXIS_TDATA : std_logic_vector(31 downto 0);
signal conware_0_M_AXIS_TKEEP : std_logic_vector(3 downto 0);
signal conware_0_M_AXIS_TLAST : std_logic;
signal conware_0_M_AXIS_TREADY : std_logic;
signal conware_0_M_AXIS_TVALID : std_logic;
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd2 : std_logic_vector(1 downto 0);
signal net_gnd3 : std_logic_vector(2 downto 0);
signal net_gnd4 : std_logic_vector(3 downto 0);
signal net_gnd5 : std_logic_vector(4 downto 0);
signal net_gnd6 : std_logic_vector(5 downto 0);
signal net_gnd8 : std_logic_vector(7 downto 0);
signal net_gnd12 : std_logic_vector(11 downto 0);
signal net_gnd16 : std_logic_vector(15 downto 0);
signal net_gnd32 : std_logic_vector(31 downto 0);
signal net_gnd64 : std_logic_vector(63 downto 0);
signal net_gnd72 : std_logic_vector(71 downto 0);
signal net_vcc0 : std_logic;
signal net_vcc4 : std_logic_vector(3 downto 0);
signal pgassign1 : std_logic_vector(5 downto 0);
signal pgassign2 : std_logic_vector(3 downto 0);
signal processing_system7_0_DDR_WEB : std_logic;
signal processing_system7_0_FCLK_CLK0_0 : std_logic_vector(0 to 0);
signal processing_system7_0_FCLK_CLK3 : std_logic;
signal processing_system7_0_FCLK_RESET0_N : std_logic;
signal processing_system7_0_PS_CLK : std_logic;
signal processing_system7_0_PS_PORB : std_logic;
signal processing_system7_0_PS_SRSTB : std_logic;
signal v_axi4s_vid_out_0_video_data : std_logic_vector(31 downto 0);
signal v_axi4s_vid_out_0_video_hsync : std_logic;
signal v_axi4s_vid_out_0_video_vsync : std_logic;
signal v_axi4s_vid_out_0_vtg_ce : std_logic;
signal v_tc_0_VTIMING_OUT_active_video : std_logic;
signal v_tc_0_VTIMING_OUT_hblank : std_logic;
signal v_tc_0_VTIMING_OUT_hsync : std_logic;
signal v_tc_0_VTIMING_OUT_vblank : std_logic;
signal v_tc_0_VTIMING_OUT_vsync : std_logic;
signal v_tc_0_fsync_out : std_logic_vector(0 to 0);
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system_axi4lite_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_sws_8bits_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_leds_8bits_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_btns_5bits_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_dma_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_interconnect_1_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_v_axi4s_vid_out_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_vdma_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_v_tc_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_processing_system7_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_conware_0_wrapper : component is "user_black_box";
begin
-- Internal assignments
v_axi4s_vid_out_0_video_vsync_pin <= v_axi4s_vid_out_0_video_vsync;
v_axi4s_vid_out_0_video_hsync_pin <= v_axi4s_vid_out_0_video_hsync;
v_axi4s_vid_out_0_video_data_pin <= v_axi4s_vid_out_0_video_data;
processing_system7_0_PS_SRSTB <= processing_system7_0_PS_SRSTB_pin;
processing_system7_0_PS_CLK <= processing_system7_0_PS_CLK_pin;
processing_system7_0_PS_PORB <= processing_system7_0_PS_PORB_pin;
processing_system7_0_DDR_WEB_pin <= processing_system7_0_DDR_WEB;
axi_interconnect_1_S_AWADDR(63 downto 32) <= B"00000000000000000000000000000000";
axi_interconnect_1_S_AWADDR(127 downto 96) <= B"00000000000000000000000000000000";
axi_interconnect_1_S_AWLEN(15 downto 8) <= B"00000000";
axi_interconnect_1_S_AWLEN(31 downto 24) <= B"00000000";
axi_interconnect_1_S_AWSIZE(5 downto 3) <= B"000";
axi_interconnect_1_S_AWSIZE(11 downto 9) <= B"000";
axi_interconnect_1_S_AWBURST(3 downto 2) <= B"00";
axi_interconnect_1_S_AWBURST(7 downto 6) <= B"00";
axi_interconnect_1_S_AWPROT(5 downto 3) <= B"000";
axi_interconnect_1_S_AWPROT(11 downto 9) <= B"000";
axi_interconnect_1_S_AWCACHE(7 downto 4) <= B"0000";
axi_interconnect_1_S_AWCACHE(15 downto 12) <= B"0000";
axi_interconnect_1_S_AWUSER(7 downto 4) <= B"0000";
axi_interconnect_1_S_AWUSER(15 downto 12) <= B"0000";
axi_interconnect_1_S_AWVALID(1 downto 1) <= B"0";
axi_interconnect_1_S_AWVALID(3 downto 3) <= B"0";
axi_interconnect_1_S_WDATA(127 downto 64) <= B"0000000000000000000000000000000000000000000000000000000000000000";
axi_interconnect_1_S_WDATA(255 downto 192) <= B"0000000000000000000000000000000000000000000000000000000000000000";
axi_interconnect_1_S_WSTRB(15 downto 8) <= B"00000000";
axi_interconnect_1_S_WSTRB(31 downto 24) <= B"00000000";
axi_interconnect_1_S_WLAST(1 downto 1) <= B"0";
axi_interconnect_1_S_WLAST(3 downto 3) <= B"0";
axi_interconnect_1_S_WVALID(1 downto 1) <= B"0";
axi_interconnect_1_S_WVALID(3 downto 3) <= B"0";
axi_interconnect_1_S_BREADY(1 downto 1) <= B"0";
axi_interconnect_1_S_BREADY(3 downto 3) <= B"0";
axi_interconnect_1_S_ARADDR(95 downto 64) <= B"00000000000000000000000000000000";
axi_interconnect_1_S_ARLEN(23 downto 16) <= B"00000000";
axi_interconnect_1_S_ARSIZE(8 downto 6) <= B"000";
axi_interconnect_1_S_ARBURST(5 downto 4) <= B"00";
axi_interconnect_1_S_ARPROT(8 downto 6) <= B"000";
axi_interconnect_1_S_ARCACHE(11 downto 8) <= B"0000";
axi_interconnect_1_S_ARUSER(11 downto 8) <= B"0000";
axi_interconnect_1_S_ARUSER(15 downto 12) <= B"0000";
axi_interconnect_1_S_ARVALID(2 downto 2) <= B"0";
axi_interconnect_1_S_RREADY(2 downto 2) <= B"0";
pgassign1(5 downto 5) <= processing_system7_0_FCLK_CLK0_0(0 to 0);
pgassign1(4 downto 4) <= processing_system7_0_FCLK_CLK0_0(0 to 0);
pgassign1(3 downto 3) <= processing_system7_0_FCLK_CLK0_0(0 to 0);
pgassign1(2 downto 2) <= processing_system7_0_FCLK_CLK0_0(0 to 0);
pgassign1(1 downto 1) <= processing_system7_0_FCLK_CLK0_0(0 to 0);
pgassign1(0 downto 0) <= processing_system7_0_FCLK_CLK0_0(0 to 0);
pgassign2(3 downto 3) <= processing_system7_0_FCLK_CLK0_0(0 to 0);
pgassign2(2 downto 2) <= processing_system7_0_FCLK_CLK0_0(0 to 0);
pgassign2(1 downto 1) <= processing_system7_0_FCLK_CLK0_0(0 to 0);
pgassign2(0 downto 0) <= processing_system7_0_FCLK_CLK0_0(0 to 0);
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd12(11 downto 0) <= B"000000000000";
net_gnd16(15 downto 0) <= B"0000000000000000";
net_gnd2(1 downto 0) <= B"00";
net_gnd3(2 downto 0) <= B"000";
net_gnd32(31 downto 0) <= B"00000000000000000000000000000000";
net_gnd4(3 downto 0) <= B"0000";
net_gnd5(4 downto 0) <= B"00000";
net_gnd6(5 downto 0) <= B"000000";
net_gnd64(63 downto 0) <= B"0000000000000000000000000000000000000000000000000000000000000000";
net_gnd72(71 downto 0) <= B"000000000000000000000000000000000000000000000000000000000000000000000000";
net_gnd8(7 downto 0) <= B"00000000";
net_vcc0 <= '1';
net_vcc4(3 downto 0) <= B"1111";
axi4lite_0 : system_axi4lite_0_wrapper
port map (
INTERCONNECT_ACLK => pgassign1(5),
INTERCONNECT_ARESETN => processing_system7_0_FCLK_RESET0_N,
S_AXI_ARESET_OUT_N => axi4lite_0_S_ARESETN(0 to 0),
M_AXI_ARESET_OUT_N => axi4lite_0_M_ARESETN,
IRQ => open,
S_AXI_ACLK => pgassign1(5 downto 5),
S_AXI_AWID => axi4lite_0_S_AWID,
S_AXI_AWADDR => axi4lite_0_S_AWADDR,
S_AXI_AWLEN => axi4lite_0_S_AWLEN,
S_AXI_AWSIZE => axi4lite_0_S_AWSIZE,
S_AXI_AWBURST => axi4lite_0_S_AWBURST,
S_AXI_AWLOCK => axi4lite_0_S_AWLOCK,
S_AXI_AWCACHE => axi4lite_0_S_AWCACHE,
S_AXI_AWPROT => axi4lite_0_S_AWPROT,
S_AXI_AWQOS => axi4lite_0_S_AWQOS,
S_AXI_AWUSER => net_gnd1(0 to 0),
S_AXI_AWVALID => axi4lite_0_S_AWVALID(0 to 0),
S_AXI_AWREADY => axi4lite_0_S_AWREADY(0 to 0),
S_AXI_WID => axi4lite_0_S_WID,
S_AXI_WDATA => axi4lite_0_S_WDATA,
S_AXI_WSTRB => axi4lite_0_S_WSTRB,
S_AXI_WLAST => axi4lite_0_S_WLAST(0 to 0),
S_AXI_WUSER => net_gnd1(0 to 0),
S_AXI_WVALID => axi4lite_0_S_WVALID(0 to 0),
S_AXI_WREADY => axi4lite_0_S_WREADY(0 to 0),
S_AXI_BID => axi4lite_0_S_BID,
S_AXI_BRESP => axi4lite_0_S_BRESP,
S_AXI_BUSER => open,
S_AXI_BVALID => axi4lite_0_S_BVALID(0 to 0),
S_AXI_BREADY => axi4lite_0_S_BREADY(0 to 0),
S_AXI_ARID => axi4lite_0_S_ARID,
S_AXI_ARADDR => axi4lite_0_S_ARADDR,
S_AXI_ARLEN => axi4lite_0_S_ARLEN,
S_AXI_ARSIZE => axi4lite_0_S_ARSIZE,
S_AXI_ARBURST => axi4lite_0_S_ARBURST,
S_AXI_ARLOCK => axi4lite_0_S_ARLOCK,
S_AXI_ARCACHE => axi4lite_0_S_ARCACHE,
S_AXI_ARPROT => axi4lite_0_S_ARPROT,
S_AXI_ARQOS => axi4lite_0_S_ARQOS,
S_AXI_ARUSER => net_gnd1(0 to 0),
S_AXI_ARVALID => axi4lite_0_S_ARVALID(0 to 0),
S_AXI_ARREADY => axi4lite_0_S_ARREADY(0 to 0),
S_AXI_RID => axi4lite_0_S_RID,
S_AXI_RDATA => axi4lite_0_S_RDATA,
S_AXI_RRESP => axi4lite_0_S_RRESP,
S_AXI_RLAST => axi4lite_0_S_RLAST(0 to 0),
S_AXI_RUSER => open,
S_AXI_RVALID => axi4lite_0_S_RVALID(0 to 0),
S_AXI_RREADY => axi4lite_0_S_RREADY(0 to 0),
M_AXI_ACLK => pgassign1,
M_AXI_AWID => open,
M_AXI_AWADDR => axi4lite_0_M_AWADDR,
M_AXI_AWLEN => open,
M_AXI_AWSIZE => open,
M_AXI_AWBURST => open,
M_AXI_AWLOCK => open,
M_AXI_AWCACHE => open,
M_AXI_AWPROT => open,
M_AXI_AWREGION => open,
M_AXI_AWQOS => open,
M_AXI_AWUSER => open,
M_AXI_AWVALID => axi4lite_0_M_AWVALID,
M_AXI_AWREADY => axi4lite_0_M_AWREADY,
M_AXI_WID => open,
M_AXI_WDATA => axi4lite_0_M_WDATA,
M_AXI_WSTRB => axi4lite_0_M_WSTRB,
M_AXI_WLAST => open,
M_AXI_WUSER => open,
M_AXI_WVALID => axi4lite_0_M_WVALID,
M_AXI_WREADY => axi4lite_0_M_WREADY,
M_AXI_BID => net_gnd72,
M_AXI_BRESP => axi4lite_0_M_BRESP,
M_AXI_BUSER => net_gnd6,
M_AXI_BVALID => axi4lite_0_M_BVALID,
M_AXI_BREADY => axi4lite_0_M_BREADY,
M_AXI_ARID => open,
M_AXI_ARADDR => axi4lite_0_M_ARADDR,
M_AXI_ARLEN => open,
M_AXI_ARSIZE => open,
M_AXI_ARBURST => open,
M_AXI_ARLOCK => open,
M_AXI_ARCACHE => open,
M_AXI_ARPROT => open,
M_AXI_ARREGION => open,
M_AXI_ARQOS => open,
M_AXI_ARUSER => open,
M_AXI_ARVALID => axi4lite_0_M_ARVALID,
M_AXI_ARREADY => axi4lite_0_M_ARREADY,
M_AXI_RID => net_gnd72,
M_AXI_RDATA => axi4lite_0_M_RDATA,
M_AXI_RRESP => axi4lite_0_M_RRESP,
M_AXI_RLAST => net_gnd6,
M_AXI_RUSER => net_gnd6,
M_AXI_RVALID => axi4lite_0_M_RVALID,
M_AXI_RREADY => axi4lite_0_M_RREADY,
S_AXI_CTRL_AWADDR => net_gnd32,
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32,
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32,
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0,
INTERCONNECT_ARESET_OUT_N => open,
DEBUG_AW_TRANS_SEQ => open,
DEBUG_AW_ARB_GRANT => open,
DEBUG_AR_TRANS_SEQ => open,
DEBUG_AR_ARB_GRANT => open,
DEBUG_AW_TRANS_QUAL => open,
DEBUG_AW_ACCEPT_CNT => open,
DEBUG_AW_ACTIVE_THREAD => open,
DEBUG_AW_ACTIVE_TARGET => open,
DEBUG_AW_ACTIVE_REGION => open,
DEBUG_AW_ERROR => open,
DEBUG_AW_TARGET => open,
DEBUG_AR_TRANS_QUAL => open,
DEBUG_AR_ACCEPT_CNT => open,
DEBUG_AR_ACTIVE_THREAD => open,
DEBUG_AR_ACTIVE_TARGET => open,
DEBUG_AR_ACTIVE_REGION => open,
DEBUG_AR_ERROR => open,
DEBUG_AR_TARGET => open,
DEBUG_B_TRANS_SEQ => open,
DEBUG_R_BEAT_CNT => open,
DEBUG_R_TRANS_SEQ => open,
DEBUG_AW_ISSUING_CNT => open,
DEBUG_AR_ISSUING_CNT => open,
DEBUG_W_BEAT_CNT => open,
DEBUG_W_TRANS_SEQ => open,
DEBUG_BID_TARGET => open,
DEBUG_BID_ERROR => open,
DEBUG_RID_TARGET => open,
DEBUG_RID_ERROR => open,
DEBUG_SR_SC_ARADDR => open,
DEBUG_SR_SC_ARADDRCONTROL => open,
DEBUG_SR_SC_AWADDR => open,
DEBUG_SR_SC_AWADDRCONTROL => open,
DEBUG_SR_SC_BRESP => open,
DEBUG_SR_SC_RDATA => open,
DEBUG_SR_SC_RDATACONTROL => open,
DEBUG_SR_SC_WDATA => open,
DEBUG_SR_SC_WDATACONTROL => open,
DEBUG_SC_SF_ARADDR => open,
DEBUG_SC_SF_ARADDRCONTROL => open,
DEBUG_SC_SF_AWADDR => open,
DEBUG_SC_SF_AWADDRCONTROL => open,
DEBUG_SC_SF_BRESP => open,
DEBUG_SC_SF_RDATA => open,
DEBUG_SC_SF_RDATACONTROL => open,
DEBUG_SC_SF_WDATA => open,
DEBUG_SC_SF_WDATACONTROL => open,
DEBUG_SF_CB_ARADDR => open,
DEBUG_SF_CB_ARADDRCONTROL => open,
DEBUG_SF_CB_AWADDR => open,
DEBUG_SF_CB_AWADDRCONTROL => open,
DEBUG_SF_CB_BRESP => open,
DEBUG_SF_CB_RDATA => open,
DEBUG_SF_CB_RDATACONTROL => open,
DEBUG_SF_CB_WDATA => open,
DEBUG_SF_CB_WDATACONTROL => open,
DEBUG_CB_MF_ARADDR => open,
DEBUG_CB_MF_ARADDRCONTROL => open,
DEBUG_CB_MF_AWADDR => open,
DEBUG_CB_MF_AWADDRCONTROL => open,
DEBUG_CB_MF_BRESP => open,
DEBUG_CB_MF_RDATA => open,
DEBUG_CB_MF_RDATACONTROL => open,
DEBUG_CB_MF_WDATA => open,
DEBUG_CB_MF_WDATACONTROL => open,
DEBUG_MF_MC_ARADDR => open,
DEBUG_MF_MC_ARADDRCONTROL => open,
DEBUG_MF_MC_AWADDR => open,
DEBUG_MF_MC_AWADDRCONTROL => open,
DEBUG_MF_MC_BRESP => open,
DEBUG_MF_MC_RDATA => open,
DEBUG_MF_MC_RDATACONTROL => open,
DEBUG_MF_MC_WDATA => open,
DEBUG_MF_MC_WDATACONTROL => open,
DEBUG_MC_MP_ARADDR => open,
DEBUG_MC_MP_ARADDRCONTROL => open,
DEBUG_MC_MP_AWADDR => open,
DEBUG_MC_MP_AWADDRCONTROL => open,
DEBUG_MC_MP_BRESP => open,
DEBUG_MC_MP_RDATA => open,
DEBUG_MC_MP_RDATACONTROL => open,
DEBUG_MC_MP_WDATA => open,
DEBUG_MC_MP_WDATACONTROL => open,
DEBUG_MP_MR_ARADDR => open,
DEBUG_MP_MR_ARADDRCONTROL => open,
DEBUG_MP_MR_AWADDR => open,
DEBUG_MP_MR_AWADDRCONTROL => open,
DEBUG_MP_MR_BRESP => open,
DEBUG_MP_MR_RDATA => open,
DEBUG_MP_MR_RDATACONTROL => open,
DEBUG_MP_MR_WDATA => open,
DEBUG_MP_MR_WDATACONTROL => open
);
SWs_8Bits : system_sws_8bits_wrapper
port map (
S_AXI_ACLK => pgassign1(5),
S_AXI_ARESETN => axi4lite_0_M_ARESETN(0),
S_AXI_AWADDR => axi4lite_0_M_AWADDR(8 downto 0),
S_AXI_AWVALID => axi4lite_0_M_AWVALID(0),
S_AXI_AWREADY => axi4lite_0_M_AWREADY(0),
S_AXI_WDATA => axi4lite_0_M_WDATA(31 downto 0),
S_AXI_WSTRB => axi4lite_0_M_WSTRB(3 downto 0),
S_AXI_WVALID => axi4lite_0_M_WVALID(0),
S_AXI_WREADY => axi4lite_0_M_WREADY(0),
S_AXI_BRESP => axi4lite_0_M_BRESP(1 downto 0),
S_AXI_BVALID => axi4lite_0_M_BVALID(0),
S_AXI_BREADY => axi4lite_0_M_BREADY(0),
S_AXI_ARADDR => axi4lite_0_M_ARADDR(8 downto 0),
S_AXI_ARVALID => axi4lite_0_M_ARVALID(0),
S_AXI_ARREADY => axi4lite_0_M_ARREADY(0),
S_AXI_RDATA => axi4lite_0_M_RDATA(31 downto 0),
S_AXI_RRESP => axi4lite_0_M_RRESP(1 downto 0),
S_AXI_RVALID => axi4lite_0_M_RVALID(0),
S_AXI_RREADY => axi4lite_0_M_RREADY(0),
IP2INTC_Irpt => open,
GPIO_IO_I => SWs_8Bits_TRI_IO_I,
GPIO_IO_O => SWs_8Bits_TRI_IO_O,
GPIO_IO_T => SWs_8Bits_TRI_IO_T,
GPIO2_IO_I => net_gnd32,
GPIO2_IO_O => open,
GPIO2_IO_T => open
);
LEDs_8Bits : system_leds_8bits_wrapper
port map (
S_AXI_ACLK => pgassign1(5),
S_AXI_ARESETN => axi4lite_0_M_ARESETN(1),
S_AXI_AWADDR => axi4lite_0_M_AWADDR(40 downto 32),
S_AXI_AWVALID => axi4lite_0_M_AWVALID(1),
S_AXI_AWREADY => axi4lite_0_M_AWREADY(1),
S_AXI_WDATA => axi4lite_0_M_WDATA(63 downto 32),
S_AXI_WSTRB => axi4lite_0_M_WSTRB(7 downto 4),
S_AXI_WVALID => axi4lite_0_M_WVALID(1),
S_AXI_WREADY => axi4lite_0_M_WREADY(1),
S_AXI_BRESP => axi4lite_0_M_BRESP(3 downto 2),
S_AXI_BVALID => axi4lite_0_M_BVALID(1),
S_AXI_BREADY => axi4lite_0_M_BREADY(1),
S_AXI_ARADDR => axi4lite_0_M_ARADDR(40 downto 32),
S_AXI_ARVALID => axi4lite_0_M_ARVALID(1),
S_AXI_ARREADY => axi4lite_0_M_ARREADY(1),
S_AXI_RDATA => axi4lite_0_M_RDATA(63 downto 32),
S_AXI_RRESP => axi4lite_0_M_RRESP(3 downto 2),
S_AXI_RVALID => axi4lite_0_M_RVALID(1),
S_AXI_RREADY => axi4lite_0_M_RREADY(1),
IP2INTC_Irpt => open,
GPIO_IO_I => net_gnd8,
GPIO_IO_O => LEDs_8Bits_TRI_IO,
GPIO_IO_T => open,
GPIO2_IO_I => net_gnd32,
GPIO2_IO_O => open,
GPIO2_IO_T => open
);
BTNs_5Bits : system_btns_5bits_wrapper
port map (
S_AXI_ACLK => pgassign1(5),
S_AXI_ARESETN => axi4lite_0_M_ARESETN(2),
S_AXI_AWADDR => axi4lite_0_M_AWADDR(72 downto 64),
S_AXI_AWVALID => axi4lite_0_M_AWVALID(2),
S_AXI_AWREADY => axi4lite_0_M_AWREADY(2),
S_AXI_WDATA => axi4lite_0_M_WDATA(95 downto 64),
S_AXI_WSTRB => axi4lite_0_M_WSTRB(11 downto 8),
S_AXI_WVALID => axi4lite_0_M_WVALID(2),
S_AXI_WREADY => axi4lite_0_M_WREADY(2),
S_AXI_BRESP => axi4lite_0_M_BRESP(5 downto 4),
S_AXI_BVALID => axi4lite_0_M_BVALID(2),
S_AXI_BREADY => axi4lite_0_M_BREADY(2),
S_AXI_ARADDR => axi4lite_0_M_ARADDR(72 downto 64),
S_AXI_ARVALID => axi4lite_0_M_ARVALID(2),
S_AXI_ARREADY => axi4lite_0_M_ARREADY(2),
S_AXI_RDATA => axi4lite_0_M_RDATA(95 downto 64),
S_AXI_RRESP => axi4lite_0_M_RRESP(5 downto 4),
S_AXI_RVALID => axi4lite_0_M_RVALID(2),
S_AXI_RREADY => axi4lite_0_M_RREADY(2),
IP2INTC_Irpt => open,
GPIO_IO_I => BTNs_5Bits_TRI_IO_I,
GPIO_IO_O => BTNs_5Bits_TRI_IO_O,
GPIO_IO_T => BTNs_5Bits_TRI_IO_T,
GPIO2_IO_I => net_gnd32,
GPIO2_IO_O => open,
GPIO2_IO_T => open
);
axi_dma_0 : system_axi_dma_0_wrapper
port map (
s_axi_lite_aclk => pgassign1(5),
m_axi_sg_aclk => pgassign1(5),
m_axi_mm2s_aclk => pgassign1(5),
m_axi_s2mm_aclk => pgassign1(5),
axi_resetn => axi4lite_0_M_ARESETN(3),
s_axi_lite_awvalid => axi4lite_0_M_AWVALID(3),
s_axi_lite_awready => axi4lite_0_M_AWREADY(3),
s_axi_lite_awaddr => axi4lite_0_M_AWADDR(105 downto 96),
s_axi_lite_wvalid => axi4lite_0_M_WVALID(3),
s_axi_lite_wready => axi4lite_0_M_WREADY(3),
s_axi_lite_wdata => axi4lite_0_M_WDATA(127 downto 96),
s_axi_lite_bresp => axi4lite_0_M_BRESP(7 downto 6),
s_axi_lite_bvalid => axi4lite_0_M_BVALID(3),
s_axi_lite_bready => axi4lite_0_M_BREADY(3),
s_axi_lite_arvalid => axi4lite_0_M_ARVALID(3),
s_axi_lite_arready => axi4lite_0_M_ARREADY(3),
s_axi_lite_araddr => axi4lite_0_M_ARADDR(105 downto 96),
s_axi_lite_rvalid => axi4lite_0_M_RVALID(3),
s_axi_lite_rready => axi4lite_0_M_RREADY(3),
s_axi_lite_rdata => axi4lite_0_M_RDATA(127 downto 96),
s_axi_lite_rresp => axi4lite_0_M_RRESP(7 downto 6),
m_axi_sg_awaddr => axi_interconnect_1_S_AWADDR(31 downto 0),
m_axi_sg_awlen => axi_interconnect_1_S_AWLEN(7 downto 0),
m_axi_sg_awsize => axi_interconnect_1_S_AWSIZE(2 downto 0),
m_axi_sg_awburst => axi_interconnect_1_S_AWBURST(1 downto 0),
m_axi_sg_awprot => axi_interconnect_1_S_AWPROT(2 downto 0),
m_axi_sg_awcache => axi_interconnect_1_S_AWCACHE(3 downto 0),
m_axi_sg_awuser => axi_interconnect_1_S_AWUSER(3 downto 0),
m_axi_sg_awvalid => axi_interconnect_1_S_AWVALID(0),
m_axi_sg_awready => axi_interconnect_1_S_AWREADY(0),
m_axi_sg_wdata => axi_interconnect_1_S_WDATA(31 downto 0),
m_axi_sg_wstrb => axi_interconnect_1_S_WSTRB(3 downto 0),
m_axi_sg_wlast => axi_interconnect_1_S_WLAST(0),
m_axi_sg_wvalid => axi_interconnect_1_S_WVALID(0),
m_axi_sg_wready => axi_interconnect_1_S_WREADY(0),
m_axi_sg_bresp => axi_interconnect_1_S_BRESP(1 downto 0),
m_axi_sg_bvalid => axi_interconnect_1_S_BVALID(0),
m_axi_sg_bready => axi_interconnect_1_S_BREADY(0),
m_axi_sg_araddr => axi_interconnect_1_S_ARADDR(31 downto 0),
m_axi_sg_arlen => axi_interconnect_1_S_ARLEN(7 downto 0),
m_axi_sg_arsize => axi_interconnect_1_S_ARSIZE(2 downto 0),
m_axi_sg_arburst => axi_interconnect_1_S_ARBURST(1 downto 0),
m_axi_sg_arprot => axi_interconnect_1_S_ARPROT(2 downto 0),
m_axi_sg_arcache => axi_interconnect_1_S_ARCACHE(3 downto 0),
m_axi_sg_aruser => axi_interconnect_1_S_ARUSER(3 downto 0),
m_axi_sg_arvalid => axi_interconnect_1_S_ARVALID(0),
m_axi_sg_arready => axi_interconnect_1_S_ARREADY(0),
m_axi_sg_rdata => axi_interconnect_1_S_RDATA(31 downto 0),
m_axi_sg_rresp => axi_interconnect_1_S_RRESP(1 downto 0),
m_axi_sg_rlast => axi_interconnect_1_S_RLAST(0),
m_axi_sg_rvalid => axi_interconnect_1_S_RVALID(0),
m_axi_sg_rready => axi_interconnect_1_S_RREADY(0),
m_axi_mm2s_araddr => axi_interconnect_1_S_ARADDR(63 downto 32),
m_axi_mm2s_arlen => axi_interconnect_1_S_ARLEN(15 downto 8),
m_axi_mm2s_arsize => axi_interconnect_1_S_ARSIZE(5 downto 3),
m_axi_mm2s_arburst => axi_interconnect_1_S_ARBURST(3 downto 2),
m_axi_mm2s_arprot => axi_interconnect_1_S_ARPROT(5 downto 3),
m_axi_mm2s_arcache => axi_interconnect_1_S_ARCACHE(7 downto 4),
m_axi_mm2s_aruser => axi_interconnect_1_S_ARUSER(7 downto 4),
m_axi_mm2s_arvalid => axi_interconnect_1_S_ARVALID(1),
m_axi_mm2s_arready => axi_interconnect_1_S_ARREADY(1),
m_axi_mm2s_rdata => axi_interconnect_1_S_RDATA(95 downto 64),
m_axi_mm2s_rresp => axi_interconnect_1_S_RRESP(3 downto 2),
m_axi_mm2s_rlast => axi_interconnect_1_S_RLAST(1),
m_axi_mm2s_rvalid => axi_interconnect_1_S_RVALID(1),
m_axi_mm2s_rready => axi_interconnect_1_S_RREADY(1),
mm2s_prmry_reset_out_n => open,
m_axis_mm2s_tdata => axi_dma_0_M_AXIS_MM2S_TDATA,
m_axis_mm2s_tkeep => open,
m_axis_mm2s_tvalid => axi_dma_0_M_AXIS_MM2S_TVALID,
m_axis_mm2s_tready => axi_dma_0_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tlast => axi_dma_0_M_AXIS_MM2S_TLAST,
m_axis_mm2s_tuser => open,
m_axis_mm2s_tid => open,
m_axis_mm2s_tdest => open,
mm2s_cntrl_reset_out_n => open,
m_axis_mm2s_cntrl_tdata => open,
m_axis_mm2s_cntrl_tkeep => open,
m_axis_mm2s_cntrl_tvalid => open,
m_axis_mm2s_cntrl_tready => net_gnd0,
m_axis_mm2s_cntrl_tlast => open,
m_axi_s2mm_awaddr => axi_interconnect_1_S_AWADDR(95 downto 64),
m_axi_s2mm_awlen => axi_interconnect_1_S_AWLEN(23 downto 16),
m_axi_s2mm_awsize => axi_interconnect_1_S_AWSIZE(8 downto 6),
m_axi_s2mm_awburst => axi_interconnect_1_S_AWBURST(5 downto 4),
m_axi_s2mm_awprot => axi_interconnect_1_S_AWPROT(8 downto 6),
m_axi_s2mm_awcache => axi_interconnect_1_S_AWCACHE(11 downto 8),
m_axi_s2mm_awuser => axi_interconnect_1_S_AWUSER(11 downto 8),
m_axi_s2mm_awvalid => axi_interconnect_1_S_AWVALID(2),
m_axi_s2mm_awready => axi_interconnect_1_S_AWREADY(2),
m_axi_s2mm_wdata => axi_interconnect_1_S_WDATA(159 downto 128),
m_axi_s2mm_wstrb => axi_interconnect_1_S_WSTRB(19 downto 16),
m_axi_s2mm_wlast => axi_interconnect_1_S_WLAST(2),
m_axi_s2mm_wvalid => axi_interconnect_1_S_WVALID(2),
m_axi_s2mm_wready => axi_interconnect_1_S_WREADY(2),
m_axi_s2mm_bresp => axi_interconnect_1_S_BRESP(5 downto 4),
m_axi_s2mm_bvalid => axi_interconnect_1_S_BVALID(2),
m_axi_s2mm_bready => axi_interconnect_1_S_BREADY(2),
s2mm_prmry_reset_out_n => open,
s_axis_s2mm_tdata => conware_0_M_AXIS_TDATA,
s_axis_s2mm_tkeep => conware_0_M_AXIS_TKEEP,
s_axis_s2mm_tvalid => conware_0_M_AXIS_TVALID,
s_axis_s2mm_tready => conware_0_M_AXIS_TREADY,
s_axis_s2mm_tlast => conware_0_M_AXIS_TLAST,
s_axis_s2mm_tuser => net_gnd4,
s_axis_s2mm_tid => net_gnd5,
s_axis_s2mm_tdest => net_gnd5,
s2mm_sts_reset_out_n => open,
s_axis_s2mm_sts_tdata => net_gnd32,
s_axis_s2mm_sts_tkeep => net_vcc4,
s_axis_s2mm_sts_tvalid => net_gnd0,
s_axis_s2mm_sts_tready => open,
s_axis_s2mm_sts_tlast => net_gnd0,
mm2s_introut => open,
s2mm_introut => open,
axi_dma_tstvec => open
);
axi_interconnect_1 : system_axi_interconnect_1_wrapper
port map (
INTERCONNECT_ACLK => pgassign1(5),
INTERCONNECT_ARESETN => processing_system7_0_FCLK_RESET0_N,
S_AXI_ARESET_OUT_N => open,
M_AXI_ARESET_OUT_N => open,
IRQ => open,
S_AXI_ACLK => pgassign2,
S_AXI_AWID => net_gnd8,
S_AXI_AWADDR => axi_interconnect_1_S_AWADDR,
S_AXI_AWLEN => axi_interconnect_1_S_AWLEN,
S_AXI_AWSIZE => axi_interconnect_1_S_AWSIZE,
S_AXI_AWBURST => axi_interconnect_1_S_AWBURST,
S_AXI_AWLOCK => net_gnd8,
S_AXI_AWCACHE => axi_interconnect_1_S_AWCACHE,
S_AXI_AWPROT => axi_interconnect_1_S_AWPROT,
S_AXI_AWQOS => net_gnd16,
S_AXI_AWUSER => axi_interconnect_1_S_AWUSER,
S_AXI_AWVALID => axi_interconnect_1_S_AWVALID,
S_AXI_AWREADY => axi_interconnect_1_S_AWREADY,
S_AXI_WID => net_gnd8,
S_AXI_WDATA => axi_interconnect_1_S_WDATA,
S_AXI_WSTRB => axi_interconnect_1_S_WSTRB,
S_AXI_WLAST => axi_interconnect_1_S_WLAST,
S_AXI_WUSER => net_gnd4,
S_AXI_WVALID => axi_interconnect_1_S_WVALID,
S_AXI_WREADY => axi_interconnect_1_S_WREADY,
S_AXI_BID => open,
S_AXI_BRESP => axi_interconnect_1_S_BRESP,
S_AXI_BUSER => open,
S_AXI_BVALID => axi_interconnect_1_S_BVALID,
S_AXI_BREADY => axi_interconnect_1_S_BREADY,
S_AXI_ARID => net_gnd8,
S_AXI_ARADDR => axi_interconnect_1_S_ARADDR,
S_AXI_ARLEN => axi_interconnect_1_S_ARLEN,
S_AXI_ARSIZE => axi_interconnect_1_S_ARSIZE,
S_AXI_ARBURST => axi_interconnect_1_S_ARBURST,
S_AXI_ARLOCK => net_gnd8,
S_AXI_ARCACHE => axi_interconnect_1_S_ARCACHE,
S_AXI_ARPROT => axi_interconnect_1_S_ARPROT,
S_AXI_ARQOS => net_gnd16,
S_AXI_ARUSER => axi_interconnect_1_S_ARUSER,
S_AXI_ARVALID => axi_interconnect_1_S_ARVALID,
S_AXI_ARREADY => axi_interconnect_1_S_ARREADY,
S_AXI_RID => open,
S_AXI_RDATA => axi_interconnect_1_S_RDATA,
S_AXI_RRESP => axi_interconnect_1_S_RRESP,
S_AXI_RLAST => axi_interconnect_1_S_RLAST,
S_AXI_RUSER => open,
S_AXI_RVALID => axi_interconnect_1_S_RVALID,
S_AXI_RREADY => axi_interconnect_1_S_RREADY,
M_AXI_ACLK => pgassign1(5 downto 5),
M_AXI_AWID => axi_interconnect_1_M_AWID,
M_AXI_AWADDR => axi_interconnect_1_M_AWADDR,
M_AXI_AWLEN => axi_interconnect_1_M_AWLEN,
M_AXI_AWSIZE => axi_interconnect_1_M_AWSIZE,
M_AXI_AWBURST => axi_interconnect_1_M_AWBURST,
M_AXI_AWLOCK => axi_interconnect_1_M_AWLOCK,
M_AXI_AWCACHE => axi_interconnect_1_M_AWCACHE,
M_AXI_AWPROT => axi_interconnect_1_M_AWPROT,
M_AXI_AWREGION => open,
M_AXI_AWQOS => axi_interconnect_1_M_AWQOS,
M_AXI_AWUSER => open,
M_AXI_AWVALID => axi_interconnect_1_M_AWVALID(0 to 0),
M_AXI_AWREADY => axi_interconnect_1_M_AWREADY(0 to 0),
M_AXI_WID => axi_interconnect_1_M_WID,
M_AXI_WDATA => axi_interconnect_1_M_WDATA,
M_AXI_WSTRB => axi_interconnect_1_M_WSTRB,
M_AXI_WLAST => axi_interconnect_1_M_WLAST(0 to 0),
M_AXI_WUSER => open,
M_AXI_WVALID => axi_interconnect_1_M_WVALID(0 to 0),
M_AXI_WREADY => axi_interconnect_1_M_WREADY(0 to 0),
M_AXI_BID => axi_interconnect_1_M_BID,
M_AXI_BRESP => axi_interconnect_1_M_BRESP,
M_AXI_BUSER => net_gnd1(0 to 0),
M_AXI_BVALID => axi_interconnect_1_M_BVALID(0 to 0),
M_AXI_BREADY => axi_interconnect_1_M_BREADY(0 to 0),
M_AXI_ARID => axi_interconnect_1_M_ARID,
M_AXI_ARADDR => axi_interconnect_1_M_ARADDR,
M_AXI_ARLEN => axi_interconnect_1_M_ARLEN,
M_AXI_ARSIZE => axi_interconnect_1_M_ARSIZE,
M_AXI_ARBURST => axi_interconnect_1_M_ARBURST,
M_AXI_ARLOCK => axi_interconnect_1_M_ARLOCK,
M_AXI_ARCACHE => axi_interconnect_1_M_ARCACHE,
M_AXI_ARPROT => axi_interconnect_1_M_ARPROT,
M_AXI_ARREGION => open,
M_AXI_ARQOS => axi_interconnect_1_M_ARQOS,
M_AXI_ARUSER => open,
M_AXI_ARVALID => axi_interconnect_1_M_ARVALID(0 to 0),
M_AXI_ARREADY => axi_interconnect_1_M_ARREADY(0 to 0),
M_AXI_RID => axi_interconnect_1_M_RID,
M_AXI_RDATA => axi_interconnect_1_M_RDATA,
M_AXI_RRESP => axi_interconnect_1_M_RRESP,
M_AXI_RLAST => axi_interconnect_1_M_RLAST(0 to 0),
M_AXI_RUSER => net_gnd1(0 to 0),
M_AXI_RVALID => axi_interconnect_1_M_RVALID(0 to 0),
M_AXI_RREADY => axi_interconnect_1_M_RREADY(0 to 0),
S_AXI_CTRL_AWADDR => net_gnd32,
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32,
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32,
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0,
INTERCONNECT_ARESET_OUT_N => open,
DEBUG_AW_TRANS_SEQ => open,
DEBUG_AW_ARB_GRANT => open,
DEBUG_AR_TRANS_SEQ => open,
DEBUG_AR_ARB_GRANT => open,
DEBUG_AW_TRANS_QUAL => open,
DEBUG_AW_ACCEPT_CNT => open,
DEBUG_AW_ACTIVE_THREAD => open,
DEBUG_AW_ACTIVE_TARGET => open,
DEBUG_AW_ACTIVE_REGION => open,
DEBUG_AW_ERROR => open,
DEBUG_AW_TARGET => open,
DEBUG_AR_TRANS_QUAL => open,
DEBUG_AR_ACCEPT_CNT => open,
DEBUG_AR_ACTIVE_THREAD => open,
DEBUG_AR_ACTIVE_TARGET => open,
DEBUG_AR_ACTIVE_REGION => open,
DEBUG_AR_ERROR => open,
DEBUG_AR_TARGET => open,
DEBUG_B_TRANS_SEQ => open,
DEBUG_R_BEAT_CNT => open,
DEBUG_R_TRANS_SEQ => open,
DEBUG_AW_ISSUING_CNT => open,
DEBUG_AR_ISSUING_CNT => open,
DEBUG_W_BEAT_CNT => open,
DEBUG_W_TRANS_SEQ => open,
DEBUG_BID_TARGET => open,
DEBUG_BID_ERROR => open,
DEBUG_RID_TARGET => open,
DEBUG_RID_ERROR => open,
DEBUG_SR_SC_ARADDR => open,
DEBUG_SR_SC_ARADDRCONTROL => open,
DEBUG_SR_SC_AWADDR => open,
DEBUG_SR_SC_AWADDRCONTROL => open,
DEBUG_SR_SC_BRESP => open,
DEBUG_SR_SC_RDATA => open,
DEBUG_SR_SC_RDATACONTROL => open,
DEBUG_SR_SC_WDATA => open,
DEBUG_SR_SC_WDATACONTROL => open,
DEBUG_SC_SF_ARADDR => open,
DEBUG_SC_SF_ARADDRCONTROL => open,
DEBUG_SC_SF_AWADDR => open,
DEBUG_SC_SF_AWADDRCONTROL => open,
DEBUG_SC_SF_BRESP => open,
DEBUG_SC_SF_RDATA => open,
DEBUG_SC_SF_RDATACONTROL => open,
DEBUG_SC_SF_WDATA => open,
DEBUG_SC_SF_WDATACONTROL => open,
DEBUG_SF_CB_ARADDR => open,
DEBUG_SF_CB_ARADDRCONTROL => open,
DEBUG_SF_CB_AWADDR => open,
DEBUG_SF_CB_AWADDRCONTROL => open,
DEBUG_SF_CB_BRESP => open,
DEBUG_SF_CB_RDATA => open,
DEBUG_SF_CB_RDATACONTROL => open,
DEBUG_SF_CB_WDATA => open,
DEBUG_SF_CB_WDATACONTROL => open,
DEBUG_CB_MF_ARADDR => open,
DEBUG_CB_MF_ARADDRCONTROL => open,
DEBUG_CB_MF_AWADDR => open,
DEBUG_CB_MF_AWADDRCONTROL => open,
DEBUG_CB_MF_BRESP => open,
DEBUG_CB_MF_RDATA => open,
DEBUG_CB_MF_RDATACONTROL => open,
DEBUG_CB_MF_WDATA => open,
DEBUG_CB_MF_WDATACONTROL => open,
DEBUG_MF_MC_ARADDR => open,
DEBUG_MF_MC_ARADDRCONTROL => open,
DEBUG_MF_MC_AWADDR => open,
DEBUG_MF_MC_AWADDRCONTROL => open,
DEBUG_MF_MC_BRESP => open,
DEBUG_MF_MC_RDATA => open,
DEBUG_MF_MC_RDATACONTROL => open,
DEBUG_MF_MC_WDATA => open,
DEBUG_MF_MC_WDATACONTROL => open,
DEBUG_MC_MP_ARADDR => open,
DEBUG_MC_MP_ARADDRCONTROL => open,
DEBUG_MC_MP_AWADDR => open,
DEBUG_MC_MP_AWADDRCONTROL => open,
DEBUG_MC_MP_BRESP => open,
DEBUG_MC_MP_RDATA => open,
DEBUG_MC_MP_RDATACONTROL => open,
DEBUG_MC_MP_WDATA => open,
DEBUG_MC_MP_WDATACONTROL => open,
DEBUG_MP_MR_ARADDR => open,
DEBUG_MP_MR_ARADDRCONTROL => open,
DEBUG_MP_MR_AWADDR => open,
DEBUG_MP_MR_AWADDRCONTROL => open,
DEBUG_MP_MR_BRESP => open,
DEBUG_MP_MR_RDATA => open,
DEBUG_MP_MR_RDATACONTROL => open,
DEBUG_MP_MR_WDATA => open,
DEBUG_MP_MR_WDATACONTROL => open
);
v_axi4s_vid_out_0 : system_v_axi4s_vid_out_0_wrapper
port map (
aclk => net_gnd0,
rst => net_gnd0,
aresetn => axi4lite_0_S_ARESETN(0),
aclken => net_vcc0,
s_axis_video_tdata => axi_vdma_0_M_AXIS_MM2S_tdata,
s_axis_video_tvalid => axi_vdma_0_M_AXIS_MM2S_tvalid,
s_axis_video_tready => axi_vdma_0_M_AXIS_MM2S_tready,
s_axis_video_tuser => axi_vdma_0_M_AXIS_MM2S_tuser(0),
s_axis_video_tlast => axi_vdma_0_M_AXIS_MM2S_tlast,
video_out_clk => processing_system7_0_FCLK_CLK3,
video_de => open,
video_vsync => v_axi4s_vid_out_0_video_vsync,
video_hsync => v_axi4s_vid_out_0_video_hsync,
video_vblank => open,
video_hblank => open,
video_data => v_axi4s_vid_out_0_video_data,
vtg_vsync => v_tc_0_VTIMING_OUT_vsync,
vtg_hsync => v_tc_0_VTIMING_OUT_hsync,
vtg_vblank => v_tc_0_VTIMING_OUT_vblank,
vtg_hblank => v_tc_0_VTIMING_OUT_hblank,
vtg_act_vid => v_tc_0_VTIMING_OUT_active_video,
vtg_ce => v_axi4s_vid_out_0_vtg_ce,
vtg_fsync => open,
locked => open,
wr_error => open,
empty => open
);
axi_vdma_0 : system_axi_vdma_0_wrapper
port map (
s_axi_lite_aclk => pgassign1(5),
m_axi_sg_aclk => net_gnd0,
m_axi_mm2s_aclk => pgassign1(5),
m_axi_s2mm_aclk => net_gnd0,
m_axis_mm2s_aclk => pgassign1(5),
s_axis_s2mm_aclk => net_gnd0,
axi_resetn => axi4lite_0_M_ARESETN(4),
s_axi_lite_awvalid => axi4lite_0_M_AWVALID(4),
s_axi_lite_awready => axi4lite_0_M_AWREADY(4),
s_axi_lite_awaddr => axi4lite_0_M_AWADDR(136 downto 128),
s_axi_lite_wvalid => axi4lite_0_M_WVALID(4),
s_axi_lite_wready => axi4lite_0_M_WREADY(4),
s_axi_lite_wdata => axi4lite_0_M_WDATA(159 downto 128),
s_axi_lite_bresp => axi4lite_0_M_BRESP(9 downto 8),
s_axi_lite_bvalid => axi4lite_0_M_BVALID(4),
s_axi_lite_bready => axi4lite_0_M_BREADY(4),
s_axi_lite_arvalid => axi4lite_0_M_ARVALID(4),
s_axi_lite_arready => axi4lite_0_M_ARREADY(4),
s_axi_lite_araddr => axi4lite_0_M_ARADDR(136 downto 128),
s_axi_lite_rvalid => axi4lite_0_M_RVALID(4),
s_axi_lite_rready => axi4lite_0_M_RREADY(4),
s_axi_lite_rdata => axi4lite_0_M_RDATA(159 downto 128),
s_axi_lite_rresp => axi4lite_0_M_RRESP(9 downto 8),
m_axi_sg_araddr => open,
m_axi_sg_arlen => open,
m_axi_sg_arsize => open,
m_axi_sg_arburst => open,
m_axi_sg_arprot => open,
m_axi_sg_arcache => open,
m_axi_sg_arvalid => open,
m_axi_sg_arready => net_gnd0,
m_axi_sg_rdata => net_gnd32,
m_axi_sg_rresp => net_gnd2,
m_axi_sg_rlast => net_gnd0,
m_axi_sg_rvalid => net_gnd0,
m_axi_sg_rready => open,
m_axi_mm2s_araddr => axi_interconnect_1_S_ARADDR(127 downto 96),
m_axi_mm2s_arlen => axi_interconnect_1_S_ARLEN(31 downto 24),
m_axi_mm2s_arsize => axi_interconnect_1_S_ARSIZE(11 downto 9),
m_axi_mm2s_arburst => axi_interconnect_1_S_ARBURST(7 downto 6),
m_axi_mm2s_arprot => axi_interconnect_1_S_ARPROT(11 downto 9),
m_axi_mm2s_arcache => axi_interconnect_1_S_ARCACHE(15 downto 12),
m_axi_mm2s_arvalid => axi_interconnect_1_S_ARVALID(3),
m_axi_mm2s_arready => axi_interconnect_1_S_ARREADY(3),
m_axi_mm2s_rdata => axi_interconnect_1_S_RDATA(223 downto 192),
m_axi_mm2s_rresp => axi_interconnect_1_S_RRESP(7 downto 6),
m_axi_mm2s_rlast => axi_interconnect_1_S_RLAST(3),
m_axi_mm2s_rvalid => axi_interconnect_1_S_RVALID(3),
m_axi_mm2s_rready => axi_interconnect_1_S_RREADY(3),
mm2s_prmry_reset_out_n => open,
m_axis_mm2s_tdata => axi_vdma_0_M_AXIS_MM2S_tdata,
m_axis_mm2s_tkeep => open,
m_axis_mm2s_tvalid => axi_vdma_0_M_AXIS_MM2S_tvalid,
m_axis_mm2s_tready => axi_vdma_0_M_AXIS_MM2S_tready,
m_axis_mm2s_tlast => axi_vdma_0_M_AXIS_MM2S_tlast,
m_axis_mm2s_tuser => axi_vdma_0_M_AXIS_MM2S_tuser(0 to 0),
m_axi_s2mm_awaddr => open,
m_axi_s2mm_awlen => open,
m_axi_s2mm_awsize => open,
m_axi_s2mm_awburst => open,
m_axi_s2mm_awprot => open,
m_axi_s2mm_awcache => open,
m_axi_s2mm_awvalid => open,
m_axi_s2mm_awready => net_gnd0,
m_axi_s2mm_wdata => open,
m_axi_s2mm_wstrb => open,
m_axi_s2mm_wlast => open,
m_axi_s2mm_wvalid => open,
m_axi_s2mm_wready => net_gnd0,
m_axi_s2mm_bresp => net_gnd2,
m_axi_s2mm_bvalid => net_gnd0,
m_axi_s2mm_bready => open,
s2mm_prmry_reset_out_n => open,
s_axis_s2mm_tdata => net_gnd32,
s_axis_s2mm_tkeep => net_vcc4,
s_axis_s2mm_tvalid => net_gnd0,
s_axis_s2mm_tready => open,
s_axis_s2mm_tlast => net_gnd0,
s_axis_s2mm_tuser => net_gnd1(0 to 0),
mm2s_fsync => v_tc_0_fsync_out(0),
mm2s_frame_ptr_in => net_gnd6,
mm2s_frame_ptr_out => open,
mm2s_fsync_out => open,
mm2s_prmtr_update => open,
mm2s_buffer_empty => open,
mm2s_buffer_almost_empty => open,
s2mm_fsync => net_gnd0,
s2mm_frame_ptr_in => net_gnd6,
s2mm_frame_ptr_out => open,
s2mm_fsync_out => open,
s2mm_buffer_full => open,
s2mm_buffer_almost_full => open,
s2mm_prmtr_update => open,
mm2s_introut => open,
s2mm_introut => open,
axi_vdma_tstvec => open
);
v_tc_0 : system_v_tc_0_wrapper
port map (
s_axi_aclk => pgassign1(5),
s_axi_aresetn => axi4lite_0_M_ARESETN(5),
s_axi_aclken => net_vcc0,
s_axi_awaddr => axi4lite_0_M_AWADDR(168 downto 160),
s_axi_awvalid => axi4lite_0_M_AWVALID(5),
s_axi_awready => axi4lite_0_M_AWREADY(5),
s_axi_wdata => axi4lite_0_M_WDATA(191 downto 160),
s_axi_wstrb => axi4lite_0_M_WSTRB(23 downto 20),
s_axi_wvalid => axi4lite_0_M_WVALID(5),
s_axi_wready => axi4lite_0_M_WREADY(5),
s_axi_bresp => axi4lite_0_M_BRESP(11 downto 10),
s_axi_bvalid => axi4lite_0_M_BVALID(5),
s_axi_bready => axi4lite_0_M_BREADY(5),
s_axi_araddr => axi4lite_0_M_ARADDR(168 downto 160),
s_axi_arvalid => axi4lite_0_M_ARVALID(5),
s_axi_arready => axi4lite_0_M_ARREADY(5),
s_axi_rdata => axi4lite_0_M_RDATA(191 downto 160),
s_axi_rresp => axi4lite_0_M_RRESP(11 downto 10),
s_axi_rvalid => axi4lite_0_M_RVALID(5),
s_axi_rready => axi4lite_0_M_RREADY(5),
irq => open,
intc_if => open,
clk => net_gnd0,
resetn => net_vcc0,
clken => net_vcc0,
det_clken => net_vcc0,
gen_clken => v_axi4s_vid_out_0_vtg_ce,
fsync_in => net_gnd0,
vblank_in => net_gnd0,
vsync_in => net_gnd0,
hblank_in => net_gnd0,
hsync_in => net_gnd0,
active_video_in => net_gnd0,
active_chroma_in => net_gnd0,
vblank_out => v_tc_0_VTIMING_OUT_vblank,
vsync_out => v_tc_0_VTIMING_OUT_vsync,
hblank_out => v_tc_0_VTIMING_OUT_hblank,
hsync_out => v_tc_0_VTIMING_OUT_hsync,
active_video_out => v_tc_0_VTIMING_OUT_active_video,
active_chroma_out => open,
fsync_out => v_tc_0_fsync_out(0 to 0)
);
processing_system7_0 : system_processing_system7_0_wrapper
port map (
CAN0_PHY_TX => open,
CAN0_PHY_RX => net_gnd0,
CAN1_PHY_TX => open,
CAN1_PHY_RX => net_gnd0,
ENET0_GMII_TX_EN => open,
ENET0_GMII_TX_ER => open,
ENET0_MDIO_MDC => open,
ENET0_MDIO_O => open,
ENET0_MDIO_T => open,
ENET0_PTP_DELAY_REQ_RX => open,
ENET0_PTP_DELAY_REQ_TX => open,
ENET0_PTP_PDELAY_REQ_RX => open,
ENET0_PTP_PDELAY_REQ_TX => open,
ENET0_PTP_PDELAY_RESP_RX => open,
ENET0_PTP_PDELAY_RESP_TX => open,
ENET0_PTP_SYNC_FRAME_RX => open,
ENET0_PTP_SYNC_FRAME_TX => open,
ENET0_SOF_RX => open,
ENET0_SOF_TX => open,
ENET0_GMII_TXD => open,
ENET0_GMII_COL => net_gnd0,
ENET0_GMII_CRS => net_gnd0,
ENET0_EXT_INTIN => net_gnd0,
ENET0_GMII_RX_CLK => net_gnd0,
ENET0_GMII_RX_DV => net_gnd0,
ENET0_GMII_RX_ER => net_gnd0,
ENET0_GMII_TX_CLK => net_gnd0,
ENET0_MDIO_I => net_gnd0,
ENET0_GMII_RXD => net_gnd8,
ENET1_GMII_TX_EN => open,
ENET1_GMII_TX_ER => open,
ENET1_MDIO_MDC => open,
ENET1_MDIO_O => open,
ENET1_MDIO_T => open,
ENET1_PTP_DELAY_REQ_RX => open,
ENET1_PTP_DELAY_REQ_TX => open,
ENET1_PTP_PDELAY_REQ_RX => open,
ENET1_PTP_PDELAY_REQ_TX => open,
ENET1_PTP_PDELAY_RESP_RX => open,
ENET1_PTP_PDELAY_RESP_TX => open,
ENET1_PTP_SYNC_FRAME_RX => open,
ENET1_PTP_SYNC_FRAME_TX => open,
ENET1_SOF_RX => open,
ENET1_SOF_TX => open,
ENET1_GMII_TXD => open,
ENET1_GMII_COL => net_gnd0,
ENET1_GMII_CRS => net_gnd0,
ENET1_EXT_INTIN => net_gnd0,
ENET1_GMII_RX_CLK => net_gnd0,
ENET1_GMII_RX_DV => net_gnd0,
ENET1_GMII_RX_ER => net_gnd0,
ENET1_GMII_TX_CLK => net_gnd0,
ENET1_MDIO_I => net_gnd0,
ENET1_GMII_RXD => net_gnd8,
GPIO_I => net_gnd64,
GPIO_O => open,
GPIO_T => open,
I2C0_SDA_I => net_gnd0,
I2C0_SDA_O => open,
I2C0_SDA_T => open,
I2C0_SCL_I => net_gnd0,
I2C0_SCL_O => open,
I2C0_SCL_T => open,
I2C1_SDA_I => net_gnd0,
I2C1_SDA_O => open,
I2C1_SDA_T => open,
I2C1_SCL_I => net_gnd0,
I2C1_SCL_O => open,
I2C1_SCL_T => open,
PJTAG_TCK => net_gnd0,
PJTAG_TMS => net_gnd0,
PJTAG_TD_I => net_gnd0,
PJTAG_TD_T => open,
PJTAG_TD_O => open,
SDIO0_CLK => open,
SDIO0_CLK_FB => net_gnd0,
SDIO0_CMD_O => open,
SDIO0_CMD_I => net_gnd0,
SDIO0_CMD_T => open,
SDIO0_DATA_I => net_gnd4,
SDIO0_DATA_O => open,
SDIO0_DATA_T => open,
SDIO0_LED => open,
SDIO0_CDN => net_gnd0,
SDIO0_WP => net_gnd0,
SDIO0_BUSPOW => open,
SDIO0_BUSVOLT => open,
SDIO1_CLK => open,
SDIO1_CLK_FB => net_gnd0,
SDIO1_CMD_O => open,
SDIO1_CMD_I => net_gnd0,
SDIO1_CMD_T => open,
SDIO1_DATA_I => net_gnd4,
SDIO1_DATA_O => open,
SDIO1_DATA_T => open,
SDIO1_LED => open,
SDIO1_CDN => net_gnd0,
SDIO1_WP => net_gnd0,
SDIO1_BUSPOW => open,
SDIO1_BUSVOLT => open,
SPI0_SCLK_I => net_gnd0,
SPI0_SCLK_O => open,
SPI0_SCLK_T => open,
SPI0_MOSI_I => net_gnd0,
SPI0_MOSI_O => open,
SPI0_MOSI_T => open,
SPI0_MISO_I => net_gnd0,
SPI0_MISO_O => open,
SPI0_MISO_T => open,
SPI0_SS_I => net_gnd0,
SPI0_SS_O => open,
SPI0_SS1_O => open,
SPI0_SS2_O => open,
SPI0_SS_T => open,
SPI1_SCLK_I => net_gnd0,
SPI1_SCLK_O => open,
SPI1_SCLK_T => open,
SPI1_MOSI_I => net_gnd0,
SPI1_MOSI_O => open,
SPI1_MOSI_T => open,
SPI1_MISO_I => net_gnd0,
SPI1_MISO_O => open,
SPI1_MISO_T => open,
SPI1_SS_I => net_gnd0,
SPI1_SS_O => open,
SPI1_SS1_O => open,
SPI1_SS2_O => open,
SPI1_SS_T => open,
UART0_DTRN => open,
UART0_RTSN => open,
UART0_TX => open,
UART0_CTSN => net_gnd0,
UART0_DCDN => net_gnd0,
UART0_DSRN => net_gnd0,
UART0_RIN => net_gnd0,
UART0_RX => net_gnd0,
UART1_DTRN => open,
UART1_RTSN => open,
UART1_TX => open,
UART1_CTSN => net_gnd0,
UART1_DCDN => net_gnd0,
UART1_DSRN => net_gnd0,
UART1_RIN => net_gnd0,
UART1_RX => net_gnd0,
TTC0_WAVE0_OUT => open,
TTC0_WAVE1_OUT => open,
TTC0_WAVE2_OUT => open,
TTC0_CLK0_IN => net_gnd0,
TTC0_CLK1_IN => net_gnd0,
TTC0_CLK2_IN => net_gnd0,
TTC1_WAVE0_OUT => open,
TTC1_WAVE1_OUT => open,
TTC1_WAVE2_OUT => open,
TTC1_CLK0_IN => net_gnd0,
TTC1_CLK1_IN => net_gnd0,
TTC1_CLK2_IN => net_gnd0,
WDT_CLK_IN => net_gnd0,
WDT_RST_OUT => open,
TRACE_CLK => net_gnd0,
TRACE_CTL => open,
TRACE_DATA => open,
USB0_PORT_INDCTL => open,
USB1_PORT_INDCTL => open,
USB0_VBUS_PWRSELECT => open,
USB1_VBUS_PWRSELECT => open,
USB0_VBUS_PWRFAULT => net_gnd0,
USB1_VBUS_PWRFAULT => net_gnd0,
SRAM_INTIN => net_gnd0,
M_AXI_GP0_ARESETN => open,
M_AXI_GP0_ARVALID => axi4lite_0_S_ARVALID(0),
M_AXI_GP0_AWVALID => axi4lite_0_S_AWVALID(0),
M_AXI_GP0_BREADY => axi4lite_0_S_BREADY(0),
M_AXI_GP0_RREADY => axi4lite_0_S_RREADY(0),
M_AXI_GP0_WLAST => axi4lite_0_S_WLAST(0),
M_AXI_GP0_WVALID => axi4lite_0_S_WVALID(0),
M_AXI_GP0_ARID => axi4lite_0_S_ARID,
M_AXI_GP0_AWID => axi4lite_0_S_AWID,
M_AXI_GP0_WID => axi4lite_0_S_WID,
M_AXI_GP0_ARBURST => axi4lite_0_S_ARBURST,
M_AXI_GP0_ARLOCK => axi4lite_0_S_ARLOCK,
M_AXI_GP0_ARSIZE => axi4lite_0_S_ARSIZE,
M_AXI_GP0_AWBURST => axi4lite_0_S_AWBURST,
M_AXI_GP0_AWLOCK => axi4lite_0_S_AWLOCK,
M_AXI_GP0_AWSIZE => axi4lite_0_S_AWSIZE,
M_AXI_GP0_ARPROT => axi4lite_0_S_ARPROT,
M_AXI_GP0_AWPROT => axi4lite_0_S_AWPROT,
M_AXI_GP0_ARADDR => axi4lite_0_S_ARADDR,
M_AXI_GP0_AWADDR => axi4lite_0_S_AWADDR,
M_AXI_GP0_WDATA => axi4lite_0_S_WDATA,
M_AXI_GP0_ARCACHE => axi4lite_0_S_ARCACHE,
M_AXI_GP0_ARLEN => axi4lite_0_S_ARLEN(3 downto 0),
M_AXI_GP0_ARQOS => axi4lite_0_S_ARQOS,
M_AXI_GP0_AWCACHE => axi4lite_0_S_AWCACHE,
M_AXI_GP0_AWLEN => axi4lite_0_S_AWLEN(3 downto 0),
M_AXI_GP0_AWQOS => axi4lite_0_S_AWQOS,
M_AXI_GP0_WSTRB => axi4lite_0_S_WSTRB,
M_AXI_GP0_ACLK => pgassign1(5),
M_AXI_GP0_ARREADY => axi4lite_0_S_ARREADY(0),
M_AXI_GP0_AWREADY => axi4lite_0_S_AWREADY(0),
M_AXI_GP0_BVALID => axi4lite_0_S_BVALID(0),
M_AXI_GP0_RLAST => axi4lite_0_S_RLAST(0),
M_AXI_GP0_RVALID => axi4lite_0_S_RVALID(0),
M_AXI_GP0_WREADY => axi4lite_0_S_WREADY(0),
M_AXI_GP0_BID => axi4lite_0_S_BID,
M_AXI_GP0_RID => axi4lite_0_S_RID,
M_AXI_GP0_BRESP => axi4lite_0_S_BRESP,
M_AXI_GP0_RRESP => axi4lite_0_S_RRESP,
M_AXI_GP0_RDATA => axi4lite_0_S_RDATA,
M_AXI_GP1_ARESETN => open,
M_AXI_GP1_ARVALID => open,
M_AXI_GP1_AWVALID => open,
M_AXI_GP1_BREADY => open,
M_AXI_GP1_RREADY => open,
M_AXI_GP1_WLAST => open,
M_AXI_GP1_WVALID => open,
M_AXI_GP1_ARID => open,
M_AXI_GP1_AWID => open,
M_AXI_GP1_WID => open,
M_AXI_GP1_ARBURST => open,
M_AXI_GP1_ARLOCK => open,
M_AXI_GP1_ARSIZE => open,
M_AXI_GP1_AWBURST => open,
M_AXI_GP1_AWLOCK => open,
M_AXI_GP1_AWSIZE => open,
M_AXI_GP1_ARPROT => open,
M_AXI_GP1_AWPROT => open,
M_AXI_GP1_ARADDR => open,
M_AXI_GP1_AWADDR => open,
M_AXI_GP1_WDATA => open,
M_AXI_GP1_ARCACHE => open,
M_AXI_GP1_ARLEN => open,
M_AXI_GP1_ARQOS => open,
M_AXI_GP1_AWCACHE => open,
M_AXI_GP1_AWLEN => open,
M_AXI_GP1_AWQOS => open,
M_AXI_GP1_WSTRB => open,
M_AXI_GP1_ACLK => net_gnd0,
M_AXI_GP1_ARREADY => net_gnd0,
M_AXI_GP1_AWREADY => net_gnd0,
M_AXI_GP1_BVALID => net_gnd0,
M_AXI_GP1_RLAST => net_gnd0,
M_AXI_GP1_RVALID => net_gnd0,
M_AXI_GP1_WREADY => net_gnd0,
M_AXI_GP1_BID => net_gnd12,
M_AXI_GP1_RID => net_gnd12,
M_AXI_GP1_BRESP => net_gnd2,
M_AXI_GP1_RRESP => net_gnd2,
M_AXI_GP1_RDATA => net_gnd32,
S_AXI_GP0_ARESETN => open,
S_AXI_GP0_ARREADY => open,
S_AXI_GP0_AWREADY => open,
S_AXI_GP0_BVALID => open,
S_AXI_GP0_RLAST => open,
S_AXI_GP0_RVALID => open,
S_AXI_GP0_WREADY => open,
S_AXI_GP0_BRESP => open,
S_AXI_GP0_RRESP => open,
S_AXI_GP0_RDATA => open,
S_AXI_GP0_BID => open,
S_AXI_GP0_RID => open,
S_AXI_GP0_ACLK => net_gnd0,
S_AXI_GP0_ARVALID => net_gnd0,
S_AXI_GP0_AWVALID => net_gnd0,
S_AXI_GP0_BREADY => net_gnd0,
S_AXI_GP0_RREADY => net_gnd0,
S_AXI_GP0_WLAST => net_gnd0,
S_AXI_GP0_WVALID => net_gnd0,
S_AXI_GP0_ARBURST => net_gnd2,
S_AXI_GP0_ARLOCK => net_gnd2,
S_AXI_GP0_ARSIZE => net_gnd3,
S_AXI_GP0_AWBURST => net_gnd2,
S_AXI_GP0_AWLOCK => net_gnd2,
S_AXI_GP0_AWSIZE => net_gnd3,
S_AXI_GP0_ARPROT => net_gnd3,
S_AXI_GP0_AWPROT => net_gnd3,
S_AXI_GP0_ARADDR => net_gnd32,
S_AXI_GP0_AWADDR => net_gnd32,
S_AXI_GP0_WDATA => net_gnd32,
S_AXI_GP0_ARCACHE => net_gnd4,
S_AXI_GP0_ARLEN => net_gnd4,
S_AXI_GP0_ARQOS => net_gnd4,
S_AXI_GP0_AWCACHE => net_gnd4,
S_AXI_GP0_AWLEN => net_gnd4,
S_AXI_GP0_AWQOS => net_gnd4,
S_AXI_GP0_WSTRB => net_gnd4,
S_AXI_GP0_ARID => net_gnd6,
S_AXI_GP0_AWID => net_gnd6,
S_AXI_GP0_WID => net_gnd6,
S_AXI_GP1_ARESETN => open,
S_AXI_GP1_ARREADY => open,
S_AXI_GP1_AWREADY => open,
S_AXI_GP1_BVALID => open,
S_AXI_GP1_RLAST => open,
S_AXI_GP1_RVALID => open,
S_AXI_GP1_WREADY => open,
S_AXI_GP1_BRESP => open,
S_AXI_GP1_RRESP => open,
S_AXI_GP1_RDATA => open,
S_AXI_GP1_BID => open,
S_AXI_GP1_RID => open,
S_AXI_GP1_ACLK => net_gnd0,
S_AXI_GP1_ARVALID => net_gnd0,
S_AXI_GP1_AWVALID => net_gnd0,
S_AXI_GP1_BREADY => net_gnd0,
S_AXI_GP1_RREADY => net_gnd0,
S_AXI_GP1_WLAST => net_gnd0,
S_AXI_GP1_WVALID => net_gnd0,
S_AXI_GP1_ARBURST => net_gnd2,
S_AXI_GP1_ARLOCK => net_gnd2,
S_AXI_GP1_ARSIZE => net_gnd3,
S_AXI_GP1_AWBURST => net_gnd2,
S_AXI_GP1_AWLOCK => net_gnd2,
S_AXI_GP1_AWSIZE => net_gnd3,
S_AXI_GP1_ARPROT => net_gnd3,
S_AXI_GP1_AWPROT => net_gnd3,
S_AXI_GP1_ARADDR => net_gnd32,
S_AXI_GP1_AWADDR => net_gnd32,
S_AXI_GP1_WDATA => net_gnd32,
S_AXI_GP1_ARCACHE => net_gnd4,
S_AXI_GP1_ARLEN => net_gnd4,
S_AXI_GP1_ARQOS => net_gnd4,
S_AXI_GP1_AWCACHE => net_gnd4,
S_AXI_GP1_AWLEN => net_gnd4,
S_AXI_GP1_AWQOS => net_gnd4,
S_AXI_GP1_WSTRB => net_gnd4,
S_AXI_GP1_ARID => net_gnd6,
S_AXI_GP1_AWID => net_gnd6,
S_AXI_GP1_WID => net_gnd6,
S_AXI_ACP_ARESETN => open,
S_AXI_ACP_AWREADY => open,
S_AXI_ACP_ARREADY => open,
S_AXI_ACP_BVALID => open,
S_AXI_ACP_RLAST => open,
S_AXI_ACP_RVALID => open,
S_AXI_ACP_WREADY => open,
S_AXI_ACP_BRESP => open,
S_AXI_ACP_RRESP => open,
S_AXI_ACP_BID => open,
S_AXI_ACP_RID => open,
S_AXI_ACP_RDATA => open,
S_AXI_ACP_ACLK => net_gnd0,
S_AXI_ACP_ARVALID => net_gnd0,
S_AXI_ACP_AWVALID => net_gnd0,
S_AXI_ACP_BREADY => net_gnd0,
S_AXI_ACP_RREADY => net_gnd0,
S_AXI_ACP_WLAST => net_gnd0,
S_AXI_ACP_WVALID => net_gnd0,
S_AXI_ACP_ARID => net_gnd3,
S_AXI_ACP_ARPROT => net_gnd3,
S_AXI_ACP_AWID => net_gnd3,
S_AXI_ACP_AWPROT => net_gnd3,
S_AXI_ACP_WID => net_gnd3,
S_AXI_ACP_ARADDR => net_gnd32,
S_AXI_ACP_AWADDR => net_gnd32,
S_AXI_ACP_ARCACHE => net_gnd4,
S_AXI_ACP_ARLEN => net_gnd4,
S_AXI_ACP_ARQOS => net_gnd4,
S_AXI_ACP_AWCACHE => net_gnd4,
S_AXI_ACP_AWLEN => net_gnd4,
S_AXI_ACP_AWQOS => net_gnd4,
S_AXI_ACP_ARBURST => net_gnd2,
S_AXI_ACP_ARLOCK => net_gnd2,
S_AXI_ACP_ARSIZE => net_gnd3,
S_AXI_ACP_AWBURST => net_gnd2,
S_AXI_ACP_AWLOCK => net_gnd2,
S_AXI_ACP_AWSIZE => net_gnd3,
S_AXI_ACP_ARUSER => net_gnd5,
S_AXI_ACP_AWUSER => net_gnd5,
S_AXI_ACP_WDATA => net_gnd64,
S_AXI_ACP_WSTRB => net_gnd8,
S_AXI_HP0_ARESETN => open,
S_AXI_HP0_ARREADY => axi_interconnect_1_M_ARREADY(0),
S_AXI_HP0_AWREADY => axi_interconnect_1_M_AWREADY(0),
S_AXI_HP0_BVALID => axi_interconnect_1_M_BVALID(0),
S_AXI_HP0_RLAST => axi_interconnect_1_M_RLAST(0),
S_AXI_HP0_RVALID => axi_interconnect_1_M_RVALID(0),
S_AXI_HP0_WREADY => axi_interconnect_1_M_WREADY(0),
S_AXI_HP0_BRESP => axi_interconnect_1_M_BRESP,
S_AXI_HP0_RRESP => axi_interconnect_1_M_RRESP,
S_AXI_HP0_BID => axi_interconnect_1_M_BID,
S_AXI_HP0_RID => axi_interconnect_1_M_RID,
S_AXI_HP0_RDATA => axi_interconnect_1_M_RDATA,
S_AXI_HP0_RCOUNT => open,
S_AXI_HP0_WCOUNT => open,
S_AXI_HP0_RACOUNT => open,
S_AXI_HP0_WACOUNT => open,
S_AXI_HP0_ACLK => pgassign1(5),
S_AXI_HP0_ARVALID => axi_interconnect_1_M_ARVALID(0),
S_AXI_HP0_AWVALID => axi_interconnect_1_M_AWVALID(0),
S_AXI_HP0_BREADY => axi_interconnect_1_M_BREADY(0),
S_AXI_HP0_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP0_RREADY => axi_interconnect_1_M_RREADY(0),
S_AXI_HP0_WLAST => axi_interconnect_1_M_WLAST(0),
S_AXI_HP0_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP0_WVALID => axi_interconnect_1_M_WVALID(0),
S_AXI_HP0_ARBURST => axi_interconnect_1_M_ARBURST,
S_AXI_HP0_ARLOCK => axi_interconnect_1_M_ARLOCK,
S_AXI_HP0_ARSIZE => axi_interconnect_1_M_ARSIZE,
S_AXI_HP0_AWBURST => axi_interconnect_1_M_AWBURST,
S_AXI_HP0_AWLOCK => axi_interconnect_1_M_AWLOCK,
S_AXI_HP0_AWSIZE => axi_interconnect_1_M_AWSIZE,
S_AXI_HP0_ARPROT => axi_interconnect_1_M_ARPROT,
S_AXI_HP0_AWPROT => axi_interconnect_1_M_AWPROT,
S_AXI_HP0_ARADDR => axi_interconnect_1_M_ARADDR,
S_AXI_HP0_AWADDR => axi_interconnect_1_M_AWADDR,
S_AXI_HP0_ARCACHE => axi_interconnect_1_M_ARCACHE,
S_AXI_HP0_ARLEN => axi_interconnect_1_M_ARLEN(3 downto 0),
S_AXI_HP0_ARQOS => axi_interconnect_1_M_ARQOS,
S_AXI_HP0_AWCACHE => axi_interconnect_1_M_AWCACHE,
S_AXI_HP0_AWLEN => axi_interconnect_1_M_AWLEN(3 downto 0),
S_AXI_HP0_AWQOS => axi_interconnect_1_M_AWQOS,
S_AXI_HP0_ARID => axi_interconnect_1_M_ARID,
S_AXI_HP0_AWID => axi_interconnect_1_M_AWID,
S_AXI_HP0_WID => axi_interconnect_1_M_WID,
S_AXI_HP0_WDATA => axi_interconnect_1_M_WDATA,
S_AXI_HP0_WSTRB => axi_interconnect_1_M_WSTRB,
S_AXI_HP1_ARESETN => open,
S_AXI_HP1_ARREADY => open,
S_AXI_HP1_AWREADY => open,
S_AXI_HP1_BVALID => open,
S_AXI_HP1_RLAST => open,
S_AXI_HP1_RVALID => open,
S_AXI_HP1_WREADY => open,
S_AXI_HP1_BRESP => open,
S_AXI_HP1_RRESP => open,
S_AXI_HP1_BID => open,
S_AXI_HP1_RID => open,
S_AXI_HP1_RDATA => open,
S_AXI_HP1_RCOUNT => open,
S_AXI_HP1_WCOUNT => open,
S_AXI_HP1_RACOUNT => open,
S_AXI_HP1_WACOUNT => open,
S_AXI_HP1_ACLK => net_gnd0,
S_AXI_HP1_ARVALID => net_gnd0,
S_AXI_HP1_AWVALID => net_gnd0,
S_AXI_HP1_BREADY => net_gnd0,
S_AXI_HP1_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP1_RREADY => net_gnd0,
S_AXI_HP1_WLAST => net_gnd0,
S_AXI_HP1_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP1_WVALID => net_gnd0,
S_AXI_HP1_ARBURST => net_gnd2,
S_AXI_HP1_ARLOCK => net_gnd2,
S_AXI_HP1_ARSIZE => net_gnd3,
S_AXI_HP1_AWBURST => net_gnd2,
S_AXI_HP1_AWLOCK => net_gnd2,
S_AXI_HP1_AWSIZE => net_gnd3,
S_AXI_HP1_ARPROT => net_gnd3,
S_AXI_HP1_AWPROT => net_gnd3,
S_AXI_HP1_ARADDR => net_gnd32,
S_AXI_HP1_AWADDR => net_gnd32,
S_AXI_HP1_ARCACHE => net_gnd4,
S_AXI_HP1_ARLEN => net_gnd4,
S_AXI_HP1_ARQOS => net_gnd4,
S_AXI_HP1_AWCACHE => net_gnd4,
S_AXI_HP1_AWLEN => net_gnd4,
S_AXI_HP1_AWQOS => net_gnd4,
S_AXI_HP1_ARID => net_gnd6,
S_AXI_HP1_AWID => net_gnd6,
S_AXI_HP1_WID => net_gnd6,
S_AXI_HP1_WDATA => net_gnd64,
S_AXI_HP1_WSTRB => net_gnd8,
S_AXI_HP2_ARESETN => open,
S_AXI_HP2_ARREADY => open,
S_AXI_HP2_AWREADY => open,
S_AXI_HP2_BVALID => open,
S_AXI_HP2_RLAST => open,
S_AXI_HP2_RVALID => open,
S_AXI_HP2_WREADY => open,
S_AXI_HP2_BRESP => open,
S_AXI_HP2_RRESP => open,
S_AXI_HP2_BID => open,
S_AXI_HP2_RID => open,
S_AXI_HP2_RDATA => open,
S_AXI_HP2_RCOUNT => open,
S_AXI_HP2_WCOUNT => open,
S_AXI_HP2_RACOUNT => open,
S_AXI_HP2_WACOUNT => open,
S_AXI_HP2_ACLK => net_gnd0,
S_AXI_HP2_ARVALID => net_gnd0,
S_AXI_HP2_AWVALID => net_gnd0,
S_AXI_HP2_BREADY => net_gnd0,
S_AXI_HP2_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP2_RREADY => net_gnd0,
S_AXI_HP2_WLAST => net_gnd0,
S_AXI_HP2_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP2_WVALID => net_gnd0,
S_AXI_HP2_ARBURST => net_gnd2,
S_AXI_HP2_ARLOCK => net_gnd2,
S_AXI_HP2_ARSIZE => net_gnd3,
S_AXI_HP2_AWBURST => net_gnd2,
S_AXI_HP2_AWLOCK => net_gnd2,
S_AXI_HP2_AWSIZE => net_gnd3,
S_AXI_HP2_ARPROT => net_gnd3,
S_AXI_HP2_AWPROT => net_gnd3,
S_AXI_HP2_ARADDR => net_gnd32,
S_AXI_HP2_AWADDR => net_gnd32,
S_AXI_HP2_ARCACHE => net_gnd4,
S_AXI_HP2_ARLEN => net_gnd4,
S_AXI_HP2_ARQOS => net_gnd4,
S_AXI_HP2_AWCACHE => net_gnd4,
S_AXI_HP2_AWLEN => net_gnd4,
S_AXI_HP2_AWQOS => net_gnd4,
S_AXI_HP2_ARID => net_gnd6,
S_AXI_HP2_AWID => net_gnd6,
S_AXI_HP2_WID => net_gnd6,
S_AXI_HP2_WDATA => net_gnd64,
S_AXI_HP2_WSTRB => net_gnd8,
S_AXI_HP3_ARESETN => open,
S_AXI_HP3_ARREADY => open,
S_AXI_HP3_AWREADY => open,
S_AXI_HP3_BVALID => open,
S_AXI_HP3_RLAST => open,
S_AXI_HP3_RVALID => open,
S_AXI_HP3_WREADY => open,
S_AXI_HP3_BRESP => open,
S_AXI_HP3_RRESP => open,
S_AXI_HP3_BID => open,
S_AXI_HP3_RID => open,
S_AXI_HP3_RDATA => open,
S_AXI_HP3_RCOUNT => open,
S_AXI_HP3_WCOUNT => open,
S_AXI_HP3_RACOUNT => open,
S_AXI_HP3_WACOUNT => open,
S_AXI_HP3_ACLK => net_gnd0,
S_AXI_HP3_ARVALID => net_gnd0,
S_AXI_HP3_AWVALID => net_gnd0,
S_AXI_HP3_BREADY => net_gnd0,
S_AXI_HP3_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP3_RREADY => net_gnd0,
S_AXI_HP3_WLAST => net_gnd0,
S_AXI_HP3_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP3_WVALID => net_gnd0,
S_AXI_HP3_ARBURST => net_gnd2,
S_AXI_HP3_ARLOCK => net_gnd2,
S_AXI_HP3_ARSIZE => net_gnd3,
S_AXI_HP3_AWBURST => net_gnd2,
S_AXI_HP3_AWLOCK => net_gnd2,
S_AXI_HP3_AWSIZE => net_gnd3,
S_AXI_HP3_ARPROT => net_gnd3,
S_AXI_HP3_AWPROT => net_gnd3,
S_AXI_HP3_ARADDR => net_gnd32,
S_AXI_HP3_AWADDR => net_gnd32,
S_AXI_HP3_ARCACHE => net_gnd4,
S_AXI_HP3_ARLEN => net_gnd4,
S_AXI_HP3_ARQOS => net_gnd4,
S_AXI_HP3_AWCACHE => net_gnd4,
S_AXI_HP3_AWLEN => net_gnd4,
S_AXI_HP3_AWQOS => net_gnd4,
S_AXI_HP3_ARID => net_gnd6,
S_AXI_HP3_AWID => net_gnd6,
S_AXI_HP3_WID => net_gnd6,
S_AXI_HP3_WDATA => net_gnd64,
S_AXI_HP3_WSTRB => net_gnd8,
DMA0_DATYPE => open,
DMA0_DAVALID => open,
DMA0_DRREADY => open,
DMA0_RSTN => open,
DMA0_ACLK => net_gnd0,
DMA0_DAREADY => net_gnd0,
DMA0_DRLAST => net_gnd0,
DMA0_DRVALID => net_gnd0,
DMA0_DRTYPE => net_gnd2,
DMA1_DATYPE => open,
DMA1_DAVALID => open,
DMA1_DRREADY => open,
DMA1_RSTN => open,
DMA1_ACLK => net_gnd0,
DMA1_DAREADY => net_gnd0,
DMA1_DRLAST => net_gnd0,
DMA1_DRVALID => net_gnd0,
DMA1_DRTYPE => net_gnd2,
DMA2_DATYPE => open,
DMA2_DAVALID => open,
DMA2_DRREADY => open,
DMA2_RSTN => open,
DMA2_ACLK => net_gnd0,
DMA2_DAREADY => net_gnd0,
DMA2_DRLAST => net_gnd0,
DMA2_DRVALID => net_gnd0,
DMA3_DRVALID => net_gnd0,
DMA3_DATYPE => open,
DMA3_DAVALID => open,
DMA3_DRREADY => open,
DMA3_RSTN => open,
DMA3_ACLK => net_gnd0,
DMA3_DAREADY => net_gnd0,
DMA3_DRLAST => net_gnd0,
DMA2_DRTYPE => net_gnd2,
DMA3_DRTYPE => net_gnd2,
FTMD_TRACEIN_DATA => net_gnd32,
FTMD_TRACEIN_VALID => net_gnd0,
FTMD_TRACEIN_CLK => net_gnd0,
FTMD_TRACEIN_ATID => net_gnd4,
FTMT_F2P_TRIG => net_gnd4,
FTMT_F2P_TRIGACK => open,
FTMT_F2P_DEBUG => net_gnd32,
FTMT_P2F_TRIGACK => net_gnd4,
FTMT_P2F_TRIG => open,
FTMT_P2F_DEBUG => open,
FCLK_CLK3 => processing_system7_0_FCLK_CLK3,
FCLK_CLK2 => open,
FCLK_CLK1 => open,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0_0(0),
FCLK_CLKTRIG3_N => net_gnd0,
FCLK_CLKTRIG2_N => net_gnd0,
FCLK_CLKTRIG1_N => net_gnd0,
FCLK_CLKTRIG0_N => net_gnd0,
FCLK_RESET3_N => open,
FCLK_RESET2_N => open,
FCLK_RESET1_N => open,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
FPGA_IDLE_N => net_gnd0,
DDR_ARB => net_gnd4,
IRQ_F2P => net_gnd1(0 to 0),
Core0_nFIQ => net_gnd0,
Core0_nIRQ => net_gnd0,
Core1_nFIQ => net_gnd0,
Core1_nIRQ => net_gnd0,
EVENT_EVENTO => open,
EVENT_STANDBYWFE => open,
EVENT_STANDBYWFI => open,
EVENT_EVENTI => net_gnd0,
MIO => processing_system7_0_MIO,
DDR_Clk => processing_system7_0_DDR_Clk,
DDR_Clk_n => processing_system7_0_DDR_Clk_n,
DDR_CKE => processing_system7_0_DDR_CKE,
DDR_CS_n => processing_system7_0_DDR_CS_n,
DDR_RAS_n => processing_system7_0_DDR_RAS_n,
DDR_CAS_n => processing_system7_0_DDR_CAS_n,
DDR_WEB => processing_system7_0_DDR_WEB,
DDR_BankAddr => processing_system7_0_DDR_BankAddr,
DDR_Addr => processing_system7_0_DDR_Addr,
DDR_ODT => processing_system7_0_DDR_ODT,
DDR_DRSTB => processing_system7_0_DDR_DRSTB,
DDR_DQ => processing_system7_0_DDR_DQ,
DDR_DM => processing_system7_0_DDR_DM,
DDR_DQS => processing_system7_0_DDR_DQS,
DDR_DQS_n => processing_system7_0_DDR_DQS_n,
DDR_VRN => processing_system7_0_DDR_VRN,
DDR_VRP => processing_system7_0_DDR_VRP,
PS_SRSTB => processing_system7_0_PS_SRSTB,
PS_CLK => processing_system7_0_PS_CLK,
PS_PORB => processing_system7_0_PS_PORB,
IRQ_P2F_DMAC_ABORT => open,
IRQ_P2F_DMAC0 => open,
IRQ_P2F_DMAC1 => open,
IRQ_P2F_DMAC2 => open,
IRQ_P2F_DMAC3 => open,
IRQ_P2F_DMAC4 => open,
IRQ_P2F_DMAC5 => open,
IRQ_P2F_DMAC6 => open,
IRQ_P2F_DMAC7 => open,
IRQ_P2F_SMC => open,
IRQ_P2F_QSPI => open,
IRQ_P2F_CTI => open,
IRQ_P2F_GPIO => open,
IRQ_P2F_USB0 => open,
IRQ_P2F_ENET0 => open,
IRQ_P2F_ENET_WAKE0 => open,
IRQ_P2F_SDIO0 => open,
IRQ_P2F_I2C0 => open,
IRQ_P2F_SPI0 => open,
IRQ_P2F_UART0 => open,
IRQ_P2F_CAN0 => open,
IRQ_P2F_USB1 => open,
IRQ_P2F_ENET1 => open,
IRQ_P2F_ENET_WAKE1 => open,
IRQ_P2F_SDIO1 => open,
IRQ_P2F_I2C1 => open,
IRQ_P2F_SPI1 => open,
IRQ_P2F_UART1 => open,
IRQ_P2F_CAN1 => open
);
conware_0 : system_conware_0_wrapper
port map (
ACLK => pgassign1(5),
ARESETN => processing_system7_0_FCLK_RESET0_N,
S_AXIS_TREADY => axi_dma_0_M_AXIS_MM2S_TREADY,
S_AXIS_TDATA => axi_dma_0_M_AXIS_MM2S_TDATA,
S_AXIS_TLAST => axi_dma_0_M_AXIS_MM2S_TLAST,
S_AXIS_TVALID => axi_dma_0_M_AXIS_MM2S_TVALID,
M_AXIS_TVALID => conware_0_M_AXIS_TVALID,
M_AXIS_TDATA => conware_0_M_AXIS_TDATA,
M_AXIS_TLAST => conware_0_M_AXIS_TLAST,
M_AXIS_TREADY => conware_0_M_AXIS_TREADY,
M_AXIS_TKEEP => conware_0_M_AXIS_TKEEP,
M_AXIS_TSTRB => open,
in_states => open,
out_states => open,
num_reads => open,
num_writes => open,
read_ctr => open,
write_ctr => open
);
iobuf_0 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(7),
IO => SWs_8Bits_TRI_IO(7),
O => SWs_8Bits_TRI_IO_I(7),
T => SWs_8Bits_TRI_IO_T(7)
);
iobuf_1 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(6),
IO => SWs_8Bits_TRI_IO(6),
O => SWs_8Bits_TRI_IO_I(6),
T => SWs_8Bits_TRI_IO_T(6)
);
iobuf_2 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(5),
IO => SWs_8Bits_TRI_IO(5),
O => SWs_8Bits_TRI_IO_I(5),
T => SWs_8Bits_TRI_IO_T(5)
);
iobuf_3 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(4),
IO => SWs_8Bits_TRI_IO(4),
O => SWs_8Bits_TRI_IO_I(4),
T => SWs_8Bits_TRI_IO_T(4)
);
iobuf_4 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(3),
IO => SWs_8Bits_TRI_IO(3),
O => SWs_8Bits_TRI_IO_I(3),
T => SWs_8Bits_TRI_IO_T(3)
);
iobuf_5 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(2),
IO => SWs_8Bits_TRI_IO(2),
O => SWs_8Bits_TRI_IO_I(2),
T => SWs_8Bits_TRI_IO_T(2)
);
iobuf_6 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(1),
IO => SWs_8Bits_TRI_IO(1),
O => SWs_8Bits_TRI_IO_I(1),
T => SWs_8Bits_TRI_IO_T(1)
);
iobuf_7 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(0),
IO => SWs_8Bits_TRI_IO(0),
O => SWs_8Bits_TRI_IO_I(0),
T => SWs_8Bits_TRI_IO_T(0)
);
iobuf_8 : IOBUF
port map (
I => BTNs_5Bits_TRI_IO_O(4),
IO => BTNs_5Bits_TRI_IO(4),
O => BTNs_5Bits_TRI_IO_I(4),
T => BTNs_5Bits_TRI_IO_T(4)
);
iobuf_9 : IOBUF
port map (
I => BTNs_5Bits_TRI_IO_O(3),
IO => BTNs_5Bits_TRI_IO(3),
O => BTNs_5Bits_TRI_IO_I(3),
T => BTNs_5Bits_TRI_IO_T(3)
);
iobuf_10 : IOBUF
port map (
I => BTNs_5Bits_TRI_IO_O(2),
IO => BTNs_5Bits_TRI_IO(2),
O => BTNs_5Bits_TRI_IO_I(2),
T => BTNs_5Bits_TRI_IO_T(2)
);
iobuf_11 : IOBUF
port map (
I => BTNs_5Bits_TRI_IO_O(1),
IO => BTNs_5Bits_TRI_IO(1),
O => BTNs_5Bits_TRI_IO_I(1),
T => BTNs_5Bits_TRI_IO_T(1)
);
iobuf_12 : IOBUF
port map (
I => BTNs_5Bits_TRI_IO_O(0),
IO => BTNs_5Bits_TRI_IO(0),
O => BTNs_5Bits_TRI_IO_I(0),
T => BTNs_5Bits_TRI_IO_T(0)
);
end architecture STRUCTURE;
|
mit
|
9deef231ead499c796db2da4778d717c
| 0.61742 | 2.805895 | false | false | false | false |
igraves/vhdl-gizmos
|
devices/serializers/64-8.vhd
| 1 | 1,228 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity serialize is
port(
clk : in std_logic;
vector : in std_logic_vector(0 to 511);
output : out std_logic_vector(0 to 63)
);
end serialize;
architecture Behavioral of serialize is
begin
dev : process(clk)
variable state : std_logic_vector (0 to 2) := "000";
variable text : std_logic_vector(0 to 447);
begin
if clk'event AND clk = '1' then
if state = "000" then
text := vector(64 to 511);
output <= vector(0 to 63);
state := "001";
elsif state = "001" then
output <= text(0 to 63);
state := "010";
elsif state = "010" then
output <= text(64 to 127);
state := "011";
elsif state = "011" then
output <= text(128 to 191);
state := "100";
elsif state = "100" then
output <= text(192 to 255);
state := "101";
elsif state = "101" then
output <= text(256 to 319);
state := "110";
elsif state = "110" then
output <= text(320 to 383);
state := "111";
else
output <= text(384 to 447);
state := "000";
end if;
end if;
end process;
end Behavioral;
|
mit
|
a2de3c04d6e59d36c5c57fbe3c330b9a
| 0.531759 | 3.687688 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_Distortion_1.0/sources_1/new/Distortion.vhd
| 1 | 12,598 |
----------------------------------------------------
-- Vladi & Adi --
-- TAU EE Senior year project --
-- --
--************************************************--
--************* Distortion /Overdrive ************--
--************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Distortion is
Port ( x : in STD_LOGIC_VECTOR(31 downto 0);
y : out STD_LOGIC_VECTOR(31 downto 0);
clk_48: in std_logic;
options : in STD_LOGIC_VECTOR(0 to 3);
en : in STD_LOGIC_VECTOR(0 to 3)
);
end Distortion;
architecture Behavioral of Distortion is
signal y_temp_s : signed(31 downto 0):= x"00000000";
begin
process(clk_48, options)
begin
if en(0)= '1' then
if rising_edge(clk_48) then
if options="1000" then --weak overdrive
if signed(x(23 downto 0)) >= 70000 then
y<=std_logic_vector(to_signed(70000,32));
elsif signed(x(23 downto 0)) <= -70000 then
y<=std_logic_vector(to_signed(-70000,32));
else
y<=x;
end if;
end if;
if options="0100" then --strong overdrive
if signed(x(23 downto 0)) >= 70000 then
y<=std_logic_vector(to_signed(90000,32));
elsif signed(x(23 downto 0)) <= -70000 then
y<=std_logic_vector(to_signed(-90000,32));
else
y<=x;
end if;
end if;
if options="0010" then --overdrive
if signed(x(23 downto 0)) >= 50000 then
y <= std_logic_vector(to_signed(50000,32));
elsif signed(x(23 downto 0)) <= -50000 then
y <= std_logic_vector(to_signed(-50000,32));
else
y<=x;
end if;
end if;
if options="0001" then --distortion
if signed(x(23 downto 0)) >= 0 and signed(x(23 downto 0)) < 50 then
y<=std_logic_vector(to_signed(200,32));
elsif signed(x(23 downto 0)) >= 50 and signed(x(23 downto 0)) < 100 then
y<=std_logic_vector(to_signed(500,32));
elsif signed(x(23 downto 0)) >= 100 and signed(x(23 downto 0)) < 200 then
y<=std_logic_vector(to_signed(1000,32));
elsif signed(x(23 downto 0)) >= 200 and signed(x(23 downto 0)) < 500 then
y<=std_logic_vector(to_signed(2000,32));
elsif signed(x(23 downto 0)) >= 500 and signed(x(23 downto 0)) < 1000 then
y<=std_logic_vector(to_signed(3000,32));
elsif signed(x(23 downto 0)) >= 1000 and signed(x(23 downto 0)) < 2000 then
y<=std_logic_vector(to_signed(4000,32));
elsif signed(x(23 downto 0)) >= 2000 and signed(x(23 downto 0)) < 3000 then
y<=std_logic_vector(to_signed(5000,32));
elsif signed(x(23 downto 0)) >= 3000 and signed(x(23 downto 0)) < 4500 then
y<=std_logic_vector(to_signed(5500,32));
elsif signed(x(23 downto 0)) >= 4000 and signed(x(23 downto 0)) < 5000 then
y<=std_logic_vector(to_signed(6000,32));
elsif signed(x(23 downto 0)) >= 5000 and signed(x(23 downto 0)) < 5500 then
y<=std_logic_vector(to_signed(7000,32));
elsif signed(x(23 downto 0)) >= 5500 and signed(x(23 downto 0)) < 6000 then
y<=std_logic_vector(to_signed(8000,32));
elsif signed(x(23 downto 0)) >= 6000 and signed(x(23 downto 0)) < 6500 then
y<=std_logic_vector(to_signed(9000,32));
elsif signed(x(23 downto 0)) >= 6500 and signed(x(23 downto 0)) < 7000 then
y<=std_logic_vector(to_signed(10000,32));
elsif signed(x(23 downto 0)) >= 7000 and signed(x(23 downto 0)) < 7500 then
y<=std_logic_vector(to_signed(20000,32));
elsif signed(x(23 downto 0)) >= 7500 and signed(x(23 downto 0)) < 8000 then
y<=std_logic_vector(to_signed(30000,32));
elsif signed(x(23 downto 0)) >= 8000 and signed(x(23 downto 0)) < 8500 then
y<=std_logic_vector(to_signed(50000,32));
elsif signed(x(23 downto 0)) >= 8500 and signed(x(23 downto 0)) < 9000 then
y<=std_logic_vector(to_signed(70000,32));
elsif signed(x(23 downto 0)) >= 9000 and signed(x(23 downto 0)) < 9500 then
y<=std_logic_vector(to_signed(95000,32));
elsif signed(x(23 downto 0)) >= 9500 and signed(x(23 downto 0)) < 10000 then
y<=std_logic_vector(to_signed(105000,32));
elsif signed(x(23 downto 0)) >= 10000 and signed(x(23 downto 0)) < 15000 then
y<=std_logic_vector(to_signed(110000,32));
elsif signed(x(23 downto 0)) >= 15000 and signed(x(23 downto 0)) < 20000 then
y<=std_logic_vector(to_signed(115000,32));
elsif signed(x(23 downto 0)) >= 20000 and signed(x(23 downto 0)) < 25000 then
y<=std_logic_vector(to_signed(120000,32));
elsif signed(x(23 downto 0)) >= 25000 and signed(x(23 downto 0)) < 30000 then
y<=std_logic_vector(to_signed(125000,32));
elsif signed(x(23 downto 0)) >= 30000 and signed(x(23 downto 0)) < 35000 then
y<=std_logic_vector(to_signed(130000,32));
elsif signed(x(23 downto 0)) >= 35000 and signed(x(23 downto 0)) < 40000 then
y<=std_logic_vector(to_signed(135000,32));
elsif signed(x(23 downto 0)) >= 40000 and signed(x(23 downto 0)) < 45000 then
y<=std_logic_vector(to_signed(140000,32));
elsif signed(x(23 downto 0)) >= 45000 and signed(x(23 downto 0)) < 50000 then
y<=std_logic_vector(to_signed(145000,32));
elsif signed(x(23 downto 0)) >= 50000 and signed(x(23 downto 0)) < 60000 then
y<=std_logic_vector(to_signed(150000,32));
elsif signed(x(23 downto 0)) >= 60000 and signed(x(23 downto 0)) < 70000 then
y<=std_logic_vector(to_signed(160000,32));
elsif signed(x(23 downto 0)) >= 70000 and signed(x(23 downto 0)) < 80000 then
y<=std_logic_vector(to_signed(170000,32));
elsif signed(x(23 downto 0)) >= 80000 and signed(x(23 downto 0)) < 90000 then
y<=std_logic_vector(to_signed(180000,32));
elsif signed(x(23 downto 0)) >= 90000 and signed(x(23 downto 0)) < 100000 then
y<=std_logic_vector(to_signed(190000,32));
elsif signed(x(23 downto 0)) >= 100000 and signed(x(23 downto 0)) < 120000 then
y<=std_logic_vector(to_signed(200000,32));
elsif signed(x(23 downto 0)) >= 120000 and signed(x(23 downto 0)) < 140000 then
y<=std_logic_vector(to_signed(220000,32));
elsif signed(x(23 downto 0)) >= 140000 and signed(x(23 downto 0)) < 160000 then
y<=std_logic_vector(to_signed(240000,32));
elsif signed(x(23 downto 0)) >= 160000 and signed(x(23 downto 0)) < 170000 then
y<=std_logic_vector(to_signed(260000,32));
elsif signed(x(23 downto 0)) >= 170000 and signed(x(23 downto 0)) < 190000 then
y<=std_logic_vector(to_signed(270000,32));
elsif signed(x(23 downto 0)) >= 190000 and signed(x(23 downto 0)) < 200000 then
y<=std_logic_vector(to_signed(290000,32));
elsif signed(x(23 downto 0)) >= 200000 and signed(x(23 downto 0)) < 220000 then
y<=std_logic_vector(to_signed(300000,32));
elsif signed(x(23 downto 0)) >= 220000 and signed(x(23 downto 0)) < 240000 then
y<=std_logic_vector(to_signed(320000,32));
elsif signed(x(23 downto 0)) >= 240000 and signed(x(23 downto 0)) < 260000 then
y<=std_logic_vector(to_signed(340000,32));
elsif signed(x(23 downto 0)) >= 260000 and signed(x(23 downto 0)) < 280000 then
y<=std_logic_vector(to_signed(360000,32));
elsif signed(x(23 downto 0)) >= 280000 and signed(x(23 downto 0)) < 300000 then
y<=std_logic_vector(to_signed(380000,32));
elsif signed(x(23 downto 0)) >= 300000 then
y<=std_logic_vector(to_signed(400000,32));
elsif signed(x(23 downto 0)) <= 0 and signed(x(23 downto 0)) > -50 then
y<=std_logic_vector(to_signed(-200,32));
elsif signed(x(23 downto 0)) <= -50 and signed(x(23 downto 0)) > -100 then
y<=std_logic_vector(to_signed(-500,32));
elsif signed(x(23 downto 0)) <= -100 and signed(x(23 downto 0)) > -200 then
y<=std_logic_vector(to_signed(-1000,32));
elsif signed(x(23 downto 0)) <= -200 and signed(x(23 downto 0)) > -500 then
y<=std_logic_vector(to_signed(-2000,32));
elsif signed(x(23 downto 0)) <= -500 and signed(x(23 downto 0)) > -1000 then
y<=std_logic_vector(to_signed(-3000,32));
elsif signed(x(23 downto 0)) <= -1000 and signed(x(23 downto 0)) > -2000 then
y<=std_logic_vector(to_signed(-4000,32));
elsif signed(x(23 downto 0)) <= -2000 and signed(x(23 downto 0)) > -3000 then
y<=std_logic_vector(to_signed(-5000,32));
elsif signed(x(23 downto 0)) <= -3000 and signed(x(23 downto 0)) > -4500 then
y<=std_logic_vector(to_signed(-5500,32));
elsif signed(x(23 downto 0)) <= -4000 and signed(x(23 downto 0)) > -5000 then
y<=std_logic_vector(to_signed(-6000,32));
elsif signed(x(23 downto 0)) <= -5000 and signed(x(23 downto 0)) > -5500 then
y<=std_logic_vector(to_signed(-7000,32));
elsif signed(x(23 downto 0)) <= -5500 and signed(x(23 downto 0)) > -6000 then
y<=std_logic_vector(to_signed(-8000,32));
elsif signed(x(23 downto 0)) <= -6000 and signed(x(23 downto 0)) > -6500 then
y<=std_logic_vector(to_signed(-9000,32));
elsif signed(x(23 downto 0)) <= -6500 and signed(x(23 downto 0)) > -7000 then
y<=std_logic_vector(to_signed(-10000,32));
elsif signed(x(23 downto 0)) <= -7000 and signed(x(23 downto 0)) > -7500 then
y<=std_logic_vector(to_signed(-20000,32));
elsif signed(x(23 downto 0)) <= -7500 and signed(x(23 downto 0)) > -8000 then
y<=std_logic_vector(to_signed(-30000,32));
elsif signed(x(23 downto 0)) <= -8000 and signed(x(23 downto 0)) > -8500 then
y<=std_logic_vector(to_signed(-50000,32));
elsif signed(x(23 downto 0)) <= -8500 and signed(x(23 downto 0)) > -9000 then
y<=std_logic_vector(to_signed(-70000,32));
elsif signed(x(23 downto 0)) <= -9000 and signed(x(23 downto 0)) > -9500 then
y<=std_logic_vector(to_signed(-95000,32));
elsif signed(x(23 downto 0)) <= -9500 and signed(x(23 downto 0)) > -10000 then
y<=std_logic_vector(to_signed(-105000,32));
elsif signed(x(23 downto 0)) <= -10000 and signed(x(23 downto 0)) > -15000 then
y<=std_logic_vector(to_signed(-110000,32));
elsif signed(x(23 downto 0)) <= -15000 and signed(x(23 downto 0)) > -20000 then
y<=std_logic_vector(to_signed(-115000,32));
elsif signed(x(23 downto 0)) <= -20000 and signed(x(23 downto 0)) > -25000 then
y<=std_logic_vector(to_signed(-120000,32));
elsif signed(x(23 downto 0)) <= -25000 and signed(x(23 downto 0)) > -30000 then
y<=std_logic_vector(to_signed(-125000,32));
elsif signed(x(23 downto 0)) <= -30000 and signed(x(23 downto 0)) > -35000 then
y<=std_logic_vector(to_signed(-130000,32));
elsif signed(x(23 downto 0)) <= -35000 and signed(x(23 downto 0)) > -40000 then
y<=std_logic_vector(to_signed(-135000,32));
elsif signed(x(23 downto 0)) <= -40000 and signed(x(23 downto 0)) > -45000 then
y<=std_logic_vector(to_signed(-140000,32));
elsif signed(x(23 downto 0)) <= -45000 and signed(x(23 downto 0)) > -50000 then
y<=std_logic_vector(to_signed(-145000,32));
elsif signed(x(23 downto 0)) <= -50000 and signed(x(23 downto 0)) > -60000 then
y<=std_logic_vector(to_signed(-150000,32));
elsif signed(x(23 downto 0)) <= -60000 and signed(x(23 downto 0)) > -70000 then
y<=std_logic_vector(to_signed(-160000,32));
elsif signed(x(23 downto 0)) <= -70000 and signed(x(23 downto 0)) > -80000 then
y<=std_logic_vector(to_signed(-170000,32));
elsif signed(x(23 downto 0)) <= -80000 and signed(x(23 downto 0)) > -90000 then
y<=std_logic_vector(to_signed(-180000,32));
elsif signed(x(23 downto 0)) <= -90000 and signed(x(23 downto 0)) > -100000 then
y<=std_logic_vector(to_signed(-190000,32));
elsif signed(x(23 downto 0)) <= -100000 and signed(x(23 downto 0)) > -120000 then
y<=std_logic_vector(to_signed(-200000,32));
elsif signed(x(23 downto 0)) <= -120000 and signed(x(23 downto 0)) > -140000 then
y<=std_logic_vector(to_signed(-240000,32));
elsif signed(x(23 downto 0)) <= -140000 and signed(x(23 downto 0)) > -160000 then
y<=std_logic_vector(to_signed(-240000,32));
elsif signed(x(23 downto 0)) <= -160000 and signed(x(23 downto 0)) > -170000 then
y<=std_logic_vector(to_signed(-260000,32));
elsif signed(x(23 downto 0)) <= -170000 and signed(x(23 downto 0)) > -190000 then
y<=std_logic_vector(to_signed(-270000,32));
elsif signed(x(23 downto 0)) <= -190000 and signed(x(23 downto 0)) > -200000 then
y<=std_logic_vector(to_signed(-290000,32));
elsif signed(x(23 downto 0)) <= -200000 and signed(x(23 downto 0)) > -220000 then
y<=std_logic_vector(to_signed(-300000,32));
elsif signed(x(23 downto 0)) <= -220000 and signed(x(23 downto 0)) > -240000 then
y<=std_logic_vector(to_signed(-320000,32));
elsif signed(x(23 downto 0)) <= -240000 and signed(x(23 downto 0)) > -260000 then
y<=std_logic_vector(to_signed(-340000,32));
elsif signed(x(23 downto 0)) <= -260000 and signed(x(23 downto 0)) > -280000 then
y<=std_logic_vector(to_signed(-360000,32));
elsif signed(x(23 downto 0)) <= -280000 and signed(x(23 downto 0)) > -300000 then
y<=std_logic_vector(to_signed(-380000,32));
elsif signed(x(23 downto 0)) <= -300000 then
y<=std_logic_vector(to_signed(-400000,32));
else
y<=x;
end if;
end if;
end if; --rising_edge(clk)
else --if effect not enabled
y<=x;
end if;--en
end process;
end Behavioral;
|
mit
|
af33ce1a927e642ace1543419bac7001
| 0.658914 | 2.887463 | false | false | false | false |
SamTheDev/VGA-VHDL-Simulator
|
image_file.vhd
| 1 | 4,900 |
------------------------------------------------------------
-- VGA SimuLator projet VHDL
-- Save a picture to a spesific location on the disk
-- S. Rubini, septembre 2015
-- save one picture after the Reset is seted using the sun raster format
-- no control uppon the count of pixels
------------------------------------------------------------
library ieee;
library std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use std.all;
entity image_file is
generic ( V_SIZE, H_SIZE : integer);
port ( clk, reset : in std_logic;
r,g,b : in std_logic_vector(7 downto 0));
end image_file;
architecture test of image_file is
type IntegerFileType is file of character ;
file data_out : IntegerFileType;
signal byte_count : integer :=0;
signal wr, wb, wg : std_logic_vector(31 downto 0) := X"00000000";
function byte_reverse(w : in integer) return integer is
variable w_in, w_out : std_logic_vector(31 downto 0);
begin
w_in := conv_std_logic_vector(w, 32);
w_out(31 downto 24) := w_in(7 downto 0);
w_out(23 downto 16) := w_in(15 downto 8);
w_out(15 downto 8) := w_in(23 downto 16);
w_out(7 downto 0) := w_in(31 downto 24);
return conv_integer(w_out);
end byte_reverse;
begin
entete : process(reset)
variable status: FILE_OPEN_STATUS;
variable c : character;
variable w : std_logic_vector(31 downto 0);
begin
if reset='1' then
FILE_OPEN(status, data_out, "MireResultante.im8", write_mode);
w := X"59a66a95";
c := character'val(conv_integer(unsigned(w(31 downto 24))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(23 downto 16))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(15 downto 8))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(7 downto 0))));
write(data_out, c);
w := conv_std_logic_vector(H_SIZE,32);
c := character'val(conv_integer(unsigned(w(31 downto 24))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(23 downto 16))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(15 downto 8))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(7 downto 0))));
write(data_out, c);
w := conv_std_logic_vector(V_SIZE,32);
c := character'val(conv_integer(unsigned(w(31 downto 24))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(23 downto 16))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(15 downto 8))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(7 downto 0))));
write(data_out, c);
w := conv_std_logic_vector(24,32);
c := character'val(conv_integer(unsigned(w(31 downto 24))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(23 downto 16))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(15 downto 8))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(7 downto 0))));
write(data_out, c);
w := conv_std_logic_vector(H_SIZE*V_SIZE*3,32);
c := character'val(conv_integer(unsigned(w(31 downto 24))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(23 downto 16))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(15 downto 8))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(7 downto 0))));
write(data_out, c);
w := conv_std_logic_vector(1,32);
c := character'val(conv_integer(unsigned(w(31 downto 24))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(23 downto 16))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(15 downto 8))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(7 downto 0))));
write(data_out, c);
w := conv_std_logic_vector(0,32);
c := character'val(conv_integer(unsigned(w(31 downto 24))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(23 downto 16))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(15 downto 8))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(7 downto 0))));
write(data_out, c);
w := conv_std_logic_vector(0,32);
c := character'val(conv_integer(unsigned(w(31 downto 24))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(23 downto 16))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(15 downto 8))));
write(data_out, c);
c := character'val(conv_integer(unsigned(w(7 downto 0))));
write(data_out, c);
end if;
end process;
process(clk)
variable c : character;
begin
if reset= '0' and falling_edge(clk) then
c := character'val(conv_integer(unsigned(r)));
write(data_out, c);
c := character'val(conv_integer(unsigned(g)));
write(data_out, c);
c := character'val(conv_integer(unsigned(b)));
write(data_out, c);
end if;
end process;
end test;
|
mit
|
0e839a00aca4a32840df92265cc3b248
| 0.63898 | 3.051059 | false | false | false | false |
DanielSouzaBertoldi/VHDL
|
ProjetoFinal/Idecode.vhd
| 1 | 4,673 |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Idecode IS
PORT(
read_data_1 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
read_data_2 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Instruction : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
ALU_result : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
RegWrite : IN STD_LOGIC;
RegDst : IN STD_LOGIC;
Sign_extend : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
clock,reset : IN STD_LOGIC;
MemToReg : IN STD_LOGIC;
read_data : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Jal : IN STD_LOGIC;
L_Address : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
Reg31 : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
a1 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
a2 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
a3 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )
);
END Idecode;
ARCHITECTURE behavior OF Idecode IS
--<insira a definição do vetor de regitradores>
--32 registradores, de 0 a 31, do tipo std_logic_vector em que cada elemento do vetor tem 32 bits
TYPE register_file IS ARRAY (0 TO 31) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
--<insira os sinais internos necessários>
SIGNAL registrator : register_file;
SIGNAL write_reg_ID : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL write_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL read_Rs_ID : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL read_Rt_ID : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL write_Rd_ID : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL write_Rt_ID : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL Immediate_value : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL RegEndereco : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
-- Os sinais abaixo devem receber as identificacoes dos registradores
-- que estao definidos na instrucao, ou seja, o indice dos registradores
-- a serem utilizados na execucao da instrucao
read_Rs_ID <= Instruction(25 DOWNTO 21);
read_Rt_ID <= Instruction(20 DOWNTO 16);
write_Rd_ID <= Instruction(15 DOWNTO 11);
write_Rt_ID <= Instruction(20 DOWNTO 16);
Immediate_value <= Instruction(15 DOWNTO 0);
-- Os sinais abaixo devem receber o conteudo dos registradores, reg(i)
-- USE "CONV_INTEGER(read_Rs_ID)" para converter os bits de indice do registrador
-- para um inteiro a ser usado como indice do vetor de registradores.
-- Exemplo: dado um sinal X do tipo array de registradores,
-- X(CONV_INTEGER("00011")) recuperaria o conteudo do registrador 3.
read_data_1 <= registrator(CONV_INTEGER(read_Rs_ID)); --Converter valor binario em read_Rs_ID para inteiro usando CONV_INTEGER
read_data_2 <= registrator(CONV_INTEGER(read_Rt_ID));
-- Crie um multiplexador que seleciona o registrador de escrita de acordo com o sinal RegDst
write_reg_ID <= write_Rd_ID WHEN RegDst = '1' ELSE write_Rt_ID; --Multiplexador
-- Ligue no sinal abaixo os bits relativos ao valor a ser escrito no registrador destino.
write_data <= read_data WHEN MemToReg = '1' ELSE ALU_result;
-- Estenda o sinal de instruções do tipo I de 16-bits to 32-bits
-- Faca isto independente do tipo de instrução, mas use apenas quando
-- for instrução do tipo I.
-- Estende os bits em 0's se o número for positivo, caso contrário estende com 1's
Sign_extend <= X"0000"&Immediate_value WHEN Immediate_value(15) = '0' ELSE X"FFFF"&Immediate_value;
--Reg31 recebe o endereco contido no registrador 31
RegEndereco <= registrator(31);
Reg31 <= RegEndereco(7 DOWNTO 0);
a1 <= registrator(5);
a2 <= registrator(6);
a3 <= registrator(7);
--Process é um FF
PROCESS
BEGIN
WAIT UNTIL clock'EVENT AND clock = '1';
IF reset = '1' THEN
-- Inicializa os registradores com seu numero
FOR i IN 0 TO 31 LOOP
registrator(i) <= CONV_STD_LOGIC_VECTOR( i, 32 ); --i é um inteiro, registrator é apenas em bits, portanto precisamos converter
END LOOP;
--O registrador 32, $ra, armazena o endereço da próxima instrução antes do pulo
ELSIF Jal = '1' THEN
registrator(31) <= X"000000"&L_Address;
ELSIF RegWrite = '1' AND write_reg_ID /= X"00" THEN
-- Escreve no registrador indicado pela instrucao
registrator(CONV_INTEGER(write_reg_ID)) <= write_data;
END IF;
END PROCESS;
END behavior;
|
gpl-3.0
|
5d8d191e77ecec70e26ee23ecc175bf8
| 0.627927 | 3.685669 | false | false | false | false |
paulmoon/seng440
|
huffman/huffman_decoder.vhd
| 1 | 1,911 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:54:51 07/31/2014
-- Design Name:
-- Module Name: huffman_decoder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use std.textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity huffman_decoder is
Port ( clock : in STD_LOGIC;
encoded_string : in STD_LOGIC_VECTOR(0 to 43);
encoding : in string(1 to 6);
output_string : out string(32 downto 1));
end huffman_decoder;
architecture Behavioral of huffman_decoder is
constant code_length : integer := 43;
begin
compute : process (clock, encoded_string, encoding)
variable i : integer := 1;
variable numOutcomes : integer := 1;
variable variableFrequency : integer := 1;
begin
if rising_edge(clock) then
if i <= code_length + 1 then
report "i: " & integer'image(i);
if (encoded_string(i-1) = '0') then
report "Outcomes " & encoding(variableFrequency);
output_string(32 - numOutComes + 1) <= encoding(variableFrequency);
numOutcomes := numOutcomes + 1;
variableFrequency := 1;
else
variableFrequency := variableFrequency + 1;
end if;
i := i + 1;
end if;
end if;
end process;
end Behavioral;
|
mit
|
45ce834019b0473e3aa64985c489cf11
| 0.583987 | 3.814371 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pkg.vhd
| 1 | 11,785 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_exdes IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(5-1 DOWNTO 0);
DOUT : OUT std_logic_vector(5-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pkg;
PACKAGE BODY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pkg;
|
mit
|
80c39ccabba99ecd5d6b2358d77adcff
| 0.519813 | 3.87537 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_3/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_3_dgen.vhd
| 1 | 4,716 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_3_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pkg.ALL;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_3_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_dma_0_wrapper_fifo_generator_v9_3_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
mit
|
631ee7cd1505f275657b80d815dc6d5f
| 0.607294 | 4.079585 | false | false | false | false |
meninge/dauphin
|
myaxifullmaster_v1_0_S00_AXI.vhd
| 1 | 50,671 |
--------------------------------------------------
-- Register mapping
--------------------------------------------------
--
-- reg 0 (partial R/W)
-- 15-00:16 : Number of data items per frame
-- 31-16:16 : Max number of data items per frame (read-only)
--
-- reg 1 (partial R/W)
-- 15-00:16 : Number of neurons in first stage
-- 31-16:16 : Max number of neurons in first stage (read-only)
--
-- reg 2 (partial R/W)
-- 15-00:16 : Number of neurons in second stage
-- 31-16:16 : Max number of neurons in second stage (read-only)
--
-- reg 3 (partial R/W)
-- 03-00:4 : What the PC is sending
-- 0000 = nothing
-- 0001 = frame data
-- 0010 = config for level 1
-- 0100 = config for recoding 1-2
-- 1000 = config for level 2
-- 08:1 : clear all (not written to register)
-- 09:1 : Read master AXI busy state
--
-- reg 4 (unused) : sortie de la première FIFO
-- reg 5 (unused) : sortie de la deuxième FIFO
--
-- reg 6 (R/W)
-- 31-00:32 : Number of NN output values to write back to DDR
--
-- reg 7 (unused) : sortie de la troisième FIFO
-- reg 8 (unused) : sortie de la quatrième FIFO
-- reg 9 (unused)
--
-- reg 10 (R/W)
-- 31-00:32 : Address for DDR read
--
-- reg 11 (R/W)
-- 31-00:32 : Address for DDR write
--
-- reg 12 (R/W)
-- 31-00:32 : Number of bursts for DDR Read. Start on write.
--
-- reg 13 (R/W)
-- 31-00:32 : Number of bursts for DDR write. Start on write.
--
-- reg 14 (read only)
-- 07-00:8 : count of fifo between level 1 and recoding 1-2
-- 15-08:8 : count of fifo between recoding 1-2 and level 2
-- 23-16:8 : count of fifo after level 2
--
-- reg 15 (read only)
-- 31-16:16 : fifo rdy/ack signals, in and out: 12 signals
--
--------------------------------------------------
-- Protocol description
--------------------------------------------------
--
-- One weight per DDR word
-- One data per DDR word
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity myaxifullmaster_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
mymaster_addr_inw : out std_logic_vector(31 downto 0);
mymaster_addr_inr : out std_logic_vector(31 downto 0);
mymaster_burstnb_inw : out std_logic_vector(31 downto 0);
mymaster_burstnb_inr : out std_logic_vector(31 downto 0);
mymaster_startw : out std_logic;
mymaster_startr : out std_logic;
mymaster_busyw : in std_logic;
mymaster_busyr : in std_logic;
mymaster_sensor : in std_logic_vector(31 downto 0); -- For various debug signals
mymaster_fifor_data : in std_logic_vector(31 downto 0);
mymaster_fifor_en : in std_logic;
mymaster_fifor_cnt : out std_logic_vector(15 downto 0);
mymaster_fifow_data : out std_logic_vector(31 downto 0);
mymaster_fifow_en : in std_logic;
mymaster_fifow_cnt : out std_logic_vector(15 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end myaxifullmaster_v1_0_S00_AXI;
architecture arch_imp of myaxifullmaster_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
------------------------------------------------
-- Some signals to make reset last longer
--------------------------------------------------
constant RESET_DURATION : natural := 64;
signal reset_counter : unsigned(15 downto 0) := (others => '0');
signal reset_reg : std_logic := '0';
------------------------------------------------
-- Signals for user logic register space
--------------------------------------------------
-- Number of Slave Registers 16
signal slv_reg0 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg1 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg2 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg3 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg4 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg5 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg6 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg7 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg8 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg9 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg10 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg11 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg12 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg13 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg14 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg15 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal slv_reg_rdaddr : std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
signal slv_reg_wraddr : std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
signal slv_reg_rddata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_wrdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_wstrb : std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
----------------------------------------------------
-- Definitions for the neural network
----------------------------------------------------
constant LAYER1_WDATA : natural := 32;
constant LAYER1_WWEIGHT : natural := 16;
constant LAYER1_WACCU : natural := 32;
constant LAYER1_FSIZE : natural := 784;
--constant LAYER1_FSIZE : natural := 64;
constant LAYER1_NBNEU : natural := 200;
--constant LAYER1_NBNEU : natural := 4;
constant RECODE_WDATA : natural := LAYER1_WACCU;
constant RECODE_WWEIGHT : natural := 16;
constant RECODE_WOUT : natural := 32;
constant RECODE_FSIZE : natural := LAYER1_NBNEU;
constant LAYER2_WDATA : natural := RECODE_WOUT;
constant LAYER2_WWEIGHT : natural := 16;
constant LAYER2_WACCU : natural := 32;
constant LAYER2_FSIZE : natural := LAYER1_NBNEU;
-- constant LAYER2_NBNEU : natural := 3;
constant LAYER2_NBNEU : natural := 10;
signal req_start_recv : std_logic := '0';
signal req_start_send : std_logic := '0';
signal items_per_frame : unsigned(15 downto 0) := (others => '0');
constant CST_RECV_FRAME : std_logic_vector(3 downto 0) := "0001";
constant CST_RECV_CFG_LEVEL1 : std_logic_vector(3 downto 0) := "0010";
constant CST_RECV_CFG_RECODE12 : std_logic_vector(3 downto 0) := "0100";
constant CST_RECV_CFG_LEVEL2 : std_logic_vector(3 downto 0) := "1000";
signal cur_recv : std_logic_vector(3 downto 0) := CST_RECV_FRAME;
signal recv_frame : std_logic := '0';
signal recv_cfgl1 : std_logic := '0';
signal recv_cfgr1 : std_logic := '0';
signal recv_cfgl2 : std_logic := '0';
-- Signals to control obtaining output values and sending them over PCIe
signal out_cur_nb, out_cur_nb_n : unsigned(31 downto 0) := (others => '0'); -- Number of values obtained
signal out_want_nb : unsigned(31 downto 0) := (others => '0'); -- Number of values to send
signal out_getres, out_getres_n : std_logic := '0';
signal out_gotall, out_gotall_n : std_logic := '0';
constant DDRFIFOS_DEPTH : natural := 64;
constant FIFOS_CNTW : natural := 8;
----------------------------------------------------
-- Components
----------------------------------------------------
-- The circular buffer / FIFO component
component circbuf_fast is
generic (
DATAW : natural := 32;
DEPTH : natural := 64;
CNTW : natural := 8
);
port (
reset : in std_logic;
clk : in std_logic;
fifo_in_data : in std_logic_vector(DATAW-1 downto 0);
fifo_in_rdy : out std_logic;
fifo_in_ack : in std_logic;
fifo_in_cnt : out std_logic_vector(CNTW-1 downto 0);
fifo_out_data : out std_logic_vector(DATAW-1 downto 0);
fifo_out_rdy : out std_logic;
fifo_out_ack : in std_logic;
fifo_out_cnt : out std_logic_vector(CNTW-1 downto 0)
);
end component;
-- Then component for one layel of the NN
component nnlayer is
generic (
-- Parameters for the neurons
WDATA : natural := 16;
WWEIGHT : natural := 16;
WACCU : natural := 48;
-- Parameters for frame and number of neurons
FSIZE : natural := 1000;
NBNEU : natural := 1000
);
port (
clk : in std_logic;
clear : in std_logic;
-- Ports for Write Enable
write_mode : in std_logic;
write_data : in std_logic_vector(WDATA-1 downto 0);
write_enable : in std_logic;
write_ready : out std_logic;
-- The user-specified frame size and number of neurons
user_fsize : in std_logic_vector(15 downto 0);
user_nbneu : in std_logic_vector(15 downto 0);
-- Data input, 2 bits
data_in : in std_logic_vector(WDATA-1 downto 0);
data_in_valid : in std_logic;
data_in_ready : out std_logic;
-- Scan chain to extract values
data_out : out std_logic_vector(WACCU-1 downto 0);
data_out_valid : out std_logic;
-- Indicate to the parent component that we are reaching the end of the current frame
end_of_frame : out std_logic;
-- The output data enters a FIFO. This indicates the available room.
out_fifo_room : in std_logic_vector(15 downto 0)
);
end component;
-- The component to recode neuron outputs
component recode is
generic(
WDATA : natural;
WWEIGHT : natural;
WOUT : natural;
FSIZE : natural
);
port(
clk : in std_logic;
-- Ports for address control
addr_clear : in std_logic;
-- Ports for Write into memory
write_mode : in std_logic;
write_data : in std_logic_vector(WDATA - 1 downto 0);
write_enable : in std_logic;
write_ready : out std_logic;
-- The user-specified number of neurons
user_nbneu : in std_logic_vector(15 downto 0);
-- Data input
data_in : in std_logic_vector(WDATA-1 downto 0);
data_in_valid : in std_logic;
data_in_ready : out std_logic;
-- Data output
data_out : out std_logic_vector(WOUT-1 downto 0);
data_out_valid : out std_logic;
-- The output data enters a FIFO. This indicates the available room.
out_fifo_room : in std_logic_vector(15 downto 0)
);
end component;
-- Signals to connect the instantiated FIFO for data read from DDR
signal inst_rdbuf_clear : std_logic := '0';
signal inst_rdbuf_in_data : std_logic_vector(31 downto 0);
signal inst_rdbuf_in_rdy : std_logic := '0';
signal inst_rdbuf_in_ack : std_logic := '0';
signal inst_rdbuf_in_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
signal inst_rdbuf_out_data : std_logic_vector(31 downto 0);
signal inst_rdbuf_out_rdy : std_logic := '0';
signal inst_rdbuf_out_ack : std_logic := '0';
signal inst_rdbuf_out_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
-- Signals to instantiate level 1
signal inst_layer1_clear : std_logic;
signal inst_layer1_write_mode : std_logic;
signal inst_layer1_write_data : std_logic_vector(LAYER1_WDATA-1 downto 0);
signal inst_layer1_write_enable : std_logic;
signal inst_layer1_write_ready : std_logic;
signal inst_layer1_user_fsize : std_logic_vector(15 downto 0);
signal inst_layer1_user_nbneu : std_logic_vector(15 downto 0);
signal inst_layer1_data_in : std_logic_vector(LAYER1_WDATA-1 downto 0);
signal inst_layer1_data_in_valid : std_logic;
signal inst_layer1_data_in_ready : std_logic;
signal inst_layer1_data_out : std_logic_vector(LAYER1_WACCU-1 downto 0);
signal inst_layer1_data_out_valid : std_logic;
signal inst_layer1_end_of_frame : std_logic;
signal inst_layer1_out_fifo_room : std_logic_vector(15 downto 0);
-- Signals to instantiate FIFO between level 1 and recode
signal inst_fifo_1r_clear : std_logic := '0';
signal inst_fifo_1r_in_data : std_logic_vector(LAYER1_WACCU-1 downto 0);
signal inst_fifo_1r_in_rdy : std_logic := '0';
signal inst_fifo_1r_in_ack : std_logic := '0';
signal inst_fifo_1r_in_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
signal inst_fifo_1r_out_data : std_logic_vector(LAYER1_WACCU-1 downto 0);
signal inst_fifo_1r_out_rdy : std_logic := '0';
signal inst_fifo_1r_out_ack : std_logic := '0';
signal inst_fifo_1r_out_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
-- Signals to instantiate recoding between levels 1 and 2
signal inst_recode_addr_clear : std_logic;
signal inst_recode_write_mode : std_logic;
signal inst_recode_write_data : std_logic_vector(LAYER1_WACCU - 1 downto 0);
signal inst_recode_write_enable : std_logic;
signal inst_recode_write_ready : std_logic;
signal inst_recode_user_nbneu : std_logic_vector(15 downto 0);
signal inst_recode_data_in : std_logic_vector(RECODE_WDATA-1 downto 0);
signal inst_recode_data_in_valid : std_logic;
signal inst_recode_data_in_ready : std_logic;
signal inst_recode_data_out : std_logic_vector(RECODE_WOUT-1 downto 0);
signal inst_recode_data_out_valid : std_logic;
signal inst_recode_out_fifo_room : std_logic_vector(15 downto 0);
-- Signals to instantiate FIFO between recode and level 2
signal inst_fifo_r2_clear : std_logic := '0';
signal inst_fifo_r2_in_data : std_logic_vector(RECODE_WOUT-1 downto 0);
signal inst_fifo_r2_in_rdy : std_logic := '0';
signal inst_fifo_r2_in_ack : std_logic := '0';
signal inst_fifo_r2_in_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
signal inst_fifo_r2_out_data : std_logic_vector(RECODE_WOUT-1 downto 0);
signal inst_fifo_r2_out_rdy : std_logic := '0';
signal inst_fifo_r2_out_ack : std_logic := '0';
signal inst_fifo_r2_out_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
-- Signals to instantiate level 2
signal inst_layer2_clear : std_logic;
signal inst_layer2_write_mode : std_logic;
signal inst_layer2_write_data : std_logic_vector(LAYER2_WDATA-1 downto 0);
signal inst_layer2_write_enable : std_logic;
signal inst_layer2_write_ready : std_logic;
signal inst_layer2_user_fsize : std_logic_vector(15 downto 0);
signal inst_layer2_user_nbneu : std_logic_vector(15 downto 0);
signal inst_layer2_data_in : std_logic_vector(LAYER2_WDATA-1 downto 0);
signal inst_layer2_data_in_valid : std_logic;
signal inst_layer2_data_in_ready : std_logic;
signal inst_layer2_data_out : std_logic_vector(LAYER2_WACCU-1 downto 0);
signal inst_layer2_data_out_valid : std_logic;
signal inst_layer2_end_of_frame : std_logic;
signal inst_layer2_out_fifo_room : std_logic_vector(15 downto 0);
-- Signals to instantiate FIFO between level 2 and output
signal inst_fifo_2o_clear : std_logic := '0';
signal inst_fifo_2o_in_data : std_logic_vector(LAYER2_WACCU-1 downto 0);
signal inst_fifo_2o_in_rdy : std_logic := '0';
signal inst_fifo_2o_in_ack : std_logic := '0';
signal inst_fifo_2o_in_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
signal inst_fifo_2o_out_data : std_logic_vector(LAYER2_WACCU-1 downto 0);
signal inst_fifo_2o_out_rdy : std_logic := '0';
signal inst_fifo_2o_out_ack : std_logic := '0';
signal inst_fifo_2o_out_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
-- Signals to connect the instantiated FIFO for data read from DDR
signal inst_wrbuf_clear : std_logic := '0';
signal inst_wrbuf_in_data : std_logic_vector(31 downto 0);
signal inst_wrbuf_in_rdy : std_logic := '0';
signal inst_wrbuf_in_ack : std_logic := '0';
signal inst_wrbuf_in_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
signal inst_wrbuf_out_data : std_logic_vector(31 downto 0);
signal inst_wrbuf_out_rdy : std_logic := '0';
signal inst_wrbuf_out_ack : std_logic := '0';
signal inst_wrbuf_out_cnt : std_logic_vector(FIFOS_CNTW-1 downto 0);
begin
----------------------------------
-- AXI functionality
----------------------------------
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- State machine for AXI Write operations
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
axi_awready <= '0';
axi_awaddr <= (others => '0');
else
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both S_AXI_AWVALID and S_AXI_WVALID are asserted.
if axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' then
-- Slave is ready to accept write data when there is a valid write address and write data on the write address and data bus.
-- This design expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both S_AXI_AWVALID and S_AXI_WVALID are asserted.
if axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' then
-- Slave is ready to accept write address when there is a valid write address and write data on the write address and data bus.
-- This design expects no outstanding transactions.
axi_awready <= '1';
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- Write strobes are used to select byte enables of slave registers while writing.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
-- State machine for AXI Write operations
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg_wren <= '0';
else
-- Note: Buffering these signals is optional. It improves routing.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID;
slv_reg_wraddr <= axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
slv_reg_wrdata <= S_AXI_WDATA;
slv_reg_wstrb <= S_AXI_WSTRB;
end if;
end if;
end process;
-- State machine for AXI Write response
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of write transaction.
if axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' then
axi_bvalid <= '1';
axi_bresp <= "00";
end if;
-- Check if bready is asserted while bvalid is high
-- (there is a possibility that bready is always asserted high)
if S_AXI_BREADY = '1' and axi_bvalid = '1' then
axi_bvalid <= '0';
end if;
end if;
end if;
end process;
-- State machine for AXI Read operation
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '0');
axi_rvalid <= '0';
axi_rresp <= "00";
axi_rdata <= (others => '0');
else
-- Get the read address
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when S_AXI_ARVALID is asserted.
-- The read address is also latched when S_AXI_ARVALID is asserted.
if axi_arready = '0' and S_AXI_ARVALID = '1' then
-- Indicates that the slave has accepted the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
-- Send the read data
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both S_AXI_ARVALID and axi_arready are asserted.
-- The slave registers data are available on the axi_rdata bus at this instance.
-- The assertion of axi_rvalid marks the validity of read data on the bus and axi_rresp indicates the status of read transaction.
if axi_arready = '1' then
axi_rdata <= slv_reg_rddata;
end if;
if axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0' then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
end if;
if (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if; -- S_AXI_ARESETN = '1'
end if; -- rising_edge(S_AXI_ACLK)
end process;
-- Alias signals to be used by the user design
slv_reg_rden <= axi_arready;
slv_reg_rdaddr <= axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
----------------------------------
-- Main design functionality
----------------------------------
-- Alias signals
cur_recv <= slv_reg3(3 downto 0);
recv_frame <= cur_recv(0);
recv_cfgl1 <= cur_recv(1);
recv_cfgr1 <= cur_recv(2);
recv_cfgl2 <= cur_recv(3);
out_want_nb <= unsigned(slv_reg6);
-- Main sequential process: write to config registers, implement all synchronous registers
process (S_AXI_ACLK)
variable tmpvar_slv_reg : std_logic_vector(31 downto 0) := (others => '0');
variable tmpvar_slv_reg_mask_we : std_logic_vector(31 downto 0) := (others => '0');
begin
if rising_edge(S_AXI_ACLK) then
-- Hold reset active for a certain duration
if reset_counter > 0 then
reset_counter <= reset_counter - 1;
reset_reg <= '1';
else
reset_reg <= '0';
end if;
-- Generate reset
if S_AXI_ARESETN = '0' then
reset_counter <= to_unsigned(RESET_DURATION, reset_counter'length);
reset_reg <= '1';
end if;
-- Default/reset assignments
req_start_recv <= '0';
req_start_send <= '0';
-- Buffers for output registers
out_cur_nb <= out_cur_nb_n;
out_getres <= out_getres_n;
out_gotall <= out_gotall_n;
if reset_reg = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg0(15 downto 0) <= std_logic_vector(to_unsigned(LAYER1_FSIZE, 16));
slv_reg0(31 downto 16) <= std_logic_vector(to_unsigned(LAYER1_FSIZE, 16));
slv_reg1(15 downto 0) <= std_logic_vector(to_unsigned(LAYER1_NBNEU, 16));
slv_reg1(31 downto 16) <= std_logic_vector(to_unsigned(LAYER1_NBNEU, 16));
slv_reg2(15 downto 0) <= std_logic_vector(to_unsigned(LAYER2_NBNEU, 16));
slv_reg2(31 downto 16) <= std_logic_vector(to_unsigned(LAYER2_NBNEU, 16));
slv_reg3(3 downto 0) <= CST_RECV_FRAME;
else
-- Write to register
if slv_reg_wren = '1' then
case slv_reg_wraddr is
when b"0000" =>
-- Slave register 0
-- Frame size. Only some bits are writable.
tmpvar_slv_reg_mask_we := x"0000FFFF";
tmpvar_slv_reg := (slv_reg_wrdata and tmpvar_slv_reg_mask_we) or (slv_reg0 and not tmpvar_slv_reg_mask_we);
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg0(byte_index*8+7 downto byte_index*8) <= tmpvar_slv_reg(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0001" =>
-- Slave register 1
-- Number of neurons in first stage. Only some bits are writable.
tmpvar_slv_reg_mask_we := x"0000FFFF";
tmpvar_slv_reg := (slv_reg_wrdata and tmpvar_slv_reg_mask_we) or (slv_reg1 and not tmpvar_slv_reg_mask_we);
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg1(byte_index*8+7 downto byte_index*8) <= tmpvar_slv_reg(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0010" =>
-- Slave register 2
-- Number of neurons in second stage. Only some bits are writable.
tmpvar_slv_reg_mask_we := x"0000FFFF";
tmpvar_slv_reg := (slv_reg_wrdata and tmpvar_slv_reg_mask_we) or (slv_reg2 and not tmpvar_slv_reg_mask_we);
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg2(byte_index*8+7 downto byte_index*8) <= tmpvar_slv_reg(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011" =>
-- Slave register 3
-- Misc status & control flags. Only some bits are writable.
tmpvar_slv_reg_mask_we := x"000000FF";
tmpvar_slv_reg := (slv_reg_wrdata and tmpvar_slv_reg_mask_we) or (slv_reg3 and not tmpvar_slv_reg_mask_we);
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg3(byte_index*8+7 downto byte_index*8) <= tmpvar_slv_reg(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- Detect the clear requests
if slv_reg_wrdata(8) = '1' then
reset_counter <= to_unsigned(RESET_DURATION, reset_counter'length);
reset_reg <= '1';
end if;
when b"0100" =>
-- Slave register 4
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg4(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0101" =>
-- Slave register 5
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg5(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0110" =>
-- Slave register 6
-- Write the number of values the PC wants to read
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg6(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0111" =>
-- Slave register 7
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg7(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1000" =>
-- Slave register 8
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg8(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1001" =>
-- Slave register 9
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg9(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1010" =>
-- Slave register 10
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg10(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1011" =>
-- Slave register 11
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg11(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1100" =>
-- Slave register 12
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg12(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- Start reading data from DDR, 1-clock pulse
req_start_recv <= '1';
when b"1101" =>
-- Slave register 13
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg13(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- Start writing data to DDR, 1-clock pulse
req_start_send <= '1';
when b"1110" =>
-- Slave register 14
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg14(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1111" =>
-- Slave register 15
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( slv_reg_wstrb(byte_index) = '1' ) then
slv_reg15(byte_index*8+7 downto byte_index*8) <= slv_reg_wrdata(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
end case; -- Address
end if; -- Write enable
end if; -- Not reset
end if; -- Clock
end process;
-- Combinatorial process - Control signals for output values
process (
reset_reg,
req_start_send,
out_cur_nb, out_want_nb, out_getres, out_gotall,
inst_fifo_2o_out_rdy, inst_wrbuf_in_rdy
)
begin
-- Default values
out_cur_nb_n <= out_cur_nb;
out_getres_n <= out_getres;
out_gotall_n <= out_gotall;
inst_fifo_2o_out_ack <= '0';
inst_wrbuf_in_ack <= '0';
-- Handle reset and when functionality is disabled
if reset_reg = '1' then
out_cur_nb_n <= (others => '0');
out_getres_n <= '0';
out_gotall_n <= '0';
else
if (req_start_send = '1') and (out_want_nb > 0) then
out_getres_n <= '1';
end if;
-- Fill the Write FIFO with data from the NN level 2
if out_getres = '1' then
inst_fifo_2o_out_ack <= inst_wrbuf_in_rdy;
inst_wrbuf_in_ack <= inst_fifo_2o_out_rdy;
if (inst_wrbuf_in_rdy = '1') and (inst_fifo_2o_out_rdy = '1') then
out_cur_nb_n <= out_cur_nb + 1;
end if;
-- Intentionally simplifying the test expression
if out_cur_nb = out_want_nb then
out_getres_n <= '0';
out_gotall_n <= '1';
end if;
end if;
-- Fill the Write FIFO with junk data
if out_gotall = '1' then
inst_wrbuf_in_ack <= '1';
end if;
end if;
end process;
-- Combinatorial process - Read register, it's a big MUX
process(
reset_reg,
-- The address of the register to read
slv_reg_rdaddr,
-- The register contents
slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7,
slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15,
-- Pipeline sensors
inst_rdbuf_in_rdy, inst_rdbuf_in_ack, inst_rdbuf_out_rdy, inst_rdbuf_out_ack, inst_rdbuf_out_cnt,
inst_wrbuf_in_rdy, inst_wrbuf_in_ack, inst_wrbuf_out_rdy, inst_wrbuf_out_ack, inst_wrbuf_out_cnt,
inst_fifo_1r_in_rdy, inst_fifo_1r_in_ack, inst_fifo_1r_out_rdy, inst_fifo_1r_out_ack, inst_fifo_1r_out_cnt,
inst_fifo_r2_in_rdy, inst_fifo_r2_in_ack, inst_fifo_r2_out_rdy, inst_fifo_r2_out_ack, inst_fifo_r2_out_cnt,
inst_fifo_2o_in_rdy, inst_fifo_2o_in_ack, inst_fifo_2o_out_rdy, inst_fifo_2o_out_ack, inst_fifo_2o_out_cnt,
inst_layer1_write_ready, inst_layer1_data_in_ready, inst_layer1_data_in_valid,
inst_layer2_write_ready, inst_layer2_data_in_ready, inst_layer2_data_in_valid,
-- Various counters
out_getres, out_gotall,
-- Master AXI sensors
mymaster_busyw, mymaster_busyr, mymaster_sensor
)
begin
slv_reg_rddata <= (others => '0');
-- Address decoding for reading registers
case slv_reg_rdaddr is
when b"0000" =>
slv_reg_rddata <= slv_reg0;
when b"0001" =>
slv_reg_rddata <= slv_reg1;
when b"0010" =>
slv_reg_rddata <= slv_reg2;
when b"0011" =>
slv_reg_rddata <= slv_reg3;
slv_reg_rddata(8) <= reset_reg;
slv_reg_rddata(9) <= mymaster_busyw;
slv_reg_rddata(10) <= mymaster_busyr;
slv_reg_rddata(11) <= out_getres;
slv_reg_rddata(12) <= out_gotall;
when b"0100" =>
--slv_reg_rddata <= slv_reg4;
slv_reg_rddata <= mymaster_sensor;
when b"0101" =>
--slv_reg_rddata <= slv_reg5;
when b"0110" =>
slv_reg_rddata <= slv_reg6;
when b"0111" =>
--slv_reg_rddata <= slv_reg7;
when b"1000" =>
slv_reg_rddata <= slv_reg8;
-- to pop data from the fifo between l1 and recode
-- THE RECODE CAN NOT POP FIFO FROM THE FIFO
-- slv_reg_rddata <= inst_fifo_1r_out_data;
--slv_reg_rddata <= inst_fifo_r2_out_data;
-- slv_reg_rddata <= inst_rdbuf_out_data;
when b"1001" =>
--slv_reg_rddata <= slv_reg9;
when b"1010" =>
slv_reg_rddata <= slv_reg10;
when b"1011" =>
slv_reg_rddata <= slv_reg11;
when b"1100" =>
slv_reg_rddata <= slv_reg12;
when b"1101" =>
slv_reg_rddata <= slv_reg13;
when b"1110" =>
slv_reg_rddata <= slv_reg14;
-- Read the amount of data still present in the FIFOs
slv_reg_rddata(7 downto 0) <= inst_fifo_1r_out_cnt;
slv_reg_rddata(15 downto 8) <= inst_fifo_r2_out_cnt;
slv_reg_rddata(23 downto 16) <= inst_fifo_2o_out_cnt;
slv_reg_rddata(31 downto 24) <= inst_rdbuf_out_cnt;
when b"1111" =>
slv_reg_rddata <= slv_reg15;
slv_reg_rddata(7 downto 0) <= inst_wrbuf_out_cnt;
-- Read the FIFO sync signals
slv_reg_rddata(12) <= inst_rdbuf_in_rdy;
slv_reg_rddata(13) <= inst_rdbuf_in_ack;
slv_reg_rddata(14) <= inst_rdbuf_out_rdy;
slv_reg_rddata(15) <= inst_rdbuf_out_ack;
slv_reg_rddata(16) <= inst_fifo_1r_in_rdy;
slv_reg_rddata(17) <= inst_fifo_1r_in_ack;
slv_reg_rddata(18) <= inst_fifo_1r_out_rdy;
slv_reg_rddata(19) <= inst_fifo_1r_out_ack;
slv_reg_rddata(20) <= inst_fifo_r2_in_rdy;
slv_reg_rddata(21) <= inst_fifo_r2_in_ack;
slv_reg_rddata(22) <= inst_fifo_r2_out_rdy;
slv_reg_rddata(23) <= inst_fifo_r2_out_ack;
slv_reg_rddata(24) <= inst_fifo_2o_in_rdy;
slv_reg_rddata(25) <= inst_fifo_2o_in_ack;
slv_reg_rddata(26) <= inst_fifo_2o_out_rdy;
slv_reg_rddata(27) <= inst_fifo_2o_out_ack;
slv_reg_rddata(28) <= inst_wrbuf_in_rdy;
slv_reg_rddata(29) <= inst_wrbuf_in_ack;
slv_reg_rddata(30) <= inst_wrbuf_out_rdy;
slv_reg_rddata(31) <= inst_wrbuf_out_ack;
when others =>
slv_reg_rddata <= (others => '0');
end case;
end process;
----------------------------------
-- FIFO to hold data read from DDR
----------------------------------
-- Instantiate the FIFO for the read values
i_rdbuf : circbuf_fast
generic map (
DATAW => 32,
DEPTH => DDRFIFOS_DEPTH,
CNTW => FIFOS_CNTW
)
port map (
clk => S_AXI_ACLK,
reset => inst_rdbuf_clear,
fifo_in_data => inst_rdbuf_in_data,
fifo_in_rdy => inst_rdbuf_in_rdy,
fifo_in_ack => inst_rdbuf_in_ack,
fifo_in_cnt => inst_rdbuf_in_cnt,
fifo_out_data => inst_rdbuf_out_data,
fifo_out_rdy => inst_rdbuf_out_rdy,
fifo_out_ack => inst_rdbuf_out_ack,
fifo_out_cnt => inst_rdbuf_out_cnt
);
inst_rdbuf_clear <= reset_reg;
inst_rdbuf_in_data <= mymaster_fifor_data;
-- for the debug
--inst_rdbuf_in_data <= slv_reg9;
inst_rdbuf_in_ack <= mymaster_fifor_en;
-- for the debug
--inst_rdbuf_in_ack <= '1' when ((slv_reg_wraddr = b"1001") and (slv_reg_wren = '1')) else '0';
inst_rdbuf_out_ack <=
(recv_cfgl1 and inst_layer1_write_ready) or
(recv_cfgr1 and inst_recode_write_ready) or
(recv_cfgl2 and inst_layer2_write_ready) or
(recv_frame and inst_layer1_data_in_ready);
-- for debug
--inst_rdbuf_out_ack <= '1' when ((slv_reg_rdaddr = b"1000") and (slv_reg_rden = '1')) else '0';
----------------------------------
-- Instantiation of NN level 1
----------------------------------
i_layer1 : nnlayer
generic map (
-- Parameters for the neurons
WDATA => LAYER1_WDATA,
WWEIGHT => LAYER1_WWEIGHT,
WACCU => LAYER1_WACCU,
-- Parameters for frame and number of neurons
FSIZE => LAYER1_FSIZE,
NBNEU => LAYER1_NBNEU
)
port map (
clk => S_AXI_ACLK,
clear => inst_layer1_clear,
write_mode => inst_layer1_write_mode,
write_data => inst_layer1_write_data,
write_enable => inst_layer1_write_enable,
write_ready => inst_layer1_write_ready,
user_fsize => inst_layer1_user_fsize,
user_nbneu => inst_layer1_user_nbneu,
data_in => inst_layer1_data_in,
data_in_valid => inst_layer1_data_in_valid,
data_in_ready => inst_layer1_data_in_ready,
data_out => inst_layer1_data_out,
data_out_valid => inst_layer1_data_out_valid,
end_of_frame => inst_layer1_end_of_frame,
out_fifo_room => inst_layer1_out_fifo_room
);
-- Set inputs
inst_layer1_clear <= reset_reg;
inst_layer1_write_mode <= recv_cfgl1;
inst_layer1_write_data <= inst_rdbuf_out_data(LAYER1_WDATA-1 downto 0);
inst_layer1_write_enable <= inst_rdbuf_out_rdy and recv_cfgl1;
inst_layer1_user_fsize <= slv_reg0(15 downto 0);
inst_layer1_user_nbneu <= slv_reg1(15 downto 0);
inst_layer1_data_in <= inst_rdbuf_out_data(LAYER1_WDATA-1 downto 0);
-- protection from reading into the 1st FIFO during configuration of others
inst_layer1_data_in_valid <= inst_rdbuf_out_rdy and recv_frame;
inst_layer1_out_fifo_room <= std_logic_vector(resize(unsigned(inst_fifo_1r_in_cnt), 16));
----------------------------------
-- FIFO between level 1 and recode
----------------------------------
i_fifo1r : circbuf_fast
generic map (
DATAW => LAYER1_WACCU,
DEPTH => DDRFIFOS_DEPTH,
CNTW => FIFOS_CNTW
)
port map (
clk => S_AXI_ACLK,
reset => inst_fifo_1r_clear,
fifo_in_data => inst_fifo_1r_in_data,
fifo_in_rdy => inst_fifo_1r_in_rdy,
fifo_in_ack => inst_fifo_1r_in_ack,
fifo_in_cnt => inst_fifo_1r_in_cnt,
fifo_out_data => inst_fifo_1r_out_data,
fifo_out_rdy => inst_fifo_1r_out_rdy,
fifo_out_ack => inst_fifo_1r_out_ack,
fifo_out_cnt => inst_fifo_1r_out_cnt
);
-- Set inputs
inst_fifo_1r_clear <= reset_reg;
inst_fifo_1r_in_data <= inst_layer1_data_out;
inst_fifo_1r_in_ack <= inst_layer1_data_out_valid;
inst_fifo_1r_out_ack <= (inst_recode_data_in_ready and recv_frame);
-- For debug, le recode can not read data from this fifo
--inst_fifo_1r_out_ack <= '1' when ((slv_reg_rdaddr = b"1000") and (slv_reg_rden = '1')) else '0';
----------------------------------
-- Recode between levels 1 and 2
----------------------------------
i_recode : recode
generic map (
WDATA => RECODE_WDATA,
WWEIGHT => RECODE_WWEIGHT,
WOUT => RECODE_WOUT,
FSIZE => RECODE_FSIZE
)
port map (
clk => S_AXI_ACLK,
addr_clear => inst_recode_addr_clear,
write_mode => inst_recode_write_mode,
write_data => inst_recode_write_data,
write_enable => inst_recode_write_enable,
write_ready => inst_recode_write_ready,
user_nbneu => inst_recode_user_nbneu,
data_in => inst_recode_data_in,
data_in_valid => inst_recode_data_in_valid,
data_in_ready => inst_recode_data_in_ready,
data_out => inst_recode_data_out,
data_out_valid => inst_recode_data_out_valid,
out_fifo_room => inst_recode_out_fifo_room
);
-- Set inputs
inst_recode_addr_clear <= reset_reg;
inst_recode_write_mode <= recv_cfgr1;
inst_recode_write_data <= inst_rdbuf_out_data;
inst_recode_write_enable <= inst_rdbuf_out_rdy and recv_cfgr1;
inst_recode_user_nbneu <= slv_reg1(15 downto 0);
inst_recode_data_in <= inst_fifo_1r_out_data;
inst_recode_data_in_valid <= inst_fifo_1r_out_rdy and recv_frame;
inst_recode_out_fifo_room <= std_logic_vector(resize(unsigned(inst_fifo_r2_in_cnt), 16));
----------------------------------
-- FIFO between recode and level 2
----------------------------------
i_fifor2 : circbuf_fast
generic map (
DATAW => RECODE_WOUT,
DEPTH => DDRFIFOS_DEPTH,
CNTW => FIFOS_CNTW
)
port map (
clk => S_AXI_ACLK,
reset => inst_fifo_r2_clear,
fifo_in_data => inst_fifo_r2_in_data,
fifo_in_rdy => inst_fifo_r2_in_rdy,
fifo_in_ack => inst_fifo_r2_in_ack,
fifo_in_cnt => inst_fifo_r2_in_cnt,
fifo_out_data => inst_fifo_r2_out_data,
fifo_out_rdy => inst_fifo_r2_out_rdy,
fifo_out_ack => inst_fifo_r2_out_ack,
fifo_out_cnt => inst_fifo_r2_out_cnt
);
-- Set inputs
inst_fifo_r2_clear <= reset_reg;
inst_fifo_r2_in_data <= inst_recode_data_out;
inst_fifo_r2_in_ack <= inst_recode_data_out_valid;
inst_fifo_r2_out_ack <= inst_layer2_data_in_ready and recv_frame;
-- for debug
--inst_fifo_r2_out_ack <= '1' when ((slv_reg_rdaddr = b"1000") and (slv_reg_rden = '1')) else '0';
----------------------------------
-- Instantiation of NN level 2
----------------------------------
i_layer2 : nnlayer
generic map (
-- Parameters for the neurons
WDATA => LAYER2_WDATA,
WWEIGHT => LAYER2_WWEIGHT,
WACCU => LAYER2_WACCU,
-- Parameters for frame and number of neurons
FSIZE => LAYER2_FSIZE,
NBNEU => LAYER2_NBNEU
)
port map (
clk => S_AXI_ACLK,
clear => inst_layer2_clear,
write_mode => inst_layer2_write_mode,
write_data => inst_layer2_write_data,
write_enable => inst_layer2_write_enable,
write_ready => inst_layer2_write_ready,
user_fsize => inst_layer2_user_fsize,
user_nbneu => inst_layer2_user_nbneu,
data_in => inst_layer2_data_in,
data_in_valid => inst_layer2_data_in_valid,
data_in_ready => inst_layer2_data_in_ready,
data_out => inst_layer2_data_out,
data_out_valid => inst_layer2_data_out_valid,
end_of_frame => inst_layer2_end_of_frame,
out_fifo_room => inst_layer2_out_fifo_room
);
-- Set inputs
inst_layer2_clear <= reset_reg;
inst_layer2_write_mode <= recv_cfgl2;
inst_layer2_write_data <= inst_rdbuf_out_data(inst_layer2_write_data'length-1 downto 0);
inst_layer2_write_enable <= inst_rdbuf_out_rdy and recv_cfgl2;
inst_layer2_user_fsize <= slv_reg1(15 downto 0);
inst_layer2_user_nbneu <= slv_reg2(15 downto 0);
inst_layer2_data_in <= inst_fifo_r2_out_data;
inst_layer2_data_in_valid <= inst_fifo_r2_out_rdy and recv_frame;
inst_layer2_out_fifo_room <= std_logic_vector(resize(unsigned(inst_fifo_2o_in_cnt), 16));
----------------------------------
-- FIFO after level 2
----------------------------------
i_fifo2o : circbuf_fast
generic map (
DATAW => LAYER2_WACCU,
DEPTH => DDRFIFOS_DEPTH,
CNTW => FIFOS_CNTW
)
port map (
clk => S_AXI_ACLK,
reset => inst_fifo_2o_clear,
fifo_in_data => inst_fifo_2o_in_data,
fifo_in_rdy => inst_fifo_2o_in_rdy,
fifo_in_ack => inst_fifo_2o_in_ack,
fifo_in_cnt => inst_fifo_2o_in_cnt,
fifo_out_data => inst_fifo_2o_out_data,
fifo_out_rdy => inst_fifo_2o_out_rdy,
fifo_out_ack => inst_fifo_2o_out_ack,
fifo_out_cnt => inst_fifo_2o_out_cnt
);
-- Set inputs
inst_fifo_2o_clear <= reset_reg;
inst_fifo_2o_in_data <= inst_layer2_data_out;
inst_fifo_2o_in_ack <= inst_layer2_data_out_valid;
----------------------------------
-- FIFO to write to DDR
----------------------------------
i_wrbuf : circbuf_fast
generic map (
DATAW => 32,
DEPTH => DDRFIFOS_DEPTH,
CNTW => FIFOS_CNTW
)
port map (
clk => S_AXI_ACLK,
reset => inst_wrbuf_clear,
fifo_in_data => inst_wrbuf_in_data,
fifo_in_rdy => inst_wrbuf_in_rdy,
fifo_in_ack => inst_wrbuf_in_ack,
fifo_in_cnt => inst_wrbuf_in_cnt,
fifo_out_data => inst_wrbuf_out_data,
fifo_out_rdy => inst_wrbuf_out_rdy,
fifo_out_ack => inst_wrbuf_out_ack,
fifo_out_cnt => inst_wrbuf_out_cnt
);
-- Set inputs
inst_wrbuf_clear <= reset_reg;
inst_wrbuf_in_data <= std_logic_vector(resize(signed(inst_fifo_2o_out_data), 32));
inst_wrbuf_out_ack <= mymaster_fifow_en;
----------------------------------
-- Talk to the Master port
----------------------------------
mymaster_fifow_data <= inst_wrbuf_out_data;
mymaster_fifor_cnt <= std_logic_vector(resize(unsigned(inst_rdbuf_in_cnt), 16));
mymaster_fifow_cnt <= std_logic_vector(resize(unsigned(inst_wrbuf_out_cnt), 16));
mymaster_addr_inr <= slv_reg10;
mymaster_addr_inw <= slv_reg11;
mymaster_burstnb_inr <= slv_reg12;
mymaster_burstnb_inw <= slv_reg13;
mymaster_startr <= req_start_recv;
mymaster_startw <= req_start_send;
end arch_imp;
|
mit
|
5b35b38ddb5c1e15872e50ac4ce59904
| 0.623581 | 2.935516 | false | false | false | false |
DanielSouzaBertoldi/VHDL
|
ProjetoFinal/Ifetch.vhd
| 1 | 3,022 |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; -- Tipo de sinal STD_LOGIC e STD_LOGIC_VECTOR
USE IEEE.STD_LOGIC_ARITH.ALL; -- Operacoes aritmeticas sobre binarios
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.ALL;
ENTITY Ifetch IS
PORT(
reset : IN STD_LOGIC;
clock : IN STD_LOGIC;
PC_out : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0);
Instruction : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0);
ADDResult : IN STD_LOGIC_VECTOR( 7 DOWNTO 0);
Reg31 : IN STD_LOGIC_VECTOR( 7 DOWNTO 0);
Beq : IN STD_LOGIC;
Bne : IN STD_LOGIC;
Zero : IN STD_LOGIC;
Jump : IN STD_LOGIC;
Jal : IN STD_LOGIC;
Jr : IN STD_LOGIC;
PC_inc : INOUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
J_Address : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 )
);
END Ifetch;
ARCHITECTURE behavior OF Ifetch IS
SIGNAL PC : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL Next_PC : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL Mem_Addr : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
-- Descrição da Memória
data_memory: altsyncram -- Declaração do compomente de memória
GENERIC MAP(
operation_mode => "ROM",
width_a => 32, -- tamanho da palavra (Word)
widthad_a => 8, -- tamanho do barramento de endereço
lpm_type => "altsyncram",
outdata_reg_a => "UNREGISTERED",
init_file => "programT.mif", -- arquivo com estado inicial
intended_device_family => "Cyclone")
PORT MAP(
address_a => Mem_Addr,
q_a => Instruction,
clock0 => clock); -- sinal de clock da memória
-- Descrição do somador
PC_inc <= PC+1;
-- Descrição do registrador
PROCESS
BEGIN
WAIT UNTIL (clock'event AND clock='1');
IF reset='1' THEN
PC <= "00000000";
ELSE
PC <= Next_PC;
END IF;
END PROCESS;
-- Usar o Next_PC ao invés do PC por quê a memória tem um registrador de entrada interno
-- Então o PC tem que ser atualizado simultâneamente com o reg interno da memória
Mem_Addr <= Next_PC;
Next_PC <= "00000000" WHEN reset = '1' ELSE
--Deve-se somar o endereço do pulo caso seja Beq ou Bne
ADDResult WHEN (Beq = '1' AND Zero = '1') OR (Bne = '1' AND Zero = '0') ELSE
--Deve-se receber o endereco requisitado caso seja uma instrucao de pulo incondicional
J_Address WHEN Jump = '1' OR Jal = '1' ELSE
--Deve-se receber o endereço armazenado no registrador 31 quando a instrução for Jr
Reg31 WHEN Jr = '1' ELSE
--Caso nao seja nenhuma instrucao de pulo, continua normalmente
PC_inc;
PC_out <= PC;
END behavior;
|
gpl-3.0
|
d58ff989a56602491fd4e1b28399e1a9
| 0.55 | 3.787879 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_3/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pkg.vhd
| 1 | 11,923 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_3_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_3_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_3_exdes IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(38-1 DOWNTO 0);
DOUT : OUT std_logic_vector(38-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pkg;
PACKAGE BODY system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pkg;
|
mit
|
4230ccf77b46df6658789bce104386a5
| 0.51321 | 3.857328 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen.vhd
| 1 | 6,070 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
SIGNAL wr_d_sel : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
gen_fifo_stim: IF(C_CH_TYPE /= 2) GENERATE
-- DIN_WIDTH < DOUT_WIDTH
gen_din_lt_dout: IF(C_DIN_WIDTH < C_DOUT_WIDTH) GENERATE
BEGIN
pr_w_en <= (AND_REDUCE(wr_d_sel)) AND PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DOUT_WIDTH-C_DIN_WIDTH*conv_integer(wr_d_sel)-1 DOWNTO C_DOUT_WIDTH-C_DIN_WIDTH*(conv_integer(wr_d_sel)+1));
PROCESS(WR_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
wr_d_sel <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK = '1') THEN
IF(FULL = '0' AND PRC_WR_EN = '1') THEN
wr_d_sel <= wr_d_sel + "1";
END IF;
END IF;
END PROCESS;
END GENERATE gen_din_lt_dout;
-- DIN_WIDTH >= DOUT_WIDTH
gen_din_gteq_dout:IF(C_DIN_WIDTH >= C_DOUT_WIDTH) GENERATE
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END GENERATE gen_din_gteq_dout;
END GENERATE gen_fifo_stim;
----------------------------------------------
-- Wiring logic stimulus generation
----------------------------------------------
gen_wiring_stim: IF (C_CH_TYPE = 2) GENERATE
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
pr_w_en <= PRC_WR_EN;
END GENERATE gen_wiring_stim;
END ARCHITECTURE;
|
mit
|
1a0e336cd2e9c302c40843f2be860325
| 0.597694 | 3.81761 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_trem_1.0/sim_1/new/trem_tb.vhd
| 1 | 2,608 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity trem_tb is
end trem_tb;
architecture Behavioral of trem_tb is
component trem
Port ( x : in STD_LOGIC_VECTOR(31 downto 0);
y : out STD_LOGIC_VECTOR(31 downto 0);
clk_48 : in std_logic;
clk_190 : in std_logic;
clk_380 : in std_logic;
clk_95 : in std_logic;
clk_48hz : in std_logic;
options : in STD_LOGIC_VECTOR(0 to 3);
en : in STD_LOGIC_VECTOR(0 to 3)
);
end component;
signal x: STD_LOGIC_VECTOR(31 downto 0);
signal y: STD_LOGIC_VECTOR(31 downto 0);
signal clk_48: std_logic :='0';
signal clk_190: std_logic;
signal clk_380: std_logic :='0';
signal clk_95: std_logic;
signal clk_48hz: std_logic;
signal options: STD_LOGIC_VECTOR(0 to 3) := "0010";
signal en: STD_LOGIC_VECTOR(0 to 3) := "0010";
constant clock_period: time := 20 us;
constant clock_period380: time := 2.63 ms;
signal rand_num : integer := 0;
begin
uut: trem port map ( x => x,
y => y,
clk_48 => clk_48,
clk_190 => clk_190,
clk_380 => clk_380,
clk_95 => clk_95,
clk_48hz => clk_48hz,
options => options,
en => en );
clk_process: process
begin
clk_48 <= '1';
wait for clock_period/2;
clk_48 <= '0';
wait for clock_period/2;
end process;
clk380_process: process
begin
clk_380 <= '1';
wait for clock_period380/2;
clk_380 <= '0';
wait for clock_period380/2;
end process;
random_num: process
variable seed1, seed2: positive; -- seed values for random generator
variable rand: real; -- random real-number value in range 0 to 1.0
variable range_of_rand : real := 150000.0; -- the range of random values created will be 0 to +30000.
begin
uniform(seed1, seed2, rand); -- generate random number
rand_num <= integer(rand*range_of_rand); -- rescale to 0..1000, convert integer part
x <= std_logic_vector(to_unsigned(rand_num, 32));
wait for 0.000020 sec;
end process;
end Behavioral;
|
mit
|
addee4028877d4c62e8db95d15d0752a
| 0.574003 | 3.632312 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_2/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pctrl.vhd
| 1 | 16,633 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pkg.ALL;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND FULL = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_dma_0_wrapper_fifo_generator_v9_3_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_dma_0_wrapper_fifo_generator_v9_3_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
mit
|
88437c9cfba08af9fc050f60bd0dd295
| 0.523838 | 3.331931 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_3/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_3_synth.vhd
| 1 | 11,106 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_3_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_3_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(7-1 DOWNTO 0);
SIGNAL wr_ack : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(38-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(38-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(38-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(38-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 100 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
fg_dg_nv: system_axi_dma_0_wrapper_fifo_generator_v9_3_3_dgen
GENERIC MAP (
C_DIN_WIDTH => 38,
C_DOUT_WIDTH => 38,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_dma_0_wrapper_fifo_generator_v9_3_3_dverif
GENERIC MAP (
C_DOUT_WIDTH => 38,
C_DIN_WIDTH => 38,
C_USE_EMBEDDED_REG => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 38,
C_DIN_WIDTH => 38,
C_WR_PNTR_WIDTH => 7,
C_RD_PNTR_WIDTH => 7,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_dma_0_wrapper_fifo_generator_v9_3_3_inst : system_axi_dma_0_wrapper_fifo_generator_v9_3_3_exdes
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
mit
|
183281e88f91dbd048c1d22eb8bf0975
| 0.467045 | 4.045902 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_octaver_1.0/sources_1/new/octaver.vhd
| 1 | 6,941 |
----------------------------------------------------
-- Vladi & Adi --
-- TAU EE Senior year project --
-- --
--************************************************--
--****************** Octaver *********************--
--************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity octaver is
generic (
T: integer := 20000;
B: integer := 15 --15 bits for 20,000 memory places
);
Port ( x : in STD_LOGIC_VECTOR(31 downto 0);
y : out STD_LOGIC_VECTOR(31 downto 0);
clk_48: in std_logic;
options : in STD_LOGIC_VECTOR(0 to 3);
en : in STD_LOGIC_VECTOR(0 to 3)
);
end octaver;
architecture Behavioral of octaver is
signal y_temp_s : signed(31 downto 0):= x"00000000";
signal i : std_logic_vector (B-1 downto 0) := "000000000000000";
signal max_delay : integer := T-1;
--********************** BRAM signals
signal we : std_logic := '1';
signal addr1 : std_logic_vector(B-1 downto 0) := "000000000000000";
signal addr2 : std_logic_vector(B-1 downto 0):= "000000000000000";
signal data_in : std_logic_vector(31 downto 0); --32 bit word
signal data_out1 : std_logic_vector(31 downto 0);
signal data_out2 : std_logic_vector(31 downto 0);
--*************************
component bram_oct is
generic (
T: integer := 20000;
B: integer := 15 --15 bits for 20,000 memory places
);
port (
CLK : in std_logic;
WE : in std_logic;
ADDR1 : in std_logic_vector(B-1 downto 0);
ADDR2 : in std_logic_vector(B-1 downto 0);
DI : in std_logic_vector(31 downto 0); --32 bit word
DO1 : out std_logic_vector(31 downto 0);
DO2 : out std_logic_vector(31 downto 0)
);
end component bram_oct;
begin
--*********** temporary debugging signals *********
--addr1_temp0 <= "00000000000000000" & std_logic_vector(addr1);
--addr2_temp1 <= "00000000000000000" & std_logic_vector(addr2);
--*************************************************
bram_oct_inst : bram_oct
port map (
CLK => clk_48,
WE => we,
ADDR1 => addr1,
ADDR2 => addr2,
DI => data_in,
DO1 => data_out1,
DO2 => data_out2
);
mem:process(clk_48)
begin
if rising_edge(clk_48) then
if to_integer(unsigned(i))= max_delay-2 then
i<= "000000000000000";
else
i <= std_logic_vector(unsigned(i)+1);
end if;
end if;
end process;
addr_1:process(clk_48)
begin
if rising_edge(clk_48) then
if (to_integer(unsigned(addr1)) = max_delay-2) then
addr1 <= "000000000000000";
else
addr1 <= std_logic_vector(unsigned(addr1) + 1);
end if;
end if;
end process;
addr_2:process(clk_48)
begin
if rising_edge(clk_48) then
--*********************** 1 octave up ****************
if (options="1000" or options="1100" or options="1110" or options="0011" or options="1111" or options="0111") then
if (to_integer(unsigned(addr2)) >= max_delay-2) then
addr2 <= "000000000000000";
end if;
addr2 <= std_logic_vector(shift_left(unsigned(i),1) + 1);
end if;
--***************************************************
--*********************** 2 octaves up ****************
if (options="0100" or options="0001" ) then
if (to_integer(unsigned(addr2)) >= max_delay-2) then
addr2 <= "000000000000000";
end if;
addr2 <= std_logic_vector(shift_left(unsigned(i),2) + 1);
end if;
--***************************************************
--*********************** 1 octave dowm ****************
if (options="0010") then
if (to_integer(unsigned(addr2)) >= max_delay-2) then
addr2 <= "000000000000000";
end if;
addr2 <= std_logic_vector(shift_right(unsigned(i),1) + 1);
end if;
--***************************************************
end if;
end process;
process (clk_48, options)
begin
if en(1)= '1' then
if rising_edge(clk_48) then
if options="1000" then --fir, 1up, 3000
max_delay <= 3000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= x;
y <= std_logic_vector(y_temp_s);
end if;
if options="1100" then --fir, 1up, 8000
max_delay <= 8000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= x;
y <= std_logic_vector(y_temp_s);
end if;
if options="1110" then --fir, 1up, 15000
max_delay <= 15000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= x;
y <= std_logic_vector(y_temp_s);
end if;
if options="1111" then --iir, 1up, 5000 (T/4)
max_delay <= 5000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= std_logic_vector(y_temp_s);
y <= std_logic_vector(y_temp_s);
end if;
if options="0111" then --iir, 1up, 10000 (T/2)
max_delay <= 10000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= std_logic_vector(y_temp_s);
y <= std_logic_vector(y_temp_s);
end if;
if options="0011" then --iir, 1up, 19999 (T-1)
max_delay <= 19999;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= std_logic_vector(y_temp_s);
y <= std_logic_vector(y_temp_s);
end if;
--********************************************************
if options="0100" then --fir, 2up, 3000
max_delay <= 3000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= x;
y <= std_logic_vector(y_temp_s);
end if;
if options="0001" then --fir, 2up, 500 - robot sound
max_delay <= 500;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= x;
y <= std_logic_vector(y_temp_s);
end if;
--********************************************************
if options="0010" then --fir, 1down, 8000
max_delay <= 8000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= x;
y <= std_logic_vector(y_temp_s);
end if;
--********************************************************
end if;
else
y<=x;
end if;
end process;
end Behavioral;
|
mit
|
11b14860ac7f044e7382fa93e9780d6e
| 0.502233 | 3.458396 | false | false | false | false |
medav/conware
|
conware_final/system/hdl/system_stub.vhd
| 1 | 5,708 |
-------------------------------------------------------------------------------
-- system_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_stub is
port (
SWs_8Bits_TRI_IO : inout std_logic_vector(7 downto 0);
LEDs_8Bits_TRI_IO : out std_logic_vector(7 downto 0);
BTNs_5Bits_TRI_IO : inout std_logic_vector(4 downto 0);
v_axi4s_vid_out_0_video_vsync_pin : out std_logic;
v_axi4s_vid_out_0_video_hsync_pin : out std_logic;
v_axi4s_vid_out_0_video_data_pin : out std_logic_vector(31 downto 0);
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic
);
end system_stub;
architecture STRUCTURE of system_stub is
component system is
port (
SWs_8Bits_TRI_IO : inout std_logic_vector(7 downto 0);
LEDs_8Bits_TRI_IO : out std_logic_vector(7 downto 0);
BTNs_5Bits_TRI_IO : inout std_logic_vector(4 downto 0);
v_axi4s_vid_out_0_video_vsync_pin : out std_logic;
v_axi4s_vid_out_0_video_hsync_pin : out std_logic;
v_axi4s_vid_out_0_video_data_pin : out std_logic_vector(31 downto 0);
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic
);
end component;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system : component is "user_black_box";
begin
system_i : system
port map (
SWs_8Bits_TRI_IO => SWs_8Bits_TRI_IO,
LEDs_8Bits_TRI_IO => LEDs_8Bits_TRI_IO,
BTNs_5Bits_TRI_IO => BTNs_5Bits_TRI_IO,
v_axi4s_vid_out_0_video_vsync_pin => v_axi4s_vid_out_0_video_vsync_pin,
v_axi4s_vid_out_0_video_hsync_pin => v_axi4s_vid_out_0_video_hsync_pin,
v_axi4s_vid_out_0_video_data_pin => v_axi4s_vid_out_0_video_data_pin,
processing_system7_0_MIO => processing_system7_0_MIO,
processing_system7_0_PS_SRSTB_pin => processing_system7_0_PS_SRSTB_pin,
processing_system7_0_PS_CLK_pin => processing_system7_0_PS_CLK_pin,
processing_system7_0_PS_PORB_pin => processing_system7_0_PS_PORB_pin,
processing_system7_0_DDR_Clk => processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n => processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE => processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n => processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n => processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n => processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr => processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT => processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB => processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ => processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM => processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS => processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n => processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN => processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP => processing_system7_0_DDR_VRP
);
end architecture STRUCTURE;
|
mit
|
f94f24c48cdb8aec6ac7e9b779d9565f
| 0.673966 | 2.976017 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg.vhd
| 1 | 11,750 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_1_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_1_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_1_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_1_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(8-1 DOWNTO 0);
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(34-1 DOWNTO 0);
DOUT : OUT std_logic_vector(34-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg;
PACKAGE BODY system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg;
|
mit
|
16be0cd5f13ccb2ac9690111bc9df421
| 0.51617 | 3.867676 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_tb.vhd
| 1 | 6,128 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_tb IS
END ENTITY;
ARCHITECTURE system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4000 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_synth
system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_synth_inst:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 21
)
PORT MAP(
S_ACLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
mit
|
b4fad358161df3f96b1f6686b060ac8a
| 0.632996 | 4.044884 | false | false | false | false |
groggemans/block-mario
|
Broncode/TestBench_MMU.vhd
| 1 | 4,889 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:08:44 01/07/2014
-- Design Name:
-- Module Name: G:/Project_Block_Mario/TestBench_MMU.vhd
-- Project Name: Block_Mario
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MMU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.sig_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TestBench_MMU IS
END TestBench_MMU;
ARCHITECTURE behavior OF TestBench_MMU IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MMU
PORT(
clk : IN std_logic;
com : IN std_logic_vector(2 downto 0);
com_ok : INOUT std_logic_vector(0 downto 0);
data_in : in core_register := ("0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000"); -- AOI vector in
data_out : out core_register := ("0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000"); -- AOI vector out
f_ram_do : IN std_logic_vector(3 downto 0);
f_ram_di : OUT std_logic_vector(3 downto 0);
f_ram_adr : OUT std_logic_vector(9 downto 0);
f_ram_we : OUT std_logic_vector(0 downto 0);
lvl_rom_do : IN std_logic_vector(3 downto 0);
lvl_rom_adr : OUT std_logic_vector(11 downto 0);
rom_lvl : in integer range 0 to 4; -- op te halen lvl (scherm)
X : in integer range 0 to 31; -- X van OOI voor AOI
Y : in integer range 0 to 23 -- Y van OOI voor AOI
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal com : std_logic_vector(2 downto 0) := (others => '0');
signal data_in : core_register := ("0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000"); -- AOI vector in
signal f_ram_do : std_logic_vector(3 downto 0) := (others => '0');
signal lvl_rom_do : std_logic_vector(3 downto 0) := (others => '0');
signal rom_lvl : integer range 0 to 4; -- op te halen lvl (scherm)
signal X : integer range 0 to 31; -- X van OOI voor AOI
signal Y : integer range 0 to 23; -- Y van OOI voor AOI
--BiDirs
signal com_ok : std_logic_vector(0 downto 0);
--Outputs
signal data_out : core_register := ("0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000"); -- AOI vector out
signal f_ram_di : std_logic_vector(3 downto 0);
signal f_ram_adr : std_logic_vector(9 downto 0);
signal f_ram_we : std_logic_vector(0 downto 0);
signal lvl_rom_adr : std_logic_vector(11 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MMU PORT MAP (
clk => clk,
com => com,
com_ok => com_ok,
data_in => data_in,
data_out => data_out,
f_ram_do => f_ram_do,
f_ram_di => f_ram_di,
f_ram_adr => f_ram_adr,
f_ram_we => f_ram_we,
lvl_rom_do => lvl_rom_do,
lvl_rom_adr => lvl_rom_adr,
rom_lvl => rom_lvl,
X => X,
Y => Y
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
com <= "000";
wait for 20 ns;
com <= "001";
-- wachten tot laden level afgelopen is
for i in 1 to 771 loop
wait for 10 ns;
end loop;
com <= "000";
wait for 20 ns;
com <= "010";
-- wachten tot AOI doorgestuurd is
-- testbench stopt hier wegens ongekende reden (mogelijk probleem met package?)
for i in 1 to 15 loop
wait for 10 ns;
end loop;
com <= "000";
wait for 20 ns;
com <= "100";
-- wachten tot AOI weggeschreven is
for i in 1 to 15 loop
wait for 10 ns;
end loop;
com <= "000";
wait;
end process;
END;
|
lgpl-3.0
|
710d84761d3330c832015004cc8cbc45
| 0.556556 | 3.467376 | false | true | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_tb.vhd
| 1 | 6,190 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_tb IS
END ENTITY;
ARCHITECTURE system_axi_vdma_0_wrapper_fifo_generator_v9_3_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2100 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth
system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth_inst:system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 38
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
mit
|
5679183ccf82779a5382776bc806970c
| 0.627141 | 4.048398 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_1/example_design/system_axi_dma_0_wrapper_fifo_generator_v9_3_1_exdes.vhd
| 1 | 5,695 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_1_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_dma_0_wrapper_fifo_generator_v9_3_1_exdes is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(39-1 DOWNTO 0);
DOUT : OUT std_logic_vector(39-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_dma_0_wrapper_fifo_generator_v9_3_1_exdes;
architecture xilinx of system_axi_dma_0_wrapper_fifo_generator_v9_3_1_exdes is
signal clk_i : std_logic;
component system_axi_dma_0_wrapper_fifo_generator_v9_3_1 is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(39-1 DOWNTO 0);
DOUT : OUT std_logic_vector(39-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_dma_0_wrapper_fifo_generator_v9_3_1
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
mit
|
d33c19d6f3350e24eec194473eb43479
| 0.517296 | 4.745833 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_synth.vhd
| 1 | 40,219 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
S_ACLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_synth IS
CONSTANT AWID_OFFSET : INTEGER := if_then_else(1 = 1,63 - 1,63);
CONSTANT AWADDR_OFFSET : INTEGER := AWID_OFFSET - 32;
CONSTANT AWLEN_OFFSET : INTEGER := if_then_else(1 = 1,AWADDR_OFFSET - 8,AWADDR_OFFSET);
CONSTANT AWSIZE_OFFSET : INTEGER := if_then_else(1 = 1,AWLEN_OFFSET - 3,AWLEN_OFFSET);
CONSTANT AWBURST_OFFSET : INTEGER := if_then_else(1 = 1,AWSIZE_OFFSET - 2,AWSIZE_OFFSET);
CONSTANT AWLOCK_OFFSET : INTEGER := if_then_else(1 = 1,AWBURST_OFFSET - 2,AWBURST_OFFSET);
CONSTANT AWCACHE_OFFSET : INTEGER := if_then_else(1 = 1,AWLOCK_OFFSET - 4,AWLOCK_OFFSET);
CONSTANT AWPROT_OFFSET : INTEGER := AWCACHE_OFFSET - 3;
CONSTANT AWQOS_OFFSET : INTEGER := AWPROT_OFFSET - 4;
CONSTANT AWREGION_OFFSET : INTEGER := AWQOS_OFFSET - 4;
CONSTANT AWUSER_OFFSET : INTEGER := if_then_else(0 = 1,AWREGION_OFFSET-4,AWREGION_OFFSET);
CONSTANT WID_OFFSET : INTEGER := if_then_else(1 = 1,74 - 1,74);
CONSTANT WDATA_OFFSET : INTEGER := WID_OFFSET - 64;
CONSTANT WSTRB_OFFSET : INTEGER := WDATA_OFFSET - 64/8;
CONSTANT WUSER_OFFSET : INTEGER := if_then_else(0 = 1,WSTRB_OFFSET-1,WSTRB_OFFSET);
CONSTANT BID_OFFSET : INTEGER := if_then_else(1 = 1,6 - 1,6);
CONSTANT BRESP_OFFSET : INTEGER := BID_OFFSET - 2;
CONSTANT BUSER_OFFSET : INTEGER := if_then_else(0 = 1,BRESP_OFFSET-1,BRESP_OFFSET);
CONSTANT ARID_OFFSET : INTEGER := if_then_else(1 = 1,63 - 1,63);
CONSTANT ARADDR_OFFSET : INTEGER := ARID_OFFSET - 32;
CONSTANT ARLEN_OFFSET : INTEGER := if_then_else(1 = 1,ARADDR_OFFSET - 8,ARADDR_OFFSET);
CONSTANT ARSIZE_OFFSET : INTEGER := if_then_else(1 = 1,ARLEN_OFFSET - 3,ARLEN_OFFSET);
CONSTANT ARBURST_OFFSET : INTEGER := if_then_else(1 = 1,ARSIZE_OFFSET - 2,ARSIZE_OFFSET);
CONSTANT ARLOCK_OFFSET : INTEGER := if_then_else(1 = 1,ARBURST_OFFSET - 2,ARBURST_OFFSET);
CONSTANT ARCACHE_OFFSET : INTEGER := if_then_else(1 = 1,ARLOCK_OFFSET - 4,ARLOCK_OFFSET);
CONSTANT ARPROT_OFFSET : INTEGER := ARCACHE_OFFSET - 3;
CONSTANT ARQOS_OFFSET : INTEGER := ARPROT_OFFSET - 4;
CONSTANT ARREGION_OFFSET : INTEGER := ARQOS_OFFSET - 4;
CONSTANT ARUSER_OFFSET : INTEGER := if_then_else(0 = 1,ARREGION_OFFSET-4,ARREGION_OFFSET);
CONSTANT RID_OFFSET : INTEGER := if_then_else(1 = 1,68 - 1,68);
CONSTANT RDATA_OFFSET : INTEGER := RID_OFFSET - 64;
CONSTANT RRESP_OFFSET : INTEGER := RDATA_OFFSET - 2;
CONSTANT RUSER_OFFSET : INTEGER := if_then_else(0 = 1,RRESP_OFFSET-1,RRESP_OFFSET);
-- FIFO interface signal declarations
SIGNAL s_aresetn : STD_LOGIC;
SIGNAL m_axi_awid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL m_axi_awaddr : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL m_axi_awlen : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL m_axi_awsize : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL m_axi_awburst : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL m_axi_awlock : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL m_axi_awcache : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL m_axi_awprot : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL m_axi_awqos : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL m_axi_awregion : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL m_axi_awvalid : STD_LOGIC;
SIGNAL m_axi_awready : STD_LOGIC;
SIGNAL m_axi_wid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL m_axi_wdata : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL m_axi_wstrb : STD_LOGIC_VECTOR(64/8-1 DOWNTO 0);
SIGNAL m_axi_wlast : STD_LOGIC;
SIGNAL m_axi_wvalid : STD_LOGIC;
SIGNAL m_axi_wready : STD_LOGIC;
SIGNAL m_axi_bid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL m_axi_bresp : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL m_axi_bvalid : STD_LOGIC;
SIGNAL m_axi_bready : STD_LOGIC;
SIGNAL s_axi_awid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL s_axi_awaddr : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL s_axi_awlen : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL s_axi_awsize : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL s_axi_awburst : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL s_axi_awlock : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL s_axi_awcache : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL s_axi_awprot : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL s_axi_awqos : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL s_axi_awregion : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL s_axi_awvalid : STD_LOGIC;
SIGNAL s_axi_awready : STD_LOGIC;
SIGNAL s_axi_wid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL s_axi_wdata : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL s_axi_wstrb : STD_LOGIC_VECTOR(64/8-1 DOWNTO 0);
SIGNAL s_axi_wlast : STD_LOGIC;
SIGNAL s_axi_wvalid : STD_LOGIC;
SIGNAL s_axi_wready : STD_LOGIC;
SIGNAL s_axi_bid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL s_axi_bresp : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL s_axi_bvalid : STD_LOGIC;
SIGNAL s_axi_bready : STD_LOGIC;
SIGNAL m_axi_arid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL m_axi_araddr : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL m_axi_arlen : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL m_axi_arsize : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL m_axi_arburst : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL m_axi_arlock : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL m_axi_arcache : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL m_axi_arprot : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL m_axi_arqos : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL m_axi_arregion : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL m_axi_arvalid : STD_LOGIC;
SIGNAL m_axi_arready : STD_LOGIC;
SIGNAL m_axi_rid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL m_axi_rdata : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL m_axi_rresp : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL m_axi_rlast : STD_LOGIC;
SIGNAL m_axi_rvalid : STD_LOGIC;
SIGNAL m_axi_rready : STD_LOGIC;
SIGNAL s_axi_arid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL s_axi_araddr : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL s_axi_arlen : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL s_axi_arsize : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL s_axi_arburst : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL s_axi_arlock : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL s_axi_arcache : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL s_axi_arprot : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL s_axi_arqos : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL s_axi_arregion : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL s_axi_arvalid : STD_LOGIC;
SIGNAL s_axi_arready : STD_LOGIC;
SIGNAL s_axi_rid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL s_axi_rdata : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL s_axi_rresp : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL s_axi_rlast : STD_LOGIC;
SIGNAL s_axi_rvalid : STD_LOGIC;
SIGNAL s_axi_rready : STD_LOGIC;
SIGNAL axi_aw_prog_full : STD_LOGIC;
SIGNAL axi_aw_prog_empty : STD_LOGIC;
SIGNAL axi_w_prog_full : STD_LOGIC;
SIGNAL axi_w_prog_empty : STD_LOGIC;
SIGNAL axi_b_prog_full : STD_LOGIC;
SIGNAL axi_b_prog_empty : STD_LOGIC;
SIGNAL axi_ar_prog_full : STD_LOGIC;
SIGNAL axi_ar_prog_empty : STD_LOGIC;
SIGNAL axi_r_prog_full : STD_LOGIC;
SIGNAL axi_r_prog_empty : STD_LOGIC;
SIGNAL s_aclk_i : STD_LOGIC;
-- TB Signals
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL status_wach : STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL status_wdch : STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL status_wrch : STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL sim_done_wach : STD_LOGIC := '0';
SIGNAL sim_done_wdch : STD_LOGIC := '0';
SIGNAL sim_done_wrch : STD_LOGIC := '0';
SIGNAL reset_en_wach : STD_LOGIC := '0';
SIGNAL reset_en_wdch : STD_LOGIC := '0';
SIGNAL reset_en_wrch : STD_LOGIC := '0';
SIGNAL wr_en_wach : STD_LOGIC := '0';
SIGNAL rd_en_wach : STD_LOGIC := '0';
SIGNAL full_wach : STD_LOGIC := '0';
SIGNAL empty_wach : STD_LOGIC := '0';
SIGNAL wr_en_wdch : STD_LOGIC := '0';
SIGNAL rd_en_wdch : STD_LOGIC := '0';
SIGNAL full_wdch : STD_LOGIC := '0';
SIGNAL empty_wdch : STD_LOGIC := '0';
SIGNAL wr_en_wrch : STD_LOGIC := '0';
SIGNAL rd_en_wrch : STD_LOGIC := '0';
SIGNAL full_wrch : STD_LOGIC := '0';
SIGNAL empty_wrch : STD_LOGIC := '0';
SIGNAL prc_we_wach : STD_LOGIC := '0';
SIGNAL prc_we_wdch : STD_LOGIC := '0';
SIGNAL prc_we_wrch : STD_LOGIC := '0';
SIGNAL prc_re_wach : STD_LOGIC := '0';
SIGNAL prc_re_wdch : STD_LOGIC := '0';
SIGNAL prc_re_wrch : STD_LOGIC := '0';
SIGNAL dout_chk_wach : STD_LOGIC := '0';
SIGNAL dout_chk_wdch : STD_LOGIC := '0';
SIGNAL dout_chk_wrch : STD_LOGIC := '0';
SIGNAL status_rach : STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL status_rdch : STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL sim_done_rach : STD_LOGIC := '0';
SIGNAL sim_done_rdch : STD_LOGIC := '0';
SIGNAL reset_en_rach : STD_LOGIC := '0';
SIGNAL reset_en_rdch : STD_LOGIC := '0';
SIGNAL wr_en_rach : STD_LOGIC := '0';
SIGNAL rd_en_rach : STD_LOGIC := '0';
SIGNAL full_rach : STD_LOGIC := '0';
SIGNAL empty_rach : STD_LOGIC := '0';
SIGNAL wr_en_rdch : STD_LOGIC := '0';
SIGNAL rd_en_rdch : STD_LOGIC := '0';
SIGNAL full_rdch : STD_LOGIC := '0';
SIGNAL empty_rdch : STD_LOGIC := '0';
SIGNAL prc_we_rach : STD_LOGIC := '0';
SIGNAL prc_we_rdch : STD_LOGIC := '0';
SIGNAL prc_re_rach : STD_LOGIC := '0';
SIGNAL prc_re_rdch : STD_LOGIC := '0';
SIGNAL dout_chk_rach : STD_LOGIC := '0';
SIGNAL dout_chk_rdch : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL din_wach : STD_LOGIC_VECTOR(63-1 DOWNTO 0);
SIGNAL din_wdch : STD_LOGIC_VECTOR(74-1 DOWNTO 0);
SIGNAL din_wrch : STD_LOGIC_VECTOR(6-1 DOWNTO 0);
SIGNAL dout_wach : STD_LOGIC_VECTOR(63-1 DOWNTO 0);
SIGNAL dout_wdch : STD_LOGIC_VECTOR(74-1 DOWNTO 0);
SIGNAL dout_wrch : STD_LOGIC_VECTOR(6-1 DOWNTO 0);
SIGNAL din_rach : STD_LOGIC_VECTOR(63-1 DOWNTO 0);
SIGNAL din_rdch : STD_LOGIC_VECTOR(68-1 DOWNTO 0);
SIGNAL dout_rach : STD_LOGIC_VECTOR(63-1 DOWNTO 0);
SIGNAL dout_rdch : STD_LOGIC_VECTOR(68-1 DOWNTO 0);
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(s_aclk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(s_aclk_i'event AND s_aclk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(s_aclk_i)
BEGIN
IF(s_aclk_i'event AND s_aclk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
s_aclk_i <= S_ACLK;
------------------
s_aresetn <= NOT (RESET OR rst_s_rd) AFTER 12 ns;
STATUS <= status_wach OR status_wdch OR status_wrch OR status_rach OR status_rdch;
SIM_DONE <= sim_done_wach AND sim_done_wdch AND sim_done_wrch AND sim_done_rach AND sim_done_rdch;
reset_en <= reset_en_wach AND reset_en_wdch AND reset_en_wrch AND reset_en_rach AND reset_en_rdch;
s_axi_awvalid <= wr_en_wach;
m_axi_awready <= rd_en_wach;
full_wach <= NOT s_axi_awready;
empty_wach <= NOT m_axi_awvalid;
s_axi_wvalid <= wr_en_wdch;
m_axi_wready <= rd_en_wdch;
full_wdch <= NOT s_axi_wready;
empty_wdch <= NOT m_axi_wvalid;
m_axi_bvalid <= wr_en_wrch;
s_axi_bready <= rd_en_wrch;
full_wrch <= NOT m_axi_bready;
empty_wrch <= NOT s_axi_bvalid;
--- WACH
fg_dg_wach: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dgen
GENERIC MAP (
C_DIN_WIDTH => 63,
C_DOUT_WIDTH => 63,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_wr,
WR_CLK => s_aclk_i,
PRC_WR_EN => prc_we_wach,
FULL => full_wach,
WR_EN => wr_en_wach,
WR_DATA => din_wach
);
fg_dv_wach: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dverif
GENERIC MAP (
C_DOUT_WIDTH => 63,
C_DIN_WIDTH => 63,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => s_aclk_i,
PRC_RD_EN => prc_re_wach,
RD_EN => rd_en_wach,
EMPTY => empty_wach,
DATA_OUT => dout_wach,
DOUT_CHK => dout_chk_wach
);
fg_pc_wach: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pctrl
GENERIC MAP (
AXI_CHANNEL => "WACH",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 63,
C_DIN_WIDTH => 63,
C_WR_PNTR_WIDTH => 5,
C_RD_PNTR_WIDTH => 5,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_STOP_CNT => TB_STOP_CNT,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en_wach,
WR_CLK => s_aclk_i,
RD_CLK => s_aclk_i,
PRC_WR_EN => prc_we_wach,
PRC_RD_EN => prc_re_wach,
FULL => full_wach,
EMPTY => empty_wach,
ALMOST_FULL => '0',
ALMOST_EMPTY => '0',
DATA_IN => din_wach,
DATA_OUT => dout_wach,
DOUT_CHK => dout_chk_wach,
SIM_DONE => sim_done_wach,
STATUS => status_wach
);
--- WDCH
fg_dg_wdch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dgen
GENERIC MAP (
C_DIN_WIDTH => 74,
C_DOUT_WIDTH => 74,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP (
RESET => rst_int_wr,
WR_CLK => s_aclk_i,
PRC_WR_EN => prc_we_wdch,
FULL => full_wdch,
WR_EN => wr_en_wdch,
WR_DATA => din_wdch
);
fg_dv_wdch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dverif
GENERIC MAP (
C_DOUT_WIDTH => 74,
C_DIN_WIDTH => 74,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP (
RESET => rst_int_rd,
RD_CLK => s_aclk_i,
PRC_RD_EN => prc_re_wdch,
RD_EN => rd_en_wdch,
EMPTY => empty_wdch,
DATA_OUT => dout_wdch,
DOUT_CHK => dout_chk_wdch
);
fg_pc_wdch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pctrl
GENERIC MAP (
AXI_CHANNEL => "WDCH",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 74,
C_DIN_WIDTH => 74,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_STOP_CNT => TB_STOP_CNT,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP (
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en_wdch,
WR_CLK => s_aclk_i,
RD_CLK => s_aclk_i,
PRC_WR_EN => prc_we_wdch,
PRC_RD_EN => prc_re_wdch,
FULL => full_wdch,
EMPTY => empty_wdch,
ALMOST_FULL => '0',
ALMOST_EMPTY => '0',
DATA_IN => din_wdch,
DATA_OUT => dout_wdch,
DOUT_CHK => dout_chk_wdch,
SIM_DONE => sim_done_wdch,
STATUS => status_wdch
);
--- WRCH
fg_dg_wrch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dgen
GENERIC MAP (
C_DIN_WIDTH => 6,
C_DOUT_WIDTH => 6,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_rd,
WR_CLK => s_aclk_i,
PRC_WR_EN => prc_we_wrch,
FULL => full_wrch,
WR_EN => wr_en_wrch,
WR_DATA => din_wrch
);
fg_dv_wrch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dverif
GENERIC MAP (
C_DOUT_WIDTH => 6,
C_DIN_WIDTH => 6,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_wr,
RD_CLK => s_aclk_i,
PRC_RD_EN => prc_re_wrch,
RD_EN => rd_en_wrch,
EMPTY => empty_wrch,
DATA_OUT => dout_wrch,
DOUT_CHK => dout_chk_wrch
);
fg_pc_wrch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pctrl
GENERIC MAP (
AXI_CHANNEL => "WRCH",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 6,
C_DIN_WIDTH => 6,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_STOP_CNT => TB_STOP_CNT,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET_WR => rst_int_rd,
RESET_RD => rst_int_wr,
RESET_EN => reset_en_wrch,
WR_CLK => s_aclk_i,
RD_CLK => s_aclk_i,
PRC_WR_EN => prc_we_wrch,
PRC_RD_EN => prc_re_wrch,
FULL => full_wrch,
EMPTY => empty_wrch,
ALMOST_FULL => '0',
ALMOST_EMPTY => '0',
DATA_IN => din_wrch,
DATA_OUT => dout_wrch,
DOUT_CHK => dout_chk_wrch,
SIM_DONE => sim_done_wrch,
STATUS => status_wrch
);
dout_wach <= m_axi_awid & m_axi_awaddr & m_axi_awlen & m_axi_awsize & m_axi_awburst & m_axi_awlock
& m_axi_awcache & m_axi_awprot & m_axi_awqos & m_axi_awregion;
s_axi_awid <= din_wach(63-1 DOWNTO AWID_OFFSET);
s_axi_awaddr <= din_wach(AWID_OFFSET-1 DOWNTO AWADDR_OFFSET);
s_axi_awlen <= din_wach(AWADDR_OFFSET-1 DOWNTO AWLEN_OFFSET);
s_axi_awsize <= din_wach(AWLEN_OFFSET-1 DOWNTO AWSIZE_OFFSET);
s_axi_awburst <= din_wach(AWSIZE_OFFSET-1 DOWNTO AWBURST_OFFSET);
s_axi_awlock <= din_wach(AWBURST_OFFSET-1 DOWNTO AWLOCK_OFFSET);
s_axi_awcache <= din_wach(AWLOCK_OFFSET-1 DOWNTO AWCACHE_OFFSET);
s_axi_awprot <= din_wach(AWCACHE_OFFSET-1 DOWNTO AWPROT_OFFSET);
s_axi_awqos <= din_wach(AWPROT_OFFSET-1 DOWNTO AWQOS_OFFSET);
s_axi_awregion <= din_wach(AWQOS_OFFSET-1 DOWNTO AWREGION_OFFSET);
dout_wdch <= m_axi_wid & m_axi_wdata & m_axi_wstrb & m_axi_wlast;
s_axi_wid <= din_wdch(74-1 DOWNTO WID_OFFSET);
s_axi_wdata <= din_wdch(WID_OFFSET-1 DOWNTO WDATA_OFFSET);
s_axi_wstrb <= din_wdch(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET);
s_axi_wlast <= din_wdch(0);
dout_wrch <= s_axi_bid & s_axi_bresp;
m_axi_bid <= din_wrch(6-1 DOWNTO BID_OFFSET);
m_axi_bresp <= din_wrch(BID_OFFSET-1 DOWNTO BRESP_OFFSET);
s_axi_arvalid <= wr_en_rach;
m_axi_arready <= rd_en_rach;
full_rach <= NOT s_axi_arready;
empty_rach <= NOT m_axi_arvalid;
m_axi_rvalid <= wr_en_rdch;
s_axi_rready <= rd_en_rdch;
full_rdch <= NOT m_axi_rready;
empty_rdch <= NOT s_axi_rvalid;
--- RACH
fg_dg_rach: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dgen
GENERIC MAP (
C_DIN_WIDTH => 63,
C_DOUT_WIDTH => 63,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_wr,
WR_CLK => s_aclk_i,
PRC_WR_EN => prc_we_rach,
FULL => full_rach,
WR_EN => wr_en_rach,
WR_DATA => din_rach
);
fg_dv_rach: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dverif
GENERIC MAP (
C_DOUT_WIDTH => 63,
C_DIN_WIDTH => 63,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_rd,
RD_CLK => s_aclk_i,
PRC_RD_EN => prc_re_rach,
RD_EN => rd_en_rach,
EMPTY => empty_rach,
DATA_OUT => dout_rach,
DOUT_CHK => dout_chk_rach
);
fg_pc_rach: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pctrl
GENERIC MAP (
AXI_CHANNEL => "RACH",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 63,
C_DIN_WIDTH => 63,
C_WR_PNTR_WIDTH => 5,
C_RD_PNTR_WIDTH => 5,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_STOP_CNT => TB_STOP_CNT,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en_rach,
WR_CLK => s_aclk_i,
RD_CLK => s_aclk_i,
PRC_WR_EN => prc_we_rach,
PRC_RD_EN => prc_re_rach,
FULL => full_rach,
EMPTY => empty_rach,
ALMOST_FULL => '0',
ALMOST_EMPTY => '0',
DATA_IN => din_rach,
DATA_OUT => dout_rach,
DOUT_CHK => dout_chk_rach,
SIM_DONE => sim_done_rach,
STATUS => status_rach
);
--- RDCH
fg_dg_rdch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dgen
GENERIC MAP (
C_DIN_WIDTH => 68,
C_DOUT_WIDTH => 68,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_rd,
WR_CLK => s_aclk_i,
PRC_WR_EN => prc_we_rdch,
FULL => full_rdch,
WR_EN => wr_en_rdch,
WR_DATA => din_rdch
);
fg_dv_rdch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dverif
GENERIC MAP (
C_DOUT_WIDTH => 68,
C_DIN_WIDTH => 68,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_wr,
RD_CLK => s_aclk_i,
PRC_RD_EN => prc_re_rdch,
RD_EN => rd_en_rdch,
EMPTY => empty_rdch,
DATA_OUT => dout_rdch,
DOUT_CHK => dout_chk_rdch
);
fg_pc_rdch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pctrl
GENERIC MAP (
AXI_CHANNEL => "RDCH",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 68,
C_DIN_WIDTH => 68,
C_WR_PNTR_WIDTH => 1,
C_RD_PNTR_WIDTH => 1,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_STOP_CNT => TB_STOP_CNT,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET_WR => rst_int_rd,
RESET_RD => rst_int_wr,
RESET_EN => reset_en_rdch,
WR_CLK => s_aclk_i,
RD_CLK => s_aclk_i,
PRC_WR_EN => prc_we_rdch,
PRC_RD_EN => prc_re_rdch,
FULL => full_rdch,
EMPTY => empty_rdch,
ALMOST_FULL => '0',
ALMOST_EMPTY => '0',
DATA_IN => din_rdch,
DATA_OUT => dout_rdch,
DOUT_CHK => dout_chk_rdch,
SIM_DONE => sim_done_rdch,
STATUS => status_rdch
);
dout_rach <= m_axi_arid & m_axi_araddr & m_axi_arlen & m_axi_arsize & m_axi_arburst & m_axi_arlock & m_axi_arcache & m_axi_arprot
& m_axi_arqos & m_axi_arregion;
s_axi_arid <= din_rach(63-1 DOWNTO ARID_OFFSET);
s_axi_araddr <= din_rach(ARID_OFFSET-1 DOWNTO ARADDR_OFFSET);
s_axi_arlen <= din_rach(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET);
s_axi_arsize <= din_rach(ARLEN_OFFSET-1 DOWNTO ARSIZE_OFFSET);
s_axi_arburst <= din_rach(ARSIZE_OFFSET-1 DOWNTO ARBURST_OFFSET);
s_axi_arlock <= din_rach(ARBURST_OFFSET-1 DOWNTO ARLOCK_OFFSET);
s_axi_arcache <= din_rach(ARLOCK_OFFSET-1 DOWNTO ARCACHE_OFFSET);
s_axi_arprot <= din_rach(ARCACHE_OFFSET-1 DOWNTO ARPROT_OFFSET);
s_axi_arqos <= din_rach(ARPROT_OFFSET-1 DOWNTO ARQOS_OFFSET);
s_axi_arregion <= din_rach(ARQOS_OFFSET-1 DOWNTO ARREGION_OFFSET);
dout_rdch <= s_axi_rid & s_axi_rdata & s_axi_rresp & s_axi_rlast;
m_axi_rid <= din_rdch(68-1 DOWNTO RID_OFFSET);
m_axi_rdata <= din_rdch(RID_OFFSET-1 DOWNTO RDATA_OFFSET);
m_axi_rresp <= din_rdch(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET);
m_axi_rlast <= din_rdch(0);
system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_exdes
PORT MAP (
S_ARESETN => s_aresetn,
M_AXI_AWID => m_axi_awid,
M_AXI_AWADDR => m_axi_awaddr,
M_AXI_AWLEN => m_axi_awlen,
M_AXI_AWSIZE => m_axi_awsize,
M_AXI_AWBURST => m_axi_awburst,
M_AXI_AWLOCK => m_axi_awlock,
M_AXI_AWCACHE => m_axi_awcache,
M_AXI_AWPROT => m_axi_awprot,
M_AXI_AWQOS => m_axi_awqos,
M_AXI_AWREGION => m_axi_awregion,
M_AXI_AWVALID => m_axi_awvalid,
M_AXI_AWREADY => m_axi_awready,
M_AXI_WID => m_axi_wid,
M_AXI_WDATA => m_axi_wdata,
M_AXI_WSTRB => m_axi_wstrb,
M_AXI_WLAST => m_axi_wlast,
M_AXI_WVALID => m_axi_wvalid,
M_AXI_WREADY => m_axi_wready,
M_AXI_BID => m_axi_bid,
M_AXI_BRESP => m_axi_bresp,
M_AXI_BVALID => m_axi_bvalid,
M_AXI_BREADY => m_axi_bready,
S_AXI_AWID => s_axi_awid,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWLEN => s_axi_awlen,
S_AXI_AWSIZE => s_axi_awsize,
S_AXI_AWBURST => s_axi_awburst,
S_AXI_AWLOCK => s_axi_awlock,
S_AXI_AWCACHE => s_axi_awcache,
S_AXI_AWPROT => s_axi_awprot,
S_AXI_AWQOS => s_axi_awqos,
S_AXI_AWREGION => s_axi_awregion,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WID => s_axi_wid,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WLAST => s_axi_wlast,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BID => s_axi_bid,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
M_AXI_ARID => m_axi_arid,
M_AXI_ARADDR => m_axi_araddr,
M_AXI_ARLEN => m_axi_arlen,
M_AXI_ARSIZE => m_axi_arsize,
M_AXI_ARBURST => m_axi_arburst,
M_AXI_ARLOCK => m_axi_arlock,
M_AXI_ARCACHE => m_axi_arcache,
M_AXI_ARPROT => m_axi_arprot,
M_AXI_ARQOS => m_axi_arqos,
M_AXI_ARREGION => m_axi_arregion,
M_AXI_ARVALID => m_axi_arvalid,
M_AXI_ARREADY => m_axi_arready,
M_AXI_RID => m_axi_rid,
M_AXI_RDATA => m_axi_rdata,
M_AXI_RRESP => m_axi_rresp,
M_AXI_RLAST => m_axi_rlast,
M_AXI_RVALID => m_axi_rvalid,
M_AXI_RREADY => m_axi_rready,
S_AXI_ARID => s_axi_arid,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARLEN => s_axi_arlen,
S_AXI_ARSIZE => s_axi_arsize,
S_AXI_ARBURST => s_axi_arburst,
S_AXI_ARLOCK => s_axi_arlock,
S_AXI_ARCACHE => s_axi_arcache,
S_AXI_ARPROT => s_axi_arprot,
S_AXI_ARQOS => s_axi_arqos,
S_AXI_ARREGION => s_axi_arregion,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RID => s_axi_rid,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RLAST => s_axi_rlast,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
AXI_AW_PROG_FULL => axi_aw_prog_full,
AXI_AW_PROG_EMPTY => axi_aw_prog_empty,
AXI_W_PROG_FULL => axi_w_prog_full,
AXI_W_PROG_EMPTY => axi_w_prog_empty,
AXI_B_PROG_FULL => axi_b_prog_full,
AXI_B_PROG_EMPTY => axi_b_prog_empty,
AXI_AR_PROG_FULL => axi_ar_prog_full,
AXI_AR_PROG_EMPTY => axi_ar_prog_empty,
AXI_R_PROG_FULL => axi_r_prog_full,
AXI_R_PROG_EMPTY => axi_r_prog_empty,
S_ACLK => s_aclk_i);
END ARCHITECTURE;
|
mit
|
d329cfdf3dc93ba3386c7294e9a2967a
| 0.457122 | 3.729853 | false | false | false | false |
thasti/dvbs
|
hdl/scrambler/scrambler_tb.vhd
| 1 | 927 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity scrambler_tb is
end scrambler_tb;
architecture tb of scrambler_tb is
-- interface signals
signal clk : std_logic := '0';
signal clk_en : std_logic := '1';
signal rst : std_logic := '1';
signal sync : std_logic := '0';
signal d : std_logic_vector(7 downto 0) := (others => '0');
signal q : std_logic_vector(7 downto 0);
begin
dut : entity work.scrambler
port map (
clk => clk,
clk_en => clk_en,
rst => rst,
sync => sync,
d => d,
q => q
);
clk <= not clk after 100 ns;
rst <= '0' after 500 ns;
process
begin
wait until falling_edge(rst);
wait until rising_edge(clk);
for i in 0 to 1880 loop
d <= std_logic_vector(to_unsigned(i mod 256,8));
if i mod 188 = 0 then
sync <= '1';
else
sync <= '0';
end if;
wait until rising_edge(clk);
end loop;
sync <= '0';
wait;
end process;
end tb;
|
gpl-2.0
|
c5d16b5984afdcffaa760c2445ff5c6b
| 0.609493 | 2.589385 | false | false | false | false |
thasti/dvbs
|
hdl/network/eth_rx/eth_rx.vhd
| 1 | 4,633 |
-- ethernet deframing unit
-- gets all data bytes from rmii_rx
-- outputs the frame payload, to a FIFO interface
--
-- Note: This is very dirty :-) The following assumptions are made:
-- - EthernetII is used, no VLAN tag
-- - only IPv4 packets are received
-- - The IPv4 header has standard length (no optional flags)
-- - All packets on UDP port 40000 are directed towards us
-- - no MAC-, IP- or checksum fields are checked
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity eth_rx is
port (
clk : in std_logic;
rst : in std_logic;
rxd : in std_logic_vector(1 downto 0);
crsdv : in std_logic;
q : out std_logic_vector(7 downto 0);
q_valid : out std_logic
);
end eth_rx;
architecture behav of eth_rx is
-- ethernet frame constants
constant type_ip_hi : std_logic_vector(7 downto 0) := x"08";
constant type_ip_lo : std_logic_vector(7 downto 0) := x"00";
constant type_udp : std_logic_vector(7 downto 0) := x"11";
constant port_udp_hi : std_logic_vector(7 downto 0) := x"9C";
constant port_udp_lo : std_logic_vector(7 downto 0) := x"40";
-- ethernet frame offsets
constant ethtype_hi_off : unsigned(10 downto 0) := to_unsigned(12, 11);
constant ethtype_lo_off : unsigned(10 downto 0) := to_unsigned(13, 11);
constant iptype_off : unsigned(10 downto 0) := to_unsigned(23, 11);
constant port_hi_off : unsigned(10 downto 0) := to_unsigned(36, 11);
constant port_lo_off : unsigned(10 downto 0) := to_unsigned(37, 11);
constant udplen_hi_off : unsigned(10 downto 0) := to_unsigned(38, 11);
constant udplen_lo_off : unsigned(10 downto 0) := to_unsigned(39, 11);
constant udpcrc_lo_off : unsigned(10 downto 0) := to_unsigned(41, 11);
constant udp_header_len : unsigned(10 downto 0) := to_unsigned(8, 11);
type rx_states is (idle, packet, payload, endofpacket);
signal state : rx_states := idle;
signal eth_count : unsigned(10 downto 0) := (others => '0');
signal payload_count : unsigned(10 downto 0) := (others => '0');
signal udp_size : unsigned(10 downto 0) := (others => '0');
signal rx_byte : std_logic_vector(7 downto 0);
signal rx_dv : std_logic;
signal rx_crs : std_logic;
begin
rmii_rx : entity work.rmii_rx
port map (clk => clk, rst => rst, rxd => rxd, crsdv => crsdv, rx_byte => rx_byte, rx_dv => rx_dv, rx_crs => rx_crs);
process
begin
wait until rising_edge(clk);
if rst = '1' then
eth_count <= to_unsigned(0, eth_count'length);
payload_count <= to_unsigned(0, payload_count'length);
udp_size <= to_unsigned(0, udp_size'length);
q_valid <= '0';
q <= (others => '0');
end if;
case state is
when idle =>
if rx_crs = '1' then
eth_count <= to_unsigned(0, eth_count'length);
state <= packet;
end if;
when packet =>
if rx_dv = '1' then
if eth_count = ethtype_hi_off and rx_byte /= type_ip_hi then
report "Not an IP packet (High)!";
state <= endofpacket;
end if;
if eth_count = ethtype_lo_off and rx_byte /= type_ip_lo then
report "Not an IP packet (Low)!";
state <= endofpacket;
end if;
if eth_count = iptype_off and rx_byte /= type_udp then
report "Not an UDP packet!";
state <= endofpacket;
end if;
if eth_count = port_hi_off and rx_byte /= port_udp_hi then
report "Port not correct (High)!";
state <= endofpacket;
end if;
if eth_count = port_lo_off and rx_byte /= port_udp_lo then
report "Port not correct (Low)!";
state <= endofpacket;
end if;
if eth_count = udplen_hi_off then
report "Latched Length (High)!";
udp_size(10 downto 8) <= unsigned(rx_byte(2 downto 0));
end if;
if eth_count = udplen_lo_off then
report "Latched Length (Low)!";
udp_size(7 downto 0) <= unsigned(rx_byte);
end if;
if eth_count = udpcrc_lo_off then
report "Begin of Payload!";
payload_count <= udp_size;
state <= payload;
end if;
eth_count <= eth_count + to_unsigned(1, eth_count'length);
end if;
if rx_crs = '0' then
state <= idle;
end if;
when payload =>
if rx_dv = '1' then
payload_count <= payload_count - to_unsigned(1, payload_count'length);
if payload_count = udp_header_len then
state <= endofpacket;
q_valid <= '0';
else
report "Wrote byte to FIFO.";
q_valid <= '1';
q <= rx_byte;
end if;
else
q_valid <= '0';
end if;
if rx_crs = '0' then
report "Packet end too early.";
state <= idle;
end if;
when endofpacket =>
if rx_crs = '0' then
state <= idle;
end if;
end case;
end process;
end behav;
|
gpl-2.0
|
e4011e6a5893f0dd7b27d4d66da87d30
| 0.622275 | 2.941587 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_1/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pctrl.vhd
| 1 | 16,633 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pkg.ALL;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND FULL = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_dma_0_wrapper_fifo_generator_v9_3_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_dma_0_wrapper_fifo_generator_v9_3_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
mit
|
49ff6819a4ffadf3f33dd12911c91d6d
| 0.523838 | 3.331931 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_2/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pkg.vhd
| 1 | 11,921 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_2_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_2_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_2_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_2_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_2_exdes IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(3-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(9-1 DOWNTO 0);
DOUT : OUT std_logic_vector(9-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pkg;
PACKAGE BODY system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pkg;
|
mit
|
200289b1e34a290262c3c4ea6a29dd7d
| 0.513128 | 3.856681 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_dgen.vhd
| 1 | 4,761 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
mit
|
0002927db7a8b2bff08eab0ae1d3d140
| 0.611006 | 4.118512 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth.vhd
| 1 | 11,096 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(7-1 DOWNTO 0);
SIGNAL wr_ack : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(35-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(35-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(35-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(35-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 50 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
fg_dg_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen
GENERIC MAP (
C_DIN_WIDTH => 35,
C_DOUT_WIDTH => 35,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_3_dverif
GENERIC MAP (
C_DOUT_WIDTH => 35,
C_DIN_WIDTH => 35,
C_USE_EMBEDDED_REG => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_3_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 35,
C_DIN_WIDTH => 35,
C_WR_PNTR_WIDTH => 7,
C_RD_PNTR_WIDTH => 7,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_vdma_0_wrapper_fifo_generator_v9_3_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
mit
|
dd9c663fa8ef8e44d516e7d8008749d4
| 0.467376 | 4.06894 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_dgen.vhd
| 1 | 4,760 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
mit
|
a4880e3600cc903b2f6aff4814a5dc78
| 0.610924 | 4.117647 | false | false | false | false |
migraichen/picocpu
|
simulation/picocpu_tb.vhd
| 1 | 12,424 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity picocpu_tb is
end picocpu_tb;
architecture behavioral of picocpu_tb is
component picocpu_rom is
port (
clk_in : in std_logic;
address_in : in std_logic_vector( 9 downto 0);
instruction_out : out std_logic_vector(17 downto 0)
);
end component;
component picocpu is
port (
clk_in : in std_logic;
rst_n_in : in std_logic;
-- Signale zumdo Programmspeicher
inst_addr_out : out std_logic_vector( 9 downto 0) := ( others => '0' );
inst_data_in : in std_logic_vector(17 downto 0);
-- Output / Input Port
port_id_out : out std_logic_vector( 7 downto 0) := ( others => '0' );
port_wr_pulse_out : out std_logic := '0';
port_data_out : out std_logic_vector( 7 downto 0) := ( others => '0' );
port_rd_pulse_out : out std_logic := '0';
port_data_in : in std_logic_vector( 7 downto 0);
-- Interrupt Port
int_in : in std_logic;
int_ack_out : out std_logic := '0'
);
end component;
constant sysclk_period_c : time := 25 ns;
constant reg_width_c : natural := 8;
constant opcode_width_c : natural := 10;
-- constant inst_width_c : natural := opcode_width_c + reg_width_c;
constant inst_width_c : natural := 18;
constant inst_depth_c : natural := 10;
signal sysclk : std_logic := '0';
signal rst_n : std_logic := '0';
-- Signale zwischen dem Programmspeicher und der Prozessor
signal inst_address : std_logic_vector(inst_depth_c-1 downto 0) := ( others => '0' );
signal instruction : std_logic_vector(inst_width_c-1 downto 0) := ( others => '0' );
-- Signale des Output / Inpot Port
signal port_id : std_logic_vector( reg_width_c-1 downto 0) := ( others => '0' );
signal port_wr_pulse : std_logic := '0';
signal port_data_out : std_logic_vector( reg_width_c-1 downto 0) := ( others => '0' );
signal port_rd_pulse : std_logic := '0';
signal port_data_in : std_logic_vector( reg_width_c-1 downto 0) := ( others => '0' );
-- Signale des Interrupt Port
signal int : std_logic := '0';
signal int_ack : std_logic := '0';
-- Debug Instruction Decode
signal inst_decoded : string(1 to 19) := " ";
begin
-- Erzeuge sysclk-Signal
system_clock : process
begin
sysclk <= '0';
wait for sysclk_period_c/2;
sysclk <= '1';
wait for sysclk_period_c/2;
end process;
-- Erzeuge rst_n-Signal
system_reset : process
begin
rst_n <= '1';
wait for sysclk_period_c*10;
rst_n <= '0';
wait for sysclk_period_c*10;
rst_n <= '1';
wait;
end process;
system_interrupt : process
begin
int <= '0';
--wait;
wait for 930 ns;
int <= '1';
wait until int_ack <= '1';
wait until rising_edge(sysclk);
int <= '0';
end process;
system_data_in : process
begin
wait until rising_edge(sysclk);
port_data_in <= std_logic_vector(unsigned(port_data_in) + 1);
end process;
socket_picocpu_rom : picocpu_rom
port map (
clk_in => sysclk,
address_in => inst_address,
instruction_out => instruction
);
socket_picocpu : picocpu
port map (
clk_in => sysclk,
rst_n_in => rst_n,
-- Signale zum Programmspeicher
inst_addr_out => inst_address,
inst_data_in => instruction,
-- Output / Input Port
port_id_out => port_id,
port_wr_pulse_out => port_wr_pulse,
port_data_out => port_data_out,
port_rd_pulse_out => port_rd_pulse,
port_data_in => port_data_in,
-- Interrupt Port
int_in => int,
int_ack_out => int_ack
);
---------------------------------
-- DEBUG :: Instruction Decode --
---------------------------------
sim_debug : process (sysclk, instruction)
variable picocpu_opcode : string(1 to 19);
variable sx_decode : string(1 to 2); --sX register specification
variable sy_decode : string(1 to 2); --sY register specification
variable kk_decode : string(1 to 2); --constant value specification
variable aaa_decode : string(1 to 3); --address specification
function hexcharacter (nibble: std_logic_vector(3 downto 0))
return character is
variable hex: character;
begin
case nibble is
when "0000" => hex := '0';
when "0001" => hex := '1';
when "0010" => hex := '2';
when "0011" => hex := '3';
when "0100" => hex := '4';
when "0101" => hex := '5';
when "0110" => hex := '6';
when "0111" => hex := '7';
when "1000" => hex := '8';
when "1001" => hex := '9';
when "1010" => hex := 'A';
when "1011" => hex := 'B';
when "1100" => hex := 'C';
when "1101" => hex := 'D';
when "1110" => hex := 'E';
when "1111" => hex := 'F';
when others => hex := 'x';
end case;
return hex;
end hexcharacter;
begin
-- decode first register
sx_decode(1) := 's';
sx_decode(2) := hexcharacter(instruction(11 downto 8));
-- decode second register
sy_decode(1) := 's';
sy_decode(2) := hexcharacter(instruction(7 downto 4));
-- decode constant value
kk_decode(1) := hexcharacter(instruction(7 downto 4));
kk_decode(2) := hexcharacter(instruction(3 downto 0));
-- address value
aaa_decode(1) := hexcharacter("00" & instruction(9 downto 8));
aaa_decode(2) := hexcharacter(instruction(7 downto 4));
aaa_decode(3) := hexcharacter(instruction(3 downto 0));
-- decode instruction
case instruction(17 downto 12) is
when "000000" => picocpu_opcode := "LOAD " & sx_decode & ',' & kk_decode & " ";
when "000001" => picocpu_opcode := "LOAD " & sx_decode & ',' & sy_decode & " ";
when "001010" => picocpu_opcode := "AND " & sx_decode & ',' & kk_decode & " ";
when "001011" => picocpu_opcode := "AND " & sx_decode & ',' & sy_decode & " ";
when "001100" => picocpu_opcode := "OR " & sx_decode & ',' & kk_decode & " ";
when "001101" => picocpu_opcode := "OR " & sx_decode & ',' & sy_decode & " ";
when "001110" => picocpu_opcode := "XOR " & sx_decode & ',' & kk_decode & " ";
when "001111" => picocpu_opcode := "XOR " & sx_decode & ',' & sy_decode & " ";
when "010010" => picocpu_opcode := "TEST " & sx_decode & ',' & kk_decode & " ";
when "010011" => picocpu_opcode := "TEST " & sx_decode & ',' & sy_decode & " ";
when "011000" => picocpu_opcode := "ADD " & sx_decode & ',' & kk_decode & " ";
when "011001" => picocpu_opcode := "ADD " & sx_decode & ',' & sy_decode & " ";
when "011010" => picocpu_opcode := "ADDCY " & sx_decode & ',' & kk_decode & " ";
when "011011" => picocpu_opcode := "ADDCY " & sx_decode & ',' & sy_decode & " ";
when "011100" => picocpu_opcode := "SUB " & sx_decode & ',' & kk_decode & " ";
when "011101" => picocpu_opcode := "SUB " & sx_decode & ',' & sy_decode & " ";
when "011110" => picocpu_opcode := "SUBCY " & sx_decode & ',' & kk_decode & " ";
when "011111" => picocpu_opcode := "SUBCY " & sx_decode & ',' & sy_decode & " ";
when "010100" => picocpu_opcode := "COMPARE " & sx_decode & ',' & kk_decode & " ";
when "010101" => picocpu_opcode := "COMPARE " & sx_decode & ',' & sy_decode & " ";
when "100000" =>
case instruction(3 downto 0) is
when "0110" => picocpu_opcode := "SL0 " & sx_decode & " ";
when "0111" => picocpu_opcode := "SL1 " & sx_decode & " ";
when "0100" => picocpu_opcode := "SLX " & sx_decode & " ";
when "0000" => picocpu_opcode := "SLA " & sx_decode & " ";
when "0010" => picocpu_opcode := "RL " & sx_decode & " ";
when "1110" => picocpu_opcode := "SR0 " & sx_decode & " ";
when "1111" => picocpu_opcode := "SR1 " & sx_decode & " ";
when "1010" => picocpu_opcode := "SRX " & sx_decode & " ";
when "1000" => picocpu_opcode := "SRA " & sx_decode & " ";
when "1100" => picocpu_opcode := "RR " & sx_decode & " ";
when others => picocpu_opcode := "Invalid Instruction";
end case;
when "101100" => picocpu_opcode := "OUTPUT " & sx_decode & ',' & kk_decode & " ";
when "101101" => picocpu_opcode := "OUTPUT " & sx_decode & ",(" & sy_decode & ") ";
when "000100" => picocpu_opcode := "INPUT " & sx_decode & ',' & kk_decode & " ";
when "000101" => picocpu_opcode := "INPUT " & sx_decode & ",(" & sy_decode & ") ";
when "101110" => picocpu_opcode := "STORE " & sx_decode & ',' & kk_decode & " ";
when "101111" => picocpu_opcode := "STORE " & sx_decode & ",(" & sy_decode & ") ";
when "000110" => picocpu_opcode := "FETCH " & sx_decode & ',' & kk_decode & " ";
when "000111" => picocpu_opcode := "FETCH " & sx_decode & ",(" & sy_decode & ") ";
when "110100" => picocpu_opcode := "JUMP " & aaa_decode & " ";
when "110101" =>
case instruction(11 downto 10) is
when "00" => picocpu_opcode := "JUMP Z," & aaa_decode & " ";
when "01" => picocpu_opcode := "JUMP NZ," & aaa_decode & " ";
when "10" => picocpu_opcode := "JUMP C," & aaa_decode & " ";
when "11" => picocpu_opcode := "JUMP NC," & aaa_decode & " ";
when others => picocpu_opcode := "Invalid Instruction";
end case;
when "110000" => picocpu_opcode := "CALL " & aaa_decode & " ";
when "110001" =>
case instruction(11 downto 10) is
when "00" => picocpu_opcode := "CALL Z," & aaa_decode & " ";
when "01" => picocpu_opcode := "CALL NZ," & aaa_decode & " ";
when "10" => picocpu_opcode := "CALL C," & aaa_decode & " ";
when "11" => picocpu_opcode := "CALL NC," & aaa_decode & " ";
when others => picocpu_opcode := "Invalid Instruction";
end case;
when "101010" => picocpu_opcode := "RETURN ";
when "101011" =>
case instruction(11 downto 10) is
when "00" => picocpu_opcode := "RETURN Z ";
when "01" => picocpu_opcode := "RETURN NZ ";
when "10" => picocpu_opcode := "RETURN C ";
when "11" => picocpu_opcode := "RETURN NC ";
when others => picocpu_opcode := "Invalid Instruction";
end case;
when "111000" =>
case instruction(0) is
when '0' => picocpu_opcode := "RETURNI DISABLE ";
when '1' => picocpu_opcode := "RETURNI ENABLE ";
when others => picocpu_opcode := "Invalid Instruction";
end case;
when "111100" =>
case instruction(0) is
when '0' => picocpu_opcode := "DISABLE INTERRUPT ";
when '1' => picocpu_opcode := "ENABLE INTERRUPT ";
when others => picocpu_opcode := "Invalid Instruction";
end case;
when others => picocpu_opcode := "Invalid Instruction";
end case;
inst_decoded <= picocpu_opcode;
end process;
end behavioral;
|
gpl-2.0
|
e411ff2e603755f1f153ae8199939677
| 0.478429 | 3.802877 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_tb.vhd
| 1 | 6,128 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_tb IS
END ENTITY;
ARCHITECTURE system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2000 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_synth
system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_synth_inst:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 40
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
mit
|
8f1581eb5eba5eb071f4f08c8b125261
| 0.63267 | 4.050231 | false | false | false | false |
thasti/dvbs
|
hdl/interleaver/interleaver.vhd
| 1 | 2,827 |
-- interleaver
--
-- The interleaver consists of I branches, each of them containing i*M bytes.
-- The first branch (index 0) includes no memory. The output is registered,
-- therefore this block introduces one cycle of delay.
-- sync resets the interleaver to the first branch
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity interleaver is
generic (
I : positive := 12; -- number of branches
M : positive := 17 -- elementary branch depth in bytes
);
port (
clk : in std_logic;
rst : in std_logic;
clk_en : in std_logic;
sync : in std_logic;
d : in std_logic_vector(7 downto 0);
q : out std_logic_vector(7 downto 0)
);
end interleaver;
architecture rtl of interleaver is
-- ram declaration (containing the delay line)
constant ram_length : positive := M * (I-1) * I / 2;
constant ram_bits : positive := integer(ceil(log2(real(ram_length))));
type memory_t is array(ram_length-1 downto 0) of std_logic_vector(7 downto 0);
signal ram : memory_t;
-- branch counter
constant I_bits : positive := integer(ceil(log2(real(I))));
signal branch : unsigned(I_bits-1 downto 0) := (others => '0');
-- intra branch address counters
constant iba_bits : positive := integer(ceil(log2(real((I-1)*M))));
type iba is array(0 to I-2) of unsigned(iba_bits-1 downto 0);
signal iba_cnt : iba := (others => (others => '0'));
signal addr_dbg : std_logic_vector(ram_bits-1 downto 0);
begin
intra_branch_counters : process
begin
wait until rising_edge(clk);
if rst = '1' then
for j in 1 to I-2 loop
iba_cnt(j) <= (others => '0');
end loop;
elsif clk_en = '1' then
if branch /= to_unsigned(0, iba_bits) then
if iba_cnt(to_integer(branch) - 1) = to_unsigned(to_integer(branch) * M - 1, iba_bits) then
iba_cnt(to_integer(branch) - 1) <= (others => '0');
else
iba_cnt(to_integer(branch) - 1) <= iba_cnt(to_integer(branch) - 1) + to_unsigned(1, iba_bits);
end if;
end if;
end if;
end process;
ram_access : process
variable addr : unsigned(ram_bits-1 downto 0) := (others => '0');
begin
wait until rising_edge(clk);
if clk_en = '1' then
if branch = to_unsigned(0, branch'length) then
q <= d;
else
-- RAM offset for current branch
-- plus intra-branch-offset for current branch
-- FIXME move complex calculation into offset LUT
addr := to_unsigned(
(to_integer(branch) - 1) * M * to_integer(branch) / 2 +
to_integer(iba_cnt(to_integer(branch)-1)), ram_bits);
addr_dbg <= std_logic_vector(addr);
ram(to_integer(addr)) <= d;
q <= ram(to_integer(addr));
end if;
if branch = to_unsigned(I-1, I_bits) then
branch <= to_unsigned(0, branch'length);
else
branch <= branch + to_unsigned(1, branch'length);
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
95e9acd31432f48f8b87ab2a1105f501
| 0.651574 | 2.954023 | false | false | false | false |
migraichen/picocpu
|
picocpu_rom.vhd
| 1 | 903 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library rom_init;
use rom_init.cpu_rom.all;
entity picocpu_rom is
port (
clk_in : in std_logic;
address_in : in std_logic_vector( 9 downto 0);
instruction_out : out std_logic_vector(17 downto 0)
);
end picocpu_rom;
architecture behavioral of picocpu_rom is
-- constant rom_addr_width_c : natural := address_in'length;
-- constant rom_data_width_c : natural := instruction_out'length;
-- type rom_type is array (0 to (2**rom_addr_width_c)-1) of std_logic_vector(rom_data_width_c-1 downto 0);
-- signal rom : rom_type := ( others => ( others => '0' ) );--
begin
process(clk_in)
begin
if clk_in'event and clk_in = '1' then
instruction_out <= rom(to_integer(unsigned(address_in)));
end if;
end process;
end behavioral;
|
gpl-2.0
|
cfe4f60a2dfb104b6b9f9cfdec87332c
| 0.615725 | 3.146341 | false | false | false | false |
meninge/dauphin
|
bram.vhd
| 1 | 947 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram is
generic (
WDATA : natural := 16;
SIZE : natural := 784;
WADDR : natural := 10
);
port (
clk : in std_logic;
we: in std_logic;
en: in std_logic;
addr : in std_logic_vector(WADDR-1 downto 0);
di: in std_logic_vector(WDATA-1 downto 0);
do: out std_logic_vector(WDATA-1 downto 0));
end ram;
architecture syn of ram is
type ram_type is array (SIZE-1 downto 0) of std_logic_vector (WDATA-1 downto 0);
signal RAM : ram_type := (others => (others => '0'));
begin
---------------------------------------------
----------- Sequential processes ------------
---------------------------------------------
process (clk)
begin
if rising_edge(clk) then
if en = '1' then
if we = '1' then
RAM(to_integer(unsigned(addr))) <= di;
end if;
do <= RAM(to_integer(unsigned(addr))) ;
end if;
end if;
end process;
end syn;
|
mit
|
45a453f3cb9483ae22dd1dc795004ff7
| 0.554382 | 3.084691 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_synth.vhd
| 1 | 40,219 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
S_ACLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_synth IS
CONSTANT AWID_OFFSET : INTEGER := if_then_else(1 = 1,63 - 1,63);
CONSTANT AWADDR_OFFSET : INTEGER := AWID_OFFSET - 32;
CONSTANT AWLEN_OFFSET : INTEGER := if_then_else(1 = 1,AWADDR_OFFSET - 8,AWADDR_OFFSET);
CONSTANT AWSIZE_OFFSET : INTEGER := if_then_else(1 = 1,AWLEN_OFFSET - 3,AWLEN_OFFSET);
CONSTANT AWBURST_OFFSET : INTEGER := if_then_else(1 = 1,AWSIZE_OFFSET - 2,AWSIZE_OFFSET);
CONSTANT AWLOCK_OFFSET : INTEGER := if_then_else(1 = 1,AWBURST_OFFSET - 2,AWBURST_OFFSET);
CONSTANT AWCACHE_OFFSET : INTEGER := if_then_else(1 = 1,AWLOCK_OFFSET - 4,AWLOCK_OFFSET);
CONSTANT AWPROT_OFFSET : INTEGER := AWCACHE_OFFSET - 3;
CONSTANT AWQOS_OFFSET : INTEGER := AWPROT_OFFSET - 4;
CONSTANT AWREGION_OFFSET : INTEGER := AWQOS_OFFSET - 4;
CONSTANT AWUSER_OFFSET : INTEGER := if_then_else(0 = 1,AWREGION_OFFSET-4,AWREGION_OFFSET);
CONSTANT WID_OFFSET : INTEGER := if_then_else(1 = 1,74 - 1,74);
CONSTANT WDATA_OFFSET : INTEGER := WID_OFFSET - 64;
CONSTANT WSTRB_OFFSET : INTEGER := WDATA_OFFSET - 64/8;
CONSTANT WUSER_OFFSET : INTEGER := if_then_else(0 = 1,WSTRB_OFFSET-1,WSTRB_OFFSET);
CONSTANT BID_OFFSET : INTEGER := if_then_else(1 = 1,6 - 1,6);
CONSTANT BRESP_OFFSET : INTEGER := BID_OFFSET - 2;
CONSTANT BUSER_OFFSET : INTEGER := if_then_else(0 = 1,BRESP_OFFSET-1,BRESP_OFFSET);
CONSTANT ARID_OFFSET : INTEGER := if_then_else(1 = 1,63 - 1,63);
CONSTANT ARADDR_OFFSET : INTEGER := ARID_OFFSET - 32;
CONSTANT ARLEN_OFFSET : INTEGER := if_then_else(1 = 1,ARADDR_OFFSET - 8,ARADDR_OFFSET);
CONSTANT ARSIZE_OFFSET : INTEGER := if_then_else(1 = 1,ARLEN_OFFSET - 3,ARLEN_OFFSET);
CONSTANT ARBURST_OFFSET : INTEGER := if_then_else(1 = 1,ARSIZE_OFFSET - 2,ARSIZE_OFFSET);
CONSTANT ARLOCK_OFFSET : INTEGER := if_then_else(1 = 1,ARBURST_OFFSET - 2,ARBURST_OFFSET);
CONSTANT ARCACHE_OFFSET : INTEGER := if_then_else(1 = 1,ARLOCK_OFFSET - 4,ARLOCK_OFFSET);
CONSTANT ARPROT_OFFSET : INTEGER := ARCACHE_OFFSET - 3;
CONSTANT ARQOS_OFFSET : INTEGER := ARPROT_OFFSET - 4;
CONSTANT ARREGION_OFFSET : INTEGER := ARQOS_OFFSET - 4;
CONSTANT ARUSER_OFFSET : INTEGER := if_then_else(0 = 1,ARREGION_OFFSET-4,ARREGION_OFFSET);
CONSTANT RID_OFFSET : INTEGER := if_then_else(1 = 1,68 - 1,68);
CONSTANT RDATA_OFFSET : INTEGER := RID_OFFSET - 64;
CONSTANT RRESP_OFFSET : INTEGER := RDATA_OFFSET - 2;
CONSTANT RUSER_OFFSET : INTEGER := if_then_else(0 = 1,RRESP_OFFSET-1,RRESP_OFFSET);
-- FIFO interface signal declarations
SIGNAL s_aresetn : STD_LOGIC;
SIGNAL m_axi_awid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL m_axi_awaddr : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL m_axi_awlen : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL m_axi_awsize : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL m_axi_awburst : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL m_axi_awlock : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL m_axi_awcache : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL m_axi_awprot : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL m_axi_awqos : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL m_axi_awregion : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL m_axi_awvalid : STD_LOGIC;
SIGNAL m_axi_awready : STD_LOGIC;
SIGNAL m_axi_wid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL m_axi_wdata : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL m_axi_wstrb : STD_LOGIC_VECTOR(64/8-1 DOWNTO 0);
SIGNAL m_axi_wlast : STD_LOGIC;
SIGNAL m_axi_wvalid : STD_LOGIC;
SIGNAL m_axi_wready : STD_LOGIC;
SIGNAL m_axi_bid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL m_axi_bresp : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL m_axi_bvalid : STD_LOGIC;
SIGNAL m_axi_bready : STD_LOGIC;
SIGNAL s_axi_awid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL s_axi_awaddr : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL s_axi_awlen : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL s_axi_awsize : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL s_axi_awburst : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL s_axi_awlock : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL s_axi_awcache : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL s_axi_awprot : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL s_axi_awqos : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL s_axi_awregion : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL s_axi_awvalid : STD_LOGIC;
SIGNAL s_axi_awready : STD_LOGIC;
SIGNAL s_axi_wid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL s_axi_wdata : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL s_axi_wstrb : STD_LOGIC_VECTOR(64/8-1 DOWNTO 0);
SIGNAL s_axi_wlast : STD_LOGIC;
SIGNAL s_axi_wvalid : STD_LOGIC;
SIGNAL s_axi_wready : STD_LOGIC;
SIGNAL s_axi_bid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL s_axi_bresp : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL s_axi_bvalid : STD_LOGIC;
SIGNAL s_axi_bready : STD_LOGIC;
SIGNAL m_axi_arid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL m_axi_araddr : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL m_axi_arlen : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL m_axi_arsize : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL m_axi_arburst : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL m_axi_arlock : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL m_axi_arcache : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL m_axi_arprot : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL m_axi_arqos : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL m_axi_arregion : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL m_axi_arvalid : STD_LOGIC;
SIGNAL m_axi_arready : STD_LOGIC;
SIGNAL m_axi_rid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL m_axi_rdata : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL m_axi_rresp : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL m_axi_rlast : STD_LOGIC;
SIGNAL m_axi_rvalid : STD_LOGIC;
SIGNAL m_axi_rready : STD_LOGIC;
SIGNAL s_axi_arid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL s_axi_araddr : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL s_axi_arlen : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL s_axi_arsize : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL s_axi_arburst : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL s_axi_arlock : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL s_axi_arcache : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL s_axi_arprot : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL s_axi_arqos : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL s_axi_arregion : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL s_axi_arvalid : STD_LOGIC;
SIGNAL s_axi_arready : STD_LOGIC;
SIGNAL s_axi_rid : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL s_axi_rdata : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL s_axi_rresp : STD_LOGIC_VECTOR(2-1 DOWNTO 0);
SIGNAL s_axi_rlast : STD_LOGIC;
SIGNAL s_axi_rvalid : STD_LOGIC;
SIGNAL s_axi_rready : STD_LOGIC;
SIGNAL axi_aw_prog_full : STD_LOGIC;
SIGNAL axi_aw_prog_empty : STD_LOGIC;
SIGNAL axi_w_prog_full : STD_LOGIC;
SIGNAL axi_w_prog_empty : STD_LOGIC;
SIGNAL axi_b_prog_full : STD_LOGIC;
SIGNAL axi_b_prog_empty : STD_LOGIC;
SIGNAL axi_ar_prog_full : STD_LOGIC;
SIGNAL axi_ar_prog_empty : STD_LOGIC;
SIGNAL axi_r_prog_full : STD_LOGIC;
SIGNAL axi_r_prog_empty : STD_LOGIC;
SIGNAL s_aclk_i : STD_LOGIC;
-- TB Signals
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL status_wach : STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL status_wdch : STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL status_wrch : STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL sim_done_wach : STD_LOGIC := '0';
SIGNAL sim_done_wdch : STD_LOGIC := '0';
SIGNAL sim_done_wrch : STD_LOGIC := '0';
SIGNAL reset_en_wach : STD_LOGIC := '0';
SIGNAL reset_en_wdch : STD_LOGIC := '0';
SIGNAL reset_en_wrch : STD_LOGIC := '0';
SIGNAL wr_en_wach : STD_LOGIC := '0';
SIGNAL rd_en_wach : STD_LOGIC := '0';
SIGNAL full_wach : STD_LOGIC := '0';
SIGNAL empty_wach : STD_LOGIC := '0';
SIGNAL wr_en_wdch : STD_LOGIC := '0';
SIGNAL rd_en_wdch : STD_LOGIC := '0';
SIGNAL full_wdch : STD_LOGIC := '0';
SIGNAL empty_wdch : STD_LOGIC := '0';
SIGNAL wr_en_wrch : STD_LOGIC := '0';
SIGNAL rd_en_wrch : STD_LOGIC := '0';
SIGNAL full_wrch : STD_LOGIC := '0';
SIGNAL empty_wrch : STD_LOGIC := '0';
SIGNAL prc_we_wach : STD_LOGIC := '0';
SIGNAL prc_we_wdch : STD_LOGIC := '0';
SIGNAL prc_we_wrch : STD_LOGIC := '0';
SIGNAL prc_re_wach : STD_LOGIC := '0';
SIGNAL prc_re_wdch : STD_LOGIC := '0';
SIGNAL prc_re_wrch : STD_LOGIC := '0';
SIGNAL dout_chk_wach : STD_LOGIC := '0';
SIGNAL dout_chk_wdch : STD_LOGIC := '0';
SIGNAL dout_chk_wrch : STD_LOGIC := '0';
SIGNAL status_rach : STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL status_rdch : STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL sim_done_rach : STD_LOGIC := '0';
SIGNAL sim_done_rdch : STD_LOGIC := '0';
SIGNAL reset_en_rach : STD_LOGIC := '0';
SIGNAL reset_en_rdch : STD_LOGIC := '0';
SIGNAL wr_en_rach : STD_LOGIC := '0';
SIGNAL rd_en_rach : STD_LOGIC := '0';
SIGNAL full_rach : STD_LOGIC := '0';
SIGNAL empty_rach : STD_LOGIC := '0';
SIGNAL wr_en_rdch : STD_LOGIC := '0';
SIGNAL rd_en_rdch : STD_LOGIC := '0';
SIGNAL full_rdch : STD_LOGIC := '0';
SIGNAL empty_rdch : STD_LOGIC := '0';
SIGNAL prc_we_rach : STD_LOGIC := '0';
SIGNAL prc_we_rdch : STD_LOGIC := '0';
SIGNAL prc_re_rach : STD_LOGIC := '0';
SIGNAL prc_re_rdch : STD_LOGIC := '0';
SIGNAL dout_chk_rach : STD_LOGIC := '0';
SIGNAL dout_chk_rdch : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL din_wach : STD_LOGIC_VECTOR(63-1 DOWNTO 0);
SIGNAL din_wdch : STD_LOGIC_VECTOR(74-1 DOWNTO 0);
SIGNAL din_wrch : STD_LOGIC_VECTOR(6-1 DOWNTO 0);
SIGNAL dout_wach : STD_LOGIC_VECTOR(63-1 DOWNTO 0);
SIGNAL dout_wdch : STD_LOGIC_VECTOR(74-1 DOWNTO 0);
SIGNAL dout_wrch : STD_LOGIC_VECTOR(6-1 DOWNTO 0);
SIGNAL din_rach : STD_LOGIC_VECTOR(63-1 DOWNTO 0);
SIGNAL din_rdch : STD_LOGIC_VECTOR(68-1 DOWNTO 0);
SIGNAL dout_rach : STD_LOGIC_VECTOR(63-1 DOWNTO 0);
SIGNAL dout_rdch : STD_LOGIC_VECTOR(68-1 DOWNTO 0);
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(s_aclk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(s_aclk_i'event AND s_aclk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(s_aclk_i)
BEGIN
IF(s_aclk_i'event AND s_aclk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
s_aclk_i <= S_ACLK;
------------------
s_aresetn <= NOT (RESET OR rst_s_rd) AFTER 12 ns;
STATUS <= status_wach OR status_wdch OR status_wrch OR status_rach OR status_rdch;
SIM_DONE <= sim_done_wach AND sim_done_wdch AND sim_done_wrch AND sim_done_rach AND sim_done_rdch;
reset_en <= reset_en_wach AND reset_en_wdch AND reset_en_wrch AND reset_en_rach AND reset_en_rdch;
s_axi_awvalid <= wr_en_wach;
m_axi_awready <= rd_en_wach;
full_wach <= NOT s_axi_awready;
empty_wach <= NOT m_axi_awvalid;
s_axi_wvalid <= wr_en_wdch;
m_axi_wready <= rd_en_wdch;
full_wdch <= NOT s_axi_wready;
empty_wdch <= NOT m_axi_wvalid;
m_axi_bvalid <= wr_en_wrch;
s_axi_bready <= rd_en_wrch;
full_wrch <= NOT m_axi_bready;
empty_wrch <= NOT s_axi_bvalid;
--- WACH
fg_dg_wach: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen
GENERIC MAP (
C_DIN_WIDTH => 63,
C_DOUT_WIDTH => 63,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_wr,
WR_CLK => s_aclk_i,
PRC_WR_EN => prc_we_wach,
FULL => full_wach,
WR_EN => wr_en_wach,
WR_DATA => din_wach
);
fg_dv_wach: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dverif
GENERIC MAP (
C_DOUT_WIDTH => 63,
C_DIN_WIDTH => 63,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => s_aclk_i,
PRC_RD_EN => prc_re_wach,
RD_EN => rd_en_wach,
EMPTY => empty_wach,
DATA_OUT => dout_wach,
DOUT_CHK => dout_chk_wach
);
fg_pc_wach: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pctrl
GENERIC MAP (
AXI_CHANNEL => "WACH",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 63,
C_DIN_WIDTH => 63,
C_WR_PNTR_WIDTH => 5,
C_RD_PNTR_WIDTH => 5,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_STOP_CNT => TB_STOP_CNT,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en_wach,
WR_CLK => s_aclk_i,
RD_CLK => s_aclk_i,
PRC_WR_EN => prc_we_wach,
PRC_RD_EN => prc_re_wach,
FULL => full_wach,
EMPTY => empty_wach,
ALMOST_FULL => '0',
ALMOST_EMPTY => '0',
DATA_IN => din_wach,
DATA_OUT => dout_wach,
DOUT_CHK => dout_chk_wach,
SIM_DONE => sim_done_wach,
STATUS => status_wach
);
--- WDCH
fg_dg_wdch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen
GENERIC MAP (
C_DIN_WIDTH => 74,
C_DOUT_WIDTH => 74,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_wr,
WR_CLK => s_aclk_i,
PRC_WR_EN => prc_we_wdch,
FULL => full_wdch,
WR_EN => wr_en_wdch,
WR_DATA => din_wdch
);
fg_dv_wdch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dverif
GENERIC MAP (
C_DOUT_WIDTH => 74,
C_DIN_WIDTH => 74,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_rd,
RD_CLK => s_aclk_i,
PRC_RD_EN => prc_re_wdch,
RD_EN => rd_en_wdch,
EMPTY => empty_wdch,
DATA_OUT => dout_wdch,
DOUT_CHK => dout_chk_wdch
);
fg_pc_wdch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pctrl
GENERIC MAP (
AXI_CHANNEL => "WDCH",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 74,
C_DIN_WIDTH => 74,
C_WR_PNTR_WIDTH => 1,
C_RD_PNTR_WIDTH => 1,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_STOP_CNT => TB_STOP_CNT,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en_wdch,
WR_CLK => s_aclk_i,
RD_CLK => s_aclk_i,
PRC_WR_EN => prc_we_wdch,
PRC_RD_EN => prc_re_wdch,
FULL => full_wdch,
EMPTY => empty_wdch,
ALMOST_FULL => '0',
ALMOST_EMPTY => '0',
DATA_IN => din_wdch,
DATA_OUT => dout_wdch,
DOUT_CHK => dout_chk_wdch,
SIM_DONE => sim_done_wdch,
STATUS => status_wdch
);
--- WRCH
fg_dg_wrch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen
GENERIC MAP (
C_DIN_WIDTH => 6,
C_DOUT_WIDTH => 6,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_rd,
WR_CLK => s_aclk_i,
PRC_WR_EN => prc_we_wrch,
FULL => full_wrch,
WR_EN => wr_en_wrch,
WR_DATA => din_wrch
);
fg_dv_wrch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dverif
GENERIC MAP (
C_DOUT_WIDTH => 6,
C_DIN_WIDTH => 6,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_wr,
RD_CLK => s_aclk_i,
PRC_RD_EN => prc_re_wrch,
RD_EN => rd_en_wrch,
EMPTY => empty_wrch,
DATA_OUT => dout_wrch,
DOUT_CHK => dout_chk_wrch
);
fg_pc_wrch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pctrl
GENERIC MAP (
AXI_CHANNEL => "WRCH",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 6,
C_DIN_WIDTH => 6,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_STOP_CNT => TB_STOP_CNT,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET_WR => rst_int_rd,
RESET_RD => rst_int_wr,
RESET_EN => reset_en_wrch,
WR_CLK => s_aclk_i,
RD_CLK => s_aclk_i,
PRC_WR_EN => prc_we_wrch,
PRC_RD_EN => prc_re_wrch,
FULL => full_wrch,
EMPTY => empty_wrch,
ALMOST_FULL => '0',
ALMOST_EMPTY => '0',
DATA_IN => din_wrch,
DATA_OUT => dout_wrch,
DOUT_CHK => dout_chk_wrch,
SIM_DONE => sim_done_wrch,
STATUS => status_wrch
);
dout_wach <= m_axi_awid & m_axi_awaddr & m_axi_awlen & m_axi_awsize & m_axi_awburst & m_axi_awlock
& m_axi_awcache & m_axi_awprot & m_axi_awqos & m_axi_awregion;
s_axi_awid <= din_wach(63-1 DOWNTO AWID_OFFSET);
s_axi_awaddr <= din_wach(AWID_OFFSET-1 DOWNTO AWADDR_OFFSET);
s_axi_awlen <= din_wach(AWADDR_OFFSET-1 DOWNTO AWLEN_OFFSET);
s_axi_awsize <= din_wach(AWLEN_OFFSET-1 DOWNTO AWSIZE_OFFSET);
s_axi_awburst <= din_wach(AWSIZE_OFFSET-1 DOWNTO AWBURST_OFFSET);
s_axi_awlock <= din_wach(AWBURST_OFFSET-1 DOWNTO AWLOCK_OFFSET);
s_axi_awcache <= din_wach(AWLOCK_OFFSET-1 DOWNTO AWCACHE_OFFSET);
s_axi_awprot <= din_wach(AWCACHE_OFFSET-1 DOWNTO AWPROT_OFFSET);
s_axi_awqos <= din_wach(AWPROT_OFFSET-1 DOWNTO AWQOS_OFFSET);
s_axi_awregion <= din_wach(AWQOS_OFFSET-1 DOWNTO AWREGION_OFFSET);
dout_wdch <= m_axi_wid & m_axi_wdata & m_axi_wstrb & m_axi_wlast;
s_axi_wid <= din_wdch(74-1 DOWNTO WID_OFFSET);
s_axi_wdata <= din_wdch(WID_OFFSET-1 DOWNTO WDATA_OFFSET);
s_axi_wstrb <= din_wdch(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET);
s_axi_wlast <= din_wdch(0);
dout_wrch <= s_axi_bid & s_axi_bresp;
m_axi_bid <= din_wrch(6-1 DOWNTO BID_OFFSET);
m_axi_bresp <= din_wrch(BID_OFFSET-1 DOWNTO BRESP_OFFSET);
s_axi_arvalid <= wr_en_rach;
m_axi_arready <= rd_en_rach;
full_rach <= NOT s_axi_arready;
empty_rach <= NOT m_axi_arvalid;
m_axi_rvalid <= wr_en_rdch;
s_axi_rready <= rd_en_rdch;
full_rdch <= NOT m_axi_rready;
empty_rdch <= NOT s_axi_rvalid;
--- RACH
fg_dg_rach: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen
GENERIC MAP (
C_DIN_WIDTH => 63,
C_DOUT_WIDTH => 63,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_wr,
WR_CLK => s_aclk_i,
PRC_WR_EN => prc_we_rach,
FULL => full_rach,
WR_EN => wr_en_rach,
WR_DATA => din_rach
);
fg_dv_rach: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dverif
GENERIC MAP (
C_DOUT_WIDTH => 63,
C_DIN_WIDTH => 63,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET => rst_int_rd,
RD_CLK => s_aclk_i,
PRC_RD_EN => prc_re_rach,
RD_EN => rd_en_rach,
EMPTY => empty_rach,
DATA_OUT => dout_rach,
DOUT_CHK => dout_chk_rach
);
fg_pc_rach: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pctrl
GENERIC MAP (
AXI_CHANNEL => "RACH",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 63,
C_DIN_WIDTH => 63,
C_WR_PNTR_WIDTH => 5,
C_RD_PNTR_WIDTH => 5,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_STOP_CNT => TB_STOP_CNT,
TB_SEED => TB_SEED,
C_CH_TYPE => 2
)
PORT MAP (
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en_rach,
WR_CLK => s_aclk_i,
RD_CLK => s_aclk_i,
PRC_WR_EN => prc_we_rach,
PRC_RD_EN => prc_re_rach,
FULL => full_rach,
EMPTY => empty_rach,
ALMOST_FULL => '0',
ALMOST_EMPTY => '0',
DATA_IN => din_rach,
DATA_OUT => dout_rach,
DOUT_CHK => dout_chk_rach,
SIM_DONE => sim_done_rach,
STATUS => status_rach
);
--- RDCH
fg_dg_rdch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen
GENERIC MAP (
C_DIN_WIDTH => 68,
C_DOUT_WIDTH => 68,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP (
RESET => rst_int_rd,
WR_CLK => s_aclk_i,
PRC_WR_EN => prc_we_rdch,
FULL => full_rdch,
WR_EN => wr_en_rdch,
WR_DATA => din_rdch
);
fg_dv_rdch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dverif
GENERIC MAP (
C_DOUT_WIDTH => 68,
C_DIN_WIDTH => 68,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP (
RESET => rst_int_wr,
RD_CLK => s_aclk_i,
PRC_RD_EN => prc_re_rdch,
RD_EN => rd_en_rdch,
EMPTY => empty_rdch,
DATA_OUT => dout_rdch,
DOUT_CHK => dout_chk_rdch
);
fg_pc_rdch: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pctrl
GENERIC MAP (
AXI_CHANNEL => "RDCH",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 68,
C_DIN_WIDTH => 68,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_STOP_CNT => TB_STOP_CNT,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP (
RESET_WR => rst_int_rd,
RESET_RD => rst_int_wr,
RESET_EN => reset_en_rdch,
WR_CLK => s_aclk_i,
RD_CLK => s_aclk_i,
PRC_WR_EN => prc_we_rdch,
PRC_RD_EN => prc_re_rdch,
FULL => full_rdch,
EMPTY => empty_rdch,
ALMOST_FULL => '0',
ALMOST_EMPTY => '0',
DATA_IN => din_rdch,
DATA_OUT => dout_rdch,
DOUT_CHK => dout_chk_rdch,
SIM_DONE => sim_done_rdch,
STATUS => status_rdch
);
dout_rach <= m_axi_arid & m_axi_araddr & m_axi_arlen & m_axi_arsize & m_axi_arburst & m_axi_arlock & m_axi_arcache & m_axi_arprot
& m_axi_arqos & m_axi_arregion;
s_axi_arid <= din_rach(63-1 DOWNTO ARID_OFFSET);
s_axi_araddr <= din_rach(ARID_OFFSET-1 DOWNTO ARADDR_OFFSET);
s_axi_arlen <= din_rach(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET);
s_axi_arsize <= din_rach(ARLEN_OFFSET-1 DOWNTO ARSIZE_OFFSET);
s_axi_arburst <= din_rach(ARSIZE_OFFSET-1 DOWNTO ARBURST_OFFSET);
s_axi_arlock <= din_rach(ARBURST_OFFSET-1 DOWNTO ARLOCK_OFFSET);
s_axi_arcache <= din_rach(ARLOCK_OFFSET-1 DOWNTO ARCACHE_OFFSET);
s_axi_arprot <= din_rach(ARCACHE_OFFSET-1 DOWNTO ARPROT_OFFSET);
s_axi_arqos <= din_rach(ARPROT_OFFSET-1 DOWNTO ARQOS_OFFSET);
s_axi_arregion <= din_rach(ARQOS_OFFSET-1 DOWNTO ARREGION_OFFSET);
dout_rdch <= s_axi_rid & s_axi_rdata & s_axi_rresp & s_axi_rlast;
m_axi_rid <= din_rdch(68-1 DOWNTO RID_OFFSET);
m_axi_rdata <= din_rdch(RID_OFFSET-1 DOWNTO RDATA_OFFSET);
m_axi_rresp <= din_rdch(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET);
m_axi_rlast <= din_rdch(0);
system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_exdes
PORT MAP (
S_ARESETN => s_aresetn,
M_AXI_AWID => m_axi_awid,
M_AXI_AWADDR => m_axi_awaddr,
M_AXI_AWLEN => m_axi_awlen,
M_AXI_AWSIZE => m_axi_awsize,
M_AXI_AWBURST => m_axi_awburst,
M_AXI_AWLOCK => m_axi_awlock,
M_AXI_AWCACHE => m_axi_awcache,
M_AXI_AWPROT => m_axi_awprot,
M_AXI_AWQOS => m_axi_awqos,
M_AXI_AWREGION => m_axi_awregion,
M_AXI_AWVALID => m_axi_awvalid,
M_AXI_AWREADY => m_axi_awready,
M_AXI_WID => m_axi_wid,
M_AXI_WDATA => m_axi_wdata,
M_AXI_WSTRB => m_axi_wstrb,
M_AXI_WLAST => m_axi_wlast,
M_AXI_WVALID => m_axi_wvalid,
M_AXI_WREADY => m_axi_wready,
M_AXI_BID => m_axi_bid,
M_AXI_BRESP => m_axi_bresp,
M_AXI_BVALID => m_axi_bvalid,
M_AXI_BREADY => m_axi_bready,
S_AXI_AWID => s_axi_awid,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWLEN => s_axi_awlen,
S_AXI_AWSIZE => s_axi_awsize,
S_AXI_AWBURST => s_axi_awburst,
S_AXI_AWLOCK => s_axi_awlock,
S_AXI_AWCACHE => s_axi_awcache,
S_AXI_AWPROT => s_axi_awprot,
S_AXI_AWQOS => s_axi_awqos,
S_AXI_AWREGION => s_axi_awregion,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WID => s_axi_wid,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WLAST => s_axi_wlast,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BID => s_axi_bid,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
M_AXI_ARID => m_axi_arid,
M_AXI_ARADDR => m_axi_araddr,
M_AXI_ARLEN => m_axi_arlen,
M_AXI_ARSIZE => m_axi_arsize,
M_AXI_ARBURST => m_axi_arburst,
M_AXI_ARLOCK => m_axi_arlock,
M_AXI_ARCACHE => m_axi_arcache,
M_AXI_ARPROT => m_axi_arprot,
M_AXI_ARQOS => m_axi_arqos,
M_AXI_ARREGION => m_axi_arregion,
M_AXI_ARVALID => m_axi_arvalid,
M_AXI_ARREADY => m_axi_arready,
M_AXI_RID => m_axi_rid,
M_AXI_RDATA => m_axi_rdata,
M_AXI_RRESP => m_axi_rresp,
M_AXI_RLAST => m_axi_rlast,
M_AXI_RVALID => m_axi_rvalid,
M_AXI_RREADY => m_axi_rready,
S_AXI_ARID => s_axi_arid,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARLEN => s_axi_arlen,
S_AXI_ARSIZE => s_axi_arsize,
S_AXI_ARBURST => s_axi_arburst,
S_AXI_ARLOCK => s_axi_arlock,
S_AXI_ARCACHE => s_axi_arcache,
S_AXI_ARPROT => s_axi_arprot,
S_AXI_ARQOS => s_axi_arqos,
S_AXI_ARREGION => s_axi_arregion,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RID => s_axi_rid,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RLAST => s_axi_rlast,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
AXI_AW_PROG_FULL => axi_aw_prog_full,
AXI_AW_PROG_EMPTY => axi_aw_prog_empty,
AXI_W_PROG_FULL => axi_w_prog_full,
AXI_W_PROG_EMPTY => axi_w_prog_empty,
AXI_B_PROG_FULL => axi_b_prog_full,
AXI_B_PROG_EMPTY => axi_b_prog_empty,
AXI_AR_PROG_FULL => axi_ar_prog_full,
AXI_AR_PROG_EMPTY => axi_ar_prog_empty,
AXI_R_PROG_FULL => axi_r_prog_full,
AXI_R_PROG_EMPTY => axi_r_prog_empty,
S_ACLK => s_aclk_i);
END ARCHITECTURE;
|
mit
|
1f8654de31994fa85687f752cdd12d3b
| 0.457122 | 3.729853 | false | false | false | false |
medav/conware
|
conware_test/system/pcores/cownare_ctl_v1_00_a/hdl/vhdl/cownare_ctl.vhd
| 1 | 19,038 |
------------------------------------------------------------------------------
-- cownare_ctl.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: cownare_ctl.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue May 02 19:23:30 2017 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity cownare_ctl is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
in_states : in std_logic_vector(7 downto 0);
out_states : in std_logic_vector(7 downto 0);
num_reads : in std_logic_vector(31 downto 0);
num_writes : in std_logic_vector(31 downto 0);
read_ctr : in std_logic_vector(7 downto 0);
write_ctr : in std_logic_vector(7 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity cownare_ctl;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of cownare_ctl is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
in_states : in std_logic_vector(7 downto 0);
out_states : in std_logic_vector(7 downto 0);
num_reads : in std_logic_vector(31 downto 0);
num_writes : in std_logic_vector(31 downto 0);
read_ctr : in std_logic_vector(7 downto 0);
write_ctr : in std_logic_vector(7 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
in_states => in_states,
out_states => out_states,
num_reads => num_reads,
num_writes => num_writes,
read_ctr => read_ctr,
write_ctr => write_ctr,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
mit
|
ac4bce22ae26e900ae45b57cce5562ec
| 0.460868 | 4.182337 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1/example_design/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes.vhd
| 1 | 5,073 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(6-1 DOWNTO 0);
DOUT : OUT std_logic_vector(6-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes;
architecture xilinx of system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes is
signal clk_i : std_logic;
component system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(6-1 DOWNTO 0);
DOUT : OUT std_logic_vector(6-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
mit
|
ba60717b79cf393e903e4fbdaab9b070
| 0.542874 | 4.767857 | false | false | false | false |
igraves/vhdl-gizmos
|
devices/clock_dividers/series7/eightdiv.vhd
| 1 | 3,539 |
library IEEE;
Library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.vcomponents.all;
entity eightdiv is
port(
clk : in std_logic;
clkdout : out std_logic;
clkout : out std_logic
);
end eightdiv;
architecture Behavioral of eightdiv is
constant LOW : std_logic := '0';
constant HIGH : std_logic := '1';
signal CLKFBOUT : std_logic;
begin
-- MMCME2_BASE: Base Mixed Mode Clock Manager
-- 7 Series
-- Xilinx HDL Libraries Guide, version 14.7
MMCME2_BASE_inst : MMCME2_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW)
CLKFBOUT_MULT_F => 2.0, -- Multiply value for all CLKOUT (2.000-64.000).
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (-360.000-360.000).
CLKIN1_PERIOD => 0.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT1_DIVIDE => 16,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT6_DIVIDE => 1,
CLKOUT0_DIVIDE_F => 2.0, -- Divide amount for CLKOUT0 (1.000-128.000).
-- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
CLKOUT6_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
CLKOUT6_PHASE => 0.0,
CLKOUT4_CASCADE => FALSE, -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
DIVCLK_DIVIDE => 1, -- Master division value (1-106)
REF_JITTER1 => 0.0, -- Reference input jitter in UI (0.000-0.999).
STARTUP_WAIT => FALSE -- Delays DONE until MMCM is locked (FALSE, TRUE)
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => clkout, -- 1-bit output: CLKOUT0
--CLKOUT0B => CLKOUT0B, -- 1-bit output: Inverted CLKOUT0
CLKOUT1 => clkdout, -- 1-bit output: CLKOUT1
--CLKOUT1B => CLKOUT1B, -- 1-bit output: Inverted CLKOUT1
--CLKOUT2 => CLKOUT2, -- 1-bit output: CLKOUT2
--CLKOUT2B => CLKOUT2B, -- 1-bit output: Inverted CLKOUT2
--CLKOUT3 => CLKOUT3, -- 1-bit output: CLKOUT3
--CLKOUT3B => CLKOUT3B, -- 1-bit output: Inverted CLKOUT3
--CLKOUT4 => CLKOUT4, -- 1-bit output: CLKOUT4
--CLKOUT5 => CLKOUT5, -- 1-bit output: CLKOUT5
--CLKOUT6 => CLKOUT6, -- 1-bit output: CLKOUT6
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT, -- 1-bit output: Feedback clock
--CLKFBOUTB => CLKFBOUTB, -- 1-bit output: Inverted CLKFBOUT
-- Status Ports: 1-bit (each) output: MMCM status ports
--LOCKED => LOCKED, -- 1-bit output: LOCK
-- Clock Inputs: 1-bit (each) input: Clock input
CLKIN1 => clk, -- 1-bit input: Clock
-- Control Ports: 1-bit (each) input: MMCM control ports
PWRDWN => LOW, -- 1-bit input: Power-down
RST => LOW, -- 1-bit input: Reset
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBOUT -- 1-bit input: Feedback clock
);
-- End of MMCME2_BASE_inst instantiation
end Behavioral;
|
mit
|
38c61d1bfe8d8730e8cd0f964bf3610c
| 0.623622 | 3.429264 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_synth.vhd
| 1 | 10,215 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_dgen
GENERIC MAP (
C_DIN_WIDTH => 1,
C_DOUT_WIDTH => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_dverif
GENERIC MAP (
C_DOUT_WIDTH => 1,
C_DIN_WIDTH => 1,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 1,
C_DIN_WIDTH => 1,
C_WR_PNTR_WIDTH => 5,
C_RD_PNTR_WIDTH => 5,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_exdes
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
mit
|
997c9a4cc8aec1043e40e9100f21e670
| 0.474107 | 4.087635 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_3/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_3_rng.vhd
| 1 | 4,001 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_3_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_3_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_3_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
mit
|
90bbcb57871973cd0f203f0fc2d4a503
| 0.64159 | 4.238347 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth.vhd
| 1 | 10,215 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(6-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(6-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(6-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(6-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_dgen
GENERIC MAP (
C_DIN_WIDTH => 6,
C_DOUT_WIDTH => 6,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_dverif
GENERIC MAP (
C_DOUT_WIDTH => 6,
C_DIN_WIDTH => 6,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 6,
C_DIN_WIDTH => 6,
C_WR_PNTR_WIDTH => 5,
C_RD_PNTR_WIDTH => 5,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
mit
|
333d038d2406f58674895de7f166bd5c
| 0.474107 | 4.087635 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pkg.vhd
| 1 | 17,482 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
S_ACLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_exdes IS
PORT (
S_ARESETN : IN std_logic;
M_AXI_AWID : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(64/8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
S_AXI_AWID : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(64/8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
M_AXI_ARID : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
S_AXI_ARID : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
AXI_AW_PROG_FULL : OUT std_logic;
AXI_AW_PROG_EMPTY : OUT std_logic;
AXI_W_PROG_FULL : OUT std_logic;
AXI_W_PROG_EMPTY : OUT std_logic;
AXI_B_PROG_FULL : OUT std_logic;
AXI_B_PROG_EMPTY : OUT std_logic;
AXI_AR_PROG_FULL : OUT std_logic;
AXI_AR_PROG_EMPTY : OUT std_logic;
AXI_R_PROG_FULL : OUT std_logic;
AXI_R_PROG_EMPTY : OUT std_logic;
S_ACLK : IN std_logic);
END COMPONENT;
------------------------
END system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pkg;
PACKAGE BODY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pkg;
|
mit
|
afdb6ffc2c1364b2223a6a429ba513a2
| 0.499085 | 3.757954 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dverif.vhd
| 1 | 5,736 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
mit
|
a04af93c5109dc3864a9fd9df01a2105
| 0.585251 | 4.02244 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_3/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_3_dverif.vhd
| 1 | 5,691 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_3_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pkg.ALL;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_3_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_3_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_dma_0_wrapper_fifo_generator_v9_3_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
mit
|
4f1b5f30cf4f38f2e9335774a5173c95
| 0.581972 | 3.990884 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4/example_design/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_exdes.vhd
| 1 | 21,095 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_exdes is
PORT (
S_ARESETN : IN std_logic;
M_AXI_AWID : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(64/8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
S_AXI_AWID : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(64/8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
M_AXI_ARID : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
S_AXI_ARID : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
AXI_AW_PROG_FULL : OUT std_logic;
AXI_AW_PROG_EMPTY : OUT std_logic;
AXI_W_PROG_FULL : OUT std_logic;
AXI_W_PROG_EMPTY : OUT std_logic;
AXI_B_PROG_FULL : OUT std_logic;
AXI_B_PROG_EMPTY : OUT std_logic;
AXI_AR_PROG_FULL : OUT std_logic;
AXI_AR_PROG_EMPTY : OUT std_logic;
AXI_R_PROG_FULL : OUT std_logic;
AXI_R_PROG_EMPTY : OUT std_logic;
S_ACLK : IN std_logic);
end system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_exdes;
architecture xilinx of system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_exdes is
signal s_aclk_i : std_logic;
component system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4 is
PORT (
S_ARESETN : IN std_logic;
M_AXI_AWID : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(64/8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
S_AXI_AWID : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(64/8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
M_AXI_ARID : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
S_AXI_ARID : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
AXI_AW_PROG_FULL : OUT std_logic;
AXI_AW_PROG_EMPTY : OUT std_logic;
AXI_W_PROG_FULL : OUT std_logic;
AXI_W_PROG_EMPTY : OUT std_logic;
AXI_B_PROG_FULL : OUT std_logic;
AXI_B_PROG_EMPTY : OUT std_logic;
AXI_AR_PROG_FULL : OUT std_logic;
AXI_AR_PROG_EMPTY : OUT std_logic;
AXI_R_PROG_FULL : OUT std_logic;
AXI_R_PROG_EMPTY : OUT std_logic;
S_ACLK : IN std_logic);
end component;
begin
s_aclk_buf: bufg
PORT map(
i => S_ACLK,
o => s_aclk_i
);
exdes_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4
PORT MAP (
S_ARESETN => s_aresetn,
M_AXI_AWID => m_axi_awid,
M_AXI_AWADDR => m_axi_awaddr,
M_AXI_AWLEN => m_axi_awlen,
M_AXI_AWSIZE => m_axi_awsize,
M_AXI_AWBURST => m_axi_awburst,
M_AXI_AWLOCK => m_axi_awlock,
M_AXI_AWCACHE => m_axi_awcache,
M_AXI_AWPROT => m_axi_awprot,
M_AXI_AWQOS => m_axi_awqos,
M_AXI_AWREGION => m_axi_awregion,
M_AXI_AWVALID => m_axi_awvalid,
M_AXI_AWREADY => m_axi_awready,
M_AXI_WID => m_axi_wid,
M_AXI_WDATA => m_axi_wdata,
M_AXI_WSTRB => m_axi_wstrb,
M_AXI_WLAST => m_axi_wlast,
M_AXI_WVALID => m_axi_wvalid,
M_AXI_WREADY => m_axi_wready,
M_AXI_BID => m_axi_bid,
M_AXI_BRESP => m_axi_bresp,
M_AXI_BVALID => m_axi_bvalid,
M_AXI_BREADY => m_axi_bready,
S_AXI_AWID => s_axi_awid,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWLEN => s_axi_awlen,
S_AXI_AWSIZE => s_axi_awsize,
S_AXI_AWBURST => s_axi_awburst,
S_AXI_AWLOCK => s_axi_awlock,
S_AXI_AWCACHE => s_axi_awcache,
S_AXI_AWPROT => s_axi_awprot,
S_AXI_AWQOS => s_axi_awqos,
S_AXI_AWREGION => s_axi_awregion,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WID => s_axi_wid,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WLAST => s_axi_wlast,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BID => s_axi_bid,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
M_AXI_ARID => m_axi_arid,
M_AXI_ARADDR => m_axi_araddr,
M_AXI_ARLEN => m_axi_arlen,
M_AXI_ARSIZE => m_axi_arsize,
M_AXI_ARBURST => m_axi_arburst,
M_AXI_ARLOCK => m_axi_arlock,
M_AXI_ARCACHE => m_axi_arcache,
M_AXI_ARPROT => m_axi_arprot,
M_AXI_ARQOS => m_axi_arqos,
M_AXI_ARREGION => m_axi_arregion,
M_AXI_ARVALID => m_axi_arvalid,
M_AXI_ARREADY => m_axi_arready,
M_AXI_RID => m_axi_rid,
M_AXI_RDATA => m_axi_rdata,
M_AXI_RRESP => m_axi_rresp,
M_AXI_RLAST => m_axi_rlast,
M_AXI_RVALID => m_axi_rvalid,
M_AXI_RREADY => m_axi_rready,
S_AXI_ARID => s_axi_arid,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARLEN => s_axi_arlen,
S_AXI_ARSIZE => s_axi_arsize,
S_AXI_ARBURST => s_axi_arburst,
S_AXI_ARLOCK => s_axi_arlock,
S_AXI_ARCACHE => s_axi_arcache,
S_AXI_ARPROT => s_axi_arprot,
S_AXI_ARQOS => s_axi_arqos,
S_AXI_ARREGION => s_axi_arregion,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RID => s_axi_rid,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RLAST => s_axi_rlast,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
AXI_AW_PROG_FULL => axi_aw_prog_full,
AXI_AW_PROG_EMPTY => axi_aw_prog_empty,
AXI_W_PROG_FULL => axi_w_prog_full,
AXI_W_PROG_EMPTY => axi_w_prog_empty,
AXI_B_PROG_FULL => axi_b_prog_full,
AXI_B_PROG_EMPTY => axi_b_prog_empty,
AXI_AR_PROG_FULL => axi_ar_prog_full,
AXI_AR_PROG_EMPTY => axi_ar_prog_empty,
AXI_R_PROG_FULL => axi_r_prog_full,
AXI_R_PROG_EMPTY => axi_r_prog_empty,
S_ACLK => s_aclk_i);
end xilinx;
|
mit
|
b10b38931be3da146e25f098e2f4094b
| 0.461342 | 3.798847 | false | false | false | false |
meninge/dauphin
|
nnlayer.vhd
| 1 | 13,589 |
-- This is one layer of a neural network
-- It contains several neurons that process input frames
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.all;
entity nnlayer is
generic (
-- Parameters for the neurons
WDATA : natural := 16;
WWEIGHT : natural := 16;
WACCU : natural := 48;
-- Parameters for frame and number of neurons
FSIZE : natural := 784;
NBNEU : natural := 200;
-- fifo count
CNTW : natural := 16
);
port (
clk : in std_logic;
-- reset
clear : in std_logic;
-- Ports for Write Enable
write_mode : in std_logic;
write_data : in std_logic_vector(WDATA-1 downto 0) ;
write_enable : in std_logic;
write_ready : out std_logic;
-- The user-specified frame size and number of neurons
user_fsize : in std_logic_vector(15 downto 0);
user_nbneu : in std_logic_vector(15 downto 0);
-- Data input, 2 bits
data_in : in std_logic_vector(WDATA-1 downto 0);
data_in_valid : in std_logic;
data_in_ready : out std_logic;
-- Scan chain to extract values
data_out : out std_logic_vector(WACCU-1 downto 0);
data_out_valid : out std_logic;
-- Indicate to the parent component that we are reaching the end of the current frame
end_of_frame : out std_logic;
-- The output data enters a FIFO. This indicates the available room.
out_fifo_room : in std_logic_vector(CNTW - 1 downto 0)
);
end nnlayer;
architecture synth of nnlayer is
-- Max fanout for signals distributed to all BRAM-based blocks
constant FANOUT : natural := 4;
-- The address to access neuron memory, read and write
constant WADDR : natural := 10;
-- Arrays of signals to instantiate the neurons
signal arr_write_data : std_logic_vector(NBNEU*WDATA-1 downto 0) := (others => '0');
-- Input data
signal arr_data_in : std_logic_vector(NBNEU*WDATA-1 downto 0) := (others => '0');
-- Controls signals, go to every neuron through distribuf
signal sg_ctrl_we_mode : std_logic_vector(0 downto 0):= (others => '0');
signal sg_ctrl_we_shift : std_logic_vector(0 downto 0):= (others => '0');
signal sg_ctrl_we_valid : std_logic_vector(0 downto 0):= (others => '0');
signal sg_ctrl_accu_clear : std_logic_vector(0 downto 0):= (others => '0');
signal sg_ctrl_accu_add : std_logic_vector(0 downto 0):= (others => '0');
signal sg_ctrl_shift_en : std_logic_vector(0 downto 0):= (others => '0');
signal sg_ctrl_shift_copy : std_logic_vector(0 downto 0):= (others => '0');
-- Address signal
signal sg_addr : std_logic_vector(WADDR - 1 downto 0):= (others => '0');
-- Signal to connect the sensor we valid from the good fifo to the fsm inside the nnlayer
signal sg_sensor_we_valid : std_logic := '0';
-- Corresponding arrays
signal arr_ctrl_we_mode : std_logic_vector(NBNEU - 1 downto 0) := (others => '0');
signal arr_ctrl_we_shift : std_logic_vector(NBNEU - 1 downto 0) := (others => '0');
signal arr_ctrl_we_valid : std_logic_vector(NBNEU - 1 downto 0) := (others => '0');
signal arr_ctrl_accu_clear : std_logic_vector(NBNEU - 1 downto 0) := (others => '0');
signal arr_ctrl_accu_add : std_logic_vector(NBNEU - 1 downto 0) := (others => '0');
signal arr_ctrl_shift_en : std_logic_vector(NBNEU - 1 downto 0) := (others => '0');
signal arr_ctrl_shift_copy : std_logic_vector(NBNEU - 1 downto 0) := (others => '0');
signal arr_addr : std_logic_vector(NBNEU * WADDR - 1 downto 0) := (others => '0');
-- Declaration of signal array to wire we_next and we_prev of every
-- neuron
-- We need 1 wire between two neurons and 2 more for first and last one.
-- Hence NBNEU + 1 values.
type match_array is array (0 to NBNEU) of std_logic;
signal we_match : match_array := (others => '0');
type match_array_waccu is array (0 to NBNEU) of std_logic_vector(WACCU - 1 downto 0);
-- Declaration of sh_data array with NBNEU wires
signal sh_data_match : match_array_waccu := (others => (others => '0'));
-- Declaration of sensor arrays
-- We use only the first one of this array
signal sensors_shift_match : match_array:= (others => '0');
signal sensors_copy_match : match_array:= (others => '0');
signal sensors_we_mode_match : match_array:= (others => '0');
signal sensors_we_shift_match : match_array:= (others => '0');
signal sensors_we_valid_match : match_array:= (others => '0');
-- FIFO management signals
signal sg_in_fifo_out_ack : std_logic := '0';
--signal sg_out_fifo_in_ack : std_logic;
signal sg_out_fifo_in_cnt : std_logic_vector(CNTW - 1 downto 0) := (others => '0');
-- Component declaration: one neuron
component neuron is
generic (
-- Parameters for the neurons
WDATA : natural := 32;
WWEIGHT : natural := 16;
WACCU : natural := 32;
-- Parameters for the frame size
FSIZE : natural := 784;
WADDR : natural := 10
);
port (
clk : in std_logic;
-- Control signals
ctrl_we_mode : in std_logic;
ctrl_we_shift : in std_logic;
ctrl_we_valid : in std_logic;
ctrl_accu_clear : in std_logic;
ctrl_accu_add : in std_logic;
ctrl_shift_en : in std_logic;
ctrl_shift_copy : in std_logic;
-- Address used for Read and Write
addr : in std_logic_vector(WADDR-1 downto 0);
-- Ports for Write Enable
we_prev : in std_logic;
we_next : out std_logic;
write_data : in std_logic_vector(WDATA-1 downto 0);
-- Data input, 2 bits
data_in : in std_logic_vector(WDATA-1 downto 0);
-- Scan chain to extract values
sh_data_in : in std_logic_vector(WACCU-1 downto 0);
sh_data_out : out std_logic_vector(WACCU-1 downto 0);
-- Sensors, for synchronization with the controller
sensor_shift : out std_logic;
sensor_copy : out std_logic;
sensor_we_mode : out std_logic;
sensor_we_shift : out std_logic;
sensor_we_valid : out std_logic
);
end component;
-- FSM for this layer
component fsm is
generic (
-- global parameters of layers
NB_NEURONS: natural := 200;
-- parameters of a neuron
WDATA : natural := 16;
WWEIGHT : natural := 16;
WACCU : natural := 48;
-- Parameters for the frame size
FSIZE : natural := 784;
WADDR : natural := 10
);
port (
reset : in std_logic;
clk : in std_logic;
-- Control signals
-- (go to all neurons)
ctrl_we_mode : out std_logic;
ctrl_we_shift : out std_logic;
ctrl_we_valid : out std_logic;
ctrl_accu_clear : out std_logic;
ctrl_accu_add : out std_logic;
ctrl_shift_en : out std_logic;
ctrl_shift_copy : out std_logic;
-- Address used for Read and Write
-- (go to all neurons)
addr : out std_logic_vector(WADDR-1 downto 0);
-- Ports for Write Enable
-- go to first neuron
n0_we_prev : out std_logic;
-- come from last neuron
nN_we_next : in std_logic;
-- Sensors, for synchronization with the controller
-- go to first neurons
sensor_shift : in std_logic;
sensor_copy : in std_logic;
sensor_we_mode : in std_logic;
sensor_we_shift : in std_logic;
sensor_we_valid : in std_logic;
-- inputs
fsm_mode : in std_logic;
-- input FIFO control
out_fifo_in_cnt : in std_logic_vector(CNTW-1 downto 0)
-- output FIFO control
--out_fifo_in_ack : out std_logic
);
end component;
-- Component declaration: distribution tree to limit fanout
component distribuf is
generic(
WDATA : natural := 32;
NBOUT : natural := 32;
FANOUT : natural := 32
);
port(
clk : in std_logic;
-- Input
idata : in std_logic_vector(WDATA-1 downto 0);
-- Outputs
odata : out std_logic_vector(WDATA*NBOUT-1 downto 0)
);
end component;
begin
-------------------------------------------------------------------
-- Instantiate the fanout distribution trees
-------------------------------------------------------------------
-- Fanout distribution tree: write_data
i_buf_write_data: distribuf
generic map (
WDATA => WDATA,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => write_data,
odata => arr_write_data
);
-- Fanout distribution tree: data_in
i_buf_data_in: distribuf
generic map (
WDATA => WDATA,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => data_in,
odata => arr_data_in
);
-- ctrl_we_mode distribution tree
i_ctrl_we_mode: distribuf
generic map (
WDATA => 1,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => sg_ctrl_we_mode,
odata => arr_ctrl_we_mode
);
-- ctrl_we_shift distribution tree
i_ctrl_we_shift: distribuf
generic map (
WDATA => 1,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => sg_ctrl_we_shift,
odata => arr_ctrl_we_shift
);
-- ctrl_we_valid distribution tree
i_ctrl_we_valid: distribuf
generic map (
WDATA => 1,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => sg_ctrl_we_valid,
odata => arr_ctrl_we_valid
);
-- ctrl_accu_clear distribution tree
i_ctrl_accu_clear: distribuf
generic map (
WDATA => 1,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => sg_ctrl_accu_clear,
odata => arr_ctrl_accu_clear
);
-- ctrl_accu_add distribution tree
i_ctrl_accu_add: distribuf
generic map (
WDATA => 1,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => sg_ctrl_accu_add,
odata => arr_ctrl_accu_add
);
-- ctrl_shift_en distribution tree
i_ctrl_shift_en: distribuf
generic map (
WDATA => 1,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => sg_ctrl_shift_en,
odata => arr_ctrl_shift_en
);
-- ctrl_shift_copy distribution tree
i_ctrl_shift_copy: distribuf
generic map (
WDATA => 1,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => sg_ctrl_shift_copy,
odata => arr_ctrl_shift_copy
);
-- we_mode distribution tree
i_addr: distribuf
generic map (
WDATA => WADDR,
NBOUT => NBNEU,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => sg_addr,
odata => arr_addr
);
-------------------------------------------------------------------
-- Instantiate the neurons
-------------------------------------------------------------------
gen_neu: for i in 0 to NBNEU-1 generate
i_neu_normal: neuron
generic map (
-- Parameters for the neurons
WDATA => WDATA,
WWEIGHT => WWEIGHT,
WACCU => WACCU,
-- Parameters for the frame size
FSIZE => FSIZE,
WADDR => WADDR
)
port map (
clk => clk,
-- Control signals
ctrl_we_mode => arr_ctrl_we_mode(i),
ctrl_we_shift => arr_ctrl_we_shift(i),
ctrl_we_valid => arr_ctrl_we_valid(i),
ctrl_accu_clear => arr_ctrl_accu_clear(i),
ctrl_accu_add => arr_ctrl_accu_add(i),
ctrl_shift_en => arr_ctrl_shift_en(i),
ctrl_shift_copy => arr_ctrl_shift_copy(i),
-- Address used for Read and Write
addr => arr_addr((i+1)*WADDR-1 downto i*WADDR),
-- Ports for Write Enable
we_prev => we_match(i),
we_next => we_match(i + 1),
write_data => arr_write_data((i+1)*WDATA-1 downto i*WDATA),
-- Data input, 2 bits
data_in => arr_data_in((i+1)*WDATA-1 downto i*WDATA),
-- Scan chain to extract values
-- Inversed from we_prev and we_next
sh_data_in => sh_data_match(i+1),
sh_data_out => sh_data_match(i),
-- Sensors, for synchronization with the controller
-- We use only the first (we suppose that synthesis will remove wires)
sensor_shift => sensors_shift_match(i),
sensor_copy => sensors_copy_match(i),
sensor_we_mode => sensors_we_mode_match(i),
sensor_we_shift => sensors_we_shift_match(i),
-- Not used
sensor_we_valid => open
);
end generate;
-------------------------------------------------------------------
-- Instantiate the FSM
-------------------------------------------------------------------
fsm_gen: fsm
generic map (
NB_NEURONS => NBNEU,
WDATA => WDATA,
WWEIGHT => WWEIGHT,
WACCU => WACCU,
FSIZE => FSIZE,
WADDR => WADDR
)
port map (
reset => clear,
clk => clk,
ctrl_we_mode => sg_ctrl_we_mode(0),
ctrl_we_shift => sg_ctrl_we_shift(0),
ctrl_we_valid => sg_ctrl_we_valid(0),
ctrl_accu_clear => sg_ctrl_accu_clear(0),
ctrl_accu_add => sg_ctrl_accu_add(0),
ctrl_shift_en => sg_ctrl_shift_en(0),
ctrl_shift_copy => sg_ctrl_shift_copy(0),
addr => sg_addr,
n0_we_prev => we_match(0),
nN_we_next => we_match(NBNEU),
sensor_shift => sensors_shift_match(0),
sensor_copy => sensors_copy_match(0),
sensor_we_mode => sensors_we_mode_match(0),
sensor_we_shift => sensors_we_shift_match(0),
sensor_we_valid => sg_sensor_we_valid,
fsm_mode => write_mode,
out_fifo_in_cnt => sg_out_fifo_in_cnt
--out_fifo_in_ack => sg_out_fifo_in_ack
);
sg_sensor_we_valid <= (data_in_valid and not(write_mode)) or (write_enable and write_mode);
data_in_ready <= sg_ctrl_accu_add(0) and not(write_mode);
write_ready <= sg_ctrl_we_valid(0) and write_mode;
sg_out_fifo_in_cnt <= out_fifo_room;
data_out <= sh_data_match(0);
sh_data_match(NBNEU) <= std_logic_vector(to_unsigned(0, sh_data_match(NBNEU)'length));
--data_out_valid <= sg_out_fifo_in_ack;
data_out_valid <= sensors_shift_match(0);
end_of_frame <= '0';
end architecture;
|
mit
|
c2c8537cda58d197c3a841fe9445ec45
| 0.600559 | 3.049596 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dverif.vhd
| 1 | 5,736 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
mit
|
28f9768d021306cd2f54636e693bc775
| 0.585251 | 4.02244 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb.vhd
| 1 | 6,038 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb IS
END ENTITY;
ARCHITECTURE system_axi_vdma_0_wrapper_fifo_generator_v9_1_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2000 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth
system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth_inst:system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 45
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
mit
|
80537d434c778d7f377a199dc3df8e8f
| 0.628685 | 4.038796 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1/example_design/system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes.vhd
| 1 | 5,216 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(8-1 DOWNTO 0);
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(34-1 DOWNTO 0);
DOUT : OUT std_logic_vector(34-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes;
architecture xilinx of system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes is
signal clk_i : std_logic;
component system_axi_vdma_0_wrapper_fifo_generator_v9_1 is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(8-1 DOWNTO 0);
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(34-1 DOWNTO 0);
DOUT : OUT std_logic_vector(34-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_1
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
mit
|
c690f18714542a6d47d373e9503aef8e
| 0.536043 | 4.741818 | false | false | false | false |
groggemans/block-mario
|
Broncode/Block_Mario_core.vhd
| 1 | 37,400 |
--
-- @file Block_Mario_core.vhd
-- @date December, 2013
-- @author G. Roggemans <[email protected]>
-- @copyright Copyright (c) GROG [https://grog.be] 2013, All Rights Reserved
--
-- This application is free software: you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- This application is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
-- for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this application. If not, see <http://www.gnu.org/licenses/>.
--
--
-- entity Block_Mario_core
--
-- Block_Mario_core verzorgt de werking van het spel.
-- Tijdens het ontwerpen van het project heb ik er voor gekozen om het project zodanig op te
-- bouwen dat met de zelfde code meerdere games gemaakt konden worden. Om dit mogelijk te maken
-- heb ik gekozen om alle game specifieke code in 1 entity te plaatsen, de core. Deze keuze
-- heeft wel met zich mee gebracht dat de core een relatief groot geheel is.
--
-- Oorspongkelijk bevatte de core het werk geugen en werden de nodige bewerkingen op het
-- voledige scherm toegepast. Dit bracht echter met zich mee dat er een enorme hoeveelheid slices
-- nodig waren om alle nodige bewerkingen te doen op het 32x24 spel raster. Door gebruik te maken
-- van een ram geheugen om het huidige speelveld in bij te houden en de bewerkingen slechts toe
-- te passen op een kleiner veld werd het aantal slices voor de core drastisch terug gebracht.
-- (zonder deze aanpassing was dit project niet mogelijk geweest)
--
-- In groffe lijnen kan de basis werking van de core als volgt worden omschreven:
--
-- 1) Input van de speler interpreteren en actie bepalen.
-- 2) Uit het werkgeheugen de velden ophalen die van belang zijn voor de actie.
-- 3) Kijk of de actie kan worden uitgevoerd en zo ja, voer uit.
-- 4) Plaats de mogelijk aangepaste velden terug in het werkgeheugen.
--
-- Het interpreteren van de input en de bewerkingen die al dan niet worden toegepast zijn
-- verschillend per spel en worden daarom in de core uitgevoerd. Comunicatie met het geheugen is
-- echter voor elk spel gelijk en word daarom afgehandelt door de MMU (Memory Managment Unit).
-- De core block comuniceert met de MMU door middel van de 'com' vector. De MMU kan doormiddel van
-- de 'com_ok' bit aangeven of de gevraagde actie uitgevoerd is.
--
-- De velden die van belang zijn voor een zekere bewerking worden hier AOI(Area Of Interest)
-- genoemd en deze zone ziet er als volgt uit.
--
-- Area of interest: (Elke 'cell' stelt een bitmap voor en kan worden omschreven door 4bit in het geheugen.)
-- ____ ____ ____
-- | 0 | 1 | 2 |
-- |____|____|____|
-- | 3 | 4 | 5 |
-- |____|____|____|
-- | 6 | 7 | 8 |
-- |____|____|____|
-- | 9 | 10 | 11 |
-- |____|____|____|
--
-- Het object waarop een bewerking word uitgevoerd, hier OOI (Object Of Interest) genoemd, bevind
-- zich op plaats 7 in de AOI. Geeft men de x en y coordinaat van het OOI door aan de MMU en vraagt
-- men om de AOI dan zal de MMU dergelijk veld terug geven in 2d vector van vectoren met op plaats
-- 7 het OOI. Op de AOI kunnen dan de nodige bewerkingen uitgevoerd worden voor een zekere actie. Na
-- deze actie word de bewerkte AOI terug gegeven aan de MMU en deze handelt dan het schrijven van de
-- juiste geheugen plaatsen af.
--
-- In enkele gevallen kan dit normaale verloop worden onderbroken:
--
-- - Een level word (opnieuw) geladen
-- De MMU zal het komando krijgen om het RAM geheugen te vullen met een bepaald level uit het level ROM
--
-- - Het ventje of een verplaatste blok valt
-- Er word een bit op 1 gezet die zorgt dat:
-- De MMU de AOI geeft met als OOI het vallende ventje of blokje.
-- Deze AOI verwerkt wordt door het 'zwaartekracht algoritme'.
-- De bit word pas gereset als het ventje of blokje op vaste ondergrond beland is.
--
-- - Een cheat code word ingevoerd
-- Nodige indactie bits worden aangepast
--
-- - De eind animatie moet worden weergegeven
-- Er word een bit op 1 gezet die zorgt dat:
-- De MMU de AOI geeft met als OOI de volgende plaats voor de eind animatie.
-- Deze AOI verwerkt wordt door het 'eind animatie algoritme'.
-- De bit word pas gereset als de eind animatie afgelopen is.
--
-- Omdat het spel dat ik wou realiseren in deze core oorspronkelijk 11 levels had en er slechts 5 geheugen
-- plaatsen zijn voor levels werdt een truc toegepast. Er werden meerdere levels in 1 scherm geplaatst.
-- hierdoor konden in de 5 geheugen plaatsen 10 levels worden ondergebracht. In de core zijn er daarom
-- array's met gegevens voorzien waaruit de nodige waardes voor elk level opgehaald kunnen worden.
--
-- Naast level specifieke informatie is er ook een constante array voorzien waarin aangegeven is wat voor
-- type blok elke bitmap voorsteld. Deze codes bepalen hierdoor het gedrag van elk blokje en maken het
-- mogelijk eenvoudig meerdere blokjes het zelfde gedrag toe te kennen en het gedrag van een blokje aan te
-- passen.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.sig_pkg.all;
entity Block_Mario_core is
Port ( clk : in STD_LOGIC; -- Werk clock
com : inout STD_LOGIC_VECTOR (2 downto 0) := "000"; -- Com vector
com_ok : in STD_LOGIC_VECTOR (0 downto 0) := "0"; -- Com ok bit
data_in : in core_register := ("0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000"); -- AOI vector in
data_out : out core_register := ("0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000"); -- AOI vector out
rom_lvl : out integer range 0 to 4 := 0; -- Te laden level
lvl : inout integer range 0 to 10 := 0; -- Huidige level
the_end : inout STD_LOGIC := '0'; -- Einde spel
X : out integer range 0 to 31; -- AOI X
Y : out integer range 0 to 23; -- AOI Y
ps2_data : in STD_LOGIC_VECTOR (7 downto 0):= "00000000"); -- Keybord input
end Block_Mario_core;
architecture Behavioral of Block_Mario_core is
signal X_dude : integer range 0 to 31 := 15; -- X coordinaat ventje
signal Y_dude : integer range 0 to 23 := 22; -- Y coordinaat ventje
signal X_blck : integer range 0 to 31 := 0; -- X coordinaat actief blokje (bij val)
signal Y_blck : integer range 0 to 23 := 0; -- Y coordinaat actief blokje (bij val)
signal NX_dude : integer range 0 to 2 :=1; -- Nieuwe X relatief tov huidige in de AOI
signal NY_dude : integer range 0 to 3 :=2; -- Nieuwe Y relatief tov huidige in de AOI
signal try_blck_lift : STD_LOGIC := '0'; -- Indicatie bit blokje opheffen
signal dude_dir : STD_LOGIC := '0'; -- Indicatie bit richting ventje
signal blck_lift : STD_LOGIC := '0'; -- Indicatie bit blokje opgehoffen
signal blck_grav : STD_LOGIC := '0'; -- Indicatie bit dat blokje valt
signal dude_grav : STD_logic := '0'; -- Indicatie bit dat ventje valt
signal D_grav : integer range 0 to 99999 := 0; -- Gravity delay counter
signal lvl_up : STD_logic := '0'; -- Indicatie bit voor level-up
signal lvl_req : integer range 0 to 10:= 0; -- Indicatie bit voor level request
signal lvl_lock : integer range 0 to 10 := 0; -- Grens tot geblokeerde levels
signal lock : STD_LOGIC := '0'; -- Indicatie bit voor bewegings blokering
signal X_end : integer range 0 to 31 := 0; -- X coordinaat eind animatie
signal Y_end : integer range 0 to 23 := 0; -- Y coordinaat eind animatie
signal X_end_max : integer range 0 to 31 := 0; -- Hulp var voor eind animatie
signal Y_end_max : integer range 0 to 23 := 0; -- Hulp var voor eind animatie
signal D_end : integer range 0 to 99999 := 0; -- Eind animatie delay counter
signal E_end : integer range 0 to 767 := 0; -- Eind animatie counter
signal PX_end : STD_LOGIC := '0'; -- Hulp var voor eind animatie
signal PY_end : STD_LOGIC := '0'; -- Hulp var voor eind animatie
signal end_lock : STD_LOGIC := '0'; -- Indicatie bit voor eind animatie
signal start_lvl : STD_LOGIC := '0'; -- Indicatie bit start level (ventje in veld plaatsen)
signal b_cheat : STD_LOGIC := '0'; --
signal b_cheat_lock : STD_LOGIC := '1'; -- Indicatie bit b_cheat actief
signal d_cheat : STD_LOGIC := '0'; --
signal d_cheat_lock : STD_LOGIC := '1'; -- Indicatie bit d_cheat actief
signal f_cheat : STD_LOGIC := '0'; --
signal f_cheat_lock : STD_LOGIC := '1'; -- Indicatie bit f_cheat actief
signal f_dir : integer range 0 to 3 := 0; -- Indicatie bit f_cheat richting veranderen
-- In de cheat_buffer worden de ingegeven cheat codes opgebouwt voor controle
type key_buffer is array (0 to 3) of STD_LOGIC_VECTOR (7 downto 0);
signal cheat_buffer : key_buffer;
signal cheat_buffer_count : integer range 0 to 3;
type Xarray is array (0 to 10) of integer range 0 to 31;
type Yarray is array (0 to 10) of integer range 0 to 23;
constant Xstart : Xarray := (15,27, 7,16,17,16,24,23,26,17,14); -- X start coordinaten voor de levels
constant Ystart :Yarray := (22, 3,15, 6, 4, 6,19,22,15,16, 6); -- Y start coordinaten voor de levels
type lvl_code_array is array (0 to 10) of integer range 0 to 4;
constant lvl_code : lvl_code_array := (0,3,2,0,2,1,0,1,2,3,4); -- Te laden scherm uit de level rom voor elk level in het spel
type func_code_array is array (0 to 15) of integer range 0 to 7;
constant func_code : func_code_array := (1,1,3,2,5,5,5,5,5,4,6,5,5,5,5,0); -- code die aangeeft wat voor type blok elke bitmap is
constant black : STD_LOGIC_VECTOR := "1011"; -- code die aangeeft welke bitmap zwart is (eind animatie)
constant background : STD_LOGIC_VECTOR := "1010"; -- code die aangeeft welke bitmap de achtergrond is
constant dude_L : STD_LOGIC_VECTOR := "0000"; -- code die aangeeft welke bitmap het linkse ventje is
constant dude_R : STD_LOGIC_VECTOR := "0001"; -- code die aangeeft welke bitmap het rechtse ventje is
begin
process (clk) begin
if rising_edge (clk) then
-- kijken in welke status de core zich bevind
case com is
when "000" => -- Input processing
-- begin level of b/d cheat word uitgevoerd
if start_lvl = '1' or b_cheat = '1' or d_cheat = '1' then
X <= X_dude;
Y <= Y_dude;
com <="010"; -- MMU om AOI vragen
-- einde van het spel is bereikt
elsif the_end = '1' then
-- eind animatie delay toepassen
if D_end = 99999 then
D_end <= 0;
com <= "110"; -- MMU om AOI vragen
X <= X_end;
Y <= Y_end;
-- Algoritme voor eind animatie (inwaartse spiraal)
-- boven zijde afgaan
if Y_end = Y_end_max and X_end < 31 - X_end_max then
X_end <= X_end + 1;
if PX_end = '1' and Y_end > 0 then
X_end_max <= X_end_max + 1;
PX_end <= '0';
end if;
-- rechter zijde afgaan
elsif X_end = 31 - X_end_max and Y_end < 23 - Y_end_max then
Y_end <= Y_end + 1;
PX_end <= '1';
-- Onder zijde afgaan
elsif Y_end = 23 - Y_end_max and X_end > X_end_max then
X_end <= X_end - 1;
PY_end <= '1';
-- linker zijde afgaan
elsif X_end = X_end_max and Y_end > Y_end_max then
Y_end <= Y_end - 1;
if PY_end = '1' then
Y_end_max <= Y_end_max + 1;
PY_end <= '0';
end if;
end if;
-- bij einde eind animatie alle gegevens resetten
if E_end = 767 then
E_end <= 0;
the_end <= '0';
X_end <= 0;
Y_end <= 0;
X_end_max <= 0;
Y_end_max <= 0;
end_lock <= '1';
-- anders verder tellen tot einde animatie
else
E_end <= E_end + 1;
end if;
-- Delay voor eind animatie tellen
else
D_end <= D_end + 1;
com <= "000"; -- Geen speciale actie ondernemen
end if;
-- level up uitvoeren
elsif lvl_up = '1' then
lvl_up <= '0';
lvl_req <= lvl + 1; -- gevraagde level is huidig level + 1
lvl_lock <= lvl_lock + 1; -- volgend level unlocken
com <= "101"; -- core vragen level load af te handelen
-- zwaartekracht toepassen
elsif dude_grav = '1' or blck_grav = '1' then
com <= "010"; -- MMU om AOI vragen
-- bepalen wat het OOI is (blokje of ventje)
if dude_grav = '1' then
X <= X_dude;
Y <= Y_dude;
else
X <= X_blck;
Y <= Y_blck;
end if;
-- er vond geen speciale actie plaats dus word keybord input geinterpreteerd
else
-- PS2 input controleren
case ps2_data is
when x"76" => -- ESC
-- Als het huidige level niet het start scherm is het huidige level opnieuw laden
if lvl > 0 then
lvl_req <= lvl;
com <= "101";
else
com <= "000";
end if;
when x"05" => -- F1
lvl_req <= 1; -- gevraagde level is 1
com <= "101"; -- core vragen level load af te handelen
-- level 2 laden
when x"06" => -- F2
lvl_req <= 2; -- gevraagde level is 2
com <= "101"; -- core vragen level load af te handelen
when x"04" => -- F3
lvl_req <= 3; -- gevraagde level is 3
com <= "101"; -- core vragen level load af te handelen
when x"0C" => -- F4
lvl_req <= 4; -- gevraagde level is 4
com <= "101"; -- core vragen level load af te handelen
when x"03" => -- F5
lvl_req <= 5; -- gevraagde level is 5
com <= "101"; -- core vragen level load af te handelen
when x"0B" => -- F6
lvl_req <= 6; -- gevraagde level is 6
com <= "101"; -- core vragen level load af te handelen
when x"83" => -- F7
lvl_req <= 7; -- gevraagde level is 7
com <= "101"; -- core vragen level load af te handelen
when x"0A" => -- F8
lvl_req <= 8; -- gevraagde level is 8
com <= "101"; -- core vragen level load af te handelen
when x"01" => -- F9
lvl_req <= 9; -- gevraagde level is 9
com <= "101"; -- core vragen level load af te handelen
when x"09" => -- F10
lvl_req <= 10; -- gevraagde level is 10
com <= "101"; -- core vragen level load af te handelen
when x"15" => -- Q
-- als cheat actief is deze uitvoeren
if b_cheat_lock = '0' then
b_cheat <= '1';
end if;
when x"24" => -- E
-- als cheat actief is deze uitvoeren
if d_cheat_lock = '0' then
d_cheat <= '1';
end if;
when x"2B" => -- F
-- als cheat actief is deze uitvoeren (in dit geval het effect op/af zetten)
if f_cheat_lock = '0' then
f_cheat <= not f_cheat;
end if;
when x"5A" => -- Enter
-- cheat buffer controleren
if cheat_buffer = (x"24",x"21",x"33",x"44") then
-- alle levels unlocken
lvl_lock <= 10;
elsif cheat_buffer = (x"2D",x"1B",x"24",x"2c") then
-- alle cheats en lvl_lock resetten
lvl_lock <= 1;
lvl_req <= 1;
lvl <= 1;
b_cheat_lock <= '1';
d_cheat_lock <= '1';
f_cheat_lock <= '1';
com <= "101";
elsif cheat_buffer = (x"4B",x"44",x"21",x"42") then
-- bewegings blokering togelen
lock <= not lock;
elsif cheat_buffer = (x"4B",x"43",x"24",x"1B") then
-- togelen van b cheat
b_cheat_lock <= not b_cheat_lock;
elsif cheat_buffer = (x"1B",x"24",x"43",x"4B") then
-- togelen d cheat
d_cheat_lock <= not d_cheat_lock;
elsif cheat_buffer = (x"2A",x"33",x"23",x"4B") then
--togelen f cheat
f_cheat_lock <= not f_cheat_lock;
elsif cheat_buffer = (x"34",x"2D",x"44",x"34") then
-- master cheat code die alle cheats activeert en levels unlocked
lock <= '0';
lvl_lock <= 10;
b_cheat_lock <= '0';
d_cheat_lock <= '0';
f_cheat_lock <= '0';
end if;
-- buffer leegmaken na controle
cheat_buffer <= (x"00",x"00",x"00",x"00");
cheat_buffer_count <= 0;
-- Movement
when x"1C" => -- A (qwerty) -> Links bewegen
-- kijken of geen enkele indacatie bit het normale verloop tegenhoud
if lock = '0' and end_lock = '0' and f_cheat = '0' then
dude_dir <= '0';
NX_dude <= 0;
NY_dude <= 2;
X <= X_dude;
Y <= Y_dude;
com <= "010"; -- AOI opvragen en daarna actie uitvoeren
-- voor f_cheat speciaal verloop starten
elsif f_cheat = '1' then
f_dir <= 0;
X <= X_dude;
Y <= Y_dude;
com <= "010"; -- AOI opvragen en daarna actie uitvoeren
end if;
when x"23" => -- D (qwerty) -> Rechts bewegen
-- kijken of geen enkele indacatie bit het normale verloop tegenhoud
if lock = '0' and end_lock = '0' and f_cheat = '0' then
dude_dir <= '1';
NX_dude <= 2;
NY_dude <= 2;
X <= X_dude;
Y <= Y_dude;
com <= "010"; -- AOI opvragen en daarna actie uitvoeren
-- voor f_cheat speciaal verloop starten
elsif f_cheat = '1' then
f_dir <= 1;
X <= X_dude;
Y <= Y_dude;
com <= "010"; -- AOI opvragen en daarna actie uitvoeren
end if;
when x"1D" => -- W (qwerty) -> Omhoog bewegen
-- kijken of geen enkele indacatie bit het normale verloop tegenhoud
if lock = '0' and end_lock ='0' and f_cheat = '0' then
if dude_dir = '0' then
NX_dude <= 0;
else
NX_dude <= 2;
end if;
NY_dude <= 1;
X <= X_dude;
Y <= Y_dude;
com <= "010"; -- AOI opvragen en daarna actie uitvoeren
-- voor f_cheat speciaal verloop starten
elsif f_cheat = '1' then
f_dir <= 2;
X <= X_dude;
Y <= Y_dude;
com <= "010"; -- AOI opvragen en daarna actie uitvoeren
end if;
when x"1B" => -- S (qwerty) -> Interatie met blokje uitvoeren
-- kijken of geen enkele indacatie bit het normale verloop tegenhoud
if lock = '0' and end_lock = '0' and f_cheat = '0' then
try_blck_lift <= '1';
NX_dude <= 1;
NY_dude <= 2;
X <= X_dude;
Y <= Y_dude;
com <= "010"; -- AOI opvragen en daarna actie uitvoeren
-- voor f_cheat speciaal verloop starten
elsif f_cheat = '1' then
f_dir <= 3;
X <= X_dude;
Y <= Y_dude;
com <= "010"; -- AOI opvragen en daarna actie uitvoeren
end if;
when others => null;
end case;
end if;
-- als er ps2 input was en het geen enter was word de key code in de cheat_buffer toegevoegd
if not (ps2_data = x"00") and not (ps2_data = x"5A") then
cheat_buffer(cheat_buffer_count) <= ps2_data;
cheat_buffer_count <= cheat_buffer_count + 1;
end if;
when "010" => -- MMU om AOI vragen
-- als MMU aangeeft dat AOI klaar is overgaan naar verwerkings gedeelte
if com_ok = "1" then
com <= "011";
end if;
when "011" => -- Actie uitvoeren
data_out <= data_in; -- nieuwe AOI begint als huidige AOI
-- Bij start level ventje op start positie plaatsen
if start_lvl = '1' then
start_lvl <= '0';
data_out(7) <= dude_L;
com <= "100"; -- MMU vragen om AOI terug te plaatsen in het geheugen
-- b_cheat uitvoeren
elsif b_cheat = '1' then
b_cheat <= '0';
if func_code(conv_integer(unsigned(data_in(4)))) = 6 then
data_out(4) <= "1001";
blck_lift <= '1';
elsif func_code(conv_integer(unsigned(data_in(4)))) = 4 then
data_out(4) <= background;
blck_lift <= '0';
end if;
com <= "100"; -- MMU vragen om AOI terug te plaatsen in het geheugen
-- d_cheat uitvoeren
elsif d_cheat = '1' then
d_cheat <= '0';
if data_in(7) = dude_L then
data_out(7) <= dude_R;
else
data_out(7) <= dude_L;
end if;
dude_dir <= not dude_dir;
com <= "100"; -- MMU vragen om AOI terug te plaatsen in het geheugen
-- f_cheat uitvoeren
elsif f_cheat = '1' then
-- f_cheat werkt enkel als ventje geen blokje vast heeft
if blck_lift = '0' then
case f_dir is
when 0 =>
if func_code(conv_integer(unsigned(data_in(6)))) = 6 then
data_out(6) <= dude_L;
dude_dir <= '0';
data_out(7) <= background;
X_dude <= X_dude - 1;
end if;
when 1 =>
if func_code(conv_integer(unsigned(data_in(8)))) = 6 then
data_out(8) <= dude_R;
dude_dir <= '1';
data_out(7) <= background;
X_dude <= X_dude + 1;
end if;
when 2 =>
if func_code(conv_integer(unsigned(data_in(4)))) = 6 then
data_out(4) <= data_in(7);
data_out(7) <= background;
Y_dude <= Y_dude - 1;
end if;
when 3 =>
if func_code(conv_integer(unsigned(data_in(10)))) = 6 then
data_out(10) <= data_in(7);
data_out(7) <= background;
Y_dude <= Y_dude + 1;
end if;
when others => null;
end case;
end if;
com <= "100"; -- MMU vragen om AOI terug te plaatsen in het geheugen
-- Kijken of spel uit is
elsif func_code(conv_integer(unsigned(data_in(10)))) = 2 then -- dude valt op princess
the_end <= '1';
com <= "000"; -- naar rust toestand (the_end bit zorgt voor eind animatie)
-- kijken of level uit is
elsif func_code(conv_integer(unsigned(data_in(10)))) = 3 then -- dude valt op deur
lvl_up <= '1';
com <= "000"; -- naar rust toestand (lvl_up bit zorgt dat volgend level geladen wordt)
-- kijken of blokje of ventje aan het vallen is
elsif dude_grav = '1' or blck_grav = '1' then -- gravity toepassen
if D_grav = 99999 then
D_grav <= 0;
if not (func_code(conv_integer(unsigned(data_in(10)))) = 6) then
if dude_grav = '1' then
dude_grav <= '0';
else
blck_grav <= '0';
end if;
else
data_out(10) <= data_in(7);
data_out(7) <= background;
if dude_grav = '1' then
Y_dude <= Y_dude + 1;
if blck_lift = '1' then
data_out(4) <= background;
data_out(7) <= data_in(4);
end if;
else
Y_blck <= Y_blck + 1;
end if;
end if;
com <= "100"; -- MMU vragen om AOI terug te plaatsen in het geheugen
else
D_grav <= D_grav + 1;
com <= "000"; -- rust toestand door gravity delay
end if;
-- normale spel verloop (geen einde, nieuw level of gravity)
else
-- dude wil doos bewegen
if try_blck_lift = '1' then
try_blck_lift <= '0';
-- dude wil doos opheffen
if blck_lift = '0' then
-- L richting
if dude_dir = '0' then
-- kijken of bewegings voorwaarden in orde zijn
if func_code(conv_integer(unsigned(data_in(6)))) = 4 and func_code(conv_integer(unsigned(data_in(3)))) = 6 and func_code(conv_integer(unsigned(data_in(4)))) = 6 then
data_out(6) <= background;
data_out(4) <= data_in(6);
blck_lift <= '1';
end if;
-- R richting
else
-- kijken of bewegings voorwaarden in orde zijn
if func_code(conv_integer(unsigned(data_in(8)))) = 4 and func_code(conv_integer(unsigned(data_in(5)))) = 6 and func_code(conv_integer(unsigned(data_in(4)))) = 6 then
data_out(8) <= background;
data_out(4) <= data_in(8);
blck_lift <= '1';
end if;
end if;
-- dude wil doos laten vallen
else
-- L richting
if dude_dir = '0' then
-- blok kan neergezet worden?
if func_code(conv_integer(unsigned(data_in(3)))) = 6 then
-- op de grond (anders op andere blok)?
if func_code(conv_integer(unsigned(data_in(6)))) = 6 then
data_out(6) <= data_in(4);
data_out(4) <= background;
-- zwaartekracht toepassen?
if func_code(conv_integer(unsigned(data_in(9)))) = 6 then
blck_grav <= '1';
X_blck <= X_dude - 1;
Y_blck <= Y_dude;
end if;
-- op andere blok
else
data_out(3) <= data_in(4);
data_out(4) <= background;
end if;
blck_lift <= '0'; -- dude heeft nietlanger blok vast
end if;
-- R richting
else
-- blok kan neergezet worden
if func_code(conv_integer(unsigned(data_in(5)))) = 6 then
-- op de grond (anders op andere blok)?
if func_code(conv_integer(unsigned(data_in(8)))) = 6 then
data_out(8) <= data_in(4);
data_out(4) <= background;
-- zwaartekracht toepassen?
if func_code(conv_integer(unsigned(data_in(11)))) = 6 then
blck_grav <= '1';
X_blck <= X_dude + 1;
Y_blck <= Y_dude;
end if;
-- op andere blok
else
data_out(5) <= data_in(4);
data_out(4) <= background;
end if;
blck_lift <= '0'; -- dude heeft niet langer blok vast
end if;
end if;
end if; -- opheffen/vallen
end if; -- wil doos bewegen
-- dude wil klimmen
if not (NY_dude = 2) then
-- dude klimt naar princess?
if func_code(conv_integer(unsigned(data_in(3 + NX_dude)))) = 2 or func_code(conv_integer(unsigned(data_in(6 + NX_dude)))) = 2 then
the_end <= '1';
com <= "000"; -- naar rust toestand (the_end bit zorgt voor eind animatie)
-- klimmen naar/op deur?
elsif func_code(conv_integer(unsigned(data_in(3 + NX_dude)))) = 3 or func_code(conv_integer(unsigned(data_in(6 + NX_dude)))) = 3 then
lvl_up <= '1';
com <= "000"; -- naar rust toestand (lvl_up bit zorgt dat volgend level geladen wordt)
-- niet naar deur
else
-- klimmen met blok
if blck_lift = '1' then
-- kijken of bewegings voorwaarden in orde zijn
if func_code(conv_integer(unsigned(data_in(3 + NX_dude)))) = 6 and (not (func_code(conv_integer(unsigned(data_in(6 + NX_dude)))) = 6)) and func_code(conv_integer(unsigned(data_in(NX_dude)))) = 6 then
X_dude <= (X_dude-1) + NX_dude;
Y_dude <= (Y_dude-2) + NY_dude;
data_out(NX_dude) <= data_in(4);
data_out(3 + NX_dude) <= data_in(7);
data_out(4) <= background;
data_out(7) <= background;
end if;
-- klimmen zonder blok
else
-- kijken of bewegings voorwaarden in orde zijn
if func_code(conv_integer(unsigned(data_in(3 + NX_dude)))) = 6 and (not (func_code(conv_integer(unsigned(data_in(6 + NX_dude)))) = 6)) and func_code(conv_integer(unsigned(data_in(4)))) = 6 then
X_dude <= (X_dude-1) + NX_dude;
Y_dude <= (Y_dude-2) + NY_dude;
data_out(3 + NX_dude) <= data_in(7);
data_out(7) <= background;
end if;
end if; -- blok
com <= "100"; -- MMU vragen om AOI terug te plaatsen in het geheugen
end if; -- deur
-- dude wil niet klimmen
else
-- dude wil L of R lopen
if not (NX_dude = 1) then
-- dude loopt naar princess?
if func_code(conv_integer(unsigned(data_in(6 + NX_dude)))) = 2 then
the_end <= '1';
com <= "000"; -- naar rust toestand (the_end bit zorgt voor eind animatie)
-- lopen naar deur
elsif func_code(conv_integer(unsigned(data_in(6 + NX_dude)))) = 3 then
lvl_up <= '1';
com <= "000"; -- naar rust toestand (lvl_up bit zorgt dat volgend level geladen wordt)
-- niet naar deur
else
-- geen opstakel?
if func_code(conv_integer(unsigned(data_in(6 + NX_dude)))) = 6 then
-- verplaatsen
X_dude <= (X_dude - 1) + NX_dude;
data_out(7) <= background;
-- in juiste richting kijken
if dude_dir = '0' then
data_out(NX_dude + 6) <= dude_L;
else
data_out(NX_dude + 6) <= dude_R;
end if;
-- zwaartekracht toepassen?
if func_code(conv_integer(unsigned(data_in(9 + NX_dude)))) = 6 then
dude_grav <= '1';
end if;
-- blok bewegen?
if blck_lift = '1' then
-- blok kan mee bewegen?
if func_code(conv_integer(unsigned(data_in(3 + NX_dude)))) = 6 then
data_out(NX_dude + 3) <= data_in(4);
data_out(4) <= background;
-- blok valt
else
blck_lift <= '0';
blck_grav <= '1';
X_blck <= X_dude;
Y_blck <= Y_dude - 1;
end if; -- blok valt
end if; -- blok
-- opstakel (enkel draaien niet verplaatsen)
else
if dude_dir = '0' then
data_out(7) <= dude_L;
else
data_out(7) <= dude_R;
end if;
end if; -- opstakel
com <= "100"; -- MMU vragen om AOI terug te plaatsen in het geheugen
end if; -- deur
-- niet omhoog/omlaag/l/r/ => doos verplaatst
else
com <= "100"; -- MMU vragen om AOI terug te plaatsen in het geheugen
end if; -- L of R lopen
end if; -- klimmen
end if; -- begin state
when "101" => -- Er werd om een level load gevraagt
-- kijken of gevraagde level unlocked is en zo ja gevraagde level laden
if lvl_lock >= lvl_req then
lvl <= lvl_req;
X_dude <= Xstart(lvl_req);
Y_dude <= Ystart(lvl_req);
rom_lvl <= lvl_code(lvl_req);
dude_dir <= '0';
dude_grav <= '0';
blck_lift <= '0';
blck_grav <= '0';
the_end <= '0';
end_lock <= '0';
start_lvl <= '1';
com <= "001"; -- MMU om level load vragen
else
com <= "000";
end if;
when "110" => -- MMU om AOI vragen
-- als MMU aangeeft dat AOI klaar is overgaan naar verwerkings gedeelte
if com_ok = "1" then
com <= "111"; -- verwerking eind animatie starten
end if;
when "111" => -- AOI voor eind animatie verwerken
data_out <= data_in;
data_out(7) <= black; -- plaats van OOI zwart maken
com <= "100"; -- MMU vragen om AOI terug in het geheugen te plaatsen
when others => -- In andere gevallen als de MMU klaar is overgaan naar de rust stand ("000")
if com_ok = "1" then
com <= "000";
end if;
end case;
end if;
end process;
end Behavioral;
|
lgpl-3.0
|
e3473548057580144babffcf6d448c97
| 0.475588 | 3.993167 | false | false | false | false |
AdanDuM/INE5406-SD
|
switch2x2.vhd
| 1 | 756 |
library IEEE;
use IEEE.std_logic_1164.all;
-- Alunos: Adan Pereira Gomes e Wesley Mayk Gama Luz
entity switch2x2 is
generic(width: integer:= 8);
port(
in_0 : in std_logic_vector(width-1 downto 0);
in_1 : in std_logic_vector(width-1 downto 0);
ctrl : in std_logic_vector(1 downto 0);
out_0: out std_logic_vector(width-1 downto 0);
out_1: out std_logic_vector(width-1 downto 0)
);
end entity;
architecture circuito of switch2x2 is
begin
outp0 <= inpt0 when ctrl = "00" else
inpt1 when ctrl = "01" else
inpt0 when ctrl = "10" else
inpt1 when ctrl = "11";
outp1 <= inpt1 when ctrl = "00" else
inpt0 when ctrl = "01" else
inpt0 when ctrl = "10" else
inpt1 when ctrl = "11";
end architecture;
|
gpl-2.0
|
561c2d45cc0df855358899febd14b6ce
| 0.648148 | 3.024 | false | false | false | false |
h3ct0rjs/ComputerArchitecture
|
Processor/Entrega3/psr.vhd
| 1 | 754 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSR is
Port ( NZVC : in STD_LOGIC_VECTOR (3 downto 0);
Rst : in STD_LOGIC;
clk : in STD_LOGIC;
Ncwp : in STD_LOGIC_VECTOR (4 downto 0);
Carry : out STD_LOGIC;
Cwp : out STD_LOGIC_VECTOR (4 downto 0);
icc : out STD_LOGIC_VECTOR (3 downto 0)
);
end PSR;
architecture Behavioral of PSR is
begin
process(clk, Rst, NZVC, Ncwp)
begin
if (rising_edge(clk)) then
if (Rst = '1') then
Carry <= '0';
Cwp <= (others => '0');
icc <= (others => '0');
else
Carry <=NZVC(0);
icc <= NZVC;
Cwp <= Ncwp;
end if;
end if;
end process;
end Behavioral;
|
mit
|
3aa57f5cc98e8ad781202f7d3bf6ffcd
| 0.509284 | 3.458716 | false | false | false | false |
vhavlena/appreal
|
netbench/pattern_match/algorithms/clark_nfa/vhdl/clark_strided_nfa.vhd
| 1 | 2,985 |
-- ----------------------------------------------------------------------------
-- Entity for implementation of Clark Strided NFA
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity CLARK_STRIDED_NFA is
generic(
DATA_WIDTH : integer := %$%;
RULES : integer := %$%
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- input data interface
DATA : in std_logic_vector(DATA_WIDTH - 1 downto 0);
SOF : in std_logic;
EOF : in std_logic;
SRC_RDY : in std_logic;
DST_RDY : out std_logic;
-- output data interface
BITMAP : out std_logic_vector(RULES - 1 downto 0);
VLD : out std_logic;
ACK : in std_logic
);
end entity CLARK_STRIDED_NFA;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of CLARK_STRIDED_NFA is
signal local_reset : std_logic;
signal local_reset_fsm : std_logic;
signal we : std_logic;
-- signal rdy : std_logic;
-- signal vld_internal : std_logic;
-- signal set : std_logic;
%$%
begin
local_reset <= RESET or local_reset_fsm;
ctrl_fsm: entity work.CONTROL_FSM
port map(
CLK => CLK,
RESET => RESET,
-- input interface
EOF => EOF,
SRC_RDY => SRC_RDY,
DST_RDY => DST_RDY,
-- output interface
WE => we,
LOCAL_RESET => local_reset_fsm,
-- inner interface
VLD => VLD,
ACK => ACK
);
-- local_reset <= RESET or ACK;
-- we <= SRC_RDY and rdy;
-- DST_RDY <= rdy;
-- VLD <= vld_internal;
-- set <= SRC_RDY and EOF and rdy;
-- rdy <= not vld_internal;
--
-- end_reg: process(CLK)
-- begin
-- if (CLK'event and CLK = '1') then
-- if (local_reset = '1') then
-- vld_internal <= '0';
-- else
-- if set = '1' then
-- vld_internal <= '1';
-- end if;
-- end if;
-- end if;
-- end process end_reg;
%$%
final_bitmap_u: entity work.FINAL_BITMAP
generic map(
DATA_WIDTH => RULES
)
port map(
CLK => CLK,
RESET => local_reset,
-- input data interface
SET => bitmap_in,
-- output data interface
BITMAP => BITMAP
);
end architecture full;
|
gpl-2.0
|
19d08e9245e0d51c418a2b56cc05e9ed
| 0.40536 | 4.313584 | false | false | false | false |
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