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stringlengths 6
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stringlengths 6
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| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
skrasser/papilio_scroller
|
hdl/scroller.vhd
| 1 | 2,106 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Scroller is
Port ( SWITCH : in STD_LOGIC_VECTOR(7 downto 0);
LED : out STD_LOGIC_VECTOR(7 downto 0);
Seg7 : out STD_LOGIC_VECTOR(7 downto 0);
Seg7AN : out STD_LOGIC_VECTOR(3 downto 0);
CLK : in STD_LOGIC
);
end Scroller;
architecture Behavioral of Scroller is
signal counter : STD_LOGIC_VECTOR(27 downto 0) := (others => '0');
signal display : STD_LOGIC_VECTOR(15 * 4 - 1 downto 0) := x"123104556780000";
signal code : STD_LOGIC_VECTOR(3 downto 0);
begin
-- decodes 4 bit code into 8 bit 7 segment input
decoder: process(code)
begin
case code is
-- ABCDEFG.
when x"1" => Seg7 <= "11100001"; -- t
when x"2" => Seg7 <= "01100001"; -- E
when x"3" => Seg7 <= "01001001"; -- S
when x"4" => Seg7 <= "01110001"; -- f
when x"5" => Seg7 <= "11000101"; -- o
when x"6" => Seg7 <= "11000001"; -- b
when x"7" => Seg7 <= "00010001"; -- A
when x"8" => Seg7 <= "11110100"; -- r.
when others => Seg7 <= "11111111";
end case;
end process;
-- shift by 4 bits to get next character in view
shifter: process(counter, display)
begin
if rising_edge(counter(23)) then
display <= display(15 * 4 - 5 downto 0) & display(15 * 4 - 1 downto 15 * 4 - 4);
end if;
end process;
-- demux two bits of counters to drive one of four digits
anode: process(counter)
begin
case counter(12 downto 11) is
when "00" =>
Seg7AN <= "1110";
code <= display(3 downto 0);
when "01" =>
Seg7AN <= "1101";
code <= display(7 downto 4);
when "10" =>
Seg7AN <= "1011";
code <= display(11 downto 8);
when "11" =>
Seg7AN <= "0111";
code <= display(15 downto 12);
when others =>
Seg7AN <= "1111";
code <= "0000";
end case;
end process;
count: process(CLK)
begin
if rising_edge(CLK) then
counter <= std_logic_vector(unsigned(counter) + 1);
end if;
end process;
end Behavioral;
|
mit
|
be8772b967fb078eb69a022a6666ba2f
| 0.564103 | 3.402262 | false | false | false | false |
Krabby127/ADC
|
scratch.vhd
| 1 | 3,152 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.all;
library std;
USE std.textio.all;
entity tb2 is
end entity;
architecture behav2 of tb2 is
component adclb
port (
reset :in std_logic;
clk :in std_logic;
clrb :in std_logic;
scl :out std_logic;
sdai :in std_logic;
sdao :out std_logic;
sda_oe :out std_logic;
min_flag :out std_logic;
max_flag :out std_logic;
diff_flag :out std_logic;
max :out std_logic_vector (7 downto 0);
min :out std_logic_vector (7 downto 0);
value :inout std_logic_vector (7 downto 0) -- data sent back to master
);
end component;
signal clk : std_logic;
signal reset : std_logic;
signal sdai : std_logic;
signal sdao : std_logic;
signal sda_oe : std_logic;
signal min_i : std_logic;
signal max_i : std_logic;
signal diff_i : std_logic;
signal upd : std_logic;
signal scl : std_logic;
-- signal start_bit : std_logic;
-- signal stop_bit : std_logic;
-- shared variable bit_count : integer := 0;
begin
adc: adclb
port map (
reset => reset,
clk => clk,
clrb => reset,
scl => scl,
sdai => sdai,
sdao => sdao,
sda_oe => sda_oe,
diff_flag => diff_i,
min_flag => min_i,
max_flag => max_i,
max => open,
min => open,
value => open
);
clk_p:process
begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process;
testb:process
begin
reset <= '1';
-- start_bit <= '0';
sdai <= '0';
upd <= '0';
wait for 200ns;
reset <= '0';
wait for 5ms;
reset<='1';
wait for 200ns;
reset<='0';
wait for 6103us;
sdai <= '1';
wait for 2us;
sdai <= '0';
wait;
end process;
-- start_b:process
-- begin
-- wait until falling_edge(sdao);
---- wait for 0.64us;
-- wait until falling_edge(scl);
-- if stop_bit /= '1' then
-- start_bit<='1';
-- else
-- start_bit<='0';
-- end if;
-- end process;
--
--
-- stop_b:process
-- begin
-- wait until rising_edge(scl) and sdao='0';
-- if sdao='0' then
-- stop_bit<='1';
-- else
-- stop_bit<='0';
-- end if;
---- if rising_edge(sdao) then
---- stop_bit<='1';
---- else
---- stop_bit<='0';
---- end if;
-- end process;
--
-- count_bits:process
-- begin
-- if stop_bit='1' then
-- bit_count:=0;
-- end if;
-- wait until start_bit='1';
-- if rising_edge(scl) then
-- bit_count:=bit_count+1;
-- else
-- bit_count:=bit_count;
-- end if;
-- end process;
end;
|
apache-2.0
|
272ddf76f0c1e2dd8b84e48dacdd83ea
| 0.45368 | 3.356763 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/VGA1/ipcore_dir/clock_manager.vhd
| 1 | 6,230 |
-- file: clock_manager.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____40.000______0.000______50.0______700.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________32____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock_manager is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
pixel_clock : out std_logic
);
end clock_manager;
architecture xilinx of clock_manager is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clock_manager,clk_wiz_v3_6,{component_name=clock_manager,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => pixel_clock,
I => clkfx);
end xilinx;
|
gpl-3.0
|
f6845d031ec681ae65fb2bd5a5dfe7c0
| 0.57496 | 4.347523 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
dvb_pll.vhd
| 1 | 15,387 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: dvb_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dvb_pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END dvb_pll;
ARCHITECTURE SYN OF dvb_pll IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
locked <= sub_wire0;
sub_wire2 <= sub_wire1(0);
c0 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 4,
clk0_phase_shift => "0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone IV GX",
lpm_hint => "CBX_MODULE_PREFIX=dvb_pll",
lpm_type => "altpll",
operation_mode => "NO_COMPENSATION",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire4,
locked => sub_wire0,
clk => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "108.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "108.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "dvb_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dvb_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dvb_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dvb_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dvb_pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dvb_pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dvb_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
gpl-3.0
|
fe376b73c9f9e2de37edfd606f625110
| 0.697797 | 3.34282 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/bd/ip/bd_proc_sys_reset_0_0/bd_proc_sys_reset_0_0_sim_netlist.vhdl
| 1 | 31,530 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Apr 14 18:32:23 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top bd_proc_sys_reset_0_0 -prefix
-- bd_proc_sys_reset_0_0_ bd_proc_sys_reset_0_0_sim_netlist.vhdl
-- Design : bd_proc_sys_reset_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_0_0_cdc_sync is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
ext_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
slowest_sync_clk : in STD_LOGIC
);
end bd_proc_sys_reset_0_0_cdc_sync;
architecture STRUCTURE of bd_proc_sys_reset_0_0_cdc_sync is
signal exr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => exr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ext_reset_in,
I1 => mb_debug_sys_rst,
O => exr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_0_0_cdc_sync_0 is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
aux_reset_in : in STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_proc_sys_reset_0_0_cdc_sync_0 : entity is "cdc_sync";
end bd_proc_sys_reset_0_0_cdc_sync_0;
architecture STRUCTURE of bd_proc_sys_reset_0_0_cdc_sync_0 is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_0_0_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end bd_proc_sys_reset_0_0_upcnt_n;
architecture STRUCTURE of bd_proc_sys_reset_0_0_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_0_0_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
aux_reset_in : in STD_LOGIC
);
end bd_proc_sys_reset_0_0_lpf;
architecture STRUCTURE of bd_proc_sys_reset_0_0_lpf is
signal \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of POR_SRL_I : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_HIGH_EXT.ACT_HI_EXT\: entity work.bd_proc_sys_reset_0_0_cdc_sync
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.bd_proc_sys_reset_0_0_cdc_sync_0
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => Q,
I1 => lpf_asr,
I2 => dcm_locked,
I3 => lpf_exr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_0_0_sequence_psr is
port (
Core : out STD_LOGIC;
bsr : out STD_LOGIC;
pr : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end bd_proc_sys_reset_0_0_sequence_psr;
architecture STRUCTURE of bd_proc_sys_reset_0_0_sequence_psr is
signal \^core\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^bsr\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^pr\ : STD_LOGIC;
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Core <= \^core\;
bsr <= \^bsr\;
pr <= \^pr\;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^core\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^core\,
S => lpf_int
);
SEQ_COUNTER: entity work.bd_proc_sys_reset_0_0_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^core\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_0_0_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of bd_proc_sys_reset_0_0_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of bd_proc_sys_reset_0_0_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of bd_proc_sys_reset_0_0_proc_sys_reset : entity is "1'b1";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of bd_proc_sys_reset_0_0_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of bd_proc_sys_reset_0_0_proc_sys_reset : entity is "artix7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of bd_proc_sys_reset_0_0_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of bd_proc_sys_reset_0_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of bd_proc_sys_reset_0_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of bd_proc_sys_reset_0_0_proc_sys_reset : entity is 1;
end bd_proc_sys_reset_0_0_proc_sys_reset;
architecture STRUCTURE of bd_proc_sys_reset_0_0_proc_sys_reset is
signal Core : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal bsr : STD_LOGIC;
signal lpf_int : STD_LOGIC;
signal pr : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \BSR_OUT_DFF[0].bus_struct_reset_reg[0]\ : label is "no";
attribute equivalent_register_removal of \PR_OUT_DFF[0].peripheral_reset_reg[0]\ : label is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.bd_proc_sys_reset_0_0_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
\PR_OUT_DFF[0].peripheral_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.bd_proc_sys_reset_0_0_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ => SEQ_n_4,
Core => Core,
bsr => bsr,
lpf_int => lpf_int,
pr => pr,
slowest_sync_clk => slowest_sync_clk
);
mb_reset_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core,
Q => mb_reset,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_0_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bd_proc_sys_reset_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bd_proc_sys_reset_0_0 : entity is "bd_proc_sys_reset_0_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bd_proc_sys_reset_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bd_proc_sys_reset_0_0 : entity is "proc_sys_reset,Vivado 2016.4";
end bd_proc_sys_reset_0_0;
architecture STRUCTURE of bd_proc_sys_reset_0_0 is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b1";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
begin
U0: entity work.bd_proc_sys_reset_0_0_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
|
mit
|
03074e5f27c89cb834f8073dd6546f67
| 0.56746 | 2.853394 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/bd/ip/bd_proc_sys_reset_1_0/synth/bd_proc_sys_reset_1_0.vhd
| 1 | 6,554 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY bd_proc_sys_reset_1_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END bd_proc_sys_reset_1_0;
ARCHITECTURE bd_proc_sys_reset_1_0_arch OF bd_proc_sys_reset_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bd_proc_sys_reset_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bd_proc_sys_reset_1_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bd_proc_sys_reset_1_0_arch : ARCHITECTURE IS "bd_proc_sys_reset_1_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bd_proc_sys_reset_1_0_arch: ARCHITECTURE IS "bd_proc_sys_reset_1_0,proc_sys_reset,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=1,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "artix7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END bd_proc_sys_reset_1_0_arch;
|
mit
|
53d16990b13ff96e7be07523bb507767
| 0.711779 | 3.467725 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
spi_master_0.vhd
| 1 | 3,513 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- spi_master_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity spi_master_0 is
port (
in_data : in std_logic_vector(15 downto 0) := (others => '0'); -- avalon_slave_0.writedata
wr_en : in std_logic := '0'; -- .write
out_data : out std_logic_vector(15 downto 0); -- .readdata
wait_req : out std_logic; -- .waitrequest
addr : in std_logic_vector(9 downto 0) := (others => '0'); -- .address
byte_en : in std_logic_vector(1 downto 0) := (others => '0'); -- .byteenable
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
sclk : out std_logic; -- conduit_end.export
mosi : out std_logic; -- .export
miso : in std_logic := '0'; -- .export
cs_n : out std_logic; -- .export
irq : out std_logic -- .export
);
end entity spi_master_0;
architecture rtl of spi_master_0 is
component spi_master_16 is
port (
in_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
wr_en : in std_logic := 'X'; -- write
out_data : out std_logic_vector(15 downto 0); -- readdata
wait_req : out std_logic; -- waitrequest
addr : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
byte_en : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
sclk : out std_logic; -- export
mosi : out std_logic; -- export
miso : in std_logic := 'X'; -- export
cs_n : out std_logic; -- export
irq : out std_logic -- export
);
end component spi_master_16;
begin
spi_master_0 : component spi_master_16
port map (
in_data => in_data, -- avalon_slave_0.writedata
wr_en => wr_en, -- .write
out_data => out_data, -- .readdata
wait_req => wait_req, -- .waitrequest
addr => addr, -- .address
byte_en => byte_en, -- .byteenable
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
sclk => sclk, -- conduit_end.export
mosi => mosi, -- .export
miso => miso, -- .export
cs_n => cs_n, -- .export
irq => irq -- .export
);
end architecture rtl; -- of spi_master_0
|
gpl-3.0
|
84af431837aec4661de25abdb2e951a5
| 0.411329 | 3.822633 | false | false | false | false |
UviDTE-UviSpace/UviSpace
|
DE1-SoC/FPGA_Design/ip/camera_controller/image_capture.vhd
| 1 | 12,380 |
------------------------------------------------------------------------
-- image_capture component
------------------------------------------------------------------------
-- This component is used to save an image in memory. It uses one
-- buffer in processor memory at address 'buff'.
-- When 'start_capture' is asserted the component waits for the next
-- positive flank of 'frame_valid' for synchronizing and starting at the
-- beginning of a new image. Then, every time 'data_valid' is
-- asserted the component packs the {R,G,B,Gray} components into a
-- 32-bit (when components are 8-bit) or 64-bit (when
-- components are 16-bit) word and writes it to the avalon bus.
-- It is assumed that the bus can react in a single clock cycle to the
-- writings because 'waitrequest' signal of avalon specification is not
-- implemented.
-- In case the slave bus cannot react in a single cycle, an
-- Avalon FIFO should be implemented in between the master of this
-- component and the slave where data is being written. In this case,
-- the component behaviour would be the following:
-- The component starts writing in buff0.
-- When a line from the image is acquired buff0full signal is
-- asserted during 1 clock cycle. Next line is written into buff1.
-- When a line from the image is acquired again the bus asserts
-- buff1full line for 1 cycle. Next line is saved in buff0 again.
-- So the component goes writing odd lines in buff0 and even lines
-- in buff1 until all lines in one image (image_height) are acquired.
-- The processor (or whatever component processes acquired lines)
-- should empty one buffer before this component finishes
-- filling the other one so data is not lost.
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all; -- For using ceil and log2.
use IEEE.NUMERIC_STD.all; -- For using to_unsigned.
use ieee.std_logic_unsigned.all; -- Needed for the sum used in counter.
entity image_capture is
generic (
-- Size of each color component in bits (8 or 16).
COMPONENT_SIZE : integer := 8;
-- Number of pixels per write in the output avalon bus (>=1)
PIX_WR : integer := 4
);
port (
-- Clock and reset.
clk : in STD_LOGIC;
reset_n : in STD_LOGIC;
-- Signals from the video stream representing one pixel in RGB and grey
R : in STD_LOGIC_VECTOR((COMPONENT_SIZE - 1) downto 0);
G : in STD_LOGIC_VECTOR((COMPONENT_SIZE - 1) downto 0);
B : in STD_LOGIC_VECTOR((COMPONENT_SIZE - 1) downto 0);
Gray : in STD_LOGIC_VECTOR((COMPONENT_SIZE - 1) downto 0);
-- Signals to control the component
-- When frame_valid is 1, the image from camera is being acquired.
frame_valid : in STD_LOGIC;
data_valid : in STD_LOGIC; -- Valid pixel in R,G,B,Gray inputs.
-- Signals to control this component (usually coming from avalon_camera)
-- When start_capture is 1, start getting a new image.
start_capture : in STD_LOGIC;
-- Number of columns and rows in the input image array.
image_size : in STD_LOGIC_VECTOR(23 downto 0);
-- Image buffer address.
buff : in STD_LOGIC_VECTOR(31 downto 0);
-- Flag that indicates that the image has been captured
-- (Active 1 clock cycle only).
image_captured : out STD_LOGIC;
-- Signal indicating standby state
--(outside of reset, waiting for flank in start_capture)
standby : out STD_LOGIC;
-- Avalon MM Master port to save data into a memory.
-- Byte addresses are multiples of 4 when accessing 32-bit data.
address : out STD_LOGIC_VECTOR(31 downto 0);
write : out STD_LOGIC;
byteenable : out STD_LOGIC_VECTOR((PIX_WR*COMPONENT_SIZE/2 - 1)
downto 0);
writedata : out STD_LOGIC_VECTOR((PIX_WR*COMPONENT_SIZE*4 - 1)
downto 0);
waitrequest : in STD_LOGIC;
burstcount : out STD_LOGIC_VECTOR(6 downto 0)
);
end image_capture;
architecture arch of image_capture is
type array_of_std_logic_vector is array(natural range <>)
of STD_LOGIC_VECTOR;
constant NUMBER_OF_STATES : INTEGER := 6;
--signals for the evolution of the state machine
signal current_state : INTEGER range 0 to (NUMBER_OF_STATES - 1);
signal next_state : INTEGER range 0 to (NUMBER_OF_STATES - 1);
-- Conditions to change next state.
-- State_condition(x) condition to go from x to x+1.
signal state_condition : STD_LOGIC_VECTOR((NUMBER_OF_STATES - 2)
downto 0);
signal condition_5_to_1 : STD_LOGIC;
--counters.
signal pix_counter : STD_LOGIC_VECTOR(23 downto 0);
signal image_end_reached : STD_LOGIC;
signal pix_wr_counter : STD_LOGIC_VECTOR(integer(
ceil(log2(real(PIX_WR+1)))) downto 0);
-- Write_buff saves the address where the next pixel will be saved.
signal write_buff : STD_LOGIC_VECTOR(31 downto 0);
-- Internal copy of the write output signal
signal av_write : STD_LOGIC;
-- Extra buffers to pack the pixels and reduce the number of writes in bus
signal output_buff : array_of_std_logic_vector((PIX_WR - 1)
downto 0) ((COMPONENT_SIZE*4-1) downto 0);
signal out_buff_EN :STD_LOGIC_VECTOR((PIX_WR - 1) downto 0);
--Packs input components into a single variable
signal input_data :STD_LOGIC_VECTOR((COMPONENT_SIZE*4 - 1)
downto 0);
-- captures a flank in start capture that comes from other clock region.
signal start_capture_reg : STD_LOGIC;
begin
-- FSM (Finite State Machine) clocking and reset.
fsm_mem: process (clk,reset_n)
begin
if rising_edge(clk) then
if reset_n = '0' then
current_state <= 0;
else
current_state <= next_state;
end if;
end if;
end process fsm_mem;
-- Evolution of FSM.
comb_fsm: process (current_state, state_condition, condition_5_to_1)
begin
case current_state is
when 0 =>
if state_condition(0) = '1' then
next_state <= 1;
else
next_state <= 0;
end if;
when 1 =>
if state_condition(1) = '1' then
next_state <= 2;
else
next_state<=1;
end if;
when 2 =>
if state_condition(2) = '1' then
next_state <= 3;
else
next_state<=2;
end if;
when 3 =>
if state_condition(3) = '1' then
next_state <= 4;
else
next_state<=3;
end if;
when 4 =>
if state_condition(4) = '1' then
next_state <= 5;
else
next_state<=4;
end if;
when 5 =>
if condition_5_to_1 = '1' then
next_state <= 1;
else
next_state<=5;
end if;
when others =>
next_state <= 0;
end case;
end process comb_fsm;
-- Conditions of FSM.
state_condition(0) <= '1';
state_condition(1) <= start_capture_reg;
state_condition(2) <= not(frame_valid);
state_condition(3) <= frame_valid;
state_condition(4) <= image_end_reached;
condition_5_to_1 <= '1';
-- Evaluation and update pix_counter.
pix_counter_proc:process (clk, current_state, data_valid)
begin
if rising_edge(clk) then
if (current_state = 1) then
-- reset the pixel counter
pix_counter <= (others => '0');
elsif (current_state = 4) and (data_valid = '1') then
-- Increment the pixel counter
pix_counter <= pix_counter + 1;
end if;
end if;
if pix_counter = image_size(23 downto 0) then
image_end_reached <= '1';
else
image_end_reached <= '0';
end if;
end process;
-- Evaluation and update pix_wr_counter.
pix_wr_counter_proc:process (clk)
begin
if rising_edge(clk) then
if (current_state = 1) then
-- reset the pixel write counter
pix_wr_counter <= (others => '0');
elsif (current_state = 4) and (data_valid = '1') then
-- Increment the pixel write counter
if pix_wr_counter = (PIX_WR-1) then
pix_wr_counter <= (others => '0');
else
pix_wr_counter <= pix_wr_counter + 1;
end if;
end if;
end if;
end process;
-- Generate standby signal
with current_state select standby <=
'1' when 1,
'0' when others;
-- Generate image_captured signal
with current_state select image_captured <=
'1' when 5,
'0' when others;
-- Save data in extra output buffers
input_data <= Gray & B & G & R;
out_buff_generate: for I in 0 to (PIX_WR-1) generate
output_buff_proc: process (clk)
begin
if rising_edge(clk) then
if current_state = 0 or current_state = 1 then
output_buff(I) <= (others => '0');
elsif (out_buff_EN(I)='1') then
output_buff(I) <= input_data;
end if;
end if;
end process;
out_buff_EN_proc: process (clk, data_valid, pix_wr_counter,
current_state)
begin
if (data_valid = '1') and (pix_wr_counter = I)
and (current_state = 4) then
out_buff_EN(I) <= '1';
else
out_buff_EN(I) <= '0';
end if;
end process;
end generate out_buff_generate;
--Generate Avalon signals
--write data
write_data_generate : for I in 0 to (PIX_WR-1) generate
writedata(((I+1)*4*COMPONENT_SIZE - 1) downto (I*4*COMPONENT_SIZE)) <=
output_buff(I);
end generate write_data_generate;
--byteenable
byteenable <= (others => '1');
--burstcount
-- Always single transactions (no burst)
burstcount <= "0000001";
-- write
write_proc : process (clk)
begin
if rising_edge(clk) then
if current_state = 0 or current_state = 1 then
av_write <= '0';
elsif out_buff_EN(PIX_WR-1) = '1' then
av_write <= '1';
else
av_write <= '0';
end if;
end if;
end process;
write <= av_write;
-- address
buff_proc:process (clk)
begin
if rising_edge(clk) then
if current_state = 1 then --reset signals to initial values
write_buff <= buff;
elsif av_write = '1' then
write_buff <= write_buff + (PIX_WR*COMPONENT_SIZE/2);
end if;
end if;
end process;
address <= write_buff;
-- Detection of a flank in start_capture. This signal is coming from the
-- processor and could have different clock. That's why flank is detected
-- instead of level.
start_capture_reg_proc:process(start_capture, current_state)
begin
if (current_state = 2 or current_state = 0) then
start_capture_reg <= '0';
elsif rising_edge(start_capture) then
start_capture_reg <= '1';
end if;
end process;
end arch;
|
gpl-3.0
|
9ba415373a0d130f86d34191f36c2239
| 0.528352 | 4.30459 | false | false | false | false |
Franderg/CE-4301-Arqui1
|
Processor/unsaved/unsaved_inst.vhd
| 1 | 1,819 |
component unsaved is
port (
clk_clk : in std_logic := 'X'; -- clk
pc_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
pc_debugaccess : in std_logic := 'X'; -- debugaccess
pc_clken : in std_logic := 'X'; -- clken
pc_chipselect : in std_logic := 'X'; -- chipselect
pc_write : in std_logic := 'X'; -- write
pc_readdata : out std_logic_vector(31 downto 0); -- readdata
pc_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
pc_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset_reset : in std_logic := 'X'; -- reset
reset_reset_req : in std_logic := 'X' -- reset_req
);
end component unsaved;
u0 : component unsaved
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
pc_address => CONNECTED_TO_pc_address, -- pc.address
pc_debugaccess => CONNECTED_TO_pc_debugaccess, -- .debugaccess
pc_clken => CONNECTED_TO_pc_clken, -- .clken
pc_chipselect => CONNECTED_TO_pc_chipselect, -- .chipselect
pc_write => CONNECTED_TO_pc_write, -- .write
pc_readdata => CONNECTED_TO_pc_readdata, -- .readdata
pc_writedata => CONNECTED_TO_pc_writedata, -- .writedata
pc_byteenable => CONNECTED_TO_pc_byteenable, -- .byteenable
reset_reset => CONNECTED_TO_reset_reset, -- reset.reset
reset_reset_req => CONNECTED_TO_reset_reset_req -- .reset_req
);
|
gpl-3.0
|
2e1d01c9ede8b3bb1cfd59181e305df4
| 0.487081 | 3.552734 | false | false | false | false |
antlr/grammars-v4
|
vhdl/examples/misc.vhd
| 5 | 32,998 |
--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--library SYNOPSYS;
--use SYNOPSYS.attributes.all;
package std_logic_misc is
-- output-strength types
type STRENGTH is (strn_X01, strn_X0H, strn_XL1, strn_X0Z, strn_XZ1,
strn_WLH, strn_WLZ, strn_WZH, strn_W0H, strn_WL1);
--synopsys synthesis_off
type MINOMAX is array (1 to 3) of TIME;
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC;
---------------------------------------------------------------------
--
-- conversion functions for STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
--synopsys synthesis_off
--attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) return STD_LOGIC;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
--synopsys synthesis_on
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_(U)LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_(U)LOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT;
--------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01;
function fun_WiredX(Input0, Input1: std_ulogic) return STD_LOGIC;
--synopsys synthesis_on
end;
package body std_logic_misc is
--synopsys synthesis_off
type STRN_STD_ULOGIC_TABLE is array (STD_ULOGIC,STRENGTH) of STD_ULOGIC;
--------------------------------------------------------------------
--
-- Truth tables for output strength --> STD_ULOGIC lookup
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
--------------------------------------------------------------------
--
-- Truth tables for strength --> STD_ULOGIC mapping ('Z' pass through)
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC_Z: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 387
begin
return tbl_STRN_STD_ULOGIC(input, strn);
end strength_map;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 388
begin
return tbl_STRN_STD_ULOGIC_Z(input, strn);
end strength_map_z;
---------------------------------------------------------------------
--
-- conversion functions for STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 389
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_ULOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 390
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_LOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
--synopsys synthesis_off
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
--
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC is
-- pragma subpgm_id 391
begin
if V = 'Z' then
return vZ;
elsif V = 'U' then
return vU;
elsif V = '-' then
return vDC;
else
return V;
end if;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 392
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 393
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 394
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 395
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
--synopsys synthesis_on
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 396
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_LOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_ULOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 397
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_ULOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_ULOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 398
variable Result: BIT;
begin
--synopsys synthesis_off
case V is
when '0' | 'L' =>
Result := '0';
when '1' | 'H' =>
Result := '1';
when 'X' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result := vZ;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result := vU;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result := vDC;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: - --> 0"
severity WARNING;
end if;
end case;
return Result;
--synopsys synthesis_on
end STD_ULOGICtoBIT;
--------------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 399
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 400
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 401
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 402
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 403
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 404
begin
return not XOR_REDUCE(ARG);
end;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 405
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 406
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 407
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 408
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 409
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 410
begin
return not XOR_REDUCE(ARG);
end;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 411
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3S: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('Z', 'Z', 'Z', 'Z'), --| 0 X01 |
('U', 'X', '0', '1')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('Z', 'Z', 'Z', 'Z'), --| 0 X0H |
('U', 'X', '0', 'H')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XL1 |
('U', 'X', 'L', '1')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('Z', 'Z', 'Z', 'Z'), --| 0 X0Z |
('U', 'X', '0', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XZ1 |
('U', 'X', 'Z', '1')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('Z', 'Z', 'Z', 'Z'), --| 0 WLH |
('U', 'W', 'L', 'H')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('Z', 'Z', 'Z', 'Z'), --| 0 WLZ |
('U', 'W', 'L', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('Z', 'Z', 'Z', 'Z'), --| 0 WZH |
('U', 'W', 'Z', 'H')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('Z', 'Z', 'Z', 'Z'), --| 0 W0H |
('U', 'W', '0', 'H')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 WL1 |
('U', 'W', 'L', '1')));--| 1 WL1 |
begin
return tbl_BUF3S(Strn, Enable, Input);
end fun_BUF3S;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 412
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3SL: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('U', 'X', '0', '1'), --| 0 X01 |
('Z', 'Z', 'Z', 'Z')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('U', 'X', '0', 'H'), --| 0 X0H |
('Z', 'Z', 'Z', 'Z')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('U', 'X', 'L', '1'), --| 0 XL1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('U', 'X', '0', 'Z'), --| 0 X0Z |
('Z', 'Z', 'Z', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('U', 'X', 'Z', '1'), --| 0 XZ1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('U', 'W', 'L', 'H'), --| 0 WLH |
('Z', 'Z', 'Z', 'Z')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('U', 'W', 'L', 'Z'), --| 0 WLZ |
('Z', 'Z', 'Z', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('U', 'W', 'Z', 'H'), --| 0 WZH |
('Z', 'Z', 'Z', 'Z')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('U', 'W', '0', 'H'), --| 0 W0H |
('Z', 'Z', 'Z', 'Z')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('U', 'W', 'L', '1'), --| 0 WL1 |
('Z', 'Z', 'Z', 'Z')));--| 1 WL1 |
begin
return tbl_BUF3SL(Strn, Enable, Input);
end fun_BUF3SL;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01 is
-- pragma subpgm_id 413
type MUX_TABLE is array (UX01, UX01, UX01) of UX01;
-- truth table for "MUX2x1" function
constant tbl_MUX2x1: MUX_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | Sel In1 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'X', '0', '1'), --| '0' 'U' |
('U', 'U', 'U', 'U')), --| '1' 'U' |
(('U', 'X', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', '1'), --| '0' 'X' |
('X', 'X', 'X', 'X')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('U', 'X', '0', '1'), --| '0' '0' |
('0', '0', '0', '0')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MUX2x1(Input1, Sel, Input0);
end fun_MUX2x1;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01 is
-- pragma subpgm_id 414
type MAJ23_TABLE is array (UX01, UX01, UX01) of UX01;
----------------------------------------------------------------------------
-- The "tbl_MAJ23" truth table return 1 if the majority of three
-- inputs is 1, a 0 if the majority is 0, a X if unknown, and a U if
-- uninitialized.
----------------------------------------------------------------------------
constant tbl_MAJ23: MAJ23_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | In1 In2 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'U', '0', 'U'), --| '0' 'U' |
('U', 'U', 'U', '1')), --| '1' 'U' |
(('U', 'U', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', 'X'), --| '0' 'X' |
('U', 'X', 'X', '1')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('0', '0', '0', '0'), --| '0' '0' |
('U', 'X', '0', '1')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MAJ23(Input0, Input1, Input2);
end fun_MAJ23;
function fun_WiredX(Input0, Input1: STD_ULOGIC) return STD_LOGIC is
-- pragma subpgm_id 415
TYPE stdlogic_table IS ARRAY(STD_ULOGIC, STD_ULOGIC) OF STD_LOGIC;
-- truth table for "WiredX" function
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ));-- | - |
begin
return resolution_table(Input0, Input1);
end fun_WiredX;
--synopsys synthesis_on
end;
|
mit
|
9511bbe26cb94c502bddf7951f5a8cee
| 0.406449 | 3.366799 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/audioDac/ipcore_dir/rom_memory/example_design/rom_memory_prod.vhd
| 1 | 9,924 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: rom_memory_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : rom_memory.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 9
-- C_READ_WIDTH_A : 9
-- C_WRITE_DEPTH_A : 57775
-- C_READ_DEPTH_A : 57775
-- C_ADDRA_WIDTH : 16
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 9
-- C_READ_WIDTH_B : 9
-- C_WRITE_DEPTH_B : 57775
-- C_READ_DEPTH_B : 57775
-- C_ADDRB_WIDTH : 16
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY rom_memory_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END rom_memory_prod;
ARCHITECTURE xilinx OF rom_memory_prod IS
COMPONENT rom_memory_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : rom_memory_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
gpl-3.0
|
af98c14cb0f89fc11b8087432654e949
| 0.495163 | 3.830181 | false | false | false | false |
arthurbenemann/fpga-bits
|
mandelbrot/ipcore_dir/clock_manager.vhd
| 1 | 6,341 |
-- file: clock_manager.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___200.000______0.000______50.0______210.548____196.077
-- CLK_OUT2____40.000______0.000______50.0______327.382____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________32____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock_manager is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_80 : out std_logic;
CLK_40 : out std_logic
);
end clock_manager;
architecture xilinx of clock_manager is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clock_manager,clk_wiz_v3_6,{component_name=clock_manager,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 4,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 20,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_80,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_40,
I => clkout1);
end xilinx;
|
gpl-3.0
|
7a596c32a606cd7ca603e7b88c72eac8
| 0.596909 | 4.171711 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/jump_pack.vhd
| 1 | 792 |
library ieee;
use ieee.std_logic_1164.all;
package jump_pack is
constant cpu_width : integer := 32;
constant ram_size : integer := 10;
subtype word_type is std_logic_vector(cpu_width-1 downto 0);
type ram_type is array(0 to ram_size-1) of word_type;
function load_hex return ram_type;
end package;
package body jump_pack is
function load_hex return ram_type is
variable ram_buffer : ram_type := (others=>(others=>'0'));
begin
ram_buffer(0) := X"3C081000";
ram_buffer(1) := X"35080000";
ram_buffer(2) := X"01000008";
ram_buffer(3) := X"00000000";
ram_buffer(4) := X"00000100";
ram_buffer(5) := X"01010001";
ram_buffer(6) := X"00000000";
ram_buffer(7) := X"00000000";
ram_buffer(8) := X"00000000";
ram_buffer(9) := X"00000000";
return ram_buffer;
end;
end;
|
mit
|
7db9e879d49ff798d86ea4ee4c9815c5
| 0.665404 | 2.703072 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/nexys4_pack.vhd
| 1 | 596 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package nexys4_pack is
constant data_out_width : integer := 16;
constant data_in_width : integer := 16;
constant cache_address_width : integer := 29;
constant cache_way_width : integer := 1;
constant cache_index_width : integer := 5;
constant cache_offset_width : integer := 4;
constant cache_replace_strat : string := "rr";
constant uart_baud : positive := 9600;
constant uart_clock_frequency : positive := 50000000;
constant lock_control_default : integer := 0;
end package;
|
mit
|
069762ab8c7af0d402aa84cf508de4a4
| 0.684564 | 3.725 | false | false | false | false |
meriororen/i2s-interface-vhdl
|
i2s.vhd
| 1 | 3,699 |
library ieee;
use ieee.std_logic_1164.all;
entity i2s_interface is
generic ( DATA_WIDTH : integer range 16 to 32;
BITPERFRAME : integer
);
port (
clk : in std_logic;
reset : in std_logic;
bclk : in std_logic;
lrclk : in std_logic;
sample_out : out std_logic_vector(DATA_WIDTH - 1 downto 0);
sample_in : in std_logic_vector(DATA_WIDTH - 1 downto 0);
dac_data : out std_logic;
adc_data : in std_logic;
valid : out std_logic;
ready : out std_logic
);
end i2s_interface;
architecture rtl of i2s_interface is
signal sr_in : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal neg_edge, pos_edge : std_logic;
signal lr_edge : std_logic;
signal new_sample : std_logic;
signal zbclk, zzbclk, zzzbclk : std_logic;
signal zlrclk, zzlrclk, zzzlrclk: std_logic;
signal cnt : integer range 0 to 31 := 0;
-- signal bits_to_rx : integer := DATA_WIDTH - 1;
signal sr_out : std_logic_vector(DATA_WIDTH - 1 downto 0);
begin
detect_edge : process(clk)
begin
if rising_edge(clk) then
zbclk <= bclk;
zzbclk <= zbclk;
zzzbclk <= zzbclk;
if zzbclk = '1' and zzzbclk = '0' then
pos_edge <= '1';
elsif zzbclk = '0' and zzzbclk = '1' then
neg_edge <= '1';
else
pos_edge <= '0';
neg_edge <= '0';
end if;
end if;
end process;
detect_lr_edge : process(clk)
begin
if rising_edge(clk) then
zlrclk <= lrclk;
zzlrclk <= zlrclk;
zzzlrclk <= zzlrclk;
if zzlrclk /= zzzlrclk then
lr_edge <= '1';
else
lr_edge <= '0';
end if;
end if;
end process;
detect_sample : process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
cnt <= 0;
valid <= '0';
else
if lr_edge = '1' then
cnt <= 0;
end if;
if pos_edge = '1' then
if cnt < BITPERFRAME/2 - 1 then
cnt <= cnt + 1;
end if;
end if;
if neg_edge = '1' then
if cnt = 1 then
new_sample <= '1';
elsif cnt >= DATA_WIDTH + 1 and cnt < BITPERFRAME/2 - 1 then
new_sample <= '0';
end if;
end if;
if cnt = DATA_WIDTH + 1 and neg_edge = '1' then
valid <= '1';
else
valid <= '0';
end if;
end if;
end if;
end process;
sample_out <= sr_in;
get_data : process(clk)
begin
if rising_edge(clk) then
if pos_edge = '1' and new_sample = '1' then
-- receive
sr_in <= sr_in(sr_in'high - 1 downto 0) & adc_data;
end if;
end if;
end process;
send_data : process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
ready <= '0';
else
if new_sample = '0' then -- get data during delay period
if pos_edge = '1' then
sr_out <= sample_in;
ready <= '1';
end if;
else
if cnt = 0 or cnt > DATA_WIDTH then
dac_data <= 'X';
else
dac_data <= sr_out(DATA_WIDTH - cnt);
end if;
ready <= '0';
end if;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
7a14a94afc65cbc27676c47fa1cceae4
| 0.452825 | 3.560154 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
fifo_in_8b_sync_1.vhd
| 1 | 3,852 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- fifo_in_8b_sync_1.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fifo_in_8b_sync_1 is
port (
byte_en : in std_logic_vector(3 downto 0) := (others => '0'); -- avalon_slave_0.byteenable
in_data : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
wr_en : in std_logic := '0'; -- .write
out_data : out std_logic_vector(31 downto 0); -- .readdata
rd_en : in std_logic := '0'; -- .read
wait_req : out std_logic; -- .waitrequest
addr : in std_logic_vector(1 downto 0) := (others => '0'); -- .address
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
st_data : in std_logic_vector(7 downto 0) := (others => '0'); -- avalon_streaming_sink.data
st_valid : in std_logic := '0'; -- .valid
st_ready : out std_logic; -- .ready
irq : out std_logic -- conduit_end.export
);
end entity fifo_in_8b_sync_1;
architecture rtl of fifo_in_8b_sync_1 is
component fifo_in_8b_sync is
generic (
FIFO_DEPTH : integer := 16;
BUS_WIDTH : integer := 32
);
port (
byte_en : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
in_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
wr_en : in std_logic := 'X'; -- write
out_data : out std_logic_vector(31 downto 0); -- readdata
rd_en : in std_logic := 'X'; -- read
wait_req : out std_logic; -- waitrequest
addr : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
st_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
st_valid : in std_logic := 'X'; -- valid
st_ready : out std_logic; -- ready
irq : out std_logic -- export
);
end component fifo_in_8b_sync;
begin
fifo_in_8b_sync_1 : component fifo_in_8b_sync
generic map (
FIFO_DEPTH => 16,
BUS_WIDTH => 32
)
port map (
byte_en => byte_en, -- avalon_slave_0.byteenable
in_data => in_data, -- .writedata
wr_en => wr_en, -- .write
out_data => out_data, -- .readdata
rd_en => rd_en, -- .read
wait_req => wait_req, -- .waitrequest
addr => addr, -- .address
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
st_data => st_data, -- avalon_streaming_sink.data
st_valid => st_valid, -- .valid
st_ready => st_ready, -- .ready
irq => irq -- conduit_end.export
);
end architecture rtl; -- of fifo_in_8b_sync_1
|
gpl-3.0
|
27a60089e29f53a83afb11aa0f9b24cb
| 0.424455 | 3.589935 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/DCM_clock/ipcore_dir/my_dcm/simulation/my_dcm_tb.vhd
| 1 | 6,118 |
-- file: my_dcm_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity my_dcm_tb is
end my_dcm_tb;
architecture test of my_dcm_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.25 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component my_dcm_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : my_dcm_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
|
gpl-3.0
|
7035340bdab6cec4ff9972da651723bb
| 0.6373 | 4.272346 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/serial_out/tb_top.vhd
| 1 | 5,183 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:59:29 02/23/2016
-- Design Name:
-- Module Name: C:/Users/Arthur/Documents/FPGA_temp/serial_out/tb_top.vhd
-- Project Name: serial_out
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: topModule
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_top IS
END tb_top;
ARCHITECTURE behavior OF tb_top IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT topModule
PORT(
CLK : IN std_logic;
GPIO0 : OUT std_logic;
GPIO1 : OUT std_logic;
RX : IN std_logic;
TX : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RX : std_logic := '1';
--Outputs
signal GPIO0 : std_logic;
signal GPIO1 : std_logic;
signal TX : std_logic;
-- Clock period definitions
constant clk_period : time := 31.25 ns;
constant bit_period : time := 8.68 us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: topModule PORT MAP (
CLK => CLK,
GPIO0 => GPIO0,
GPIO1 => GPIO1,
RX => RX,
TX => TX
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_period*10;
-- insert stimulus here
wait for 10 us;
-- send '0000000'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '0'; -- data
wait for bit_period*8;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '11111111'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period*8;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '11110000'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '00001111'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '01010101'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
-- send '10101010'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
-- send '01010101'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 200 us;
end process;
END;
|
gpl-3.0
|
84181f47c0871d01ed882febc0e62dc4
| 0.550453 | 2.977025 | false | false | false | false |
rinatzakirov/vhdl
|
clock_gen.vhd
| 1 | 906 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
USE IEEE.math_real.ALL;
entity clock_gen is
generic ( freq: real := 100.0 );
port
(
clk: out std_logic;
rst: out std_logic;
rnd: out real
);
end entity;
architecture syn of clock_gen is
signal clk_i: std_logic := '0';
signal rst_i: std_logic := '1';
begin
clk <= clk_i;
rst <= rst_i;
process
variable seed1, seed2: positive;
variable rnd_var: real;
begin
wait for (500 ns / freq);
clk_i <= not clk_i;
uniform(seed1, seed2, rnd_var);
rnd <= rnd_var after 10 ps;
end process;
process(clk_i)
variable count: integer := 0;
begin
if rising_edge(clk_i) then
count := count + 1;
if count = 10 then
rst_i <= '0';
end if;
end if;
end process;
end architecture;
|
lgpl-2.1
|
6c5defb767112ea59435898f1c668114
| 0.547461 | 3.282609 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/FPGA SigGen/Testbenches/SynchronizedGatedCounter_Tester.vhd
| 1 | 7,851 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Tests the synchronized gated counter.
-- To allow testing the overflow circuits, the UUT is configured to a very
-- small counter width.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Globals.all;
entity SynchronizedGatedCounter_Tester is
end entity;
architecture stdarch of SynchronizedGatedCounter_Tester is
--------------------
-- Constants
--------------------
constant counter_width: natural := 4;
constant pulse_period: time := 5ns;
constant toggled_gate_latency_cycles: integer := 2;
constant output_latency_cycles: integer := 2;
--------------------
-- Inputs
--------------------
signal pulse_signal: std_logic := '0';
signal update_output: std_logic := '0';
signal toggled_gate_signal: std_logic := '0';
--------------------
-- Outputs
--------------------
signal counter_value: unsigned(counter_width-1 downto 0);
signal overflow: std_logic;
signal toggled_gate_detected: std_logic;
--------------------
-- Internals
--------------------
signal run_test: boolean := true;
------------------------------------------------------------------------
-- Waits for the four cycle latency that the counter´s registers need
-- to provide the value at its output after toggling the gate signal.
-- Note that the first four cycles of the next counter value are already
-- captured during this time.
------------------------------------------------------------------------
procedure await_output_latency is
begin
-- Wait two cycles, then check whether the toggled gate signal was
-- detected.
wait for toggled_gate_latency_cycles * pulse_period;
assert (toggled_gate_detected = toggled_gate_signal)
report "Toggled gate was not detected." severity error;
-- Wait another two cycles for the counter´s value to get available.
wait for output_latency_cycles * pulse_period;
end procedure;
------------------------------------------------------------------------
-- Prepares the counter to count the first value.
------------------------------------------------------------------------
procedure init_counter is
begin
-- Discard any counter value and start counting.
wait until falling_edge(pulse_signal);
toggled_gate_signal <= not toggled_gate_signal;
-- Await the input to output latency.
await_output_latency;
end procedure;
------------------------------------------------------------------------
-- Makes the counter count the specified number of pulse cycles.
------------------------------------------------------------------------
procedure count_pulse_cycles(no_of_cycles: integer) is
begin
-- Ensure that at least the input to output latency is taken care of
-- (this is necessary because of the sequential testing used here).
assert (no_of_cycles >= (toggled_gate_latency_cycles + output_latency_cycles))
report "Provide at least the latency cycles."
severity error;
-- Count the specified number of cycles excluding the cycles already
-- counted during the input to output latency.
wait for (no_of_cycles-(toggled_gate_latency_cycles + output_latency_cycles)) * pulse_period;
toggled_gate_signal <= not toggled_gate_signal;
-- Await the input to output latency.
await_output_latency;
end procedure;
--------------------------------------------------------------------------
-- Counts different numbers of pulse cycles and checks whether the counter
-- works properly including overflow detection.
--------------------------------------------------------------------------
procedure verify_counter(no_of_cycles: integer; must_overflow: boolean) is
variable expected_value: integer;
begin
count_pulse_cycles(no_of_cycles);
expected_value := no_of_cycles mod 2**counter_width;
assert (counter_value = expected_value)
report "Counter value incorrect, was " &
integer'image(to_integer(counter_value)) & " instead of " &
integer'image(expected_value) & "."
severity error;
if (must_overflow) then
assert (overflow = '1') report "Overflow not indicated."
severity error;
else
assert (overflow = '0') report "Overflow indicated unexpectedly."
severity error;
end if;
end procedure;
begin
--------------------------------------------------------------------------------
-- Instantiate the UUT(s).
--------------------------------------------------------------------------------
uut: entity work.SynchronizedGatedCounter
generic map
(
counter_width => counter_width
)
port map
(
pulse_signal => pulse_signal,
toggled_gate_signal => toggled_gate_signal,
update_output => update_output,
value => counter_value,
overflow => overflow,
toggled_gate_detected => toggled_gate_detected
);
--------------------------------------------------------------------------------
-- Generate the counter clock.
--------------------------------------------------------------------------------
pulse_signal <= not pulse_signal after pulse_period/2 when run_test;
--------------------------------------------------------------------------------
-- Stimulate the UUT.
--------------------------------------------------------------------------------
stimulus: process is
variable iteration: integer := 0;
begin
-- Initialize the counter.
update_output <= '1';
init_counter;
-- Count different numbers of pulse cycles and check whether the counter works properly
-- including overflow detection.
verify_counter(10, false);
verify_counter(4, false);
verify_counter(15, false);
verify_counter(16, true); -- will overflow once
verify_counter(5, false);
verify_counter(40, true); -- will overflow several times
-- Repeat the test once to verify proper continuous operation, then
-- terminate the test.
if (iteration = 0) then
iteration := iteration + 1;
else
run_test <= false;
wait;
end if;
end process;
end architecture;
|
gpl-3.0
|
14fa6f75d52884557e0668f9f31938cc
| 0.492421 | 5.685011 | false | false | false | false |
rinatzakirov/vhdl
|
random_stream_source.vhd
| 1 | 1,684 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
USE IEEE.math_real.ALL;
entity random_stream_source is
generic
(
speed: real := 1.0;
bw : integer := 8;
seed1: positive := 55352;
seed2: positive := 23124;
incrementing: boolean := false
);
port
(
clk : in std_logic ;
rst : in std_logic ;
out_valid : out std_logic ;
out_ready : in std_logic ;
out_data : out std_logic_vector(bw - 1 downto 0)
);
end entity;
architecture syn of random_stream_source is
signal out_valid_i: std_logic;
begin
out_valid <= out_valid_i;
process(clk)
variable rand: real;
variable seed1var: positive := seed1;
variable seed2var: positive := seed2;
variable count: integer := 0;
begin
if rising_edge(clk) then
if rst = '1' then
out_valid_i <= '0';
out_data <= (others => '0');
count := 0;
else
uniform(seed1var, seed2var, rand);
if rand < speed then
out_valid_i <= '1';
else
out_valid_i <= '0';
end if;
if out_valid_i = '1' and out_ready = '1' then
if incrementing then
count := count + 1;
out_data <= std_logic_vector(to_unsigned(count, bw));
else
out_data <= std_logic_vector(to_unsigned(INTEGER(TRUNC(rand * 1048577.0)), bw));
end if;
end if;
end if;
end if;
end process;
end architecture;
|
lgpl-2.1
|
4494ba0f36bca864640e6088cd3e7853
| 0.488124 | 3.750557 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
ci_control.vhd
| 1 | 5,656 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ci_control is
generic (
t_h : natural := 18750000; -- 300 ms
t_w : natural := 12500; -- 200 us aospan:increase reset time (20->200usec) for neotion cam's
t_su : natural := 1251250 -- t_w + 20 ms
);
port (
clk : in std_logic;
rst : in std_logic;
-- CAM control
soft_reset : in std_logic;
stschg_ack : in std_logic;
ci_timeout : in std_logic;
-- CAM interface
ci_cd_n : in std_logic_vector(1 downto 0);
ci_reset : out std_logic;
ci_reset_oe_n : out std_logic;
ci_overcurrent_n : in std_logic;
ci_ireq_n : in std_logic;
-- CAM status
cam_stschg : out std_logic;
cam_present : out std_logic;
cam_reset : out std_logic;
cam_ready : out std_logic;
cam_error : out std_logic;
cam_ovcp : out std_logic;
cam_busy : out std_logic;
cam_interrupt : out std_logic
);
end entity;
architecture rtl of ci_control is
signal ci_cd_meta : std_logic_vector(1 downto 0);
signal ci_cd_sync : std_logic_vector(1 downto 0);
signal ci_ovcp_meta : std_logic;
signal ci_ovcp_sync : std_logic;
signal ci_ireq_meta : std_logic;
signal ci_ireq_sync : std_logic;
signal end_of_por : std_logic;
signal end_of_reset : std_logic;
signal end_of_tsu : std_logic;
signal ci_cnt : unsigned(24 downto 0);
signal ci_cd : std_logic;
signal ci_stschg : std_logic;
signal ci_reset_oe_i : std_logic;
signal ci_reset_phase_n : std_logic;
signal ci_reset_n : std_logic;
type ci_state_t is (
ci_state_por,
ci_state_reset,
ci_state_busy,
ci_state_ready,
ci_state_ovcp,
ci_state_error
);
signal ci_state : ci_state_t;
begin
ci_reset_oe_n <= not ci_reset_oe_i;
ci_reset <= not ci_reset_n;
cam_stschg <= ci_stschg;
cam_present <= ci_cd;
cam_reset <= '1' when ci_state = ci_state_reset else '0';
cam_ready <= '1' when ci_state = ci_state_ready else '0';
cam_busy <= '1' when ci_state = ci_state_busy else '0';
cam_ovcp <= '1' when ci_state = ci_state_ovcp else '0';
cam_error <= '1' when ci_state = ci_state_error else '0';
process (rst, clk, ci_cd)
begin
if rising_edge(clk) then
ci_cd_meta <= not ci_cd_n;
ci_cd_sync <= ci_cd_meta;
ci_cd <= ci_cd_sync(1) and ci_cd_sync(0);
--
ci_ovcp_meta <= not ci_overcurrent_n;
ci_ovcp_sync <= ci_ovcp_meta;
ci_ireq_meta <= not ci_ireq_n;
ci_ireq_sync <= ci_ireq_meta;
-- process timer
if ci_cnt = t_h then
end_of_por <= not ci_reset_oe_i;
else
end_of_por <= '0';
end if;
if ci_cnt = t_w then
end_of_reset <= ci_reset_oe_i;
else
end_of_reset <= '0';
end if;
if ci_cnt = t_su then
end_of_tsu <= ci_reset_oe_i;
else
end_of_tsu <= '0';
end if;
if end_of_por or ci_reset_phase_n then
ci_cnt <= (others => '0');
else
ci_cnt <= ci_cnt + 1;
end if;
--
if stschg_ack then
ci_stschg <= '0';
end if;
case ci_state is
when ci_state_reset | ci_state_busy =>
if ci_reset_phase_n and (ci_ovcp_sync or not ci_ireq_sync) then
ci_stschg <= '1';
end if;
when ci_state_ready =>
if ci_ovcp_sync or ci_timeout or (ci_cd_sync(1) nand ci_cd_sync(0)) then
ci_stschg <= '1';
end if;
when ci_state_ovcp | ci_state_error =>
if ci_cd_sync(1) nand ci_cd_sync(0) then
ci_stschg <= '1';
end if;
when others =>
null;
end case;
-- process reset state machine
ci_reset_oe_i <= ci_reset_oe_i or end_of_por;
if ci_reset_phase_n and soft_reset then
ci_reset_n <= '0';
ci_reset_phase_n <= '0';
else
ci_reset_n <= ci_reset_n or end_of_reset;
ci_reset_phase_n <= ci_reset_phase_n or end_of_tsu;
end if;
-- status state machine
case ci_state is
when ci_state_por =>
if ci_reset_oe_i then
ci_state <= ci_state_reset;
end if;
when ci_state_reset =>
if ci_reset_phase_n then
if ci_ovcp_sync then
ci_state <= ci_state_ovcp;
elsif ci_ireq_sync then
ci_state <= ci_state_busy;
else
ci_state <= ci_state_ready;
end if;
end if;
when ci_state_busy =>
if not ci_reset_phase_n then
ci_state <= ci_state_reset;
elsif ci_ovcp_sync then
ci_state <= ci_state_ovcp;
elsif not ci_ireq_sync then
ci_state <= ci_state_ready;
end if;
when ci_state_ready =>
if not ci_reset_phase_n then
ci_state <= ci_state_reset;
elsif ci_ovcp_sync then
ci_state <= ci_state_ovcp;
elsif ci_timeout then
ci_state <= ci_state_error;
end if;
when ci_state_ovcp =>
if not ci_reset_phase_n then
ci_state <= ci_state_reset;
end if;
when ci_state_error =>
if not ci_reset_phase_n then
ci_state <= ci_state_reset;
end if;
end case;
-- interrupt function
if ci_state = ci_state_ready then
cam_interrupt <= ci_ireq_sync;
else
cam_interrupt <= '0';
end if;
end if;
if not ci_cd then
end_of_por <= '0';
end_of_reset <= '0';
end_of_tsu <= '0';
ci_cnt <= (others => '0');
--
ci_reset_oe_i <= '0';
ci_reset_phase_n <= '0';
ci_reset_n <= '0';
--
ci_state <= ci_state_por;
--
cam_interrupt <= '0';
end if;
if rst then
ci_cd_meta <= (others => '0');
ci_cd_sync <= (others => '0');
--
ci_ovcp_meta <= '0';
ci_ovcp_sync <= '0';
--
ci_ireq_meta <= '0';
ci_ireq_sync <= '0';
--
ci_cd <= '0';
ci_stschg <= '0';
end if;
end process;
end architecture;
|
gpl-3.0
|
f5436c8dec846c34eadafd6aca187e79
| 0.588932 | 2.520499 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/koc/koc_signal.vhd
| 1 | 7,990 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity koc_signal is
generic (
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32;
axi_control_offset : integer := 0;
axi_control_signal_bit_loc : integer := 0;
axi_control_status_bit_loc : integer := 1);
port (
-- Global Interface.
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic; --! Reset on low.
-- Slave AXI4-Lite Write interface.
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal.
axi_awready : out std_logic; --! AXI4-Lite Address Write signal.
axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal.
axi_wready : out std_logic; --! AXI4-Lite Write Data signal.
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal.
axi_bready : in std_logic; --! AXI4-Lite Write Response signal.
axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
-- Slave AXI4-Lite Read interface.
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal.
axi_arready : out std_logic; --! AXI4-Lite Address Read signal.
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal.
axi_rready : in std_logic; --! AXI4-Lite Read Data signal.
axi_rresp : out std_logic_vector(1 downto 0);
-- Events.
sig_out : out std_logic;
sig_in : in std_logic;
int : out std_logic);
end koc_signal;
architecture Behavioral of koc_signal is
component koc_signal_cntrl is
port (
aclk : in std_logic;
aresetn : in std_Logic;
sig_ack : in std_logic;
sig_trig : in std_logic;
sig_in : in std_logic;
sig_out : out std_logic;
int : out std_logic);
end component;
component koc_signal_axi4_write_cntrl is
generic (
axi_address_width : integer := 16;
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000";
reg_control_signal_bit_loc : integer := 0;
reg_control_status_bit_loc : integer := 1);
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_awprot : in std_logic_vector(2 downto 0);
axi_awvalid : in std_logic;
axi_awready : out std_logic;
axi_wvalid : in std_logic;
axi_wready : out std_logic;
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
axi_bvalid : out std_logic;
axi_bready : in std_logic;
axi_bresp : out std_logic_vector(1 downto 0);
sig_trig : out std_logic;
sig_ack : out std_logic);
end component;
component koc_signal_axi4_read_cntrl is
generic (
axi_address_width : integer := 16;
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000";
reg_control_signal_bit_loc : integer := 0;
reg_control_status_bit_loc : integer := 1);
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_arprot : in std_logic_vector(2 downto 0);
axi_arvalid : in std_logic;
axi_arready : out std_logic;
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
axi_rvalid : out std_logic;
axi_rready : in std_logic;
axi_rresp : out std_logic_vector(1 downto 0);
int : in std_logic);
end component;
constant axi_control_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_control_offset,axi_address_width));
signal sig_ack : std_logic;
signal sig_trig : std_logic;
signal int_buff : std_logic;
begin
int <= int_buff;
koc_signal_cntrl_inst : koc_signal_cntrl
port map (
aclk => aclk,
aresetn => aresetn,
sig_ack => sig_ack,
sig_trig => sig_trig,
sig_in => sig_in,
sig_out => sig_out,
int => int_buff);
koc_signal_axi4_write_cntrl_inst : koc_signal_axi4_write_cntrl
generic map (
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
reg_control_offset => axi_control_offset_slv,
reg_control_signal_bit_loc => axi_control_signal_bit_loc,
reg_control_status_bit_loc => axi_control_status_bit_loc)
port map (
aclk => aclk,
aresetn => aresetn,
axi_awaddr => axi_awaddr,
axi_awprot => axi_awprot,
axi_awvalid => axi_awvalid,
axi_awready => axi_awready,
axi_wvalid => axi_wvalid,
axi_wready => axi_wready,
axi_wdata => axi_wdata,
axi_wstrb => axi_wstrb,
axi_bvalid => axi_bvalid,
axi_bready => axi_bready,
axi_bresp => axi_bresp,
sig_trig => sig_trig,
sig_ack => sig_ack);
koc_signal_axi4_read_cntrl_inst : koc_signal_axi4_read_cntrl
generic map (
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
reg_control_offset => axi_control_offset_slv,
reg_control_signal_bit_loc => axi_control_signal_bit_loc,
reg_control_status_bit_loc => axi_control_status_bit_loc)
port map (
aclk => aclk,
aresetn => aresetn,
axi_araddr => axi_araddr,
axi_arprot => axi_arprot,
axi_arvalid => axi_arvalid,
axi_arready => axi_arready,
axi_rdata => axi_rdata,
axi_rvalid => axi_rvalid,
axi_rready => axi_rready,
axi_rresp => axi_rresp,
int => int_buff);
end Behavioral;
|
mit
|
d190450a9f7e4591b3a83417be38ebe4
| 0.489612 | 4.236479 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/audioDac/ipcore_dir/rom_memory.vhd
| 2 | 5,412 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file rom_memory.vhd when simulating
-- the core, rom_memory. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY rom_memory IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END rom_memory;
ARCHITECTURE rom_memory_a OF rom_memory IS
-- synthesis translate_off
COMPONENT wrapped_rom_memory
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_rom_memory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 16,
c_addrb_width => 16,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "rom_memory.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 57775,
c_read_depth_b => 57775,
c_read_width_a => 9,
c_read_width_b => 9,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 57775,
c_write_depth_b => 57775,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 9,
c_write_width_b => 9,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_rom_memory
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END rom_memory_a;
|
gpl-3.0
|
a8b008337d5657569f462877397c67ee
| 0.530488 | 3.997046 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/audioDac/tb_audio.vhd
| 1 | 1,022 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_audio IS
END tb_audio;
ARCHITECTURE behavior OF tb_audio IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT topModule
PORT(
CLK : IN std_logic;
AUDIO1_RIGHT : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
--Outputs
signal AUDIO1_RIGHT : std_logic;
-- Clock period definitions
constant CLK_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: topModule PORT MAP (
CLK => CLK,
AUDIO1_RIGHT => AUDIO1_RIGHT
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
afa5ce6362daaeaa58b4cce28a117bcb
| 0.592955 | 3.785185 | false | false | false | false |
antlr/grammars-v4
|
vhdl/examples/numeric_std.vhd
| 6 | 34,284 |
-- --------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_STD)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type STD_LOGIC.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_STD. The NUMERIC_STD package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
--
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- Version: 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD is
constant CopyRightNotice: STRING
:= "Copyright 1995 IEEE. All rights reserved.";
--============================================================================
-- Numeric array type definitions
--============================================================================
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
--============================================================================
-- Arithmetic Operators:
--===========================================================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the absolute value of a SIGNED vector ARG.
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the value of the unary minus operation on a
-- SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two SIGNED vectors that may be of different lengths.
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
-- Id: A.7
function "+" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
-- vector, R.
-- Id: A.8
function "+" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.11
function "-" (L: UNSIGNED;R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts an INTEGER, R, from a SIGNED vector, L.
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is
-- converted to a SIGNED vector of SIZE L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of SIZE R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an SIGNED vector, L, by another SIGNED vector, R.
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides a SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by a SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are SIGNED vectors.
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are SIGNED vectors.
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is a SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is a SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on a SIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on a SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost
-- element, ARG'LEFT. The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of a SIGNED
-- vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of a SIGNED
-- vector COUNT times.
--============================================================================
--============================================================================
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts a SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
-- Id: D.4
function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a SIGNED vector of the specified SIZE.
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
-- ---------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
-- ---------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
-- ---------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
-- ---------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED; --V93
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
--============================================================================
-- Match Functions
--============================================================================
-- Id: M.1
function STD_MATCH (L, R: STD_ULOGIC) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.2
function STD_MATCH (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.3
function STD_MATCH (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.4
function STD_MATCH (L, R: STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.5
function STD_MATCH (L, R: STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
--============================================================================
-- Translation Functions
--============================================================================
-- Id: T.1
function TO_01 (S: UNSIGNED; XMAP: STD_LOGIC := '0') return UNSIGNED;
-- Result subtype: UNSIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
-- Id: T.2
function TO_01 (S: SIGNED; XMAP: STD_LOGIC := '0') return SIGNED;
-- Result subtype: SIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
end NUMERIC_STD;
|
mit
|
64549a89c804f84fb6b282c38f875004
| 0.562274 | 4.201471 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/bd/hdl/bd.vhd
| 1 | 75,238 |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Wed May 03 18:19:08 2017
--Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
--Command : generate_target bd.bd
--Design : bd
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1RTNB1L is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1RTNB1L;
architecture STRUCTURE of s00_couplers_imp_1RTNB1L is
component bd_auto_cc_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component bd_auto_cc_0;
signal M_ACLK_1 : STD_LOGIC;
signal M_ARESETN_1 : STD_LOGIC;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_cc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_cc_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_cc_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_cc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_cc_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_cc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_cc_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_cc_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_cc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_cc_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_cc_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_cc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_cc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_cc_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_RLAST : STD_LOGIC;
signal auto_cc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_cc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_cc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_cc_to_s00_couplers_WLAST : STD_LOGIC;
signal auto_cc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_cc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_cc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_cc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_cc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_auto_cc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_auto_cc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_cc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_cc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_cc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_cc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_cc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_cc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_auto_cc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_auto_cc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_cc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_cc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_cc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_cc_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_cc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_cc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_cc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_cc_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_cc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_cc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_cc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_cc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_cc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_cc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_cc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_WVALID : STD_LOGIC;
signal NLW_auto_cc_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_auto_cc_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_ACLK_1 <= M_ACLK;
M_ARESETN_1 <= M_ARESETN;
M_AXI_araddr(31 downto 0) <= auto_cc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_cc_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_cc_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(3 downto 0) <= auto_cc_to_s00_couplers_ARID(3 downto 0);
M_AXI_arlen(7 downto 0) <= auto_cc_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= auto_cc_to_s00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_cc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_cc_to_s00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_cc_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_cc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_cc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_cc_to_s00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_cc_to_s00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(3 downto 0) <= auto_cc_to_s00_couplers_AWID(3 downto 0);
M_AXI_awlen(7 downto 0) <= auto_cc_to_s00_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= auto_cc_to_s00_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_cc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_cc_to_s00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_cc_to_s00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_cc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_cc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_cc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_cc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wlast <= auto_cc_to_s00_couplers_WLAST;
M_AXI_wstrb(3 downto 0) <= auto_cc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_cc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s00_couplers_to_auto_cc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_cc_AWREADY;
S_AXI_bid(3 downto 0) <= s00_couplers_to_auto_cc_BID(3 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_cc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_cc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_cc_RDATA(31 downto 0);
S_AXI_rid(3 downto 0) <= s00_couplers_to_auto_cc_RID(3 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_cc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_cc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_cc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_cc_WREADY;
auto_cc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_cc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_cc_to_s00_couplers_BID(3 downto 0) <= M_AXI_bid(3 downto 0);
auto_cc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_cc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_cc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_cc_to_s00_couplers_RID(3 downto 0) <= M_AXI_rid(3 downto 0);
auto_cc_to_s00_couplers_RLAST <= M_AXI_rlast;
auto_cc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_cc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_cc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_cc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_cc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_cc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_cc_ARID(3 downto 0) <= S_AXI_arid(3 downto 0);
s00_couplers_to_auto_cc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_auto_cc_ARLOCK(0) <= S_AXI_arlock(0);
s00_couplers_to_auto_cc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_cc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_cc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
s00_couplers_to_auto_cc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_cc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_cc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_cc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_cc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_cc_AWID(3 downto 0) <= S_AXI_awid(3 downto 0);
s00_couplers_to_auto_cc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s00_couplers_to_auto_cc_AWLOCK(0) <= S_AXI_awlock(0);
s00_couplers_to_auto_cc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_cc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_cc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
s00_couplers_to_auto_cc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_cc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_cc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_cc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_cc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_cc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_cc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_cc_WVALID <= S_AXI_wvalid;
auto_cc: component bd_auto_cc_0
port map (
m_axi_aclk => M_ACLK_1,
m_axi_araddr(31 downto 0) => auto_cc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_cc_to_s00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_cc_to_s00_couplers_ARCACHE(3 downto 0),
m_axi_aresetn => M_ARESETN_1,
m_axi_arid(3 downto 0) => auto_cc_to_s00_couplers_ARID(3 downto 0),
m_axi_arlen(7 downto 0) => auto_cc_to_s00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_cc_to_s00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_cc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_cc_to_s00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_cc_to_s00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_cc_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_cc_to_s00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_cc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_cc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_cc_to_s00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_cc_to_s00_couplers_AWCACHE(3 downto 0),
m_axi_awid(3 downto 0) => auto_cc_to_s00_couplers_AWID(3 downto 0),
m_axi_awlen(7 downto 0) => auto_cc_to_s00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_cc_to_s00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_cc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_cc_to_s00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_cc_to_s00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_cc_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_cc_to_s00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_cc_to_s00_couplers_AWVALID,
m_axi_bid(3 downto 0) => auto_cc_to_s00_couplers_BID(3 downto 0),
m_axi_bready => auto_cc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_cc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_cc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_cc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rid(3 downto 0) => auto_cc_to_s00_couplers_RID(3 downto 0),
m_axi_rlast => auto_cc_to_s00_couplers_RLAST,
m_axi_rready => auto_cc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_cc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_cc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_cc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wlast => auto_cc_to_s00_couplers_WLAST,
m_axi_wready => auto_cc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_cc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_cc_to_s00_couplers_WVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_cc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_cc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_cc_ARCACHE(3 downto 0),
s_axi_aresetn => S_ARESETN_1,
s_axi_arid(3 downto 0) => s00_couplers_to_auto_cc_ARID(3 downto 0),
s_axi_arlen(7 downto 0) => s00_couplers_to_auto_cc_ARLEN(7 downto 0),
s_axi_arlock(0) => s00_couplers_to_auto_cc_ARLOCK(0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_cc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_cc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_cc_ARREADY,
s_axi_arregion(3 downto 0) => s00_couplers_to_auto_cc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_cc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_cc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_cc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_cc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_cc_AWCACHE(3 downto 0),
s_axi_awid(3 downto 0) => s00_couplers_to_auto_cc_AWID(3 downto 0),
s_axi_awlen(7 downto 0) => s00_couplers_to_auto_cc_AWLEN(7 downto 0),
s_axi_awlock(0) => s00_couplers_to_auto_cc_AWLOCK(0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_cc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_cc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_cc_AWREADY,
s_axi_awregion(3 downto 0) => s00_couplers_to_auto_cc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_cc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_cc_AWVALID,
s_axi_bid(3 downto 0) => s00_couplers_to_auto_cc_BID(3 downto 0),
s_axi_bready => s00_couplers_to_auto_cc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_cc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_cc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_cc_RDATA(31 downto 0),
s_axi_rid(3 downto 0) => s00_couplers_to_auto_cc_RID(3 downto 0),
s_axi_rlast => s00_couplers_to_auto_cc_RLAST,
s_axi_rready => s00_couplers_to_auto_cc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_cc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_cc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_cc_WDATA(31 downto 0),
s_axi_wlast => s00_couplers_to_auto_cc_WLAST,
s_axi_wready => s00_couplers_to_auto_cc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_cc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_cc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_axi_interconnect_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end bd_axi_interconnect_0_0;
architecture STRUCTURE of bd_axi_interconnect_0_0 is
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal axi_interconnect_0_ACLK_net : STD_LOGIC;
signal axi_interconnect_0_ARESETN_net : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_BREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_BVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WLAST : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_axi_interconnect_0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_axi_interconnect_0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_RLAST : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_WLAST : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
begin
M00_AXI_araddr(31 downto 0) <= s00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
M00_AXI_arburst(1 downto 0) <= s00_couplers_to_axi_interconnect_0_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= s00_couplers_to_axi_interconnect_0_ARCACHE(3 downto 0);
M00_AXI_arid(3 downto 0) <= s00_couplers_to_axi_interconnect_0_ARID(3 downto 0);
M00_AXI_arlen(7 downto 0) <= s00_couplers_to_axi_interconnect_0_ARLEN(7 downto 0);
M00_AXI_arlock(0) <= s00_couplers_to_axi_interconnect_0_ARLOCK(0);
M00_AXI_arprot(2 downto 0) <= s00_couplers_to_axi_interconnect_0_ARPROT(2 downto 0);
M00_AXI_arqos(3 downto 0) <= s00_couplers_to_axi_interconnect_0_ARQOS(3 downto 0);
M00_AXI_arsize(2 downto 0) <= s00_couplers_to_axi_interconnect_0_ARSIZE(2 downto 0);
M00_AXI_arvalid <= s00_couplers_to_axi_interconnect_0_ARVALID;
M00_AXI_awaddr(31 downto 0) <= s00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
M00_AXI_awburst(1 downto 0) <= s00_couplers_to_axi_interconnect_0_AWBURST(1 downto 0);
M00_AXI_awcache(3 downto 0) <= s00_couplers_to_axi_interconnect_0_AWCACHE(3 downto 0);
M00_AXI_awid(3 downto 0) <= s00_couplers_to_axi_interconnect_0_AWID(3 downto 0);
M00_AXI_awlen(7 downto 0) <= s00_couplers_to_axi_interconnect_0_AWLEN(7 downto 0);
M00_AXI_awlock(0) <= s00_couplers_to_axi_interconnect_0_AWLOCK(0);
M00_AXI_awprot(2 downto 0) <= s00_couplers_to_axi_interconnect_0_AWPROT(2 downto 0);
M00_AXI_awqos(3 downto 0) <= s00_couplers_to_axi_interconnect_0_AWQOS(3 downto 0);
M00_AXI_awsize(2 downto 0) <= s00_couplers_to_axi_interconnect_0_AWSIZE(2 downto 0);
M00_AXI_awvalid <= s00_couplers_to_axi_interconnect_0_AWVALID;
M00_AXI_bready <= s00_couplers_to_axi_interconnect_0_BREADY;
M00_AXI_rready <= s00_couplers_to_axi_interconnect_0_RREADY;
M00_AXI_wdata(31 downto 0) <= s00_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M00_AXI_wlast <= s00_couplers_to_axi_interconnect_0_WLAST;
M00_AXI_wstrb(3 downto 0) <= s00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M00_AXI_wvalid <= s00_couplers_to_axi_interconnect_0_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready <= axi_interconnect_0_to_s00_couplers_ARREADY;
S00_AXI_awready <= axi_interconnect_0_to_s00_couplers_AWREADY;
S00_AXI_bid(3 downto 0) <= axi_interconnect_0_to_s00_couplers_BID(3 downto 0);
S00_AXI_bresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= axi_interconnect_0_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(3 downto 0) <= axi_interconnect_0_to_s00_couplers_RID(3 downto 0);
S00_AXI_rlast <= axi_interconnect_0_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_interconnect_0_to_s00_couplers_RVALID;
S00_AXI_wready <= axi_interconnect_0_to_s00_couplers_WREADY;
axi_interconnect_0_ACLK_net <= M00_ACLK;
axi_interconnect_0_ARESETN_net <= M00_ARESETN;
axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARID(3 downto 0) <= S00_AXI_arid(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_interconnect_0_to_s00_couplers_ARLOCK(0) <= S00_AXI_arlock(0);
axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARREGION(3 downto 0) <= S00_AXI_arregion(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_interconnect_0_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWID(3 downto 0) <= S00_AXI_awid(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWLEN(7 downto 0) <= S00_AXI_awlen(7 downto 0);
axi_interconnect_0_to_s00_couplers_AWLOCK(0) <= S00_AXI_awlock(0);
axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWREGION(3 downto 0) <= S00_AXI_awregion(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
axi_interconnect_0_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
axi_interconnect_0_to_s00_couplers_BREADY <= S00_AXI_bready;
axi_interconnect_0_to_s00_couplers_RREADY <= S00_AXI_rready;
axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
axi_interconnect_0_to_s00_couplers_WLAST <= S00_AXI_wlast;
axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
axi_interconnect_0_to_s00_couplers_WVALID <= S00_AXI_wvalid;
s00_couplers_to_axi_interconnect_0_ARREADY <= M00_AXI_arready;
s00_couplers_to_axi_interconnect_0_AWREADY <= M00_AXI_awready;
s00_couplers_to_axi_interconnect_0_BID(3 downto 0) <= M00_AXI_bid(3 downto 0);
s00_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
s00_couplers_to_axi_interconnect_0_BVALID <= M00_AXI_bvalid;
s00_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
s00_couplers_to_axi_interconnect_0_RID(3 downto 0) <= M00_AXI_rid(3 downto 0);
s00_couplers_to_axi_interconnect_0_RLAST <= M00_AXI_rlast;
s00_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
s00_couplers_to_axi_interconnect_0_RVALID <= M00_AXI_rvalid;
s00_couplers_to_axi_interconnect_0_WREADY <= M00_AXI_wready;
s00_couplers: entity work.s00_couplers_imp_1RTNB1L
port map (
M_ACLK => axi_interconnect_0_ACLK_net,
M_ARESETN => axi_interconnect_0_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_axi_interconnect_0_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_axi_interconnect_0_ARCACHE(3 downto 0),
M_AXI_arid(3 downto 0) => s00_couplers_to_axi_interconnect_0_ARID(3 downto 0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_axi_interconnect_0_ARLEN(7 downto 0),
M_AXI_arlock(0) => s00_couplers_to_axi_interconnect_0_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_axi_interconnect_0_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s00_couplers_to_axi_interconnect_0_ARQOS(3 downto 0),
M_AXI_arready => s00_couplers_to_axi_interconnect_0_ARREADY,
M_AXI_arsize(2 downto 0) => s00_couplers_to_axi_interconnect_0_ARSIZE(2 downto 0),
M_AXI_arvalid => s00_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s00_couplers_to_axi_interconnect_0_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s00_couplers_to_axi_interconnect_0_AWCACHE(3 downto 0),
M_AXI_awid(3 downto 0) => s00_couplers_to_axi_interconnect_0_AWID(3 downto 0),
M_AXI_awlen(7 downto 0) => s00_couplers_to_axi_interconnect_0_AWLEN(7 downto 0),
M_AXI_awlock(0) => s00_couplers_to_axi_interconnect_0_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_axi_interconnect_0_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s00_couplers_to_axi_interconnect_0_AWQOS(3 downto 0),
M_AXI_awready => s00_couplers_to_axi_interconnect_0_AWREADY,
M_AXI_awsize(2 downto 0) => s00_couplers_to_axi_interconnect_0_AWSIZE(2 downto 0),
M_AXI_awvalid => s00_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bid(3 downto 0) => s00_couplers_to_axi_interconnect_0_BID(3 downto 0),
M_AXI_bready => s00_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_axi_interconnect_0_BVALID,
M_AXI_rdata(31 downto 0) => s00_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rid(3 downto 0) => s00_couplers_to_axi_interconnect_0_RID(3 downto 0),
M_AXI_rlast => s00_couplers_to_axi_interconnect_0_RLAST,
M_AXI_rready => s00_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_axi_interconnect_0_RVALID,
M_AXI_wdata(31 downto 0) => s00_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wlast => s00_couplers_to_axi_interconnect_0_WLAST,
M_AXI_wready => s00_couplers_to_axi_interconnect_0_WREADY,
M_AXI_wstrb(3 downto 0) => s00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN => S00_ARESETN_1,
S_AXI_araddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARID(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_interconnect_0_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => axi_interconnect_0_to_s00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => axi_interconnect_0_to_s00_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARREGION(3 downto 0),
S_AXI_arsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_interconnect_0_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWID(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_interconnect_0_to_s00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => axi_interconnect_0_to_s00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => axi_interconnect_0_to_s00_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWREGION(3 downto 0),
S_AXI_awsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_interconnect_0_to_s00_couplers_AWVALID,
S_AXI_bid(3 downto 0) => axi_interconnect_0_to_s00_couplers_BID(3 downto 0),
S_AXI_bready => axi_interconnect_0_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_interconnect_0_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(3 downto 0) => axi_interconnect_0_to_s00_couplers_RID(3 downto 0),
S_AXI_rlast => axi_interconnect_0_to_s00_couplers_RLAST,
S_AXI_rready => axi_interconnect_0_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_interconnect_0_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wlast => axi_interconnect_0_to_s00_couplers_WLAST,
S_AXI_wready => axi_interconnect_0_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_interconnect_0_to_s00_couplers_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd is
port (
DDR2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
DDR2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR2_cas_n : out STD_LOGIC;
DDR2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ras_n : out STD_LOGIC;
DDR2_we_n : out STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC;
aclk : out STD_LOGIC;
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
sys_clk_i : in STD_LOGIC;
sys_rst : in STD_LOGIC
);
attribute core_generation_info : string;
attribute core_generation_info of bd : entity is "bd,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute hw_handoff : string;
attribute hw_handoff of bd : entity is "bd.hwdef";
end bd;
architecture STRUCTURE of bd is
component bd_mig_7series_0_0 is
port (
sys_rst : in STD_LOGIC;
clk_ref_i : in STD_LOGIC;
ddr2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
ddr2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
ddr2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
ddr2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
ui_clk_sync_rst : out STD_LOGIC;
ui_clk : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
mmcm_locked : out STD_LOGIC;
sys_clk_i : in STD_LOGIC;
init_calib_complete : out STD_LOGIC;
aresetn : in STD_LOGIC
);
end component bd_mig_7series_0_0;
component bd_proc_sys_reset_0_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component bd_proc_sys_reset_0_0;
component bd_proc_sys_reset_1_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component bd_proc_sys_reset_1_0;
component bd_clk_wiz_0_0 is
port (
resetn : in STD_LOGIC;
clk_in1 : in STD_LOGIC;
clk_ref_i : out STD_LOGIC;
aclk : out STD_LOGIC;
sys_clk_i : out STD_LOGIC
);
end component bd_clk_wiz_0_0;
signal S00_AXI_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal S00_AXI_1_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_AXI_1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARREADY : STD_LOGIC;
signal S00_AXI_1_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_ARVALID : STD_LOGIC;
signal S00_AXI_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal S00_AXI_1_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_AXI_1_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWREADY : STD_LOGIC;
signal S00_AXI_1_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_AWVALID : STD_LOGIC;
signal S00_AXI_1_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_BREADY : STD_LOGIC;
signal S00_AXI_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_BVALID : STD_LOGIC;
signal S00_AXI_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_RLAST : STD_LOGIC;
signal S00_AXI_1_RREADY : STD_LOGIC;
signal S00_AXI_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_RVALID : STD_LOGIC;
signal S00_AXI_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_WLAST : STD_LOGIC;
signal S00_AXI_1_WREADY : STD_LOGIC;
signal S00_AXI_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_WVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_interconnect_0_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_interconnect_0_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_RLAST : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_WLAST : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_WVALID : STD_LOGIC;
signal clk_wiz_0_clk_ref_i : STD_LOGIC;
signal clk_wiz_0_sys_clk_i : STD_LOGIC;
signal mig_7series_0_DDR2_ADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal mig_7series_0_DDR2_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal mig_7series_0_DDR2_CAS_N : STD_LOGIC;
signal mig_7series_0_DDR2_CKE : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR2_CK_N : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR2_CK_P : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR2_CS_N : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR2_DM : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mig_7series_0_DDR2_DQ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal mig_7series_0_DDR2_DQS_N : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mig_7series_0_DDR2_DQS_P : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mig_7series_0_DDR2_ODT : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR2_RAS_N : STD_LOGIC;
signal mig_7series_0_DDR2_WE_N : STD_LOGIC;
signal mig_7series_0_mmcm_locked : STD_LOGIC;
signal mig_7series_0_ui_addn_clk_0 : STD_LOGIC;
signal mig_7series_0_ui_clk : STD_LOGIC;
signal mig_7series_0_ui_clk_sync_rst : STD_LOGIC;
signal proc_sys_reset_0_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal proc_sys_reset_0_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal proc_sys_reset_1_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal sys_clk_i_1 : STD_LOGIC;
signal sys_rst_1 : STD_LOGIC;
signal NLW_mig_7series_0_init_calib_complete_UNCONNECTED : STD_LOGIC;
signal NLW_proc_sys_reset_0_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_proc_sys_reset_0_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_1_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_proc_sys_reset_1_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_1_interconnect_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_1_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
DDR2_addr(12 downto 0) <= mig_7series_0_DDR2_ADDR(12 downto 0);
DDR2_ba(2 downto 0) <= mig_7series_0_DDR2_BA(2 downto 0);
DDR2_cas_n <= mig_7series_0_DDR2_CAS_N;
DDR2_ck_n(0) <= mig_7series_0_DDR2_CK_N(0);
DDR2_ck_p(0) <= mig_7series_0_DDR2_CK_P(0);
DDR2_cke(0) <= mig_7series_0_DDR2_CKE(0);
DDR2_cs_n(0) <= mig_7series_0_DDR2_CS_N(0);
DDR2_dm(1 downto 0) <= mig_7series_0_DDR2_DM(1 downto 0);
DDR2_odt(0) <= mig_7series_0_DDR2_ODT(0);
DDR2_ras_n <= mig_7series_0_DDR2_RAS_N;
DDR2_we_n <= mig_7series_0_DDR2_WE_N;
S00_AXI_1_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
S00_AXI_1_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
S00_AXI_1_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
S00_AXI_1_ARID(3 downto 0) <= S00_AXI_arid(3 downto 0);
S00_AXI_1_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
S00_AXI_1_ARLOCK(0) <= S00_AXI_arlock(0);
S00_AXI_1_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
S00_AXI_1_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
S00_AXI_1_ARREGION(3 downto 0) <= S00_AXI_arregion(3 downto 0);
S00_AXI_1_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
S00_AXI_1_ARVALID <= S00_AXI_arvalid;
S00_AXI_1_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
S00_AXI_1_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
S00_AXI_1_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
S00_AXI_1_AWID(3 downto 0) <= S00_AXI_awid(3 downto 0);
S00_AXI_1_AWLEN(7 downto 0) <= S00_AXI_awlen(7 downto 0);
S00_AXI_1_AWLOCK(0) <= S00_AXI_awlock(0);
S00_AXI_1_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
S00_AXI_1_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
S00_AXI_1_AWREGION(3 downto 0) <= S00_AXI_awregion(3 downto 0);
S00_AXI_1_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
S00_AXI_1_AWVALID <= S00_AXI_awvalid;
S00_AXI_1_BREADY <= S00_AXI_bready;
S00_AXI_1_RREADY <= S00_AXI_rready;
S00_AXI_1_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
S00_AXI_1_WLAST <= S00_AXI_wlast;
S00_AXI_1_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
S00_AXI_1_WVALID <= S00_AXI_wvalid;
S00_AXI_arready <= S00_AXI_1_ARREADY;
S00_AXI_awready <= S00_AXI_1_AWREADY;
S00_AXI_bid(3 downto 0) <= S00_AXI_1_BID(3 downto 0);
S00_AXI_bresp(1 downto 0) <= S00_AXI_1_BRESP(1 downto 0);
S00_AXI_bvalid <= S00_AXI_1_BVALID;
S00_AXI_rdata(31 downto 0) <= S00_AXI_1_RDATA(31 downto 0);
S00_AXI_rid(3 downto 0) <= S00_AXI_1_RID(3 downto 0);
S00_AXI_rlast <= S00_AXI_1_RLAST;
S00_AXI_rresp(1 downto 0) <= S00_AXI_1_RRESP(1 downto 0);
S00_AXI_rvalid <= S00_AXI_1_RVALID;
S00_AXI_wready <= S00_AXI_1_WREADY;
aclk <= mig_7series_0_ui_addn_clk_0;
interconnect_aresetn(0) <= proc_sys_reset_0_interconnect_aresetn(0);
peripheral_aresetn(0) <= proc_sys_reset_0_peripheral_aresetn(0);
sys_clk_i_1 <= sys_clk_i;
sys_rst_1 <= sys_rst;
axi_interconnect_0: entity work.bd_axi_interconnect_0_0
port map (
ACLK => mig_7series_0_ui_addn_clk_0,
ARESETN => proc_sys_reset_0_interconnect_aresetn(0),
M00_ACLK => mig_7series_0_ui_clk,
M00_ARESETN => proc_sys_reset_1_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arburst(1 downto 0) => axi_interconnect_0_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_interconnect_0_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arid(3 downto 0) => axi_interconnect_0_M00_AXI_ARID(3 downto 0),
M00_AXI_arlen(7 downto 0) => axi_interconnect_0_M00_AXI_ARLEN(7 downto 0),
M00_AXI_arlock(0) => axi_interconnect_0_M00_AXI_ARLOCK(0),
M00_AXI_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => axi_interconnect_0_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => axi_interconnect_0_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_interconnect_0_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awburst(1 downto 0) => axi_interconnect_0_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => axi_interconnect_0_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awid(3 downto 0) => axi_interconnect_0_M00_AXI_AWID(3 downto 0),
M00_AXI_awlen(7 downto 0) => axi_interconnect_0_M00_AXI_AWLEN(7 downto 0),
M00_AXI_awlock(0) => axi_interconnect_0_M00_AXI_AWLOCK(0),
M00_AXI_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awqos(3 downto 0) => axi_interconnect_0_M00_AXI_AWQOS(3 downto 0),
M00_AXI_awready => axi_interconnect_0_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => axi_interconnect_0_M00_AXI_AWSIZE(2 downto 0),
M00_AXI_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
M00_AXI_bid(3 downto 0) => axi_interconnect_0_M00_AXI_BID(3 downto 0),
M00_AXI_bready => axi_interconnect_0_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_interconnect_0_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
M00_AXI_rid(3 downto 0) => axi_interconnect_0_M00_AXI_RID(3 downto 0),
M00_AXI_rlast => axi_interconnect_0_M00_AXI_RLAST,
M00_AXI_rready => axi_interconnect_0_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_interconnect_0_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
M00_AXI_wlast => axi_interconnect_0_M00_AXI_WLAST,
M00_AXI_wready => axi_interconnect_0_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => axi_interconnect_0_M00_AXI_WVALID,
S00_ACLK => mig_7series_0_ui_addn_clk_0,
S00_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => S00_AXI_1_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => S00_AXI_1_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => S00_AXI_1_ARCACHE(3 downto 0),
S00_AXI_arid(3 downto 0) => S00_AXI_1_ARID(3 downto 0),
S00_AXI_arlen(7 downto 0) => S00_AXI_1_ARLEN(7 downto 0),
S00_AXI_arlock(0) => S00_AXI_1_ARLOCK(0),
S00_AXI_arprot(2 downto 0) => S00_AXI_1_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => S00_AXI_1_ARQOS(3 downto 0),
S00_AXI_arready => S00_AXI_1_ARREADY,
S00_AXI_arregion(3 downto 0) => S00_AXI_1_ARREGION(3 downto 0),
S00_AXI_arsize(2 downto 0) => S00_AXI_1_ARSIZE(2 downto 0),
S00_AXI_arvalid => S00_AXI_1_ARVALID,
S00_AXI_awaddr(31 downto 0) => S00_AXI_1_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => S00_AXI_1_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => S00_AXI_1_AWCACHE(3 downto 0),
S00_AXI_awid(3 downto 0) => S00_AXI_1_AWID(3 downto 0),
S00_AXI_awlen(7 downto 0) => S00_AXI_1_AWLEN(7 downto 0),
S00_AXI_awlock(0) => S00_AXI_1_AWLOCK(0),
S00_AXI_awprot(2 downto 0) => S00_AXI_1_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => S00_AXI_1_AWQOS(3 downto 0),
S00_AXI_awready => S00_AXI_1_AWREADY,
S00_AXI_awregion(3 downto 0) => S00_AXI_1_AWREGION(3 downto 0),
S00_AXI_awsize(2 downto 0) => S00_AXI_1_AWSIZE(2 downto 0),
S00_AXI_awvalid => S00_AXI_1_AWVALID,
S00_AXI_bid(3 downto 0) => S00_AXI_1_BID(3 downto 0),
S00_AXI_bready => S00_AXI_1_BREADY,
S00_AXI_bresp(1 downto 0) => S00_AXI_1_BRESP(1 downto 0),
S00_AXI_bvalid => S00_AXI_1_BVALID,
S00_AXI_rdata(31 downto 0) => S00_AXI_1_RDATA(31 downto 0),
S00_AXI_rid(3 downto 0) => S00_AXI_1_RID(3 downto 0),
S00_AXI_rlast => S00_AXI_1_RLAST,
S00_AXI_rready => S00_AXI_1_RREADY,
S00_AXI_rresp(1 downto 0) => S00_AXI_1_RRESP(1 downto 0),
S00_AXI_rvalid => S00_AXI_1_RVALID,
S00_AXI_wdata(31 downto 0) => S00_AXI_1_WDATA(31 downto 0),
S00_AXI_wlast => S00_AXI_1_WLAST,
S00_AXI_wready => S00_AXI_1_WREADY,
S00_AXI_wstrb(3 downto 0) => S00_AXI_1_WSTRB(3 downto 0),
S00_AXI_wvalid => S00_AXI_1_WVALID
);
clk_wiz_0: component bd_clk_wiz_0_0
port map (
aclk => mig_7series_0_ui_addn_clk_0,
clk_in1 => sys_clk_i_1,
clk_ref_i => clk_wiz_0_clk_ref_i,
resetn => sys_rst_1,
sys_clk_i => clk_wiz_0_sys_clk_i
);
mig_7series_0: component bd_mig_7series_0_0
port map (
aresetn => proc_sys_reset_1_peripheral_aresetn(0),
clk_ref_i => clk_wiz_0_clk_ref_i,
ddr2_addr(12 downto 0) => mig_7series_0_DDR2_ADDR(12 downto 0),
ddr2_ba(2 downto 0) => mig_7series_0_DDR2_BA(2 downto 0),
ddr2_cas_n => mig_7series_0_DDR2_CAS_N,
ddr2_ck_n(0) => mig_7series_0_DDR2_CK_N(0),
ddr2_ck_p(0) => mig_7series_0_DDR2_CK_P(0),
ddr2_cke(0) => mig_7series_0_DDR2_CKE(0),
ddr2_cs_n(0) => mig_7series_0_DDR2_CS_N(0),
ddr2_dm(1 downto 0) => mig_7series_0_DDR2_DM(1 downto 0),
ddr2_dq(15 downto 0) => DDR2_dq(15 downto 0),
ddr2_dqs_n(1 downto 0) => DDR2_dqs_n(1 downto 0),
ddr2_dqs_p(1 downto 0) => DDR2_dqs_p(1 downto 0),
ddr2_odt(0) => mig_7series_0_DDR2_ODT(0),
ddr2_ras_n => mig_7series_0_DDR2_RAS_N,
ddr2_we_n => mig_7series_0_DDR2_WE_N,
init_calib_complete => NLW_mig_7series_0_init_calib_complete_UNCONNECTED,
mmcm_locked => mig_7series_0_mmcm_locked,
s_axi_araddr(31 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => axi_interconnect_0_M00_AXI_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => axi_interconnect_0_M00_AXI_ARCACHE(3 downto 0),
s_axi_arid(3 downto 0) => axi_interconnect_0_M00_AXI_ARID(3 downto 0),
s_axi_arlen(7 downto 0) => axi_interconnect_0_M00_AXI_ARLEN(7 downto 0),
s_axi_arlock => axi_interconnect_0_M00_AXI_ARLOCK(0),
s_axi_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => axi_interconnect_0_M00_AXI_ARQOS(3 downto 0),
s_axi_arready => axi_interconnect_0_M00_AXI_ARREADY,
s_axi_arsize(2 downto 0) => axi_interconnect_0_M00_AXI_ARSIZE(2 downto 0),
s_axi_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
s_axi_awaddr(31 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => axi_interconnect_0_M00_AXI_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => axi_interconnect_0_M00_AXI_AWCACHE(3 downto 0),
s_axi_awid(3 downto 0) => axi_interconnect_0_M00_AXI_AWID(3 downto 0),
s_axi_awlen(7 downto 0) => axi_interconnect_0_M00_AXI_AWLEN(7 downto 0),
s_axi_awlock => axi_interconnect_0_M00_AXI_AWLOCK(0),
s_axi_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => axi_interconnect_0_M00_AXI_AWQOS(3 downto 0),
s_axi_awready => axi_interconnect_0_M00_AXI_AWREADY,
s_axi_awsize(2 downto 0) => axi_interconnect_0_M00_AXI_AWSIZE(2 downto 0),
s_axi_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
s_axi_bid(3 downto 0) => axi_interconnect_0_M00_AXI_BID(3 downto 0),
s_axi_bready => axi_interconnect_0_M00_AXI_BREADY,
s_axi_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => axi_interconnect_0_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
s_axi_rid(3 downto 0) => axi_interconnect_0_M00_AXI_RID(3 downto 0),
s_axi_rlast => axi_interconnect_0_M00_AXI_RLAST,
s_axi_rready => axi_interconnect_0_M00_AXI_RREADY,
s_axi_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => axi_interconnect_0_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
s_axi_wlast => axi_interconnect_0_M00_AXI_WLAST,
s_axi_wready => axi_interconnect_0_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => axi_interconnect_0_M00_AXI_WVALID,
sys_clk_i => clk_wiz_0_sys_clk_i,
sys_rst => sys_rst_1,
ui_clk => mig_7series_0_ui_clk,
ui_clk_sync_rst => mig_7series_0_ui_clk_sync_rst
);
proc_sys_reset_0: component bd_proc_sys_reset_0_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_proc_sys_reset_0_bus_struct_reset_UNCONNECTED(0),
dcm_locked => mig_7series_0_mmcm_locked,
ext_reset_in => mig_7series_0_ui_clk_sync_rst,
interconnect_aresetn(0) => proc_sys_reset_0_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_proc_sys_reset_0_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => proc_sys_reset_0_peripheral_aresetn(0),
peripheral_reset(0) => NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => mig_7series_0_ui_addn_clk_0
);
proc_sys_reset_1: component bd_proc_sys_reset_1_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_proc_sys_reset_1_bus_struct_reset_UNCONNECTED(0),
dcm_locked => mig_7series_0_mmcm_locked,
ext_reset_in => mig_7series_0_ui_clk_sync_rst,
interconnect_aresetn(0) => NLW_proc_sys_reset_1_interconnect_aresetn_UNCONNECTED(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_proc_sys_reset_1_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => proc_sys_reset_1_peripheral_aresetn(0),
peripheral_reset(0) => NLW_proc_sys_reset_1_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => mig_7series_0_ui_clk
);
end STRUCTURE;
|
mit
|
8b511ae784237303ab408765756084fc
| 0.669781 | 2.805922 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/SRAM_Controller/Testbenches/SRAM_Controller_Tester.vhd
| 1 | 16,863 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Tests the SRAM controller.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SRAM_Controller_Tester is
end entity;
architecture stdarch of SRAM_Controller_Tester is
--------------------
-- Constants
--------------------
constant clk_period: time := 10ns; -- 100MHz
constant num_of_total_wait_states: natural := 9; -- 90ns @ 100MHz (min 70ns)
constant num_of_write_pulse_wait_states: natural := 6; -- 60ns @ 100MHz (min 50ns)
constant num_of_wait_states_before_write_after_read: natural := 4; -- 40ns @ 100MHz (min 30ns)
constant data_width: natural := 8;
constant address_width: natural := 16;
constant start_address: natural := 16#40#;
constant num_of_test_cycles: natural := 5;
constant end_address: natural := start_address + num_of_test_cycles - 1;
constant address_to_data_offset: natural := 16#10#;
constant ram_access_time: time := 70ns;
constant ram_output_disable_time: time := 30ns;
constant end_address_for_automatic_increment: natural := end_address - 2;
constant use_automatic_address_increment: boolean := false;
-- This configures the test bench whether it tests in single operation or
-- burst mode.
-- In single operation mode, we activate the read or write signal just for
-- one clock cycle. The according operation is completed anyway. In burst
-- mode, we keep the read or write signal active all the time, thus reading
-- or writing continuously.
-- Burst mode cannot be used when synchronizing the ready signal to the clock
-- (see below).
constant burst_mode: boolean := false;
-- This configures the test bench whether it uses the ready signal asynchronously
-- or syncs it to the clock.
-- When used asynchronously, the next address and input data are applied
-- immediately and thus are available to the SRAM controller on the next clock
-- cycle.
-- When synchronized to the clock, the next address and input data are applied
-- with a latency of one clock cycle. This is one clock cycle too late for burst
-- mode (see above).
constant sync_ready_to_clk: boolean := false;
--------------------
-- Inputs
--------------------
signal clk: std_logic := '0';
signal read: std_logic;
signal write: std_logic;
signal auto_increment_address: std_logic;
signal address: unsigned(address_width-1 downto 0);
signal data_in: std_logic_vector(data_width-1 downto 0);
--------------------
-- Outputs
--------------------
signal ready: std_logic;
signal auto_increment_end_address_reached: std_logic;
signal data_out: std_logic_vector(data_width-1 downto 0);
signal ram_we_n: std_logic;
signal ram_oe_n: std_logic;
signal ram_address: unsigned(address_width-1 downto 0);
--------------------
-- Bidirectional
--------------------
signal ram_data: std_logic_vector(data_width-1 downto 0);
--------------------
-- Internals
--------------------
signal run_test: boolean := true;
begin
--------------------------------------------------------------------------------
-- UUT instantiation.
--------------------------------------------------------------------------------
uut: entity work.SRAM_Controller
generic map
(
num_of_total_wait_states => num_of_total_wait_states,
num_of_write_pulse_wait_states => num_of_write_pulse_wait_states,
num_of_wait_states_before_write_after_read => num_of_wait_states_before_write_after_read,
data_width => data_width,
address_width => address_width
)
port map
(
clk => clk,
read => read,
write => write,
ready => ready,
auto_increment_address => auto_increment_address,
auto_increment_end_address_reached => auto_increment_end_address_reached,
address => address,
data_in => data_in,
data_out => data_out,
ram_we_n => ram_we_n,
ram_oe_n => ram_oe_n,
ram_address => ram_address,
ram_data => ram_data
);
--------------------------------------------------------------------------------
-- UUT stimulation.
-------------------------------------------------------------------------
-- Reads from and writes to the SRAM, either in non-burst or burst mode.
-- For non-burst mode, the read or write signal is active for just the
-- first clock cycle of the read or write cycle (this is the minimum,
-- longer durations are allowed).
-- For burst mode, the read or write signal is active until the entire
-- batch of data is transferred.
--------------------------------------------------------------------------------
-- Generates the system clock.
clk <= not clk after clk_period/2 when run_test;
-- Stimulates and controls the UUT and the tests at all.
stimulus: process is
begin
-- Wait a little for better waveform view.
wait until rising_edge(clk);
-- Set the end address for automatic address increment.
address <= to_unsigned(end_address_for_automatic_increment, address_width);
write <= '1';
read <= '1';
wait until rising_edge(clk);
write <= '0';
read <= '0';
wait until rising_edge(clk);
-- Read from the SRAM several times.
write <= '0';
auto_increment_address <= '0';
for adr in start_address to end_address loop
if (not use_automatic_address_increment or adr = start_address) then
-- We do not use automatic address increment or we are in its first cycle, just
-- memorize the current address (start address for automatic address increment).
address <= to_unsigned(adr, address_width);
else
-- We use automatic address increment and we are not in its first cycle, make
-- the controller automatically increment the address shown to the SRAM.
auto_increment_address <= '1';
end if;
read <= '1';
if (not burst_mode) then
wait for clk_period;
read <= '0';
wait on clk,ready until ready = '1';
else
wait for num_of_total_wait_states * clk_period;
end if;
if (sync_ready_to_clk) then
wait until rising_edge(clk);
end if;
end loop;
-- Deactivate SRAM access.
write <= '0';
read <= '0';
-- Write to the SRAM several times.
read <= '0';
auto_increment_address <= '0';
for adr in start_address to end_address loop
data_in <= std_logic_vector(to_unsigned(adr + address_to_data_offset, data_width));
if (not use_automatic_address_increment or adr = start_address) then
-- We do not use automatic address increment or we are in its first cycle, just
-- memorize the current address (start address for automatic address increment).
address <= to_unsigned(adr, address_width);
else
-- We use automatic address increment and we are not in its first cycle, make
-- the controller automatically increment the address shown to the SRAM.
auto_increment_address <= '1';
end if;
write <= '1';
if (not burst_mode) then
wait for clk_period;
write <= '0';
wait on clk,ready until ready = '1';
else
wait for num_of_total_wait_states * clk_period;
end if;
wait on clk,ready until ready = '1';
if (sync_ready_to_clk) then
wait until rising_edge(clk);
end if;
end loop;
-- Deactivate SRAM access.
write <= '0';
read <= '0';
wait for 5 * clk_period; -- wait a little to finish
-- Stop the tests.
run_test <= false;
wait;
end process;
-- Simulates the external SRAM (worst timing conditions).
sram: process is
begin
wait on ram_we_n, ram_oe_n, ram_address;
if (ram_we_n = '1' and ram_oe_n = '0') then
ram_data <= inertial std_logic_vector(ram_address(data_width-1 downto 0) + address_to_data_offset)
after ram_access_time;
else
ram_data <= inertial (others => 'Z') after ram_output_disable_time;
end if;
end process;
--------------------------------------------------------------------------------
-- Specifications.
--------------------------------------------------------------------------------
-- Verifies proper RAM signal generation and overall timing.
must_create_correct_signals: process is
variable expected_address: unsigned(address_width-1 downto 0);
variable expected_data: unsigned(data_width-1 downto 0);
variable effective_start_address: natural;
begin
-- Synchronize with the stimulus.
wait until falling_edge(clk);
wait until falling_edge(clk);
-- Verify that the SRAM is deactivated completely at the beginning.
assert (ram_we_n = '1') report "SRAM WE signal is not initially inactive." severity error;
assert (ram_oe_n = '1') report "SRAM OE signal is not initially inactive." severity error;
-- For each read access to the SRAM.
effective_start_address := start_address;
for adr in effective_start_address to end_address loop
-- Wait until the current read cycle starts.
if read /= '1' then
wait until read = '1';
wait until rising_edge(clk);
end if;
-- Verify that the SRAM controller generates the correct signals for the entire read cycle.
for wait_state in 0 to num_of_total_wait_states - 1 loop
-- Verify that the SRAM gets the correct address and signals during a read cycle.
wait until falling_edge(clk);
assert (ram_we_n = '1') report "SRAM WE signal is not inactive during a read cycle." severity error;
assert (ram_oe_n = '0') report "SRAM OE signal is not active during a read cycle." severity error;
if (use_automatic_address_increment and adr > end_address_for_automatic_increment) then
expected_address := to_unsigned(end_address_for_automatic_increment, address_width);
else
expected_address := to_unsigned(adr, address_width);
end if;
assert (ram_address = expected_address)
report "SRAM address is wrong during a read cycle, expected " & integer'image(to_integer(expected_address)) & "."
severity error;
-- Verify that the ready signal is active exactly at the end of the read cycle and that the data
-- are available then.
if (wait_state < num_of_total_wait_states - 1) then
assert (ready = '0') report "The ready signal is not inactive during a read cycle." severity error;
else
assert (ready = '1') report "The ready signal is not active at the end of a read cycle." severity error;
assert (data_out = ram_data) report "The data are not available at the end of a read cycle." severity error;
end if;
end loop;
end loop;
-- Verify that the SRAM is deactivated completely after the read.
wait for clk_period;
assert (ram_we_n = '1') report "SRAM WE signal is not inactive after the read." severity error;
assert (ram_oe_n = '1') report "SRAM OE signal is not inactive after the read." severity error;
report "Read has finished" severity note;
-- TODO: Consider syncing on ready signal instead of write signal. This would avoid the
-- time-based delay workaround for burst mode below. Also change the same above for reading.
if (burst_mode) then
effective_start_address := start_address;
wait for num_of_wait_states_before_write_after_read * clk_period;
else
-- For each write access to the SRAM except the first one.
-- The first cycle is skipped here because we have missed the according write signal edge.
effective_start_address := start_address + 1;
end if;
for adr in effective_start_address to end_address loop
-- Wait until the current write cycle starts.
if write /= '1' then
wait until write = '1';
wait until rising_edge(clk);
end if;
-- Verify that the SRAM controller generates the correct signals for the entire write cycle.
for wait_state in 0 to num_of_total_wait_states - 1 loop
-- Verify that the SRAM gets the correct address, data and signals during a write cycle.
wait until falling_edge(clk);
if (wait_state < num_of_total_wait_states - 1 - num_of_write_pulse_wait_states
or wait_state = num_of_total_wait_states - 1) then
assert (ram_we_n = '1') report "SRAM WE signal is not inactive while preparing a write cycle." severity error;
else
assert (ram_we_n = '0') report "SRAM WE signal is not active while executing a write cycle." severity error;
end if;
assert (ram_oe_n = '1') report "SRAM OE signal is not inactive during a write cycle." severity error;
if (use_automatic_address_increment and adr > end_address_for_automatic_increment) then
expected_address := to_unsigned(end_address_for_automatic_increment, address_width);
else
expected_address := to_unsigned(adr, address_width);
end if;
assert (ram_address = expected_address)
report "SRAM address is wrong during a write cycle, expected " & integer'image(to_integer(expected_address)) & "."
severity error;
expected_data := to_unsigned(adr + address_to_data_offset, data_width);
assert (ram_data = std_logic_vector(expected_data))
report "SRAM data is wrong during a write cycle, expected " & integer'image(to_integer(expected_data)) & "."
severity error;
-- Verify that the ready signal is active exactly at the end of the write cycle.
if (wait_state < num_of_total_wait_states - 1) then
assert (ready = '0') report "The ready signal is not inactive during a write cycle." severity error;
else
assert (ready = '1') report "The ready signal is not active at the end of a write cycle." severity error;
end if;
end loop;
end loop;
-- Verify that the SRAM is decativated completely after the write.
assert (ram_we_n = '1') report "SRAM WE signal is not inactive after the write." severity error;
assert (ram_oe_n = '1') report "SRAM OE signal is not inactive after the write." severity error;
report "Write has finished" severity note;
wait;
end process;
end architecture;
|
gpl-3.0
|
1fb1ed34e5ef7f720d1f0bf7b860c8ce
| 0.557374 | 4.681566 | false | false | false | false |
arthurTemporim/SD_SS
|
pre/3/projetos/complemento1/overflow.vhd
| 1 | 687 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;
entity overflow is
Port ( entrada1 : in STD_LOGIC_VECTOR (2 downto 0);
entrada2 : in STD_LOGIC_VECTOR (2 downto 0);
sel : in STD_LOGIC;
saida : out STD_LOGIC_VECTOR (2 downto 0);
cout : out STD_LOGIC);
end overflow;
architecture Behavioral of overflow is
--signal aux : STD_LOGIC_VECTOR (2 downto 0);
begin
process (entrada1, entrada2, sel)
begin
case sel is
when '0' =>
saida <= entrada1 + entrada2;
when '1' =>
--saida <= entrada1 - entrada2;
when others =>
saida <= "000";
end case;
end process;
end Behavioral;
|
mit
|
1210ba01271522eb967b27222b8475d3
| 0.647744 | 3.136986 | false | false | false | false |
SalvatoreBarone/Zynq7000DriverPack
|
Src/myGPIO/VHDL/myGPIO.vhd
| 1 | 11,717 |
--! @file myGPIO.vhd
--! @author Salvatore Barone <[email protected]>
--! @date 22 06 2017
--!
--! @copyright
--! Copyright 2017 Salvatore Barone <[email protected]>
--!
--! This file is part of Zynq7000DriverPack
--!
--! Zynq7000DriverPack is free software; you can redistribute it and/or modify it under the terms of
--! the GNU General Public License as published by the Free Software Foundation; either version 3 of
--! the License, or any later version.
--!
--! Zynq7000DriverPack is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
--! without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--! GNU General Public License for more details.
--!
--! You should have received a copy of the GNU General Public License along with this program; if not,
--! write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
--! USA.
--!
--! @addtogroup myGPIO
--! @{
--! @addtogroup AXI-device
--! @{
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! @mainpage
--! @brief Periferica AXI4 Lite che implementa una GPIO pilotabile da processing-system.
--!
--! @details
--!
--! <h4>Registri interni del device</h4>
--! Il device possiede i registri indicati di seguito. Per oognuno di essi viene indicata la modalità di
--! accesso (R sola lettura, W sola scrittura, R/W lettura scrittura), e l'offset, rispetto all'indirizzo
--! base del device, col quale è possibile indirizzarli.
--!
--! - MODE (R/W, offset +0x0): consente di impostare i singoli pin del device come ingressi o uscite; solo i
--! GPIO_width bit meno significativi del registro hanno significato, agire sui restanti bit non produce
--! nessun effetto; Il valore che i singoli pin possono
--! assumere è:
--! - '1': il pin viene configurato come pin di uscita;
--! - 'ò: il pin viene configurato come pin di ingresso;
--! .
--! - WRITE (R/W, offset +0x4): consente di imporre un valore ai pin del device, qualora essi siano configurati
--! come uscite; solo i GPIO_width bit meno significativi del hanno significato, agire sui restanti bit non produce
--! nessun effetto;
--! - READ (R, offset +0x8): consente di leggere il valore dei pin del device, sia quelli configurati come
--! ingressi che quelli configurati come uscite (il cui valore coincide con quello settato nel registro
--! WRITE); solo i GPIO_width bit meno significativi del registro hanno significato, gli altri vengono letti
--! zero;
--! - GIES (Global Interrupt Enable/Status, R/W, offset 0xC): Consente di abilitare/disabilitare gli interrupt
--! globali della periferica; solo due dei bit sono significativi:
--! - IE (bit 0): interrupt enable, abilita gli interrupt, può essere scritto e letto; se posto ad '1'
--! la periferica potrà generare interrupt quando uno dei pin impostati come ingresso assume
--! valore '1' (ed il corrispondente bit in PIE è impostato ad '1'); se posto a '0' il device
--! non genererà mai interruzioni;
--! - IS (bit 1): interrupt status, settato internamente ad '1' nel caso in cui la periferica abbia
--! generato interrupt; replica del segnale "interrupt" diretto verso il processing-system.
--! - PIE (Pin Interrupt Enable, R/W, offset 0x10): consente di abilitare/disabilitare gli interrupt per i
--! singoli pin. Con GIES(0)='1' e MODE(n)='0' (cioè se gli interrupt globali sono abilitati e il pin
--! n-esimo è configurato come input), se PIE(n)='1' allora il device genererà un interrupt verso il
--! processing-system quando il pin n-esimo assumerà valore '1', mentre, se PIE(n)='0' non verrà
--! generata una interruzione;
--! - IRQ (Interrupt Request, R, offset 0x14): IRQ(n)='1' indica che la sorgente di interruzione è il bit
--! n-esimo; la or-reduce di tale registro costituisce il segnale "interrupt" diretto verso il processing
--! system;
--! - IACK (Interrupt Ack, W, offset 0x18): imponento IACK(n)='1' è possibile segnalare al device che
--! l'interruzione generata dal in n-esimo è stata servita; il bit IRQ(n) verrà resettato automaticamente.
--!
--!
--! <h4>Process di scrittura dei registri della periferica</h4>
--! Il process che implementa la logica di scrittura dei registri è stato modificato in modo da ottenere
--! il seguente indirizzamento:
--! <table>
--! <tr><th>Indirizzo</th><th>Offset</th><th>Registro</th></tr>
--! <tr><td>b"00000"</td><td>0x00</td><td>MODE</td></tr>
--! <tr><td>b"00100"</td><td>0x04</td><td>WRITE</td></tr>
--! <tr><td>b"01000"</td><td>0x08</td><td>READ(*)</td></tr>
--! <tr><td>b"01100"</td><td>0x0C</td><td>GIES(**)</td></tr>
--! <tr><td>b"10000"</td><td>0x10</td><td>PIE</td></tr>
--! <tr><td>b"10100"</td><td>0x14</td><td>IRQ(***)</td></tr>
--! <tr><td>b"11000"</td><td>0x18</td><td>IACK(****)</td></tr>
--! </table>
--! (*) Il registro READ è a sola lettura: le scritture su questo registro non producono effetti;
--! la scrittura, infatti, avviene su slv_reg2, che è inutilizzato;<br>
--! (**) La scrittura ha effetto solo sul bit zero del registro;<br>
--! (***) Il registro IRQ è a sola lettura: le scritture su questo registro non producono effetti;
--! la scrittura, infatti, avviene su slv_reg5, che è inutilizzato;<br>
--! (****) La scrittura su IACK è fittizzia, nel senso che appena si smette di indirizzare il registro,
--! esso assume valore zero;<br>
--!
--!
--! <h4>Process di lettura dei registri della periferica</h4>
--! Il process che implementa la logica di lettura dei registri è stato modificato in modo da ottenere
--! il seguente indirizzamento:
--! <table>
--! <tr><th>Indirizzo</th><th>Offset</th><th>Registro</th></tr>
--! <tr><td>b"00000"</td><td>0x00</td><td>MODE</td></tr>
--! <tr><td>b"00100"</td><td>0x04</td><td>WRITE</td></tr>
--! <tr><td>b"01000"</td><td>0x08</td><td>READ(*)</td></tr>
--! <tr><td>b"01100"</td><td>0x0C</td><td>GIES(**)</td></tr>
--! <tr><td>b"10000"</td><td>0x10</td><td>PIE</td></tr>
--! <tr><td>b"10100"</td><td>0x14</td><td>IRQ</td></tr>
--! <tr><td>b"11000"</td><td>0x18</td><td>IACK(***)</td></tr>
--! </table>
--! (*) Il registro READ è direttamente connesso alla porta GPIO_inout<br>
--! (**) Il bit 2 di GIES è il flag "interrupt", che vale '1' nel caso in cui la periferica abbia generato
--! interrupt ancora non gestiti.<br>
--! (***) Viene letto sempre zero, dal momento che la scrittura su tale registro è fittizzia.
--!
--!
--! <h4>Process di scrittura su IRQ</h4>
--! La logica di scrittura su IRQ è semplice (non viene scritto come un normale registro, ma pilotato
--! internamente dalla periferica):
--! se uno dei bit di GPIO_inout_masked è '1', (la or-reduce è 1) allora il valore del segnale GPIO_inout_masked
--! viene posto in bitwise-or con il valore attuale del registro IRQ, in modo da non resettare i bit di quest'
--! ultimo che siano stati settati a seguito di una interruzione non ancora servita
--! se uno dei bit di IACK è '1' (la or-reduce è '1'), allora il nuovo valore del registro IRQ viene ottenuto
--! - mascherando IACK con l'attuale valore di IRQ, in modo da non effettuare il set di bit resettati
--! - ponendo in XOR la maschera precedente con il valore attuale del registro
entity myGPIO is
generic (
-- Users to add parameters here
GPIO_width : natural := 4; --! numero di GPIO offerti dalla periferica, di default pari a 4 celle.
-- User parameters ends
-- Do not modify the parameters beyond this line
--! @cond
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 5
--! @endcond
);
port (
-- Users to add ports here
GPIO_inout : inout std_logic_vector (GPIO_width-1 downto 0); --!
--! segnale bidirezionale diretto verso l'esterno del device.
interrupt : out std_logic; --!
--! segnale di interrupt a livelli diretto verso il processing - system. Se le interruzioni sono
--! abilitate ed uno dei pin del device è settato come input ed è abilitato a generare interruzioni,
--! diventa '1' appena tale pin assume valore '1', e mantiene tale valore fino a quando tutte le
--! interruzioni non siano state servite.
--! @cond
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
--! @endcond
);
end myGPIO;
--! @cond
architecture arch_imp of myGPIO is
-- component declaration
component myGPIO_AXI is
generic (
GPIO_width : natural := 4;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
GPIO_inout : inout std_logic_vector (GPIO_width-1 downto 0);
interrupt : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component myGPIO_AXI;
begin
myGPIO_AXI_inst : myGPIO_AXI
generic map (
GPIO_width => GPIO_width,
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
GPIO_inout => GPIO_inout,
interrupt => interrupt,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
--! @endcond
--! @}
--! @}
|
gpl-3.0
|
e5db724c75f0dd19366d7110b2c2f95b
| 0.682273 | 2.896133 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/SPI Interface/Testbenches/SPI_SlaveReceiverTester.vhd
| 1 | 6,552 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Tests the SPI slave receiver.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Globals.all;
use work.TestTools.all;
entity SPI_SlaveReceiver_Tester is
end entity;
architecture stdarch of SPI_SlaveReceiver_Tester is
-- Constants
constant test_delay: time := 1ps;
constant address_width: positive := 2;
constant number_of_data_outputs: positive := 2**address_width;
constant clk_period: time := 20ns; -- 50 MHz system clock
constant sclk_period: time := 91ns; -- about 11 MHz serial clock
-- Inputs
signal clk: std_logic := '0';
signal sclk: std_logic := '1';
signal ss_address: std_logic :='1';
signal ss_data: std_logic :='1';
signal mosi: std_logic := '0';
-- Outputs
signal address: unsigned(address_width-1 downto 0) := (others => '0');
signal data_x: data_buffer_vector(number_of_data_outputs-1 downto 0);
signal ready_x: std_logic_vector(number_of_data_outputs-1 downto 0);
-- Internals
signal run_test: boolean := true;
-------------------------------------------------------------------------
-- Create a test value unique for the current address.
-------------------------------------------------------------------------
function get_test_value(address: natural) return data_buffer
is
begin
return std_logic_vector(to_unsigned(16 + (address * 2), data_width));
end function;
-------------------------------------------------------------------------
-- Passes a test value to the receiver and verifies the data appearing
-- at the specified receiver buffer´s parallel output.
-------------------------------------------------------------------------
procedure receive_data_and_check_behaviour(output_address: natural)
is
variable previous_data: data_buffer;
begin
previous_data := data_x(output_address);
-- Send the output address.
ss_address <= '0';
serialize_byte(sclk_period, std_logic_vector(to_unsigned(output_address,8)), sclk, mosi);
ss_address <= '1';
-- Activate the buffer´s slave select (SS) signal and check whether
-- the output buffer´s ready signal is deactivated at the next
-- rising CLK edge.
ss_data <= '0';
wait until rising_edge(clk);
wait for test_delay;
assert (ready_x(output_address) = '0')
report "READY activated unexpectedly." severity error;
-- Serialize a test value to the receiver´s serial input.
serialize_longword(sclk_period, get_test_value(output_address), sclk, mosi);
-- Check whether the buffer still holds the previous value.
assert (data_x(output_address) = previous_data)
report "Previous data not correctly preserved." severity error;
-- Deactivate the buffer´s slave select (SS) signal and and check
-- whether the output buffer fetches the value at the next rising CLK
-- edge.
ss_data <= '1';
wait until rising_edge(clk);
wait for test_delay;
-- Check whether the buffer holds the new value.
assert (ready_x(output_address) = '1')
report "READY not activated." severity error;
assert (data_x(output_address) = get_test_value(output_address))
report "Data not correctly received." severity error;
end procedure;
begin
--------------------------------------------------------------------------------
-- Instantiate the UUT(s).
--------------------------------------------------------------------------------
uut: entity work.SPI_SlaveReceiver
generic map
(
address_width => address_width
)
port map
(
clk => clk,
buffer_enable => ss_data,
sclk => sclk,
ss_address => ss_address,
address => address,
mosi => mosi,
data_x => data_x,
ready_x => ready_x
);
--------------------------------------------------------------------------------
-- Generate the system clock.
--------------------------------------------------------------------------------
clk <= not clk after clk_period/2 when run_test;
--------------------------------------------------------------------------------
-- Stimulate the UUT.
--------------------------------------------------------------------------------
stimulus: process is
begin
-- Receive several values via different outputs and check whether they
-- arrive without changing unselected outputs.
for i in 0 to number_of_data_outputs-1 loop
wait for sclk_period; -- for a better readable timing diagram
receive_data_and_check_behaviour(i);
end loop;
wait for sclk_period; -- for a better readable timing diagram
-- Check whether all received data have been buffered and preserved correctly.
for i in 0 to number_of_data_outputs-1 loop
assert (data_x(i) = get_test_value(i))
report "Data for address(" & integer'image(i) &
") not correctly received and preserved."
severity error;
end loop;
run_test <= false;
wait;
end process;
end architecture;
|
gpl-3.0
|
8a97b03a197d5385ce143f2b77a41977
| 0.505647 | 5.063369 | false | true | false | false |
arthurbenemann/fpga-bits
|
undocumented/VGA1/ipcore_dir/clock_manager/example_design/clock_manager_exdes.vhd
| 1 | 5,436 |
-- file: clock_manager_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock_manager_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end clock_manager_exdes;
architecture xilinx of clock_manager_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counter
signal clk : std_logic;
signal clk_int : std_logic;
signal clk_n : std_logic;
signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0');
signal rst_sync : std_logic;
signal rst_sync_int : std_logic;
signal rst_sync_int1 : std_logic;
signal rst_sync_int2 : std_logic;
component clock_manager is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
pixel_clock : out std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= COUNTER_RESET;
process (clk, reset_int) begin
if (reset_int = '1') then
rst_sync <= '1';
rst_sync_int <= '1';
rst_sync_int1 <= '1';
rst_sync_int2 <= '1';
elsif (clk 'event and clk='1') then
rst_sync <= '0';
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end if;
end process;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : clock_manager
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
pixel_clock => clk_int);
clk_n <= not clk;
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(1),
C0 => clk,
C1 => clk_n,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
-- Connect the output clocks to the design
-------------------------------------------
clk <= clk_int;
-- Output clock sampling
-------------------------------------
process (clk, rst_sync_int2) begin
if (rst_sync_int2 = '1') then
counter <= (others => '0') after TCQ;
elsif (rising_edge(clk)) then
counter <= counter + 1 after TCQ;
end if;
end process;
-- alias the high bit to the output
COUNT <= counter(C_W-1);
end xilinx;
|
gpl-3.0
|
945ddc3d7c72f8d10fd9ec7cd660cd88
| 0.619389 | 4.090293 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/VGA1/ipcore_dir/h_timer.vhd
| 1 | 4,041 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file h_timer.vhd when simulating
-- the core, h_timer. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY h_timer IS
PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END h_timer;
ARCHITECTURE h_timer_a OF h_timer IS
-- synthesis translate_off
COMPONENT wrapped_h_timer
PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_h_timer USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral)
GENERIC MAP (
c_ainit_val => "0",
c_ce_overrides_sync => 0,
c_count_by => "1",
c_count_mode => 0,
c_count_to => "1100011111",
c_fb_latency => 0,
c_has_ce => 0,
c_has_load => 0,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_has_thresh0 => 0,
c_implementation => 0,
c_latency => 1,
c_load_low => 0,
c_restrict_count => 1,
c_sclr_overrides_sset => 1,
c_sinit_val => "0",
c_thresh0_value => "1",
c_verbosity => 0,
c_width => 10,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_h_timer
PORT MAP (
clk => clk,
q => q
);
-- synthesis translate_on
END h_timer_a;
|
gpl-3.0
|
9211cf3d09c558dabe610ae67c16e79e
| 0.532541 | 4.677083 | false | false | false | false |
maijohnson/comp3601_blue_15s2
|
AudioController/I2CMaster.vhdl
| 1 | 12,598 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY i2c_master IS
GENERIC(
input_clk : INTEGER := 100_000_000; --input clock speed from user logic in Hz
bus_clk : INTEGER := 100_000); --speed the i2c bus (scl) will run at in Hz
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
ena : IN STD_LOGIC; --latch in command
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
busy : OUT STD_LOGIC; --indicates transaction in progress
data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
sda : INOUT STD_LOGIC; --serial data output of i2c bus
scl : INOUT STD_LOGIC); --serial clock output of i2c bus
END i2c_master;
ARCHITECTURE logic OF i2c_master IS
CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
CONSTANT divider1_1 : INTEGER := divider*1 - 1;
CONSTANT divider2_1 : INTEGER := divider*2 - 1;
CONSTANT divider2 : INTEGER := divider*2;
CONSTANT divider3_1 : INTEGER := divider*3 - 1;
CONSTANT divider3 : INTEGER := divider*3;
CONSTANT divider4_1 : INTEGER := divider*4 - 1;
CONSTANT divider4 : INTEGER := divider*4;
TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
SIGNAL state : machine; --state machine
SIGNAL data_clk : STD_LOGIC; --clock edges for sda
SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
BEGIN
--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
PROCESS(clk, reset_n)
VARIABLE count : INTEGER RANGE 0 TO divider4; --timing for clock generation
BEGIN
IF(reset_n = '0') THEN --reset asserted
stretch <= '0';
count := 0;
ELSIF(clk'EVENT AND clk = '1') THEN
IF(count = divider4_1) THEN --end of timing cycle
count := 0; --reset timer
ELSIF(stretch = '0') THEN --clock stretching from slave not detected
count := count + 1; --continue clock generation timing
END IF;
CASE count IS
WHEN 0 TO divider1_1 => --first 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '0';
WHEN divider TO divider2_1 => --second 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '1';
WHEN divider2 TO divider3_1 => --third 1/4 cycle of clocking
scl_clk <= '1'; --release scl
IF(scl = '0') THEN --detect if slave is stretching clock
stretch <= '1';
ELSE
stretch <= '0';
END IF;
data_clk <= '1';
WHEN OTHERS => --last 1/4 cycle of clocking
scl_clk <= '1';
data_clk <= '0';
END CASE;
END IF;
END PROCESS;
--state machine and writing to sda during scl low (data_clk rising edge)
PROCESS(data_clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset asserted
state <= ready; --return to initial state
busy <= '1'; --indicate not available
scl_ena <= '0'; --sets scl high impedance
sda_int <= '1'; --sets sda high impedance
bit_cnt <= 7; --restarts data bit counter
data_rd <= "00000000"; --clear data read port
ELSIF(data_clk'EVENT AND data_clk = '1') THEN
CASE state IS
WHEN ready => --idle state
IF(ena = '1') THEN --transaction requested
busy <= '1'; --flag busy
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
state <= start; --go to start bit
ELSE --remain idle
busy <= '0'; --unflag busy
state <= ready; --remain idle
END IF;
WHEN start => --start bit of transaction
busy <= '1'; --resume busy if continuous mode
scl_ena <= '1'; --enable scl output
sda_int <= addr_rw(bit_cnt); --set first address bit to bus
state <= command; --go to command
WHEN command => --address and command byte of transaction
IF(bit_cnt = 0) THEN --command transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack1; --go to slave acknowledge (command)
ELSE --next clock cycle of command state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
state <= command; --continue with command
END IF;
WHEN slv_ack1 => --slave acknowledge bit (command)
IF(addr_rw(0) = '0') THEN --write command
sda_int <= data_tx(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --read command
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
END IF;
WHEN wr => --write byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --write byte transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack2; --go to slave acknowledge (write)
ELSE --next clock cycle of write state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= data_tx(bit_cnt-1); --write next bit to bus
state <= wr; --continue writing
END IF;
WHEN rd => --read byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --read byte receive finished
IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address
sda_int <= '0'; --acknowledge the byte has been received
ELSE --stopping or continuing with a write
sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
END IF;
bit_cnt <= 7; --reset bit counter for "byte" states
data_rd <= data_rx; --output received data
state <= mstr_ack; --go to master acknowledge
ELSE --next clock cycle of read state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
state <= rd; --continue reading
END IF;
WHEN slv_ack2 => --slave acknowledge bit (write)
IF(ena = '1') THEN --continue transaction
busy <= '0'; --continue is accepted
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another write
sda_int <= data_wr(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --continue transaction with a read or new slave
state <= start; --go to repeated start
END IF;
ELSE --complete transaction
scl_ena <= '0'; --disable scl
state <= stop; --go to stop bit
END IF;
WHEN mstr_ack => --master acknowledge bit after a read
IF(ena = '1') THEN --continue transaction
busy <= '0'; --continue is accepted and data received is available on bus
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another read
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
ELSE --continue transaction with a write or new slave
state <= start; --repeated start
END IF;
ELSE --complete transaction
scl_ena <= '0'; --disable scl
state <= stop; --go to stop bit
END IF;
WHEN stop => --stop bit of transaction
busy <= '0'; --unflag busy
state <= ready; --go to idle state
END CASE;
END IF;
--reading from sda during scl high (falling edge of data_clk)
IF(reset_n = '0') THEN --reset asserted
ack_error <= '0';
ELSIF(data_clk'EVENT AND data_clk = '0') THEN
CASE state IS
WHEN start =>
IF(scl_ena = '0') THEN --starting new transaction
ack_error <= '0'; --reset acknowledge error output
END IF;
WHEN slv_ack1 => --receiving slave acknowledge (command)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN rd => --receiving slave data
data_rx(bit_cnt) <= sda; --receive current slave data bit
WHEN slv_ack2 => --receiving slave acknowledge (write)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END PROCESS;
--set sda output
WITH state SELECT
sda_ena_n <= data_clk WHEN start, --generate start condition
NOT data_clk WHEN stop, --generate stop condition
sda_int WHEN OTHERS; --set to internal sda signal
--set scl and sda outputs
scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
END logic;
|
mit
|
34f55b19159a8b5551dc06a760c0f293
| 0.481505 | 4.515412 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/koc_wrapper.vhd
| 1 | 271,742 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.nexys4_pack.all;
use work.plasoc_interconnect_crossbar_wrap_pack.plasoc_interconnect_crossbar_wrap;
use work.plasoc_interconnect_crossbar_wrap_pack.clogb2;
use work.plasoc_cpu_0_crossbar_wrap_pack.plasoc_cpu_0_crossbar_wrap;
use work.plasoc_cpu_1_crossbar_wrap_pack.plasoc_cpu_1_crossbar_wrap;
use work.plasoc_cpu_2_crossbar_wrap_pack.plasoc_cpu_2_crossbar_wrap;
use work.plasoc_cpu_pack.plasoc_cpu;
use work.plasoc_int_pack.plasoc_int;
use work.plasoc_int_pack.default_interrupt_total;
use work.plasoc_timer_pack.plasoc_timer;
use work.plasoc_gpio_pack.plasoc_gpio;
use work.plasoc_uart_pack.plasoc_uart;
use work.plasoc_axi4_full2lite_pack.plasoc_axi4_full2lite;
use work.koc_lock_pack.koc_lock;
use work.koc_signal_pack.koc_signal;
entity koc_wrapper is
generic (
lower_app : string := "boot";
upper_app : string := "none";
upper_ext : boolean := true);
port (
sys_clk_i : in std_logic;
sys_rst : in std_logic;
gpio_output : out std_logic_vector(data_out_width-1 downto 0);
gpio_input : in std_logic_vector(data_in_width-1 downto 0);
uart_tx : out std_logic;
uart_rx : in std_logic;
DDR2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
DDR2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR2_cas_n : out STD_LOGIC;
DDR2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ras_n : out STD_LOGIC;
DDR2_we_n : out STD_LOGIC);
end koc_wrapper;
architecture Behavioral of koc_wrapper is
----------------------------
-- Component Declarations --
----------------------------
component bd_wrapper is
port (
DDR2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
DDR2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR2_cas_n : out STD_LOGIC;
DDR2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ras_n : out STD_LOGIC;
DDR2_we_n : out STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC;
aclk : out STD_LOGIC;
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
sys_clk_i : in STD_LOGIC;
sys_rst : in STD_LOGIC);
end component;
component bram is
generic (
select_app : string := "none"; -- jump, boot, main
address_width : integer := 18;
data_width : integer := 32;
bram_depth : integer := 65536);
port(
bram_rst_a : in std_logic;
bram_clk_a : in std_logic;
bram_en_a : in std_logic;
bram_we_a : in std_logic_vector(data_width/8-1 downto 0);
bram_addr_a : in std_logic_vector(address_width-1 downto 0);
bram_wrdata_a : in std_logic_vector(data_width-1 downto 0);
bram_rddata_a : out std_logic_vector(data_width-1 downto 0) := (others=>'0'));
end component;
component axi_bram_ctrl_0 IS
port (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
end component;
component clk_wiz_0
port (
aclk : out std_logic;
resetn : in std_logic;
locked : out std_logic;
sys_clk_i : in std_logic);
end component;
component proc_sys_reset_0 is
port (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0));
end component;
constant axi_cpu_bus_slave_amount : integer := 1;
constant axi_cpu_bus_slave_id_width : integer := 0;
constant axi_cpu_bus_master_id_width : integer := clogb2(axi_cpu_bus_slave_amount)+axi_cpu_bus_slave_id_width;
constant axi_slave_amount : integer := 3;
constant axi_slave_id_width : integer := axi_cpu_bus_master_id_width;
constant axi_master_id_width : integer := clogb2(axi_slave_amount)+axi_slave_id_width;
constant axi_address_width : integer := 32;
constant axi_address_periph_width : integer := 16;
constant axi_data_width : integer := 32;
constant bram_address_width : integer := 16;
constant bram_data_width : integer := axi_data_width;
constant bram_bram_depth : integer := 16384;
signal aclk : std_logic;
signal interconnect_aresetn : std_logic_vector(0 downto 0);
signal peripheral_aresetn : std_logic_vector(0 downto 0);
signal dcm_locked : std_logic;
signal ram_bram_rst_a : std_logic;
signal ram_bram_clk_a : std_logic;
signal ram_bram_en_a : std_logic;
signal ram_bram_we_a : std_logic_vector(3 downto 0);
signal ram_bram_addr_a : std_logic_vector(15 downto 0);
signal ram_bram_wrdata_a : std_logic_vector(31 downto 0);
signal ram_bram_rddata_a : std_logic_vector(31 downto 0);
signal boot_bram_rst_a : std_logic;
signal boot_bram_clk_a : std_logic;
signal boot_bram_en_a : std_logic;
signal boot_bram_we_a : std_logic_vector(3 downto 0);
signal boot_bram_addr_a : std_logic_vector(15 downto 0);
signal boot_bram_wrdata_a : std_logic_vector(31 downto 0);
signal boot_bram_rddata_a : std_logic_vector(31 downto 0);
-------------------------------
-- Main Interconnect Signals --
-------------------------------
signal cpu_0_axi_full_awid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_0_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_0_axi_full_awlen : std_logic_vector(7 downto 0);
signal cpu_0_axi_full_awsize : std_logic_vector(2 downto 0);
signal cpu_0_axi_full_awburst : std_logic_vector(1 downto 0);
signal cpu_0_axi_full_awlock : std_logic;
signal cpu_0_axi_full_awcache : std_logic_vector(3 downto 0);
signal cpu_0_axi_full_awprot : std_logic_vector(2 downto 0);
signal cpu_0_axi_full_awqos : std_logic_vector(3 downto 0);
signal cpu_0_axi_full_awregion : std_logic_vector(3 downto 0);
signal cpu_0_axi_full_awvalid : std_logic;
signal cpu_0_axi_full_awready : std_logic;
signal cpu_0_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_0_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpu_0_axi_full_wlast : std_logic;
signal cpu_0_axi_full_wvalid : std_logic;
signal cpu_0_axi_full_wready : std_logic;
signal cpu_0_axi_full_bid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_0_axi_full_bresp : std_logic_vector(1 downto 0);
signal cpu_0_axi_full_bvalid : std_logic;
signal cpu_0_axi_full_bready : std_logic;
signal cpu_0_axi_full_arid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_0_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_0_axi_full_arlen : std_logic_vector(7 downto 0);
signal cpu_0_axi_full_arsize : std_logic_vector(2 downto 0);
signal cpu_0_axi_full_arburst : std_logic_vector(1 downto 0);
signal cpu_0_axi_full_arlock : std_logic;
signal cpu_0_axi_full_arcache : std_logic_vector(3 downto 0);
signal cpu_0_axi_full_arprot : std_logic_vector(2 downto 0);
signal cpu_0_axi_full_arqos : std_logic_vector(3 downto 0);
signal cpu_0_axi_full_arregion : std_logic_vector(3 downto 0);
signal cpu_0_axi_full_arvalid : std_logic;
signal cpu_0_axi_full_arready : std_logic;
signal cpu_0_axi_full_rid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_0_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_0_axi_full_rresp : std_logic_vector(1 downto 0);
signal cpu_0_axi_full_rlast : std_logic;
signal cpu_0_axi_full_rvalid : std_logic;
signal cpu_0_axi_full_rready : std_logic;
signal cpu_1_axi_full_awid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_1_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_1_axi_full_awlen : std_logic_vector(7 downto 0);
signal cpu_1_axi_full_awsize : std_logic_vector(2 downto 0);
signal cpu_1_axi_full_awburst : std_logic_vector(1 downto 0);
signal cpu_1_axi_full_awlock : std_logic;
signal cpu_1_axi_full_awcache : std_logic_vector(3 downto 0);
signal cpu_1_axi_full_awprot : std_logic_vector(2 downto 0);
signal cpu_1_axi_full_awqos : std_logic_vector(3 downto 0);
signal cpu_1_axi_full_awregion : std_logic_vector(3 downto 0);
signal cpu_1_axi_full_awvalid : std_logic;
signal cpu_1_axi_full_awready : std_logic;
signal cpu_1_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_1_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpu_1_axi_full_wlast : std_logic;
signal cpu_1_axi_full_wvalid : std_logic;
signal cpu_1_axi_full_wready : std_logic;
signal cpu_1_axi_full_bid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_1_axi_full_bresp : std_logic_vector(1 downto 0);
signal cpu_1_axi_full_bvalid : std_logic;
signal cpu_1_axi_full_bready : std_logic;
signal cpu_1_axi_full_arid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_1_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_1_axi_full_arlen : std_logic_vector(7 downto 0);
signal cpu_1_axi_full_arsize : std_logic_vector(2 downto 0);
signal cpu_1_axi_full_arburst : std_logic_vector(1 downto 0);
signal cpu_1_axi_full_arlock : std_logic;
signal cpu_1_axi_full_arcache : std_logic_vector(3 downto 0);
signal cpu_1_axi_full_arprot : std_logic_vector(2 downto 0);
signal cpu_1_axi_full_arqos : std_logic_vector(3 downto 0);
signal cpu_1_axi_full_arregion : std_logic_vector(3 downto 0);
signal cpu_1_axi_full_arvalid : std_logic;
signal cpu_1_axi_full_arready : std_logic;
signal cpu_1_axi_full_rid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_1_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_1_axi_full_rresp : std_logic_vector(1 downto 0);
signal cpu_1_axi_full_rlast : std_logic;
signal cpu_1_axi_full_rvalid : std_logic;
signal cpu_1_axi_full_rready : std_logic;
signal cpu_2_axi_full_awid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_2_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_2_axi_full_awlen : std_logic_vector(7 downto 0);
signal cpu_2_axi_full_awsize : std_logic_vector(2 downto 0);
signal cpu_2_axi_full_awburst : std_logic_vector(1 downto 0);
signal cpu_2_axi_full_awlock : std_logic;
signal cpu_2_axi_full_awcache : std_logic_vector(3 downto 0);
signal cpu_2_axi_full_awprot : std_logic_vector(2 downto 0);
signal cpu_2_axi_full_awqos : std_logic_vector(3 downto 0);
signal cpu_2_axi_full_awregion : std_logic_vector(3 downto 0);
signal cpu_2_axi_full_awvalid : std_logic;
signal cpu_2_axi_full_awready : std_logic;
signal cpu_2_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_2_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpu_2_axi_full_wlast : std_logic;
signal cpu_2_axi_full_wvalid : std_logic;
signal cpu_2_axi_full_wready : std_logic;
signal cpu_2_axi_full_bid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_2_axi_full_bresp : std_logic_vector(1 downto 0);
signal cpu_2_axi_full_bvalid : std_logic;
signal cpu_2_axi_full_bready : std_logic;
signal cpu_2_axi_full_arid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_2_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_2_axi_full_arlen : std_logic_vector(7 downto 0);
signal cpu_2_axi_full_arsize : std_logic_vector(2 downto 0);
signal cpu_2_axi_full_arburst : std_logic_vector(1 downto 0);
signal cpu_2_axi_full_arlock : std_logic;
signal cpu_2_axi_full_arcache : std_logic_vector(3 downto 0);
signal cpu_2_axi_full_arprot : std_logic_vector(2 downto 0);
signal cpu_2_axi_full_arqos : std_logic_vector(3 downto 0);
signal cpu_2_axi_full_arregion : std_logic_vector(3 downto 0);
signal cpu_2_axi_full_arvalid : std_logic;
signal cpu_2_axi_full_arready : std_logic;
signal cpu_2_axi_full_rid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_2_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_2_axi_full_rresp : std_logic_vector(1 downto 0);
signal cpu_2_axi_full_rlast : std_logic;
signal cpu_2_axi_full_rvalid : std_logic;
signal cpu_2_axi_full_rready : std_logic;
signal boot_bram_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal boot_bram_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal boot_bram_axi_full_awlen : std_logic_vector(7 downto 0);
signal boot_bram_axi_full_awsize : std_logic_vector(2 downto 0);
signal boot_bram_axi_full_awburst : std_logic_vector(1 downto 0);
signal boot_bram_axi_full_awlock : std_logic;
signal boot_bram_axi_full_awcache : std_logic_vector(3 downto 0);
signal boot_bram_axi_full_awprot : std_logic_vector(2 downto 0);
signal boot_bram_axi_full_awqos : std_logic_vector(3 downto 0);
signal boot_bram_axi_full_awregion : std_logic_vector(3 downto 0);
signal boot_bram_axi_full_awvalid : std_logic;
signal boot_bram_axi_full_awready : std_logic;
signal boot_bram_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal boot_bram_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal boot_bram_axi_full_wlast : std_logic;
signal boot_bram_axi_full_wvalid : std_logic;
signal boot_bram_axi_full_wready : std_logic;
signal boot_bram_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal boot_bram_axi_full_bresp : std_logic_vector(1 downto 0);
signal boot_bram_axi_full_bvalid : std_logic;
signal boot_bram_axi_full_bready : std_logic;
signal boot_bram_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal boot_bram_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal boot_bram_axi_full_arlen : std_logic_vector(7 downto 0);
signal boot_bram_axi_full_arsize : std_logic_vector(2 downto 0);
signal boot_bram_axi_full_arburst : std_logic_vector(1 downto 0);
signal boot_bram_axi_full_arlock : std_logic;
signal boot_bram_axi_full_arcache : std_logic_vector(3 downto 0);
signal boot_bram_axi_full_arprot : std_logic_vector(2 downto 0);
signal boot_bram_axi_full_arqos : std_logic_vector(3 downto 0);
signal boot_bram_axi_full_arregion : std_logic_vector(3 downto 0);
signal boot_bram_axi_full_arvalid : std_logic;
signal boot_bram_axi_full_arready : std_logic;
signal boot_bram_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal boot_bram_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal boot_bram_axi_full_rresp : std_logic_vector(1 downto 0);
signal boot_bram_axi_full_rlast : std_logic;
signal boot_bram_axi_full_rvalid : std_logic;
signal boot_bram_axi_full_rready : std_logic;
signal ram_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal ram_axi_full_awid_ext : std_logic_vector(3 downto 0) := (others=>'0');
signal ram_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0) := (others=>'0');
signal ram_axi_full_awlen : std_logic_vector(7 downto 0);
signal ram_axi_full_awsize : std_logic_vector(2 downto 0);
signal ram_axi_full_awburst : std_logic_vector(1 downto 0);
signal ram_axi_full_awlock : std_logic;
signal ram_axi_full_awlock_slv : std_logic_vector(0 downto 0);
signal ram_axi_full_awcache : std_logic_vector(3 downto 0);
signal ram_axi_full_awprot : std_logic_vector(2 downto 0);
signal ram_axi_full_awqos : std_logic_vector(3 downto 0);
signal ram_axi_full_awregion : std_logic_vector(3 downto 0);
signal ram_axi_full_awvalid : std_logic;
signal ram_axi_full_awready : std_logic;
signal ram_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal ram_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal ram_axi_full_wlast : std_logic;
signal ram_axi_full_wvalid : std_logic;
signal ram_axi_full_wready : std_logic;
signal ram_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal ram_axi_full_bid_ext : std_logic_vector(3 downto 0) := (others=>'0');
signal ram_axi_full_bresp : std_logic_vector(1 downto 0);
signal ram_axi_full_bvalid : std_logic;
signal ram_axi_full_bready : std_logic;
signal ram_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal ram_axi_full_arid_ext : std_logic_vector(3 downto 0) := (others=>'0');
signal ram_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0) := (others=>'0');
signal ram_axi_full_arlen : std_logic_vector(7 downto 0);
signal ram_axi_full_arsize : std_logic_vector(2 downto 0);
signal ram_axi_full_arburst : std_logic_vector(1 downto 0);
signal ram_axi_full_arlock : std_logic;
signal ram_axi_full_arlock_slv : std_logic_vector(0 downto 0);
signal ram_axi_full_arcache : std_logic_vector(3 downto 0);
signal ram_axi_full_arprot : std_logic_vector(2 downto 0);
signal ram_axi_full_arqos : std_logic_vector(3 downto 0);
signal ram_axi_full_arregion : std_logic_vector(3 downto 0);
signal ram_axi_full_arvalid : std_logic;
signal ram_axi_full_arready : std_logic;
signal ram_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal ram_axi_full_rid_ext : std_logic_vector(3 downto 0) := (others=>'0');
signal ram_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal ram_axi_full_rresp : std_logic_vector(1 downto 0);
signal ram_axi_full_rlast : std_logic;
signal ram_axi_full_rvalid : std_logic;
signal ram_axi_full_rready : std_logic;
signal int_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal int_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_axi_full_awlen : std_logic_vector(7 downto 0);
signal int_axi_full_awsize : std_logic_vector(2 downto 0);
signal int_axi_full_awburst : std_logic_vector(1 downto 0);
signal int_axi_full_awlock : std_logic;
signal int_axi_full_awcache : std_logic_vector(3 downto 0);
signal int_axi_full_awprot : std_logic_vector(2 downto 0);
signal int_axi_full_awqos : std_logic_vector(3 downto 0);
signal int_axi_full_awregion : std_logic_vector(3 downto 0);
signal int_axi_full_awvalid : std_logic;
signal int_axi_full_awready : std_logic;
signal int_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_axi_full_wlast : std_logic;
signal int_axi_full_wvalid : std_logic;
signal int_axi_full_wready : std_logic;
signal int_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal int_axi_full_bresp : std_logic_vector(1 downto 0);
signal int_axi_full_bvalid : std_logic;
signal int_axi_full_bready : std_logic;
signal int_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal int_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_axi_full_arlen : std_logic_vector(7 downto 0);
signal int_axi_full_arsize : std_logic_vector(2 downto 0);
signal int_axi_full_arburst : std_logic_vector(1 downto 0);
signal int_axi_full_arlock : std_logic;
signal int_axi_full_arcache : std_logic_vector(3 downto 0);
signal int_axi_full_arprot : std_logic_vector(2 downto 0);
signal int_axi_full_arqos : std_logic_vector(3 downto 0);
signal int_axi_full_arregion : std_logic_vector(3 downto 0);
signal int_axi_full_arvalid : std_logic;
signal int_axi_full_arready : std_logic;
signal int_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal int_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_axi_full_rresp : std_logic_vector(1 downto 0);
signal int_axi_full_rlast : std_logic;
signal int_axi_full_rvalid : std_logic;
signal int_axi_full_rready : std_logic;
signal timer_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_axi_full_awlen : std_logic_vector(7 downto 0);
signal timer_axi_full_awsize : std_logic_vector(2 downto 0);
signal timer_axi_full_awburst : std_logic_vector(1 downto 0);
signal timer_axi_full_awlock : std_logic;
signal timer_axi_full_awcache : std_logic_vector(3 downto 0);
signal timer_axi_full_awprot : std_logic_vector(2 downto 0);
signal timer_axi_full_awqos : std_logic_vector(3 downto 0);
signal timer_axi_full_awregion : std_logic_vector(3 downto 0);
signal timer_axi_full_awvalid : std_logic;
signal timer_axi_full_awready : std_logic;
signal timer_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_axi_full_wlast : std_logic;
signal timer_axi_full_wvalid : std_logic;
signal timer_axi_full_wready : std_logic;
signal timer_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_axi_full_bresp : std_logic_vector(1 downto 0);
signal timer_axi_full_bvalid : std_logic;
signal timer_axi_full_bready : std_logic;
signal timer_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_axi_full_arlen : std_logic_vector(7 downto 0);
signal timer_axi_full_arsize : std_logic_vector(2 downto 0);
signal timer_axi_full_arburst : std_logic_vector(1 downto 0);
signal timer_axi_full_arlock : std_logic;
signal timer_axi_full_arcache : std_logic_vector(3 downto 0);
signal timer_axi_full_arprot : std_logic_vector(2 downto 0);
signal timer_axi_full_arqos : std_logic_vector(3 downto 0);
signal timer_axi_full_arregion : std_logic_vector(3 downto 0);
signal timer_axi_full_arvalid : std_logic;
signal timer_axi_full_arready : std_logic;
signal timer_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_axi_full_rresp : std_logic_vector(1 downto 0);
signal timer_axi_full_rlast : std_logic;
signal timer_axi_full_rvalid : std_logic;
signal timer_axi_full_rready : std_logic;
signal gpio_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal gpio_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal gpio_axi_full_awlen : std_logic_vector(7 downto 0);
signal gpio_axi_full_awsize : std_logic_vector(2 downto 0);
signal gpio_axi_full_awburst : std_logic_vector(1 downto 0);
signal gpio_axi_full_awlock : std_logic;
signal gpio_axi_full_awcache : std_logic_vector(3 downto 0);
signal gpio_axi_full_awprot : std_logic_vector(2 downto 0);
signal gpio_axi_full_awqos : std_logic_vector(3 downto 0);
signal gpio_axi_full_awregion : std_logic_vector(3 downto 0);
signal gpio_axi_full_awvalid : std_logic;
signal gpio_axi_full_awready : std_logic;
signal gpio_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal gpio_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal gpio_axi_full_wlast : std_logic;
signal gpio_axi_full_wvalid : std_logic;
signal gpio_axi_full_wready : std_logic;
signal gpio_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal gpio_axi_full_bresp : std_logic_vector(1 downto 0);
signal gpio_axi_full_bvalid : std_logic;
signal gpio_axi_full_bready : std_logic;
signal gpio_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal gpio_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal gpio_axi_full_arlen : std_logic_vector(7 downto 0);
signal gpio_axi_full_arsize : std_logic_vector(2 downto 0);
signal gpio_axi_full_arburst : std_logic_vector(1 downto 0);
signal gpio_axi_full_arlock : std_logic;
signal gpio_axi_full_arcache : std_logic_vector(3 downto 0);
signal gpio_axi_full_arprot : std_logic_vector(2 downto 0);
signal gpio_axi_full_arqos : std_logic_vector(3 downto 0);
signal gpio_axi_full_arregion : std_logic_vector(3 downto 0);
signal gpio_axi_full_arvalid : std_logic;
signal gpio_axi_full_arready : std_logic;
signal gpio_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal gpio_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal gpio_axi_full_rresp : std_logic_vector(1 downto 0);
signal gpio_axi_full_rlast : std_logic;
signal gpio_axi_full_rvalid : std_logic;
signal gpio_axi_full_rready : std_logic;
signal uart_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal uart_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal uart_axi_full_awlen : std_logic_vector(7 downto 0);
signal uart_axi_full_awsize : std_logic_vector(2 downto 0);
signal uart_axi_full_awburst : std_logic_vector(1 downto 0);
signal uart_axi_full_awlock : std_logic;
signal uart_axi_full_awcache : std_logic_vector(3 downto 0);
signal uart_axi_full_awprot : std_logic_vector(2 downto 0);
signal uart_axi_full_awqos : std_logic_vector(3 downto 0);
signal uart_axi_full_awregion : std_logic_vector(3 downto 0);
signal uart_axi_full_awvalid : std_logic;
signal uart_axi_full_awready : std_logic;
signal uart_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal uart_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal uart_axi_full_wlast : std_logic;
signal uart_axi_full_wvalid : std_logic;
signal uart_axi_full_wready : std_logic;
signal uart_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal uart_axi_full_bresp : std_logic_vector(1 downto 0);
signal uart_axi_full_bvalid : std_logic;
signal uart_axi_full_bready : std_logic;
signal uart_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal uart_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal uart_axi_full_arlen : std_logic_vector(7 downto 0);
signal uart_axi_full_arsize : std_logic_vector(2 downto 0);
signal uart_axi_full_arburst : std_logic_vector(1 downto 0);
signal uart_axi_full_arlock : std_logic;
signal uart_axi_full_arcache : std_logic_vector(3 downto 0);
signal uart_axi_full_arprot : std_logic_vector(2 downto 0);
signal uart_axi_full_arqos : std_logic_vector(3 downto 0);
signal uart_axi_full_arregion : std_logic_vector(3 downto 0);
signal uart_axi_full_arvalid : std_logic;
signal uart_axi_full_arready : std_logic;
signal uart_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal uart_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal uart_axi_full_rresp : std_logic_vector(1 downto 0);
signal uart_axi_full_rlast : std_logic;
signal uart_axi_full_rvalid : std_logic;
signal uart_axi_full_rready : std_logic;
signal lock_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal lock_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal lock_axi_full_awlen : std_logic_vector(7 downto 0);
signal lock_axi_full_awsize : std_logic_vector(2 downto 0);
signal lock_axi_full_awburst : std_logic_vector(1 downto 0);
signal lock_axi_full_awlock : std_logic;
signal lock_axi_full_awcache : std_logic_vector(3 downto 0);
signal lock_axi_full_awprot : std_logic_vector(2 downto 0);
signal lock_axi_full_awqos : std_logic_vector(3 downto 0);
signal lock_axi_full_awregion : std_logic_vector(3 downto 0);
signal lock_axi_full_awvalid : std_logic;
signal lock_axi_full_awready : std_logic;
signal lock_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal lock_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal lock_axi_full_wlast : std_logic;
signal lock_axi_full_wvalid : std_logic;
signal lock_axi_full_wready : std_logic;
signal lock_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal lock_axi_full_bresp : std_logic_vector(1 downto 0);
signal lock_axi_full_bvalid : std_logic;
signal lock_axi_full_bready : std_logic;
signal lock_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal lock_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal lock_axi_full_arlen : std_logic_vector(7 downto 0);
signal lock_axi_full_arsize : std_logic_vector(2 downto 0);
signal lock_axi_full_arburst : std_logic_vector(1 downto 0);
signal lock_axi_full_arlock : std_logic;
signal lock_axi_full_arcache : std_logic_vector(3 downto 0);
signal lock_axi_full_arprot : std_logic_vector(2 downto 0);
signal lock_axi_full_arqos : std_logic_vector(3 downto 0);
signal lock_axi_full_arregion : std_logic_vector(3 downto 0);
signal lock_axi_full_arvalid : std_logic;
signal lock_axi_full_arready : std_logic;
signal lock_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal lock_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal lock_axi_full_rresp : std_logic_vector(1 downto 0);
signal lock_axi_full_rlast : std_logic;
signal lock_axi_full_rvalid : std_logic;
signal lock_axi_full_rready : std_logic;
---------------------
-- CPU Bus Signals --
---------------------
signal cpu_bus_0_full_awid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_0_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_bus_0_full_awlen : std_logic_vector(7 downto 0);
signal cpu_bus_0_full_awsize : std_logic_vector(2 downto 0);
signal cpu_bus_0_full_awburst : std_logic_vector(1 downto 0);
signal cpu_bus_0_full_awlock : std_logic;
signal cpu_bus_0_full_awcache : std_logic_vector(3 downto 0);
signal cpu_bus_0_full_awprot : std_logic_vector(2 downto 0);
signal cpu_bus_0_full_awqos : std_logic_vector(3 downto 0);
signal cpu_bus_0_full_awregion : std_logic_vector(3 downto 0);
signal cpu_bus_0_full_awvalid : std_logic;
signal cpu_bus_0_full_awready : std_logic;
signal cpu_bus_0_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_bus_0_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpu_bus_0_full_wlast : std_logic;
signal cpu_bus_0_full_wvalid : std_logic;
signal cpu_bus_0_full_wready : std_logic;
signal cpu_bus_0_full_bid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_0_full_bresp : std_logic_vector(1 downto 0);
signal cpu_bus_0_full_bvalid : std_logic;
signal cpu_bus_0_full_bready : std_logic;
signal cpu_bus_0_full_arid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_0_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_bus_0_full_arlen : std_logic_vector(7 downto 0);
signal cpu_bus_0_full_arsize : std_logic_vector(2 downto 0);
signal cpu_bus_0_full_arburst : std_logic_vector(1 downto 0);
signal cpu_bus_0_full_arlock : std_logic;
signal cpu_bus_0_full_arcache : std_logic_vector(3 downto 0);
signal cpu_bus_0_full_arprot : std_logic_vector(2 downto 0);
signal cpu_bus_0_full_arqos : std_logic_vector(3 downto 0);
signal cpu_bus_0_full_arregion : std_logic_vector(3 downto 0);
signal cpu_bus_0_full_arvalid : std_logic;
signal cpu_bus_0_full_arready : std_logic;
signal cpu_bus_0_full_rid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_0_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_bus_0_full_rresp : std_logic_vector(1 downto 0);
signal cpu_bus_0_full_rlast : std_logic;
signal cpu_bus_0_full_rvalid : std_logic;
signal cpu_bus_0_full_rready : std_logic;
signal cpuid_gpio_bus_0_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_0_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_0_full_awlen : std_logic_vector(7 downto 0);
signal cpuid_gpio_bus_0_full_awsize : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_0_full_awburst : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_0_full_awlock : std_logic;
signal cpuid_gpio_bus_0_full_awcache : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_0_full_awprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_0_full_awqos : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_0_full_awregion : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_0_full_awvalid : std_logic;
signal cpuid_gpio_bus_0_full_awready : std_logic;
signal cpuid_gpio_bus_0_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_0_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpuid_gpio_bus_0_full_wlast : std_logic;
signal cpuid_gpio_bus_0_full_wvalid : std_logic;
signal cpuid_gpio_bus_0_full_wready : std_logic;
signal cpuid_gpio_bus_0_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_0_full_bresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_0_full_bvalid : std_logic;
signal cpuid_gpio_bus_0_full_bready : std_logic;
signal cpuid_gpio_bus_0_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_0_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_0_full_arlen : std_logic_vector(7 downto 0);
signal cpuid_gpio_bus_0_full_arsize : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_0_full_arburst : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_0_full_arlock : std_logic;
signal cpuid_gpio_bus_0_full_arcache : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_0_full_arprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_0_full_arqos : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_0_full_arregion : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_0_full_arvalid : std_logic;
signal cpuid_gpio_bus_0_full_arready : std_logic;
signal cpuid_gpio_bus_0_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_0_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_0_full_rresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_0_full_rlast : std_logic;
signal cpuid_gpio_bus_0_full_rvalid : std_logic;
signal cpuid_gpio_bus_0_full_rready : std_logic;
signal int_bus_0_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_0_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_0_full_awlen : std_logic_vector(7 downto 0);
signal int_bus_0_full_awsize : std_logic_vector(2 downto 0);
signal int_bus_0_full_awburst : std_logic_vector(1 downto 0);
signal int_bus_0_full_awlock : std_logic;
signal int_bus_0_full_awcache : std_logic_vector(3 downto 0);
signal int_bus_0_full_awprot : std_logic_vector(2 downto 0);
signal int_bus_0_full_awqos : std_logic_vector(3 downto 0);
signal int_bus_0_full_awregion : std_logic_vector(3 downto 0);
signal int_bus_0_full_awvalid : std_logic;
signal int_bus_0_full_awready : std_logic;
signal int_bus_0_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_0_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_bus_0_full_wlast : std_logic;
signal int_bus_0_full_wvalid : std_logic;
signal int_bus_0_full_wready : std_logic;
signal int_bus_0_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_0_full_bresp : std_logic_vector(1 downto 0);
signal int_bus_0_full_bvalid : std_logic;
signal int_bus_0_full_bready : std_logic;
signal int_bus_0_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_0_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_0_full_arlen : std_logic_vector(7 downto 0);
signal int_bus_0_full_arsize : std_logic_vector(2 downto 0);
signal int_bus_0_full_arburst : std_logic_vector(1 downto 0);
signal int_bus_0_full_arlock : std_logic;
signal int_bus_0_full_arcache : std_logic_vector(3 downto 0);
signal int_bus_0_full_arprot : std_logic_vector(2 downto 0);
signal int_bus_0_full_arqos : std_logic_vector(3 downto 0);
signal int_bus_0_full_arregion : std_logic_vector(3 downto 0);
signal int_bus_0_full_arvalid : std_logic;
signal int_bus_0_full_arready : std_logic;
signal int_bus_0_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_0_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_0_full_rresp : std_logic_vector(1 downto 0);
signal int_bus_0_full_rlast : std_logic;
signal int_bus_0_full_rvalid : std_logic;
signal int_bus_0_full_rready : std_logic;
signal signal_bus_0_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_0_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_0_full_awlen : std_logic_vector(7 downto 0);
signal signal_bus_0_full_awsize : std_logic_vector(2 downto 0);
signal signal_bus_0_full_awburst : std_logic_vector(1 downto 0);
signal signal_bus_0_full_awlock : std_logic;
signal signal_bus_0_full_awcache : std_logic_vector(3 downto 0);
signal signal_bus_0_full_awprot : std_logic_vector(2 downto 0);
signal signal_bus_0_full_awqos : std_logic_vector(3 downto 0);
signal signal_bus_0_full_awregion : std_logic_vector(3 downto 0);
signal signal_bus_0_full_awvalid : std_logic;
signal signal_bus_0_full_awready : std_logic;
signal signal_bus_0_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_0_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal signal_bus_0_full_wlast : std_logic;
signal signal_bus_0_full_wvalid : std_logic;
signal signal_bus_0_full_wready : std_logic;
signal signal_bus_0_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_0_full_bresp : std_logic_vector(1 downto 0);
signal signal_bus_0_full_bvalid : std_logic;
signal signal_bus_0_full_bready : std_logic;
signal signal_bus_0_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_0_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_0_full_arlen : std_logic_vector(7 downto 0);
signal signal_bus_0_full_arsize : std_logic_vector(2 downto 0);
signal signal_bus_0_full_arburst : std_logic_vector(1 downto 0);
signal signal_bus_0_full_arlock : std_logic;
signal signal_bus_0_full_arcache : std_logic_vector(3 downto 0);
signal signal_bus_0_full_arprot : std_logic_vector(2 downto 0);
signal signal_bus_0_full_arqos : std_logic_vector(3 downto 0);
signal signal_bus_0_full_arregion : std_logic_vector(3 downto 0);
signal signal_bus_0_full_arvalid : std_logic;
signal signal_bus_0_full_arready : std_logic;
signal signal_bus_0_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_0_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_0_full_rresp : std_logic_vector(1 downto 0);
signal signal_bus_0_full_rlast : std_logic;
signal signal_bus_0_full_rvalid : std_logic;
signal signal_bus_0_full_rready : std_logic;
signal timer_bus_0_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_0_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_0_full_awlen : std_logic_vector(7 downto 0);
signal timer_bus_0_full_awsize : std_logic_vector(2 downto 0);
signal timer_bus_0_full_awburst : std_logic_vector(1 downto 0);
signal timer_bus_0_full_awlock : std_logic;
signal timer_bus_0_full_awcache : std_logic_vector(3 downto 0);
signal timer_bus_0_full_awprot : std_logic_vector(2 downto 0);
signal timer_bus_0_full_awqos : std_logic_vector(3 downto 0);
signal timer_bus_0_full_awregion : std_logic_vector(3 downto 0);
signal timer_bus_0_full_awvalid : std_logic;
signal timer_bus_0_full_awready : std_logic;
signal timer_bus_0_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_0_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_bus_0_full_wlast : std_logic;
signal timer_bus_0_full_wvalid : std_logic;
signal timer_bus_0_full_wready : std_logic;
signal timer_bus_0_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_0_full_bresp : std_logic_vector(1 downto 0);
signal timer_bus_0_full_bvalid : std_logic;
signal timer_bus_0_full_bready : std_logic;
signal timer_bus_0_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_0_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_0_full_arlen : std_logic_vector(7 downto 0);
signal timer_bus_0_full_arsize : std_logic_vector(2 downto 0);
signal timer_bus_0_full_arburst : std_logic_vector(1 downto 0);
signal timer_bus_0_full_arlock : std_logic;
signal timer_bus_0_full_arcache : std_logic_vector(3 downto 0);
signal timer_bus_0_full_arprot : std_logic_vector(2 downto 0);
signal timer_bus_0_full_arqos : std_logic_vector(3 downto 0);
signal timer_bus_0_full_arregion : std_logic_vector(3 downto 0);
signal timer_bus_0_full_arvalid : std_logic;
signal timer_bus_0_full_arready : std_logic;
signal timer_bus_0_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_0_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_0_full_rresp : std_logic_vector(1 downto 0);
signal timer_bus_0_full_rlast : std_logic;
signal timer_bus_0_full_rvalid : std_logic;
signal timer_bus_0_full_rready : std_logic;
signal cpu_bus_1_full_awid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_1_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_bus_1_full_awlen : std_logic_vector(7 downto 0);
signal cpu_bus_1_full_awsize : std_logic_vector(2 downto 0);
signal cpu_bus_1_full_awburst : std_logic_vector(1 downto 0);
signal cpu_bus_1_full_awlock : std_logic;
signal cpu_bus_1_full_awcache : std_logic_vector(3 downto 0);
signal cpu_bus_1_full_awprot : std_logic_vector(2 downto 0);
signal cpu_bus_1_full_awqos : std_logic_vector(3 downto 0);
signal cpu_bus_1_full_awregion : std_logic_vector(3 downto 0);
signal cpu_bus_1_full_awvalid : std_logic;
signal cpu_bus_1_full_awready : std_logic;
signal cpu_bus_1_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_bus_1_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpu_bus_1_full_wlast : std_logic;
signal cpu_bus_1_full_wvalid : std_logic;
signal cpu_bus_1_full_wready : std_logic;
signal cpu_bus_1_full_bid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_1_full_bresp : std_logic_vector(1 downto 0);
signal cpu_bus_1_full_bvalid : std_logic;
signal cpu_bus_1_full_bready : std_logic;
signal cpu_bus_1_full_arid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_1_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_bus_1_full_arlen : std_logic_vector(7 downto 0);
signal cpu_bus_1_full_arsize : std_logic_vector(2 downto 0);
signal cpu_bus_1_full_arburst : std_logic_vector(1 downto 0);
signal cpu_bus_1_full_arlock : std_logic;
signal cpu_bus_1_full_arcache : std_logic_vector(3 downto 0);
signal cpu_bus_1_full_arprot : std_logic_vector(2 downto 0);
signal cpu_bus_1_full_arqos : std_logic_vector(3 downto 0);
signal cpu_bus_1_full_arregion : std_logic_vector(3 downto 0);
signal cpu_bus_1_full_arvalid : std_logic;
signal cpu_bus_1_full_arready : std_logic;
signal cpu_bus_1_full_rid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_1_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_bus_1_full_rresp : std_logic_vector(1 downto 0);
signal cpu_bus_1_full_rlast : std_logic;
signal cpu_bus_1_full_rvalid : std_logic;
signal cpu_bus_1_full_rready : std_logic;
signal cpuid_gpio_bus_1_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_1_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_1_full_awlen : std_logic_vector(7 downto 0);
signal cpuid_gpio_bus_1_full_awsize : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_1_full_awburst : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_1_full_awlock : std_logic;
signal cpuid_gpio_bus_1_full_awcache : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_1_full_awprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_1_full_awqos : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_1_full_awregion : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_1_full_awvalid : std_logic;
signal cpuid_gpio_bus_1_full_awready : std_logic;
signal cpuid_gpio_bus_1_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_1_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpuid_gpio_bus_1_full_wlast : std_logic;
signal cpuid_gpio_bus_1_full_wvalid : std_logic;
signal cpuid_gpio_bus_1_full_wready : std_logic;
signal cpuid_gpio_bus_1_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_1_full_bresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_1_full_bvalid : std_logic;
signal cpuid_gpio_bus_1_full_bready : std_logic;
signal cpuid_gpio_bus_1_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_1_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_1_full_arlen : std_logic_vector(7 downto 0);
signal cpuid_gpio_bus_1_full_arsize : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_1_full_arburst : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_1_full_arlock : std_logic;
signal cpuid_gpio_bus_1_full_arcache : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_1_full_arprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_1_full_arqos : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_1_full_arregion : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_1_full_arvalid : std_logic;
signal cpuid_gpio_bus_1_full_arready : std_logic;
signal cpuid_gpio_bus_1_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_1_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_1_full_rresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_1_full_rlast : std_logic;
signal cpuid_gpio_bus_1_full_rvalid : std_logic;
signal cpuid_gpio_bus_1_full_rready : std_logic;
signal int_bus_1_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_1_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_1_full_awlen : std_logic_vector(7 downto 0);
signal int_bus_1_full_awsize : std_logic_vector(2 downto 0);
signal int_bus_1_full_awburst : std_logic_vector(1 downto 0);
signal int_bus_1_full_awlock : std_logic;
signal int_bus_1_full_awcache : std_logic_vector(3 downto 0);
signal int_bus_1_full_awprot : std_logic_vector(2 downto 0);
signal int_bus_1_full_awqos : std_logic_vector(3 downto 0);
signal int_bus_1_full_awregion : std_logic_vector(3 downto 0);
signal int_bus_1_full_awvalid : std_logic;
signal int_bus_1_full_awready : std_logic;
signal int_bus_1_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_1_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_bus_1_full_wlast : std_logic;
signal int_bus_1_full_wvalid : std_logic;
signal int_bus_1_full_wready : std_logic;
signal int_bus_1_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_1_full_bresp : std_logic_vector(1 downto 0);
signal int_bus_1_full_bvalid : std_logic;
signal int_bus_1_full_bready : std_logic;
signal int_bus_1_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_1_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_1_full_arlen : std_logic_vector(7 downto 0);
signal int_bus_1_full_arsize : std_logic_vector(2 downto 0);
signal int_bus_1_full_arburst : std_logic_vector(1 downto 0);
signal int_bus_1_full_arlock : std_logic;
signal int_bus_1_full_arcache : std_logic_vector(3 downto 0);
signal int_bus_1_full_arprot : std_logic_vector(2 downto 0);
signal int_bus_1_full_arqos : std_logic_vector(3 downto 0);
signal int_bus_1_full_arregion : std_logic_vector(3 downto 0);
signal int_bus_1_full_arvalid : std_logic;
signal int_bus_1_full_arready : std_logic;
signal int_bus_1_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_1_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_1_full_rresp : std_logic_vector(1 downto 0);
signal int_bus_1_full_rlast : std_logic;
signal int_bus_1_full_rvalid : std_logic;
signal int_bus_1_full_rready : std_logic;
signal signal_bus_1_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_1_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_1_full_awlen : std_logic_vector(7 downto 0);
signal signal_bus_1_full_awsize : std_logic_vector(2 downto 0);
signal signal_bus_1_full_awburst : std_logic_vector(1 downto 0);
signal signal_bus_1_full_awlock : std_logic;
signal signal_bus_1_full_awcache : std_logic_vector(3 downto 0);
signal signal_bus_1_full_awprot : std_logic_vector(2 downto 0);
signal signal_bus_1_full_awqos : std_logic_vector(3 downto 0);
signal signal_bus_1_full_awregion : std_logic_vector(3 downto 0);
signal signal_bus_1_full_awvalid : std_logic;
signal signal_bus_1_full_awready : std_logic;
signal signal_bus_1_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_1_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal signal_bus_1_full_wlast : std_logic;
signal signal_bus_1_full_wvalid : std_logic;
signal signal_bus_1_full_wready : std_logic;
signal signal_bus_1_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_1_full_bresp : std_logic_vector(1 downto 0);
signal signal_bus_1_full_bvalid : std_logic;
signal signal_bus_1_full_bready : std_logic;
signal signal_bus_1_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_1_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_1_full_arlen : std_logic_vector(7 downto 0);
signal signal_bus_1_full_arsize : std_logic_vector(2 downto 0);
signal signal_bus_1_full_arburst : std_logic_vector(1 downto 0);
signal signal_bus_1_full_arlock : std_logic;
signal signal_bus_1_full_arcache : std_logic_vector(3 downto 0);
signal signal_bus_1_full_arprot : std_logic_vector(2 downto 0);
signal signal_bus_1_full_arqos : std_logic_vector(3 downto 0);
signal signal_bus_1_full_arregion : std_logic_vector(3 downto 0);
signal signal_bus_1_full_arvalid : std_logic;
signal signal_bus_1_full_arready : std_logic;
signal signal_bus_1_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_1_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_1_full_rresp : std_logic_vector(1 downto 0);
signal signal_bus_1_full_rlast : std_logic;
signal signal_bus_1_full_rvalid : std_logic;
signal signal_bus_1_full_rready : std_logic;
signal timer_bus_1_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_1_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_1_full_awlen : std_logic_vector(7 downto 0);
signal timer_bus_1_full_awsize : std_logic_vector(2 downto 0);
signal timer_bus_1_full_awburst : std_logic_vector(1 downto 0);
signal timer_bus_1_full_awlock : std_logic;
signal timer_bus_1_full_awcache : std_logic_vector(3 downto 0);
signal timer_bus_1_full_awprot : std_logic_vector(2 downto 0);
signal timer_bus_1_full_awqos : std_logic_vector(3 downto 0);
signal timer_bus_1_full_awregion : std_logic_vector(3 downto 0);
signal timer_bus_1_full_awvalid : std_logic;
signal timer_bus_1_full_awready : std_logic;
signal timer_bus_1_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_1_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_bus_1_full_wlast : std_logic;
signal timer_bus_1_full_wvalid : std_logic;
signal timer_bus_1_full_wready : std_logic;
signal timer_bus_1_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_1_full_bresp : std_logic_vector(1 downto 0);
signal timer_bus_1_full_bvalid : std_logic;
signal timer_bus_1_full_bready : std_logic;
signal timer_bus_1_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_1_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_1_full_arlen : std_logic_vector(7 downto 0);
signal timer_bus_1_full_arsize : std_logic_vector(2 downto 0);
signal timer_bus_1_full_arburst : std_logic_vector(1 downto 0);
signal timer_bus_1_full_arlock : std_logic;
signal timer_bus_1_full_arcache : std_logic_vector(3 downto 0);
signal timer_bus_1_full_arprot : std_logic_vector(2 downto 0);
signal timer_bus_1_full_arqos : std_logic_vector(3 downto 0);
signal timer_bus_1_full_arregion : std_logic_vector(3 downto 0);
signal timer_bus_1_full_arvalid : std_logic;
signal timer_bus_1_full_arready : std_logic;
signal timer_bus_1_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_1_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_1_full_rresp : std_logic_vector(1 downto 0);
signal timer_bus_1_full_rlast : std_logic;
signal timer_bus_1_full_rvalid : std_logic;
signal timer_bus_1_full_rready : std_logic;
signal cpu_bus_2_full_awid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_2_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_bus_2_full_awlen : std_logic_vector(7 downto 0);
signal cpu_bus_2_full_awsize : std_logic_vector(2 downto 0);
signal cpu_bus_2_full_awburst : std_logic_vector(1 downto 0);
signal cpu_bus_2_full_awlock : std_logic;
signal cpu_bus_2_full_awcache : std_logic_vector(3 downto 0);
signal cpu_bus_2_full_awprot : std_logic_vector(2 downto 0);
signal cpu_bus_2_full_awqos : std_logic_vector(3 downto 0);
signal cpu_bus_2_full_awregion : std_logic_vector(3 downto 0);
signal cpu_bus_2_full_awvalid : std_logic;
signal cpu_bus_2_full_awready : std_logic;
signal cpu_bus_2_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_bus_2_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpu_bus_2_full_wlast : std_logic;
signal cpu_bus_2_full_wvalid : std_logic;
signal cpu_bus_2_full_wready : std_logic;
signal cpu_bus_2_full_bid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_2_full_bresp : std_logic_vector(1 downto 0);
signal cpu_bus_2_full_bvalid : std_logic;
signal cpu_bus_2_full_bready : std_logic;
signal cpu_bus_2_full_arid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_2_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_bus_2_full_arlen : std_logic_vector(7 downto 0);
signal cpu_bus_2_full_arsize : std_logic_vector(2 downto 0);
signal cpu_bus_2_full_arburst : std_logic_vector(1 downto 0);
signal cpu_bus_2_full_arlock : std_logic;
signal cpu_bus_2_full_arcache : std_logic_vector(3 downto 0);
signal cpu_bus_2_full_arprot : std_logic_vector(2 downto 0);
signal cpu_bus_2_full_arqos : std_logic_vector(3 downto 0);
signal cpu_bus_2_full_arregion : std_logic_vector(3 downto 0);
signal cpu_bus_2_full_arvalid : std_logic;
signal cpu_bus_2_full_arready : std_logic;
signal cpu_bus_2_full_rid : std_logic_vector(axi_cpu_bus_slave_id_width-1 downto 0);
signal cpu_bus_2_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_bus_2_full_rresp : std_logic_vector(1 downto 0);
signal cpu_bus_2_full_rlast : std_logic;
signal cpu_bus_2_full_rvalid : std_logic;
signal cpu_bus_2_full_rready : std_logic;
signal cpuid_gpio_bus_2_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_2_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_2_full_awlen : std_logic_vector(7 downto 0);
signal cpuid_gpio_bus_2_full_awsize : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_2_full_awburst : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_2_full_awlock : std_logic;
signal cpuid_gpio_bus_2_full_awcache : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_2_full_awprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_2_full_awqos : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_2_full_awregion : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_2_full_awvalid : std_logic;
signal cpuid_gpio_bus_2_full_awready : std_logic;
signal cpuid_gpio_bus_2_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_2_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpuid_gpio_bus_2_full_wlast : std_logic;
signal cpuid_gpio_bus_2_full_wvalid : std_logic;
signal cpuid_gpio_bus_2_full_wready : std_logic;
signal cpuid_gpio_bus_2_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_2_full_bresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_2_full_bvalid : std_logic;
signal cpuid_gpio_bus_2_full_bready : std_logic;
signal cpuid_gpio_bus_2_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_2_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_2_full_arlen : std_logic_vector(7 downto 0);
signal cpuid_gpio_bus_2_full_arsize : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_2_full_arburst : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_2_full_arlock : std_logic;
signal cpuid_gpio_bus_2_full_arcache : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_2_full_arprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_2_full_arqos : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_2_full_arregion : std_logic_vector(3 downto 0);
signal cpuid_gpio_bus_2_full_arvalid : std_logic;
signal cpuid_gpio_bus_2_full_arready : std_logic;
signal cpuid_gpio_bus_2_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal cpuid_gpio_bus_2_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_2_full_rresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_2_full_rlast : std_logic;
signal cpuid_gpio_bus_2_full_rvalid : std_logic;
signal cpuid_gpio_bus_2_full_rready : std_logic;
signal int_bus_2_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_2_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_2_full_awlen : std_logic_vector(7 downto 0);
signal int_bus_2_full_awsize : std_logic_vector(2 downto 0);
signal int_bus_2_full_awburst : std_logic_vector(1 downto 0);
signal int_bus_2_full_awlock : std_logic;
signal int_bus_2_full_awcache : std_logic_vector(3 downto 0);
signal int_bus_2_full_awprot : std_logic_vector(2 downto 0);
signal int_bus_2_full_awqos : std_logic_vector(3 downto 0);
signal int_bus_2_full_awregion : std_logic_vector(3 downto 0);
signal int_bus_2_full_awvalid : std_logic;
signal int_bus_2_full_awready : std_logic;
signal int_bus_2_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_2_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_bus_2_full_wlast : std_logic;
signal int_bus_2_full_wvalid : std_logic;
signal int_bus_2_full_wready : std_logic;
signal int_bus_2_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_2_full_bresp : std_logic_vector(1 downto 0);
signal int_bus_2_full_bvalid : std_logic;
signal int_bus_2_full_bready : std_logic;
signal int_bus_2_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_2_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_2_full_arlen : std_logic_vector(7 downto 0);
signal int_bus_2_full_arsize : std_logic_vector(2 downto 0);
signal int_bus_2_full_arburst : std_logic_vector(1 downto 0);
signal int_bus_2_full_arlock : std_logic;
signal int_bus_2_full_arcache : std_logic_vector(3 downto 0);
signal int_bus_2_full_arprot : std_logic_vector(2 downto 0);
signal int_bus_2_full_arqos : std_logic_vector(3 downto 0);
signal int_bus_2_full_arregion : std_logic_vector(3 downto 0);
signal int_bus_2_full_arvalid : std_logic;
signal int_bus_2_full_arready : std_logic;
signal int_bus_2_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal int_bus_2_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_2_full_rresp : std_logic_vector(1 downto 0);
signal int_bus_2_full_rlast : std_logic;
signal int_bus_2_full_rvalid : std_logic;
signal int_bus_2_full_rready : std_logic;
signal signal_bus_2_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_2_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_2_full_awlen : std_logic_vector(7 downto 0);
signal signal_bus_2_full_awsize : std_logic_vector(2 downto 0);
signal signal_bus_2_full_awburst : std_logic_vector(1 downto 0);
signal signal_bus_2_full_awlock : std_logic;
signal signal_bus_2_full_awcache : std_logic_vector(3 downto 0);
signal signal_bus_2_full_awprot : std_logic_vector(2 downto 0);
signal signal_bus_2_full_awqos : std_logic_vector(3 downto 0);
signal signal_bus_2_full_awregion : std_logic_vector(3 downto 0);
signal signal_bus_2_full_awvalid : std_logic;
signal signal_bus_2_full_awready : std_logic;
signal signal_bus_2_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_2_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal signal_bus_2_full_wlast : std_logic;
signal signal_bus_2_full_wvalid : std_logic;
signal signal_bus_2_full_wready : std_logic;
signal signal_bus_2_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_2_full_bresp : std_logic_vector(1 downto 0);
signal signal_bus_2_full_bvalid : std_logic;
signal signal_bus_2_full_bready : std_logic;
signal signal_bus_2_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_2_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_2_full_arlen : std_logic_vector(7 downto 0);
signal signal_bus_2_full_arsize : std_logic_vector(2 downto 0);
signal signal_bus_2_full_arburst : std_logic_vector(1 downto 0);
signal signal_bus_2_full_arlock : std_logic;
signal signal_bus_2_full_arcache : std_logic_vector(3 downto 0);
signal signal_bus_2_full_arprot : std_logic_vector(2 downto 0);
signal signal_bus_2_full_arqos : std_logic_vector(3 downto 0);
signal signal_bus_2_full_arregion : std_logic_vector(3 downto 0);
signal signal_bus_2_full_arvalid : std_logic;
signal signal_bus_2_full_arready : std_logic;
signal signal_bus_2_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal signal_bus_2_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_2_full_rresp : std_logic_vector(1 downto 0);
signal signal_bus_2_full_rlast : std_logic;
signal signal_bus_2_full_rvalid : std_logic;
signal signal_bus_2_full_rready : std_logic;
signal timer_bus_2_full_awid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_2_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_2_full_awlen : std_logic_vector(7 downto 0);
signal timer_bus_2_full_awsize : std_logic_vector(2 downto 0);
signal timer_bus_2_full_awburst : std_logic_vector(1 downto 0);
signal timer_bus_2_full_awlock : std_logic;
signal timer_bus_2_full_awcache : std_logic_vector(3 downto 0);
signal timer_bus_2_full_awprot : std_logic_vector(2 downto 0);
signal timer_bus_2_full_awqos : std_logic_vector(3 downto 0);
signal timer_bus_2_full_awregion : std_logic_vector(3 downto 0);
signal timer_bus_2_full_awvalid : std_logic;
signal timer_bus_2_full_awready : std_logic;
signal timer_bus_2_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_2_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_bus_2_full_wlast : std_logic;
signal timer_bus_2_full_wvalid : std_logic;
signal timer_bus_2_full_wready : std_logic;
signal timer_bus_2_full_bid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_2_full_bresp : std_logic_vector(1 downto 0);
signal timer_bus_2_full_bvalid : std_logic;
signal timer_bus_2_full_bready : std_logic;
signal timer_bus_2_full_arid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_2_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_2_full_arlen : std_logic_vector(7 downto 0);
signal timer_bus_2_full_arsize : std_logic_vector(2 downto 0);
signal timer_bus_2_full_arburst : std_logic_vector(1 downto 0);
signal timer_bus_2_full_arlock : std_logic;
signal timer_bus_2_full_arcache : std_logic_vector(3 downto 0);
signal timer_bus_2_full_arprot : std_logic_vector(2 downto 0);
signal timer_bus_2_full_arqos : std_logic_vector(3 downto 0);
signal timer_bus_2_full_arregion : std_logic_vector(3 downto 0);
signal timer_bus_2_full_arvalid : std_logic;
signal timer_bus_2_full_arready : std_logic;
signal timer_bus_2_full_rid : std_logic_vector(axi_cpu_bus_master_id_width-1 downto 0);
signal timer_bus_2_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_2_full_rresp : std_logic_vector(1 downto 0);
signal timer_bus_2_full_rlast : std_logic;
signal timer_bus_2_full_rvalid : std_logic;
signal timer_bus_2_full_rready : std_logic;
--------------------------------------
-- CPUID GPIO AXI Full2Lite Signals --
--------------------------------------
signal cpuid_gpio_bus_0_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_0_lite_awprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_0_lite_awvalid : std_logic;
signal cpuid_gpio_bus_0_lite_awready : std_logic;
signal cpuid_gpio_bus_0_lite_wvalid : std_logic;
signal cpuid_gpio_bus_0_lite_wready : std_logic;
signal cpuid_gpio_bus_0_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_0_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpuid_gpio_bus_0_lite_bvalid : std_logic;
signal cpuid_gpio_bus_0_lite_bready : std_logic;
signal cpuid_gpio_bus_0_lite_bresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_0_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_0_lite_arprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_0_lite_arvalid : std_logic;
signal cpuid_gpio_bus_0_lite_arready : std_logic;
signal cpuid_gpio_bus_0_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_0_lite_rvalid : std_logic;
signal cpuid_gpio_bus_0_lite_rready : std_logic;
signal cpuid_gpio_bus_0_lite_rresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_1_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_1_lite_awprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_1_lite_awvalid : std_logic;
signal cpuid_gpio_bus_1_lite_awready : std_logic;
signal cpuid_gpio_bus_1_lite_wvalid : std_logic;
signal cpuid_gpio_bus_1_lite_wready : std_logic;
signal cpuid_gpio_bus_1_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_1_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpuid_gpio_bus_1_lite_bvalid : std_logic;
signal cpuid_gpio_bus_1_lite_bready : std_logic;
signal cpuid_gpio_bus_1_lite_bresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_1_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_1_lite_arprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_1_lite_arvalid : std_logic;
signal cpuid_gpio_bus_1_lite_arready : std_logic;
signal cpuid_gpio_bus_1_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_1_lite_rvalid : std_logic;
signal cpuid_gpio_bus_1_lite_rready : std_logic;
signal cpuid_gpio_bus_1_lite_rresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_2_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_2_lite_awprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_2_lite_awvalid : std_logic;
signal cpuid_gpio_bus_2_lite_awready : std_logic;
signal cpuid_gpio_bus_2_lite_wvalid : std_logic;
signal cpuid_gpio_bus_2_lite_wready : std_logic;
signal cpuid_gpio_bus_2_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_2_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpuid_gpio_bus_2_lite_bvalid : std_logic;
signal cpuid_gpio_bus_2_lite_bready : std_logic;
signal cpuid_gpio_bus_2_lite_bresp : std_logic_vector(1 downto 0);
signal cpuid_gpio_bus_2_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpuid_gpio_bus_2_lite_arprot : std_logic_vector(2 downto 0);
signal cpuid_gpio_bus_2_lite_arvalid : std_logic;
signal cpuid_gpio_bus_2_lite_arready : std_logic;
signal cpuid_gpio_bus_2_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpuid_gpio_bus_2_lite_rvalid : std_logic;
signal cpuid_gpio_bus_2_lite_rready : std_logic;
signal cpuid_gpio_bus_2_lite_rresp : std_logic_vector(1 downto 0);
-----------------------------------
-- CPU INT AXI Full2Lite Signals --
-----------------------------------
signal int_bus_0_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_0_lite_awprot : std_logic_vector(2 downto 0);
signal int_bus_0_lite_awvalid : std_logic;
signal int_bus_0_lite_awready : std_logic;
signal int_bus_0_lite_wvalid : std_logic;
signal int_bus_0_lite_wready : std_logic;
signal int_bus_0_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_0_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_bus_0_lite_bvalid : std_logic;
signal int_bus_0_lite_bready : std_logic;
signal int_bus_0_lite_bresp : std_logic_vector(1 downto 0);
signal int_bus_0_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_0_lite_arprot : std_logic_vector(2 downto 0);
signal int_bus_0_lite_arvalid : std_logic;
signal int_bus_0_lite_arready : std_logic;
signal int_bus_0_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_0_lite_rvalid : std_logic;
signal int_bus_0_lite_rready : std_logic;
signal int_bus_0_lite_rresp : std_logic_vector(1 downto 0);
signal int_bus_1_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_1_lite_awprot : std_logic_vector(2 downto 0);
signal int_bus_1_lite_awvalid : std_logic;
signal int_bus_1_lite_awready : std_logic;
signal int_bus_1_lite_wvalid : std_logic;
signal int_bus_1_lite_wready : std_logic;
signal int_bus_1_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_1_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_bus_1_lite_bvalid : std_logic;
signal int_bus_1_lite_bready : std_logic;
signal int_bus_1_lite_bresp : std_logic_vector(1 downto 0);
signal int_bus_1_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_1_lite_arprot : std_logic_vector(2 downto 0);
signal int_bus_1_lite_arvalid : std_logic;
signal int_bus_1_lite_arready : std_logic;
signal int_bus_1_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_1_lite_rvalid : std_logic;
signal int_bus_1_lite_rready : std_logic;
signal int_bus_1_lite_rresp : std_logic_vector(1 downto 0);
signal int_bus_2_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_2_lite_awprot : std_logic_vector(2 downto 0);
signal int_bus_2_lite_awvalid : std_logic;
signal int_bus_2_lite_awready : std_logic;
signal int_bus_2_lite_wvalid : std_logic;
signal int_bus_2_lite_wready : std_logic;
signal int_bus_2_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_2_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_bus_2_lite_bvalid : std_logic;
signal int_bus_2_lite_bready : std_logic;
signal int_bus_2_lite_bresp : std_logic_vector(1 downto 0);
signal int_bus_2_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_bus_2_lite_arprot : std_logic_vector(2 downto 0);
signal int_bus_2_lite_arvalid : std_logic;
signal int_bus_2_lite_arready : std_logic;
signal int_bus_2_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_bus_2_lite_rvalid : std_logic;
signal int_bus_2_lite_rready : std_logic;
signal int_bus_2_lite_rresp : std_logic_vector(1 downto 0);
--------------------------------------
-- CPU Signal AXI Full2Lite Signals --
--------------------------------------
signal signal_bus_0_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_0_lite_awprot : std_logic_vector(2 downto 0);
signal signal_bus_0_lite_awvalid : std_logic;
signal signal_bus_0_lite_awready : std_logic;
signal signal_bus_0_lite_wvalid : std_logic;
signal signal_bus_0_lite_wready : std_logic;
signal signal_bus_0_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_0_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal signal_bus_0_lite_bvalid : std_logic;
signal signal_bus_0_lite_bready : std_logic;
signal signal_bus_0_lite_bresp : std_logic_vector(1 downto 0);
signal signal_bus_0_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_0_lite_arprot : std_logic_vector(2 downto 0);
signal signal_bus_0_lite_arvalid : std_logic;
signal signal_bus_0_lite_arready : std_logic;
signal signal_bus_0_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_0_lite_rvalid : std_logic;
signal signal_bus_0_lite_rready : std_logic;
signal signal_bus_0_lite_rresp : std_logic_vector(1 downto 0);
signal signal_bus_1_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_1_lite_awprot : std_logic_vector(2 downto 0);
signal signal_bus_1_lite_awvalid : std_logic;
signal signal_bus_1_lite_awready : std_logic;
signal signal_bus_1_lite_wvalid : std_logic;
signal signal_bus_1_lite_wready : std_logic;
signal signal_bus_1_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_1_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal signal_bus_1_lite_bvalid : std_logic;
signal signal_bus_1_lite_bready : std_logic;
signal signal_bus_1_lite_bresp : std_logic_vector(1 downto 0);
signal signal_bus_1_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_1_lite_arprot : std_logic_vector(2 downto 0);
signal signal_bus_1_lite_arvalid : std_logic;
signal signal_bus_1_lite_arready : std_logic;
signal signal_bus_1_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_1_lite_rvalid : std_logic;
signal signal_bus_1_lite_rready : std_logic;
signal signal_bus_1_lite_rresp : std_logic_vector(1 downto 0);
signal signal_bus_2_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_2_lite_awprot : std_logic_vector(2 downto 0);
signal signal_bus_2_lite_awvalid : std_logic;
signal signal_bus_2_lite_awready : std_logic;
signal signal_bus_2_lite_wvalid : std_logic;
signal signal_bus_2_lite_wready : std_logic;
signal signal_bus_2_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_2_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal signal_bus_2_lite_bvalid : std_logic;
signal signal_bus_2_lite_bready : std_logic;
signal signal_bus_2_lite_bresp : std_logic_vector(1 downto 0);
signal signal_bus_2_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal signal_bus_2_lite_arprot : std_logic_vector(2 downto 0);
signal signal_bus_2_lite_arvalid : std_logic;
signal signal_bus_2_lite_arready : std_logic;
signal signal_bus_2_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal signal_bus_2_lite_rvalid : std_logic;
signal signal_bus_2_lite_rready : std_logic;
signal signal_bus_2_lite_rresp : std_logic_vector(1 downto 0);
-------------------------------------
-- CPU Timer AXI Full2Lite Signals --
-------------------------------------
signal timer_bus_0_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_0_lite_awprot : std_logic_vector(2 downto 0);
signal timer_bus_0_lite_awvalid : std_logic;
signal timer_bus_0_lite_awready : std_logic;
signal timer_bus_0_lite_wvalid : std_logic;
signal timer_bus_0_lite_wready : std_logic;
signal timer_bus_0_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_0_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_bus_0_lite_bvalid : std_logic;
signal timer_bus_0_lite_bready : std_logic;
signal timer_bus_0_lite_bresp : std_logic_vector(1 downto 0);
signal timer_bus_0_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_0_lite_arprot : std_logic_vector(2 downto 0);
signal timer_bus_0_lite_arvalid : std_logic;
signal timer_bus_0_lite_arready : std_logic;
signal timer_bus_0_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_0_lite_rvalid : std_logic;
signal timer_bus_0_lite_rready : std_logic;
signal timer_bus_0_lite_rresp : std_logic_vector(1 downto 0);
signal timer_bus_1_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_1_lite_awprot : std_logic_vector(2 downto 0);
signal timer_bus_1_lite_awvalid : std_logic;
signal timer_bus_1_lite_awready : std_logic;
signal timer_bus_1_lite_wvalid : std_logic;
signal timer_bus_1_lite_wready : std_logic;
signal timer_bus_1_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_1_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_bus_1_lite_bvalid : std_logic;
signal timer_bus_1_lite_bready : std_logic;
signal timer_bus_1_lite_bresp : std_logic_vector(1 downto 0);
signal timer_bus_1_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_1_lite_arprot : std_logic_vector(2 downto 0);
signal timer_bus_1_lite_arvalid : std_logic;
signal timer_bus_1_lite_arready : std_logic;
signal timer_bus_1_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_1_lite_rvalid : std_logic;
signal timer_bus_1_lite_rready : std_logic;
signal timer_bus_1_lite_rresp : std_logic_vector(1 downto 0);
signal timer_bus_2_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_2_lite_awprot : std_logic_vector(2 downto 0);
signal timer_bus_2_lite_awvalid : std_logic;
signal timer_bus_2_lite_awready : std_logic;
signal timer_bus_2_lite_wvalid : std_logic;
signal timer_bus_2_lite_wready : std_logic;
signal timer_bus_2_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_2_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_bus_2_lite_bvalid : std_logic;
signal timer_bus_2_lite_bready : std_logic;
signal timer_bus_2_lite_bresp : std_logic_vector(1 downto 0);
signal timer_bus_2_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_bus_2_lite_arprot : std_logic_vector(2 downto 0);
signal timer_bus_2_lite_arvalid : std_logic;
signal timer_bus_2_lite_arready : std_logic;
signal timer_bus_2_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_bus_2_lite_rvalid : std_logic;
signal timer_bus_2_lite_rready : std_logic;
signal timer_bus_2_lite_rresp : std_logic_vector(1 downto 0);
---------------------------------------------
-- Main Interconnect AXI Full2Lite Signals --
---------------------------------------------
signal int_axi_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_axi_lite_awprot : std_logic_vector(2 downto 0);
signal int_axi_lite_awvalid : std_logic;
signal int_axi_lite_awready : std_logic;
signal int_axi_lite_wvalid : std_logic;
signal int_axi_lite_wready : std_logic;
signal int_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_axi_lite_bvalid : std_logic;
signal int_axi_lite_bready : std_logic;
signal int_axi_lite_bresp : std_logic_vector(1 downto 0);
signal int_axi_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_axi_lite_arprot : std_logic_vector(2 downto 0);
signal int_axi_lite_arvalid : std_logic;
signal int_axi_lite_arready : std_logic;
signal int_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_axi_lite_rvalid : std_logic;
signal int_axi_lite_rready : std_logic;
signal int_axi_lite_rresp : std_logic_vector(1 downto 0);
signal timer_axi_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_axi_lite_awprot : std_logic_vector(2 downto 0);
signal timer_axi_lite_awvalid : std_logic;
signal timer_axi_lite_awready : std_logic;
signal timer_axi_lite_wvalid : std_logic;
signal timer_axi_lite_wready : std_logic;
signal timer_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_axi_lite_bvalid : std_logic;
signal timer_axi_lite_bready : std_logic;
signal timer_axi_lite_bresp : std_logic_vector(1 downto 0);
signal timer_axi_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_axi_lite_arprot : std_logic_vector(2 downto 0);
signal timer_axi_lite_arvalid : std_logic;
signal timer_axi_lite_arready : std_logic;
signal timer_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_axi_lite_rvalid : std_logic;
signal timer_axi_lite_rready : std_logic;
signal timer_axi_lite_rresp : std_logic_vector(1 downto 0);
signal gpio_axi_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal gpio_axi_lite_awprot : std_logic_vector(2 downto 0);
signal gpio_axi_lite_awvalid : std_logic;
signal gpio_axi_lite_awready : std_logic;
signal gpio_axi_lite_wvalid : std_logic;
signal gpio_axi_lite_wready : std_logic;
signal gpio_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal gpio_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal gpio_axi_lite_bvalid : std_logic;
signal gpio_axi_lite_bready : std_logic;
signal gpio_axi_lite_bresp : std_logic_vector(1 downto 0);
signal gpio_axi_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal gpio_axi_lite_arprot : std_logic_vector(2 downto 0);
signal gpio_axi_lite_arvalid : std_logic;
signal gpio_axi_lite_arready : std_logic;
signal gpio_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal gpio_axi_lite_rvalid : std_logic;
signal gpio_axi_lite_rready : std_logic;
signal gpio_axi_lite_rresp : std_logic_vector(1 downto 0);
signal uart_axi_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal uart_axi_lite_awprot : std_logic_vector(2 downto 0);
signal uart_axi_lite_awvalid : std_logic;
signal uart_axi_lite_awready : std_logic;
signal uart_axi_lite_wvalid : std_logic;
signal uart_axi_lite_wready : std_logic;
signal uart_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal uart_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal uart_axi_lite_bvalid : std_logic;
signal uart_axi_lite_bready : std_logic;
signal uart_axi_lite_bresp : std_logic_vector(1 downto 0);
signal uart_axi_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal uart_axi_lite_arprot : std_logic_vector(2 downto 0);
signal uart_axi_lite_arvalid : std_logic;
signal uart_axi_lite_arready : std_logic;
signal uart_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal uart_axi_lite_rvalid : std_logic;
signal uart_axi_lite_rready : std_logic;
signal uart_axi_lite_rresp : std_logic_vector(1 downto 0);
signal lock_axi_lite_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal lock_axi_lite_awprot : std_logic_vector(2 downto 0);
signal lock_axi_lite_awvalid : std_logic;
signal lock_axi_lite_awready : std_logic;
signal lock_axi_lite_wvalid : std_logic;
signal lock_axi_lite_wready : std_logic;
signal lock_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal lock_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal lock_axi_lite_bvalid : std_logic;
signal lock_axi_lite_bready : std_logic;
signal lock_axi_lite_bresp : std_logic_vector(1 downto 0);
signal lock_axi_lite_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal lock_axi_lite_arprot : std_logic_vector(2 downto 0);
signal lock_axi_lite_arvalid : std_logic;
signal lock_axi_lite_arready : std_logic;
signal lock_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal lock_axi_lite_rvalid : std_logic;
signal lock_axi_lite_rready : std_logic;
signal lock_axi_lite_rresp : std_logic_vector(1 downto 0);
------------------------
-- Peripheral Signals --
------------------------
signal cpu_int : std_logic;
signal dev_ints : std_logic_vector(default_interrupt_total-1 downto 0) := (others=>'0');
signal cpu_0_int : std_logic;
signal dev_0_ints : std_logic_vector(default_interrupt_total-1 downto 0) := (others=>'0');
signal cpu_1_int : std_logic;
signal dev_1_ints : std_logic_vector(default_interrupt_total-1 downto 0) := (others=>'0');
signal cpu_2_int : std_logic;
signal dev_2_ints : std_logic_vector(default_interrupt_total-1 downto 0) := (others=>'0');
signal sig_0_1 : std_logic;
signal sig_1_2 : std_logic;
begin
ram_axi_full_arlock_slv(0) <= ram_axi_full_arlock;
ram_axi_full_awlock_slv(0) <= ram_axi_full_awlock;
ram_axi_full_awid_ext(axi_master_id_width-1 downto 0) <= ram_axi_full_awid;
ram_axi_full_bid_ext(axi_master_id_width-1 downto 0) <= ram_axi_full_bid;
ram_axi_full_arid_ext(axi_master_id_width-1 downto 0) <= ram_axi_full_arid;
ram_axi_full_rid_ext(axi_master_id_width-1 downto 0) <= ram_axi_full_rid;
-----------------
-- ID samplers --
-----------------
process (aclk)
begin
if rising_edge (aclk) then
if boot_bram_axi_full_awvalid='1' and boot_bram_axi_full_awready='1' then
boot_bram_axi_full_bid <= boot_bram_axi_full_awid;
end if;
if boot_bram_axi_full_arvalid='1' and boot_bram_axi_full_arready='1' then
boot_bram_axi_full_rid <= boot_bram_axi_full_arid;
end if;
if upper_ext=false then
if ram_axi_full_awvalid='1'and ram_axi_full_awready='1' then
ram_axi_full_bid <= ram_axi_full_awid;
end if;
if ram_axi_full_arvalid='1' and ram_axi_full_arready='1' then
ram_axi_full_rid <= ram_axi_full_arid;
end if;
end if;
end if;
end process;
------------------------------
-- Boot Bram Instantiations --
------------------------------
boot_bram_axi_bram_ctrl_0_inst : axi_bram_ctrl_0
port map (
s_axi_aclk => aclk,
s_axi_aresetn => peripheral_aresetn(0),
s_axi_awaddr => boot_bram_axi_full_awaddr(bram_address_width-1 downto 0),
s_axi_awlen => boot_bram_axi_full_awlen,
s_axi_awsize => boot_bram_axi_full_awsize,
s_axi_awburst => boot_bram_axi_full_awburst,
s_axi_awlock => boot_bram_axi_full_awlock,
s_axi_awcache => boot_bram_axi_full_awcache,
s_axi_awprot => boot_bram_axi_full_awprot,
s_axi_awvalid => boot_bram_axi_full_awvalid,
s_axi_awready => boot_bram_axi_full_awready,
s_axi_wdata => boot_bram_axi_full_wdata,
s_axi_wstrb => boot_bram_axi_full_wstrb,
s_axi_wlast => boot_bram_axi_full_wlast,
s_axi_wvalid => boot_bram_axi_full_wvalid,
s_axi_wready => boot_bram_axi_full_wready,
s_axi_bresp => boot_bram_axi_full_bresp,
s_axi_bvalid => boot_bram_axi_full_bvalid,
s_axi_bready => boot_bram_axi_full_bready,
s_axi_araddr => boot_bram_axi_full_araddr(bram_address_width-1 downto 0),
s_axi_arlen => boot_bram_axi_full_arlen,
s_axi_arsize => boot_bram_axi_full_arsize,
s_axi_arburst => boot_bram_axi_full_arburst,
s_axi_arlock => boot_bram_axi_full_arlock,
s_axi_arcache => boot_bram_axi_full_arcache,
s_axi_arprot => boot_bram_axi_full_arprot,
s_axi_arvalid => boot_bram_axi_full_arvalid,
s_axi_arready => boot_bram_axi_full_arready,
s_axi_rdata => boot_bram_axi_full_rdata,
s_axi_rresp => boot_bram_axi_full_rresp,
s_axi_rlast => boot_bram_axi_full_rlast,
s_axi_rvalid => boot_bram_axi_full_rvalid,
s_axi_rready => boot_bram_axi_full_rready,
bram_rst_a => boot_bram_rst_a,
bram_clk_a => boot_bram_clk_a,
bram_en_a => boot_bram_en_a,
bram_we_a => boot_bram_we_a,
bram_addr_a => boot_bram_addr_a,
bram_wrdata_a => boot_bram_wrdata_a,
bram_rddata_a => boot_bram_rddata_a);
boot_bram_inst : bram
generic map (
select_app => lower_app,
address_width => bram_address_width,
data_width => bram_data_width,
bram_depth => bram_bram_depth)
port map (
bram_rst_a => boot_bram_rst_a,
bram_clk_a => boot_bram_clk_a,
bram_en_a => boot_bram_en_a,
bram_we_a => boot_bram_we_a,
bram_addr_a => boot_bram_addr_a,
bram_wrdata_a => boot_bram_wrdata_a,
bram_rddata_a => boot_bram_rddata_a);
-------------------------------------
-- Main Memory and Synchronization --
-------------------------------------
gen_ext_mm :
if upper_ext=true generate
bd_wrapper_inst : bd_wrapper
port map (
DDR2_addr => DDR2_addr,
DDR2_ba => DDR2_ba,
DDR2_cas_n => DDR2_cas_n,
DDR2_ck_n => DDR2_ck_n,
DDR2_ck_p => DDR2_ck_p,
DDR2_cke => DDR2_cke,
DDR2_cs_n => DDR2_cs_n,
DDR2_dm => DDR2_dm,
DDR2_dq => DDR2_dq,
DDR2_dqs_n => DDR2_dqs_n,
DDR2_dqs_p => DDR2_dqs_p,
DDR2_odt => DDR2_odt,
DDR2_ras_n => DDR2_ras_n,
DDR2_we_n => DDR2_we_n,
S00_AXI_araddr => ram_axi_full_araddr,
S00_AXI_arburst => ram_axi_full_arburst,
S00_AXI_arcache => ram_axi_full_arcache,
S00_AXI_arid => ram_axi_full_arid_ext,
S00_AXI_arlen => ram_axi_full_arlen,
S00_AXI_arlock => ram_axi_full_arlock_slv,
S00_AXI_arprot => ram_axi_full_arprot,
S00_AXI_arqos => ram_axi_full_arqos,
S00_AXI_arready => ram_axi_full_arready,
S00_AXI_arregion => ram_axi_full_arregion,
S00_AXI_arsize => ram_axi_full_arsize,
S00_AXI_arvalid => ram_axi_full_arvalid,
S00_AXI_awaddr => ram_axi_full_awaddr,
S00_AXI_awburst => ram_axi_full_awburst,
S00_AXI_awcache => ram_axi_full_awcache,
S00_AXI_awid => ram_axi_full_awid_ext,
S00_AXI_awlen => ram_axi_full_awlen,
S00_AXI_awlock => ram_axi_full_awlock_slv,
S00_AXI_awprot => ram_axi_full_awprot,
S00_AXI_awqos => ram_axi_full_awqos,
S00_AXI_awready => ram_axi_full_awready,
S00_AXI_awregion => ram_axi_full_awregion,
S00_AXI_awsize => ram_axi_full_awsize,
S00_AXI_awvalid => ram_axi_full_awvalid,
S00_AXI_bid => ram_axi_full_bid_ext,
S00_AXI_bready => ram_axi_full_bready,
S00_AXI_bresp => ram_axi_full_bresp,
S00_AXI_bvalid => ram_axi_full_bvalid,
S00_AXI_rdata => ram_axi_full_rdata,
S00_AXI_rid => ram_axi_full_rid_ext,
S00_AXI_rlast => ram_axi_full_rlast,
S00_AXI_rready => ram_axi_full_rready,
S00_AXI_rresp => ram_axi_full_rresp,
S00_AXI_rvalid => ram_axi_full_rvalid,
S00_AXI_wdata => ram_axi_full_wdata,
S00_AXI_wlast => ram_axi_full_wlast,
S00_AXI_wready => ram_axi_full_wready,
S00_AXI_wstrb => ram_axi_full_wstrb,
S00_AXI_wvalid => ram_axi_full_wvalid,
aclk => aclk,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn,
sys_clk_i => sys_clk_i,
sys_rst => sys_rst);
end generate;
gen_int_mm :
if upper_ext=false generate
bd_axi_bram_ctrl_0_inst : axi_bram_ctrl_0
port map (
s_axi_aclk => aclk,
s_axi_aresetn => peripheral_aresetn(0),
s_axi_awaddr => ram_axi_full_awaddr(bram_address_width-1 downto 0),
s_axi_awlen => ram_axi_full_awlen,
s_axi_awsize => ram_axi_full_awsize,
s_axi_awburst => ram_axi_full_awburst,
s_axi_awlock => ram_axi_full_awlock,
s_axi_awcache => ram_axi_full_awcache,
s_axi_awprot => ram_axi_full_awprot,
s_axi_awvalid => ram_axi_full_awvalid,
s_axi_awready => ram_axi_full_awready,
s_axi_wdata => ram_axi_full_wdata,
s_axi_wstrb => ram_axi_full_wstrb,
s_axi_wlast => ram_axi_full_wlast,
s_axi_wvalid => ram_axi_full_wvalid,
s_axi_wready => ram_axi_full_wready,
s_axi_bresp => ram_axi_full_bresp,
s_axi_bvalid => ram_axi_full_bvalid,
s_axi_bready => ram_axi_full_bready,
s_axi_araddr => ram_axi_full_araddr(bram_address_width-1 downto 0),
s_axi_arlen => ram_axi_full_arlen,
s_axi_arsize => ram_axi_full_arsize,
s_axi_arburst => ram_axi_full_arburst,
s_axi_arlock => ram_axi_full_arlock,
s_axi_arcache => ram_axi_full_arcache,
s_axi_arprot => ram_axi_full_arprot,
s_axi_arvalid => ram_axi_full_arvalid,
s_axi_arready => ram_axi_full_arready,
s_axi_rdata => ram_axi_full_rdata,
s_axi_rresp => ram_axi_full_rresp,
s_axi_rlast => ram_axi_full_rlast,
s_axi_rvalid => ram_axi_full_rvalid,
s_axi_rready => ram_axi_full_rready,
bram_rst_a => ram_bram_rst_a,
bram_clk_a => ram_bram_clk_a,
bram_en_a => ram_bram_en_a,
bram_we_a => ram_bram_we_a,
bram_addr_a => ram_bram_addr_a,
bram_wrdata_a => ram_bram_wrdata_a,
bram_rddata_a => ram_bram_rddata_a);
bd_bram_inst : bram
generic map (
select_app => upper_app,
address_width => bram_address_width,
data_width => bram_data_width,
bram_depth => bram_bram_depth)
port map (
bram_rst_a => ram_bram_rst_a,
bram_clk_a => ram_bram_clk_a,
bram_en_a => ram_bram_en_a,
bram_we_a => ram_bram_we_a,
bram_addr_a => ram_bram_addr_a,
bram_wrdata_a => ram_bram_wrdata_a,
bram_rddata_a => ram_bram_rddata_a);
bd_clk_wiz_inst : clk_wiz_0
port map (
aclk => aclk,
resetn => sys_rst,
locked => dcm_locked,
sys_clk_i => sys_clk_i);
bd_proc_sys_reset_inst : proc_sys_reset_0
port map (
slowest_sync_clk => aclk,
ext_reset_in => sys_clk_i,
aux_reset_in => '0',
mb_debug_sys_rst => '0',
dcm_locked => dcm_locked,
mb_reset => open,
bus_struct_reset => open,
peripheral_reset => open,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn);
end generate;
-----------------------
-- Main Interconnect --
-----------------------
plasoc_interconnect_crossbar_wrap_inst : plasoc_interconnect_crossbar_wrap
port map (
cpu_0_s_axi_awid => cpu_0_axi_full_awid,
cpu_0_s_axi_awaddr => cpu_0_axi_full_awaddr,
cpu_0_s_axi_awlen => cpu_0_axi_full_awlen,
cpu_0_s_axi_awsize => cpu_0_axi_full_awsize,
cpu_0_s_axi_awburst => cpu_0_axi_full_awburst,
cpu_0_s_axi_awlock => cpu_0_axi_full_awlock,
cpu_0_s_axi_awcache => cpu_0_axi_full_awcache,
cpu_0_s_axi_awprot => cpu_0_axi_full_awprot,
cpu_0_s_axi_awqos => cpu_0_axi_full_awqos,
cpu_0_s_axi_awregion => cpu_0_axi_full_awregion,
cpu_0_s_axi_awvalid => cpu_0_axi_full_awvalid,
cpu_0_s_axi_awready => cpu_0_axi_full_awready,
cpu_0_s_axi_wdata => cpu_0_axi_full_wdata,
cpu_0_s_axi_wstrb => cpu_0_axi_full_wstrb,
cpu_0_s_axi_wlast => cpu_0_axi_full_wlast,
cpu_0_s_axi_wvalid => cpu_0_axi_full_wvalid,
cpu_0_s_axi_wready => cpu_0_axi_full_wready,
cpu_0_s_axi_bid => cpu_0_axi_full_bid,
cpu_0_s_axi_bresp => cpu_0_axi_full_bresp,
cpu_0_s_axi_bvalid => cpu_0_axi_full_bvalid,
cpu_0_s_axi_bready => cpu_0_axi_full_bready,
cpu_0_s_axi_arid => cpu_0_axi_full_arid,
cpu_0_s_axi_araddr => cpu_0_axi_full_araddr,
cpu_0_s_axi_arlen => cpu_0_axi_full_arlen,
cpu_0_s_axi_arsize => cpu_0_axi_full_arsize,
cpu_0_s_axi_arburst => cpu_0_axi_full_arburst,
cpu_0_s_axi_arlock => cpu_0_axi_full_arlock,
cpu_0_s_axi_arcache => cpu_0_axi_full_arcache,
cpu_0_s_axi_arprot => cpu_0_axi_full_arprot,
cpu_0_s_axi_arqos => cpu_0_axi_full_arqos,
cpu_0_s_axi_arregion => cpu_0_axi_full_arregion,
cpu_0_s_axi_arvalid => cpu_0_axi_full_arvalid,
cpu_0_s_axi_arready => cpu_0_axi_full_arready,
cpu_0_s_axi_rid => cpu_0_axi_full_rid,
cpu_0_s_axi_rdata => cpu_0_axi_full_rdata,
cpu_0_s_axi_rresp => cpu_0_axi_full_rresp,
cpu_0_s_axi_rlast => cpu_0_axi_full_rlast,
cpu_0_s_axi_rvalid => cpu_0_axi_full_rvalid,
cpu_0_s_axi_rready => cpu_0_axi_full_rready,
cpu_1_s_axi_awid => cpu_1_axi_full_awid,
cpu_1_s_axi_awaddr => cpu_1_axi_full_awaddr,
cpu_1_s_axi_awlen => cpu_1_axi_full_awlen,
cpu_1_s_axi_awsize => cpu_1_axi_full_awsize,
cpu_1_s_axi_awburst => cpu_1_axi_full_awburst,
cpu_1_s_axi_awlock => cpu_1_axi_full_awlock,
cpu_1_s_axi_awcache => cpu_1_axi_full_awcache,
cpu_1_s_axi_awprot => cpu_1_axi_full_awprot,
cpu_1_s_axi_awqos => cpu_1_axi_full_awqos,
cpu_1_s_axi_awregion => cpu_1_axi_full_awregion,
cpu_1_s_axi_awvalid => cpu_1_axi_full_awvalid,
cpu_1_s_axi_awready => cpu_1_axi_full_awready,
cpu_1_s_axi_wdata => cpu_1_axi_full_wdata,
cpu_1_s_axi_wstrb => cpu_1_axi_full_wstrb,
cpu_1_s_axi_wlast => cpu_1_axi_full_wlast,
cpu_1_s_axi_wvalid => cpu_1_axi_full_wvalid,
cpu_1_s_axi_wready => cpu_1_axi_full_wready,
cpu_1_s_axi_bid => cpu_1_axi_full_bid,
cpu_1_s_axi_bresp => cpu_1_axi_full_bresp,
cpu_1_s_axi_bvalid => cpu_1_axi_full_bvalid,
cpu_1_s_axi_bready => cpu_1_axi_full_bready,
cpu_1_s_axi_arid => cpu_1_axi_full_arid,
cpu_1_s_axi_araddr => cpu_1_axi_full_araddr,
cpu_1_s_axi_arlen => cpu_1_axi_full_arlen,
cpu_1_s_axi_arsize => cpu_1_axi_full_arsize,
cpu_1_s_axi_arburst => cpu_1_axi_full_arburst,
cpu_1_s_axi_arlock => cpu_1_axi_full_arlock,
cpu_1_s_axi_arcache => cpu_1_axi_full_arcache,
cpu_1_s_axi_arprot => cpu_1_axi_full_arprot,
cpu_1_s_axi_arqos => cpu_1_axi_full_arqos,
cpu_1_s_axi_arregion => cpu_1_axi_full_arregion,
cpu_1_s_axi_arvalid => cpu_1_axi_full_arvalid,
cpu_1_s_axi_arready => cpu_1_axi_full_arready,
cpu_1_s_axi_rid => cpu_1_axi_full_rid,
cpu_1_s_axi_rdata => cpu_1_axi_full_rdata,
cpu_1_s_axi_rresp => cpu_1_axi_full_rresp,
cpu_1_s_axi_rlast => cpu_1_axi_full_rlast,
cpu_1_s_axi_rvalid => cpu_1_axi_full_rvalid,
cpu_1_s_axi_rready => cpu_1_axi_full_rready,
cpu_2_s_axi_awid => cpu_2_axi_full_awid,
cpu_2_s_axi_awaddr => cpu_2_axi_full_awaddr,
cpu_2_s_axi_awlen => cpu_2_axi_full_awlen,
cpu_2_s_axi_awsize => cpu_2_axi_full_awsize,
cpu_2_s_axi_awburst => cpu_2_axi_full_awburst,
cpu_2_s_axi_awlock => cpu_2_axi_full_awlock,
cpu_2_s_axi_awcache => cpu_2_axi_full_awcache,
cpu_2_s_axi_awprot => cpu_2_axi_full_awprot,
cpu_2_s_axi_awqos => cpu_2_axi_full_awqos,
cpu_2_s_axi_awregion => cpu_2_axi_full_awregion,
cpu_2_s_axi_awvalid => cpu_2_axi_full_awvalid,
cpu_2_s_axi_awready => cpu_2_axi_full_awready,
cpu_2_s_axi_wdata => cpu_2_axi_full_wdata,
cpu_2_s_axi_wstrb => cpu_2_axi_full_wstrb,
cpu_2_s_axi_wlast => cpu_2_axi_full_wlast,
cpu_2_s_axi_wvalid => cpu_2_axi_full_wvalid,
cpu_2_s_axi_wready => cpu_2_axi_full_wready,
cpu_2_s_axi_bid => cpu_2_axi_full_bid,
cpu_2_s_axi_bresp => cpu_2_axi_full_bresp,
cpu_2_s_axi_bvalid => cpu_2_axi_full_bvalid,
cpu_2_s_axi_bready => cpu_2_axi_full_bready,
cpu_2_s_axi_arid => cpu_2_axi_full_arid,
cpu_2_s_axi_araddr => cpu_2_axi_full_araddr,
cpu_2_s_axi_arlen => cpu_2_axi_full_arlen,
cpu_2_s_axi_arsize => cpu_2_axi_full_arsize,
cpu_2_s_axi_arburst => cpu_2_axi_full_arburst,
cpu_2_s_axi_arlock => cpu_2_axi_full_arlock,
cpu_2_s_axi_arcache => cpu_2_axi_full_arcache,
cpu_2_s_axi_arprot => cpu_2_axi_full_arprot,
cpu_2_s_axi_arqos => cpu_2_axi_full_arqos,
cpu_2_s_axi_arregion => cpu_2_axi_full_arregion,
cpu_2_s_axi_arvalid => cpu_2_axi_full_arvalid,
cpu_2_s_axi_arready => cpu_2_axi_full_arready,
cpu_2_s_axi_rid => cpu_2_axi_full_rid,
cpu_2_s_axi_rdata => cpu_2_axi_full_rdata,
cpu_2_s_axi_rresp => cpu_2_axi_full_rresp,
cpu_2_s_axi_rlast => cpu_2_axi_full_rlast,
cpu_2_s_axi_rvalid => cpu_2_axi_full_rvalid,
cpu_2_s_axi_rready => cpu_2_axi_full_rready,
boot_bram_m_axi_awid => boot_bram_axi_full_awid,
boot_bram_m_axi_awaddr => boot_bram_axi_full_awaddr,
boot_bram_m_axi_awlen => boot_bram_axi_full_awlen,
boot_bram_m_axi_awsize => boot_bram_axi_full_awsize,
boot_bram_m_axi_awburst => boot_bram_axi_full_awburst,
boot_bram_m_axi_awlock => boot_bram_axi_full_awlock,
boot_bram_m_axi_awcache => boot_bram_axi_full_awcache,
boot_bram_m_axi_awprot => boot_bram_axi_full_awprot,
boot_bram_m_axi_awqos => boot_bram_axi_full_awqos,
boot_bram_m_axi_awregion => boot_bram_axi_full_awregion,
boot_bram_m_axi_awvalid => boot_bram_axi_full_awvalid,
boot_bram_m_axi_awready => boot_bram_axi_full_awready,
boot_bram_m_axi_wdata => boot_bram_axi_full_wdata,
boot_bram_m_axi_wstrb => boot_bram_axi_full_wstrb,
boot_bram_m_axi_wlast => boot_bram_axi_full_wlast,
boot_bram_m_axi_wvalid => boot_bram_axi_full_wvalid,
boot_bram_m_axi_wready => boot_bram_axi_full_wready,
boot_bram_m_axi_bid => boot_bram_axi_full_bid,
boot_bram_m_axi_bresp => boot_bram_axi_full_bresp,
boot_bram_m_axi_bvalid => boot_bram_axi_full_bvalid,
boot_bram_m_axi_bready => boot_bram_axi_full_bready,
boot_bram_m_axi_arid => boot_bram_axi_full_arid,
boot_bram_m_axi_araddr => boot_bram_axi_full_araddr,
boot_bram_m_axi_arlen => boot_bram_axi_full_arlen,
boot_bram_m_axi_arsize => boot_bram_axi_full_arsize,
boot_bram_m_axi_arburst => boot_bram_axi_full_arburst,
boot_bram_m_axi_arlock => boot_bram_axi_full_arlock,
boot_bram_m_axi_arcache => boot_bram_axi_full_arcache,
boot_bram_m_axi_arprot => boot_bram_axi_full_arprot,
boot_bram_m_axi_arqos => boot_bram_axi_full_arqos,
boot_bram_m_axi_arregion => boot_bram_axi_full_arregion,
boot_bram_m_axi_arvalid => boot_bram_axi_full_arvalid,
boot_bram_m_axi_arready => boot_bram_axi_full_arready,
boot_bram_m_axi_rid => boot_bram_axi_full_rid,
boot_bram_m_axi_rdata => boot_bram_axi_full_rdata,
boot_bram_m_axi_rresp => boot_bram_axi_full_rresp,
boot_bram_m_axi_rlast => boot_bram_axi_full_rlast,
boot_bram_m_axi_rvalid => boot_bram_axi_full_rvalid,
boot_bram_m_axi_rready => boot_bram_axi_full_rready,
ram_m_axi_awid => ram_axi_full_awid,
ram_m_axi_awaddr => ram_axi_full_awaddr,
ram_m_axi_awlen => ram_axi_full_awlen,
ram_m_axi_awsize => ram_axi_full_awsize,
ram_m_axi_awburst => ram_axi_full_awburst,
ram_m_axi_awlock => ram_axi_full_awlock,
ram_m_axi_awcache => ram_axi_full_awcache,
ram_m_axi_awprot => ram_axi_full_awprot,
ram_m_axi_awqos => ram_axi_full_awqos,
ram_m_axi_awregion => ram_axi_full_awregion,
ram_m_axi_awvalid => ram_axi_full_awvalid,
ram_m_axi_awready => ram_axi_full_awready,
ram_m_axi_wdata => ram_axi_full_wdata,
ram_m_axi_wstrb => ram_axi_full_wstrb,
ram_m_axi_wlast => ram_axi_full_wlast,
ram_m_axi_wvalid => ram_axi_full_wvalid,
ram_m_axi_wready => ram_axi_full_wready,
ram_m_axi_bid => ram_axi_full_bid,
ram_m_axi_bresp => ram_axi_full_bresp,
ram_m_axi_bvalid => ram_axi_full_bvalid,
ram_m_axi_bready => ram_axi_full_bready,
ram_m_axi_arid => ram_axi_full_arid,
ram_m_axi_araddr => ram_axi_full_araddr,
ram_m_axi_arlen => ram_axi_full_arlen,
ram_m_axi_arsize => ram_axi_full_arsize,
ram_m_axi_arburst => ram_axi_full_arburst,
ram_m_axi_arlock => ram_axi_full_arlock,
ram_m_axi_arcache => ram_axi_full_arcache,
ram_m_axi_arprot => ram_axi_full_arprot,
ram_m_axi_arqos => ram_axi_full_arqos,
ram_m_axi_arregion => ram_axi_full_arregion,
ram_m_axi_arvalid => ram_axi_full_arvalid,
ram_m_axi_arready => ram_axi_full_arready,
ram_m_axi_rid => ram_axi_full_rid,
ram_m_axi_rdata => ram_axi_full_rdata,
ram_m_axi_rresp => ram_axi_full_rresp,
ram_m_axi_rlast => ram_axi_full_rlast,
ram_m_axi_rvalid => ram_axi_full_rvalid,
ram_m_axi_rready => ram_axi_full_rready,
int_m_axi_awid => int_axi_full_awid,
int_m_axi_awaddr => int_axi_full_awaddr,
int_m_axi_awlen => int_axi_full_awlen,
int_m_axi_awsize => int_axi_full_awsize,
int_m_axi_awburst => int_axi_full_awburst,
int_m_axi_awlock => int_axi_full_awlock,
int_m_axi_awcache => int_axi_full_awcache,
int_m_axi_awprot => int_axi_full_awprot,
int_m_axi_awqos => int_axi_full_awqos,
int_m_axi_awregion => int_axi_full_awregion,
int_m_axi_awvalid => int_axi_full_awvalid,
int_m_axi_awready => int_axi_full_awready,
int_m_axi_wdata => int_axi_full_wdata,
int_m_axi_wstrb => int_axi_full_wstrb,
int_m_axi_wlast => int_axi_full_wlast,
int_m_axi_wvalid => int_axi_full_wvalid,
int_m_axi_wready => int_axi_full_wready,
int_m_axi_bid => int_axi_full_bid,
int_m_axi_bresp => int_axi_full_bresp,
int_m_axi_bvalid => int_axi_full_bvalid,
int_m_axi_bready => int_axi_full_bready,
int_m_axi_arid => int_axi_full_arid,
int_m_axi_araddr => int_axi_full_araddr,
int_m_axi_arlen => int_axi_full_arlen,
int_m_axi_arsize => int_axi_full_arsize,
int_m_axi_arburst => int_axi_full_arburst,
int_m_axi_arlock => int_axi_full_arlock,
int_m_axi_arcache => int_axi_full_arcache,
int_m_axi_arprot => int_axi_full_arprot,
int_m_axi_arqos => int_axi_full_arqos,
int_m_axi_arregion => int_axi_full_arregion,
int_m_axi_arvalid => int_axi_full_arvalid,
int_m_axi_arready => int_axi_full_arready,
int_m_axi_rid => int_axi_full_rid,
int_m_axi_rdata => int_axi_full_rdata,
int_m_axi_rresp => int_axi_full_rresp,
int_m_axi_rlast => int_axi_full_rlast,
int_m_axi_rvalid => int_axi_full_rvalid,
int_m_axi_rready => int_axi_full_rready,
timer_m_axi_awid => timer_axi_full_awid,
timer_m_axi_awaddr => timer_axi_full_awaddr,
timer_m_axi_awlen => timer_axi_full_awlen,
timer_m_axi_awsize => timer_axi_full_awsize,
timer_m_axi_awburst => timer_axi_full_awburst,
timer_m_axi_awlock => timer_axi_full_awlock,
timer_m_axi_awcache => timer_axi_full_awcache,
timer_m_axi_awprot => timer_axi_full_awprot,
timer_m_axi_awqos => timer_axi_full_awqos,
timer_m_axi_awregion => timer_axi_full_awregion,
timer_m_axi_awvalid => timer_axi_full_awvalid,
timer_m_axi_awready => timer_axi_full_awready,
timer_m_axi_wdata => timer_axi_full_wdata,
timer_m_axi_wstrb => timer_axi_full_wstrb,
timer_m_axi_wlast => timer_axi_full_wlast,
timer_m_axi_wvalid => timer_axi_full_wvalid,
timer_m_axi_wready => timer_axi_full_wready,
timer_m_axi_bid => timer_axi_full_bid,
timer_m_axi_bresp => timer_axi_full_bresp,
timer_m_axi_bvalid => timer_axi_full_bvalid,
timer_m_axi_bready => timer_axi_full_bready,
timer_m_axi_arid => timer_axi_full_arid,
timer_m_axi_araddr => timer_axi_full_araddr,
timer_m_axi_arlen => timer_axi_full_arlen,
timer_m_axi_arsize => timer_axi_full_arsize,
timer_m_axi_arburst => timer_axi_full_arburst,
timer_m_axi_arlock => timer_axi_full_arlock,
timer_m_axi_arcache => timer_axi_full_arcache,
timer_m_axi_arprot => timer_axi_full_arprot,
timer_m_axi_arqos => timer_axi_full_arqos,
timer_m_axi_arregion => timer_axi_full_arregion,
timer_m_axi_arvalid => timer_axi_full_arvalid,
timer_m_axi_arready => timer_axi_full_arready,
timer_m_axi_rid => timer_axi_full_rid,
timer_m_axi_rdata => timer_axi_full_rdata,
timer_m_axi_rresp => timer_axi_full_rresp,
timer_m_axi_rlast => timer_axi_full_rlast,
timer_m_axi_rvalid => timer_axi_full_rvalid,
timer_m_axi_rready => timer_axi_full_rready,
gpio_m_axi_awid => gpio_axi_full_awid,
gpio_m_axi_awaddr => gpio_axi_full_awaddr,
gpio_m_axi_awlen => gpio_axi_full_awlen,
gpio_m_axi_awsize => gpio_axi_full_awsize,
gpio_m_axi_awburst => gpio_axi_full_awburst,
gpio_m_axi_awlock => gpio_axi_full_awlock,
gpio_m_axi_awcache => gpio_axi_full_awcache,
gpio_m_axi_awprot => gpio_axi_full_awprot,
gpio_m_axi_awqos => gpio_axi_full_awqos,
gpio_m_axi_awregion => gpio_axi_full_awregion,
gpio_m_axi_awvalid => gpio_axi_full_awvalid,
gpio_m_axi_awready => gpio_axi_full_awready,
gpio_m_axi_wdata => gpio_axi_full_wdata,
gpio_m_axi_wstrb => gpio_axi_full_wstrb,
gpio_m_axi_wlast => gpio_axi_full_wlast,
gpio_m_axi_wvalid => gpio_axi_full_wvalid,
gpio_m_axi_wready => gpio_axi_full_wready,
gpio_m_axi_bid => gpio_axi_full_bid,
gpio_m_axi_bresp => gpio_axi_full_bresp,
gpio_m_axi_bvalid => gpio_axi_full_bvalid,
gpio_m_axi_bready => gpio_axi_full_bready,
gpio_m_axi_arid => gpio_axi_full_arid,
gpio_m_axi_araddr => gpio_axi_full_araddr,
gpio_m_axi_arlen => gpio_axi_full_arlen,
gpio_m_axi_arsize => gpio_axi_full_arsize,
gpio_m_axi_arburst => gpio_axi_full_arburst,
gpio_m_axi_arlock => gpio_axi_full_arlock,
gpio_m_axi_arcache => gpio_axi_full_arcache,
gpio_m_axi_arprot => gpio_axi_full_arprot,
gpio_m_axi_arqos => gpio_axi_full_arqos,
gpio_m_axi_arregion => gpio_axi_full_arregion,
gpio_m_axi_arvalid => gpio_axi_full_arvalid,
gpio_m_axi_arready => gpio_axi_full_arready,
gpio_m_axi_rid => gpio_axi_full_rid,
gpio_m_axi_rdata => gpio_axi_full_rdata,
gpio_m_axi_rresp => gpio_axi_full_rresp,
gpio_m_axi_rlast => gpio_axi_full_rlast,
gpio_m_axi_rvalid => gpio_axi_full_rvalid,
gpio_m_axi_rready => gpio_axi_full_rready,
uart_m_axi_awid => uart_axi_full_awid,
uart_m_axi_awaddr => uart_axi_full_awaddr,
uart_m_axi_awlen => uart_axi_full_awlen,
uart_m_axi_awsize => uart_axi_full_awsize,
uart_m_axi_awburst => uart_axi_full_awburst,
uart_m_axi_awlock => uart_axi_full_awlock,
uart_m_axi_awcache => uart_axi_full_awcache,
uart_m_axi_awprot => uart_axi_full_awprot,
uart_m_axi_awqos => uart_axi_full_awqos,
uart_m_axi_awregion => uart_axi_full_awregion,
uart_m_axi_awvalid => uart_axi_full_awvalid,
uart_m_axi_awready => uart_axi_full_awready,
uart_m_axi_wdata => uart_axi_full_wdata,
uart_m_axi_wstrb => uart_axi_full_wstrb,
uart_m_axi_wlast => uart_axi_full_wlast,
uart_m_axi_wvalid => uart_axi_full_wvalid,
uart_m_axi_wready => uart_axi_full_wready,
uart_m_axi_bid => uart_axi_full_bid,
uart_m_axi_bresp => uart_axi_full_bresp,
uart_m_axi_bvalid => uart_axi_full_bvalid,
uart_m_axi_bready => uart_axi_full_bready,
uart_m_axi_arid => uart_axi_full_arid,
uart_m_axi_araddr => uart_axi_full_araddr,
uart_m_axi_arlen => uart_axi_full_arlen,
uart_m_axi_arsize => uart_axi_full_arsize,
uart_m_axi_arburst => uart_axi_full_arburst,
uart_m_axi_arlock => uart_axi_full_arlock,
uart_m_axi_arcache => uart_axi_full_arcache,
uart_m_axi_arprot => uart_axi_full_arprot,
uart_m_axi_arqos => uart_axi_full_arqos,
uart_m_axi_arregion => uart_axi_full_arregion,
uart_m_axi_arvalid => uart_axi_full_arvalid,
uart_m_axi_arready => uart_axi_full_arready,
uart_m_axi_rid => uart_axi_full_rid,
uart_m_axi_rdata => uart_axi_full_rdata,
uart_m_axi_rresp => uart_axi_full_rresp,
uart_m_axi_rlast => uart_axi_full_rlast,
uart_m_axi_rvalid => uart_axi_full_rvalid,
uart_m_axi_rready => uart_axi_full_rready,
lock_m_axi_awid => lock_axi_full_awid,
lock_m_axi_awaddr => lock_axi_full_awaddr,
lock_m_axi_awlen => lock_axi_full_awlen,
lock_m_axi_awsize => lock_axi_full_awsize,
lock_m_axi_awburst => lock_axi_full_awburst,
lock_m_axi_awlock => lock_axi_full_awlock,
lock_m_axi_awcache => lock_axi_full_awcache,
lock_m_axi_awprot => lock_axi_full_awprot,
lock_m_axi_awqos => lock_axi_full_awqos,
lock_m_axi_awregion => lock_axi_full_awregion,
lock_m_axi_awvalid => lock_axi_full_awvalid,
lock_m_axi_awready => lock_axi_full_awready,
lock_m_axi_wdata => lock_axi_full_wdata,
lock_m_axi_wstrb => lock_axi_full_wstrb,
lock_m_axi_wlast => lock_axi_full_wlast,
lock_m_axi_wvalid => lock_axi_full_wvalid,
lock_m_axi_wready => lock_axi_full_wready,
lock_m_axi_bid => lock_axi_full_bid,
lock_m_axi_bresp => lock_axi_full_bresp,
lock_m_axi_bvalid => lock_axi_full_bvalid,
lock_m_axi_bready => lock_axi_full_bready,
lock_m_axi_arid => lock_axi_full_arid,
lock_m_axi_araddr => lock_axi_full_araddr,
lock_m_axi_arlen => lock_axi_full_arlen,
lock_m_axi_arsize => lock_axi_full_arsize,
lock_m_axi_arburst => lock_axi_full_arburst,
lock_m_axi_arlock => lock_axi_full_arlock,
lock_m_axi_arcache => lock_axi_full_arcache,
lock_m_axi_arprot => lock_axi_full_arprot,
lock_m_axi_arqos => lock_axi_full_arqos,
lock_m_axi_arregion => lock_axi_full_arregion,
lock_m_axi_arvalid => lock_axi_full_arvalid,
lock_m_axi_arready => lock_axi_full_arready,
lock_m_axi_rid => lock_axi_full_rid,
lock_m_axi_rdata => lock_axi_full_rdata,
lock_m_axi_rresp => lock_axi_full_rresp,
lock_m_axi_rlast => lock_axi_full_rlast,
lock_m_axi_rvalid => lock_axi_full_rvalid,
lock_m_axi_rready => lock_axi_full_rready,
aclk => aclk, aresetn => interconnect_aresetn(0));
---------------
-- CPU Buses --
---------------
cpu_0_bus_inst : plasoc_cpu_0_crossbar_wrap
port map (
cpu_s_axi_awid => cpu_bus_0_full_awid,
cpu_s_axi_awaddr => cpu_bus_0_full_awaddr,
cpu_s_axi_awlen => cpu_bus_0_full_awlen,
cpu_s_axi_awsize => cpu_bus_0_full_awsize,
cpu_s_axi_awburst => cpu_bus_0_full_awburst,
cpu_s_axi_awlock => cpu_bus_0_full_awlock,
cpu_s_axi_awcache => cpu_bus_0_full_awcache,
cpu_s_axi_awprot => cpu_bus_0_full_awprot,
cpu_s_axi_awqos => cpu_bus_0_full_awqos,
cpu_s_axi_awregion => cpu_bus_0_full_awregion,
cpu_s_axi_awvalid => cpu_bus_0_full_awvalid,
cpu_s_axi_awready => cpu_bus_0_full_awready,
cpu_s_axi_wdata => cpu_bus_0_full_wdata,
cpu_s_axi_wstrb => cpu_bus_0_full_wstrb,
cpu_s_axi_wlast => cpu_bus_0_full_wlast,
cpu_s_axi_wvalid => cpu_bus_0_full_wvalid,
cpu_s_axi_wready => cpu_bus_0_full_wready,
cpu_s_axi_bid => cpu_bus_0_full_bid,
cpu_s_axi_bresp => cpu_bus_0_full_bresp,
cpu_s_axi_bvalid => cpu_bus_0_full_bvalid,
cpu_s_axi_bready => cpu_bus_0_full_bready,
cpu_s_axi_arid => cpu_bus_0_full_arid,
cpu_s_axi_araddr => cpu_bus_0_full_araddr,
cpu_s_axi_arlen => cpu_bus_0_full_arlen,
cpu_s_axi_arsize => cpu_bus_0_full_arsize,
cpu_s_axi_arburst => cpu_bus_0_full_arburst,
cpu_s_axi_arlock => cpu_bus_0_full_arlock,
cpu_s_axi_arcache => cpu_bus_0_full_arcache,
cpu_s_axi_arprot => cpu_bus_0_full_arprot,
cpu_s_axi_arqos => cpu_bus_0_full_arqos,
cpu_s_axi_arregion => cpu_bus_0_full_arregion,
cpu_s_axi_arvalid => cpu_bus_0_full_arvalid,
cpu_s_axi_arready => cpu_bus_0_full_arready,
cpu_s_axi_rid => cpu_bus_0_full_rid,
cpu_s_axi_rdata => cpu_bus_0_full_rdata,
cpu_s_axi_rresp => cpu_bus_0_full_rresp,
cpu_s_axi_rlast => cpu_bus_0_full_rlast,
cpu_s_axi_rvalid => cpu_bus_0_full_rvalid,
cpu_s_axi_rready => cpu_bus_0_full_rready,
ip_m_axi_awid => cpu_0_axi_full_awid,
ip_m_axi_awaddr => cpu_0_axi_full_awaddr,
ip_m_axi_awlen => cpu_0_axi_full_awlen,
ip_m_axi_awsize => cpu_0_axi_full_awsize,
ip_m_axi_awburst => cpu_0_axi_full_awburst,
ip_m_axi_awlock => cpu_0_axi_full_awlock,
ip_m_axi_awcache => cpu_0_axi_full_awcache,
ip_m_axi_awprot => cpu_0_axi_full_awprot,
ip_m_axi_awqos => cpu_0_axi_full_awqos,
ip_m_axi_awregion => cpu_0_axi_full_awregion,
ip_m_axi_awvalid => cpu_0_axi_full_awvalid,
ip_m_axi_awready => cpu_0_axi_full_awready,
ip_m_axi_wdata => cpu_0_axi_full_wdata,
ip_m_axi_wstrb => cpu_0_axi_full_wstrb,
ip_m_axi_wlast => cpu_0_axi_full_wlast,
ip_m_axi_wvalid => cpu_0_axi_full_wvalid,
ip_m_axi_wready => cpu_0_axi_full_wready,
ip_m_axi_bid => cpu_0_axi_full_bid,
ip_m_axi_bresp => cpu_0_axi_full_bresp,
ip_m_axi_bvalid => cpu_0_axi_full_bvalid,
ip_m_axi_bready => cpu_0_axi_full_bready,
ip_m_axi_arid => cpu_0_axi_full_arid,
ip_m_axi_araddr => cpu_0_axi_full_araddr,
ip_m_axi_arlen => cpu_0_axi_full_arlen,
ip_m_axi_arsize => cpu_0_axi_full_arsize,
ip_m_axi_arburst => cpu_0_axi_full_arburst,
ip_m_axi_arlock => cpu_0_axi_full_arlock,
ip_m_axi_arcache => cpu_0_axi_full_arcache,
ip_m_axi_arprot => cpu_0_axi_full_arprot,
ip_m_axi_arqos => cpu_0_axi_full_arqos,
ip_m_axi_arregion => cpu_0_axi_full_arregion,
ip_m_axi_arvalid => cpu_0_axi_full_arvalid,
ip_m_axi_arready => cpu_0_axi_full_arready,
ip_m_axi_rid => cpu_0_axi_full_rid,
ip_m_axi_rdata => cpu_0_axi_full_rdata,
ip_m_axi_rresp => cpu_0_axi_full_rresp,
ip_m_axi_rlast => cpu_0_axi_full_rlast,
ip_m_axi_rvalid => cpu_0_axi_full_rvalid,
ip_m_axi_rready => cpu_0_axi_full_rready,
cpuid_gpio_m_axi_awid => cpuid_gpio_bus_0_full_awid,
cpuid_gpio_m_axi_awaddr => cpuid_gpio_bus_0_full_awaddr,
cpuid_gpio_m_axi_awlen => cpuid_gpio_bus_0_full_awlen,
cpuid_gpio_m_axi_awsize => cpuid_gpio_bus_0_full_awsize,
cpuid_gpio_m_axi_awburst => cpuid_gpio_bus_0_full_awburst,
cpuid_gpio_m_axi_awlock => cpuid_gpio_bus_0_full_awlock,
cpuid_gpio_m_axi_awcache => cpuid_gpio_bus_0_full_awcache,
cpuid_gpio_m_axi_awprot => cpuid_gpio_bus_0_full_awprot,
cpuid_gpio_m_axi_awqos => cpuid_gpio_bus_0_full_awqos,
cpuid_gpio_m_axi_awregion => cpuid_gpio_bus_0_full_awregion,
cpuid_gpio_m_axi_awvalid => cpuid_gpio_bus_0_full_awvalid,
cpuid_gpio_m_axi_awready => cpuid_gpio_bus_0_full_awready,
cpuid_gpio_m_axi_wdata => cpuid_gpio_bus_0_full_wdata,
cpuid_gpio_m_axi_wstrb => cpuid_gpio_bus_0_full_wstrb,
cpuid_gpio_m_axi_wlast => cpuid_gpio_bus_0_full_wlast,
cpuid_gpio_m_axi_wvalid => cpuid_gpio_bus_0_full_wvalid,
cpuid_gpio_m_axi_wready => cpuid_gpio_bus_0_full_wready,
cpuid_gpio_m_axi_bid => cpuid_gpio_bus_0_full_bid,
cpuid_gpio_m_axi_bresp => cpuid_gpio_bus_0_full_bresp,
cpuid_gpio_m_axi_bvalid => cpuid_gpio_bus_0_full_bvalid,
cpuid_gpio_m_axi_bready => cpuid_gpio_bus_0_full_bready,
cpuid_gpio_m_axi_arid => cpuid_gpio_bus_0_full_arid,
cpuid_gpio_m_axi_araddr => cpuid_gpio_bus_0_full_araddr,
cpuid_gpio_m_axi_arlen => cpuid_gpio_bus_0_full_arlen,
cpuid_gpio_m_axi_arsize => cpuid_gpio_bus_0_full_arsize,
cpuid_gpio_m_axi_arburst => cpuid_gpio_bus_0_full_arburst,
cpuid_gpio_m_axi_arlock => cpuid_gpio_bus_0_full_arlock,
cpuid_gpio_m_axi_arcache => cpuid_gpio_bus_0_full_arcache,
cpuid_gpio_m_axi_arprot => cpuid_gpio_bus_0_full_arprot,
cpuid_gpio_m_axi_arqos => cpuid_gpio_bus_0_full_arqos,
cpuid_gpio_m_axi_arregion => cpuid_gpio_bus_0_full_arregion,
cpuid_gpio_m_axi_arvalid => cpuid_gpio_bus_0_full_arvalid,
cpuid_gpio_m_axi_arready => cpuid_gpio_bus_0_full_arready,
cpuid_gpio_m_axi_rid => cpuid_gpio_bus_0_full_rid,
cpuid_gpio_m_axi_rdata => cpuid_gpio_bus_0_full_rdata,
cpuid_gpio_m_axi_rresp => cpuid_gpio_bus_0_full_rresp,
cpuid_gpio_m_axi_rlast => cpuid_gpio_bus_0_full_rlast,
cpuid_gpio_m_axi_rvalid => cpuid_gpio_bus_0_full_rvalid,
cpuid_gpio_m_axi_rready => cpuid_gpio_bus_0_full_rready,
int_m_axi_awid => int_bus_0_full_awid,
int_m_axi_awaddr => int_bus_0_full_awaddr,
int_m_axi_awlen => int_bus_0_full_awlen,
int_m_axi_awsize => int_bus_0_full_awsize,
int_m_axi_awburst => int_bus_0_full_awburst,
int_m_axi_awlock => int_bus_0_full_awlock,
int_m_axi_awcache => int_bus_0_full_awcache,
int_m_axi_awprot => int_bus_0_full_awprot,
int_m_axi_awqos => int_bus_0_full_awqos,
int_m_axi_awregion => int_bus_0_full_awregion,
int_m_axi_awvalid => int_bus_0_full_awvalid,
int_m_axi_awready => int_bus_0_full_awready,
int_m_axi_wdata => int_bus_0_full_wdata,
int_m_axi_wstrb => int_bus_0_full_wstrb,
int_m_axi_wlast => int_bus_0_full_wlast,
int_m_axi_wvalid => int_bus_0_full_wvalid,
int_m_axi_wready => int_bus_0_full_wready,
int_m_axi_bid => int_bus_0_full_bid,
int_m_axi_bresp => int_bus_0_full_bresp,
int_m_axi_bvalid => int_bus_0_full_bvalid,
int_m_axi_bready => int_bus_0_full_bready,
int_m_axi_arid => int_bus_0_full_arid,
int_m_axi_araddr => int_bus_0_full_araddr,
int_m_axi_arlen => int_bus_0_full_arlen,
int_m_axi_arsize => int_bus_0_full_arsize,
int_m_axi_arburst => int_bus_0_full_arburst,
int_m_axi_arlock => int_bus_0_full_arlock,
int_m_axi_arcache => int_bus_0_full_arcache,
int_m_axi_arprot => int_bus_0_full_arprot,
int_m_axi_arqos => int_bus_0_full_arqos,
int_m_axi_arregion => int_bus_0_full_arregion,
int_m_axi_arvalid => int_bus_0_full_arvalid,
int_m_axi_arready => int_bus_0_full_arready,
int_m_axi_rid => int_bus_0_full_rid,
int_m_axi_rdata => int_bus_0_full_rdata,
int_m_axi_rresp => int_bus_0_full_rresp,
int_m_axi_rlast => int_bus_0_full_rlast,
int_m_axi_rvalid => int_bus_0_full_rvalid,
int_m_axi_rready => int_bus_0_full_rready,
signal_m_axi_awid => signal_bus_0_full_awid,
signal_m_axi_awaddr => signal_bus_0_full_awaddr,
signal_m_axi_awlen => signal_bus_0_full_awlen,
signal_m_axi_awsize => signal_bus_0_full_awsize,
signal_m_axi_awburst => signal_bus_0_full_awburst,
signal_m_axi_awlock => signal_bus_0_full_awlock,
signal_m_axi_awcache => signal_bus_0_full_awcache,
signal_m_axi_awprot => signal_bus_0_full_awprot,
signal_m_axi_awqos => signal_bus_0_full_awqos,
signal_m_axi_awregion => signal_bus_0_full_awregion,
signal_m_axi_awvalid => signal_bus_0_full_awvalid,
signal_m_axi_awready => signal_bus_0_full_awready,
signal_m_axi_wdata => signal_bus_0_full_wdata,
signal_m_axi_wstrb => signal_bus_0_full_wstrb,
signal_m_axi_wlast => signal_bus_0_full_wlast,
signal_m_axi_wvalid => signal_bus_0_full_wvalid,
signal_m_axi_wready => signal_bus_0_full_wready,
signal_m_axi_bid => signal_bus_0_full_bid,
signal_m_axi_bresp => signal_bus_0_full_bresp,
signal_m_axi_bvalid => signal_bus_0_full_bvalid,
signal_m_axi_bready => signal_bus_0_full_bready,
signal_m_axi_arid => signal_bus_0_full_arid,
signal_m_axi_araddr => signal_bus_0_full_araddr,
signal_m_axi_arlen => signal_bus_0_full_arlen,
signal_m_axi_arsize => signal_bus_0_full_arsize,
signal_m_axi_arburst => signal_bus_0_full_arburst,
signal_m_axi_arlock => signal_bus_0_full_arlock,
signal_m_axi_arcache => signal_bus_0_full_arcache,
signal_m_axi_arprot => signal_bus_0_full_arprot,
signal_m_axi_arqos => signal_bus_0_full_arqos,
signal_m_axi_arregion => signal_bus_0_full_arregion,
signal_m_axi_arvalid => signal_bus_0_full_arvalid,
signal_m_axi_arready => signal_bus_0_full_arready,
signal_m_axi_rid => signal_bus_0_full_rid,
signal_m_axi_rdata => signal_bus_0_full_rdata,
signal_m_axi_rresp => signal_bus_0_full_rresp,
signal_m_axi_rlast => signal_bus_0_full_rlast,
signal_m_axi_rvalid => signal_bus_0_full_rvalid,
timer_m_axi_awid => timer_bus_0_full_awid,
timer_m_axi_awaddr => timer_bus_0_full_awaddr,
timer_m_axi_awlen => timer_bus_0_full_awlen,
timer_m_axi_awsize => timer_bus_0_full_awsize,
timer_m_axi_awburst => timer_bus_0_full_awburst,
timer_m_axi_awlock => timer_bus_0_full_awlock,
timer_m_axi_awcache => timer_bus_0_full_awcache,
timer_m_axi_awprot => timer_bus_0_full_awprot,
timer_m_axi_awqos => timer_bus_0_full_awqos,
timer_m_axi_awregion => timer_bus_0_full_awregion,
timer_m_axi_awvalid => timer_bus_0_full_awvalid,
timer_m_axi_awready => timer_bus_0_full_awready,
timer_m_axi_wdata => timer_bus_0_full_wdata,
timer_m_axi_wstrb => timer_bus_0_full_wstrb,
timer_m_axi_wlast => timer_bus_0_full_wlast,
timer_m_axi_wvalid => timer_bus_0_full_wvalid,
timer_m_axi_wready => timer_bus_0_full_wready,
timer_m_axi_bid => timer_bus_0_full_bid,
timer_m_axi_bresp => timer_bus_0_full_bresp,
timer_m_axi_bvalid => timer_bus_0_full_bvalid,
timer_m_axi_bready => timer_bus_0_full_bready,
timer_m_axi_arid => timer_bus_0_full_arid,
timer_m_axi_araddr => timer_bus_0_full_araddr,
timer_m_axi_arlen => timer_bus_0_full_arlen,
timer_m_axi_arsize => timer_bus_0_full_arsize,
timer_m_axi_arburst => timer_bus_0_full_arburst,
timer_m_axi_arlock => timer_bus_0_full_arlock,
timer_m_axi_arcache => timer_bus_0_full_arcache,
timer_m_axi_arprot => timer_bus_0_full_arprot,
timer_m_axi_arqos => timer_bus_0_full_arqos,
timer_m_axi_arregion => timer_bus_0_full_arregion,
timer_m_axi_arvalid => timer_bus_0_full_arvalid,
timer_m_axi_arready => timer_bus_0_full_arready,
timer_m_axi_rid => timer_bus_0_full_rid,
timer_m_axi_rdata => timer_bus_0_full_rdata,
timer_m_axi_rresp => timer_bus_0_full_rresp,
timer_m_axi_rlast => timer_bus_0_full_rlast,
timer_m_axi_rvalid => timer_bus_0_full_rvalid,
aclk => aclk, aresetn => peripheral_aresetn(0));
cpu_1_bus_inst : plasoc_cpu_1_crossbar_wrap
port map (
cpu_s_axi_awid => cpu_bus_1_full_awid,
cpu_s_axi_awaddr => cpu_bus_1_full_awaddr,
cpu_s_axi_awlen => cpu_bus_1_full_awlen,
cpu_s_axi_awsize => cpu_bus_1_full_awsize,
cpu_s_axi_awburst => cpu_bus_1_full_awburst,
cpu_s_axi_awlock => cpu_bus_1_full_awlock,
cpu_s_axi_awcache => cpu_bus_1_full_awcache,
cpu_s_axi_awprot => cpu_bus_1_full_awprot,
cpu_s_axi_awqos => cpu_bus_1_full_awqos,
cpu_s_axi_awregion => cpu_bus_1_full_awregion,
cpu_s_axi_awvalid => cpu_bus_1_full_awvalid,
cpu_s_axi_awready => cpu_bus_1_full_awready,
cpu_s_axi_wdata => cpu_bus_1_full_wdata,
cpu_s_axi_wstrb => cpu_bus_1_full_wstrb,
cpu_s_axi_wlast => cpu_bus_1_full_wlast,
cpu_s_axi_wvalid => cpu_bus_1_full_wvalid,
cpu_s_axi_wready => cpu_bus_1_full_wready,
cpu_s_axi_bid => cpu_bus_1_full_bid,
cpu_s_axi_bresp => cpu_bus_1_full_bresp,
cpu_s_axi_bvalid => cpu_bus_1_full_bvalid,
cpu_s_axi_bready => cpu_bus_1_full_bready,
cpu_s_axi_arid => cpu_bus_1_full_arid,
cpu_s_axi_araddr => cpu_bus_1_full_araddr,
cpu_s_axi_arlen => cpu_bus_1_full_arlen,
cpu_s_axi_arsize => cpu_bus_1_full_arsize,
cpu_s_axi_arburst => cpu_bus_1_full_arburst,
cpu_s_axi_arlock => cpu_bus_1_full_arlock,
cpu_s_axi_arcache => cpu_bus_1_full_arcache,
cpu_s_axi_arprot => cpu_bus_1_full_arprot,
cpu_s_axi_arqos => cpu_bus_1_full_arqos,
cpu_s_axi_arregion => cpu_bus_1_full_arregion,
cpu_s_axi_arvalid => cpu_bus_1_full_arvalid,
cpu_s_axi_arready => cpu_bus_1_full_arready,
cpu_s_axi_rid => cpu_bus_1_full_rid,
cpu_s_axi_rdata => cpu_bus_1_full_rdata,
cpu_s_axi_rresp => cpu_bus_1_full_rresp,
cpu_s_axi_rlast => cpu_bus_1_full_rlast,
cpu_s_axi_rvalid => cpu_bus_1_full_rvalid,
cpu_s_axi_rready => cpu_bus_1_full_rready,
ip_m_axi_awid => cpu_1_axi_full_awid,
ip_m_axi_awaddr => cpu_1_axi_full_awaddr,
ip_m_axi_awlen => cpu_1_axi_full_awlen,
ip_m_axi_awsize => cpu_1_axi_full_awsize,
ip_m_axi_awburst => cpu_1_axi_full_awburst,
ip_m_axi_awlock => cpu_1_axi_full_awlock,
ip_m_axi_awcache => cpu_1_axi_full_awcache,
ip_m_axi_awprot => cpu_1_axi_full_awprot,
ip_m_axi_awqos => cpu_1_axi_full_awqos,
ip_m_axi_awregion => cpu_1_axi_full_awregion,
ip_m_axi_awvalid => cpu_1_axi_full_awvalid,
ip_m_axi_awready => cpu_1_axi_full_awready,
ip_m_axi_wdata => cpu_1_axi_full_wdata,
ip_m_axi_wstrb => cpu_1_axi_full_wstrb,
ip_m_axi_wlast => cpu_1_axi_full_wlast,
ip_m_axi_wvalid => cpu_1_axi_full_wvalid,
ip_m_axi_wready => cpu_1_axi_full_wready,
ip_m_axi_bid => cpu_1_axi_full_bid,
ip_m_axi_bresp => cpu_1_axi_full_bresp,
ip_m_axi_bvalid => cpu_1_axi_full_bvalid,
ip_m_axi_bready => cpu_1_axi_full_bready,
ip_m_axi_arid => cpu_1_axi_full_arid,
ip_m_axi_araddr => cpu_1_axi_full_araddr,
ip_m_axi_arlen => cpu_1_axi_full_arlen,
ip_m_axi_arsize => cpu_1_axi_full_arsize,
ip_m_axi_arburst => cpu_1_axi_full_arburst,
ip_m_axi_arlock => cpu_1_axi_full_arlock,
ip_m_axi_arcache => cpu_1_axi_full_arcache,
ip_m_axi_arprot => cpu_1_axi_full_arprot,
ip_m_axi_arqos => cpu_1_axi_full_arqos,
ip_m_axi_arregion => cpu_1_axi_full_arregion,
ip_m_axi_arvalid => cpu_1_axi_full_arvalid,
ip_m_axi_arready => cpu_1_axi_full_arready,
ip_m_axi_rid => cpu_1_axi_full_rid,
ip_m_axi_rdata => cpu_1_axi_full_rdata,
ip_m_axi_rresp => cpu_1_axi_full_rresp,
ip_m_axi_rlast => cpu_1_axi_full_rlast,
ip_m_axi_rvalid => cpu_1_axi_full_rvalid,
ip_m_axi_rready => cpu_1_axi_full_rready,
cpuid_gpio_m_axi_awid => cpuid_gpio_bus_1_full_awid,
cpuid_gpio_m_axi_awaddr => cpuid_gpio_bus_1_full_awaddr,
cpuid_gpio_m_axi_awlen => cpuid_gpio_bus_1_full_awlen,
cpuid_gpio_m_axi_awsize => cpuid_gpio_bus_1_full_awsize,
cpuid_gpio_m_axi_awburst => cpuid_gpio_bus_1_full_awburst,
cpuid_gpio_m_axi_awlock => cpuid_gpio_bus_1_full_awlock,
cpuid_gpio_m_axi_awcache => cpuid_gpio_bus_1_full_awcache,
cpuid_gpio_m_axi_awprot => cpuid_gpio_bus_1_full_awprot,
cpuid_gpio_m_axi_awqos => cpuid_gpio_bus_1_full_awqos,
cpuid_gpio_m_axi_awregion => cpuid_gpio_bus_1_full_awregion,
cpuid_gpio_m_axi_awvalid => cpuid_gpio_bus_1_full_awvalid,
cpuid_gpio_m_axi_awready => cpuid_gpio_bus_1_full_awready,
cpuid_gpio_m_axi_wdata => cpuid_gpio_bus_1_full_wdata,
cpuid_gpio_m_axi_wstrb => cpuid_gpio_bus_1_full_wstrb,
cpuid_gpio_m_axi_wlast => cpuid_gpio_bus_1_full_wlast,
cpuid_gpio_m_axi_wvalid => cpuid_gpio_bus_1_full_wvalid,
cpuid_gpio_m_axi_wready => cpuid_gpio_bus_1_full_wready,
cpuid_gpio_m_axi_bid => cpuid_gpio_bus_1_full_bid,
cpuid_gpio_m_axi_bresp => cpuid_gpio_bus_1_full_bresp,
cpuid_gpio_m_axi_bvalid => cpuid_gpio_bus_1_full_bvalid,
cpuid_gpio_m_axi_bready => cpuid_gpio_bus_1_full_bready,
cpuid_gpio_m_axi_arid => cpuid_gpio_bus_1_full_arid,
cpuid_gpio_m_axi_araddr => cpuid_gpio_bus_1_full_araddr,
cpuid_gpio_m_axi_arlen => cpuid_gpio_bus_1_full_arlen,
cpuid_gpio_m_axi_arsize => cpuid_gpio_bus_1_full_arsize,
cpuid_gpio_m_axi_arburst => cpuid_gpio_bus_1_full_arburst,
cpuid_gpio_m_axi_arlock => cpuid_gpio_bus_1_full_arlock,
cpuid_gpio_m_axi_arcache => cpuid_gpio_bus_1_full_arcache,
cpuid_gpio_m_axi_arprot => cpuid_gpio_bus_1_full_arprot,
cpuid_gpio_m_axi_arqos => cpuid_gpio_bus_1_full_arqos,
cpuid_gpio_m_axi_arregion => cpuid_gpio_bus_1_full_arregion,
cpuid_gpio_m_axi_arvalid => cpuid_gpio_bus_1_full_arvalid,
cpuid_gpio_m_axi_arready => cpuid_gpio_bus_1_full_arready,
cpuid_gpio_m_axi_rid => cpuid_gpio_bus_1_full_rid,
cpuid_gpio_m_axi_rdata => cpuid_gpio_bus_1_full_rdata,
cpuid_gpio_m_axi_rresp => cpuid_gpio_bus_1_full_rresp,
cpuid_gpio_m_axi_rlast => cpuid_gpio_bus_1_full_rlast,
cpuid_gpio_m_axi_rvalid => cpuid_gpio_bus_1_full_rvalid,
cpuid_gpio_m_axi_rready => cpuid_gpio_bus_1_full_rready,
int_m_axi_awid => int_bus_1_full_awid,
int_m_axi_awaddr => int_bus_1_full_awaddr,
int_m_axi_awlen => int_bus_1_full_awlen,
int_m_axi_awsize => int_bus_1_full_awsize,
int_m_axi_awburst => int_bus_1_full_awburst,
int_m_axi_awlock => int_bus_1_full_awlock,
int_m_axi_awcache => int_bus_1_full_awcache,
int_m_axi_awprot => int_bus_1_full_awprot,
int_m_axi_awqos => int_bus_1_full_awqos,
int_m_axi_awregion => int_bus_1_full_awregion,
int_m_axi_awvalid => int_bus_1_full_awvalid,
int_m_axi_awready => int_bus_1_full_awready,
int_m_axi_wdata => int_bus_1_full_wdata,
int_m_axi_wstrb => int_bus_1_full_wstrb,
int_m_axi_wlast => int_bus_1_full_wlast,
int_m_axi_wvalid => int_bus_1_full_wvalid,
int_m_axi_wready => int_bus_1_full_wready,
int_m_axi_bid => int_bus_1_full_bid,
int_m_axi_bresp => int_bus_1_full_bresp,
int_m_axi_bvalid => int_bus_1_full_bvalid,
int_m_axi_bready => int_bus_1_full_bready,
int_m_axi_arid => int_bus_1_full_arid,
int_m_axi_araddr => int_bus_1_full_araddr,
int_m_axi_arlen => int_bus_1_full_arlen,
int_m_axi_arsize => int_bus_1_full_arsize,
int_m_axi_arburst => int_bus_1_full_arburst,
int_m_axi_arlock => int_bus_1_full_arlock,
int_m_axi_arcache => int_bus_1_full_arcache,
int_m_axi_arprot => int_bus_1_full_arprot,
int_m_axi_arqos => int_bus_1_full_arqos,
int_m_axi_arregion => int_bus_1_full_arregion,
int_m_axi_arvalid => int_bus_1_full_arvalid,
int_m_axi_arready => int_bus_1_full_arready,
int_m_axi_rid => int_bus_1_full_rid,
int_m_axi_rdata => int_bus_1_full_rdata,
int_m_axi_rresp => int_bus_1_full_rresp,
int_m_axi_rlast => int_bus_1_full_rlast,
int_m_axi_rvalid => int_bus_1_full_rvalid,
int_m_axi_rready => int_bus_1_full_rready,
signal_m_axi_awid => signal_bus_1_full_awid,
signal_m_axi_awaddr => signal_bus_1_full_awaddr,
signal_m_axi_awlen => signal_bus_1_full_awlen,
signal_m_axi_awsize => signal_bus_1_full_awsize,
signal_m_axi_awburst => signal_bus_1_full_awburst,
signal_m_axi_awlock => signal_bus_1_full_awlock,
signal_m_axi_awcache => signal_bus_1_full_awcache,
signal_m_axi_awprot => signal_bus_1_full_awprot,
signal_m_axi_awqos => signal_bus_1_full_awqos,
signal_m_axi_awregion => signal_bus_1_full_awregion,
signal_m_axi_awvalid => signal_bus_1_full_awvalid,
signal_m_axi_awready => signal_bus_1_full_awready,
signal_m_axi_wdata => signal_bus_1_full_wdata,
signal_m_axi_wstrb => signal_bus_1_full_wstrb,
signal_m_axi_wlast => signal_bus_1_full_wlast,
signal_m_axi_wvalid => signal_bus_1_full_wvalid,
signal_m_axi_wready => signal_bus_1_full_wready,
signal_m_axi_bid => signal_bus_1_full_bid,
signal_m_axi_bresp => signal_bus_1_full_bresp,
signal_m_axi_bvalid => signal_bus_1_full_bvalid,
signal_m_axi_bready => signal_bus_1_full_bready,
signal_m_axi_arid => signal_bus_1_full_arid,
signal_m_axi_araddr => signal_bus_1_full_araddr,
signal_m_axi_arlen => signal_bus_1_full_arlen,
signal_m_axi_arsize => signal_bus_1_full_arsize,
signal_m_axi_arburst => signal_bus_1_full_arburst,
signal_m_axi_arlock => signal_bus_1_full_arlock,
signal_m_axi_arcache => signal_bus_1_full_arcache,
signal_m_axi_arprot => signal_bus_1_full_arprot,
signal_m_axi_arqos => signal_bus_1_full_arqos,
signal_m_axi_arregion => signal_bus_1_full_arregion,
signal_m_axi_arvalid => signal_bus_1_full_arvalid,
signal_m_axi_arready => signal_bus_1_full_arready,
signal_m_axi_rid => signal_bus_1_full_rid,
signal_m_axi_rdata => signal_bus_1_full_rdata,
signal_m_axi_rresp => signal_bus_1_full_rresp,
signal_m_axi_rlast => signal_bus_1_full_rlast,
signal_m_axi_rvalid => signal_bus_1_full_rvalid,
timer_m_axi_awid => timer_bus_1_full_awid,
timer_m_axi_awaddr => timer_bus_1_full_awaddr,
timer_m_axi_awlen => timer_bus_1_full_awlen,
timer_m_axi_awsize => timer_bus_1_full_awsize,
timer_m_axi_awburst => timer_bus_1_full_awburst,
timer_m_axi_awlock => timer_bus_1_full_awlock,
timer_m_axi_awcache => timer_bus_1_full_awcache,
timer_m_axi_awprot => timer_bus_1_full_awprot,
timer_m_axi_awqos => timer_bus_1_full_awqos,
timer_m_axi_awregion => timer_bus_1_full_awregion,
timer_m_axi_awvalid => timer_bus_1_full_awvalid,
timer_m_axi_awready => timer_bus_1_full_awready,
timer_m_axi_wdata => timer_bus_1_full_wdata,
timer_m_axi_wstrb => timer_bus_1_full_wstrb,
timer_m_axi_wlast => timer_bus_1_full_wlast,
timer_m_axi_wvalid => timer_bus_1_full_wvalid,
timer_m_axi_wready => timer_bus_1_full_wready,
timer_m_axi_bid => timer_bus_1_full_bid,
timer_m_axi_bresp => timer_bus_1_full_bresp,
timer_m_axi_bvalid => timer_bus_1_full_bvalid,
timer_m_axi_bready => timer_bus_1_full_bready,
timer_m_axi_arid => timer_bus_1_full_arid,
timer_m_axi_araddr => timer_bus_1_full_araddr,
timer_m_axi_arlen => timer_bus_1_full_arlen,
timer_m_axi_arsize => timer_bus_1_full_arsize,
timer_m_axi_arburst => timer_bus_1_full_arburst,
timer_m_axi_arlock => timer_bus_1_full_arlock,
timer_m_axi_arcache => timer_bus_1_full_arcache,
timer_m_axi_arprot => timer_bus_1_full_arprot,
timer_m_axi_arqos => timer_bus_1_full_arqos,
timer_m_axi_arregion => timer_bus_1_full_arregion,
timer_m_axi_arvalid => timer_bus_1_full_arvalid,
timer_m_axi_arready => timer_bus_1_full_arready,
timer_m_axi_rid => timer_bus_1_full_rid,
timer_m_axi_rdata => timer_bus_1_full_rdata,
timer_m_axi_rresp => timer_bus_1_full_rresp,
timer_m_axi_rlast => timer_bus_1_full_rlast,
timer_m_axi_rvalid => timer_bus_1_full_rvalid,
aclk => aclk, aresetn => peripheral_aresetn(0));
cpu_2_bus_inst : plasoc_cpu_2_crossbar_wrap
port map (
cpu_s_axi_awid => cpu_bus_2_full_awid,
cpu_s_axi_awaddr => cpu_bus_2_full_awaddr,
cpu_s_axi_awlen => cpu_bus_2_full_awlen,
cpu_s_axi_awsize => cpu_bus_2_full_awsize,
cpu_s_axi_awburst => cpu_bus_2_full_awburst,
cpu_s_axi_awlock => cpu_bus_2_full_awlock,
cpu_s_axi_awcache => cpu_bus_2_full_awcache,
cpu_s_axi_awprot => cpu_bus_2_full_awprot,
cpu_s_axi_awqos => cpu_bus_2_full_awqos,
cpu_s_axi_awregion => cpu_bus_2_full_awregion,
cpu_s_axi_awvalid => cpu_bus_2_full_awvalid,
cpu_s_axi_awready => cpu_bus_2_full_awready,
cpu_s_axi_wdata => cpu_bus_2_full_wdata,
cpu_s_axi_wstrb => cpu_bus_2_full_wstrb,
cpu_s_axi_wlast => cpu_bus_2_full_wlast,
cpu_s_axi_wvalid => cpu_bus_2_full_wvalid,
cpu_s_axi_wready => cpu_bus_2_full_wready,
cpu_s_axi_bid => cpu_bus_2_full_bid,
cpu_s_axi_bresp => cpu_bus_2_full_bresp,
cpu_s_axi_bvalid => cpu_bus_2_full_bvalid,
cpu_s_axi_bready => cpu_bus_2_full_bready,
cpu_s_axi_arid => cpu_bus_2_full_arid,
cpu_s_axi_araddr => cpu_bus_2_full_araddr,
cpu_s_axi_arlen => cpu_bus_2_full_arlen,
cpu_s_axi_arsize => cpu_bus_2_full_arsize,
cpu_s_axi_arburst => cpu_bus_2_full_arburst,
cpu_s_axi_arlock => cpu_bus_2_full_arlock,
cpu_s_axi_arcache => cpu_bus_2_full_arcache,
cpu_s_axi_arprot => cpu_bus_2_full_arprot,
cpu_s_axi_arqos => cpu_bus_2_full_arqos,
cpu_s_axi_arregion => cpu_bus_2_full_arregion,
cpu_s_axi_arvalid => cpu_bus_2_full_arvalid,
cpu_s_axi_arready => cpu_bus_2_full_arready,
cpu_s_axi_rid => cpu_bus_2_full_rid,
cpu_s_axi_rdata => cpu_bus_2_full_rdata,
cpu_s_axi_rresp => cpu_bus_2_full_rresp,
cpu_s_axi_rlast => cpu_bus_2_full_rlast,
cpu_s_axi_rvalid => cpu_bus_2_full_rvalid,
cpu_s_axi_rready => cpu_bus_2_full_rready,
ip_m_axi_awid => cpu_2_axi_full_awid,
ip_m_axi_awaddr => cpu_2_axi_full_awaddr,
ip_m_axi_awlen => cpu_2_axi_full_awlen,
ip_m_axi_awsize => cpu_2_axi_full_awsize,
ip_m_axi_awburst => cpu_2_axi_full_awburst,
ip_m_axi_awlock => cpu_2_axi_full_awlock,
ip_m_axi_awcache => cpu_2_axi_full_awcache,
ip_m_axi_awprot => cpu_2_axi_full_awprot,
ip_m_axi_awqos => cpu_2_axi_full_awqos,
ip_m_axi_awregion => cpu_2_axi_full_awregion,
ip_m_axi_awvalid => cpu_2_axi_full_awvalid,
ip_m_axi_awready => cpu_2_axi_full_awready,
ip_m_axi_wdata => cpu_2_axi_full_wdata,
ip_m_axi_wstrb => cpu_2_axi_full_wstrb,
ip_m_axi_wlast => cpu_2_axi_full_wlast,
ip_m_axi_wvalid => cpu_2_axi_full_wvalid,
ip_m_axi_wready => cpu_2_axi_full_wready,
ip_m_axi_bid => cpu_2_axi_full_bid,
ip_m_axi_bresp => cpu_2_axi_full_bresp,
ip_m_axi_bvalid => cpu_2_axi_full_bvalid,
ip_m_axi_bready => cpu_2_axi_full_bready,
ip_m_axi_arid => cpu_2_axi_full_arid,
ip_m_axi_araddr => cpu_2_axi_full_araddr,
ip_m_axi_arlen => cpu_2_axi_full_arlen,
ip_m_axi_arsize => cpu_2_axi_full_arsize,
ip_m_axi_arburst => cpu_2_axi_full_arburst,
ip_m_axi_arlock => cpu_2_axi_full_arlock,
ip_m_axi_arcache => cpu_2_axi_full_arcache,
ip_m_axi_arprot => cpu_2_axi_full_arprot,
ip_m_axi_arqos => cpu_2_axi_full_arqos,
ip_m_axi_arregion => cpu_2_axi_full_arregion,
ip_m_axi_arvalid => cpu_2_axi_full_arvalid,
ip_m_axi_arready => cpu_2_axi_full_arready,
ip_m_axi_rid => cpu_2_axi_full_rid,
ip_m_axi_rdata => cpu_2_axi_full_rdata,
ip_m_axi_rresp => cpu_2_axi_full_rresp,
ip_m_axi_rlast => cpu_2_axi_full_rlast,
ip_m_axi_rvalid => cpu_2_axi_full_rvalid,
ip_m_axi_rready => cpu_2_axi_full_rready,
cpuid_gpio_m_axi_awid => cpuid_gpio_bus_2_full_awid,
cpuid_gpio_m_axi_awaddr => cpuid_gpio_bus_2_full_awaddr,
cpuid_gpio_m_axi_awlen => cpuid_gpio_bus_2_full_awlen,
cpuid_gpio_m_axi_awsize => cpuid_gpio_bus_2_full_awsize,
cpuid_gpio_m_axi_awburst => cpuid_gpio_bus_2_full_awburst,
cpuid_gpio_m_axi_awlock => cpuid_gpio_bus_2_full_awlock,
cpuid_gpio_m_axi_awcache => cpuid_gpio_bus_2_full_awcache,
cpuid_gpio_m_axi_awprot => cpuid_gpio_bus_2_full_awprot,
cpuid_gpio_m_axi_awqos => cpuid_gpio_bus_2_full_awqos,
cpuid_gpio_m_axi_awregion => cpuid_gpio_bus_2_full_awregion,
cpuid_gpio_m_axi_awvalid => cpuid_gpio_bus_2_full_awvalid,
cpuid_gpio_m_axi_awready => cpuid_gpio_bus_2_full_awready,
cpuid_gpio_m_axi_wdata => cpuid_gpio_bus_2_full_wdata,
cpuid_gpio_m_axi_wstrb => cpuid_gpio_bus_2_full_wstrb,
cpuid_gpio_m_axi_wlast => cpuid_gpio_bus_2_full_wlast,
cpuid_gpio_m_axi_wvalid => cpuid_gpio_bus_2_full_wvalid,
cpuid_gpio_m_axi_wready => cpuid_gpio_bus_2_full_wready,
cpuid_gpio_m_axi_bid => cpuid_gpio_bus_2_full_bid,
cpuid_gpio_m_axi_bresp => cpuid_gpio_bus_2_full_bresp,
cpuid_gpio_m_axi_bvalid => cpuid_gpio_bus_2_full_bvalid,
cpuid_gpio_m_axi_bready => cpuid_gpio_bus_2_full_bready,
cpuid_gpio_m_axi_arid => cpuid_gpio_bus_2_full_arid,
cpuid_gpio_m_axi_araddr => cpuid_gpio_bus_2_full_araddr,
cpuid_gpio_m_axi_arlen => cpuid_gpio_bus_2_full_arlen,
cpuid_gpio_m_axi_arsize => cpuid_gpio_bus_2_full_arsize,
cpuid_gpio_m_axi_arburst => cpuid_gpio_bus_2_full_arburst,
cpuid_gpio_m_axi_arlock => cpuid_gpio_bus_2_full_arlock,
cpuid_gpio_m_axi_arcache => cpuid_gpio_bus_2_full_arcache,
cpuid_gpio_m_axi_arprot => cpuid_gpio_bus_2_full_arprot,
cpuid_gpio_m_axi_arqos => cpuid_gpio_bus_2_full_arqos,
cpuid_gpio_m_axi_arregion => cpuid_gpio_bus_2_full_arregion,
cpuid_gpio_m_axi_arvalid => cpuid_gpio_bus_2_full_arvalid,
cpuid_gpio_m_axi_arready => cpuid_gpio_bus_2_full_arready,
cpuid_gpio_m_axi_rid => cpuid_gpio_bus_2_full_rid,
cpuid_gpio_m_axi_rdata => cpuid_gpio_bus_2_full_rdata,
cpuid_gpio_m_axi_rresp => cpuid_gpio_bus_2_full_rresp,
cpuid_gpio_m_axi_rlast => cpuid_gpio_bus_2_full_rlast,
cpuid_gpio_m_axi_rvalid => cpuid_gpio_bus_2_full_rvalid,
cpuid_gpio_m_axi_rready => cpuid_gpio_bus_2_full_rready,
int_m_axi_awid => int_bus_2_full_awid,
int_m_axi_awaddr => int_bus_2_full_awaddr,
int_m_axi_awlen => int_bus_2_full_awlen,
int_m_axi_awsize => int_bus_2_full_awsize,
int_m_axi_awburst => int_bus_2_full_awburst,
int_m_axi_awlock => int_bus_2_full_awlock,
int_m_axi_awcache => int_bus_2_full_awcache,
int_m_axi_awprot => int_bus_2_full_awprot,
int_m_axi_awqos => int_bus_2_full_awqos,
int_m_axi_awregion => int_bus_2_full_awregion,
int_m_axi_awvalid => int_bus_2_full_awvalid,
int_m_axi_awready => int_bus_2_full_awready,
int_m_axi_wdata => int_bus_2_full_wdata,
int_m_axi_wstrb => int_bus_2_full_wstrb,
int_m_axi_wlast => int_bus_2_full_wlast,
int_m_axi_wvalid => int_bus_2_full_wvalid,
int_m_axi_wready => int_bus_2_full_wready,
int_m_axi_bid => int_bus_2_full_bid,
int_m_axi_bresp => int_bus_2_full_bresp,
int_m_axi_bvalid => int_bus_2_full_bvalid,
int_m_axi_bready => int_bus_2_full_bready,
int_m_axi_arid => int_bus_2_full_arid,
int_m_axi_araddr => int_bus_2_full_araddr,
int_m_axi_arlen => int_bus_2_full_arlen,
int_m_axi_arsize => int_bus_2_full_arsize,
int_m_axi_arburst => int_bus_2_full_arburst,
int_m_axi_arlock => int_bus_2_full_arlock,
int_m_axi_arcache => int_bus_2_full_arcache,
int_m_axi_arprot => int_bus_2_full_arprot,
int_m_axi_arqos => int_bus_2_full_arqos,
int_m_axi_arregion => int_bus_2_full_arregion,
int_m_axi_arvalid => int_bus_2_full_arvalid,
int_m_axi_arready => int_bus_2_full_arready,
int_m_axi_rid => int_bus_2_full_rid,
int_m_axi_rdata => int_bus_2_full_rdata,
int_m_axi_rresp => int_bus_2_full_rresp,
int_m_axi_rlast => int_bus_2_full_rlast,
int_m_axi_rvalid => int_bus_2_full_rvalid,
int_m_axi_rready => int_bus_2_full_rready,
signal_m_axi_awid => signal_bus_2_full_awid,
signal_m_axi_awaddr => signal_bus_2_full_awaddr,
signal_m_axi_awlen => signal_bus_2_full_awlen,
signal_m_axi_awsize => signal_bus_2_full_awsize,
signal_m_axi_awburst => signal_bus_2_full_awburst,
signal_m_axi_awlock => signal_bus_2_full_awlock,
signal_m_axi_awcache => signal_bus_2_full_awcache,
signal_m_axi_awprot => signal_bus_2_full_awprot,
signal_m_axi_awqos => signal_bus_2_full_awqos,
signal_m_axi_awregion => signal_bus_2_full_awregion,
signal_m_axi_awvalid => signal_bus_2_full_awvalid,
signal_m_axi_awready => signal_bus_2_full_awready,
signal_m_axi_wdata => signal_bus_2_full_wdata,
signal_m_axi_wstrb => signal_bus_2_full_wstrb,
signal_m_axi_wlast => signal_bus_2_full_wlast,
signal_m_axi_wvalid => signal_bus_2_full_wvalid,
signal_m_axi_wready => signal_bus_2_full_wready,
signal_m_axi_bid => signal_bus_2_full_bid,
signal_m_axi_bresp => signal_bus_2_full_bresp,
signal_m_axi_bvalid => signal_bus_2_full_bvalid,
signal_m_axi_bready => signal_bus_2_full_bready,
signal_m_axi_arid => signal_bus_2_full_arid,
signal_m_axi_araddr => signal_bus_2_full_araddr,
signal_m_axi_arlen => signal_bus_2_full_arlen,
signal_m_axi_arsize => signal_bus_2_full_arsize,
signal_m_axi_arburst => signal_bus_2_full_arburst,
signal_m_axi_arlock => signal_bus_2_full_arlock,
signal_m_axi_arcache => signal_bus_2_full_arcache,
signal_m_axi_arprot => signal_bus_2_full_arprot,
signal_m_axi_arqos => signal_bus_2_full_arqos,
signal_m_axi_arregion => signal_bus_2_full_arregion,
signal_m_axi_arvalid => signal_bus_2_full_arvalid,
signal_m_axi_arready => signal_bus_2_full_arready,
signal_m_axi_rid => signal_bus_2_full_rid,
signal_m_axi_rdata => signal_bus_2_full_rdata,
signal_m_axi_rresp => signal_bus_2_full_rresp,
signal_m_axi_rlast => signal_bus_2_full_rlast,
signal_m_axi_rvalid => signal_bus_2_full_rvalid,
timer_m_axi_awid => timer_bus_2_full_awid,
timer_m_axi_awaddr => timer_bus_2_full_awaddr,
timer_m_axi_awlen => timer_bus_2_full_awlen,
timer_m_axi_awsize => timer_bus_2_full_awsize,
timer_m_axi_awburst => timer_bus_2_full_awburst,
timer_m_axi_awlock => timer_bus_2_full_awlock,
timer_m_axi_awcache => timer_bus_2_full_awcache,
timer_m_axi_awprot => timer_bus_2_full_awprot,
timer_m_axi_awqos => timer_bus_2_full_awqos,
timer_m_axi_awregion => timer_bus_2_full_awregion,
timer_m_axi_awvalid => timer_bus_2_full_awvalid,
timer_m_axi_awready => timer_bus_2_full_awready,
timer_m_axi_wdata => timer_bus_2_full_wdata,
timer_m_axi_wstrb => timer_bus_2_full_wstrb,
timer_m_axi_wlast => timer_bus_2_full_wlast,
timer_m_axi_wvalid => timer_bus_2_full_wvalid,
timer_m_axi_wready => timer_bus_2_full_wready,
timer_m_axi_bid => timer_bus_2_full_bid,
timer_m_axi_bresp => timer_bus_2_full_bresp,
timer_m_axi_bvalid => timer_bus_2_full_bvalid,
timer_m_axi_bready => timer_bus_2_full_bready,
timer_m_axi_arid => timer_bus_2_full_arid,
timer_m_axi_araddr => timer_bus_2_full_araddr,
timer_m_axi_arlen => timer_bus_2_full_arlen,
timer_m_axi_arsize => timer_bus_2_full_arsize,
timer_m_axi_arburst => timer_bus_2_full_arburst,
timer_m_axi_arlock => timer_bus_2_full_arlock,
timer_m_axi_arcache => timer_bus_2_full_arcache,
timer_m_axi_arprot => timer_bus_2_full_arprot,
timer_m_axi_arqos => timer_bus_2_full_arqos,
timer_m_axi_arregion => timer_bus_2_full_arregion,
timer_m_axi_arvalid => timer_bus_2_full_arvalid,
timer_m_axi_arready => timer_bus_2_full_arready,
timer_m_axi_rid => timer_bus_2_full_rid,
timer_m_axi_rdata => timer_bus_2_full_rdata,
timer_m_axi_rresp => timer_bus_2_full_rresp,
timer_m_axi_rlast => timer_bus_2_full_rlast,
timer_m_axi_rvalid => timer_bus_2_full_rvalid,
aclk => aclk, aresetn => peripheral_aresetn(0));
------------------------
-- CPU Instantiations --
------------------------
plasoc_cpu_0_inst : plasoc_cpu
generic map (
cache_address_width => cache_address_width,
cache_way_width => cache_way_width,
cache_index_width => cache_index_width,
cache_offset_width => cache_offset_width,
cache_replace_strat => cache_replace_strat)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awid => cpu_bus_0_full_awid,
axi_awaddr => cpu_bus_0_full_awaddr,
axi_awlen => cpu_bus_0_full_awlen,
axi_awsize => cpu_bus_0_full_awsize,
axi_awburst => cpu_bus_0_full_awburst,
axi_awlock => cpu_bus_0_full_awlock,
axi_awcache => cpu_bus_0_full_awcache,
axi_awprot => cpu_bus_0_full_awprot,
axi_awqos => cpu_bus_0_full_awqos,
axi_awregion => cpu_bus_0_full_awregion,
axi_awvalid => cpu_bus_0_full_awvalid,
axi_awready => cpu_bus_0_full_awready,
axi_wdata => cpu_bus_0_full_wdata,
axi_wstrb => cpu_bus_0_full_wstrb,
axi_wlast => cpu_bus_0_full_wlast,
axi_wvalid => cpu_bus_0_full_wvalid,
axi_wready => cpu_bus_0_full_wready,
axi_bid => cpu_bus_0_full_bid,
axi_bresp => cpu_bus_0_full_bresp,
axi_bvalid => cpu_bus_0_full_bvalid,
axi_bready => cpu_bus_0_full_bready,
axi_arid => cpu_bus_0_full_arid,
axi_araddr => cpu_bus_0_full_araddr,
axi_arlen => cpu_bus_0_full_arlen,
axi_arsize => cpu_bus_0_full_arsize,
axi_arburst => cpu_bus_0_full_arburst,
axi_arlock => cpu_bus_0_full_arlock,
axi_arcache => cpu_bus_0_full_arcache,
axi_arprot => cpu_bus_0_full_arprot,
axi_arqos => cpu_bus_0_full_arqos,
axi_arregion => cpu_bus_0_full_arregion,
axi_arvalid => cpu_bus_0_full_arvalid,
axi_arready => cpu_bus_0_full_arready,
axi_rid => cpu_bus_0_full_rid,
axi_rdata => cpu_bus_0_full_rdata,
axi_rresp => cpu_bus_0_full_rresp,
axi_rlast => cpu_bus_0_full_rlast,
axi_rvalid => cpu_bus_0_full_rvalid,
axi_rready => cpu_bus_0_full_rready,
intr_in => cpu_0_int);
plasoc_cpu_1_inst : plasoc_cpu
generic map (
cache_address_width => cache_address_width,
cache_way_width => cache_way_width,
cache_index_width => cache_index_width,
cache_offset_width => cache_offset_width,
cache_replace_strat => cache_replace_strat)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awid => cpu_bus_1_full_awid,
axi_awaddr => cpu_bus_1_full_awaddr,
axi_awlen => cpu_bus_1_full_awlen,
axi_awsize => cpu_bus_1_full_awsize,
axi_awburst => cpu_bus_1_full_awburst,
axi_awlock => cpu_bus_1_full_awlock,
axi_awcache => cpu_bus_1_full_awcache,
axi_awprot => cpu_bus_1_full_awprot,
axi_awqos => cpu_bus_1_full_awqos,
axi_awregion => cpu_bus_1_full_awregion,
axi_awvalid => cpu_bus_1_full_awvalid,
axi_awready => cpu_bus_1_full_awready,
axi_wdata => cpu_bus_1_full_wdata,
axi_wstrb => cpu_bus_1_full_wstrb,
axi_wlast => cpu_bus_1_full_wlast,
axi_wvalid => cpu_bus_1_full_wvalid,
axi_wready => cpu_bus_1_full_wready,
axi_bid => cpu_bus_1_full_bid,
axi_bresp => cpu_bus_1_full_bresp,
axi_bvalid => cpu_bus_1_full_bvalid,
axi_bready => cpu_bus_1_full_bready,
axi_arid => cpu_bus_1_full_arid,
axi_araddr => cpu_bus_1_full_araddr,
axi_arlen => cpu_bus_1_full_arlen,
axi_arsize => cpu_bus_1_full_arsize,
axi_arburst => cpu_bus_1_full_arburst,
axi_arlock => cpu_bus_1_full_arlock,
axi_arcache => cpu_bus_1_full_arcache,
axi_arprot => cpu_bus_1_full_arprot,
axi_arqos => cpu_bus_1_full_arqos,
axi_arregion => cpu_bus_1_full_arregion,
axi_arvalid => cpu_bus_1_full_arvalid,
axi_arready => cpu_bus_1_full_arready,
axi_rid => cpu_bus_1_full_rid,
axi_rdata => cpu_bus_1_full_rdata,
axi_rresp => cpu_bus_1_full_rresp,
axi_rlast => cpu_bus_1_full_rlast,
axi_rvalid => cpu_bus_1_full_rvalid,
axi_rready => cpu_bus_1_full_rready,
intr_in => cpu_1_int);
plasoc_cpu_2_inst : plasoc_cpu
generic map (
cache_address_width => cache_address_width,
cache_way_width => cache_way_width,
cache_index_width => cache_index_width,
cache_offset_width => cache_offset_width,
cache_replace_strat => cache_replace_strat)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awid => cpu_bus_2_full_awid,
axi_awaddr => cpu_bus_2_full_awaddr,
axi_awlen => cpu_bus_2_full_awlen,
axi_awsize => cpu_bus_2_full_awsize,
axi_awburst => cpu_bus_2_full_awburst,
axi_awlock => cpu_bus_2_full_awlock,
axi_awcache => cpu_bus_2_full_awcache,
axi_awprot => cpu_bus_2_full_awprot,
axi_awqos => cpu_bus_2_full_awqos,
axi_awregion => cpu_bus_2_full_awregion,
axi_awvalid => cpu_bus_2_full_awvalid,
axi_awready => cpu_bus_2_full_awready,
axi_wdata => cpu_bus_2_full_wdata,
axi_wstrb => cpu_bus_2_full_wstrb,
axi_wlast => cpu_bus_2_full_wlast,
axi_wvalid => cpu_bus_2_full_wvalid,
axi_wready => cpu_bus_2_full_wready,
axi_bid => cpu_bus_2_full_bid,
axi_bresp => cpu_bus_2_full_bresp,
axi_bvalid => cpu_bus_2_full_bvalid,
axi_bready => cpu_bus_2_full_bready,
axi_arid => cpu_bus_2_full_arid,
axi_araddr => cpu_bus_2_full_araddr,
axi_arlen => cpu_bus_2_full_arlen,
axi_arsize => cpu_bus_2_full_arsize,
axi_arburst => cpu_bus_2_full_arburst,
axi_arlock => cpu_bus_2_full_arlock,
axi_arcache => cpu_bus_2_full_arcache,
axi_arprot => cpu_bus_2_full_arprot,
axi_arqos => cpu_bus_2_full_arqos,
axi_arregion => cpu_bus_2_full_arregion,
axi_arvalid => cpu_bus_2_full_arvalid,
axi_arready => cpu_bus_2_full_arready,
axi_rid => cpu_bus_2_full_rid,
axi_rdata => cpu_bus_2_full_rdata,
axi_rresp => cpu_bus_2_full_rresp,
axi_rlast => cpu_bus_2_full_rlast,
axi_rvalid => cpu_bus_2_full_rvalid,
axi_rready => cpu_bus_2_full_rready,
intr_in => cpu_2_int);
---------------------------------------------
-- CPUID GPIO AXI Full2Lite Instantiations --
---------------------------------------------
cpuid_gpio_0_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => cpuid_gpio_bus_0_full_awid,
s_axi_awaddr => cpuid_gpio_bus_0_full_awaddr,
s_axi_awlen => cpuid_gpio_bus_0_full_awlen,
s_axi_awsize => cpuid_gpio_bus_0_full_awsize,
s_axi_awburst => cpuid_gpio_bus_0_full_awburst,
s_axi_awlock => cpuid_gpio_bus_0_full_awlock,
s_axi_awcache => cpuid_gpio_bus_0_full_awcache,
s_axi_awprot => cpuid_gpio_bus_0_full_awprot,
s_axi_awqos => cpuid_gpio_bus_0_full_awqos,
s_axi_awregion => cpuid_gpio_bus_0_full_awregion,
s_axi_awvalid => cpuid_gpio_bus_0_full_awvalid,
s_axi_awready => cpuid_gpio_bus_0_full_awready,
s_axi_wdata => cpuid_gpio_bus_0_full_wdata,
s_axi_wstrb => cpuid_gpio_bus_0_full_wstrb,
s_axi_wlast => cpuid_gpio_bus_0_full_wlast,
s_axi_wvalid => cpuid_gpio_bus_0_full_wvalid,
s_axi_wready => cpuid_gpio_bus_0_full_wready,
s_axi_bid => cpuid_gpio_bus_0_full_bid,
s_axi_bresp => cpuid_gpio_bus_0_full_bresp,
s_axi_bvalid => cpuid_gpio_bus_0_full_bvalid,
s_axi_bready => cpuid_gpio_bus_0_full_bready,
s_axi_arid => cpuid_gpio_bus_0_full_arid,
s_axi_araddr => cpuid_gpio_bus_0_full_araddr,
s_axi_arlen => cpuid_gpio_bus_0_full_arlen,
s_axi_arsize => cpuid_gpio_bus_0_full_arsize,
s_axi_arburst => cpuid_gpio_bus_0_full_arburst,
s_axi_arlock => cpuid_gpio_bus_0_full_arlock,
s_axi_arcache => cpuid_gpio_bus_0_full_arcache,
s_axi_arprot => cpuid_gpio_bus_0_full_arprot,
s_axi_arqos => cpuid_gpio_bus_0_full_arqos,
s_axi_arregion => cpuid_gpio_bus_0_full_arregion,
s_axi_arvalid => cpuid_gpio_bus_0_full_arvalid,
s_axi_arready => cpuid_gpio_bus_0_full_arready,
s_axi_rid => cpuid_gpio_bus_0_full_rid,
s_axi_rdata => cpuid_gpio_bus_0_full_rdata,
s_axi_rresp => cpuid_gpio_bus_0_full_rresp,
s_axi_rlast => cpuid_gpio_bus_0_full_rlast,
s_axi_rvalid => cpuid_gpio_bus_0_full_rvalid,
s_axi_rready => cpuid_gpio_bus_0_full_rready,
m_axi_awaddr => cpuid_gpio_bus_0_lite_awaddr,
m_axi_awprot => cpuid_gpio_bus_0_lite_awprot,
m_axi_awvalid => cpuid_gpio_bus_0_lite_awvalid,
m_axi_awready => cpuid_gpio_bus_0_lite_awready,
m_axi_wvalid => cpuid_gpio_bus_0_lite_wvalid,
m_axi_wready => cpuid_gpio_bus_0_lite_wready,
m_axi_wdata => cpuid_gpio_bus_0_lite_wdata,
m_axi_wstrb => cpuid_gpio_bus_0_lite_wstrb,
m_axi_bvalid => cpuid_gpio_bus_0_lite_bvalid,
m_axi_bready => cpuid_gpio_bus_0_lite_bready,
m_axi_bresp => cpuid_gpio_bus_0_lite_bresp,
m_axi_araddr => cpuid_gpio_bus_0_lite_araddr,
m_axi_arprot => cpuid_gpio_bus_0_lite_arprot,
m_axi_arvalid => cpuid_gpio_bus_0_lite_arvalid,
m_axi_arready => cpuid_gpio_bus_0_lite_arready,
m_axi_rdata => cpuid_gpio_bus_0_lite_rdata,
m_axi_rvalid => cpuid_gpio_bus_0_lite_rvalid,
m_axi_rready => cpuid_gpio_bus_0_lite_rready,
m_axi_rresp => cpuid_gpio_bus_0_lite_rresp);
cpuid_gpio_1_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => cpuid_gpio_bus_1_full_awid,
s_axi_awaddr => cpuid_gpio_bus_1_full_awaddr,
s_axi_awlen => cpuid_gpio_bus_1_full_awlen,
s_axi_awsize => cpuid_gpio_bus_1_full_awsize,
s_axi_awburst => cpuid_gpio_bus_1_full_awburst,
s_axi_awlock => cpuid_gpio_bus_1_full_awlock,
s_axi_awcache => cpuid_gpio_bus_1_full_awcache,
s_axi_awprot => cpuid_gpio_bus_1_full_awprot,
s_axi_awqos => cpuid_gpio_bus_1_full_awqos,
s_axi_awregion => cpuid_gpio_bus_1_full_awregion,
s_axi_awvalid => cpuid_gpio_bus_1_full_awvalid,
s_axi_awready => cpuid_gpio_bus_1_full_awready,
s_axi_wdata => cpuid_gpio_bus_1_full_wdata,
s_axi_wstrb => cpuid_gpio_bus_1_full_wstrb,
s_axi_wlast => cpuid_gpio_bus_1_full_wlast,
s_axi_wvalid => cpuid_gpio_bus_1_full_wvalid,
s_axi_wready => cpuid_gpio_bus_1_full_wready,
s_axi_bid => cpuid_gpio_bus_1_full_bid,
s_axi_bresp => cpuid_gpio_bus_1_full_bresp,
s_axi_bvalid => cpuid_gpio_bus_1_full_bvalid,
s_axi_bready => cpuid_gpio_bus_1_full_bready,
s_axi_arid => cpuid_gpio_bus_1_full_arid,
s_axi_araddr => cpuid_gpio_bus_1_full_araddr,
s_axi_arlen => cpuid_gpio_bus_1_full_arlen,
s_axi_arsize => cpuid_gpio_bus_1_full_arsize,
s_axi_arburst => cpuid_gpio_bus_1_full_arburst,
s_axi_arlock => cpuid_gpio_bus_1_full_arlock,
s_axi_arcache => cpuid_gpio_bus_1_full_arcache,
s_axi_arprot => cpuid_gpio_bus_1_full_arprot,
s_axi_arqos => cpuid_gpio_bus_1_full_arqos,
s_axi_arregion => cpuid_gpio_bus_1_full_arregion,
s_axi_arvalid => cpuid_gpio_bus_1_full_arvalid,
s_axi_arready => cpuid_gpio_bus_1_full_arready,
s_axi_rid => cpuid_gpio_bus_1_full_rid,
s_axi_rdata => cpuid_gpio_bus_1_full_rdata,
s_axi_rresp => cpuid_gpio_bus_1_full_rresp,
s_axi_rlast => cpuid_gpio_bus_1_full_rlast,
s_axi_rvalid => cpuid_gpio_bus_1_full_rvalid,
s_axi_rready => cpuid_gpio_bus_1_full_rready,
m_axi_awaddr => cpuid_gpio_bus_1_lite_awaddr,
m_axi_awprot => cpuid_gpio_bus_1_lite_awprot,
m_axi_awvalid => cpuid_gpio_bus_1_lite_awvalid,
m_axi_awready => cpuid_gpio_bus_1_lite_awready,
m_axi_wvalid => cpuid_gpio_bus_1_lite_wvalid,
m_axi_wready => cpuid_gpio_bus_1_lite_wready,
m_axi_wdata => cpuid_gpio_bus_1_lite_wdata,
m_axi_wstrb => cpuid_gpio_bus_1_lite_wstrb,
m_axi_bvalid => cpuid_gpio_bus_1_lite_bvalid,
m_axi_bready => cpuid_gpio_bus_1_lite_bready,
m_axi_bresp => cpuid_gpio_bus_1_lite_bresp,
m_axi_araddr => cpuid_gpio_bus_1_lite_araddr,
m_axi_arprot => cpuid_gpio_bus_1_lite_arprot,
m_axi_arvalid => cpuid_gpio_bus_1_lite_arvalid,
m_axi_arready => cpuid_gpio_bus_1_lite_arready,
m_axi_rdata => cpuid_gpio_bus_1_lite_rdata,
m_axi_rvalid => cpuid_gpio_bus_1_lite_rvalid,
m_axi_rready => cpuid_gpio_bus_1_lite_rready,
m_axi_rresp => cpuid_gpio_bus_1_lite_rresp);
cpuid_gpio_2_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => cpuid_gpio_bus_2_full_awid,
s_axi_awaddr => cpuid_gpio_bus_2_full_awaddr,
s_axi_awlen => cpuid_gpio_bus_2_full_awlen,
s_axi_awsize => cpuid_gpio_bus_2_full_awsize,
s_axi_awburst => cpuid_gpio_bus_2_full_awburst,
s_axi_awlock => cpuid_gpio_bus_2_full_awlock,
s_axi_awcache => cpuid_gpio_bus_2_full_awcache,
s_axi_awprot => cpuid_gpio_bus_2_full_awprot,
s_axi_awqos => cpuid_gpio_bus_2_full_awqos,
s_axi_awregion => cpuid_gpio_bus_2_full_awregion,
s_axi_awvalid => cpuid_gpio_bus_2_full_awvalid,
s_axi_awready => cpuid_gpio_bus_2_full_awready,
s_axi_wdata => cpuid_gpio_bus_2_full_wdata,
s_axi_wstrb => cpuid_gpio_bus_2_full_wstrb,
s_axi_wlast => cpuid_gpio_bus_2_full_wlast,
s_axi_wvalid => cpuid_gpio_bus_2_full_wvalid,
s_axi_wready => cpuid_gpio_bus_2_full_wready,
s_axi_bid => cpuid_gpio_bus_2_full_bid,
s_axi_bresp => cpuid_gpio_bus_2_full_bresp,
s_axi_bvalid => cpuid_gpio_bus_2_full_bvalid,
s_axi_bready => cpuid_gpio_bus_2_full_bready,
s_axi_arid => cpuid_gpio_bus_2_full_arid,
s_axi_araddr => cpuid_gpio_bus_2_full_araddr,
s_axi_arlen => cpuid_gpio_bus_2_full_arlen,
s_axi_arsize => cpuid_gpio_bus_2_full_arsize,
s_axi_arburst => cpuid_gpio_bus_2_full_arburst,
s_axi_arlock => cpuid_gpio_bus_2_full_arlock,
s_axi_arcache => cpuid_gpio_bus_2_full_arcache,
s_axi_arprot => cpuid_gpio_bus_2_full_arprot,
s_axi_arqos => cpuid_gpio_bus_2_full_arqos,
s_axi_arregion => cpuid_gpio_bus_2_full_arregion,
s_axi_arvalid => cpuid_gpio_bus_2_full_arvalid,
s_axi_arready => cpuid_gpio_bus_2_full_arready,
s_axi_rid => cpuid_gpio_bus_2_full_rid,
s_axi_rdata => cpuid_gpio_bus_2_full_rdata,
s_axi_rresp => cpuid_gpio_bus_2_full_rresp,
s_axi_rlast => cpuid_gpio_bus_2_full_rlast,
s_axi_rvalid => cpuid_gpio_bus_2_full_rvalid,
s_axi_rready => cpuid_gpio_bus_2_full_rready,
m_axi_awaddr => cpuid_gpio_bus_2_lite_awaddr,
m_axi_awprot => cpuid_gpio_bus_2_lite_awprot,
m_axi_awvalid => cpuid_gpio_bus_2_lite_awvalid,
m_axi_awready => cpuid_gpio_bus_2_lite_awready,
m_axi_wvalid => cpuid_gpio_bus_2_lite_wvalid,
m_axi_wready => cpuid_gpio_bus_2_lite_wready,
m_axi_wdata => cpuid_gpio_bus_2_lite_wdata,
m_axi_wstrb => cpuid_gpio_bus_2_lite_wstrb,
m_axi_bvalid => cpuid_gpio_bus_2_lite_bvalid,
m_axi_bready => cpuid_gpio_bus_2_lite_bready,
m_axi_bresp => cpuid_gpio_bus_2_lite_bresp,
m_axi_araddr => cpuid_gpio_bus_2_lite_araddr,
m_axi_arprot => cpuid_gpio_bus_2_lite_arprot,
m_axi_arvalid => cpuid_gpio_bus_2_lite_arvalid,
m_axi_arready => cpuid_gpio_bus_2_lite_arready,
m_axi_rdata => cpuid_gpio_bus_2_lite_rdata,
m_axi_rvalid => cpuid_gpio_bus_2_lite_rvalid,
m_axi_rready => cpuid_gpio_bus_2_lite_rready,
m_axi_rresp => cpuid_gpio_bus_2_lite_rresp);
------------------------------------------
-- CPU INT AXI Full2Lite Instantiations --
------------------------------------------
int_0_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => int_bus_0_full_awid,
s_axi_awaddr => int_bus_0_full_awaddr,
s_axi_awlen => int_bus_0_full_awlen,
s_axi_awsize => int_bus_0_full_awsize,
s_axi_awburst => int_bus_0_full_awburst,
s_axi_awlock => int_bus_0_full_awlock,
s_axi_awcache => int_bus_0_full_awcache,
s_axi_awprot => int_bus_0_full_awprot,
s_axi_awqos => int_bus_0_full_awqos,
s_axi_awregion => int_bus_0_full_awregion,
s_axi_awvalid => int_bus_0_full_awvalid,
s_axi_awready => int_bus_0_full_awready,
s_axi_wdata => int_bus_0_full_wdata,
s_axi_wstrb => int_bus_0_full_wstrb,
s_axi_wlast => int_bus_0_full_wlast,
s_axi_wvalid => int_bus_0_full_wvalid,
s_axi_wready => int_bus_0_full_wready,
s_axi_bid => int_bus_0_full_bid,
s_axi_bresp => int_bus_0_full_bresp,
s_axi_bvalid => int_bus_0_full_bvalid,
s_axi_bready => int_bus_0_full_bready,
s_axi_arid => int_bus_0_full_arid,
s_axi_araddr => int_bus_0_full_araddr,
s_axi_arlen => int_bus_0_full_arlen,
s_axi_arsize => int_bus_0_full_arsize,
s_axi_arburst => int_bus_0_full_arburst,
s_axi_arlock => int_bus_0_full_arlock,
s_axi_arcache => int_bus_0_full_arcache,
s_axi_arprot => int_bus_0_full_arprot,
s_axi_arqos => int_bus_0_full_arqos,
s_axi_arregion => int_bus_0_full_arregion,
s_axi_arvalid => int_bus_0_full_arvalid,
s_axi_arready => int_bus_0_full_arready,
s_axi_rid => int_bus_0_full_rid,
s_axi_rdata => int_bus_0_full_rdata,
s_axi_rresp => int_bus_0_full_rresp,
s_axi_rlast => int_bus_0_full_rlast,
s_axi_rvalid => int_bus_0_full_rvalid,
s_axi_rready => int_bus_0_full_rready,
m_axi_awaddr => int_bus_0_lite_awaddr,
m_axi_awprot => int_bus_0_lite_awprot,
m_axi_awvalid => int_bus_0_lite_awvalid,
m_axi_awready => int_bus_0_lite_awready,
m_axi_wvalid => int_bus_0_lite_wvalid,
m_axi_wready => int_bus_0_lite_wready,
m_axi_wdata => int_bus_0_lite_wdata,
m_axi_wstrb => int_bus_0_lite_wstrb,
m_axi_bvalid => int_bus_0_lite_bvalid,
m_axi_bready => int_bus_0_lite_bready,
m_axi_bresp => int_bus_0_lite_bresp,
m_axi_araddr => int_bus_0_lite_araddr,
m_axi_arprot => int_bus_0_lite_arprot,
m_axi_arvalid => int_bus_0_lite_arvalid,
m_axi_arready => int_bus_0_lite_arready,
m_axi_rdata => int_bus_0_lite_rdata,
m_axi_rvalid => int_bus_0_lite_rvalid,
m_axi_rready => int_bus_0_lite_rready,
m_axi_rresp => int_bus_0_lite_rresp);
int_1_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => int_bus_1_full_awid,
s_axi_awaddr => int_bus_1_full_awaddr,
s_axi_awlen => int_bus_1_full_awlen,
s_axi_awsize => int_bus_1_full_awsize,
s_axi_awburst => int_bus_1_full_awburst,
s_axi_awlock => int_bus_1_full_awlock,
s_axi_awcache => int_bus_1_full_awcache,
s_axi_awprot => int_bus_1_full_awprot,
s_axi_awqos => int_bus_1_full_awqos,
s_axi_awregion => int_bus_1_full_awregion,
s_axi_awvalid => int_bus_1_full_awvalid,
s_axi_awready => int_bus_1_full_awready,
s_axi_wdata => int_bus_1_full_wdata,
s_axi_wstrb => int_bus_1_full_wstrb,
s_axi_wlast => int_bus_1_full_wlast,
s_axi_wvalid => int_bus_1_full_wvalid,
s_axi_wready => int_bus_1_full_wready,
s_axi_bid => int_bus_1_full_bid,
s_axi_bresp => int_bus_1_full_bresp,
s_axi_bvalid => int_bus_1_full_bvalid,
s_axi_bready => int_bus_1_full_bready,
s_axi_arid => int_bus_1_full_arid,
s_axi_araddr => int_bus_1_full_araddr,
s_axi_arlen => int_bus_1_full_arlen,
s_axi_arsize => int_bus_1_full_arsize,
s_axi_arburst => int_bus_1_full_arburst,
s_axi_arlock => int_bus_1_full_arlock,
s_axi_arcache => int_bus_1_full_arcache,
s_axi_arprot => int_bus_1_full_arprot,
s_axi_arqos => int_bus_1_full_arqos,
s_axi_arregion => int_bus_1_full_arregion,
s_axi_arvalid => int_bus_1_full_arvalid,
s_axi_arready => int_bus_1_full_arready,
s_axi_rid => int_bus_1_full_rid,
s_axi_rdata => int_bus_1_full_rdata,
s_axi_rresp => int_bus_1_full_rresp,
s_axi_rlast => int_bus_1_full_rlast,
s_axi_rvalid => int_bus_1_full_rvalid,
s_axi_rready => int_bus_1_full_rready,
m_axi_awaddr => int_bus_1_lite_awaddr,
m_axi_awprot => int_bus_1_lite_awprot,
m_axi_awvalid => int_bus_1_lite_awvalid,
m_axi_awready => int_bus_1_lite_awready,
m_axi_wvalid => int_bus_1_lite_wvalid,
m_axi_wready => int_bus_1_lite_wready,
m_axi_wdata => int_bus_1_lite_wdata,
m_axi_wstrb => int_bus_1_lite_wstrb,
m_axi_bvalid => int_bus_1_lite_bvalid,
m_axi_bready => int_bus_1_lite_bready,
m_axi_bresp => int_bus_1_lite_bresp,
m_axi_araddr => int_bus_1_lite_araddr,
m_axi_arprot => int_bus_1_lite_arprot,
m_axi_arvalid => int_bus_1_lite_arvalid,
m_axi_arready => int_bus_1_lite_arready,
m_axi_rdata => int_bus_1_lite_rdata,
m_axi_rvalid => int_bus_1_lite_rvalid,
m_axi_rready => int_bus_1_lite_rready,
m_axi_rresp => int_bus_1_lite_rresp);
int_2_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => int_bus_2_full_awid,
s_axi_awaddr => int_bus_2_full_awaddr,
s_axi_awlen => int_bus_2_full_awlen,
s_axi_awsize => int_bus_2_full_awsize,
s_axi_awburst => int_bus_2_full_awburst,
s_axi_awlock => int_bus_2_full_awlock,
s_axi_awcache => int_bus_2_full_awcache,
s_axi_awprot => int_bus_2_full_awprot,
s_axi_awqos => int_bus_2_full_awqos,
s_axi_awregion => int_bus_2_full_awregion,
s_axi_awvalid => int_bus_2_full_awvalid,
s_axi_awready => int_bus_2_full_awready,
s_axi_wdata => int_bus_2_full_wdata,
s_axi_wstrb => int_bus_2_full_wstrb,
s_axi_wlast => int_bus_2_full_wlast,
s_axi_wvalid => int_bus_2_full_wvalid,
s_axi_wready => int_bus_2_full_wready,
s_axi_bid => int_bus_2_full_bid,
s_axi_bresp => int_bus_2_full_bresp,
s_axi_bvalid => int_bus_2_full_bvalid,
s_axi_bready => int_bus_2_full_bready,
s_axi_arid => int_bus_2_full_arid,
s_axi_araddr => int_bus_2_full_araddr,
s_axi_arlen => int_bus_2_full_arlen,
s_axi_arsize => int_bus_2_full_arsize,
s_axi_arburst => int_bus_2_full_arburst,
s_axi_arlock => int_bus_2_full_arlock,
s_axi_arcache => int_bus_2_full_arcache,
s_axi_arprot => int_bus_2_full_arprot,
s_axi_arqos => int_bus_2_full_arqos,
s_axi_arregion => int_bus_2_full_arregion,
s_axi_arvalid => int_bus_2_full_arvalid,
s_axi_arready => int_bus_2_full_arready,
s_axi_rid => int_bus_2_full_rid,
s_axi_rdata => int_bus_2_full_rdata,
s_axi_rresp => int_bus_2_full_rresp,
s_axi_rlast => int_bus_2_full_rlast,
s_axi_rvalid => int_bus_2_full_rvalid,
s_axi_rready => int_bus_2_full_rready,
m_axi_awaddr => int_bus_2_lite_awaddr,
m_axi_awprot => int_bus_2_lite_awprot,
m_axi_awvalid => int_bus_2_lite_awvalid,
m_axi_awready => int_bus_2_lite_awready,
m_axi_wvalid => int_bus_2_lite_wvalid,
m_axi_wready => int_bus_2_lite_wready,
m_axi_wdata => int_bus_2_lite_wdata,
m_axi_wstrb => int_bus_2_lite_wstrb,
m_axi_bvalid => int_bus_2_lite_bvalid,
m_axi_bready => int_bus_2_lite_bready,
m_axi_bresp => int_bus_2_lite_bresp,
m_axi_araddr => int_bus_2_lite_araddr,
m_axi_arprot => int_bus_2_lite_arprot,
m_axi_arvalid => int_bus_2_lite_arvalid,
m_axi_arready => int_bus_2_lite_arready,
m_axi_rdata => int_bus_2_lite_rdata,
m_axi_rvalid => int_bus_2_lite_rvalid,
m_axi_rready => int_bus_2_lite_rready,
m_axi_rresp => int_bus_2_lite_rresp);
---------------------------------------------
-- CPU Signal AXI Full2Lite Instantiations --
---------------------------------------------
signal_0_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => signal_bus_0_full_awid,
s_axi_awaddr => signal_bus_0_full_awaddr,
s_axi_awlen => signal_bus_0_full_awlen,
s_axi_awsize => signal_bus_0_full_awsize,
s_axi_awburst => signal_bus_0_full_awburst,
s_axi_awlock => signal_bus_0_full_awlock,
s_axi_awcache => signal_bus_0_full_awcache,
s_axi_awprot => signal_bus_0_full_awprot,
s_axi_awqos => signal_bus_0_full_awqos,
s_axi_awregion => signal_bus_0_full_awregion,
s_axi_awvalid => signal_bus_0_full_awvalid,
s_axi_awready => signal_bus_0_full_awready,
s_axi_wdata => signal_bus_0_full_wdata,
s_axi_wstrb => signal_bus_0_full_wstrb,
s_axi_wlast => signal_bus_0_full_wlast,
s_axi_wvalid => signal_bus_0_full_wvalid,
s_axi_wready => signal_bus_0_full_wready,
s_axi_bid => signal_bus_0_full_bid,
s_axi_bresp => signal_bus_0_full_bresp,
s_axi_bvalid => signal_bus_0_full_bvalid,
s_axi_bready => signal_bus_0_full_bready,
s_axi_arid => signal_bus_0_full_arid,
s_axi_araddr => signal_bus_0_full_araddr,
s_axi_arlen => signal_bus_0_full_arlen,
s_axi_arsize => signal_bus_0_full_arsize,
s_axi_arburst => signal_bus_0_full_arburst,
s_axi_arlock => signal_bus_0_full_arlock,
s_axi_arcache => signal_bus_0_full_arcache,
s_axi_arprot => signal_bus_0_full_arprot,
s_axi_arqos => signal_bus_0_full_arqos,
s_axi_arregion => signal_bus_0_full_arregion,
s_axi_arvalid => signal_bus_0_full_arvalid,
s_axi_arready => signal_bus_0_full_arready,
s_axi_rid => signal_bus_0_full_rid,
s_axi_rdata => signal_bus_0_full_rdata,
s_axi_rresp => signal_bus_0_full_rresp,
s_axi_rlast => signal_bus_0_full_rlast,
s_axi_rvalid => signal_bus_0_full_rvalid,
s_axi_rready => signal_bus_0_full_rready,
m_axi_awaddr => signal_bus_0_lite_awaddr,
m_axi_awprot => signal_bus_0_lite_awprot,
m_axi_awvalid => signal_bus_0_lite_awvalid,
m_axi_awready => signal_bus_0_lite_awready,
m_axi_wvalid => signal_bus_0_lite_wvalid,
m_axi_wready => signal_bus_0_lite_wready,
m_axi_wdata => signal_bus_0_lite_wdata,
m_axi_wstrb => signal_bus_0_lite_wstrb,
m_axi_bvalid => signal_bus_0_lite_bvalid,
m_axi_bready => signal_bus_0_lite_bready,
m_axi_bresp => signal_bus_0_lite_bresp,
m_axi_araddr => signal_bus_0_lite_araddr,
m_axi_arprot => signal_bus_0_lite_arprot,
m_axi_arvalid => signal_bus_0_lite_arvalid,
m_axi_arready => signal_bus_0_lite_arready,
m_axi_rdata => signal_bus_0_lite_rdata,
m_axi_rvalid => signal_bus_0_lite_rvalid,
m_axi_rready => signal_bus_0_lite_rready,
m_axi_rresp => signal_bus_0_lite_rresp);
signal_1_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => signal_bus_1_full_awid,
s_axi_awaddr => signal_bus_1_full_awaddr,
s_axi_awlen => signal_bus_1_full_awlen,
s_axi_awsize => signal_bus_1_full_awsize,
s_axi_awburst => signal_bus_1_full_awburst,
s_axi_awlock => signal_bus_1_full_awlock,
s_axi_awcache => signal_bus_1_full_awcache,
s_axi_awprot => signal_bus_1_full_awprot,
s_axi_awqos => signal_bus_1_full_awqos,
s_axi_awregion => signal_bus_1_full_awregion,
s_axi_awvalid => signal_bus_1_full_awvalid,
s_axi_awready => signal_bus_1_full_awready,
s_axi_wdata => signal_bus_1_full_wdata,
s_axi_wstrb => signal_bus_1_full_wstrb,
s_axi_wlast => signal_bus_1_full_wlast,
s_axi_wvalid => signal_bus_1_full_wvalid,
s_axi_wready => signal_bus_1_full_wready,
s_axi_bid => signal_bus_1_full_bid,
s_axi_bresp => signal_bus_1_full_bresp,
s_axi_bvalid => signal_bus_1_full_bvalid,
s_axi_bready => signal_bus_1_full_bready,
s_axi_arid => signal_bus_1_full_arid,
s_axi_araddr => signal_bus_1_full_araddr,
s_axi_arlen => signal_bus_1_full_arlen,
s_axi_arsize => signal_bus_1_full_arsize,
s_axi_arburst => signal_bus_1_full_arburst,
s_axi_arlock => signal_bus_1_full_arlock,
s_axi_arcache => signal_bus_1_full_arcache,
s_axi_arprot => signal_bus_1_full_arprot,
s_axi_arqos => signal_bus_1_full_arqos,
s_axi_arregion => signal_bus_1_full_arregion,
s_axi_arvalid => signal_bus_1_full_arvalid,
s_axi_arready => signal_bus_1_full_arready,
s_axi_rid => signal_bus_1_full_rid,
s_axi_rdata => signal_bus_1_full_rdata,
s_axi_rresp => signal_bus_1_full_rresp,
s_axi_rlast => signal_bus_1_full_rlast,
s_axi_rvalid => signal_bus_1_full_rvalid,
s_axi_rready => signal_bus_1_full_rready,
m_axi_awaddr => signal_bus_1_lite_awaddr,
m_axi_awprot => signal_bus_1_lite_awprot,
m_axi_awvalid => signal_bus_1_lite_awvalid,
m_axi_awready => signal_bus_1_lite_awready,
m_axi_wvalid => signal_bus_1_lite_wvalid,
m_axi_wready => signal_bus_1_lite_wready,
m_axi_wdata => signal_bus_1_lite_wdata,
m_axi_wstrb => signal_bus_1_lite_wstrb,
m_axi_bvalid => signal_bus_1_lite_bvalid,
m_axi_bready => signal_bus_1_lite_bready,
m_axi_bresp => signal_bus_1_lite_bresp,
m_axi_araddr => signal_bus_1_lite_araddr,
m_axi_arprot => signal_bus_1_lite_arprot,
m_axi_arvalid => signal_bus_1_lite_arvalid,
m_axi_arready => signal_bus_1_lite_arready,
m_axi_rdata => signal_bus_1_lite_rdata,
m_axi_rvalid => signal_bus_1_lite_rvalid,
m_axi_rready => signal_bus_1_lite_rready,
m_axi_rresp => signal_bus_1_lite_rresp);
signal_2_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => signal_bus_2_full_awid,
s_axi_awaddr => signal_bus_2_full_awaddr,
s_axi_awlen => signal_bus_2_full_awlen,
s_axi_awsize => signal_bus_2_full_awsize,
s_axi_awburst => signal_bus_2_full_awburst,
s_axi_awlock => signal_bus_2_full_awlock,
s_axi_awcache => signal_bus_2_full_awcache,
s_axi_awprot => signal_bus_2_full_awprot,
s_axi_awqos => signal_bus_2_full_awqos,
s_axi_awregion => signal_bus_2_full_awregion,
s_axi_awvalid => signal_bus_2_full_awvalid,
s_axi_awready => signal_bus_2_full_awready,
s_axi_wdata => signal_bus_2_full_wdata,
s_axi_wstrb => signal_bus_2_full_wstrb,
s_axi_wlast => signal_bus_2_full_wlast,
s_axi_wvalid => signal_bus_2_full_wvalid,
s_axi_wready => signal_bus_2_full_wready,
s_axi_bid => signal_bus_2_full_bid,
s_axi_bresp => signal_bus_2_full_bresp,
s_axi_bvalid => signal_bus_2_full_bvalid,
s_axi_bready => signal_bus_2_full_bready,
s_axi_arid => signal_bus_2_full_arid,
s_axi_araddr => signal_bus_2_full_araddr,
s_axi_arlen => signal_bus_2_full_arlen,
s_axi_arsize => signal_bus_2_full_arsize,
s_axi_arburst => signal_bus_2_full_arburst,
s_axi_arlock => signal_bus_2_full_arlock,
s_axi_arcache => signal_bus_2_full_arcache,
s_axi_arprot => signal_bus_2_full_arprot,
s_axi_arqos => signal_bus_2_full_arqos,
s_axi_arregion => signal_bus_2_full_arregion,
s_axi_arvalid => signal_bus_2_full_arvalid,
s_axi_arready => signal_bus_2_full_arready,
s_axi_rid => signal_bus_2_full_rid,
s_axi_rdata => signal_bus_2_full_rdata,
s_axi_rresp => signal_bus_2_full_rresp,
s_axi_rlast => signal_bus_2_full_rlast,
s_axi_rvalid => signal_bus_2_full_rvalid,
s_axi_rready => signal_bus_2_full_rready,
m_axi_awaddr => signal_bus_2_lite_awaddr,
m_axi_awprot => signal_bus_2_lite_awprot,
m_axi_awvalid => signal_bus_2_lite_awvalid,
m_axi_awready => signal_bus_2_lite_awready,
m_axi_wvalid => signal_bus_2_lite_wvalid,
m_axi_wready => signal_bus_2_lite_wready,
m_axi_wdata => signal_bus_2_lite_wdata,
m_axi_wstrb => signal_bus_2_lite_wstrb,
m_axi_bvalid => signal_bus_2_lite_bvalid,
m_axi_bready => signal_bus_2_lite_bready,
m_axi_bresp => signal_bus_2_lite_bresp,
m_axi_araddr => signal_bus_2_lite_araddr,
m_axi_arprot => signal_bus_2_lite_arprot,
m_axi_arvalid => signal_bus_2_lite_arvalid,
m_axi_arready => signal_bus_2_lite_arready,
m_axi_rdata => signal_bus_2_lite_rdata,
m_axi_rvalid => signal_bus_2_lite_rvalid,
m_axi_rready => signal_bus_2_lite_rready,
m_axi_rresp => signal_bus_2_lite_rresp);
------------------------------------------
-- CPU Timer AXI Full2Lite Instantiations --
------------------------------------------
timer_0_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => timer_bus_0_full_awid,
s_axi_awaddr => timer_bus_0_full_awaddr,
s_axi_awlen => timer_bus_0_full_awlen,
s_axi_awsize => timer_bus_0_full_awsize,
s_axi_awburst => timer_bus_0_full_awburst,
s_axi_awlock => timer_bus_0_full_awlock,
s_axi_awcache => timer_bus_0_full_awcache,
s_axi_awprot => timer_bus_0_full_awprot,
s_axi_awqos => timer_bus_0_full_awqos,
s_axi_awregion => timer_bus_0_full_awregion,
s_axi_awvalid => timer_bus_0_full_awvalid,
s_axi_awready => timer_bus_0_full_awready,
s_axi_wdata => timer_bus_0_full_wdata,
s_axi_wstrb => timer_bus_0_full_wstrb,
s_axi_wlast => timer_bus_0_full_wlast,
s_axi_wvalid => timer_bus_0_full_wvalid,
s_axi_wready => timer_bus_0_full_wready,
s_axi_bid => timer_bus_0_full_bid,
s_axi_bresp => timer_bus_0_full_bresp,
s_axi_bvalid => timer_bus_0_full_bvalid,
s_axi_bready => timer_bus_0_full_bready,
s_axi_arid => timer_bus_0_full_arid,
s_axi_araddr => timer_bus_0_full_araddr,
s_axi_arlen => timer_bus_0_full_arlen,
s_axi_arsize => timer_bus_0_full_arsize,
s_axi_arburst => timer_bus_0_full_arburst,
s_axi_arlock => timer_bus_0_full_arlock,
s_axi_arcache => timer_bus_0_full_arcache,
s_axi_arprot => timer_bus_0_full_arprot,
s_axi_arqos => timer_bus_0_full_arqos,
s_axi_arregion => timer_bus_0_full_arregion,
s_axi_arvalid => timer_bus_0_full_arvalid,
s_axi_arready => timer_bus_0_full_arready,
s_axi_rid => timer_bus_0_full_rid,
s_axi_rdata => timer_bus_0_full_rdata,
s_axi_rresp => timer_bus_0_full_rresp,
s_axi_rlast => timer_bus_0_full_rlast,
s_axi_rvalid => timer_bus_0_full_rvalid,
s_axi_rready => timer_bus_0_full_rready,
m_axi_awaddr => timer_bus_0_lite_awaddr,
m_axi_awprot => timer_bus_0_lite_awprot,
m_axi_awvalid => timer_bus_0_lite_awvalid,
m_axi_awready => timer_bus_0_lite_awready,
m_axi_wvalid => timer_bus_0_lite_wvalid,
m_axi_wready => timer_bus_0_lite_wready,
m_axi_wdata => timer_bus_0_lite_wdata,
m_axi_wstrb => timer_bus_0_lite_wstrb,
m_axi_bvalid => timer_bus_0_lite_bvalid,
m_axi_bready => timer_bus_0_lite_bready,
m_axi_bresp => timer_bus_0_lite_bresp,
m_axi_araddr => timer_bus_0_lite_araddr,
m_axi_arprot => timer_bus_0_lite_arprot,
m_axi_arvalid => timer_bus_0_lite_arvalid,
m_axi_arready => timer_bus_0_lite_arready,
m_axi_rdata => timer_bus_0_lite_rdata,
m_axi_rvalid => timer_bus_0_lite_rvalid,
m_axi_rready => timer_bus_0_lite_rready,
m_axi_rresp => timer_bus_0_lite_rresp);
timer_1_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => timer_bus_1_full_awid,
s_axi_awaddr => timer_bus_1_full_awaddr,
s_axi_awlen => timer_bus_1_full_awlen,
s_axi_awsize => timer_bus_1_full_awsize,
s_axi_awburst => timer_bus_1_full_awburst,
s_axi_awlock => timer_bus_1_full_awlock,
s_axi_awcache => timer_bus_1_full_awcache,
s_axi_awprot => timer_bus_1_full_awprot,
s_axi_awqos => timer_bus_1_full_awqos,
s_axi_awregion => timer_bus_1_full_awregion,
s_axi_awvalid => timer_bus_1_full_awvalid,
s_axi_awready => timer_bus_1_full_awready,
s_axi_wdata => timer_bus_1_full_wdata,
s_axi_wstrb => timer_bus_1_full_wstrb,
s_axi_wlast => timer_bus_1_full_wlast,
s_axi_wvalid => timer_bus_1_full_wvalid,
s_axi_wready => timer_bus_1_full_wready,
s_axi_bid => timer_bus_1_full_bid,
s_axi_bresp => timer_bus_1_full_bresp,
s_axi_bvalid => timer_bus_1_full_bvalid,
s_axi_bready => timer_bus_1_full_bready,
s_axi_arid => timer_bus_1_full_arid,
s_axi_araddr => timer_bus_1_full_araddr,
s_axi_arlen => timer_bus_1_full_arlen,
s_axi_arsize => timer_bus_1_full_arsize,
s_axi_arburst => timer_bus_1_full_arburst,
s_axi_arlock => timer_bus_1_full_arlock,
s_axi_arcache => timer_bus_1_full_arcache,
s_axi_arprot => timer_bus_1_full_arprot,
s_axi_arqos => timer_bus_1_full_arqos,
s_axi_arregion => timer_bus_1_full_arregion,
s_axi_arvalid => timer_bus_1_full_arvalid,
s_axi_arready => timer_bus_1_full_arready,
s_axi_rid => timer_bus_1_full_rid,
s_axi_rdata => timer_bus_1_full_rdata,
s_axi_rresp => timer_bus_1_full_rresp,
s_axi_rlast => timer_bus_1_full_rlast,
s_axi_rvalid => timer_bus_1_full_rvalid,
s_axi_rready => timer_bus_1_full_rready,
m_axi_awaddr => timer_bus_1_lite_awaddr,
m_axi_awprot => timer_bus_1_lite_awprot,
m_axi_awvalid => timer_bus_1_lite_awvalid,
m_axi_awready => timer_bus_1_lite_awready,
m_axi_wvalid => timer_bus_1_lite_wvalid,
m_axi_wready => timer_bus_1_lite_wready,
m_axi_wdata => timer_bus_1_lite_wdata,
m_axi_wstrb => timer_bus_1_lite_wstrb,
m_axi_bvalid => timer_bus_1_lite_bvalid,
m_axi_bready => timer_bus_1_lite_bready,
m_axi_bresp => timer_bus_1_lite_bresp,
m_axi_araddr => timer_bus_1_lite_araddr,
m_axi_arprot => timer_bus_1_lite_arprot,
m_axi_arvalid => timer_bus_1_lite_arvalid,
m_axi_arready => timer_bus_1_lite_arready,
m_axi_rdata => timer_bus_1_lite_rdata,
m_axi_rvalid => timer_bus_1_lite_rvalid,
m_axi_rready => timer_bus_1_lite_rready,
m_axi_rresp => timer_bus_1_lite_rresp);
timer_2_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_cpu_bus_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => timer_bus_2_full_awid,
s_axi_awaddr => timer_bus_2_full_awaddr,
s_axi_awlen => timer_bus_2_full_awlen,
s_axi_awsize => timer_bus_2_full_awsize,
s_axi_awburst => timer_bus_2_full_awburst,
s_axi_awlock => timer_bus_2_full_awlock,
s_axi_awcache => timer_bus_2_full_awcache,
s_axi_awprot => timer_bus_2_full_awprot,
s_axi_awqos => timer_bus_2_full_awqos,
s_axi_awregion => timer_bus_2_full_awregion,
s_axi_awvalid => timer_bus_2_full_awvalid,
s_axi_awready => timer_bus_2_full_awready,
s_axi_wdata => timer_bus_2_full_wdata,
s_axi_wstrb => timer_bus_2_full_wstrb,
s_axi_wlast => timer_bus_2_full_wlast,
s_axi_wvalid => timer_bus_2_full_wvalid,
s_axi_wready => timer_bus_2_full_wready,
s_axi_bid => timer_bus_2_full_bid,
s_axi_bresp => timer_bus_2_full_bresp,
s_axi_bvalid => timer_bus_2_full_bvalid,
s_axi_bready => timer_bus_2_full_bready,
s_axi_arid => timer_bus_2_full_arid,
s_axi_araddr => timer_bus_2_full_araddr,
s_axi_arlen => timer_bus_2_full_arlen,
s_axi_arsize => timer_bus_2_full_arsize,
s_axi_arburst => timer_bus_2_full_arburst,
s_axi_arlock => timer_bus_2_full_arlock,
s_axi_arcache => timer_bus_2_full_arcache,
s_axi_arprot => timer_bus_2_full_arprot,
s_axi_arqos => timer_bus_2_full_arqos,
s_axi_arregion => timer_bus_2_full_arregion,
s_axi_arvalid => timer_bus_2_full_arvalid,
s_axi_arready => timer_bus_2_full_arready,
s_axi_rid => timer_bus_2_full_rid,
s_axi_rdata => timer_bus_2_full_rdata,
s_axi_rresp => timer_bus_2_full_rresp,
s_axi_rlast => timer_bus_2_full_rlast,
s_axi_rvalid => timer_bus_2_full_rvalid,
s_axi_rready => timer_bus_2_full_rready,
m_axi_awaddr => timer_bus_2_lite_awaddr,
m_axi_awprot => timer_bus_2_lite_awprot,
m_axi_awvalid => timer_bus_2_lite_awvalid,
m_axi_awready => timer_bus_2_lite_awready,
m_axi_wvalid => timer_bus_2_lite_wvalid,
m_axi_wready => timer_bus_2_lite_wready,
m_axi_wdata => timer_bus_2_lite_wdata,
m_axi_wstrb => timer_bus_2_lite_wstrb,
m_axi_bvalid => timer_bus_2_lite_bvalid,
m_axi_bready => timer_bus_2_lite_bready,
m_axi_bresp => timer_bus_2_lite_bresp,
m_axi_araddr => timer_bus_2_lite_araddr,
m_axi_arprot => timer_bus_2_lite_arprot,
m_axi_arvalid => timer_bus_2_lite_arvalid,
m_axi_arready => timer_bus_2_lite_arready,
m_axi_rdata => timer_bus_2_lite_rdata,
m_axi_rvalid => timer_bus_2_lite_rvalid,
m_axi_rready => timer_bus_2_lite_rready,
m_axi_rresp => timer_bus_2_lite_rresp);
----------------------------------------------------
-- Main Interconnect AXI Full2Lite Instantiations --
----------------------------------------------------
int_main_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => int_axi_full_awid,
s_axi_awaddr => int_axi_full_awaddr,
s_axi_awlen => int_axi_full_awlen,
s_axi_awsize => int_axi_full_awsize,
s_axi_awburst => int_axi_full_awburst,
s_axi_awlock => int_axi_full_awlock,
s_axi_awcache => int_axi_full_awcache,
s_axi_awprot => int_axi_full_awprot,
s_axi_awqos => int_axi_full_awqos,
s_axi_awregion => int_axi_full_awregion,
s_axi_awvalid => int_axi_full_awvalid,
s_axi_awready => int_axi_full_awready,
s_axi_wdata => int_axi_full_wdata,
s_axi_wstrb => int_axi_full_wstrb,
s_axi_wlast => int_axi_full_wlast,
s_axi_wvalid => int_axi_full_wvalid,
s_axi_wready => int_axi_full_wready,
s_axi_bid => int_axi_full_bid,
s_axi_bresp => int_axi_full_bresp,
s_axi_bvalid => int_axi_full_bvalid,
s_axi_bready => int_axi_full_bready,
s_axi_arid => int_axi_full_arid,
s_axi_araddr => int_axi_full_araddr,
s_axi_arlen => int_axi_full_arlen,
s_axi_arsize => int_axi_full_arsize,
s_axi_arburst => int_axi_full_arburst,
s_axi_arlock => int_axi_full_arlock,
s_axi_arcache => int_axi_full_arcache,
s_axi_arprot => int_axi_full_arprot,
s_axi_arqos => int_axi_full_arqos,
s_axi_arregion => int_axi_full_arregion,
s_axi_arvalid => int_axi_full_arvalid,
s_axi_arready => int_axi_full_arready,
s_axi_rid => int_axi_full_rid,
s_axi_rdata => int_axi_full_rdata,
s_axi_rresp => int_axi_full_rresp,
s_axi_rlast => int_axi_full_rlast,
s_axi_rvalid => int_axi_full_rvalid,
s_axi_rready => int_axi_full_rready,
m_axi_awaddr => int_axi_lite_awaddr,
m_axi_awprot => int_axi_lite_awprot,
m_axi_awvalid => int_axi_lite_awvalid,
m_axi_awready => int_axi_lite_awready,
m_axi_wvalid => int_axi_lite_wvalid,
m_axi_wready => int_axi_lite_wready,
m_axi_wdata => int_axi_lite_wdata,
m_axi_wstrb => int_axi_lite_wstrb,
m_axi_bvalid => int_axi_lite_bvalid,
m_axi_bready => int_axi_lite_bready,
m_axi_bresp => int_axi_lite_bresp,
m_axi_araddr => int_axi_lite_araddr,
m_axi_arprot => int_axi_lite_arprot,
m_axi_arvalid => int_axi_lite_arvalid,
m_axi_arready => int_axi_lite_arready,
m_axi_rdata => int_axi_lite_rdata,
m_axi_rvalid => int_axi_lite_rvalid,
m_axi_rready => int_axi_lite_rready,
m_axi_rresp => int_axi_lite_rresp);
timer_main_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => timer_axi_full_awid,
s_axi_awaddr => timer_axi_full_awaddr,
s_axi_awlen => timer_axi_full_awlen,
s_axi_awsize => timer_axi_full_awsize,
s_axi_awburst => timer_axi_full_awburst,
s_axi_awlock => timer_axi_full_awlock,
s_axi_awcache => timer_axi_full_awcache,
s_axi_awprot => timer_axi_full_awprot,
s_axi_awqos => timer_axi_full_awqos,
s_axi_awregion => timer_axi_full_awregion,
s_axi_awvalid => timer_axi_full_awvalid,
s_axi_awready => timer_axi_full_awready,
s_axi_wdata => timer_axi_full_wdata,
s_axi_wstrb => timer_axi_full_wstrb,
s_axi_wlast => timer_axi_full_wlast,
s_axi_wvalid => timer_axi_full_wvalid,
s_axi_wready => timer_axi_full_wready,
s_axi_bid => timer_axi_full_bid,
s_axi_bresp => timer_axi_full_bresp,
s_axi_bvalid => timer_axi_full_bvalid,
s_axi_bready => timer_axi_full_bready,
s_axi_arid => timer_axi_full_arid,
s_axi_araddr => timer_axi_full_araddr,
s_axi_arlen => timer_axi_full_arlen,
s_axi_arsize => timer_axi_full_arsize,
s_axi_arburst => timer_axi_full_arburst,
s_axi_arlock => timer_axi_full_arlock,
s_axi_arcache => timer_axi_full_arcache,
s_axi_arprot => timer_axi_full_arprot,
s_axi_arqos => timer_axi_full_arqos,
s_axi_arregion => timer_axi_full_arregion,
s_axi_arvalid => timer_axi_full_arvalid,
s_axi_arready => timer_axi_full_arready,
s_axi_rid => timer_axi_full_rid,
s_axi_rdata => timer_axi_full_rdata,
s_axi_rresp => timer_axi_full_rresp,
s_axi_rlast => timer_axi_full_rlast,
s_axi_rvalid => timer_axi_full_rvalid,
s_axi_rready => timer_axi_full_rready,
m_axi_awaddr => timer_axi_lite_awaddr,
m_axi_awprot => timer_axi_lite_awprot,
m_axi_awvalid => timer_axi_lite_awvalid,
m_axi_awready => timer_axi_lite_awready,
m_axi_wvalid => timer_axi_lite_wvalid,
m_axi_wready => timer_axi_lite_wready,
m_axi_wdata => timer_axi_lite_wdata,
m_axi_wstrb => timer_axi_lite_wstrb,
m_axi_bvalid => timer_axi_lite_bvalid,
m_axi_bready => timer_axi_lite_bready,
m_axi_bresp => timer_axi_lite_bresp,
m_axi_araddr => timer_axi_lite_araddr,
m_axi_arprot => timer_axi_lite_arprot,
m_axi_arvalid => timer_axi_lite_arvalid,
m_axi_arready => timer_axi_lite_arready,
m_axi_rdata => timer_axi_lite_rdata,
m_axi_rvalid => timer_axi_lite_rvalid,
m_axi_rready => timer_axi_lite_rready,
m_axi_rresp => timer_axi_lite_rresp);
gpio_main_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => gpio_axi_full_awid,
s_axi_awaddr => gpio_axi_full_awaddr,
s_axi_awlen => gpio_axi_full_awlen,
s_axi_awsize => gpio_axi_full_awsize,
s_axi_awburst => gpio_axi_full_awburst,
s_axi_awlock => gpio_axi_full_awlock,
s_axi_awcache => gpio_axi_full_awcache,
s_axi_awprot => gpio_axi_full_awprot,
s_axi_awqos => gpio_axi_full_awqos,
s_axi_awregion => gpio_axi_full_awregion,
s_axi_awvalid => gpio_axi_full_awvalid,
s_axi_awready => gpio_axi_full_awready,
s_axi_wdata => gpio_axi_full_wdata,
s_axi_wstrb => gpio_axi_full_wstrb,
s_axi_wlast => gpio_axi_full_wlast,
s_axi_wvalid => gpio_axi_full_wvalid,
s_axi_wready => gpio_axi_full_wready,
s_axi_bid => gpio_axi_full_bid,
s_axi_bresp => gpio_axi_full_bresp,
s_axi_bvalid => gpio_axi_full_bvalid,
s_axi_bready => gpio_axi_full_bready,
s_axi_arid => gpio_axi_full_arid,
s_axi_araddr => gpio_axi_full_araddr,
s_axi_arlen => gpio_axi_full_arlen,
s_axi_arsize => gpio_axi_full_arsize,
s_axi_arburst => gpio_axi_full_arburst,
s_axi_arlock => gpio_axi_full_arlock,
s_axi_arcache => gpio_axi_full_arcache,
s_axi_arprot => gpio_axi_full_arprot,
s_axi_arqos => gpio_axi_full_arqos,
s_axi_arregion => gpio_axi_full_arregion,
s_axi_arvalid => gpio_axi_full_arvalid,
s_axi_arready => gpio_axi_full_arready,
s_axi_rid => gpio_axi_full_rid,
s_axi_rdata => gpio_axi_full_rdata,
s_axi_rresp => gpio_axi_full_rresp,
s_axi_rlast => gpio_axi_full_rlast,
s_axi_rvalid => gpio_axi_full_rvalid,
s_axi_rready => gpio_axi_full_rready,
m_axi_awaddr => gpio_axi_lite_awaddr,
m_axi_awprot => gpio_axi_lite_awprot,
m_axi_awvalid => gpio_axi_lite_awvalid,
m_axi_awready => gpio_axi_lite_awready,
m_axi_wvalid => gpio_axi_lite_wvalid,
m_axi_wready => gpio_axi_lite_wready,
m_axi_wdata => gpio_axi_lite_wdata,
m_axi_wstrb => gpio_axi_lite_wstrb,
m_axi_bvalid => gpio_axi_lite_bvalid,
m_axi_bready => gpio_axi_lite_bready,
m_axi_bresp => gpio_axi_lite_bresp,
m_axi_araddr => gpio_axi_lite_araddr,
m_axi_arprot => gpio_axi_lite_arprot,
m_axi_arvalid => gpio_axi_lite_arvalid,
m_axi_arready => gpio_axi_lite_arready,
m_axi_rdata => gpio_axi_lite_rdata,
m_axi_rvalid => gpio_axi_lite_rvalid,
m_axi_rready => gpio_axi_lite_rready,
m_axi_rresp => gpio_axi_lite_rresp);
uart_main_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => uart_axi_full_awid,
s_axi_awaddr => uart_axi_full_awaddr,
s_axi_awlen => uart_axi_full_awlen,
s_axi_awsize => uart_axi_full_awsize,
s_axi_awburst => uart_axi_full_awburst,
s_axi_awlock => uart_axi_full_awlock,
s_axi_awcache => uart_axi_full_awcache,
s_axi_awprot => uart_axi_full_awprot,
s_axi_awqos => uart_axi_full_awqos,
s_axi_awregion => uart_axi_full_awregion,
s_axi_awvalid => uart_axi_full_awvalid,
s_axi_awready => uart_axi_full_awready,
s_axi_wdata => uart_axi_full_wdata,
s_axi_wstrb => uart_axi_full_wstrb,
s_axi_wlast => uart_axi_full_wlast,
s_axi_wvalid => uart_axi_full_wvalid,
s_axi_wready => uart_axi_full_wready,
s_axi_bid => uart_axi_full_bid,
s_axi_bresp => uart_axi_full_bresp,
s_axi_bvalid => uart_axi_full_bvalid,
s_axi_bready => uart_axi_full_bready,
s_axi_arid => uart_axi_full_arid,
s_axi_araddr => uart_axi_full_araddr,
s_axi_arlen => uart_axi_full_arlen,
s_axi_arsize => uart_axi_full_arsize,
s_axi_arburst => uart_axi_full_arburst,
s_axi_arlock => uart_axi_full_arlock,
s_axi_arcache => uart_axi_full_arcache,
s_axi_arprot => uart_axi_full_arprot,
s_axi_arqos => uart_axi_full_arqos,
s_axi_arregion => uart_axi_full_arregion,
s_axi_arvalid => uart_axi_full_arvalid,
s_axi_arready => uart_axi_full_arready,
s_axi_rid => uart_axi_full_rid,
s_axi_rdata => uart_axi_full_rdata,
s_axi_rresp => uart_axi_full_rresp,
s_axi_rlast => uart_axi_full_rlast,
s_axi_rvalid => uart_axi_full_rvalid,
s_axi_rready => uart_axi_full_rready,
m_axi_awaddr => uart_axi_lite_awaddr,
m_axi_awprot => uart_axi_lite_awprot,
m_axi_awvalid => uart_axi_lite_awvalid,
m_axi_awready => uart_axi_lite_awready,
m_axi_wvalid => uart_axi_lite_wvalid,
m_axi_wready => uart_axi_lite_wready,
m_axi_wdata => uart_axi_lite_wdata,
m_axi_wstrb => uart_axi_lite_wstrb,
m_axi_bvalid => uart_axi_lite_bvalid,
m_axi_bready => uart_axi_lite_bready,
m_axi_bresp => uart_axi_lite_bresp,
m_axi_araddr => uart_axi_lite_araddr,
m_axi_arprot => uart_axi_lite_arprot,
m_axi_arvalid => uart_axi_lite_arvalid,
m_axi_arready => uart_axi_lite_arready,
m_axi_rdata => uart_axi_lite_rdata,
m_axi_rvalid => uart_axi_lite_rvalid,
m_axi_rready => uart_axi_lite_rready,
m_axi_rresp => uart_axi_lite_rresp);
lock_main_full2lite : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
s_axi_awid => lock_axi_full_awid,
s_axi_awaddr => lock_axi_full_awaddr,
s_axi_awlen => lock_axi_full_awlen,
s_axi_awsize => lock_axi_full_awsize,
s_axi_awburst => lock_axi_full_awburst,
s_axi_awlock => lock_axi_full_awlock,
s_axi_awcache => lock_axi_full_awcache,
s_axi_awprot => lock_axi_full_awprot,
s_axi_awqos => lock_axi_full_awqos,
s_axi_awregion => lock_axi_full_awregion,
s_axi_awvalid => lock_axi_full_awvalid,
s_axi_awready => lock_axi_full_awready,
s_axi_wdata => lock_axi_full_wdata,
s_axi_wstrb => lock_axi_full_wstrb,
s_axi_wlast => lock_axi_full_wlast,
s_axi_wvalid => lock_axi_full_wvalid,
s_axi_wready => lock_axi_full_wready,
s_axi_bid => lock_axi_full_bid,
s_axi_bresp => lock_axi_full_bresp,
s_axi_bvalid => lock_axi_full_bvalid,
s_axi_bready => lock_axi_full_bready,
s_axi_arid => lock_axi_full_arid,
s_axi_araddr => lock_axi_full_araddr,
s_axi_arlen => lock_axi_full_arlen,
s_axi_arsize => lock_axi_full_arsize,
s_axi_arburst => lock_axi_full_arburst,
s_axi_arlock => lock_axi_full_arlock,
s_axi_arcache => lock_axi_full_arcache,
s_axi_arprot => lock_axi_full_arprot,
s_axi_arqos => lock_axi_full_arqos,
s_axi_arregion => lock_axi_full_arregion,
s_axi_arvalid => lock_axi_full_arvalid,
s_axi_arready => lock_axi_full_arready,
s_axi_rid => lock_axi_full_rid,
s_axi_rdata => lock_axi_full_rdata,
s_axi_rresp => lock_axi_full_rresp,
s_axi_rlast => lock_axi_full_rlast,
s_axi_rvalid => lock_axi_full_rvalid,
s_axi_rready => lock_axi_full_rready,
m_axi_awaddr => lock_axi_lite_awaddr,
m_axi_awprot => lock_axi_lite_awprot,
m_axi_awvalid => lock_axi_lite_awvalid,
m_axi_awready => lock_axi_lite_awready,
m_axi_wvalid => lock_axi_lite_wvalid,
m_axi_wready => lock_axi_lite_wready,
m_axi_wdata => lock_axi_lite_wdata,
m_axi_wstrb => lock_axi_lite_wstrb,
m_axi_bvalid => lock_axi_lite_bvalid,
m_axi_bready => lock_axi_lite_bready,
m_axi_bresp => lock_axi_lite_bresp,
m_axi_araddr => lock_axi_lite_araddr,
m_axi_arprot => lock_axi_lite_arprot,
m_axi_arvalid => lock_axi_lite_arvalid,
m_axi_arready => lock_axi_lite_arready,
m_axi_rdata => lock_axi_lite_rdata,
m_axi_rvalid => lock_axi_lite_rvalid,
m_axi_rready => lock_axi_lite_rready,
m_axi_rresp => lock_axi_lite_rresp);
----------------------
-- CPUID GPIO Cores --
----------------------
cpuid_gpio_0_inst : plasoc_gpio
generic map (
data_in_width => axi_data_width,
data_out_width => 0,
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
data_in => std_logic_vector(to_unsigned(0,axi_data_width)),
data_out => open,
axi_awaddr => cpuid_gpio_bus_0_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => cpuid_gpio_bus_0_lite_awprot,
axi_awvalid => cpuid_gpio_bus_0_lite_awvalid,
axi_awready => cpuid_gpio_bus_0_lite_awready,
axi_wvalid => cpuid_gpio_bus_0_lite_wvalid,
axi_wready => cpuid_gpio_bus_0_lite_wready,
axi_wdata => cpuid_gpio_bus_0_lite_wdata,
axi_wstrb => cpuid_gpio_bus_0_lite_wstrb,
axi_bvalid => cpuid_gpio_bus_0_lite_bvalid,
axi_bready => cpuid_gpio_bus_0_lite_bready,
axi_bresp => cpuid_gpio_bus_0_lite_bresp,
axi_araddr => cpuid_gpio_bus_0_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => cpuid_gpio_bus_0_lite_arprot,
axi_arvalid => cpuid_gpio_bus_0_lite_arvalid,
axi_arready => cpuid_gpio_bus_0_lite_arready,
axi_rdata => cpuid_gpio_bus_0_lite_rdata,
axi_rvalid => cpuid_gpio_bus_0_lite_rvalid,
axi_rready => cpuid_gpio_bus_0_lite_rready,
axi_rresp => cpuid_gpio_bus_0_lite_rresp,
int => open);
cpuid_gpio_1_inst : plasoc_gpio
generic map (
data_in_width => axi_data_width,
data_out_width => 0,
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
data_in => std_logic_vector(to_unsigned(1,axi_data_width)),
data_out => open,
axi_awaddr => cpuid_gpio_bus_1_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => cpuid_gpio_bus_1_lite_awprot,
axi_awvalid => cpuid_gpio_bus_1_lite_awvalid,
axi_awready => cpuid_gpio_bus_1_lite_awready,
axi_wvalid => cpuid_gpio_bus_1_lite_wvalid,
axi_wready => cpuid_gpio_bus_1_lite_wready,
axi_wdata => cpuid_gpio_bus_1_lite_wdata,
axi_wstrb => cpuid_gpio_bus_1_lite_wstrb,
axi_bvalid => cpuid_gpio_bus_1_lite_bvalid,
axi_bready => cpuid_gpio_bus_1_lite_bready,
axi_bresp => cpuid_gpio_bus_1_lite_bresp,
axi_araddr => cpuid_gpio_bus_1_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => cpuid_gpio_bus_1_lite_arprot,
axi_arvalid => cpuid_gpio_bus_1_lite_arvalid,
axi_arready => cpuid_gpio_bus_1_lite_arready,
axi_rdata => cpuid_gpio_bus_1_lite_rdata,
axi_rvalid => cpuid_gpio_bus_1_lite_rvalid,
axi_rready => cpuid_gpio_bus_1_lite_rready,
axi_rresp => cpuid_gpio_bus_1_lite_rresp,
int => open);
cpuid_gpio_2_inst : plasoc_gpio
generic map (
data_in_width => axi_data_width,
data_out_width => 0,
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
data_in => std_logic_vector(to_unsigned(2,axi_data_width)),
data_out => open,
axi_awaddr => cpuid_gpio_bus_2_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => cpuid_gpio_bus_2_lite_awprot,
axi_awvalid => cpuid_gpio_bus_2_lite_awvalid,
axi_awready => cpuid_gpio_bus_2_lite_awready,
axi_wvalid => cpuid_gpio_bus_2_lite_wvalid,
axi_wready => cpuid_gpio_bus_2_lite_wready,
axi_wdata => cpuid_gpio_bus_2_lite_wdata,
axi_wstrb => cpuid_gpio_bus_2_lite_wstrb,
axi_bvalid => cpuid_gpio_bus_2_lite_bvalid,
axi_bready => cpuid_gpio_bus_2_lite_bready,
axi_bresp => cpuid_gpio_bus_2_lite_bresp,
axi_araddr => cpuid_gpio_bus_2_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => cpuid_gpio_bus_2_lite_arprot,
axi_arvalid => cpuid_gpio_bus_2_lite_arvalid,
axi_arready => cpuid_gpio_bus_2_lite_arready,
axi_rdata => cpuid_gpio_bus_2_lite_rdata,
axi_rvalid => cpuid_gpio_bus_2_lite_rvalid,
axi_rready => cpuid_gpio_bus_2_lite_rready,
axi_rresp => cpuid_gpio_bus_2_lite_rresp,
int => open);
-------------------
-- CPU INT Cores --
-------------------
int_0_inst : plasoc_int
generic map (
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => int_bus_0_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => int_bus_0_lite_awprot,
axi_awvalid => int_bus_0_lite_awvalid,
axi_awready => int_bus_0_lite_awready,
axi_wvalid => int_bus_0_lite_wvalid,
axi_wready => int_bus_0_lite_wready,
axi_wdata => int_bus_0_lite_wdata,
axi_wstrb => int_bus_0_lite_wstrb,
axi_bvalid => int_bus_0_lite_bvalid,
axi_bready => int_bus_0_lite_bready,
axi_bresp => int_bus_0_lite_bresp,
axi_araddr => int_bus_0_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => int_bus_0_lite_arprot,
axi_arvalid => int_bus_0_lite_arvalid,
axi_arready => int_bus_0_lite_arready,
axi_rdata => int_bus_0_lite_rdata,
axi_rvalid => int_bus_0_lite_rvalid,
axi_rready => int_bus_0_lite_rready,
axi_rresp => int_bus_0_lite_rresp,
cpu_int => cpu_0_int,
dev_ints => dev_0_ints);
int_1_inst : plasoc_int
generic map (
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => int_bus_1_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => int_bus_1_lite_awprot,
axi_awvalid => int_bus_1_lite_awvalid,
axi_awready => int_bus_1_lite_awready,
axi_wvalid => int_bus_1_lite_wvalid,
axi_wready => int_bus_1_lite_wready,
axi_wdata => int_bus_1_lite_wdata,
axi_wstrb => int_bus_1_lite_wstrb,
axi_bvalid => int_bus_1_lite_bvalid,
axi_bready => int_bus_1_lite_bready,
axi_bresp => int_bus_1_lite_bresp,
axi_araddr => int_bus_1_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => int_bus_1_lite_arprot,
axi_arvalid => int_bus_1_lite_arvalid,
axi_arready => int_bus_1_lite_arready,
axi_rdata => int_bus_1_lite_rdata,
axi_rvalid => int_bus_1_lite_rvalid,
axi_rready => int_bus_1_lite_rready,
axi_rresp => int_bus_1_lite_rresp,
cpu_int => cpu_1_int,
dev_ints => dev_1_ints);
int_2_inst : plasoc_int
generic map (
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => int_bus_2_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => int_bus_2_lite_awprot,
axi_awvalid => int_bus_2_lite_awvalid,
axi_awready => int_bus_2_lite_awready,
axi_wvalid => int_bus_2_lite_wvalid,
axi_wready => int_bus_2_lite_wready,
axi_wdata => int_bus_2_lite_wdata,
axi_wstrb => int_bus_2_lite_wstrb,
axi_bvalid => int_bus_2_lite_bvalid,
axi_bready => int_bus_2_lite_bready,
axi_bresp => int_bus_2_lite_bresp,
axi_araddr => int_bus_2_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => int_bus_2_lite_arprot,
axi_arvalid => int_bus_2_lite_arvalid,
axi_arready => int_bus_2_lite_arready,
axi_rdata => int_bus_2_lite_rdata,
axi_rvalid => int_bus_2_lite_rvalid,
axi_rready => int_bus_2_lite_rready,
axi_rresp => int_bus_2_lite_rresp,
cpu_int => cpu_2_int,
dev_ints => dev_2_ints);
----------------------
-- CPU Signal Cores --
----------------------
signal_0_inst : koc_signal
generic map (
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => signal_bus_0_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => signal_bus_0_lite_awprot,
axi_awvalid => signal_bus_0_lite_awvalid,
axi_awready => signal_bus_0_lite_awready,
axi_wvalid => signal_bus_0_lite_wvalid,
axi_wready => signal_bus_0_lite_wready,
axi_wdata => signal_bus_0_lite_wdata,
axi_wstrb => signal_bus_0_lite_wstrb,
axi_bvalid => signal_bus_0_lite_bvalid,
axi_bready => signal_bus_0_lite_bready,
axi_bresp => signal_bus_0_lite_bresp,
axi_araddr => signal_bus_0_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => signal_bus_0_lite_arprot,
axi_arvalid => signal_bus_0_lite_arvalid,
axi_arready => signal_bus_0_lite_arready,
axi_rdata => signal_bus_0_lite_rdata,
axi_rvalid => signal_bus_0_lite_rvalid,
axi_rready => signal_bus_0_lite_rready,
axi_rresp => signal_bus_0_lite_rresp,
sig_out => sig_0_1,
sig_in => '0',
int => dev_0_ints(0));
signal_1_inst : koc_signal
generic map (
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => signal_bus_1_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => signal_bus_1_lite_awprot,
axi_awvalid => signal_bus_1_lite_awvalid,
axi_awready => signal_bus_1_lite_awready,
axi_wvalid => signal_bus_1_lite_wvalid,
axi_wready => signal_bus_1_lite_wready,
axi_wdata => signal_bus_1_lite_wdata,
axi_wstrb => signal_bus_1_lite_wstrb,
axi_bvalid => signal_bus_1_lite_bvalid,
axi_bready => signal_bus_1_lite_bready,
axi_bresp => signal_bus_1_lite_bresp,
axi_araddr => signal_bus_1_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => signal_bus_1_lite_arprot,
axi_arvalid => signal_bus_1_lite_arvalid,
axi_arready => signal_bus_1_lite_arready,
axi_rdata => signal_bus_1_lite_rdata,
axi_rvalid => signal_bus_1_lite_rvalid,
axi_rready => signal_bus_1_lite_rready,
axi_rresp => signal_bus_1_lite_rresp,
sig_out => sig_1_2,
sig_in => sig_0_1,
int => dev_1_ints(0));
signal_2_inst : koc_signal
generic map (
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => signal_bus_2_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => signal_bus_2_lite_awprot,
axi_awvalid => signal_bus_2_lite_awvalid,
axi_awready => signal_bus_2_lite_awready,
axi_wvalid => signal_bus_2_lite_wvalid,
axi_wready => signal_bus_2_lite_wready,
axi_wdata => signal_bus_2_lite_wdata,
axi_wstrb => signal_bus_2_lite_wstrb,
axi_bvalid => signal_bus_2_lite_bvalid,
axi_bready => signal_bus_2_lite_bready,
axi_bresp => signal_bus_2_lite_bresp,
axi_araddr => signal_bus_2_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => signal_bus_2_lite_arprot,
axi_arvalid => signal_bus_2_lite_arvalid,
axi_arready => signal_bus_2_lite_arready,
axi_rdata => signal_bus_2_lite_rdata,
axi_rvalid => signal_bus_2_lite_rvalid,
axi_rready => signal_bus_2_lite_rready,
axi_rresp => signal_bus_2_lite_rresp,
sig_out => open,
sig_in => sig_1_2,
int => dev_2_ints(0));
---------------------
-- CPU Timer Cores --
---------------------
time_0_inst : plasoc_timer
generic map (
timer_width => axi_data_width,
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => timer_bus_0_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => timer_bus_0_lite_awprot,
axi_awvalid => timer_bus_0_lite_awvalid,
axi_awready => timer_bus_0_lite_awready,
axi_wvalid => timer_bus_0_lite_wvalid,
axi_wready => timer_bus_0_lite_wready,
axi_wdata => timer_bus_0_lite_wdata,
axi_wstrb => timer_bus_0_lite_wstrb,
axi_bvalid => timer_bus_0_lite_bvalid,
axi_bready => timer_bus_0_lite_bready,
axi_bresp => timer_bus_0_lite_bresp,
axi_araddr => timer_bus_0_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => timer_bus_0_lite_arprot,
axi_arvalid => timer_bus_0_lite_arvalid,
axi_arready => timer_bus_0_lite_arready,
axi_rdata => timer_bus_0_lite_rdata,
axi_rvalid => timer_bus_0_lite_rvalid,
axi_rready => timer_bus_0_lite_rready,
axi_rresp => timer_bus_0_lite_rresp,
done => dev_0_ints(1));
time_1_inst : plasoc_timer
generic map (
timer_width => axi_data_width,
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => timer_bus_1_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => timer_bus_1_lite_awprot,
axi_awvalid => timer_bus_1_lite_awvalid,
axi_awready => timer_bus_1_lite_awready,
axi_wvalid => timer_bus_1_lite_wvalid,
axi_wready => timer_bus_1_lite_wready,
axi_wdata => timer_bus_1_lite_wdata,
axi_wstrb => timer_bus_1_lite_wstrb,
axi_bvalid => timer_bus_1_lite_bvalid,
axi_bready => timer_bus_1_lite_bready,
axi_bresp => timer_bus_1_lite_bresp,
axi_araddr => timer_bus_1_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => timer_bus_1_lite_arprot,
axi_arvalid => timer_bus_1_lite_arvalid,
axi_arready => timer_bus_1_lite_arready,
axi_rdata => timer_bus_1_lite_rdata,
axi_rvalid => timer_bus_1_lite_rvalid,
axi_rready => timer_bus_1_lite_rready,
axi_rresp => timer_bus_1_lite_rresp,
done => dev_1_ints(1));
time_2_inst : plasoc_timer
generic map (
timer_width => axi_data_width,
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => timer_bus_2_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => timer_bus_2_lite_awprot,
axi_awvalid => timer_bus_2_lite_awvalid,
axi_awready => timer_bus_2_lite_awready,
axi_wvalid => timer_bus_2_lite_wvalid,
axi_wready => timer_bus_2_lite_wready,
axi_wdata => timer_bus_2_lite_wdata,
axi_wstrb => timer_bus_2_lite_wstrb,
axi_bvalid => timer_bus_2_lite_bvalid,
axi_bready => timer_bus_2_lite_bready,
axi_bresp => timer_bus_2_lite_bresp,
axi_araddr => timer_bus_2_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => timer_bus_2_lite_arprot,
axi_arvalid => timer_bus_2_lite_arvalid,
axi_arready => timer_bus_2_lite_arready,
axi_rdata => timer_bus_2_lite_rdata,
axi_rvalid => timer_bus_2_lite_rvalid,
axi_rready => timer_bus_2_lite_rready,
axi_rresp => timer_bus_2_lite_rresp,
done => dev_2_ints(1));
-----------------------------
-- Main Interconnect Cores --
-----------------------------
int_main_inst : plasoc_int
generic map (
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => int_axi_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => int_axi_lite_awprot,
axi_awvalid => int_axi_lite_awvalid,
axi_awready => int_axi_lite_awready,
axi_wvalid => int_axi_lite_wvalid,
axi_wready => int_axi_lite_wready,
axi_wdata => int_axi_lite_wdata,
axi_wstrb => int_axi_lite_wstrb,
axi_bvalid => int_axi_lite_bvalid,
axi_bready => int_axi_lite_bready,
axi_bresp => int_axi_lite_bresp,
axi_araddr => int_axi_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => int_axi_lite_arprot,
axi_arvalid => int_axi_lite_arvalid,
axi_arready => int_axi_lite_arready,
axi_rdata => int_axi_lite_rdata,
axi_rvalid => int_axi_lite_rvalid,
axi_rready => int_axi_lite_rready,
axi_rresp => int_axi_lite_rresp,
cpu_int => dev_0_ints(default_interrupt_total-1),
dev_ints => dev_ints);
timer_main_inst : plasoc_timer
generic map (
timer_width => axi_data_width,
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => timer_axi_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => timer_axi_lite_awprot,
axi_awvalid => timer_axi_lite_awvalid,
axi_awready => timer_axi_lite_awready,
axi_wvalid => timer_axi_lite_wvalid,
axi_wready => timer_axi_lite_wready,
axi_wdata => timer_axi_lite_wdata,
axi_wstrb => timer_axi_lite_wstrb,
axi_bvalid => timer_axi_lite_bvalid,
axi_bready => timer_axi_lite_bready,
axi_bresp => timer_axi_lite_bresp,
axi_araddr => timer_axi_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => timer_axi_lite_arprot,
axi_arvalid => timer_axi_lite_arvalid,
axi_arready => timer_axi_lite_arready,
axi_rdata => timer_axi_lite_rdata,
axi_rvalid => timer_axi_lite_rvalid,
axi_rready => timer_axi_lite_rready,
axi_rresp => timer_axi_lite_rresp,
done => dev_ints(0));
gpio_main_inst : plasoc_gpio
generic map (
data_in_width => data_in_width,
data_out_width => data_out_width,
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
data_in => gpio_input,
data_out => gpio_output,
axi_awaddr => gpio_axi_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => gpio_axi_lite_awprot,
axi_awvalid => gpio_axi_lite_awvalid,
axi_awready => gpio_axi_lite_awready,
axi_wvalid => gpio_axi_lite_wvalid,
axi_wready => gpio_axi_lite_wready,
axi_wdata => gpio_axi_lite_wdata,
axi_wstrb => gpio_axi_lite_wstrb,
axi_bvalid => gpio_axi_lite_bvalid,
axi_bready => gpio_axi_lite_bready,
axi_bresp => gpio_axi_lite_bresp,
axi_araddr => gpio_axi_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => gpio_axi_lite_arprot,
axi_arvalid => gpio_axi_lite_arvalid,
axi_arready => gpio_axi_lite_arready,
axi_rdata => gpio_axi_lite_rdata,
axi_rvalid => gpio_axi_lite_rvalid,
axi_rready => gpio_axi_lite_rready,
axi_rresp => gpio_axi_lite_rresp,
int => dev_ints(1));
uart_main_inst : plasoc_uart
generic map (
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width,
baud => uart_baud,
clock_frequency => uart_clock_frequency)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => uart_axi_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => uart_axi_lite_awprot,
axi_awvalid => uart_axi_lite_awvalid,
axi_awready => uart_axi_lite_awready,
axi_wvalid => uart_axi_lite_wvalid,
axi_wready => uart_axi_lite_wready,
axi_wdata => uart_axi_lite_wdata,
axi_wstrb => uart_axi_lite_wstrb,
axi_bvalid => uart_axi_lite_bvalid,
axi_bready => uart_axi_lite_bready,
axi_bresp => uart_axi_lite_bresp,
axi_araddr => uart_axi_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => uart_axi_lite_arprot,
axi_arvalid => uart_axi_lite_arvalid,
axi_arready => uart_axi_lite_arready,
axi_rdata => uart_axi_lite_rdata,
axi_rvalid => uart_axi_lite_rvalid,
axi_rready => uart_axi_lite_rready,
axi_rresp => uart_axi_lite_rresp,
tx => uart_tx,
rx => uart_rx,
status_in_avail => dev_ints(2));
lock_main_inst : koc_lock
generic map (
axi_address_width => axi_address_periph_width,
axi_data_width => axi_data_width,
control_default => lock_control_default)
port map (
aclk => aclk,
aresetn => peripheral_aresetn(0),
axi_awaddr => lock_axi_lite_awaddr(axi_address_periph_width-1 downto 0),
axi_awprot => lock_axi_lite_awprot,
axi_awvalid => lock_axi_lite_awvalid,
axi_awready => lock_axi_lite_awready,
axi_wvalid => lock_axi_lite_wvalid,
axi_wready => lock_axi_lite_wready,
axi_wdata => lock_axi_lite_wdata,
axi_wstrb => lock_axi_lite_wstrb,
axi_bvalid => lock_axi_lite_bvalid,
axi_bready => lock_axi_lite_bready,
axi_bresp => lock_axi_lite_bresp,
axi_araddr => lock_axi_lite_araddr(axi_address_periph_width-1 downto 0),
axi_arprot => lock_axi_lite_arprot,
axi_arvalid => lock_axi_lite_arvalid,
axi_arready => lock_axi_lite_arready,
axi_rdata => lock_axi_lite_rdata,
axi_rvalid => lock_axi_lite_rvalid,
axi_rready => lock_axi_lite_rready,
axi_rresp => lock_axi_lite_rresp);
end Behavioral;
|
mit
|
3ebd2034ad699a5e755f67388e3557d0
| 0.566453 | 3.29752 | false | false | false | false |
rinatzakirov/vhdl
|
memory.vhdl
| 1 | 7,024 |
--------------------------------------------------------------------
-- _ __ __ __ ____ __ = --
-- | | / // / / // __ \ / / = --
-- | | / // /_/ // / / // / = .__ |/ _/_ .__ .__ __ --
-- | |/ // __ // /_/ // /___ = /___) | / / ) / ) (_ ` --
-- |___//_/ /_//_____//_____/ = (___ /| (_ / (___(_ (__) --
-- ===== / --
-- === --
----------------------------- = ----------------------------------
--# memory.vhdl - Generic memories
--# $Id$
--# Freely available from VHDL-extras (http://code.google.com/p/vhdl-extras)
--#
--# Copyright � 2014 Kevin Thibedeau
--# (kevin 'period' thibedeau 'at' gmail 'punto' com)
--#
--# Permission is hereby granted, free of charge, to any person obtaining a
--# copy of this software and associated documentation files (the "Software"),
--# to deal in the Software without restriction, including without limitation
--# the rights to use, copy, modify, merge, publish, distribute, sublicense,
--# and/or sell copies of the Software, and to permit persons to whom the
--# Software is furnished to do so, subject to the following conditions:
--#
--# The above copyright notice and this permission notice shall be included in
--# all copies or substantial portions of the Software.
--#
--# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
--# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
--# DEALINGS IN THE SOFTWARE.
--#
--# DEPENDENCIES: none
--#
--# DESCRIPTION:
--# This package provides general purpose components for inferred RAM and ROM.
--# These memories share a SYNC_READ generic which will optionally generate
--# synchronous or asynchronous read ports for each instance. On Xilinx devices
--# asynchronous read forces the synthesis of distributed RAM using LUTs rather
--# than BRAMs. When SYNC_READ is false the Read enable input is unused.
--#
--# The ROM component gets its contents using synthesizable file IO to read a
--# list of binary or hex values.
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package memory is
component dual_port_ram is
generic (
MEM_SIZE : positive;
SYNC_READ : boolean := true
);
port (
Wr_clock : in std_ulogic;
We : in std_ulogic; -- Write enable
Wr_addr : in natural range 0 to MEM_SIZE-1;
Wr_data : in std_ulogic_vector;
Rd_clock : in std_ulogic;
Re : in std_ulogic; -- Read enable
Rd_addr : in natural range 0 to MEM_SIZE-1;
Rd_data : out std_ulogic_vector
);
end component;
type rom_format is (BINARY_TEXT, HEX_TEXT);
component rom is
generic (
ROM_FILE : string;
FORMAT : rom_format;
MEM_SIZE : positive;
SYNC_READ : boolean := true
);
port (
Clock : in std_ulogic;
Re : in std_ulogic; -- Read enable
Addr : in natural range 0 to MEM_SIZE-1;
Data : out std_ulogic_vector
);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
entity dual_port_ram is
generic (
MEM_SIZE : positive;
SYNC_READ : boolean := true
);
port (
Wr_clock : in std_ulogic;
We : in std_ulogic; -- Write enable
Wr_addr : in natural range 0 to MEM_SIZE-1;
Wr_data : in std_ulogic_vector;
Rd_clock : in std_ulogic;
Re : in std_ulogic; -- Read enable
Rd_addr : in natural range 0 to MEM_SIZE-1;
Rd_data : out std_ulogic_vector
);
end entity;
architecture rtl of dual_port_ram is
type ram_type is array (0 to MEM_SIZE-1) of std_ulogic_vector(Wr_data'length-1 downto 0);
signal ram : ram_type;
signal sync_rdata : std_ulogic_vector(Rd_data'range);
begin
assert Wr_data'length = Rd_data'length report "Data bus size mismatch" severity failure;
wr: process(Wr_clock)
begin
if rising_edge(Wr_clock) then
if We = '1' then
ram(Wr_addr) <= Wr_data;
end if;
end if;
end process;
sread: if SYNC_READ = true generate
rd: process(Rd_clock)
begin
if rising_edge(Rd_clock) then
if Re = '1' then
sync_rdata <= ram(Rd_addr);
end if;
end if;
end process;
end generate;
Rd_data <= ram(Rd_addr) when SYNC_READ = false else sync_rdata;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_bit.all;
use ieee.std_logic_textio.all;
use std.textio.all;
library work;
use work.memory.all;
entity rom is
generic (
ROM_FILE : string;
FORMAT : rom_format;
MEM_SIZE : positive;
SYNC_READ : boolean := true
);
port (
Clock : in std_ulogic;
Re : in std_ulogic; -- Read enable
Addr : in natural range 0 to MEM_SIZE-1;
Data : out std_ulogic_vector
);
end entity;
architecture rtl of rom is
type rom_mem is array (0 to MEM_SIZE-1) of bit_vector(Data'length-1 downto 0);
impure function read_rom_file(file_name : string; format : in rom_format) return rom_mem is
-- Read a ROM file in hex or binary format
file fh : text open read_mode is file_name;
variable ln : line;
variable addr : natural := 0;
variable word : std_logic_vector(Data'length-1 downto 0);
variable rom : rom_mem;
procedure read_hex(ln : inout line; hex : out std_logic_vector) is
-- The standard hread() procedure doesn't work well when the target bit vector
-- is not a multiple of four. This wrapper provides better behavior.
variable hex4 : std_logic_vector(((hex'length + 3) / 4) * 4 - 1 downto 0);
begin
hread(ln, hex4);
-- Trim upper bits if the target is shorter than the nibble adjusted word
hex := hex4(hex'length-1 downto 0);
end procedure;
begin
while addr < MEM_SIZE loop
if endfile(fh) then
exit;
end if;
readline(fh, ln);
if format = HEX_TEXT then
read_hex(ln, word); -- Convert hex string to bits
else -- Binary text
read(ln, word);
end if;
rom(addr) := to_bitvector(word);
addr := addr + 1;
end loop;
return rom;
end function;
signal rom_data : rom_mem := read_rom_file(ROM_FILE, FORMAT);
signal sync_rdata : std_ulogic_vector(Data'range);
begin
rd: process(Clock)
begin
if rising_edge(Clock) then
if Re = '1' then
sync_rdata <= to_stdulogicvector(rom_data(Addr));
end if;
end if;
end process;
Data <= to_stdulogicvector(rom_data(Addr)) when SYNC_READ = false else sync_rdata;
end architecture;
|
lgpl-2.1
|
75d24801764ef1838dc80acaab04fead
| 0.590003 | 3.761114 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/FPGA SigGen/Source/SignalGenerator.vhd
| 1 | 8,222 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Creates periodic signals (e.g. sine, square, and sawtooth) using a phase
-- accumulator. The current phase is also available.
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FunctionGenerator_Declarations.all;
entity SignalGenerator is
generic
(
-- The width of the phase values.
phase_width: natural := 32;
-- The width of the phase values of the waveform lookup table (must not
-- exceed phase_width).
lookup_table_phase_width: natural := 12;
-- The width of the level values.
level_width: natural := 16;
-- The width of the sample values.
sample_width: natural := 16
);
port
(
-- The system clock.
clk: in std_logic;
-- The configuration (e.g. waveform).
config: in generator_config;
-- The increment to be added to the phase accumulator in each clock cycle.
phase_increment: in unsigned (phase_width-1 downto 0);
-- The phase value to be added to the current phase value before determining
-- the sample value. Corresponds to a range of 0..2*Pi.
phase_shift: in unsigned(phase_width-1 downto 0);
-- The level value used to attenuate the sample signal.
level: in signed (level_width-1 downto 0);
-- A signal used to reset the generator´s phase.
reset_phase: in std_logic;
-- The current internal phase value. This is exactly synchronized to sample.
-- Its MSB is 0 for the first half of the period and 1 for the second half.
phase: out unsigned (phase_width-1 downto 0);
-- The sample value according to the current phase.
sample: out signed (sample_width-1 downto 0)
);
end entity;
architecture stdarch of SignalGenerator is
signal phase_int, phase_int_reg: unsigned(phase_width-1 downto 0) := (others => '0');
signal phase_int_shifted: unsigned(phase_width-1 downto 0) := (others => '0');
signal limited_level: signed (level_width-1 downto 0) := (others => '0');
signal sample_int, sample_int_reg: signed (sample_width-1 downto 0) := (others => '0');
signal sample_level_product: signed (2*sample_width-1 downto 0) := (others => '0');
-- Declarations necessary to delay phase to get in sync with sample.
constant phase_sync_delay: integer := 3; -- delay in clk cycles
type phase_vector is array (natural range <>) of unsigned(phase_width-1 downto 0);
signal phase_int_sync: phase_vector(phase_sync_delay-1 downto 0) := (others => (others => '0'));
begin
--------------------------------------------------------------------------------
-- Connections to and from internal signals.
--------------------------------------------------------------------------------
-- Add one clock cycle latency to meet timing requirements when adding phase shift.
add_phase_shift: process is
begin
wait until rising_edge(clk);
phase_int_reg <= phase_int;
end process;
-- Shift the current phase value before determining the sample value.
phase_int_shifted <= phase_int_reg + phase_shift;
-- The MSB of the multiplier output is only needed if both inputs have the
-- smallest possible values: -(2**(n-1)). If at least one of the inputs is
-- limited to -(2**(n-1)-1), the MSB is always identical to the next lower-order
-- bit. To use the entire multiplier output range (and thus the entire sample
-- value range), we limit the level´s value here.
process (level) is
begin
limited_level <= level;
if (level(level_width-1) = '1' and
level(level_width-2 downto 0) = (level_width-2 downto 0 => '0'))
then
limited_level(0) <= '1';
end if;
end process;
-- Attenuate the sample value according to the level.
attenuate_sample: process is
begin
-- Xilinx XST will infer a multiplier here. As an alternative, a multiplier can
-- be instantiated explicitly. Either a multiplier supplied by the FPGA vendor
-- or an own implementation can be used. Portable implementations can be found
-- e.g. in that book: Pong P. Chu, "RTL Hardware Design Using VHDL".
wait until rising_edge(clk);
sample_level_product <= limited_level * sample_int_reg;
end process;
-- Delay returned signals to get them in sync with the sample signal.
delay_signals: process is
begin
wait until rising_edge(clk);
phase_int_sync(phase_int_sync'high downto 1) <=
phase_int_sync(phase_int_sync'high-1 downto 0);
phase_int_sync(0) <= phase_int_reg;
end process;
-- Add one clock cycle latency to satisfy timing constraints between function
-- generator and level multiplier.
decouple_sample: process is
begin
wait until rising_edge(clk);
sample_int_reg <= sample_int;
end process;
--------------------------------------------------------------------------------
-- Component instantiation.
--------------------------------------------------------------------------------
-- The phase generator controlled by a phase accumulator. Generates cyclic
-- phase values used for DDS signal generation.
phase_generator: entity work.PhaseGenerator
generic map
(
phase_width => phase_width
)
port map
(
clk => clk,
phase_increment => phase_increment,
reset_phase => reset_phase,
phase => phase_int
);
-- The function generator producing miscellaneous waveforms using cyclic phase
-- values.
function_generator: entity work.FunctionGenerator
generic map
(
phase_width => phase_width,
lookup_table_phase_width => lookup_table_phase_width,
sample_width => sample_width
)
port map
(
clk => clk,
config => config,
phase => phase_int_shifted,
sample => sample_int
);
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
-- Provides the output signals synchronously, i.e. registered. This is done to
-- satisfy the timing requirements. Otherwise all delays including those of the
-- multiplier are too long for one clock cycle.
provide_output: process is
begin
wait until rising_edge(clk);
-- Provide the MSB´s of the product created from the level and sample values.
-- We have ensured that only one input value of the multiplier can be
-- -(2**(n-1)). Thus we can ignore the result´s MSB and use the full output
-- range.
sample <= sample_level_product(2*sample_width-2 downto sample_width-1);
-- Return the phase value that´s synchronized to the sample value.
phase <= phase_int_sync(phase_int_sync'high);
end process;
end architecture;
|
gpl-3.0
|
790c26833e0d1db0ef3c07bcb4600ce6
| 0.571394 | 4.700972 | false | false | false | false |
arthurbenemann/fpga-bits
|
fm_transmitter/ipcore_dir/phase_adder.vhd
| 1 | 4,378 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file phase_adder.vhd when simulating
-- the core, phase_adder. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY phase_adder IS
PORT (
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
clk : IN STD_LOGIC;
s : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END phase_adder;
ARCHITECTURE phase_adder_a OF phase_adder IS
-- synthesis translate_off
COMPONENT wrapped_phase_adder
PORT (
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
clk : IN STD_LOGIC;
s : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_phase_adder USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 32,
c_add_mode => 0,
c_ainit_val => "0",
c_b_constant => 0,
c_b_type => 0,
c_b_value => "00000000000000000000000000000000",
c_b_width => 32,
c_borrow_low => 1,
c_bypass_low => 0,
c_ce_overrides_bypass => 1,
c_ce_overrides_sclr => 0,
c_has_bypass => 0,
c_has_c_in => 0,
c_has_c_out => 0,
c_has_ce => 0,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_implementation => 0,
c_latency => 1,
c_out_width => 32,
c_sclr_overrides_sset => 1,
c_sinit_val => "0",
c_verbosity => 0,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_phase_adder
PORT MAP (
a => a,
b => b,
clk => clk,
s => s
);
-- synthesis translate_on
END phase_adder_a;
|
gpl-3.0
|
86871ea7f5596d9be88febfc2bbda8cd
| 0.536775 | 4.527404 | false | false | false | false |
arthurTemporim/SD_SS
|
rel/final/projetoVivado/projetoVivado.srcs/sources_1/new/projeto2.vhd
| 2 | 1,779 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity projeto2 is
port (
a : in std_logic_vector (3 downto 0) := "0001"; -- Entrada A.
b : in std_logic_vector (3 downto 0) := "0000"; -- Entrada B.
clk : in std_logic := '0'; -- Clock.
display1 : out std_logic_vector (6 downto 0);
display2 : out std_logic_vector (6 downto 0)
);
end projeto2;
architecture Behavioral of projeto2 is
signal saida_mux : std_logic_vector (3 downto 0);
signal bcd : std_logic_vector (6 downto 0); -- BCD.
begin
-- Mux 8->4.
process (a,b, clk)
begin
if (clk = '0') then
saida_mux <= a;
else
saida_mux <= b;
end if;
end process;
-- BCD.
process (a,b,clk, saida_mux, bcd)
begin
if (saida_mux = "0000") then -- 0
bcd <= "1111110";
elsif (saida_mux = "0001") then -- 1
bcd <= "0110000";
elsif (saida_mux = "0010") then -- 2
bcd <= "1101101";
elsif (saida_mux = "0011") then -- 3
bcd <= "1111001";
elsif (saida_mux = "0100") then -- 4
bcd <= "0110010";
elsif (saida_mux = "0101") then -- 5
bcd <= "1011010";
elsif (saida_mux = "0110") then -- 6
bcd <= "1011111";
elsif (saida_mux = "0111") then -- 7
bcd <= "1110000";
elsif (saida_mux = "1000") then -- 8
bcd <= "1111111";
elsif (saida_mux = "1001") then -- 9
bcd <= "1111011";
elsif (saida_mux = "1010") then -- A
bcd <= "1110111";
elsif (saida_mux = "1011") then -- B
bcd <= "0011111";
elsif (saida_mux = "1100") then -- C
bcd <= "1001110";
elsif (saida_mux = "1101") then -- D
bcd <= "0111101";
elsif (saida_mux = "1110") then -- E
bcd <= "1001111";
else
bcd <= "1000111"; -- Caso defaul -> 'F'
end if;
end process;
-- Mux 1->2.
process (bcd, clk)
begin
if (clk = '0') then
display1 <= bcd;
else
display2 <= bcd;
end if;
end process;
end Behavioral;
|
mit
|
eb4b92bf456c526033bf3b2a1555b52d
| 0.58235 | 2.667166 | false | false | false | false |
arthurTemporim/SD_SS
|
rel/3/projetos/aula3/complemento4.vhd
| 1 | 510 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity complemento4 is
Port ( entrada : in STD_LOGIC_VECTOR (3 downto 0) := "0000";
sel : in STD_LOGIC := '1';
saida : out STD_LOGIC_VECTOR (3 downto 0)
);
end complemento4;
architecture Behavioral of complemento4 is
signal aux : STD_LOGIC_VECTOR (3 downto 0);
begin
process (entrada,sel,aux)
begin
if (sel = '1') then
aux <= entrada xor "1111";
else
aux <= entrada;
end if;
end process;
saida <= aux;
end Behavioral;
|
mit
|
f8d9822aee613238c57fc659ddb42f93
| 0.641176 | 3.109756 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/DCM_clock/ipcore_dir/my_dcm/example_design/my_dcm_exdes.vhd
| 1 | 5,388 |
-- file: my_dcm_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity my_dcm_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end my_dcm_exdes;
architecture xilinx of my_dcm_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counter
signal clk : std_logic;
signal clk_int : std_logic;
signal clk_n : std_logic;
signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0');
signal rst_sync : std_logic;
signal rst_sync_int : std_logic;
signal rst_sync_int1 : std_logic;
signal rst_sync_int2 : std_logic;
component my_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= COUNTER_RESET;
process (clk, reset_int) begin
if (reset_int = '1') then
rst_sync <= '1';
rst_sync_int <= '1';
rst_sync_int1 <= '1';
rst_sync_int2 <= '1';
elsif (clk 'event and clk='1') then
rst_sync <= '0';
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end if;
end process;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : my_dcm
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int);
clk_n <= not clk;
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(1),
C0 => clk,
C1 => clk_n,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
-- Connect the output clocks to the design
-------------------------------------------
clk <= clk_int;
-- Output clock sampling
-------------------------------------
process (clk, rst_sync_int2) begin
if (rst_sync_int2 = '1') then
counter <= (others => '0') after TCQ;
elsif (rising_edge(clk)) then
counter <= counter + 1 after TCQ;
end if;
end process;
-- alias the high bit to the output
COUNT <= counter(C_W-1);
end xilinx;
|
gpl-3.0
|
cc14d15a78d5ed3a81eefac0fab91357
| 0.615999 | 4.048084 | false | false | false | false |
Anding/DDR2_memory_interface
|
rtl/system/fpga_top.vhd
| 1 | 19,343 |
-- DDR2 memory interface
-- Andrew Read, March 2016
-- This project is based on a working DDR2 interface very kindly donated by a friend
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
entity fpga_top is port(
clk : in std_logic;
nrst : in std_logic;
led : out std_logic_vector(1 downto 0);
sevenseg : out STD_LOGIC_VECTOR (6 downto 0);
anode : out STD_LOGIC_VECTOR (7 downto 0);
SDRAM_A : out std_logic_vector(13 downto 0);
SDRAM_BA : out std_logic_vector(2 downto 0);
SDRAM_CKE : out std_logic;
SDRAM_CK : out std_logic;
SDRAM_nCK : out std_logic;
SDRAM_DQ : inout std_logic_vector(15 downto 0);
SDRAM_DQS : inout std_logic_vector(1 downto 0);
--SDRAM_nDQS : inout std_logic_vector(1 downto 0);
SDRAM_UDQM : out std_logic;
SDRAM_LDQM : out std_logic;
SDRAM_nCAS : out std_logic;
SDRAM_nCS : out std_logic;
SDRAM_nRAS : out std_logic;
SDRAM_nWE : out std_logic;
SDRAM_ODT : out std_logic);
end fpga_top;
architecture RTL of fpga_top is
component ByteHEXdisplay is
Port (
clk : in STD_LOGIC;
ssData : in STD_LOGIC_VECTOR (31 downto 0);
sevenseg : out STD_LOGIC_VECTOR (6 downto 0);
anode : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component SDRAM_CTRL is
port (
CLK : in std_logic;
CLK_130 : in std_logic;
reset : in std_logic;
wrrd_ba_add : in std_logic_vector(2 downto 0);
wrrd_ras_add : in std_logic_vector(12 downto 0);
wrrd_cas_add : in std_logic_vector(8 downto 0);
wr_we : in std_logic_vector(3 downto 0);
wr_add : in std_logic_vector(25 downto 0);
wr_dat : in std_logic_vector(31 downto 0);
wr_ack : out std_logic;
rd_re : in std_logic;
rd_add : in std_logic_vector(25 downto 0);
rd_dat : out std_logic_vector(31 downto 0);
rd_ack : out std_logic;
rd_valid : out std_logic;
SDRAM_A : out std_logic_vector(13 downto 0);
SDRAM_BA : out std_logic_vector(2 downto 0);
SDRAM_CKE : out std_logic;
SDRAM_CK : out std_logic;
SDRAM_nCK : out std_logic;
SDRAM_DQ : inout std_logic_vector(15 downto 0);
SDRAM_DQS : inout std_logic_vector(1 downto 0);
--SDRAM_nDQS : inout std_logic_vector(1 downto 0);
SDRAM_DM : out std_logic_vector(1 downto 0);
SDRAM_nCAS : out std_logic;
SDRAM_nCS : out std_logic;
SDRAM_nRAS : out std_logic;
SDRAM_nWE : out std_logic);
end component;
component clk_manager
Port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC
-- resetn : in STD_LOGIC;
-- locked : out STD_LOGIC
);
end component;
type fsm_type is (init,
write_0_0, write_0_1,
write_1_0, write_1_1, write_1_2, write_1_3,
write_2_0, write_2_1, write_2_2, write_2_3, write_2_4, write_2_5,
write_3_0, write_3_1,
write_4_0, write_4_1,
read_0_0, read_0_1, read_0_2,
read_1_0, read_1_1, read_1_2, read_1_3, read_1_4, read_1_5,
read_2_0, read_2_1, read_2_2, read_2_3, read_2_4, read_2_5, read_2_6, read_2_7, read_2_8, read_2_9, read_2_10, read_2_11,
read_3_0, read_3_1, read_3_2,
read_4_0, read_4_1, read_4_2,
refreshWait);
signal wrrd_ba_add : std_logic_vector(2 downto 0);
signal wrrd_ras_add : std_logic_vector(12 downto 0);
signal wrrd_cas_add : std_logic_vector(8 downto 0);
signal wr_we : std_logic_vector(3 downto 0);
signal wr_add : std_logic_vector(25 downto 0);
signal wr_dat : std_logic_vector(31 downto 0);
signal wr_ack : std_logic;
signal rd_re : std_logic;
signal rd_add : std_logic_vector(25 downto 0);
signal rd_dat, rd_dat_reg, rd_dat_reg0 : std_logic_vector(31 downto 0);
signal rd_ack : std_logic;
signal rd_valid : std_logic;
signal bug_found : std_logic;
signal SDRAM_DM : std_logic_vector(1 downto 0);
signal clk_int : std_logic;
signal clk_int_130 : std_logic;
signal nrst_reg : std_logic;
signal state : fsm_type;
signal counter : integer range 0 to 32768;
signal time_cnt1 : integer range 0 to 65535;
signal time_cnt2 : integer range 0 to 4095;
signal led_toggle : std_logic;
signal ssdata : std_logic_vector(31 downto 0);
signal reset : std_logic := '1';
signal reset_counter : integer range 0 to 4095 := 0;
begin
SDRAM_ODT <= '0';
-----------------------------------------------------
-- clk
-----------------------------------------------------
-- reset process
process
begin
wait until rising_edge(clk_int);
if nrst = '0' then
reset_counter <= 0;
reset <= '1';
elsif reset_counter = 2000 then
reset <= '0';
else
reset_counter <= reset_counter + 1;
end if;
end process;
CLOCKMANAGER: clk_manager
port map
(-- Clock in ports
clk_in1 => clk,
clk_out1 => clk_int,
clk_out2 => clk_int_130
--resetn => nrst,
--locked => locked
);
----------------------------------------------
-- nrst_reg
----------------------------------------------
--nrst_reg_proc : process (clk_int, nrst) begin
--if (clk_int = '1' and clk_int'event) then
-- nrst_reg <= '0';
-- if (nrst = '1') then
-- nrst_reg <= '1';
-- end if;
--end if;
--end process;
-----------------------------------------------------
-- For relaxing the timing: rd_dat gets registered
-----------------------------------------------------
rd_dat_reg_gen : process (clk_int, reset)
begin
if (reset='1') then
rd_dat_reg <= conv_std_logic_vector(0, rd_dat_reg'length);
-- rd_dat_reg0 <= conv_std_logic_vector(0, rd_dat_reg0'length);
elsif (clk_int'event and clk_int='1') then
rd_dat_reg <= rd_dat_reg0; -- one cycle delay for some reason
end if;
end process;
-- rd_dat is already registered by PHYIO
rd_dat_reg0 <= rd_dat;
-----------------------------------------------------
-- FSM
-----------------------------------------------------
gen_fsm : process (clk_int, reset)
variable counter_bus : std_logic_vector(15 downto 0);
begin
if (reset='1') then
wrrd_ba_add <= conv_std_logic_vector(0, wrrd_ba_add'length);
wrrd_ras_add <= conv_std_logic_vector(0, wrrd_ras_add'length);
wrrd_cas_add <= conv_std_logic_vector(0, wrrd_cas_add'length);
led <= "00";
state <= init;
wr_add <= conv_std_logic_vector(0, wr_add'length);
wr_dat <= conv_std_logic_vector(0, wr_dat'length);
wr_we <= "0000";
rd_re <= '0';
rd_add <= conv_std_logic_vector(0, rd_add'length);
counter <= 0;
bug_found <= '0';
time_cnt1 <= 0;
time_cnt2 <= 0;
led_toggle <= '0';
ssdata <= x"01234567";
elsif (clk_int'event and clk_int='1') then
case (state) is
-----------------------------------------------------
-- mode
-----------------------------------------------------
when init => state <= write_0_0;
-----------------------------------------------------
-- write bank: 0 page: 0 add: 0 data: 5555AAAA
-----------------------------------------------------
when write_0_0 =>
wr_we <= "1111";
wr_dat <= x"7755AACC";
wrrd_cas_add <= conv_std_logic_vector(0, wrrd_cas_add'length);
state <= write_0_1;
when write_0_1 =>
if (wr_ack = '1') then
wr_we <= "0000";
state <= read_0_0;
rd_re <= '1';
end if;
-----------------------------------------------------
-- read bank: 0 page: 0 add: 0 data: 0000FFF0
-----------------------------------------------------
when read_0_0 =>
if (rd_ack = '1') then
rd_re <= '0';
state <= read_0_1;
end if;
when read_0_1 =>
if (rd_valid = '1') then
state <= read_0_2;
end if;
when read_0_2 =>
--state <= write_4_0;
--counter <= 32768;
--------------------
state <= write_1_0;
ssdata <= rd_dat_reg;
if NOT (rd_dat_reg(31 downto 0) = x"7755AACC") then
--if NOT (rd_dat_reg(31 downto 0) = x"AAAA5555") then
bug_found <= '1';
end if;
-----------------------------------------------------
-- write bank: 0 page: 0 add: 0 data: 0000FFFF
-----------------------------------------------------
when write_1_0 =>
wr_we <= "1111";
wrrd_cas_add <= conv_std_logic_vector(0, wrrd_cas_add'length);
wr_dat <= x"0000FFFF";
state <= write_1_1;
when write_1_1 =>
if (wr_ack = '1') then
wr_we <= "0000";
state <= write_1_2;
end if;
-----------------------------------------------------
-- write bank: 0 page: 0 add: 1 data: 0001FFFE
-----------------------------------------------------
when write_1_2 =>
wr_we <= "1111";
wrrd_cas_add <= conv_std_logic_vector(1, wrrd_cas_add'length);
wr_dat <= x"0001FFFE";
state <= write_1_3;
when write_1_3 =>
if (wr_ack = '1') then
wr_we <= "0000";
state <= read_1_0;
rd_re <= '1';
wrrd_cas_add <= conv_std_logic_vector(0, wrrd_cas_add'length);
end if;
-----------------------------------------------------
-- read bank: 0 page: 0 add: 0 data: 0000FFFF
-----------------------------------------------------
when read_1_0 =>
if (rd_ack = '1') then
rd_re <= '0';
state <= read_1_1;
end if;
when read_1_1 =>
if (rd_valid = '1') then
state <= read_1_2;
end if;
when read_1_2 =>
state <= read_1_3;
rd_re <= '1';
wrrd_cas_add <= conv_std_logic_vector(1, wrrd_cas_add'length);
if NOT (rd_dat_reg(31 downto 0) = x"0000FFFF") then
bug_found <= '1';
end if;
-----------------------------------------------------
-- read bank: 0 page: 0 add: 1 data: 0001FFFE
-----------------------------------------------------
when read_1_3 =>
if (rd_ack = '1') then
rd_re <= '0';
state <= read_1_4;
end if;
when read_1_4 =>
if (rd_valid = '1') then
state <= read_1_5;
end if;
when read_1_5 =>
state <= write_2_0;
if NOT (rd_dat_reg(31 downto 0) = x"0001FFFE") then
bug_found <= '1';
end if;
-----------------------------------------------------
-- write bank: 0 page: 1 add: 1 data: 0011FFEE
-----------------------------------------------------
when write_2_0 =>
wr_we <= "1111";
wrrd_cas_add <= conv_std_logic_vector(1, wrrd_cas_add'length);
wrrd_ras_add <= "0" & x"001";
wr_dat <= x"0011FFEE";
state <= write_2_1;
when write_2_1 =>
if (wr_ack = '1') then
wr_we <= "0000";
state <= write_2_2;
end if;
-----------------------------------------------------
-- write bank: 0 page: 2 add: 1 data: 0021FFDE
-----------------------------------------------------
when write_2_2 =>
wr_we <= "1111";
wrrd_ras_add <= "0" & x"002";
wr_dat <= x"0021FFDE";
state <= write_2_3;
when write_2_3 =>
if (wr_ack = '1') then
wr_we <= "0000";
state <= write_2_4;
end if;
-----------------------------------------------------
-- write bank: 1 page: 2 add: 1 data: 0121FEDE
-----------------------------------------------------
when write_2_4 =>
wr_we <= "1111";
wrrd_ba_add <= "001";
wr_dat <= x"0121FEDE";
state <= write_2_5;
when write_2_5 =>
if (wr_ack = '1') then
wr_we <= "0000";
state <= read_2_0;
rd_re <= '1';
wrrd_ba_add <= "000";
wrrd_ras_add <= "0" & x"000";
end if;
-----------------------------------------------------
-- read bank: 0 page: 0 add: 1 data: 0001FFFE
-----------------------------------------------------
when read_2_0 =>
if (rd_ack = '1') then
rd_re <= '0';
state <= read_2_1;
end if;
when read_2_1 =>
if (rd_valid = '1') then
state <= read_2_2;
end if;
when read_2_2 =>
state <= read_2_3;
rd_re <= '1';
wrrd_ras_add <= "0" & x"001";
if NOT (rd_dat_reg(31 downto 0) = x"0001FFFE") then
bug_found <= '1';
end if;
-----------------------------------------------------
-- read bank: 0 page: 1 add: 1 data: 0011FFEE
-----------------------------------------------------
when read_2_3 =>
if (rd_ack = '1') then
rd_re <= '0';
state <= read_2_4;
end if;
when read_2_4 =>
if (rd_valid = '1') then
state <= read_2_5;
end if;
when read_2_5 =>
state <= read_2_6;
rd_re <= '1';
wrrd_ras_add <= "0" & x"002";
if NOT (rd_dat_reg(31 downto 0) = x"0011FFEE") then
bug_found <= '1';
end if;
-----------------------------------------------------
-- read bank: 0 page: 2 add: 1 data: 0021FFDE
-----------------------------------------------------
when read_2_6 =>
if (rd_ack = '1') then
rd_re <= '0';
state <= read_2_7;
end if;
when read_2_7 =>
if (rd_valid = '1') then
state <= read_2_8;
end if;
when read_2_8 =>
state <= read_2_9;
rd_re <= '1';
wrrd_ba_add <= "001";
wrrd_ras_add <= "0" & x"002";
if NOT (rd_dat_reg(31 downto 0) = x"0021FFDE") then
bug_found <= '1';
end if;
-----------------------------------------------------
-- read bank: 1 page: 2 add: 1 data: 0121FEDE
-----------------------------------------------------
when read_2_9 =>
if (rd_ack = '1') then
rd_re <= '0';
state <= read_2_10;
end if;
when read_2_10 =>
if (rd_valid = '1') then
state <= read_2_11;
end if;
when read_2_11 =>
state <= write_3_0;
if NOT (rd_dat_reg(31 downto 0) = x"0121FEDE") then
bug_found <= '1';
end if;
counter <= 256;
-----------------------------------------------------
-- write bank: 3 page: 3 add: 0..255 data: 0330<cas>
-----------------------------------------------------
when write_3_0 =>
wr_we <= "1111";
wrrd_ba_add <= "011";
wrrd_ras_add <= "0" & x"003";
wrrd_cas_add <= conv_std_logic_vector(counter, wrrd_cas_add'length);
wr_dat <= x"0330" & conv_std_logic_vector(counter, 16);
state <= write_3_1;
when write_3_1 =>
if (wr_ack = '1') then
if (counter = 0) then
wr_we <= "0000";
state <= read_3_0;
rd_re <= '1';
counter <= 256;
wrrd_cas_add <= conv_std_logic_vector(256, wrrd_cas_add'length);
else
counter <= counter / 2;
wrrd_cas_add <= conv_std_logic_vector(counter / 2, wrrd_cas_add'length);
wr_dat <= x"0330" & conv_std_logic_vector(counter / 2, 16);
end if;
end if;
-----------------------------------------------------
-- read bank: 0 page: 0 add: 0 data: 0000FFFF
-----------------------------------------------------
when read_3_0 =>
if (rd_ack = '1') then
rd_re <= '0';
state <= read_3_1;
end if;
when read_3_1 =>
if (rd_valid = '1') then
state <= read_3_2;
end if;
when read_3_2 =>
if (counter = 0) then
state <= write_4_0;
counter <= 32768;
else
rd_re <= '1';
state <= read_3_0;
counter <= counter / 2;
wrrd_cas_add <= conv_std_logic_vector(counter / 2, wrrd_cas_add'length);
end if;
if (NOT (rd_dat_reg(31 downto 16) = x"0330")) OR
(NOT (rd_dat_reg(15 downto 9) = "0000000")) OR
(NOT (rd_dat_reg(8 downto 0) = conv_std_logic_vector(counter, wrrd_cas_add'length))) then
bug_found <= '1';
end if;
-----------------------------------------------------
-- write bank: 3 page: 3 add: 0..255 data: 0330<cas>
-----------------------------------------------------
when write_4_0 =>
wr_we <= "1111";
counter_bus := conv_std_logic_vector(counter, counter_bus'length);
wrrd_ba_add <= counter_bus(15 downto 13);
wrrd_ras_add <= counter_bus(12 downto 0);
wrrd_cas_add <= conv_std_logic_vector(4, wrrd_cas_add'length);
wr_dat <= conv_std_logic_vector(counter + time_cnt2, 32);
state <= write_4_1;
when write_4_1 =>
if (wr_ack = '1') then
if (counter = 0) then
wr_we <= "0000";
state <= read_4_0;
rd_re <= '1';
counter <= 32768;
counter_bus := conv_std_logic_vector(32768, counter_bus'length);
wrrd_ba_add <= counter_bus(15 downto 13);
wrrd_ras_add <= counter_bus(12 downto 0);
else
counter <= counter / 2;
counter_bus := conv_std_logic_vector(counter / 2, counter_bus'length);
wrrd_ba_add <= counter_bus(15 downto 13);
wrrd_ras_add <= counter_bus(12 downto 0);
wr_dat <= conv_std_logic_vector((counter / 2) + time_cnt2, 32);
end if;
end if;
-----------------------------------------------------
-- read bank: 0 page: 0 add: 0 data: 0000FFFF
-----------------------------------------------------
when read_4_0 =>
if (rd_ack = '1') then
rd_re <= '0';
state <= read_4_1;
end if;
when read_4_1 =>
if (rd_valid = '1') then
state <= read_4_2;
end if;
when read_4_2 =>
if (counter = 0) then
state <= refreshWait;
counter <= 32768;
else
rd_re <= '1';
state <= read_4_0;
counter <= counter / 2;
counter_bus := conv_std_logic_vector(counter / 2, counter_bus'length);
wrrd_ba_add <= counter_bus(15 downto 13);
wrrd_ras_add <= counter_bus(12 downto 0);
end if;
if (NOT (rd_dat_reg(31 downto 0) = conv_std_logic_vector(counter + time_cnt2, 32))) then
bug_found <= '1';
end if;
-----------------------------------------------------
-- refreshWait
-----------------------------------------------------
when refreshWait =>
led(0) <= not led_toggle;
if (bug_found = '0') then
led(1) <= '1';
if (time_cnt1 = 4095) then
time_cnt1 <= 0;
if (time_cnt2 = 4095) then
state <= read_3_0;
rd_re <= '1';
counter <= 256;
wrrd_ba_add <= "011";
wrrd_ras_add <= "0" & x"003";
wrrd_cas_add <= conv_std_logic_vector(256, wrrd_cas_add'length);
time_cnt2 <= 0;
led_toggle <= not led_toggle;
else
state <= write_4_0;
time_cnt2 <= time_cnt2 + 1;
end if;
else
state <= write_4_0;
time_cnt1 <= time_cnt1 + 1;
end if;
else
led(1) <= '0';
if (time_cnt1 = 65535) then
time_cnt1 <= 0;
if (time_cnt2 = 511) then
time_cnt2 <= 0;
led_toggle <= not led_toggle;
else
time_cnt2 <= time_cnt2 + 1;
end if;
else
time_cnt1 <= time_cnt1 + 1;
end if;
end if;
when others =>
end case;
end if;
end process;
SDRAM_UDQM <= SDRAM_DM(1);
SDRAM_LDQM <= SDRAM_DM(0);
-----------------------------------------------------
-- SDRAM_CTRL
-----------------------------------------------------
SDRAM_CTRLi : SDRAM_CTRL
port map (
CLK => clk_int,
CLK_130 => clk_int_130,
reset => reset,
wrrd_ba_add => wrrd_ba_add,
wrrd_ras_add => wrrd_ras_add,
wrrd_cas_add => wrrd_cas_add,
wr_we => wr_we,
wr_add => wr_add,
wr_dat => wr_dat,
wr_ack => wr_ack,
rd_re => rd_re,
rd_add => rd_add,
rd_dat => rd_dat,
rd_ack => rd_ack,
rd_valid => rd_valid,
SDRAM_A => SDRAM_A,
SDRAM_BA => SDRAM_BA,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CK => SDRAM_CK,
SDRAM_nCK => SDRAM_nCK,
SDRAM_DQ => SDRAM_DQ,
SDRAM_DQS => SDRAM_DQS,
--SDRAM_nDQS => SDRAM_nDQS,
SDRAM_DM => SDRAM_DM,
SDRAM_nCAS => SDRAM_nCAS,
SDRAM_nCS => SDRAM_nCS,
SDRAM_nRAS => SDRAM_nRAS,
SDRAM_nWE => SDRAM_nWE);
hex : ByteHEXdisplay
Port map (
clk => clk_int,
ssData => ssData,
sevenseg => sevenseg,
anode => anode
);
end RTL;
|
gpl-2.0
|
985edc136a5c394a72bd399c989f8d86
| 0.480432 | 2.98181 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
dvb_dma_fifo_ram.vhd
| 1 | 9,766 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: dvb_dma_fifo_ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dvb_dma_fifo_ram IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
rdclock : IN STD_LOGIC ;
rdclocken : IN STD_LOGIC := '1';
wraddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
wrclock : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END dvb_dma_fifo_ram;
ARCHITECTURE SYN OF dvb_dma_fifo_ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (63 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_b : STRING;
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock0 : IN STD_LOGIC ;
clocken1 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock1 : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(63 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
intended_device_family => "Cyclone IV GX",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 128,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
widthad_a => 10,
widthad_b => 7,
width_a => 8,
width_b => 64,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
clock0 => wrclock,
clocken1 => rdclocken,
data_a => data,
wren_a => wren,
address_b => rdaddress,
clock1 => rdclock,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "1"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "1"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "64"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "1"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "NORMAL"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "128"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "7"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "64"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 7 0 INPUT NODEFVAL "rdaddress[6..0]"
-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
-- Retrieval info: USED_PORT: rdclocken 0 0 0 0 INPUT VCC "rdclocken"
-- Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 7 0 rdaddress 0 0 7 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
-- Retrieval info: CONNECT: @clocken1 0 0 0 0 rdclocken 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 64 0 @q_b 0 0 64 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dvb_dma_fifo_ram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dvb_dma_fifo_ram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dvb_dma_fifo_ram.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dvb_dma_fifo_ram.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dvb_dma_fifo_ram_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-3.0
|
933b997e2e31cdf2533825d3eb015b4e
| 0.680422 | 3.418271 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
dvb_ts_sync.vhd
| 1 | 3,390 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dvb_ts_sync is
port (
-- transport stream input port
ts_clk : in std_logic;
ts_strt : in std_logic;
ts_dval : in std_logic;
ts_data : in std_logic_vector(7 downto 0);
-- data output port (system clock domain)
rst : in std_logic;
clk : in std_logic;
--
strt : out std_logic;
data : out std_logic_vector(7 downto 0);
dval : out std_logic
);
end entity;
architecture rtl of dvb_ts_sync is
signal ts_rst_meta : std_logic;
signal ts_rst_n : std_logic;
signal src_latch : std_logic_vector(ts_data'left + 2 downto 0);
signal src_hold_0 : std_logic_vector(ts_data'left + 1 downto 0);
signal src_hold_1 : std_logic_vector(ts_data'left + 1 downto 0);
signal src_hold_2 : std_logic_vector(ts_data'left + 1 downto 0);
signal src_hold_3 : std_logic_vector(ts_data'left + 1 downto 0);
signal src_ptr : std_logic_vector(1 downto 0);
signal src_ptr_meta : std_logic_vector(1 downto 0);
signal src_ptr_sync : std_logic_vector(1 downto 0);
signal dst_ptr : std_logic_vector(1 downto 0);
begin
process (rst, ts_rst_n, ts_clk)
begin
if rising_edge(ts_clk) then
ts_rst_meta <= '1';
ts_rst_n <= ts_rst_meta;
--
src_latch <= ts_dval & ts_strt & ts_data;
if src_latch(src_latch'left) then
src_ptr(0) <= not src_ptr(1);
src_ptr(1) <= src_ptr(0);
if src_ptr = "00" then
src_hold_0 <= src_latch(src_latch'left - 1 downto 0);
end if;
if src_ptr = "01" then
src_hold_1 <= src_latch(src_latch'left - 1 downto 0);
end if;
if src_ptr = "11" then
src_hold_2 <= src_latch(src_latch'left - 1 downto 0);
end if;
if src_ptr = "10" then
src_hold_3 <= src_latch(src_latch'left - 1 downto 0);
end if;
end if;
end if;
if rst then
ts_rst_meta <= '0';
ts_rst_n <= '0';
end if;
if not ts_rst_n then
src_latch <= (others => '0');
src_ptr <= (others => '0');
src_hold_0 <= (others => '0');
src_hold_1 <= (others => '0');
src_hold_2 <= (others => '0');
src_hold_3 <= (others => '0');
end if;
end process;
process (rst, clk)
variable fifo_not_empty : std_logic;
begin
if rising_edge(clk) then
src_ptr_meta <= src_ptr;
src_ptr_sync <= src_ptr_meta;
--
fifo_not_empty := (src_ptr_sync(1) xor dst_ptr(1)) or (src_ptr_sync(0) xor dst_ptr(0));
if fifo_not_empty then
dst_ptr(0) <= not dst_ptr(1);
dst_ptr(1) <= dst_ptr(0);
case dst_ptr is
when "00" =>
strt <= src_hold_0(src_hold_0'left);
data <= src_hold_0(src_hold_0'left - 1 downto 0);
when "01" =>
strt <= src_hold_1(src_hold_1'left);
data <= src_hold_1(src_hold_1'left - 1 downto 0);
when "11" =>
strt <= src_hold_2(src_hold_2'left);
data <= src_hold_2(src_hold_2'left - 1 downto 0);
when others =>
strt <= src_hold_3(src_hold_3'left);
data <= src_hold_3(src_hold_3'left - 1 downto 0);
end case;
end if;
dval <= fifo_not_empty;
end if;
if rst then
src_ptr_meta <= (others => '0');
src_ptr_sync <= (others => '0');
dst_ptr <= (others => '0');
strt <= '0';
data <= (others => '0');
dval <= '0';
end if;
end process;
end;
|
gpl-3.0
|
530a971b1eae953958449f6338cc9009
| 0.59056 | 2.512973 | false | false | false | false |
arthurbenemann/fpga-bits
|
mandelbrot/ipcore_dir/color_palette.vhd
| 1 | 5,435 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file color_palette.vhd when simulating
-- the core, color_palette. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY color_palette IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END color_palette;
ARCHITECTURE color_palette_a OF color_palette IS
-- synthesis translate_off
COMPONENT wrapped_color_palette
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_color_palette USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 4,
c_addrb_width => 4,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "color_palette.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16,
c_read_depth_b => 16,
c_read_width_a => 12,
c_read_width_b => 12,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16,
c_write_depth_b => 16,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 12,
c_write_width_b => 12,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_color_palette
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END color_palette_a;
|
gpl-3.0
|
ed96baa10c8db62d391bcbe37ba5e322
| 0.532475 | 4.014032 | false | false | false | false |
arthurbenemann/fpga-bits
|
fm_transmitter/tb_top.vhd
| 1 | 1,244 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.numeric_std.ALL;
ENTITY tb_top IS
END tb_top;
ARCHITECTURE behavior OF tb_top IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT topModule
PORT(
CLK : IN std_logic;
GPIO0 : OUT std_logic;
AUDIO1_RIGHT : OUT std_logic;
AUDIO1_LEFT : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
--Outputs
signal GPIO0 : std_logic;
signal AUDIO1_RIGHT : std_logic;
signal AUDIO1_LEFT : std_logic;
-- Clock period definitions
constant CLK_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: topModule PORT MAP (
CLK => CLK,
GPIO0 => GPIO0,
AUDIO1_RIGHT => AUDIO1_RIGHT,
AUDIO1_LEFT => AUDIO1_LEFT
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
4c52bd9a9b1b8e26eecaaa75a1b3fa71
| 0.586817 | 3.648094 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/audioDac/ipcore_dir/rom_memory/simulation/rom_memory_synth.vhd
| 1 | 6,840 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rom_memory_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY rom_memory_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE rom_memory_synth_ARCH OF rom_memory_synth IS
COMPONENT rom_memory_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: rom_memory_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
gpl-3.0
|
2a616c8b3fff0b0cae398807f5ffb55f
| 0.580702 | 3.804227 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/audioDac/ipcore_dir/rom_memory/simulation/bmg_stim_gen.vhd
| 1 | 12,581 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (8 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(8 DOWNTO 0):= hex_to_std_logic_vector("0",9);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (57774 downto 0) of std_logic_vector(8 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(8 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"rom_memory.mif",
DEFAULT_DATA,
9,
57775);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>57775 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(15 DOWNTO 0) <= READ_ADDR(15 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 57775 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
gpl-3.0
|
21020cf65c3b6edab4f2dc5acccc15d1
| 0.547731 | 3.684041 | false | false | false | false |
Daverball/reconos
|
demos/reconf_led/hw/hwt_led_on_v1_00_a/hdl/vhdl/hwt_led_on.vhd
| 2 | 3,395 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_01_a;
use reconos_v3_01_a.reconos_pkg.all;
entity hwt_led_on is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic;
USER_Led : out std_logic
);
attribute SIGIS : string;
attribute SIGIS of HWT_Clk : signal is "Clk";
attribute SIGIS of HWT_Rst : signal is "Rst";
end hwt_led_on;
architecture imp of hwt_led_on is
attribute keep_hierarchy : string;
attribute keep_hierarchy of IMP: architecture is "true";
constant MBOX_RECV : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_SEND : std_logic_vector(31 downto 0) := x"00000001";
type STATE_TYPE is (STATE_RECV_CMD,STATE_EXEC,STATE_SEND_ACK);
signal state : STATE_TYPE;
signal data : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
signal counter : std_logic_vector(31 downto 0);
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal clk : std_logic;
signal rst : std_logic;
begin
clk <= HWT_Clk;
rst <= HWT_Rst;
-- ReconOS initilization
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
-- drive memif constant
MEMIF_FIFO_Hwt2Mem_Data <= (others => '0');
MEMIF_FIFO_Hwt2Mem_WE <= '0';
MEMIF_FIFO_Mem2Hwt_RE <= '0';
USER_Led <= '1';
-- os and memory synchronisation state machine
RECONOS_FSM_PROCESS: process (clk,rst) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
done := false;
state <= STATE_RECV_CMD;
elsif rising_edge(clk) then
case state is
when STATE_RECV_CMD =>
osif_mbox_get(i_osif, o_osif, MBOX_RECV, data, done);
if done then
counter <= data(31 downto 0);
state <= STATE_EXEC;
end if;
when STATE_EXEC =>
if or_reduce(counter) = '0' then
state <= STATE_SEND_ACK;
else
counter <= counter - 1;
end if;
when STATE_SEND_ACK =>
osif_set_yield(i_osif, o_osif);
osif_mbox_put(i_osif, o_osif, MBOX_SEND, (others => '0'), ignore, done);
if done then
state <= STATE_RECV_CMD;
end if;
end case;
end if;
end process RECONOS_FSM_PROCESS;
end architecture imp;
|
gpl-2.0
|
f35e6f0ae6ef6e7892d4deacadb25d2b
| 0.654197 | 2.666929 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
dvb_dma.vhd
| 1 | 15,562 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.avblabs_common_pkg.all;
entity dvb_dma is
port (
rst : in std_logic;
clk : in std_logic;
-- control port
address : in std_logic_vector(3 downto 0);
byteenable : in std_logic_vector(3 downto 0);
writedata : in std_logic_vector(31 downto 0);
write : in std_logic;
readdata : out std_logic_vector(31 downto 0);
interrupt : out std_logic;
-- DVB port
dvb_sop : in std_logic;
dvb_data : in std_logic_vector(7 downto 0);
dvb_dval : in std_logic;
-- memory port
mem_size : out std_logic_vector(6 downto 0);
mem_addr : out std_logic_vector(63 downto 3);
mem_byteen : out std_logic_vector(7 downto 0);
mem_wrdata : out std_logic_vector(63 downto 0);
mem_write : out std_logic;
mem_waitreq : in std_logic
);
end;
architecture rtl of dvb_dma is
constant REG_DMA_CTRLSTAT : natural := 0;
constant REG_DMA_CTRLSTAT_SET : natural := 0;
constant REG_DMA_CTRLSTAT_CLR : natural := 1;
constant REG_DMA_START_ADDR_L : natural := 2; -- first address of the ring buffer
constant REG_DMA_START_ADDR_H : natural := 3;
constant REG_DMA_SIZE : natural := 4; -- packet size, number of packets per interrupt block and number of blocks per buffer
constant REG_DMA_TIMEOUT : natural := 5; -- force interrupt when timer expires
constant REG_DMA_CURR_ADDR_L : natural := 6;
constant REG_DMA_CURR_ADDR_H : natural := 7;
constant REG_STAT_PKT_RECEIVED : natural := 8;
constant REG_STAT_PKT_ACCEPTED : natural := 9;
constant REG_STAT_PKT_OVERRUNS : natural := 10;
constant REG_STAT_PKT_UNDERRUNS : natural := 11;
constant REG_STAT_FIFO_OVERRUNS : natural := 12;
constant BIT_DMA_RUN : natural := 0;
constant BIT_DMA_IRQ : natural := 9;
signal dma_ctrlstat_reg : std_logic_vector(31 downto 0);
signal dma_start_addr : std_logic_vector(63 downto 0);
signal dma_timeout : std_logic_vector(31 downto 0);
alias dma_start_addr_l : std_logic_vector(31 downto 0) is dma_start_addr(31 downto 0);
alias dma_start_addr_h : std_logic_vector(31 downto 0) is dma_start_addr(63 downto 32);
signal dma_packet_size : std_logic_vector(7 downto 0);
signal dma_block_size : std_logic_vector(23 downto 8);
signal dma_length : std_logic_vector(31 downto 24);
-- control stat register fields
signal dma_run : std_logic;
signal dma_irq : std_logic;
signal dma_curr_addr : unsigned(63 downto 0);
alias dma_curr_addr_l : unsigned(31 downto 0) is dma_curr_addr(31 downto 0);
alias dma_curr_addr_h : unsigned(31 downto 0) is dma_curr_addr(63 downto 32);
signal dma_irq_reset : std_logic;
signal pkt_size : unsigned(dma_packet_size'length downto 0);
signal block_size : unsigned(dma_block_size'length downto 0);
signal blocks_num : unsigned(dma_length'length downto 0);
signal dvb_latch_data : std_logic_vector(dvb_data'range);
signal dvb_latch_dval : std_logic;
signal dvb_overrun_n : std_logic;
signal fifo_overflow : std_logic;
signal dvb_cnt : unsigned(pkt_size'range);
signal write_page : unsigned(2 downto 0);
signal write_addr_l : unsigned(dma_packet_size'range);
alias write_addr_h is write_page(write_page'left - 1 downto write_page'right);
signal stat_pkts_received : unsigned(31 downto 0);
signal stat_pkts_accepted : unsigned(31 downto 0);
signal stat_pkt_overruns : unsigned(31 downto 0);
signal stat_pkt_underruns : unsigned(31 downto 0);
signal stat_fifo_overruns : unsigned(31 downto 0);
signal dma_cnt : unsigned(pkt_size'range);
signal read_page : unsigned(2 downto 0);
alias read_addr_l is dma_cnt(dma_cnt'left - 1 downto dma_cnt'right + 3);
alias read_addr_h is read_page(read_page'left - 1 downto read_page'right);
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_rdclken : std_logic;
signal fifo_rdaddr : std_logic_vector(6 downto 0);
signal fifo_rddata : std_logic_vector(63 downto 0);
signal fifo_wraddr : std_logic_vector(9 downto 0);
signal fifo_wrdata : std_logic_vector(7 downto 0);
signal fifo_wren : std_logic;
signal fifo_latch_valid : std_logic;
signal fifo_rddata_valid : std_logic;
signal dma_reg : std_logic_vector(63 downto 0);
signal dma_reg_be : std_logic_vector(7 downto 0);
signal dma_reg_pad : std_logic_vector(63 downto 8);
signal dma_reg_pad_be : std_logic_vector(7 downto 1);
signal dma_reg_pad_wren : std_logic;
signal mem_write_i : std_logic;
signal burst_addr : unsigned(63 downto 0);
signal burst : std_logic;
signal burst_end : std_logic;
signal dma_pkt_cnt : unsigned(dma_block_size'length downto 0);
signal dma_blk_cnt : unsigned(dma_length'length downto 0);
signal dma_irq_pend : std_logic;
signal dma_reload_n : std_logic;
signal dma_timer : signed(dma_timeout'length downto 0);
signal dma_timer_d : std_logic;
begin
process (rst, clk)
begin
if rising_edge(clk) then
if write then
write_sr_flag(dma_run, REG_DMA_CTRLSTAT_SET, BIT_DMA_RUN, address, writedata, byteenable);
if not dma_run then
write_reg(dma_start_addr_l, REG_DMA_START_ADDR_L, address, writedata, byteenable);
write_reg(dma_start_addr_h, REG_DMA_START_ADDR_H, address, writedata, byteenable);
write_reg(dma_packet_size, REG_DMA_SIZE, address, writedata, byteenable);
write_reg(dma_block_size, REG_DMA_SIZE, address, writedata, byteenable);
write_reg(dma_length, REG_DMA_SIZE, address, writedata, byteenable);
write_reg(dma_timeout, REG_DMA_TIMEOUT, address, writedata, byteenable);
end if;
end if;
if unsigned(address) = REG_DMA_CTRLSTAT_CLR then
dma_irq_reset <= write and byteenable(BIT_DMA_IRQ / 8) and writedata(BIT_DMA_IRQ);
else
dma_irq_reset <= '0';
end if;
end if;
if rst then
dma_run <= '0';
dma_irq_reset <= '0';
--
dma_start_addr_l <= (others => '0');
dma_start_addr_h <= (others => '0');
dma_packet_size <= (others => '0');
dma_block_size <= (others => '0');
dma_length <= (others => '0');
dma_timeout <= (others => '0');
end if;
end process;
dma_ctrlstat_reg <= (
BIT_DMA_RUN => dma_run,
BIT_DMA_IRQ => dma_irq,
--
others => '0'
);
with to_integer(unsigned(address)) select
readdata <= dma_ctrlstat_reg when REG_DMA_CTRLSTAT_SET | REG_DMA_CTRLSTAT_CLR,
dma_start_addr_l when REG_DMA_START_ADDR_L,
dma_start_addr_h when REG_DMA_START_ADDR_H,
dma_length & dma_block_size & dma_packet_size when REG_DMA_SIZE,
dma_timeout when REG_DMA_TIMEOUT,
std_logic_vector(dma_curr_addr_l) when REG_DMA_CURR_ADDR_L,
std_logic_vector(dma_curr_addr_h) when REG_DMA_CURR_ADDR_H,
std_logic_vector(stat_pkts_received) when REG_STAT_PKT_RECEIVED,
std_logic_vector(stat_pkts_accepted) when REG_STAT_PKT_ACCEPTED,
std_logic_vector(stat_pkt_overruns) when REG_STAT_PKT_OVERRUNS,
std_logic_vector(stat_pkt_underruns) when REG_STAT_PKT_UNDERRUNS,
std_logic_vector(stat_fifo_overruns) when REG_STAT_FIFO_OVERRUNS,
(others => 'X') when others;
FIFO_0 : entity work.dvb_dma_fifo_ram
port map (
wrclock => clk,
wraddress => fifo_wraddr,
data => fifo_wrdata,
wren => fifo_wren,
--
rdclock => clk,
rdclocken => fifo_rdclken,
rdaddress => fifo_rdaddr,
q => fifo_rddata
);
fifo_wraddr <= std_logic_vector(write_addr_h & write_addr_l);
fifo_wrdata <= dvb_latch_data;
fifo_wren <= dvb_latch_dval;
fifo_rdaddr <= std_logic_vector(read_addr_h & read_addr_l);
fifo_rdclken <= mem_write_i nand mem_waitreq;
fifo_full <= write_page(write_page'left) xor read_page(read_page'left) when write_addr_h = read_addr_h else '0';
fifo_empty <= '1' when write_page = read_page else '0';
pkt_size(pkt_size'left) <= '1' when unsigned(dma_packet_size) = 0 else '0';
pkt_size(pkt_size'left - 1 downto 0) <= unsigned(dma_packet_size);
block_size(block_size'left) <= '1' when unsigned(dma_block_size) = 0 else '0';
block_size(block_size'left - 1 downto 0) <= unsigned(dma_block_size);
blocks_num(blocks_num'left) <= '1' when unsigned(dma_length) = 0 else '0';
blocks_num(blocks_num'left - 1 downto 0) <= unsigned(dma_length);
process (rst, dma_run, clk)
variable sop : std_logic;
variable burst_size : unsigned(8 downto 0);
begin
if rising_edge(clk) then
-- FIFO primary side
sop := dvb_sop and dvb_dval;
--
dvb_latch_data <= dvb_data;
dvb_latch_dval <= dvb_dval and ((dvb_sop and not fifo_full) or (dvb_cnt(dvb_cnt'left) and not fifo_overflow));
if dvb_dval then
if dvb_sop then
fifo_overflow <= fifo_full;
end if;
if dvb_sop then
dvb_cnt <= unsigned('1' & (-signed(dma_packet_size))) + 1;
elsif dvb_cnt(dvb_cnt'left) then
dvb_cnt <= dvb_cnt + 1;
end if;
if dvb_sop then
dvb_overrun_n <= '1';
else
dvb_overrun_n <= dvb_cnt(dvb_cnt'left);
end if;
end if;
if sop then
write_addr_l <= (others => '0');
elsif dvb_latch_dval then
write_addr_l <= write_addr_l + 1;
end if;
if not dvb_cnt(dvb_cnt'left) and dvb_latch_dval then
write_page <= write_page + 1;
end if;
-- statistic counters
if sop then
stat_pkts_received <= stat_pkts_received + 1;
end if;
if not dvb_cnt(dvb_cnt'left) and dvb_latch_dval then
stat_pkts_accepted <= stat_pkts_accepted + 1;
end if;
if not dvb_cnt(dvb_cnt'left) and dvb_dval and not dvb_sop and dvb_overrun_n then
stat_pkt_overruns <= stat_pkt_overruns + 1;
end if;
if sop and dvb_cnt(dvb_cnt'left) then
stat_pkt_underruns <= stat_pkt_underruns + 1;
end if;
if sop and fifo_full then
stat_fifo_overruns <= stat_fifo_overruns + 1;
end if;
-- FIFO secondary side
if fifo_rdclken then
if burst_end then
burst <= '0';
elsif not fifo_empty then
burst <= '1';
end if;
if not burst then
dma_cnt <= (others => '0');
else
dma_cnt <= dma_cnt + 8;
end if;
if dma_cnt < pkt_size then
fifo_latch_valid <= burst;
else
fifo_latch_valid <= '0';
end if;
fifo_rddata_valid <= fifo_latch_valid;
if not fifo_latch_valid and fifo_rddata_valid then
read_page <= read_page + 1;
end if;
-- bus alignment
dma_reg <= fifo_rddata;
case std_logic_vector(fifo_latch_valid & pkt_size(2 downto 0)) is
when "0111" =>
dma_reg_be <= (7 => '0', others => fifo_rddata_valid);
when "0110" =>
dma_reg_be <= (7 downto 6 => '0', others => fifo_rddata_valid);
when "0101" =>
dma_reg_be <= (7 downto 5 => '0', others => fifo_rddata_valid);
when "0100" =>
dma_reg_be <= (7 downto 4 => '0', others => fifo_rddata_valid);
when "0011" =>
dma_reg_be <= (7 downto 3 => '0', others => fifo_rddata_valid);
when "0010" =>
dma_reg_be <= (7 downto 2 => '0', others => fifo_rddata_valid);
when "0001" =>
dma_reg_be <= (7 downto 1 => '0', others => fifo_rddata_valid);
when others =>
dma_reg_be <= (others => fifo_rddata_valid);
end case;
dma_reg_pad <= dma_reg(63 downto 8);
dma_reg_pad_be <= dma_reg_be(7 downto 1);
case burst_addr(2 downto 0) is
when "111" =>
mem_wrdata <= dma_reg(7 downto 0) & dma_reg_pad;
mem_byteen <= dma_reg_be(0) & dma_reg_pad_be;
dma_reg_pad_wren <= dma_reg_be(1);
when "110" =>
mem_wrdata <= dma_reg(15 downto 0) & dma_reg_pad(63 downto 16);
mem_byteen <= dma_reg_be(1 downto 0) & dma_reg_pad_be(7 downto 2);
dma_reg_pad_wren <= dma_reg_be(2);
when "101" =>
mem_wrdata <= dma_reg(23 downto 0) & dma_reg_pad(63 downto 24);
mem_byteen <= dma_reg_be(2 downto 0) & dma_reg_pad_be(7 downto 3);
dma_reg_pad_wren <= dma_reg_be(3);
when "100" =>
mem_wrdata <= dma_reg(31 downto 0) & dma_reg_pad(63 downto 32);
mem_byteen <= dma_reg_be(3 downto 0) & dma_reg_pad_be(7 downto 4);
dma_reg_pad_wren <= dma_reg_be(4);
when "011" =>
mem_wrdata <= dma_reg(39 downto 0) & dma_reg_pad(63 downto 40);
mem_byteen <= dma_reg_be(4 downto 0) & dma_reg_pad_be(7 downto 5);
dma_reg_pad_wren <= dma_reg_be(5);
when "010" =>
mem_wrdata <= dma_reg(47 downto 0) & dma_reg_pad(63 downto 48);
mem_byteen <= dma_reg_be(5 downto 0) & dma_reg_pad_be(7 downto 6);
dma_reg_pad_wren <= dma_reg_be(6);
when "001" =>
mem_wrdata <= dma_reg(55 downto 0) & dma_reg_pad(63 downto 56);
mem_byteen <= dma_reg_be(6 downto 0) & dma_reg_pad_be(7);
dma_reg_pad_wren <= dma_reg_be(7);
when others =>
mem_wrdata <= dma_reg;
mem_byteen <= dma_reg_be;
dma_reg_pad_wren <= '0';
end case;
mem_write_i <= dma_reg_be(0) or dma_reg_pad_wren;
end if;
if not mem_write_i and dma_reg_be(0) then
burst_size := pkt_size + burst_addr(2 downto 0) + 7;
mem_size <= '0' & std_logic_vector(burst_size(8 downto 3));
end if;
burst_end <= (mem_write_i and not mem_waitreq) and (dma_reg_be(0) nor dma_reg_pad_wren);
-- process memory pointers
if dma_pkt_cnt = block_size then
dma_irq_pend <= not dma_irq_pend;
else
dma_irq_pend <= '0';
end if;
if dma_blk_cnt = blocks_num then
dma_reload_n <= not dma_reload_n;
else
dma_reload_n <= '1';
end if;
if dma_irq_pend then
dma_pkt_cnt <= (others => '0');
elsif burst_end then
dma_pkt_cnt <= dma_pkt_cnt + 1;
end if;
if not dma_reload_n then
dma_blk_cnt <= (others => '0');
elsif dma_irq_pend then
dma_blk_cnt <= dma_blk_cnt + 1;
end if;
if not dma_reload_n then
burst_addr <= unsigned(dma_start_addr);
elsif burst_end then
burst_addr <= burst_addr + pkt_size;
end if;
-- interrupts and status
if not dma_irq then
dma_curr_addr <= burst_addr;
end if;
if dma_irq_reset then
dma_irq <= '0';
elsif dma_irq_pend or (not dma_timer(dma_timer'left) and dma_timer_d) then
dma_irq <= '1';
end if;
-- DMA timeout timer
if burst_end or not dma_timer(dma_timer'left) then
dma_timer <= -signed('0' & dma_timeout);
else
dma_timer <= dma_timer + 1;
end if;
dma_timer_d <= dma_timer(dma_timer'left);
end if;
if not dma_run then
dvb_latch_data <= (others => '0');
dvb_latch_dval <= '0';
dvb_cnt <= (others => '0');
write_addr_l <= (others => '0');
write_page <= (others => '0');
dvb_overrun_n <= '0';
fifo_overflow <= '0';
-- statistic counters
stat_pkts_received <= (others => '0');
stat_pkts_accepted <= (others => '0');
stat_pkt_overruns <= (others => '0');
stat_pkt_underruns <= (others => '0');
stat_fifo_overruns <= (others => '0');
--
read_page <= (others => '0');
--
dma_pkt_cnt <= (others => '0');
dma_blk_cnt <= (others => '0');
dma_irq_pend <= '0';
dma_reload_n <= '0';
--
dma_curr_addr <= (others => '0');
dma_irq <= '0';
--
dma_timer <= (others => '0');
dma_timer_d <= '0';
end if;
if rst then
dma_cnt <= (others => '0');
fifo_latch_valid <= '0';
fifo_rddata_valid <= '0';
dma_reg <= (others => '0');
dma_reg_be <= (others => '0');
dma_reg_pad <= (others => '0');
dma_reg_pad_be <= (others => '0');
dma_reg_pad_wren <= '0';
--
burst <= '0';
burst_end <= '0';
burst_addr <= (others => '0');
--
mem_byteen <= (others => '0');
mem_wrdata <= (others => '0');
mem_write_i <= '0';
end if;
end process;
mem_addr <= std_logic_vector(burst_addr(63 downto 3));
mem_write <= mem_write_i;
interrupt <= dma_irq;
end;
|
gpl-3.0
|
45640df0f51110c258e658accff303f9
| 0.629803 | 2.739306 | false | false | false | false |
antlr/grammars-v4
|
vhdl/examples/textio.vhd
| 5 | 3,689 |
---------------------------------------------------------------------------
-- Package TEXTIO as defined in Chapter 14 of the IEEE Standard VHDL
-- Language Reference Manual (IEEE Std. 1076-1987), as modified
-- by the Issues Screening and Analysis Committee (ISAC), a subcommittee
-- of the VHDL Analysis and Standardization Group (VASG) on
-- 10 November, 1988. See "The Sense of the VASG", October, 1989.
---------------------------------------------------------------------------
-- Version information: %W% %G%
---------------------------------------------------------------------------
package TEXTIO is
type LINE is access string;
type TEXT is file of string;
type SIDE is (right, left);
subtype WIDTH is natural;
-- changed for vhdl92 syntax:
file input : TEXT open read_mode is "STD_INPUT";
file output : TEXT open write_mode is "STD_OUTPUT";
-- changed for vhdl92 syntax (and now a built-in):
procedure READLINE(file f: TEXT; L: out LINE);
procedure READ(L:inout LINE; VALUE: out bit; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out bit);
procedure READ(L:inout LINE; VALUE: out bit_vector; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out bit_vector);
procedure READ(L:inout LINE; VALUE: out BOOLEAN; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out character; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out character);
procedure READ(L:inout LINE; VALUE: out integer; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out integer);
procedure READ(L:inout LINE; VALUE: out real; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out real);
procedure READ(L:inout LINE; VALUE: out string; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out string);
procedure READ(L:inout LINE; VALUE: out time; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out time);
-- changed for vhdl92 syntax (and now a built-in):
procedure WRITELINE(file f : TEXT; L : inout LINE);
procedure WRITE(L : inout LINE; VALUE : in bit;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in bit_vector;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in BOOLEAN;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in character;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in integer;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in real;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0;
DIGITS: in NATURAL := 0);
procedure WRITE(L : inout LINE; VALUE : in string;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in time;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0;
UNIT: in TIME := ns);
-- is implicit built-in:
-- function ENDFILE(file F : TEXT) return boolean;
-- function ENDLINE(variable L : in LINE) return BOOLEAN;
--
-- Function ENDLINE as declared cannot be legal VHDL, and
-- the entire function was deleted from the definition
-- by the Issues Screening and Analysis Committee (ISAC),
-- a subcommittee of the VHDL Analysis and Standardization
-- Group (VASG) on 10 November, 1988. See "The Sense of
-- the VASG", October, 1989, VHDL Issue Number 0032.
end;
|
mit
|
fa316919494b9b345f8d15ca53ce662b
| 0.61209 | 4.098889 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/koc/koc_signal_axi4_read_cntrl.vhd
| 1 | 3,628 |
library ieee;
use ieee.std_logic_1164.all;
use work.koc_signal_pack.all;
entity koc_signal_axi4_read_cntrl is
generic (
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000";
reg_control_signal_bit_loc : integer := 0;
reg_control_status_bit_loc : integer := 1
);
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal.
axi_arready : out std_logic; --! AXI4-Lite Address Read signal.
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal.
axi_rready : in std_logic; --! AXI4-Lite Read Data signal.
axi_rresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Read Data signal.
int : in std_logic);
end koc_signal_axi4_read_cntrl;
architecture Behavioral of koc_signal_axi4_read_cntrl is
type state_type is (state_wait,state_read);
signal state : state_type := state_wait;
signal axi_arready_buff : std_logic := '0';
signal axi_rvalid_buff : std_logic := '0';
signal axi_araddr_buff : std_logic_vector(axi_address_width-1 downto 0);
begin
axi_arready <= axi_arready_buff;
axi_rvalid <= axi_rvalid_buff;
axi_rresp <= axi_resp_okay;
process (aclk)
variable reg_control_var : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
begin
if rising_edge(aclk) then
if aresetn='0' then
axi_arready_buff <= '0';
axi_rvalid_buff <= '0';
state <= state_wait;
else
case state is
when state_wait=>
if axi_arvalid='1' and axi_arready_buff='1' then
axi_arready_buff <= '0';
axi_rvalid_buff <= '1';
axi_araddr_buff <= axi_araddr;
state <= state_read;
else
axi_arready_buff <= '1';
end if;
when state_read=>
if axi_rvalid_buff='1' and axi_rready='1' then
axi_rvalid_buff <= '0';
state <= state_wait;
else
axi_rvalid_buff <= '1';
if axi_araddr_buff=reg_control_offset then
reg_control_var := (others=>'0');
reg_control_var(reg_control_status_bit_loc) := int;
axi_rdata <= reg_control_var;
else
axi_rdata <= (others=>'0');
end if;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
5a25306e94acc8392ddce3798d7a3a8d
| 0.453418 | 4.435208 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/koc/koc_lock_axi4_write_cntrl.vhd
| 1 | 5,077 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.koc_lock_pack.all;
entity koc_lock_axi4_write_cntrl is
generic (
axi_address_width : integer := 16;
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000";
reg_control_default : std_logic_vector := X"00000001"
);
port (
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic;
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal.
axi_awready : out std_logic; --! AXI4-Lite Address Write signal.
axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal.
axi_wready : out std_logic; --! AXI4-Lite Write Data signal.
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal.
axi_bready : in std_logic; --! AXI4-Lite Write Response signal.
axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
reg_control : out std_logic_vector(axi_data_width-1 downto 0)
);
end koc_lock_axi4_write_cntrl;
architecture Behavioral of koc_lock_axi4_write_cntrl is
type state_type is (state_wait,state_write,state_response);
signal state : state_type := state_wait;
signal axi_awready_buff : std_logic := '0';
signal axi_awaddr_buff : std_logic_vector(axi_address_width-1 downto 0);
signal axi_wready_buff : std_logic := '0';
signal axi_bvalid_buff : std_logic := '0';
signal reg_control_buff : std_logic_vector(axi_data_width-1 downto 0) := reg_control_default;
begin
axi_awready <= axi_awready_buff;
axi_wready <= axi_wready_buff;
axi_bvalid <= axi_bvalid_buff;
axi_bresp <= axi_resp_okay;
reg_control <= reg_control_buff;
-- Drive the axi write interface.
process (aclk)
variable reg_control_var : std_logic_vector(axi_data_width-1 downto 0);
begin
-- Perform operations on the clock's positive edge.
if rising_edge(aclk) then
if aresetn='0' then
axi_awready_buff <= '0';
axi_wready_buff <= '0';
axi_bvalid_buff <= '0';
reg_control_buff <= reg_control_default;
state <= state_wait;
else
case state is
when state_wait=>
if axi_awvalid='1' and axi_awready_buff='1' then
axi_awready_buff <= '0';
axi_awaddr_buff <= axi_awaddr;
axi_wready_buff <= '1';
state <= state_write;
else
axi_awready_buff <= '1';
end if;
when state_write=>
if axi_wvalid='1' and axi_wready_buff='1' then
axi_wready_buff <= '0';
-- Determine control value from device requesting lock.
reg_control_var := (others=>'0');
for each_byte in 0 to axi_data_width/8-1 loop
if axi_awaddr_buff=reg_control_offset and axi_wstrb(each_byte)='1' then
reg_control_var(7+each_byte*8 downto each_byte*8) :=
axi_wdata(7+each_byte*8 downto each_byte*8);
end if;
end loop;
-- Perform lock if lock is available, or release it.
if reg_control_buff=reg_control_var then
reg_control_buff <= (others=>'0');
elsif reg_control_buff=std_logic_vector(to_unsigned(0,axi_data_width)) then
reg_control_buff <= reg_control_var;
end if;
state <= state_response;
axi_bvalid_buff <= '1';
end if;
when state_response=>
if axi_bvalid_buff='1' and axi_bready='1' then
axi_bvalid_buff <= '0';
state <= state_wait;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
75cc7d76dcf99c835a267431fc0ca8dd
| 0.484538 | 4.331911 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/SPI Interface/Source/SPI_SlaveTransmitter.vhd
| 1 | 4,223 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Provides an SPI slave transmitter consisting of an input selector, a single
-- transmitter buffer, and a transmitter serializer. The data width is fixed (see
-- data_width constant value in the Globals package).
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.globals.all;
-- Note: It's not possible to use generics for both the data width and the number
-- of buffers to be generated. This would need a signal that is an array of
-- unconstrained arrays which is not yet supported by VHDL. Thus, the data width
-- is fixed (see Globals package).
entity SPI_SlaveTransmitter is
generic
(
-- The width of the address.
address_width: positive
);
port
(
-- The system clock.
clk: in std_logic;
-- Controls when the data to be transmitted are read (input is passed
-- when enable is '1', synchronous to CLK).
buffer_enable: in std_logic;
-- The clock controlling the serial data transmission.
sclk: in std_logic;
-- The (active low) slave select.
ss: in std_logic;
-- The selected address to read the data to be transmitted from.
address: in unsigned(address_width-1 downto 0);
-- The parallel inputs used to get the data to be sent from.
data_x: in data_buffer_vector((2**address_width)-1 downto 0);
-- The serial output.
miso: out std_logic
);
end entity;
architecture stdarch of SPI_SlaveTransmitter is
constant number_of_data_buffers: positive := 2**address_width;
signal selected_data, transmitter_data: data_buffer;
begin
--------------------------------------------------------------------------------
-- Instantiate components.
--------------------------------------------------------------------------------
-- The input data buffer (transparent if the enable signal is '1'; synchronous
-- to clk).
data_buffer: entity work.SPI_SlaveDataBuffer
generic map
(
width => data_width,
edge_triggered => false
)
port map
(
clk => clk,
buffer_enable => buffer_enable,
data => selected_data,
buffered_data => transmitter_data,
ready => open
);
-- The slave transmitter serializer.
serializer: entity work.SPI_SlaveTransmitterSerializer
generic map
(
width => data_width
)
port map
(
sclk => sclk,
ss => ss,
data => transmitter_data,
miso => miso
);
--------------------------------------------------------------------------------
-- Input selection logic.
--------------------------------------------------------------------------------
-- The data buffer.
input_selector: process(address, data_x) is
begin
selected_data <= (others => '1');
for i in number_of_data_buffers-1 downto 0 loop
if (address = to_unsigned(i, address_width)) then
selected_data <= data_x(i);
end if;
end loop;
end process;
end architecture;
|
gpl-3.0
|
2041731996eedc7e37e7ca224b1ba045
| 0.528061 | 4.997633 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/flashyLights/ipcore_dir/memmory/simulation/bmg_tb_pkg.vhd
| 101 | 6,006 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
|
gpl-3.0
|
e2ab1e568c94b1517e2d0e90d3d8c2ff
| 0.577589 | 4.609363 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/koc/koc_signal_axi4_write_cntrl.vhd
| 1 | 5,141 |
library ieee;
use ieee.std_logic_1164.all;
use work.koc_signal_pack.all;
entity koc_signal_axi4_write_cntrl is
generic (
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000";
reg_control_signal_bit_loc : integer := 0;
reg_control_status_bit_loc : integer := 1
);
port (
-- Global Interface.
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic; --! Reset on low.
-- Slave AXI4-Lite Write interface.
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal.
axi_awready : out std_logic; --! AXI4-Lite Address Write signal.
axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal.
axi_wready : out std_logic; --! AXI4-Lite Write Data signal.
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal.
axi_bready : in std_logic; --! AXI4-Lite Write Response signal.
axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
sig_trig : out std_logic;
sig_ack : out std_logic
);
end koc_signal_axi4_write_cntrl;
architecture Behavioral of koc_signal_axi4_write_cntrl is
type state_type is (state_wait,state_write,state_response);
signal state : state_type := state_wait;
signal axi_awready_buff : std_logic := '0';
signal axi_awaddr_buff : std_logic_vector(axi_address_width-1 downto 0);
signal axi_wready_buff : std_logic := '0';
signal axi_bvalid_buff : std_logic := '0';
begin
axi_awready <= axi_awready_buff;
axi_wready <= axi_wready_buff;
axi_bvalid <= axi_bvalid_buff;
axi_bresp <= axi_resp_okay;
-- Drive the axi write interface.
process (aclk)
variable reg_control_var : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
begin
-- Perform operations on the clock's positive edge.
if rising_edge(aclk) then
if aresetn='0' then
axi_awready_buff <= '0';
axi_wready_buff <= '0';
axi_bvalid_buff <= '0';
state <= state_wait;
else
case state is
when state_wait=>
if axi_awvalid='1' and axi_awready_buff='1' then
axi_awready_buff <= '0';
axi_awaddr_buff <= axi_awaddr;
axi_wready_buff <= '1';
state <= state_write;
else
axi_awready_buff <= '1';
end if;
when state_write=>
if axi_wvalid='1' and axi_wready_buff='1' then
axi_wready_buff <= '0';
reg_control_var := (others=>'0');
for each_byte in 0 to axi_data_width/8-1 loop
if axi_wstrb(each_byte)='1' then
if axi_awaddr_buff=reg_control_offset then
reg_control_var(7+each_byte*8 downto each_byte*8) :=
axi_wdata(7+each_byte*8 downto each_byte*8);
end if;
end if;
end loop;
if axi_awaddr_buff=reg_control_offset then
sig_trig <= reg_control_var(reg_control_signal_bit_loc);
sig_ack <= reg_control_var(reg_control_status_bit_loc);
end if;
state <= state_response;
axi_bvalid_buff <= '1';
end if;
when state_response=>
sig_trig <= '0';
sig_ack <= '0';
if axi_bvalid_buff='1' and axi_bready='1' then
axi_bvalid_buff <= '0';
state <= state_wait;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
4d485611afbe340521a889500709a5ea
| 0.454192 | 4.501751 | false | false | false | false |
arthurTemporim/SD_SS
|
pre/7/projetos/projeto1/projeto2.vhd
| 1 | 2,703 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library adk;
use adk.all;
entity projeto2 is
port(
clk : in std_logic;
a : in std_logic := '0';
b : in std_logic := '0';
c : in std_logic := '0';
sa : out std_logic;
sb : out std_logic;
sc : out std_logic
);
end projeto2;
architecture Behavioral of projeto2 is
--###################################################--
-- COMPONENTS
-- FLIP-FLOP
component flip_flop_jk
port( J: in std_logic;
K: in std_logic;
Reset: in std_logic;
Clock_enable: in std_logic;
Clock: in std_logic;
Output: out std_logic);
end component;
-- DISPLAY
COMPONENT display
PORT(
a : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
display1 : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
-- SINAIS
--###################################################--
signal Clock : std_logic := '0';
-- FLIP-FLOPs
-- SINAIS GENERICOS DOS FFs
signal Reset : std_logic := '0'; -- Funciona como Clear.
signal Clock_enable : std_logic := '1';
--FFa
--Inputs
signal Ja : std_logic := '1';
signal Ka : std_logic := '1';
--Outputs
signal OutA : std_logic;
--FFb
--Inputs
signal Jb : std_logic := '1';
signal Kb : std_logic := '1';
--Outputs
signal OutB : std_logic;
--FFc
--Inputs
signal Jc : std_logic := '1';
signal Kc : std_logic := '1';
--Outputs
signal OutC : std_logic;
--DISPLAYs
--Inputs
signal inDisplay1 : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal outDisplay1 : std_logic_vector(6 downto 0);
--###################################################--
begin
-- Inicializa componentes
--###################################################--
--FFs
fa: flip_flop_jk PORT MAP (
J => Ja,
K => Ka,
Reset => Reset,
Clock_enable => Clock_enable,
Clock => Clock,
Output => outA
);
fb: flip_flop_jk PORT MAP (
J => Jb,
K => Kb,
Reset => Reset,
Clock_enable => Clock_enable,
Clock => Clock,
Output => outB
);
fc: flip_flop_jk PORT MAP (
J => Jc,
K => Kc,
Reset => Reset,
Clock_enable => Clock_enable,
Clock => Clock,
Output => outC
);
-- DISPLAYs
display1: display PORT MAP (
a => inDisplay1,
clk => Clock,
display1 => outDisplay1
);
--###################################################--
clock <= clk;
-- process(Ja,Ka,Jb,Kb,Jc,Kc,Reset,outA,outB,outC,clk)
-- begin
Ja <= '1';
Ka <= '1';
Jb <= outA;
Kb <= outA;
Jc <= (outA and outB);
Kc <= (outA and outB);
inDisplay1(3) <= '0';
inDisplay1(2) <= OutC;
inDisplay1(1) <= OutB;
inDisplay1(0) <= OutA;
-- end process;
sa <= outA;
sb <= outB;
sc <= outC;
end Behavioral;
|
mit
|
7829f619223f6841580f4ce0a778b147
| 0.520903 | 3.013378 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/DCM_clock/ipcore_dir/my_dcm/simulation/timing/my_dcm_tb.vhd
| 1 | 6,254 |
-- file: my_dcm_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity my_dcm_tb is
end my_dcm_tb;
architecture test of my_dcm_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.25 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component my_dcm_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
report "Timing checks are not valid" severity note;
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19.5);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : my_dcm_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
|
gpl-3.0
|
97b35e3f1daa14a2ef9c057cdf89fb31
| 0.642309 | 4.24 | false | false | false | false |
arthurbenemann/fpga-bits
|
mandelbrot/mandelbrot_pipeline4.vhd
| 1 | 1,865 |
--
-- Pipeline of 4 mandelbrot iteration blocks
--
-- * 4x latency of each block (total of 28 cycles)
-- * no registers
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
entity mandelbrot_pipeline4 is port (
clk : IN std_logic;
ov_in : in std_logic;
x,y,x0,y0 : IN std_logic_vector(17 downto 0);
x_out,y_out,x0_out,y0_out : OUT std_logic_vector(17 downto 0);
ov : OUT std_logic_vector (3 downto 0));
end mandelbrot_pipeline4;
architecture Behavioral of mandelbrot_pipeline4 is
component mandelbrot_iteration port(
clk : IN std_logic;
ov_in : in std_logic;
x,y,x0,y0 : IN std_logic_vector(17 downto 0);
x_out,y_out,x0_out,y0_out : OUT std_logic_vector(17 downto 0);
ov : OUT std_logic);
end component;
signal x1,x2,x3,x0_1,x0_2,x0_3 : std_logic_vector (17 downto 0);
signal y1,y2,y3,y0_1,y0_2,y0_3 : std_logic_vector (17 downto 0);
signal o1,o2,o3,o4 : std_logic;
begin
iteration1 : mandelbrot_iteration port map(
clk => clk,
ov_in => ov_in,
x => x, y => y, x0 => x0, y0 => y0, -- inputs
x_out => x1, y_out => y1, ov => o1, -- outputs
x0_out=> x0_1, y0_out => y0_1
);
iteration2 : mandelbrot_iteration port map(
clk => clk,
ov_in => o1,
x => x1, y => y1, x0 => x0_1, y0 => y0_1, -- inputs
x_out => x2, y_out => y2, ov => o2, -- outputs
x0_out=> x0_2, y0_out => y0_2
);
iteration3 : mandelbrot_iteration port map(
clk => clk,
ov_in => o2,
x => x2, y => y2, x0 => x0_2, y0 => y0_2, -- inputs
x_out => x3, y_out => y3, ov => o3, -- outputs
x0_out=> x0_3, y0_out => y0_3
);
iteration4 : mandelbrot_iteration port map(
clk => clk,
ov_in => o3,
x => x3, y => y3, x0 => x0_3, y0 => y0_3, -- inputs
x_out => x_out, y_out => y_out, ov => o4, -- outputs
x0_out=> x0_out, y0_out => y0_out
);
ov <= o1 & o2 & o3 & o4;
end Behavioral;
|
gpl-3.0
|
6972aeb364e206590cc740e556ebfee9
| 0.590349 | 2.31677 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/bd/ip/bd_proc_sys_reset_0_0/synth/bd_proc_sys_reset_0_0.vhd
| 1 | 6,554 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY bd_proc_sys_reset_0_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END bd_proc_sys_reset_0_0;
ARCHITECTURE bd_proc_sys_reset_0_0_arch OF bd_proc_sys_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bd_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bd_proc_sys_reset_0_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bd_proc_sys_reset_0_0_arch : ARCHITECTURE IS "bd_proc_sys_reset_0_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bd_proc_sys_reset_0_0_arch: ARCHITECTURE IS "bd_proc_sys_reset_0_0,proc_sys_reset,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=1,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "artix7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END bd_proc_sys_reset_0_0_arch;
|
mit
|
776e43c57ed80934ba2206d718a4c8ef
| 0.711779 | 3.467725 | false | false | false | false |
arthurbenemann/fpga-bits
|
mandelbrot/iteration.vhd
| 1 | 1,386 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity iteration is port (
clk : in std_logic;
-- inputs
x : in std_logic_vector (17 downto 0);
y : in std_logic_vector (17 downto 0);
x0 : in std_logic_vector (17 downto 0);
y0 : in std_logic_vector (17 downto 0);
-- outputs
x_out : out std_logic_vector (17 downto 0);
y_out : out std_logic_vector (17 downto 0);
ov : out std_logic);
end iteration;
architecture Behavioral of iteration is
signal px : std_logic_vector (17 downto 0);
signal py : std_logic_vector (17 downto 0);
signal sumx : std_logic_vector (17 downto 0);
signal sumy : std_logic_vector (17 downto 0);
component multiplier port (
clk: in std_logic;
ar: in std_logic_vector(17 downto 0);
ai: in std_logic_vector(17 downto 0);
br: in std_logic_vector(17 downto 0);
bi: in std_logic_vector(17 downto 0);
pr: out std_logic_vector(17 downto 0);
pi: out std_logic_vector(17 downto 0));
end component;
constant escape : std_logic_vector(17 downto 0) := "11"& x"0000";
begin
mul1 : multiplier port map (
clk => clk,
ar => x,
ai => y,
br => x,
bi => y,
pr => px,
pi => py);
sumx <= px + x0;
sumy <= py + y0;
--ov <= sumx(7) or sumy(5);
x_out <= x;
y_out <= y;
ov <= '1' when (sumx > escape) or (sumy > escape) else '0';
end Behavioral;
|
gpl-3.0
|
d64896cd151616090871ee7f4721fdd6
| 0.633478 | 2.701754 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/flashyLights/ipcore_dir/counter30.vhd
| 1 | 4,054 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file counter30.vhd when simulating
-- the core, counter30. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY counter30 IS
PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(29 DOWNTO 0)
);
END counter30;
ARCHITECTURE counter30_a OF counter30 IS
-- synthesis translate_off
COMPONENT wrapped_counter30
PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(29 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_counter30 USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral)
GENERIC MAP (
c_ainit_val => "0",
c_ce_overrides_sync => 0,
c_count_by => "1",
c_count_mode => 0,
c_count_to => "1",
c_fb_latency => 0,
c_has_ce => 0,
c_has_load => 0,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_has_thresh0 => 0,
c_implementation => 0,
c_latency => 1,
c_load_low => 0,
c_restrict_count => 0,
c_sclr_overrides_sset => 1,
c_sinit_val => "0",
c_thresh0_value => "1",
c_verbosity => 0,
c_width => 30,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_counter30
PORT MAP (
clk => clk,
q => q
);
-- synthesis translate_on
END counter30_a;
|
gpl-3.0
|
bcaca4d150e783e4e10cb79f2ccca9d5
| 0.536507 | 4.747073 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
fifo_out_8b_sync_1.vhd
| 1 | 3,681 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- fifo_out_8b_sync_1.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fifo_out_8b_sync_1 is
port (
addr : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_slave_0.address
in_data : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
wr_en : in std_logic := '0'; -- .write
out_data : out std_logic_vector(31 downto 0); -- .readdata
wait_req : out std_logic; -- .waitrequest
byte_en : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
st_data : out std_logic_vector(7 downto 0); -- avalon_streaming_source.data
st_ready : in std_logic := '0'; -- .ready
st_valid : out std_logic; -- .valid
irq : out std_logic -- conduit_end.export
);
end entity fifo_out_8b_sync_1;
architecture rtl of fifo_out_8b_sync_1 is
component fifo_out_8b_sync is
generic (
FIFO_DEPTH : integer := 16;
BUS_WIDTH : integer := 32
);
port (
addr : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
in_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
wr_en : in std_logic := 'X'; -- write
out_data : out std_logic_vector(31 downto 0); -- readdata
wait_req : out std_logic; -- waitrequest
byte_en : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
st_data : out std_logic_vector(7 downto 0); -- data
st_ready : in std_logic := 'X'; -- ready
st_valid : out std_logic; -- valid
irq : out std_logic -- export
);
end component fifo_out_8b_sync;
begin
fifo_out_8b_sync_1 : component fifo_out_8b_sync
generic map (
FIFO_DEPTH => 16,
BUS_WIDTH => 32
)
port map (
addr => addr, -- avalon_slave_0.address
in_data => in_data, -- .writedata
wr_en => wr_en, -- .write
out_data => out_data, -- .readdata
wait_req => wait_req, -- .waitrequest
byte_en => byte_en, -- .byteenable
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
st_data => st_data, -- avalon_streaming_source.data
st_ready => st_ready, -- .ready
st_valid => st_valid, -- .valid
irq => irq -- conduit_end.export
);
end architecture rtl; -- of fifo_out_8b_sync_1
|
gpl-3.0
|
109aaca3a358ef28ef469d899e1f1b68
| 0.430861 | 3.684685 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/flashyLights/ipcore_dir/memmory/simulation/addr_gen.vhd
| 101 | 4,409 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
e8650984ac77fc98f78573f615e0a967
| 0.579496 | 4.58316 | false | false | false | false |
rinatzakirov/vhdl
|
sizing.vhdl
| 1 | 6,144 |
--------------------------------------------------------------------
-- _ __ __ __ ____ __ = --
-- | | / // / / // __ \ / / = --
-- | | / // /_/ // / / // / = .__ |/ _/_ .__ .__ __ --
-- | |/ // __ // /_/ // /___ = /___) | / / ) / ) (_ ` --
-- |___//_/ /_//_____//_____/ = (___ /| (_ / (___(_ (__) --
-- ===== / --
-- === --
----------------------------- = ----------------------------------
--# sizing.vhdl - Functions to compute array sizes
--# $Id$
--# Freely available from VHDL-extras (http://code.google.com/p/vhdl-extras)
--#
--# Copyright © 2010 Kevin Thibedeau
--# (kevin 'period' thibedeau 'at' gmail 'punto' com)
--#
--# Permission is hereby granted, free of charge, to any person obtaining a
--# copy of this software and associated documentation files (the "Software"),
--# to deal in the Software without restriction, including without limitation
--# the rights to use, copy, modify, merge, publish, distribute, sublicense,
--# and/or sell copies of the Software, and to permit persons to whom the
--# Software is furnished to do so, subject to the following conditions:
--#
--# The above copyright notice and this permission notice shall be included in
--# all copies or substantial portions of the Software.
--#
--# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
--# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
--# DEALINGS IN THE SOFTWARE.
--#
--# DEPENDENCIES: none
--#
--# DESCRIPTION:
--# This package provides functions used to compute integer approximations
--# of logarithms. The primary use of these functions is to determine the
--# size of arrays using the bit_size and encoding_size functions. When put to
--# maximal use it is possible to create designs that eliminate hardcoded
--# ranges and automatically resize their signals and variables by changing a
--# few key constants or generics.
--#
--# These functions can be used in most synthesizers to compute ranges for
--# arrays. The core functionality is provided in the ceil_log and
--# floor_log subprograms. These compute the logarithm in any integer base.
--# For convenenience, base-2 functions are also provided along with the array
--# sizing functions.
--#
--# EXAMPLE USAGE:
--# constant MAX_COUNT : natural := 1000;
--# constant COUNT_SIZE : natural := bit_size(MAX_COUNT);
--# signal counter : unsigned(COUNT_SIZE-1 downto 0);
--# ...
--# counter <= to_unsigned(MAX_COUNT, COUNT_SIZE);
--# -- counter will resize itself as MAX_COUNT is changed
--------------------------------------------------------------------
package sizing is
--## Compute the integer result of the function floor(log(n)) where b is the base
function floor_log(n, b : positive) return natural;
--## Compute the integer result of the function ceil(log(n)) where b is the base
function ceil_log(n, b : positive) return natural;
--## Compute the integer result of the function floor(log2(n))
function floor_log2(n : positive) return natural;
--## Compute the integer result of the function ceil(log2(n))
function ceil_log2(n : positive) return natural;
--## Compute the total number of bits needed to represent a number in binary
function bit_size(n : natural) return natural;
--## Compute the number of bits needed to encode n items
function encoding_size(n : positive) return natural;
-- synthesis translate_off
-- Needed to keep Xilinx ISE 12.1 happy
alias unsigned_size is bit_size[natural return natural];
-- synthesis translate_on
--## Compute the total number of bits to represent a 2's complement signed
--# integer in binary
function signed_size(n : integer) return natural;
end package;
package body sizing is
--## Compute the integer result of the function floor(log(n)) where b is the base
function floor_log(n, b : positive) return natural is
variable log, residual : natural;
begin
residual := n;
log := 0;
while residual > (b - 1) loop
residual := residual / b;
log := log + 1;
end loop;
return log;
end function;
--## Compute the integer result of the function ceil(log(n)) where b is the base
function ceil_log(n, b : positive) return natural is
variable log, residual : natural;
begin
residual := n - 1;
log := 0;
while residual > 0 loop
residual := residual / b;
log := log + 1;
end loop;
return log;
end function;
--## Compute the integer result of the function floor(log2(n))
function floor_log2(n : positive) return natural is
begin
return floor_log(n, 2);
end function;
--## Compute the integer result of the function ceil(log2(n))
function ceil_log2(n : positive) return natural is
begin
return ceil_log(n, 2);
end function;
--## Compute the total number of bits needed to represent a number in binary
function bit_size(n : natural) return natural is
begin
if n = 0 then
return 1;
else
return floor_log2(n) + 1;
end if;
end function;
--## Compute the number of bits needed to encode n items
function encoding_size(n : positive) return natural is
begin
if n = 1 then
return 1;
else
return ceil_log2(n);
end if;
end function;
--## Compute the total number of bits to represent a 2's complement signed
--# integer in binary
function signed_size(n : integer) return natural is
begin
if n = 0 then
return 2; -- sign bit plus single numeric bit
elsif n > 0 then
return bit_size(n) + 1;
else -- n < 0
return bit_size(-1 - n) + 1;
end if;
end function;
end package body;
|
lgpl-2.1
|
5402c202a60f2f7ca2d573888ad9cf9f
| 0.616211 | 4.190996 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/SPI Interface/Source/SPI_SlaveReceiverDeserializer.vhd
| 1 | 2,968 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Provides an SPI slave receiver deserializer operating in SPI mode 3. This means
-- that the incoming serial data are sampled at the trailing (rising) SCLK edges.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SPI_SlaveReceiverDeserializer is
generic
(
-- The width of the data.
width: positive
);
port
(
-- The clock controlling the serial data transmission.
sclk: in std_logic;
-- The serial input.
mosi: in std_logic;
-- The parallel output providing the data received.
data: out std_logic_vector(width-1 downto 0) := (others => '0')
);
end entity;
architecture stdarch of SPI_SlaveReceiverDeserializer is
type reg_type is record
data: std_logic_vector(width-1 downto 0);
end record;
signal state, next_state: reg_type :=
(
data => (others => '0')
);
begin
--------------------------------------------------------------------------------
-- State register.
--------------------------------------------------------------------------------
state_register: process is
begin
wait until rising_edge(sclk);
state <= next_state;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state_logic: process(state, mosi) is
begin
-- Defaults.
next_state <= state;
next_state.data <= state.data(width-2 downto 0) & mosi;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
data <= state.data;
end architecture;
|
gpl-3.0
|
3f60e3169112f8092101188675699974
| 0.453504 | 5.589454 | false | false | false | false |
arthurTemporim/SD_SS
|
pre/3/projetos/somaSub.vhd
| 1 | 1,530 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity somaSub is
Port (
A : in std_logic_vector (2 downto 0) := "011";
B : in std_logic_vector (2 downto 0) := "001";
sel : in std_logic := '0';
S : out std_logic_vector (2 downto 0);
E : out std_logic
);
end somaSub;
architecture Behavioral of somaSub is
signal aux : std_logic_vector (2 downto 0);
signal c : std_logic;
signal c2 : std_logic;
signal ccomp : std_logic;
signal over : std_logic;
signal igua : std_logic;
signal comp1 : std_logic_vector (2 downto 0);
signal comp2 : std_logic_vector (2 downto 0);
begin
process (a,b,sel,c,c2,comp1,comp2,ccomp,aux, igua)
begin
-- Soma
if (sel = '0') then
aux(0) <= a(0) xor b(0);
c <= a(0) and b(0);
aux(1) <= a(1) xor b(1) xor c;
aux(2) <= (a(1) and b(1)) or (a(1) and c) or (b(1) and c);
igua <= not(a(0) xor b(0));
over <= c and igua;
--subtrai
else
-- Aplica complemento de 1 no B
comp1 <= b xor "111";
-- Aplica complemento de 2 no B
comp2(0) <= comp1(0) xor '1';
ccomp <= comp1(0) and '1';
comp2(1) <= comp1(1) xor ccomp;
comp2(2) <= (comp1(1) and '1') or (comp1(1) and ccomp) or ('1' and ccomp);
-- Faz a soma
aux(0) <= a(0) xor comp2(0);
c2 <= (a(0) and comp2(0)) or (a(0) and ccomp) or (comp2(0) and ccomp);
aux(1) <= a(1) xor comp2(1) xor c2;
aux(2) <= (a(1) and comp2(1)) or (a(1) and c2);
igua <= not(a(0) xor comp2(0));
over <= c2 and igua;
end if;
end process;
e <= over;
s <= aux;
end Behavioral;
|
mit
|
91c114c9f8d7c4f5c419a46578cadd0f
| 0.570588 | 2.335878 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/SRAM/sram.vhd
| 1 | 1,590 |
--
-- SRAM controller for Papilio Duo
--
-- based on 'FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version' by Pong P. Chu
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sram is port (
-- interface
clk : in std_logic;
mem : in std_logic;
rw : in std_logic; -- read '1' / write '0'
ready : out std_logic;
addr : in std_logic_vector(20 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
-- SRAM interface
SRAM_ADDR : out std_logic_vector (20 downto 0);
SRAM_DATA : inout std_logic_vector (7 downto 0);
SRAM_CE : out std_logic;
SRAM_WE : out std_logic;
SRAM_OE : out std_logic);
end sram;
architecture Behavioral of sram is
type state_t is (idle, read1, read2, write1, write2);
signal state : state_t := idle;
begin
SRAM_CE <= '0'; -- sram always enabled
--SRAM_OE <= '1';
process(clk) begin
if rising_edge(clk) then
case state is
when idle =>
ready <= '1';
SRAM_DATA <= "ZZZZZZZZ";
SRAM_WE <= '1';
SRAM_OE <= '1';
if mem = '1' then
SRAM_ADDR <= addr;
if rw = '1' then
state <= read1;
else
state <= write1;
SRAM_DATA <= din;
end if;
end if;
when read1 =>
ready <= '0';
SRAM_OE <= '0';
state <= read2;
when read2 =>
SRAM_OE <= '0';
dout <= SRAM_DATA;
state <= idle;
when write1 =>
ready <= '0';
SRAM_WE <= '0';
state <= write2;
when write2 =>
SRAM_DATA <= din;
state <= idle;
end case;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
2e8e24b3c90920d1745615f4e3605750
| 0.566667 | 2.885662 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
twi_master_0.vhd
| 1 | 5,525 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- twi_master_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity twi_master_0 is
port (
addr : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_slave_0.address
wr_en : in std_logic := '0'; -- .write
out_data : out std_logic_vector(15 downto 0); -- .readdata
byte_en : in std_logic_vector(1 downto 0) := (others => '0'); -- .byteenable
in_data : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
in_octet : in std_logic_vector(7 downto 0) := (others => '0'); -- avalon_streaming_sink.data
in_valid : in std_logic := '0'; -- .valid
in_ready : out std_logic; -- .ready
out_octet : out std_logic_vector(7 downto 0); -- avalon_streaming_source.data
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
scl_in : in std_logic := '0'; -- conduit_end.export
scl_act : out std_logic; -- .export
sda_in : in std_logic := '0'; -- .export
sda_act : out std_logic; -- .export
sink_irq : in std_logic := '0'; -- .export
source_irq : in std_logic := '0'; -- .export
irq : out std_logic -- .export
);
end entity twi_master_0;
architecture rtl of twi_master_0 is
component twi_master is
port (
addr : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
wr_en : in std_logic := 'X'; -- write
out_data : out std_logic_vector(15 downto 0); -- readdata
byte_en : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
in_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
in_octet : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
out_octet : out std_logic_vector(7 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
scl_in : in std_logic := 'X'; -- export
scl_act : out std_logic; -- export
sda_in : in std_logic := 'X'; -- export
sda_act : out std_logic; -- export
sink_irq : in std_logic := 'X'; -- export
source_irq : in std_logic := 'X'; -- export
irq : out std_logic -- export
);
end component twi_master;
begin
twi_master_0 : component twi_master
port map (
addr => addr, -- avalon_slave_0.address
wr_en => wr_en, -- .write
out_data => out_data, -- .readdata
byte_en => byte_en, -- .byteenable
in_data => in_data, -- .writedata
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
in_octet => in_octet, -- avalon_streaming_sink.data
in_valid => in_valid, -- .valid
in_ready => in_ready, -- .ready
out_octet => out_octet, -- avalon_streaming_source.data
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
scl_in => scl_in, -- conduit_end.export
scl_act => scl_act, -- .export
sda_in => sda_in, -- .export
sda_act => sda_act, -- .export
sink_irq => sink_irq, -- .export
source_irq => source_irq, -- .export
irq => irq -- .export
);
end architecture rtl; -- of twi_master_0
|
gpl-3.0
|
19e2435e08e14df6c69e8ad2a330f67b
| 0.375023 | 3.983417 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/SPI Interface/Testbenches/SPI_SlaveTransmitterTester.vhd
| 1 | 4,952 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Tests the SPI slave receiver.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Globals.all;
use work.TestTools.all;
entity SPI_SlaveTransmitter_Tester is
end entity;
architecture stdarch of SPI_SlaveTransmitter_Tester is
-- Constants
constant test_delay: time := 1ps;
constant address_width: positive := 2;
constant number_of_data_inputs: positive := 2**address_width;
constant clk_period: time := 20ns; -- 50 MHz system clock
constant sclk_period: time := 91ns; -- about 11 MHz serial clock
-- Inputs
signal clk: std_logic := '0';
signal sclk: std_logic := '1';
signal ss: std_logic :='1';
signal address: unsigned(address_width-1 downto 0) := (others => '0');
signal data_x: data_buffer_vector(number_of_data_inputs-1 downto 0) :=
(others => (others => '0'));
-- Outputs
signal miso: std_logic;
-- Internals
signal deserialized_data: data_buffer := (others => '0');
signal run_test: boolean := true;
-------------------------------------------------------------------------
-- Passes a test value to the transmitter and verifies the data appearing
-- at the transmitter´s serial output.
-------------------------------------------------------------------------
procedure transmit_data_and_check_behaviour(current_address: natural)
is
begin
deserialized_data <= (deserialized_data'range => '0');
-- Set the address and wait for the input data being buffered at the
-- next rising CLK edge.
address <= to_unsigned(current_address, address_width);
wait until rising_edge(clk);
-- Activate the slave select (SS) signal, transmit the test value,
-- and deactivate SS.
ss <= '0';
wait for test_delay;
deserialize_longword(sclk_period, miso, sclk, deserialized_data);
ss <= '1';
-- Check whether the test value has been received.
assert (deserialized_data = data_x(current_address))
report "Data not correctly transmitted." severity error;
end procedure;
begin
--------------------------------------------------------------------------------
-- Instantiate the UUT(s).
--------------------------------------------------------------------------------
uut: entity work.SPI_SlaveTransmitter
generic map
(
address_width => address_width
)
port map
(
clk => clk,
buffer_enable => ss,
sclk => sclk,
ss => ss,
address => address,
data_x => data_x,
miso => miso
);
--------------------------------------------------------------------------------
-- Generate the system clock.
--------------------------------------------------------------------------------
clk <= not clk after clk_period/2 when run_test;
--------------------------------------------------------------------------------
-- Stimulate the UUT.
--------------------------------------------------------------------------------
stimulus: process is
begin
-- Create test value unique for each input.
for i in 0 to number_of_data_inputs-1 loop
data_x(i) <= std_logic_vector(to_unsigned(16 + (i * 2), data_width));
end loop;
wait for test_delay;
-- Transmit several values and check whether they arrive.
for i in 0 to number_of_data_inputs-1 loop
wait for sclk_period; -- for a better readable timing diagram
transmit_data_and_check_behaviour(i);
end loop;
wait for sclk_period; -- for a better readable timing diagram
run_test <= false;
wait;
end process;
end architecture;
|
gpl-3.0
|
237856bcdf4937b3e48262469f4b0be1
| 0.489095 | 5.110423 | false | true | false | false |
stuarthodgson/cocotb
|
examples/mean/hdl/mean.vhd
| 4 | 1,583 |
-------------------------------------------------------------------------------
-- Calculates mean of data input bus
-------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mean_pkg.all;
entity mean is
generic (
BUS_WIDTH : natural := 2);
port (
clk : in std_logic;
rst : in std_logic;
i_valid : in std_logic;
i_data : in t_data_array(0 to BUS_WIDTH-1);
o_valid : out std_logic;
o_data : out t_data
);
end mean;
architecture RTL of mean is
signal s_sum : unsigned(DATA_WIDTH + clog2(BUS_WIDTH-1)-1 downto 0) := (others => '0'); -- introduce bug
-- signal s_sum : unsigned(DATA_WIDTH + clog2(BUS_WIDTH)-1 downto 0) := (others => '0');
signal s_valid : std_logic := '0';
begin
assert BUS_WIDTH = 2**(clog2(BUS_WIDTH))
report LF & " BUS_WIDTH = " & integer'image(BUS_WIDTH) & " , should be a power of 2!"
severity Failure;
process(clk)
variable v_sum : unsigned(s_sum'range);
begin
if rising_edge(clk) then
s_valid <= i_valid;
if i_valid = '1' then
v_sum := (others => '0');
for i in i_data'range loop
v_sum := v_sum + resize(i_data(i), v_sum'length);
end loop;
s_sum <= v_sum;
end if;
if rst = '1' then
s_sum <= (others => '0');
s_valid <= '0';
end if;
end if;
end process;
o_valid <= s_valid;
o_data <= resize(shift_right(s_sum, clog2(BUS_WIDTH)), o_data'length);
end rtl;
|
bsd-3-clause
|
b30128e6b7b781eb9734d4e123ce2be1
| 0.503474 | 3.297917 | false | false | false | false |
Daverball/reconos
|
pcores/reconos_osif_intc_v1_00_a/hdl/vhdl/user_logic.vhd
| 2 | 4,926 |
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - INTC - INTC implementation
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: A simple interrupt controller with variable number of
-- inputs to connect the RECONOS_AXI_FIFO-interrupts to
-- the processor.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity user_logic is
generic (
-- INTC parameters
C_NUM_INTERRUPTS : integer := 1;
-- Bus protocol parameters
C_NUM_REG : integer := 1;
C_SLV_DWIDTH : integer := 32
);
port (
OSIF_INTC_Rst : in std_logic;
OSIF_INTC_in : in std_logic_vector(C_NUM_INTERRUPTS - 1 downto 0);
OSIF_INTC_out : out std_logic;
-- Bus protocol ports
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "Clk";
attribute SIGIS of Bus2IP_Resetn : signal is "Rst";
attribute SIGIS of OSIF_INTC_Rst : signal is "Rst";
attribute SIGIS of OSIF_INTC_in : signal is "Intr_Level_High";
attribute SIGIS of OSIF_INTC_out : signal is "Intr_Level_High";
end entity user_logic;
architecture implementation of user_logic is
-- padding to fill unused interrupts in interrupt_reg
signal pad : std_logic_vector(C_SLV_DWIDTH * C_NUM_REG - C_NUM_INTERRUPTS - 1 downto 0);
signal interrupt_masked : std_logic_vector(C_NUM_INTERRUPTS - 1 downto 0);
signal interrupt_enable : std_logic_vector(C_NUM_INTERRUPTS - 1 downto 0);
signal interrupt_reg : std_logic_vector(C_NUM_REG * 32 - 1 downto 0);
signal interrupt_enable_reg : std_logic_vector(C_NUM_REG * 32 - 1 downto 0);
-- Signals for user logic slave model s/w accessible register example
signal slv_reg_write_sel : std_logic_vector(C_NUM_REG - 1 downto 0);
signal slv_reg_read_sel : std_logic_vector(C_NUM_REG - 1 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal clk : std_logic;
signal rst : std_logic;
begin
clk <= Bus2IP_Clk;
rst <= OSIF_INTC_Rst or not Bus2IP_Resetn;
pad <= (others => '0');
interrupt_enable <= interrupt_enable_reg(C_NUM_INTERRUPTS - 1 downto 0);
interrupt_masked <= OSIF_INTC_in and interrupt_enable;
-- interrupt register only contains enabled interrupts
interrupt_reg <= pad & interrupt_masked;
OSIF_INTC_Out <= or_reduce(interrupt_masked);
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
-- Example code to drive IP to Bus signals
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0');
slv_reg_write_sel <= Bus2IP_WrCE;
slv_reg_read_sel <= Bus2IP_RdCE;
slv_write_ack <= or_reduce(Bus2IP_WrCE);
slv_read_ack <= or_reduce(Bus2IP_RdCE);
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
int_enable_reg_proc : process(clk,rst) is
begin
if rst = '1' then
interrupt_enable_reg <= (others => '0');
elsif rising_edge(clk) then
for i in 0 to C_NUM_REG - 1 loop
if slv_reg_write_sel(C_NUM_REG - 1 - i) = '1' then
interrupt_enable_reg(32 * i + 31 downto 32 * i) <= Bus2IP_Data;
end if;
end loop;
end if;
end process int_enable_reg_proc;
bus_read_reg_proc : process(slv_reg_read_sel) is
begin
for i in 0 to C_NUM_REG - 1 loop
if slv_reg_read_sel(C_NUM_REG - 1 - i) = '1' then
slv_ip2bus_data <= interrupt_reg(32 * i + 31 downto 32 * i);
end if;
end loop;
end process bus_read_reg_proc;
end implementation;
|
gpl-2.0
|
2eed47750e7062dda6aea97d0f721d4d
| 0.578883 | 3.078125 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/DCM_clock/ms_clock.vhd
| 3 | 554 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ms_timer is
Port ( clk : in STD_LOGIC;
clk_1ms : out STD_LOGIC);
end ms_timer;
architecture Behavioral of ms_timer is
signal counter : STD_LOGIC_VECTOR(21 downto 0) := (others =>'0');
begin
clk_process: process(clk)
begin
if rising_edge(clk) then
if counter = ((32000000/1000)-1) then
counter <= (others =>'0');
clk_1ms <= '1';
else
counter <= counter +1;
clk_1ms <= '0';
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
9851d598fa47c568daf40555d83703f0
| 0.629964 | 2.900524 | false | false | false | false |
arthurTemporim/SD_SS
|
pre/7/projetos/projeto1/display.vhd
| 1 | 1,310 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity display is
port (
a : in std_logic_vector (3 downto 0) := "0001"; -- Entrada A.
clk : in std_logic := '0'; -- Clock.
display1 : out std_logic_vector (6 downto 0)
);
end display;
architecture Behavioral of display is
signal bcd : std_logic_vector (6 downto 0); -- BCD.
begin
-- BCD.
process (a, bcd, clk)
begin
if (rising_edge(clk)) then
if (a = "0000") then -- 0
bcd <= "1111110";
elsif (a = "0001") then -- 1
bcd <= "0110000";
elsif (a = "0010") then -- 2
bcd <= "1101101";
elsif (a = "0011") then -- 3
bcd <= "1111001";
elsif (a = "0100") then -- 4
bcd <= "0110010";
elsif (a = "0101") then -- 5
bcd <= "1011010";
elsif (a = "0110") then -- 6
bcd <= "1011111";
elsif (a = "0111") then -- 7
bcd <= "1110000";
elsif (a = "1000") then -- 8
bcd <= "1111111";
elsif (a = "1001") then -- 9
bcd <= "1111011";
elsif (a = "1010") then -- A
bcd <= "1110111";
elsif (a = "1011") then -- B
bcd <= "0011111";
elsif (a = "1100") then -- C
bcd <= "1001110";
elsif (a = "1101") then -- D
bcd <= "0111101";
elsif (a = "1110") then -- E
bcd <= "1001111";
else
bcd <= "1000111"; -- Caso defaul -> 'F'
end if;
end if;
end process;
display1 <= bcd;
end Behavioral;
|
mit
|
f93fd8032b92859ca7403175d322fa23
| 0.538168 | 2.729167 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/VGA1/ipcore_dir/clock_manager/simulation/timing/clock_manager_tb.vhd
| 1 | 6,296 |
-- file: clock_manager_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clock_manager_tb is
end clock_manager_tb;
architecture test of clock_manager_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.25 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component clock_manager_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
report "Timing checks are not valid" severity note;
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19.5);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clock_manager_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
|
gpl-3.0
|
89e3554ee24ac559a62c57379e6453fd
| 0.644695 | 4.268475 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/bd/ip/bd_proc_sys_reset_1_0/sim/bd_proc_sys_reset_1_0.vhd
| 1 | 5,829 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_10;
USE proc_sys_reset_v5_0_10.proc_sys_reset;
ENTITY bd_proc_sys_reset_1_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END bd_proc_sys_reset_1_0;
ARCHITECTURE bd_proc_sys_reset_1_0_arch OF bd_proc_sys_reset_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bd_proc_sys_reset_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "artix7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END bd_proc_sys_reset_1_0_arch;
|
mit
|
195b758646991e828b89f3badd069f6f
| 0.70561 | 3.578269 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/flashyLights/ipcore_dir/memmory/simulation/random.vhd
| 101 | 4,108 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
cebbcbbda391fbbc4d841d9789a20a53
| 0.59445 | 4.711009 | false | false | false | false |
phil91stud/protocol_hdl
|
SPI_master/hdl/loopback_spi.vhd
| 1 | 2,434 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity loopback_spi is
port(
clock_50 : in std_logic;
led : out std_logic_vector(7 downto 0);
sw : in std_logic_vector(1 downto 0);
mosi : out std_logic;
miso : in std_logic;
sclk : out std_logic;
cs_n : out std_logic
);
end entity loopback_spi;
architecture mixed of loopback_spi is
-- component declarations
component spi_master is
generic(
clk_freq : natural := 50000000; -- 50 MHz
spi_freq : natural := 1000000; -- 1 MHz
pre_delay : natural := 10; -- us
post_delay : natural := 10;
wordlength : natural := 16
);
port (
clk : in std_logic;
start_tx : in std_logic;
tx_done : out std_logic;
rx_data : out std_logic_vector(wordlength-1 downto 0);
tx_data : in std_logic_vector(wordlength-1 downto 0);
-- spi mode configuration
cpol : in std_logic;
cpha : in std_logic;
-- spi pins
mosi : out std_logic;
miso : in std_logic;
sclk : out std_logic;
ss : out std_logic -- more cs via demux
);
end component spi_master;
-- signals
signal start_tx : std_logic;
signal tx_done : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
signal tx_data : std_logic_vector(7 downto 0);
signal cpol : std_logic;
signal cpha : std_logic;
type sm_t is (idle, active, done, err);
signal state : sm_t := idle;
signal counter : integer range 0 to 15 := 0;
begin
cpol <= sw(1);
cpha <= sw(0);
i_spi_master:
spi_master
generic map(
clk_freq => 50000000,
spi_freq => 1000000,
pre_delay => 0,
post_delay => 0,
wordlength => 8
)
port map(
clk => clock_50,
start_tx => start_tx,
tx_done => tx_done,
rx_data => rx_data,
tx_data => tx_data,
cpol => cpol,
cpha => cpha,
mosi => mosi,
miso => miso,
sclk => sclk,
ss => cs_n
);
-- TODO
state_machine:
process(clock_50, rx_data,tx_done)
begin
if clock_50'event and clock_50 = '1' then
case(state) is
when idle =>
start_tx <= '0';
tx_data <= X"ae";
counter <= counter + 1;
if counter = 15 then
led <= (others => '0');
state <= active;
end if;
when active =>
start_tx <= '1';
if tx_done = '1' then
state <= done;
end if;
when done =>
start_tx <= '0';
if rx_data = tx_data then
state <= idle;
led <= X"0f";
else
state <= err;
end if;
when err =>
led <= X"01";
state <= idle;
end case;
end if;
end process state_machine;
end architecture mixed;
|
gpl-2.0
|
d92d48c8b1699957f86890099f5c7e4c
| 0.613394 | 2.583864 | false | false | false | false |
arthurbenemann/fpga-bits
|
fm_transmitter/ipcore_dir/pll.vhd
| 1 | 6,401 |
-- file: pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___256.000______0.000______50.0______278.125____150.000
-- CLK_OUT2____32.000______0.000______50.0______200.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
clk_modulator : out std_logic;
clk_32 : out std_logic
);
end pll;
architecture xilinx of pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "pll,clk_wiz_v3_6,{component_name=pll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clk_out2_internal : std_logic;
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 8,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkfb <= clk_out2_internal;
clkout1_buf : BUFG
port map
(O => clk_modulator,
I => clkfx);
clkout2_buf : BUFG
port map
(O => clk_out2_internal,
I => clk0);
clk_32 <= clk_out2_internal;
end xilinx;
|
gpl-3.0
|
33f6c29cc1f2e76d1664b76d17f8d9ee
| 0.572567 | 4.255984 | false | false | false | false |
antlr/grammars-v4
|
vhdl/examples/std_logic_textio.vhd
| 5 | 17,743 |
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value(value'range) := (others => 'U');
good := FALSE;
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value(value'range) := (others => 'U');
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value(value'range) := (others => 'U');
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value(value'range) := (others => 'U');
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out Bit_Vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: bit_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := bv(4*i to 4*i+3);
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: bit_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := bv(3*i to 3*i+2);
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_X01(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end HWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end OWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
end STD_LOGIC_TEXTIO;
|
mit
|
6fdd920b24a1b49ad4c85d32f181e441
| 0.609987 | 2.838426 | false | false | false | false |
Krabby127/ADC
|
adclb/adclb.vhd
| 1 | 13,669 |
-------------------------------------------------------
-- Design Name : adclb
-- File Name : adclb.vhd
-- Function : I2C ADC w/ alarms
-- Author : Michael Eller
-------------------------------------------------------
-- Standard libraries
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity adclb is
port (
reset :in std_logic; -- reset ADC
clk :in std_logic; -- clock
clrb :in std_logic; -- clear interrupt bit
scl :out std_logic; -- I2C clock
sdai :in std_logic; -- data in
sdao :out std_logic; -- data out
sda_oe :out std_logic; -- master control of sda line
min_flag :out std_logic; -- whether the threshold has been met
max_flag :out std_logic; -- whether the threshold has been met
diff_flag :out std_logic; -- whether the threshold has been met
max :out std_logic_vector (7 downto 0); -- max value read from ADC
min :out std_logic_vector (7 downto 0); -- min value read from ADC
value :inout std_logic_vector (7 downto 0) -- data sent back to master
);
end entity;
architecture rtl of adclb is
signal datao :std_logic_vector (7 downto 0); -- data output
signal datai :std_logic_vector (7 downto 0); -- data input
signal amux :std_logic_vector (7 downto 0); -- address selection
signal dmux :std_logic_vector (7 downto 0); -- data selection
signal max_seen :std_logic_vector (7 downto 0); -- maximum value seen so far
signal min_seen :std_logic_vector (7 downto 0); -- minimum value seen so far
signal val :std_logic_vector (7 downto 0); -- internal signal for value read
signal diff :std_logic_vector (8 downto 0); -- difference between min and max
signal count :std_logic_vector (6 downto 0); -- clock counter
signal bit_cnt :std_logic_vector (6 downto 0); -- bit counter
signal init_cnt :std_logic_vector (2 downto 0); -- initialization counter
signal state :std_logic_vector (3 downto 0); -- the current state we're in
signal upd_cnt :std_logic_vector (10 downto 0); -- uptime counter
signal max_i :std_logic; -- internal max flag
signal min_i :std_logic; -- internal min flag
signal diff_i :std_logic; -- internal difference flag
signal count_half:std_logic; -- midway state counter
signal count_end :std_logic; -- state counter
signal sdao_i :std_logic; -- internal data out
signal upd_i :std_logic; -- internal uptime counter finish flag
-- VAR = NUM * (2550Ω/(10000Ω+2550Ω)) / 3.3V * 255
-- actual read value seems to be
-- 50-60 mv high in signle test case
constant MAX_THRESHOLD :integer := 192; -- 12.23 V 0xC0
constant MIN_THRESHOLD :integer := 184; -- 11.72 V 0xB4
constant DIFF_THRESHOLD :integer := 4; -- 0.25 V difference
begin
sdao<=sdao_i;
max<=max_seen;
min<=min_seen;
diff_flag<=diff_i or min_i or max_i;
value<=val;
count_proc: process (clk, reset)
begin
if reset = '1' then
count <= "0000000";
count_end<='0';
count_half<='0';
bit_cnt <= "0000000";
init_cnt <= "000";
sda_oe<='0'; -- disable data output
-- Merely maintaining a large 7 bit counter
-- Counting to 127
elsif clk'event and clk='1' then
count <= count+'1';
if count="0111110" then
count_half<='1';
else
count_half<='0';
end if;
if count="1111110" then
count_end<='1';
-- high every 1280 ns for 1 tick
else
-- only high for one tick
count_end<='0';
end if;
-- Increment to next state
-- state 0101 lives for 1280 ns
-- Initialization timer
if state="0101" and count_end='1' then
if init_cnt="110" then
-- turn off init_cnt
init_cnt<="000";
else
init_cnt<=init_cnt+'1';
end if;
end if;
-- Reset bit_cnt at states 1,5,9,d
-- Intended for only d and 9, but doesn't matter for 1 and 5
if state(1 downto 0)="01" then
bit_cnt<="0000000";
-- Increment bit_cnt if in stage 3 or b
elsif state(1 downto 0)="11" and count_end='1' then
bit_cnt<=bit_cnt+'1';
end if;
-- count_end is the state transition timer
-- count_half means we're in the middle of a state
-- good time to transmit data
if count_half='1' then
if state="1100" and bit_cnt="0011010" then
-- NAK from state 0d12 0hC 0011010
sdao_i<='1'; --NAK
elsif bit_cnt="0011010" then
sdao_i<=sdao_i; --NAK
elsif state(2 downto 0)="000" then
sdao_i<='1'; -- NAK
elsif state(2 downto 0)="101" then
sdao_i<='1'; -- NAK
elsif state="1100" and bit_cnt="0010010" then
sdao_i<='1'; -- NAK; done reading
-- just finished reading 2 bytes
elsif state="1011" and bit_cnt="0010010" then
sdao_i<='0'; -- ACK to receive next byte
elsif bit_cnt="0010010" then
sdao_i<=sdao_i; -- Remain at previous state
elsif state(2 downto 0)="001" then
sdao_i<='0'; -- NAK
else
sdao_i<=datao(7); -- Transfer the data
end if;
end if;
-- count_half marks state change
if count_half='1' then
-- bit_cnt is 8 or 17 or if done with init with bit_cnt at 0x1A 0d26
-- after 1 packet or 3 packets in case of init
-- just finished address byte
if bit_cnt="0001000" then
--(state(3)='1' and bit_cnt="011011") then
-- waiting for slave ACK confirming address
sda_oe<='0';
-- packets 4,5,6,7,8,9,10
-- bit_cnt > 8, /= 17 (redundancy from above), /=45, /=54, /=63, /=72, /=81
-- end of 9-bit packets
-- ony if in active reading/writing (state b/c)
sda_oe<='0';
-- bit_cnt marks number of bits that have already been transmitted
-- when bit_cnt is 8, a full byte has already been processed
elsif state(3)='1' and bit_cnt>"0001000" and bit_cnt/="0010001" and bit_cnt/="0011010" then
-- Allows for slave to drive SDA and ACK
sda_oe<='0';
else
-- Otherwise, bring control to master
-- Corresponding ACK from master after each of 8 bits read
sda_oe<='1';
end if;
end if;
-- toggle sclock high when in states 2,A,4,C
-- keep high when sleeping (state 8) to prepare for start bit
if state(2 downto 0)="010" or state(2 downto 0)="100" then
scl<='0';
else
scl<='1';
end if;
end if;
end process;
state_proc: process (clk, reset)
begin
if reset = '1' then
state <= (others=>'0'); -- set to state 0
elsif clk'event and clk='1' then
-- count_end occurs when count reaches 127
-- 2.56 us
if count_end='1' then
-- if we're still in initialization, increment state
-- states 0,1,2,3
if state(3 downto 2)= "00" then
state <= state+'1';
elsif state = "0100" then -- after reading 27 bits
-- go from state 4 to 5
if bit_cnt="0011011" then -- 0x1B 0d27
state <= "0101"; -- now in state 5
else
state <= "0011"; -- not 27 bits read: go to state 3
end if;
elsif state = "0101" then -- if in state 5 after 2.56 us
if init_cnt="110" then -- once initialization is done, go to state 8
state <= "1000";
else
state <= "0001"; -- otherwise go to state 1
end if;
elsif (state = "1000" and upd_i='1') or
(state(3 downto 2)="10" and state(1 downto 0)/="00") then
-- upd_i time is 2622.72 us
-- if in state 8 after waiting for upd_i time, or in state 9,a,b
-- go to next state
state <= state+'1';
elsif state = "1100" then
-- after reading 27 bits in state c,
-- go to state d
-- change to reading 27 bits for ADC
if bit_cnt="0011010" then
state <= "1101";
else
-- otherwise, go back to reading in state b
state <= "1011";
end if;
elsif state = "1101" then
-- go from d to 8
-- not done reading yet
state <= "1000";
end if;
end if;
end if;
end process;
dio_proc: process
begin
wait until clk'event and clk='1';
if state="1011" and count_half='1' then
-- v Reading the data v
datai<=datai(6 downto 0) & sdai;
-- ^ Reading the data ^
end if;
-- before writes, in state 1 or 9
if state="1001" and count_half='1' then
-- Slave address check
datao<="10100011"; -- chip address, read
-- read from states b or 3 every count_half
elsif state(2 downto 0)="011" and count_half='1' then
-- shift left one bit
datao<=datao(6 downto 0) & '0';
end if;
if reset='1' or clrb='1' then
upd_cnt <= (others=>'0');
elsif state="1000" and count_end='1' and upd_i='0' then
upd_cnt<=upd_cnt+'1';
end if;
if upd_cnt="11111111111" and count_end='1' then
-- upd_cnt maxxed every 1.31072 ms
-- state changes from == 8
upd_i <= '1';
-- upd_i goes high every 3.13216 ms for 1280 ns
elsif count_end='1' then
upd_i <= '0';
end if;
end process;
reg_proc: process(clk, reset)
begin
-- all the reading is done in state b
-- state b, bit_cnt 0d35
if reset='1' then
diff_i<='0';
max_i<='0';
min_i<='0';
diff<="000000000";
max_seen<="00000000";
min_seen<="11111111";
val<="00000000";
elsif clk'event and clk='1' then
if clrb='1' then
diff_i<='0';
max_i<='0';
min_i<='0';
diff<="000000000";
max_seen<="00000000";
min_seen<="11111111";
val<="00000000";
end if;
-- shift first 4 after 16 bits
if state="1011" and bit_cnt="0010000" and count_end='1' then
val(7 downto 4) <= datai(3 downto 0);
end if;
-- shift last 4 after 25 bits
if state="1011" and bit_cnt="0011001" and count_end='1' then
val(3 downto 0) <= datai(7 downto 4);
end if;
if state="1101" and count_end='1' then
if (val>max_seen) then
max_seen<=val;
elsif (val<=max_seen) then
max_seen<=max_seen;
else
max_seen<="00000000";
end if;
-- max_seen<="11111110";
if (val<min_seen) then
min_seen<=val;
elsif (val>=min_seen) then
min_seen<=min_seen;
else
min_seen<="11111111";
end if;
end if;
-- bit_cnt=62 (0x3E)
if state="1000" and count_end='1' then
diff<=('0'&max_seen)-('0'&min_seen);
-- '0'&#### forces unsigned math
else
diff<=diff;
end if;
if state="1000" then
if diff>DIFF_THRESHOLD and (diff(8)/='1') then
diff_i<='1';
else
diff_i<='0';
end if;
if max_seen>MAX_THRESHOLD then
max_i<='1';
else
max_i<='0';
end if;
if min_seen<MIN_THRESHOLD then
min_i<='1';
else
min_i<='0';
end if;
end if;
end if;
end process;
end architecture;
|
apache-2.0
|
5725a82c1d4660582ec559d3d1ba5175
| 0.458657 | 4.421223 | false | false | false | false |
arthurbenemann/fpga-bits
|
fm_transmitter/fm_modulator.vhd
| 1 | 1,303 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.MATH_REAL.ALL;
entity fm_modulator is Port (
clk, clk_modulator : in STD_LOGIC;
data : in signed (8 downto 0);
fm_out : out STD_LOGIC);
end fm_modulator;
architecture Behavioral of fm_modulator is
constant input_clk : real := 256.0; -- MHz
constant accumulator_size : real := 2**32.0;
constant fm_frequency : real := 94.7; -- MHz
constant center_freq : signed(31 downto 0) := to_signed(integer(accumulator_size*fm_frequency/input_clk),32);
component phase_adder port (
clk: in std_logic;
a,b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
end component;
signal ph_shift_data,ph_shift: signed (31 downto 0);
signal sum : std_logic_vector (31 downto 0);
begin
process (clk) begin
if rising_edge(clk) then
ph_shift_data <= resize(data & x"000",32); -- right shift data 12 times so the full range is about +-10000000, which should equal a freq. dev. of +-75kHz
ph_shift <= center_freq + ph_shift_data;
end if;
end process;
fast_adder : phase_adder port map ( -- the adder IP is required to run this sum at 320MHz
clk => clk_modulator,
a => std_logic_vector(ph_shift), b => sum,
s => sum
);
fm_out <= sum(31);
end Behavioral;
|
gpl-3.0
|
3217823be50dbd59bdaa393ef76dd129
| 0.67076 | 3.037296 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/FPGA SigGen/Source/GatedCounter.vhd
| 1 | 6,435 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Provides a simple counter capable of counting a faster pulse signal using a
-- slower gate signal. Uses a freely running counter that is not cleared. When
-- the gate signal is '1', the counter´s value is stored. The measurement value
-- is determined by calculating the difference between the current and the
-- previous counter value. Overflow is detected and signalled.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library Common;
use work.Globals.all;
entity GatedCounter is
generic
(
-- The width of the measured frequency or period value.
counter_width: natural := 32
);
port
(
-- The pulse signal that drives the counter.
pulse_signal: in std_logic;
-- The signal that controls the counter. The rising pulse edges between
-- two consecutive gate '1' signals are counted. Note that the gate signal
-- is level-sensitive, not edge-sensitive.
gate_signal: in std_logic;
-- The measured frequency or period value.
value: out unsigned (counter_width-1 downto 0);
-- '1' if an overflow has occurred in the current measurement period.
overflow: out std_logic
);
end entity;
architecture stdarch of GatedCounter is
type reg_type is record
finished_counter_value, old_finished_counter_value: unsigned (counter_width-1 downto 0);
running_overflow, finished_overflow: std_logic;
end record;
signal state, next_state: reg_type :=
(
finished_counter_value => (others => '0'),
old_finished_counter_value => (others => '0'),
running_overflow => '0',
finished_overflow => '0'
);
signal running_counter_value: unsigned (counter_width-1 downto 0) := (others => '0');
begin
--------------------------------------------------------------------------------
-- Instantiate components.
--------------------------------------------------------------------------------
-- Counts the pulse signal continuously.
counter: entity Common.Counter
generic map
(
width => counter_width
)
port map
(
clk => pulse_signal,
clear => '0',
ce => '1',
value => running_counter_value
);
--------------------------------------------------------------------------------
-- State and data register.
--------------------------------------------------------------------------------
state_register: process is
begin
wait until rising_edge(pulse_signal);
state <= next_state;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state_logic: process(state, running_counter_value, gate_signal) is
begin
-- Defaults.
next_state <= state;
if (gate_signal = '1') then
-- An active ('1') gate signal has been detected. We finish the current
-- measurement cycle and start a new one.
-- Memorize the counter value and overflow status.
next_state.finished_counter_value <= running_counter_value;
next_state.old_finished_counter_value <= state.finished_counter_value;
next_state.finished_overflow <= state.running_overflow;
if (running_counter_value = state.finished_counter_value) then
-- There was an overflow at the very end of the measurement cycle(i.e. the counter
-- has wrapped around and reached the same value again). Set the finished counter
-- value´s overflow marker directly.
next_state.finished_overflow <= '1';
else
-- There was no overflow at the very end of the measurement cycle, we just keep
-- the overflows that have happened so far.
next_state.finished_overflow <= state.running_overflow;
end if;
-- Reset the running counter value´s overflow marker as we start a new measurement
-- cycle.
next_state.running_overflow <= '0';
elsif (running_counter_value = state.finished_counter_value) then
-- We´re not at the end of a measurement cycle but there was an overflow (i.e. the counter
-- has wrapped around and reached the same value again). This might occur even multiple
-- times per gate signal period, we capture the first occurrence.
next_state.running_overflow <= '1';
end if;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
-- Calculate the number of pulse cycles between the last and the last but one
-- active gate signal. This works even if the freely running counter wraps around
-- as long as the last value stays below the last but one value.
value <= state.finished_counter_value - state.old_finished_counter_value;
overflow <= state.finished_overflow;
end architecture;
|
gpl-3.0
|
ee83451652189b124c29358f4eb4d0b9
| 0.52805 | 5.287592 | false | false | false | false |
arthurbenemann/fpga-bits
|
mandelbrot/tb_top.vhd
| 1 | 3,290 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:22:43 02/25/2016
-- Design Name:
-- Module Name: C:/Users/Arthur/Documents/GitHub/fpga-bits/mandelbrot_monochromatic/tb_top.vhd
-- Project Name: mandelbrot_monochromatic
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: mandel_mono
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_top IS
END tb_top;
ARCHITECTURE behavior OF tb_top IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mandel_mono
PORT(
CLK : IN std_logic;
SW : IN std_logic_vector(7 downto 0);
DIR_UP : IN std_logic;
DIR_DOWN : IN std_logic;
DIR_LEFT : IN std_logic;
DIR_RIGHT : IN std_logic;
VGA_RED : OUT std_logic_vector(3 downto 0);
VGA_GREEN : OUT std_logic_vector(3 downto 0);
VGA_BLUE : OUT std_logic_vector(3 downto 0);
VGA_VSYNC : OUT std_logic;
VGA_HSYNC : OUT std_logic;
LED : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal SW : std_logic_vector(7 downto 0) := (others => '0');
signal DIR_UP : std_logic := '0';
signal DIR_DOWN : std_logic := '0';
signal DIR_LEFT : std_logic := '0';
signal DIR_RIGHT : std_logic := '0';
--Outputs
signal VGA_RED : std_logic_vector(3 downto 0);
signal VGA_GREEN : std_logic_vector(3 downto 0);
signal VGA_BLUE : std_logic_vector(3 downto 0);
signal VGA_VSYNC : std_logic;
signal VGA_HSYNC : std_logic;
signal LED : std_logic_vector(7 downto 0);
-- Clock period definitions
constant CLK_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mandel_mono PORT MAP (
CLK => CLK,
SW => SW,
DIR_UP => DIR_UP,
DIR_DOWN => DIR_DOWN,
DIR_LEFT => DIR_LEFT,
DIR_RIGHT => DIR_RIGHT,
VGA_RED => VGA_RED,
VGA_GREEN => VGA_GREEN,
VGA_BLUE => VGA_BLUE,
VGA_VSYNC => VGA_VSYNC,
VGA_HSYNC => VGA_HSYNC,
LED => LED
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
bf3c3bcb0104d7663f482023f190c49f
| 0.579331 | 3.709132 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/koc/koc_lock.vhd
| 1 | 7,568 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.plasoc_gpio_pack.all;
entity koc_lock is
generic (
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width.
axi_control_offset : integer := 0; --! Defines the offset for the Control register.
control_default : integer := 1
);
port (
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic;
-- Slave AXI4-Lite Write interface.
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal.
axi_awready : out std_logic; --! AXI4-Lite Address Write signal.
axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal.
axi_wready : out std_logic; --! AXI4-Lite Write Data signal.
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal.
axi_bready : in std_logic; --! AXI4-Lite Write Response signal.
axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
-- Slave AXI4-Lite Read interface.
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal.
axi_arready : out std_logic; --! AXI4-Lite Address Read signal.
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal.
axi_rready : in std_logic; --! AXI4-Lite Read Data signal.
axi_rresp : out std_logic_vector(1 downto 0)
);
end koc_lock;
architecture Behavioral of koc_lock is
component koc_lock_axi4_write_cntrl is
generic (
axi_address_width : integer := 16;
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000";
reg_control_default : std_logic_vector := X"00000001"
);
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_awprot : in std_logic_vector(2 downto 0);
axi_awvalid : in std_logic;
axi_awready : out std_logic;
axi_wvalid : in std_logic;
axi_wready : out std_logic;
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
axi_bvalid : out std_logic;
axi_bready : in std_logic;
axi_bresp : out std_logic_vector(1 downto 0);
reg_control : out std_logic_vector(axi_data_width-1 downto 0)
);
end component;
component koc_lock_axi4_read_cntrl is
generic (
axi_address_width : integer := 16;
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000"
);
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal.
axi_arready : out std_logic; --! AXI4-Lite Address Read signal.
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal.
axi_rready : in std_logic; --! AXI4-Lite Read Data signal.
axi_rresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Read Data signal.
reg_control : in std_logic_vector(axi_data_width-1 downto 0)
);
end component;
constant axi_control_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_control_offset,axi_address_width));
constant control_default_slv : std_logic_vector := std_logic_vector(to_unsigned(control_default,axi_data_width));
signal reg_control : std_logic_vector(axi_data_width-1 downto 0);
begin
koc_lock_axi4_write_cntrl_inst : koc_lock_axi4_write_cntrl
generic map (
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
reg_control_offset => axi_control_offset_slv,
reg_control_default => control_default_slv)
port map (
aclk => aclk,
aresetn => aresetn,
axi_awaddr => axi_awaddr,
axi_awprot => axi_awprot,
axi_awvalid => axi_awvalid,
axi_awready => axi_awready,
axi_wvalid => axi_wvalid,
axi_wready => axi_wready,
axi_wdata => axi_wdata,
axi_wstrb => axi_wstrb,
axi_bvalid => axi_bvalid,
axi_bready => axi_bready,
axi_bresp => axi_bresp,
reg_control => reg_control);
koc_lock_axi4_read_cntrl_inst : koc_lock_axi4_read_cntrl
generic map (
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
reg_control_offset => axi_control_offset_slv)
port map (
aclk => aclk,
aresetn => aresetn,
axi_araddr => axi_araddr,
axi_arprot => axi_arprot,
axi_arvalid => axi_arvalid,
axi_arready => axi_arready,
axi_rdata => axi_rdata,
axi_rvalid => axi_rvalid,
axi_rready => axi_rready,
axi_rresp => axi_rresp,
reg_control => reg_control);
end Behavioral;
|
mit
|
7709dce88480ccc56a2dea98b639a5c5
| 0.486126 | 4.425731 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/SRAM_Controller/Source/ClockManager.vhd
| 2 | 3,169 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Manages the clocks used throughout the system.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ClockManager is
port
(
-- The system clock.
clk: in std_logic;
-- The 50 MHz clock.
clk_50mhz: out std_logic;
-- The 100 MHz clock.
clk_100mhz: out std_logic
);
end entity;
architecture stdarch of ClockManager is
signal clk50_unbuf, clk50_buf: std_logic;
signal clk100_unbuf, clk100_buf: std_logic;
begin
--------------------------------------------------------------------------------
-- Connections to and from internal signals.
--------------------------------------------------------------------------------
clk_50mhz <= clk;
clk_100mhz <= clk100_buf;
--------------------------------------------------------------------------------
-- Instantiate components.
--------------------------------------------------------------------------------
dcm_instance: DCM
generic map
(
CLKIN_PERIOD => 20.0,
-- DLL attributes
CLK_FEEDBACK => "1X",
DLL_FREQUENCY_MODE => "LOW",
CLKIN_DIVIDE_BY_2 => FALSE,
CLKDV_DIVIDE => 2.0,
DUTY_CYCLE_CORRECTION => TRUE,
-- DFS attributes
DFS_FREQUENCY_MODE => "LOW",
CLKFX_MULTIPLY => 2,
CLKFX_DIVIDE => 1
)
port map
(
RST => '0',
CLKIN => clk,
CLKFB => clk50_buf,
PSEN => '0',
PSCLK => '0',
PSINCDEC => '0',
CLK0 => clk50_unbuf,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKDV => open,
CLKFX => clk100_unbuf,
CLKFX180 => open,
LOCKED => open,
STATUS => open,
PSDONE => open
);
clk50_bufg: BUFG
port map
(
I => clk50_unbuf,
O => clk50_buf
);
clk100_bufg: BUFG
port map
(
I => clk100_unbuf,
O => clk100_buf
);
end architecture;
|
gpl-3.0
|
728ebdff56f65f492b8a48688493744e
| 0.451562 | 4.794251 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
gpout_0.vhd
| 1 | 2,499 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- gpout_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity gpout_0 is
port (
address : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_slave_0.address
byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .byteenable
writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
write : in std_logic := '0'; -- .write
readdata : out std_logic_vector(15 downto 0); -- .readdata
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
pins : out std_logic_vector(15 downto 0) -- conduit_end.export
);
end entity gpout_0;
architecture rtl of gpout_0 is
component gpout is
generic (
POLARITY_MASK : natural := 0
);
port (
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(15 downto 0); -- readdata
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
pins : out std_logic_vector(15 downto 0) -- export
);
end component gpout;
begin
gpout_0 : component gpout
generic map (
POLARITY_MASK => 0
)
port map (
address => address, -- avalon_slave_0.address
byteenable => byteenable, -- .byteenable
writedata => writedata, -- .writedata
write => write, -- .write
readdata => readdata, -- .readdata
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
pins => pins -- conduit_end.export
);
end architecture rtl; -- of gpout_0
|
gpl-3.0
|
128843b42b28f886d80b4b6aeed7bf12
| 0.492997 | 3.642857 | false | false | false | false |
phil91stud/protocol_hdl
|
SPI_master/hdl/system_top.vhd
| 1 | 1,847 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity system_top is
port(
clock_50 : in std_logic;
rxdata : out std_logic_vector(7 downto 0);
done : out std_logic;
start : in std_logic;
mosi : out std_logic; -- mosi
miso : in std_logic; -- miso
csn : out std_logic; -- csn
sclk : out std_logic -- sclk
);
end entity system_top;
architecture wrapper of system_top is
-- component declaration
component spi_master
generic(
clk_freq : natural := 50000000; -- 50 MHz
spi_freq : natural := 10000000; -- 1 MHz
pre_delay : natural := 10; -- us
post_delay : natural := 10;
wordlength : natural := 16
);
port (
clk : in std_logic;
start_tx : in std_logic;
tx_done : out std_logic;
rx_data : out std_logic_vector(wordlength-1 downto 0);
tx_data : in std_logic_vector(wordlength-1 downto 0);
-- spi mode configuration
cpol : in std_logic;
cpha : in std_logic;
-- spi pins
mosi : out std_logic;
miso : in std_logic;
sclk : out std_logic;
ss : out std_logic -- more cs via demux
);
end component spi_master;
constant cpha : std_logic := '0';
constant cpol : std_logic := '1';
constant txdata : std_logic_vector(7 downto 0) := X"ae";
--signal rxdata : std_logic_vector(7 downto 0);
--signal start : std_logic;
signal gpio0 : std_logic_vector(3 downto 0);
begin
mosi <= gpio0(0);
gpio0(1) <= miso;
csn <= gpio0(2);
sclk <= gpio0(3);
i_spi_master:
spi_master
generic map(
clk_freq => 50000000,
spi_freq => 10000000,
pre_delay => 0,
post_delay => 0,
wordlength => 8
)
port map(
clk => clock_50,
start_tx => start,
tx_done => done,
rx_data => rxdata,
tx_data => txdata,
cpol => cpol,
cpha => cpha,
mosi => gpio0(0),
miso => gpio0(1),
ss => gpio0(2),
sclk => gpio0(3)
);
end architecture wrapper;
|
gpl-2.0
|
383e80fde53dcc39306da1aab0d664df
| 0.621007 | 2.634807 | false | false | false | false |
antlr/grammars-v4
|
vhdl/examples/std_logic_1164_body.vhd
| 7 | 34,613 |
-- --------------------------------------------------------------------
--
-- Title : std_logic_1164 multi-value logic system
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (par 1164)
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : std_logic_1164. The std_logic_1164 package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- version | mod. date:|
-- v4.200 | 01/02/91 |
-- --------------------------------------------------------------------
PACKAGE BODY std_logic_1164 IS
-------------------------------------------------------------------
-- local types
-------------------------------------------------------------------
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := 'Z'; -- weakest state default
BEGIN
-- the test for a single driver is essential otherwise the
-- loop would return 'X' for a single driver of '-' and that
-- would conflict with the value of a single driver unresolved
-- signal.
IF (s'LENGTH = 1) THEN RETURN s(s'LOW);
ELSE
FOR i IN s'RANGE LOOP
result := resolution_table(result, s(i));
END LOOP;
END IF;
RETURN result;
END resolved;
-------------------------------------------------------------------
-- tables for logical operations
-------------------------------------------------------------------
-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - |
);
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | - |
);
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
-- truth table for "not" function
CONSTANT not_table: stdlogic_1d :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H - |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
-------------------------------------------------------------------
-- overloaded logical operators ( with optimizing hints )
-------------------------------------------------------------------
FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (and_table(l, r));
END "and";
FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table ( and_table(l, r)));
END "nand";
FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (or_table(l, r));
END "or";
FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table ( or_table( l, r )));
END "nor";
FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (xor_table(l, r));
END "xor";
--START-V93
FUNCTION "xnor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN not_table(xor_table(l, r));
END "xnor";
--END-V93
FUNCTION "not" ( l : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table(l));
END "not";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
FUNCTION "and" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'and' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := and_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "and";
---------------------------------------------------------------------
FUNCTION "and" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'and' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := and_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
FUNCTION "nand" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nand' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(and_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nand";
---------------------------------------------------------------------
FUNCTION "nand" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nand' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(and_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
FUNCTION "or" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'or' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := or_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "or";
---------------------------------------------------------------------
FUNCTION "or" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'or' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := or_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
FUNCTION "nor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(or_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nor";
---------------------------------------------------------------------
FUNCTION "nor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(or_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nor";
---------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
FUNCTION "xor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := xor_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "xor";
---------------------------------------------------------------------
FUNCTION "xor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := xor_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "xor";
-- -------------------------------------------------------------------
-- -- xnor
-- -------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- Note : The declaration and implementation of the "xnor" function is
-- specifically commented until at which time the VHDL language has been
-- officially adopted as containing such a function. At such a point,
-- the following comments may be removed along with this notice without
-- further "official" ballotting of this std_logic_1164 package. It is
-- the intent of this effort to provide such a function once it becomes
-- available in the VHDL standard.
-- -----------------------------------------------------------------------
--START-V93
FUNCTION "xnor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xnor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(xor_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "xnor";
---------------------------------------------------------------------
FUNCTION "xnor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xnor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(xor_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "xnor";
--END-V93
-------------------------------------------------------------------
-- not
-------------------------------------------------------------------
FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
BEGIN
FOR i IN result'RANGE LOOP
result(i) := not_table( lv(i) );
END LOOP;
RETURN result;
END;
---------------------------------------------------------------------
FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
BEGIN
FOR i IN result'RANGE LOOP
result(i) := not_table( lv(i) );
END LOOP;
RETURN result;
END;
-------------------------------------------------------------------
-- conversion tables
-------------------------------------------------------------------
TYPE logic_x01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01;
TYPE logic_x01z_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01Z;
TYPE logic_ux01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF UX01;
----------------------------------------------------------
-- table name : cvt_to_x01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_x01 : logic_x01_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_x01z
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01z -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01z (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_x01z : logic_x01z_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'Z', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_ux01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : ux01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_ux01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_ux01 : logic_ux01_table := (
'U', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT IS
BEGIN
CASE s IS
WHEN '0' | 'L' => RETURN ('0');
WHEN '1' | 'H' => RETURN ('1');
WHEN OTHERS => RETURN xmap;
END CASE;
END;
--------------------------------------------------------------------
FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR IS
ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE sv(i) IS
WHEN '0' | 'L' => result(i) := '0';
WHEN '1' | 'H' => result(i) := '1';
WHEN OTHERS => result(i) := xmap;
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR IS
ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE sv(i) IS
WHEN '0' | 'L' => result(i) := '0';
WHEN '1' | 'H' => result(i) := '1';
WHEN OTHERS => result(i) := xmap;
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic IS
BEGIN
CASE b IS
WHEN '0' => RETURN '0';
WHEN '1' => RETURN '1';
END CASE;
END;
--------------------------------------------------------------------
FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
VARIABLE result : std_logic_vector ( b'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : std_logic_vector ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := sv(i);
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
VARIABLE result : std_ulogic_vector ( b'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := sv(i);
END LOOP;
RETURN result;
END;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
-- to_x01
-------------------------------------------------------------------
FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( s : std_ulogic ) RETURN X01 IS
BEGIN
RETURN (cvt_to_x01(s));
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT ) RETURN X01 IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
--------------------------------------------------------------------
-- to_x01z
-------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01z (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01z (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z IS
BEGIN
RETURN (cvt_to_x01z(s));
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT ) RETURN X01Z IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
--------------------------------------------------------------------
-- to_ux01
-------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_ux01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_ux01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (cvt_to_ux01(s));
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT ) RETURN UX01 IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND (To_X01(s) = '1') AND
(To_X01(s'LAST_VALUE) = '0'));
END;
FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND (To_X01(s) = '0') AND
(To_X01(s'LAST_VALUE) = '1'));
END;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN IS
BEGIN
FOR i IN s'RANGE LOOP
CASE s(i) IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
END LOOP;
RETURN FALSE;
END;
--------------------------------------------------------------------
FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN IS
BEGIN
FOR i IN s'RANGE LOOP
CASE s(i) IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
END LOOP;
RETURN FALSE;
END;
--------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN IS
BEGIN
CASE s IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
RETURN FALSE;
END;
END std_logic_1164;
|
mit
|
e382db4572d721054780312d4f1c3c90
| 0.387282 | 4.173258 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
testbench/ci_control_tb.vhd
| 1 | 5,545 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.avblabs_common_pkg.all;
entity ci_control_tb is
end;
architecture sym of ci_control_tb is
signal rst : std_logic := '1';
signal clk : std_logic := '0';
signal soft_reset : std_logic := '0';
signal stschg_ack : std_logic := '0';
signal ci_timeout : std_logic := '0';
signal ci_cd_n : std_logic_vector(1 downto 0) := "11";
signal ci_reset : std_logic;
signal ci_reset_oe_n : std_logic;
signal ci_overcurrent_n : std_logic := '1';
signal ci_ireq_n : std_logic := '1';
signal cam_stat_changed : std_logic;
signal cam_stat_present : std_logic;
signal cam_stat_reset : std_logic;
signal cam_stat_ready : std_logic;
signal cam_stat_error : std_logic;
signal cam_stat_ovcp : std_logic;
signal cam_stat_busy : std_logic;
signal cam_interrupt : std_logic;
signal cam_reset : std_logic;
begin
cam_reset <= 'Z' when ci_reset_oe_n else ci_reset;
CI_CTRL_0 : entity work.ci_control
generic map (
t_h => 18750,
t_w => 1250,
t_su => 6250
)
port map (
clk => clk,
rst => rst,
--
soft_reset => soft_reset,
stschg_ack => stschg_ack,
ci_timeout => ci_timeout,
ci_cd_n => ci_cd_n,
ci_reset => ci_reset,
ci_reset_oe_n => ci_reset_oe_n,
ci_overcurrent_n => ci_overcurrent_n,
ci_ireq_n => ci_ireq_n,
cam_stschg => cam_stat_changed,
cam_present => cam_stat_present,
cam_reset => cam_stat_reset,
cam_ready => cam_stat_ready,
cam_error => cam_stat_error,
cam_ovcp => cam_stat_ovcp,
cam_busy => cam_stat_busy,
cam_interrupt => cam_interrupt
);
process
begin
wait for 8 ns;
clk <= not clk;
end process;
process
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
rst <= '0';
wait for 5 us;
--
report "CAM inserted";
ci_cd_n <= "00";
wait for 100 us;
ci_ireq_n <= '0';
wait for 380 us;
ci_ireq_n <= '1';
wait until rising_edge(clk) and cam_stat_changed = '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
stschg_ack <= '1';
wait until rising_edge(clk);
stschg_ack <= '0';
wait until rising_edge(clk);
--
wait for 100 us;
--
report "CAM removed";
ci_cd_n <= "11";
wait until rising_edge(clk) and cam_stat_changed = '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
stschg_ack <= '1';
wait until rising_edge(clk);
stschg_ack <= '0';
wait until rising_edge(clk);
--
wait for 200 us;
--
report "CAM inserted";
ci_cd_n <= "00";
wait for 100 us;
ci_ireq_n <= '0';
wait for 380 us;
ci_ireq_n <= '1';
wait until rising_edge(clk) and cam_stat_changed = '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
stschg_ack <= '1';
wait until rising_edge(clk);
stschg_ack <= '0';
wait until rising_edge(clk);
--
wait for 50 us;
--
report "Soft reset";
wait until rising_edge(clk);
soft_reset <= '1';
wait until rising_edge(clk);
soft_reset <= '0';
wait until rising_edge(clk) and cam_stat_changed = '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
stschg_ack <= '1';
wait until rising_edge(clk);
stschg_ack <= '0';
wait until rising_edge(clk);
--
wait for 50 us;
--
report "Overcurrent";
ci_overcurrent_n <= '0';
wait until rising_edge(clk) and cam_stat_changed = '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
stschg_ack <= '1';
wait until rising_edge(clk);
stschg_ack <= '0';
wait until rising_edge(clk);
--
wait for 50 us;
--
report "Soft reset";
wait until rising_edge(clk);
soft_reset <= '1';
wait until rising_edge(clk);
soft_reset <= '0';
wait until rising_edge(clk) and cam_stat_changed = '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
stschg_ack <= '1';
wait until rising_edge(clk);
stschg_ack <= '0';
wait until rising_edge(clk);
--
wait for 50 us;
--
report "CAM removed";
ci_cd_n <= "11";
wait until rising_edge(clk) and cam_stat_changed = '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
stschg_ack <= '1';
wait until rising_edge(clk);
stschg_ack <= '0';
wait until rising_edge(clk);
--
wait for 50 us;
ci_overcurrent_n <= '1';
--
report "CAM inserted";
ci_cd_n <= "00";
wait for 100 us;
ci_ireq_n <= '0';
wait for 380 us;
ci_ireq_n <= '1';
wait until rising_edge(clk) and cam_stat_changed = '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
stschg_ack <= '1';
wait until rising_edge(clk);
stschg_ack <= '0';
wait until rising_edge(clk);
--
wait for 50 us;
--
report "CAM timeout";
wait until rising_edge(clk);
ci_timeout <= '1';
wait until rising_edge(clk);
ci_timeout <= '0';
wait until rising_edge(clk) and cam_stat_changed = '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
stschg_ack <= '1';
wait until rising_edge(clk);
stschg_ack <= '0';
wait until rising_edge(clk);
--
wait for 50 us;
--
report "Soft reset";
wait until rising_edge(clk);
soft_reset <= '1';
wait until rising_edge(clk);
soft_reset <= '0';
wait until rising_edge(clk) and cam_stat_changed = '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
stschg_ack <= '1';
wait until rising_edge(clk);
stschg_ack <= '0';
wait until rising_edge(clk);
--
wait;
end process;
end;
|
gpl-3.0
|
586910d49fa5bf87d79ea71fb942d982
| 0.621461 | 2.62051 | false | false | false | false |
rinatzakirov/vhdl
|
stream_to_avalon_tb.vhd
| 1 | 3,127 |
use work.all;
use work.util.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
USE IEEE.math_real.ALL;
use work.testbench_mm_master_pkg.all;
entity stream_to_avalon_tb is
end entity;
architecture sim of stream_to_avalon_tb is
signal stream_valid : std_logic ;
signal stream_ready : std_logic ;
signal stream_data : std_logic_vector(15 downto 0);
signal ctl_write: std_logic;
signal ctl_read: std_logic;
signal ctl_address: std_logic_vector(31 downto 0);
signal ctl_writedata: std_logic_vector(31 downto 0);
signal ctl_readdata: std_logic_vector(31 downto 0);
signal ctl_waitrequest: std_logic;
signal ctl_readdatavalid: std_logic;
signal writer_write: std_logic;
signal writer_waitrequest: std_logic;
signal writer_address: std_logic_vector(31 downto 0);
signal writer_burstcount: std_logic_vector(9 downto 0);
signal writer_writedata: std_logic_vector(127 downto 0);
signal clk, rst: std_logic;
signal rnd: real;
begin
clock: entity work.clock_gen
port map
(
clk => clk ,
rst => rst ,
rnd => rnd
);
source: entity work.random_stream_source
generic map (speed => 0.1, bw => 16, incrementing => true)
port map
(
clk => clk ,
rst => rst ,
out_valid => stream_valid ,
out_ready => stream_ready ,
out_data => stream_data
);
writer_waitrequest <= '1' when rnd > 0.01 else '0';
dut: entity work.stream_to_avalon
port map
(
stream_clk => clk ,
stream_rst => rst ,
stream_data => stream_data ,
stream_valid => stream_valid ,
stream_ready => stream_ready ,
clk => clk,
rst => rst,
ctl_write => ctl_write ,
ctl_read => ctl_read ,
ctl_address => ctl_address(3 downto 0) ,
ctl_writedata => ctl_writedata ,
ctl_readdata => ctl_readdata ,
ctl_waitrequest => ctl_waitrequest ,
ctl_readdatavalid => ctl_readdatavalid ,
writer_write => writer_write ,
writer_waitrequest => writer_waitrequest ,
writer_address => writer_address ,
writer_burstcount => writer_burstcount ,
writer_writedata => writer_writedata
);
tb_sm: entity work.testbench_mm_master generic map (instructions => (
(do_write, 1, 1024),
(do_write, 2, 8192),
(do_write, 0, 1),
(do_write, 0, 2),
(do_write, 0, 0),
(do_idle, 0, 0)
)) port map
(
clk => clk,
rst => rst,
mm_write => ctl_write ,
mm_waitrequest => ctl_waitrequest ,
mm_address => ctl_address ,
mm_writedata => ctl_writedata
);
ctl_read <= '0';
end architecture;
|
lgpl-2.1
|
48becf47372b991f01d104949973edf9
| 0.522546 | 3.841523 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/boot_pack.vhd
| 1 | 23,041 |
library ieee;
use ieee.std_logic_1164.all;
package boot_pack is
constant cpu_width : integer := 32;
constant ram_size : integer := 667;
subtype word_type is std_logic_vector(cpu_width-1 downto 0);
type ram_type is array(0 to ram_size-1) of word_type;
function load_hex return ram_type;
end package;
package body boot_pack is
function load_hex return ram_type is
variable ram_buffer : ram_type := (others=>(others=>'0'));
begin
ram_buffer(0) := X"3C1C0001";
ram_buffer(1) := X"279C8A60";
ram_buffer(2) := X"3C1D0000";
ram_buffer(3) := X"27BD0A98";
ram_buffer(4) := X"0C0001BC";
ram_buffer(5) := X"00000000";
ram_buffer(6) := X"00000000";
ram_buffer(7) := X"00000000";
ram_buffer(8) := X"00000000";
ram_buffer(9) := X"00000000";
ram_buffer(10) := X"00000000";
ram_buffer(11) := X"00000000";
ram_buffer(12) := X"00000000";
ram_buffer(13) := X"00000000";
ram_buffer(14) := X"00000000";
ram_buffer(15) := X"23BDFF98";
ram_buffer(16) := X"AFA10010";
ram_buffer(17) := X"AFA20014";
ram_buffer(18) := X"AFA30018";
ram_buffer(19) := X"AFA4001C";
ram_buffer(20) := X"AFA50020";
ram_buffer(21) := X"AFA60024";
ram_buffer(22) := X"AFA70028";
ram_buffer(23) := X"AFA8002C";
ram_buffer(24) := X"AFA90030";
ram_buffer(25) := X"AFAA0034";
ram_buffer(26) := X"AFAB0038";
ram_buffer(27) := X"AFAC003C";
ram_buffer(28) := X"AFAD0040";
ram_buffer(29) := X"AFAE0044";
ram_buffer(30) := X"AFAF0048";
ram_buffer(31) := X"AFB8004C";
ram_buffer(32) := X"AFB90050";
ram_buffer(33) := X"AFBF0054";
ram_buffer(34) := X"401A7000";
ram_buffer(35) := X"235AFFFC";
ram_buffer(36) := X"AFBA0058";
ram_buffer(37) := X"0000D810";
ram_buffer(38) := X"AFBB005C";
ram_buffer(39) := X"0000D812";
ram_buffer(40) := X"AFBB0060";
ram_buffer(41) := X"0C000194";
ram_buffer(42) := X"23A50000";
ram_buffer(43) := X"8FA10010";
ram_buffer(44) := X"8FA20014";
ram_buffer(45) := X"8FA30018";
ram_buffer(46) := X"8FA4001C";
ram_buffer(47) := X"8FA50020";
ram_buffer(48) := X"8FA60024";
ram_buffer(49) := X"8FA70028";
ram_buffer(50) := X"8FA8002C";
ram_buffer(51) := X"8FA90030";
ram_buffer(52) := X"8FAA0034";
ram_buffer(53) := X"8FAB0038";
ram_buffer(54) := X"8FAC003C";
ram_buffer(55) := X"8FAD0040";
ram_buffer(56) := X"8FAE0044";
ram_buffer(57) := X"8FAF0048";
ram_buffer(58) := X"8FB8004C";
ram_buffer(59) := X"8FB90050";
ram_buffer(60) := X"8FBF0054";
ram_buffer(61) := X"8FBA0058";
ram_buffer(62) := X"8FBB005C";
ram_buffer(63) := X"03600011";
ram_buffer(64) := X"8FBB0060";
ram_buffer(65) := X"03600013";
ram_buffer(66) := X"23BD0068";
ram_buffer(67) := X"341B0001";
ram_buffer(68) := X"03400008";
ram_buffer(69) := X"409B6000";
ram_buffer(70) := X"40026000";
ram_buffer(71) := X"03E00008";
ram_buffer(72) := X"40846000";
ram_buffer(73) := X"3C050000";
ram_buffer(74) := X"24A50150";
ram_buffer(75) := X"8CA60000";
ram_buffer(76) := X"AC06003C";
ram_buffer(77) := X"8CA60004";
ram_buffer(78) := X"AC060040";
ram_buffer(79) := X"8CA60008";
ram_buffer(80) := X"AC060044";
ram_buffer(81) := X"8CA6000C";
ram_buffer(82) := X"03E00008";
ram_buffer(83) := X"AC060048";
ram_buffer(84) := X"3C1A0000";
ram_buffer(85) := X"375A003C";
ram_buffer(86) := X"03400008";
ram_buffer(87) := X"00000000";
ram_buffer(88) := X"00850019";
ram_buffer(89) := X"00001012";
ram_buffer(90) := X"00002010";
ram_buffer(91) := X"03E00008";
ram_buffer(92) := X"ACC40000";
ram_buffer(93) := X"0000000C";
ram_buffer(94) := X"03E00008";
ram_buffer(95) := X"00000000";
ram_buffer(96) := X"AC900000";
ram_buffer(97) := X"AC910004";
ram_buffer(98) := X"AC920008";
ram_buffer(99) := X"AC93000C";
ram_buffer(100) := X"AC940010";
ram_buffer(101) := X"AC950014";
ram_buffer(102) := X"AC960018";
ram_buffer(103) := X"AC97001C";
ram_buffer(104) := X"AC9E0020";
ram_buffer(105) := X"AC9C0024";
ram_buffer(106) := X"AC9D0028";
ram_buffer(107) := X"AC9F002C";
ram_buffer(108) := X"03E00008";
ram_buffer(109) := X"34020000";
ram_buffer(110) := X"8C900000";
ram_buffer(111) := X"8C910004";
ram_buffer(112) := X"8C920008";
ram_buffer(113) := X"8C93000C";
ram_buffer(114) := X"8C940010";
ram_buffer(115) := X"8C950014";
ram_buffer(116) := X"8C960018";
ram_buffer(117) := X"8C97001C";
ram_buffer(118) := X"8C9E0020";
ram_buffer(119) := X"8C9C0024";
ram_buffer(120) := X"8C9D0028";
ram_buffer(121) := X"8C9F002C";
ram_buffer(122) := X"03E00008";
ram_buffer(123) := X"34A20000";
ram_buffer(124) := X"27BDFFC0";
ram_buffer(125) := X"AFBF003C";
ram_buffer(126) := X"AFB70034";
ram_buffer(127) := X"AFB5002C";
ram_buffer(128) := X"AFB1001C";
ram_buffer(129) := X"AFB00018";
ram_buffer(130) := X"AFBE0038";
ram_buffer(131) := X"AFB60030";
ram_buffer(132) := X"AFB40028";
ram_buffer(133) := X"AFB30024";
ram_buffer(134) := X"AFB20020";
ram_buffer(135) := X"0C000109";
ram_buffer(136) := X"3C15F0F0";
ram_buffer(137) := X"3C100000";
ram_buffer(138) := X"24040001";
ram_buffer(139) := X"0C000186";
ram_buffer(140) := X"3C110000";
ram_buffer(141) := X"36B5F0F0";
ram_buffer(142) := X"24170003";
ram_buffer(143) := X"26100988";
ram_buffer(144) := X"26310354";
ram_buffer(145) := X"0C000177";
ram_buffer(146) := X"00000000";
ram_buffer(147) := X"1455FFFD";
ram_buffer(148) := X"00000000";
ram_buffer(149) := X"0C000149";
ram_buffer(150) := X"24040001";
ram_buffer(151) := X"0C000186";
ram_buffer(152) := X"24040002";
ram_buffer(153) := X"3C131000";
ram_buffer(154) := X"00009025";
ram_buffer(155) := X"3C141000";
ram_buffer(156) := X"241600E6";
ram_buffer(157) := X"0C000177";
ram_buffer(158) := X"00000000";
ram_buffer(159) := X"0C000153";
ram_buffer(160) := X"AFA20014";
ram_buffer(161) := X"0C000153";
ram_buffer(162) := X"AFA20010";
ram_buffer(163) := X"8FA30014";
ram_buffer(164) := X"8FA40010";
ram_buffer(165) := X"16C00002";
ram_buffer(166) := X"0076001B";
ram_buffer(167) := X"0007000D";
ram_buffer(168) := X"305E00FF";
ram_buffer(169) := X"308400FF";
ram_buffer(170) := X"00001010";
ram_buffer(171) := X"14820025";
ram_buffer(172) := X"00000000";
ram_buffer(173) := X"AE630000";
ram_buffer(174) := X"16570020";
ram_buffer(175) := X"26730004";
ram_buffer(176) := X"02802825";
ram_buffer(177) := X"24060010";
ram_buffer(178) := X"0C000211";
ram_buffer(179) := X"24040004";
ram_buffer(180) := X"0260A025";
ram_buffer(181) := X"00009025";
ram_buffer(182) := X"0C000149";
ram_buffer(183) := X"24040001";
ram_buffer(184) := X"24020002";
ram_buffer(185) := X"17C2FFE3";
ram_buffer(186) := X"24060010";
ram_buffer(187) := X"02802825";
ram_buffer(188) := X"0C000211";
ram_buffer(189) := X"24040004";
ram_buffer(190) := X"0C00013C";
ram_buffer(191) := X"00000000";
ram_buffer(192) := X"0C000186";
ram_buffer(193) := X"24040003";
ram_buffer(194) := X"2404000C";
ram_buffer(195) := X"0C000227";
ram_buffer(196) := X"AE110004";
ram_buffer(197) := X"2404000C";
ram_buffer(198) := X"0C000227";
ram_buffer(199) := X"AE110008";
ram_buffer(200) := X"0C000186";
ram_buffer(201) := X"24040004";
ram_buffer(202) := X"3C021000";
ram_buffer(203) := X"00400008";
ram_buffer(204) := X"00000000";
ram_buffer(205) := X"1000FFC3";
ram_buffer(206) := X"00000000";
ram_buffer(207) := X"1000FFE6";
ram_buffer(208) := X"26520001";
ram_buffer(209) := X"0C000149";
ram_buffer(210) := X"24040002";
ram_buffer(211) := X"1000FFE5";
ram_buffer(212) := X"24020002";
ram_buffer(213) := X"3C021000";
ram_buffer(214) := X"00400008";
ram_buffer(215) := X"00000000";
ram_buffer(216) := X"03E00008";
ram_buffer(217) := X"00000000";
ram_buffer(218) := X"27BDFFE0";
ram_buffer(219) := X"AFBF001C";
ram_buffer(220) := X"AFB10018";
ram_buffer(221) := X"AFB00014";
ram_buffer(222) := X"3C030000";
ram_buffer(223) := X"8C620CB0";
ram_buffer(224) := X"3C110000";
ram_buffer(225) := X"8C420004";
ram_buffer(226) := X"00608025";
ram_buffer(227) := X"26310CB4";
ram_buffer(228) := X"2C430008";
ram_buffer(229) := X"14600006";
ram_buffer(230) := X"00000000";
ram_buffer(231) := X"8FBF001C";
ram_buffer(232) := X"8FB10018";
ram_buffer(233) := X"8FB00014";
ram_buffer(234) := X"03E00008";
ram_buffer(235) := X"27BD0020";
ram_buffer(236) := X"000210C0";
ram_buffer(237) := X"02221021";
ram_buffer(238) := X"8C430000";
ram_buffer(239) := X"8C440004";
ram_buffer(240) := X"0060F809";
ram_buffer(241) := X"00000000";
ram_buffer(242) := X"8E020CB0";
ram_buffer(243) := X"00000000";
ram_buffer(244) := X"8C420004";
ram_buffer(245) := X"1000FFEF";
ram_buffer(246) := X"2C430008";
ram_buffer(247) := X"8F828018";
ram_buffer(248) := X"00000000";
ram_buffer(249) := X"8C440004";
ram_buffer(250) := X"8F828010";
ram_buffer(251) := X"8F83800C";
ram_buffer(252) := X"24420001";
ram_buffer(253) := X"304201FF";
ram_buffer(254) := X"10430008";
ram_buffer(255) := X"00000000";
ram_buffer(256) := X"8F838010";
ram_buffer(257) := X"3C050000";
ram_buffer(258) := X"24A50AB0";
ram_buffer(259) := X"308400FF";
ram_buffer(260) := X"00651821";
ram_buffer(261) := X"A0640000";
ram_buffer(262) := X"AF828010";
ram_buffer(263) := X"03E00008";
ram_buffer(264) := X"00000000";
ram_buffer(265) := X"3C022004";
ram_buffer(266) := X"AF828018";
ram_buffer(267) := X"3C022003";
ram_buffer(268) := X"AF828014";
ram_buffer(269) := X"3C030000";
ram_buffer(270) := X"3C022001";
ram_buffer(271) := X"AC620CB0";
ram_buffer(272) := X"3C040000";
ram_buffer(273) := X"3C020000";
ram_buffer(274) := X"24420CB4";
ram_buffer(275) := X"24840CF4";
ram_buffer(276) := X"24420008";
ram_buffer(277) := X"1444FFFE";
ram_buffer(278) := X"AC40FFF8";
ram_buffer(279) := X"3C020000";
ram_buffer(280) := X"24640CB0";
ram_buffer(281) := X"244203DC";
ram_buffer(282) := X"AC820014";
ram_buffer(283) := X"AC800018";
ram_buffer(284) := X"3C06F000";
ram_buffer(285) := X"8CC40004";
ram_buffer(286) := X"3C050000";
ram_buffer(287) := X"00041100";
ram_buffer(288) := X"00441021";
ram_buffer(289) := X"00021080";
ram_buffer(290) := X"3C040000";
ram_buffer(291) := X"248409A0";
ram_buffer(292) := X"24420004";
ram_buffer(293) := X"00821021";
ram_buffer(294) := X"24A50368";
ram_buffer(295) := X"AC450038";
ram_buffer(296) := X"AC40003C";
ram_buffer(297) := X"8C630CB0";
ram_buffer(298) := X"00000000";
ram_buffer(299) := X"8C620000";
ram_buffer(300) := X"00000000";
ram_buffer(301) := X"34420004";
ram_buffer(302) := X"AC620000";
ram_buffer(303) := X"8CC30004";
ram_buffer(304) := X"00000000";
ram_buffer(305) := X"00031100";
ram_buffer(306) := X"00431021";
ram_buffer(307) := X"00021080";
ram_buffer(308) := X"00441021";
ram_buffer(309) := X"8C430000";
ram_buffer(310) := X"24040001";
ram_buffer(311) := X"8C620000";
ram_buffer(312) := X"00000000";
ram_buffer(313) := X"34420080";
ram_buffer(314) := X"08000046";
ram_buffer(315) := X"AC620000";
ram_buffer(316) := X"27BDFFE8";
ram_buffer(317) := X"AFBF0014";
ram_buffer(318) := X"0C000046";
ram_buffer(319) := X"00002025";
ram_buffer(320) := X"3C020000";
ram_buffer(321) := X"8C430CB0";
ram_buffer(322) := X"8FBF0014";
ram_buffer(323) := X"8C620000";
ram_buffer(324) := X"2404FFFB";
ram_buffer(325) := X"00441024";
ram_buffer(326) := X"AC620000";
ram_buffer(327) := X"03E00008";
ram_buffer(328) := X"27BD0018";
ram_buffer(329) := X"8F838018";
ram_buffer(330) := X"00000000";
ram_buffer(331) := X"8C620000";
ram_buffer(332) := X"00000000";
ram_buffer(333) := X"30420002";
ram_buffer(334) := X"1040FFFC";
ram_buffer(335) := X"00000000";
ram_buffer(336) := X"AC640008";
ram_buffer(337) := X"03E00008";
ram_buffer(338) := X"00000000";
ram_buffer(339) := X"40046000";
ram_buffer(340) := X"40806000";
ram_buffer(341) := X"8F838010";
ram_buffer(342) := X"8F82800C";
ram_buffer(343) := X"00000000";
ram_buffer(344) := X"14620004";
ram_buffer(345) := X"00000000";
ram_buffer(346) := X"40846000";
ram_buffer(347) := X"1000FFF7";
ram_buffer(348) := X"00000000";
ram_buffer(349) := X"8F82800C";
ram_buffer(350) := X"3C030000";
ram_buffer(351) := X"24630AB0";
ram_buffer(352) := X"00431021";
ram_buffer(353) := X"90420000";
ram_buffer(354) := X"8F83800C";
ram_buffer(355) := X"304200FF";
ram_buffer(356) := X"24630001";
ram_buffer(357) := X"306301FF";
ram_buffer(358) := X"AF83800C";
ram_buffer(359) := X"40846000";
ram_buffer(360) := X"03E00008";
ram_buffer(361) := X"00000000";
ram_buffer(362) := X"27BDFFE8";
ram_buffer(363) := X"00803025";
ram_buffer(364) := X"24050004";
ram_buffer(365) := X"AFBF0014";
ram_buffer(366) := X"0C000149";
ram_buffer(367) := X"30C400FF";
ram_buffer(368) := X"24A5FFFF";
ram_buffer(369) := X"14A0FFFC";
ram_buffer(370) := X"00063202";
ram_buffer(371) := X"8FBF0014";
ram_buffer(372) := X"00000000";
ram_buffer(373) := X"03E00008";
ram_buffer(374) := X"27BD0018";
ram_buffer(375) := X"27BDFFE8";
ram_buffer(376) := X"00002825";
ram_buffer(377) := X"00003025";
ram_buffer(378) := X"AFBF0014";
ram_buffer(379) := X"24070020";
ram_buffer(380) := X"0C000153";
ram_buffer(381) := X"00000000";
ram_buffer(382) := X"00A21004";
ram_buffer(383) := X"24A50008";
ram_buffer(384) := X"14A7FFFB";
ram_buffer(385) := X"00C23025";
ram_buffer(386) := X"8FBF0014";
ram_buffer(387) := X"00C01025";
ram_buffer(388) := X"03E00008";
ram_buffer(389) := X"27BD0018";
ram_buffer(390) := X"8F828014";
ram_buffer(391) := X"00000000";
ram_buffer(392) := X"03E00008";
ram_buffer(393) := X"AC440008";
ram_buffer(394) := X"3C02F000";
ram_buffer(395) := X"8C420004";
ram_buffer(396) := X"3C030000";
ram_buffer(397) := X"24630994";
ram_buffer(398) := X"00021080";
ram_buffer(399) := X"00431021";
ram_buffer(400) := X"8C420000";
ram_buffer(401) := X"24030002";
ram_buffer(402) := X"03E00008";
ram_buffer(403) := X"AC430000";
ram_buffer(404) := X"27BDFFE0";
ram_buffer(405) := X"AFBF001C";
ram_buffer(406) := X"AFB20018";
ram_buffer(407) := X"AFB10014";
ram_buffer(408) := X"AFB00010";
ram_buffer(409) := X"3C02F000";
ram_buffer(410) := X"8C430004";
ram_buffer(411) := X"00000000";
ram_buffer(412) := X"00031100";
ram_buffer(413) := X"00431021";
ram_buffer(414) := X"00021080";
ram_buffer(415) := X"24520004";
ram_buffer(416) := X"3C110000";
ram_buffer(417) := X"263109A0";
ram_buffer(418) := X"02221021";
ram_buffer(419) := X"8C430000";
ram_buffer(420) := X"00408025";
ram_buffer(421) := X"8C630004";
ram_buffer(422) := X"00000000";
ram_buffer(423) := X"2C620008";
ram_buffer(424) := X"14400007";
ram_buffer(425) := X"00000000";
ram_buffer(426) := X"8FBF001C";
ram_buffer(427) := X"8FB20018";
ram_buffer(428) := X"8FB10014";
ram_buffer(429) := X"8FB00010";
ram_buffer(430) := X"03E00008";
ram_buffer(431) := X"27BD0020";
ram_buffer(432) := X"000318C0";
ram_buffer(433) := X"00721821";
ram_buffer(434) := X"02231821";
ram_buffer(435) := X"8C620000";
ram_buffer(436) := X"8C640004";
ram_buffer(437) := X"0040F809";
ram_buffer(438) := X"00000000";
ram_buffer(439) := X"8E020000";
ram_buffer(440) := X"00000000";
ram_buffer(441) := X"8C430004";
ram_buffer(442) := X"1000FFED";
ram_buffer(443) := X"2C620008";
ram_buffer(444) := X"27BDFFE0";
ram_buffer(445) := X"AFBF001C";
ram_buffer(446) := X"AFB20018";
ram_buffer(447) := X"AFB10014";
ram_buffer(448) := X"AFB00010";
ram_buffer(449) := X"3C05F000";
ram_buffer(450) := X"8CA20004";
ram_buffer(451) := X"00000000";
ram_buffer(452) := X"00021240";
ram_buffer(453) := X"244301E8";
ram_buffer(454) := X"3C020000";
ram_buffer(455) := X"24420CF4";
ram_buffer(456) := X"00431021";
ram_buffer(457) := X"0040E825";
ram_buffer(458) := X"8CB00004";
ram_buffer(459) := X"8CA70004";
ram_buffer(460) := X"00000000";
ram_buffer(461) := X"00072100";
ram_buffer(462) := X"8CA20004";
ram_buffer(463) := X"3C030000";
ram_buffer(464) := X"24630994";
ram_buffer(465) := X"00021080";
ram_buffer(466) := X"00431021";
ram_buffer(467) := X"3C03F002";
ram_buffer(468) := X"AC430000";
ram_buffer(469) := X"00871021";
ram_buffer(470) := X"3C030000";
ram_buffer(471) := X"00021080";
ram_buffer(472) := X"246309A0";
ram_buffer(473) := X"00432821";
ram_buffer(474) := X"24420004";
ram_buffer(475) := X"3C06F001";
ram_buffer(476) := X"00621021";
ram_buffer(477) := X"ACA60000";
ram_buffer(478) := X"24A60044";
ram_buffer(479) := X"00402825";
ram_buffer(480) := X"14C50014";
ram_buffer(481) := X"24A50008";
ram_buffer(482) := X"3C050000";
ram_buffer(483) := X"24A50628";
ram_buffer(484) := X"AC450000";
ram_buffer(485) := X"AC400004";
ram_buffer(486) := X"00872021";
ram_buffer(487) := X"00042080";
ram_buffer(488) := X"00641821";
ram_buffer(489) := X"8C620000";
ram_buffer(490) := X"24030001";
ram_buffer(491) := X"AC430000";
ram_buffer(492) := X"1600000C";
ram_buffer(493) := X"2782800C";
ram_buffer(494) := X"27838894";
ram_buffer(495) := X"14430007";
ram_buffer(496) := X"24420004";
ram_buffer(497) := X"0C00007C";
ram_buffer(498) := X"00000000";
ram_buffer(499) := X"1000FFFF";
ram_buffer(500) := X"00000000";
ram_buffer(501) := X"1000FFEA";
ram_buffer(502) := X"ACA0FFF8";
ram_buffer(503) := X"1000FFF7";
ram_buffer(504) := X"AC40FFFC";
ram_buffer(505) := X"0C000227";
ram_buffer(506) := X"2404000C";
ram_buffer(507) := X"00101080";
ram_buffer(508) := X"3C100000";
ram_buffer(509) := X"26100988";
ram_buffer(510) := X"02028021";
ram_buffer(511) := X"02008825";
ram_buffer(512) := X"2412FFFF";
ram_buffer(513) := X"24060004";
ram_buffer(514) := X"02002825";
ram_buffer(515) := X"0C000211";
ram_buffer(516) := X"00002025";
ram_buffer(517) := X"8E220000";
ram_buffer(518) := X"00000000";
ram_buffer(519) := X"1052FFFA";
ram_buffer(520) := X"24060004";
ram_buffer(521) := X"0C000237";
ram_buffer(522) := X"00000000";
ram_buffer(523) := X"8E220000";
ram_buffer(524) := X"00000000";
ram_buffer(525) := X"0040F809";
ram_buffer(526) := X"00000000";
ram_buffer(527) := X"1000FFE3";
ram_buffer(528) := X"00000000";
ram_buffer(529) := X"10C00013";
ram_buffer(530) := X"00C51821";
ram_buffer(531) := X"2406FFF0";
ram_buffer(532) := X"00661024";
ram_buffer(533) := X"0043182B";
ram_buffer(534) := X"00031900";
ram_buffer(535) := X"24420010";
ram_buffer(536) := X"00A62824";
ram_buffer(537) := X"00431821";
ram_buffer(538) := X"40076000";
ram_buffer(539) := X"40806000";
ram_buffer(540) := X"10A30007";
ram_buffer(541) := X"2484FF00";
ram_buffer(542) := X"00A61024";
ram_buffer(543) := X"AC820000";
ram_buffer(544) := X"AC400000";
ram_buffer(545) := X"24A50010";
ram_buffer(546) := X"14A3FFFC";
ram_buffer(547) := X"00A61024";
ram_buffer(548) := X"40876000";
ram_buffer(549) := X"03E00008";
ram_buffer(550) := X"00000000";
ram_buffer(551) := X"40066000";
ram_buffer(552) := X"40806000";
ram_buffer(553) := X"00001025";
ram_buffer(554) := X"2483FF00";
ram_buffer(555) := X"24050200";
ram_buffer(556) := X"AC620000";
ram_buffer(557) := X"AC400000";
ram_buffer(558) := X"34440200";
ram_buffer(559) := X"AC640000";
ram_buffer(560) := X"AC800000";
ram_buffer(561) := X"24420010";
ram_buffer(562) := X"1445FFF9";
ram_buffer(563) := X"00000000";
ram_buffer(564) := X"40866000";
ram_buffer(565) := X"03E00008";
ram_buffer(566) := X"00000000";
ram_buffer(567) := X"40066000";
ram_buffer(568) := X"40806000";
ram_buffer(569) := X"00000000";
ram_buffer(570) := X"40076000";
ram_buffer(571) := X"40806000";
ram_buffer(572) := X"00001025";
ram_buffer(573) := X"2403FF0C";
ram_buffer(574) := X"24050200";
ram_buffer(575) := X"AC620000";
ram_buffer(576) := X"AC400000";
ram_buffer(577) := X"34440200";
ram_buffer(578) := X"AC640000";
ram_buffer(579) := X"AC800000";
ram_buffer(580) := X"24420010";
ram_buffer(581) := X"1445FFF9";
ram_buffer(582) := X"00000000";
ram_buffer(583) := X"40876000";
ram_buffer(584) := X"00000000";
ram_buffer(585) := X"40076000";
ram_buffer(586) := X"40806000";
ram_buffer(587) := X"00001025";
ram_buffer(588) := X"2403FF08";
ram_buffer(589) := X"24050200";
ram_buffer(590) := X"AC620000";
ram_buffer(591) := X"AC400000";
ram_buffer(592) := X"34440200";
ram_buffer(593) := X"AC640000";
ram_buffer(594) := X"AC800000";
ram_buffer(595) := X"24420010";
ram_buffer(596) := X"1445FFF9";
ram_buffer(597) := X"00000000";
ram_buffer(598) := X"40876000";
ram_buffer(599) := X"00000000";
ram_buffer(600) := X"40866000";
ram_buffer(601) := X"03E00008";
ram_buffer(602) := X"00000000";
ram_buffer(603) := X"00000000";
ram_buffer(604) := X"00000100";
ram_buffer(605) := X"01010001";
ram_buffer(606) := X"00000000";
ram_buffer(607) := X"00000000";
ram_buffer(608) := X"00000000";
ram_buffer(609) := X"00000000";
ram_buffer(610) := X"FFFFFFFF";
ram_buffer(611) := X"FFFFFFFF";
ram_buffer(612) := X"FFFFFFFF";
ram_buffer(613) := X"FFFFFFFF";
ram_buffer(614) := X"FFFFFFFF";
ram_buffer(615) := X"FFFFFFFF";
ram_buffer(616) := X"FFFFFFFF";
ram_buffer(617) := X"00000000";
ram_buffer(618) := X"00000000";
ram_buffer(619) := X"00000000";
ram_buffer(620) := X"00000000";
ram_buffer(621) := X"00000000";
ram_buffer(622) := X"00000000";
ram_buffer(623) := X"00000000";
ram_buffer(624) := X"00000000";
ram_buffer(625) := X"00000000";
ram_buffer(626) := X"00000000";
ram_buffer(627) := X"00000000";
ram_buffer(628) := X"00000000";
ram_buffer(629) := X"00000000";
ram_buffer(630) := X"00000000";
ram_buffer(631) := X"00000000";
ram_buffer(632) := X"00000000";
ram_buffer(633) := X"FFFFFFFF";
ram_buffer(634) := X"00000000";
ram_buffer(635) := X"00000000";
ram_buffer(636) := X"00000000";
ram_buffer(637) := X"00000000";
ram_buffer(638) := X"00000000";
ram_buffer(639) := X"00000000";
ram_buffer(640) := X"00000000";
ram_buffer(641) := X"00000000";
ram_buffer(642) := X"00000000";
ram_buffer(643) := X"00000000";
ram_buffer(644) := X"00000000";
ram_buffer(645) := X"00000000";
ram_buffer(646) := X"00000000";
ram_buffer(647) := X"00000000";
ram_buffer(648) := X"00000000";
ram_buffer(649) := X"00000000";
ram_buffer(650) := X"FFFFFFFF";
ram_buffer(651) := X"00000000";
ram_buffer(652) := X"00000000";
ram_buffer(653) := X"00000000";
ram_buffer(654) := X"00000000";
ram_buffer(655) := X"00000000";
ram_buffer(656) := X"00000000";
ram_buffer(657) := X"00000000";
ram_buffer(658) := X"00000000";
ram_buffer(659) := X"00000000";
ram_buffer(660) := X"00000000";
ram_buffer(661) := X"00000000";
ram_buffer(662) := X"00000000";
ram_buffer(663) := X"00000000";
ram_buffer(664) := X"00000000";
ram_buffer(665) := X"00000000";
ram_buffer(666) := X"00000000";
return ram_buffer;
end;
end;
|
mit
|
f16f6ef0982600bf7d7afaa8f9a98995
| 0.617812 | 2.356171 | false | false | false | false |
Anding/DDR2_memory_interface
|
rtl/system/SDRAM_PHYIO.vhd
| 1 | 36,154 |
-- DDR2 memory interface
-- Andrew Read, March 2016
-- This project is based on a working DDR2 interface very kindly donated by a friend
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_textio.all;
entity SDRAM_PHYIO is
port (
CLK : in std_logic; -- 125MHz clock (this is the "system clock")
CLK_130 : in std_logic; -- 125MHz clock 130 degree phase shift (special clock for certain DDR2 SDRAM signals)
reset : in std_logic; -- active low reset
-- user interface
wrrd_ba_add : in std_logic_vector(2 downto 0); -- bank address
wrrd_ras_add : in std_logic_vector(12 downto 0); -- row address
wrrd_cas_add : in std_logic_vector(8 downto 0); -- column address
wr_we : in std_logic_vector(3 downto 0); -- set high to request write
wr_add : in std_logic_vector(25 downto 0); -- NOT USED
wr_dat : in std_logic_vector(31 downto 0); -- write data
wr_ack : out std_logic; -- hold write request until wr_ack goes high
rd_re : in std_logic; -- set high to request read
rd_add : in std_logic_vector(25 downto 0); -- NOT USED
rd_dat : out std_logic_vector(31 downto 0); -- read data
rd_ack : out std_logic; -- hold read request until rd_ack goes high
rd_valid : out std_logic; -- accept read rd_dat during the same cycle that rd_valid is high
refresh : in std_logic; -- cycle refresh high to allow periodic SDRAM refresh (driven by SDRAM_CTRL)
ref_ack : out std_logic; -- hold refresh request until ref_ack goes high
-- DDR2 SDRAM interface (MT47H64M16HR-25E)
SDRAM_A : out std_logic_vector(13 downto 0); -- address inputs: should be (12 downto 0), no A[13] in 16x
SDRAM_BA : out std_logic_vector(2 downto 0); -- bank address
SDRAM_CKE : out std_logic; -- clock enable
SDRAM_CK : out std_logic; -- positive clock (differential pair)
SDRAM_nCK : out std_logic; -- negative clock (differential pair)
SDRAM_DQ : inout std_logic_vector(15 downto 0); -- bidirectional data input / output
SDRAM_DQS : inout std_logic_vector(1 downto 0); -- bidirectional data strobe (input not currently used)
--SDRAM_nDQS : out std_logic_vector(1 downto 0); -- differential DQS not currently used
SDRAM_DM : out std_logic_vector(1 downto 0); -- data mask for write data
SDRAM_nCAS : out std_logic; -- CAS# command input
SDRAM_nCS : out std_logic; -- chip select
SDRAM_nRAS : out std_logic; -- RAS# command input
SDRAM_nWE : out std_logic); -- WE# command input
end SDRAM_PHYIO;
-- This is a DD2 SDRAM interface developed on the Diglient Nexys4-DDR board. It interfaces with the Micron MT47H64M16HR-25E
-- The module is driven by two clocks due to the need to provide a strobe (DQS_out) at a nominal 90 degree phase off set from write data (DQ)
-- In this design the clock that drives the DQS strobe is actually at a 130 degree phase offset to the write data (DQ). A 130 degree phase offset
-- is within the specification (see tDQSS on the datasheet 1Gb_DDR2 p34), but compared to a 90 degree phase offset the extra phase shift
-- allows a sufficent DQS write preamble (see tWPRE) without needing to toggle the clock enable port on DQS's ODDR buffer
-- This in turn saves the need for what would be a very time constrained cross clock domain signal between the FSM and ODDR/CE
--
-- Clocking summary
-- CLK drives the most of the logic internal to this memory controller, including the user interface and the finite state machine
-- CLK also drives SDRAM_DQ, and all of SDRAM_CAS#, etc. on the SDRAM
-- CLK_130 drives SDRAM_CK/n and SDRAM_DQS
-- A summary of MT47H64M16HR-25E addressing
-- Banks 8
-- Rows 8,192
-- Columns 1,024
-- Addresses 67,108,864
-- Word size 16
-- Bits 1,073,741,824
-- Gbits 1.00000
-- Known limitations
-- 1. DQS in not used in READ cycles
-- DD2 specifications require that DQ_in is clocked into registers at the transitions of DQS_in, after DQS_in has been delayed 90 degree
-- (relative to the clock period). However to delay the actual DQS_in signals is not straightforward and so a workaround is currently being used.
-- DQ_in is being clocked in using an IDDR buffer driven by "not CLK_130" which has been found through trial and error to be a good enough
-- approximation to DQS_in to work in simulation and in hardware on the Nexys4-DDR at the tested clock frequencies
-- If higher clock frequencies are to be attempted then I would suggest to generate a third clock and experimenting with various phase offsets to drive DQ_in's IDDR
-- naturally any solution arrived at with this method will only be applicable to a particular board and clock frequency!
-- 2. The write postamble (WPST, p34) is (technically) violated although the Micron DDR model does not complain
-- The use of a 130 degree phase offset as opposed to a 90 degree phase offset clock to drive DQS allows a difficult cross-clock domain signal to be avoided
-- but the compromises is that the extra 40 degrees applied to the DQS write preamble is "stolen" from the write postamble (see tWPST, p36). The Micron DDR2 model
-- is very sensitive to the correct DQS write preamble but does not raise any error or warning about this violation of the write postamble
-- 3. On die termination (ODT) is not used
architecture Struct of SDRAM_PHYIO is
component OBUFDS is
-- OBUFDS creates a differential output from a single-ended input
-- see ug471 p. 45
generic(
CAPACITANCE : string := "DONT_CARE";
IOSTANDARD : string := "DEFAULT"; -- DIFF_HSTL_II_18 is the default for differential I/O's
SLEW : string := "SLOW"
);
port(
O : out std_ulogic; -- positive output same as input
OB : out std_ulogic; -- negative output opposite to input
I : in std_ulogic -- input
);
end component;
component ODDR
-- ODDR (dual data rate output buffer) creates an 1-bit wide DDR output from a 2-bit wide clock-synchronous input without manual multiplexing
-- see ug471 p. 127
generic(
DDR_CLK_EDGE : string := "OPPOSITE_EDGE"; -- in OPPOSITE_EDGE mode D2 is captured on a falling clock edge and
-- presented at output on the next rising clock edge
-- in SAME_EDGE mode D2 is captured on a rising clock edge and
-- presented at output one full clock cycle later on the rising edge
-- in both cases D1 is captured on a rising clock edge and presented
-- at output on the next falling clock edge
INIT : bit := '0'; -- initial value of Q
SRTYPE : string := "SYNC" -- set/reset with respect to clock
);
port(
Q : out std_ulogic; -- output
C : in std_ulogic; -- clock input port
CE : in std_ulogic; -- clock enable port (low disables the output port on Q)
D1 : in std_ulogic; -- inputs
D2 : in std_ulogic;
R : in std_ulogic := 'L'; -- synchronous reset (ignore - not used)
S : in std_ulogic := 'L' -- synchronous set (ignore - not used)
);
end component;
component IDDR
-- IDDR (dual data rate input buffer) creates a 2-bit wide clock-synchronous output from a 1-bit wide DDR input without manual multiplexing
-- ug471 p110
generic(
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
IS_C_INVERTED : bit := '0';
IS_D_INVERTED : bit := '0';
SRTYPE : string := "SYNC" -- set/reset with respect to clock
);
port(
Q1 : out std_ulogic; -- outputs
Q2 : out std_ulogic;
C : in std_ulogic; -- clock input port
CE : in std_ulogic; -- clock enable port
D : in std_ulogic; -- input
R : in std_ulogic := 'L'; -- synchronous reset (ignore - not used)
S : in std_ulogic := 'L' -- synchronous set (ignore - not used)
);
end component;
type fsm_type is (init,
init_precharge, init_precharge_done,
init_mode_2, init_mode_2_done,
init_mode_3, init_mode_3_done,
init_mode_1, init_mode_1_done,
init_mode_0, init_mode_0_done,
init_precharge_0, init_precharge_0_done,
init_refresh_0, init_refresh_0_done,
init_refresh_1, init_refresh_1_done,
init_mode_0_2, init_mode_0_2_done,
init_mode_1_2, init_mode_1_2_done,
init_mode_1_3, init_mode_1_3_done,
write_0, write_1, write_2, write_3, write_4, write_5,
idle,
bank_0, bank_done,
active,
precharge_0, precharge_done,
read_0, read_1, read_2, read_3, read_3b, read_4, read_5, read_done,
refresh_0, refresh_1);
-- DDR2 SRAM commands (1Gb_DDD2.pdf, p70) values of CKE CS# RAS# CAS# WE#
constant CMD_LOAD_MODE : std_logic_vector(4 downto 0) := "10000";
constant CMD_REFRESH : std_logic_vector(4 downto 0) := "10001";
constant CMD_ENTER_SELF_REFRESH : std_logic_vector(4 downto 0) := "00001";
constant CMD_EXIT_SELF_REFRESH : std_logic_vector(4 downto 0) := "10111";
constant CMD_PRECHARGE : std_logic_vector(4 downto 0) := "10010";
constant CMD_ACTIVATE : std_logic_vector(4 downto 0) := "10011";
constant CMD_WRITE : std_logic_vector(4 downto 0) := "10100"; -- also WRITE with auto precharge
constant CMD_READ : std_logic_vector(4 downto 0) := "10101"; -- also READ with auto precharge
constant CMD_NOP : std_logic_vector(4 downto 0) := "10111"; -- also EXIT_POWER_DOWN
constant CMD_DESELECT : std_logic_vector(4 downto 0) := "11111";
constant CMD_ENTER_POWER_DOWN : std_logic_vector(4 downto 0) := "00111";
-- Refresh parameter, see documentation in SDRAM_CTRL
constant refreshCount : integer range 0 to 8191 := 7; -- number of REFRESH commands issued during each refresh phase, minus 1
-- Timing parameters (ref. 1GB_DDR2 datasheet page numbers)
-- ct_int power up and stabilize clock, p87: ct > 400ns
-- ct_precharge tRP, precharge period, p36: (ct + 1) > 12.5ns
-- ct_refresh tRFC, refresh interval, p37: (ct + 1) > 127.5ns
-- ct_RCD tRCD, ROW to COLUMN delay, p36: (ct + 1) > 12.5ns
-- ct_writerec tWR, write recovery, p37: p (ct + 1) > 15ns
-- reg_CAS, ct_CAS tCAS, CAS latency, pp32, 77: Allowed values of CAS are 3, 4, 5, 6, 7
-- Timing parameters at 100MHz (based on a 9us clock period including allowance)
constant ct_init : integer range 0 to 1023 := 45;
constant ct_precharge : integer range 0 to 1023 := 1;
constant ct_refresh : integer range 0 to 1023 := 14;
constant ct_RCD : integer range 0 to 1023 := 1;
constant ct_WR : integer range 0 to 1023 := 1;
constant reg_CAS : std_logic_vector(2 downto 0) := "011" ;
constant ct_CAS : integer range 0 to 1023 := 0; -- ct_CAS must be set to reg_CAS - 3
-- Timing parameters at 125MHz (based on a 7.2us clock period including allowance)
--constant ct_init : integer range 0 to 1023 := 56;
--constant ct_precharge : integer range 0 to 1023 := 2;
--constant ct_refresh : integer range 0 to 1023 := 17;
--constant ct_RCD : integer range 0 to 1023 := 1;
--constant ct_WR : integer range 0 to 1023 := 2;
--constant reg_CAS : std_logic_vector(2 downto 0) := "011" ;
--constant ct_CAS : integer range 0 to 1023 := 0; -- ct_CAS must be set to reg_CAS - 3
-- Timing parameters at 200MHz (based on a 5us clock period)
--constant ct_init : integer range 0 to 1023 := 80;
--constant ct_precharge : integer range 0 to 1023 := 2;
--constant ct_refresh : integer range 0 to 1023 := 25;
--constant ct_RCD : integer range 0 to 1023 := 2;
--constant ct_WR : integer range 0 to 1023 := 3;
--constant reg_CAS : std_logic_vector(2 downto 0) := "011" ;
--constant ct_CAS : integer range 0 to 1023 := 0; -- ct_CAS must be set to reg_CAS - 3
signal SDRAM_dq_out_tmp : std_logic_vector(15 downto 0);
signal SDRAM_dq_out : std_logic_vector(31 downto 0);
signal SDRAM_dq_in_tmp : std_logic_vector(15 downto 0);
signal SDRAM_dq_in, SDRAM_dq_in_reg : std_logic_vector(31 downto 0);
signal SDRAM_dqs_out_tmp : std_logic_vector(1 downto 0);
signal state : fsm_type;
signal counter : integer range 0 to 1023;
signal dq_write, dq_write_reg : std_logic;
signal dqs_write, dqs_write_reg : std_logic;
signal dm_write : std_logic_vector(3 downto 0);
signal bank_row_active : std_logic_vector(13 downto 0);
signal bank_active : std_logic_vector(2 downto 0);
signal clk_int_xor_delay : std_logic;
signal clk_int_rise : std_logic := '0';
signal clk_int_fall : std_logic := '0';
signal clk_int_xor : std_logic;
signal command : std_logic_vector(4 downto 0);
signal rd_dat_r : std_logic_vector(63 downto 0);
signal dqs_out_ce : std_logic;
signal SDRAM_DQS_reg : std_logic_vector(1 downto 0);
signal wr_dat_64 : std_logic_vector(63 downto 0);
signal wr_we_8 : std_logic_vector(7 downto 0);
signal counterRefresh : integer range 0 to 8191;
begin
-----------------------------------------------------
-- PHY: SDRAM commands
-----------------------------------------------------
SDRAM_CKE <= COMMAND(4);
SDRAM_nCS <= COMMAND(3);
SDRAM_nRAS <= COMMAND(2);
SDRAM_nCAS <= COMMAND(1);
SDRAM_nWE <= COMMAND(0);
-----------------------------------------------------
-- PHY: SDRAM_CLK
-----------------------------------------------------
OBUFDSi : OBUFDS
port map (
O => SDRAM_CK,
OB => SDRAM_nCK,
I => clk_130
);
-- SDRAM_CK/n is created with a 90 degree phase offset so that its transitions are at the midpoint of the stable
-- values of the control lines CAS#, RAS#, etc.
-----------------------------------------------------
-- PHY: SDRAM_DQ
-----------------------------------------------------
SDRAM_dq_in_tmp <= SDRAM_DQ after 1 ps; -- reflect board timing "after 1 ps" is ignored by synthesis
dq_iddr : for i in 0 to 15 generate
dq_iddrn : IDDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
INIT_Q1 => '0',
INIT_Q2 => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
SRTYPE => "SYNC"
)
port map(
Q1 => SDRAM_dq_in(i), -- bits 15 downto 0 are taken on one clock edge and
Q2 => SDRAM_dq_in(i + 16), -- bits 32 downto 16 are taken on the opposite clock edge (see DDR_CLK_EDGE setting and timing diagrams in ug471 p110
C => not CLK_130, -- a workaround, see limitation above: should actually be clocked by DQS_in after delaying that by 90 degrees.
CE => '1',
D => SDRAM_dq_in_tmp(i),
R => '0',
S => '0'
);
end generate;
-- 16 IDDR buffers are uses to generate a 32-bit wide clock-synchronous output from 16-bit wide READ data originating on the DDR2 SDRAM
dq_oddr : for i in 0 to 15 generate
dq_oddrn : ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC"
)
port map(
Q => SDRAM_dq_out_tmp(i),
C => CLK,
CE => '1',
D1 => SDRAM_dq_out(i),
D2 => SDRAM_dq_out(i + 16),
R => '0',
S => '0'
);
end generate;
-- 16 IDDR buffers are uses to generate a 16-bit wide DDR output from 32-bit wide clock-synchronous WRITE data originating in this controller
SDRAM_DQ <= SDRAM_dq_out_tmp when (dq_write = '1') else "ZZZZZZZZZZZZZZZZ";
-- SDRAM_DQ is bidirectional, set to hi-Z when not using it for a write
-----------------------------------------------------
-- PHY: SDRAM_DQS (single ended)
-----------------------------------------------------
dqs_oddr : for i in 0 to 1 generate
dqs_oddrn : ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC"
)
port map(
Q => SDRAM_dqs_out_tmp(i),
C => CLK_130,
CE => '1',-- dq_write_reg, -- DQS is not a free-running clock. Only strobe when data is present on DQ, otherwise go low for pre/postamble
D1 => '1',
D2 => '0',
R => '0',
S => '0'
);
end generate;
SDRAM_DQS <= SDRAM_dqs_out_tmp when (dq_write = '1') else "ZZ"; -- (dqs_write_reg = '1') else "ZZ";
-- SDRAM_DQ is bidirectional, set to hi-Z when not using it for a write, write_preamble, or write_postamble
-----------------------------------------------------
-- PHY: SDRAM_DM
-----------------------------------------------------
-- the data mask allows the selection of individual bytes during a 32-bit longword WRITE
-- bytes that should not be written are "masked" by setting DM high
-- there are two DM lines in a 16x SDRAM chip, one for the high byte and one for the low byte
-- The four bits of dm_write are ordered as follows "hi_word_hi_byte hi_word_lo_byte lo_word_lo_byte lo_word_lo_byte"
dm_oddr : for i in 0 to 1 generate
dm_oddrn : ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC"
)
port map(
Q => SDRAM_DM(i), -- data mask. assert high to mask, lo to write
C => CLK, -- the write mask is written in phase with the data
CE => '1',
D1 => dm_write(i),
D2 => dm_write(i + 2), -- "+ 2" to separate the hi-bytes and lo-bytes (see above) into the hi-byte and lo-byte DM lines
R => '0',
S => '0'
);
end generate;
-----------------------------------------------------
-- Stubs for 64 bit functionality
-----------------------------------------------------
wr_dat_64 <= x"01234567" & wr_dat;
wr_we_8 <= "0000" & wr_we;
rd_dat <= rd_dat_r(31 downto 0);
--process
--begin
-- wait until rising_edge(CLK);
-- dq_write_reg <= dq_write;
-- dqs_write_reg <= dqs_write;
--end process;
process
begin
wait until rising_edge(CLK_130);
SDRAM_dq_in_reg <= SDRAM_dq_in;
end process;
-----------------------------------------------------
-- FSM
-----------------------------------------------------
gen_fsm : process (CLK, reset)
variable bank : integer range 0 to 3;
begin
if (reset='1') then -- reset state should be held for 200us MIN
state <= init;
SDRAM_A <= conv_std_logic_vector(0, SDRAM_A'length);
SDRAM_BA <= "000";
COMMAND <= CMD_ENTER_POWER_DOWN;
dq_write <= '0';
dqs_write <= '0';
dm_write <= "1111";
bank_active <= conv_std_logic_vector(0, bank_active'length);
bank_row_active <= conv_std_logic_vector(0, bank_row_active'length);
wr_ack <= '0';
rd_valid <= '0';
rd_ack <= '0';
counter <= 0;
bank_active <= "000";
dqs_out_ce <= '0';
ref_ack <= '0';
counterRefresh <= 0;
elsif (CLK'event and CLK='1') then
case (state) is
-----------------------------------------------------
-- set nCS
-----------------------------------------------------
when init =>
if (counter = ct_init) then
state <= init_precharge;
counter <= 0;
else
counter <= counter + 1;
end if;
COMMAND <= CMD_NOP;
wr_ack <= '0';
-----------------------------------------------------
-- initial precharge all command (1Gb_DDR2 p87)
-----------------------------------------------------
when init_precharge =>
SDRAM_BA <= "000";
SDRAM_A <= "00010000000000"; -- A10 high indicates an all bank precharge command
COMMAND <= CMD_PRECHARGE;
counter <= 0;
state <= init_precharge_done;
when init_precharge_done =>
SDRAM_BA <= "000";
SDRAM_A <= "00010000000000";
COMMAND <= CMD_NOP;
if (counter = ct_precharge) then
state <= init_mode_2; -- follow prescribed init sequence (1Gb_DDR2 p87)
counter <= 0;
else
counter <= counter + 1;
end if;
-----------------------------------------------------
-- init_mode 2 Register
-----------------------------------------------------
when init_mode_2 =>
SDRAM_BA <= "010"; -- Extended Mode Register (EMR) 2
SDRAM_A <= "00000000000000"; -- SDRAM_A is used to set the mode register
-- E7 '0' = 1x refresh rate (0C to 85C)
-- all other bits must be zero (1GB_DDR p85)
COMMAND <= CMD_LOAD_MODE;
counter <= 0;
state <= init_mode_2_done;
when init_mode_2_done => -- NOP command
SDRAM_BA <= "000";
SDRAM_A <= "00000000000000";
COMMAND <= CMD_NOP;
if (counter = 1) then -- tMRD timing requirement is 2 clock cycles (p37)
state <= init_mode_3; -- follow prescribed init sequence (1Gb_DDR2 p87)
counter <= 0;
else
counter <= counter + 1;
end if;
-----------------------------------------------------
-- init_mode 3 Register
-----------------------------------------------------
when init_mode_3 =>
SDRAM_BA <= "011"; -- Extended Mode Register (EMR) 3
SDRAM_A <= "00000000000000"; -- See 1GB_DDR2 p86 for register definition
COMMAND <= CMD_LOAD_MODE;
counter <= 0;
state <= init_mode_3_done;
when init_mode_3_done =>
SDRAM_BA <= "000";
SDRAM_A <= "00000000000000";
COMMAND <= CMD_NOP;
if (counter = 1) then -- tMRD timing requirement is 2 clock cycles (p37)
state <= init_mode_1;
counter <= 0;
else
counter <= counter + 1;
end if;
-----------------------------------------------------
-- init_mode 1 Register
-----------------------------------------------------
when init_mode_1 =>
SDRAM_BA <= "001"; -- Extended Mode Register (EMR) 1
SDRAM_A <= "00010000000100"; -- DQS# disable / RTT = 75 Ohms
-- See 1GB_DDR p81 for register definition
COMMAND <= CMD_LOAD_MODE;
counter <= 0;
state <= init_mode_1_done;
when init_mode_1_done =>
SDRAM_BA <= "000";
SDRAM_A <= "00000000000000";
COMMAND <= CMD_NOP;
if (counter = 1) then -- tMRD timing requirement is 2 clock cycles (p37)
state <= init_mode_0; -- follow prescribed init sequence (1Gb_DDR2 p87)
counter <= 0;
else
counter <= counter + 1;
end if;
-----------------------------------------------------
-- init_mode 0 Register
-----------------------------------------------------
when init_mode_0 =>
SDRAM_BA <= "000"; -- Mode register
SDRAM_A <= "0001010" & reg_CAS & "0010"; -- Burst length = 4 / Reset DLL / Write recovery = 3
COMMAND <= CMD_LOAD_MODE;
counter <= 0;
state <= init_mode_0_done;
when init_mode_0_done =>
SDRAM_BA <= "000";
SDRAM_A <= "00000000000000";
COMMAND <= CMD_NOP;
if (counter = 199) then -- 200 cycles of clock until READ/WRITE are required following DLL reset
state <= init_precharge_0; -- follow prescribed init sequence (1Gb_DDR2 p87)
counter <= 0;
else
counter <= counter + 1;
end if;
-----------------------------------------------------
-- Precharge 0
-----------------------------------------------------
when init_precharge_0 => -- another init precharge command
SDRAM_BA <= "000";
SDRAM_A <= "00010000000000";
COMMAND <= CMD_PRECHARGE;
counter <= 0;
state <= init_precharge_0_done;
when init_precharge_0_done =>
SDRAM_BA <= "000";
SDRAM_A <= "00000000000000";
COMMAND <= CMD_NOP;
if (counter = ct_precharge) then -- tRPA (precharge all) timing requirement = 12.5ns (p36)
state <= init_refresh_0; -- follow prescribed init sequence (1Gb_DDR2 p87)
counter <= 0;
else
counter <= counter + 1;
end if;
-----------------------------------------------------
-- refresh 0
-----------------------------------------------------
when init_refresh_0 =>
SDRAM_BA <= "000"; -- REFRESH command
SDRAM_A <= "00010000000000"; -- A10 actually has no effect
COMMAND <= CMD_REFRESH;
counter <= 0;
state <= init_refresh_0_done;
when init_refresh_0_done =>
SDRAM_BA <= "000";
SDRAM_A <= "00000000000000";
COMMAND <= CMD_NOP;
if (counter = ct_refresh) then -- tRFC (REFRESH interval) = 127.5ns (p37)
state <= init_refresh_1; -- follow prescribed init sequence (1Gb_DDR2 p87)
counter <= 0;
else
counter <= counter + 1;
end if;
-----------------------------------------------------
-- refresh 1
-----------------------------------------------------
when init_refresh_1 => -- two or more refresh commands are required (note 10, p89)
SDRAM_BA <= "000";
SDRAM_A <= "00010000000000";
COMMAND <= CMD_REFRESH;
counter <= 0;
state <= init_refresh_1_done;
when init_refresh_1_done =>
SDRAM_BA <= "000";
SDRAM_A <= "00000000000000";
COMMAND <= CMD_NOP;
if (counter = ct_refresh) then
state <= init_mode_0_2; -- follow prescribed init sequence (1Gb_DDR2 p87)
counter <= 0;
else
counter <= counter + 1;
end if;
-----------------------------------------------------
-- init_mode 0 Register 2nd
-----------------------------------------------------
when init_mode_0_2 =>
SDRAM_BA <= "000"; -- Mode register
SDRAM_A <= "0001000" & reg_CAS & "0010"; --same settings EXCEPT do not reset the DLL
COMMAND <= CMD_LOAD_MODE;
counter <= 0;
state <= init_mode_0_2_done;
when init_mode_0_2_done =>
SDRAM_BA <= "000";
SDRAM_A <= "00000000000000";
COMMAND <= CMD_NOP;
if (counter = 1) then -- tMRD timing requirement is 2 clock cycles (p37)
state <= init_mode_1_2; -- follow prescribed init sequence (1Gb_DDR2 p87)
counter <= 0;
else
counter <= counter + 1;
end if;
-----------------------------------------------------
-- init_mode 1 Register 2nd
-----------------------------------------------------
when init_mode_1_2 =>
SDRAM_BA <= "001"; -- EMR 1
SDRAM_A <= "00011110000100"; -- Default OCD / DQS# disable / RTT = 75 Ohm
-- See 1GB_DDR p81 for register definition
COMMAND <= CMD_LOAD_MODE;
counter <= 0;
state <= init_mode_1_2_done;
when init_mode_1_2_done =>
SDRAM_BA <= "000";
SDRAM_A <= "00000000000000";
COMMAND <= CMD_NOP;
if (counter = 1) then -- tMRD timing requirement is 2 clock cycles (p37)
state <= init_mode_1_3; -- follow prescribed init sequence (1Gb_DDR2 p87)
counter <= 0;
else
counter <= counter + 1;
end if;
-----------------------------------------------------
-- init_mode 1 Register 3rd
-----------------------------------------------------
when init_mode_1_3 =>
SDRAM_BA <= "001"; -- EMR 1
SDRAM_A <= "00010000000100"; -- Exit OCD / DQS# disable / RTT = 75 Ohm
-- "00010001000100" -- Exit OCD / DQS# disable / RTT = 75 Ohm
COMMAND <= CMD_LOAD_MODE;
counter <= 0;
state <= init_mode_1_3_done;
when init_mode_1_3_done =>
SDRAM_BA <= "000";
SDRAM_A <= "00000000000000";
COMMAND <= CMD_NOP;
if (counter = 20) then -- tMRD timing requirement is 2 clock cycles (p37)
if (wr_we /= "0000") then
state <= idle; --write_0;
counter <= 0;
end if;
else
counter <= counter + 1;
end if;
-----------------------------------------------------
-- IDLE
-----------------------------------------------------
when idle =>
COMMAND <= CMD_NOP;
wr_ack <= '0';
rd_valid <= '0';
dm_write <= not wr_we;
SDRAM_dq_out <= wr_dat_64(31 downto 0);
counter <= 0;
SDRAM_A <= '0' & wrrd_ras_add; -- Row address in A[12:0] (8K) - 1Gb_DDR2 p2
if refresh = '1' then
state <= refresh_0;
elsif (wr_we /= "0000") OR
(rd_re = '1') then
SDRAM_BA <= wrrd_ba_add; -- Bank address in BA[2:0] (8) - 1Gb_DDR2 p2
COMMAND <= CMD_ACTIVATE;
state <= bank_0;
bank_active <= wrrd_ba_add; -- save the activating bank (to detect a change)
bank_row_active <= '0' & wrrd_ras_add; -- save the activating row (to detect a change)
-- ACTIVE to PRECHARGE delay tRAS = 70us MAX (p36) : has this been considered?
end if;
-----------------------------------------------------
-- Bank Active
-----------------------------------------------------
when bank_0 => -- first state after activating a bank
COMMAND <= CMD_NOP;
SDRAM_A <= "00000000000000";
if (counter = ct_RCD) then
state <= active;
counter <= 0;
else
counter <= counter + 1;
end if;
-----------------------------------------------------
-- Bank Active Done
-----------------------------------------------------
--when bank_done =>
-- COMMAND <= CMD_NOP;
-- state <= active; -- tRCD (ROW to COLUMN delay) = 12.5 ns
-----------------------------------------------------
-- Active
-----------------------------------------------------
when active => -- Command to Bank n, 1Gb_DDDR2 p71
COMMAND <= CMD_NOP;
wr_ack <= '0';
rd_valid <= '0';
dm_write <= not wr_we_8(3 downto 0);
SDRAM_dq_out <= wr_dat_64(31 downto 0);
counter <= 0;
SDRAM_A <= "00000000000000";
SDRAM_A <= "0000" & wrrd_cas_add(8 downto 0) & '0'; -- For READ/WRITE column address in A[9:0] (1K) - MT47H64M16HR-25E is WORD addressable- 1Gb_DDR2 p2
-- For a PRECHARGE operation only A[10] is significant and we require A[10] = '0' for single bank
-----------------------------------------------------
-- Refresh handling
-----------------------------------------------------
if (refresh = '1') then
--SDRAM_A <= "00000000000000"; -- PRECHARGE
COMMAND <= CMD_PRECHARGE;
state <= precharge_0;
-----------------------------------------------------
-- Bank handling
-----------------------------------------------------
elsif( (wr_we /= "0000") OR
(rd_re = '1') ) AND
( (NOT (bank_active = wrrd_ba_add)) OR -- changing bank
(NOT (bank_row_active(12 downto 0) = wrrd_ras_add)) ) then -- changing row
--SDRAM_A <= "00000000000000";
COMMAND <= CMD_PRECHARGE;
state <= precharge_0;
-----------------------------------------------------
-- CAS handling
-----------------------------------------------------
elsif (wr_we /= "0000") OR
(rd_re = '1') then
if (wr_we /= "0000") then
COMMAND <= CMD_WRITE;
state <= write_1;
else
state <= read_0;
COMMAND <= CMD_READ;
rd_ack <= '1';
end if;
end if;
-----------------------------------------------------
-- Precharge All Delay
-----------------------------------------------------
when precharge_0 => -- tRPA (precharge all) timing requirement = 12.5ns (p36)
COMMAND <= CMD_NOP;
SDRAM_A <= "00000000000000";
counter <= counter + 1;
if (counter = ct_precharge) then
counter <= 0;
if (refresh = '1') then
state <= refresh_0;
else
state <= idle;
end if;
end if;
-----------------------------------------------------
-- Precharge All Done
-----------------------------------------------------
--when precharge_done =>
-- COMMAND <= CMD_NOP;
-- counter <= counter + 1;
-- if (counter = 0) then
-- if (refresh = '1') then
-- state <= refresh_0;
-- else
-- state <= idle;
-- end if;
-- end if;
-----------------------------------------------------
-- Refresh All Delay
-----------------------------------------------------
when refresh_0 =>
COMMAND <= CMD_REFRESH;
SDRAM_A <= "00000000000000";
ref_ack <= '1';
state <= refresh_1;
counter <= 0;
when refresh_1 =>
COMMAND <= CMD_NOP;
SDRAM_A <= "00000000000000";
ref_ack <= '0';
counter <= counter + 1;
if (counter = ct_refresh) then -- tRFC = refresh-to-refresh (or refresh-to-activate) = 127.5 ns
counterRefresh <= counterRefresh + 1;
if counterRefresh = refreshCount then
counterRefresh <= 0;
state <= idle;
else
state <= refresh_0;
end if;
end if;
-----------------------------------------------------
-- Write 0
-----------------------------------------------------
--when write_0 => -- SDRAM registers WRITE command
-- COMMAND <= CMD_NOP;
-- state <= write_1;
-----------------------------------------------------
-- Write 1
-----------------------------------------------------
when write_1 =>
COMMAND <= CMD_NOP;
SDRAM_A <= "00000000000000";
--dqs_write <= '1';
if (counter = ct_CAS) then
state <= write_2;
counter <= 0;
else
counter <= counter + 1;
end if;
-----------------------------------------------------
-- Write 2
-----------------------------------------------------
when write_2 => -- 4n prefectch with x16 requires a second longword
dq_write <= '1';
COMMAND <= CMD_NOP;
SDRAM_A <= "00000000000000";
SDRAM_dq_out <= wr_dat_64(63 downto 32);
dm_write <= not wr_we_8(7 downto 4); -- dm is output through the DDR interface
state <= write_3; -- however the last 32 bits are not presented by the controller
-----------------------------------------------------
-- Write 3
-----------------------------------------------------
when write_3 =>
COMMAND <= CMD_NOP;
SDRAM_A <= "00000000000000";
state <= write_4;
-----------------------------------------------------
-- Write 4
-----------------------------------------------------
when write_4 =>
dq_write <= '0';
wr_ack <= '1';
COMMAND <= CMD_NOP;
SDRAM_A <= "00000000000000";
--dqs_write <= '0';
counter <= 0;
state <= write_5;
-----------------------------------------------------
-- Write 4
-----------------------------------------------------
when write_5 =>
wr_ack <= '0';
COMMAND <= CMD_NOP;
SDRAM_A <= "00000000000000";
counter <= counter + 1;
if (counter = ct_WR) then -- tWR Write Recovery time 15ns
state <= active;
end if;
-----------------------------------------------------
-- Read 0
-----------------------------------------------------
when read_0 => -- SDRAM registers READ command
SDRAM_A <= "00000000000000";
COMMAND <= CMD_NOP;
if (counter = ct_CAS) then
state <= read_1;
counter <= 0;
else
counter <= counter + 1;
end if;
rd_ack <= '0';
-----------------------------------------------------
-- Read 1
-----------------------------------------------------
when read_1 =>
SDRAM_A <= "00000000000000";
COMMAND <= CMD_NOP;
state <= read_2;
-----------------------------------------------------
-- Read 2
-----------------------------------------------------
when read_2 =>
SDRAM_A <= "00000000000000";
COMMAND <= CMD_NOP;
state <= read_3;
-----------------------------------------------------
-- Read 3
-----------------------------------------------------
when read_3 =>
SDRAM_A <= "00000000000000";
COMMAND <= CMD_NOP;
state <= read_3b;
when read_3b =>
SDRAM_A <= "00000000000000";
COMMAND <= CMD_NOP;
state <= read_4;
-----------------------------------------------------
-- Read 3
-----------------------------------------------------
when read_4 =>
SDRAM_A <= "00000000000000";
COMMAND <= CMD_NOP;
rd_dat_r(31 downto 0) <= SDRAM_dq_in_reg; -- register data in - low word of burst
state <= read_5;
when read_5 =>
SDRAM_A <= "00000000000000";
COMMAND <= CMD_NOP;
rd_dat_r(63 downto 32) <= SDRAM_dq_in_reg; -- register data in - high word of burst
rd_valid <= '1';
state <= active;
-----------------------------------------------------
-- Read Done
-----------------------------------------------------
--when read_done => -- IDDR buffer has registered signal at the output
-- COMMAND <= CMD_NOP;
-- rd_valid <= '1'; -- "rd_dat <= SDRAM_dq_in" is made as a concurrent statement and rd_dat is not registered
-- state <= active; -- keep ROW open and return to ACTIVE state (next access likely on same row)
-- -- 4n prefetch with x16 yields a 64 bit word, the latter 32 bits currently ignored
--
-----------------------------------------------------
-- Others
-----------------------------------------------------
when others =>
end case;
end if;
end process;
end Struct;
|
gpl-2.0
|
783fc32fcc7473bcf2f0cd49ad340e4a
| 0.530259 | 3.563375 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
testbench/afifo_ptr_tb.vhd
| 1 | 1,057 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.avblabs_common_pkg.all;
entity afifo_ptr_tb is
end;
architecture sym of afifo_ptr_tb is
signal rst : std_logic := '1';
signal clk : std_logic := '0';
signal clk_en : std_logic := '1';
signal ptr : std_logic_vector(4 downto 0);
signal addr : unsigned(ptr'left - 1 downto 0);
begin
PTR_0 : entity work.afifo_ptr
generic map (
PTR_WIDTH => ptr'length
)
port map (
clk => clk,
rst => rst,
clk_en => clk_en,
ptr => ptr,
addr => addr,
ptr_async => (others => '0'),
ptr_sync => open
);
process
begin
wait for 8 ns;
clk <= '0';
wait for 8 ns;
clk <= '1';
clk_en <= '0';
wait for 8 ns;
clk <= '0';
wait for 8 ns;
clk <= '1';
clk_en <= '1';
end process;
process
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
rst <= '0';
--
wait;
end process;
end;
|
gpl-3.0
|
7b784e7a5dd6379eb6f594eb5d43c749
| 0.59508 | 2.528708 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
unici_core_burst_1.vhd
| 1 | 21,988 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
--Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--
--Burst adapter parameters:
--adapter is mastered by: pcie_compiler_0/Rx_Interface
--adapter masters: avalon64_to_avalon8_0/avalon_slave_0
--asp_debug: 0
--byteaddr_width: 21
--ceil_data_width: 64
--data_width: 64
--dbs_shift: 0
--dbs_upstream_burstcount_width: 10
--downstream_addr_shift: 3
--downstream_burstcount_width: 1
--downstream_max_burstcount: 1
--downstream_pipeline: 0
--dynamic_slave: 1
--master_always_burst_max_burst: 0
--master_burst_on_burst_boundaries_only: 0
--master_data_width: 64
--master_interleave: 0
--master_linewrap_bursts: 0
--nativeaddr_width: 18
--slave_always_burst_max_burst: 0
--slave_burst_on_burst_boundaries_only: 0
--slave_interleave: 0
--slave_linewrap_bursts: 0
--upstream_burstcount: upstream_burstcount
--upstream_burstcount_width: 10
--upstream_max_burstcount: 512
--zero_address_width: 0
entity unici_core_burst_1 is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal downstream_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal downstream_readdatavalid : IN STD_LOGIC;
signal downstream_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal upstream_address : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
signal upstream_burstcount : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal upstream_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal upstream_debugaccess : IN STD_LOGIC;
signal upstream_nativeaddress : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal upstream_read : IN STD_LOGIC;
signal upstream_write : IN STD_LOGIC;
signal upstream_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal downstream_address : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
signal downstream_arbitrationshare : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal downstream_burstcount : OUT STD_LOGIC;
signal downstream_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal downstream_debugaccess : OUT STD_LOGIC;
signal downstream_nativeaddress : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
signal downstream_read : OUT STD_LOGIC;
signal downstream_write : OUT STD_LOGIC;
signal downstream_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal upstream_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal upstream_readdatavalid : OUT STD_LOGIC;
signal upstream_waitrequest : OUT STD_LOGIC
);
end entity unici_core_burst_1;
architecture europa of unici_core_burst_1 is
signal address_offset : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal atomic_counter : STD_LOGIC;
signal current_upstream_address : STD_LOGIC_VECTOR (20 DOWNTO 0);
signal current_upstream_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal current_upstream_read : STD_LOGIC;
signal current_upstream_write : STD_LOGIC;
signal data_counter : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal downstream_address_base : STD_LOGIC_VECTOR (20 DOWNTO 0);
signal downstream_burstdone : STD_LOGIC;
signal downstream_write_reg : STD_LOGIC;
signal enable_state_change : STD_LOGIC;
signal fifo_empty : STD_LOGIC;
signal internal_downstream_burstcount : STD_LOGIC;
signal internal_downstream_read : STD_LOGIC;
signal internal_downstream_write : STD_LOGIC;
signal internal_upstream_waitrequest : STD_LOGIC;
signal max_burst_size : STD_LOGIC;
signal p1_atomic_counter : STD_LOGIC;
signal p1_fifo_empty : STD_LOGIC;
signal p1_state_busy : STD_LOGIC;
signal p1_state_idle : STD_LOGIC;
signal pending_register_enable : STD_LOGIC;
signal pending_upstream_read : STD_LOGIC;
signal pending_upstream_read_reg : STD_LOGIC;
signal pending_upstream_write : STD_LOGIC;
signal pending_upstream_write_reg : STD_LOGIC;
signal read_address_offset : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal read_update_count : STD_LOGIC;
signal read_write_dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal registered_read_write_dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal registered_upstream_address : STD_LOGIC_VECTOR (20 DOWNTO 0);
signal registered_upstream_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal registered_upstream_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal registered_upstream_nativeaddress : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal registered_upstream_read : STD_LOGIC;
signal registered_upstream_write : STD_LOGIC;
signal state_busy : STD_LOGIC;
signal state_idle : STD_LOGIC;
signal sync_nativeaddress : STD_LOGIC;
signal transactions_remaining : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal transactions_remaining_reg : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal update_count : STD_LOGIC;
signal upstream_burstdone : STD_LOGIC;
signal upstream_read_run : STD_LOGIC;
signal upstream_write_run : STD_LOGIC;
signal write_address_offset : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal write_update_count : STD_LOGIC;
begin
sync_nativeaddress <= or_reduce(upstream_nativeaddress);
--downstream, which is an e_avalon_master
--upstream, which is an e_avalon_slave
upstream_burstdone <= A_WE_StdLogic((std_logic'(current_upstream_read) = '1'), ((to_std_logic(((transactions_remaining = (std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))))) AND internal_downstream_read) AND NOT downstream_waitrequest), ((to_std_logic((((std_logic_vector'("00000000000000000000000") & (transactions_remaining)) = (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(atomic_counter))) + std_logic_vector'("000000000000000000000000000000001")))))) AND internal_downstream_write) AND NOT downstream_waitrequest));
p1_atomic_counter <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(atomic_counter))) + (std_logic_vector'("0") & ((A_WE_StdLogicVector((std_logic'(internal_downstream_read) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount))), std_logic_vector'("00000000000000000000000000000001")))))));
downstream_burstdone <= (((internal_downstream_read OR internal_downstream_write)) AND NOT downstream_waitrequest) AND to_std_logic(((std_logic'(p1_atomic_counter) = std_logic'(internal_downstream_burstcount))));
dbs_adjusted_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(pending_register_enable) = '1'), read_write_dbs_adjusted_upstream_burstcount, registered_read_write_dbs_adjusted_upstream_burstcount);
read_write_dbs_adjusted_upstream_burstcount <= upstream_burstcount;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_read_write_dbs_adjusted_upstream_burstcount <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_read_write_dbs_adjusted_upstream_burstcount <= read_write_dbs_adjusted_upstream_burstcount;
end if;
end if;
end process;
p1_state_idle <= ((state_idle AND NOT upstream_read) AND NOT upstream_write) OR ((((state_busy AND to_std_logic((((std_logic_vector'("0000000000000000000000") & (data_counter)) = std_logic_vector'("00000000000000000000000000000000"))))) AND p1_fifo_empty) AND NOT pending_upstream_read) AND NOT pending_upstream_write);
p1_state_busy <= (state_idle AND ((upstream_read OR upstream_write))) OR (state_busy AND ((((to_std_logic(NOT (((std_logic_vector'("0000000000000000000000") & (data_counter)) = std_logic_vector'("00000000000000000000000000000000")))) OR NOT p1_fifo_empty) OR pending_upstream_read) OR pending_upstream_write)));
enable_state_change <= NOT ((internal_downstream_read OR internal_downstream_write)) OR NOT downstream_waitrequest;
process (clk, reset_n)
begin
if reset_n = '0' then
pending_upstream_read_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((upstream_read AND state_idle)) = '1' then
pending_upstream_read_reg <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
elsif std_logic'(upstream_burstdone) = '1' then
pending_upstream_read_reg <= std_logic'('0');
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
pending_upstream_write_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(upstream_burstdone) = '1' then
pending_upstream_write_reg <= std_logic'('0');
elsif std_logic'((upstream_write AND ((state_idle OR NOT internal_upstream_waitrequest)))) = '1' then
pending_upstream_write_reg <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
state_idle <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(enable_state_change) = '1' then
state_idle <= p1_state_idle;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
state_busy <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(enable_state_change) = '1' then
state_busy <= p1_state_busy;
end if;
end if;
end process;
pending_upstream_read <= pending_upstream_read_reg;
pending_upstream_write <= pending_upstream_write_reg AND NOT upstream_burstdone;
pending_register_enable <= state_idle OR ((((upstream_read OR upstream_write)) AND NOT internal_upstream_waitrequest));
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_read <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_read <= upstream_read;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_write <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_write <= upstream_write;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_burstcount <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_burstcount <= upstream_burstcount;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_address <= std_logic_vector'("000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_address <= upstream_address;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_nativeaddress <= std_logic_vector'("000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_nativeaddress <= upstream_nativeaddress;
end if;
end if;
end process;
current_upstream_read <= registered_upstream_read AND NOT(internal_downstream_write);
current_upstream_write <= registered_upstream_write;
current_upstream_address <= registered_upstream_address;
current_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(pending_register_enable) = '1'), upstream_burstcount, registered_upstream_burstcount);
process (clk, reset_n)
begin
if reset_n = '0' then
atomic_counter <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((internal_downstream_read OR internal_downstream_write)) AND NOT downstream_waitrequest)) = '1' then
atomic_counter <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(downstream_burstdone) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_atomic_counter)))));
end if;
end if;
end process;
read_update_count <= current_upstream_read AND NOT downstream_waitrequest;
write_update_count <= (current_upstream_write AND internal_downstream_write) AND downstream_burstdone;
update_count <= read_update_count OR write_update_count;
transactions_remaining <= A_WE_StdLogicVector((std_logic'(((state_idle AND ((upstream_read OR upstream_write))))) = '1'), dbs_adjusted_upstream_burstcount, transactions_remaining_reg);
process (clk, reset_n)
begin
if reset_n = '0' then
transactions_remaining_reg <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
transactions_remaining_reg <= A_EXT (A_WE_StdLogicVector((std_logic'(((state_idle AND ((upstream_read OR upstream_write))))) = '1'), (std_logic_vector'("0") & (dbs_adjusted_upstream_burstcount)), A_WE_StdLogicVector((std_logic'(update_count) = '1'), ((std_logic_vector'("0") & (transactions_remaining_reg)) - (std_logic_vector'("0000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (transactions_remaining_reg)))), 10);
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
data_counter <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
data_counter <= A_EXT (A_WE_StdLogicVector((std_logic'(((state_idle AND upstream_read) AND NOT internal_upstream_waitrequest)) = '1'), (std_logic_vector'("00000000000000000000000") & (dbs_adjusted_upstream_burstcount)), A_WE_StdLogicVector((std_logic'(downstream_readdatavalid) = '1'), ((std_logic_vector'("00000000000000000000000") & (data_counter)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("00000000000000000000000") & (data_counter)))), 10);
end if;
end process;
max_burst_size <= std_logic'('1');
internal_downstream_burstcount <= Vector_To_Std_Logic(A_WE_StdLogicVector(((transactions_remaining>(std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(max_burst_size))))), (std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(max_burst_size))), transactions_remaining));
downstream_arbitrationshare <= A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), (dbs_adjusted_upstream_burstcount), dbs_adjusted_upstream_burstcount);
process (clk, reset_n)
begin
if reset_n = '0' then
write_address_offset <= std_logic_vector'("000000000");
elsif clk'event and clk = '1' then
write_address_offset <= A_EXT (A_WE_StdLogicVector((std_logic'((state_idle AND upstream_write)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000") & (A_WE_StdLogicVector((std_logic'((((internal_downstream_write AND NOT downstream_waitrequest) AND downstream_burstdone))) = '1'), ((std_logic_vector'("0") & (write_address_offset)) + (std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (write_address_offset)))))), 9);
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
read_address_offset <= std_logic_vector'("000000000");
elsif clk'event and clk = '1' then
read_address_offset <= A_EXT (A_WE_StdLogicVector((std_logic'((state_idle AND upstream_read)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((internal_downstream_read AND NOT downstream_waitrequest))) = '1'), ((std_logic_vector'("0") & (read_address_offset)) + (std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (read_address_offset)))))), 9);
end if;
end process;
downstream_nativeaddress <= A_SRL(registered_upstream_nativeaddress,std_logic_vector'("00000000000000000000000000000011"));
address_offset <= A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), read_address_offset, write_address_offset);
downstream_address_base <= current_upstream_address;
downstream_address <= A_EXT (((std_logic_vector'("0") & (downstream_address_base)) + (std_logic_vector'("0000000000") & ((address_offset & std_logic_vector'("000"))))), 18);
process (clk, reset_n)
begin
if reset_n = '0' then
internal_downstream_read <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((NOT internal_downstream_read OR NOT downstream_waitrequest)) = '1' then
internal_downstream_read <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((state_idle AND upstream_read)) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector(((transactions_remaining = (std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount))))), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_read))))));
end if;
end if;
end process;
upstream_readdatavalid <= downstream_readdatavalid;
upstream_readdata <= downstream_readdata;
fifo_empty <= std_logic'('1');
p1_fifo_empty <= std_logic'('1');
process (clk, reset_n)
begin
if reset_n = '0' then
downstream_write_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((NOT downstream_write_reg OR NOT downstream_waitrequest)) = '1' then
downstream_write_reg <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((state_idle AND upstream_write)) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(((to_std_logic(((transactions_remaining = (std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))))) AND downstream_burstdone))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(downstream_write_reg))))));
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_byteenable <= std_logic_vector'("11111111");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_byteenable <= upstream_byteenable;
end if;
end if;
end process;
internal_downstream_write <= (downstream_write_reg AND upstream_write) AND NOT(internal_downstream_read);
downstream_byteenable <= A_WE_StdLogicVector((std_logic'(downstream_write_reg) = '1'), upstream_byteenable, registered_upstream_byteenable);
downstream_writedata <= upstream_writedata;
upstream_read_run <= state_idle AND upstream_read;
upstream_write_run <= ((state_busy AND upstream_write) AND NOT downstream_waitrequest) AND NOT(internal_downstream_read);
internal_upstream_waitrequest <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(((upstream_read OR current_upstream_read))) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT upstream_read_run))), A_WE_StdLogicVector((std_logic'(current_upstream_write) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT upstream_write_run))), std_logic_vector'("00000000000000000000000000000001"))));
downstream_debugaccess <= upstream_debugaccess;
--vhdl renameroo for output signals
downstream_burstcount <= internal_downstream_burstcount;
--vhdl renameroo for output signals
downstream_read <= internal_downstream_read;
--vhdl renameroo for output signals
downstream_write <= internal_downstream_write;
--vhdl renameroo for output signals
upstream_waitrequest <= internal_upstream_waitrequest;
end europa;
|
gpl-3.0
|
11cc6858ea486bf7521b416d3cfa8d8f
| 0.677324 | 3.995639 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/FPGA SigGen/Source/DACController.vhd
| 1 | 4,331 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generates all control signals for the DACs, multiplexes the values for the
-- dual DAC and adds an offset to the DAC value to make it purely positive.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DACController is
generic
(
-- The width of the DAC values.
data_width: natural
);
port
(
-- The system clock.
clk: in std_logic;
-- The value for DAC channel 0.
channel_0_value : in signed(data_width-1 downto 0);
-- The value for DAC channel 1.
channel_1_value : in signed(data_width-1 downto 0);
-- The DAC´s channel selection signal.
dac_channel_select: out std_logic;
-- The DAC´s write signal.
dac_write: out std_logic;
-- The currently selected DAC value with an offset added.
dac_value : out unsigned(data_width-1 downto 0)
);
end entity;
architecture stdarch of DACController is
type reg_type is record
dac_channel_select, dac_write: std_logic;
dac_value : unsigned(data_width-1 downto 0);
end record;
signal state, next_state: reg_type :=
(
dac_channel_select => '0',
dac_write => '0',
dac_value => (others => '0')
);
begin
--------------------------------------------------------------------------------
-- State register.
--------------------------------------------------------------------------------
state_register: process is
begin
wait until rising_edge(clk);
state <= next_state;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state_logic: process(state, channel_0_value, channel_1_value) is
variable next_dac_value: signed(data_width-1 downto 0);
begin
-- Defaults.
next_state <= state;
-- Switch to the next channel when the write signal gets deactivated.
if (state.dac_write = '1') then
-- Switch to the next channel and get this channel´s value.
if state.dac_channel_select = '0' then
next_state.dac_channel_select <= '1';
next_dac_value := channel_1_value;
else
next_state.dac_channel_select <= '0';
next_dac_value := channel_0_value;
end if;
-- Toggle the sign bit, i.e. convert the signed value to an unsigned value
-- with an offset.
next_dac_value(data_width-1) := not next_dac_value(data_width-1);
next_state.dac_value <= unsigned(next_dac_value);
end if;
-- Toggle the write signal.
next_state.dac_write <= not state.dac_write;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
dac_channel_select <= state.dac_channel_select;
dac_write <= state.dac_write;
dac_value <= state.dac_value;
end architecture;
|
gpl-3.0
|
ca1355018d51c5757f876febc10edc73
| 0.482798 | 4.888262 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
avalon64_to_avalon8.vhd
| 1 | 2,419 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity avalon64_to_avalon8 is
generic (
OUT_ADDR_WIDTH : natural range 1 to natural'high := 15
);
port (
rst : in std_logic;
clk : in std_logic;
-- Avalon-MM slave (input) port
address : in std_logic_vector(OUT_ADDR_WIDTH - 4 downto 0);
byteenable : in std_logic_vector(7 downto 0);
writedata : in std_logic_vector(63 downto 0);
write : in std_logic;
readdata : out std_logic_vector(63 downto 0);
read : in std_logic;
waitrequest : out std_logic;
-- Avalon-MM master (output) port
out_address : out std_logic_vector(OUT_ADDR_WIDTH - 1 downto 0);
out_writedata : out std_logic_vector(7 downto 0);
out_write : out std_logic;
out_readdata : in std_logic_vector(7 downto 0);
out_read : out std_logic;
out_waitrequest : in std_logic
);
end entity;
architecture rtl of avalon64_to_avalon8 is
signal idle_n : std_logic;
signal cntr : unsigned(3 downto 0);
signal shift_reg : std_logic_vector(63 downto 0);
signal writes : std_logic_vector(7 downto 0);
signal reads : std_logic_vector(7 downto 0);
begin
readdata <= shift_reg;
waitrequest <= not cntr(cntr'left) and (read or write);
out_address <= address & std_logic_vector(cntr(2 downto 0));
out_writedata <= shift_reg(7 downto 0);
out_write <= writes(0);
out_read <= reads(0);
process (rst, clk)
variable shift_en : std_logic;
begin
if rising_edge(clk) then
shift_en := out_waitrequest nand (writes(0) or reads(0));
--
idle_n <= not cntr(cntr'left) and (idle_n or read or write);
if cntr(cntr'left) then
cntr <= (others => '0');
elsif shift_en then
cntr <= cntr + unsigned'(0 => idle_n);
end if;
if not idle_n then
shift_reg <= writedata;
writes <= byteenable and (byteenable'range => write);
reads <= byteenable and (byteenable'range => read);
elsif shift_en then
shift_reg <= out_readdata & shift_reg(63 downto 8);
writes <= '0' & writes(7 downto 1);
reads <= '0' & reads(7 downto 1);
end if;
end if;
if rst then
idle_n <= '0';
cntr <= (others => '0');
shift_reg <= (others => '0');
writes <= (others => '0');
reads <= (others => '0');
end if;
end process;
end;
|
gpl-3.0
|
7cd07f0000d33ac9212d1aa5bec58c7a
| 0.643654 | 2.852594 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/flashyLights/ipcore_dir/memmory/example_design/memmory_exdes.vhd
| 1 | 4,324 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: memmory_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY memmory_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END memmory_exdes;
ARCHITECTURE xilinx OF memmory_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT memmory IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : memmory
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
gpl-3.0
|
ba915aec281c26ecfd02bbdc09b813c8
| 0.574931 | 4.852974 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/plasoc_cpu_2_crossbar_wrap_pack.vhd
| 1 | 14,838 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package plasoc_cpu_2_crossbar_wrap_pack is
function clogb2(bit_depth : in integer ) return integer;
component plasoc_cpu_2_crossbar_wrap is
generic
(
axi_address_width : integer := 32;
axi_data_width : integer := 32;
axi_slave_id_width : integer := 0;
axi_master_amount : integer := 5;
axi_slave_amount : integer := 1;
axi_master_base_address : std_logic_vector := X"f0030000f0020000f0010000f000000000000000";
axi_master_high_address : std_logic_vector := X"f003fffff002fffff001fffff000ffffefffffff"
);
port
(
cpu_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_awlen : in std_logic_vector(7 downto 0);
cpu_s_axi_awsize : in std_logic_vector(2 downto 0);
cpu_s_axi_awburst : in std_logic_vector(1 downto 0);
cpu_s_axi_awlock : in std_logic;
cpu_s_axi_awcache : in std_logic_vector(3 downto 0);
cpu_s_axi_awprot : in std_logic_vector(2 downto 0);
cpu_s_axi_awqos : in std_logic_vector(3 downto 0);
cpu_s_axi_awregion : in std_logic_vector(3 downto 0);
cpu_s_axi_awvalid : in std_logic;
cpu_s_axi_awready : out std_logic;
cpu_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cpu_s_axi_wlast : in std_logic;
cpu_s_axi_wvalid : in std_logic;
cpu_s_axi_wready : out std_logic;
cpu_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_bresp : out std_logic_vector(1 downto 0);
cpu_s_axi_bvalid : out std_logic;
cpu_s_axi_bready : in std_logic;
cpu_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_arlen : in std_logic_vector(7 downto 0);
cpu_s_axi_arsize : in std_logic_vector(2 downto 0);
cpu_s_axi_arburst : in std_logic_vector(1 downto 0);
cpu_s_axi_arlock : in std_logic;
cpu_s_axi_arcache : in std_logic_vector(3 downto 0);
cpu_s_axi_arprot : in std_logic_vector(2 downto 0);
cpu_s_axi_arqos : in std_logic_vector(3 downto 0);
cpu_s_axi_arregion : in std_logic_vector(3 downto 0);
cpu_s_axi_arvalid : in std_logic;
cpu_s_axi_arready : out std_logic;
cpu_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_rresp : out std_logic_vector(1 downto 0);
cpu_s_axi_rlast : out std_logic;
cpu_s_axi_rvalid : out std_logic;
cpu_s_axi_rready : in std_logic;
ip_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
ip_m_axi_awlen : out std_logic_vector(7 downto 0);
ip_m_axi_awsize : out std_logic_vector(2 downto 0);
ip_m_axi_awburst : out std_logic_vector(1 downto 0);
ip_m_axi_awlock : out std_logic;
ip_m_axi_awcache : out std_logic_vector(3 downto 0);
ip_m_axi_awprot : out std_logic_vector(2 downto 0);
ip_m_axi_awqos : out std_logic_vector(3 downto 0);
ip_m_axi_awregion : out std_logic_vector(3 downto 0);
ip_m_axi_awvalid : out std_logic;
ip_m_axi_awready : in std_logic;
ip_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
ip_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
ip_m_axi_wlast : out std_logic;
ip_m_axi_wvalid : out std_logic;
ip_m_axi_wready : in std_logic;
ip_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_bresp : in std_logic_vector(1 downto 0);
ip_m_axi_bvalid : in std_logic;
ip_m_axi_bready : out std_logic;
ip_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
ip_m_axi_arlen : out std_logic_vector(7 downto 0);
ip_m_axi_arsize : out std_logic_vector(2 downto 0);
ip_m_axi_arburst : out std_logic_vector(1 downto 0);
ip_m_axi_arlock : out std_logic;
ip_m_axi_arcache : out std_logic_vector(3 downto 0);
ip_m_axi_arprot : out std_logic_vector(2 downto 0);
ip_m_axi_arqos : out std_logic_vector(3 downto 0);
ip_m_axi_arregion : out std_logic_vector(3 downto 0);
ip_m_axi_arvalid : out std_logic;
ip_m_axi_arready : in std_logic;
ip_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
ip_m_axi_rresp : in std_logic_vector(1 downto 0);
ip_m_axi_rlast : in std_logic;
ip_m_axi_rvalid : in std_logic;
ip_m_axi_rready : out std_logic;
cpuid_gpio_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
cpuid_gpio_m_axi_awlen : out std_logic_vector(7 downto 0);
cpuid_gpio_m_axi_awsize : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_awburst : out std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_awlock : out std_logic;
cpuid_gpio_m_axi_awcache : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awprot : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_awqos : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awregion : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awvalid : out std_logic;
cpuid_gpio_m_axi_awready : in std_logic;
cpuid_gpio_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
cpuid_gpio_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
cpuid_gpio_m_axi_wlast : out std_logic;
cpuid_gpio_m_axi_wvalid : out std_logic;
cpuid_gpio_m_axi_wready : in std_logic;
cpuid_gpio_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_bresp : in std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_bvalid : in std_logic;
cpuid_gpio_m_axi_bready : out std_logic;
cpuid_gpio_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
cpuid_gpio_m_axi_arlen : out std_logic_vector(7 downto 0);
cpuid_gpio_m_axi_arsize : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_arburst : out std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_arlock : out std_logic;
cpuid_gpio_m_axi_arcache : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arprot : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_arqos : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arregion : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arvalid : out std_logic;
cpuid_gpio_m_axi_arready : in std_logic;
cpuid_gpio_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
cpuid_gpio_m_axi_rresp : in std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_rlast : in std_logic;
cpuid_gpio_m_axi_rvalid : in std_logic;
cpuid_gpio_m_axi_rready : out std_logic;
int_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_awlen : out std_logic_vector(7 downto 0);
int_m_axi_awsize : out std_logic_vector(2 downto 0);
int_m_axi_awburst : out std_logic_vector(1 downto 0);
int_m_axi_awlock : out std_logic;
int_m_axi_awcache : out std_logic_vector(3 downto 0);
int_m_axi_awprot : out std_logic_vector(2 downto 0);
int_m_axi_awqos : out std_logic_vector(3 downto 0);
int_m_axi_awregion : out std_logic_vector(3 downto 0);
int_m_axi_awvalid : out std_logic;
int_m_axi_awready : in std_logic;
int_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
int_m_axi_wlast : out std_logic;
int_m_axi_wvalid : out std_logic;
int_m_axi_wready : in std_logic;
int_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_bresp : in std_logic_vector(1 downto 0);
int_m_axi_bvalid : in std_logic;
int_m_axi_bready : out std_logic;
int_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_arlen : out std_logic_vector(7 downto 0);
int_m_axi_arsize : out std_logic_vector(2 downto 0);
int_m_axi_arburst : out std_logic_vector(1 downto 0);
int_m_axi_arlock : out std_logic;
int_m_axi_arcache : out std_logic_vector(3 downto 0);
int_m_axi_arprot : out std_logic_vector(2 downto 0);
int_m_axi_arqos : out std_logic_vector(3 downto 0);
int_m_axi_arregion : out std_logic_vector(3 downto 0);
int_m_axi_arvalid : out std_logic;
int_m_axi_arready : in std_logic;
int_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_rresp : in std_logic_vector(1 downto 0);
int_m_axi_rlast : in std_logic;
int_m_axi_rvalid : in std_logic;
int_m_axi_rready : out std_logic;
signal_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
signal_m_axi_awlen : out std_logic_vector(7 downto 0);
signal_m_axi_awsize : out std_logic_vector(2 downto 0);
signal_m_axi_awburst : out std_logic_vector(1 downto 0);
signal_m_axi_awlock : out std_logic;
signal_m_axi_awcache : out std_logic_vector(3 downto 0);
signal_m_axi_awprot : out std_logic_vector(2 downto 0);
signal_m_axi_awqos : out std_logic_vector(3 downto 0);
signal_m_axi_awregion : out std_logic_vector(3 downto 0);
signal_m_axi_awvalid : out std_logic;
signal_m_axi_awready : in std_logic;
signal_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
signal_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
signal_m_axi_wlast : out std_logic;
signal_m_axi_wvalid : out std_logic;
signal_m_axi_wready : in std_logic;
signal_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_bresp : in std_logic_vector(1 downto 0);
signal_m_axi_bvalid : in std_logic;
signal_m_axi_bready : out std_logic;
signal_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
signal_m_axi_arlen : out std_logic_vector(7 downto 0);
signal_m_axi_arsize : out std_logic_vector(2 downto 0);
signal_m_axi_arburst : out std_logic_vector(1 downto 0);
signal_m_axi_arlock : out std_logic;
signal_m_axi_arcache : out std_logic_vector(3 downto 0);
signal_m_axi_arprot : out std_logic_vector(2 downto 0);
signal_m_axi_arqos : out std_logic_vector(3 downto 0);
signal_m_axi_arregion : out std_logic_vector(3 downto 0);
signal_m_axi_arvalid : out std_logic;
signal_m_axi_arready : in std_logic;
signal_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
signal_m_axi_rresp : in std_logic_vector(1 downto 0);
signal_m_axi_rlast : in std_logic;
signal_m_axi_rvalid : in std_logic;
signal_m_axi_rready : out std_logic;
timer_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_awlen : out std_logic_vector(7 downto 0);
timer_m_axi_awsize : out std_logic_vector(2 downto 0);
timer_m_axi_awburst : out std_logic_vector(1 downto 0);
timer_m_axi_awlock : out std_logic;
timer_m_axi_awcache : out std_logic_vector(3 downto 0);
timer_m_axi_awprot : out std_logic_vector(2 downto 0);
timer_m_axi_awqos : out std_logic_vector(3 downto 0);
timer_m_axi_awregion : out std_logic_vector(3 downto 0);
timer_m_axi_awvalid : out std_logic;
timer_m_axi_awready : in std_logic;
timer_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
timer_m_axi_wlast : out std_logic;
timer_m_axi_wvalid : out std_logic;
timer_m_axi_wready : in std_logic;
timer_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_bresp : in std_logic_vector(1 downto 0);
timer_m_axi_bvalid : in std_logic;
timer_m_axi_bready : out std_logic;
timer_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_arlen : out std_logic_vector(7 downto 0);
timer_m_axi_arsize : out std_logic_vector(2 downto 0);
timer_m_axi_arburst : out std_logic_vector(1 downto 0);
timer_m_axi_arlock : out std_logic;
timer_m_axi_arcache : out std_logic_vector(3 downto 0);
timer_m_axi_arprot : out std_logic_vector(2 downto 0);
timer_m_axi_arqos : out std_logic_vector(3 downto 0);
timer_m_axi_arregion : out std_logic_vector(3 downto 0);
timer_m_axi_arvalid : out std_logic;
timer_m_axi_arready : in std_logic;
timer_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_rresp : in std_logic_vector(1 downto 0);
timer_m_axi_rlast : in std_logic;
timer_m_axi_rvalid : in std_logic;
timer_m_axi_rready : out std_logic;
aclk : in std_logic;
aresetn : in std_logic
);
end component;
end;
package body plasoc_cpu_2_crossbar_wrap_pack is
function flogb2(bit_depth : in natural ) return integer is
variable result : integer := 0;
variable bit_depth_buff : integer := bit_depth;
begin
while bit_depth_buff>1 loop
bit_depth_buff := bit_depth_buff/2;
result := result+1;
end loop;
return result;
end function flogb2;
function clogb2 (bit_depth : in natural ) return natural is
variable result : integer := 0;
begin
result := flogb2(bit_depth);
if (bit_depth > (2**result)) then
return(result + 1);
else
return result;
end if;
end function clogb2;
end;
|
mit
|
7e1bf3b602cfd65c6dcd42f01b259a04
| 0.677517 | 2.489597 | false | false | false | false |
arthurbenemann/fpga-bits
|
softcore/softcore.vhd
| 1 | 701 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
entity softcore is port (
clk, RX : in STD_LOGIC;
TX : out STD_LOGIC;
SW : in std_logic_vector(7 downto 0);
LED : out STD_LOGIC_VECTOR (7 downto 0));
end softcore;
architecture Behavioral of softcore is
component microblaze port(
Clk, Reset, UART_Rx : IN STD_LOGIC;
UART_Tx : OUT STD_LOGIC;
GPO1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
GPI1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
GPI1_Interrupt : OUT STD_LOGIC);
end component;
begin
core0 : microblaze port map(
Clk => Clk, Reset => '0',
UART_Rx => RX, UART_Tx => TX,
GPO1 => LED,
GPI1 => SW,
GPI1_Interrupt => open
);
end Behavioral;
|
gpl-3.0
|
c9bc6eb1c9ee289ed0da3136aeb77b7a
| 0.649073 | 2.957806 | false | false | false | false |
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