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float64 0.25
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classes | has_no_keywords
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class |
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arthurTemporim/SD_SS
|
pre/6/projetos/projeto2/projeto2.vhd
| 1 | 2,232 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity projeto2 is
port (
a : in std_logic_vector (3 downto 0) := "0001"; -- Entrada A.
b : in std_logic_vector (3 downto 0) := "0000"; -- Entrada B.
sel : in std_logic := '0'; -- Seletora de displays.
clk : in std_logic := '0'; -- Clock.
display1 : out std_logic_vector (6 downto 0);
display2 : out std_logic_vector (6 downto 0)
);
end projeto2;
architecture Behavioral of projeto2 is
signal saida_mux : std_logic_vector (3 downto 0);
signal bcd : std_logic_vector (6 downto 0); -- BCD.
begin
-- Mux 8->4.
process (a,b, clk)
begin
if (clk = '0') then
saida_mux <= a;
else
saida_mux <= b;
end if;
end process;
-- BCD.
process (a,b,clk, saida_mux, bcd)
begin
if (saida_mux = "0000") then -- 0
bcd <= "1111110";
elsif (saida_mux = "0001") then -- 1
bcd <= "0110000";
elsif (saida_mux = "0010") then -- 2
bcd <= "1101101";
elsif (saida_mux = "0011") then -- 3
bcd <= "1111001";
elsif (saida_mux = "0100") then -- 4
bcd <= "0110010";
elsif (saida_mux = "0101") then -- 5
bcd <= "1011010";
elsif (saida_mux = "0110") then -- 6
bcd <= "1011111";
elsif (saida_mux = "0111") then -- 7
bcd <= "1110000";
elsif (saida_mux = "1000") then -- 8
bcd <= "1111111";
elsif (saida_mux = "1001") then -- 9
bcd <= "1111011";
elsif (saida_mux = "1010") then -- A
bcd <= "1110111";
elsif (saida_mux = "1011") then -- B
bcd <= "0011111";
elsif (saida_mux = "1100") then -- C
bcd <= "1001110";
elsif (saida_mux = "1101") then -- D
bcd <= "0111101";
elsif (saida_mux = "1110") then -- E
bcd <= "1001111";
else
bcd <= "1000111"; -- Caso defaul -> 'F'
end if;
end process;
-- Mux 1->2.
process (bcd, clk, sel)
begin
if (clk = '0' and sel = '0') then -- Se sel = 0 então mostra B.
display2 <= bcd; -- Mostra B no display.
display1 <= "00000000"; -- Desliga A.
elsif (clk = '1' and sel = '1') then -- Se sel = 1 então mostra A.
display1 <= bcd; -- Mostra A no display.
display2 <= "00000000"; -- Desliga B.
else
-- Caso inesperado.
display1 <= "00000000"; -- Desliga A.
display2 <= "00000000"; -- Desliga B.
end if;
end process;
end Behavioral;
|
mit
|
b94021d39df490eb705a37965f9b0750
| 0.572197 | 2.712895 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
gpout.vhd
| 1 | 1,560 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gpout is
generic (
POLARITY_MASK : natural := 0
);
port (
rst : in std_logic := '0';
clk : in std_logic;
--
address : in std_logic_vector(1 downto 0);
byteenable : in std_logic_vector(1 downto 0);
writedata : in std_logic_vector(15 downto 0);
write : in std_logic;
readdata : out std_logic_vector(15 downto 0);
--
pins : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of gpout is
constant REG_IO : std_logic_vector(address'range) := "00";
constant REG_IO_TOGGLE : std_logic_vector(address'range) := "01";
constant REG_IO_SET : std_logic_vector(address'range) := "10";
constant REG_IO_CLEAR : std_logic_vector(address'range) := "11";
signal latch : std_logic_vector(pins'range);
begin
process (rst, clk)
begin
if rising_edge(clk) then
for i in latch'range loop
if write and byteenable(i / 8) then
if address = "00" then
latch(i) <= writedata(i);
elsif writedata(i) then
if not address(1) then
latch(i) <= not latch(i);
else
latch(i) <= not address(0);
end if;
end if;
end if;
end loop;
end if;
if rst then
latch <= (others => '0');
end if;
end process;
readdata <= latch;
pins <= latch xor std_logic_vector(to_unsigned(POLARITY_MASK, 16));
end architecture;
|
gpl-3.0
|
459d781931df67e1f80e5872dec5260d
| 0.640385 | 2.85192 | false | false | false | false |
arthurbenemann/fpga-bits
|
fm_transmitter/topModule.vhd
| 1 | 2,718 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity topModule is Port (
CLK : in STD_LOGIC;
GPIO0,AUDIO1_RIGHT,AUDIO1_LEFT : out STD_LOGIC;
SEVENSEG_SEG : out std_logic_vector(7 downto 0);
SEVENSEG_AN : out std_logic_vector(4 downto 0));
end topModule;
architecture Behavioral of topModule is
component pll port (
CLK_IN1 : in std_logic;
clk_modulator : out std_logic;
clk_32 : out std_logic
);
end component;
signal audio_clk : std_logic;
signal clk_modulator : std_logic;
signal clk_32 : std_logic;
COMPONENT counter PORT ( -- max count of 236646400
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(27 DOWNTO 0));
END COMPONENT;
signal addr_counter : STD_LOGIC_VECTOR(27 downto 0);
COMPONENT rom_memory PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
END COMPONENT;
signal douta : STD_LOGIC_VECTOR(8 DOWNTO 0);
signal audio_data_unsigned : unsigned(8 downto 0);
signal audio_data_signed : signed(8 downto 0);
COMPONENT audio_dac_8bit PORT(
clk : IN std_logic;
data : IN signed(8 downto 0);
pulseStream : OUT std_logic
);
END COMPONENT;
signal audio_out : std_logic;
COMPONENT fm_modulator PORT(
clk, clk_modulator : IN std_logic;
data : IN signed(8 downto 0);
fm_out : OUT std_logic);
END COMPONENT;
COMPONENT ms_timer PORT(
clk : IN std_logic;
clk_1ms : OUT std_logic);
END COMPONENT;
signal clk_1ms : std_logic;
COMPONENT seven_seg PORT(
display_hex : IN std_logic_vector(15 downto 0);
clk : IN std_logic;
double_dot : IN std_logic;
anodes : OUT std_logic_vector(4 downto 0);
sevenseg : OUT std_logic_vector(7 downto 0));
END COMPONENT;
begin
clock_manager : pll port map (
CLK_IN1 => CLK,
clk_modulator => clk_modulator,
clk_32 => clk_32
);
addr_counter1 : counter PORT MAP (
clk => clk_32,
q => addr_counter
);
waveform_rom : rom_memory PORT MAP (
clka => clk_32,
addra => addr_counter(27 downto 12),
douta => douta
);
audio_data_signed <= signed(douta xor "100000000");
Inst_audio_dac_8bit: audio_dac_8bit PORT MAP(
clk => clk_32,
data => audio_data_signed,
pulseStream => audio_out
);
AUDIO1_LEFT <= audio_out;
AUDIO1_RIGHT <= audio_out;
Inst_fm_modulator: fm_modulator PORT MAP(
clk => clk_32,
clk_modulator => clk_modulator,
data => audio_data_signed,
fm_out => GPIO0
);
Inst_ms_timer: ms_timer PORT MAP(
clk => clk_32,
clk_1ms => clk_1ms
);
Inst_seven_seg: seven_seg PORT MAP(
display_hex => x"f947",
clk => clk_1ms,
double_dot => '0',
anodes => SEVENSEG_AN,
sevenseg => SEVENSEG_SEG
);
end Behavioral;
|
gpl-3.0
|
556404cbb06c4e9670eea1aa53d78d80
| 0.657469 | 2.922581 | false | false | false | false |
russdill/pybis
|
samples/ideal_driver.vhd
| 1 | 2,219 |
library IEEE;
use IEEE.math_real.all;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.energy_systems.all;
entity driver_ideal is
generic (r_open : resistance := 1000.0;
r_closed : resistance := 5.0;
trans_time : real := 500.0e-12;
cap : capacitance := 5.1e-12;
delay : time := 0 ns);
port(
dig_input : in std_logic;
terminal v_pwr : electrical;
terminal v_gnd : electrical;
terminal v_driver : electrical
);
end driver_ideal;
architecture linear of driver_ideal is
signal d_input_inv : std_logic;
signal r_pu_sig : resistance := r_open;
signal r_pd_sig : resistance := r_open;
quantity v_pu across i_pu through v_pwr to v_driver;
quantity r_pu : resistance;
quantity v_pd across i_pd through v_driver to v_gnd;
quantity r_pd : resistance;
quantity v_cap across i_cap through v_driver to v_gnd;
quantity v_gc across i_gc through v_gnd to v_driver;
quantity v_pc across i_pc through v_driver to v_pwr;
constant isat : current := 1.0e-14; -- Saturation current [Amps]
constant TempC : real := 27.0; -- Ambient Temperature [Degrees]
constant TempK : real := 273.0 + TempC; -- Temperaure [Kelvin]
constant vt : real := K*TempK/Q; -- Thermal Voltage
begin
d_input_inv <= not dig_input after delay;
DetectPUState: process (dig_input)
begin
if (dig_input'event and dig_input = '0') then
r_pu_sig <= r_open;
elsif (dig_input'event and dig_input = '1') then
r_pu_sig <= r_closed;
end if;
end process DetectPUState;
r_pu == r_pu_sig'ramp(trans_time, trans_time);
v_pu == r_pu*i_pu;
DetectPDState: process (d_input_inv)
begin
if (d_input_inv'event and d_input_inv = '0') then
r_pd_sig <= r_open;
elsif (d_input_inv'event and d_input_inv = '1') then
r_pd_sig <= r_closed;
end if;
end process DetectPDState;
r_pd == r_pd_sig'ramp(trans_time, trans_time);
v_pd == r_pd*i_pd;
v_cap*cap == i_cap'integ;
i_gc == isat*(exp(v_gc/vt) - 1.0);
i_pc == isat*(exp(v_pc/vt) - 1.0);
end linear;
|
lgpl-2.1
|
2d7d531e98519ec1ff177b6e1b47822b
| 0.611537 | 3.002706 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/plasoc_cpu_1_crossbar_wrap_pack.vhd
| 1 | 14,838 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package plasoc_cpu_1_crossbar_wrap_pack is
function clogb2(bit_depth : in integer ) return integer;
component plasoc_cpu_1_crossbar_wrap is
generic
(
axi_address_width : integer := 32;
axi_data_width : integer := 32;
axi_slave_id_width : integer := 0;
axi_master_amount : integer := 5;
axi_slave_amount : integer := 1;
axi_master_base_address : std_logic_vector := X"f0030000f0020000f0010000f000000000000000";
axi_master_high_address : std_logic_vector := X"f003fffff002fffff001fffff000ffffefffffff"
);
port
(
cpu_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_awlen : in std_logic_vector(7 downto 0);
cpu_s_axi_awsize : in std_logic_vector(2 downto 0);
cpu_s_axi_awburst : in std_logic_vector(1 downto 0);
cpu_s_axi_awlock : in std_logic;
cpu_s_axi_awcache : in std_logic_vector(3 downto 0);
cpu_s_axi_awprot : in std_logic_vector(2 downto 0);
cpu_s_axi_awqos : in std_logic_vector(3 downto 0);
cpu_s_axi_awregion : in std_logic_vector(3 downto 0);
cpu_s_axi_awvalid : in std_logic;
cpu_s_axi_awready : out std_logic;
cpu_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cpu_s_axi_wlast : in std_logic;
cpu_s_axi_wvalid : in std_logic;
cpu_s_axi_wready : out std_logic;
cpu_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_bresp : out std_logic_vector(1 downto 0);
cpu_s_axi_bvalid : out std_logic;
cpu_s_axi_bready : in std_logic;
cpu_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_arlen : in std_logic_vector(7 downto 0);
cpu_s_axi_arsize : in std_logic_vector(2 downto 0);
cpu_s_axi_arburst : in std_logic_vector(1 downto 0);
cpu_s_axi_arlock : in std_logic;
cpu_s_axi_arcache : in std_logic_vector(3 downto 0);
cpu_s_axi_arprot : in std_logic_vector(2 downto 0);
cpu_s_axi_arqos : in std_logic_vector(3 downto 0);
cpu_s_axi_arregion : in std_logic_vector(3 downto 0);
cpu_s_axi_arvalid : in std_logic;
cpu_s_axi_arready : out std_logic;
cpu_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_rresp : out std_logic_vector(1 downto 0);
cpu_s_axi_rlast : out std_logic;
cpu_s_axi_rvalid : out std_logic;
cpu_s_axi_rready : in std_logic;
ip_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
ip_m_axi_awlen : out std_logic_vector(7 downto 0);
ip_m_axi_awsize : out std_logic_vector(2 downto 0);
ip_m_axi_awburst : out std_logic_vector(1 downto 0);
ip_m_axi_awlock : out std_logic;
ip_m_axi_awcache : out std_logic_vector(3 downto 0);
ip_m_axi_awprot : out std_logic_vector(2 downto 0);
ip_m_axi_awqos : out std_logic_vector(3 downto 0);
ip_m_axi_awregion : out std_logic_vector(3 downto 0);
ip_m_axi_awvalid : out std_logic;
ip_m_axi_awready : in std_logic;
ip_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
ip_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
ip_m_axi_wlast : out std_logic;
ip_m_axi_wvalid : out std_logic;
ip_m_axi_wready : in std_logic;
ip_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_bresp : in std_logic_vector(1 downto 0);
ip_m_axi_bvalid : in std_logic;
ip_m_axi_bready : out std_logic;
ip_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
ip_m_axi_arlen : out std_logic_vector(7 downto 0);
ip_m_axi_arsize : out std_logic_vector(2 downto 0);
ip_m_axi_arburst : out std_logic_vector(1 downto 0);
ip_m_axi_arlock : out std_logic;
ip_m_axi_arcache : out std_logic_vector(3 downto 0);
ip_m_axi_arprot : out std_logic_vector(2 downto 0);
ip_m_axi_arqos : out std_logic_vector(3 downto 0);
ip_m_axi_arregion : out std_logic_vector(3 downto 0);
ip_m_axi_arvalid : out std_logic;
ip_m_axi_arready : in std_logic;
ip_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
ip_m_axi_rresp : in std_logic_vector(1 downto 0);
ip_m_axi_rlast : in std_logic;
ip_m_axi_rvalid : in std_logic;
ip_m_axi_rready : out std_logic;
cpuid_gpio_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
cpuid_gpio_m_axi_awlen : out std_logic_vector(7 downto 0);
cpuid_gpio_m_axi_awsize : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_awburst : out std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_awlock : out std_logic;
cpuid_gpio_m_axi_awcache : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awprot : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_awqos : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awregion : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awvalid : out std_logic;
cpuid_gpio_m_axi_awready : in std_logic;
cpuid_gpio_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
cpuid_gpio_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
cpuid_gpio_m_axi_wlast : out std_logic;
cpuid_gpio_m_axi_wvalid : out std_logic;
cpuid_gpio_m_axi_wready : in std_logic;
cpuid_gpio_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_bresp : in std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_bvalid : in std_logic;
cpuid_gpio_m_axi_bready : out std_logic;
cpuid_gpio_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
cpuid_gpio_m_axi_arlen : out std_logic_vector(7 downto 0);
cpuid_gpio_m_axi_arsize : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_arburst : out std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_arlock : out std_logic;
cpuid_gpio_m_axi_arcache : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arprot : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_arqos : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arregion : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arvalid : out std_logic;
cpuid_gpio_m_axi_arready : in std_logic;
cpuid_gpio_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
cpuid_gpio_m_axi_rresp : in std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_rlast : in std_logic;
cpuid_gpio_m_axi_rvalid : in std_logic;
cpuid_gpio_m_axi_rready : out std_logic;
int_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_awlen : out std_logic_vector(7 downto 0);
int_m_axi_awsize : out std_logic_vector(2 downto 0);
int_m_axi_awburst : out std_logic_vector(1 downto 0);
int_m_axi_awlock : out std_logic;
int_m_axi_awcache : out std_logic_vector(3 downto 0);
int_m_axi_awprot : out std_logic_vector(2 downto 0);
int_m_axi_awqos : out std_logic_vector(3 downto 0);
int_m_axi_awregion : out std_logic_vector(3 downto 0);
int_m_axi_awvalid : out std_logic;
int_m_axi_awready : in std_logic;
int_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
int_m_axi_wlast : out std_logic;
int_m_axi_wvalid : out std_logic;
int_m_axi_wready : in std_logic;
int_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_bresp : in std_logic_vector(1 downto 0);
int_m_axi_bvalid : in std_logic;
int_m_axi_bready : out std_logic;
int_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_arlen : out std_logic_vector(7 downto 0);
int_m_axi_arsize : out std_logic_vector(2 downto 0);
int_m_axi_arburst : out std_logic_vector(1 downto 0);
int_m_axi_arlock : out std_logic;
int_m_axi_arcache : out std_logic_vector(3 downto 0);
int_m_axi_arprot : out std_logic_vector(2 downto 0);
int_m_axi_arqos : out std_logic_vector(3 downto 0);
int_m_axi_arregion : out std_logic_vector(3 downto 0);
int_m_axi_arvalid : out std_logic;
int_m_axi_arready : in std_logic;
int_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_rresp : in std_logic_vector(1 downto 0);
int_m_axi_rlast : in std_logic;
int_m_axi_rvalid : in std_logic;
int_m_axi_rready : out std_logic;
signal_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
signal_m_axi_awlen : out std_logic_vector(7 downto 0);
signal_m_axi_awsize : out std_logic_vector(2 downto 0);
signal_m_axi_awburst : out std_logic_vector(1 downto 0);
signal_m_axi_awlock : out std_logic;
signal_m_axi_awcache : out std_logic_vector(3 downto 0);
signal_m_axi_awprot : out std_logic_vector(2 downto 0);
signal_m_axi_awqos : out std_logic_vector(3 downto 0);
signal_m_axi_awregion : out std_logic_vector(3 downto 0);
signal_m_axi_awvalid : out std_logic;
signal_m_axi_awready : in std_logic;
signal_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
signal_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
signal_m_axi_wlast : out std_logic;
signal_m_axi_wvalid : out std_logic;
signal_m_axi_wready : in std_logic;
signal_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_bresp : in std_logic_vector(1 downto 0);
signal_m_axi_bvalid : in std_logic;
signal_m_axi_bready : out std_logic;
signal_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
signal_m_axi_arlen : out std_logic_vector(7 downto 0);
signal_m_axi_arsize : out std_logic_vector(2 downto 0);
signal_m_axi_arburst : out std_logic_vector(1 downto 0);
signal_m_axi_arlock : out std_logic;
signal_m_axi_arcache : out std_logic_vector(3 downto 0);
signal_m_axi_arprot : out std_logic_vector(2 downto 0);
signal_m_axi_arqos : out std_logic_vector(3 downto 0);
signal_m_axi_arregion : out std_logic_vector(3 downto 0);
signal_m_axi_arvalid : out std_logic;
signal_m_axi_arready : in std_logic;
signal_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
signal_m_axi_rresp : in std_logic_vector(1 downto 0);
signal_m_axi_rlast : in std_logic;
signal_m_axi_rvalid : in std_logic;
signal_m_axi_rready : out std_logic;
timer_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_awlen : out std_logic_vector(7 downto 0);
timer_m_axi_awsize : out std_logic_vector(2 downto 0);
timer_m_axi_awburst : out std_logic_vector(1 downto 0);
timer_m_axi_awlock : out std_logic;
timer_m_axi_awcache : out std_logic_vector(3 downto 0);
timer_m_axi_awprot : out std_logic_vector(2 downto 0);
timer_m_axi_awqos : out std_logic_vector(3 downto 0);
timer_m_axi_awregion : out std_logic_vector(3 downto 0);
timer_m_axi_awvalid : out std_logic;
timer_m_axi_awready : in std_logic;
timer_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
timer_m_axi_wlast : out std_logic;
timer_m_axi_wvalid : out std_logic;
timer_m_axi_wready : in std_logic;
timer_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_bresp : in std_logic_vector(1 downto 0);
timer_m_axi_bvalid : in std_logic;
timer_m_axi_bready : out std_logic;
timer_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_arlen : out std_logic_vector(7 downto 0);
timer_m_axi_arsize : out std_logic_vector(2 downto 0);
timer_m_axi_arburst : out std_logic_vector(1 downto 0);
timer_m_axi_arlock : out std_logic;
timer_m_axi_arcache : out std_logic_vector(3 downto 0);
timer_m_axi_arprot : out std_logic_vector(2 downto 0);
timer_m_axi_arqos : out std_logic_vector(3 downto 0);
timer_m_axi_arregion : out std_logic_vector(3 downto 0);
timer_m_axi_arvalid : out std_logic;
timer_m_axi_arready : in std_logic;
timer_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_rresp : in std_logic_vector(1 downto 0);
timer_m_axi_rlast : in std_logic;
timer_m_axi_rvalid : in std_logic;
timer_m_axi_rready : out std_logic;
aclk : in std_logic;
aresetn : in std_logic
);
end component;
end;
package body plasoc_cpu_1_crossbar_wrap_pack is
function flogb2(bit_depth : in natural ) return integer is
variable result : integer := 0;
variable bit_depth_buff : integer := bit_depth;
begin
while bit_depth_buff>1 loop
bit_depth_buff := bit_depth_buff/2;
result := result+1;
end loop;
return result;
end function flogb2;
function clogb2 (bit_depth : in natural ) return natural is
variable result : integer := 0;
begin
result := flogb2(bit_depth);
if (bit_depth > (2**result)) then
return(result + 1);
else
return result;
end if;
end function clogb2;
end;
|
mit
|
86c586f7d84f4a82ad55f79f0df6cfa9
| 0.677517 | 2.489597 | false | false | false | false |
maijohnson/comp3601_blue_15s2
|
AudioController/I2CMasterTop.vhdl
| 1 | 2,813 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
ENTITY I2CMasterTop IS
GENERIC(
DEVICE_ADDR : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1101000"
);
PORT(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
start : IN STD_LOGIC;
rd_wr : IN STD_LOGIC;
reg_addr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rd_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
busy : BUFFER STD_LOGIC;
scl : INOUT STD_LOGIC;
sda : INOUT STD_LOGIC
);
END I2CMasterTop;
ARCHITECTURE logic OF I2CMasterTop IS
TYPE machine IS(idle, wr_reg_busy, rd_wr_busy, done);
SIGNAL state : machine;
SIGNAL i2c_busy_prev : STD_LOGIC;
SIGNAL i2c_en : STD_LOGIC;
SIGNAL i2c_rw : STD_LOGIC;
SIGNAL i2c_wr_data : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL i2c_busy : STD_LOGIC;
SIGNAL i2c_rd_data : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL i2c_error : STD_LOGIC;
SIGNAL rd_wr_i : STD_LOGIC;
SIGNAL wr_data_i : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
I2C_Master : entity work.i2c_master
port map(
clk => clk,
reset_n => not rst,
ena => i2c_en,
addr => DEVICE_ADDR,
rw => i2c_rw,
data_wr => i2c_wr_data,
busy => i2c_busy,
data_rd => i2c_rd_data,
ack_error => i2c_error,
sda => sda,
scl => scl
);
--For writing: S,AD+W,RA,WR_DATA,...,P
--For reading: S,AD+W,RA,`S,AD+R,RD_DATA,....,P
PROCESS(clk, rst) BEGIN
IF(rst = '1') THEN
i2c_busy_prev <= '0';
i2c_en <= '0';
i2c_rw <= '1';
i2c_wr_data <= "00000000";
rd_data <= "00000000";
wr_data_i <= "00000000";
busy <= '1';
state <= idle;
ELSIF(clk'EVENT AND clk = '1') THEN
i2c_busy_prev <= i2c_busy;
CASE state IS
WHEN idle =>
IF( i2c_busy = '1' ) THEN
busy <= '1';
ELSIF(start = '1') THEN
busy <= '1';
rd_wr_i <= rd_wr;
i2c_wr_data <= reg_addr;
i2c_rw <= '0';
i2c_en <= '1';
state <= wr_reg_busy;
ELSE
busy <= '0';
END IF;
WHEN wr_reg_busy =>
--Once busy, can setup I2C for reading or writing
IF(i2c_busy_prev = '0' AND i2c_busy = '1') THEN
i2c_rw <= rd_wr_i;
i2c_wr_data <= wr_data_i;
state <= rd_wr_busy;
END IF;
WHEN rd_wr_busy =>
--Once busy, can deassert enable
IF(i2c_busy_prev = '0' AND i2c_busy = '1') THEN
i2c_en <= '0';
state <= done;
END IF;
WHEN done =>
--Once no longer busy, get read data regardless
IF(i2c_busy = '0') THEN
rd_data <= i2c_rd_data;
busy <= '0';
state <= idle;
END IF;
END CASE;
END IF;
END PROCESS;
END logic;
|
mit
|
f4cbb80488bb62349014a8ed447b5b60
| 0.533239 | 2.359899 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
unici_core_burst_0.vhd
| 1 | 21,963 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
--Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--
--Burst adapter parameters:
--adapter is mastered by: pcie_compiler_0/Rx_Interface
--adapter masters: pipeline_bridge_0/s1
--asp_debug: 0
--byteaddr_width: 18
--ceil_data_width: 64
--data_width: 64
--dbs_shift: 0
--dbs_upstream_burstcount_width: 10
--downstream_addr_shift: 3
--downstream_burstcount_width: 1
--downstream_max_burstcount: 1
--downstream_pipeline: 0
--dynamic_slave: 1
--master_always_burst_max_burst: 0
--master_burst_on_burst_boundaries_only: 0
--master_data_width: 64
--master_interleave: 0
--master_linewrap_bursts: 0
--nativeaddr_width: 15
--slave_always_burst_max_burst: 0
--slave_burst_on_burst_boundaries_only: 0
--slave_interleave: 0
--slave_linewrap_bursts: 0
--upstream_burstcount: upstream_burstcount
--upstream_burstcount_width: 10
--upstream_max_burstcount: 512
--zero_address_width: 0
entity unici_core_burst_0 is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal downstream_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal downstream_readdatavalid : IN STD_LOGIC;
signal downstream_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal upstream_address : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal upstream_burstcount : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal upstream_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal upstream_debugaccess : IN STD_LOGIC;
signal upstream_nativeaddress : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal upstream_read : IN STD_LOGIC;
signal upstream_write : IN STD_LOGIC;
signal upstream_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal downstream_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal downstream_arbitrationshare : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal downstream_burstcount : OUT STD_LOGIC;
signal downstream_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal downstream_debugaccess : OUT STD_LOGIC;
signal downstream_nativeaddress : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal downstream_read : OUT STD_LOGIC;
signal downstream_write : OUT STD_LOGIC;
signal downstream_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal upstream_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal upstream_readdatavalid : OUT STD_LOGIC;
signal upstream_waitrequest : OUT STD_LOGIC
);
end entity unici_core_burst_0;
architecture europa of unici_core_burst_0 is
signal address_offset : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal atomic_counter : STD_LOGIC;
signal current_upstream_address : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal current_upstream_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal current_upstream_read : STD_LOGIC;
signal current_upstream_write : STD_LOGIC;
signal data_counter : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal downstream_address_base : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal downstream_burstdone : STD_LOGIC;
signal downstream_write_reg : STD_LOGIC;
signal enable_state_change : STD_LOGIC;
signal fifo_empty : STD_LOGIC;
signal internal_downstream_burstcount : STD_LOGIC;
signal internal_downstream_read : STD_LOGIC;
signal internal_downstream_write : STD_LOGIC;
signal internal_upstream_waitrequest : STD_LOGIC;
signal max_burst_size : STD_LOGIC;
signal p1_atomic_counter : STD_LOGIC;
signal p1_fifo_empty : STD_LOGIC;
signal p1_state_busy : STD_LOGIC;
signal p1_state_idle : STD_LOGIC;
signal pending_register_enable : STD_LOGIC;
signal pending_upstream_read : STD_LOGIC;
signal pending_upstream_read_reg : STD_LOGIC;
signal pending_upstream_write : STD_LOGIC;
signal pending_upstream_write_reg : STD_LOGIC;
signal read_address_offset : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal read_update_count : STD_LOGIC;
signal read_write_dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal registered_read_write_dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal registered_upstream_address : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal registered_upstream_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal registered_upstream_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal registered_upstream_nativeaddress : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal registered_upstream_read : STD_LOGIC;
signal registered_upstream_write : STD_LOGIC;
signal state_busy : STD_LOGIC;
signal state_idle : STD_LOGIC;
signal sync_nativeaddress : STD_LOGIC;
signal transactions_remaining : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal transactions_remaining_reg : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal update_count : STD_LOGIC;
signal upstream_burstdone : STD_LOGIC;
signal upstream_read_run : STD_LOGIC;
signal upstream_write_run : STD_LOGIC;
signal write_address_offset : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal write_update_count : STD_LOGIC;
begin
sync_nativeaddress <= or_reduce(upstream_nativeaddress);
--downstream, which is an e_avalon_master
--upstream, which is an e_avalon_slave
upstream_burstdone <= A_WE_StdLogic((std_logic'(current_upstream_read) = '1'), ((to_std_logic(((transactions_remaining = (std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))))) AND internal_downstream_read) AND NOT downstream_waitrequest), ((to_std_logic((((std_logic_vector'("00000000000000000000000") & (transactions_remaining)) = (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(atomic_counter))) + std_logic_vector'("000000000000000000000000000000001")))))) AND internal_downstream_write) AND NOT downstream_waitrequest));
p1_atomic_counter <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(atomic_counter))) + (std_logic_vector'("0") & ((A_WE_StdLogicVector((std_logic'(internal_downstream_read) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount))), std_logic_vector'("00000000000000000000000000000001")))))));
downstream_burstdone <= (((internal_downstream_read OR internal_downstream_write)) AND NOT downstream_waitrequest) AND to_std_logic(((std_logic'(p1_atomic_counter) = std_logic'(internal_downstream_burstcount))));
dbs_adjusted_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(pending_register_enable) = '1'), read_write_dbs_adjusted_upstream_burstcount, registered_read_write_dbs_adjusted_upstream_burstcount);
read_write_dbs_adjusted_upstream_burstcount <= upstream_burstcount;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_read_write_dbs_adjusted_upstream_burstcount <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_read_write_dbs_adjusted_upstream_burstcount <= read_write_dbs_adjusted_upstream_burstcount;
end if;
end if;
end process;
p1_state_idle <= ((state_idle AND NOT upstream_read) AND NOT upstream_write) OR ((((state_busy AND to_std_logic((((std_logic_vector'("0000000000000000000000") & (data_counter)) = std_logic_vector'("00000000000000000000000000000000"))))) AND p1_fifo_empty) AND NOT pending_upstream_read) AND NOT pending_upstream_write);
p1_state_busy <= (state_idle AND ((upstream_read OR upstream_write))) OR (state_busy AND ((((to_std_logic(NOT (((std_logic_vector'("0000000000000000000000") & (data_counter)) = std_logic_vector'("00000000000000000000000000000000")))) OR NOT p1_fifo_empty) OR pending_upstream_read) OR pending_upstream_write)));
enable_state_change <= NOT ((internal_downstream_read OR internal_downstream_write)) OR NOT downstream_waitrequest;
process (clk, reset_n)
begin
if reset_n = '0' then
pending_upstream_read_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((upstream_read AND state_idle)) = '1' then
pending_upstream_read_reg <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
elsif std_logic'(upstream_burstdone) = '1' then
pending_upstream_read_reg <= std_logic'('0');
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
pending_upstream_write_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(upstream_burstdone) = '1' then
pending_upstream_write_reg <= std_logic'('0');
elsif std_logic'((upstream_write AND ((state_idle OR NOT internal_upstream_waitrequest)))) = '1' then
pending_upstream_write_reg <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
state_idle <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(enable_state_change) = '1' then
state_idle <= p1_state_idle;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
state_busy <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(enable_state_change) = '1' then
state_busy <= p1_state_busy;
end if;
end if;
end process;
pending_upstream_read <= pending_upstream_read_reg;
pending_upstream_write <= pending_upstream_write_reg AND NOT upstream_burstdone;
pending_register_enable <= state_idle OR ((((upstream_read OR upstream_write)) AND NOT internal_upstream_waitrequest));
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_read <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_read <= upstream_read;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_write <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_write <= upstream_write;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_burstcount <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_burstcount <= upstream_burstcount;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_address <= std_logic_vector'("000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_address <= upstream_address;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_nativeaddress <= std_logic_vector'("000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_nativeaddress <= upstream_nativeaddress;
end if;
end if;
end process;
current_upstream_read <= registered_upstream_read AND NOT(internal_downstream_write);
current_upstream_write <= registered_upstream_write;
current_upstream_address <= registered_upstream_address;
current_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(pending_register_enable) = '1'), upstream_burstcount, registered_upstream_burstcount);
process (clk, reset_n)
begin
if reset_n = '0' then
atomic_counter <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((internal_downstream_read OR internal_downstream_write)) AND NOT downstream_waitrequest)) = '1' then
atomic_counter <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(downstream_burstdone) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_atomic_counter)))));
end if;
end if;
end process;
read_update_count <= current_upstream_read AND NOT downstream_waitrequest;
write_update_count <= (current_upstream_write AND internal_downstream_write) AND downstream_burstdone;
update_count <= read_update_count OR write_update_count;
transactions_remaining <= A_WE_StdLogicVector((std_logic'(((state_idle AND ((upstream_read OR upstream_write))))) = '1'), dbs_adjusted_upstream_burstcount, transactions_remaining_reg);
process (clk, reset_n)
begin
if reset_n = '0' then
transactions_remaining_reg <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
transactions_remaining_reg <= A_EXT (A_WE_StdLogicVector((std_logic'(((state_idle AND ((upstream_read OR upstream_write))))) = '1'), (std_logic_vector'("0") & (dbs_adjusted_upstream_burstcount)), A_WE_StdLogicVector((std_logic'(update_count) = '1'), ((std_logic_vector'("0") & (transactions_remaining_reg)) - (std_logic_vector'("0000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (transactions_remaining_reg)))), 10);
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
data_counter <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
data_counter <= A_EXT (A_WE_StdLogicVector((std_logic'(((state_idle AND upstream_read) AND NOT internal_upstream_waitrequest)) = '1'), (std_logic_vector'("00000000000000000000000") & (dbs_adjusted_upstream_burstcount)), A_WE_StdLogicVector((std_logic'(downstream_readdatavalid) = '1'), ((std_logic_vector'("00000000000000000000000") & (data_counter)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("00000000000000000000000") & (data_counter)))), 10);
end if;
end process;
max_burst_size <= std_logic'('1');
internal_downstream_burstcount <= Vector_To_Std_Logic(A_WE_StdLogicVector(((transactions_remaining>(std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(max_burst_size))))), (std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(max_burst_size))), transactions_remaining));
downstream_arbitrationshare <= A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), (dbs_adjusted_upstream_burstcount), dbs_adjusted_upstream_burstcount);
process (clk, reset_n)
begin
if reset_n = '0' then
write_address_offset <= std_logic_vector'("000000000");
elsif clk'event and clk = '1' then
write_address_offset <= A_EXT (A_WE_StdLogicVector((std_logic'((state_idle AND upstream_write)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000") & (A_WE_StdLogicVector((std_logic'((((internal_downstream_write AND NOT downstream_waitrequest) AND downstream_burstdone))) = '1'), ((std_logic_vector'("0") & (write_address_offset)) + (std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (write_address_offset)))))), 9);
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
read_address_offset <= std_logic_vector'("000000000");
elsif clk'event and clk = '1' then
read_address_offset <= A_EXT (A_WE_StdLogicVector((std_logic'((state_idle AND upstream_read)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((internal_downstream_read AND NOT downstream_waitrequest))) = '1'), ((std_logic_vector'("0") & (read_address_offset)) + (std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (read_address_offset)))))), 9);
end if;
end process;
downstream_nativeaddress <= A_SRL(registered_upstream_nativeaddress,std_logic_vector'("00000000000000000000000000000011"));
address_offset <= A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), read_address_offset, write_address_offset);
downstream_address_base <= current_upstream_address;
downstream_address <= A_EXT (((std_logic_vector'("0") & (downstream_address_base)) + (std_logic_vector'("0000000") & ((address_offset & std_logic_vector'("000"))))), 15);
process (clk, reset_n)
begin
if reset_n = '0' then
internal_downstream_read <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((NOT internal_downstream_read OR NOT downstream_waitrequest)) = '1' then
internal_downstream_read <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((state_idle AND upstream_read)) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector(((transactions_remaining = (std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount))))), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_read))))));
end if;
end if;
end process;
upstream_readdatavalid <= downstream_readdatavalid;
upstream_readdata <= downstream_readdata;
fifo_empty <= std_logic'('1');
p1_fifo_empty <= std_logic'('1');
process (clk, reset_n)
begin
if reset_n = '0' then
downstream_write_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((NOT downstream_write_reg OR NOT downstream_waitrequest)) = '1' then
downstream_write_reg <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((state_idle AND upstream_write)) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(((to_std_logic(((transactions_remaining = (std_logic_vector'("000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))))) AND downstream_burstdone))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(downstream_write_reg))))));
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_byteenable <= std_logic_vector'("11111111");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_byteenable <= upstream_byteenable;
end if;
end if;
end process;
internal_downstream_write <= (downstream_write_reg AND upstream_write) AND NOT(internal_downstream_read);
downstream_byteenable <= A_WE_StdLogicVector((std_logic'(downstream_write_reg) = '1'), upstream_byteenable, registered_upstream_byteenable);
downstream_writedata <= upstream_writedata;
upstream_read_run <= state_idle AND upstream_read;
upstream_write_run <= ((state_busy AND upstream_write) AND NOT downstream_waitrequest) AND NOT(internal_downstream_read);
internal_upstream_waitrequest <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(((upstream_read OR current_upstream_read))) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT upstream_read_run))), A_WE_StdLogicVector((std_logic'(current_upstream_write) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT upstream_write_run))), std_logic_vector'("00000000000000000000000000000001"))));
downstream_debugaccess <= upstream_debugaccess;
--vhdl renameroo for output signals
downstream_burstcount <= internal_downstream_burstcount;
--vhdl renameroo for output signals
downstream_read <= internal_downstream_read;
--vhdl renameroo for output signals
downstream_write <= internal_downstream_write;
--vhdl renameroo for output signals
upstream_waitrequest <= internal_upstream_waitrequest;
end europa;
|
gpl-3.0
|
e77c0d7f3d5ae24214426098a40196ba
| 0.677093 | 3.996179 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/FPGA SigGen/Source/UniversalCounter.vhd
| 1 | 7,578 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Measures an external signal´s frequency or period. To do this, this component
-- counts an asynchronous external pulse signal using an internal gate signal or
-- an internal pulse signal using an asynchronous external gate signal. Counting
-- is done using a synchronized gated counter. The counter itself runs in the
-- clock domain of the pulse signal. The gate signal is synchronized to the
-- pulse signal. The outputs also belong to the pulse signal´s clock domain.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library Common;
use work.Globals.all;
entity UniversalCounter is
generic
(
-- The width of the measured frequency or period value.
counter_width: natural := 32;
-- The width of the internal clock divider.
clock_divider_width: natural := 32;
-- '0' for normal operation, '1' to ignore the real system clock
-- frequency when dividing the clock frequency.
clock_divider_test_mode: boolean := false
);
port
(
-- The system clock.
clk: in std_logic;
-- '0' to hold output values, '1' to update them.
update_output: in std_logic;
-- The signal to measure the frequency or the period from.
external_signal: in std_logic;
-- '0' for frequency measurement, '1' for period measurement.
measure_period: in std_logic;
-- A value indicating the clock division mode.
clk_division_mode: in std_logic_vector (3 downto 0);
-- The measured frequency or period value.
value: out unsigned (counter_width-1 downto 0);
-- '1' if an overflow has occurred in the current measurement period.
overflow: out std_logic;
-- Toggles each time a gate event has been successfully detected which
-- indicates that there are proper gate and pulse signals.
ready: out std_logic
--TODO: ready umbenennen und ggf. von toggeln auf Puls umstellen (muss dann aber bis zum Auslesen per SPI gespeichert werden).
);
end entity;
architecture stdarch of UniversalCounter is
-- Gate, pulse, and related signals.
signal external_signal_synced_to_clk: std_logic := '0';
signal internal_signal: std_logic := '0';
signal pulse_signal: std_logic := '0';
signal gate_signal, toggled_gate_signal: std_logic := '0';
signal toggled_gate_detected, toggled_gate_detected_synced_to_clk: std_logic := '0';
begin
--------------------------------------------------------------------------------
-- Instantiate components.
--------------------------------------------------------------------------------
-- Synchronizes the external signal to the system clock. This is necessary when
-- it is used as a gate signal because in this case we must toggle it using clk.
external_synchronizer: entity Common.Synchronizer
generic map
(
pulse_stretcher => false,
nr_of_stages => 2
)
port map
(
clk => clk,
in_async => external_signal,
out_sync => external_signal_synced_to_clk
);
-- Toggles the gate signal so that we can pass it safely to the pulse´s clock
-- domain. There, a dual edge detector will reconstruct the signal.
fast_pulse_toggler: entity Common.Toggler
port map
(
clk => clk,
sigin => gate_signal,
toggled_sigout => toggled_gate_signal
);
-- Generates the pulse or gate signal for the counter.
clock_divider: entity work.CounterClockDivider
generic map
(
clock_divider_width => clock_divider_width,
clock_divider_test_mode => clock_divider_test_mode
)
port map
(
clk => clk,
clk_division_mode => clk_division_mode,
divider_tick => internal_signal
);
-- Counts a pulse signal with respect to a gate signal. This counter runs in the
-- clock domain of the pulse signal. It synchronizes ingoing signals properly but
-- outgoing signals belong to that domain.
counter: entity work.SynchronizedGatedCounter
generic map
(
counter_width => counter_width
)
port map
(
pulse_signal => pulse_signal,
toggled_gate_signal => toggled_gate_signal,
update_output => update_output,
value => value,
overflow => overflow,
toggled_gate_detected => toggled_gate_detected
);
-- Synchronizes the value ready indicator to the system clock.
overflow_synchronizer: entity Common.Synchronizer
generic map
(
pulse_stretcher => false,
nr_of_stages => 2
)
port map
(
clk => clk,
in_async => toggled_gate_detected,
out_sync => toggled_gate_detected_synced_to_clk
);
--------------------------------------------------------------------------------
-- Configuration logic (asynchronous but rarely changed).
--------------------------------------------------------------------------------
-- Connect the external and internal signals to pulse and gate corresponding to
-- the selected signal mode. Note that the two input signals (internal_signal
-- and external_signal) are asynchronous to each other. One of these two signals
-- is selected as the counters pulse (pulse_signal) that also acts as the
-- reference for synchronization. Thus, this switchover must be done asynchronously.
-- But this happens rather seldom and any metastability settles down automatically
-- here. Thus this is ignored.
select_measurement_mode: process (measure_period, internal_signal, external_signal,
external_signal_synced_to_clk) is
begin
if (measure_period = '1') then
-- External gate (synced to clk) and internal pulse.
gate_signal <= external_signal_synced_to_clk;
pulse_signal <= internal_signal;
else
-- Internal gate and external pulse (no sync necessary here).
gate_signal <= internal_signal;
pulse_signal <= external_signal;
end if;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
ready <= toggled_gate_detected_synced_to_clk;
end architecture;
|
gpl-3.0
|
24af21a438467275a6a6ff65a5ccfa3a
| 0.57403 | 4.914397 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/bd/ip/bd_clk_wiz_0_0/bd_clk_wiz_0_0_sim_netlist.vhdl
| 1 | 7,962 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Wed May 03 18:20:15 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/andrewandre/Documents/GitHub/kernel-on-chip/hdl/projects/Nexys4/bd/ip/bd_clk_wiz_0_0/bd_clk_wiz_0_0_sim_netlist.vhdl
-- Design : bd_clk_wiz_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_clk_wiz_0_0_bd_clk_wiz_0_0_clk_wiz is
port (
clk_ref_i : out STD_LOGIC;
aclk : out STD_LOGIC;
sys_clk_i : out STD_LOGIC;
resetn : in STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_clk_wiz_0_0_bd_clk_wiz_0_0_clk_wiz : entity is "bd_clk_wiz_0_0_clk_wiz";
end bd_clk_wiz_0_0_bd_clk_wiz_0_0_clk_wiz;
architecture STRUCTURE of bd_clk_wiz_0_0_bd_clk_wiz_0_0_clk_wiz is
signal aclk_bd_clk_wiz_0_0 : STD_LOGIC;
signal clk_in1_bd_clk_wiz_0_0 : STD_LOGIC;
signal clk_ref_i_bd_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_bd_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_buf_bd_clk_wiz_0_0 : STD_LOGIC;
signal reset_high : STD_LOGIC;
signal sys_clk_i_bd_clk_wiz_0_0 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout3_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_bd_clk_wiz_0_0,
O => clkfbout_buf_bd_clk_wiz_0_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_bd_clk_wiz_0_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_ref_i_bd_clk_wiz_0_0,
O => clk_ref_i
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => aclk_bd_clk_wiz_0_0,
O => aclk
);
clkout3_buf: unisim.vcomponents.BUFG
port map (
I => sys_clk_i_bd_clk_wiz_0_0,
O => sys_clk_i
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 10.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 5.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 20,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 10,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_bd_clk_wiz_0_0,
CLKFBOUT => clkfbout_bd_clk_wiz_0_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_bd_clk_wiz_0_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_ref_i_bd_clk_wiz_0_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => aclk_bd_clk_wiz_0_0,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => sys_clk_i_bd_clk_wiz_0_0,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => reset_high
);
mmcm_adv_inst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => resetn,
O => reset_high
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_clk_wiz_0_0 is
port (
clk_ref_i : out STD_LOGIC;
aclk : out STD_LOGIC;
sys_clk_i : out STD_LOGIC;
resetn : in STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bd_clk_wiz_0_0 : entity is true;
end bd_clk_wiz_0_0;
architecture STRUCTURE of bd_clk_wiz_0_0 is
begin
inst: entity work.bd_clk_wiz_0_0_bd_clk_wiz_0_0_clk_wiz
port map (
aclk => aclk,
clk_in1 => clk_in1,
clk_ref_i => clk_ref_i,
resetn => resetn,
sys_clk_i => sys_clk_i
);
end STRUCTURE;
|
mit
|
bedc455104264ff4b8e526f52fc68930
| 0.627355 | 3.170848 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
fifo_in_8b_sync.vhd
| 1 | 5,612 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_in_8b_sync is
generic (
FIFO_DEPTH : natural range 8 to 64 := 16;
BUS_WIDTH : natural range 16 to 64 := 32
);
port (
rst : in std_logic;
clk : in std_logic;
irq : out std_logic;
-- Avalon-MM 32-bits slave
addr : in std_logic_vector(1 downto 0);
byte_en : in std_logic_vector(3 downto 0) := (others => '1');
in_data : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
out_data : out std_logic_vector(31 downto 0);
rd_en : in std_logic;
wait_req : out std_logic;
-- output stream
st_data : in std_logic_vector(7 downto 0);
st_valid : in std_logic;
st_ready : out std_logic
);
end entity;
architecture RTL of fifo_in_8b_sync is
function log2ceil (arg: natural) return natural is
begin
if arg < 2 then
return 1;
else
return log2ceil(arg / 2) + 1;
end if;
end function;
constant FIFO_ADDR_WIDTH : natural := log2ceil(FIFO_DEPTH - 1);
constant REG_DATA : std_logic_vector(1 downto 0) := "00";
constant REG_CTRL_STAT : std_logic_vector(1 downto 0) := "10";
signal read_ptr : unsigned(FIFO_ADDR_WIDTH downto 0);
signal write_ptr : unsigned(FIFO_ADDR_WIDTH downto 0);
signal not_empty : std_logic;
signal data_rden : std_logic;
signal ctrl_wren : std_logic;
signal read_phase : unsigned(1 downto 0);
signal end_phase : std_logic_vector(2 downto 0);
signal read_not_compl : std_logic;
signal fifo_reset : std_logic;
signal imask : std_logic;
signal ipend : std_logic;
signal fill : unsigned(FIFO_ADDR_WIDTH downto 0);
signal threshold : unsigned(FIFO_ADDR_WIDTH - 1 downto 0);
signal valid_i : std_logic;
signal read_buffer : std_logic_vector(BUS_WIDTH - 1 downto 0);
signal read_data : std_logic_vector(BUS_WIDTH - 1 downto 0);
type mem_t is array(0 to FIFO_DEPTH - 1) of std_logic_vector(7 downto 0);
signal fifo_ram : mem_t;
signal fifo_ram_we : std_logic;
signal fifo_ram_re : std_logic;
signal fifo_ram_d : std_logic_vector(7 downto 0);
signal fifo_ram_q : std_logic_vector(7 downto 0);
attribute ramstyle : string;
attribute ramstyle of fifo_ram : signal is "logic";
begin
-- RAM block logic
process (clk)
begin
if rising_edge(clk) then
if fifo_ram_we = '1' then
fifo_ram(to_integer(write_ptr(FIFO_ADDR_WIDTH - 1 downto 0))) <= fifo_ram_d;
end if;
if fifo_ram_re = '1' then
fifo_ram_q <= fifo_ram(to_integer(read_ptr(FIFO_ADDR_WIDTH - 1 downto 0)));
end if;
end if;
end process;
-- FIFO pointers logic
process (rst, clk)
begin
if rising_edge(clk) then
if fifo_ram_we = '1' then
write_ptr <= write_ptr + 1;
end if;
if fifo_ram_re = '1' then
read_ptr <= read_ptr + 1;
end if;
valid_i <= not_empty or (valid_i and not end_phase(2));
if fifo_reset = '1' then
read_ptr <= (others => '0');
write_ptr <= (others => '0');
valid_i <= '0';
end if;
end if;
if rst = '1' then
read_ptr <= (others => '0');
write_ptr <= (others => '0');
valid_i <= '0';
end if;
end process;
not_empty <= '0' when read_ptr = write_ptr else '1';
fill <= write_ptr - read_ptr when valid_i = '0' else write_ptr - read_ptr + 1;
-- bus interface logic
ipend <= '1' when fill > unsigned('0' & threshold) else '0';
with addr select
out_data <= (BUS_WIDTH - 1 downto 16 => '0') & imask & (14 downto FIFO_ADDR_WIDTH + 8 => '0') & std_logic_vector(threshold) & ipend & (6 downto FIFO_ADDR_WIDTH + 1 => '0') & std_logic_vector(fill) when REG_CTRL_STAT,
read_data when others;
data_rden <= (rd_en and valid_i) when addr = REG_DATA else '0';
ctrl_wren <= (byte_en(1) and wr_en) when addr = REG_CTRL_STAT else '0';
fifo_reset <= ctrl_wren and in_data(14);
with byte_en select
end_phase <= data_rden & "00" when "0001",
data_rden & "01" when "0011",
data_rden & "11" when "1111",
"000" when others;
read_not_compl <= end_phase(2) when read_phase /= unsigned(end_phase(1 downto 0)) else '0';
process (rst, clk)
begin
if rising_edge(clk) then
if ctrl_wren = '1' then
imask <= in_data(15);
threshold <= unsigned(in_data(FIFO_ADDR_WIDTH + 7 downto 8));
end if;
if read_not_compl = '0' then
read_phase <= (others => '0');
else
read_phase <= read_phase + 1;
end if;
if read_not_compl = '1' then
case read_phase(1 downto 0) is
when "00" =>
read_buffer(7 downto 0) <= fifo_ram_q;
when "01" =>
read_buffer(15 downto 8) <= fifo_ram_q;
when "10" =>
read_buffer(23 downto 16) <= fifo_ram_q;
when others =>
read_buffer(31 downto 24) <= fifo_ram_q;
end case;
end if;
end if;
if rst = '1' then
imask <= '0';
threshold <= (others => '0');
read_phase <= (others => '0');
read_buffer <= (others => '0');
end if;
end process;
wait_req <= read_not_compl;
read_data(31 downto 24) <= fifo_ram_q when read_phase(1 downto 0) = 3 else read_buffer(31 downto 24);
read_data(23 downto 16) <= fifo_ram_q when read_phase(1 downto 0) = 2 else read_buffer(23 downto 16);
read_data(15 downto 8) <= fifo_ram_q when read_phase(1 downto 0) = 1 else read_buffer(15 downto 8);
read_data(7 downto 0) <= fifo_ram_q when read_phase(1 downto 0) = 0 else read_buffer(7 downto 0);
fifo_ram_d <= st_data;
fifo_ram_we <= st_valid and not fill(FIFO_ADDR_WIDTH);
fifo_ram_re <= not_empty and (end_phase(2) or not valid_i);
st_ready <= not fill(FIFO_ADDR_WIDTH);
irq <= ipend and imask;
end architecture;
|
gpl-3.0
|
3d5a7d131084f4dac36e3a4aa8220feb
| 0.630078 | 2.694191 | false | false | false | false |
antlr/grammars-v4
|
vhdl/examples/arith.vhd
| 6 | 72,193 |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990,1991,1992 by Synopsys, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_ARITH --
-- --
-- Purpose: --
-- A set of arithemtic, conversion, and comparison functions --
-- for SIGNED, UNSIGNED, SMALL_INT, INTEGER, --
-- STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package std_logic_arith is
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
subtype SMALL_INT is INTEGER range 0 to 1;
----------------
-- add operators
----------------
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: INTEGER) return SIGNED;
function "+"(L: INTEGER; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
---------------------
-- subtract operators
---------------------
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: INTEGER) return SIGNED;
function "-"(L: INTEGER; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
------------------
-- unary operators
------------------
function "+"(L: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED) return SIGNED;
function "-"(L: SIGNED) return SIGNED;
function "ABS"(L: SIGNED) return SIGNED;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR;
---------------------------
-- multiplication operators
---------------------------
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "*"(L: SIGNED; R: SIGNED) return SIGNED;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
-----------------------
-- less_than comparison
-----------------------
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN;
--------------------------------
-- less_than_or_equal comparison
--------------------------------
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN;
--------------------------
-- greater_than comparison
--------------------------
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN;
-----------------------------------
-- greater_than_or_equal comparison
-----------------------------------
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN;
-------------------
-- equal comparison
-------------------
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN;
-----------------------
-- not equal comparison
-----------------------
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN;
------------------
-- shift operators
------------------
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
-----------------------
-- conversion operators
-----------------------
function CONV_INTEGER(ARG: INTEGER) return INTEGER;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER;
function CONV_INTEGER(ARG: SIGNED) return INTEGER;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT;
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED;
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED;
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER) return STD_LOGIC_VECTOR;
----------------------------------------------
-- zero extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- returns STD_LOGIC_VECTOR(SIZE-1 downto 0)
----------------------------------------------
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
----------------------------------------------
-- sign extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- return STD_LOGIC_VECTOR(SIZE-1 downto 0)
----------------------------------------------
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end Std_logic_arith;
library IEEE;
use IEEE.std_logic_1164.all;
package body std_logic_arith is
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
-- synopsys synthesis_off
type tbl_type is array (STD_ULOGIC) of STD_ULOGIC;
constant tbl_BINARY : tbl_type :=
('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X');
-- synopsys synthesis_on
-- synopsys synthesis_off
type tbl_mvl9_boolean is array (STD_ULOGIC) of boolean;
constant IS_X : tbl_mvl9_boolean :=
(true, true, false, false, true, true, false, false, true);
-- synopsys synthesis_on
function MAKE_BINARY(A : STD_ULOGIC) return STD_ULOGIC is
-- synopsys built_in SYN_FEED_THRU
begin
-- synopsys synthesis_off
if (IS_X(A)) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
return ('X');
end if;
return tbl_BINARY(A);
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
-- Type propagation function which returns a signed type with the
-- size of the left arg.
function LEFT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the left arg.
function LEFT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns a signed type with the
-- size of the result of a signed multiplication
function MULT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the result of a unsigned multiplication
function MULT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
function mult(A,B: SIGNED) return SIGNED is
variable BA: SIGNED((A'length+B'length-1) downto 0);
variable PA: SIGNED((A'length+B'length-1) downto 0);
variable AA: SIGNED(A'length downto 0);
variable neg: STD_ULOGIC;
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_TC_OP
-- pragma type_function MULT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
neg := B(B'left) xor A(A'left);
BA := CONV_SIGNED(('0' & ABS(B)),(A'length+B'length));
AA := '0' & ABS(A);
for i in 0 to A'length-1 loop
if AA(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
if (neg= '1') then
return(-PA);
else
return(PA);
end if;
end;
function mult(A,B: UNSIGNED) return UNSIGNED is
variable BA: UNSIGNED((A'length+B'length-1) downto 0);
variable PA: UNSIGNED((A'length+B'length-1) downto 0);
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_UNS_OP
-- pragma type_function MULT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
BA := CONV_UNSIGNED(B,(A'length+B'length));
for i in 0 to A'length-1 loop
if A(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
return(PA);
end;
-- subtract two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function minus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: SIGNED (A'left downto 0);
-- pragma map_to_operator SUB_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function plus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: SIGNED (A'left downto 0);
-- pragma map_to_operator ADD_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- subtract two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_minus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator SUB_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_plus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator ADD_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
function "*"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to mult
begin
return mult(CONV_UNSIGNED(L, L'length),
CONV_UNSIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
begin
return mult(CONV_SIGNED(L, L'length+1),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to plus
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length+1)); -- pragma label mult
end;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
begin
return STD_LOGIC_VECTOR (mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length))); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
begin
return STD_LOGIC_VECTOR (mult(CONV_UNSIGNED(L, L'length),
CONV_UNSIGNED(R, R'length))); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
begin
return STD_LOGIC_VECTOR (mult(CONV_SIGNED(L, L'length+1),
CONV_SIGNED(R, R'length))); -- pragma label mult
end;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
begin
return STD_LOGIC_VECTOR (mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length+1))); -- pragma label mult
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := max(L'length, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := max(L'length + 1, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := max(L'length, R'length + 1);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1);
end;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1);
end;
function "+"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := L'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)) ; -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := R'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length))); -- pragma label plus
end;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label plus
end;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1));
end;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1));
end;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label plus
end;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length))) ; -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length))); -- pragma label plus
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label plus
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_minus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := max(L'length, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := max(L'length + 1, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := max(L'length, R'length + 1);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1);
end;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1);
end;
function "-"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1);
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1);
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (unsigned_minus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length))); -- pragma label minus
end;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label minus
end;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1));
end;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1));
end;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label minus
end;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1));
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1));
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label minus
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label minus
end;
function "+"(L: UNSIGNED) return UNSIGNED is
begin
return L;
end;
function "+"(L: SIGNED) return SIGNED is
begin
return L;
end;
function "-"(L: SIGNED) return SIGNED is
-- pragma label_applies_to minus
begin
return 0 - L; -- pragma label minus
end;
function "ABS"(L: SIGNED) return SIGNED is
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return L;
else
return 0 - L;
end if;
end;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L);
end;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L);
end;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable tmp: SIGNED(L'length-1 downto 0);
begin
tmp := 0 - L; -- pragma label minus
return STD_LOGIC_VECTOR (tmp);
end;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR is
variable tmp: SIGNED(L'length-1 downto 0);
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return STD_LOGIC_VECTOR (L);
else
tmp := 0 - L;
return STD_LOGIC_VECTOR (tmp);
end if;
end;
-- Type propagation function which returns the type BOOLEAN
function UNSIGNED_RETURN_BOOLEAN(A,B: UNSIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns the type BOOLEAN
function SIGNED_RETURN_BOOLEAN(A,B: SIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := FALSE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less_or_equal(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := TRUE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := FALSE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less_or_equal(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := TRUE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_eql(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_EQL
begin
for i in L'range loop
if L(i) /= R(i) then
return FALSE;
end if;
end loop;
return TRUE;
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_neq(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_NEQ
begin
for i in L'range loop
if L(i) /= R(i) then
return TRUE;
end if;
end loop;
return FALSE;
end;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN is
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
constant length: INTEGER := L'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
constant length: INTEGER := R'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN is
constant length: INTEGER := L'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN is
constant length: INTEGER := R'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN is
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
constant length: INTEGER := L'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
constant length: INTEGER := R'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN is
constant length: INTEGER := L'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN is
constant length: INTEGER := R'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
variable sign_bit: STD_ULOGIC;
begin
control := MAKE_BINARY(COUNT);
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := ARG;
sign_bit := ARG(ARG'left);
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => sign_bit);
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function CONV_INTEGER(ARG: INTEGER) return INTEGER is
begin
return ARG;
end;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_UNSIGNED_TO_INTEGER
begin
-- synopsys synthesis_off
assert ARG'length <= 31
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: SIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_SIGNED_TO_INTEGER
begin
-- synopsys synthesis_off
assert ARG'length <= 32
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
if i /= ARG'left then
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
end if;
end if;
end loop;
tmp := MAKE_BINARY(ARG(ARG'left));
if tmp = '1' then
if ARG'length = 32 then
result := (result - 2**30) - 2**30;
else
result := result - (2 ** (ARG'length-1));
end if;
end if;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT is
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_FEED_THRU
begin
-- synopsys synthesis_off
tmp := tbl_BINARY(ARG);
if tmp = '1' then
return 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
else
return 0;
end if;
-- synopsys synthesis_on
end;
-- convert an integer to a unsigned STD_ULOGIC_VECTOR
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED is
variable result: UNSIGNED(SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_UNSIGNED
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED is
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to a 2's complement STD_ULOGIC_VECTOR
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED is
variable result: SIGNED (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED is
subtype rtype is SIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to an STD_LOGIC_VECTOR
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER) return STD_LOGIC_VECTOR is
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER)
return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds: STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
end std_logic_arith;
|
mit
|
067471bfca06708c5b2379bf8fbfaf91
| 0.585929 | 3.900005 | false | false | false | false |
antlr/grammars-v4
|
vhdl/examples/unsigned.vhd
| 5 | 10,600 |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_UNSIGNED --
-- --
-- --
-- Date: 09/11/92 KN --
-- 10/08/92 AMT --
-- --
-- Purpose: --
-- A set of unsigned arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: comparision of same length discrete arrays is defined --
-- by the LRM. This package will "overload" those --
-- definitions --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_UNSIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
end STD_LOGIC_UNSIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_UNSIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) + UNSIGNED(R);
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) - UNSIGNED(R);
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R);
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R);
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + UNSIGNED(L);
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := UNSIGNED(L) * UNSIGNED(R);
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
constant length: INTEGER := maximum(L'length, R'length);
begin
return UNSIGNED(L) < UNSIGNED(R);
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) < R;
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L < UNSIGNED(R);
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) <= UNSIGNED(R);
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) <= R;
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L <= UNSIGNED(R);
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) > UNSIGNED(R);
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) > R;
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L > UNSIGNED(R);
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) >= UNSIGNED(R);
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) >= R;
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L >= UNSIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : UNSIGNED(ARG'range);
begin
result := UNSIGNED(ARG);
return CONV_INTEGER(result);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
-- remove this since it is already in std_logic_arith
--function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
--variable result1 : UNSIGNED (SIZE-1 downto 0);
--variable result2 : STD_LOGIC_VECTOR (SIZE-1 downto 0);
--begin
--result1 := CONV_UNSIGNED(ARG,SIZE);
--return std_logic_vector(result1);
--end;
end STD_LOGIC_UNSIGNED;
|
mit
|
a30e220190294d8a7609e465fc1ee6b0
| 0.587453 | 3.773585 | false | false | false | false |
arthurbenemann/fpga-bits
|
mandelbrot/tb_pixel_gen.vhd
| 1 | 3,875 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:42:20 02/25/2016
-- Design Name:
-- Module Name: C:/Users/Arthur/Documents/GitHub/fpga-bits/mandelbrot_monochromatic/tb_pixel_gen.vhd
-- Project Name: mandelbrot_monochromatic
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: pixel_gen
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_pixel_gen IS
END tb_pixel_gen;
ARCHITECTURE behavior OF tb_pixel_gen IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pixel_gen
PORT(
clk : IN std_logic;
x0 : IN std_logic_vector(17 downto 0);
y0 : IN std_logic_vector(17 downto 0);
color : OUT std_logic_vector(19 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal x0 : std_logic_vector(17 downto 0) := (others => '0');
signal y0 : std_logic_vector(17 downto 0) := (others => '0');
--Outputs
signal color : std_logic_vector(19 downto 0);
-- Clock period definitions
constant clk_period : time := 5 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pixel_gen PORT MAP (
clk => clk,
x0 => x0,
y0 => y0,
color => color
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*100.5;
-- insert stimulus here
x0<= std_logic_vector(to_signed(+2*(2**15),18));
y0<= std_logic_vector(to_signed(+2*(2**15),18));
x0 <= std_logic_vector(to_signed(+1*(2**15),18));
y0 <= std_logic_vector(to_signed(+2*(2**15),18));
wait for clk_period*200;
x0 <= std_logic_vector(to_signed(-1*(2**15),18));
y0 <= std_logic_vector(to_signed(+0*(2**15),18));
wait for clk_period*200;
x0 <= std_logic_vector(to_signed(+0*(2**15),18));
y0 <= std_logic_vector(to_signed(+1*(2**15),18));
wait for clk_period*200;
x0 <= std_logic_vector(to_signed(+0*(2**15),18));
y0 <= std_logic_vector(to_signed(-1*(2**15),18));
wait for clk_period*200;
x0 <= std_logic_vector(to_signed(+1*(2**15),18));
y0 <= std_logic_vector(to_signed(+1*(2**15),18));
wait for clk_period*200;
x0 <= std_logic_vector(to_signed(-1*(2**15),18));
y0 <= std_logic_vector(to_signed(-1*(2**15),18));
wait for clk_period*20;
x0 <= std_logic_vector(to_signed(+1*(2**15),18));
y0 <= std_logic_vector(to_signed(-1*(2**15),18));
wait for clk_period*20;
x0 <= std_logic_vector(to_signed(-1*(2**15),18));
y0 <= std_logic_vector(to_signed(1*(2**15),18));
wait for clk_period*20;
x0 <= std_logic_vector(to_signed(2*(2**15),18));
y0 <= std_logic_vector(to_signed(1*(2**15),18));
wait for clk_period*20;
x0 <= std_logic_vector(to_signed(2*(2**15),18));
y0 <= std_logic_vector(to_signed(2*(2**15),18));
wait for clk_period*20;
wait;
end process;
END;
|
gpl-3.0
|
aee74623822a0ee4ac7054279c654427
| 0.588387 | 3.173628 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
int_ctrl_0.vhd
| 1 | 6,562 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- int_ctrl_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity int_ctrl_0 is
port (
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
avls_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- avalon_slave.byteenable
avls_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avls_write : in std_logic := '0'; -- .write
avls_readdata : out std_logic_vector(31 downto 0); -- .readdata
avls_read : in std_logic := '0'; -- .read
avls_waitrequest : out std_logic; -- .waitrequest
avls_address : in std_logic_vector(12 downto 0) := (others => '0'); -- .address
address : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_cra.address
byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .byteenable
writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
write : in std_logic := '0'; -- .write
readdata : out std_logic_vector(15 downto 0); -- .readdata
avlm_address : out std_logic_vector(14 downto 0); -- avalon_master.address
avlm_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
avlm_writedata : out std_logic_vector(31 downto 0); -- .writedata
avlm_write : out std_logic; -- .write
avlm_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
avlm_read : out std_logic; -- .read
avlm_waitrequest : in std_logic := '0'; -- .waitrequest
avls_irq : out std_logic; -- interrupt_sender.irq
avlm_irq : in std_logic_vector(15 downto 0) := (others => '0') -- conduit_end.export
);
end entity int_ctrl_0;
architecture rtl of int_ctrl_0 is
component int_ctrl is
port (
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
avls_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
avls_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avls_write : in std_logic := 'X'; -- write
avls_readdata : out std_logic_vector(31 downto 0); -- readdata
avls_read : in std_logic := 'X'; -- read
avls_waitrequest : out std_logic; -- waitrequest
avls_address : in std_logic_vector(12 downto 0) := (others => 'X'); -- address
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(15 downto 0); -- readdata
avlm_address : out std_logic_vector(14 downto 0); -- address
avlm_byteenable : out std_logic_vector(3 downto 0); -- byteenable
avlm_writedata : out std_logic_vector(31 downto 0); -- writedata
avlm_write : out std_logic; -- write
avlm_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
avlm_read : out std_logic; -- read
avlm_waitrequest : in std_logic := 'X'; -- waitrequest
avls_irq : out std_logic; -- irq
avlm_irq : in std_logic_vector(15 downto 0) := (others => 'X') -- export
);
end component int_ctrl;
begin
int_ctrl_0 : component int_ctrl
port map (
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
avls_byteenable => avls_byteenable, -- avalon_slave.byteenable
avls_writedata => avls_writedata, -- .writedata
avls_write => avls_write, -- .write
avls_readdata => avls_readdata, -- .readdata
avls_read => avls_read, -- .read
avls_waitrequest => avls_waitrequest, -- .waitrequest
avls_address => avls_address, -- .address
address => address, -- avalon_cra.address
byteenable => byteenable, -- .byteenable
writedata => writedata, -- .writedata
write => write, -- .write
readdata => readdata, -- .readdata
avlm_address => avlm_address, -- avalon_master.address
avlm_byteenable => avlm_byteenable, -- .byteenable
avlm_writedata => avlm_writedata, -- .writedata
avlm_write => avlm_write, -- .write
avlm_readdata => avlm_readdata, -- .readdata
avlm_read => avlm_read, -- .read
avlm_waitrequest => avlm_waitrequest, -- .waitrequest
avls_irq => avls_irq, -- interrupt_sender.irq
avlm_irq => avlm_irq -- conduit_end.export
);
end architecture rtl; -- of int_ctrl_0
|
gpl-3.0
|
6bd6b862d39ec8348be57f176832c08a
| 0.445748 | 4.073246 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/bd/hdl/bd_wrapper.vhd
| 1 | 9,396 |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Wed May 03 18:19:08 2017
--Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
--Command : generate_target bd_wrapper.bd
--Design : bd_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_wrapper is
port (
DDR2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
DDR2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR2_cas_n : out STD_LOGIC;
DDR2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ras_n : out STD_LOGIC;
DDR2_we_n : out STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC;
aclk : out STD_LOGIC;
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
sys_clk_i : in STD_LOGIC;
sys_rst : in STD_LOGIC
);
end bd_wrapper;
architecture STRUCTURE of bd_wrapper is
component bd is
port (
DDR2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
DDR2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR2_ras_n : out STD_LOGIC;
DDR2_cas_n : out STD_LOGIC;
DDR2_we_n : out STD_LOGIC;
DDR2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
aclk : out STD_LOGIC;
sys_rst : in STD_LOGIC;
sys_clk_i : in STD_LOGIC;
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_awready : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wvalid : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_bready : in STD_LOGIC;
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_arready : out STD_LOGIC;
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC
);
end component bd;
begin
bd_i: component bd
port map (
DDR2_addr(12 downto 0) => DDR2_addr(12 downto 0),
DDR2_ba(2 downto 0) => DDR2_ba(2 downto 0),
DDR2_cas_n => DDR2_cas_n,
DDR2_ck_n(0) => DDR2_ck_n(0),
DDR2_ck_p(0) => DDR2_ck_p(0),
DDR2_cke(0) => DDR2_cke(0),
DDR2_cs_n(0) => DDR2_cs_n(0),
DDR2_dm(1 downto 0) => DDR2_dm(1 downto 0),
DDR2_dq(15 downto 0) => DDR2_dq(15 downto 0),
DDR2_dqs_n(1 downto 0) => DDR2_dqs_n(1 downto 0),
DDR2_dqs_p(1 downto 0) => DDR2_dqs_p(1 downto 0),
DDR2_odt(0) => DDR2_odt(0),
DDR2_ras_n => DDR2_ras_n,
DDR2_we_n => DDR2_we_n,
S00_AXI_araddr(31 downto 0) => S00_AXI_araddr(31 downto 0),
S00_AXI_arburst(1 downto 0) => S00_AXI_arburst(1 downto 0),
S00_AXI_arcache(3 downto 0) => S00_AXI_arcache(3 downto 0),
S00_AXI_arid(3 downto 0) => S00_AXI_arid(3 downto 0),
S00_AXI_arlen(7 downto 0) => S00_AXI_arlen(7 downto 0),
S00_AXI_arlock(0) => S00_AXI_arlock(0),
S00_AXI_arprot(2 downto 0) => S00_AXI_arprot(2 downto 0),
S00_AXI_arqos(3 downto 0) => S00_AXI_arqos(3 downto 0),
S00_AXI_arready => S00_AXI_arready,
S00_AXI_arregion(3 downto 0) => S00_AXI_arregion(3 downto 0),
S00_AXI_arsize(2 downto 0) => S00_AXI_arsize(2 downto 0),
S00_AXI_arvalid => S00_AXI_arvalid,
S00_AXI_awaddr(31 downto 0) => S00_AXI_awaddr(31 downto 0),
S00_AXI_awburst(1 downto 0) => S00_AXI_awburst(1 downto 0),
S00_AXI_awcache(3 downto 0) => S00_AXI_awcache(3 downto 0),
S00_AXI_awid(3 downto 0) => S00_AXI_awid(3 downto 0),
S00_AXI_awlen(7 downto 0) => S00_AXI_awlen(7 downto 0),
S00_AXI_awlock(0) => S00_AXI_awlock(0),
S00_AXI_awprot(2 downto 0) => S00_AXI_awprot(2 downto 0),
S00_AXI_awqos(3 downto 0) => S00_AXI_awqos(3 downto 0),
S00_AXI_awready => S00_AXI_awready,
S00_AXI_awregion(3 downto 0) => S00_AXI_awregion(3 downto 0),
S00_AXI_awsize(2 downto 0) => S00_AXI_awsize(2 downto 0),
S00_AXI_awvalid => S00_AXI_awvalid,
S00_AXI_bid(3 downto 0) => S00_AXI_bid(3 downto 0),
S00_AXI_bready => S00_AXI_bready,
S00_AXI_bresp(1 downto 0) => S00_AXI_bresp(1 downto 0),
S00_AXI_bvalid => S00_AXI_bvalid,
S00_AXI_rdata(31 downto 0) => S00_AXI_rdata(31 downto 0),
S00_AXI_rid(3 downto 0) => S00_AXI_rid(3 downto 0),
S00_AXI_rlast => S00_AXI_rlast,
S00_AXI_rready => S00_AXI_rready,
S00_AXI_rresp(1 downto 0) => S00_AXI_rresp(1 downto 0),
S00_AXI_rvalid => S00_AXI_rvalid,
S00_AXI_wdata(31 downto 0) => S00_AXI_wdata(31 downto 0),
S00_AXI_wlast => S00_AXI_wlast,
S00_AXI_wready => S00_AXI_wready,
S00_AXI_wstrb(3 downto 0) => S00_AXI_wstrb(3 downto 0),
S00_AXI_wvalid => S00_AXI_wvalid,
aclk => aclk,
interconnect_aresetn(0) => interconnect_aresetn(0),
peripheral_aresetn(0) => peripheral_aresetn(0),
sys_clk_i => sys_clk_i,
sys_rst => sys_rst
);
end STRUCTURE;
|
mit
|
bee419a6e432239134cd4aa783f6a95f
| 0.607918 | 2.872516 | false | false | false | false |
antlr/grammars-v4
|
vhdl/examples/signed.vhd
| 5 | 10,990 |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_SIGNED --
-- --
-- --
-- Date: 09/11/91 KN --
-- 10/08/92 AMT change std_ulogic to signed std_logic --
-- 10/28/92 AMT added signed functions, -, ABS --
-- --
-- Purpose: --
-- A set of signed arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: Comparision of same length std_logic_vector is defined --
-- in the LRM. The interpretation is for unsigned vectors --
-- This package will "overload" that definition. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_SIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
end STD_LOGIC_SIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_SIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) + SIGNED(R);
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R;
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R);
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R;
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R);
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) - SIGNED(R);
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R);
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R);
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + SIGNED(L);
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := - SIGNED(L);
return std_logic_vector(result);
end;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := ABS( SIGNED(L));
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := SIGNED(L) * SIGNED(R);
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
constant length: INTEGER := maximum(L'length, R'length);
begin
return SIGNED(L) < SIGNED(R);
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) < R;
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L < SIGNED(R);
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) <= SIGNED(R);
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) <= R;
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L <= SIGNED(R);
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) > SIGNED(R);
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) > R;
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L > SIGNED(R);
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) >= SIGNED(R);
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) >= R;
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L >= SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) = SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) /= SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= SIGNED(R);
end;
-- This function converts std_logic_vector to a signed integer value
-- using a conversion function in std_logic_arith
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : SIGNED(ARG'range);
begin
result := SIGNED(ARG);
return CONV_INTEGER(result);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT)));
end;
end STD_LOGIC_SIGNED;
|
mit
|
d2b67d3c313634d045095613793d029f
| 0.584258 | 3.763699 | false | false | false | false |
arthurTemporim/SD_SS
|
final/projeto/Main.vhd
| 1 | 3,408 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Main is
port(
-- Gera / Valida. [sel 1]
modo : in std_logic := '0';
-- Seleciona um grupo de até 16 bits. [sel 2 - 5]
k : in std_logic_vector (3 downto 0) := "1000";
-- Seleciona um valor. [sel 6~9]
s : in std_logic_vector (3 downto 0) := "0000";
-- Habilitador de clock. [sel 10]
hab_clk : in std_logic := '1';
-- Botão pra trabalhar como clock. [sel 11]
but_clk : in std_logic := '0';
-- Clock do circuito.
clk : in std_logic := '0';
-- Display usado para mostrar estatisticas.
display : out std_logic_vector (6 to 0);
-- LEDs de saída do circuito.
leds : out std_logic_vector (15 downto 0)
);
end Main;
architecture Behavioral of Main is
-- Vetor usado para deslocamento de bits.
signal vetor : std_logic_vector (15 downto 0) := "0000000000000010";
-- Guarda quantas vezes o valor de 'S' aparece.
signal estatistica : std_logic_vector (3 downto 0) := "0000";
-- Sinal para conectar estatística com display.
signal bcd : std_logic_vector (6 to 0);
-- Conta quantas vezes o valor de 'S' aparece no vetor.
signal conta_s : integer range 0 to 15;
begin
process (vetor, clk, modo)
-- Transforma o valor binário do grupo 'k' em inteiro.
variable grupo : integer range 0 to 15;
begin
-- Função GERA e VALIDA implementadas juntas.
if (modo = '0') then
-- Variável que contém tamanho do grupo.
grupo := to_integer(unsigned(k));
-- Aplica a geração aleatória.
vetor(grupo) <= vetor(0) xor vetor(1);
-- Da o shift nos bits em borda de subida.
if (clk'event and clk = '1' and hab_clk = '1') then
vetor <= std_logic_vector(unsigned(vetor) srl 1);
elsif (but_clk'event and but_clk = '1') then
vetor <= std_logic_vector(unsigned(vetor) srl 1);
end if;
-- VALIDA
-- Se os 4 últimos digitos do vetor foram iguais ao valor de 'S' então conta.
if (vetor(0) = s(0) and vetor(1) = s(1) and vetor(2) = s(2) and vetor(3) = s(3)) then
conta_s <= conta_s + 1;
end if;
end if;
end process;
-- Atribui valor inteiro da contagem para sinal.
estatistica <= std_logic_vector(to_unsigned(conta_s, 4));
-- BCD.
process (estatistica, clk)
begin
if (estatistica = "0000") then -- 0
bcd <= "1111110";
elsif (estatistica = "0001") then -- 1
bcd <= "0110000";
elsif (estatistica = "0010") then -- 2
bcd <= "1101101";
elsif (estatistica = "0011") then -- 3
bcd <= "1111001";
elsif (estatistica = "0100") then -- 4
bcd <= "0110010";
elsif (estatistica = "0101") then -- 5
bcd <= "1011010";
elsif (estatistica = "0110") then -- 6
bcd <= "1011111";
elsif (estatistica = "0111") then -- 7
bcd <= "1110000";
elsif (estatistica = "1000") then -- 8
bcd <= "1111111";
elsif (estatistica = "1001") then -- 9
bcd <= "1111011";
elsif (estatistica = "1010") then -- A
bcd <= "1110111";
elsif (estatistica = "1011") then -- B
bcd <= "0011111";
elsif (estatistica = "1100") then -- C
bcd <= "1001110";
elsif (estatistica = "1101") then -- D
bcd <= "0111101";
elsif (estatistica = "1110") then -- E
bcd <= "1001111";
else
bcd <= "1000111"; -- Caso defaul -> 'F'
end if;
end process;
-- Inverte os valores do display pois é anodo.
display <= not bcd;
-- Atribui o valor do vetor deslocado aos LEDs de saida.
leds <= vetor;
end Behavioral;
|
mit
|
d35e6e85194b309e0fdb042ab3a00c0a
| 0.622753 | 2.935121 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
afifo_ptr.vhd
| 1 | 1,968 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity afifo_ptr is
generic (
PTR_WIDTH : natural range 3 to natural'high
);
port (
rst : in std_logic;
clk : in std_logic;
clk_en : in std_logic;
--
ptr : out std_logic_vector(PTR_WIDTH - 1 downto 0); -- FIFO pointer (use for crossing clock domains)
addr : out unsigned(PTR_WIDTH - 2 downto 0); -- FIFO ram address
--
ptr_async : in std_logic_vector(PTR_WIDTH - 1 downto 0);
ptr_sync : out std_logic_vector(PTR_WIDTH - 1 downto 0)
);
end entity;
architecture rtl of afifo_ptr is
signal gray_aux : std_logic;
signal gray_i : std_logic_vector(PTR_WIDTH - 1 downto 0);
signal addr_h : std_logic;
signal ptr_meta : std_logic_vector(PTR_WIDTH - 1 downto 0);
begin
process (rst, clk)
variable toggle : std_logic;
variable carry : std_logic;
variable nxtbt : std_logic;
begin
if rising_edge(clk) then
ptr_meta <= ptr_async;
ptr_sync <= ptr_meta;
--
if clk_en then
-- invert parity
gray_aux <= not gray_aux;
-- proceed with bits from 0 to PTR - 2
toggle := not gray_aux;
carry := gray_aux;
for i in 0 to PTR_WIDTH - 2 loop
nxtbt := gray_i(i) xor toggle;
toggle := carry and gray_i(i);
carry := carry and not gray_i(i);
gray_i(i) <= nxtbt;
end loop;
-- proceed with last bit
toggle := toggle or carry;
gray_i(PTR_WIDTH - 1) <= gray_i(PTR_WIDTH - 1) xor toggle;
addr_h <= nxtbt xor gray_i(PTR_WIDTH - 1) xor toggle;
end if;
end if;
if rst then
ptr_meta <= (others => '0');
ptr_sync <= (others => '0');
--
gray_aux <= '0';
gray_i <= (others => '0');
addr_h <= '0';
end if;
end process;
ptr <= gray_i;
addr <= unsigned(addr_h & gray_i(PTR_WIDTH - 3 downto 0));
end architecture;
|
gpl-3.0
|
9a488687d60040ef931fa0da12298795
| 0.621443 | 2.764045 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/DCM_clock/ipcore_dir/my_dcm.vhd
| 1 | 6,183 |
-- file: my_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___320.000______0.000______50.0______262.500____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________32____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity my_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end my_dcm;
architecture xilinx of my_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "my_dcm,clk_wiz_v3_6,{component_name=my_dcm,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 10,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkfx);
end xilinx;
|
gpl-3.0
|
c986518c252e47619929e31d0db8b427
| 0.571891 | 4.308711 | false | false | false | false |
SalvatoreBarone/Zynq7000DriverPack
|
Src/myGPIO/VHDL/GPIOsingle.vhd
| 1 | 2,451 |
--! @file GPIOsingle.vhd
--! @author Salvatore Barone <[email protected]>
--! @date 07 04 2017
--!
--! @copyright
--! Copyright 2017 Salvatore Barone <[email protected]>
--!
--! This file is part of Zynq7000DriverPack
--!
--! Zynq7000DriverPack is free software; you can redistribute it and/or modify it under the terms of
--! the GNU General Public License as published by the Free Software Foundation; either version 3 of
--! the License, or any later version.
--!
--! Zynq7000DriverPack is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
--! without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--! GNU General Public License for more details.
--!
--! You should have received a copy of the GNU General Public License along with this program; if not,
--! write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
--! USA.
--!
--! @addtogroup myGPIO
--! @{
--! @addtogroup GPIO-single
--! @{
library ieee;
use ieee.std_logic_1164.all;
--! @brief Cella base GPIO
entity GPIOsingle is
Port ( GPIO_enable : in std_logic; --!
--! segnale di abilitazione, permette di pilotare la linea "GPIO_inout".
--! Quando GPIO_enable=1, la linea GPIO_inout e quella GPIO_write sono connesse tra loro, consentendo
--! la scrittura del valore del segnale GPIO_inout
GPIO_write : in std_logic; --!
--! segnale di input, diretto verso l'esterno del device GPIOsingle.
--! Quando GPIO_enable=1, la linea GPIO_inout e quella GPIO_write sono connesse tra loro, consentendo
--! la scrittura del valore del pin GPIO_inout.
GPIO_inout : inout std_logic; --!
--! segnale bidirezionale diretto verso l'esterno del device. Può essere usato per leggere/scrivere
--! segnali digitali da/verso l'esterno del device GPIOsingle
GPIO_read : out std_logic); --!
--! segnale di output, diretto verso l'esterno del device.
--! Quando GPIO_enable=1, la linea GPIO_inout e quella GPIO_write sono connesse tra loro, consentendo
--! la scrittura del valore dei pin, per cui questo segnale assume esattamente il valore con cui viene
--! impostato il segnale GPIO_write
end GPIOsingle;
architecture Structural of GPIOsingle is
begin
GPIO_read <= GPIO_inout;
with GPIO_enable select
GPIO_inout <= GPIO_write when '1',
'Z' when others;
end Structural;
--! @}
--! @}
|
gpl-3.0
|
171c9cd649cc2fde49b48e1b327f3555
| 0.709388 | 3.804348 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/koc/koc_signal_cntrl.vhd
| 1 | 1,467 |
library ieee;
use ieee.std_logic_1164.all;
entity koc_signal_cntrl is
port (
aclk : in std_logic;
aresetn : in std_Logic;
sig_ack : in std_logic;
sig_trig : in std_logic;
sig_in : in std_logic;
sig_out : out std_logic;
int : out std_logic);
end koc_signal_cntrl;
architecture Behavioral of koc_signal_cntrl is
signal sig_occurred : boolean := false;
signal sig_out_buff : std_logic := '0';
signal int_buff : std_logic := '0';
begin
sig_out <= sig_out_buff;
int <= int_buff;
process (aclk)
variable sig_event : boolean;
begin
if rising_edge(aclk) then
if aresetn='0' then
sig_out_buff <= '0';
sig_occurred <= false;
int_buff <= '0';
else
sig_event := sig_in='1' or sig_trig='1';
if sig_event and not sig_occurred then
sig_out_buff <= '1';
else
sig_out_buff <= '0';
end if;
if sig_event then
sig_occurred <= true;
else
sig_occurred <= false;
end if;
if sig_ack='1' then
int_buff <= '0';
elsif sig_in='1' then
int_buff <= '1';
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
49e76b276c1a24f518f669b48d05ce2f
| 0.454669 | 4.03022 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/VGA1/top_module.vhd
| 1 | 1,137 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top_module is Port (
CLK : in STD_LOGIC;
VGA_RED : out STD_LOGIC_VECTOR(3 downto 0);
VGA_GREEN : out STD_LOGIC_VECTOR(3 downto 0);
VGA_BLUE : out STD_LOGIC_VECTOR(3 downto 0);
VGA_VSYNC : out STD_LOGIC;
VGA_HSYNC : out STD_LOGIC;
SW : in std_logic_vector(0 downto 0));
end top_module;
architecture Behavioral of top_module is
component vga800x600 port(
clk : IN std_logic;
red : OUT std_logic_vector(3 downto 0);
green : OUT std_logic_vector(3 downto 0);
blue : OUT std_logic_vector(3 downto 0);
vsync : OUT std_logic;
hsync : OUT std_logic;
SW : IN std_logic);
end component;
component clock_manager port (
CLK_IN1 : in std_logic;
pixel_clock : out std_logic);
end component;
signal rgb : std_logic_vector (11 downto 0);
signal pixel_clock : std_logic;
begin
pll1: clock_manager port map (
CLK_IN1 => CLK,
pixel_clock => pixel_clock
);
vga1: vga800x600 PORT MAP(
clk => pixel_clock,
red => VGA_RED,
green => VGA_GREEN,
blue => VGA_BLUE,
vsync => VGA_VSYNC,
hsync => VGA_HSYNC ,
SW => SW(0)
);
end Behavioral;
|
gpl-3.0
|
a43f7f6781f50330b9caca759411b586
| 0.66051 | 2.807407 | false | false | false | false |
arthurbenemann/fpga-bits
|
mandelbrot/user_interface.vhd
| 1 | 860 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity user_interface is port(
clk,DIR_UP,DIR_DOWN,DIR_LEFT,DIR_RIGHT : in std_logic;
x_offset,y_offset : out std_logic_vector(8 downto 0));
end user_interface;
architecture Behavioral of user_interface is
signal x,y : signed(8 downto 0) :=(others=>'0');
signal counter : unsigned(17 downto 0) := to_unsigned(0,18);
begin
x_offset <= std_logic_vector(x);
y_offset <= std_logic_vector(y);
panning : process (clk) begin
if rising_edge(clk) then
counter <= counter +1;
if counter = 0 then
if DIR_LEFT = '1' then
x <= x + 1;
end if;
if DIR_RIGHT = '1' then
x <= x - 1;
end if;
if DIR_UP = '1' then
y <= y + 1;
end if;
if DIR_DOWN = '1' then
y <= y - 1;
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
e495d7cffeb01d8703066c945cc1007c
| 0.60814 | 2.712934 | false | false | false | false |
arthurTemporim/SD_SS
|
proj/display/prova.vhd
| 1 | 804 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity prova is
port(
entrada : in std_logic_vector (6 downto 0) := "0000000";
display : out std_logic_vector (6 downto 0)
);
end prova;
architecture Behavioral of prova is
signal bcd : std_logic_vector (6 downto 0);
begin
-- BCD.
process (entrada)
begin
if (entrada = "0000000") then -- 0
bcd <= "1111110";
elsif (entrada = "0000001") then -- 1
bcd <= "0110000";
elsif (entrada = "0000010") then -- 2
bcd <= "1101101";
elsif (entrada = "0000100") then -- 3
bcd <= "1111001";
elsif (entrada = "0001000") then -- 4
bcd <= "0110010";
elsif (entrada = "0010000") then -- 5
bcd <= "1011010";
elsif (entrada = "0100000") then -- 6
bcd <= "1011111";
else
bcd <= "1110000";
end if;
end process;
display <= bcd;
end Behavioral;
|
mit
|
2b5f316cca544e9fb36f423c1560c6da
| 0.626866 | 2.988848 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
dvb_ts.vhd
| 1 | 5,434 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.avblabs_common_pkg.all;
entity dvb_ts is
port (
rst : in std_logic;
clk : in std_logic;
-- control
address : in std_logic_vector(8 downto 0);
byteenable : in std_logic_vector(3 downto 0);
writedata : in std_logic_vector(31 downto 0);
write : in std_logic;
readdata : out std_logic_vector(31 downto 0);
read : in std_logic;
waitrequest : out std_logic;
--
interrupt : out std_logic;
cam_bypass : in std_logic;
-- input port 1
dvb_in0_dsop : in std_logic;
dvb_in0_data : in std_logic_vector(7 downto 0);
dvb_in0_dval : in std_logic;
-- input port 2
dvb_in1_dsop : in std_logic;
dvb_in1_data : in std_logic_vector(7 downto 0);
dvb_in1_dval : in std_logic;
-- input port 3
dvb_in2_dsop : in std_logic;
dvb_in2_data : in std_logic_vector(7 downto 0);
dvb_in2_dval : in std_logic;
-- CAM port
cam_baseclk : in std_logic;
cam_mclki : out std_logic;
cam_mdi : out std_logic_vector(7 downto 0);
cam_mival : out std_logic;
cam_mistrt : out std_logic;
cam_mclko : in std_logic;
cam_mdo : in std_logic_vector(7 downto 0);
cam_moval : in std_logic;
cam_mostrt : in std_logic;
-- output port (DMA)
dvb_out_dsop : out std_logic;
dvb_out_data : out std_logic_vector(7 downto 0);
dvb_out_dval : out std_logic
);
end entity;
architecture rtl of dvb_ts is
constant REG_CLKDIV : natural := 0;
constant REG_SRCSEL : natural := 1;
signal clkdiv : std_logic_vector(3 downto 0);
signal srcsel : std_logic_vector(1 downto 0);
signal cam_dsop : std_logic;
signal cam_data : std_logic_vector(7 downto 0);
signal cam_dval : std_logic;
signal swts_dsop : std_logic;
signal swts_data : std_logic_vector(7 downto 0);
signal swts_dval : std_logic;
signal mux_dsop : std_logic;
signal mux_data : std_logic_vector(7 downto 0);
signal mux_dval : std_logic;
signal filter_dsop : std_logic;
signal filter_data : std_logic_vector(7 downto 0);
signal filter_dval : std_logic;
signal pid_tbl_read : std_logic;
signal pid_tbl_write : std_logic;
signal pid_tbl_rddata : std_logic_vector(31 downto 0);
signal pid_tbl_waitreq : std_logic;
begin
-- control
pid_tbl_write <= write and address(8);
pid_tbl_read <= read and address(8);
waitrequest <= pid_tbl_waitreq;
readdata <= pid_tbl_rddata when address(8) else
X"0000000" & clkdiv when not address(0) else
X"0000000" & "00" & srcsel;
interrupt <= '0';
process (rst, clk)
begin
if rising_edge(clk) then
if write and byteenable(0) then
if not address(0) and not address(8) then
clkdiv <= writedata(clkdiv'range);
end if;
if address(0) and not address(8) then
srcsel <= writedata(srcsel'range);
end if;
end if;
end if;
if rst then
clkdiv <= (others => '0');
srcsel <= (others => '0');
end if;
end process;
-- input demux
process (rst, clk)
begin
if rising_edge(clk) then
case srcsel is
when "00" =>
mux_dsop <= dvb_in0_dsop;
mux_data <= dvb_in0_data;
mux_dval <= dvb_in0_dval;
when "01" =>
mux_dsop <= dvb_in1_dsop;
mux_data <= dvb_in1_data;
mux_dval <= dvb_in1_dval;
when "10" =>
mux_dsop <= dvb_in2_dsop;
mux_data <= dvb_in2_data;
mux_dval <= dvb_in2_dval;
when others =>
mux_dsop <= swts_dsop;
mux_data <= swts_data;
mux_dval <= swts_dval;
end case;
end if;
if rst then
mux_dsop <= '0';
mux_data <= (others => '0');
mux_dval <= '0';
end if;
end process;
FILTER_0 : entity work.dvb_ts_filter
port map (
rst => rst,
clk => clk,
--
pid_tbl_addr => address(7 downto 0),
pid_tbl_be => byteenable,
pid_tbl_wrdata => writedata,
pid_tbl_write => pid_tbl_write,
pid_tbl_rddata => pid_tbl_rddata,
pid_tbl_read => pid_tbl_read,
pid_tbl_waitreq => pid_tbl_waitreq,
--
dvb_in_dsop => mux_dsop,
dvb_in_data => mux_data,
dvb_in_dval => mux_dval,
--
dvb_out_dsop => filter_dsop,
dvb_out_data => filter_data,
dvb_out_dval => filter_dval
);
CAM_OUT_0 : entity work.dvb_ts_shaper
port map (
rst => rst,
clk => clk,
--
bypass_test => cam_bypass,
--
clkdiv => X"2",
--
dvb_indrdy => open,
dvb_indata => filter_data,
dvb_indsop => filter_dsop,
dvb_indval => filter_dval,
-- stream domain
dvb_clk => cam_baseclk,
--
dvb_out_clk => cam_mclki,
dvb_out_data => cam_mdi,
dvb_out_dval => cam_mival,
dvb_out_dsop => cam_mistrt
);
CAM_IN_0 : entity work.dvb_ts_sync
port map (
ts_clk => cam_mclko,
ts_strt => cam_mostrt,
ts_dval => cam_moval,
ts_data => cam_mdo,
--
rst => rst,
clk => clk,
--
strt => cam_dsop,
data => cam_data,
dval => cam_dval
);
-- CAM bypass cotrol
process (rst, clk)
begin
if rising_edge(clk) then
if cam_bypass then
dvb_out_dsop <= filter_dsop;
dvb_out_data <= filter_data;
dvb_out_dval <= filter_dval;
else
dvb_out_dsop <= cam_dsop;
dvb_out_data <= cam_data;
dvb_out_dval <= cam_dval;
end if;
end if;
if rst then
dvb_out_dsop <= '0';
dvb_out_data <= (others => '0');
dvb_out_dval <= '0';
end if;
end process;
end architecture;
|
gpl-3.0
|
c438fcf820a431de8e6d1af2b083205b
| 0.613544 | 2.541628 | false | false | false | false |
Daverball/reconos
|
pcores/reconos_proc_control_v1_00_a/hdl/vhdl/user_logic.vhd
| 2 | 8,865 |
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - PROC_CONTROL - Proc control implementation
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: The Proc Conrol is used to control the different
-- hardware parts through a single interface. It allows
-- to reset the HWTs seperately and asynchronously and
-- configures the MMU. To provide its functionality it
-- has several registers.
-- Register Definition (as seen from Bus):
-- Reg0: Number of HWT-Slots (OSIFS) - Read only
-- # all MMU related stuff
-- Reg1: PGD address - Read / Write
-- Reg2: Page fault address (only valid on interrupt)
-- read to clear interrupt, write after handling
-- Reg3: TLB hits - Read only
-- Reg4: TLB misses - Read only
-- # resets
-- Reg5: ReconOS reset (reset everything) - Write only
-- Reg6: HWT reset (multiple registers) - Write only
-- | x , x-1, ... | x-32 , x-33, ... 0 |
--
-- Page fault handling works the following:
-- 1.) MMU raises MMU_Pgf
-- 2.) Proc control raises PROC_Pgf_Int
-- 3.) CPU clears interrupt by reading register 2
-- 4.) CPU handles page fault and acknowledges this
-- by writing to register 2
-- 5.) Proc control informs MMU by raising MMU_Ready
-- that the page fault has been handled
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity user_logic is
generic (
-- Proc Control parameters
C_NUM_HWTS : integer := 1;
-- Bus protocol parameters
C_NUM_REG : integer := 1;
C_SLV_DWIDTH : integer := 32
);
port (
-- PROC control ports
PROC_Clk : in std_logic;
PROC_Rst : in std_logic;
PROC_Hwt_Rst : out std_logic_vector(C_NUM_HWTS - 1 downto 0);
PROC_Sys_Rst : out std_logic;
PROC_Pgf_Int : out std_logic;
-- MMU related ports
MMU_Pgf : in std_logic;
MMU_Fault_Addr : in std_logic_vector(31 downto 0);
MMU_Retry : out std_logic;
MMU_Pgd : out std_logic_vector(31 downto 0);
MMU_Tlb_Hits : in std_logic_vector(31 downto 0);
MMU_Tlb_Misses : in std_logic_vector(31 downto 0);
-- Bus protocol ports
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "Clk";
attribute SIGIS of PROC_Clk : signal is "Clk";
attribute SIGIS of Bus2IP_Resetn : signal is "Rst";
attribute SIGIS of PROC_Rst : signal is "Rst";
attribute SIGIS of PROC_Hwt_Rst : signal is "Rst";
attribute SIGIS of PROC_Sys_Rst : signal is "Rst";
attribute SIGIS of PROC_Pgf_Int : signal is "Intr_Level_High";
end entity user_logic;
architecture implementation of user_logic is
type PGF_INT_STATE_TYPE is (WAIT_PGF, WAIT_CLEAR, WAIT_READY);
signal pgf_int_state : PGF_INT_STATE_TYPE;
type SYS_RESET_STATE_TYPE is (WAIT_RST, PERF_RST);
signal sys_reset_state : SYS_RESET_STATE_TYPE;
signal sys_reset_counter : std_logic_vector(3 downto 0);
-- padding to fill unused resets in hwt_reset_reg
signal pad : std_logic_vector(C_SLV_DWIDTH * (C_NUM_REG - 6) - C_NUM_HWTS - 1 downto 0);
signal pgd : std_logic_vector(31 downto 0);
signal fault_addr : std_logic_vector(31 downto 0);
signal tlb_hits : std_logic_vector(31 downto 0);
signal tlb_misses : std_logic_vector(31 downto 0);
signal sys_reset : std_logic;
signal hwt_reset : std_logic_vector(C_NUM_HWTS - 1 downto 0);
signal hwt_reset_reg : std_logic_vector((C_NUM_REG - 6) * C_SLV_DWIDTH - 1 downto 0);
-- Signals for user logic slave model s/w accessible register
signal slv_reg_write_sel : std_logic_vector(C_NUM_REG - 1 downto 0);
signal slv_reg_read_sel : std_logic_vector(C_NUM_REG - 1 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal clk : std_logic;
signal rst : std_logic;
begin
clk <= Bus2IP_Clk;
rst <= PROC_Rst or not Bus2IP_Resetn;
pad <= (others => '0');
-- Dive bus signals
IP2Bus_Data <= slv_ip2bus_data;
slv_reg_write_sel <= Bus2IP_WrCE;
slv_reg_read_sel <= Bus2IP_RdCE;
slv_read_ack <= or_reduce(Bus2IP_RdCE);
slv_write_ack <= or_reduce(Bus2IP_WrCE);
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
-- proc realted signals
fault_addr <= MMU_Fault_Addr;
tlb_hits <= MMU_Tlb_Hits;
tlb_misses <= MMU_Tlb_Misses;
PROC_Hwt_Rst <= hwt_reset;
PROC_Sys_Rst <= sys_reset;
hwt_reset <= hwt_reset_reg(C_NUM_HWTS - 1 downto 0);
MMU_Pgd <= pgd;
-- page fault handlig (for details see description above)
pgf_int_proc : process(clk,rst) is
begin
if rst = '1' or sys_reset = '1' then
PROC_Pgf_Int <= '0';
pgf_int_state <= WAIT_PGF;
elsif rising_edge(clk) then
MMU_Retry <= '0';
case pgf_int_state is
when WAIT_PGF =>
if MMU_Pgf = '1' then
PROC_Pgf_Int <= '1';
pgf_int_state <= WAIT_CLEAR;
end if;
when WAIT_CLEAR =>
-- reading from page_fault_addr register
if slv_reg_read_sel(C_NUM_REG - 3) = '1' then
PROC_Pgf_Int <= '0';
pgf_int_state <= WAIT_READY;
end if;
when WAIT_READY =>
-- writing to page_fault_addr register
if slv_reg_write_sel(C_NUM_REG - 3) = '1' then
MMU_Retry <= '1';
pgf_int_state <= WAIT_PGF;
end if;
end case;
end if;
end process pgf_int_proc;
hwt_reset_proc : process(clk,rst) is
begin
if rst = '1' or sys_reset = '1' then
hwt_reset_reg <= (others => '1');
elsif rising_edge(clk) then
-- writing to hwt_reset
-- ignoring byte enable
for i in 0 to C_NUM_REG - 7 loop
if slv_reg_write_sel(C_NUM_REG - 7 - i) = '1' then
hwt_reset_reg(32 * i + 31 downto 32 * i) <= Bus2IP_Data;
end if;
end loop;
end if;
end process hwt_reset_proc;
sys_reset_proc : process(clk,rst) is
begin
if rst = '1' then
sys_reset <= '1';
sys_reset_state <= PERF_RST;
sys_reset_counter <= (others => '0');
elsif rising_edge(clk) then
sys_reset <= '0';
case sys_reset_state is
when WAIT_RST =>
if slv_reg_write_sel(C_NUM_REG - 6) = '1' then
sys_reset_state <= PERF_RST;
sys_reset <= '1';
sys_reset_counter <= (others => '0');
end if;
when PERF_RST =>
sys_reset <= '1';
sys_reset_counter <= sys_reset_counter + 1;
if and_reduce(sys_reset_counter) = '1' then
sys_reset_state <= WAIT_RST;
end if;
end case;
end if;
end process sys_reset_proc;
pgd_proc : process(clk,rst) is
begin
if rst = '1' or sys_reset = '1' then
pgd <= (others => '0');
else
if slv_reg_write_sel(C_NUM_REG - 2) = '1' then
pgd <= Bus2IP_Data;
end if;
end if;
end process pgd_proc;
bus_reg_read_proc : process(slv_reg_read_sel) is
begin
case slv_reg_read_sel(C_NUM_REG - 1 downto C_NUM_REG - 6) is
when "100000" => slv_ip2bus_data <= CONV_STD_LOGIC_VECTOR(C_NUM_HWTS, C_SLV_DWIDTH);
when "010000" => slv_ip2bus_data <= pgd;
when "001000" => slv_ip2bus_data <= fault_addr;
when "000100" => slv_ip2bus_data <= tlb_hits;
when "000010" => slv_ip2bus_data <= tlb_misses;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process bus_reg_read_proc;
end implementation;
|
gpl-2.0
|
7d8a799a42296aaec97375002dc987d7
| 0.563741 | 3.090656 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/DCM_clock/top_module.vhd
| 1 | 986 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Switches_LEDs is
Port (
CLK : in std_logic;
SW : in std_logic_vector(7 downto 0);
LED : out std_logic_vector(7 downto 0);
SEVENSEG_SEG : out std_logic_vector(7 downto 0);
SEVENSEG_AN : out std_logic_vector(4 downto 0)
);
end Switches_LEDs;
architecture Behavioral of Switches_LEDs is
COMPONENT clock_24h_7seg PORT(
CLK : IN std_logic;
SEVENSEG_SEG : OUT std_logic_vector(7 downto 0);
SEVENSEG_AN : OUT std_logic_vector(4 downto 0)
);
END COMPONENT;
component my_dcm port (
CLK_IN1 : in std_logic;
CLK_OUT1 : out std_logic
);
end component;
signal CLK_PLL : STD_LOGIC;
begin
LED <= SW;
clock_manager : my_dcm port map (
CLK_IN1 => CLK,
CLK_OUT1 => CLK_PLL
);
Inst_clock_24h_7seg: clock_24h_7seg PORT MAP(
CLK => CLK_PLL,
SEVENSEG_SEG => SEVENSEG_SEG,
SEVENSEG_AN => SEVENSEG_AN
);
end Behavioral;
|
gpl-3.0
|
b5f59fbce188b2267d22dc1d9162575f
| 0.643002 | 2.934524 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
dvb_ts_shaper.vhd
| 1 | 5,161 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.avblabs_common_pkg.all;
entity dvb_ts_shaper is
generic (
FIFO_DEPTH : natural := 16384
);
port (
-- system domain
rst : in std_logic;
clk : in std_logic;
-- test
bypass_test : in std_logic;
--
clkdiv : in std_logic_vector(3 downto 0);
--
dvb_indrdy : out std_logic;
dvb_indata : in std_logic_vector(7 downto 0);
dvb_indsop : in std_logic;
dvb_indval : in std_logic;
-- stream domain
dvb_clk : in std_logic;
--
dvb_out_clk : out std_logic;
dvb_out_data : out std_logic_vector(7 downto 0);
dvb_out_dval : out std_logic;
dvb_out_dsop : out std_logic
);
end entity;
architecture rtl of dvb_ts_shaper is
attribute ramstyle : string;
type mem_t is array(0 to FIFO_DEPTH - 1) of std_logic_vector(8 downto 0);
constant RAM_ADDR_MSB : natural := ulen(FIFO_DEPTH - 1) - 1;
constant FIFO_PTR_MSB : natural := RAM_ADDR_MSB + 1;
signal fifo_ram : mem_t;
attribute ramstyle of fifo_ram : signal is "M9K, no_rw_check";
signal ram_wr_addr : unsigned(RAM_ADDR_MSB downto 0);
signal ram_rd_addr : unsigned(RAM_ADDR_MSB downto 0);
signal fifo_wr_ptr : std_logic_vector(ram_wr_addr'length downto 0);
signal fifo_rd_ptr : std_logic_vector(ram_rd_addr'length downto 0);
signal fifo_wr_ptr_sync : std_logic_vector(fifo_wr_ptr'range);
signal fifo_rd_ptr_sync : std_logic_vector(fifo_rd_ptr'range);
signal fifo_we : std_logic;
signal fifo_re : std_logic;
signal fifo_fill : unsigned(RAM_ADDR_MSB downto 0);
signal dvb_out_clk_edge : std_logic;
signal dvb_out_clk_cnt : signed(clkdiv'length downto 0);
signal fifo_ram_latch : std_logic_vector(8 downto 0);
signal fifo_ram_latch_valid : std_logic;
signal fifo_ram_latch_clk : std_logic;
signal fifo_ram_reg : std_logic_vector(8 downto 0);
signal fifo_ram_reg_valid : std_logic;
signal fifo_ram_reg_clk : std_logic;
signal dvb_out_clk_en : std_logic;
signal dvb_rst_meta : std_logic;
signal dvb_rst_sync : std_logic;
begin
assert (to_unsigned(FIFO_DEPTH, RAM_ADDR_MSB + 2) and to_unsigned(FIFO_DEPTH - 1, RAM_ADDR_MSB + 2)) = 0
report "FIFO_DEPTH must be power of two!";
WR_PTR : entity work.afifo_ptr
generic map (
PTR_WIDTH => ram_wr_addr'length + 1
)
port map (
rst => rst,
clk => clk,
clk_en => fifo_we,
--
ptr => fifo_wr_ptr,
addr => ram_wr_addr,
--
ptr_async => fifo_rd_ptr,
ptr_sync => fifo_rd_ptr_sync
);
RD_PTR : entity work.afifo_ptr
generic map (
PTR_WIDTH => ram_rd_addr'length + 1
)
port map (
rst => not dvb_rst_sync,
clk => dvb_clk,
clk_en => fifo_re,
--
ptr => fifo_rd_ptr,
addr => ram_rd_addr,
--
ptr_async => fifo_wr_ptr,
ptr_sync => fifo_wr_ptr_sync
);
fifo_we <= fifo_not_full(fifo_wr_ptr, fifo_rd_ptr_sync) and dvb_indval;
fifo_re <= fifo_not_empty(fifo_wr_ptr_sync, fifo_rd_ptr) and (fifo_ram_latch_clk and dvb_out_clk_edge) and not bypass_test;
fifo_fill <= fifo_water_level(fifo_wr_ptr, fifo_rd_ptr_sync);
process (rst, clk)
begin
if rising_edge(clk) then
if fifo_fill(fifo_fill'left) nor fifo_fill(fifo_fill'left - 1) then
dvb_indrdy <= '1';
elsif fifo_fill(fifo_fill'left) and fifo_fill(fifo_fill'left - 1) then
dvb_indrdy <= '0';
end if;
if fifo_we then
fifo_ram(to_integer(ram_wr_addr)) <= dvb_indsop & dvb_indata;
end if;
end if;
if rst then
dvb_indrdy <= '0';
end if;
end process;
process (rst, dvb_rst_sync, dvb_clk)
begin
if rising_edge(dvb_clk) then
dvb_rst_meta <= '1';
dvb_rst_sync <= dvb_rst_meta;
--
if dvb_out_clk_cnt = to_signed(-2, dvb_out_clk_cnt'length) then
dvb_out_clk_edge <= '1';
else
dvb_out_clk_edge <= '0';
end if;
if dvb_out_clk_edge then
dvb_out_clk_cnt <= signed('0' & clkdiv);
else
dvb_out_clk_cnt <= dvb_out_clk_cnt - 1;
end if;
--
fifo_ram_latch <= fifo_ram(to_integer(ram_rd_addr));
fifo_ram_latch_clk <= fifo_ram_latch_clk xor dvb_out_clk_edge;
fifo_ram_latch_valid <= fifo_re;
--
fifo_ram_reg <= fifo_ram_latch;
fifo_ram_reg_valid <= fifo_ram_latch_valid;
fifo_ram_reg_clk <= fifo_ram_latch_clk;
--
dvb_out_clk_en <= fifo_ram_reg_clk and not fifo_ram_latch_clk;
dvb_out_clk <= fifo_ram_reg_clk and not bypass_test;
if dvb_out_clk_en then
dvb_out_dval <= fifo_ram_reg_valid;
dvb_out_data <= fifo_ram_reg(7 downto 0);
dvb_out_dsop <= fifo_ram_reg(8);
end if;
end if;
if rst then
dvb_rst_meta <= '0';
dvb_rst_sync <= '0';
end if;
if not dvb_rst_sync then
dvb_out_clk_edge <= '0';
dvb_out_clk_cnt <= (others => '0');
--
fifo_ram_latch_clk <= '0';
fifo_ram_latch_valid <= '0';
--
fifo_ram_reg <= (others => '0');
fifo_ram_reg_valid <= '0';
fifo_ram_reg_clk <= '0';
--
dvb_out_clk_en <= '0';
dvb_out_clk <= '0';
dvb_out_dval <= '0';
dvb_out_data <= (others => '0');
dvb_out_dsop <= '0';
end if;
end process;
end architecture;
|
gpl-3.0
|
616aef44212d8bb7bb49de13a7c358cd
| 0.628948 | 2.493237 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/SPI Interface/Source/SPI_SlaveDataBuffer.vhd
| 1 | 3,944 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Provides an SPI slave buffer that can be used for buffering data received or to
-- be sent. The buffer can be either controlled by the rising edge or by the level
-- of the enable signal, both synchronous to CLK).
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SPI_SlaveDataBuffer is
generic
(
-- The width of the data.
width: positive;
-- Indicates whether the buffer is triggered on a rising edge of the enable
-- signal instead of the enable signal being high.
edge_triggered: boolean
);
port
(
-- The system clock.
clk: in std_logic;
-- Controls when the buffer passes the input data to its output (behaviour
-- depends on the edge_triggered generic: either on the rising edge or when
-- '1', both synchronous to CLK).
buffer_enable: in std_logic;
-- The parallel unbuffered data.
data: in std_logic_vector(width-1 downto 0);
-- The parallel buffered data.
buffered_data: out std_logic_vector(width-1 downto 0) := (others => '0');
-- Indicates whether the buffered data are stable.
ready: out std_logic := '0'
);
end entity;
architecture stdarch of SPI_SlaveDataBuffer is
type reg_type is record
buffer_enable: std_logic;
data: std_logic_vector(width-1 downto 0);
end record;
signal state, next_state: reg_type :=
(
buffer_enable => '0',
data => (others => '0')
);
begin
--------------------------------------------------------------------------------
-- State register.
--------------------------------------------------------------------------------
state_register: process is
begin
wait until rising_edge(clk);
state <= next_state;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state_logic: process(state, buffer_enable, data) is
begin
-- Defaults.
next_state <= state;
next_state.buffer_enable <= buffer_enable;
-- Buffer the input data either on a rising buffer_enable edge or when
-- buffer_enable is '1'.
if ((edge_triggered and state.buffer_enable = '0' and buffer_enable = '1') or
((not edge_triggered) and buffer_enable = '1')) then
next_state.data <= data;
end if;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
buffered_data <= state.data;
ready <= state.buffer_enable;
end architecture;
|
gpl-3.0
|
fcb9e492f9c6d134f518fe6c7491221a
| 0.491379 | 5.182654 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/plasoc_cpu_1_crossbar_wrap.vhd
| 1 | 45,569 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.plasoc_crossbar_pack.plasoc_crossbar;
use work.plasoc_cpu_1_crossbar_wrap_pack.all;
entity plasoc_cpu_1_crossbar_wrap is
generic
(
axi_address_width : integer := 32;
axi_data_width : integer := 32;
axi_slave_id_width : integer := 0;
axi_master_amount : integer := 5;
axi_slave_amount : integer := 1;
axi_master_base_address : std_logic_vector := X"f0030000f0020000f0010000f000000000000000";
axi_master_high_address : std_logic_vector := X"f003fffff002fffff001fffff000ffffefffffff"
);
port
(
cpu_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_awlen : in std_logic_vector(7 downto 0);
cpu_s_axi_awsize : in std_logic_vector(2 downto 0);
cpu_s_axi_awburst : in std_logic_vector(1 downto 0);
cpu_s_axi_awlock : in std_logic;
cpu_s_axi_awcache : in std_logic_vector(3 downto 0);
cpu_s_axi_awprot : in std_logic_vector(2 downto 0);
cpu_s_axi_awqos : in std_logic_vector(3 downto 0);
cpu_s_axi_awregion : in std_logic_vector(3 downto 0);
cpu_s_axi_awvalid : in std_logic;
cpu_s_axi_awready : out std_logic;
cpu_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cpu_s_axi_wlast : in std_logic;
cpu_s_axi_wvalid : in std_logic;
cpu_s_axi_wready : out std_logic;
cpu_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_bresp : out std_logic_vector(1 downto 0);
cpu_s_axi_bvalid : out std_logic;
cpu_s_axi_bready : in std_logic;
cpu_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_arlen : in std_logic_vector(7 downto 0);
cpu_s_axi_arsize : in std_logic_vector(2 downto 0);
cpu_s_axi_arburst : in std_logic_vector(1 downto 0);
cpu_s_axi_arlock : in std_logic;
cpu_s_axi_arcache : in std_logic_vector(3 downto 0);
cpu_s_axi_arprot : in std_logic_vector(2 downto 0);
cpu_s_axi_arqos : in std_logic_vector(3 downto 0);
cpu_s_axi_arregion : in std_logic_vector(3 downto 0);
cpu_s_axi_arvalid : in std_logic;
cpu_s_axi_arready : out std_logic;
cpu_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_rresp : out std_logic_vector(1 downto 0);
cpu_s_axi_rlast : out std_logic;
cpu_s_axi_rvalid : out std_logic;
cpu_s_axi_rready : in std_logic;
ip_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
ip_m_axi_awlen : out std_logic_vector(7 downto 0);
ip_m_axi_awsize : out std_logic_vector(2 downto 0);
ip_m_axi_awburst : out std_logic_vector(1 downto 0);
ip_m_axi_awlock : out std_logic;
ip_m_axi_awcache : out std_logic_vector(3 downto 0);
ip_m_axi_awprot : out std_logic_vector(2 downto 0);
ip_m_axi_awqos : out std_logic_vector(3 downto 0);
ip_m_axi_awregion : out std_logic_vector(3 downto 0);
ip_m_axi_awvalid : out std_logic;
ip_m_axi_awready : in std_logic;
ip_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
ip_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
ip_m_axi_wlast : out std_logic;
ip_m_axi_wvalid : out std_logic;
ip_m_axi_wready : in std_logic;
ip_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_bresp : in std_logic_vector(1 downto 0);
ip_m_axi_bvalid : in std_logic;
ip_m_axi_bready : out std_logic;
ip_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
ip_m_axi_arlen : out std_logic_vector(7 downto 0);
ip_m_axi_arsize : out std_logic_vector(2 downto 0);
ip_m_axi_arburst : out std_logic_vector(1 downto 0);
ip_m_axi_arlock : out std_logic;
ip_m_axi_arcache : out std_logic_vector(3 downto 0);
ip_m_axi_arprot : out std_logic_vector(2 downto 0);
ip_m_axi_arqos : out std_logic_vector(3 downto 0);
ip_m_axi_arregion : out std_logic_vector(3 downto 0);
ip_m_axi_arvalid : out std_logic;
ip_m_axi_arready : in std_logic;
ip_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
ip_m_axi_rresp : in std_logic_vector(1 downto 0);
ip_m_axi_rlast : in std_logic;
ip_m_axi_rvalid : in std_logic;
ip_m_axi_rready : out std_logic;
cpuid_gpio_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
cpuid_gpio_m_axi_awlen : out std_logic_vector(7 downto 0);
cpuid_gpio_m_axi_awsize : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_awburst : out std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_awlock : out std_logic;
cpuid_gpio_m_axi_awcache : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awprot : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_awqos : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awregion : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awvalid : out std_logic;
cpuid_gpio_m_axi_awready : in std_logic;
cpuid_gpio_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
cpuid_gpio_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
cpuid_gpio_m_axi_wlast : out std_logic;
cpuid_gpio_m_axi_wvalid : out std_logic;
cpuid_gpio_m_axi_wready : in std_logic;
cpuid_gpio_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_bresp : in std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_bvalid : in std_logic;
cpuid_gpio_m_axi_bready : out std_logic;
cpuid_gpio_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
cpuid_gpio_m_axi_arlen : out std_logic_vector(7 downto 0);
cpuid_gpio_m_axi_arsize : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_arburst : out std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_arlock : out std_logic;
cpuid_gpio_m_axi_arcache : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arprot : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_arqos : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arregion : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arvalid : out std_logic;
cpuid_gpio_m_axi_arready : in std_logic;
cpuid_gpio_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
cpuid_gpio_m_axi_rresp : in std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_rlast : in std_logic;
cpuid_gpio_m_axi_rvalid : in std_logic;
cpuid_gpio_m_axi_rready : out std_logic;
int_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_awlen : out std_logic_vector(7 downto 0);
int_m_axi_awsize : out std_logic_vector(2 downto 0);
int_m_axi_awburst : out std_logic_vector(1 downto 0);
int_m_axi_awlock : out std_logic;
int_m_axi_awcache : out std_logic_vector(3 downto 0);
int_m_axi_awprot : out std_logic_vector(2 downto 0);
int_m_axi_awqos : out std_logic_vector(3 downto 0);
int_m_axi_awregion : out std_logic_vector(3 downto 0);
int_m_axi_awvalid : out std_logic;
int_m_axi_awready : in std_logic;
int_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
int_m_axi_wlast : out std_logic;
int_m_axi_wvalid : out std_logic;
int_m_axi_wready : in std_logic;
int_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_bresp : in std_logic_vector(1 downto 0);
int_m_axi_bvalid : in std_logic;
int_m_axi_bready : out std_logic;
int_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_arlen : out std_logic_vector(7 downto 0);
int_m_axi_arsize : out std_logic_vector(2 downto 0);
int_m_axi_arburst : out std_logic_vector(1 downto 0);
int_m_axi_arlock : out std_logic;
int_m_axi_arcache : out std_logic_vector(3 downto 0);
int_m_axi_arprot : out std_logic_vector(2 downto 0);
int_m_axi_arqos : out std_logic_vector(3 downto 0);
int_m_axi_arregion : out std_logic_vector(3 downto 0);
int_m_axi_arvalid : out std_logic;
int_m_axi_arready : in std_logic;
int_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_rresp : in std_logic_vector(1 downto 0);
int_m_axi_rlast : in std_logic;
int_m_axi_rvalid : in std_logic;
int_m_axi_rready : out std_logic;
signal_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
signal_m_axi_awlen : out std_logic_vector(7 downto 0);
signal_m_axi_awsize : out std_logic_vector(2 downto 0);
signal_m_axi_awburst : out std_logic_vector(1 downto 0);
signal_m_axi_awlock : out std_logic;
signal_m_axi_awcache : out std_logic_vector(3 downto 0);
signal_m_axi_awprot : out std_logic_vector(2 downto 0);
signal_m_axi_awqos : out std_logic_vector(3 downto 0);
signal_m_axi_awregion : out std_logic_vector(3 downto 0);
signal_m_axi_awvalid : out std_logic;
signal_m_axi_awready : in std_logic;
signal_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
signal_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
signal_m_axi_wlast : out std_logic;
signal_m_axi_wvalid : out std_logic;
signal_m_axi_wready : in std_logic;
signal_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_bresp : in std_logic_vector(1 downto 0);
signal_m_axi_bvalid : in std_logic;
signal_m_axi_bready : out std_logic;
signal_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
signal_m_axi_arlen : out std_logic_vector(7 downto 0);
signal_m_axi_arsize : out std_logic_vector(2 downto 0);
signal_m_axi_arburst : out std_logic_vector(1 downto 0);
signal_m_axi_arlock : out std_logic;
signal_m_axi_arcache : out std_logic_vector(3 downto 0);
signal_m_axi_arprot : out std_logic_vector(2 downto 0);
signal_m_axi_arqos : out std_logic_vector(3 downto 0);
signal_m_axi_arregion : out std_logic_vector(3 downto 0);
signal_m_axi_arvalid : out std_logic;
signal_m_axi_arready : in std_logic;
signal_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
signal_m_axi_rresp : in std_logic_vector(1 downto 0);
signal_m_axi_rlast : in std_logic;
signal_m_axi_rvalid : in std_logic;
signal_m_axi_rready : out std_logic;
timer_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_awlen : out std_logic_vector(7 downto 0);
timer_m_axi_awsize : out std_logic_vector(2 downto 0);
timer_m_axi_awburst : out std_logic_vector(1 downto 0);
timer_m_axi_awlock : out std_logic;
timer_m_axi_awcache : out std_logic_vector(3 downto 0);
timer_m_axi_awprot : out std_logic_vector(2 downto 0);
timer_m_axi_awqos : out std_logic_vector(3 downto 0);
timer_m_axi_awregion : out std_logic_vector(3 downto 0);
timer_m_axi_awvalid : out std_logic;
timer_m_axi_awready : in std_logic;
timer_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
timer_m_axi_wlast : out std_logic;
timer_m_axi_wvalid : out std_logic;
timer_m_axi_wready : in std_logic;
timer_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_bresp : in std_logic_vector(1 downto 0);
timer_m_axi_bvalid : in std_logic;
timer_m_axi_bready : out std_logic;
timer_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_arlen : out std_logic_vector(7 downto 0);
timer_m_axi_arsize : out std_logic_vector(2 downto 0);
timer_m_axi_arburst : out std_logic_vector(1 downto 0);
timer_m_axi_arlock : out std_logic;
timer_m_axi_arcache : out std_logic_vector(3 downto 0);
timer_m_axi_arprot : out std_logic_vector(2 downto 0);
timer_m_axi_arqos : out std_logic_vector(3 downto 0);
timer_m_axi_arregion : out std_logic_vector(3 downto 0);
timer_m_axi_arvalid : out std_logic;
timer_m_axi_arready : in std_logic;
timer_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_rresp : in std_logic_vector(1 downto 0);
timer_m_axi_rlast : in std_logic;
timer_m_axi_rvalid : in std_logic;
timer_m_axi_rready : out std_logic;
aclk : in std_logic;
aresetn : in std_logic
);
end plasoc_cpu_1_crossbar_wrap;
architecture Behavioral of plasoc_cpu_1_crossbar_wrap is
constant axi_master_id_width : integer := clogb2(axi_slave_amount)+axi_slave_id_width;
signal s_axi_awid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_awaddr : std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
signal s_axi_awlen : std_logic_vector(axi_slave_amount*8-1 downto 0);
signal s_axi_awsize : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_awburst : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_awlock : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_awcache : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_awprot : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_awqos : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_awregion : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_awvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_awready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_wdata : std_logic_vector(axi_slave_amount*axi_data_width-1 downto 0);
signal s_axi_wstrb : std_logic_vector(axi_slave_amount*axi_data_width/8-1 downto 0);
signal s_axi_wlast : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_wvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_wready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_bid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_bresp : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_bvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_bready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_arid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_araddr : std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
signal s_axi_arlen : std_logic_vector(axi_slave_amount*8-1 downto 0);
signal s_axi_arsize : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_arburst : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_arlock : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_arcache : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_arprot : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_arqos : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_arregion : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_arvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_arready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_rid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_rdata : std_logic_vector(axi_slave_amount*axi_data_width-1 downto 0);
signal s_axi_rresp : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_rlast : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_rvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_rready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal m_axi_awid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_awaddr : std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
signal m_axi_awlen : std_logic_vector(axi_master_amount*8-1 downto 0);
signal m_axi_awsize : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_awburst : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_awlock : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_awcache : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_awprot : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_awqos : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_awregion : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_awvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_awready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_wdata : std_logic_vector(axi_master_amount*axi_data_width-1 downto 0);
signal m_axi_wstrb : std_logic_vector(axi_master_amount*axi_data_width/8-1 downto 0);
signal m_axi_wlast : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_wvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_wready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_bid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_bresp : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_bvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_bready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_arid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_araddr : std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
signal m_axi_arlen : std_logic_vector(axi_master_amount*8-1 downto 0);
signal m_axi_arsize : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_arburst : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_arlock : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_arcache : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_arprot : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_arqos : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_arregion : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_arvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_arready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_rid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_rdata : std_logic_vector(axi_master_amount*axi_data_width-1 downto 0);
signal m_axi_rresp : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_rlast : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_rvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_rready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal s_address_write_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_data_write_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_response_write_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_address_read_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_data_read_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal m_address_write_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_data_write_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_response_write_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_address_read_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_data_read_connected : std_logic_vector(axi_master_amount-1 downto 0);
begin
s_axi_awid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awid;
s_axi_awaddr <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awaddr;
s_axi_awlen <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awlen;
s_axi_awsize <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awsize;
s_axi_awburst <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awburst;
s_axi_awlock <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awlock;
s_axi_awcache <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awcache;
s_axi_awprot <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awprot;
s_axi_awqos <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awqos;
s_axi_awregion <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awregion;
s_axi_awvalid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awvalid;
s_axi_wdata <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_wdata;
s_axi_wstrb <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_wstrb;
s_axi_wlast <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_wlast;
s_axi_wvalid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_wvalid;
s_axi_bready <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_bready;
s_axi_arid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arid;
s_axi_araddr <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_araddr;
s_axi_arlen <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arlen;
s_axi_arsize <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arsize;
s_axi_arburst <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arburst;
s_axi_arlock <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arlock;
s_axi_arcache <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arcache;
s_axi_arprot <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arprot;
s_axi_arqos <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arqos;
s_axi_arregion <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arregion;
s_axi_arvalid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arvalid;
s_axi_rready <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_rready;
m_axi_awready <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_awready & signal_m_axi_awready & int_m_axi_awready & cpuid_gpio_m_axi_awready & ip_m_axi_awready;
m_axi_wready <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_wready & signal_m_axi_wready & int_m_axi_wready & cpuid_gpio_m_axi_wready & ip_m_axi_wready;
m_axi_bid <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_bid & signal_m_axi_bid & int_m_axi_bid & cpuid_gpio_m_axi_bid & ip_m_axi_bid;
m_axi_bresp <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_bresp & signal_m_axi_bresp & int_m_axi_bresp & cpuid_gpio_m_axi_bresp & ip_m_axi_bresp;
m_axi_bvalid <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_bvalid & signal_m_axi_bvalid & int_m_axi_bvalid & cpuid_gpio_m_axi_bvalid & ip_m_axi_bvalid;
m_axi_arready <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_arready & signal_m_axi_arready & int_m_axi_arready & cpuid_gpio_m_axi_arready & ip_m_axi_arready;
m_axi_rid <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rid & signal_m_axi_rid & int_m_axi_rid & cpuid_gpio_m_axi_rid & ip_m_axi_rid;
m_axi_rdata <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rdata & signal_m_axi_rdata & int_m_axi_rdata & cpuid_gpio_m_axi_rdata & ip_m_axi_rdata;
m_axi_rresp <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rresp & signal_m_axi_rresp & int_m_axi_rresp & cpuid_gpio_m_axi_rresp & ip_m_axi_rresp;
m_axi_rlast <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rlast & signal_m_axi_rlast & int_m_axi_rlast & cpuid_gpio_m_axi_rlast & ip_m_axi_rlast;
m_axi_rvalid <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rvalid & signal_m_axi_rvalid & int_m_axi_rvalid & cpuid_gpio_m_axi_rvalid & ip_m_axi_rvalid;
cpu_s_axi_awready <= '0' when s_address_write_connected(0)='0' else s_axi_awready(0);
cpu_s_axi_wready <= '0' when s_data_write_connected(0)='0' else s_axi_wready(0);
cpu_s_axi_bid <= (others=>'0') when s_response_write_connected(0)='0' else s_axi_bid((1+0)*axi_slave_id_width-1 downto 0*axi_slave_id_width);
cpu_s_axi_bresp <= (others=>'0') when s_response_write_connected(0)='0' else s_axi_bresp((1+0)*2-1 downto 0*2);
cpu_s_axi_bvalid <= '0' when s_response_write_connected(0)='0' else s_axi_bvalid(0);
cpu_s_axi_arready <= '0' when s_address_read_connected(0)='0' else s_axi_arready(0);
cpu_s_axi_rid <= (others=>'0') when s_data_read_connected(0)='0' else s_axi_rid((1+0)*axi_slave_id_width-1 downto 0*axi_slave_id_width);
cpu_s_axi_rdata <= (others=>'0') when s_data_read_connected(0)='0' else s_axi_rdata((1+0)*axi_data_width-1 downto 0*axi_data_width);
cpu_s_axi_rresp <= (others=>'0') when s_data_read_connected(0)='0' else s_axi_rresp((1+0)*2-1 downto 0*2);
cpu_s_axi_rlast <= '0' when s_data_read_connected(0)='0' else s_axi_rlast(0);
cpu_s_axi_rvalid <= '0' when s_data_read_connected(0)='0' else s_axi_rvalid(0);
ip_m_axi_awid <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awid((1+0)*axi_master_id_width-1 downto 0*axi_master_id_width);
cpuid_gpio_m_axi_awid <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awid((1+1)*axi_master_id_width-1 downto 1*axi_master_id_width);
int_m_axi_awid <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awid((1+2)*axi_master_id_width-1 downto 2*axi_master_id_width);
signal_m_axi_awid <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awid((1+3)*axi_master_id_width-1 downto 3*axi_master_id_width);
timer_m_axi_awid <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awid((1+4)*axi_master_id_width-1 downto 4*axi_master_id_width);
ip_m_axi_awaddr <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awaddr((1+0)*axi_address_width-1 downto 0*axi_address_width);
cpuid_gpio_m_axi_awaddr <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awaddr((1+1)*axi_address_width-1 downto 1*axi_address_width);
int_m_axi_awaddr <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awaddr((1+2)*axi_address_width-1 downto 2*axi_address_width);
signal_m_axi_awaddr <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awaddr((1+3)*axi_address_width-1 downto 3*axi_address_width);
timer_m_axi_awaddr <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awaddr((1+4)*axi_address_width-1 downto 4*axi_address_width);
ip_m_axi_awlen <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awlen((1+0)*8-1 downto 0*8);
cpuid_gpio_m_axi_awlen <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awlen((1+1)*8-1 downto 1*8);
int_m_axi_awlen <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awlen((1+2)*8-1 downto 2*8);
signal_m_axi_awlen <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awlen((1+3)*8-1 downto 3*8);
timer_m_axi_awlen <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awlen((1+4)*8-1 downto 4*8);
ip_m_axi_awsize <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awsize((1+0)*3-1 downto 0*3);
cpuid_gpio_m_axi_awsize <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awsize((1+1)*3-1 downto 1*3);
int_m_axi_awsize <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awsize((1+2)*3-1 downto 2*3);
signal_m_axi_awsize <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awsize((1+3)*3-1 downto 3*3);
timer_m_axi_awsize <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awsize((1+4)*3-1 downto 4*3);
ip_m_axi_awburst <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awburst((1+0)*2-1 downto 0*2);
cpuid_gpio_m_axi_awburst <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awburst((1+1)*2-1 downto 1*2);
int_m_axi_awburst <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awburst((1+2)*2-1 downto 2*2);
signal_m_axi_awburst <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awburst((1+3)*2-1 downto 3*2);
timer_m_axi_awburst <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awburst((1+4)*2-1 downto 4*2);
ip_m_axi_awlock <= '0' when m_address_write_connected(0)='0' else m_axi_awlock(0);
cpuid_gpio_m_axi_awlock <= '0' when m_address_write_connected(1)='0' else m_axi_awlock(1);
int_m_axi_awlock <= '0' when m_address_write_connected(2)='0' else m_axi_awlock(2);
signal_m_axi_awlock <= '0' when m_address_write_connected(3)='0' else m_axi_awlock(3);
timer_m_axi_awlock <= '0' when m_address_write_connected(4)='0' else m_axi_awlock(4);
ip_m_axi_awcache <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awcache((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_awcache <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awcache((1+1)*4-1 downto 1*4);
int_m_axi_awcache <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awcache((1+2)*4-1 downto 2*4);
signal_m_axi_awcache <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awcache((1+3)*4-1 downto 3*4);
timer_m_axi_awcache <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awcache((1+4)*4-1 downto 4*4);
ip_m_axi_awprot <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awprot((1+0)*3-1 downto 0*3);
cpuid_gpio_m_axi_awprot <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awprot((1+1)*3-1 downto 1*3);
int_m_axi_awprot <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awprot((1+2)*3-1 downto 2*3);
signal_m_axi_awprot <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awprot((1+3)*3-1 downto 3*3);
timer_m_axi_awprot <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awprot((1+4)*3-1 downto 4*3);
ip_m_axi_awqos <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awqos((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_awqos <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awqos((1+1)*4-1 downto 1*4);
int_m_axi_awqos <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awqos((1+2)*4-1 downto 2*4);
signal_m_axi_awqos <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awqos((1+3)*4-1 downto 3*4);
timer_m_axi_awqos <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awqos((1+4)*4-1 downto 4*4);
ip_m_axi_awregion <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awregion((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_awregion <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awregion((1+1)*4-1 downto 1*4);
int_m_axi_awregion <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awregion((1+2)*4-1 downto 2*4);
signal_m_axi_awregion <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awregion((1+3)*4-1 downto 3*4);
timer_m_axi_awregion <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awregion((1+4)*4-1 downto 4*4);
ip_m_axi_awvalid <= '0' when m_address_write_connected(0)='0' else m_axi_awvalid(0);
cpuid_gpio_m_axi_awvalid <= '0' when m_address_write_connected(1)='0' else m_axi_awvalid(1);
int_m_axi_awvalid <= '0' when m_address_write_connected(2)='0' else m_axi_awvalid(2);
signal_m_axi_awvalid <= '0' when m_address_write_connected(3)='0' else m_axi_awvalid(3);
timer_m_axi_awvalid <= '0' when m_address_write_connected(4)='0' else m_axi_awvalid(4);
ip_m_axi_wdata <= (others=>'0') when m_data_write_connected(0)='0' else m_axi_wdata((1+0)*axi_data_width-1 downto 0*axi_data_width);
cpuid_gpio_m_axi_wdata <= (others=>'0') when m_data_write_connected(1)='0' else m_axi_wdata((1+1)*axi_data_width-1 downto 1*axi_data_width);
int_m_axi_wdata <= (others=>'0') when m_data_write_connected(2)='0' else m_axi_wdata((1+2)*axi_data_width-1 downto 2*axi_data_width);
signal_m_axi_wdata <= (others=>'0') when m_data_write_connected(3)='0' else m_axi_wdata((1+3)*axi_data_width-1 downto 3*axi_data_width);
timer_m_axi_wdata <= (others=>'0') when m_data_write_connected(4)='0' else m_axi_wdata((1+4)*axi_data_width-1 downto 4*axi_data_width);
ip_m_axi_wstrb <= (others=>'0') when m_data_write_connected(0)='0' else m_axi_wstrb((1+0)*axi_data_width/8-1 downto 0*axi_data_width/8);
cpuid_gpio_m_axi_wstrb <= (others=>'0') when m_data_write_connected(1)='0' else m_axi_wstrb((1+1)*axi_data_width/8-1 downto 1*axi_data_width/8);
int_m_axi_wstrb <= (others=>'0') when m_data_write_connected(2)='0' else m_axi_wstrb((1+2)*axi_data_width/8-1 downto 2*axi_data_width/8);
signal_m_axi_wstrb <= (others=>'0') when m_data_write_connected(3)='0' else m_axi_wstrb((1+3)*axi_data_width/8-1 downto 3*axi_data_width/8);
timer_m_axi_wstrb <= (others=>'0') when m_data_write_connected(4)='0' else m_axi_wstrb((1+4)*axi_data_width/8-1 downto 4*axi_data_width/8);
ip_m_axi_wlast <= '0' when m_data_write_connected(0)='0' else m_axi_wlast(0);
cpuid_gpio_m_axi_wlast <= '0' when m_data_write_connected(1)='0' else m_axi_wlast(1);
int_m_axi_wlast <= '0' when m_data_write_connected(2)='0' else m_axi_wlast(2);
signal_m_axi_wlast <= '0' when m_data_write_connected(3)='0' else m_axi_wlast(3);
timer_m_axi_wlast <= '0' when m_data_write_connected(4)='0' else m_axi_wlast(4);
ip_m_axi_wvalid <= '0' when m_data_write_connected(0)='0' else m_axi_wvalid(0);
cpuid_gpio_m_axi_wvalid <= '0' when m_data_write_connected(1)='0' else m_axi_wvalid(1);
int_m_axi_wvalid <= '0' when m_data_write_connected(2)='0' else m_axi_wvalid(2);
signal_m_axi_wvalid <= '0' when m_data_write_connected(3)='0' else m_axi_wvalid(3);
timer_m_axi_wvalid <= '0' when m_data_write_connected(4)='0' else m_axi_wvalid(4);
ip_m_axi_bready <= '0' when m_response_write_connected(0)='0' else m_axi_bready(0);
cpuid_gpio_m_axi_bready <= '0' when m_response_write_connected(1)='0' else m_axi_bready(1);
int_m_axi_bready <= '0' when m_response_write_connected(2)='0' else m_axi_bready(2);
signal_m_axi_bready <= '0' when m_response_write_connected(3)='0' else m_axi_bready(3);
timer_m_axi_bready <= '0' when m_response_write_connected(4)='0' else m_axi_bready(4);
ip_m_axi_arid <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arid((1+0)*axi_master_id_width-1 downto 0*axi_master_id_width);
cpuid_gpio_m_axi_arid <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arid((1+1)*axi_master_id_width-1 downto 1*axi_master_id_width);
int_m_axi_arid <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arid((1+2)*axi_master_id_width-1 downto 2*axi_master_id_width);
signal_m_axi_arid <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arid((1+3)*axi_master_id_width-1 downto 3*axi_master_id_width);
timer_m_axi_arid <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arid((1+4)*axi_master_id_width-1 downto 4*axi_master_id_width);
ip_m_axi_araddr <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_araddr((1+0)*axi_address_width-1 downto 0*axi_address_width);
cpuid_gpio_m_axi_araddr <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_araddr((1+1)*axi_address_width-1 downto 1*axi_address_width);
int_m_axi_araddr <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_araddr((1+2)*axi_address_width-1 downto 2*axi_address_width);
signal_m_axi_araddr <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_araddr((1+3)*axi_address_width-1 downto 3*axi_address_width);
timer_m_axi_araddr <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_araddr((1+4)*axi_address_width-1 downto 4*axi_address_width);
ip_m_axi_arlen <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arlen((1+0)*8-1 downto 0*8);
cpuid_gpio_m_axi_arlen <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arlen((1+1)*8-1 downto 1*8);
int_m_axi_arlen <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arlen((1+2)*8-1 downto 2*8);
signal_m_axi_arlen <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arlen((1+3)*8-1 downto 3*8);
timer_m_axi_arlen <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arlen((1+4)*8-1 downto 4*8);
ip_m_axi_arsize <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arsize((1+0)*3-1 downto 0*3);
cpuid_gpio_m_axi_arsize <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arsize((1+1)*3-1 downto 1*3);
int_m_axi_arsize <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arsize((1+2)*3-1 downto 2*3);
signal_m_axi_arsize <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arsize((1+3)*3-1 downto 3*3);
timer_m_axi_arsize <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arsize((1+4)*3-1 downto 4*3);
ip_m_axi_arburst <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arburst((1+0)*2-1 downto 0*2);
cpuid_gpio_m_axi_arburst <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arburst((1+1)*2-1 downto 1*2);
int_m_axi_arburst <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arburst((1+2)*2-1 downto 2*2);
signal_m_axi_arburst <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arburst((1+3)*2-1 downto 3*2);
timer_m_axi_arburst <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arburst((1+4)*2-1 downto 4*2);
ip_m_axi_arlock <= '0' when m_address_read_connected(0)='0' else m_axi_arlock(0);
cpuid_gpio_m_axi_arlock <= '0' when m_address_read_connected(1)='0' else m_axi_arlock(1);
int_m_axi_arlock <= '0' when m_address_read_connected(2)='0' else m_axi_arlock(2);
signal_m_axi_arlock <= '0' when m_address_read_connected(3)='0' else m_axi_arlock(3);
timer_m_axi_arlock <= '0' when m_address_read_connected(4)='0' else m_axi_arlock(4);
ip_m_axi_arcache <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arcache((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_arcache <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arcache((1+1)*4-1 downto 1*4);
int_m_axi_arcache <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arcache((1+2)*4-1 downto 2*4);
signal_m_axi_arcache <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arcache((1+3)*4-1 downto 3*4);
timer_m_axi_arcache <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arcache((1+4)*4-1 downto 4*4);
ip_m_axi_arprot <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arprot((1+0)*3-1 downto 0*3);
cpuid_gpio_m_axi_arprot <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arprot((1+1)*3-1 downto 1*3);
int_m_axi_arprot <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arprot((1+2)*3-1 downto 2*3);
signal_m_axi_arprot <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arprot((1+3)*3-1 downto 3*3);
timer_m_axi_arprot <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arprot((1+4)*3-1 downto 4*3);
ip_m_axi_arqos <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arqos((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_arqos <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arqos((1+1)*4-1 downto 1*4);
int_m_axi_arqos <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arqos((1+2)*4-1 downto 2*4);
signal_m_axi_arqos <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arqos((1+3)*4-1 downto 3*4);
timer_m_axi_arqos <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arqos((1+4)*4-1 downto 4*4);
ip_m_axi_arregion <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arregion((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_arregion <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arregion((1+1)*4-1 downto 1*4);
int_m_axi_arregion <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arregion((1+2)*4-1 downto 2*4);
signal_m_axi_arregion <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arregion((1+3)*4-1 downto 3*4);
timer_m_axi_arregion <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arregion((1+4)*4-1 downto 4*4);
ip_m_axi_arvalid <= '0' when m_address_read_connected(0)='0' else m_axi_arvalid(0);
cpuid_gpio_m_axi_arvalid <= '0' when m_address_read_connected(1)='0' else m_axi_arvalid(1);
int_m_axi_arvalid <= '0' when m_address_read_connected(2)='0' else m_axi_arvalid(2);
signal_m_axi_arvalid <= '0' when m_address_read_connected(3)='0' else m_axi_arvalid(3);
timer_m_axi_arvalid <= '0' when m_address_read_connected(4)='0' else m_axi_arvalid(4);
ip_m_axi_rready <= '0' when m_data_read_connected(0)='0' else m_axi_rready(0);
cpuid_gpio_m_axi_rready <= '0' when m_data_read_connected(1)='0' else m_axi_rready(1);
int_m_axi_rready <= '0' when m_data_read_connected(2)='0' else m_axi_rready(2);
signal_m_axi_rready <= '0' when m_data_read_connected(3)='0' else m_axi_rready(3);
timer_m_axi_rready <= '0' when m_data_read_connected(4)='0' else m_axi_rready(4);
plasoc_crossbar_inst : plasoc_crossbar
generic map
(
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
axi_master_amount => axi_master_amount,
axi_slave_id_width => axi_slave_id_width,
axi_slave_amount => axi_slave_amount,
axi_master_base_address => axi_master_base_address,
axi_master_high_address => axi_master_high_address
)
port map
(
aclk => aclk,
aresetn => aresetn,
s_address_write_connected => s_address_write_connected,
s_data_write_connected => s_data_write_connected,
s_response_write_connected => s_response_write_connected,
s_address_read_connected => s_address_read_connected,
s_data_read_connected => s_data_read_connected,
m_address_write_connected => m_address_write_connected,
m_data_write_connected => m_data_write_connected,
m_response_write_connected => m_response_write_connected,
m_address_read_connected => m_address_read_connected,
m_data_read_connected => m_data_read_connected,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awqos => s_axi_awqos,
s_axi_awregion => s_axi_awregion,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arqos => s_axi_arqos,
s_axi_arregion => s_axi_arregion,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
m_axi_awid => m_axi_awid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awburst => m_axi_awburst,
m_axi_awlock => m_axi_awlock,
m_axi_awcache => m_axi_awcache,
m_axi_awprot => m_axi_awprot,
m_axi_awqos => m_axi_awqos,
m_axi_awregion => m_axi_awregion,
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => m_axi_awready,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_wlast => m_axi_wlast,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => m_axi_wready,
m_axi_bid => m_axi_bid,
m_axi_bresp => m_axi_bresp,
m_axi_bvalid => m_axi_bvalid,
m_axi_bready => m_axi_bready,
m_axi_arid => m_axi_arid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arlock => m_axi_arlock,
m_axi_arcache => m_axi_arcache,
m_axi_arprot => m_axi_arprot,
m_axi_arqos => m_axi_arqos,
m_axi_arregion => m_axi_arregion,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => m_axi_arready,
m_axi_rid => m_axi_rid,
m_axi_rdata => m_axi_rdata,
m_axi_rresp => m_axi_rresp,
m_axi_rlast => m_axi_rlast,
m_axi_rvalid => m_axi_rvalid,
m_axi_rready => m_axi_rready
);
end Behavioral;
|
mit
|
e10f8d386b479b2487030cc0100b679e
| 0.681033 | 2.494881 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/serial_out/topModule.vhd
| 1 | 1,446 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity topModule is Port (
CLK : in std_logic;
GPIO0: out std_logic;
GPIO1: out std_logic;
RX: in std_logic;
TX: out std_logic);
end topModule;
architecture Behavioral of topModule is
component uart_tx port(
clk : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
tx_en : in std_logic;
tx_ready : out std_logic;
tx : out std_logic);
end component;
component uart_rx port (
clk : in std_logic;
rx :in std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_ready : out std_logic);
end component;
signal counter : std_logic_vector(7 downto 0):= (others=>'0');
signal tx_en : std_logic := '0';
signal tx_ready : std_logic;
signal tx_out : std_logic;
signal tx_data : std_logic_vector(7 downto 0):= (others=>'0');
signal rx_ready : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
begin
TX <= tx_out;
GPIO0 <= RX;
GPIO1 <= tx_out;
uart1_tx : uart_tx port map(
clk => CLK,
tx_data => tx_data,
tx_en => tx_en,
tx_ready => tx_ready,
tx => tx_out
);
uart1_rx: uart_rx port map(
clk => CLK,
rx => RX,
rx_data => rx_data,
rx_ready => rx_ready
);
retransmit : process(clk) begin
if rising_edge(clk) then
if (rx_ready and tx_ready) = '1' then
tx_data <= rx_data + 1;
tx_en <= '1';
else
tx_en <= '0';
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
047bc4d6537d4d1e5db227024efd5aad
| 0.621024 | 2.624319 | false | false | false | false |
thasti/dvbs
|
hdl/mapper/mapper.vhd
| 1 | 1,335 |
-- interpolating mapper
-- outputs mapped I/Q symbols when data valid signal is asserted
-- outputs zero-stuffing otherwise
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity mapper is
generic (
width : positive := 8
);
port (
clk : in std_logic;
rst : in std_logic;
clk_en : in std_logic;
d_valid : in std_logic;
d_i : in std_logic;
d_q : in std_logic;
q_i : out std_logic_vector(width-1 downto 0);
q_q : out std_logic_vector(width-1 downto 0)
);
end mapper;
architecture rtl of mapper is
constant mag : signed(width-1 downto 0) :=
to_signed(integer((real(2**(width-1) - 1) * sqrt(2.0)/2.0)),width);
begin
process
begin
wait until rising_edge(clk);
if rst = '1' then
q_i <= (others => '0');
q_q <= (others => '0');
elsif clk_en = '1' then
if d_valid = '1' then
case d_i is
when '0' =>
q_i <= std_logic_vector(mag);
when '1' =>
q_i <= std_logic_vector(-mag);
when others =>
report "Unreachable";
end case;
case d_q is
when '0' =>
q_q <= std_logic_vector(mag);
when '1' =>
q_q <= std_logic_vector(-mag);
when others =>
report "Unreachable";
end case;
else
q_i <= (others => '0');
q_q <= (others => '0');
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
71819c52156f5403634b333e7569d6c6
| 0.58427 | 2.63834 | false | false | false | false |
ciroceissler/sva_example
|
dut/FSM3.vhd
| 1 | 2,206 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:07:18 05/29/2014
-- Design Name:
-- Module Name: FSM3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FSM3 is
Port (
reset : in std_logic;
clk : in std_logic;
start: in std_logic;
data_in : in std_logic_vector(3 downto 0);
AVAIL : out std_logic;
DONE : out std_logic;
flag : out std_logic_vector(1 downto 0));
end FSM3;
architecture Behavioral of FSM3 is
type tipoestado is (s0, s1, s2, s3, s4, s5, s6);
signal estado : tipoestado;
begin
process(reset, clk)
variable regd : std_logic_vector(3 downto 0);
variable cont : std_logic_vector(6 downto 0);
begin
if reset = '1' then
estado <= s0;
AVAIL <= '1'; done <= '0'; flag <= "00"; regd := "0000"; cont := "0000000";
elsif (clk'event and clk='1') then
CASE estado IS
WHEN s0 =>
AVAIL <= '1'; done <= '0'; flag <= "00"; regd := "0000"; cont := "0000000"; if start='0'then estado
<= s0; else estado <= s1; end if;
WHEN s1 =>
AVAIL <= '0'; done <= '0'; flag <= "00"; regd := data_in; cont := cont+1;
if (regd = "1011" and cont <= "1000100") then estado <= s2;
elsif cont="1100100" then estado <= s4;
else estado <= s1;
end if;
WHEN s2 => -- achou um valor em <=100
AVAIL <= '0'; done <= '1'; flag <= "01"; estado <= s3;
WHEN s3 =>
AVAIL <= '0'; done <= '1'; flag <= "01"; estado <= s0;
WHEN s4 => -- nao achou valor ate 100 dados
AVAIL <= '0'; done <= '1'; flag <= "00"; estado <= s5;
WHEN s5 =>
AVAIL <= '0'; done <= '1'; flag <= "00"; estado <= s0;
WHEN others =>
AVAIL <= '1'; done <= '0'; flag <= "00"; estado <= s0;
end CASE;
end if;
end process;
end Behavioral;
|
apache-2.0
|
ba66d2b8547766710ea7b2e121f3fc78
| 0.508613 | 3.307346 | false | false | false | false |
SamTheDev/VGA-VHDL-Simulator
|
VGA.vhd
| 1 | 1,788 |
------------------------------------------------------------
-- VGA Simulator projet VHDL
-- Generate the Pixel-clk, H_SYNC and V_SYNC clock signals
-- Elhamer Oussama abdelkhalek
-- Generate sync signals if Reset = '0'
-- No control uppon the amount of pixel_clk edges received
------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity VGA is
generic ( V_SIZE, H_SIZE : integer);
Port ( Reset : in STD_LOGIC;
Pixel_clk : inout STD_LOGIC;
H_SYNC : inout STD_LOGIC;
V_SYNC : inout STD_LOGIC);
end VGA;
architecture Behavioral of VGA is
begin
Pixel_horloge: PROCESS (Reset, Pixel_clk)
variable counter : integer :=0;
BEGIN
if(Reset='1') then
Pixel_clk <='0' ;
elsif (falling_edge(Reset)) and (Reset = '0') then
Pixel_clk <= '1' after 8.2 us;
counter :=1;
else
if (counter = (H_SIZE * 2)) and (Pixel_clk = '0') then
Pixel_clk <= '1' after 8.2 us ;
counter :=1;
elsif (counter < (H_SIZE * 2)) then
Pixel_clk <= NOT Pixel_clk AFTER 20 ns;
counter := counter + 1;
end if;
end if;
END PROCESS Pixel_horloge;
HSYNC: PROCESS (H_SYNC, Reset)
BEGIN
if (Reset = '1') then
H_SYNC <= '0' ;
elsif falling_edge(Reset) and (Reset = '0') then
H_SYNC <= '1' ;
elsif(H_SYNC = '1') then
H_SYNC <= '0' AFTER 4 us;
elsif(H_SYNC = '0') then
H_SYNC <= '1' AFTER 29.8 us;
end if;
END PROCESS HSYNC;
VSYNC: PROCESS (V_SYNC, Reset)
BEGIN
if (Reset = '1') then
V_SYNC <= '0' ;
elsif falling_edge(Reset) and (Reset = '0') then
V_SYNC <= '1';
elsif(V_SYNC = '1') then
V_SYNC <= '0' AFTER 316 us;
elsif(V_SYNC = '0') then
V_SYNC <= '1' AFTER 15.908 ms;
end if;
END PROCESS VSYNC;
end Behavioral;
|
mit
|
63f1b2322b48b70261a3adf8a9763595
| 0.555928 | 3.204301 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/iis_deser.vhd
| 3 | 4,601 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:13:58 12/21/2011
-- Design Name:
-- Module Name: iis_deser - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity iis_deser is
Port ( CLK_100MHZ : in STD_LOGIC;
SCLK : in STD_LOGIC;
LRCLK : in STD_LOGIC;
SDATA : in STD_LOGIC;
EN : in STD_LOGIC;
LDATA : out STD_LOGIC_VECTOR (23 downto 0);
RDATA : out STD_LOGIC_VECTOR (23 downto 0);
VALID : out STD_LOGIC);
end iis_deser;
architecture Behavioral of iis_deser is
constant bit_cntr_max : std_logic_vector(4 downto 0) := "11000";
type IIS_STATE_TYPE is (RESET, WAIT_LEFT, SKIP_LEFT, READ_LEFT, WAIT_RIGHT, SKIP_RIGHT, READ_RIGHT);
signal start_left : std_logic;
signal start_right : std_logic;
signal bit_rdy : std_logic;
signal sclk_d1 : std_logic := '0';
signal lrclk_d1 : std_logic := '0';
signal bit_cntr : std_logic_vector(4 downto 0) := (others => '0');
signal ldata_reg : std_logic_vector(23 downto 0) := (others => '0');
signal rdata_reg : std_logic_vector(23 downto 0) := (others => '0');
--signal valid_reg : std_logic := '0';
signal iis_state : IIS_STATE_TYPE := RESET;
begin
process(CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
sclk_d1 <= SCLK;
lrclk_d1 <= LRCLK;
end if;
end process;
--Detect falling edge on LRCLK
start_left <= (lrclk_d1 and not(LRCLK));
--Detect rising edge on LRCLK
start_right <= (not(lrclk_d1) and LRCLK);
--Detect rising edge on SCLK
bit_rdy <= (not(sclk_d1) and SCLK);
--Next state logic
next_iis_state_process : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
case iis_state is
when RESET =>
if (EN = '1') then
iis_state <= WAIT_LEFT;
end if;
when WAIT_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (start_left = '1') then
iis_state <= SKIP_LEFT;
end if;
when SKIP_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_rdy = '1') then
iis_state <= READ_LEFT;
end if;
when READ_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_cntr = bit_cntr_max) then
iis_state <= WAIT_RIGHT;
end if;
when WAIT_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (start_right = '1') then
iis_state <= SKIP_RIGHT;
end if;
when SKIP_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_rdy = '1') then
iis_state <= READ_RIGHT;
end if;
when READ_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_cntr = bit_cntr_max) then
iis_state <= WAIT_LEFT;
end if;
when others=> --should never be reached
iis_state <= RESET;
end case;
end if;
end process;
process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = READ_RIGHT or iis_state = READ_LEFT) then
if (bit_rdy = '1') then
bit_cntr <= bit_cntr + 1;
end if;
else
bit_cntr <= (others => '0');
end if;
end if;
end process;
process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = RESET) then
ldata_reg <= (others => '0');
rdata_reg <= (others => '0');
else
if (iis_state = READ_LEFT and bit_rdy = '1') then
ldata_reg(23 downto 1) <= ldata_reg(22 downto 0);
ldata_reg(0) <= SDATA;
end if;
if (iis_state = READ_RIGHT and bit_rdy = '1') then
rdata_reg(23 downto 1) <= rdata_reg(22 downto 0);
rdata_reg(0) <= SDATA;
end if;
end if;
end if;
end process;
--process (CLK_100MHZ)
--begin
-- if (rising_edge(CLK_100MHZ)) then
-- if (iis_state = READ_RIGHT and bit_cntr = bit_cntr_max) then
-- valid_reg <= '1';
-- else
-- valid_reg <= '0';
-- end if;
-- end if;
--end process;
--!!!TODO:
--Ensure this triggers PWM correctly, It may be causing the data to latch before the last bit is shifted on the Right Channel
VALID <= '1' when (iis_state = READ_RIGHT and bit_cntr = bit_cntr_max) else
'0';
LDATA <= ldata_reg;
RDATA <= rdata_reg;
end Behavioral;
|
mit
|
567cfc9f6ceb2e8accdef9fa4b2404d7
| 0.551619 | 3.136333 | false | false | false | false |
DanielSouzaBertoldi/VHDL
|
ProjetoFinal/LCD_Display.vhd
| 1 | 10,958 |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
-- SW8 (GLOBAL RESET) resets LCD
ENTITY LCD_Display IS
-- Enter number of live Hex hardware data values to display
-- (do not count ASCII character constants)
GENERIC(NumHexDig: Integer:= 11);
-----------------------------------------------------------------------
-- LCD Displays 16 Characters on 2 lines
-- LCD_display string is an ASCII character string entered in hex for
-- the two lines of the LCD Display (See ASCII to hex table below)
-- Edit LCD_Display_String entries above to modify display
-- Enter the ASCII character's 2 hex digit equivalent value
-- (see table below for ASCII hex values)
-- To display character assign ASCII value to LCD_display_string(x)
-- To skip a character use X"20" (ASCII space)
-- To dislay "live" hex values from hardware on LCD use the following:
-- make array element for that character location X"0" & 4-bit field from HexDisplayData
-- state machine sees X"0" in high 4-bits & grabs the next lower 4-bits from HexDisplayData input
-- and performs 4-bit binary to ASCII conversion needed to print a hex digit
-- Num_Hex_Digits must be set to the count of hex data characters (ie. "00"s) in the display
-- Connect hardware bits to display to HexDisplayData input
-- To display less than 32 characters, terminate string with an entry of X"FE"
-- (fewer characters may slightly increase the LCD's data update rate)
-------------------------------------------------------------------
-- ASCII HEX TABLE
-- Hex Low Hex Digit
-- Value 0 1 2 3 4 5 6 7 8 9 A B C D E F
------\----------------------------------------------------------------
--H 2 | SP ! " # $ % & ' ( ) * + , - . /
--i 3 | 0 1 2 3 4 5 6 7 8 9 : ; < = > ?
--g 4 | @ A B C D E F G H I J K L M N O
--h 5 | P Q R S T U V W X Y Z [ \ ] ^ _
-- 6 | ` a b c d e f g h i j k l m n o
-- 7 | p q r s t u v w x y z { | } ~ DEL
-----------------------------------------------------------------------
-- Example "A" is row 4 column 1, so hex value is X"41"
-- *see LCD Controller's Datasheet for other graphics characters available
--
PORT(
reset, clk_48Mhz : IN STD_LOGIC;
HexDisplayData : IN STD_LOGIC_VECTOR((NumHexDig*4)-1 DOWNTO 0);
LCD_RS, LCD_E : OUT STD_LOGIC;
LCD_RW : OUT STD_LOGIC;
DATA_BUS : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY LCD_Display;
ARCHITECTURE a OF LCD_Display IS
TYPE character_string IS ARRAY ( 0 TO 31 ) OF STD_LOGIC_VECTOR( 7 DOWNTO 0 );
TYPE STATE_TYPE IS (HOLD, FUNC_SET, DISPLAY_ON, MODE_SET, Print_String,
LINE2, RETURN_HOME, DROP_LCD_E, RESET1, RESET2,
RESET3, DISPLAY_OFF, DISPLAY_CLEAR);
SIGNAL state, next_command: STATE_TYPE;
SIGNAL LCD_display_string : character_string;
-- Enter new ASCII hex data above for LCD Display
SIGNAL DATA_BUS_VALUE, Next_Char: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CLK_COUNT_400HZ: STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL CHAR_COUNT: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL CLK_400HZ_Enable,LCD_RW_INT : STD_LOGIC;
SIGNAL Line1_chars, Line2_chars: STD_LOGIC_VECTOR(127 DOWNTO 0);
BEGIN
LCD_display_string <= (
-- ASCII hex values for LCD Display
-- Enter Live Hex Data Values from hardware here
-- LCD DISPLAYS THE FOLLOWING:
------------------------------
--| MIPS PC=XXX |
--| INST=XXXXXXXX |
------------------------------
-- Line 1
X"4D",X"49",X"50",X"53",X"20",X"20",X"50",X"43",X"3D",
X"0" & "00" & HexDisplayData(41 DOWNTO 40),
X"0" & HexDisplayData(39 DOWNTO 36),
X"0" & HexDisplayData(35 DOWNTO 32),
X"20",X"20",X"20",X"20",
-- Line 2
X"49",X"6E",X"73",X"74",X"3D",
X"0" & HexDisplayData (31 DOWNTO 28),
X"0" & HexDisplayData (27 DOWNTO 24),
X"0" & HexDisplayData (23 DOWNTO 20),
X"0" & HexDisplayData (19 DOWNTO 16),
X"0" & HexDisplayData (15 DOWNTO 12),
X"0" & HexDisplayData (11 DOWNTO 8),
X"0" & HexDisplayData (7 DOWNTO 4),
X"0" & HexDisplayData (3 DOWNTO 0),
X"20",X"20",X"20");
-- BIDIRECTIONAL TRI STATE LCD DATA BUS
DATA_BUS <= DATA_BUS_VALUE WHEN LCD_RW_INT = '0' ELSE "ZZZZZZZZ";
-- get next character in display string
Next_Char <= LCD_display_string(CONV_INTEGER(CHAR_COUNT));
LCD_RW <= LCD_RW_INT;
PROCESS
BEGIN
WAIT UNTIL CLK_48MHZ'EVENT AND CLK_48MHZ = '1';
IF RESET = '1' THEN
CLK_COUNT_400HZ <= X"00000";
CLK_400HZ_Enable <= '0';
ELSE
IF CLK_COUNT_400HZ < X"0EA60" THEN
CLK_COUNT_400HZ <= CLK_COUNT_400HZ + 1;
CLK_400HZ_Enable <='0';
ELSE
CLK_COUNT_400HZ <= X"00000";
CLK_400HZ_Enable <= '1';
END IF;
END IF;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL CLK_48MHZ'EVENT AND CLK_48MHZ = '1';
IF reset = '1' THEN
state <= RESET1;
DATA_BUS_VALUE <= X"38";
next_command <= RESET2;
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '1';
ELSE
IF CLK_400HZ_Enable = '1' THEN
-- State Machine to send commands and data to LCD DISPLAY
CASE state IS
-- Set Function to 8-bit transfer and 2 line display with 5x8 Font size
-- see Hitachi HD44780 family data sheet for LCD command and timing details
WHEN RESET1 =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_E;
next_command <= RESET2;
CHAR_COUNT <= "00000";
WHEN RESET2 =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_E;
next_command <= RESET3;
WHEN RESET3 =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_E;
next_command <= FUNC_SET;
-- EXTRA STATES ABOVE ARE NEEDED FOR RELIABLE PUSHBUTTON RESET OF LCD
WHEN FUNC_SET =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_E;
next_command <= DISPLAY_OFF;
-- Turn off Display and Turn off cursor
WHEN DISPLAY_OFF =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"08";
state <= DROP_LCD_E;
next_command <= DISPLAY_CLEAR;
-- Clear Display and Turn off cursor
WHEN DISPLAY_CLEAR =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"01";
state <= DROP_LCD_E;
next_command <= DISPLAY_ON;
-- Turn on Display and Turn off cursor
WHEN DISPLAY_ON =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"0C";
state <= DROP_LCD_E;
next_command <= MODE_SET;
-- Set write mode to auto increment address and move cursor to the right
WHEN MODE_SET =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"06";
state <= DROP_LCD_E;
next_command <= Print_String;
-- Write ASCII hex character in first LCD character location
WHEN Print_String =>
state <= DROP_LCD_E;
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW_INT <= '0';
-- ASCII character to output
IF Next_Char(7 DOWNTO 4) /= X"0" THEN DATA_BUS_VALUE <= Next_Char;
ELSE
-- Convert 4-bit value to an ASCII hex digit
IF Next_Char(3 DOWNTO 0) >9 THEN
-- ASCII A...F
DATA_BUS_VALUE <= X"4" & (Next_Char(3 DOWNTO 0)-9);
ELSE
-- ASCII 0...9
DATA_BUS_VALUE <= X"3" & Next_Char(3 DOWNTO 0);
END IF;
END IF;
-- Loop to send out 32 characters to LCD Display (16 by 2 lines)
IF (CHAR_COUNT < 31) AND (Next_Char /= X"FE") THEN
CHAR_COUNT <= CHAR_COUNT + 1;
ELSE
CHAR_COUNT <= "00000";
END IF;
-- Jump to second line?
IF CHAR_COUNT = 15 THEN next_command <= line2;
-- Return to first line?
ELSIF (CHAR_COUNT = 31) OR (Next_Char = X"FE") THEN
next_command <= return_home;
ELSE next_command <= Print_String; END IF;
-- Set write address to line 2 character 1
WHEN LINE2 =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"C0";
state <= DROP_LCD_E;
next_command <= Print_String;
-- Return write address to first character postion on line 1
WHEN RETURN_HOME =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"80";
state <= DROP_LCD_E;
next_command <= Print_String;
-- The next three states occur at the end of each command or data transfer to the LCD
-- Drop LCD E line - falling edge loads inst/data to LCD controller
WHEN DROP_LCD_E =>
LCD_E <= '0';
state <= HOLD;
-- Hold LCD inst/data valid after falling edge of E line
WHEN HOLD =>
state <= next_command;
END CASE;
END IF;
END IF;
END PROCESS;
END a;
|
gpl-3.0
|
dadce9ed4b75fde69b1e01debb037c47
| 0.462311 | 3.835492 | false | false | false | false |
meninge/dauphin
|
test_bench/test_fifo_recode_fifo.vhd
| 1 | 7,966 |
----------------------------------------------------------------
-- uut:
-- recode.vhd
-- circbuf_fast.vhd
-- description:
-- simple test_bench to verify recode behavior in normal conditions
-- with a fifo just before
-- and a fifo just after
-- expected result:
-- recode should be configured in weight configuration mode
-- in normal mode, recode should act as:
-- output = (input < 0) ? 0 : input + cst[addr]
-- recode should correctly interact with input and output fifos
----------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;
use ieee.numeric_std.all;
-- entity declaration for your testbench.Dont declare any ports here
ENTITY test_fifo_recode_fifo IS
END test_fifo_recode_fifo;
ARCHITECTURE behavior OF test_fifo_recode_fifo IS
-- add component under test
-- Parameters for the neurons
constant WDATA : natural := 32;
constant WOUT : natural := WDATA;
constant WWEIGHT : natural := 16;
constant WACCU : natural := 32;
-- Parameters for frame and number of neurons
constant FSIZE : natural := 4;
constant NBNEU : natural := 4;
constant DATAW : natural := 32;
constant DEPTH : natural := 8;
constant CNTW : natural := 16;
component recode
generic(
WDATA : natural := WDATA;
WWEIGHT : natural := WWEIGHT;
WOUT : natural := WOUT;
FSIZE : natural := NBNEU -- warning, this is NB_NEU
);
port(
clk : in std_logic;
-- Ports for address control
addr_clear : in std_logic;
-- Ports for Write into memory
write_mode : in std_logic;
write_data : in std_logic_vector(WDATA - 1 downto 0);
write_enable : in std_logic;
write_ready : out std_logic;
-- The user-specified number of neurons
user_nbneu : in std_logic_vector(15 downto 0);
-- Data input
data_in : in std_logic_vector(WDATA-1 downto 0);
data_in_valid : in std_logic;
data_in_ready : out std_logic;
-- Data output
data_out : out std_logic_vector(WOUT-1 downto 0);
data_out_valid : out std_logic;
-- The output data enters a FIFO. This indicates the available room.
out_fifo_room : in std_logic_vector(15 downto 0)
);
end component;
component circbuf_fast is
generic (
DATAW : natural := DATAW;
DEPTH : natural := DEPTH;
CNTW : natural := CNTW
);
port (
reset : in std_logic;
clk : in std_logic;
fifo_in_data : in std_logic_vector(DATAW-1 downto 0);
fifo_in_rdy : out std_logic;
fifo_in_ack : in std_logic;
fifo_in_cnt : out std_logic_vector(CNTW-1 downto 0);
fifo_out_data : out std_logic_vector(DATAW-1 downto 0);
fifo_out_rdy : out std_logic;
fifo_out_ack : in std_logic;
fifo_out_cnt : out std_logic_vector(CNTW-1 downto 0)
);
end component;
-- clock period definition
constant clk_period : time := 1 ns;
signal clear : std_logic := '0';
signal clk : std_logic := '0';
-- recode signals
signal addr_clear : std_logic;
signal write_mode : std_logic;
signal write_data : std_logic_vector(WDATA - 1 downto 0);
signal write_enable : std_logic;
signal write_ready : std_logic;
signal user_nbneu : std_logic_vector(15 downto 0);
signal data_in : std_logic_vector(WDATA-1 downto 0);
signal data_in_valid : std_logic;
signal data_in_ready : std_logic;
signal data_out : std_logic_vector(WOUT-1 downto 0);
signal data_out_valid : std_logic;
signal out_fifo_room : std_logic_vector(15 downto 0);
-- for the fifo_1
signal fifo_in_data_1 : std_logic_vector(DATAW-1 downto 0);
signal fifo_in_rdy_1 : std_logic;
signal fifo_in_ack_1 : std_logic;
signal fifo_in_cnt_1 : std_logic_vector(CNTW-1 downto 0);
signal fifo_out_data_1 : std_logic_vector(DATAW-1 downto 0);
signal fifo_out_rdy_1 : std_logic;
signal fifo_out_ack_1 : std_logic;
signal fifo_out_cnt_1 : std_logic_vector(CNTW-1 downto 0);
-- for the fifo_2
signal fifo_in_data_2 : std_logic_vector(DATAW-1 downto 0);
signal fifo_in_rdy_2 : std_logic;
signal fifo_in_ack_2 : std_logic;
signal fifo_in_cnt_2 : std_logic_vector(CNTW-1 downto 0);
signal fifo_out_data_2 : std_logic_vector(DATAW-1 downto 0);
signal fifo_out_rdy_2 : std_logic;
signal fifo_out_ack_2 : std_logic;
signal fifo_out_cnt_2 : std_logic_vector(CNTW-1 downto 0);
begin
fifo_1: circbuf_fast
port map (
reset => clear,
clk => clk,
fifo_in_data => fifo_in_data_1,
fifo_in_rdy => fifo_in_rdy_1,
fifo_in_ack => fifo_in_ack_1,
fifo_in_cnt => fifo_in_cnt_1,
fifo_out_data => fifo_out_data_1,
fifo_out_rdy => fifo_out_rdy_1,
fifo_out_ack => fifo_out_ack_1,
fifo_out_cnt => fifo_out_cnt_1
);
fifo_2: circbuf_fast
port map (
reset => clear,
clk => clk,
fifo_in_data => fifo_in_data_2,
fifo_in_rdy => fifo_in_rdy_2,
fifo_in_ack => fifo_in_ack_2,
fifo_in_cnt => fifo_in_cnt_2,
fifo_out_data => fifo_out_data_2,
fifo_out_rdy => fifo_out_rdy_2,
fifo_out_ack => fifo_out_ack_2,
fifo_out_cnt => fifo_out_cnt_2
);
recode_1 : recode
port map (
clk => clk,
addr_clear => addr_clear,
write_mode => write_mode,
write_data => write_data,
write_enable => write_enable,
write_ready => write_ready,
user_nbneu => user_nbneu,
data_in => data_in,
data_in_valid => data_in_valid,
data_in_ready => data_in_ready,
data_out => data_out,
data_out_valid => data_out_valid,
out_fifo_room => out_fifo_room
);
write_data <= fifo_out_data_1;
write_enable <= fifo_out_rdy_1;
data_in <= fifo_out_data_1;
data_in_valid <= fifo_out_rdy_1;
--data_in_ready <= fifo_out_ack;
fifo_out_ack_1 <= data_in_ready or write_ready;
fifo_in_ack_2 <= data_out_valid;
fifo_in_data_2 <= data_out;
out_fifo_room <= fifo_in_cnt_2;
-- Clock process definitions( clock with 50% duty cycle is generated here.
clk_process : process
begin
clk <= '1';
wait for clk_period/2; --for 0.5 ns signal is '1'.
clk <= '0';
wait for clk_period/2; --for next 0.5 ns signal is '0'.
end process;
stim_proc: process
variable counter : integer := 0;
variable neurons : integer := 0;
begin
-------------------------------
-- TEST CHARGEMENT DES POIDS --
-------------------------------
-- reset
clear <= '1';
fifo_in_data_1 <= std_logic_vector(to_unsigned(0, 32));
fifo_in_ack_1 <= '0';
wait for 3*clk_period;
clear <= '0';
write_mode <= '1'; -- load weights
-- load data into the fifo
fifo_in_data_1 <= std_logic_vector(to_unsigned(3, 32));
fifo_in_ack_1 <= '1';
--while neurons < NBNEU loop
counter := 0;
neurons := neurons + 1;
wait for clk_period;
wait for clk_period;
counter := 0;
fifo_in_data_1 <= std_logic_vector(to_signed(4, 32));
fifo_in_ack_1 <= '1';
neurons := neurons +1;
wait for clk_period;
counter := 0;
fifo_in_data_1 <= std_logic_vector(to_signed(5, 32));
fifo_in_ack_1 <= '1';
neurons := neurons +1;
wait for clk_period;
counter := 0;
fifo_in_data_1 <= std_logic_vector(to_signed(1, 32));
fifo_in_ack_1 <= '1';
neurons := neurons +1;
wait for clk_period;
fifo_in_data_1 <= std_logic_vector(to_signed(10, 32));
fifo_in_ack_1 <= '0';
--end loop;
wait for clk_period;
wait for clk_period;
wait for clk_period;
wait for clk_period;
wait for clk_period;
write_mode <= '0'; -- accu add
fifo_in_ack_1 <= '1';
wait for clk_period;
----------------------------
-- TEST MODE ACCUMULATION --
----------------------------
write_mode <= '0'; -- accu add
fifo_in_data_1 <= std_logic_vector(to_unsigned(64, 32));
counter := 0;
while (counter < FSIZE) loop
wait for clk_period;
fifo_in_data_1 <= std_logic_vector(to_unsigned(128, 32));
counter := counter + 1;
wait for clk_period;
fifo_in_data_1 <= std_logic_vector(to_unsigned(64, 32));
end loop;
wait;
end process;
END;
|
mit
|
50ffa3c8c957015452809a43569a9d3b
| 0.62001 | 2.805918 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_2/example_design/system_axi_dma_0_wrapper_fifo_generator_v9_3_2_exdes.vhd
| 1 | 5,691 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_2_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_dma_0_wrapper_fifo_generator_v9_3_2_exdes is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(3-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(9-1 DOWNTO 0);
DOUT : OUT std_logic_vector(9-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_dma_0_wrapper_fifo_generator_v9_3_2_exdes;
architecture xilinx of system_axi_dma_0_wrapper_fifo_generator_v9_3_2_exdes is
signal clk_i : std_logic;
component system_axi_dma_0_wrapper_fifo_generator_v9_3_2 is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(3-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(9-1 DOWNTO 0);
DOUT : OUT std_logic_vector(9-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_dma_0_wrapper_fifo_generator_v9_3_2
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
mit
|
95c43f86d1112d33aaa34a9348c17180
| 0.516957 | 4.7425 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_delay_1.0/sources_1/new/bram.vhd
| 1 | 985 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bram is
generic (
T: integer := 20000;
B: integer := 15 --15 bits for 20,000 memory places
);
port (clk : in std_logic;
we : in std_logic;
addr1 : in std_logic_vector(B-1 downto 0);
addr2 : in std_logic_vector(B-1 downto 0);
di : in std_logic_vector(31 downto 0); --32 bit word
do1 : out std_logic_vector(31 downto 0);
do2 : out std_logic_vector(31 downto 0));
end bram;
architecture arch of bram is
type ram_type is array (0 to T-1) of std_logic_vector (31 downto 0);
signal RAM : ram_type:= (T-1 downto 0 => x"00000000"); --define and initialize RAM
begin
process (clk)
begin
if rising_edge(clk) then
if we = '1' then
RAM(conv_integer(addr1)) <= di;
end if;
do1 <= RAM(conv_integer(addr1));
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
do2 <= RAM(conv_integer(addr2));
end if;
end process;
end arch;
|
mit
|
973adfa33c2f71f4e787a641980f4e2e
| 0.643655 | 2.975831 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_1/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_1_dverif.vhd
| 1 | 5,691 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_1_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pkg.ALL;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_1_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_1_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_dma_0_wrapper_fifo_generator_v9_3_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
mit
|
9bbeadf0a93ad10984667a1ed2e562d0
| 0.581972 | 3.990884 | false | false | false | false |
medav/conware
|
conware_test/system/hdl/system_cownare_ctl_0_wrapper.vhd
| 1 | 4,569 |
-------------------------------------------------------------------------------
-- system_cownare_ctl_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library cownare_ctl_v1_00_a;
use cownare_ctl_v1_00_a.all;
entity system_cownare_ctl_0_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
in_states : in std_logic_vector(7 downto 0);
out_states : in std_logic_vector(7 downto 0);
num_reads : in std_logic_vector(31 downto 0);
num_writes : in std_logic_vector(31 downto 0);
read_ctr : in std_logic_vector(7 downto 0);
write_ctr : in std_logic_vector(7 downto 0)
);
end system_cownare_ctl_0_wrapper;
architecture STRUCTURE of system_cownare_ctl_0_wrapper is
component cownare_ctl is
generic (
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_MIN_SIZE : std_logic_vector;
C_USE_WSTRB : INTEGER;
C_DPHASE_TIMEOUT : INTEGER;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_FAMILY : STRING;
C_NUM_REG : INTEGER;
C_NUM_MEM : INTEGER;
C_SLV_AWIDTH : INTEGER;
C_SLV_DWIDTH : INTEGER
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
in_states : in std_logic_vector(7 downto 0);
out_states : in std_logic_vector(7 downto 0);
num_reads : in std_logic_vector(31 downto 0);
num_writes : in std_logic_vector(31 downto 0);
read_ctr : in std_logic_vector(7 downto 0);
write_ctr : in std_logic_vector(7 downto 0)
);
end component;
begin
cownare_ctl_0 : cownare_ctl
generic map (
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_MIN_SIZE => X"000001ff",
C_USE_WSTRB => 0,
C_DPHASE_TIMEOUT => 8,
C_BASEADDR => X"74400000",
C_HIGHADDR => X"7440ffff",
C_FAMILY => "zynq",
C_NUM_REG => 1,
C_NUM_MEM => 1,
C_SLV_AWIDTH => 32,
C_SLV_DWIDTH => 32
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
in_states => in_states,
out_states => out_states,
num_reads => num_reads,
num_writes => num_writes,
read_ctr => read_ctr,
write_ctr => write_ctr
);
end architecture STRUCTURE;
|
mit
|
15e600df6df1e2e85e9b9febaf11802f
| 0.582184 | 3.021825 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3/example_design/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_exdes.vhd
| 1 | 5,073 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_exdes is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_exdes;
architecture xilinx of system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_exdes is
signal clk_i : std_logic;
component system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
mit
|
e09b2fe78d3877cb641903fe73399676
| 0.542874 | 4.767857 | false | false | false | false |
thasti/dvbs
|
hdl/conv_coder/conv_coder.vhd
| 1 | 740 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_coder is
port (
clk : in std_logic;
rst : in std_logic;
clk_en : in std_logic;
d : in std_logic;
x : out std_logic;
y : out std_logic
);
end conv_coder;
architecture rtl of conv_coder is
signal delay : std_logic_vector(0 to 5) := (others => '0');
begin
process
begin
wait until rising_edge(clk);
if rst = '1' then
delay <= (others => '0');
elsif clk_en = '1' then
delay <= d & delay(0 to 4);
-- X has G = 171o = 121d = 1111001
x <= d xor delay(0) xor delay(1) xor delay(2) xor delay(5);
-- Y has G = 133o = 91d = 1011011
y <= d xor delay(1) xor delay(2) xor delay(4) xor delay(5);
end if;
end process;
end rtl;
|
gpl-2.0
|
d6e7cb90b25465f6b3189c86bcbea0e4
| 0.612162 | 2.525597 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_control_1.0/control_tb.vhd
| 1 | 2,806 |
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity control_tb is
end;
architecture bench of control_tb is
component control
Port ( Switches : in STD_LOGIC_VECTOR (0 to 7);
clk_12hz : in std_logic;
clk_1hz5 : in std_logic;
Leds : out STD_LOGIC_VECTOR (0 to 7) := "10000000"; --left to right
butn_in : in STD_LOGIC_VECTOR (0 to 2);
en : out STD_LOGIC_VECTOR (0 to 3):= "0000";
options0 : out STD_LOGIC_VECTOR (0 to 3);
options1 : out STD_LOGIC_VECTOR (0 to 3);
options2 : out STD_LOGIC_VECTOR (0 to 3);
options3 : out STD_LOGIC_VECTOR (0 to 3)
);
end component;
signal Switches: STD_LOGIC_VECTOR (0 to 7);
signal clk_12hz : std_logic;
signal clk_1hz5 : std_logic;
signal Leds : STD_LOGIC_VECTOR (0 to 7) := "10000000"; --left to right
signal butn_in : STD_LOGIC_VECTOR (0 to 2);
signal en : STD_LOGIC_VECTOR (0 to 3):= "0000";
signal options0 : STD_LOGIC_VECTOR (0 to 3);
signal options1 : STD_LOGIC_VECTOR (0 to 3);
signal options2 : STD_LOGIC_VECTOR (0 to 3);
signal options3 : STD_LOGIC_VECTOR (0 to 3);
constant clock_period: time := 83 ms;
constant clock_period2: time := 0.66 sec;
begin
uut: control port map ( Switches => Switches,
clk_12hz => clk_12hz,
clk_1hz5 => clk_1hz5,
Leds => Leds,
butn_in => butn_in,
en => en,
options0 => options0,
options1 => options1,
options2 => options2,
options3 => options3 );
clk_process: process
begin
clk_12hz <= '1';
wait for clock_period/2;
clk_12hz <= '0';
wait for clock_period/2;
end process;
clk2_process: process
begin
clk_1hz5 <= '1';
wait for clock_period2/2;
clk_1hz5 <= '0';
wait for clock_period2/2;
end process;
stimulus: process
begin
butn_in <= "001";
wait for 100ms;
butn_in <= "00000";
wait for 50ms;
butn_in <= "001";
wait for 200ms;
butn_in <= "00000";
wait for 50ms;
-- butn_in <= "00100";
-- wait for 200ms;
-- butn_in <= "00000";
-- wait for 100ms;
-- butn_in <= "00010";
-- wait for 200ms;
-- butn_in <= "00000";
-- wait for 100ms;
--butn_in <= "00001";
-- wait for 100ms;
-- butn_in <= "00000";
-- wait for 50ms;
-- butn_in <= "01000";
-- wait for 200ms;
-- butn_in <= "00000";
-- wait for 50ms;
-- butn_in <= "00100";
-- wait for 200ms;
-- butn_in <= "00000";
-- wait for 100ms;
-- butn_in <= "00010";
-- wait for 200ms;
-- butn_in <= "00000";
-- wait for 100ms;
wait;
end process;
end;
|
mit
|
c695590c0b9b3239efd1c8976bbaa46d
| 0.535282 | 3.181406 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_synth.vhd
| 1 | 10,215 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(5-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(5-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(5-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(5-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_dgen
GENERIC MAP (
C_DIN_WIDTH => 5,
C_DOUT_WIDTH => 5,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_dverif
GENERIC MAP (
C_DOUT_WIDTH => 5,
C_DIN_WIDTH => 5,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 5,
C_DIN_WIDTH => 5,
C_WR_PNTR_WIDTH => 5,
C_RD_PNTR_WIDTH => 5,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_exdes
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
mit
|
2e43b82de8cef709f485c5670d0f4d00
| 0.474107 | 4.087635 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_PL_to_PS_1.0/hdl/PL_to_PS_v1_0_S00_AXI.vhd
| 1 | 15,744 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PL_to_PS_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end PL_to_PS_v1_0_S00_AXI;
architecture arch_imp of PL_to_PS_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_wstrb_const : std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0) ; --vl - my addition
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 4
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
--slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
axi_awaddr <= "0000"; --vl - 0000 is slv_reg0- the address range for AXI lite in this code is from 0000 to 1111 (the last 4 bits of the actual address).
-- constant state of write-enable
slv_reg_wren <= '1' ;--vl
axi_wstrb_const <= "1111"; --vl
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( axi_wstrb_const(byte_index) = '1' ) then --vl
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00" =>
reg_data_out <= slv_reg0;
when b"01" =>
reg_data_out <= slv_reg1;
when b"10" =>
reg_data_out <= slv_reg2;
when b"11" =>
reg_data_out <= slv_reg3;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
-- User logic ends
end arch_imp;
|
mit
|
d2006d8ac4f73994349d8c1c91dd21bf
| 0.602706 | 3.518999 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_2/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_2_synth.vhd
| 1 | 11,095 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_2_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_2_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_2_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(3-1 DOWNTO 0);
SIGNAL wr_ack : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 50 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
fg_dg_nv: system_axi_dma_0_wrapper_fifo_generator_v9_3_2_dgen
GENERIC MAP (
C_DIN_WIDTH => 9,
C_DOUT_WIDTH => 9,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_dma_0_wrapper_fifo_generator_v9_3_2_dverif
GENERIC MAP (
C_DOUT_WIDTH => 9,
C_DIN_WIDTH => 9,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 9,
C_DIN_WIDTH => 9,
C_WR_PNTR_WIDTH => 3,
C_RD_PNTR_WIDTH => 3,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_dma_0_wrapper_fifo_generator_v9_3_2_inst : system_axi_dma_0_wrapper_fifo_generator_v9_3_2_exdes
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
mit
|
571ca72475b79bcab7288281819fa344
| 0.466516 | 4.041894 | false | false | false | false |
thasti/dvbs
|
hdl/network/rmii_tx/rmii_tx.vhd
| 1 | 1,561 |
-- ethernet RMII interface
-- Stefan Biereigel
-- reads data from the RMII PHY interface
-- RX preamble & FSC is stripped, only data in frame is output to
--
-- port description
--
-- TO PHY:
-- txd0,1 output data
-- txen output data valid
--
-- TO CTRL:
-- clk 50 MHz RMII clock
-- rst sync reset
-- start_tx send trigger input
-- tx_rdy tx module is ready for transfer
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rmii_tx is
port (
clk : in std_logic;
rst : in std_logic;
txd : out std_logic_vector(1 downto 0);
txen : out std_logic;
tx_run : in std_logic;
tx_byte : in std_logic_vector(7 downto 0)
);
end rmii_tx;
architecture behav of rmii_tx is
type tx_states is (idle, tx);
signal cnt : unsigned(1 downto 0);
signal data : std_logic_vector(7 downto 0);
signal tx_state : tx_states;
begin
tx_proc : process
begin
wait until rising_edge(clk);
if rst = '1' then
txen <= '0';
txd <= "00";
cnt <= to_unsigned(0,cnt'length);
else
case tx_state is
when idle =>
txd <= "00";
txen <= '0';
if tx_run = '1' then
tx_state <= tx;
data <= tx_byte;
end if;
when tx =>
txen <= '1';
cnt <= cnt + to_unsigned(1,cnt'length);
txd(1 downto 0) <= data(2*to_integer(cnt)+1 downto 2*to_integer(cnt));
if cnt = 3 then
-- fifo read deassert
-- read data
if tx_run = '0' then
tx_state <= idle;
else
data <= tx_byte;
end if;
end if;
end case;
end if;
end process;
end behav;
|
gpl-2.0
|
e00008858f3eb6acfebed76b454cda39
| 0.597694 | 2.822785 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_clk_slow_1.0/sources_1/new/clk_slow.vhd
| 1 | 1,675 |
----------------------------------------------------
-- Vladi & Adi --
-- TAU EE Senior year project --
-- --
--************************************************--
--************* Clocks generator *****************--
--************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity clk_slow is
Port ( clk_in : in STD_LOGIC;
clk_190hz : out STD_LOGIC;
clk_380hz : out STD_LOGIC;
clk_95hz : out STD_LOGIC;
clk_48hz : out STD_LOGIC;
clk_12hz : out STD_LOGIC;
clk1hz5 : out STD_LOGIC
-- clk_1k5hz : out STD_LOGIC;
-- clk3k : out STD_LOGIC;
-- clk_762hz : out STD_LOGIC;
-- clk_24khz : out STD_LOGIC
);
end clk_slow;
architecture Behavioral of clk_slow is
signal clk_sig: std_logic;
signal clk_cntr : std_logic_vector(25 downto 0) := (others => '0');
begin
count: process(clk_in)
begin
if rising_edge(clk_in) then
clk_cntr <= std_logic_vector(unsigned(clk_cntr)+1);
end if;
end process;
--****** for control block *****
clk_12hz <= clk_cntr(21);
clk1hz5 <= clk_cntr(24);
--******************************
--****** for tremolo **********
clk_380hz <= clk_cntr(16);
clk_190hz <= clk_cntr(17);
clk_95hz <= clk_cntr(18);
clk_48hz <= clk_cntr(19);
--******************************
--**** other clocks *****
--clk_24khz <= clk_cntr(10);
--clk3k <= clk_cntr(13);
--clk_1k5hz <= clk_cntr(14);
--clk_762hz <= clk_cntr(15);
end Behavioral;
|
mit
|
6ab17eac9e047f05a9642449da37bb50
| 0.437612 | 3.617711 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_rng.vhd
| 1 | 4,028 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
mit
|
6f47f90b9d2d8e15cf681094c99e3f04
| 0.643992 | 4.266949 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_PS_to_PL_1.0/hdl/PS_to_PL_v1_0.vhd
| 1 | 4,034 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PS_to_PL_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
AXI_to_PL : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); --VL
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end PS_to_PL_v1_0;
architecture arch_imp of PS_to_PL_v1_0 is
-- component declaration
component PS_to_PL_v1_0_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
AUDIO_OUT_FROM_AXI_TO_EFFECT : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); --VL
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component PS_to_PL_v1_0_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
PS_to_PL_v1_0_S00_AXI_inst : PS_to_PL_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
AUDIO_OUT_FROM_AXI_TO_EFFECT => AXI_to_PL, --vl
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
|
mit
|
dc4c88acb8156e35e8131780794dc339
| 0.647496 | 2.405486 | false | false | false | false |
meninge/dauphin
|
test_bench/test_fifo_nnlayer_fifo_recode.vhd
| 1 | 11,215 |
----------------------------------------------------------------
-- uut:
-- nnlayer.vhd
-- neuron.vhd
-- fsm.vhd
-- distribuf.vhd
-- recode.vhd
-- circbuf_fast.vhd
-- de
-- simple test_bench to verify nnlayer and recode behaviors in normal conditions
-- with a fifo just before nnlayer,
-- and a fifo between nnlayer and recode
-- expected result:
-- neurons should be configured in weight configuration mode
-- in normal mode, neurons should input accumulation of
-- data*weights
-- nnlayer should correctly interact with input and output fifos
-- recode should be configured in weight configuration mode
-- in normal mode, recode should act as:
-- output = (input < 0) ? 0 : input + cst[addr]
-- recode should correctly interact with input fifo
--
-- total outputs:
-- total = (sum(datas*weights[neuron]) < 0) ?
-- 0 : sum(datas*weights[neuron]) + cst[corresponding neuron]
----------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;
use ieee.numeric_std.all;
-- entity declaration for your testbench.Dont declare any ports here
ENTITY test_nnlayer_fifo IS
END test_nnlayer_fifo;
ARCHITECTURE behavior OF test_nnlayer_fifo IS
-- add component under test
-- Parameters for the neurons
constant WDATA : natural := 32;
constant WOUT : natural := WDATA;
-- Weight width for neurons and recode
constant WWEIGHT : natural := 16;
constant WACCU : natural := 32;
-- Parameters for frame and number of neurons
constant FSIZE : natural := 64;
constant NBNEU : natural := 4;
constant DATAW : natural := WDATA;
constant DEPTH : natural := 64;
constant CNTW : natural := 8;
component nnlayer is
generic (
-- Parameters for the neurons
WDATA : natural := WDATA;
WWEIGHT : natural := WWEIGHT;
WACCU : natural := WACCU;
-- Parameters for frame and number of neurons
FSIZE : natural := FSIZE;
NBNEU : natural := NBNEU
);
port (
clk : in std_logic;
clear : in std_logic;
-- Ports for Write Enable
write_mode : in std_logic;
write_data : in std_logic_vector(WDATA-1 downto 0);
write_enable : in std_logic;
write_ready : out std_logic;
-- The user-specified frame size and number of neurons
user_fsize : in std_logic_vector(15 downto 0);
user_nbneu : in std_logic_vector(15 downto 0);
-- Data input, 2 bits
data_in : in std_logic_vector(WDATA-1 downto 0);
data_in_valid : in std_logic;
data_in_ready : out std_logic;
-- Scan chain to extract values
data_out : out std_logic_vector(WACCU-1 downto 0);
data_out_valid : out std_logic;
-- Indicate to the parent component that we are reaching the end of the current frame
end_of_frame : out std_logic;
-- The output data enters a FIFO. This indicates the available room.
out_fifo_room : in std_logic_vector(15 downto 0)
);
end component;
component circbuf_fast is
generic (
DATAW : natural := DATAW;
DEPTH : natural := DEPTH;
CNTW : natural := CNTW
);
port (
reset : in std_logic;
clk : in std_logic;
fifo_in_data : in std_logic_vector(DATAW-1 downto 0);
fifo_in_rdy : out std_logic;
fifo_in_ack : in std_logic;
fifo_in_cnt : out std_logic_vector(CNTW-1 downto 0);
fifo_out_data : out std_logic_vector(DATAW-1 downto 0);
fifo_out_rdy : out std_logic;
fifo_out_ack : in std_logic;
fifo_out_cnt : out std_logic_vector(CNTW-1 downto 0)
);
end component;
component recode
generic(
WDATA : natural := WDATA;
WWEIGHT : natural := WWEIGHT;
WOUT : natural := WOUT;
FSIZE : natural := NBNEU -- warning, this is NB_NEU
);
port(
clk : in std_logic;
addr_clear : in std_logic;
write_mode : in std_logic;
write_data : in std_logic_vector(WDATA - 1 downto 0);
write_enable : in std_logic;
write_ready : out std_logic;
user_nbneu : in std_logic_vector(15 downto 0);
data_in : in std_logic_vector(WDATA-1 downto 0);
data_in_valid : in std_logic;
data_in_ready : out std_logic;
data_out : out std_logic_vector(WOUT-1 downto 0);
data_out_valid : out std_logic;
out_fifo_room : in std_logic_vector(15 downto 0)
);
end component;
-- clock period definition
constant clk_period : time := 1 ns;
signal clk : std_logic := '0';
signal clear : std_logic := '0';
-- nnlayer signals
signal write_mode : std_logic := '0';
signal write_data : std_logic_vector(WDATA-1 downto 0);
signal write_enable : std_logic := '0';
signal write_ready : std_logic := '0';
signal user_fsize : std_logic_vector(15 downto 0);
signal user_nbneu : std_logic_vector(15 downto 0);
signal data_in : std_logic_vector(WDATA-1 downto 0);
signal data_in_valid : std_logic := '0';
signal data_in_ready : std_logic := '0';
signal data_out : std_logic_vector(WACCU-1 downto 0);
signal data_out_valid : std_logic := '0';
signal end_of_frame : std_logic := '0';
signal out_fifo_room : std_logic_vector(15 downto 0);
-- for the fifo_1
signal fifo_in_data_1 : std_logic_vector(DATAW-1 downto 0);
signal fifo_in_rdy_1 : std_logic;
signal fifo_in_ack_1 : std_logic;
signal fifo_in_cnt_1 : std_logic_vector(CNTW-1 downto 0);
signal fifo_out_data_1 : std_logic_vector(DATAW-1 downto 0);
signal fifo_out_rdy_1 : std_logic;
signal fifo_out_ack_1 : std_logic;
signal fifo_out_cnt_1 : std_logic_vector(CNTW-1 downto 0);
-- for the fifo_2
signal fifo_in_data_2 : std_logic_vector(DATAW-1 downto 0);
signal fifo_in_rdy_2 : std_logic;
signal fifo_in_ack_2 : std_logic;
signal fifo_in_cnt_2 : std_logic_vector(CNTW-1 downto 0);
signal fifo_out_data_2 : std_logic_vector(DATAW-1 downto 0);
signal fifo_out_rdy_2 : std_logic;
signal fifo_out_ack_2 : std_logic;
signal fifo_out_cnt_2 : std_logic_vector(CNTW-1 downto 0);
-- recode signals
signal recode_write_mode : std_logic;
signal recode_write_data : std_logic_vector(WDATA - 1 downto 0);
signal recode_write_enable : std_logic;
signal recode_write_ready : std_logic;
signal recode_user_nbneu : std_logic_vector(15 downto 0);
signal recode_data_in : std_logic_vector(WDATA-1 downto 0);
signal recode_data_in_valid : std_logic;
signal recode_data_in_ready : std_logic;
signal recode_data_out : std_logic_vector(WOUT-1 downto 0);
signal recode_data_out_valid : std_logic;
signal recode_out_fifo_room : std_logic_vector(15 downto 0);
begin
-- Instantiate the Uni../recode.vhd:12:t Under Test (UUT)
nnlayer_1 : nnlayer
port map (
clk => clk,
clear => clear,
write_mode => write_mode,
write_data => write_data,
write_enable => write_enable,
write_ready => write_ready,
user_fsize => user_fsize,
user_nbneu => user_nbneu,
data_in => data_in,
data_in_valid => data_in_valid,
data_in_ready => data_in_ready,
data_out => data_out,
data_out_valid => data_out_valid,
end_of_frame => end_of_frame,
out_fifo_room => out_fifo_room
);
fifo_1: circbuf_fast
port map (
reset => clear,
clk => clk,
fifo_in_data => fifo_in_data_1,
fifo_in_rdy => fifo_in_rdy_1,
fifo_in_ack => fifo_in_ack_1,
fifo_in_cnt => fifo_in_cnt_1,
fifo_out_data => fifo_out_data_1,
fifo_out_rdy => fifo_out_rdy_1,
fifo_out_ack => fifo_out_ack_1,
fifo_out_cnt => fifo_out_cnt_1
);
fifo_2: circbuf_fast
port map (
reset => clear,
clk => clk,
fifo_in_data => fifo_in_data_2,
fifo_in_rdy => fifo_in_rdy_2,
fifo_in_ack => fifo_in_ack_2,
fifo_in_cnt => fifo_in_cnt_2,
fifo_out_data => fifo_out_data_2,
fifo_out_rdy => fifo_out_rdy_2,
fifo_out_ack => fifo_out_ack_2,
fifo_out_cnt => fifo_out_cnt_2
);
recode_1 : recode
port map (
clk => clk,
addr_clear => clear,
write_mode => recode_write_mode,
write_data => recode_write_data,
write_enable => recode_write_enable,
write_ready => recode_write_ready,
user_nbneu => recode_user_nbneu,
data_in => recode_data_in,
data_in_valid => recode_data_in_valid,
data_in_ready => recode_data_in_ready,
data_out => recode_data_out,
data_out_valid => recode_data_out_valid,
out_fifo_room => recode_out_fifo_room
);
-- fifo 1 & nnlayer_1
write_data <= fifo_out_data_1;
data_in <= fifo_out_data_1;
data_in_valid <= fifo_out_rdy_1 and not write_mode;
write_enable <= fifo_out_rdy_1 and write_mode;
-- fifo 2 & nnlayer_1
fifo_in_data_2 <= data_out;
fifo_in_ack_2 <= data_out_valid;
-- fifo_2 & recode
recode_data_in <= fifo_out_data_2;
recode_data_in_valid <= fifo_out_rdy_2;
fifo_out_ack_2 <= recode_data_in_ready and not recode_write_mode;
recode_write_enable <= fifo_out_rdy_1;
-- special case for config recode!
fifo_out_ack_1 <=
(write_mode and write_ready) or
(recode_write_mode and recode_write_ready) or
(not(write_mode or recode_write_mode) and data_in_ready);
recode_write_data <= fifo_out_data_1;
-- Clock process definitions( clock with 50% duty cycle is generated here.
clk_process : process
begin
clk <= '1';
wait for clk_period/2; --for 0.5 ns signal is '1'.
clk <= '0';
wait for clk_period/2; --for next 0.5 ns signal is '0'.
end process;
out_fifo_room_proc : process
begin
wait for clk_period;
out_fifo_room <= X"00FF";
wait for clk_period;
wait for clk_period;
out_fifo_room <= X"00FF";
end process;
data_in_fifo : process
begin
fifo_in_ack_1 <= '1';
wait for clk_period;
fifo_in_ack_1 <= '0';
wait for clk_period;
end process;
stim_proc: process
variable counter : integer := 0;
variable neurons : integer := 0;
begin
-------------------------------
-- TEST CHARGEMENT DES POIDS --
-------------------------------
-- reset
clear <= '1';
wait for 3*clk_period;
clear <= '0';
write_mode <= '0'; -- load weights
-- recode write config
recode_write_mode <= '1'; -- load weights
neurons := 0;
counter := 0;
fifo_in_data_1 <= X"FFFFFC18";
wait for clk_period;
wait for clk_period;
fifo_in_data_1 <= X"FFFFFC18";
wait for clk_period;
wait for clk_period;
fifo_in_data_1 <= X"FFFFFC18";
wait for clk_period;
wait for clk_period;
fifo_in_data_1 <= X"00000032";
recode_write_mode <= '0'; -- accu add
write_mode <= '1'; -- load weights
recode_write_mode <= '0';
recode_out_fifo_room <= X"000F";
-- load data into the fifo
fifo_in_data_1 <= X"00000001";
wait for 5*clk_period;
while neurons < NBNEU loop
counter := 0;
fifo_in_data_1 <= X"00000001";
while (counter < FSIZE) loop
wait for clk_period;
counter := counter + 1;
wait for clk_period;
end loop;
neurons := neurons +1;
end loop;
wait for 30*clk_period;
write_mode <= '0'; -- load weights
----------------------------
-- TEST MODE ACCUMULATION --
----------------------------
write_mode <= '0'; -- accu add
counter := 0;
fifo_in_data_1 <= X"0000000F";
while (counter < FSIZE) loop
wait for clk_period;
counter := counter + 1;
wait for clk_period;
end loop;
wait;
end process;
END;
|
mit
|
5ff730398124ef367f46c240720b44fc
| 0.6321 | 2.887487 | false | false | false | false |
thasti/dvbs
|
hdl/network/eth_rx/eth_rx_tb.vhd
| 1 | 1,394 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity eth_rx_tb is
end eth_rx_tb;
architecture behav of eth_rx_tb is
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal rxd : std_logic_vector(1 downto 0) := "00";
signal crsdv : std_logic := '0';
signal q : std_logic_vector(7 downto 0);
signal q_valid : std_logic;
begin
dut : entity work.eth_rx port map(clk, rst, rxd, crsdv, q, q_valid);
rst <= '1', '0' after 100 ns;
clk <= not clk after 10 ns;
rx_test : process
variable tmp : integer;
variable tmp_v : std_logic_vector(7 downto 0);
variable l : line;
file input_file : text is in "mpeg_packet.txt";
begin
wait until falling_edge(rst);
wait until rising_edge(clk);
wait until rising_edge(clk);
-- preamble
crsdv <= '1';
rxd <= "01";
for i in 0 to 10 loop
wait until rising_edge(clk);
end loop;
-- SFD
rxd <= "11";
wait until rising_edge(clk);
while not endfile(input_file) loop
readline(input_file, l);
read(l, tmp);
tmp_v := std_logic_vector(to_unsigned(tmp, 8));
for i in 0 to 3 loop
rxd <= tmp_v(2*i + 1) & tmp_v(2*i);
wait until rising_edge(clk);
end loop;
end loop;
for i in 0 to 1 loop
crsdv <= '0';
wait until rising_edge(clk);
crsdv <= '1';
wait until rising_edge(clk);
end loop;
crsdv <= '0';
wait;
end process;
end behav;
|
gpl-2.0
|
a204d33f89e9e5c840375a8d06befcad
| 0.629125 | 2.645161 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/user_logic.vhd
| 3 | 12,934 |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Wed Aug 15 18:20:40 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 5;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
BCLK : out STD_LOGIC;
LRCLK : out STD_LOGIC;
SDATA_I : in STD_LOGIC;
SDATA_O : out STD_LOGIC;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
COMPONENT iis_deser
PORT(
CLK_100MHZ : IN std_logic;
SCLK : IN std_logic;
LRCLK : IN std_logic;
SDATA : IN std_logic;
EN : IN std_logic;
LDATA : OUT std_logic_vector(23 downto 0);
RDATA : OUT std_logic_vector(23 downto 0);
VALID : OUT std_logic
);
END COMPONENT;
COMPONENT iis_ser
PORT(
CLK_100MHZ : IN std_logic;
SCLK : IN std_logic;
LRCLK : IN std_logic;
EN : IN std_logic;
LDATA : IN std_logic_vector(23 downto 0);
RDATA : IN std_logic_vector(23 downto 0);
SDATA : OUT std_logic
);
END COMPONENT;
signal clk_cntr : std_logic_vector(10 downto 0) := (others => '0');
--internal logic "clock" signals
signal sclk_int : std_logic;
signal lrclk_int : std_logic;
signal en : std_logic;
signal ldata_in : std_logic_vector(23 downto 0);
signal rdata_in : std_logic_vector(23 downto 0);
signal data_rdy : std_logic;
signal data_rdy_bit : std_logic := '0';
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal DataRx_L : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal DataRx_R : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal DataTx_L : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal DataTx_R : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal slv_reg4 : std_logic;
signal slv_reg_write_sel : std_logic_vector(4 downto 0);
signal slv_reg_read_sel : std_logic_vector(4 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
en <= '1';
process(Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
clk_cntr <= clk_cntr + 1;
end if;
end process;
--sclk = 100MHz / 32 = 3.125 MHz
sclk_int <= clk_cntr(4);
--lrclk = 100MHz / 2048 = 48.828125 KHz
lrclk_int <= clk_cntr(10);
Inst_iis_deser: iis_deser PORT MAP(
CLK_100MHZ => Bus2IP_Clk,
SCLK => sclk_int,
LRCLK => lrclk_int,
SDATA => SDATA_I,
EN => en,
LDATA => ldata_in,
RDATA => rdata_in,
VALID => data_rdy
);
process(Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
if (data_rdy = '1') then
DataRx_L <= x"00" & ldata_in;
DataRx_R <= x"00" & rdata_in;
end if;
end if;
end process;
Inst_iis_ser: iis_ser PORT MAP(
CLK_100MHZ => Bus2IP_Clk,
SCLK => sclk_int,
LRCLK => lrclk_int,
SDATA => SDATA_O,
EN => en,
LDATA => DataTx_L(23 downto 0),
RDATA => DataTx_R(23 downto 0)
);
LRCLK <= lrclk_int;
BCLK <= sclk_int;
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(4 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(4 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
DataTx_L <= (others => '0');
DataTx_R <= (others => '0');
data_rdy_bit <= '0';
else
case slv_reg_write_sel is
when "00100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
DataTx_L(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
DataTx_R(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001" =>
data_rdy_bit <= '0';
when others =>
if (data_rdy = '1') then
data_rdy_bit <= '1';
end if;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, DataRx_L, DataRx_R, DataTx_L, DataTx_R, data_rdy_bit ) is
begin
case slv_reg_read_sel is
when "10000" => slv_ip2bus_data <= DataRx_L;
when "01000" => slv_ip2bus_data <= DataRx_R;
when "00100" => slv_ip2bus_data <= DataTx_L;
when "00010" => slv_ip2bus_data <= DataTx_R;
when "00001" => slv_ip2bus_data <= "0000000000000000000000000000000" & data_rdy_bit;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
mit
|
e697af3c2156d406a9c8dbbc45f0f423
| 0.480207 | 3.995675 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_clk_slow_1.0/sim_1/new/clk_slow_tb.vhd
| 1 | 1,230 |
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity clk_slow_tb is
end;
architecture bench of clk_slow_tb is
component clk_slow
Port ( clk_in : in STD_LOGIC;
clk_190hz : out STD_LOGIC;
clk_380hz : out STD_LOGIC;
clk_95hz : out STD_LOGIC;
clk_48hz : out STD_LOGIC;
clk_12hz : out STD_LOGIC;
clk1hz5 : out STD_LOGIC
);
end component;
signal clk_in: STD_LOGIC;
signal clk_190hz : STD_LOGIC;
signal clk_380hz : STD_LOGIC;
signal clk_95hz : STD_LOGIC;
signal clk_48hz : STD_LOGIC;
signal clk_12hz : STD_LOGIC;
signal clk1hz5 : STD_LOGIC;
constant clock_period: time := 20 ns; --50Mhz
begin
uut: clk_slow port map ( clk_in => clk_in,
clk_190hz => clk_190hz,
clk_380hz => clk_380hz,
clk_95hz => clk_95hz,
clk_48hz => clk_48hz,
clk_12hz => clk_12hz,
clk1hz5 => clk1hz5
);
clk_process: process
begin
clk_in <= '1';
wait for clock_period/2;
clk_in <= '0';
wait for clock_period/2;
end process;
end;
|
mit
|
1cac3a17408e153545ac8d2d55f0023b
| 0.523577 | 3.315364 | false | false | false | false |
meninge/dauphin
|
test_bench/test_fifo_nnlayer.vhd
| 1 | 7,429 |
----------------------------------------------------------------
-- uut:
-- nnlayer.vhd
-- neuron.vhd
-- fsm.vhd
-- distribuf.vhd
-- circbuf_fast.vhd
-- description:
-- simple test_bench to verify nnlayer behavior in normal conditions
-- with a fifo just before
-- expected result:
-- neurons should be configured in weight configuration mode
-- in normal mode, neurons should input accumulation of
-- data*weights
-- nnlayer should correctly interact with input fifo
----------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;
use ieee.numeric_std.all;
-- entity declaration for your testbench.Dont declare any ports here
ENTITY test_fifo_nnlayer IS
END test_fifo_nnlayer;
ARCHITECTURE behavior OF test_fifo_nnlayer IS
-- add component under test
-- Parameters for the neurons
constant WDATA : natural := 32;
constant WWEIGHT : natural := 16;
constant WACCU : natural := 32;
-- Parameters for frame and number of neurons
constant FSIZE : natural := 64;
constant NBNEU : natural := 4;
constant DATAW : natural := 32;
constant DEPTH : natural := 8;
constant CNTW : natural := 16;
component nnlayer is
generic (
-- Parameters for the neurons
WDATA : natural := WDATA;
WWEIGHT : natural := WWEIGHT;
WACCU : natural := WACCU;
-- Parameters for frame and number of neurons
FSIZE : natural := FSIZE;
NBNEU : natural := NBNEU
);
port (
clk : in std_logic;
clear : in std_logic;
-- Ports for Write Enable
write_mode : in std_logic;
write_data : in std_logic_vector(WDATA-1 downto 0);
write_enable : in std_logic;
write_ready : out std_logic;
-- The user-specified frame size and number of neurons
user_fsize : in std_logic_vector(15 downto 0);
user_nbneu : in std_logic_vector(15 downto 0);
-- Data input, 2 bits
data_in : in std_logic_vector(WDATA-1 downto 0);
data_in_valid : in std_logic;
data_in_ready : out std_logic;
-- Scan chain to extract values
data_out : out std_logic_vector(WACCU-1 downto 0);
data_out_valid : out std_logic;
-- Indicate to the parent component that we are reaching the end of the current frame
end_of_frame : out std_logic;
-- The output data enters a FIFO. This indicates the available room.
out_fifo_room : in std_logic_vector(15 downto 0)
);
end component;
component circbuf_fast is
generic (
DATAW : natural := DATAW;
DEPTH : natural := DEPTH;
CNTW : natural := CNTW
);
port (
reset : in std_logic;
clk : in std_logic;
fifo_in_data : in std_logic_vector(DATAW-1 downto 0);
fifo_in_rdy : out std_logic;
fifo_in_ack : in std_logic;
fifo_in_cnt : out std_logic_vector(CNTW-1 downto 0);
fifo_out_data : out std_logic_vector(DATAW-1 downto 0);
fifo_out_rdy : out std_logic;
fifo_out_ack : in std_logic;
fifo_out_cnt : out std_logic_vector(CNTW-1 downto 0)
);
end component;
-- clock period definition
constant clk_period : time := 1 ns;
-- Control signals
signal clk : std_logic := '0';
signal clear : std_logic := '0';
-- Ports for Write Enable
signal write_mode : std_logic := '0';
signal write_data : std_logic_vector(WDATA-1 downto 0);
signal write_enable : std_logic := '0';
signal write_ready : std_logic := '0';
-- The user-specified frame size and number of neurons
signal user_fsize : std_logic_vector(15 downto 0);
signal user_nbneu : std_logic_vector(15 downto 0);
signal data_in : std_logic_vector(WDATA-1 downto 0);
signal data_in_valid : std_logic := '0';
signal data_in_ready : std_logic := '0';
-- Scan chain to extract values
signal data_out : std_logic_vector(WACCU-1 downto 0);
signal data_out_valid : std_logic := '0';
-- Indicate to the parent component that we are reaching the end of the current frame
signal end_of_frame : std_logic := '0';
-- The output data enters a FIFO. This indicates the available room.
signal out_fifo_room : std_logic_vector(15 downto 0);
-- for the fifo
signal fifo_in_data : std_logic_vector(DATAW-1 downto 0);
signal fifo_in_rdy : std_logic;
signal fifo_in_ack : std_logic;
signal fifo_in_cnt : std_logic_vector(CNTW-1 downto 0);
signal fifo_out_data : std_logic_vector(DATAW-1 downto 0);
signal fifo_out_rdy : std_logic;
signal fifo_out_ack : std_logic;
signal fifo_out_cnt : std_logic_vector(CNTW-1 downto 0);
begin
-- Instantiate the Uni../recode.vhd:12:t Under Test (UUT)
uut: nnlayer
port map (
clk => clk,
clear => clear,
-- Ports for Write Enable
write_mode => write_mode,
write_data => write_data,
write_enable => fifo_out_rdy,
write_ready => write_ready,
-- The user-specified frame size and number of neurons
user_fsize => user_fsize,
user_nbneu => user_nbneu,
-- Data input, 2 bits
data_in => data_in,
data_in_valid => data_in_valid,
data_in_ready => data_in_ready,
-- Scan chain to extract values
data_out => data_out,
data_out_valid => data_out_valid,
-- Indicate to the parent component that we are reaching the end of the current frame
end_of_frame => end_of_frame,
-- The output data enters a FIFO. This indicates the available room.
out_fifo_room => out_fifo_room
);
fifo: circbuf_fast
port map (
reset => clear,
clk => clk,
fifo_in_data => fifo_in_data,
fifo_in_rdy => fifo_in_rdy,
fifo_in_ack => fifo_in_ack,
fifo_in_cnt => fifo_in_cnt,
fifo_out_data => fifo_out_data,
fifo_out_rdy => fifo_out_rdy,
fifo_out_ack => fifo_out_ack,
fifo_out_cnt => fifo_out_cnt
);
write_data <= fifo_out_data;
data_in <= fifo_out_data;
data_in_valid <= fifo_out_rdy;
--data_in_ready <= fifo_out_ack;
fifo_out_ack <= data_in_ready or write_ready;
-- Clock process definitions( clock with 50% duty cycle is generated here.
clk_process : process
begin
clk <= '1';
wait for clk_period/2; --for 0.5 ns signal is '1'.
clk <= '0';
wait for clk_period/2; --for next 0.5 ns signal is '0'.
end process;
out_fifo_room_proc : process
begin
wait for clk_period;
out_fifo_room <= X"0007";
wait for clk_period;
wait for clk_period;
out_fifo_room <= X"0002";
end process;
stim_proc: process
variable counter : integer := 0;
variable neurons : integer := 0;
begin
-------------------------------
-- TEST CHARGEMENT DES POIDS --
-------------------------------
-- reset
clear <= '1';
wait for 3*clk_period;
clear <= '0';
write_mode <= '1'; -- load weights
while neurons < NBNEU loop
counter := 0;
while (counter < FSIZE) loop
fifo_in_data <= std_logic_vector(to_signed(counter + 10, 32));
fifo_in_ack <= '1';
wait for clk_period;
counter := counter + 1;
fifo_in_data <= std_logic_vector(to_signed(counter*10 + 10, 32));
fifo_in_ack <= '1';
wait for clk_period;
end loop;
neurons := neurons +1;
--wait for 10 * clk_period;
end loop;
wait for 100 * clk_period;
----------------------------
-- TEST MODE ACCUMULATION --
----------------------------
write_mode <= '0'; -- accu add
counter := 0;
while (counter < FSIZE) loop
wait for clk_period;
counter := counter + 1;
wait for clk_period;
end loop;
wait;
end process;
END;
|
mit
|
5a56648c059b37832c58d114f0da9757
| 0.631579 | 3.104471 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_1/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pkg.vhd
| 1 | 11,923 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_1_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_1_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_1_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_1_exdes IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(39-1 DOWNTO 0);
DOUT : OUT std_logic_vector(39-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pkg;
PACKAGE BODY system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pkg;
|
mit
|
e0128c5384dbd3e8744fdbec51f82946
| 0.51321 | 3.857328 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.vhd
| 1 | 11,912 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(35-1 DOWNTO 0);
DOUT : OUT std_logic_vector(35-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg;
PACKAGE BODY system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg;
|
mit
|
0ce82d7660b23cc5d4ea6c23f6a6d3fa
| 0.513684 | 3.881395 | false | false | false | false |
SamTheDev/VGA-VHDL-Simulator
|
VGA_SIMULATOR.vhd
| 1 | 1,888 |
------------------------------------------------------------
-- VGA Simulator projet VHDL
-- The whole system implementation that holds the three modules
-- Elhamer Oussama abdelkhalek
-- Generate a picture, save if on a spesific location on the disk, and generate the corresponding H_Sync and V_Sync
-- the three modules are setted with the 640 * 480 resolution
------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity VGA_SIMULATOR is
Port ( Reset : in STD_LOGIC;
H_SYNC : inout STD_LOGIC;
V_SYNC : inout STD_LOGIC );
end VGA_SIMULATOR;
architecture Behavioral of VGA_SIMULATOR is
component VGA is
generic ( V_SIZE, H_SIZE : integer);
Port ( Reset : in STD_LOGIC;
Pixel_clk : inout STD_LOGIC;
H_SYNC : inout STD_LOGIC;
V_SYNC : inout STD_LOGIC);
end component;
component MIRE is
generic ( V_SIZE, H_SIZE : integer);
Port ( Reset : in STD_LOGIC;
Pixel_clk : in STD_LOGIC;
R : out STD_LOGIC_VECTOR (7 downto 0);
G : out STD_LOGIC_VECTOR (7 downto 0);
B : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component image_file is
generic ( V_SIZE, H_SIZE : integer);
port ( clk, reset : in std_logic;
r,g,b : in std_logic_vector);
end component;
signal Pix_sig : std_logic;
signal R_sig : std_logic_vector(7 downto 0) ;
signal G_sig : std_logic_vector(7 downto 0);
signal B_sig : std_logic_vector(7 downto 0);
begin
VGA_Module : VGA generic map (V_SIZE => 480, H_SIZE => 640) port map (Reset, Pix_sig, H_SYNC, V_SYNC);
MIRE_Module : MIRE generic map (V_SIZE => 480, H_SIZE => 640) port map (Reset, Pix_sig, R_sig, G_sig, B_sig);
SAVE_IMAGE_MODULE : image_file generic map (V_SIZE =>480, H_SIZE => 640) port map (Pix_sig, Reset, R_sig, G_sig, B_sig);
end Behavioral;
|
mit
|
d1464977f87400be114dfc02abaa1bf2
| 0.601695 | 3.414105 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_delay_1.0/sim_1/new/delay_tb.vhd
| 1 | 2,436 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity delay_tb is
end delay_tb;
architecture Behavioral of delay_tb is
component delay is
Port ( x : in STD_LOGIC_VECTOR(31 downto 0);
y : out STD_LOGIC_VECTOR(31 downto 0);
clk_48: in std_logic :='1';
clk_24: in std_logic;
options : in STD_LOGIC_VECTOR(0 to 3);
en : in STD_LOGIC_VECTOR(0 to 3)
);
end component;
signal x : STD_LOGIC_VECTOR(31 downto 0) := "00000000000000000000000000000000";
signal y : STD_LOGIC_VECTOR(31 downto 0);
signal clk_48: std_logic := '1';
signal clk_24: std_logic;
signal options : STD_LOGIC_VECTOR(0 to 3) := "0100";
signal en : STD_LOGIC_VECTOR(0 to 3) := "0001";
-- signal addr1_temp0 : std_logic_vector (31 downto 0);
-- signal addr2_temp1 : std_logic_vector (31 downto 0);
constant clock_period: time := 20 us;
signal rand_num : integer := 0;
begin
uut: delay
port map(
x => x,
y => y,
clk_48 => clk_48,
clk_24 => clk_24,
options => options,
en => en
--addr1_temp0 => addr1_temp0,
--addr2_temp1 => addr2_temp1
);
clk_process: process
begin
clk_48 <= '1';
wait for clock_period/2;
clk_48 <= '0';
wait for clock_period/2;
end process;
clk2_process: process
begin
clk_24 <= '1';
wait for clock_period;
clk_24 <= '0';
wait for clock_period;
end process;
process
begin
x <= std_logic_vector(signed(x)+1);
wait for clock_period;
end process;
--random_num: process
-- variable seed1, seed2: positive; -- seed values for random generator
-- variable rand: real; -- random real-number value in range 0 to 1.0
-- variable range_of_rand : real := 150000.0; -- the range of random values created will be 0 to +30000.
-- begin
-- uniform(seed1, seed2, rand); -- generate random number
-- rand_num <= integer(rand*range_of_rand); -- rescale to 0..1000, convert integer part
-- x <= std_logic_vector(to_unsigned(rand_num, 32));
-- wait for 0.000020 sec;
-- end process;
end Behavioral;
|
mit
|
79e2ad12ca0fb68e9e357875ea05bbba
| 0.626437 | 3.323329 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_octaver_1.0/sim_1/new/octaver_tb.vhd
| 1 | 2,684 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity octaver_tb is
end octaver_tb;
architecture Behavioral of octaver_tb is
component octaver is
Port ( x : in STD_LOGIC_VECTOR(31 downto 0);
y : out STD_LOGIC_VECTOR(31 downto 0);
clk_48: in std_logic :='1';
clk_24: in std_logic;
options : in STD_LOGIC_VECTOR(0 to 3);
en : in STD_LOGIC_VECTOR(0 to 3);
addr1_temp0 : out std_logic_vector (31 downto 0);
addr2_temp1 : out std_logic_vector (31 downto 0)
);
end component;
signal x : STD_LOGIC_VECTOR(31 downto 0) := "00000000000000000000000000000000";
signal y : STD_LOGIC_VECTOR(31 downto 0);
signal clk_48: std_logic := '1';
signal clk_24: std_logic;
signal options : STD_LOGIC_VECTOR(0 to 3) := "0000";
signal en : STD_LOGIC_VECTOR(0 to 3) := "0100";
signal addr1_temp0 : std_logic_vector (31 downto 0);
signal addr2_temp1 : std_logic_vector (31 downto 0);
-- signal del_temp2 : std_logic_vector (31 downto 0);
-- signal del_temp_last : std_logic_vector (31 downto 0);
constant clock_period: time := 20 us;
signal rand_num : integer := 0;
begin
uut: octaver
port map(
x => x,
y => y,
clk_48 => clk_48,
clk_24 => clk_24,
options => options,
en => en
--addr1_temp0 => addr1_temp0,
--addr2_temp1 => addr2_temp1
);
clk_process: process
begin
clk_48 <= '1';
wait for clock_period/2;
clk_48 <= '0';
wait for clock_period/2;
end process;
clk2_process: process
begin
clk_24 <= '1';
wait for clock_period;
clk_24 <= '0';
wait for clock_period;
end process;
process
begin
x <= std_logic_vector(signed(x)+1);
wait for clock_period;
end process;
--random_num: process
-- variable seed1, seed2: positive; -- seed values for random generator
-- variable rand: real; -- random real-number value in range 0 to 1.0
-- variable range_of_rand : real := 150000.0; -- the range of random values created will be 0 to +30000.
-- begin
-- uniform(seed1, seed2, rand); -- generate random number
-- rand_num <= integer(rand*range_of_rand); -- rescale to 0..1000, convert integer part
-- x <= std_logic_vector(to_unsigned(rand_num, 32));
-- wait for 0.000020 sec;
-- end process;
end Behavioral;
|
mit
|
b7d8d5f76184fd6cf57d4d1c2e86d7dc
| 0.627794 | 3.309494 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_Distortion_1.0/sim_1/new/Distortion_tb.vhd
| 1 | 2,459 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/06/2017 12:37:23 PM
-- Design Name:
-- Module Name: dist_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Distortion_tb is
-- Port ( );
end Distortion_tb;
architecture Behavioral of Distortion_tb is
component Distortion
Port ( x : in STD_LOGIC_VECTOR(31 downto 0);
y : out STD_LOGIC_VECTOR(31 downto 0);
clk_48: in std_logic;
options : in STD_LOGIC_VECTOR(0 to 3);
en : in STD_LOGIC_VECTOR(0 to 3)
);
end component;
signal x: STD_LOGIC_VECTOR(31 downto 0);
signal y: STD_LOGIC_VECTOR(31 downto 0);
signal clk_48: std_logic;
signal options: STD_LOGIC_VECTOR(0 to 3):="1000";
signal en: STD_LOGIC_VECTOR(0 to 3):="1000";
constant clock_period: time := 20 us;
signal rand_num : integer := 0;
begin
uut: Distortion port map ( x => x,
y => y,
clk_48 => clk_48,
options => options,
en => en );
clk_process: process
begin
clk_48 <= '1';
wait for clock_period/2;
clk_48 <= '0';
wait for clock_period/2;
end process;
random_num: process
variable seed1, seed2: positive; -- seed values for random generator
variable rand: real; -- random real-number value in range 0 to 1.0
variable range_of_rand : real := 500000.0; -- the range of random values created will be 0 to +30000.
begin
uniform(seed1, seed2, rand); -- generate random number
rand_num <= integer(rand*range_of_rand); -- rescale to 0..1000, convert integer part
x <= std_logic_vector(to_unsigned(rand_num, 32));
wait for 0.000020 sec;
end process;
end Behavioral;
|
mit
|
9a71816348cf06b48fa7709fdc471164
| 0.568117 | 3.896989 | false | false | false | false |
thasti/dvbs
|
hdl/ps_converter/ps_converter.vhd
| 1 | 758 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ps_converter is
port (
clk : in std_logic;
rst : in std_logic;
clk_en : in std_logic;
start : in std_logic;
d : in std_logic_vector(7 downto 0);
q : out std_logic
);
end ps_converter;
architecture rtl of ps_converter is
signal reg : std_logic_vector(7 downto 0) := (others => '0');
signal cnt : unsigned(2 downto 0) := to_unsigned(0, 3);
begin
process
begin
wait until rising_edge(clk);
if rst = '1' then
reg <= (others => '0');
elsif clk_en = '1' then
if start = '1' then
reg <= d;
q <= d(7);
cnt <= to_unsigned(6, 3);
else
q <= d(to_integer(cnt));
cnt <= cnt - to_unsigned(1, 3);
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
5ce5ebe7d73dce2c03ecd66a01ab771d
| 0.604222 | 2.569492 | false | false | false | false |
paulmoon/seng440
|
huffman/huffman_testbench.vhd
| 1 | 2,743 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:24:15 07/31/2014
-- Design Name:
-- Module Name: C:/Documents and Settings/paulmoon/Desktop/SENG440/huffman/huffman_testbench.vhd
-- Project Name: huffman
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: huffman_decoder
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY huffman_testbench IS
END huffman_testbench;
ARCHITECTURE behavior OF huffman_testbench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT huffman_decoder
PORT(
clock : IN std_logic;
encoded_string : IN std_logic_vector(0 to 43);
encoding : IN string(1 to 6);
output_string : OUT string(32 downto 1)
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal encoded_string : std_logic_vector(0 to 43) := (others => '0');
signal encoding : string(1 to 6) := (others => '0');
--Outputs
signal output_string : string(32 downto 1);
-- Clock period definitions
constant clock_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: huffman_decoder PORT MAP (
clock => clock,
encoded_string => encoded_string,
encoding => encoding,
output_string => output_string
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
encoded_string <= "01011011101111001111101101110110100111011110";
encoding <= "dbecfa";
wait for 100 ns;
wait for clock_period*10;
-- output_string <= "00000000000000000000000000000000";
-- insert stimulus here
wait;
end process;
END;
|
mit
|
abeb7344fbfa7d3de03d14b3a09a26f6
| 0.595698 | 4.149773 | false | true | false | false |
medav/conware
|
conware_final/system/hdl/system_axi_dma_0_wrapper.vhd
| 1 | 20,344 |
-------------------------------------------------------------------------------
-- system_axi_dma_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_dma_v6_03_a;
use axi_dma_v6_03_a.all;
entity system_axi_dma_0_wrapper is
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(9 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(9 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_awaddr : out std_logic_vector(31 downto 0);
m_axi_sg_awlen : out std_logic_vector(7 downto 0);
m_axi_sg_awsize : out std_logic_vector(2 downto 0);
m_axi_sg_awburst : out std_logic_vector(1 downto 0);
m_axi_sg_awprot : out std_logic_vector(2 downto 0);
m_axi_sg_awcache : out std_logic_vector(3 downto 0);
m_axi_sg_awuser : out std_logic_vector(3 downto 0);
m_axi_sg_awvalid : out std_logic;
m_axi_sg_awready : in std_logic;
m_axi_sg_wdata : out std_logic_vector(31 downto 0);
m_axi_sg_wstrb : out std_logic_vector(3 downto 0);
m_axi_sg_wlast : out std_logic;
m_axi_sg_wvalid : out std_logic;
m_axi_sg_wready : in std_logic;
m_axi_sg_bresp : in std_logic_vector(1 downto 0);
m_axi_sg_bvalid : in std_logic;
m_axi_sg_bready : out std_logic;
m_axi_sg_araddr : out std_logic_vector(31 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_aruser : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(31 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(31 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(3 downto 0);
m_axis_mm2s_tid : out std_logic_vector(4 downto 0);
m_axis_mm2s_tdest : out std_logic_vector(4 downto 0);
mm2s_cntrl_reset_out_n : out std_logic;
m_axis_mm2s_cntrl_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_cntrl_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_cntrl_tvalid : out std_logic;
m_axis_mm2s_cntrl_tready : in std_logic;
m_axis_mm2s_cntrl_tlast : out std_logic;
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(31 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(3 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(3 downto 0);
s_axis_s2mm_tid : in std_logic_vector(4 downto 0);
s_axis_s2mm_tdest : in std_logic_vector(4 downto 0);
s2mm_sts_reset_out_n : out std_logic;
s_axis_s2mm_sts_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_sts_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_sts_tvalid : in std_logic;
s_axis_s2mm_sts_tready : out std_logic;
s_axis_s2mm_sts_tlast : in std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_dma_tstvec : out std_logic_vector(31 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_axi_dma_0_wrapper : entity is "axi_dma_v6_03_a";
end system_axi_dma_0_wrapper;
architecture STRUCTURE of system_axi_dma_0_wrapper is
component axi_dma is
generic (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_INCLUDE_SG : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_SG_INCLUDE_DESC_QUEUE : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_FAMILY : STRING;
C_INSTANCE : STRING
);
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_awaddr : out std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_sg_awlen : out std_logic_vector(7 downto 0);
m_axi_sg_awsize : out std_logic_vector(2 downto 0);
m_axi_sg_awburst : out std_logic_vector(1 downto 0);
m_axi_sg_awprot : out std_logic_vector(2 downto 0);
m_axi_sg_awcache : out std_logic_vector(3 downto 0);
m_axi_sg_awuser : out std_logic_vector(3 downto 0);
m_axi_sg_awvalid : out std_logic;
m_axi_sg_awready : in std_logic;
m_axi_sg_wdata : out std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0);
m_axi_sg_wstrb : out std_logic_vector((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0);
m_axi_sg_wlast : out std_logic;
m_axi_sg_wvalid : out std_logic;
m_axi_sg_wready : in std_logic;
m_axi_sg_bresp : in std_logic_vector(1 downto 0);
m_axi_sg_bvalid : in std_logic;
m_axi_sg_bready : out std_logic;
m_axi_sg_araddr : out std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_aruser : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(3 downto 0);
m_axis_mm2s_tid : out std_logic_vector(4 downto 0);
m_axis_mm2s_tdest : out std_logic_vector(4 downto 0);
mm2s_cntrl_reset_out_n : out std_logic;
m_axis_mm2s_cntrl_tdata : out std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
m_axis_mm2s_cntrl_tkeep : out std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);
m_axis_mm2s_cntrl_tvalid : out std_logic;
m_axis_mm2s_cntrl_tready : in std_logic;
m_axis_mm2s_cntrl_tlast : out std_logic;
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(3 downto 0);
s_axis_s2mm_tid : in std_logic_vector(4 downto 0);
s_axis_s2mm_tdest : in std_logic_vector(4 downto 0);
s2mm_sts_reset_out_n : out std_logic;
s_axis_s2mm_sts_tdata : in std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0);
s_axis_s2mm_sts_tkeep : in std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0);
s_axis_s2mm_sts_tvalid : in std_logic;
s_axis_s2mm_sts_tready : out std_logic;
s_axis_s2mm_sts_tlast : in std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_dma_tstvec : out std_logic_vector(31 downto 0)
);
end component;
begin
axi_dma_0 : axi_dma
generic map (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_INCLUDE_SG => 1,
C_ENABLE_MULTI_CHANNEL => 0,
C_SG_INCLUDE_DESC_QUEUE => 0,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 1,
C_SG_LENGTH_WIDTH => 23,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_INCLUDE_MM2S_DRE => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_INCLUDE_S2MM_DRE => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_NUM_S2MM_CHANNELS => 1,
C_NUM_MM2S_CHANNELS => 1,
C_FAMILY => "zynq",
C_INSTANCE => "axi_dma_0"
)
port map (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => m_axi_sg_aclk,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awaddr => m_axi_sg_awaddr,
m_axi_sg_awlen => m_axi_sg_awlen,
m_axi_sg_awsize => m_axi_sg_awsize,
m_axi_sg_awburst => m_axi_sg_awburst,
m_axi_sg_awprot => m_axi_sg_awprot,
m_axi_sg_awcache => m_axi_sg_awcache,
m_axi_sg_awuser => m_axi_sg_awuser,
m_axi_sg_awvalid => m_axi_sg_awvalid,
m_axi_sg_awready => m_axi_sg_awready,
m_axi_sg_wdata => m_axi_sg_wdata,
m_axi_sg_wstrb => m_axi_sg_wstrb,
m_axi_sg_wlast => m_axi_sg_wlast,
m_axi_sg_wvalid => m_axi_sg_wvalid,
m_axi_sg_wready => m_axi_sg_wready,
m_axi_sg_bresp => m_axi_sg_bresp,
m_axi_sg_bvalid => m_axi_sg_bvalid,
m_axi_sg_bready => m_axi_sg_bready,
m_axi_sg_araddr => m_axi_sg_araddr,
m_axi_sg_arlen => m_axi_sg_arlen,
m_axi_sg_arsize => m_axi_sg_arsize,
m_axi_sg_arburst => m_axi_sg_arburst,
m_axi_sg_arprot => m_axi_sg_arprot,
m_axi_sg_arcache => m_axi_sg_arcache,
m_axi_sg_aruser => m_axi_sg_aruser,
m_axi_sg_arvalid => m_axi_sg_arvalid,
m_axi_sg_arready => m_axi_sg_arready,
m_axi_sg_rdata => m_axi_sg_rdata,
m_axi_sg_rresp => m_axi_sg_rresp,
m_axi_sg_rlast => m_axi_sg_rlast,
m_axi_sg_rvalid => m_axi_sg_rvalid,
m_axi_sg_rready => m_axi_sg_rready,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_aruser => m_axi_mm2s_aruser,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axis_mm2s_tid => m_axis_mm2s_tid,
m_axis_mm2s_tdest => m_axis_mm2s_tdest,
mm2s_cntrl_reset_out_n => mm2s_cntrl_reset_out_n,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awuser => m_axi_s2mm_awuser,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => s_axis_s2mm_tuser,
s_axis_s2mm_tid => s_axis_s2mm_tid,
s_axis_s2mm_tdest => s_axis_s2mm_tdest,
s2mm_sts_reset_out_n => s2mm_sts_reset_out_n,
s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata,
s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep,
s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid,
s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready,
s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast,
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
end architecture STRUCTURE;
|
mit
|
3dde07db6de5070536839554b02e2012
| 0.622739 | 2.576494 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3/example_design/system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes.vhd
| 1 | 5,689 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(35-1 DOWNTO 0);
DOUT : OUT std_logic_vector(35-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes;
architecture xilinx of system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes is
signal clk_i : std_logic;
component system_axi_vdma_0_wrapper_fifo_generator_v9_3 is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(35-1 DOWNTO 0);
DOUT : OUT std_logic_vector(35-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_3
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
mit
|
90eba22908d74d67ac5714dc44fdfbfe
| 0.517841 | 4.788721 | false | false | false | false |
igraves/vhdl-gizmos
|
devices/serializers/64-8-triggered.vhd
| 1 | 1,407 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity serializer is
port(
clk : in std_logic;
input : in std_logic_vector(0 to 512);
output : out std_logic_vector(0 to 63)
);
end serializer;
architecture Behavioral of serializer is
alias reset : std_logic is input(0);
alias vector : std_logic_vector(0 to 511) is input(1 to 512);
begin
process(clk)
variable state : std_logic_vector (0 to 2) := "000";
variable text : std_logic_vector (0 to 511) := (others => '0');
begin
if clk'event AND clk = '1' then
if reset = '1' then
text := vector;
output <= text(0 to 63);
state := "001";
else
if (state = "000") then
output <= text(0 to 63);
state := "001";
elsif (state = "001") then
output <= text(64 to 127);
state := "010";
elsif (state = "010") then
output <= text(128 to 191);
state := "011";
elsif (state = "011") then
output <= text(192 to 255);
state := "100";
elsif (state = "100") then
output <= text(256 to 319);
state := "101";
elsif (state = "101") then
output <= text(320 to 383);
state := "110";
elsif (state = "110") then
output <= text(384 to 447);
state := "111";
else
output <= text(448 to 511);
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
e4bebaa9f9481368a8760760b18b2bd2
| 0.539446 | 3.5 | false | false | false | false |
meninge/dauphin
|
circbuf_fast.vhd
| 1 | 6,966 |
-- FIFO implemented as a circular buffer
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity circbuf_fast is
generic (
DATAW : natural := 32;
DEPTH : natural := 8;
CNTW : natural := 16
);
port (
reset : in std_logic;
clk : in std_logic;
fifo_in_data : in std_logic_vector(DATAW-1 downto 0);
fifo_in_rdy : out std_logic;
fifo_in_ack : in std_logic;
fifo_in_cnt : out std_logic_vector(CNTW-1 downto 0);
fifo_out_data : out std_logic_vector(DATAW-1 downto 0);
fifo_out_rdy : out std_logic;
fifo_out_ack : in std_logic;
fifo_out_cnt : out std_logic_vector(CNTW-1 downto 0)
);
end circbuf_fast;
architecture synth of circbuf_fast is
-- Compute the minimum number of bits needed to store the input value
function storebitsnb(vin : natural) return natural is
variable r : natural := 1;
variable v : natural := vin;
begin
loop
exit when v <= 1;
r := r + 1;
v := v / 2;
end loop;
return r;
end function;
-- Compute the minimum number of bits needed to store the input value
function ispower2(vin : natural) return boolean is
begin
if storebitsnb(vin-1) /= storebitsnb(vin) then return true; end if;
return false;
end function;
-- The needed index width
constant IDXW : natural := storebitsnb(DEPTH-1);
-- Detect when the number of cells is power of 2, this enables to skip some tests
constant DEPTHISPOW2 : boolean := ispower2(DEPTH);
-- The embedded memory
type mem_type is array (0 to DEPTH-1) of std_logic_vector(DATAW-1 downto 0);
signal mem : mem_type := (others => (others => '0'));
attribute ram_style : String;
attribute ram_style of mem : signal is "distributed";
-- Internal registers
signal idx_in, idx_in_n : unsigned(IDXW-1 downto 0) := to_unsigned(0, IDXW);
signal idx_out, idx_out_n : unsigned(IDXW-1 downto 0) := to_unsigned(0, IDXW);
signal reg_cnt_in, reg_cnt_in_n : unsigned(CNTW-1 downto 0) := to_unsigned(0, CNTW);
signal reg_cnt_out, reg_cnt_out_n : unsigned(CNTW-1 downto 0) := to_unsigned(0, CNTW);
signal reg_in2out, reg_in2out_n : std_logic;
signal reg_out2in, reg_out2in_n : std_logic;
signal regout_data : std_logic_vector(DATAW-1 downto 0) := (others => '0');
signal regin_rdy, regin_rdy_n : std_logic := '1';
signal regout_rdy, regout_rdy_n : std_logic := '0';
-- Signals for mem write enable and read enable
signal sigmem_ren : std_logic := '0';
signal sigmem_wen : std_logic := '0';
-- Signals to enable update the in and out indexes
signal idx_in_we : std_logic := '0';
signal idx_out_we : std_logic := '0';
begin
---------------------------------------------
----------- Sequential processes ------------
---------------------------------------------
process (clk)
begin
if rising_edge(clk) then
if idx_in_we = '1' then
idx_in <= idx_in_n;
end if;
if idx_out_we = '1' then
idx_out <= idx_out_n;
end if;
reg_cnt_in <= reg_cnt_in_n;
reg_cnt_out <= reg_cnt_out_n;
reg_in2out <= reg_in2out_n;
reg_out2in <= reg_out2in_n;
regin_rdy <= regin_rdy_n;
regout_rdy <= regout_rdy_n;
-- Write the input value to the memory
if sigmem_wen = '1' then
mem(to_integer(idx_in)) <= fifo_in_data;
end if;
-- Read the output value from the memory
if sigmem_ren = '1' then
regout_data <= mem(to_integer(idx_out));
end if;
end if;
end process;
---------------------------------------------
--------- Combinatorial processes -----------
---------------------------------------------
process (
reset,
reg_cnt_in, reg_cnt_out,
reg_in2out, reg_out2in,
idx_in, idx_out,
regin_rdy, regout_rdy,
fifo_in_ack, fifo_out_ack
)
variable var_doin : std_logic := '0';
variable var_doout : std_logic := '0';
variable var_cnt_inc : unsigned(CNTW-1 downto 0) := to_unsigned(0, CNTW);
begin
-- Default values for the variables
var_doin := '0';
var_doout := '0';
-- Default next values for internal registers
idx_in_we <= '0';
idx_out_we <= '0';
idx_in_n <= idx_in;
idx_out_n <= idx_out;
reg_cnt_in_n <= reg_cnt_in;
reg_cnt_out_n <= reg_cnt_out;
reg_in2out_n <= '0';
reg_out2in_n <= '0';
regin_rdy_n <= regin_rdy;
regout_rdy_n <= regout_rdy;
-- Default values for internal signals
sigmem_wen <= '0';
sigmem_ren <= '0';
-- Handle FIFO input
if (regin_rdy = '1') and (fifo_in_ack = '1') then
sigmem_wen <= '1';
var_doin := '1';
idx_in_we <= '1';
reg_in2out_n <= '1';
end if;
-- Handle FIFO output
if (regout_rdy = '1') and (fifo_out_ack = '1') then
sigmem_ren <= '1';
var_doout := '1';
idx_out_we <= '1';
reg_out2in_n <= '1';
-- Don't increment index when reading the last value
if reg_cnt_out = 1 then
sigmem_ren <= '0';
idx_out_we <= '0';
end if;
end if;
-- Increment the output counter by +1 if doing only input, or -1 if doing only output
var_cnt_inc(CNTW-1 downto 1) := (others => var_doout and not reg_in2out);
var_cnt_inc(0) := var_doout xor reg_in2out;
-- Next value for the counter
reg_cnt_out_n <= reg_cnt_out + var_cnt_inc;
-- Increment the input counter by +1 if doing only output, or -1 if doing only input
var_cnt_inc(CNTW-1 downto 1) := (others => var_doin and not reg_out2in);
var_cnt_inc(0) := var_doin xor reg_out2in;
-- Next value for the counter
reg_cnt_in_n <= reg_cnt_in + var_cnt_inc;
-- Next value for the in_rdy register
if reg_cnt_in = 1 then
regin_rdy_n <= (not var_doin) or reg_out2in;
end if;
-- Next value for the out_rdy register
if reg_cnt_out = 1 then
regout_rdy_n <= not var_doout;
end if;
-- Perform one mem read to initialize the output register
if (reg_cnt_out = 1) and (regout_rdy = '0') then
sigmem_ren <= '1';
regout_rdy_n <= '1';
idx_out_we <= '1';
end if;
-- Systematically compute the next value of the in index
idx_in_n <= idx_in + 1;
if (DEPTHISPOW2 = false) and (idx_in = DEPTH-1) then
idx_in_n <= to_unsigned(0, IDXW);
end if;
-- Systematically compute the next value of the out index
idx_out_n <= idx_out + 1;
if (DEPTHISPOW2 = false) and (idx_out = DEPTH-1) then
idx_out_n <= to_unsigned(0, IDXW);
end if;
-- Handle reset
-- Note: The memory content is not affected by reset
if reset = '1' then
idx_in_n <= to_unsigned(0, IDXW);
idx_out_n <= to_unsigned(0, IDXW);
reg_cnt_in_n <= to_unsigned(DEPTH, CNTW);
reg_cnt_out_n <= to_unsigned(0, CNTW);
regin_rdy_n <= '1';
regout_rdy_n <= '0';
idx_in_we <= '1';
idx_out_we <= '1';
end if;
end process;
---------------------------------------------
----------- Ports assignements --------------
---------------------------------------------
fifo_in_rdy <= regin_rdy;
fifo_out_rdy <= regout_rdy;
fifo_out_data <= regout_data;
fifo_in_cnt <= std_logic_vector(reg_cnt_in);
fifo_out_cnt <= std_logic_vector(reg_cnt_out);
end architecture;
|
mit
|
d37fc2a8518938b2fea62a17b9235048
| 0.593885 | 2.79759 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dgen.vhd
| 1 | 6,070 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
SIGNAL wr_d_sel : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
gen_fifo_stim: IF(C_CH_TYPE /= 2) GENERATE
-- DIN_WIDTH < DOUT_WIDTH
gen_din_lt_dout: IF(C_DIN_WIDTH < C_DOUT_WIDTH) GENERATE
BEGIN
pr_w_en <= (AND_REDUCE(wr_d_sel)) AND PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DOUT_WIDTH-C_DIN_WIDTH*conv_integer(wr_d_sel)-1 DOWNTO C_DOUT_WIDTH-C_DIN_WIDTH*(conv_integer(wr_d_sel)+1));
PROCESS(WR_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
wr_d_sel <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK = '1') THEN
IF(FULL = '0' AND PRC_WR_EN = '1') THEN
wr_d_sel <= wr_d_sel + "1";
END IF;
END IF;
END PROCESS;
END GENERATE gen_din_lt_dout;
-- DIN_WIDTH >= DOUT_WIDTH
gen_din_gteq_dout:IF(C_DIN_WIDTH >= C_DOUT_WIDTH) GENERATE
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END GENERATE gen_din_gteq_dout;
END GENERATE gen_fifo_stim;
----------------------------------------------
-- Wiring logic stimulus generation
----------------------------------------------
gen_wiring_stim: IF (C_CH_TYPE = 2) GENERATE
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
pr_w_en <= PRC_WR_EN;
END GENERATE gen_wiring_stim;
END ARCHITECTURE;
|
mit
|
cab99fec2d2a7ebd0d1a7c7ead6d0011
| 0.597694 | 3.81761 | false | false | false | false |
groggemans/block-mario
|
Broncode/MMU.vhd
| 1 | 4,817 |
--
-- @file MMU.vhd
-- @date December, 2013
-- @author G. Roggemans <[email protected]>
-- @copyright Copyright (c) GROG [https://grog.be] 2013, All Rights Reserved
--
-- This application is free software: you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- This application is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
-- for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this application. If not, see <http://www.gnu.org/licenses/>.
--
--
-- entity MMU
--
-- MMU(Memory Managment Unit) verzorgt de interactie met het werk en level geheugen.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.sig_pkg.all;
entity MMU is
Port ( clk : in STD_LOGIC; -- klok
com : in STD_LOGIC_VECTOR (2 downto 0) := "000"; -- Com vector
com_ok : inout STD_LOGIC_VECTOR (0 downto 0) := "0"; -- Com ok bit
data_in : in core_register := ("0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000"); -- AOI vector in
data_out : out core_register := ("0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000"); -- AOI vector out
f_ram_do : in STD_LOGIC_VECTOR (3 downto 0) := "0000"; -- ram data uitgang
f_ram_di : out STD_LOGIC_VECTOR (3 downto 0) := "0000"; -- ram data ingang
f_ram_adr : out STD_LOGIC_VECTOR (9 downto 0); -- ram adres ingang
f_ram_we : out STD_LOGIC_VECTOR(0 DOWNTO 0) := "0"; -- ram write enable
lvl_rom_do : in STD_LOGIC_VECTOR (3 downto 0) := "0000"; -- rom data uitgang
lvl_rom_adr : out STD_LOGIC_VECTOR (11 downto 0); -- rom adres ingang
rom_lvl : in integer range 0 to 4; -- op te halen lvl (scherm)
X : in integer range 0 to 31; -- X van OOI voor AOI
Y : in integer range 0 to 23); -- Y van OOI voor AOI
end MMU;
architecture Behavioral of MMU is
signal lvl_load_c : integer range 0 to 770 := 0; -- teller voor level load
signal ram_load_c : integer range 0 to 13 := 0; -- teller voor ram load
signal ram_load_w : integer range 0 to 2 := 0; -- hulp teller ram load
signal ram_load_h : integer range 0 to 3 := 0; -- hulp teller ram load
begin
process (clk)
begin
if rising_edge (clk) then
case com is
-- lvl loading
when "001" =>
lvl_load_c <= lvl_load_c + 1;
-- adres bepalen
if lvl_load_c > 0 and lvl_load_c < 769 then
lvl_rom_adr <= std_logic_vector(to_unsigned((lvl_load_c - 1) + ((rom_lvl) * 768),12));
end if;
-- data verplaatsen
if lvl_load_c > 1 and lvl_load_c < 770 then
f_ram_adr <= std_logic_vector(to_unsigned(lvl_load_c - 2,10));
f_ram_di <= lvl_rom_do;
f_ram_we <= "1";
end if;
-- lvl load gedaan
if lvl_load_c = 770 then
lvl_load_c <= 0;
com_ok <= "1";
f_ram_we <= "0";
end if;
-- w_ram loading
when "010" | "100" | "110" =>
-- count w_ram
if ram_load_w = 2 then
ram_load_w <= 0;
ram_load_h <= ram_load_h + 1;
else
ram_load_w <= ram_load_w + 1;
end if;
ram_load_c <= ram_load_c + 1;
-- w_ram laden
if com = "010" or com ="110" then
f_ram_adr <= std_logic_vector(to_unsigned((((ram_load_h + (Y-2)) * 32) + (ram_load_w + (X-1))),10));
if ram_load_c = 13 then
com_ok <= "1";
end if;
if ram_load_c > 0 then
data_out(ram_load_c - 2) <= f_ram_do;
end if;
--w_ram terugschrijven
elsif com = "100" then
if ram_load_c < 12 then
f_ram_adr <= std_logic_vector(to_unsigned((((ram_load_h + (Y-2)) * 32) + (ram_load_w + (X-1))),10));
f_ram_di <= data_in(ram_load_c);
f_ram_we <= "1";
else
com_ok <= "1";
f_ram_we <= "0";
end if;
end if;
-- reset toestant
when others =>
com_ok <= "0";
ram_load_c <= 0;
ram_load_w <= 0;
ram_load_h <= 0;
end case;
end if;
end process;
end Behavioral;
|
lgpl-3.0
|
b1e699f874d2b7e22cef6338619eb2a7
| 0.533112 | 3.411473 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_rng.vhd
| 1 | 4,028 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_5_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
mit
|
6459154bd32d1f695d261e830c187e0c
| 0.643992 | 4.266949 | false | false | false | false |
thasti/dvbs
|
hdl/ps_converter/ps_converter_tb.vhd
| 1 | 1,675 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity ps_converter_tb is
end ps_converter_tb;
architecture tb of ps_converter_tb is
-- interface signals
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal clk_en : std_logic := '0';
signal start : std_logic := '0';
signal d : std_logic_vector(7 downto 0) := (others => '0');
signal q : std_logic;
-- number of bits to check
constant n_byte : positive := 100;
-- test vector
type byte_array is array(0 to n_byte-1) of std_logic_vector(7 downto 0);
signal rand_vector : byte_array;
begin
dut : entity work.ps_converter
port map(clk => clk, rst => rst, clk_en => clk_en, start => start, d => d, q => q);
clk <= not clk after 100 ns;
rst <= '0' after 500 ns;
prepare : process
variable seed1, seed2 : positive;
variable rand : real;
variable rand_unsigned : std_logic_vector(7 downto 0);
begin
for i in 0 to n_byte-1 loop
uniform(seed1, seed2, rand);
rand_unsigned := std_logic_vector(to_unsigned(integer(round(255.0*rand)),8));
rand_vector(i) <= rand_unsigned;
end loop;
wait;
end process;
test : process
begin
wait until falling_edge(rst);
wait until rising_edge(clk);
wait until falling_edge(clk);
for i in 0 to n_byte - 1 loop
clk_en <= '1';
start <= '1';
d <= rand_vector(i);
for j in 0 to 7 loop
wait until rising_edge(clk);
start <= '0';
wait until falling_edge(clk);
assert q = rand_vector(i)(7-j)
report "Q output error with i = " & integer'image(i) & " and j = " & integer'image(j) & "."
severity warning;
end loop;
end loop;
end process;
end tb;
|
gpl-2.0
|
6fe20bf8ec760d0963091ee446c603f3
| 0.639403 | 2.759473 | false | false | false | false |
meninge/dauphin
|
distribuf.vhd
| 1 | 2,466 |
-- This is multi-stage shift register designed to limit fanout
-- There is at least one register, there may be more depending on wanted fanout
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity distribuf is
generic(
WDATA : natural := 20;
NBOUT : natural := 20;
FANOUT : natural := 20
);
port(
clk : in std_logic;
-- Input
idata : in std_logic_vector(WDATA-1 downto 0);
-- Output
odata : out std_logic_vector(WDATA*NBOUT-1 downto 0)
);
end distribuf;
architecture synth of distribuf is
-- Stupid compnent declaration for recursive instantiation
component distribuf is
generic(
WDATA : natural := 20;
NBOUT : natural := 20;
FANOUT : natural := 20
);
port(
clk : in std_logic;
-- Input
idata : in std_logic_vector(WDATA-1 downto 0);
-- Outputs
odata : out std_logic_vector(WDATA*NBOUT-1 downto 0)
);
end component;
-- The number of registers needed in the local stage
constant NBREGS : natural := (NBOUT + FANOUT - 1) / FANOUT;
-- The registers, and the signal to compute their input
signal regs, regs_n : std_logic_vector(NBREGS*WDATA-1 downto 0) := (others => '0');
begin
-- If the fanout is low enough, just connect the input port to the registers
gen_lowfan_in: if NBREGS <= FANOUT generate
gen_lowfan_in_loop: for i in 0 to NBREGS-1 generate
regs_n((i+1)*WDATA-1 downto i*WDATA) <= idata;
end generate;
end generate;
-- If the fanout is high enough, recursively instantiate a sub-component
gen_highfan_in: if NBREGS > FANOUT generate
-- Instantiate the sub-stage
i_stage: distribuf
generic map (
WDATA => WDATA,
NBOUT => NBREGS,
FANOUT => FANOUT
)
port map (
clk => clk,
idata => idata,
odata => regs_n
);
end generate;
-- Write to registers
process(clk)
begin
if rising_edge(clk) then
regs <= regs_n;
end if;
end process;
-- Connect outputs: first guaranteed max-fanout outputs
gen_maxfan: if NBREGS > 1 generate
gen_maxfan_reg: for r in 0 to NBREGS-2 generate
gen_maxfan_regloop: for i in r * FANOUT to (r+1) * FANOUT - 1 generate
odata((i+1)*WDATA-1 downto i*WDATA) <= regs((r+1) * WDATA - 1 downto r * WDATA);
end generate;
end generate;
end generate;
-- Connect last outputs
gen_lastout_loop: for i in (NBREGS-1) * FANOUT to NBOUT - 1 generate
odata((i+1)*WDATA-1 downto i*WDATA) <= regs(NBREGS * WDATA - 1 downto (NBREGS-1) * WDATA);
end generate;
end architecture;
|
mit
|
eba79c066992fbfeb1ef3727e4d34b8b
| 0.671533 | 3.15749 | false | false | false | false |
mgajda/clash-demo-digitalclock
|
TopEntity.vhd
| 1 | 1,673 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:12:12 10/24/2014
-- Design Name:
-- Module Name: SevenSeg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD;
use IEEE.NUMERIC_STD.ALL;
use work.all;
use work.types.all;
use work.topEntity_0;
--library UNISIM;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SevenSeg is
port ( Seg7 : OUT STD_LOGIC_VECTOR(6 downto 0)
; Seg7_AN : OUT STD_LOGIC_VECTOR(3 downto 0)
; Seg7_DP : OUT STD_LOGIC
; Switch : IN STD_LOGIC_VECTOR(7 downto 0)
; Led : OUT STD_LOGIC_VECTOR(7 downto 0)
; clk : IN STD_LOGIC
);
end SevenSeg;
ARCHITECTURE Behavioral OF SevenSeg IS
signal recordish : product2;
signal clkin : STD_LOGIC;
BEGIN
t : entity topEntity_0 PORT MAP (
system1000 => clkin
, system1000_rst => '1'
, topLet_o => recordish
);
clkin <= clk;
Seg7_an <= toSLV(recordish.product2_sel0);
Seg7 <= toSLV(recordish.product2_sel1);
Seg7_DP <= '1';
Led <= Switch;
END Behavioral;
|
bsd-3-clause
|
6d3f01a82c776ce25a325f4eaa40b377
| 0.588763 | 3.621212 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_tb.vhd
| 1 | 6,128 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_tb IS
END ENTITY;
ARCHITECTURE system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4000 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth
system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth_inst:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 41
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
mit
|
df99ee9012cd5ed0ed0085dd6917f7f5
| 0.63267 | 4.050231 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pctrl.vhd
| 1 | 15,657 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
mit
|
8faf945eff15c333a4d0f47778a190a2
| 0.525133 | 3.364926 | false | false | false | false |
meninge/dauphin
|
myaxifullmaster_v1_0_M00_AXI.vhd
| 1 | 30,895 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity myaxifullmaster_v1_0_M00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths
C_M_AXI_BURST_LEN : integer := 16;
-- Thread ID Width
C_M_AXI_ID_WIDTH : integer := 1;
-- Width of Address Bus
C_M_AXI_ADDR_WIDTH : integer := 32;
-- Width of Data Bus
C_M_AXI_DATA_WIDTH : integer := 32;
-- Width of User Write Address Bus
C_M_AXI_AWUSER_WIDTH : integer := 0;
-- Width of User Read Address Bus
C_M_AXI_ARUSER_WIDTH : integer := 0;
-- Width of User Write Data Bus
C_M_AXI_WUSER_WIDTH : integer := 0;
-- Width of User Read Data Bus
C_M_AXI_RUSER_WIDTH : integer := 0;
-- Width of User Response Bus
C_M_AXI_BUSER_WIDTH : integer := 0
);
port (
-- Users to add ports here
mymaster_addr_inw : in std_logic_vector(31 downto 0);
mymaster_addr_inr : in std_logic_vector(31 downto 0);
mymaster_burstnb_inw : in std_logic_vector(31 downto 0);
mymaster_burstnb_inr : in std_logic_vector(31 downto 0);
mymaster_startw : in std_logic;
mymaster_startr : in std_logic;
mymaster_busyw : out std_logic;
mymaster_busyr : out std_logic;
mymaster_sensor : out std_logic_vector(31 downto 0); -- For various debug signals
mymaster_fifor_data : out std_logic_vector(31 downto 0);
mymaster_fifor_en : out std_logic;
mymaster_fifor_cnt : in std_logic_vector(15 downto 0);
mymaster_fifow_data : in std_logic_vector(31 downto 0);
mymaster_fifow_en : out std_logic;
mymaster_fifow_cnt : in std_logic_vector(15 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal.
M_AXI_ACLK : in std_logic;
-- Global Reset Singal. This Signal is Active Low
M_AXI_ARESETN : in std_logic;
-- Master Interface Write Address ID
M_AXI_AWID : out std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
-- Master Interface Write Address
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
-- Lock type. Provides additional information about the
-- atomic characteristics of the transfer.
M_AXI_AWLOCK : out std_logic;
-- Memory type. This signal indicates how transactions
-- are required to progress through a system.
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
-- Quality of Service, QoS identifier sent for each write transaction.
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
-- Optional User-defined signal in the write address channel.
M_AXI_AWUSER : out std_logic_vector(C_M_AXI_AWUSER_WIDTH-1 downto 0);
-- Write address valid. This signal indicates that
-- the channel is signaling valid write address and control information.
M_AXI_AWVALID : out std_logic;
-- Write address ready. This signal indicates that
-- the slave is ready to accept an address and associated control signals
M_AXI_AWREADY : in std_logic;
-- Master Interface Write Data.
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte
-- lanes hold valid data. There is one write strobe
-- bit for each eight bits of the write data bus.
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
-- Write last. This signal indicates the last transfer in a write burst.
M_AXI_WLAST : out std_logic;
-- Optional User-defined signal in the write data channel.
M_AXI_WUSER : out std_logic_vector(C_M_AXI_WUSER_WIDTH-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available
M_AXI_WVALID : out std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
M_AXI_WREADY : in std_logic;
-- Master Interface Write Response.
M_AXI_BID : in std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
-- Write response. This signal indicates the status of the write transaction.
M_AXI_BRESP : in std_logic_vector(1 downto 0);
-- Optional User-defined signal in the write response channel
M_AXI_BUSER : in std_logic_vector(C_M_AXI_BUSER_WIDTH-1 downto 0);
-- Write response valid. This signal indicates that the
-- channel is signaling a valid write response.
M_AXI_BVALID : in std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
M_AXI_BREADY : out std_logic;
-- Master Interface Read Address.
M_AXI_ARID : out std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
-- Read address. This signal indicates the initial
-- address of a read burst transaction.
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
-- Lock type. Provides additional information about the
-- atomic characteristics of the transfer.
M_AXI_ARLOCK : out std_logic;
-- Memory type. This signal indicates how transactions
-- are required to progress through a system.
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
-- Quality of Service, QoS identifier sent for each read transaction
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
-- Optional User-defined signal in the read address channel.
M_AXI_ARUSER : out std_logic_vector(C_M_AXI_ARUSER_WIDTH-1 downto 0);
-- Write address valid. This signal indicates that
-- the channel is signaling valid read address and control information
M_AXI_ARVALID : out std_logic;
-- Read address ready. This signal indicates that
-- the slave is ready to accept an address and associated control signals
M_AXI_ARREADY : in std_logic;
-- Read ID tag. This signal is the identification tag
-- for the read data group of signals generated by the slave.
M_AXI_RID : in std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
-- Master Read Data
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the read transfer
M_AXI_RRESP : in std_logic_vector(1 downto 0);
-- Read last. This signal indicates the last transfer in a read burst
M_AXI_RLAST : in std_logic;
-- Optional User-defined signal in the read address channel.
M_AXI_RUSER : in std_logic_vector(C_M_AXI_RUSER_WIDTH-1 downto 0);
-- Read valid. This signal indicates that the channel
-- is signaling the required read data.
M_AXI_RVALID : in std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
M_AXI_RREADY : out std_logic
);
end myaxifullmaster_v1_0_M00_AXI;
architecture implementation of myaxifullmaster_v1_0_M00_AXI is
-- Function called clogb2 that the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
-- C_TRANSACTIONS_NUM is the width of the index counter for
-- number of beats in a burst write or burst read transaction.
constant C_TRANSACTIONS_NUM : integer := clogb2(C_M_AXI_BURST_LEN-1);
-- State machine to initialize counter, initialize write transactions,
-- initialize read transactions and comparison of read data with the written data words.
signal write_busy : std_logic := '0';
signal read_busy : std_logic := '0';
-- AXI4FULL signals
--AXI4 internal temp signals
signal axi_awaddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awvalid : std_logic;
signal axi_wdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal axi_wlast : std_logic;
signal axi_wvalid : std_logic;
signal axi_bready : std_logic;
signal axi_araddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arvalid : std_logic;
signal axi_rready : std_logic;
-- Beat counts in current bursts
signal write_index : unsigned(C_TRANSACTIONS_NUM downto 0);
signal read_index : unsigned(C_TRANSACTIONS_NUM downto 0);
-- Buffered flags to indicate end of current bursts
signal write_index_end : std_logic := '0';
signal read_index_end : std_logic := '0';
-- Size of C_M_AXI_BURST_LEN length burst in bytes
signal burst_size_bytes : std_logic_vector(31 downto 0);
-- Burst counters
signal write_burst_counter : unsigned(31 downto 0);
signal read_burst_counter : unsigned(31 downto 0);
-- Buffered flags to indicate end of bursts
signal write_burst_end : std_logic := '0';
signal read_burst_end : std_logic := '0';
signal start_single_burst_write : std_logic;
signal start_single_burst_read : std_logic;
signal writes_done : std_logic;
signal reads_done : std_logic;
signal burst_write_active : std_logic;
signal burst_read_active : std_logic;
--Interface response error flags
signal write_resp_error : std_logic;
signal read_resp_error : std_logic;
signal wnext : std_logic;
signal rnext : std_logic;
begin
----------------------
-- I/O Connections assignments
----------------------
--I/O Connections. Write Address (AW)
M_AXI_AWID <= (others => '0');
--The AXI address is a concatenation of the target base address + active offset range
M_AXI_AWADDR <= axi_awaddr;
--Burst LENgth is number of transaction beats, minus 1
M_AXI_AWLEN <= std_logic_vector( to_unsigned(C_M_AXI_BURST_LEN - 1, 8) );
--Size should be C_M_AXI_DATA_WIDTH, in 2^SIZE bytes, otherwise narrow bursts are used
M_AXI_AWSIZE <= std_logic_vector( to_unsigned(clogb2((C_M_AXI_DATA_WIDTH/8)-1), 3) );
--INCR burst type is usually used, except for keyhole bursts
M_AXI_AWBURST <= "01";
M_AXI_AWLOCK <= '0';
--Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache.
M_AXI_AWCACHE <= "0010";
M_AXI_AWPROT <= "000";
M_AXI_AWQOS <= x"0";
M_AXI_AWUSER <= (others => '1');
M_AXI_AWVALID <= axi_awvalid;
--Write Data(W)
M_AXI_WDATA <= axi_wdata;
--WARNING: In the current code, all bursts are complete and aligned
M_AXI_WSTRB <= (others => '1');
M_AXI_WLAST <= axi_wlast;
M_AXI_WUSER <= (others => '0');
M_AXI_WVALID <= axi_wvalid;
--Write Response (B)
M_AXI_BREADY <= axi_bready;
--Read Address (AR)
M_AXI_ARID <= (others => '0');
M_AXI_ARADDR <= axi_araddr;
--Burst LENgth is number of transaction beats, minus 1
M_AXI_ARLEN <= std_logic_vector( to_unsigned(C_M_AXI_BURST_LEN - 1, 8) );
--Size should be C_M_AXI_DATA_WIDTH, in 2^n bytes, otherwise narrow bursts are used
M_AXI_ARSIZE <= std_logic_vector( to_unsigned( clogb2((C_M_AXI_DATA_WIDTH/8)-1),3 ));
--INCR burst type is usually used, except for keyhole bursts
M_AXI_ARBURST <= "01";
M_AXI_ARLOCK <= '0';
--Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache.
M_AXI_ARCACHE <= "0010";
M_AXI_ARPROT <= "000";
M_AXI_ARQOS <= x"0";
M_AXI_ARUSER <= (others => '1');
M_AXI_ARVALID <= axi_arvalid;
--Read and Read Response (R)
M_AXI_RREADY <= axi_rready;
-- Utility signal: burst size in bytes
burst_size_bytes <= std_logic_vector(to_unsigned(C_M_AXI_BURST_LEN * (C_M_AXI_DATA_WIDTH/8), burst_size_bytes'length));
----------------------
-- Write Address Channel
----------------------
-- The purpose of the write address channel is to request the address and
-- command information for the entire transaction. It is a single beat
-- of information.
-- The AXI4 Write address channel in this example will continue to initiate
-- write commands as fast as it is allowed by the slave/interconnect.
-- The address will be incremented on each accepted address transaction,
-- by burst_size_byte to point to the next address.
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startw = '1') then
axi_awvalid <= '0';
else
-- If previously not valid , start next transaction
if (axi_awvalid = '0') and (start_single_burst_write = '1') then
axi_awvalid <= '1';
-- Once asserted, VALIDs cannot be deasserted,
-- so axi_awvalid must wait until transaction is accepted
elsif (M_AXI_AWREADY = '1') and (axi_awvalid = '1') then
axi_awvalid <= '0';
else
axi_awvalid <= axi_awvalid;
end if;
end if;
end if;
end process;
-- Next address after AWREADY indicates previous address acceptance
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startw = '1') then
axi_awaddr <= mymaster_addr_inw;
else
if (M_AXI_AWREADY= '1') and (axi_awvalid = '1') then
axi_awaddr <= std_logic_vector(unsigned(axi_awaddr) + unsigned(burst_size_bytes));
end if;
end if;
end if;
end process;
----------------------
-- Write Data Channel
----------------------
--The write data will continually try to push write data across the interface.
--The amount of data accepted will depend on the AXI slave and the AXI
--Interconnect settings, such as if there are FIFOs enabled in interconnect.
--Note that there is no explicit timing relationship to the write address channel.
--The write channel has its own throttling flag, separate from the AW channel.
--Synchronization between the channels must be determined by the user.
--The simpliest but lowest performance would be to only issue one address write
--and write data burst at a time.
--In this example they are kept in sync by using the same address increment
--and burst sizes. Then the AW and W channels have their transactions measured
--with threshold counters as part of the user logic, to make sure neither
--channel gets too far ahead of each other.
--Forward movement occurs when the write channel is valid and ready
wnext <= M_AXI_WREADY and axi_wvalid;
-- WVALID logic, similar to the axi_awvalid always block above
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startw = '1') then
axi_wvalid <= '0';
else
if (axi_wvalid = '0') and (start_single_burst_write = '1') then
-- If previously not valid, start next transaction
axi_wvalid <= '1';
-- If WREADY and too many writes, throttle WVALID
-- Once asserted, VALIDs cannot be deasserted, so WVALID must wait until burst is complete with WLAST
elsif (wnext = '1') and (axi_wlast = '1') then
axi_wvalid <= '0';
else
axi_wvalid <= axi_wvalid;
end if;
end if;
end if;
end process;
-- WLAST generation on the MSB of a counter underflow
-- WVALID logic, similar to the axi_awvalid always block above
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startw = '1') then
axi_wlast <= '0';
-- axi_wlast is asserted when the write index
-- count reaches the penultimate count to synchronize
-- with the last write data when write_index is b1111
-- elsif (&(write_index[C_TRANSACTIONS_NUM-1:1])&& ~write_index[0] && wnext)
else
if (( (write_index = C_M_AXI_BURST_LEN-2) and C_M_AXI_BURST_LEN >= 2) and wnext = '1' ) or (C_M_AXI_BURST_LEN = 1) then
axi_wlast <= '1';
-- Deassert axi_wlast when the last write data has been
-- accepted by the slave with a valid response
elsif wnext = '1' then
axi_wlast <= '0';
elsif (axi_wlast = '1') and (C_M_AXI_BURST_LEN = 1) then
axi_wlast <= '0';
end if;
end if;
end if;
end process;
-- Burst length counter
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (start_single_burst_write = '1') or (mymaster_startw = '1') then
write_index <= (others => '0');
else
if (wnext = '1') and (write_index /= C_M_AXI_BURST_LEN-1) then
write_index <= write_index + 1;
end if;
end if;
end if;
end process;
------------------------------
-- Write Response (B) Channel
------------------------------
--The write response channel provides feedback that the write has committed
--to memory. BREADY will occur when all of the data and the write address
--has arrived and been accepted by the slave.
--The write issuance (number of outstanding write addresses) is started by
--the Address Write transfer, and is completed by a BREADY/BRESP.
--While negating BREADY will eventually throttle the AWREADY signal,
--it is best not to throttle the whole data channel this way.
--The BRESP bit [1] is used indicate any errors from the interconnect or
--slave for the entire write burst. This example will capture the error
--into the ERROR output.
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startw = '1') then
axi_bready <= '0';
-- accept/acknowledge bresp with axi_bready by the master
-- when M_AXI_BVALID is asserted by slave
else
if (M_AXI_BVALID = '1') and (axi_bready = '0') then
axi_bready <= '1';
-- deassert after one clock cycle
elsif axi_bready = '1' then
axi_bready <= '0';
end if;
end if;
end if;
end process;
-- Flag any write response errors
write_resp_error <= axi_bready and M_AXI_BVALID and M_AXI_BRESP(1);
------------------------------
-- Read Address Channel
------------------------------
--The Read Address Channel (AW) provides a similar function to the
--Write Address channel- to provide the tranfer qualifiers for the burst.
--In this example, the read address increments in the same
--manner as the write address channel.
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startr = '1') then
axi_arvalid <= '0';
-- If previously not valid , start next transaction
else
if (axi_arvalid = '0') and (start_single_burst_read = '1') then
axi_arvalid <= '1';
elsif (M_AXI_ARREADY = '1') and (axi_arvalid = '1') then
axi_arvalid <= '0';
end if;
end if;
end if;
end process;
-- Next address after ARREADY indicates previous address acceptance
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startr = '1') then
axi_araddr <= mymaster_addr_inr;
else
if (M_AXI_ARREADY = '1') and (axi_arvalid = '1') then
axi_araddr <= std_logic_vector(unsigned(axi_araddr) + unsigned(burst_size_bytes));
end if;
end if;
end if;
end process;
----------------------------------
-- Read Data (and Response) Channel
----------------------------------
-- Forward movement occurs when the channel is valid and ready
rnext <= M_AXI_RVALID and axi_rready;
-- Burst length counter. Uses extra counter register bit to indicate
-- terminal count to reduce decode logic
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (start_single_burst_read = '1') or (mymaster_startr = '1') then
read_index <= (others => '0');
else
if (rnext = '1') and (read_index <= C_M_AXI_BURST_LEN-1) then
read_index <= read_index + 1;
end if;
end if;
end if;
end process;
-- The Read Data channel returns the results of the read request
-- Note: in this component the data consumer (FIFO) is already known to be able to take all the data at full speed,
-- so no need to throttle the RREADY signal
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startr = '1') then
axi_rready <= '0';
-- accept/acknowledge rdata/rresp with axi_rready by the master
-- when M_AXI_RVALID is asserted by slave
else
if M_AXI_RVALID = '1' then
if (M_AXI_RLAST = '1') and (axi_rready = '1') then
axi_rready <= '0';
else
axi_rready <= '1';
end if;
end if;
end if;
end if;
end process;
-- Flag any read response errors
read_resp_error <= axi_rready and M_AXI_RVALID and M_AXI_RRESP(1);
------------------------------------
-- Error register, status register
------------------------------------
-- Register and hold read/write interface errors
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' then
mymaster_sensor <= (others => '0');
else
if write_resp_error = '1' then
mymaster_sensor(0) <= '1';
end if;
if mymaster_startw = '1' then
mymaster_sensor(15 downto 0) <= (others => '0');
end if;
if read_resp_error = '1' then
mymaster_sensor(16) <= '1';
end if;
if mymaster_startr = '1' then
mymaster_sensor(31 downto 16) <= (others => '0');
end if;
end if;
end if;
end process;
----------------------------------
-- Example design throttling
----------------------------------
-- For maximum port throughput, this user example code will try to allow
-- each channel to run as independently and as quickly as possible.
-- However, there are times when the flow of data needs to be throtted by
-- the user application. This example application requires that data is
-- not read before it is written and that the write channels do not
-- advance beyond an arbitrary threshold (say to prevent an
-- overrun of the current read address by the write address).
-- From AXI4 Specification, 13.13.1: "If a master requires ordering between
-- read and write transactions, it must ensure that a response is received
-- for the previous transaction before issuing the next transaction."
-- This example accomplishes this user application throttling through:
-- -Reads wait for writes to fully complete
-- -Address writes wait when not read + issued transaction counts pass
-- a parameterized threshold
-- -Writes wait when a not read + active data burst count pass
-- a parameterized threshold
-- write_burst_counter counter keeps track with the number of burst transactions initiated
-- against the number of burst transactions the master needs to initiate
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startw = '1') then
write_burst_counter <= unsigned(mymaster_burstnb_inw);
write_burst_end <= '0';
if unsigned(mymaster_burstnb_inw) = 1 then
write_burst_end <= '1';
end if;
else
if (M_AXI_AWREADY = '1') and (axi_awvalid = '1') then
write_burst_end <= '0';
if write_burst_counter = 1 then
write_burst_end <= '1';
end if;
if write_burst_end = '0' then
write_burst_counter <= write_burst_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- read_burst_counter counter keeps track with the number of burst transaction initiated
-- against the number of burst transactions the master needs to initiate
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startr = '1') then
read_burst_counter <= unsigned(mymaster_burstnb_inr);
read_burst_end <= '0';
if unsigned(mymaster_burstnb_inr) = 1 then
read_burst_end <= '1';
end if;
else
if (M_AXI_ARREADY = '1') and (axi_arvalid = '1') then
read_burst_end <= '0';
if read_burst_counter = 1 then
read_burst_end <= '1';
end if;
if read_burst_end = '0' then
read_burst_counter <= read_burst_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- burst_write_active signal is asserted when there is a burst write transaction
-- is initiated by the assertion of start_single_burst_write. burst_write_active
-- signal remains asserted until the burst write is accepted by the slave
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startw = '1') then
burst_write_active <= '0';
--The burst_write_active is asserted when a write burst transaction is initiated
else
if start_single_burst_write = '1' then
burst_write_active <= '1';
elsif (M_AXI_BVALID = '1') and (axi_bready = '1') then
burst_write_active <= '0';
end if;
end if;
end if;
end process;
-- Check for last write completion.
-- This logic is to qualify the last write count with the final write response.
-- This demonstrates how to confirm that a write has been committed.
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startw = '1') then
writes_done <= '0';
--The reads_done should be associated with a rready response
--elsif (M_AXI_RVALID && axi_rready && (read_burst_counter == {(C_NO_BURSTS_REQ-1){1}}) && axi_rlast)
else
if (M_AXI_BVALID = '1') and (axi_bready = '1') and (write_burst_end = '1') then
writes_done <= '1';
end if;
end if;
end if;
end process;
-- burst_read_active signal is asserted when there is a burst write transaction
-- is initiated by the assertion of start_single_burst_write. start_single_burst_read
-- signal remains asserted until the burst read is accepted by the master
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startr = '1') then
burst_read_active <= '0';
-- The burst_write_active is asserted when a write burst transaction is initiated
else
if start_single_burst_read = '1' then
burst_read_active <= '1';
elsif (M_AXI_RVALID = '1') and (axi_rready = '1') and (M_AXI_RLAST = '1') then
burst_read_active <= '0';
end if;
end if;
end if;
end process;
-- Check for last read completion.
-- This logic is to qualify the last read count with the final read response.
-- This demonstrates how to confirm that a read has been committed.
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if (M_AXI_ARESETN = '0') or (mymaster_startr = '1') then
reads_done <= '0';
--The reads_done should be associated with a rready response
--elsif (M_AXI_RVALID && axi_rready && (read_burst_counter == {(C_NO_BURSTS_REQ-1){1}}) && axi_rlast)
else
if (M_AXI_RVALID = '1') and (axi_rready = '1') and (read_index = C_M_AXI_BURST_LEN-1) and (read_burst_end = '1') then
reads_done <= '1';
end if;
end if;
end if;
end process;
----------------------------------
-- Main functionality
----------------------------------
-- State machine for Write operations
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' then
-- reset condition
-- All the signals are set default values under reset condition
write_busy <= '0';
start_single_burst_write <= '0';
else
-- State transition
case write_busy is
when '0' =>
-- Detect when to launch bursts
if mymaster_startw = '1' and (unsigned(mymaster_burstnb_inw) > 0) then
write_busy <= '1';
else
write_busy <= '0';
end if;
when '1' =>
-- This state is responsible to issue start_single_write pulse to initiate a write transaction.
-- Write transactions will be issued until burst_write_active signal is asserted.
if writes_done = '1' then
write_busy <= '0';
else
write_busy <= '1';
-- Launch write bursts only when the FIFO is full enough
if
(axi_awvalid = '0') and (start_single_burst_write = '0') and
(burst_write_active = '0') and (unsigned(mymaster_fifow_cnt) >= C_M_AXI_BURST_LEN)
then
start_single_burst_write <= '1';
else
-- Immediately clear to generate a pulse
start_single_burst_write <= '0';
end if;
end if;
when others =>
write_busy <= '0';
end case;
end if; -- Not reset
end if; -- Clock
end process;
-- State machine for Read operations
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' then
-- reset condition
-- All the signals are set default values under reset condition
read_busy <= '0';
start_single_burst_read <= '0';
else
-- state transition
case read_busy is
when '0' =>
-- Detect when to launch bursts
if (mymaster_startr = '1') and (unsigned(mymaster_burstnb_inr) > 0) then
read_busy <= '1';
else
read_busy <= '0';
end if;
when '1' =>
-- This state is responsible to issue start_single_read pulse to initiate a read transaction.
-- Read transactions will be issued until burst_read_active signal is asserted.
if reads_done = '1' then
read_busy <= '0';
else
read_busy <= '1';
-- Launch read bursts only when the FIFO is empty enough
if
(axi_arvalid = '0') and (burst_read_active = '0') and
(start_single_burst_read = '0') and (unsigned(mymaster_fifor_cnt) >= C_M_AXI_BURST_LEN)
then
start_single_burst_read <= '1';
else
-- Immediately clear to generate a pulse
start_single_burst_read <= '0';
end if;
end if;
when others =>
read_busy <= '0';
end case;
end if; -- Not reset
end if; -- Clock
end process;
mymaster_busyw <= write_busy;
mymaster_busyr <= read_busy;
mymaster_fifor_data <= M_AXI_RDATA;
axi_wdata <= mymaster_fifow_data;
mymaster_fifor_en <= '1' when (M_AXI_ARESETN = '1') and (mymaster_startr = '0') and (rnext = '1') else '0';
mymaster_fifow_en <= '1' when (M_AXI_ARESETN = '1') and (mymaster_startw = '0') and (wnext = '1') else '0';
end implementation;
|
mit
|
546421e8c83806748d410b33492460ef
| 0.662308 | 3.269312 | false | false | false | false |
meninge/dauphin
|
test_bench/test_neuron.vhd
| 1 | 5,797 |
----------------------------------------------------------------
-- uut:
-- neuron.vhd
-- description:
-- simple test_bench to verify neuron behavior in simple cases
-- expected result:
-- neuron should behave as we describe in the neuron schematic
----------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;
use ieee.numeric_std.all;
-- entity declaration for your testbench.Dont declare any ports here
ENTITY test_neuron IS
END test_neuron;
ARCHITECTURE behavior OF test_neuron IS
-- add component under test
component neuron
generic (
-- Parameters for the neurons
WDATA : natural := 32;
WWEIGHT : natural := 16;
WACCU : natural := 32;
-- Parameters for the frame size
FSIZE : natural := 784;
WADDR : natural := 10
);
port (
clk : in std_logic;
-- Control signals
ctrl_we_mode : in std_logic;
ctrl_we_shift : in std_logic;
ctrl_we_valid : in std_logic;
ctrl_accu_clear : in std_logic;
ctrl_accu_add : in std_logic;
ctrl_shift_en : in std_logic;
ctrl_shift_copy : in std_logic;
-- Address used for Read and Write
addr : in std_logic_vector(WADDR-1 downto 0);
-- Ports for Write Enable
we_prev : in std_logic;
we_next : out std_logic;
write_data : in std_logic_vector(WDATA-1 downto 0);
-- Data input, 2 bits
data_in : in std_logic_vector(WDATA-1 downto 0);
-- Scan chain to extract values
sh_data_in : in std_logic_vector(WACCU-1 downto 0);
sh_data_out : out std_logic_vector(WACCU-1 downto 0);
-- Sensors, for synchronization with the controller
sensor_shift : out std_logic;
sensor_copy : out std_logic;
sensor_we_mode : out std_logic;
sensor_we_shift : out std_logic;
sensor_we_valid : out std_logic
);
end component;
signal clk : std_logic := '0';
-- Control signals
signal ctrl_we_mode : std_logic := '0';
signal ctrl_we_shift : std_logic := '0';
signal ctrl_we_valid : std_logic := '0';
signal ctrl_accu_clear : std_logic := '0';
signal ctrl_accu_add : std_logic := '0';
signal ctrl_shift_en : std_logic := '0';
signal ctrl_shift_copy : std_logic := '0';
-- Address used for Read and Write
signal addr : std_logic_vector(9 downto 0);
-- Ports for Write Enable
signal we_prev : std_logic := '0';
signal we_next : std_logic := '0';
signal write_data : std_logic_vector(31 downto 0);
-- Data input, 2 bits
signal data_in : std_logic_vector(31 downto 0);
-- Scan chain to extract values
signal sh_data_in : std_logic_vector(31 downto 0);
signal sh_data_out : std_logic_vector(31 downto 0);
-- Sensors, for synchronization with the controller
signal sensor_shift : std_logic := '0';
signal sensor_copy : std_logic := '0';
signal sensor_we_mode : std_logic := '0';
signal sensor_we_shift : std_logic := '0';
signal sensor_we_valid : std_logic := '0';
-- clock period definition
constant clk_period : time := 1 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut: neuron
port map (
clk => clk ,
-- Control signals
ctrl_we_mode => ctrl_we_mode ,
ctrl_we_shift => ctrl_we_shift ,
ctrl_we_valid => ctrl_we_valid ,
ctrl_accu_clear => ctrl_accu_clear,
ctrl_accu_add => ctrl_accu_add ,
ctrl_shift_en => ctrl_shift_en ,
ctrl_shift_copy => ctrl_shift_copy,
-- Address used for Read and Write
addr => addr ,
-- Ports for Write Enable
we_prev => we_prev ,
we_next => we_next ,
write_data => write_data,
data_in => data_in,
sh_data_in => sh_data_in,
sh_data_out => sh_data_out,
-- Sensors, for synchronization with the controller
sensor_shift => sensor_shift ,
sensor_copy => sensor_copy ,
sensor_we_mode => sensor_we_mode ,
sensor_we_shift => sensor_we_shift,
sensor_we_valid => sensor_we_valid
);
-- Clock process definitions( clock with 50% duty cycle is generated here.
clk_process : process
begin
clk <= '1';
wait for clk_period/2; --for 0.5 ns signal is '1'.
clk <= '0';
wait for clk_period/2; --for next 0.5 ns signal is '0'.
end process;
-- Stimulus process
stim_proc: process
begin
-------------------------------
-- TEST CHARGEMENT DES POIDS --
-------------------------------
wait for clk_period;
ctrl_we_mode <= '1';
sh_data_in <= X"00000000";
wait for clk_period;
we_prev <= '1';
ctrl_we_shift <= '1';
wait for clk_period;
we_prev <= '0';
ctrl_we_shift <= '0';
ctrl_we_valid <= '1';
for I in 0 to 783 loop
addr <= std_logic_vector(to_unsigned(I, addr'length));
write_data <= std_logic_vector(to_unsigned(I mod 2, write_data'length));
wait for clk_period;
end loop;
ctrl_we_valid <= '0';
ctrl_we_shift <= '1';
we_prev <= '0';
wait for clk_period;
ctrl_we_shift <= '0';
wait for clk_period;
wait for clk_period;
wait for clk_period;
-----------------------
-- TEST ACCUMULATION --
-----------------------
ctrl_we_mode <= '0';
wait for clk_period;
ctrl_accu_clear <= '1';
wait for clk_period;
ctrl_accu_clear <= '0';
ctrl_accu_add <= '1';
data_in <= X"00000001";
addr <= std_logic_vector(to_unsigned(0, addr'length));
for I in 0 to 783 loop
addr <= std_logic_vector(to_unsigned(I, addr'length));
wait for clk_period;
end loop;
ctrl_accu_add <= '0';
ctrl_shift_copy <= '1';
wait for clk_period;
ctrl_shift_copy <= '0';
ctrl_shift_en <= '1';
wait for clk_period;
ctrl_shift_en <= '0';
wait for clk_period;
wait;
end process;
END;
|
mit
|
f20d651bc98fac4c09411acbfd8afc16
| 0.59479 | 3.072072 | false | false | false | false |
migraichen/picocpu
|
picocpu.vhd
| 1 | 32,376 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity picocpu is
port (
clk_in : in std_logic;
rst_n_in : in std_logic;
-- Signale zumdo Programmspeicher
inst_addr_out : out std_logic_vector( 9 downto 0) := ( others => '0' );
inst_data_in : in std_logic_vector(17 downto 0);
-- Output / Input Port
port_id_out : out std_logic_vector( 7 downto 0) := ( others => '0' );
port_wr_pulse_out : out std_logic := '0';
port_data_out : out std_logic_vector( 7 downto 0) := ( others => '0' );
port_rd_pulse_out : out std_logic := '0';
port_data_in : in std_logic_vector( 7 downto 0);
-- Interrupt Port
int_in : in std_logic;
int_ack_out : out std_logic := '0'
);
end picocpu;
architecture behavioral of picocpu is
------------------------------------
-- intern verwendete Definitionen --
------------------------------------
constant reg_num_c : natural := 16;
constant reg_width_c : natural := 8;
constant inst_depth_c : natural := 10;
constant zero_c : std_logic_vector( reg_width_c-1 downto 0) := ( others => '0' );
constant int_vec_c : std_logic_vector(inst_depth_c-1 downto 0) := ( others => '1' );
constant opcode_msb_c : natural := inst_data_in'high;
constant opcode_width_c : natural := 8;
-- Instructions Codes
constant inst_msb_c : natural := inst_data_in'high;
constant inst_width_c : natural := 5;
-- write to register from (constant, register, read port or scratchpad - "000_00" bis "100_11" )
constant load_c : std_logic_vector(inst_width_c-1 downto 0) := b"000_00"; -- read from constant or register
--constant : std_logic_vector(inst_width_c downto 0) := b"000_01"; -- read from spare input (e.g ext ram or divider/multiplier/other calculator)
constant input_c : std_logic_vector(inst_width_c-1 downto 0) := b"000_10"; -- read from port value, write port id,
constant fetch_c : std_logic_vector(inst_width_c-1 downto 0) := b"000_11"; -- read from scratchpad
-- ALU
-- logical and arithmetik operations
--constant inv_c : std_logic_vector(inst_width_c-1 downto 0) := b"001_00"; -- ALU logical not
constant and_c : std_logic_vector(inst_width_c-1 downto 0) := b"001_01"; -- ALU logical and
constant or_c : std_logic_vector(inst_width_c-1 downto 0) := b"001_10"; -- ALU locigal or
constant xor_c : std_logic_vector(inst_width_c-1 downto 0) := b"001_11"; -- ALU logical xor
--constant : std_logic_vector(inst_width_c-1 downto 0) := b"010_00"; -- ALU logical ??? ( don't write to register )
constant test_c : std_logic_vector(inst_width_c-1 downto 0) := b"010_01"; -- ALU logical and ( don't write to register )
constant compare_c : std_logic_vector(inst_width_c-1 downto 0) := b"010_10"; -- ALU logical sub ( don't write to register )
--constant : std_logic_vector(inst_width_c-1 downto 0) := b"010_11"; -- ALU logical ??? ( don't write to register )
constant add_c : std_logic_vector(inst_width_c-1 downto 0) := b"011_00"; -- ALU arithmetik add
constant addcy_c : std_logic_vector(inst_width_c-1 downto 0) := b"011_01"; -- ALU arithmetik add with carry
constant sub_c : std_logic_vector(inst_width_c-1 downto 0) := b"011_10"; -- ALU arithmetik sub
constant subcy_c : std_logic_vector(inst_width_c-1 downto 0) := b"011_11"; -- ALU arithmetik sub with carry
-- shift operations
constant sr_c : std_logic_vector(inst_width_c-1 downto 0) := b"100_00"; -- ALU shift operation
-- constant : std_logic_vector(inst_width_c-1 downto 0) := b"100_01"; -- ALU spare (e.g. divider/multiplier/other calculator)
-- constant : std_logic_vector(inst_width_c-1 downto 0) := b"100_10"; -- ALU spare (e.g. divider/multiplier/other calculator)
-- constant : std_logic_vector(inst_width_c-1 downto 0) := b"100_11"; -- ALU spare (e.g. divider/multiplier/other calculator)
-- address operation (no write to register - "1010_0" bis "1111_1" )
-- constant : std_logic_vector(inst_width_c-1 downto 0) := b"1010_0"; -- spare
constant return_c : std_logic_vector(inst_width_c-1 downto 0) := b"1010_1"; -- jump to stack address
-- write operations
constant output_c : std_logic_vector(inst_width_c-1 downto 0) := b"1011_0"; -- write port id and port value
constant store_c : std_logic_vector(inst_width_c-1 downto 0) := b"1011_1"; -- write in scratchpad
-- (PC operation) Jump to address
constant call_c : std_logic_vector(inst_width_c-1 downto 0) := b"1100_0"; -- Jump to address, store pc to stack
--constant : std_logic_vector(inst_width_c-1 downto 0) := b"1100_1"; --
constant jump_c : std_logic_vector(inst_width_c-1 downto 0) := b"1101_0"; -- Jump to address
--constant : std_logic_vector(inst_width_c-1 downto 0) := b"1101_1"; --
constant returni_c : std_logic_vector(inst_width_c-1 downto 0) := b"1110_0"; -- Jump from interrupt, reload flags
--constant : std_logic_vector(inst_width_c-1 downto 0) := b"1110_1"; --
-- Setzt oder lösche Flags
constant interrupt_c : std_logic_vector(inst_width_c-1 downto 0) := b"1111_0"; -- enable / disable interrupts
--constant : std_logic_vector(inst_width_c-1 downto 0) := b"1111_1"; -- divide or multiply
-- Es fehlen noch überlegungen zu einer Memory management Unit
-- leider finde ich dazu gerade keine Informationen
constant sr_code_width_c : natural := 3;
-- ACHTUNG :: sub Codes für Shift right und shift Left sind nicht gleich !!! (x und rotate sind vertauscht)
-- Vermutlich wegen des Rotierens in der ALU
constant shift_a : std_logic_vector(sr_code_width_c-1 downto 0) := "000";
constant shift_x : std_logic_vector(sr_code_width_c-1 downto 0) := "010";
constant rotate : std_logic_vector(sr_code_width_c-1 downto 0) := "100";
constant shift_0 : std_logic_vector(sr_code_width_c-1 downto 0) := "110";
constant shift_1 : std_logic_vector(sr_code_width_c-1 downto 0) := "111";
-- Positionen wo in dem Befehl welche Informationen zu finden sind
constant condition_pos_c : natural := inst_data_in'high-inst_width_c;
constant addr_lsb_c : natural := 0;
constant addr_width_c : natural := inst_depth_c;
constant sX_msb_c : natural := inst_data_in'high-inst_width_c-1;
constant sX_width_c : natural := 4;
constant sY_msb_c : natural := inst_data_in'high-inst_width_c-sX_width_c-1;
constant sY_width_c : natural := 4;
constant const_lsb_c : natural := 0;
constant const_width_c : natural := reg_width_c;
constant direction_pos_c : natural := 3;
constant sr_code_lsb_c : natural := 0;
constant int_enable_pos_c : natural := 0;
-- Berechne die Bereiche der obrigen Informationen
subtype opcode_r is integer range opcode_msb_c downto opcode_msb_c-opcode_width_c+1;
subtype inst_r is integer range inst_msb_c downto inst_msb_c-inst_width_c+1;
subtype addr_r is integer range addr_lsb_c+addr_width_c-1 downto addr_lsb_c;
subtype sX_r is integer range sX_msb_c downto sX_msb_c-sX_width_c+1;
subtype sY_r is integer range sY_msb_c downto sY_msb_c-sX_width_c+1;
subtype const_r is integer range const_lsb_c+const_width_c-1 downto const_lsb_c;
subtype sr_code_r is integer range sr_code_lsb_c+sr_code_width_c-1 downto sr_code_lsb_c;
-- intern verwendete Bezeichnungen
alias opcode : std_logic_vector( opcode_width_c-1 downto 0) is inst_data_in(opcode_r); -- 17 downto 10
alias inst : std_logic_vector( inst_width_c-1 downto 0) is inst_data_in(inst_r); -- 17 downto 13
alias condition : std_logic is inst_data_in(condition_pos_c); -- 12
alias addr : std_logic_vector( addr_width_c-1 downto 0) is inst_data_in(addr_r); -- 9 downto 0
alias sX : std_logic_vector( sX_width_c-1 downto 0) is inst_data_in(sX_r); -- 11 downto 8
alias sY : std_logic_vector( sY_width_c-1 downto 0) is inst_data_in(sY_r); -- 7 downto 4
alias const : std_logic_vector( reg_width_c-1 downto 0) is inst_data_in(const_r); -- 7 downto 0
alias direction : std_logic is inst_data_in(direction_pos_c); -- 3
alias sr_code : std_logic_vector(sr_code_width_c-1 downto 0) is inst_data_in(sr_code_r); -- 2 downto 0
alias int_enable : std_logic is inst_data_in(int_enable_pos_c); -- 0
-------------------------------
-- intern verwendete Signale --
-------------------------------
type t_state is ( get, set ); -- PicoCPU State Maschine
signal state : t_state := get;
signal rst_n : std_logic := '1';
signal int : std_logic := '0';
signal pc : std_logic_vector(inst_depth_c-1 downto 0) := ( others => '0' );
signal next_addr : std_logic_vector(inst_depth_c-1 downto 0) := ( others => '0' );
signal last_addr : std_logic_vector(inst_depth_c-1 downto 0) := ( others => '0' );
signal cond_valid : std_logic := '0';
signal zero : std_logic := '0';
signal not_zero : std_logic := '0';
signal carry : std_logic := '0';
signal not_carry : std_logic := '0';
signal alu_a : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
signal alu_b : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
signal alu_c : std_logic := '0';
signal res : std_logic_vector(reg_width_c downto 0) := ( others => '0' );
signal res_reg : std_logic_vector(reg_width_c downto 0) := ( others => '0' );
signal int_en_flag : std_logic := '0';
signal zero_flag : std_logic := '0';
alias carry_flag : std_logic is res_reg(res_reg'high);
signal preserved_zero : std_logic := '0';
signal preserved_carry : std_logic := '0';
attribute ram_style : string;
attribute keep : string;
type regs_t is array(0 to reg_num_c-1) of std_logic_vector(reg_width_c-1 downto 0);
signal regs_x : regs_t := ( others => ( others => '0' ));
signal regs_y : regs_t := ( others => ( others => '0' ));
attribute keep of regs_x : signal is "true";
attribute keep of regs_y : signal is "true";
attribute ram_style of regs_x : signal is "distributed";
attribute ram_style of regs_y : signal is "distributed";
signal wr_reg : std_logic := '0';
signal reg_in_addr : std_logic_vector(3 downto 0) := ( others => '0' );
signal reg_in : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
signal reg_x_out_addr : std_logic_vector(3 downto 0) := ( others => '0' );
signal reg_x_out : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
signal reg_y_out_addr : std_logic_vector(3 downto 0) := ( others => '0' );
signal reg_y_out : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
constant stack_width_c : natural := 5;
type stack_t is array (0 to (2**stack_width_c)-1) of std_logic_vector(addr'range);
signal stack : stack_t := ( others => ( others => '0'));
attribute keep of stack : signal is "true";
attribute ram_style of stack : signal is "distributed";
signal stack_ptr : std_logic_vector(stack_width_c-1 downto 0) := ( others => '0' );
signal stack_wr : std_logic := '0';
signal stack_rd : std_logic := '0';
signal stack_data_in : std_logic_vector(inst_depth_c-1 downto 0) := ( others => '0' );
signal stack_top : std_logic_vector(inst_depth_c-1 downto 0) := ( others => '0' );
signal stack_top_p : std_logic_vector(inst_depth_c-1 downto 0) := ( others => '0' );
signal port_out_en : std_logic := '0';
signal port_in_en : std_logic := '0';
signal port_id_en : std_logic := '0';
signal port_id : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
signal port_data_i : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
signal port_data_o : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
constant scratchpad_width_c : natural := 2;
type scratchpad_t is array (0 to (2**scratchpad_width_c)-1) of std_logic_vector(reg_width_c-1 downto 0);
signal scratchpad : scratchpad_t := ( others => ( others => '0'));
attribute keep of scratchpad : signal is "true";
attribute ram_style of scratchpad : signal is "distributed";
signal wr_scratchpad : std_logic := '0';
signal scratchpad_addr : std_logic_vector(scratchpad_width_c-1 downto 0):= ( others => '0' );
signal scratchpad_in : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
signal scratchpad_out : std_logic_vector(reg_width_c-1 downto 0) := ( others => '0' );
function parity (din : std_logic_vector) return std_logic is
variable temp : std_logic := '0';
begin
for i in din'range loop
temp := temp xor din(i);
end loop;
return temp;
end parity;
begin
-- TODO::
-- Interrupts nochmal überprüfen, Interrups zeitgleich mit call, jump, return ???
-- Dynamischer gestallten: Registerbreite 4, 8, 16, 32, 64, 128
-- Anzahl der Register,
-- Größe des Scratchpad
-- Überlegungen zu prozessor skalierung
--
-- Slice Logic Utilization:
-- Number of Slice Registers: 89 out of 54576 0%
-- Number of Slice LUTs: 337 out of 27288 1%
-- Number used as Logic: 301 out of 27288 1%
-- Number used as Memory: 36 out of 6408 0%
-- Number used as RAM: 36
------------------------------------------------------------------
-- General Signals --
------------------------------------------------------------------
-- Reset und Interrupt Einsynchronisieren
socket_sync_ext_signal : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
rst_n <= rst_n_in;
int <= int_in;
end if;
end process;
-- PicoCPU State Maschine (da jeder Befehl genau zwei Takte benoetigen darf)
socket_picocpu_state_maschine : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
state <= get;
else
case state is
when get => state <= set;
when set => state <= get;
end case;
end if;
end if;
end process;
------------------------------------------------------------------
-- Operational Control & Instruction Decode --
------------------------------------------------------------------
zero <= '1' when opcode(1 downto 0) = "00" else '0';
not_zero <= '1' when opcode(1 downto 0) = "01" else '0';
carry <= '1' when opcode(1 downto 0) = "10" else '0';
not_carry <= '1' when opcode(1 downto 0) = "11" else '0';
------------------------------------------------------------------
-- Instruction Decode --
------------------------------------------------------------------
cond_valid <= '1' when condition = '0' else
'1' when condition = '1' and zero = '1' and zero_flag = '1' else
'1' when condition = '1' and not_zero = '1' and zero_flag = '0' else
'1' when condition = '1' and carry = '1' and carry_flag = '1' else
'1' when condition = '1' and not_carry = '1' and carry_flag = '0' else
'0';
stack_wr <= '1' when state = get and pc = int_vec_c else
'1' when state = get and inst = call_c and cond_valid = '1' else
'0';
stack_rd <= '1' when state = get and inst = return_c and cond_valid = '1' else
'1' when state = get and inst = returni_c else
'0';
wr_reg <= '1' when state = set and inst = load_c else
'1' when state = set and inst = input_c else
'1' when state = set and inst = fetch_c else
'1' when state = set and inst = and_c else
'1' when state = set and inst = or_c else
'1' when state = set and inst = xor_c else
'1' when state = set and inst = add_c else
'1' when state = set and inst = addcy_c else
'1' when state = set and inst = sub_c else
'1' when state = set and inst = subcy_c else
'1' when state = set and inst = sr_c else
'0';
port_out_en <= '1' when state = get and inst = output_c else '0';
port_in_en <= '1' when state = get and inst = input_c else '0';
port_id_en <= port_out_en or port_in_en;
wr_scratchpad <= '1' when state = set and inst = store_c else '0';
------------------------------------------------------------------
-- Program Counter --
------------------------------------------------------------------
next_addr <= addr when inst = jump_c and cond_valid = '1' else
addr when inst = call_c and cond_valid = '1' else
stack_top_p when inst = return_c and cond_valid = '1' else
stack_top when inst = returni_c else
std_logic_vector(unsigned(pc) + 1);
socket_test : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if state = get then
last_addr <= next_addr;
end if;
end if;
end process;
socket_program_counter : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
pc <= ( others => '0' );
else
if state = get then
if int = '1' and int_en_flag = '1' then
pc <= int_vec_c;
else
pc <= next_addr;
end if;
end if;
end if;
end if;
end process;
inst_addr_out <= pc;
------------------------------------------------------------------
-- Program Counter Stack --
------------------------------------------------------------------
stack_top <= std_logic_vector(unsigned(stack(to_integer(unsigned(stack_ptr)-1))));
stack_top_p <= std_logic_vector(unsigned(stack_top)+1);
stack_data_in <= last_addr when pc = int_vec_c else pc;
socket_stack_ptr : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
stack_ptr <= ( others => '0' );
else
if stack_wr = '1' then
stack(to_integer(unsigned(stack_ptr))) <= stack_data_in;
stack_ptr <= std_logic_vector(unsigned(stack_ptr) + 1);
elsif stack_rd = '1' then
stack_ptr <= std_logic_vector(unsigned(stack_ptr) - 1);
end if;
end if;
end if;
end process;
------------------------------------------------------------------
-- Arithmetic Logic Union --
------------------------------------------------------------------
alu_a <= reg_x_out;
alu_b <= const when condition = '0' else
reg_y_out;
alu_c <= parity(res_reg) when inst = test_c else
'0' when inst = sr_c and sr_code = shift_0 else
'1' when inst = sr_c and sr_code = shift_1 else
reg_x_out(reg_x_out'left) when inst = sr_c and sr_code = shift_x else
carry_flag when inst = sr_c and sr_code = shift_a else
reg_x_out(reg_x_out'right) when inst = sr_c and sr_code = rotate else
'0';
res <= alu_c & alu_a and alu_c & alu_b when inst = and_c else
alu_c & alu_a or alu_c & alu_b when inst = or_c else
alu_c & alu_a xor alu_c & alu_b when inst = xor_c else
alu_c & alu_a and alu_c & alu_b when inst = test_c else
-- Arithmetic Group
std_logic_vector(unsigned(alu_c & alu_a) + unsigned(alu_c & alu_b)) when inst = add_c else
std_logic_vector(unsigned(alu_c & alu_a) + unsigned(alu_c & alu_b) + unsigned(zero_c & carry_flag)) when inst = addcy_c else
std_logic_vector(unsigned(alu_c & alu_a) - unsigned(alu_c & alu_b)) when inst = sub_c else
std_logic_vector(unsigned(alu_c & alu_a) - unsigned(alu_c & alu_b) - unsigned(zero_c & carry_flag)) when inst = subcy_c else
std_logic_vector(unsigned(alu_c & alu_a) - unsigned(alu_c & alu_b)) when inst = compare_c else
-- Shift and Rotate Groupe
alu_a(alu_a'right) & alu_c & alu_a(reg_width_c-1 downto 1) when inst = sr_c and direction = '1' else
alu_a(alu_a'left) & alu_a(reg_width_c-2 downto 0) & alu_c when inst = sr_c and direction = '0' else
-- Return from Interrupt
preserved_carry & zero_c when inst = returni_c else
( others => '0' );
socket_alu : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
res_reg <= ( others => '0' );
else
if state = get then
res_reg <= res;
end if;
end if;
end if;
end process;
socket_flags : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
zero_flag <= '0';
else
if inst = returni_c and state = set then
zero_flag <= preserved_zero;
elsif res_reg(reg_width_c-1 downto 0) = zero_c then
zero_flag <= '1';
else
zero_flag <= '0';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------------------------
-- 16 Registers -- 2x SLICEM / MLAB used as Dual-Port RAM on Spartan 6 / ARRIA II --
-------------------------------------------------------------------------------------------------
-- Hier werden die Register doppelt abgespeichert, das benötigt 9 Slices mehr --
-- hat aber den Vorteil, das mit sX und sY gleichzeitig zwei Register ausgelesen werden können --
-------------------------------------------------------------------------------------------------
reg_in_addr <= sX;
reg_in <= const when inst = load_c and condition = '0' else
reg_y_out when inst = load_c and condition = '1' else
scratchpad_out when inst = fetch_c else
port_data_i when inst = input_c else
res_reg(reg_in'range);
reg_x_out_addr <= sX;
reg_y_out_addr <= sY;
reg_x_out <= regs_x(to_integer(unsigned(reg_x_out_addr)));
reg_y_out <= regs_y(to_integer(unsigned(reg_y_out_addr)));
socket_regs_x : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if wr_reg = '1' then
regs_x(to_integer(unsigned(reg_in_addr))) <= reg_in;
end if;
end if;
end process;
socket_regs_y : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if wr_reg = '1' then
regs_y(to_integer(unsigned(reg_in_addr))) <= reg_in;
end if;
end if;
end process;
------------------------------------------------------------------
-- Port Address Control --
------------------------------------------------------------------
port_id <= const when inst = output_c and condition = '0' else
reg_y_out when inst = output_c and condition = '1' else
const when inst = input_c and condition = '0' else
reg_y_out when inst = input_c and condition = '1' else
( others => '0' );
port_data_o <= reg_x_out;
socket_port_id_ctrl : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
port_id_out <= ( others => '0' );
else
if port_id_en = '1' then
port_id_out <= port_id;
else
port_id_out <= ( others => '0' );
end if;
end if;
end if;
end process;
socket_port_output_ctrl : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
port_wr_pulse_out <= '0';
port_data_out <= ( others => '0' );
else
if port_out_en = '1' then
port_wr_pulse_out <= '1';
port_data_out <= port_data_o;
else
port_wr_pulse_out <= '0';
port_data_out <= ( others => '0' );
end if;
end if;
end if;
end process;
socket_port_input_ctrl : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
port_rd_pulse_out <= '0';
else
if port_in_en = '1' then
port_rd_pulse_out <= '1';
else
port_rd_pulse_out <= '0';
end if;
end if;
end if;
end process;
port_data_i <= port_data_in;
------------------------------------------------------------------
-- Scratch Pad Memory -- SLICEM / MLAB used as Singel-Port RAM --
------------------------------------------------------------------
scratchpad_addr <= const(scratchpad_addr'range) when condition = '0' else reg_x_out(scratchpad_addr'range);
scratchpad_in <= reg_x_out;
scratchpad_out <= scratchpad(to_integer(unsigned(scratchpad_addr)));
socket_scratchpad : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if wr_scratchpad = '1' then
scratchpad(to_integer(unsigned(scratchpad_addr))) <= scratchpad_in;
end if;
end if;
end process;
------------------------------------------------------------------
-- Interrupt Controller --
------------------------------------------------------------------
socket_interrupt_shadow_flags : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
preserved_zero <= '0';
preserved_carry <= '0';
else
if int = '1' and pc = int_vec_c and state = set then
preserved_zero <= zero_flag;
preserved_carry <= carry_flag;
end if;
end if;
end if;
end process;
socket_interrupt_enable_flag : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if rst_n = '0' then
int_en_flag <= '0';
else
if pc = int_vec_c then
int_en_flag <= '0';
elsif inst = returni_c then
int_en_flag <= int_enable;
elsif inst = interrupt_c then
int_en_flag <= int_enable;
end if;
end if;
end if;
end process;
socket_int_ack : process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if state = set and pc = int_vec_c then
int_ack_out <= '1';
else
int_ack_out <= '0';
end if;
end if;
end process;
end behavioral;
|
gpl-2.0
|
9079fd17ce19127ed040dfd80aa888c9
| 0.444712 | 3.969593 | false | false | false | false |
ciroceissler/sva_example
|
dut/FSM2.vhd
| 1 | 2,206 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:06:07 05/29/2014
-- Design Name:
-- Module Name: FSM2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FSM2 is
Port (
reset : in std_logic;
clk : in std_logic;
start: in std_logic;
data_in : in std_logic_vector(3 downto 0);
AVAIL : out std_logic;
DONE : out std_logic;
flag : out std_logic_vector(1 downto 0));
end FSM2;
architecture Behavioral of FSM2 is
type tipoestado is (s0, s1, s2, s3, s4, s5, s6);
signal estado : tipoestado;
begin
process(reset, clk)
variable regd : std_logic_vector(3 downto 0);
variable cont : std_logic_vector(6 downto 0);
begin
if reset = '1' then
estado <= s0;
AVAIL <= '1'; done <= '0'; flag <= "00"; regd := "0000"; cont := "0000000";
elsif (clk'event and clk='1') then
CASE estado IS
WHEN s0 =>
AVAIL <= '1'; done <= '0'; flag <= "00"; regd := "0000"; cont := "0000000"; if start='0'then estado
<= s0; else estado <= s1; end if;
WHEN s1 =>
AVAIL <= '0'; done <= '0'; flag <= "00"; regd := data_in; cont := cont+1;
if (regd = "1011" and cont <= "1100100") then estado <= s2;
elsif cont="1100100" then estado <= s4;
else estado <= s1;
end if;
WHEN s2 => -- achou um valor em <=100
AVAIL <= '0'; done <= '1'; flag <= "01"; estado <= s0;
WHEN s3 =>
AVAIL <= '0'; done <= '1'; flag <= "01"; estado <= s0;
WHEN s4 => -- nao achou valor ate 100 dados
AVAIL <= '0'; done <= '1'; flag <= "00"; estado <= s5;
WHEN s5 =>
AVAIL <= '0'; done <= '1'; flag <= "00"; estado <= s0;
WHEN others =>
AVAIL <= '1'; done <= '0'; flag <= "00"; estado <= s0;
end CASE;
end if;
end process;
end Behavioral;
|
apache-2.0
|
4ae38bf8e765eab8dd0e86fca5317d38
| 0.508613 | 3.307346 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_tb.vhd
| 1 | 6,128 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_tb IS
END ENTITY;
ARCHITECTURE system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4000 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_synth
system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_synth_inst:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 21
)
PORT MAP(
S_ACLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
mit
|
107dfd11377a8100f2ca530764a6c975
| 0.632996 | 4.044884 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_dverif.vhd
| 1 | 5,736 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
mit
|
93ae3efb5674562a7e66cf8bbb0f9e59
| 0.585251 | 4.02244 | false | false | false | false |
SamTheDev/VGA-VHDL-Simulator
|
VGA_Simulator_TB.vhd
| 1 | 1,112 |
------------------------------------------------------------
-- mini-projet VHDL
-- Le testBench du systemE de simulation d'un VGA
-- Elhamer Oussama abdelkhalek
-- après 1 ms le système declanche en mettant Reset a '0'
------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY VGA_Simulator_TB IS
END VGA_Simulator_TB;
ARCHITECTURE behavior OF VGA_Simulator_TB IS
COMPONENT VGA_SIMULATOR
PORT(
Reset : IN std_logic;
H_SYNC : INOUT std_logic;
V_SYNC : INOUT std_logic
);
END COMPONENT;
signal Reset : std_logic := '1' ;
signal H_SYNC : std_logic := '0';
signal V_SYNC : std_logic := '0';
BEGIN
uut: VGA_SIMULATOR PORT MAP (
Reset => Reset,
H_SYNC => H_SYNC,
V_SYNC => V_SYNC
);
-- Processus de simulation
proc_simulation: process (Reset)
begin
Reset <= '0' after 1ms ;
--Reset <= '1' after 16.223ms; -- the time to get one picture
end process;
END;
|
mit
|
fab84f0a21c8c32b0c33a942b3823dc5
| 0.497302 | 3.874564 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/axi_lite_ipif.vhd
| 3 | 13,994 |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_ipif.vhd
-- Version: v1.01.a
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.common_types.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_lite_ipif is
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity work.slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
|
mit
|
0f96c5e2ad9d97e24b9cc39274ab644b
| 0.477062 | 4.157457 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2/example_design/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_exdes.vhd
| 1 | 5,073 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_exdes is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(5-1 DOWNTO 0);
DOUT : OUT std_logic_vector(5-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_exdes;
architecture xilinx of system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_exdes is
signal clk_i : std_logic;
component system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(5-1 DOWNTO 0);
DOUT : OUT std_logic_vector(5-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
mit
|
996f6f9f562ffb1038cb144b1f176a95
| 0.542874 | 4.767857 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_1/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_1_rng.vhd
| 1 | 4,001 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_1_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_1_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_1_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
mit
|
ad42c2a778bc44bffa3f5466327e7f50
| 0.64159 | 4.238347 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_3/example_design/system_axi_dma_0_wrapper_fifo_generator_v9_3_3_exdes.vhd
| 1 | 5,695 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_3_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_dma_0_wrapper_fifo_generator_v9_3_3_exdes is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(38-1 DOWNTO 0);
DOUT : OUT std_logic_vector(38-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_dma_0_wrapper_fifo_generator_v9_3_3_exdes;
architecture xilinx of system_axi_dma_0_wrapper_fifo_generator_v9_3_3_exdes is
signal clk_i : std_logic;
component system_axi_dma_0_wrapper_fifo_generator_v9_3_3 is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(38-1 DOWNTO 0);
DOUT : OUT std_logic_vector(38-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_dma_0_wrapper_fifo_generator_v9_3_3
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
mit
|
0619e93c2b9d9fcce7d54429a3346534
| 0.517296 | 4.745833 | false | false | false | false |
meninge/dauphin
|
neuron.vhd
| 1 | 5,445 |
-- This is one neuron
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity neuron is
generic (
-- Parameters for the neurons
WDATA : natural := 32;
WWEIGHT : natural := 16;
WACCU : natural := 32;
-- Parameters for the frame size
FSIZE : natural := 784;
WADDR : natural := 10
);
port (
clk : in std_logic;
-- Control signals, test
ctrl_we_mode : in std_logic;
ctrl_we_shift : in std_logic;
ctrl_we_valid : in std_logic;
ctrl_accu_clear : in std_logic;
ctrl_accu_add : in std_logic;
ctrl_shift_en : in std_logic;
ctrl_shift_copy : in std_logic;
-- Address used for Read and Write
addr : in std_logic_vector(WADDR-1 downto 0);
-- Ports for Write Enable
we_prev : in std_logic;
we_next : out std_logic;
write_data : in std_logic_vector(WDATA-1 downto 0);
-- Data input, 2 bits
data_in : in std_logic_vector(WDATA-1 downto 0);
-- Scan chain to extract values
sh_data_in : in std_logic_vector(WACCU-1 downto 0);
sh_data_out : out std_logic_vector(WACCU-1 downto 0);
-- Sensors, for synchronization with the controller
sensor_shift : out std_logic;
sensor_copy : out std_logic;
sensor_we_mode : out std_logic;
sensor_we_shift : out std_logic;
sensor_we_valid : out std_logic
);
end neuron;
architecture synth of neuron is
-- Registre contenant l'accumulation du DSP
signal accu : signed(47 downto 0) := (others => '0');
-- Registre contenant la copy de l'accu
signal mirror : std_logic_vector(WACCU-1 downto 0) := (others => '0');
-- Registre memorisant si on se trouve dans un etat de config
signal reg_config : std_logic := '0';
-- output signals
signal out_sensor_shift : std_logic := '0';
signal out_sensor_copy : std_logic := '0';
signal out_sensor_we_mode : std_logic := '0';
signal out_sensor_we_shift : std_logic := '0';
signal weight : std_logic_vector(WWEIGHT-1 downto 0);
signal write_data_in : std_logic_vector(WWEIGHT-1 downto 0);
component ram is
generic (
WDATA : natural := 16;
SIZE : natural := 784;
WADDR : natural := 10
);
port ( clk : in std_logic;
we : in std_logic;
en : in std_logic;
addr : in std_logic_vector(WADDR-1 downto 0);
di : in std_logic_vector(WDATA-1 downto 0);
do : out std_logic_vector(WDATA-1 downto 0));
end component;
signal we_ram : std_logic := '0';
signal en_ram : std_logic := '0';
begin
-------------------------------------------------------------------
-- instanciation of component
-------------------------------------------------------------------
i_ram: ram
generic map (
WDATA => WWEIGHT,
SIZE => FSIZE,
WADDR => WADDR
)
port map (
clk => clk,
we => we_ram,
en => en_ram,
addr => addr,
di => write_data_in,
do => weight
);
---------------------------------------------
----------- Sequential processes ------------
---------------------------------------------
mac : process (clk)
begin
if rising_edge(clk) then
-- Mode accumulation
if (ctrl_we_mode = '0') then
-- we need to clear accu
if (ctrl_accu_clear = '1') then
accu <= (others => '0');
-- data available
elsif (ctrl_accu_add = '1') then
accu <= accu + signed(data_in(24 downto 0))*(resize(signed(weight), 18));
end if;
end if;
end if;
end process mac;
shift: process (clk)
begin
if (rising_edge(clk)) then
-- we have to copy the accu reg into the miroir reg
if ((ctrl_shift_copy = '1')) then
mirror <= std_logic_vector(accu(WACCU-1 downto 0));
elsif (ctrl_shift_en = '1') then
-- we have to shift the miroir prev into the miroir next
mirror <= sh_data_in;
end if;
end if;
end process;
reg_conf : process (clk)
begin
if rising_edge(clk) then
if (ctrl_we_mode = '1') and (ctrl_we_shift = '1') then
-- update the reg_config
reg_config <= we_prev;
end if;
end if;
end process reg_conf;
---------------------------------------------
--------- Combinatorial processes -----------
---------------------------------------------
sensor : process (ctrl_we_mode, ctrl_we_shift, ctrl_shift_copy, ctrl_shift_en)
begin
-- updating the reg_conf
if (ctrl_we_shift = '1') then
-- notify the fsm
out_sensor_we_shift <= '1';
else
out_sensor_we_shift <= '0';
end if;
if (ctrl_we_mode = '1') then
out_sensor_we_mode <= '1';
else
out_sensor_we_mode <= '0';
end if;
-- we have to copy the accu reg into the miroir reg
if (ctrl_shift_copy = '1') then
out_sensor_copy <= '1';
else
out_sensor_copy <= '0';
end if;
-- we have to shift the miroir prev into the miroir next
if (ctrl_shift_en = '1') then
out_sensor_shift <= '1';
else
out_sensor_shift <= '0';
end if;
end process sensor;
---------------------------------------------
----------- Ports assignements --------------
---------------------------------------------
en_ram <= '1';
we_ram <= ctrl_we_mode and reg_config and not(ctrl_we_shift);
we_next <= reg_config;
sh_data_out <= mirror;
-- not used, but need to be set
sensor_we_valid <= '1';
sensor_shift <= out_sensor_shift;
sensor_copy <= out_sensor_copy;
sensor_we_mode <= out_sensor_we_mode;
sensor_we_shift <= out_sensor_we_shift;
-- to get right conversion for the BRAM
write_data_in <= std_logic_vector(resize(signed(write_data), WWEIGHT));
end architecture;
|
mit
|
827e78b53e41ee6ded4ae05498df902e
| 0.568411 | 3.07801 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_PL_to_PS_1.0/hdl/PL_to_PS_v1_0.vhd
| 1 | 4,044 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PL_to_PS_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
AXI_from_PL : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end PL_to_PS_v1_0;
architecture arch_imp of PL_to_PS_v1_0 is
signal axi_00_effect_connection : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); --VL
-- component declaration
component PL_to_PS_v1_0_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component PL_to_PS_v1_0_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
PL_to_PS_v1_0_S00_AXI_inst : PL_to_PS_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => axi_00_effect_connection, --VL. was s01_axi_wdata
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
axi_00_effect_connection <= AXI_from_PL;
-- User logic ends
end arch_imp;
|
mit
|
3d1f3a96f425c496f12775f818a07bc5
| 0.652324 | 2.411449 | false | false | false | false |
ciroceissler/sva_example
|
dut/FSM1.vhd
| 1 | 2,209 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:04:25 05/29/2014
-- Design Name:
-- Module Name: FSM1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FSM1 is
Port (
reset : in std_logic;
clk : in std_logic;
start: in std_logic;
data_in : in std_logic_vector(3 downto 0);
AVAIL : out std_logic;
DONE : out std_logic;
flag : out std_logic_vector(1 downto 0));
end FSM1;
architecture Behavioral of FSM1 is
type tipoestado is (s0, s1, s2, s3, s4, s5, s6);
signal estado : tipoestado;
begin
process(reset, clk)
variable regd : std_logic_vector(3 downto 0);
variable cont : std_logic_vector(6 downto 0);
begin
if reset = '1' then
estado <= s0;
AVAIL <= '1'; done <= '0'; flag <= "00"; regd := "0000"; cont := "0000000";
elsif (clk'event and clk='1') then
CASE estado IS
WHEN s0 =>
AVAIL <= '1'; done <= '0'; flag <= "00"; regd := "0000"; cont := "0000000"; if start='0'then estado
<= s0; else estado <= s1; end if;
WHEN s1 =>
AVAIL <= '1'; done <= '0'; flag <= "00"; regd := data_in; cont := cont+1;
if (regd = "1011" and cont <= "1100100") then estado <= s2;
elsif cont="1100100" then estado <= s4;
else estado <= s1;
end if;
WHEN s2 => -- achou um valor em <=100
AVAIL <= '0'; done <= '1'; flag <= "01"; estado <= s3;
WHEN s3 =>
AVAIL <= '0'; done <= '1'; flag <= "01"; estado <= s0;
WHEN s4 => -- nao achou valor ate 100 dados
AVAIL <= '0'; done <= '1'; flag <= "00"; estado <= s5;
WHEN s5 =>
AVAIL <= '0'; done <= '1'; flag <= "00"; estado <= s0;
WHEN others =>
AVAIL <= '1'; done <= '0'; flag <= "00"; estado <= s0;
end CASE;
end if;
end process;
end Behavioral;
|
apache-2.0
|
6683ed9e18b79b7a78dcc0cd7d3912ce
| 0.507922 | 3.306886 | false | false | false | false |
thasti/dvbs
|
hdl/fifo/fifo_tb.vhd
| 1 | 1,310 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity fifo_tb is
end fifo_tb;
architecture tb of fifo_tb is
constant width : positive := 8;
-- interface signals
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal d : std_logic_vector(width-1 downto 0) := (others => '0');
signal we : std_logic := '0';
signal full : std_logic;
signal al_full : std_logic;
signal q : std_logic_vector(width-1 downto 0);
signal re : std_logic := '0';
signal empty : std_logic;
signal al_empty : std_logic;
begin
dut : entity work.fifo
generic map (num_words => 8, word_width => width, al_full_lvl => 6, al_empty_lvl => 2)
port map(clk => clk, rst => rst, d => d, we => we, full => full, al_full => al_full, q => q, re => re, empty => empty, al_empty => al_empty);
clk <= not clk after 100 ns;
rst <= '0' after 500 ns;
test : process
begin
wait until falling_edge(rst);
wait until rising_edge(clk);
we <= '1';
d <= x"AA";
wait until rising_edge(clk);
d <= x"55";
wait until rising_edge(clk);
d <= x"CC";
wait until rising_edge(clk);
we <= '0';
re <= '1';
wait until rising_edge(clk);
re <= '0';
wait until rising_edge(clk);
re <= '1';
wait until rising_edge(clk);
re <= '0';
wait;
end process;
end tb;
|
gpl-2.0
|
dc9f4d38cef5ed68fe51fd65cc69280b
| 0.614504 | 2.630522 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_pctrl.vhd
| 1 | 15,597 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_vdma_0_wrapper_fifo_generator_v9_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_vdma_0_wrapper_fifo_generator_v9_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
mit
|
a3400ec7f959dced31f7dd84243b0a6b
| 0.52369 | 3.360698 | false | false | false | false |
thasti/dvbs
|
hdl/fifo/fifo.vhd
| 1 | 2,605 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity fifo is
generic (
num_words : positive := 8; -- FIFO Depth
word_width : positive := 24; -- FIFO Width
al_full_lvl : natural := 5; -- FIFO Almost Full Level
al_empty_lvl : natural := 3 -- FIFO Almost Empty Level
);
port (
clk : in std_logic; -- System Clock
rst : in std_logic; -- System Reset
d : in std_logic_vector(word_width-1 downto 0); -- Input Data
we : in std_logic; -- Write Enable
full : out std_logic; -- Full Flag
al_full : out std_logic; -- Almost Full Flag
q : out std_logic_vector(word_width-1 downto 0); -- Output Data
re : in std_logic; -- Read Signal
empty : out std_logic; -- Empty Flag
al_empty: out std_logic -- Almost Empty Flag
);
end entity;
architecture behavioral of fifo is
type mem_type is array(num_words-1 downto 0) of std_logic_vector(word_width-1 downto 0);
constant adr_width: integer := integer(ceil(log2(real(num_words))));
constant full_value: unsigned(adr_width-1 downto 0) := to_unsigned(num_words-1,adr_width);
constant empty_value: unsigned(adr_width-1 downto 0) := (others => '0');
signal mem: mem_type;
signal read_adr: unsigned(adr_width-1 downto 0) := (others => '0');
signal write_adr: unsigned(adr_width-1 downto 0) := (others => '0');
signal full_int: std_logic;
signal empty_int: std_logic;
begin
process
begin
wait until rising_edge(clk);
if rst = '1' then
read_adr <= (others => '0');
write_adr <= (others => '0');
else
if (we = '1' and full_int = '0') then
mem(to_integer(write_adr)) <= d;
write_adr <= write_adr + 1;
end if;
if (re = '1' and empty_int = '0') then
read_adr <= read_adr + 1;
q <= mem(to_integer(read_adr));
end if;
end if;
end process;
full_int <= '1' when (write_adr = (read_adr - 1)) else '0';
empty_int <= '1' when (read_adr = write_adr) else '0';
full <= full_int;
empty <= empty_int;
al_full <= '1' when ((write_adr - read_adr) >= al_full_lvl) else '0';
al_empty <= '1' when ((write_adr - read_adr) <= al_empty_lvl) else '0';
end behavioral;
|
gpl-2.0
|
bd026ace913cb0e32b250b0a1213789b
| 0.515163 | 3.2933 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth.vhd
| 1 | 10,727 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(34-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(34-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(34-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(34-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 50 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_1_dgen
GENERIC MAP (
C_DIN_WIDTH => 34,
C_DOUT_WIDTH => 34,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_1_dverif
GENERIC MAP (
C_DOUT_WIDTH => 34,
C_DIN_WIDTH => 34,
C_USE_EMBEDDED_REG => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_1_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 34,
C_DIN_WIDTH => 34,
C_WR_PNTR_WIDTH => 7,
C_RD_PNTR_WIDTH => 7,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_vdma_0_wrapper_fifo_generator_v9_1_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
mit
|
d2c151f86fa56fbeb7d0d15843bbf621
| 0.47152 | 4.041824 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_2/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_2_rng.vhd
| 1 | 4,001 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_2_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_2_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_2_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
mit
|
bcd7c4e9ee8d9a081e0c634f3a8d2b89
| 0.64159 | 4.238347 | false | false | false | false |
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_delay_1.0/sources_1/new/delay.vhd
| 1 | 5,875 |
----------------------------------------------------
-- Vladi & Adi --
-- TAU EE Senior year project --
-- --
--************************************************--
--****************** Delay ***********************--
--************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity delay is
generic (
T: integer := 20000;
B: integer := 15 --15 bits for 20,000 memory places
);
Port ( x : in STD_LOGIC_VECTOR(31 downto 0);
y : out STD_LOGIC_VECTOR(31 downto 0);
clk_48: in std_logic;
options : in STD_LOGIC_VECTOR(0 to 3);
en : in STD_LOGIC_VECTOR(0 to 3)
);
end delay;
architecture Behavioral of delay is
signal y_temp_s : signed(31 downto 0):= x"00000000";
--triangular wave parameters
signal direction: std_logic := '0';
signal count: integer := 5;
signal i : std_logic_vector (B-1 downto 0) := "000000000000000";
signal max_delay : integer := T-1;
--********************** BRAM signals
signal we : std_logic := '1';
signal addr1 : std_logic_vector(B-1 downto 0) := "000000000000000";
signal addr2 : std_logic_vector(B-1 downto 0):= "000000000000000";
signal data_in : std_logic_vector(31 downto 0); --32 bit word
signal data_out1 : std_logic_vector(31 downto 0);
signal data_out2 : std_logic_vector(31 downto 0);
--*************************
component bram is
generic (
T: integer := 20000;
B: integer := 15 --15 bits for 20,000 memory places
);
port (
CLK : in std_logic;
WE : in std_logic;
ADDR1 : in std_logic_vector(B-1 downto 0);
ADDR2 : in std_logic_vector(B-1 downto 0);
DI : in std_logic_vector(31 downto 0); --32 bit word
DO1 : out std_logic_vector(31 downto 0);
DO2 : out std_logic_vector(31 downto 0)
);
end component bram;
component bram_d_allpass is
generic (
T: integer := 20000;
B: integer := 15 --15 bits for 20,000 memory places
);
port (
CLK : in std_logic;
WE : in std_logic;
ADDR1 : in std_logic_vector(B-1 downto 0);
ADDR2 : in std_logic_vector(B-1 downto 0);
DI : in std_logic_vector(31 downto 0); --32 bit word
DO1 : out std_logic_vector(31 downto 0);
DO2 : out std_logic_vector(31 downto 0)
);
end component bram_d_allpass;
begin
--*********** temporary debugging signals *********
--addr1_temp0 <= "00000000000000000" & std_logic_vector(addr1);
--addr2_temp1 <= "00000000000000000" & std_logic_vector(addr2);
--*************************************************
bram_inst : bram
port map (
CLK => clk_48,
WE => we,
ADDR1 => addr1,
ADDR2 => addr2,
DI => data_in,
DO1 => data_out1,
DO2 => data_out2
);
process(count) --triangular wave, creates long delay
begin
if (count=2440) then
direction <= '1';
end if;
if (count=0) then
direction <= '0';
end if;
end process;
dir1:process(direction, clk_48)
begin
if rising_edge(clk_48) then
if (direction='0') then
count <= count+1;
end if;
if (direction='1') then
count <= count-1;
end if;
end if;
end process;
process(clk_48)
begin
if rising_edge(clk_48) then
if to_integer(unsigned(i)) = max_delay-2 then
i<= "000000000000000";
else
i <= std_logic_vector(unsigned(i)+1);
end if;
end if;
end process;
addr_1:process(clk_48) --BRAM write pointer
begin
if rising_edge(clk_48) then
if (to_integer(unsigned(addr1)) = max_delay-2) then
addr1 <= "000000000000000";
else
addr1 <= std_logic_vector(unsigned(addr1) + 1);
end if;
end if;
end process;
addr_2:process(clk_48) --BRAM read pointer
begin
if rising_edge(clk_48) then
if (options="1000" or options="0100" or options="0010" or options="1100" or options="1110") then
if (to_integer(unsigned(addr2)) = max_delay-2) then
addr2 <= "000000000000000";
end if;
addr2 <= std_logic_vector(unsigned(i) + 1);
end if;
end if;
end process;
main:process (clk_48, options)
begin
if en(3)= '1' then
if rising_edge(clk_48) then
if options="1000" then --iir , play Buckethead's Whitewash!
max_delay <= T-1;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= std_logic_vector(y_temp_s);
y <= std_logic_vector(y_temp_s);
end if;
if options="1100" then --iir, faster delay
max_delay <= T/2-1;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= std_logic_vector(y_temp_s);
y <= std_logic_vector(y_temp_s);
end if;
if options="1110" then --iir, very slight reverb
max_delay <= T/2-1;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),3)));
data_in <= std_logic_vector(y_temp_s);
y <= std_logic_vector(y_temp_s);
end if;
if options="0100" then --iir, long delay
max_delay <= count;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= std_logic_vector(y_temp_s);
y <= std_logic_vector(y_temp_s);
end if;
if options="0010" then --fir sigle tap, long delay
max_delay <= count;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= x;
y <= std_logic_vector(y_temp_s);
end if;
end if;
else
y<=x;
end if;
end process;
end Behavioral;
|
mit
|
3658072307a5f47c637fa0ce9aa185c0
| 0.549957 | 3.315463 | false | false | false | false |
thasti/dvbs
|
hdl/network/rmii_rx/rmii_rx.vhd
| 1 | 2,159 |
-- ethernet RMII interface
-- Stefan Biereigel
-- reads data from the RMII PHY interface
-- RX preamble & FSC is stripped, only data in frame is output to
--
-- port description
--
-- TO PHY:
-- rxd0,1 output data
-- crsdv output data valid
--
-- TO CTRL:
-- clk 50 MHz RMII clock
-- rst sync reset
-- rx_dv send trigger input
-- rx_byte tx module is ready for transfer
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rmii_rx is
port (
clk : in std_logic;
rst : in std_logic;
rxd : in std_logic_vector(1 downto 0);
crsdv : in std_logic;
rx_byte : out std_logic_vector(7 downto 0);
rx_dv : out std_logic;
rx_crs : out std_logic
);
end rmii_rx;
architecture behav of rmii_rx is
type rx_states is (idle, sync, data);
signal cnt : unsigned(1 downto 0);
signal data_i : std_logic_vector(7 downto 0);
signal rx_state : rx_states;
signal crs_i : std_logic;
signal dv_i : std_logic;
begin
tx_proc : process
begin
wait until rising_edge(clk);
if rst = '1' then
cnt <= to_unsigned(0,cnt'length);
rx_state <= idle;
crs_i <= '0';
dv_i <= '0';
rx_dv <= '0';
rx_crs <= '0';
rx_byte <= x"00";
else
case rx_state is
when idle =>
rx_dv <= '0';
rx_crs <= '0';
rx_byte <= x"00";
crs_i <= '0';
dv_i <= '0';
if crsdv = '1' then
rx_state <= sync;
end if;
when sync =>
if rxd = "11" then -- FSD
rx_state <= data;
cnt <= to_unsigned(0, cnt'length);
elsif rxd /= "01" or crsdv = '0' then -- no sync pattern anymore
rx_state <= idle;
end if;
when data =>
if cnt = to_unsigned(0, cnt'length) and dv_i = '1' then
rx_byte <= data_i;
rx_dv <= '1';
else
rx_dv <= '0';
end if;
rx_crs <= '1';
data_i(2*to_integer(cnt)+1 downto 2*to_integer(cnt)) <= rxd(1 downto 0);
if cnt(0) = '0' then -- crsdv resembles CRS
crs_i <= crsdv;
else
dv_i <= crsdv;
if crsdv <= '0' then
rx_state <= idle;
rx_crs <= '0';
end if;
end if;
cnt <= cnt + to_unsigned(1,cnt'length);
end case;
end if;
end process;
end behav;
|
gpl-2.0
|
81d167cdd996659a643e8ff67ec3eafa
| 0.566003 | 2.695381 | false | false | false | false |
ciroceissler/sva_example
|
dut/FSM4.vhd
| 1 | 2,198 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:08:36 05/29/2014
-- Design Name:
-- Module Name: FSM4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FSM4 is
Port (
reset : in std_logic;
clk : in std_logic;
start: in std_logic;
data_in : in std_logic_vector(3 downto 0);
AVAIL : out std_logic;
DONE : out std_logic;
flag : out std_logic_vector(1 downto 0));
end FSM4;
architecture Behavioral of FSM4 is
type tipoestado is (s0, s1, s2, s3, s4, s5, s6);
signal regd : std_logic_vector(3 downto 0);
signal cont : std_logic_vector(6 downto 0);
signal estado : tipoestado;
begin
process(reset, clk)
begin
if reset = '1' then
estado <= s0;
AVAIL <= '1'; done <= '0'; flag <= "00"; regd <= "0000"; cont <= "0000000";
elsif (clk'event and clk='1') then
CASE estado IS
WHEN s0 =>
AVAIL <= '1'; done <= '0'; flag <= "00"; regd <= "0000"; cont <= "0000000"; if start='0'then estado
<= s0; else estado <= s1; end if;
WHEN s1 =>
AVAIL <= '0'; done <= '0'; flag <= "00"; regd <= data_in; cont <= cont+1;
if (regd = "1011" and cont <= "1100100") then estado <= s2;
elsif cont="1100100" then estado <= s4;
else estado <= s1;
end if;
WHEN s2 => -- achou um valor em <=100
AVAIL <= '0'; done <= '1'; flag <= "01"; estado <= s3;
WHEN s3 =>
AVAIL <= '0'; done <= '1'; flag <= "01"; estado <= s0;
WHEN s4 => -- nao achou valor ate 100 dados
AVAIL <= '0'; done <= '1'; flag <= "00"; estado <= s5;
WHEN s5 =>
AVAIL <= '0'; done <= '1'; flag <= "00"; estado <= s0;
WHEN others =>
AVAIL <= '1'; done <= '0'; flag <= "00"; estado <= s0;
end CASE;
end if;
end process;
end Behavioral;
|
apache-2.0
|
325cac3916910766cc3ca2d287a4ae1b
| 0.508644 | 3.3003 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_dma_0_wrapper_fifo_generator_v9_3_1/simulation/system_axi_dma_0_wrapper_fifo_generator_v9_3_1_tb.vhd
| 1 | 6,199 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_1_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pkg.ALL;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_1_tb IS
END ENTITY;
ARCHITECTURE system_axi_dma_0_wrapper_fifo_generator_v9_3_1_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_1_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2100 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_dma_0_wrapper_fifo_generator_v9_3_1_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_dma_0_wrapper_fifo_generator_v9_3_1_synth
system_axi_dma_0_wrapper_fifo_generator_v9_3_1_synth_inst:system_axi_dma_0_wrapper_fifo_generator_v9_3_1_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 42
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
mit
|
56aecf2fe2d29e86250af2453ff017f9
| 0.62623 | 4.007111 | false | false | false | false |
medav/conware
|
conware_final/system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pkg.vhd
| 1 | 17,482 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
S_ACLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_exdes IS
PORT (
S_ARESETN : IN std_logic;
M_AXI_AWID : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(64/8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
S_AXI_AWID : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(64/8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
M_AXI_ARID : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
S_AXI_ARID : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
AXI_AW_PROG_FULL : OUT std_logic;
AXI_AW_PROG_EMPTY : OUT std_logic;
AXI_W_PROG_FULL : OUT std_logic;
AXI_W_PROG_EMPTY : OUT std_logic;
AXI_B_PROG_FULL : OUT std_logic;
AXI_B_PROG_EMPTY : OUT std_logic;
AXI_AR_PROG_FULL : OUT std_logic;
AXI_AR_PROG_EMPTY : OUT std_logic;
AXI_R_PROG_FULL : OUT std_logic;
AXI_R_PROG_EMPTY : OUT std_logic;
S_ACLK : IN std_logic);
END COMPONENT;
------------------------
END system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pkg;
PACKAGE BODY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pkg;
|
mit
|
52187c23845e5960766d68b1a8dbd88c
| 0.499085 | 3.757954 | false | false | false | false |
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